Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
82704155 | 2 | Copyright (C) 1993-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 | 424 | || (CPU) == CPU_R5900) \ |
bd782c07 | 425 | && ((CPU) != CPU_GS464 \ |
9108bc33 CX |
426 | || (CPU) != CPU_GS464E \ |
427 | || (CPU) != CPU_GS264E)) | |
af7ee8bf | 428 | |
ad3fea08 TS |
429 | /* Return true if ISA supports move to/from high part of a 64-bit |
430 | floating-point register. */ | |
431 | #define ISA_HAS_MXHC1(ISA) \ | |
432 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
433 | || (ISA) == ISA_MIPS32R3 \ |
434 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
435 | || (ISA) == ISA_MIPS32R6 \ |
436 | || (ISA) == ISA_MIPS64R2 \ | |
437 | || (ISA) == ISA_MIPS64R3 \ | |
438 | || (ISA) == ISA_MIPS64R5 \ | |
439 | || (ISA) == ISA_MIPS64R6) | |
440 | ||
441 | /* Return true if ISA supports legacy NAN. */ | |
442 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
443 | ((ISA) == ISA_MIPS1 \ | |
444 | || (ISA) == ISA_MIPS2 \ | |
445 | || (ISA) == ISA_MIPS3 \ | |
446 | || (ISA) == ISA_MIPS4 \ | |
447 | || (ISA) == ISA_MIPS5 \ | |
448 | || (ISA) == ISA_MIPS32 \ | |
449 | || (ISA) == ISA_MIPS32R2 \ | |
450 | || (ISA) == ISA_MIPS32R3 \ | |
451 | || (ISA) == ISA_MIPS32R5 \ | |
452 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
453 | || (ISA) == ISA_MIPS64R2 \ |
454 | || (ISA) == ISA_MIPS64R3 \ | |
455 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 456 | |
bad1aba3 | 457 | #define GPR_SIZE \ |
458 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
459 | ? 32 \ | |
460 | : mips_opts.gp) | |
ca4e0257 | 461 | |
bad1aba3 | 462 | #define FPR_SIZE \ |
463 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
464 | ? 32 \ | |
465 | : mips_opts.fp) | |
ca4e0257 | 466 | |
316f5878 | 467 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 468 | |
316f5878 | 469 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 470 | |
3b91255e RS |
471 | /* True if relocations are stored in-place. */ |
472 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
473 | ||
aed1a261 RS |
474 | /* The ABI-derived address size. */ |
475 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 476 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 477 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 478 | |
aed1a261 RS |
479 | /* The size of symbolic constants (i.e., expressions of the form |
480 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
481 | #define HAVE_32BIT_SYMBOLS \ | |
482 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
483 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 484 | |
b7c7d6c1 TS |
485 | /* Addresses are loaded in different ways, depending on the address size |
486 | in use. The n32 ABI Documentation also mandates the use of additions | |
487 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 488 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 489 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
490 | |
491 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 492 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
493 | |
494 | #define ADDRESS_LOAD_INSN \ | |
495 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
496 | ||
497 | #define ADDRESS_STORE_INSN \ | |
498 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
499 | ||
a4672219 | 500 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
501 | #define CPU_HAS_MIPS16(cpu) \ |
502 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
503 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 504 | |
2309ddf2 | 505 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
506 | #define CPU_HAS_MICROMIPS(cpu) 0 |
507 | ||
60b63b72 RS |
508 | /* True if CPU has a dror instruction. */ |
509 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
510 | ||
511 | /* True if CPU has a ror instruction. */ | |
512 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
513 | ||
dd6a37e7 | 514 | /* True if CPU is in the Octeon family */ |
2c629856 N |
515 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
516 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 517 | |
dd3cbb7e | 518 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 519 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 520 | |
0aa27725 RS |
521 | /* True, if CPU has support for ldc1 and sdc1. */ |
522 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
523 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
524 | ||
c8978940 CD |
525 | /* True if mflo and mfhi can be immediately followed by instructions |
526 | which write to the HI and LO registers. | |
527 | ||
528 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
529 | (at least) two instructions between the reads of HI/LO and | |
530 | instructions which write them, and later ISAs do not. Contradicting | |
531 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
532 | the UM for the NEC Vr5000) document needing the instructions between | |
533 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
534 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
535 | earlier-ISA CPUs for which CPU documentation declares that the | |
536 | instructions are really interlocked. */ | |
537 | #define hilo_interlocks \ | |
538 | (mips_opts.isa == ISA_MIPS32 \ | |
539 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
540 | || mips_opts.isa == ISA_MIPS32R3 \ |
541 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 542 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
543 | || mips_opts.isa == ISA_MIPS64 \ |
544 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
545 | || mips_opts.isa == ISA_MIPS64R3 \ |
546 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 547 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 548 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 549 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
550 | || mips_opts.arch == CPU_R10000 \ |
551 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
552 | || mips_opts.arch == CPU_R14000 \ |
553 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 554 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 555 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 556 | || mips_opts.micromips \ |
c8978940 | 557 | ) |
252b5132 RH |
558 | |
559 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
560 | from the GPRs after they are loaded from memory, and thus does not |
561 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 562 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
563 | level I and microMIPS mode instructions are always interlocked. */ |
564 | #define gpr_interlocks \ | |
565 | (mips_opts.isa != ISA_MIPS1 \ | |
566 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 567 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
568 | || mips_opts.micromips \ |
569 | ) | |
252b5132 | 570 | |
81912461 ILT |
571 | /* Whether the processor uses hardware interlocks to avoid delays |
572 | required by coprocessor instructions, and thus does not require | |
573 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
574 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
575 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 576 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
577 | levels I, II, and III and microMIPS mode instructions are always |
578 | interlocked. */ | |
bdaaa2e1 | 579 | /* Itbl support may require additional care here. */ |
81912461 ILT |
580 | #define cop_interlocks \ |
581 | ((mips_opts.isa != ISA_MIPS1 \ | |
582 | && mips_opts.isa != ISA_MIPS2 \ | |
583 | && mips_opts.isa != ISA_MIPS3) \ | |
584 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 585 | || mips_opts.micromips \ |
81912461 ILT |
586 | ) |
587 | ||
588 | /* Whether the processor uses hardware interlocks to protect reads | |
589 | from coprocessor registers after they are loaded from memory, and | |
590 | thus does not require nops to be inserted. This applies to | |
591 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
592 | requires at MIPS ISA level I and microMIPS mode instructions are |
593 | always interlocked. */ | |
594 | #define cop_mem_interlocks \ | |
595 | (mips_opts.isa != ISA_MIPS1 \ | |
596 | || mips_opts.micromips \ | |
597 | ) | |
252b5132 | 598 | |
6b76fefe CM |
599 | /* Is this a mfhi or mflo instruction? */ |
600 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
601 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
602 | ||
df58fc94 RS |
603 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
604 | has been selected. This implies, in particular, that addresses of text | |
605 | labels have their LSB set. */ | |
606 | #define HAVE_CODE_COMPRESSION \ | |
607 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
608 | ||
42429eac | 609 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 610 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
611 | #define GPR_SMIN (-GPR_SMAX - 1) |
612 | ||
252b5132 RH |
613 | /* MIPS PIC level. */ |
614 | ||
a161fe53 | 615 | enum mips_pic_level mips_pic; |
252b5132 | 616 | |
c9914766 | 617 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 618 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 619 | static int mips_big_got = 0; |
252b5132 RH |
620 | |
621 | /* 1 if trap instructions should used for overflow rather than break | |
622 | instructions. */ | |
c9914766 | 623 | static int mips_trap = 0; |
252b5132 | 624 | |
119d663a | 625 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 626 | by assembling two single width halves into two single width floating |
119d663a NC |
627 | point registers which just happen to alias the double width destination |
628 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 629 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
630 | automatically at assemble time. */ |
631 | static int mips_disable_float_construction; | |
632 | ||
252b5132 RH |
633 | /* Non-zero if any .set noreorder directives were used. */ |
634 | ||
635 | static int mips_any_noreorder; | |
636 | ||
6b76fefe CM |
637 | /* Non-zero if nops should be inserted when the register referenced in |
638 | an mfhi/mflo instruction is read in the next two instructions. */ | |
639 | static int mips_7000_hilo_fix; | |
640 | ||
02ffd3e4 | 641 | /* The size of objects in the small data section. */ |
156c2f8b | 642 | static unsigned int g_switch_value = 8; |
252b5132 RH |
643 | /* Whether the -G option was used. */ |
644 | static int g_switch_seen = 0; | |
645 | ||
646 | #define N_RMASK 0xc4 | |
647 | #define N_VFP 0xd4 | |
648 | ||
649 | /* If we can determine in advance that GP optimization won't be | |
650 | possible, we can skip the relaxation stuff that tries to produce | |
651 | GP-relative references. This makes delay slot optimization work | |
652 | better. | |
653 | ||
654 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
655 | gcc output. It needs to guess right for gcc, otherwise gcc |
656 | will put what it thinks is a GP-relative instruction in a branch | |
657 | delay slot. | |
252b5132 RH |
658 | |
659 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
660 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 661 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
662 | |
663 | /* handle of the OPCODE hash table */ | |
664 | static struct hash_control *op_hash = NULL; | |
665 | ||
666 | /* The opcode hash table we use for the mips16. */ | |
667 | static struct hash_control *mips16_op_hash = NULL; | |
668 | ||
df58fc94 RS |
669 | /* The opcode hash table we use for the microMIPS ASE. */ |
670 | static struct hash_control *micromips_op_hash = NULL; | |
671 | ||
252b5132 RH |
672 | /* This array holds the chars that always start a comment. If the |
673 | pre-processor is disabled, these aren't very useful */ | |
674 | const char comment_chars[] = "#"; | |
675 | ||
676 | /* This array holds the chars that only start a comment at the beginning of | |
677 | a line. If the line seems to have the form '# 123 filename' | |
678 | .line and .file directives will appear in the pre-processed output */ | |
679 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
680 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 681 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
682 | /* Also note that C style comments are always supported. */ |
683 | const char line_comment_chars[] = "#"; | |
684 | ||
bdaaa2e1 | 685 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 686 | const char line_separator_chars[] = ";"; |
252b5132 RH |
687 | |
688 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
689 | const char EXP_CHARS[] = "eE"; | |
690 | ||
691 | /* Chars that mean this number is a floating point constant */ | |
692 | /* As in 0f12.456 */ | |
693 | /* or 0d1.2345e12 */ | |
694 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
695 | ||
696 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
697 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
698 | but nothing is ideal around here. | |
699 | */ | |
700 | ||
e3de51ce RS |
701 | /* Types of printf format used for instruction-related error messages. |
702 | "I" means int ("%d") and "S" means string ("%s"). */ | |
703 | enum mips_insn_error_format { | |
704 | ERR_FMT_PLAIN, | |
705 | ERR_FMT_I, | |
706 | ERR_FMT_SS, | |
707 | }; | |
708 | ||
709 | /* Information about an error that was found while assembling the current | |
710 | instruction. */ | |
711 | struct mips_insn_error { | |
712 | /* We sometimes need to match an instruction against more than one | |
713 | opcode table entry. Errors found during this matching are reported | |
714 | against a particular syntactic argument rather than against the | |
715 | instruction as a whole. We grade these messages so that errors | |
716 | against argument N have a greater priority than an error against | |
717 | any argument < N, since the former implies that arguments up to N | |
718 | were acceptable and that the opcode entry was therefore a closer match. | |
719 | If several matches report an error against the same argument, | |
720 | we only use that error if it is the same in all cases. | |
721 | ||
722 | min_argnum is the minimum argument number for which an error message | |
723 | should be accepted. It is 0 if MSG is against the instruction as | |
724 | a whole. */ | |
725 | int min_argnum; | |
726 | ||
727 | /* The printf()-style message, including its format and arguments. */ | |
728 | enum mips_insn_error_format format; | |
729 | const char *msg; | |
730 | union { | |
731 | int i; | |
732 | const char *ss[2]; | |
733 | } u; | |
734 | }; | |
735 | ||
736 | /* The error that should be reported for the current instruction. */ | |
737 | static struct mips_insn_error insn_error; | |
252b5132 RH |
738 | |
739 | static int auto_align = 1; | |
740 | ||
741 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
742 | offset in the stack frame from which to restore the $gp register. | |
743 | This is set by the .cprestore pseudo-op, and saved in this | |
744 | variable. */ | |
745 | static offsetT mips_cprestore_offset = -1; | |
746 | ||
67c1ffbe | 747 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 748 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 749 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
750 | static offsetT mips_cpreturn_offset = -1; |
751 | static int mips_cpreturn_register = -1; | |
752 | static int mips_gp_register = GP; | |
def2e0dd | 753 | static int mips_gprel_offset = 0; |
6478892d | 754 | |
7a621144 DJ |
755 | /* Whether mips_cprestore_offset has been set in the current function |
756 | (or whether it has already been warned about, if not). */ | |
757 | static int mips_cprestore_valid = 0; | |
758 | ||
252b5132 RH |
759 | /* This is the register which holds the stack frame, as set by the |
760 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
761 | static int mips_frame_reg = SP; | |
762 | ||
7a621144 DJ |
763 | /* Whether mips_frame_reg has been set in the current function |
764 | (or whether it has already been warned about, if not). */ | |
765 | static int mips_frame_reg_valid = 0; | |
766 | ||
252b5132 RH |
767 | /* To output NOP instructions correctly, we need to keep information |
768 | about the previous two instructions. */ | |
769 | ||
770 | /* Whether we are optimizing. The default value of 2 means to remove | |
771 | unneeded NOPs and swap branch instructions when possible. A value | |
772 | of 1 means to not swap branches. A value of 0 means to always | |
773 | insert NOPs. */ | |
774 | static int mips_optimize = 2; | |
775 | ||
776 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
777 | equivalent to seeing no -g option at all. */ | |
778 | static int mips_debug = 0; | |
779 | ||
7d8e00cf RS |
780 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
781 | #define MAX_VR4130_NOPS 4 | |
782 | ||
783 | /* The maximum number of NOPs needed to fill delay slots. */ | |
784 | #define MAX_DELAY_NOPS 2 | |
785 | ||
786 | /* The maximum number of NOPs needed for any purpose. */ | |
787 | #define MAX_NOPS 4 | |
71400594 RS |
788 | |
789 | /* A list of previous instructions, with index 0 being the most recent. | |
790 | We need to look back MAX_NOPS instructions when filling delay slots | |
791 | or working around processor errata. We need to look back one | |
792 | instruction further if we're thinking about using history[0] to | |
793 | fill a branch delay slot. */ | |
794 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 795 | |
fc76e730 | 796 | /* Arrays of operands for each instruction. */ |
14daeee3 | 797 | #define MAX_OPERANDS 6 |
fc76e730 RS |
798 | struct mips_operand_array { |
799 | const struct mips_operand *operand[MAX_OPERANDS]; | |
800 | }; | |
801 | static struct mips_operand_array *mips_operands; | |
802 | static struct mips_operand_array *mips16_operands; | |
803 | static struct mips_operand_array *micromips_operands; | |
804 | ||
1e915849 | 805 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
806 | static struct mips_cl_insn nop_insn; |
807 | static struct mips_cl_insn mips16_nop_insn; | |
808 | static struct mips_cl_insn micromips_nop16_insn; | |
809 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
810 | |
811 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
812 | #define NOP_INSN (mips_opts.mips16 \ |
813 | ? &mips16_nop_insn \ | |
814 | : (mips_opts.micromips \ | |
815 | ? (mips_opts.insn32 \ | |
816 | ? µmips_nop32_insn \ | |
817 | : µmips_nop16_insn) \ | |
818 | : &nop_insn)) | |
df58fc94 RS |
819 | |
820 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
821 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
822 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
823 | ? 2 : 4) | |
252b5132 | 824 | |
252b5132 RH |
825 | /* If this is set, it points to a frag holding nop instructions which |
826 | were inserted before the start of a noreorder section. If those | |
827 | nops turn out to be unnecessary, the size of the frag can be | |
828 | decreased. */ | |
829 | static fragS *prev_nop_frag; | |
830 | ||
831 | /* The number of nop instructions we created in prev_nop_frag. */ | |
832 | static int prev_nop_frag_holds; | |
833 | ||
834 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 835 | prev_nop_frag. */ |
252b5132 RH |
836 | static int prev_nop_frag_required; |
837 | ||
838 | /* The number of instructions we've seen since prev_nop_frag. */ | |
839 | static int prev_nop_frag_since; | |
840 | ||
e8044f35 RS |
841 | /* Relocations against symbols are sometimes done in two parts, with a HI |
842 | relocation and a LO relocation. Each relocation has only 16 bits of | |
843 | space to store an addend. This means that in order for the linker to | |
844 | handle carries correctly, it must be able to locate both the HI and | |
845 | the LO relocation. This means that the relocations must appear in | |
846 | order in the relocation table. | |
252b5132 RH |
847 | |
848 | In order to implement this, we keep track of each unmatched HI | |
849 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 850 | corresponding LO relocation. */ |
252b5132 | 851 | |
e972090a NC |
852 | struct mips_hi_fixup |
853 | { | |
252b5132 RH |
854 | /* Next HI fixup. */ |
855 | struct mips_hi_fixup *next; | |
856 | /* This fixup. */ | |
857 | fixS *fixp; | |
858 | /* The section this fixup is in. */ | |
859 | segT seg; | |
860 | }; | |
861 | ||
862 | /* The list of unmatched HI relocs. */ | |
863 | ||
864 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
865 | ||
64bdfcaf RS |
866 | /* The frag containing the last explicit relocation operator. |
867 | Null if explicit relocations have not been used. */ | |
868 | ||
869 | static fragS *prev_reloc_op_frag; | |
870 | ||
252b5132 RH |
871 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
872 | ||
e972090a NC |
873 | static const unsigned int mips16_to_32_reg_map[] = |
874 | { | |
252b5132 RH |
875 | 16, 17, 2, 3, 4, 5, 6, 7 |
876 | }; | |
60b63b72 | 877 | |
df58fc94 RS |
878 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
879 | ||
df58fc94 | 880 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
881 | |
882 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 883 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
884 | { |
885 | 5, 5, 6, 4, 4, 4, 4, 4 | |
886 | }; | |
e76ff5ab | 887 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
888 | { |
889 | 6, 7, 7, 21, 22, 5, 6, 7 | |
890 | }; | |
891 | ||
df58fc94 RS |
892 | /* The microMIPS registers with type m. */ |
893 | static const unsigned int micromips_to_32_reg_m_map[] = | |
894 | { | |
895 | 0, 17, 2, 3, 16, 18, 19, 20 | |
896 | }; | |
897 | ||
898 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
899 | ||
71400594 RS |
900 | /* Classifies the kind of instructions we're interested in when |
901 | implementing -mfix-vr4120. */ | |
c67a084a NC |
902 | enum fix_vr4120_class |
903 | { | |
71400594 RS |
904 | FIX_VR4120_MACC, |
905 | FIX_VR4120_DMACC, | |
906 | FIX_VR4120_MULT, | |
907 | FIX_VR4120_DMULT, | |
908 | FIX_VR4120_DIV, | |
909 | FIX_VR4120_MTHILO, | |
910 | NUM_FIX_VR4120_CLASSES | |
911 | }; | |
912 | ||
c67a084a NC |
913 | /* ...likewise -mfix-loongson2f-jump. */ |
914 | static bfd_boolean mips_fix_loongson2f_jump; | |
915 | ||
916 | /* ...likewise -mfix-loongson2f-nop. */ | |
917 | static bfd_boolean mips_fix_loongson2f_nop; | |
918 | ||
919 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
920 | static bfd_boolean mips_fix_loongson2f; | |
921 | ||
71400594 RS |
922 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
923 | there must be at least one other instruction between an instruction | |
924 | of type X and an instruction of type Y. */ | |
925 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
926 | ||
927 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 928 | static int mips_fix_vr4120; |
4a6a3df4 | 929 | |
7d8e00cf RS |
930 | /* ...likewise -mfix-vr4130. */ |
931 | static int mips_fix_vr4130; | |
932 | ||
6a32d874 CM |
933 | /* ...likewise -mfix-24k. */ |
934 | static int mips_fix_24k; | |
935 | ||
a8d14a88 CM |
936 | /* ...likewise -mfix-rm7000 */ |
937 | static int mips_fix_rm7000; | |
938 | ||
d954098f DD |
939 | /* ...likewise -mfix-cn63xxp1 */ |
940 | static bfd_boolean mips_fix_cn63xxp1; | |
941 | ||
27c634e0 FN |
942 | /* ...likewise -mfix-r5900 */ |
943 | static bfd_boolean mips_fix_r5900; | |
944 | static bfd_boolean mips_fix_r5900_explicit; | |
945 | ||
4a6a3df4 AO |
946 | /* We don't relax branches by default, since this causes us to expand |
947 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
948 | fail to compute the offset before expanding the macro to the most | |
949 | efficient expansion. */ | |
950 | ||
951 | static int mips_relax_branch; | |
8b10b0b3 MR |
952 | |
953 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
954 | Needed for broken assembly produced by some GCC versions and some | |
955 | sloppy code out there, where branches to data labels are present. */ | |
956 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 957 | \f |
4d7206a2 RS |
958 | /* The expansion of many macros depends on the type of symbol that |
959 | they refer to. For example, when generating position-dependent code, | |
960 | a macro that refers to a symbol may have two different expansions, | |
961 | one which uses GP-relative addresses and one which uses absolute | |
962 | addresses. When generating SVR4-style PIC, a macro may have | |
963 | different expansions for local and global symbols. | |
964 | ||
965 | We handle these situations by generating both sequences and putting | |
966 | them in variant frags. In position-dependent code, the first sequence | |
967 | will be the GP-relative one and the second sequence will be the | |
968 | absolute one. In SVR4 PIC, the first sequence will be for global | |
969 | symbols and the second will be for local symbols. | |
970 | ||
584892a6 RS |
971 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
972 | SECOND are the lengths of the two sequences in bytes. These fields | |
973 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
974 | the subtype has the following flags: | |
4d7206a2 | 975 | |
ce8ad872 MR |
976 | RELAX_PIC |
977 | Set if generating PIC code. | |
978 | ||
584892a6 RS |
979 | RELAX_USE_SECOND |
980 | Set if it has been decided that we should use the second | |
981 | sequence instead of the first. | |
982 | ||
983 | RELAX_SECOND_LONGER | |
984 | Set in the first variant frag if the macro's second implementation | |
985 | is longer than its first. This refers to the macro as a whole, | |
986 | not an individual relaxation. | |
987 | ||
988 | RELAX_NOMACRO | |
989 | Set in the first variant frag if the macro appeared in a .set nomacro | |
990 | block and if one alternative requires a warning but the other does not. | |
991 | ||
992 | RELAX_DELAY_SLOT | |
993 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
994 | delay slot. | |
4d7206a2 | 995 | |
df58fc94 RS |
996 | RELAX_DELAY_SLOT_16BIT |
997 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
998 | 16-bit instruction. | |
999 | ||
1000 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1001 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1002 | the macro is of the wrong size for the branch delay slot. | |
1003 | ||
1004 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1005 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1006 | the macro is of the wrong size for the branch delay slot. | |
1007 | ||
4d7206a2 RS |
1008 | The frag's "opcode" points to the first fixup for relaxable code. |
1009 | ||
1010 | Relaxable macros are generated using a sequence such as: | |
1011 | ||
1012 | relax_start (SYMBOL); | |
1013 | ... generate first expansion ... | |
1014 | relax_switch (); | |
1015 | ... generate second expansion ... | |
1016 | relax_end (); | |
1017 | ||
1018 | The code and fixups for the unwanted alternative are discarded | |
1019 | by md_convert_frag. */ | |
ce8ad872 MR |
1020 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1021 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1022 | |
584892a6 RS |
1023 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1024 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1025 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1026 | #define RELAX_USE_SECOND 0x20000 | |
1027 | #define RELAX_SECOND_LONGER 0x40000 | |
1028 | #define RELAX_NOMACRO 0x80000 | |
1029 | #define RELAX_DELAY_SLOT 0x100000 | |
1030 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1031 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1032 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1033 | |
4a6a3df4 AO |
1034 | /* Branch without likely bit. If label is out of range, we turn: |
1035 | ||
134c0c8b | 1036 | beq reg1, reg2, label |
4a6a3df4 AO |
1037 | delay slot |
1038 | ||
1039 | into | |
1040 | ||
1041 | bne reg1, reg2, 0f | |
1042 | nop | |
1043 | j label | |
1044 | 0: delay slot | |
1045 | ||
1046 | with the following opcode replacements: | |
1047 | ||
1048 | beq <-> bne | |
1049 | blez <-> bgtz | |
1050 | bltz <-> bgez | |
1051 | bc1f <-> bc1t | |
1052 | ||
1053 | bltzal <-> bgezal (with jal label instead of j label) | |
1054 | ||
1055 | Even though keeping the delay slot instruction in the delay slot of | |
1056 | the branch would be more efficient, it would be very tricky to do | |
1057 | correctly, because we'd have to introduce a variable frag *after* | |
1058 | the delay slot instruction, and expand that instead. Let's do it | |
1059 | the easy way for now, even if the branch-not-taken case now costs | |
1060 | one additional instruction. Out-of-range branches are not supposed | |
1061 | to be common, anyway. | |
1062 | ||
1063 | Branch likely. If label is out of range, we turn: | |
1064 | ||
1065 | beql reg1, reg2, label | |
1066 | delay slot (annulled if branch not taken) | |
1067 | ||
1068 | into | |
1069 | ||
1070 | beql reg1, reg2, 1f | |
1071 | nop | |
1072 | beql $0, $0, 2f | |
1073 | nop | |
1074 | 1: j[al] label | |
1075 | delay slot (executed only if branch taken) | |
1076 | 2: | |
1077 | ||
1078 | It would be possible to generate a shorter sequence by losing the | |
1079 | likely bit, generating something like: | |
b34976b6 | 1080 | |
4a6a3df4 AO |
1081 | bne reg1, reg2, 0f |
1082 | nop | |
1083 | j[al] label | |
1084 | delay slot (executed only if branch taken) | |
1085 | 0: | |
1086 | ||
1087 | beql -> bne | |
1088 | bnel -> beq | |
1089 | blezl -> bgtz | |
1090 | bgtzl -> blez | |
1091 | bltzl -> bgez | |
1092 | bgezl -> bltz | |
1093 | bc1fl -> bc1t | |
1094 | bc1tl -> bc1f | |
1095 | ||
1096 | bltzall -> bgezal (with jal label instead of j label) | |
1097 | bgezall -> bltzal (ditto) | |
1098 | ||
1099 | ||
1100 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1101 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1102 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1103 | ((relax_substateT) \ |
1104 | (0xc0000000 \ | |
1105 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1106 | | ((pic) ? 0x20 : 0) \ |
1107 | | ((toofar) ? 0x40 : 0) \ | |
1108 | | ((link) ? 0x80 : 0) \ | |
1109 | | ((likely) ? 0x100 : 0) \ | |
1110 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1111 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1112 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1113 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1114 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1115 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1116 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1117 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1118 | |
252b5132 RH |
1119 | /* For mips16 code, we use an entirely different form of relaxation. |
1120 | mips16 supports two versions of most instructions which take | |
1121 | immediate values: a small one which takes some small value, and a | |
1122 | larger one which takes a 16 bit value. Since branches also follow | |
1123 | this pattern, relaxing these values is required. | |
1124 | ||
1125 | We can assemble both mips16 and normal MIPS code in a single | |
1126 | object. Therefore, we need to support this type of relaxation at | |
1127 | the same time that we support the relaxation described above. We | |
1128 | use the high bit of the subtype field to distinguish these cases. | |
1129 | ||
1130 | The information we store for this type of relaxation is the | |
1131 | argument code found in the opcode file for this relocation, whether | |
1132 | the user explicitly requested a small or extended form, and whether | |
1133 | the relocation is in a jump or jal delay slot. That tells us the | |
1134 | size of the value, and how it should be stored. We also store | |
1135 | whether the fragment is considered to be extended or not. We also | |
1136 | store whether this is known to be a branch to a different section, | |
1137 | whether we have tried to relax this frag yet, and whether we have | |
1138 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1139 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1140 | small, ext, \ |
1141 | dslot, jal_dslot) \ | |
252b5132 RH |
1142 | (0x80000000 \ |
1143 | | ((type) & 0xff) \ | |
25499ac7 MR |
1144 | | ((e2) ? 0x100 : 0) \ |
1145 | | ((pic) ? 0x200 : 0) \ | |
1146 | | ((sym32) ? 0x400 : 0) \ | |
1147 | | ((nomacro) ? 0x800 : 0) \ | |
1148 | | ((small) ? 0x1000 : 0) \ | |
1149 | | ((ext) ? 0x2000 : 0) \ | |
1150 | | ((dslot) ? 0x4000 : 0) \ | |
1151 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1152 | |
4a6a3df4 | 1153 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1154 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1155 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1156 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1157 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1158 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1159 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1160 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1161 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1162 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1163 | ||
1164 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1165 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1166 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1167 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1168 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1169 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1170 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1171 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1172 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1173 | |
df58fc94 RS |
1174 | /* For microMIPS code, we use relaxation similar to one we use for |
1175 | MIPS16 code. Some instructions that take immediate values support | |
1176 | two encodings: a small one which takes some small value, and a | |
1177 | larger one which takes a 16 bit value. As some branches also follow | |
1178 | this pattern, relaxing these values is required. | |
1179 | ||
1180 | We can assemble both microMIPS and normal MIPS code in a single | |
1181 | object. Therefore, we need to support this type of relaxation at | |
1182 | the same time that we support the relaxation described above. We | |
1183 | use one of the high bits of the subtype field to distinguish these | |
1184 | cases. | |
1185 | ||
1186 | The information we store for this type of relaxation is the argument | |
1187 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1188 | selected as the assembler temporary, whether in the 32-bit |
1189 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1190 | compact, whether there is no delay-slot instruction available to fill |
1191 | in, whether it stores the link address implicitly in $ra, whether | |
1192 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1193 | instructions is enabled, and whether the displacement of a branch is |
1194 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1195 | branch, respectively. */ | |
ce8ad872 | 1196 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1197 | uncond, compact, link, nods, \ |
40209cad MR |
1198 | relax32, toofar16, toofar32) \ |
1199 | (0x40000000 \ | |
1200 | | ((type) & 0xff) \ | |
1201 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1202 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1203 | | ((pic) ? 0x4000 : 0) \ |
1204 | | ((uncond) ? 0x8000 : 0) \ | |
1205 | | ((compact) ? 0x10000 : 0) \ | |
1206 | | ((link) ? 0x20000 : 0) \ | |
1207 | | ((nods) ? 0x40000 : 0) \ | |
1208 | | ((relax32) ? 0x80000 : 0) \ | |
1209 | | ((toofar16) ? 0x100000 : 0) \ | |
1210 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1211 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1212 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1213 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1214 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1215 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1216 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1217 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1218 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1219 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1220 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1221 | ||
1222 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1223 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1224 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1225 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1226 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1227 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1228 | |
43c0598f RS |
1229 | /* Sign-extend 16-bit value X. */ |
1230 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1231 | ||
885add95 CD |
1232 | /* Is the given value a sign-extended 32-bit value? */ |
1233 | #define IS_SEXT_32BIT_NUM(x) \ | |
1234 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1235 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1236 | ||
1237 | /* Is the given value a sign-extended 16-bit value? */ | |
1238 | #define IS_SEXT_16BIT_NUM(x) \ | |
1239 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1240 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1241 | ||
df58fc94 RS |
1242 | /* Is the given value a sign-extended 12-bit value? */ |
1243 | #define IS_SEXT_12BIT_NUM(x) \ | |
1244 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1245 | ||
7f3c4072 CM |
1246 | /* Is the given value a sign-extended 9-bit value? */ |
1247 | #define IS_SEXT_9BIT_NUM(x) \ | |
1248 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1249 | ||
2051e8c4 MR |
1250 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1251 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1252 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1253 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1254 | ||
bf12938e RS |
1255 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1256 | SHIFT places. */ | |
1257 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1258 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1259 | ||
bf12938e | 1260 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1261 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1262 | (!(MICROMIPS) \ | |
1263 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1264 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1265 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1266 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1267 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1268 | MIPS16OP_MASK_##FIELD, \ | |
1269 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1270 | |
1271 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1272 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1273 | \f |
df58fc94 RS |
1274 | /* Whether or not we are emitting a branch-likely macro. */ |
1275 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1276 | ||
4d7206a2 RS |
1277 | /* Global variables used when generating relaxable macros. See the |
1278 | comment above RELAX_ENCODE for more details about how relaxation | |
1279 | is used. */ | |
1280 | static struct { | |
1281 | /* 0 if we're not emitting a relaxable macro. | |
1282 | 1 if we're emitting the first of the two relaxation alternatives. | |
1283 | 2 if we're emitting the second alternative. */ | |
1284 | int sequence; | |
1285 | ||
1286 | /* The first relaxable fixup in the current frag. (In other words, | |
1287 | the first fixup that refers to relaxable code.) */ | |
1288 | fixS *first_fixup; | |
1289 | ||
1290 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1291 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1292 | unsigned int sizes[2]; | |
1293 | ||
1294 | /* The symbol on which the choice of sequence depends. */ | |
1295 | symbolS *symbol; | |
1296 | } mips_relax; | |
252b5132 | 1297 | \f |
584892a6 RS |
1298 | /* Global variables used to decide whether a macro needs a warning. */ |
1299 | static struct { | |
1300 | /* True if the macro is in a branch delay slot. */ | |
1301 | bfd_boolean delay_slot_p; | |
1302 | ||
df58fc94 RS |
1303 | /* Set to the length in bytes required if the macro is in a delay slot |
1304 | that requires a specific length of instruction, otherwise zero. */ | |
1305 | unsigned int delay_slot_length; | |
1306 | ||
584892a6 RS |
1307 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1308 | in bytes and sizes[1] is the length of the second alternative. | |
1309 | For non-relaxable macros, both elements give the length of the | |
1310 | macro in bytes. */ | |
1311 | unsigned int sizes[2]; | |
1312 | ||
df58fc94 RS |
1313 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1314 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1315 | is the length of the first instruction of the second alternative. | |
1316 | For non-relaxable macros, both elements give the length of the first | |
1317 | instruction in bytes. | |
1318 | ||
1319 | Set to zero if we haven't yet seen the first instruction. */ | |
1320 | unsigned int first_insn_sizes[2]; | |
1321 | ||
1322 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1323 | first alternative and insns[1] is the number of instructions for the | |
1324 | second alternative. | |
1325 | ||
1326 | For non-relaxable macros, both elements give the number of | |
1327 | instructions for the macro. */ | |
1328 | unsigned int insns[2]; | |
1329 | ||
584892a6 RS |
1330 | /* The first variant frag for this macro. */ |
1331 | fragS *first_frag; | |
1332 | } mips_macro_warning; | |
1333 | \f | |
252b5132 RH |
1334 | /* Prototypes for static functions. */ |
1335 | ||
252b5132 RH |
1336 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1337 | ||
b34976b6 | 1338 | static void append_insn |
df58fc94 RS |
1339 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1340 | bfd_boolean expansionp); | |
7d10b47d | 1341 | static void mips_no_prev_insn (void); |
c67a084a | 1342 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1343 | static void mips16_macro_build |
03ea81db | 1344 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1345 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1346 | static void macro_start (void); |
1347 | static void macro_end (void); | |
833794fc | 1348 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1349 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1350 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1351 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1352 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1353 | static void mips16_immed |
3b4dbbbf | 1354 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1355 | unsigned int, unsigned long *); |
5e0116d5 | 1356 | static size_t my_getSmallExpression |
17a2f251 TS |
1357 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1358 | static void my_getExpression (expressionS *, char *); | |
1359 | static void s_align (int); | |
1360 | static void s_change_sec (int); | |
1361 | static void s_change_section (int); | |
1362 | static void s_cons (int); | |
1363 | static void s_float_cons (int); | |
1364 | static void s_mips_globl (int); | |
1365 | static void s_option (int); | |
1366 | static void s_mipsset (int); | |
1367 | static void s_abicalls (int); | |
1368 | static void s_cpload (int); | |
1369 | static void s_cpsetup (int); | |
1370 | static void s_cplocal (int); | |
1371 | static void s_cprestore (int); | |
1372 | static void s_cpreturn (int); | |
741d6ea8 JM |
1373 | static void s_dtprelword (int); |
1374 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1375 | static void s_tprelword (int); |
1376 | static void s_tpreldword (int); | |
17a2f251 TS |
1377 | static void s_gpvalue (int); |
1378 | static void s_gpword (int); | |
1379 | static void s_gpdword (int); | |
a3f278e2 | 1380 | static void s_ehword (int); |
17a2f251 TS |
1381 | static void s_cpadd (int); |
1382 | static void s_insn (int); | |
ba92f887 | 1383 | static void s_nan (int); |
919731af | 1384 | static void s_module (int); |
17a2f251 TS |
1385 | static void s_mips_ent (int); |
1386 | static void s_mips_end (int); | |
1387 | static void s_mips_frame (int); | |
1388 | static void s_mips_mask (int reg_type); | |
1389 | static void s_mips_stab (int); | |
1390 | static void s_mips_weakext (int); | |
1391 | static void s_mips_file (int); | |
1392 | static void s_mips_loc (int); | |
9e009953 | 1393 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1394 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1395 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1396 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1397 | static void file_mips_check_options (void); |
e7af610e NC |
1398 | |
1399 | /* Table and functions used to map between CPU/ISA names, and | |
1400 | ISA levels, and CPU numbers. */ | |
1401 | ||
e972090a NC |
1402 | struct mips_cpu_info |
1403 | { | |
e7af610e | 1404 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1405 | int flags; /* MIPS_CPU_* flags. */ |
1406 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1407 | int isa; /* ISA level. */ |
1408 | int cpu; /* CPU number (default CPU if ISA). */ | |
1409 | }; | |
1410 | ||
ad3fea08 | 1411 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1412 | |
17a2f251 TS |
1413 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1414 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1415 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1416 | \f |
c31f3936 RS |
1417 | /* Command-line options. */ |
1418 | const char *md_shortopts = "O::g::G:"; | |
1419 | ||
1420 | enum options | |
1421 | { | |
1422 | OPTION_MARCH = OPTION_MD_BASE, | |
1423 | OPTION_MTUNE, | |
1424 | OPTION_MIPS1, | |
1425 | OPTION_MIPS2, | |
1426 | OPTION_MIPS3, | |
1427 | OPTION_MIPS4, | |
1428 | OPTION_MIPS5, | |
1429 | OPTION_MIPS32, | |
1430 | OPTION_MIPS64, | |
1431 | OPTION_MIPS32R2, | |
ae52f483 AB |
1432 | OPTION_MIPS32R3, |
1433 | OPTION_MIPS32R5, | |
7361da2c | 1434 | OPTION_MIPS32R6, |
c31f3936 | 1435 | OPTION_MIPS64R2, |
ae52f483 AB |
1436 | OPTION_MIPS64R3, |
1437 | OPTION_MIPS64R5, | |
7361da2c | 1438 | OPTION_MIPS64R6, |
c31f3936 RS |
1439 | OPTION_MIPS16, |
1440 | OPTION_NO_MIPS16, | |
1441 | OPTION_MIPS3D, | |
1442 | OPTION_NO_MIPS3D, | |
1443 | OPTION_MDMX, | |
1444 | OPTION_NO_MDMX, | |
1445 | OPTION_DSP, | |
1446 | OPTION_NO_DSP, | |
1447 | OPTION_MT, | |
1448 | OPTION_NO_MT, | |
1449 | OPTION_VIRT, | |
1450 | OPTION_NO_VIRT, | |
56d438b1 CF |
1451 | OPTION_MSA, |
1452 | OPTION_NO_MSA, | |
c31f3936 RS |
1453 | OPTION_SMARTMIPS, |
1454 | OPTION_NO_SMARTMIPS, | |
1455 | OPTION_DSPR2, | |
1456 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1457 | OPTION_DSPR3, |
1458 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1459 | OPTION_EVA, |
1460 | OPTION_NO_EVA, | |
7d64c587 AB |
1461 | OPTION_XPA, |
1462 | OPTION_NO_XPA, | |
c31f3936 RS |
1463 | OPTION_MICROMIPS, |
1464 | OPTION_NO_MICROMIPS, | |
1465 | OPTION_MCU, | |
1466 | OPTION_NO_MCU, | |
25499ac7 MR |
1467 | OPTION_MIPS16E2, |
1468 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1469 | OPTION_CRC, |
1470 | OPTION_NO_CRC, | |
c31f3936 RS |
1471 | OPTION_M4650, |
1472 | OPTION_NO_M4650, | |
1473 | OPTION_M4010, | |
1474 | OPTION_NO_M4010, | |
1475 | OPTION_M4100, | |
1476 | OPTION_NO_M4100, | |
1477 | OPTION_M3900, | |
1478 | OPTION_NO_M3900, | |
1479 | OPTION_M7000_HILO_FIX, | |
1480 | OPTION_MNO_7000_HILO_FIX, | |
1481 | OPTION_FIX_24K, | |
1482 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1483 | OPTION_FIX_RM7000, |
1484 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1485 | OPTION_FIX_LOONGSON2F_JUMP, |
1486 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1487 | OPTION_FIX_LOONGSON2F_NOP, | |
1488 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1489 | OPTION_FIX_VR4120, | |
1490 | OPTION_NO_FIX_VR4120, | |
1491 | OPTION_FIX_VR4130, | |
1492 | OPTION_NO_FIX_VR4130, | |
1493 | OPTION_FIX_CN63XXP1, | |
1494 | OPTION_NO_FIX_CN63XXP1, | |
27c634e0 FN |
1495 | OPTION_FIX_R5900, |
1496 | OPTION_NO_FIX_R5900, | |
c31f3936 RS |
1497 | OPTION_TRAP, |
1498 | OPTION_BREAK, | |
1499 | OPTION_EB, | |
1500 | OPTION_EL, | |
1501 | OPTION_FP32, | |
1502 | OPTION_GP32, | |
1503 | OPTION_CONSTRUCT_FLOATS, | |
1504 | OPTION_NO_CONSTRUCT_FLOATS, | |
1505 | OPTION_FP64, | |
351cdf24 | 1506 | OPTION_FPXX, |
c31f3936 RS |
1507 | OPTION_GP64, |
1508 | OPTION_RELAX_BRANCH, | |
1509 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1510 | OPTION_IGNORE_BRANCH_ISA, |
1511 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1512 | OPTION_INSN32, |
1513 | OPTION_NO_INSN32, | |
c31f3936 RS |
1514 | OPTION_MSHARED, |
1515 | OPTION_MNO_SHARED, | |
1516 | OPTION_MSYM32, | |
1517 | OPTION_MNO_SYM32, | |
1518 | OPTION_SOFT_FLOAT, | |
1519 | OPTION_HARD_FLOAT, | |
1520 | OPTION_SINGLE_FLOAT, | |
1521 | OPTION_DOUBLE_FLOAT, | |
1522 | OPTION_32, | |
c31f3936 RS |
1523 | OPTION_CALL_SHARED, |
1524 | OPTION_CALL_NONPIC, | |
1525 | OPTION_NON_SHARED, | |
1526 | OPTION_XGOT, | |
1527 | OPTION_MABI, | |
1528 | OPTION_N32, | |
1529 | OPTION_64, | |
1530 | OPTION_MDEBUG, | |
1531 | OPTION_NO_MDEBUG, | |
1532 | OPTION_PDR, | |
1533 | OPTION_NO_PDR, | |
1534 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1535 | OPTION_NAN, |
351cdf24 MF |
1536 | OPTION_ODD_SPREG, |
1537 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1538 | OPTION_GINV, |
1539 | OPTION_NO_GINV, | |
8095d2f7 CX |
1540 | OPTION_LOONGSON_MMI, |
1541 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1542 | OPTION_LOONGSON_CAM, |
1543 | OPTION_NO_LOONGSON_CAM, | |
bdc6c06e CX |
1544 | OPTION_LOONGSON_EXT, |
1545 | OPTION_NO_LOONGSON_EXT, | |
a693765e CX |
1546 | OPTION_LOONGSON_EXT2, |
1547 | OPTION_NO_LOONGSON_EXT2, | |
c31f3936 RS |
1548 | OPTION_END_OF_ENUM |
1549 | }; | |
1550 | ||
1551 | struct option md_longopts[] = | |
1552 | { | |
1553 | /* Options which specify architecture. */ | |
1554 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1555 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1556 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1557 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1558 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1559 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1560 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1561 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1562 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1563 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1564 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1565 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1566 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1567 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1568 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1569 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1570 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1571 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1572 | |
1573 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1574 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1575 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1576 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1577 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1578 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1579 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1580 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1581 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1582 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1583 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1584 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1585 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1586 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1587 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1588 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1589 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1590 | {"meva", no_argument, NULL, OPTION_EVA}, |
1591 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1592 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1593 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1594 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1595 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1596 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1597 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1598 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1599 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1600 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1601 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1602 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1603 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1604 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1605 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1606 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1607 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1608 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1609 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1610 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1611 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
bdc6c06e CX |
1612 | {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, |
1613 | {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
a693765e CX |
1614 | {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, |
1615 | {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
c31f3936 RS |
1616 | |
1617 | /* Old-style architecture options. Don't add more of these. */ | |
1618 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1619 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1620 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1621 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1622 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1623 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1624 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1625 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1626 | ||
1627 | /* Options which enable bug fixes. */ | |
1628 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1629 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1630 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1631 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1632 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1633 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1634 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1635 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1636 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1637 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1638 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1639 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1640 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1641 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1642 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1643 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1644 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
27c634e0 FN |
1645 | {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, |
1646 | {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, | |
c31f3936 RS |
1647 | |
1648 | /* Miscellaneous options. */ | |
1649 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1650 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1651 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1652 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1653 | {"EB", no_argument, NULL, OPTION_EB}, | |
1654 | {"EL", no_argument, NULL, OPTION_EL}, | |
1655 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1656 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1657 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1658 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1659 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1660 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1661 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1662 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1663 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1664 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1665 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1666 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1667 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1668 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1669 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1670 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1671 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1672 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1673 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1674 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1675 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1676 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1677 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1678 | |
1679 | /* Strictly speaking this next option is ELF specific, | |
1680 | but we allow it for other ports as well in order to | |
1681 | make testing easier. */ | |
1682 | {"32", no_argument, NULL, OPTION_32}, | |
1683 | ||
1684 | /* ELF-specific options. */ | |
c31f3936 RS |
1685 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1686 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1687 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1688 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1689 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1690 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1691 | {"n32", no_argument, NULL, OPTION_N32}, | |
1692 | {"64", no_argument, NULL, OPTION_64}, | |
1693 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1694 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1695 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1696 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1697 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1698 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1699 | |
1700 | {NULL, no_argument, NULL, 0} | |
1701 | }; | |
1702 | size_t md_longopts_size = sizeof (md_longopts); | |
1703 | \f | |
c6278170 RS |
1704 | /* Information about either an Application Specific Extension or an |
1705 | optional architecture feature that, for simplicity, we treat in the | |
1706 | same way as an ASE. */ | |
1707 | struct mips_ase | |
1708 | { | |
1709 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1710 | const char *name; | |
1711 | ||
1712 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1713 | and 64-bit architectures, the flags here refer to the subset that | |
1714 | is available on both. */ | |
1715 | unsigned int flags; | |
1716 | ||
1717 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1718 | architectures but that are not included in FLAGS. */ | |
1719 | unsigned int flags64; | |
1720 | ||
1721 | /* The command-line options that turn the ASE on and off. */ | |
1722 | int option_on; | |
1723 | int option_off; | |
1724 | ||
1725 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1726 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1727 | int mips32_rev; | |
1728 | int mips64_rev; | |
1729 | int micromips32_rev; | |
1730 | int micromips64_rev; | |
7361da2c AB |
1731 | |
1732 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1733 | been removed. */ | |
1734 | int rem_rev; | |
c6278170 RS |
1735 | }; |
1736 | ||
1737 | /* A table of all supported ASEs. */ | |
1738 | static const struct mips_ase mips_ases[] = { | |
1739 | { "dsp", ASE_DSP, ASE_DSP64, | |
1740 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1741 | 2, 2, 2, 2, |
1742 | -1 }, | |
c6278170 RS |
1743 | |
1744 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1745 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1746 | 2, 2, 2, 2, |
1747 | -1 }, | |
c6278170 | 1748 | |
8f4f9071 MF |
1749 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1750 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1751 | 6, 6, -1, -1, | |
1752 | -1 }, | |
1753 | ||
c6278170 RS |
1754 | { "eva", ASE_EVA, 0, |
1755 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1756 | 2, 2, 2, 2, |
1757 | -1 }, | |
c6278170 RS |
1758 | |
1759 | { "mcu", ASE_MCU, 0, | |
1760 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1761 | 2, 2, 2, 2, |
1762 | -1 }, | |
c6278170 RS |
1763 | |
1764 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1765 | { "mdmx", ASE_MDMX, 0, | |
1766 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1767 | -1, 1, -1, -1, |
1768 | 6 }, | |
c6278170 RS |
1769 | |
1770 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1771 | { "mips3d", ASE_MIPS3D, 0, | |
1772 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1773 | 2, 1, -1, -1, |
1774 | 6 }, | |
c6278170 RS |
1775 | |
1776 | { "mt", ASE_MT, 0, | |
1777 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1778 | 2, 2, -1, -1, |
1779 | -1 }, | |
c6278170 RS |
1780 | |
1781 | { "smartmips", ASE_SMARTMIPS, 0, | |
1782 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1783 | 1, -1, -1, -1, |
1784 | 6 }, | |
c6278170 RS |
1785 | |
1786 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1787 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1788 | 2, 2, 2, 2, |
1789 | -1 }, | |
56d438b1 CF |
1790 | |
1791 | { "msa", ASE_MSA, ASE_MSA64, | |
1792 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1793 | 2, 2, 2, 2, |
1794 | -1 }, | |
7d64c587 AB |
1795 | |
1796 | { "xpa", ASE_XPA, 0, | |
1797 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1798 | 2, 2, 2, 2, |
7361da2c | 1799 | -1 }, |
25499ac7 MR |
1800 | |
1801 | { "mips16e2", ASE_MIPS16E2, 0, | |
1802 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1803 | 2, 2, -1, -1, | |
1804 | 6 }, | |
730c3174 SE |
1805 | |
1806 | { "crc", ASE_CRC, ASE_CRC64, | |
1807 | OPTION_CRC, OPTION_NO_CRC, | |
1808 | 6, 6, -1, -1, | |
1809 | -1 }, | |
6f20c942 FS |
1810 | |
1811 | { "ginv", ASE_GINV, 0, | |
1812 | OPTION_GINV, OPTION_NO_GINV, | |
1813 | 6, 6, 6, 6, | |
1814 | -1 }, | |
8095d2f7 CX |
1815 | |
1816 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1817 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1818 | 0, 0, -1, -1, | |
1819 | -1 }, | |
716c08de CX |
1820 | |
1821 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1822 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1823 | 0, 0, -1, -1, | |
1824 | -1 }, | |
bdc6c06e CX |
1825 | |
1826 | { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
1827 | OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
1828 | 0, 0, -1, -1, | |
1829 | -1 }, | |
a693765e CX |
1830 | |
1831 | { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
1832 | OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
1833 | 0, 0, -1, -1, | |
1834 | -1 }, | |
c6278170 RS |
1835 | }; |
1836 | ||
1837 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1838 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1839 | |
1840 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1841 | static const unsigned int mips_ase_groups[] = { | |
a693765e CX |
1842 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3, |
1843 | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
c6278170 RS |
1844 | }; |
1845 | \f | |
252b5132 RH |
1846 | /* Pseudo-op table. |
1847 | ||
1848 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1849 | should be defined here, but are currently unsupported: .alias, | |
1850 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1851 | ||
1852 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1853 | specific to the type of debugging information being generated, and | |
1854 | should be defined by the object format: .aent, .begin, .bend, | |
1855 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1856 | .vreg. | |
1857 | ||
1858 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1859 | not MIPS CPU specific, but are also not specific to the object file | |
1860 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1861 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1862 | |
e972090a NC |
1863 | static const pseudo_typeS mips_pseudo_table[] = |
1864 | { | |
beae10d5 | 1865 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1866 | {"option", s_option, 0}, |
1867 | {"set", s_mipsset, 0}, | |
1868 | {"rdata", s_change_sec, 'r'}, | |
1869 | {"sdata", s_change_sec, 's'}, | |
1870 | {"livereg", s_ignore, 0}, | |
1871 | {"abicalls", s_abicalls, 0}, | |
1872 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1873 | {"cpsetup", s_cpsetup, 0}, |
1874 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1875 | {"cprestore", s_cprestore, 0}, |
6478892d | 1876 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1877 | {"dtprelword", s_dtprelword, 0}, |
1878 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1879 | {"tprelword", s_tprelword, 0}, |
1880 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1881 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1882 | {"gpword", s_gpword, 0}, |
10181a0d | 1883 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1884 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1885 | {"cpadd", s_cpadd, 0}, |
1886 | {"insn", s_insn, 0}, | |
ba92f887 | 1887 | {"nan", s_nan, 0}, |
919731af | 1888 | {"module", s_module, 0}, |
252b5132 | 1889 | |
beae10d5 | 1890 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1891 | chips. */ |
38a57ae7 | 1892 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1893 | {"bss", s_change_sec, 'b'}, |
1894 | {"err", s_err, 0}, | |
1895 | {"half", s_cons, 1}, | |
1896 | {"dword", s_cons, 3}, | |
1897 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1898 | {"origin", s_org, 0}, |
1899 | {"repeat", s_rept, 0}, | |
252b5132 | 1900 | |
998b3c36 MR |
1901 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1902 | {"sbss", s_change_sec, 'B'}, | |
1903 | ||
beae10d5 | 1904 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1905 | here for one reason or another. */ |
1906 | {"align", s_align, 0}, | |
1907 | {"byte", s_cons, 0}, | |
1908 | {"data", s_change_sec, 'd'}, | |
1909 | {"double", s_float_cons, 'd'}, | |
1910 | {"float", s_float_cons, 'f'}, | |
1911 | {"globl", s_mips_globl, 0}, | |
1912 | {"global", s_mips_globl, 0}, | |
1913 | {"hword", s_cons, 1}, | |
1914 | {"int", s_cons, 2}, | |
1915 | {"long", s_cons, 2}, | |
1916 | {"octa", s_cons, 4}, | |
1917 | {"quad", s_cons, 3}, | |
cca86cc8 | 1918 | {"section", s_change_section, 0}, |
252b5132 RH |
1919 | {"short", s_cons, 1}, |
1920 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1921 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1922 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1923 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1924 | {"text", s_change_sec, 't'}, |
1925 | {"word", s_cons, 2}, | |
add56521 | 1926 | |
add56521 | 1927 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1928 | |
43841e91 | 1929 | { NULL, NULL, 0 }, |
252b5132 RH |
1930 | }; |
1931 | ||
e972090a NC |
1932 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1933 | { | |
beae10d5 KH |
1934 | /* These pseudo-ops should be defined by the object file format. |
1935 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1936 | {"aent", s_mips_ent, 1}, |
1937 | {"bgnb", s_ignore, 0}, | |
1938 | {"end", s_mips_end, 0}, | |
1939 | {"endb", s_ignore, 0}, | |
1940 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1941 | {"file", s_mips_file, 0}, |
252b5132 RH |
1942 | {"fmask", s_mips_mask, 'F'}, |
1943 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1944 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1945 | {"mask", s_mips_mask, 'R'}, |
1946 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1947 | { NULL, NULL, 0 }, |
252b5132 RH |
1948 | }; |
1949 | ||
3ae8dd8d MR |
1950 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1951 | purpose of the `.dc.a' internal pseudo-op. */ | |
1952 | ||
1953 | int | |
1954 | mips_address_bytes (void) | |
1955 | { | |
919731af | 1956 | file_mips_check_options (); |
3ae8dd8d MR |
1957 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1958 | } | |
1959 | ||
17a2f251 | 1960 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1961 | |
1962 | void | |
17a2f251 | 1963 | mips_pop_insert (void) |
252b5132 RH |
1964 | { |
1965 | pop_insert (mips_pseudo_table); | |
1966 | if (! ECOFF_DEBUGGING) | |
1967 | pop_insert (mips_nonecoff_pseudo_table); | |
1968 | } | |
1969 | \f | |
1970 | /* Symbols labelling the current insn. */ | |
1971 | ||
e972090a NC |
1972 | struct insn_label_list |
1973 | { | |
252b5132 RH |
1974 | struct insn_label_list *next; |
1975 | symbolS *label; | |
1976 | }; | |
1977 | ||
252b5132 | 1978 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1979 | #define label_list tc_segment_info_data.labels |
252b5132 | 1980 | |
17a2f251 | 1981 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1982 | static void mips_mark_labels (void); |
1983 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1984 | |
1985 | static inline void | |
17a2f251 | 1986 | mips_clear_insn_labels (void) |
252b5132 | 1987 | { |
ed9e98c2 | 1988 | struct insn_label_list **pl; |
a8dbcb85 | 1989 | segment_info_type *si; |
252b5132 | 1990 | |
a8dbcb85 TS |
1991 | if (now_seg) |
1992 | { | |
1993 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1994 | ; | |
3739860c | 1995 | |
a8dbcb85 TS |
1996 | si = seg_info (now_seg); |
1997 | *pl = si->label_list; | |
1998 | si->label_list = NULL; | |
1999 | } | |
252b5132 | 2000 | } |
a8dbcb85 | 2001 | |
df58fc94 RS |
2002 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
2003 | ||
2004 | static inline void | |
2005 | mips_mark_labels (void) | |
2006 | { | |
2007 | if (HAVE_CODE_COMPRESSION) | |
2008 | mips_compressed_mark_labels (); | |
2009 | } | |
252b5132 RH |
2010 | \f |
2011 | static char *expr_end; | |
2012 | ||
e423441d | 2013 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 2014 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
2015 | |
2016 | static expressionS imm_expr; | |
252b5132 | 2017 | |
77bd4346 RS |
2018 | /* The relocatable field in an instruction and the relocs associated |
2019 | with it. These variables are used for instructions like LUI and | |
2020 | JAL as well as true offsets. They are also used for address | |
2021 | operands in macros. */ | |
252b5132 | 2022 | |
77bd4346 | 2023 | static expressionS offset_expr; |
f6688943 TS |
2024 | static bfd_reloc_code_real_type offset_reloc[3] |
2025 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2026 | |
df58fc94 RS |
2027 | /* This is set to the resulting size of the instruction to be produced |
2028 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2029 | explicit size is supplied. */ | |
252b5132 | 2030 | |
df58fc94 | 2031 | static unsigned int forced_insn_length; |
252b5132 | 2032 | |
e1b47bd5 RS |
2033 | /* True if we are assembling an instruction. All dot symbols defined during |
2034 | this time should be treated as code labels. */ | |
2035 | ||
2036 | static bfd_boolean mips_assembling_insn; | |
2037 | ||
ecb4347a DJ |
2038 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2039 | ECOFF debugging. */ | |
252b5132 RH |
2040 | |
2041 | static segT pdr_seg; | |
252b5132 | 2042 | |
e013f690 TS |
2043 | /* The default target format to use. */ |
2044 | ||
aeffff67 RS |
2045 | #if defined (TE_FreeBSD) |
2046 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2047 | #elif defined (TE_TMIPS) | |
2048 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2049 | #else | |
2050 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2051 | #endif | |
2052 | ||
e013f690 | 2053 | const char * |
17a2f251 | 2054 | mips_target_format (void) |
e013f690 TS |
2055 | { |
2056 | switch (OUTPUT_FLAVOR) | |
2057 | { | |
e013f690 | 2058 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2059 | #ifdef TE_VXWORKS |
2060 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2061 | return (target_big_endian | |
2062 | ? "elf32-bigmips-vxworks" | |
2063 | : "elf32-littlemips-vxworks"); | |
2064 | #endif | |
e013f690 | 2065 | return (target_big_endian |
cfe86eaa | 2066 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2067 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2068 | : (HAVE_NEWABI |
aeffff67 RS |
2069 | ? ELF_TARGET ("elf32-n", "big") |
2070 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2071 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2072 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2073 | : (HAVE_NEWABI |
aeffff67 RS |
2074 | ? ELF_TARGET ("elf32-n", "little") |
2075 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2076 | default: |
2077 | abort (); | |
2078 | return NULL; | |
2079 | } | |
2080 | } | |
2081 | ||
c6278170 RS |
2082 | /* Return the ISA revision that is currently in use, or 0 if we are |
2083 | generating code for MIPS V or below. */ | |
2084 | ||
2085 | static int | |
2086 | mips_isa_rev (void) | |
2087 | { | |
2088 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2089 | return 2; | |
2090 | ||
ae52f483 AB |
2091 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2092 | return 3; | |
2093 | ||
2094 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2095 | return 5; | |
2096 | ||
7361da2c AB |
2097 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2098 | return 6; | |
2099 | ||
c6278170 RS |
2100 | /* microMIPS implies revision 2 or above. */ |
2101 | if (mips_opts.micromips) | |
2102 | return 2; | |
2103 | ||
2104 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2105 | return 1; | |
2106 | ||
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2111 | ||
2112 | static unsigned int | |
2113 | mips_ase_mask (unsigned int flags) | |
2114 | { | |
2115 | unsigned int i; | |
2116 | ||
2117 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2118 | if (flags & mips_ase_groups[i]) | |
2119 | flags |= mips_ase_groups[i]; | |
2120 | return flags; | |
2121 | } | |
2122 | ||
2123 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2124 | appropriate. */ | |
2125 | ||
2126 | static void | |
2127 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2128 | { | |
2129 | const char *base; | |
2130 | int min_rev, size; | |
2131 | static unsigned int warned_isa; | |
2132 | static unsigned int warned_fp32; | |
2133 | ||
2134 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2135 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2136 | else | |
2137 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2138 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2139 | && (warned_isa & ase->flags) != ase->flags) | |
2140 | { | |
2141 | warned_isa |= ase->flags; | |
2142 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2143 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2144 | if (min_rev < 0) | |
1661c76c | 2145 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2146 | " `%s' extension"), size, base, ase->name); |
2147 | else | |
1661c76c | 2148 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2149 | ase->name, base, size, min_rev); |
2150 | } | |
7361da2c AB |
2151 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2152 | && (warned_isa & ase->flags) != ase->flags) | |
2153 | { | |
2154 | warned_isa |= ase->flags; | |
2155 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2156 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2157 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2158 | ase->name, base, size, ase->rem_rev); | |
2159 | } | |
2160 | ||
c6278170 | 2161 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2162 | && mips_opts.fp != 64 |
c6278170 RS |
2163 | && (warned_fp32 & ase->flags) != ase->flags) |
2164 | { | |
2165 | warned_fp32 |= ase->flags; | |
1661c76c | 2166 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2167 | } |
2168 | } | |
2169 | ||
2170 | /* Check all enabled ASEs to see whether they are supported by the | |
2171 | chosen architecture. */ | |
2172 | ||
2173 | static void | |
2174 | mips_check_isa_supports_ases (void) | |
2175 | { | |
2176 | unsigned int i, mask; | |
2177 | ||
2178 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2179 | { | |
2180 | mask = mips_ase_mask (mips_ases[i].flags); | |
2181 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2182 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2183 | } | |
2184 | } | |
2185 | ||
2186 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2187 | that were affected. */ | |
2188 | ||
2189 | static unsigned int | |
919731af | 2190 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2191 | bfd_boolean enabled_p) | |
c6278170 RS |
2192 | { |
2193 | unsigned int mask; | |
2194 | ||
2195 | mask = mips_ase_mask (ase->flags); | |
919731af | 2196 | opts->ase &= ~mask; |
92cebb3d MR |
2197 | |
2198 | /* Clear combination ASE flags, which need to be recalculated based on | |
2199 | updated regular ASE settings. */ | |
9785fc2a | 2200 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT); |
92cebb3d | 2201 | |
c6278170 | 2202 | if (enabled_p) |
919731af | 2203 | opts->ase |= ase->flags; |
25499ac7 | 2204 | |
9785fc2a MR |
2205 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2206 | instructions which are only valid when both ASEs are enabled. | |
2207 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2208 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2209 | { | |
2210 | opts->ase |= ASE_XPA_VIRT; | |
2211 | mask |= ASE_XPA_VIRT; | |
2212 | } | |
25499ac7 MR |
2213 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2214 | { | |
2215 | opts->ase |= ASE_MIPS16E2_MT; | |
2216 | mask |= ASE_MIPS16E2_MT; | |
2217 | } | |
2218 | ||
c6278170 RS |
2219 | return mask; |
2220 | } | |
2221 | ||
2222 | /* Return the ASE called NAME, or null if none. */ | |
2223 | ||
2224 | static const struct mips_ase * | |
2225 | mips_lookup_ase (const char *name) | |
2226 | { | |
2227 | unsigned int i; | |
2228 | ||
2229 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2230 | if (strcmp (name, mips_ases[i].name) == 0) | |
2231 | return &mips_ases[i]; | |
2232 | return NULL; | |
2233 | } | |
2234 | ||
df58fc94 | 2235 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2236 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2237 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2238 | |
2239 | static inline unsigned int | |
2240 | micromips_insn_length (const struct mips_opcode *mo) | |
2241 | { | |
7fd53920 | 2242 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2243 | } |
2244 | ||
5c04167a RS |
2245 | /* Return the length of MIPS16 instruction OPCODE. */ |
2246 | ||
2247 | static inline unsigned int | |
2248 | mips16_opcode_length (unsigned long opcode) | |
2249 | { | |
2250 | return (opcode >> 16) == 0 ? 2 : 4; | |
2251 | } | |
2252 | ||
1e915849 RS |
2253 | /* Return the length of instruction INSN. */ |
2254 | ||
2255 | static inline unsigned int | |
2256 | insn_length (const struct mips_cl_insn *insn) | |
2257 | { | |
df58fc94 RS |
2258 | if (mips_opts.micromips) |
2259 | return micromips_insn_length (insn->insn_mo); | |
2260 | else if (mips_opts.mips16) | |
5c04167a | 2261 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2262 | else |
1e915849 | 2263 | return 4; |
1e915849 RS |
2264 | } |
2265 | ||
2266 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2267 | ||
2268 | static void | |
2269 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2270 | { | |
2271 | size_t i; | |
2272 | ||
2273 | insn->insn_mo = mo; | |
1e915849 RS |
2274 | insn->insn_opcode = mo->match; |
2275 | insn->frag = NULL; | |
2276 | insn->where = 0; | |
2277 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2278 | insn->fixp[i] = NULL; | |
2279 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2280 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2281 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2282 | insn->complete_p = 0; |
e407c74b | 2283 | insn->cleared_p = 0; |
1e915849 RS |
2284 | } |
2285 | ||
fc76e730 RS |
2286 | /* Get a list of all the operands in INSN. */ |
2287 | ||
2288 | static const struct mips_operand_array * | |
2289 | insn_operands (const struct mips_cl_insn *insn) | |
2290 | { | |
2291 | if (insn->insn_mo >= &mips_opcodes[0] | |
2292 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2293 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2294 | ||
2295 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2296 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2297 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2298 | ||
2299 | if (insn->insn_mo >= µmips_opcodes[0] | |
2300 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2301 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2302 | ||
2303 | abort (); | |
2304 | } | |
2305 | ||
2306 | /* Get a description of operand OPNO of INSN. */ | |
2307 | ||
2308 | static const struct mips_operand * | |
2309 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2310 | { | |
2311 | const struct mips_operand_array *operands; | |
2312 | ||
2313 | operands = insn_operands (insn); | |
2314 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2315 | abort (); | |
2316 | return operands->operand[opno]; | |
2317 | } | |
2318 | ||
e077a1c8 RS |
2319 | /* Install UVAL as the value of OPERAND in INSN. */ |
2320 | ||
2321 | static inline void | |
2322 | insn_insert_operand (struct mips_cl_insn *insn, | |
2323 | const struct mips_operand *operand, unsigned int uval) | |
2324 | { | |
25499ac7 MR |
2325 | if (mips_opts.mips16 |
2326 | && operand->type == OP_INT && operand->lsb == 0 | |
2327 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2328 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2329 | else | |
2330 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2331 | } |
2332 | ||
fc76e730 RS |
2333 | /* Extract the value of OPERAND from INSN. */ |
2334 | ||
2335 | static inline unsigned | |
2336 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2337 | const struct mips_operand *operand) | |
2338 | { | |
2339 | return mips_extract_operand (operand, insn->insn_opcode); | |
2340 | } | |
2341 | ||
df58fc94 | 2342 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2343 | |
2344 | static void | |
df58fc94 | 2345 | mips_record_compressed_mode (void) |
742a56fe RS |
2346 | { |
2347 | segment_info_type *si; | |
2348 | ||
2349 | si = seg_info (now_seg); | |
2350 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2351 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2352 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2353 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2354 | } |
2355 | ||
4d68580a RS |
2356 | /* Read a standard MIPS instruction from BUF. */ |
2357 | ||
2358 | static unsigned long | |
2359 | read_insn (char *buf) | |
2360 | { | |
2361 | if (target_big_endian) | |
2362 | return bfd_getb32 ((bfd_byte *) buf); | |
2363 | else | |
2364 | return bfd_getl32 ((bfd_byte *) buf); | |
2365 | } | |
2366 | ||
2367 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2368 | the next byte. */ | |
2369 | ||
2370 | static char * | |
2371 | write_insn (char *buf, unsigned int insn) | |
2372 | { | |
2373 | md_number_to_chars (buf, insn, 4); | |
2374 | return buf + 4; | |
2375 | } | |
2376 | ||
2377 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2378 | has length LENGTH. */ | |
2379 | ||
2380 | static unsigned long | |
2381 | read_compressed_insn (char *buf, unsigned int length) | |
2382 | { | |
2383 | unsigned long insn; | |
2384 | unsigned int i; | |
2385 | ||
2386 | insn = 0; | |
2387 | for (i = 0; i < length; i += 2) | |
2388 | { | |
2389 | insn <<= 16; | |
2390 | if (target_big_endian) | |
2391 | insn |= bfd_getb16 ((char *) buf); | |
2392 | else | |
2393 | insn |= bfd_getl16 ((char *) buf); | |
2394 | buf += 2; | |
2395 | } | |
2396 | return insn; | |
2397 | } | |
2398 | ||
5c04167a RS |
2399 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2400 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2401 | ||
2402 | static char * | |
2403 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2404 | { | |
2405 | unsigned int i; | |
2406 | ||
2407 | for (i = 0; i < length; i += 2) | |
2408 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2409 | return buf + length; | |
2410 | } | |
2411 | ||
1e915849 RS |
2412 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2413 | ||
2414 | static void | |
2415 | install_insn (const struct mips_cl_insn *insn) | |
2416 | { | |
2417 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2418 | if (HAVE_CODE_COMPRESSION) |
2419 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2420 | else |
4d68580a | 2421 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2422 | mips_record_compressed_mode (); |
1e915849 RS |
2423 | } |
2424 | ||
2425 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2426 | and install the opcode in the new location. */ | |
2427 | ||
2428 | static void | |
2429 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2430 | { | |
2431 | size_t i; | |
2432 | ||
2433 | insn->frag = frag; | |
2434 | insn->where = where; | |
2435 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2436 | if (insn->fixp[i] != NULL) | |
2437 | { | |
2438 | insn->fixp[i]->fx_frag = frag; | |
2439 | insn->fixp[i]->fx_where = where; | |
2440 | } | |
2441 | install_insn (insn); | |
2442 | } | |
2443 | ||
2444 | /* Add INSN to the end of the output. */ | |
2445 | ||
2446 | static void | |
2447 | add_fixed_insn (struct mips_cl_insn *insn) | |
2448 | { | |
2449 | char *f = frag_more (insn_length (insn)); | |
2450 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2451 | } | |
2452 | ||
2453 | /* Start a variant frag and move INSN to the start of the variant part, | |
2454 | marking it as fixed. The other arguments are as for frag_var. */ | |
2455 | ||
2456 | static void | |
2457 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2458 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2459 | { | |
2460 | frag_grow (max_chars); | |
2461 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2462 | insn->fixed_p = 1; | |
2463 | frag_var (rs_machine_dependent, max_chars, var, | |
2464 | subtype, symbol, offset, NULL); | |
2465 | } | |
2466 | ||
2467 | /* Insert N copies of INSN into the history buffer, starting at | |
2468 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2469 | ||
2470 | static void | |
2471 | insert_into_history (unsigned int first, unsigned int n, | |
2472 | const struct mips_cl_insn *insn) | |
2473 | { | |
2474 | if (mips_relax.sequence != 2) | |
2475 | { | |
2476 | unsigned int i; | |
2477 | ||
2478 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2479 | if (i >= first + n) | |
2480 | history[i] = history[i - n]; | |
2481 | else | |
2482 | history[i] = *insn; | |
2483 | } | |
2484 | } | |
2485 | ||
e3de51ce RS |
2486 | /* Clear the error in insn_error. */ |
2487 | ||
2488 | static void | |
2489 | clear_insn_error (void) | |
2490 | { | |
2491 | memset (&insn_error, 0, sizeof (insn_error)); | |
2492 | } | |
2493 | ||
2494 | /* Possibly record error message MSG for the current instruction. | |
2495 | If the error is about a particular argument, ARGNUM is the 1-based | |
2496 | number of that argument, otherwise it is 0. FORMAT is the format | |
2497 | of MSG. Return true if MSG was used, false if the current message | |
2498 | was kept. */ | |
2499 | ||
2500 | static bfd_boolean | |
2501 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2502 | const char *msg) | |
2503 | { | |
2504 | if (argnum == 0) | |
2505 | { | |
2506 | /* Give priority to errors against specific arguments, and to | |
2507 | the first whole-instruction message. */ | |
2508 | if (insn_error.msg) | |
2509 | return FALSE; | |
2510 | } | |
2511 | else | |
2512 | { | |
2513 | /* Keep insn_error if it is against a later argument. */ | |
2514 | if (argnum < insn_error.min_argnum) | |
2515 | return FALSE; | |
2516 | ||
2517 | /* If both errors are against the same argument but are different, | |
2518 | give up on reporting a specific error for this argument. | |
2519 | See the comment about mips_insn_error for details. */ | |
2520 | if (argnum == insn_error.min_argnum | |
2521 | && insn_error.msg | |
2522 | && strcmp (insn_error.msg, msg) != 0) | |
2523 | { | |
2524 | insn_error.msg = 0; | |
2525 | insn_error.min_argnum += 1; | |
2526 | return FALSE; | |
2527 | } | |
2528 | } | |
2529 | insn_error.min_argnum = argnum; | |
2530 | insn_error.format = format; | |
2531 | insn_error.msg = msg; | |
2532 | return TRUE; | |
2533 | } | |
2534 | ||
2535 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2536 | as for set_insn_error_format. */ | |
2537 | ||
2538 | static void | |
2539 | set_insn_error (int argnum, const char *msg) | |
2540 | { | |
2541 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2542 | } | |
2543 | ||
2544 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2545 | as for set_insn_error_format. */ | |
2546 | ||
2547 | static void | |
2548 | set_insn_error_i (int argnum, const char *msg, int i) | |
2549 | { | |
2550 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2551 | insn_error.u.i = i; | |
2552 | } | |
2553 | ||
2554 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2555 | are as for set_insn_error_format. */ | |
2556 | ||
2557 | static void | |
2558 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2559 | { | |
2560 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2561 | { | |
2562 | insn_error.u.ss[0] = s1; | |
2563 | insn_error.u.ss[1] = s2; | |
2564 | } | |
2565 | } | |
2566 | ||
2567 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2568 | ||
2569 | static void | |
2570 | report_insn_error (const char *str) | |
2571 | { | |
e1fa0163 | 2572 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2573 | |
e3de51ce RS |
2574 | switch (insn_error.format) |
2575 | { | |
2576 | case ERR_FMT_PLAIN: | |
2577 | as_bad (msg, str); | |
2578 | break; | |
2579 | ||
2580 | case ERR_FMT_I: | |
2581 | as_bad (msg, insn_error.u.i, str); | |
2582 | break; | |
2583 | ||
2584 | case ERR_FMT_SS: | |
2585 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2586 | break; | |
2587 | } | |
e1fa0163 NC |
2588 | |
2589 | free ((char *) msg); | |
e3de51ce RS |
2590 | } |
2591 | ||
71400594 RS |
2592 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2593 | the idea is to make it obvious at a glance that each errata is | |
2594 | included. */ | |
2595 | ||
2596 | static void | |
2597 | init_vr4120_conflicts (void) | |
2598 | { | |
2599 | #define CONFLICT(FIRST, SECOND) \ | |
2600 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2601 | ||
2602 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2603 | CONFLICT (MACC, DIV); | |
2604 | CONFLICT (DMACC, DIV); | |
2605 | ||
2606 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2607 | CONFLICT (DMULT, DMULT); | |
2608 | CONFLICT (DMULT, DMACC); | |
2609 | CONFLICT (DMACC, DMULT); | |
2610 | CONFLICT (DMACC, DMACC); | |
2611 | ||
2612 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2613 | CONFLICT (MACC, MTHILO); | |
2614 | CONFLICT (DMACC, MTHILO); | |
2615 | ||
2616 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2617 | instruction is executed immediately after a MACC or DMACC | |
2618 | instruction, the result of [either instruction] is incorrect." */ | |
2619 | CONFLICT (MACC, MULT); | |
2620 | CONFLICT (MACC, DMULT); | |
2621 | CONFLICT (DMACC, MULT); | |
2622 | CONFLICT (DMACC, DMULT); | |
2623 | ||
2624 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2625 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2626 | DDIV or DDIVU instruction, the result of the MACC or | |
2627 | DMACC instruction is incorrect.". */ | |
2628 | CONFLICT (DMULT, MACC); | |
2629 | CONFLICT (DMULT, DMACC); | |
2630 | CONFLICT (DIV, MACC); | |
2631 | CONFLICT (DIV, DMACC); | |
2632 | ||
2633 | #undef CONFLICT | |
2634 | } | |
2635 | ||
707bfff6 TS |
2636 | struct regname { |
2637 | const char *name; | |
2638 | unsigned int num; | |
2639 | }; | |
2640 | ||
14daeee3 | 2641 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2642 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2643 | #define RTYPE_NUM 0x0000100 |
2644 | #define RTYPE_FPU 0x0000200 | |
2645 | #define RTYPE_FCC 0x0000400 | |
2646 | #define RTYPE_VEC 0x0000800 | |
2647 | #define RTYPE_GP 0x0001000 | |
2648 | #define RTYPE_CP0 0x0002000 | |
2649 | #define RTYPE_PC 0x0004000 | |
2650 | #define RTYPE_ACC 0x0008000 | |
2651 | #define RTYPE_CCC 0x0010000 | |
2652 | #define RTYPE_VI 0x0020000 | |
2653 | #define RTYPE_VF 0x0040000 | |
2654 | #define RTYPE_R5900_I 0x0080000 | |
2655 | #define RTYPE_R5900_Q 0x0100000 | |
2656 | #define RTYPE_R5900_R 0x0200000 | |
2657 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2658 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2659 | #define RWARN 0x8000000 |
707bfff6 TS |
2660 | |
2661 | #define GENERIC_REGISTER_NUMBERS \ | |
2662 | {"$0", RTYPE_NUM | 0}, \ | |
2663 | {"$1", RTYPE_NUM | 1}, \ | |
2664 | {"$2", RTYPE_NUM | 2}, \ | |
2665 | {"$3", RTYPE_NUM | 3}, \ | |
2666 | {"$4", RTYPE_NUM | 4}, \ | |
2667 | {"$5", RTYPE_NUM | 5}, \ | |
2668 | {"$6", RTYPE_NUM | 6}, \ | |
2669 | {"$7", RTYPE_NUM | 7}, \ | |
2670 | {"$8", RTYPE_NUM | 8}, \ | |
2671 | {"$9", RTYPE_NUM | 9}, \ | |
2672 | {"$10", RTYPE_NUM | 10}, \ | |
2673 | {"$11", RTYPE_NUM | 11}, \ | |
2674 | {"$12", RTYPE_NUM | 12}, \ | |
2675 | {"$13", RTYPE_NUM | 13}, \ | |
2676 | {"$14", RTYPE_NUM | 14}, \ | |
2677 | {"$15", RTYPE_NUM | 15}, \ | |
2678 | {"$16", RTYPE_NUM | 16}, \ | |
2679 | {"$17", RTYPE_NUM | 17}, \ | |
2680 | {"$18", RTYPE_NUM | 18}, \ | |
2681 | {"$19", RTYPE_NUM | 19}, \ | |
2682 | {"$20", RTYPE_NUM | 20}, \ | |
2683 | {"$21", RTYPE_NUM | 21}, \ | |
2684 | {"$22", RTYPE_NUM | 22}, \ | |
2685 | {"$23", RTYPE_NUM | 23}, \ | |
2686 | {"$24", RTYPE_NUM | 24}, \ | |
2687 | {"$25", RTYPE_NUM | 25}, \ | |
2688 | {"$26", RTYPE_NUM | 26}, \ | |
2689 | {"$27", RTYPE_NUM | 27}, \ | |
2690 | {"$28", RTYPE_NUM | 28}, \ | |
2691 | {"$29", RTYPE_NUM | 29}, \ | |
2692 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2693 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2694 | |
2695 | #define FPU_REGISTER_NAMES \ | |
2696 | {"$f0", RTYPE_FPU | 0}, \ | |
2697 | {"$f1", RTYPE_FPU | 1}, \ | |
2698 | {"$f2", RTYPE_FPU | 2}, \ | |
2699 | {"$f3", RTYPE_FPU | 3}, \ | |
2700 | {"$f4", RTYPE_FPU | 4}, \ | |
2701 | {"$f5", RTYPE_FPU | 5}, \ | |
2702 | {"$f6", RTYPE_FPU | 6}, \ | |
2703 | {"$f7", RTYPE_FPU | 7}, \ | |
2704 | {"$f8", RTYPE_FPU | 8}, \ | |
2705 | {"$f9", RTYPE_FPU | 9}, \ | |
2706 | {"$f10", RTYPE_FPU | 10}, \ | |
2707 | {"$f11", RTYPE_FPU | 11}, \ | |
2708 | {"$f12", RTYPE_FPU | 12}, \ | |
2709 | {"$f13", RTYPE_FPU | 13}, \ | |
2710 | {"$f14", RTYPE_FPU | 14}, \ | |
2711 | {"$f15", RTYPE_FPU | 15}, \ | |
2712 | {"$f16", RTYPE_FPU | 16}, \ | |
2713 | {"$f17", RTYPE_FPU | 17}, \ | |
2714 | {"$f18", RTYPE_FPU | 18}, \ | |
2715 | {"$f19", RTYPE_FPU | 19}, \ | |
2716 | {"$f20", RTYPE_FPU | 20}, \ | |
2717 | {"$f21", RTYPE_FPU | 21}, \ | |
2718 | {"$f22", RTYPE_FPU | 22}, \ | |
2719 | {"$f23", RTYPE_FPU | 23}, \ | |
2720 | {"$f24", RTYPE_FPU | 24}, \ | |
2721 | {"$f25", RTYPE_FPU | 25}, \ | |
2722 | {"$f26", RTYPE_FPU | 26}, \ | |
2723 | {"$f27", RTYPE_FPU | 27}, \ | |
2724 | {"$f28", RTYPE_FPU | 28}, \ | |
2725 | {"$f29", RTYPE_FPU | 29}, \ | |
2726 | {"$f30", RTYPE_FPU | 30}, \ | |
2727 | {"$f31", RTYPE_FPU | 31} | |
2728 | ||
2729 | #define FPU_CONDITION_CODE_NAMES \ | |
2730 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2731 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2732 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2733 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2734 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2735 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2736 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2737 | {"$fcc7", RTYPE_FCC | 7} | |
2738 | ||
2739 | #define COPROC_CONDITION_CODE_NAMES \ | |
2740 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2741 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2742 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2743 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2744 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2745 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2746 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2747 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2748 | ||
2749 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2750 | {"$a4", RTYPE_GP | 8}, \ | |
2751 | {"$a5", RTYPE_GP | 9}, \ | |
2752 | {"$a6", RTYPE_GP | 10}, \ | |
2753 | {"$a7", RTYPE_GP | 11}, \ | |
2754 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2755 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2756 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2757 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2758 | {"$t0", RTYPE_GP | 12}, \ | |
2759 | {"$t1", RTYPE_GP | 13}, \ | |
2760 | {"$t2", RTYPE_GP | 14}, \ | |
2761 | {"$t3", RTYPE_GP | 15} | |
2762 | ||
2763 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2764 | {"$t0", RTYPE_GP | 8}, \ | |
2765 | {"$t1", RTYPE_GP | 9}, \ | |
2766 | {"$t2", RTYPE_GP | 10}, \ | |
2767 | {"$t3", RTYPE_GP | 11}, \ | |
2768 | {"$t4", RTYPE_GP | 12}, \ | |
2769 | {"$t5", RTYPE_GP | 13}, \ | |
2770 | {"$t6", RTYPE_GP | 14}, \ | |
2771 | {"$t7", RTYPE_GP | 15}, \ | |
2772 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2773 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2774 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2775 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2776 | |
2777 | /* Remaining symbolic register names */ | |
2778 | #define SYMBOLIC_REGISTER_NAMES \ | |
2779 | {"$zero", RTYPE_GP | 0}, \ | |
2780 | {"$at", RTYPE_GP | 1}, \ | |
2781 | {"$AT", RTYPE_GP | 1}, \ | |
2782 | {"$v0", RTYPE_GP | 2}, \ | |
2783 | {"$v1", RTYPE_GP | 3}, \ | |
2784 | {"$a0", RTYPE_GP | 4}, \ | |
2785 | {"$a1", RTYPE_GP | 5}, \ | |
2786 | {"$a2", RTYPE_GP | 6}, \ | |
2787 | {"$a3", RTYPE_GP | 7}, \ | |
2788 | {"$s0", RTYPE_GP | 16}, \ | |
2789 | {"$s1", RTYPE_GP | 17}, \ | |
2790 | {"$s2", RTYPE_GP | 18}, \ | |
2791 | {"$s3", RTYPE_GP | 19}, \ | |
2792 | {"$s4", RTYPE_GP | 20}, \ | |
2793 | {"$s5", RTYPE_GP | 21}, \ | |
2794 | {"$s6", RTYPE_GP | 22}, \ | |
2795 | {"$s7", RTYPE_GP | 23}, \ | |
2796 | {"$t8", RTYPE_GP | 24}, \ | |
2797 | {"$t9", RTYPE_GP | 25}, \ | |
2798 | {"$k0", RTYPE_GP | 26}, \ | |
2799 | {"$kt0", RTYPE_GP | 26}, \ | |
2800 | {"$k1", RTYPE_GP | 27}, \ | |
2801 | {"$kt1", RTYPE_GP | 27}, \ | |
2802 | {"$gp", RTYPE_GP | 28}, \ | |
2803 | {"$sp", RTYPE_GP | 29}, \ | |
2804 | {"$s8", RTYPE_GP | 30}, \ | |
2805 | {"$fp", RTYPE_GP | 30}, \ | |
2806 | {"$ra", RTYPE_GP | 31} | |
2807 | ||
2808 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2809 | {"$pc", RTYPE_PC | 0} | |
2810 | ||
2811 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2812 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2813 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2814 | {"$v2", RTYPE_VEC | 2}, \ | |
2815 | {"$v3", RTYPE_VEC | 3}, \ | |
2816 | {"$v4", RTYPE_VEC | 4}, \ | |
2817 | {"$v5", RTYPE_VEC | 5}, \ | |
2818 | {"$v6", RTYPE_VEC | 6}, \ | |
2819 | {"$v7", RTYPE_VEC | 7}, \ | |
2820 | {"$v8", RTYPE_VEC | 8}, \ | |
2821 | {"$v9", RTYPE_VEC | 9}, \ | |
2822 | {"$v10", RTYPE_VEC | 10}, \ | |
2823 | {"$v11", RTYPE_VEC | 11}, \ | |
2824 | {"$v12", RTYPE_VEC | 12}, \ | |
2825 | {"$v13", RTYPE_VEC | 13}, \ | |
2826 | {"$v14", RTYPE_VEC | 14}, \ | |
2827 | {"$v15", RTYPE_VEC | 15}, \ | |
2828 | {"$v16", RTYPE_VEC | 16}, \ | |
2829 | {"$v17", RTYPE_VEC | 17}, \ | |
2830 | {"$v18", RTYPE_VEC | 18}, \ | |
2831 | {"$v19", RTYPE_VEC | 19}, \ | |
2832 | {"$v20", RTYPE_VEC | 20}, \ | |
2833 | {"$v21", RTYPE_VEC | 21}, \ | |
2834 | {"$v22", RTYPE_VEC | 22}, \ | |
2835 | {"$v23", RTYPE_VEC | 23}, \ | |
2836 | {"$v24", RTYPE_VEC | 24}, \ | |
2837 | {"$v25", RTYPE_VEC | 25}, \ | |
2838 | {"$v26", RTYPE_VEC | 26}, \ | |
2839 | {"$v27", RTYPE_VEC | 27}, \ | |
2840 | {"$v28", RTYPE_VEC | 28}, \ | |
2841 | {"$v29", RTYPE_VEC | 29}, \ | |
2842 | {"$v30", RTYPE_VEC | 30}, \ | |
2843 | {"$v31", RTYPE_VEC | 31} | |
2844 | ||
14daeee3 RS |
2845 | #define R5900_I_NAMES \ |
2846 | {"$I", RTYPE_R5900_I | 0} | |
2847 | ||
2848 | #define R5900_Q_NAMES \ | |
2849 | {"$Q", RTYPE_R5900_Q | 0} | |
2850 | ||
2851 | #define R5900_R_NAMES \ | |
2852 | {"$R", RTYPE_R5900_R | 0} | |
2853 | ||
2854 | #define R5900_ACC_NAMES \ | |
2855 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2856 | ||
707bfff6 TS |
2857 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2858 | {"$ac0", RTYPE_ACC | 0}, \ | |
2859 | {"$ac1", RTYPE_ACC | 1}, \ | |
2860 | {"$ac2", RTYPE_ACC | 2}, \ | |
2861 | {"$ac3", RTYPE_ACC | 3} | |
2862 | ||
2863 | static const struct regname reg_names[] = { | |
2864 | GENERIC_REGISTER_NUMBERS, | |
2865 | FPU_REGISTER_NAMES, | |
2866 | FPU_CONDITION_CODE_NAMES, | |
2867 | COPROC_CONDITION_CODE_NAMES, | |
2868 | ||
2869 | /* The $txx registers depends on the abi, | |
2870 | these will be added later into the symbol table from | |
3739860c | 2871 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2872 | parsing of arguments from the command line. */ |
2873 | SYMBOLIC_REGISTER_NAMES, | |
2874 | ||
2875 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2876 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2877 | R5900_I_NAMES, |
2878 | R5900_Q_NAMES, | |
2879 | R5900_R_NAMES, | |
2880 | R5900_ACC_NAMES, | |
707bfff6 TS |
2881 | MIPS_DSP_ACCUMULATOR_NAMES, |
2882 | {0, 0} | |
2883 | }; | |
2884 | ||
2885 | static const struct regname reg_names_o32[] = { | |
2886 | O32_SYMBOLIC_REGISTER_NAMES, | |
2887 | {0, 0} | |
2888 | }; | |
2889 | ||
2890 | static const struct regname reg_names_n32n64[] = { | |
2891 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2892 | {0, 0} | |
2893 | }; | |
2894 | ||
a92713e6 RS |
2895 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2896 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2897 | of these register symbols, return the associated vector register, | |
2898 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2899 | |
a92713e6 RS |
2900 | static unsigned int |
2901 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2902 | { |
a92713e6 RS |
2903 | if ((symval & -2) == (RTYPE_GP | 2)) |
2904 | return RTYPE_VEC | (symval & 1); | |
2905 | return symval; | |
2906 | } | |
2907 | ||
14daeee3 RS |
2908 | /* Return true if string [S, E) is a valid register name, storing its |
2909 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2910 | |
2911 | static bfd_boolean | |
14daeee3 | 2912 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2913 | { |
707bfff6 | 2914 | char save_c; |
14daeee3 | 2915 | symbolS *symbol; |
707bfff6 TS |
2916 | |
2917 | /* Terminate name. */ | |
2918 | save_c = *e; | |
2919 | *e = '\0'; | |
2920 | ||
a92713e6 RS |
2921 | /* Look up the name. */ |
2922 | symbol = symbol_find (s); | |
2923 | *e = save_c; | |
2924 | ||
2925 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2926 | return FALSE; | |
2927 | ||
14daeee3 RS |
2928 | *symval_ptr = S_GET_VALUE (symbol); |
2929 | return TRUE; | |
2930 | } | |
2931 | ||
2932 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2933 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2934 | is nonnull. | |
2935 | ||
2936 | When returning true, move *SPTR past the register, store the | |
2937 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2938 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2939 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2940 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2941 | ||
2942 | static bfd_boolean | |
2943 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2944 | unsigned int *channels_ptr) | |
2945 | { | |
2946 | char *s, *e, *m; | |
2947 | const char *q; | |
2948 | unsigned int channels, symval, bit; | |
2949 | ||
2950 | /* Find end of name. */ | |
2951 | s = e = *sptr; | |
2952 | if (is_name_beginner (*e)) | |
2953 | ++e; | |
2954 | while (is_part_of_name (*e)) | |
2955 | ++e; | |
2956 | ||
2957 | channels = 0; | |
2958 | if (!mips_parse_register_1 (s, e, &symval)) | |
2959 | { | |
2960 | if (!channels_ptr) | |
2961 | return FALSE; | |
2962 | ||
2963 | /* Eat characters from the end of the string that are valid | |
2964 | channel suffixes. The preceding register must be $ACC or | |
2965 | end with a digit, so there is no ambiguity. */ | |
2966 | bit = 1; | |
2967 | m = e; | |
2968 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2969 | if (m > s && m[-1] == *q) | |
2970 | { | |
2971 | --m; | |
2972 | channels |= bit; | |
2973 | } | |
2974 | ||
2975 | if (channels == 0 | |
2976 | || !mips_parse_register_1 (s, m, &symval) | |
2977 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2978 | return FALSE; | |
2979 | } | |
2980 | ||
a92713e6 | 2981 | *sptr = e; |
14daeee3 RS |
2982 | *symval_ptr = symval; |
2983 | if (channels_ptr) | |
2984 | *channels_ptr = channels; | |
a92713e6 RS |
2985 | return TRUE; |
2986 | } | |
2987 | ||
2988 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2989 | If so, then return 1, advance S to consume the specifier and store | |
2990 | the register's number in REGNOP, otherwise return 0. */ | |
2991 | ||
2992 | static int | |
2993 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2994 | { | |
2995 | unsigned int regno; | |
2996 | ||
14daeee3 | 2997 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2998 | { |
a92713e6 RS |
2999 | if (types & RTYPE_VEC) |
3000 | regno = mips_prefer_vec_regno (regno); | |
3001 | if (regno & types) | |
3002 | regno &= RNUM_MASK; | |
3003 | else | |
3004 | regno = ~0; | |
707bfff6 | 3005 | } |
a92713e6 | 3006 | else |
707bfff6 | 3007 | { |
a92713e6 | 3008 | if (types & RWARN) |
1661c76c | 3009 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 3010 | regno = ~0; |
707bfff6 | 3011 | } |
707bfff6 | 3012 | if (regnop) |
a92713e6 RS |
3013 | *regnop = regno; |
3014 | return regno <= RNUM_MASK; | |
707bfff6 TS |
3015 | } |
3016 | ||
14daeee3 RS |
3017 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
3018 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
3019 | ||
3020 | static char * | |
3021 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
3022 | { | |
3023 | unsigned int i; | |
3024 | ||
3025 | *channels = 0; | |
3026 | for (i = 0; i < 4; i++) | |
3027 | if (*s == "xyzw"[i]) | |
3028 | { | |
3029 | *channels |= 1 << (3 - i); | |
3030 | ++s; | |
3031 | } | |
3032 | return s; | |
3033 | } | |
3034 | ||
a92713e6 RS |
3035 | /* Token types for parsed operand lists. */ |
3036 | enum mips_operand_token_type { | |
3037 | /* A plain register, e.g. $f2. */ | |
3038 | OT_REG, | |
df58fc94 | 3039 | |
14daeee3 RS |
3040 | /* A 4-bit XYZW channel mask. */ |
3041 | OT_CHANNELS, | |
3042 | ||
56d438b1 CF |
3043 | /* A constant vector index, e.g. [1]. */ |
3044 | OT_INTEGER_INDEX, | |
3045 | ||
3046 | /* A register vector index, e.g. [$2]. */ | |
3047 | OT_REG_INDEX, | |
df58fc94 | 3048 | |
a92713e6 RS |
3049 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3050 | OT_REG_RANGE, | |
3051 | ||
3052 | /* A (possibly relocated) expression. */ | |
3053 | OT_INTEGER, | |
3054 | ||
3055 | /* A floating-point value. */ | |
3056 | OT_FLOAT, | |
3057 | ||
3058 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3059 | before OT_REGs. */ | |
3060 | OT_CHAR, | |
3061 | ||
14daeee3 RS |
3062 | /* A doubled character, either "--" or "++". */ |
3063 | OT_DOUBLE_CHAR, | |
3064 | ||
a92713e6 RS |
3065 | /* The end of the operand list. */ |
3066 | OT_END | |
3067 | }; | |
3068 | ||
3069 | /* A parsed operand token. */ | |
3070 | struct mips_operand_token | |
3071 | { | |
3072 | /* The type of token. */ | |
3073 | enum mips_operand_token_type type; | |
3074 | union | |
3075 | { | |
56d438b1 | 3076 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3077 | unsigned int regno; |
3078 | ||
14daeee3 RS |
3079 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3080 | unsigned int channels; | |
3081 | ||
56d438b1 CF |
3082 | /* The integer value of an OT_INTEGER_INDEX. */ |
3083 | addressT index; | |
a92713e6 RS |
3084 | |
3085 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3086 | struct { | |
3087 | unsigned int regno1; | |
3088 | unsigned int regno2; | |
3089 | } reg_range; | |
3090 | ||
3091 | /* The value of an OT_INTEGER. The value is represented as an | |
3092 | expression and the relocation operators that were applied to | |
3093 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3094 | relocation operators were used. */ | |
3095 | struct { | |
3096 | expressionS value; | |
3097 | bfd_reloc_code_real_type relocs[3]; | |
3098 | } integer; | |
3099 | ||
3100 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3101 | in the constant. */ | |
3102 | struct { | |
3103 | unsigned char data[8]; | |
3104 | int length; | |
3105 | } flt; | |
3106 | ||
14daeee3 | 3107 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3108 | char ch; |
3109 | } u; | |
3110 | }; | |
3111 | ||
3112 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3113 | static struct obstack mips_operand_tokens; | |
3114 | ||
3115 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3116 | ||
3117 | static void | |
3118 | mips_add_token (struct mips_operand_token *token, | |
3119 | enum mips_operand_token_type type) | |
3120 | { | |
3121 | token->type = type; | |
3122 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3123 | } | |
3124 | ||
3125 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3126 | and OT_REG tokens for them if so, and return a pointer to the first | |
3127 | unconsumed character. Return null otherwise. */ | |
3128 | ||
3129 | static char * | |
3130 | mips_parse_base_start (char *s) | |
3131 | { | |
3132 | struct mips_operand_token token; | |
14daeee3 RS |
3133 | unsigned int regno, channels; |
3134 | bfd_boolean decrement_p; | |
df58fc94 | 3135 | |
a92713e6 RS |
3136 | if (*s != '(') |
3137 | return 0; | |
3138 | ||
3139 | ++s; | |
3140 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3141 | |
3142 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3143 | is a double negative. */ | |
3144 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3145 | if (decrement_p) | |
3146 | { | |
3147 | s += 2; | |
3148 | SKIP_SPACE_TABS (s); | |
3149 | } | |
3150 | ||
3151 | /* Allow a channel specifier because that leads to better error messages | |
3152 | than treating something like "$vf0x++" as an expression. */ | |
3153 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3154 | return 0; |
3155 | ||
3156 | token.u.ch = '('; | |
3157 | mips_add_token (&token, OT_CHAR); | |
3158 | ||
14daeee3 RS |
3159 | if (decrement_p) |
3160 | { | |
3161 | token.u.ch = '-'; | |
3162 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3163 | } | |
3164 | ||
a92713e6 RS |
3165 | token.u.regno = regno; |
3166 | mips_add_token (&token, OT_REG); | |
3167 | ||
14daeee3 RS |
3168 | if (channels) |
3169 | { | |
3170 | token.u.channels = channels; | |
3171 | mips_add_token (&token, OT_CHANNELS); | |
3172 | } | |
3173 | ||
3174 | /* For consistency, only match "++" as part of base expressions too. */ | |
3175 | SKIP_SPACE_TABS (s); | |
3176 | if (s[0] == '+' && s[1] == '+') | |
3177 | { | |
3178 | s += 2; | |
3179 | token.u.ch = '+'; | |
3180 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3181 | } | |
3182 | ||
a92713e6 RS |
3183 | return s; |
3184 | } | |
3185 | ||
3186 | /* Parse one or more tokens from S. Return a pointer to the first | |
3187 | unconsumed character on success. Return null if an error was found | |
3188 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3189 | mips_parse_arguments. */ | |
3190 | ||
3191 | static char * | |
3192 | mips_parse_argument_token (char *s, char float_format) | |
3193 | { | |
6d4af3c2 AM |
3194 | char *end, *save_in; |
3195 | const char *err; | |
14daeee3 | 3196 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3197 | struct mips_operand_token token; |
3198 | ||
3199 | /* First look for "($reg", since we want to treat that as an | |
3200 | OT_CHAR and OT_REG rather than an expression. */ | |
3201 | end = mips_parse_base_start (s); | |
3202 | if (end) | |
3203 | return end; | |
3204 | ||
3205 | /* Handle other characters that end up as OT_CHARs. */ | |
3206 | if (*s == ')' || *s == ',') | |
3207 | { | |
3208 | token.u.ch = *s; | |
3209 | mips_add_token (&token, OT_CHAR); | |
3210 | ++s; | |
3211 | return s; | |
3212 | } | |
3213 | ||
3214 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3215 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3216 | { |
14daeee3 RS |
3217 | if (channels) |
3218 | { | |
3219 | /* A register and a VU0 channel suffix. */ | |
3220 | token.u.regno = regno1; | |
3221 | mips_add_token (&token, OT_REG); | |
3222 | ||
3223 | token.u.channels = channels; | |
3224 | mips_add_token (&token, OT_CHANNELS); | |
3225 | return s; | |
3226 | } | |
3227 | ||
a92713e6 RS |
3228 | SKIP_SPACE_TABS (s); |
3229 | if (*s == '-') | |
df58fc94 | 3230 | { |
a92713e6 RS |
3231 | /* A register range. */ |
3232 | ++s; | |
3233 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3234 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3235 | { |
1661c76c | 3236 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3237 | return 0; |
3238 | } | |
df58fc94 | 3239 | |
a92713e6 RS |
3240 | token.u.reg_range.regno1 = regno1; |
3241 | token.u.reg_range.regno2 = regno2; | |
3242 | mips_add_token (&token, OT_REG_RANGE); | |
3243 | return s; | |
3244 | } | |
a92713e6 | 3245 | |
56d438b1 CF |
3246 | /* Add the register itself. */ |
3247 | token.u.regno = regno1; | |
3248 | mips_add_token (&token, OT_REG); | |
3249 | ||
3250 | /* Check for a vector index. */ | |
3251 | if (*s == '[') | |
3252 | { | |
a92713e6 RS |
3253 | ++s; |
3254 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3255 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3256 | mips_add_token (&token, OT_REG_INDEX); | |
3257 | else | |
a92713e6 | 3258 | { |
56d438b1 CF |
3259 | expressionS element; |
3260 | ||
3261 | my_getExpression (&element, s); | |
3262 | if (element.X_op != O_constant) | |
3263 | { | |
3264 | set_insn_error (0, _("vector element must be constant")); | |
3265 | return 0; | |
3266 | } | |
3267 | s = expr_end; | |
3268 | token.u.index = element.X_add_number; | |
3269 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3270 | } |
a92713e6 RS |
3271 | SKIP_SPACE_TABS (s); |
3272 | if (*s != ']') | |
3273 | { | |
1661c76c | 3274 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3275 | return 0; |
3276 | } | |
3277 | ++s; | |
df58fc94 | 3278 | } |
a92713e6 | 3279 | return s; |
df58fc94 RS |
3280 | } |
3281 | ||
a92713e6 RS |
3282 | if (float_format) |
3283 | { | |
3284 | /* First try to treat expressions as floats. */ | |
3285 | save_in = input_line_pointer; | |
3286 | input_line_pointer = s; | |
3287 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3288 | &token.u.flt.length); | |
3289 | end = input_line_pointer; | |
3290 | input_line_pointer = save_in; | |
3291 | if (err && *err) | |
3292 | { | |
e3de51ce | 3293 | set_insn_error (0, err); |
a92713e6 RS |
3294 | return 0; |
3295 | } | |
3296 | if (s != end) | |
3297 | { | |
3298 | mips_add_token (&token, OT_FLOAT); | |
3299 | return end; | |
3300 | } | |
3301 | } | |
3302 | ||
3303 | /* Treat everything else as an integer expression. */ | |
3304 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3305 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3306 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3307 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3308 | s = expr_end; | |
3309 | mips_add_token (&token, OT_INTEGER); | |
3310 | return s; | |
3311 | } | |
3312 | ||
3313 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3314 | if expressions should be treated as 32-bit floating-point constants, | |
3315 | 'd' if they should be treated as 64-bit floating-point constants, | |
3316 | or 0 if they should be treated as integer expressions (the usual case). | |
3317 | ||
3318 | Return a list of tokens on success, otherwise return 0. The caller | |
3319 | must obstack_free the list after use. */ | |
3320 | ||
3321 | static struct mips_operand_token * | |
3322 | mips_parse_arguments (char *s, char float_format) | |
3323 | { | |
3324 | struct mips_operand_token token; | |
3325 | ||
3326 | SKIP_SPACE_TABS (s); | |
3327 | while (*s) | |
3328 | { | |
3329 | s = mips_parse_argument_token (s, float_format); | |
3330 | if (!s) | |
3331 | { | |
3332 | obstack_free (&mips_operand_tokens, | |
3333 | obstack_finish (&mips_operand_tokens)); | |
3334 | return 0; | |
3335 | } | |
3336 | SKIP_SPACE_TABS (s); | |
3337 | } | |
3338 | mips_add_token (&token, OT_END); | |
3339 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3340 | } |
3341 | ||
d301a56b RS |
3342 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3343 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3344 | |
3345 | static bfd_boolean | |
f79e2745 | 3346 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3347 | { |
3348 | int isa = mips_opts.isa; | |
846ef2d0 | 3349 | int ase = mips_opts.ase; |
037b32b9 | 3350 | int fp_s, fp_d; |
c6278170 | 3351 | unsigned int i; |
037b32b9 | 3352 | |
be0fcbee | 3353 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3354 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3355 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3356 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3357 | |
d301a56b | 3358 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3359 | return FALSE; |
3360 | ||
3361 | /* Check whether the instruction or macro requires single-precision or | |
3362 | double-precision floating-point support. Note that this information is | |
3363 | stored differently in the opcode table for insns and macros. */ | |
3364 | if (mo->pinfo == INSN_MACRO) | |
3365 | { | |
3366 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3367 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3368 | } | |
3369 | else | |
3370 | { | |
3371 | fp_s = mo->pinfo & FP_S; | |
3372 | fp_d = mo->pinfo & FP_D; | |
3373 | } | |
3374 | ||
3375 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3376 | return FALSE; | |
3377 | ||
3378 | if (fp_s && mips_opts.soft_float) | |
3379 | return FALSE; | |
3380 | ||
3381 | return TRUE; | |
3382 | } | |
3383 | ||
3384 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3385 | selected ISA and architecture. */ | |
3386 | ||
3387 | static bfd_boolean | |
3388 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3389 | { | |
25499ac7 MR |
3390 | int isa = mips_opts.isa; |
3391 | int ase = mips_opts.ase; | |
3392 | unsigned int i; | |
3393 | ||
3394 | if (ISA_HAS_64BIT_REGS (isa)) | |
3395 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3396 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3397 | ase |= mips_ases[i].flags64; | |
3398 | ||
3399 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3400 | } |
3401 | ||
df58fc94 | 3402 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3403 | explicitly requested. Always TRUE in the standard MIPS mode. |
3404 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3405 | |
3406 | static bfd_boolean | |
3407 | is_size_valid (const struct mips_opcode *mo) | |
3408 | { | |
3409 | if (!mips_opts.micromips) | |
3410 | return TRUE; | |
3411 | ||
833794fc MR |
3412 | if (mips_opts.insn32) |
3413 | { | |
3414 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3415 | return FALSE; | |
3416 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3417 | return FALSE; | |
3418 | } | |
df58fc94 RS |
3419 | if (!forced_insn_length) |
3420 | return TRUE; | |
3421 | if (mo->pinfo == INSN_MACRO) | |
3422 | return FALSE; | |
3423 | return forced_insn_length == micromips_insn_length (mo); | |
3424 | } | |
3425 | ||
7fd53920 MR |
3426 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3427 | explicitly requested. */ | |
3428 | ||
3429 | static bfd_boolean | |
3430 | is_size_valid_16 (const struct mips_opcode *mo) | |
3431 | { | |
3432 | if (!forced_insn_length) | |
3433 | return TRUE; | |
3434 | if (mo->pinfo == INSN_MACRO) | |
3435 | return FALSE; | |
3436 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3437 | return FALSE; | |
0674ee5d MR |
3438 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3439 | return FALSE; | |
7fd53920 MR |
3440 | return TRUE; |
3441 | } | |
3442 | ||
df58fc94 | 3443 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3444 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3445 | ||
3446 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3447 | a macro expansion fails because it relies on a preceding 32-bit real | |
3448 | instruction to have matched and does not handle the operands correctly. | |
3449 | The only macros that may expand to 16-bit instructions are JAL that | |
3450 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3451 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3452 | a NOP. In all these cases the macros precede any corresponding real | |
3453 | instruction definitions in the opcode table, so they will match in the | |
3454 | second pass where the size of the delay slot is ignored and therefore | |
3455 | produce correct code. */ | |
df58fc94 RS |
3456 | |
3457 | static bfd_boolean | |
3458 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3459 | { | |
3460 | if (!mips_opts.micromips) | |
3461 | return TRUE; | |
3462 | ||
3463 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3464 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3465 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3466 | && micromips_insn_length (mo) != 4) | |
3467 | return FALSE; | |
3468 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3469 | && micromips_insn_length (mo) != 2) | |
3470 | return FALSE; | |
3471 | ||
3472 | return TRUE; | |
3473 | } | |
3474 | ||
fc76e730 RS |
3475 | /* For consistency checking, verify that all bits of OPCODE are specified |
3476 | either by the match/mask part of the instruction definition, or by the | |
3477 | operand list. Also build up a list of operands in OPERANDS. | |
3478 | ||
3479 | INSN_BITS says which bits of the instruction are significant. | |
3480 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3481 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3482 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3483 | |
3484 | static int | |
3485 | validate_mips_insn (const struct mips_opcode *opcode, | |
3486 | unsigned long insn_bits, | |
fc76e730 RS |
3487 | const struct mips_operand *(*decode_operand) (const char *), |
3488 | struct mips_operand_array *operands) | |
ab902481 RS |
3489 | { |
3490 | const char *s; | |
fc76e730 | 3491 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3492 | const struct mips_operand *operand; |
3493 | ||
fc76e730 RS |
3494 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3495 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3496 | { |
3497 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3498 | opcode->name, opcode->args); | |
3499 | return 0; | |
3500 | } | |
3501 | used_bits = 0; | |
fc76e730 | 3502 | opno = 0; |
14daeee3 RS |
3503 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3504 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3505 | for (s = opcode->args; *s; ++s) |
3506 | switch (*s) | |
3507 | { | |
3508 | case ',': | |
3509 | case '(': | |
3510 | case ')': | |
3511 | break; | |
3512 | ||
14daeee3 RS |
3513 | case '#': |
3514 | s++; | |
3515 | break; | |
3516 | ||
ab902481 | 3517 | default: |
fc76e730 | 3518 | if (!decode_operand) |
7fd53920 | 3519 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3520 | else |
3521 | operand = decode_operand (s); | |
3522 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3523 | { |
3524 | as_bad (_("internal: unknown operand type: %s %s"), | |
3525 | opcode->name, opcode->args); | |
3526 | return 0; | |
3527 | } | |
fc76e730 RS |
3528 | gas_assert (opno < MAX_OPERANDS); |
3529 | operands->operand[opno] = operand; | |
25499ac7 MR |
3530 | if (!decode_operand && operand |
3531 | && operand->type == OP_INT && operand->lsb == 0 | |
3532 | && mips_opcode_32bit_p (opcode)) | |
3533 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3534 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3535 | { |
14daeee3 | 3536 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3537 | if (operand->type == OP_MDMX_IMM_REG) |
3538 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3539 | has separate entries for each format. */ | |
3540 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3541 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3542 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3543 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3544 | operand field that cannot be fully described with LSB/SIZE. */ | |
3545 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3546 | used_bits &= ~0x6000; | |
fc76e730 | 3547 | } |
ab902481 | 3548 | /* Skip prefix characters. */ |
7361da2c | 3549 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3550 | ++s; |
fc76e730 | 3551 | opno += 1; |
ab902481 RS |
3552 | break; |
3553 | } | |
fc76e730 | 3554 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3555 | if (doubled) |
3556 | { | |
3557 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3558 | " %s %s"), doubled, opcode->name, opcode->args); | |
3559 | return 0; | |
3560 | } | |
fc76e730 | 3561 | used_bits |= mask; |
ab902481 | 3562 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3563 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3564 | { |
3565 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3566 | undefined, opcode->name, opcode->args); | |
3567 | return 0; | |
3568 | } | |
3569 | used_bits &= ~insn_bits; | |
3570 | if (used_bits) | |
3571 | { | |
3572 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3573 | used_bits, opcode->name, opcode->args); | |
3574 | return 0; | |
3575 | } | |
3576 | return 1; | |
3577 | } | |
3578 | ||
fc76e730 RS |
3579 | /* The MIPS16 version of validate_mips_insn. */ |
3580 | ||
3581 | static int | |
3582 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3583 | struct mips_operand_array *operands) | |
3584 | { | |
7fd53920 | 3585 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3586 | |
7fd53920 | 3587 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3588 | } |
3589 | ||
ab902481 RS |
3590 | /* The microMIPS version of validate_mips_insn. */ |
3591 | ||
3592 | static int | |
fc76e730 RS |
3593 | validate_micromips_insn (const struct mips_opcode *opc, |
3594 | struct mips_operand_array *operands) | |
ab902481 RS |
3595 | { |
3596 | unsigned long insn_bits; | |
3597 | unsigned long major; | |
3598 | unsigned int length; | |
3599 | ||
fc76e730 RS |
3600 | if (opc->pinfo == INSN_MACRO) |
3601 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3602 | operands); | |
3603 | ||
ab902481 RS |
3604 | length = micromips_insn_length (opc); |
3605 | if (length != 2 && length != 4) | |
3606 | { | |
1661c76c | 3607 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3608 | "%s %s"), length, opc->name, opc->args); |
3609 | return 0; | |
3610 | } | |
3611 | major = opc->match >> (10 + 8 * (length - 2)); | |
3612 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3613 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3614 | { | |
1661c76c | 3615 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3616 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3617 | return 0; | |
3618 | } | |
3619 | ||
3620 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3621 | insn_bits = 1 << 4 * length; | |
3622 | insn_bits <<= 4 * length; | |
3623 | insn_bits -= 1; | |
fc76e730 RS |
3624 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3625 | operands); | |
ab902481 RS |
3626 | } |
3627 | ||
707bfff6 TS |
3628 | /* This function is called once, at assembler startup time. It should set up |
3629 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3630 | |
252b5132 | 3631 | void |
17a2f251 | 3632 | md_begin (void) |
252b5132 | 3633 | { |
3994f87e | 3634 | const char *retval = NULL; |
156c2f8b | 3635 | int i = 0; |
252b5132 | 3636 | int broken = 0; |
1f25f5d3 | 3637 | |
0a44bf69 RS |
3638 | if (mips_pic != NO_PIC) |
3639 | { | |
3640 | if (g_switch_seen && g_switch_value != 0) | |
3641 | as_bad (_("-G may not be used in position-independent code")); | |
3642 | g_switch_value = 0; | |
3643 | } | |
00acd688 CM |
3644 | else if (mips_abicalls) |
3645 | { | |
3646 | if (g_switch_seen && g_switch_value != 0) | |
3647 | as_bad (_("-G may not be used with abicalls")); | |
3648 | g_switch_value = 0; | |
3649 | } | |
0a44bf69 | 3650 | |
0b35dfee | 3651 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3652 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3653 | |
252b5132 RH |
3654 | op_hash = hash_new (); |
3655 | ||
fc76e730 | 3656 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3657 | for (i = 0; i < NUMOPCODES;) |
3658 | { | |
3659 | const char *name = mips_opcodes[i].name; | |
3660 | ||
17a2f251 | 3661 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3662 | if (retval != NULL) |
3663 | { | |
3664 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3665 | mips_opcodes[i].name, retval); | |
3666 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3667 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3668 | } |
3669 | do | |
3670 | { | |
fc76e730 RS |
3671 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3672 | decode_mips_operand, &mips_operands[i])) | |
3673 | broken = 1; | |
3674 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3675 | { |
fc76e730 RS |
3676 | create_insn (&nop_insn, mips_opcodes + i); |
3677 | if (mips_fix_loongson2f_nop) | |
3678 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3679 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3680 | } |
3681 | ++i; | |
3682 | } | |
3683 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3684 | } | |
3685 | ||
3686 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3687 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3688 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3689 | |
3690 | i = 0; | |
3691 | while (i < bfd_mips16_num_opcodes) | |
3692 | { | |
3693 | const char *name = mips16_opcodes[i].name; | |
3694 | ||
17a2f251 | 3695 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3696 | if (retval != NULL) |
3697 | as_fatal (_("internal: can't hash `%s': %s"), | |
3698 | mips16_opcodes[i].name, retval); | |
3699 | do | |
3700 | { | |
fc76e730 RS |
3701 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3702 | broken = 1; | |
1e915849 RS |
3703 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3704 | { | |
3705 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3706 | mips16_nop_insn.fixed_p = 1; | |
3707 | } | |
252b5132 RH |
3708 | ++i; |
3709 | } | |
3710 | while (i < bfd_mips16_num_opcodes | |
3711 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3712 | } | |
3713 | ||
df58fc94 | 3714 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3715 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3716 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3717 | |
3718 | i = 0; | |
3719 | while (i < bfd_micromips_num_opcodes) | |
3720 | { | |
3721 | const char *name = micromips_opcodes[i].name; | |
3722 | ||
3723 | retval = hash_insert (micromips_op_hash, name, | |
3724 | (void *) µmips_opcodes[i]); | |
3725 | if (retval != NULL) | |
3726 | as_fatal (_("internal: can't hash `%s': %s"), | |
3727 | micromips_opcodes[i].name, retval); | |
3728 | do | |
fc76e730 RS |
3729 | { |
3730 | struct mips_cl_insn *micromips_nop_insn; | |
3731 | ||
3732 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3733 | µmips_operands[i])) | |
3734 | broken = 1; | |
3735 | ||
3736 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3737 | { | |
3738 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3739 | micromips_nop_insn = µmips_nop16_insn; | |
3740 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3741 | micromips_nop_insn = µmips_nop32_insn; | |
3742 | else | |
3743 | continue; | |
3744 | ||
3745 | if (micromips_nop_insn->insn_mo == NULL | |
3746 | && strcmp (name, "nop") == 0) | |
3747 | { | |
3748 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3749 | micromips_nop_insn->fixed_p = 1; | |
3750 | } | |
3751 | } | |
3752 | } | |
df58fc94 RS |
3753 | while (++i < bfd_micromips_num_opcodes |
3754 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3755 | } | |
3756 | ||
252b5132 | 3757 | if (broken) |
1661c76c | 3758 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3759 | |
3760 | /* We add all the general register names to the symbol table. This | |
3761 | helps us detect invalid uses of them. */ | |
3739860c | 3762 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3763 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3764 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3765 | &zero_address_frag)); |
3766 | if (HAVE_NEWABI) | |
3739860c | 3767 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3768 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3769 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3770 | &zero_address_frag)); |
707bfff6 | 3771 | else |
3739860c | 3772 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3773 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3774 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3775 | &zero_address_frag)); |
6047c971 | 3776 | |
14daeee3 RS |
3777 | for (i = 0; i < 32; i++) |
3778 | { | |
92fce9bd | 3779 | char regname[6]; |
14daeee3 RS |
3780 | |
3781 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3782 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3783 | symbol_table_insert (symbol_new (regname, reg_section, |
3784 | RTYPE_VF | i, &zero_address_frag)); | |
3785 | ||
3786 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3787 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3788 | symbol_table_insert (symbol_new (regname, reg_section, |
3789 | RTYPE_VI | i, &zero_address_frag)); | |
3790 | ||
56d438b1 | 3791 | /* MSA register. */ |
92fce9bd | 3792 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3793 | symbol_table_insert (symbol_new (regname, reg_section, |
3794 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3795 | } |
3796 | ||
a92713e6 RS |
3797 | obstack_init (&mips_operand_tokens); |
3798 | ||
7d10b47d | 3799 | mips_no_prev_insn (); |
252b5132 RH |
3800 | |
3801 | mips_gprmask = 0; | |
3802 | mips_cprmask[0] = 0; | |
3803 | mips_cprmask[1] = 0; | |
3804 | mips_cprmask[2] = 0; | |
3805 | mips_cprmask[3] = 0; | |
3806 | ||
3807 | /* set the default alignment for the text section (2**2) */ | |
3808 | record_alignment (text_section, 2); | |
3809 | ||
4d0d148d | 3810 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3811 | |
f3ded42a RS |
3812 | /* On a native system other than VxWorks, sections must be aligned |
3813 | to 16 byte boundaries. When configured for an embedded ELF | |
3814 | target, we don't bother. */ | |
3815 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3816 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3817 | { |
f3ded42a RS |
3818 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3819 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3820 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3821 | } | |
252b5132 | 3822 | |
f3ded42a RS |
3823 | /* Create a .reginfo section for register masks and a .mdebug |
3824 | section for debugging information. */ | |
3825 | { | |
3826 | segT seg; | |
3827 | subsegT subseg; | |
3828 | flagword flags; | |
3829 | segT sec; | |
3830 | ||
3831 | seg = now_seg; | |
3832 | subseg = now_subseg; | |
3833 | ||
3834 | /* The ABI says this section should be loaded so that the | |
3835 | running program can access it. However, we don't load it | |
3836 | if we are configured for an embedded target */ | |
3837 | flags = SEC_READONLY | SEC_DATA; | |
3838 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3839 | flags |= SEC_ALLOC | SEC_LOAD; | |
3840 | ||
3841 | if (mips_abi != N64_ABI) | |
252b5132 | 3842 | { |
f3ded42a | 3843 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3844 | |
f3ded42a RS |
3845 | bfd_set_section_flags (stdoutput, sec, flags); |
3846 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3847 | |
f3ded42a RS |
3848 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3849 | } | |
3850 | else | |
3851 | { | |
3852 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3853 | .reginfo section. */ | |
3854 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3855 | bfd_set_section_flags (stdoutput, sec, flags); | |
3856 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3857 | |
f3ded42a RS |
3858 | /* Set up the option header. */ |
3859 | { | |
3860 | Elf_Internal_Options opthdr; | |
3861 | char *f; | |
3862 | ||
3863 | opthdr.kind = ODK_REGINFO; | |
3864 | opthdr.size = (sizeof (Elf_External_Options) | |
3865 | + sizeof (Elf64_External_RegInfo)); | |
3866 | opthdr.section = 0; | |
3867 | opthdr.info = 0; | |
3868 | f = frag_more (sizeof (Elf_External_Options)); | |
3869 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3870 | (Elf_External_Options *) f); | |
3871 | ||
3872 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3873 | } | |
3874 | } | |
252b5132 | 3875 | |
351cdf24 MF |
3876 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3877 | bfd_set_section_flags (stdoutput, sec, | |
3878 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3879 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3880 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3881 | ||
f3ded42a RS |
3882 | if (ECOFF_DEBUGGING) |
3883 | { | |
3884 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3885 | (void) bfd_set_section_flags (stdoutput, sec, | |
3886 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3887 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3888 | } |
f3ded42a RS |
3889 | else if (mips_flag_pdr) |
3890 | { | |
3891 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3892 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3893 | SEC_READONLY | SEC_RELOC | |
3894 | | SEC_DEBUGGING); | |
3895 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3896 | } | |
3897 | ||
3898 | subseg_set (seg, subseg); | |
3899 | } | |
252b5132 | 3900 | |
71400594 RS |
3901 | if (mips_fix_vr4120) |
3902 | init_vr4120_conflicts (); | |
252b5132 RH |
3903 | } |
3904 | ||
351cdf24 MF |
3905 | static inline void |
3906 | fpabi_incompatible_with (int fpabi, const char *what) | |
3907 | { | |
3908 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3909 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3910 | } | |
3911 | ||
3912 | static inline void | |
3913 | fpabi_requires (int fpabi, const char *what) | |
3914 | { | |
3915 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3916 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3917 | } | |
3918 | ||
3919 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3920 | static void | |
3921 | check_fpabi (int fpabi) | |
3922 | { | |
351cdf24 MF |
3923 | switch (fpabi) |
3924 | { | |
3925 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3926 | if (file_mips_opts.soft_float) |
3927 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3928 | else if (file_mips_opts.single_float) | |
3929 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3930 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3931 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3932 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3933 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3934 | break; |
3935 | ||
3936 | case Val_GNU_MIPS_ABI_FP_XX: | |
3937 | if (mips_abi != O32_ABI) | |
3938 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3939 | else if (file_mips_opts.soft_float) |
3940 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3941 | else if (file_mips_opts.single_float) | |
3942 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3943 | else if (file_mips_opts.fp != 0) |
3944 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3945 | break; |
3946 | ||
3947 | case Val_GNU_MIPS_ABI_FP_64A: | |
3948 | case Val_GNU_MIPS_ABI_FP_64: | |
3949 | if (mips_abi != O32_ABI) | |
3950 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3951 | else if (file_mips_opts.soft_float) |
3952 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3953 | else if (file_mips_opts.single_float) | |
3954 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3955 | else if (file_mips_opts.fp != 64) |
3956 | fpabi_requires (fpabi, "fp=64"); | |
3957 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3958 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3959 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3960 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3961 | break; |
3962 | ||
3963 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3964 | if (file_mips_opts.soft_float) | |
3965 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3966 | else if (!file_mips_opts.single_float) | |
3967 | fpabi_requires (fpabi, "singlefloat"); | |
3968 | break; | |
3969 | ||
3970 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3971 | if (!file_mips_opts.soft_float) | |
3972 | fpabi_requires (fpabi, "softfloat"); | |
3973 | break; | |
3974 | ||
3975 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3976 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3977 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3978 | break; | |
3979 | ||
3350cc01 CM |
3980 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3981 | /* Silently ignore compatibility value. */ | |
3982 | break; | |
3983 | ||
351cdf24 MF |
3984 | default: |
3985 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3986 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3987 | break; | |
3988 | } | |
351cdf24 MF |
3989 | } |
3990 | ||
919731af | 3991 | /* Perform consistency checks on the current options. */ |
3992 | ||
3993 | static void | |
3994 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3995 | { | |
3996 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3997 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3998 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3999 | else if (abi_checks | |
4000 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4001 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
4002 | else if (abi_checks | |
4003 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
4004 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
4005 | ||
4006 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
4007 | switch (opts->fp) | |
4008 | { | |
351cdf24 MF |
4009 | case 0: |
4010 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
4011 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
4012 | else if (opts->single_float == 1) | |
4013 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
4014 | break; | |
919731af | 4015 | case 64: |
4016 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
4017 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
4018 | else if (abi_checks | |
4019 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
4020 | && !ISA_HAS_MXHC1 (opts->isa)) | |
4021 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
4022 | break; | |
4023 | case 32: | |
4024 | if (abi_checks | |
4025 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4026 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 4027 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 4028 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4029 | break; |
4030 | default: | |
4031 | as_bad (_("Unknown size of floating point registers")); | |
4032 | break; | |
4033 | } | |
4034 | ||
351cdf24 MF |
4035 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4036 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4037 | ||
919731af | 4038 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4039 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4040 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4041 | && (opts->micromips == 1 |
4042 | || opts->mips16 == 1)) | |
1357373c | 4043 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4044 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4045 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4046 | |
4047 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4048 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4049 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4050 | } |
4051 | ||
4052 | /* Perform consistency checks on the module level options exactly once. | |
4053 | This is a deferred check that happens: | |
4054 | at the first .set directive | |
4055 | or, at the first pseudo op that generates code (inc .dc.a) | |
4056 | or, at the first instruction | |
4057 | or, at the end. */ | |
4058 | ||
4059 | static void | |
4060 | file_mips_check_options (void) | |
4061 | { | |
4062 | const struct mips_cpu_info *arch_info = 0; | |
4063 | ||
4064 | if (file_mips_opts_checked) | |
4065 | return; | |
4066 | ||
4067 | /* The following code determines the register size. | |
4068 | Similar code was added to GCC 3.3 (see override_options() in | |
4069 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4070 | as much as possible. */ | |
4071 | ||
4072 | if (file_mips_opts.gp < 0) | |
4073 | { | |
4074 | /* Infer the integer register size from the ABI and processor. | |
4075 | Restrict ourselves to 32-bit registers if that's all the | |
4076 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4077 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4078 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4079 | ? 32 : 64; | |
4080 | } | |
4081 | ||
4082 | if (file_mips_opts.fp < 0) | |
4083 | { | |
4084 | /* No user specified float register size. | |
4085 | ??? GAS treats single-float processors as though they had 64-bit | |
4086 | float registers (although it complains when double-precision | |
4087 | instructions are used). As things stand, saying they have 32-bit | |
4088 | registers would lead to spurious "register must be even" messages. | |
4089 | So here we assume float registers are never smaller than the | |
4090 | integer ones. */ | |
4091 | if (file_mips_opts.gp == 64) | |
4092 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4093 | file_mips_opts.fp = 64; | |
4094 | else if ((file_mips_opts.ase & FP64_ASES) | |
4095 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4096 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4097 | file_mips_opts.fp = 64; | |
7361da2c AB |
4098 | else if (ISA_IS_R6 (mips_opts.isa)) |
4099 | /* R6 implies 64-bit float registers. */ | |
4100 | file_mips_opts.fp = 64; | |
919731af | 4101 | else |
4102 | /* 32-bit float registers. */ | |
4103 | file_mips_opts.fp = 32; | |
4104 | } | |
4105 | ||
4106 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
4107 | ||
351cdf24 MF |
4108 | /* Disable operations on odd-numbered floating-point registers by default |
4109 | when using the FPXX ABI. */ | |
4110 | if (file_mips_opts.oddspreg < 0) | |
4111 | { | |
4112 | if (file_mips_opts.fp == 0) | |
4113 | file_mips_opts.oddspreg = 0; | |
4114 | else | |
4115 | file_mips_opts.oddspreg = 1; | |
4116 | } | |
4117 | ||
919731af | 4118 | /* End of GCC-shared inference code. */ |
4119 | ||
4120 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4121 | 32-bit wide registers. Note that EABI does not use it. */ | |
4122 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4123 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4124 | || mips_abi == O32_ABI)) | |
4125 | mips_32bitmode = 1; | |
4126 | ||
4127 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4128 | as_bad (_("trap exception not supported at ISA 1")); | |
4129 | ||
4130 | /* If the selected architecture includes support for ASEs, enable | |
4131 | generation of code for them. */ | |
4132 | if (file_mips_opts.mips16 == -1) | |
4133 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4134 | if (file_mips_opts.micromips == -1) | |
4135 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4136 | ? 1 : 0; | |
4137 | ||
7361da2c AB |
4138 | if (mips_nan2008 == -1) |
4139 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4140 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4141 | as_fatal (_("`%s' does not support legacy NaN"), | |
4142 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4143 | ||
919731af | 4144 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4145 | being selected implicitly. */ | |
4146 | if (file_mips_opts.fp != 64) | |
4147 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4148 | ||
4149 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4150 | use the default setting for the CPU. */ | |
4151 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4152 | ||
4153 | /* Set up the current options. These may change throughout assembly. */ | |
4154 | mips_opts = file_mips_opts; | |
4155 | ||
4156 | mips_check_isa_supports_ases (); | |
4157 | mips_check_options (&file_mips_opts, TRUE); | |
4158 | file_mips_opts_checked = TRUE; | |
4159 | ||
4160 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4161 | as_warn (_("could not set architecture and machine")); | |
4162 | } | |
4163 | ||
252b5132 | 4164 | void |
17a2f251 | 4165 | md_assemble (char *str) |
252b5132 RH |
4166 | { |
4167 | struct mips_cl_insn insn; | |
f6688943 TS |
4168 | bfd_reloc_code_real_type unused_reloc[3] |
4169 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4170 | |
919731af | 4171 | file_mips_check_options (); |
4172 | ||
252b5132 | 4173 | imm_expr.X_op = O_absent; |
252b5132 | 4174 | offset_expr.X_op = O_absent; |
f6688943 TS |
4175 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4176 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4177 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4178 | |
e1b47bd5 RS |
4179 | mips_mark_labels (); |
4180 | mips_assembling_insn = TRUE; | |
e3de51ce | 4181 | clear_insn_error (); |
e1b47bd5 | 4182 | |
252b5132 RH |
4183 | if (mips_opts.mips16) |
4184 | mips16_ip (str, &insn); | |
4185 | else | |
4186 | { | |
4187 | mips_ip (str, &insn); | |
beae10d5 KH |
4188 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4189 | str, insn.insn_opcode)); | |
252b5132 RH |
4190 | } |
4191 | ||
e3de51ce RS |
4192 | if (insn_error.msg) |
4193 | report_insn_error (str); | |
e1b47bd5 | 4194 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4195 | { |
584892a6 | 4196 | macro_start (); |
252b5132 RH |
4197 | if (mips_opts.mips16) |
4198 | mips16_macro (&insn); | |
4199 | else | |
833794fc | 4200 | macro (&insn, str); |
584892a6 | 4201 | macro_end (); |
252b5132 RH |
4202 | } |
4203 | else | |
4204 | { | |
77bd4346 | 4205 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4206 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4207 | else |
df58fc94 | 4208 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4209 | } |
e1b47bd5 RS |
4210 | |
4211 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4212 | } |
4213 | ||
738e5348 RS |
4214 | /* Convenience functions for abstracting away the differences between |
4215 | MIPS16 and non-MIPS16 relocations. */ | |
4216 | ||
4217 | static inline bfd_boolean | |
4218 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4219 | { | |
4220 | switch (reloc) | |
4221 | { | |
4222 | case BFD_RELOC_MIPS16_JMP: | |
4223 | case BFD_RELOC_MIPS16_GPREL: | |
4224 | case BFD_RELOC_MIPS16_GOT16: | |
4225 | case BFD_RELOC_MIPS16_CALL16: | |
4226 | case BFD_RELOC_MIPS16_HI16_S: | |
4227 | case BFD_RELOC_MIPS16_HI16: | |
4228 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4229 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4230 | return TRUE; |
4231 | ||
4232 | default: | |
4233 | return FALSE; | |
4234 | } | |
4235 | } | |
4236 | ||
df58fc94 RS |
4237 | static inline bfd_boolean |
4238 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4239 | { | |
4240 | switch (reloc) | |
4241 | { | |
4242 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4243 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4244 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4245 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4246 | case BFD_RELOC_MICROMIPS_JMP: | |
4247 | case BFD_RELOC_MICROMIPS_HI16: | |
4248 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4249 | case BFD_RELOC_MICROMIPS_LO16: | |
4250 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4251 | case BFD_RELOC_MICROMIPS_GOT16: | |
4252 | case BFD_RELOC_MICROMIPS_CALL16: | |
4253 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4254 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4255 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4256 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4257 | case BFD_RELOC_MICROMIPS_SUB: | |
4258 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4259 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4260 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4261 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4262 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4263 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4264 | case BFD_RELOC_MICROMIPS_JALR: | |
4265 | return TRUE; | |
4266 | ||
4267 | default: | |
4268 | return FALSE; | |
4269 | } | |
4270 | } | |
4271 | ||
2309ddf2 MR |
4272 | static inline bfd_boolean |
4273 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4274 | { | |
4275 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4276 | } | |
4277 | ||
0e9c5a5c MR |
4278 | static inline bfd_boolean |
4279 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4280 | { | |
4281 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4282 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4283 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4284 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4285 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4286 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4287 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4288 | } | |
4289 | ||
738e5348 RS |
4290 | static inline bfd_boolean |
4291 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4292 | { | |
2309ddf2 | 4293 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4294 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4295 | } |
4296 | ||
4297 | static inline bfd_boolean | |
4298 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4299 | { | |
2309ddf2 | 4300 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4301 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4302 | } |
4303 | ||
4304 | static inline bfd_boolean | |
4305 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4306 | { | |
2309ddf2 | 4307 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4308 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4309 | } | |
4310 | ||
df58fc94 RS |
4311 | static inline bfd_boolean |
4312 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4313 | { | |
2309ddf2 | 4314 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4315 | } |
4316 | ||
f2ae14a1 RS |
4317 | static inline bfd_boolean |
4318 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4319 | { | |
4320 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4321 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4322 | } | |
4323 | ||
2de39019 CM |
4324 | /* Return true if RELOC is a PC-relative relocation that does not have |
4325 | full address range. */ | |
4326 | ||
4327 | static inline bfd_boolean | |
4328 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4329 | { | |
4330 | switch (reloc) | |
4331 | { | |
4332 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4333 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4334 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4335 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4336 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4337 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4338 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4339 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4340 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4341 | return TRUE; |
4342 | ||
b47468a6 | 4343 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4344 | case BFD_RELOC_HI16_S_PCREL: |
4345 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4346 | return HAVE_64BIT_ADDRESSES; |
4347 | ||
2de39019 CM |
4348 | default: |
4349 | return FALSE; | |
4350 | } | |
4351 | } | |
b47468a6 | 4352 | |
5919d012 | 4353 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4354 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4355 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4356 | |
4357 | static inline bfd_boolean | |
17a2f251 | 4358 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4359 | { |
3b91255e | 4360 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4361 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4362 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4363 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4364 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4365 | } | |
4366 | ||
4367 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4368 | reloc_needs_lo_p. */ | |
4369 | ||
4370 | static inline bfd_reloc_code_real_type | |
4371 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4372 | { | |
df58fc94 RS |
4373 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4374 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4375 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4376 | } |
4377 | ||
4378 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4379 | relocation. */ | |
4380 | ||
4381 | static inline bfd_boolean | |
17a2f251 | 4382 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4383 | { |
4384 | return (fixp->fx_next != NULL | |
738e5348 | 4385 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4386 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4387 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4388 | } | |
4389 | ||
462427c4 RS |
4390 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4391 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4392 | |
4393 | static void | |
462427c4 | 4394 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4395 | { |
4396 | struct insn_label_list *l; | |
4397 | valueT val; | |
4398 | ||
462427c4 | 4399 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4400 | { |
9c2799c2 | 4401 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4402 | symbol_set_frag (l->label, frag_now); |
4403 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4404 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4405 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4406 | ++val; |
4407 | S_SET_VALUE (l->label, val); | |
4408 | } | |
4409 | } | |
4410 | ||
462427c4 RS |
4411 | /* Move all labels in insn_labels to the current insertion point |
4412 | and treat them as text labels. */ | |
4413 | ||
4414 | static void | |
4415 | mips_move_text_labels (void) | |
4416 | { | |
4417 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4418 | } | |
4419 | ||
9e009953 MR |
4420 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4421 | ||
5f0fe04b TS |
4422 | static bfd_boolean |
4423 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4424 | { | |
4425 | bfd_boolean linkonce = FALSE; | |
4426 | segT symseg = S_GET_SEGMENT (sym); | |
4427 | ||
4428 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4429 | { | |
4430 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4431 | linkonce = TRUE; | |
5f0fe04b TS |
4432 | /* The GNU toolchain uses an extension for ELF: a section |
4433 | beginning with the magic string .gnu.linkonce is a | |
4434 | linkonce section. */ | |
4435 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4436 | sizeof ".gnu.linkonce" - 1) == 0) | |
4437 | linkonce = TRUE; | |
5f0fe04b TS |
4438 | } |
4439 | return linkonce; | |
4440 | } | |
4441 | ||
e1b47bd5 | 4442 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4443 | linker to handle them specially, such as generating jalx instructions |
4444 | when needed. We also make them odd for the duration of the assembly, | |
4445 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4446 | in the adjust_symtab routine, while leaving them marked. This is |
4447 | convenient for the debugger and the disassembler. The linker knows | |
4448 | to make them odd again. */ | |
4449 | ||
4450 | static void | |
e1b47bd5 | 4451 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4452 | { |
df58fc94 | 4453 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4454 | |
f3ded42a RS |
4455 | if (mips_opts.mips16) |
4456 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4457 | else | |
4458 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4459 | if ((S_GET_VALUE (label) & 1) == 0 |
4460 | /* Don't adjust the address if the label is global or weak, or | |
4461 | in a link-once section, since we'll be emitting symbol reloc | |
4462 | references to it which will be patched up by the linker, and | |
4463 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4464 | && !S_IS_WEAK (label) | |
4465 | && !S_IS_EXTERNAL (label) | |
4466 | && !s_is_linkonce (label, now_seg)) | |
4467 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4468 | } | |
4469 | ||
4470 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4471 | ||
4472 | static void | |
4473 | mips_compressed_mark_labels (void) | |
4474 | { | |
4475 | struct insn_label_list *l; | |
4476 | ||
4477 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4478 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4479 | } |
4480 | ||
4d7206a2 RS |
4481 | /* End the current frag. Make it a variant frag and record the |
4482 | relaxation info. */ | |
4483 | ||
4484 | static void | |
4485 | relax_close_frag (void) | |
4486 | { | |
584892a6 | 4487 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4488 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4489 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4490 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4491 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4492 | ||
4493 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4494 | mips_relax.first_fixup = 0; | |
4495 | } | |
4496 | ||
4497 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4498 | See the comment above RELAX_ENCODE for more details. */ | |
4499 | ||
4500 | static void | |
4501 | relax_start (symbolS *symbol) | |
4502 | { | |
9c2799c2 | 4503 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4504 | mips_relax.sequence = 1; |
4505 | mips_relax.symbol = symbol; | |
4506 | } | |
4507 | ||
4508 | /* Start generating the second version of a relaxable sequence. | |
4509 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4510 | |
4511 | static void | |
4d7206a2 RS |
4512 | relax_switch (void) |
4513 | { | |
9c2799c2 | 4514 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4515 | mips_relax.sequence = 2; |
4516 | } | |
4517 | ||
4518 | /* End the current relaxable sequence. */ | |
4519 | ||
4520 | static void | |
4521 | relax_end (void) | |
4522 | { | |
9c2799c2 | 4523 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4524 | relax_close_frag (); |
4525 | mips_relax.sequence = 0; | |
4526 | } | |
4527 | ||
11625dd8 RS |
4528 | /* Return true if IP is a delayed branch or jump. */ |
4529 | ||
4530 | static inline bfd_boolean | |
4531 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4532 | { | |
4533 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4534 | | INSN_COND_BRANCH_DELAY | |
4535 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4536 | } | |
4537 | ||
4538 | /* Return true if IP is a compact branch or jump. */ | |
4539 | ||
4540 | static inline bfd_boolean | |
4541 | compact_branch_p (const struct mips_cl_insn *ip) | |
4542 | { | |
26545944 RS |
4543 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4544 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4545 | } |
4546 | ||
4547 | /* Return true if IP is an unconditional branch or jump. */ | |
4548 | ||
4549 | static inline bfd_boolean | |
4550 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4551 | { | |
4552 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4553 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4554 | } |
4555 | ||
4556 | /* Return true if IP is a branch-likely instruction. */ | |
4557 | ||
4558 | static inline bfd_boolean | |
4559 | branch_likely_p (const struct mips_cl_insn *ip) | |
4560 | { | |
4561 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4562 | } | |
4563 | ||
14fe068b RS |
4564 | /* Return the type of nop that should be used to fill the delay slot |
4565 | of delayed branch IP. */ | |
4566 | ||
4567 | static struct mips_cl_insn * | |
4568 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4569 | { | |
4570 | if (mips_opts.micromips | |
4571 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4572 | return µmips_nop32_insn; | |
4573 | return NOP_INSN; | |
4574 | } | |
4575 | ||
fc76e730 RS |
4576 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4577 | in operand N. */ | |
df58fc94 RS |
4578 | |
4579 | static unsigned int | |
fc76e730 | 4580 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4581 | { |
fc76e730 RS |
4582 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4583 | } | |
df58fc94 | 4584 | |
fc76e730 RS |
4585 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4586 | in operand N. */ | |
4587 | ||
4588 | static unsigned int | |
4589 | insn_write_mask (const struct mips_opcode *opcode) | |
4590 | { | |
4591 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4592 | } | |
4593 | ||
4594 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4595 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4596 | is set. */ | |
4597 | ||
4598 | static unsigned int | |
4599 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4600 | const struct mips_operand *operand, | |
4601 | unsigned int type_mask) | |
4602 | { | |
4603 | unsigned int uval, vsel; | |
4604 | ||
4605 | switch (operand->type) | |
df58fc94 | 4606 | { |
fc76e730 RS |
4607 | case OP_INT: |
4608 | case OP_MAPPED_INT: | |
4609 | case OP_MSB: | |
4610 | case OP_PCREL: | |
4611 | case OP_PERF_REG: | |
4612 | case OP_ADDIUSP_INT: | |
4613 | case OP_ENTRY_EXIT_LIST: | |
4614 | case OP_REPEAT_DEST_REG: | |
4615 | case OP_REPEAT_PREV_REG: | |
4616 | case OP_PC: | |
14daeee3 RS |
4617 | case OP_VU0_SUFFIX: |
4618 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4619 | case OP_IMM_INDEX: |
fc76e730 RS |
4620 | abort (); |
4621 | ||
25499ac7 MR |
4622 | case OP_REG28: |
4623 | return 1 << 28; | |
4624 | ||
fc76e730 | 4625 | case OP_REG: |
0f35dbc4 | 4626 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4627 | { |
4628 | const struct mips_reg_operand *reg_op; | |
4629 | ||
4630 | reg_op = (const struct mips_reg_operand *) operand; | |
4631 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4632 | return 0; | |
4633 | uval = insn_extract_operand (insn, operand); | |
4634 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4635 | } | |
4636 | ||
4637 | case OP_REG_PAIR: | |
4638 | { | |
4639 | const struct mips_reg_pair_operand *pair_op; | |
4640 | ||
4641 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4642 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4643 | return 0; | |
4644 | uval = insn_extract_operand (insn, operand); | |
4645 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4646 | } | |
4647 | ||
4648 | case OP_CLO_CLZ_DEST: | |
4649 | if (!(type_mask & (1 << OP_REG_GP))) | |
4650 | return 0; | |
4651 | uval = insn_extract_operand (insn, operand); | |
4652 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4653 | ||
7361da2c AB |
4654 | case OP_SAME_RS_RT: |
4655 | if (!(type_mask & (1 << OP_REG_GP))) | |
4656 | return 0; | |
4657 | uval = insn_extract_operand (insn, operand); | |
4658 | gas_assert ((uval & 31) == (uval >> 5)); | |
4659 | return 1 << (uval & 31); | |
4660 | ||
4661 | case OP_CHECK_PREV: | |
4662 | case OP_NON_ZERO_REG: | |
4663 | if (!(type_mask & (1 << OP_REG_GP))) | |
4664 | return 0; | |
4665 | uval = insn_extract_operand (insn, operand); | |
4666 | return 1 << (uval & 31); | |
4667 | ||
fc76e730 RS |
4668 | case OP_LWM_SWM_LIST: |
4669 | abort (); | |
4670 | ||
4671 | case OP_SAVE_RESTORE_LIST: | |
4672 | abort (); | |
4673 | ||
4674 | case OP_MDMX_IMM_REG: | |
4675 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4676 | return 0; | |
4677 | uval = insn_extract_operand (insn, operand); | |
4678 | vsel = uval >> 5; | |
4679 | if ((vsel & 0x18) == 0x18) | |
4680 | return 0; | |
4681 | return 1 << (uval & 31); | |
56d438b1 CF |
4682 | |
4683 | case OP_REG_INDEX: | |
4684 | if (!(type_mask & (1 << OP_REG_GP))) | |
4685 | return 0; | |
4686 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4687 | } |
fc76e730 RS |
4688 | abort (); |
4689 | } | |
4690 | ||
4691 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4692 | where bit N of OPNO_MASK is set if operand N should be included. | |
4693 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4694 | is set. */ | |
4695 | ||
4696 | static unsigned int | |
4697 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4698 | unsigned int type_mask, unsigned int opno_mask) | |
4699 | { | |
4700 | unsigned int opno, reg_mask; | |
4701 | ||
4702 | opno = 0; | |
4703 | reg_mask = 0; | |
4704 | while (opno_mask != 0) | |
4705 | { | |
4706 | if (opno_mask & 1) | |
4707 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4708 | opno_mask >>= 1; | |
4709 | opno += 1; | |
4710 | } | |
4711 | return reg_mask; | |
df58fc94 RS |
4712 | } |
4713 | ||
4c260379 RS |
4714 | /* Return the mask of core registers that IP reads. */ |
4715 | ||
4716 | static unsigned int | |
4717 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4718 | { | |
4719 | unsigned long pinfo, pinfo2; | |
4720 | unsigned int mask; | |
4721 | ||
fc76e730 | 4722 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4723 | pinfo = ip->insn_mo->pinfo; |
4724 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4725 | if (pinfo & INSN_UDI) |
4c260379 | 4726 | { |
fc76e730 RS |
4727 | /* UDI instructions have traditionally been assumed to read RS |
4728 | and RT. */ | |
4729 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4730 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4731 | } |
fc76e730 RS |
4732 | if (pinfo & INSN_READ_GPR_24) |
4733 | mask |= 1 << 24; | |
4734 | if (pinfo2 & INSN2_READ_GPR_16) | |
4735 | mask |= 1 << 16; | |
4736 | if (pinfo2 & INSN2_READ_SP) | |
4737 | mask |= 1 << SP; | |
26545944 | 4738 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4739 | mask |= 1 << 31; |
fe35f09f RS |
4740 | /* Don't include register 0. */ |
4741 | return mask & ~1; | |
4c260379 RS |
4742 | } |
4743 | ||
4744 | /* Return the mask of core registers that IP writes. */ | |
4745 | ||
4746 | static unsigned int | |
4747 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4748 | { | |
4749 | unsigned long pinfo, pinfo2; | |
4750 | unsigned int mask; | |
4751 | ||
fc76e730 | 4752 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4753 | pinfo = ip->insn_mo->pinfo; |
4754 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4755 | if (pinfo & INSN_WRITE_GPR_24) |
4756 | mask |= 1 << 24; | |
4757 | if (pinfo & INSN_WRITE_GPR_31) | |
4758 | mask |= 1 << 31; | |
4759 | if (pinfo & INSN_UDI) | |
4760 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4761 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4762 | if (pinfo2 & INSN2_WRITE_SP) | |
4763 | mask |= 1 << SP; | |
fe35f09f RS |
4764 | /* Don't include register 0. */ |
4765 | return mask & ~1; | |
4c260379 RS |
4766 | } |
4767 | ||
4768 | /* Return the mask of floating-point registers that IP reads. */ | |
4769 | ||
4770 | static unsigned int | |
4771 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4772 | { | |
fc76e730 | 4773 | unsigned long pinfo; |
4c260379 RS |
4774 | unsigned int mask; |
4775 | ||
9d5de888 CF |
4776 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4777 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4778 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4779 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4780 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4781 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4782 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4783 | mask |= mask << 1; |
4784 | return mask; | |
4785 | } | |
4786 | ||
4787 | /* Return the mask of floating-point registers that IP writes. */ | |
4788 | ||
4789 | static unsigned int | |
4790 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4791 | { | |
fc76e730 | 4792 | unsigned long pinfo; |
4c260379 RS |
4793 | unsigned int mask; |
4794 | ||
9d5de888 CF |
4795 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4796 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4797 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4798 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4799 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4800 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4801 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4802 | mask |= mask << 1; |
4803 | return mask; | |
4804 | } | |
4805 | ||
a1d78564 RS |
4806 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4807 | Check whether that is allowed. */ | |
4808 | ||
4809 | static bfd_boolean | |
4810 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4811 | { | |
4812 | const char *s = insn->name; | |
351cdf24 MF |
4813 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4814 | || FPR_SIZE == 64) | |
4815 | && mips_opts.oddspreg; | |
a1d78564 RS |
4816 | |
4817 | if (insn->pinfo == INSN_MACRO) | |
4818 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4819 | return TRUE; | |
4820 | ||
351cdf24 MF |
4821 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4822 | otherwise it depends on oddspreg. */ | |
4823 | if ((insn->pinfo & FP_S) | |
4824 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4825 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4826 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4827 | |
351cdf24 MF |
4828 | /* Allow odd registers for single-precision ops and double-precision if the |
4829 | floating-point registers are 64-bit wide. */ | |
4830 | switch (insn->pinfo & (FP_S | FP_D)) | |
4831 | { | |
4832 | case FP_S: | |
4833 | case 0: | |
4834 | return oddspreg; | |
4835 | case FP_D: | |
4836 | return FPR_SIZE == 64; | |
4837 | default: | |
4838 | break; | |
a1d78564 RS |
4839 | } |
4840 | ||
351cdf24 MF |
4841 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4842 | s = strchr (insn->name, '.'); | |
4843 | if (s != NULL && opnum == 2) | |
4844 | s = strchr (s + 1, '.'); | |
4845 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4846 | return oddspreg; | |
a1d78564 | 4847 | |
351cdf24 | 4848 | return FPR_SIZE == 64; |
a1d78564 RS |
4849 | } |
4850 | ||
a1d78564 RS |
4851 | /* Information about an instruction argument that we're trying to match. */ |
4852 | struct mips_arg_info | |
4853 | { | |
4854 | /* The instruction so far. */ | |
4855 | struct mips_cl_insn *insn; | |
4856 | ||
a92713e6 RS |
4857 | /* The first unconsumed operand token. */ |
4858 | struct mips_operand_token *token; | |
4859 | ||
a1d78564 RS |
4860 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4861 | int opnum; | |
4862 | ||
4863 | /* The 1-based argument number, for error reporting. This does not | |
4864 | count elided optional registers, etc.. */ | |
4865 | int argnum; | |
4866 | ||
4867 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4868 | unsigned int last_regno; | |
4869 | ||
4870 | /* If the first operand was an OP_REG, this is the register that it | |
4871 | specified, otherwise it is ILLEGAL_REG. */ | |
4872 | unsigned int dest_regno; | |
4873 | ||
4874 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4875 | where it gives the lsb position. */ | |
4876 | unsigned int last_op_int; | |
4877 | ||
60f20e8b | 4878 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4879 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4880 | possible. Match routines should not report errors if something |
4881 | is only invalid for !LAX_MATCH. */ | |
4882 | bfd_boolean lax_match; | |
a1d78564 | 4883 | |
a1d78564 RS |
4884 | /* True if a reference to the current AT register was seen. */ |
4885 | bfd_boolean seen_at; | |
4886 | }; | |
4887 | ||
1a00e612 RS |
4888 | /* Record that the argument is out of range. */ |
4889 | ||
4890 | static void | |
4891 | match_out_of_range (struct mips_arg_info *arg) | |
4892 | { | |
4893 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4894 | } | |
4895 | ||
4896 | /* Record that the argument isn't constant but needs to be. */ | |
4897 | ||
4898 | static void | |
4899 | match_not_constant (struct mips_arg_info *arg) | |
4900 | { | |
4901 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4902 | arg->argnum); | |
4903 | } | |
4904 | ||
a92713e6 RS |
4905 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4906 | and return true on success, otherwise return false. */ | |
a1d78564 | 4907 | |
a92713e6 RS |
4908 | static bfd_boolean |
4909 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4910 | { |
a92713e6 RS |
4911 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4912 | { | |
4913 | ++arg->token; | |
4914 | if (ch == ',') | |
4915 | arg->argnum += 1; | |
4916 | return TRUE; | |
4917 | } | |
4918 | return FALSE; | |
4919 | } | |
a1d78564 | 4920 | |
a92713e6 RS |
4921 | /* Try to get an expression from the next tokens in ARG. Consume the |
4922 | tokens and return true on success, storing the expression value in | |
4923 | VALUE and relocation types in R. */ | |
4924 | ||
4925 | static bfd_boolean | |
4926 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4927 | bfd_reloc_code_real_type *r) | |
4928 | { | |
d436c1c2 RS |
4929 | /* If the next token is a '(' that was parsed as being part of a base |
4930 | expression, assume we have an elided offset. The later match will fail | |
4931 | if this turns out to be wrong. */ | |
4932 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4933 | { |
d436c1c2 RS |
4934 | value->X_op = O_constant; |
4935 | value->X_add_number = 0; | |
4936 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4937 | return TRUE; |
4938 | } | |
4939 | ||
d436c1c2 RS |
4940 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4941 | For plain registers the default error seems more appropriate. */ | |
4942 | if (arg->token->type == OT_INTEGER | |
4943 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4944 | { |
d436c1c2 RS |
4945 | set_insn_error (arg->argnum, _("register value used as expression")); |
4946 | return FALSE; | |
a1d78564 | 4947 | } |
d436c1c2 RS |
4948 | |
4949 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4950 | { |
d436c1c2 RS |
4951 | *value = arg->token->u.integer.value; |
4952 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4953 | ++arg->token; | |
4954 | return TRUE; | |
a92713e6 | 4955 | } |
a92713e6 | 4956 | |
d436c1c2 RS |
4957 | set_insn_error_i |
4958 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4959 | arg->argnum); | |
4960 | return FALSE; | |
a92713e6 RS |
4961 | } |
4962 | ||
4963 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 4964 | the tokens and return true on success, storing the constant value |
a54d5f8b | 4965 | in *VALUE. */ |
a92713e6 RS |
4966 | |
4967 | static bfd_boolean | |
1a00e612 | 4968 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4969 | { |
4970 | expressionS ex; | |
4971 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4972 | |
a92713e6 RS |
4973 | if (!match_expression (arg, &ex, r)) |
4974 | return FALSE; | |
4975 | ||
4976 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4977 | *value = ex.X_add_number; |
4978 | else | |
4979 | { | |
c96425c5 MR |
4980 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
4981 | match_out_of_range (arg); | |
4982 | else | |
4983 | match_not_constant (arg); | |
1a00e612 | 4984 | return FALSE; |
a1d78564 | 4985 | } |
a92713e6 | 4986 | return TRUE; |
a1d78564 RS |
4987 | } |
4988 | ||
4989 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4990 | appears in instruction OPCODE. */ | |
4991 | ||
4992 | static unsigned int | |
4993 | convert_reg_type (const struct mips_opcode *opcode, | |
4994 | enum mips_reg_operand_type type) | |
4995 | { | |
4996 | switch (type) | |
4997 | { | |
4998 | case OP_REG_GP: | |
4999 | return RTYPE_NUM | RTYPE_GP; | |
5000 | ||
5001 | case OP_REG_FP: | |
5002 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
5003 | FPR load, store or move (including moves to and from GPRs). */ | |
5004 | if ((mips_opts.ase & ASE_MDMX) | |
5005 | && (opcode->pinfo & FP_D) | |
43885403 | 5006 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 5007 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 5008 | | INSN_LOAD_COPROC |
67dc82bc | 5009 | | INSN_LOAD_MEMORY |
a1d78564 RS |
5010 | | INSN_STORE_MEMORY))) |
5011 | return RTYPE_FPU | RTYPE_VEC; | |
5012 | return RTYPE_FPU; | |
5013 | ||
5014 | case OP_REG_CCC: | |
5015 | if (opcode->pinfo & (FP_D | FP_S)) | |
5016 | return RTYPE_CCC | RTYPE_FCC; | |
5017 | return RTYPE_CCC; | |
5018 | ||
5019 | case OP_REG_VEC: | |
5020 | if (opcode->membership & INSN_5400) | |
5021 | return RTYPE_FPU; | |
5022 | return RTYPE_FPU | RTYPE_VEC; | |
5023 | ||
5024 | case OP_REG_ACC: | |
5025 | return RTYPE_ACC; | |
5026 | ||
5027 | case OP_REG_COPRO: | |
5028 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5029 | return RTYPE_NUM | RTYPE_CP0; | |
5030 | return RTYPE_NUM; | |
5031 | ||
5032 | case OP_REG_HW: | |
5033 | return RTYPE_NUM; | |
14daeee3 RS |
5034 | |
5035 | case OP_REG_VI: | |
5036 | return RTYPE_NUM | RTYPE_VI; | |
5037 | ||
5038 | case OP_REG_VF: | |
5039 | return RTYPE_NUM | RTYPE_VF; | |
5040 | ||
5041 | case OP_REG_R5900_I: | |
5042 | return RTYPE_R5900_I; | |
5043 | ||
5044 | case OP_REG_R5900_Q: | |
5045 | return RTYPE_R5900_Q; | |
5046 | ||
5047 | case OP_REG_R5900_R: | |
5048 | return RTYPE_R5900_R; | |
5049 | ||
5050 | case OP_REG_R5900_ACC: | |
5051 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5052 | |
5053 | case OP_REG_MSA: | |
5054 | return RTYPE_MSA; | |
5055 | ||
5056 | case OP_REG_MSA_CTRL: | |
5057 | return RTYPE_NUM; | |
a1d78564 RS |
5058 | } |
5059 | abort (); | |
5060 | } | |
5061 | ||
5062 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5063 | ||
5064 | static void | |
5065 | check_regno (struct mips_arg_info *arg, | |
5066 | enum mips_reg_operand_type type, unsigned int regno) | |
5067 | { | |
5068 | if (AT && type == OP_REG_GP && regno == AT) | |
5069 | arg->seen_at = TRUE; | |
5070 | ||
5071 | if (type == OP_REG_FP | |
5072 | && (regno & 1) != 0 | |
a1d78564 | 5073 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5074 | { |
5075 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5076 | so maintain a warning for FP32 but raise an error for the new | |
5077 | cases. */ | |
5078 | if (FPR_SIZE == 32) | |
5079 | as_warn (_("float register should be even, was %d"), regno); | |
5080 | else | |
5081 | as_bad (_("float register should be even, was %d"), regno); | |
5082 | } | |
a1d78564 RS |
5083 | |
5084 | if (type == OP_REG_CCC) | |
5085 | { | |
5086 | const char *name; | |
5087 | size_t length; | |
5088 | ||
5089 | name = arg->insn->insn_mo->name; | |
5090 | length = strlen (name); | |
5091 | if ((regno & 1) != 0 | |
5092 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5093 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5094 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5095 | name, regno); |
5096 | ||
5097 | if ((regno & 3) != 0 | |
5098 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5099 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5100 | name, regno); |
5101 | } | |
5102 | } | |
5103 | ||
a92713e6 RS |
5104 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5105 | a register of type TYPE. Return true on success, storing the register | |
5106 | number in *REGNO and warning about any dubious uses. */ | |
5107 | ||
5108 | static bfd_boolean | |
5109 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5110 | unsigned int symval, unsigned int *regno) | |
5111 | { | |
5112 | if (type == OP_REG_VEC) | |
5113 | symval = mips_prefer_vec_regno (symval); | |
5114 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5115 | return FALSE; | |
5116 | ||
5117 | *regno = symval & RNUM_MASK; | |
5118 | check_regno (arg, type, *regno); | |
5119 | return TRUE; | |
5120 | } | |
5121 | ||
5122 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5123 | Consume the token and return true on success, storing the register | |
5124 | number in *REGNO. Return false on failure. */ | |
5125 | ||
5126 | static bfd_boolean | |
5127 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5128 | unsigned int *regno) | |
5129 | { | |
5130 | if (arg->token->type == OT_REG | |
5131 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5132 | { | |
5133 | ++arg->token; | |
5134 | return TRUE; | |
5135 | } | |
5136 | return FALSE; | |
5137 | } | |
5138 | ||
5139 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5140 | Consume the token and return true on success, storing the register numbers | |
5141 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5142 | ||
5143 | static bfd_boolean | |
5144 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5145 | unsigned int *regno1, unsigned int *regno2) | |
5146 | { | |
5147 | if (match_reg (arg, type, regno1)) | |
5148 | { | |
5149 | *regno2 = *regno1; | |
5150 | return TRUE; | |
5151 | } | |
5152 | if (arg->token->type == OT_REG_RANGE | |
5153 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5154 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5155 | && *regno1 <= *regno2) | |
5156 | { | |
5157 | ++arg->token; | |
5158 | return TRUE; | |
5159 | } | |
5160 | return FALSE; | |
5161 | } | |
5162 | ||
a1d78564 RS |
5163 | /* OP_INT matcher. */ |
5164 | ||
a92713e6 | 5165 | static bfd_boolean |
a1d78564 | 5166 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5167 | const struct mips_operand *operand_base) |
a1d78564 RS |
5168 | { |
5169 | const struct mips_int_operand *operand; | |
3ccad066 | 5170 | unsigned int uval; |
a1d78564 RS |
5171 | int min_val, max_val, factor; |
5172 | offsetT sval; | |
a1d78564 RS |
5173 | |
5174 | operand = (const struct mips_int_operand *) operand_base; | |
5175 | factor = 1 << operand->shift; | |
3ccad066 RS |
5176 | min_val = mips_int_operand_min (operand); |
5177 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5178 | |
d436c1c2 RS |
5179 | if (operand_base->lsb == 0 |
5180 | && operand_base->size == 16 | |
5181 | && operand->shift == 0 | |
5182 | && operand->bias == 0 | |
5183 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5184 | { |
5185 | /* The operand can be relocated. */ | |
a92713e6 RS |
5186 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5187 | return FALSE; | |
5188 | ||
c96425c5 MR |
5189 | if (offset_expr.X_op == O_big) |
5190 | { | |
5191 | match_out_of_range (arg); | |
5192 | return FALSE; | |
5193 | } | |
5194 | ||
a92713e6 | 5195 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5196 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5197 | leave the relocation value in offset_expr and offset_relocs |
5198 | for the caller to process. */ | |
a92713e6 RS |
5199 | return TRUE; |
5200 | ||
5201 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5202 | { |
60f20e8b RS |
5203 | /* Accept non-constant operands if no later alternative matches, |
5204 | leaving it for the caller to process. */ | |
5205 | if (!arg->lax_match) | |
602b88e3 MR |
5206 | { |
5207 | match_not_constant (arg); | |
5208 | return FALSE; | |
5209 | } | |
a92713e6 RS |
5210 | offset_reloc[0] = BFD_RELOC_LO16; |
5211 | return TRUE; | |
a1d78564 | 5212 | } |
a92713e6 | 5213 | |
a1d78564 RS |
5214 | /* Clear the global state; we're going to install the operand |
5215 | ourselves. */ | |
a92713e6 | 5216 | sval = offset_expr.X_add_number; |
a1d78564 | 5217 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5218 | |
5219 | /* For compatibility with older assemblers, we accept | |
5220 | 0x8000-0xffff as signed 16-bit numbers when only | |
5221 | signed numbers are allowed. */ | |
5222 | if (sval > max_val) | |
5223 | { | |
5224 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5225 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5226 | { |
5227 | match_out_of_range (arg); | |
5228 | return FALSE; | |
5229 | } | |
60f20e8b | 5230 | } |
a1d78564 RS |
5231 | } |
5232 | else | |
5233 | { | |
1a00e612 | 5234 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5235 | return FALSE; |
a1d78564 RS |
5236 | } |
5237 | ||
5238 | arg->last_op_int = sval; | |
5239 | ||
1a00e612 | 5240 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5241 | { |
1a00e612 RS |
5242 | match_out_of_range (arg); |
5243 | return FALSE; | |
a1d78564 RS |
5244 | } |
5245 | ||
5246 | uval = (unsigned int) sval >> operand->shift; | |
5247 | uval -= operand->bias; | |
5248 | ||
5249 | /* Handle -mfix-cn63xxp1. */ | |
5250 | if (arg->opnum == 1 | |
5251 | && mips_fix_cn63xxp1 | |
5252 | && !mips_opts.micromips | |
5253 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5254 | switch (uval) | |
5255 | { | |
5256 | case 5: | |
5257 | case 25: | |
5258 | case 26: | |
5259 | case 27: | |
5260 | case 28: | |
5261 | case 29: | |
5262 | case 30: | |
5263 | case 31: | |
5264 | /* These are ok. */ | |
5265 | break; | |
5266 | ||
5267 | default: | |
5268 | /* The rest must be changed to 28. */ | |
5269 | uval = 28; | |
5270 | break; | |
5271 | } | |
5272 | ||
5273 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5274 | return TRUE; |
a1d78564 RS |
5275 | } |
5276 | ||
5277 | /* OP_MAPPED_INT matcher. */ | |
5278 | ||
a92713e6 | 5279 | static bfd_boolean |
a1d78564 | 5280 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5281 | const struct mips_operand *operand_base) |
a1d78564 RS |
5282 | { |
5283 | const struct mips_mapped_int_operand *operand; | |
5284 | unsigned int uval, num_vals; | |
5285 | offsetT sval; | |
5286 | ||
5287 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5288 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5289 | return FALSE; |
a1d78564 RS |
5290 | |
5291 | num_vals = 1 << operand_base->size; | |
5292 | for (uval = 0; uval < num_vals; uval++) | |
5293 | if (operand->int_map[uval] == sval) | |
5294 | break; | |
5295 | if (uval == num_vals) | |
1a00e612 RS |
5296 | { |
5297 | match_out_of_range (arg); | |
5298 | return FALSE; | |
5299 | } | |
a1d78564 RS |
5300 | |
5301 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5302 | return TRUE; |
a1d78564 RS |
5303 | } |
5304 | ||
5305 | /* OP_MSB matcher. */ | |
5306 | ||
a92713e6 | 5307 | static bfd_boolean |
a1d78564 | 5308 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5309 | const struct mips_operand *operand_base) |
a1d78564 RS |
5310 | { |
5311 | const struct mips_msb_operand *operand; | |
5312 | int min_val, max_val, max_high; | |
5313 | offsetT size, sval, high; | |
5314 | ||
5315 | operand = (const struct mips_msb_operand *) operand_base; | |
5316 | min_val = operand->bias; | |
5317 | max_val = min_val + (1 << operand_base->size) - 1; | |
5318 | max_high = operand->opsize; | |
5319 | ||
1a00e612 | 5320 | if (!match_const_int (arg, &size)) |
a92713e6 | 5321 | return FALSE; |
a1d78564 RS |
5322 | |
5323 | high = size + arg->last_op_int; | |
5324 | sval = operand->add_lsb ? high : size; | |
5325 | ||
5326 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5327 | { | |
1a00e612 RS |
5328 | match_out_of_range (arg); |
5329 | return FALSE; | |
a1d78564 RS |
5330 | } |
5331 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5332 | return TRUE; |
a1d78564 RS |
5333 | } |
5334 | ||
5335 | /* OP_REG matcher. */ | |
5336 | ||
a92713e6 | 5337 | static bfd_boolean |
a1d78564 | 5338 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5339 | const struct mips_operand *operand_base) |
a1d78564 RS |
5340 | { |
5341 | const struct mips_reg_operand *operand; | |
a92713e6 | 5342 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5343 | |
5344 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5345 | if (!match_reg (arg, operand->reg_type, ®no)) |
5346 | return FALSE; | |
a1d78564 RS |
5347 | |
5348 | if (operand->reg_map) | |
5349 | { | |
5350 | num_vals = 1 << operand->root.size; | |
5351 | for (uval = 0; uval < num_vals; uval++) | |
5352 | if (operand->reg_map[uval] == regno) | |
5353 | break; | |
5354 | if (num_vals == uval) | |
a92713e6 | 5355 | return FALSE; |
a1d78564 RS |
5356 | } |
5357 | else | |
5358 | uval = regno; | |
5359 | ||
a1d78564 RS |
5360 | arg->last_regno = regno; |
5361 | if (arg->opnum == 1) | |
5362 | arg->dest_regno = regno; | |
5363 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5364 | return TRUE; |
a1d78564 RS |
5365 | } |
5366 | ||
5367 | /* OP_REG_PAIR matcher. */ | |
5368 | ||
a92713e6 | 5369 | static bfd_boolean |
a1d78564 | 5370 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5371 | const struct mips_operand *operand_base) |
a1d78564 RS |
5372 | { |
5373 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5374 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5375 | |
5376 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5377 | if (!match_reg (arg, operand->reg_type, ®no1) |
5378 | || !match_char (arg, ',') | |
5379 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5380 | return FALSE; | |
a1d78564 RS |
5381 | |
5382 | num_vals = 1 << operand_base->size; | |
5383 | for (uval = 0; uval < num_vals; uval++) | |
5384 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5385 | break; | |
5386 | if (uval == num_vals) | |
a92713e6 | 5387 | return FALSE; |
a1d78564 | 5388 | |
a1d78564 | 5389 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5390 | return TRUE; |
a1d78564 RS |
5391 | } |
5392 | ||
5393 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5394 | ||
a92713e6 RS |
5395 | static bfd_boolean |
5396 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5397 | { |
a92713e6 RS |
5398 | bfd_reloc_code_real_type r[3]; |
5399 | ||
5400 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5401 | } |
5402 | ||
5403 | /* OP_PERF_REG matcher. */ | |
5404 | ||
a92713e6 | 5405 | static bfd_boolean |
a1d78564 | 5406 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5407 | const struct mips_operand *operand) |
a1d78564 RS |
5408 | { |
5409 | offsetT sval; | |
5410 | ||
1a00e612 | 5411 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5412 | return FALSE; |
a1d78564 RS |
5413 | |
5414 | if (sval != 0 | |
5415 | && (sval != 1 | |
5416 | || (mips_opts.arch == CPU_R5900 | |
5417 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5418 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5419 | { | |
1a00e612 RS |
5420 | set_insn_error (arg->argnum, _("invalid performance register")); |
5421 | return FALSE; | |
a1d78564 RS |
5422 | } |
5423 | ||
5424 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5425 | return TRUE; |
a1d78564 RS |
5426 | } |
5427 | ||
5428 | /* OP_ADDIUSP matcher. */ | |
5429 | ||
a92713e6 | 5430 | static bfd_boolean |
a1d78564 | 5431 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5432 | const struct mips_operand *operand) |
a1d78564 RS |
5433 | { |
5434 | offsetT sval; | |
5435 | unsigned int uval; | |
5436 | ||
1a00e612 | 5437 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5438 | return FALSE; |
a1d78564 RS |
5439 | |
5440 | if (sval % 4) | |
1a00e612 RS |
5441 | { |
5442 | match_out_of_range (arg); | |
5443 | return FALSE; | |
5444 | } | |
a1d78564 RS |
5445 | |
5446 | sval /= 4; | |
5447 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5448 | { |
5449 | match_out_of_range (arg); | |
5450 | return FALSE; | |
5451 | } | |
a1d78564 RS |
5452 | |
5453 | uval = (unsigned int) sval; | |
5454 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5455 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5456 | return TRUE; |
a1d78564 RS |
5457 | } |
5458 | ||
5459 | /* OP_CLO_CLZ_DEST matcher. */ | |
5460 | ||
a92713e6 | 5461 | static bfd_boolean |
a1d78564 | 5462 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5463 | const struct mips_operand *operand) |
a1d78564 RS |
5464 | { |
5465 | unsigned int regno; | |
5466 | ||
a92713e6 RS |
5467 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5468 | return FALSE; | |
a1d78564 | 5469 | |
a1d78564 | 5470 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5471 | return TRUE; |
a1d78564 RS |
5472 | } |
5473 | ||
7361da2c AB |
5474 | /* OP_CHECK_PREV matcher. */ |
5475 | ||
5476 | static bfd_boolean | |
5477 | match_check_prev_operand (struct mips_arg_info *arg, | |
5478 | const struct mips_operand *operand_base) | |
5479 | { | |
5480 | const struct mips_check_prev_operand *operand; | |
5481 | unsigned int regno; | |
5482 | ||
5483 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5484 | ||
5485 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5486 | return FALSE; | |
5487 | ||
5488 | if (!operand->zero_ok && regno == 0) | |
5489 | return FALSE; | |
5490 | ||
5491 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5492 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5493 | || (operand->equal_ok && regno == arg->last_regno)) | |
5494 | { | |
5495 | arg->last_regno = regno; | |
5496 | insn_insert_operand (arg->insn, operand_base, regno); | |
5497 | return TRUE; | |
5498 | } | |
5499 | ||
5500 | return FALSE; | |
5501 | } | |
5502 | ||
5503 | /* OP_SAME_RS_RT matcher. */ | |
5504 | ||
5505 | static bfd_boolean | |
5506 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5507 | const struct mips_operand *operand) | |
5508 | { | |
5509 | unsigned int regno; | |
5510 | ||
5511 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5512 | return FALSE; | |
5513 | ||
5514 | if (regno == 0) | |
5515 | { | |
5516 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5517 | return FALSE; | |
5518 | } | |
5519 | ||
5520 | arg->last_regno = regno; | |
5521 | ||
5522 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5523 | return TRUE; | |
5524 | } | |
5525 | ||
a1d78564 RS |
5526 | /* OP_LWM_SWM_LIST matcher. */ |
5527 | ||
a92713e6 | 5528 | static bfd_boolean |
a1d78564 | 5529 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5530 | const struct mips_operand *operand) |
a1d78564 | 5531 | { |
a92713e6 RS |
5532 | unsigned int reglist, sregs, ra, regno1, regno2; |
5533 | struct mips_arg_info reset; | |
a1d78564 | 5534 | |
a92713e6 RS |
5535 | reglist = 0; |
5536 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5537 | return FALSE; | |
5538 | do | |
5539 | { | |
5540 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5541 | { | |
5542 | reglist |= 1 << FP; | |
5543 | regno2 = S7; | |
5544 | } | |
5545 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5546 | reset = *arg; | |
5547 | } | |
5548 | while (match_char (arg, ',') | |
5549 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5550 | *arg = reset; | |
a1d78564 RS |
5551 | |
5552 | if (operand->size == 2) | |
5553 | { | |
5554 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5555 | ||
5556 | s0, ra | |
5557 | s0, s1, ra, s2, s3 | |
5558 | s0-s2, ra | |
5559 | ||
5560 | and any permutations of these. */ | |
5561 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5562 | return FALSE; |
a1d78564 RS |
5563 | |
5564 | sregs = (reglist >> 17) & 7; | |
5565 | ra = 0; | |
5566 | } | |
5567 | else | |
5568 | { | |
5569 | /* The list must include at least one of ra and s0-sN, | |
5570 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5571 | which are $23 and $30 respectively.) E.g.: | |
5572 | ||
5573 | ra | |
5574 | s0 | |
5575 | ra, s0, s1, s2 | |
5576 | s0-s8 | |
5577 | s0-s5, ra | |
5578 | ||
5579 | and any permutations of these. */ | |
5580 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5581 | return FALSE; |
a1d78564 RS |
5582 | |
5583 | ra = (reglist >> 27) & 0x10; | |
5584 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5585 | } | |
5586 | sregs += 1; | |
5587 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5588 | return FALSE; |
a1d78564 RS |
5589 | |
5590 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5591 | return TRUE; |
a1d78564 RS |
5592 | } |
5593 | ||
364215c8 RS |
5594 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5595 | ||
a92713e6 | 5596 | static unsigned int |
364215c8 | 5597 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5598 | const struct mips_operand *operand) |
364215c8 RS |
5599 | { |
5600 | unsigned int mask; | |
5601 | bfd_boolean is_exit; | |
5602 | ||
5603 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5604 | are different. */ | |
5605 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5606 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5607 | do |
364215c8 RS |
5608 | { |
5609 | unsigned int regno1, regno2; | |
5610 | bfd_boolean is_freg; | |
5611 | ||
a92713e6 | 5612 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5613 | is_freg = FALSE; |
a92713e6 | 5614 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5615 | is_freg = TRUE; |
5616 | else | |
a92713e6 | 5617 | return FALSE; |
364215c8 RS |
5618 | |
5619 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5620 | { | |
5621 | mask &= ~(7 << 3); | |
5622 | mask |= (5 + regno2) << 3; | |
5623 | } | |
5624 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5625 | mask |= (regno2 - 3) << 3; | |
5626 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5627 | mask |= (regno2 - 15) << 1; | |
5628 | else if (regno1 == RA && regno2 == RA) | |
5629 | mask |= 1; | |
5630 | else | |
a92713e6 | 5631 | return FALSE; |
364215c8 | 5632 | } |
a92713e6 RS |
5633 | while (match_char (arg, ',')); |
5634 | ||
364215c8 | 5635 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5636 | return TRUE; |
364215c8 RS |
5637 | } |
5638 | ||
38bf472a MR |
5639 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5640 | the argument register mask AMASK, the number of static registers | |
5641 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5642 | respectively, and the frame size FRAME_SIZE. */ | |
5643 | ||
5644 | static unsigned int | |
5645 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5646 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5647 | unsigned int frame_size) | |
5648 | { | |
5649 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5650 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5651 | } | |
5652 | ||
5653 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5654 | argument register mask AMASK, the number of static registers saved | |
5655 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5656 | respectively, and the frame size FRAME_SIZE. */ | |
5657 | ||
5658 | static unsigned int | |
5659 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5660 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5661 | unsigned int frame_size) | |
5662 | { | |
5663 | unsigned int args; | |
5664 | ||
5665 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5666 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5667 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5668 | | ((frame_size & 0xf0) << 16)); | |
5669 | return args; | |
5670 | } | |
5671 | ||
364215c8 RS |
5672 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5673 | ||
a92713e6 RS |
5674 | static bfd_boolean |
5675 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5676 | { |
5677 | unsigned int opcode, args, statics, sregs; | |
5678 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5679 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5680 | offsetT frame_size; |
364215c8 | 5681 | |
364215c8 RS |
5682 | opcode = arg->insn->insn_opcode; |
5683 | frame_size = 0; | |
5684 | num_frame_sizes = 0; | |
5685 | args = 0; | |
5686 | statics = 0; | |
5687 | sregs = 0; | |
38bf472a MR |
5688 | ra = 0; |
5689 | s0 = 0; | |
5690 | s1 = 0; | |
a92713e6 | 5691 | do |
364215c8 RS |
5692 | { |
5693 | unsigned int regno1, regno2; | |
5694 | ||
a92713e6 | 5695 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5696 | { |
5697 | /* Handle the frame size. */ | |
1a00e612 | 5698 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5699 | return FALSE; |
364215c8 | 5700 | num_frame_sizes += 1; |
364215c8 RS |
5701 | } |
5702 | else | |
5703 | { | |
a92713e6 RS |
5704 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5705 | return FALSE; | |
364215c8 RS |
5706 | |
5707 | while (regno1 <= regno2) | |
5708 | { | |
5709 | if (regno1 >= 4 && regno1 <= 7) | |
5710 | { | |
5711 | if (num_frame_sizes == 0) | |
5712 | /* args $a0-$a3 */ | |
5713 | args |= 1 << (regno1 - 4); | |
5714 | else | |
5715 | /* statics $a0-$a3 */ | |
5716 | statics |= 1 << (regno1 - 4); | |
5717 | } | |
5718 | else if (regno1 >= 16 && regno1 <= 23) | |
5719 | /* $s0-$s7 */ | |
5720 | sregs |= 1 << (regno1 - 16); | |
5721 | else if (regno1 == 30) | |
5722 | /* $s8 */ | |
5723 | sregs |= 1 << 8; | |
5724 | else if (regno1 == 31) | |
5725 | /* Add $ra to insn. */ | |
38bf472a | 5726 | ra = 1; |
364215c8 | 5727 | else |
a92713e6 | 5728 | return FALSE; |
364215c8 RS |
5729 | regno1 += 1; |
5730 | if (regno1 == 24) | |
5731 | regno1 = 30; | |
5732 | } | |
5733 | } | |
364215c8 | 5734 | } |
a92713e6 | 5735 | while (match_char (arg, ',')); |
364215c8 RS |
5736 | |
5737 | /* Encode args/statics combination. */ | |
5738 | if (args & statics) | |
a92713e6 | 5739 | return FALSE; |
364215c8 RS |
5740 | else if (args == 0xf) |
5741 | /* All $a0-$a3 are args. */ | |
38bf472a | 5742 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5743 | else if (statics == 0xf) |
5744 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5745 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5746 | else |
5747 | { | |
5748 | /* Count arg registers. */ | |
5749 | num_args = 0; | |
5750 | while (args & 0x1) | |
5751 | { | |
5752 | args >>= 1; | |
5753 | num_args += 1; | |
5754 | } | |
5755 | if (args != 0) | |
a92713e6 | 5756 | return FALSE; |
364215c8 RS |
5757 | |
5758 | /* Count static registers. */ | |
5759 | num_statics = 0; | |
5760 | while (statics & 0x8) | |
5761 | { | |
5762 | statics = (statics << 1) & 0xf; | |
5763 | num_statics += 1; | |
5764 | } | |
5765 | if (statics != 0) | |
a92713e6 | 5766 | return FALSE; |
364215c8 RS |
5767 | |
5768 | /* Encode args/statics. */ | |
38bf472a | 5769 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5770 | } |
5771 | ||
5772 | /* Encode $s0/$s1. */ | |
5773 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5774 | s0 = 1; |
364215c8 | 5775 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5776 | s1 = 1; |
364215c8 RS |
5777 | sregs >>= 2; |
5778 | ||
5779 | /* Encode $s2-$s8. */ | |
5780 | num_sregs = 0; | |
5781 | while (sregs & 1) | |
5782 | { | |
5783 | sregs >>= 1; | |
5784 | num_sregs += 1; | |
5785 | } | |
5786 | if (sregs != 0) | |
a92713e6 | 5787 | return FALSE; |
364215c8 RS |
5788 | |
5789 | /* Encode frame size. */ | |
5790 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5791 | { |
5792 | set_insn_error (arg->argnum, _("missing frame size")); | |
5793 | return FALSE; | |
5794 | } | |
5795 | if (num_frame_sizes > 1) | |
5796 | { | |
5797 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5798 | return FALSE; | |
5799 | } | |
5800 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5801 | { | |
5802 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5803 | return FALSE; | |
5804 | } | |
38bf472a | 5805 | frame_size /= 8; |
364215c8 | 5806 | |
364215c8 | 5807 | /* Finally build the instruction. */ |
38bf472a MR |
5808 | if (mips_opts.mips16) |
5809 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5810 | frame_size); | |
5811 | else if (!mips_opts.micromips) | |
5812 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5813 | frame_size); | |
5814 | else | |
5815 | abort (); | |
5816 | ||
364215c8 | 5817 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5818 | return TRUE; |
364215c8 RS |
5819 | } |
5820 | ||
a1d78564 RS |
5821 | /* OP_MDMX_IMM_REG matcher. */ |
5822 | ||
a92713e6 | 5823 | static bfd_boolean |
a1d78564 | 5824 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5825 | const struct mips_operand *operand) |
a1d78564 | 5826 | { |
a92713e6 | 5827 | unsigned int regno, uval; |
a1d78564 RS |
5828 | bfd_boolean is_qh; |
5829 | const struct mips_opcode *opcode; | |
5830 | ||
5831 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5832 | instruction. Start out with that bit in place. */ | |
5833 | opcode = arg->insn->insn_mo; | |
5834 | uval = mips_extract_operand (operand, opcode->match); | |
5835 | is_qh = (uval != 0); | |
5836 | ||
56d438b1 | 5837 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5838 | { |
5839 | if ((opcode->membership & INSN_5400) | |
5840 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5841 | { | |
1a00e612 RS |
5842 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5843 | arg->argnum); | |
5844 | return FALSE; | |
a1d78564 RS |
5845 | } |
5846 | ||
56d438b1 CF |
5847 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5848 | return FALSE; | |
5849 | ++arg->token; | |
5850 | ||
a1d78564 RS |
5851 | /* Check whether this is a vector register or a broadcast of |
5852 | a single element. */ | |
56d438b1 | 5853 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5854 | { |
56d438b1 | 5855 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5856 | { |
1a00e612 RS |
5857 | set_insn_error (arg->argnum, _("invalid element selector")); |
5858 | return FALSE; | |
a1d78564 | 5859 | } |
56d438b1 CF |
5860 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5861 | ++arg->token; | |
a1d78564 RS |
5862 | } |
5863 | else | |
5864 | { | |
5865 | /* A full vector. */ | |
5866 | if ((opcode->membership & INSN_5400) | |
5867 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5868 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5869 | { | |
1a00e612 RS |
5870 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5871 | arg->argnum); | |
5872 | return FALSE; | |
a1d78564 RS |
5873 | } |
5874 | ||
5875 | if (is_qh) | |
5876 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5877 | else | |
5878 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5879 | } | |
a1d78564 RS |
5880 | uval |= regno; |
5881 | } | |
5882 | else | |
5883 | { | |
5884 | offsetT sval; | |
5885 | ||
1a00e612 | 5886 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5887 | return FALSE; |
a1d78564 RS |
5888 | if (sval < 0 || sval > 31) |
5889 | { | |
1a00e612 RS |
5890 | match_out_of_range (arg); |
5891 | return FALSE; | |
a1d78564 RS |
5892 | } |
5893 | uval |= (sval & 31); | |
5894 | if (is_qh) | |
5895 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5896 | else | |
5897 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5898 | } | |
5899 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5900 | return TRUE; |
a1d78564 RS |
5901 | } |
5902 | ||
56d438b1 CF |
5903 | /* OP_IMM_INDEX matcher. */ |
5904 | ||
5905 | static bfd_boolean | |
5906 | match_imm_index_operand (struct mips_arg_info *arg, | |
5907 | const struct mips_operand *operand) | |
5908 | { | |
5909 | unsigned int max_val; | |
5910 | ||
5911 | if (arg->token->type != OT_INTEGER_INDEX) | |
5912 | return FALSE; | |
5913 | ||
5914 | max_val = (1 << operand->size) - 1; | |
5915 | if (arg->token->u.index > max_val) | |
5916 | { | |
5917 | match_out_of_range (arg); | |
5918 | return FALSE; | |
5919 | } | |
5920 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5921 | ++arg->token; | |
5922 | return TRUE; | |
5923 | } | |
5924 | ||
5925 | /* OP_REG_INDEX matcher. */ | |
5926 | ||
5927 | static bfd_boolean | |
5928 | match_reg_index_operand (struct mips_arg_info *arg, | |
5929 | const struct mips_operand *operand) | |
5930 | { | |
5931 | unsigned int regno; | |
5932 | ||
5933 | if (arg->token->type != OT_REG_INDEX) | |
5934 | return FALSE; | |
5935 | ||
5936 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5937 | return FALSE; | |
5938 | ||
5939 | insn_insert_operand (arg->insn, operand, regno); | |
5940 | ++arg->token; | |
5941 | return TRUE; | |
5942 | } | |
5943 | ||
a1d78564 RS |
5944 | /* OP_PC matcher. */ |
5945 | ||
a92713e6 RS |
5946 | static bfd_boolean |
5947 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5948 | { |
a92713e6 RS |
5949 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5950 | { | |
5951 | ++arg->token; | |
5952 | return TRUE; | |
5953 | } | |
5954 | return FALSE; | |
a1d78564 RS |
5955 | } |
5956 | ||
25499ac7 MR |
5957 | /* OP_REG28 matcher. */ |
5958 | ||
5959 | static bfd_boolean | |
5960 | match_reg28_operand (struct mips_arg_info *arg) | |
5961 | { | |
5962 | unsigned int regno; | |
5963 | ||
5964 | if (arg->token->type == OT_REG | |
5965 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
5966 | && regno == GP) | |
5967 | { | |
5968 | ++arg->token; | |
5969 | return TRUE; | |
5970 | } | |
5971 | return FALSE; | |
5972 | } | |
5973 | ||
7361da2c AB |
5974 | /* OP_NON_ZERO_REG matcher. */ |
5975 | ||
5976 | static bfd_boolean | |
5977 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5978 | const struct mips_operand *operand) | |
5979 | { | |
5980 | unsigned int regno; | |
5981 | ||
5982 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5983 | return FALSE; | |
5984 | ||
5985 | if (regno == 0) | |
5986 | return FALSE; | |
5987 | ||
5988 | arg->last_regno = regno; | |
5989 | insn_insert_operand (arg->insn, operand, regno); | |
5990 | return TRUE; | |
5991 | } | |
5992 | ||
a1d78564 RS |
5993 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5994 | register that we need to match. */ | |
5995 | ||
a92713e6 RS |
5996 | static bfd_boolean |
5997 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5998 | { |
5999 | unsigned int regno; | |
6000 | ||
a92713e6 | 6001 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
6002 | } |
6003 | ||
33f46696 MR |
6004 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
6005 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
6006 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
6007 | |
6008 | Return the constant in IMM and OFFSET as follows: | |
6009 | ||
6010 | - If the constant should be loaded via memory, set IMM to O_absent and | |
6011 | OFFSET to the memory address. | |
6012 | ||
6013 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
6014 | set IMM to the O_constant to load into the high register and OFFSET | |
6015 | to the corresponding value for the low register. | |
6016 | ||
6017 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
6018 | ||
6019 | These constants only appear as the last operand in an instruction, | |
6020 | and every instruction that accepts them in any variant accepts them | |
6021 | in all variants. This means we don't have to worry about backing out | |
6022 | any changes if the instruction does not match. We just match | |
6023 | unconditionally and report an error if the constant is invalid. */ | |
6024 | ||
a92713e6 RS |
6025 | static bfd_boolean |
6026 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
6027 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 6028 | { |
a92713e6 | 6029 | char *p; |
89565f1b RS |
6030 | segT seg, new_seg; |
6031 | subsegT subseg; | |
6032 | const char *newname; | |
a92713e6 | 6033 | unsigned char *data; |
89565f1b RS |
6034 | |
6035 | /* Where the constant is placed is based on how the MIPS assembler | |
6036 | does things: | |
6037 | ||
6038 | length == 4 && using_gprs -- immediate value only | |
6039 | length == 8 && using_gprs -- .rdata or immediate value | |
6040 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6041 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6042 | ||
6043 | The .lit4 and .lit8 sections are only used if permitted by the | |
6044 | -G argument. */ | |
a92713e6 | 6045 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6046 | { |
6047 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6048 | return FALSE; | |
6049 | } | |
a92713e6 RS |
6050 | |
6051 | gas_assert (arg->token->u.flt.length == length); | |
6052 | data = arg->token->u.flt.data; | |
6053 | ++arg->token; | |
89565f1b RS |
6054 | |
6055 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6056 | if (length == 4 | |
6057 | && (using_gprs | |
6058 | || g_switch_value < 4 | |
6059 | || (data[0] == 0 && data[1] == 0) | |
6060 | || (data[2] == 0 && data[3] == 0))) | |
6061 | { | |
6062 | imm->X_op = O_constant; | |
6063 | if (!target_big_endian) | |
6064 | imm->X_add_number = bfd_getl32 (data); | |
6065 | else | |
6066 | imm->X_add_number = bfd_getb32 (data); | |
6067 | offset->X_op = O_absent; | |
a92713e6 | 6068 | return TRUE; |
89565f1b RS |
6069 | } |
6070 | ||
6071 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6072 | if (length == 8 | |
6073 | && !mips_disable_float_construction | |
351cdf24 MF |
6074 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6075 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6076 | Unlike most tests for 32-bit floating-point registers this check | |
6077 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6078 | permit 64-bit moves without MXHC1. | |
6079 | Force the constant into memory otherwise. */ | |
6080 | && (using_gprs | |
6081 | || GPR_SIZE == 64 | |
6082 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6083 | || FPR_SIZE == 32) | |
89565f1b RS |
6084 | && ((data[0] == 0 && data[1] == 0) |
6085 | || (data[2] == 0 && data[3] == 0)) | |
6086 | && ((data[4] == 0 && data[5] == 0) | |
6087 | || (data[6] == 0 && data[7] == 0))) | |
6088 | { | |
6089 | /* The value is simple enough to load with a couple of instructions. | |
6090 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6091 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6092 | 64 bit constant. */ | |
351cdf24 | 6093 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6094 | { |
6095 | imm->X_op = O_constant; | |
6096 | offset->X_op = O_constant; | |
6097 | if (!target_big_endian) | |
6098 | { | |
6099 | imm->X_add_number = bfd_getl32 (data + 4); | |
6100 | offset->X_add_number = bfd_getl32 (data); | |
6101 | } | |
6102 | else | |
6103 | { | |
6104 | imm->X_add_number = bfd_getb32 (data); | |
6105 | offset->X_add_number = bfd_getb32 (data + 4); | |
6106 | } | |
6107 | if (offset->X_add_number == 0) | |
6108 | offset->X_op = O_absent; | |
6109 | } | |
6110 | else | |
6111 | { | |
6112 | imm->X_op = O_constant; | |
6113 | if (!target_big_endian) | |
6114 | imm->X_add_number = bfd_getl64 (data); | |
6115 | else | |
6116 | imm->X_add_number = bfd_getb64 (data); | |
6117 | offset->X_op = O_absent; | |
6118 | } | |
a92713e6 | 6119 | return TRUE; |
89565f1b RS |
6120 | } |
6121 | ||
6122 | /* Switch to the right section. */ | |
6123 | seg = now_seg; | |
6124 | subseg = now_subseg; | |
6125 | if (length == 4) | |
6126 | { | |
6127 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6128 | newname = ".lit4"; | |
6129 | } | |
6130 | else | |
6131 | { | |
6132 | if (using_gprs || g_switch_value < 8) | |
6133 | newname = RDATA_SECTION_NAME; | |
6134 | else | |
6135 | newname = ".lit8"; | |
6136 | } | |
6137 | ||
6138 | new_seg = subseg_new (newname, (subsegT) 0); | |
6139 | bfd_set_section_flags (stdoutput, new_seg, | |
6140 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6141 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6142 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6143 | record_alignment (new_seg, 4); | |
6144 | else | |
6145 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6146 | if (seg == now_seg) | |
1661c76c | 6147 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6148 | |
6149 | /* Set the argument to the current address in the section. */ | |
6150 | imm->X_op = O_absent; | |
6151 | offset->X_op = O_symbol; | |
6152 | offset->X_add_symbol = symbol_temp_new_now (); | |
6153 | offset->X_add_number = 0; | |
6154 | ||
6155 | /* Put the floating point number into the section. */ | |
6156 | p = frag_more (length); | |
6157 | memcpy (p, data, length); | |
6158 | ||
6159 | /* Switch back to the original section. */ | |
6160 | subseg_set (seg, subseg); | |
a92713e6 | 6161 | return TRUE; |
89565f1b RS |
6162 | } |
6163 | ||
14daeee3 RS |
6164 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6165 | them. */ | |
6166 | ||
6167 | static bfd_boolean | |
6168 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6169 | const struct mips_operand *operand, | |
6170 | bfd_boolean match_p) | |
6171 | { | |
6172 | unsigned int uval; | |
6173 | ||
6174 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6175 | (with X being 0). */ | |
6176 | gas_assert (operand->size == 2 || operand->size == 4); | |
6177 | ||
ee5734f0 | 6178 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6179 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6180 | return match_p; |
14daeee3 RS |
6181 | |
6182 | uval = arg->token->u.channels; | |
6183 | if (operand->size == 2) | |
6184 | { | |
6185 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6186 | if ((uval & -uval) != uval) | |
6187 | return FALSE; | |
6188 | uval = 4 - ffs (uval); | |
6189 | } | |
6190 | ||
6191 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6192 | return FALSE; | |
6193 | ||
6194 | ++arg->token; | |
6195 | if (!match_p) | |
6196 | insn_insert_operand (arg->insn, operand, uval); | |
6197 | return TRUE; | |
6198 | } | |
6199 | ||
33f46696 MR |
6200 | /* Try to match a token from ARG against OPERAND. Consume the token |
6201 | and return true on success, otherwise return false. */ | |
a1d78564 | 6202 | |
a92713e6 | 6203 | static bfd_boolean |
a1d78564 | 6204 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6205 | const struct mips_operand *operand) |
a1d78564 RS |
6206 | { |
6207 | switch (operand->type) | |
6208 | { | |
6209 | case OP_INT: | |
a92713e6 | 6210 | return match_int_operand (arg, operand); |
a1d78564 RS |
6211 | |
6212 | case OP_MAPPED_INT: | |
a92713e6 | 6213 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6214 | |
6215 | case OP_MSB: | |
a92713e6 | 6216 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6217 | |
6218 | case OP_REG: | |
0f35dbc4 | 6219 | case OP_OPTIONAL_REG: |
a92713e6 | 6220 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6221 | |
6222 | case OP_REG_PAIR: | |
a92713e6 | 6223 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6224 | |
6225 | case OP_PCREL: | |
a92713e6 | 6226 | return match_pcrel_operand (arg); |
a1d78564 RS |
6227 | |
6228 | case OP_PERF_REG: | |
a92713e6 | 6229 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6230 | |
6231 | case OP_ADDIUSP_INT: | |
a92713e6 | 6232 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6233 | |
6234 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6235 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6236 | |
6237 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6238 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6239 | |
6240 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6241 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6242 | |
a1d78564 | 6243 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6244 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6245 | |
6246 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6247 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6248 | |
6249 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6250 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6251 | |
6252 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6253 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6254 | |
6255 | case OP_PC: | |
a92713e6 | 6256 | return match_pc_operand (arg); |
14daeee3 | 6257 | |
25499ac7 MR |
6258 | case OP_REG28: |
6259 | return match_reg28_operand (arg); | |
6260 | ||
14daeee3 RS |
6261 | case OP_VU0_SUFFIX: |
6262 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6263 | ||
6264 | case OP_VU0_MATCH_SUFFIX: | |
6265 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6266 | |
6267 | case OP_IMM_INDEX: | |
6268 | return match_imm_index_operand (arg, operand); | |
6269 | ||
6270 | case OP_REG_INDEX: | |
6271 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6272 | |
6273 | case OP_SAME_RS_RT: | |
6274 | return match_same_rs_rt_operand (arg, operand); | |
6275 | ||
6276 | case OP_CHECK_PREV: | |
6277 | return match_check_prev_operand (arg, operand); | |
6278 | ||
6279 | case OP_NON_ZERO_REG: | |
6280 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6281 | } |
6282 | abort (); | |
6283 | } | |
6284 | ||
6285 | /* ARG is the state after successfully matching an instruction. | |
6286 | Issue any queued-up warnings. */ | |
6287 | ||
6288 | static void | |
6289 | check_completed_insn (struct mips_arg_info *arg) | |
6290 | { | |
6291 | if (arg->seen_at) | |
6292 | { | |
6293 | if (AT == ATREG) | |
1661c76c | 6294 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6295 | else |
1661c76c | 6296 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6297 | } |
6298 | } | |
a1d78564 | 6299 | |
85fcb30f RS |
6300 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6301 | ||
6302 | static bfd_boolean | |
6303 | reg_needs_delay (unsigned int reg) | |
6304 | { | |
6305 | unsigned long prev_pinfo; | |
6306 | ||
6307 | prev_pinfo = history[0].insn_mo->pinfo; | |
6308 | if (!mips_opts.noreorder | |
67dc82bc | 6309 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6310 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6311 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6312 | return TRUE; | |
6313 | ||
6314 | return FALSE; | |
6315 | } | |
6316 | ||
71400594 RS |
6317 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6318 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6319 | by VR4120 errata. */ | |
4d7206a2 | 6320 | |
71400594 RS |
6321 | static unsigned int |
6322 | classify_vr4120_insn (const char *name) | |
252b5132 | 6323 | { |
71400594 RS |
6324 | if (strncmp (name, "macc", 4) == 0) |
6325 | return FIX_VR4120_MACC; | |
6326 | if (strncmp (name, "dmacc", 5) == 0) | |
6327 | return FIX_VR4120_DMACC; | |
6328 | if (strncmp (name, "mult", 4) == 0) | |
6329 | return FIX_VR4120_MULT; | |
6330 | if (strncmp (name, "dmult", 5) == 0) | |
6331 | return FIX_VR4120_DMULT; | |
6332 | if (strstr (name, "div")) | |
6333 | return FIX_VR4120_DIV; | |
6334 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6335 | return FIX_VR4120_MTHILO; | |
6336 | return NUM_FIX_VR4120_CLASSES; | |
6337 | } | |
252b5132 | 6338 | |
a8d14a88 CM |
6339 | #define INSN_ERET 0x42000018 |
6340 | #define INSN_DERET 0x4200001f | |
6341 | #define INSN_DMULT 0x1c | |
6342 | #define INSN_DMULTU 0x1d | |
ff239038 | 6343 | |
71400594 RS |
6344 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6345 | where INSN1 is the earlier instruction. Return the worst-case value | |
6346 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6347 | |
71400594 RS |
6348 | static unsigned int |
6349 | insns_between (const struct mips_cl_insn *insn1, | |
6350 | const struct mips_cl_insn *insn2) | |
6351 | { | |
6352 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6353 | unsigned int mask; |
71400594 | 6354 | |
85fcb30f RS |
6355 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6356 | the second instruction. */ | |
71400594 RS |
6357 | pinfo1 = insn1->insn_mo->pinfo; |
6358 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6359 | |
71400594 RS |
6360 | /* For most targets, write-after-read dependencies on the HI and LO |
6361 | registers must be separated by at least two instructions. */ | |
6362 | if (!hilo_interlocks) | |
252b5132 | 6363 | { |
71400594 RS |
6364 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6365 | return 2; | |
6366 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6367 | return 2; | |
6368 | } | |
6369 | ||
6370 | /* If we're working around r7000 errata, there must be two instructions | |
6371 | between an mfhi or mflo and any instruction that uses the result. */ | |
6372 | if (mips_7000_hilo_fix | |
df58fc94 | 6373 | && !mips_opts.micromips |
71400594 | 6374 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6375 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6376 | return 2; |
6377 | ||
ff239038 CM |
6378 | /* If we're working around 24K errata, one instruction is required |
6379 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6380 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6381 | { |
6382 | if (insn1->insn_opcode == INSN_ERET | |
6383 | || insn1->insn_opcode == INSN_DERET) | |
6384 | { | |
6385 | if (insn2 == NULL | |
6386 | || insn2->insn_opcode == INSN_ERET | |
6387 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6388 | || delayed_branch_p (insn2)) |
ff239038 CM |
6389 | return 1; |
6390 | } | |
6391 | } | |
6392 | ||
a8d14a88 CM |
6393 | /* If we're working around PMC RM7000 errata, there must be three |
6394 | nops between a dmult and a load instruction. */ | |
6395 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6396 | { | |
6397 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6398 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6399 | { | |
6400 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6401 | return 3; | |
6402 | } | |
6403 | } | |
6404 | ||
71400594 RS |
6405 | /* If working around VR4120 errata, check for combinations that need |
6406 | a single intervening instruction. */ | |
df58fc94 | 6407 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6408 | { |
6409 | unsigned int class1, class2; | |
252b5132 | 6410 | |
71400594 RS |
6411 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6412 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6413 | { |
71400594 RS |
6414 | if (insn2 == NULL) |
6415 | return 1; | |
6416 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6417 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6418 | return 1; | |
252b5132 | 6419 | } |
71400594 RS |
6420 | } |
6421 | ||
df58fc94 | 6422 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6423 | { |
6424 | /* Check for GPR or coprocessor load delays. All such delays | |
6425 | are on the RT register. */ | |
6426 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6427 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6428 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6429 | { |
85fcb30f | 6430 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6431 | return 1; |
6432 | } | |
6433 | ||
6434 | /* Check for generic coprocessor hazards. | |
6435 | ||
6436 | This case is not handled very well. There is no special | |
6437 | knowledge of CP0 handling, and the coprocessors other than | |
6438 | the floating point unit are not distinguished at all. */ | |
6439 | /* Itbl support may require additional care here. FIXME! | |
6440 | Need to modify this to include knowledge about | |
6441 | user specified delays! */ | |
43885403 | 6442 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6443 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6444 | { | |
6445 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6446 | register. There must be a one instruction delay before INSN2 | |
6447 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6448 | mask = fpr_write_mask (insn1); |
6449 | if (mask != 0) | |
252b5132 | 6450 | { |
4c260379 | 6451 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6452 | return 1; |
252b5132 RH |
6453 | } |
6454 | else | |
6455 | { | |
71400594 RS |
6456 | /* Read-after-write dependencies on the control registers |
6457 | require a two-instruction gap. */ | |
6458 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6459 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6460 | return 2; | |
6461 | ||
6462 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6463 | also a coprocessor instruction, assume there must be | |
6464 | a one instruction gap. */ | |
6465 | if (pinfo2 & INSN_COP) | |
6466 | return 1; | |
252b5132 RH |
6467 | } |
6468 | } | |
6b76fefe | 6469 | |
71400594 RS |
6470 | /* Check for read-after-write dependencies on the coprocessor |
6471 | control registers in cases where INSN1 does not need a general | |
6472 | coprocessor delay. This means that INSN1 is a floating point | |
6473 | comparison instruction. */ | |
6474 | /* Itbl support may require additional care here. */ | |
6475 | else if (!cop_interlocks | |
6476 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6477 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6478 | return 1; | |
6479 | } | |
6b76fefe | 6480 | |
7361da2c AB |
6481 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6482 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6483 | and pause. */ | |
6484 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6485 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6486 | || (insn2 && delayed_branch_p (insn2)))) | |
6487 | return 1; | |
6488 | ||
71400594 RS |
6489 | return 0; |
6490 | } | |
6b76fefe | 6491 | |
7d8e00cf RS |
6492 | /* Return the number of nops that would be needed to work around the |
6493 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6494 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6495 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6496 | |
6497 | static int | |
932d1a1b | 6498 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6499 | const struct mips_cl_insn *insn) |
6500 | { | |
4c260379 RS |
6501 | int i, j; |
6502 | unsigned int mask; | |
7d8e00cf RS |
6503 | |
6504 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6505 | are not affected by the errata. */ | |
6506 | if (insn != 0 | |
6507 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6508 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6509 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6510 | return 0; | |
6511 | ||
6512 | /* Search for the first MFLO or MFHI. */ | |
6513 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6514 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6515 | { |
6516 | /* Extract the destination register. */ | |
4c260379 | 6517 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6518 | |
6519 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6520 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6521 | return 0; |
6522 | ||
6523 | /* ...or if any of the intervening instructions do. */ | |
6524 | for (j = 0; j < i; j++) | |
4c260379 | 6525 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6526 | return 0; |
6527 | ||
932d1a1b RS |
6528 | if (i >= ignore) |
6529 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6530 | } |
6531 | return 0; | |
6532 | } | |
6533 | ||
134c0c8b MR |
6534 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6535 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6536 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6537 | ||
6538 | /* Return the minimum alignment for this store instruction. */ | |
6539 | ||
6540 | static int | |
6541 | fix_24k_align_to (const struct mips_opcode *mo) | |
6542 | { | |
6543 | if (strcmp (mo->name, "sh") == 0) | |
6544 | return 2; | |
6545 | ||
6546 | if (strcmp (mo->name, "swc1") == 0 | |
6547 | || strcmp (mo->name, "swc2") == 0 | |
6548 | || strcmp (mo->name, "sw") == 0 | |
6549 | || strcmp (mo->name, "sc") == 0 | |
6550 | || strcmp (mo->name, "s.s") == 0) | |
6551 | return 4; | |
6552 | ||
6553 | if (strcmp (mo->name, "sdc1") == 0 | |
6554 | || strcmp (mo->name, "sdc2") == 0 | |
6555 | || strcmp (mo->name, "s.d") == 0) | |
6556 | return 8; | |
6557 | ||
6558 | /* sb, swl, swr */ | |
6559 | return 1; | |
6560 | } | |
6561 | ||
6562 | struct fix_24k_store_info | |
6563 | { | |
6564 | /* Immediate offset, if any, for this store instruction. */ | |
6565 | short off; | |
6566 | /* Alignment required by this store instruction. */ | |
6567 | int align_to; | |
6568 | /* True for register offsets. */ | |
6569 | int register_offset; | |
6570 | }; | |
6571 | ||
6572 | /* Comparison function used by qsort. */ | |
6573 | ||
6574 | static int | |
6575 | fix_24k_sort (const void *a, const void *b) | |
6576 | { | |
6577 | const struct fix_24k_store_info *pos1 = a; | |
6578 | const struct fix_24k_store_info *pos2 = b; | |
6579 | ||
6580 | return (pos1->off - pos2->off); | |
6581 | } | |
6582 | ||
6583 | /* INSN is a store instruction. Try to record the store information | |
6584 | in STINFO. Return false if the information isn't known. */ | |
6585 | ||
6586 | static bfd_boolean | |
6587 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6588 | const struct mips_cl_insn *insn) |
15be625d CM |
6589 | { |
6590 | /* The instruction must have a known offset. */ | |
6591 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6592 | return FALSE; | |
6593 | ||
6594 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6595 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6596 | return TRUE; | |
6597 | } | |
6598 | ||
932d1a1b RS |
6599 | /* Return the number of nops that would be needed to work around the 24k |
6600 | "lost data on stores during refill" errata if instruction INSN | |
6601 | immediately followed the 2 instructions described by HIST. | |
6602 | Ignore hazards that are contained within the first IGNORE | |
6603 | instructions of HIST. | |
6604 | ||
6605 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6606 | for the data cache refills and store data. The following describes | |
6607 | the scenario where the store data could be lost. | |
6608 | ||
6609 | * A data cache miss, due to either a load or a store, causing fill | |
6610 | data to be supplied by the memory subsystem | |
6611 | * The first three doublewords of fill data are returned and written | |
6612 | into the cache | |
6613 | * A sequence of four stores occurs in consecutive cycles around the | |
6614 | final doubleword of the fill: | |
6615 | * Store A | |
6616 | * Store B | |
6617 | * Store C | |
6618 | * Zero, One or more instructions | |
6619 | * Store D | |
6620 | ||
6621 | The four stores A-D must be to different doublewords of the line that | |
6622 | is being filled. The fourth instruction in the sequence above permits | |
6623 | the fill of the final doubleword to be transferred from the FSB into | |
6624 | the cache. In the sequence above, the stores may be either integer | |
6625 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6626 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6627 | different doublewords on the line. If the floating point unit is | |
6628 | running in 1:2 mode, it is not possible to create the sequence above | |
6629 | using only floating point store instructions. | |
15be625d CM |
6630 | |
6631 | In this case, the cache line being filled is incorrectly marked | |
6632 | invalid, thereby losing the data from any store to the line that | |
6633 | occurs between the original miss and the completion of the five | |
6634 | cycle sequence shown above. | |
6635 | ||
932d1a1b | 6636 | The workarounds are: |
15be625d | 6637 | |
932d1a1b RS |
6638 | * Run the data cache in write-through mode. |
6639 | * Insert a non-store instruction between | |
6640 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6641 | |
15be625d | 6642 | static int |
932d1a1b | 6643 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6644 | const struct mips_cl_insn *insn) |
6645 | { | |
6646 | struct fix_24k_store_info pos[3]; | |
6647 | int align, i, base_offset; | |
6648 | ||
932d1a1b RS |
6649 | if (ignore >= 2) |
6650 | return 0; | |
6651 | ||
ab9794cf RS |
6652 | /* If the previous instruction wasn't a store, there's nothing to |
6653 | worry about. */ | |
15be625d CM |
6654 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6655 | return 0; | |
6656 | ||
ab9794cf RS |
6657 | /* If the instructions after the previous one are unknown, we have |
6658 | to assume the worst. */ | |
6659 | if (!insn) | |
15be625d CM |
6660 | return 1; |
6661 | ||
ab9794cf RS |
6662 | /* Check whether we are dealing with three consecutive stores. */ |
6663 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6664 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6665 | return 0; |
6666 | ||
6667 | /* If we don't know the relationship between the store addresses, | |
6668 | assume the worst. */ | |
ab9794cf | 6669 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6670 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6671 | return 1; | |
6672 | ||
6673 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6674 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6675 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6676 | return 1; | |
6677 | ||
6678 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6679 | ||
6680 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6681 | X bytes and such that the base register + X is known to be aligned | |
6682 | to align bytes. */ | |
6683 | ||
6684 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6685 | align = 8; | |
6686 | else | |
6687 | { | |
6688 | align = pos[0].align_to; | |
6689 | base_offset = pos[0].off; | |
6690 | for (i = 1; i < 3; i++) | |
6691 | if (align < pos[i].align_to) | |
6692 | { | |
6693 | align = pos[i].align_to; | |
6694 | base_offset = pos[i].off; | |
6695 | } | |
6696 | for (i = 0; i < 3; i++) | |
6697 | pos[i].off -= base_offset; | |
6698 | } | |
6699 | ||
6700 | pos[0].off &= ~align + 1; | |
6701 | pos[1].off &= ~align + 1; | |
6702 | pos[2].off &= ~align + 1; | |
6703 | ||
6704 | /* If any two stores write to the same chunk, they also write to the | |
6705 | same doubleword. The offsets are still sorted at this point. */ | |
6706 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6707 | return 0; | |
6708 | ||
6709 | /* A range of at least 9 bytes is needed for the stores to be in | |
6710 | non-overlapping doublewords. */ | |
6711 | if (pos[2].off - pos[0].off <= 8) | |
6712 | return 0; | |
6713 | ||
6714 | if (pos[2].off - pos[1].off >= 24 | |
6715 | || pos[1].off - pos[0].off >= 24 | |
6716 | || pos[2].off - pos[0].off >= 32) | |
6717 | return 0; | |
6718 | ||
6719 | return 1; | |
6720 | } | |
6721 | ||
71400594 | 6722 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6723 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6724 | where HIST[0] is the most recent instruction. Ignore hazards |
6725 | between INSN and the first IGNORE instructions in HIST. | |
6726 | ||
6727 | If INSN is null, return the worse-case number of nops for any | |
6728 | instruction. */ | |
bdaaa2e1 | 6729 | |
71400594 | 6730 | static int |
932d1a1b | 6731 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6732 | const struct mips_cl_insn *insn) |
6733 | { | |
6734 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6735 | |
71400594 | 6736 | nops = 0; |
932d1a1b | 6737 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6738 | { |
91d6fa6a | 6739 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6740 | if (tmp_nops > nops) |
6741 | nops = tmp_nops; | |
6742 | } | |
7d8e00cf | 6743 | |
df58fc94 | 6744 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6745 | { |
932d1a1b | 6746 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6747 | if (tmp_nops > nops) |
6748 | nops = tmp_nops; | |
6749 | } | |
6750 | ||
df58fc94 | 6751 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6752 | { |
932d1a1b | 6753 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6754 | if (tmp_nops > nops) |
6755 | nops = tmp_nops; | |
6756 | } | |
6757 | ||
71400594 RS |
6758 | return nops; |
6759 | } | |
252b5132 | 6760 | |
71400594 | 6761 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6762 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6763 | would be needed after the extended sequence, ignoring hazards |
6764 | in the first IGNORE instructions. */ | |
252b5132 | 6765 | |
71400594 | 6766 | static int |
932d1a1b RS |
6767 | nops_for_sequence (int num_insns, int ignore, |
6768 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6769 | { |
6770 | va_list args; | |
6771 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6772 | struct mips_cl_insn *cursor; | |
6773 | int nops; | |
6774 | ||
91d6fa6a | 6775 | va_start (args, hist); |
71400594 | 6776 | cursor = buffer + num_insns; |
91d6fa6a | 6777 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6778 | while (cursor > buffer) |
6779 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6780 | ||
932d1a1b | 6781 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6782 | va_end (args); |
6783 | return nops; | |
6784 | } | |
252b5132 | 6785 | |
71400594 RS |
6786 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6787 | worst-case delay for the branch target. */ | |
252b5132 | 6788 | |
71400594 | 6789 | static int |
932d1a1b | 6790 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6791 | const struct mips_cl_insn *insn) |
6792 | { | |
6793 | int nops, tmp_nops; | |
60b63b72 | 6794 | |
932d1a1b | 6795 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6796 | if (delayed_branch_p (insn)) |
71400594 | 6797 | { |
932d1a1b | 6798 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6799 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6800 | if (tmp_nops > nops) |
6801 | nops = tmp_nops; | |
6802 | } | |
11625dd8 | 6803 | else if (compact_branch_p (insn)) |
71400594 | 6804 | { |
932d1a1b | 6805 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6806 | if (tmp_nops > nops) |
6807 | nops = tmp_nops; | |
6808 | } | |
6809 | return nops; | |
6810 | } | |
6811 | ||
c67a084a NC |
6812 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6813 | ||
6814 | static void | |
6815 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6816 | { | |
df58fc94 | 6817 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6818 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6819 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6820 | } | |
6821 | ||
6822 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6823 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6824 | ||
6825 | static void | |
6826 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6827 | { | |
df58fc94 | 6828 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6829 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6830 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6831 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6832 | { | |
6833 | int sreg; | |
6834 | expressionS ep; | |
6835 | ||
6836 | if (! mips_opts.at) | |
6837 | return; | |
6838 | ||
df58fc94 | 6839 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6840 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6841 | return; | |
6842 | ||
6843 | ep.X_op = O_constant; | |
6844 | ep.X_add_number = 0xcfff0000; | |
6845 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6846 | ep.X_add_number = 0xffff; | |
6847 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6848 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6849 | } | |
6850 | } | |
6851 | ||
6852 | static void | |
6853 | fix_loongson2f (struct mips_cl_insn * ip) | |
6854 | { | |
6855 | if (mips_fix_loongson2f_nop) | |
6856 | fix_loongson2f_nop (ip); | |
6857 | ||
6858 | if (mips_fix_loongson2f_jump) | |
6859 | fix_loongson2f_jump (ip); | |
6860 | } | |
6861 | ||
a4e06468 RS |
6862 | /* IP is a branch that has a delay slot, and we need to fill it |
6863 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6864 | with the previous instruction. |
6865 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6866 | RELOC_TYPE. */ | |
a4e06468 RS |
6867 | |
6868 | static bfd_boolean | |
e407c74b | 6869 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6870 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6871 | { |
2b0c8b40 | 6872 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6873 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6874 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6875 | |
6876 | /* -O2 and above is required for this optimization. */ | |
6877 | if (mips_optimize < 2) | |
6878 | return FALSE; | |
6879 | ||
6880 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6881 | if (mips_opts.nomove) | |
6882 | return FALSE; | |
6883 | ||
6884 | /* We can't swap if the previous instruction's position is fixed. */ | |
6885 | if (history[0].fixed_p) | |
6886 | return FALSE; | |
6887 | ||
6888 | /* If the previous previous insn was in a .set noreorder, we can't | |
6889 | swap. Actually, the MIPS assembler will swap in this situation. | |
6890 | However, gcc configured -with-gnu-as will generate code like | |
6891 | ||
6892 | .set noreorder | |
6893 | lw $4,XXX | |
6894 | .set reorder | |
6895 | INSN | |
6896 | bne $4,$0,foo | |
6897 | ||
6898 | in which we can not swap the bne and INSN. If gcc is not configured | |
6899 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6900 | if (history[1].noreorder_p) | |
6901 | return FALSE; | |
6902 | ||
87333bb7 MR |
6903 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6904 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6905 | if (mips_opts.mips16 && history[0].fixp[0]) |
6906 | return FALSE; | |
6907 | ||
6908 | /* If the branch is itself the target of a branch, we can not swap. | |
6909 | We cheat on this; all we check for is whether there is a label on | |
6910 | this instruction. If there are any branches to anything other than | |
6911 | a label, users must use .set noreorder. */ | |
6912 | if (seg_info (now_seg)->label_list) | |
6913 | return FALSE; | |
6914 | ||
6915 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6916 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6917 | MIPS16 code, which uses variant frags for different purposes. */ |
6918 | if (!mips_opts.mips16 | |
a4e06468 RS |
6919 | && history[0].frag |
6920 | && history[0].frag->fr_type == rs_machine_dependent) | |
6921 | return FALSE; | |
6922 | ||
bcd530a7 RS |
6923 | /* We do not swap with instructions that cannot architecturally |
6924 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6925 | also refrain from swapping with a trap instruction, since it | |
6926 | complicates trap handlers to have the trap instruction be in | |
6927 | a delay slot. */ | |
a4e06468 | 6928 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6929 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6930 | return FALSE; |
6931 | ||
6932 | /* Check for conflicts between the branch and the instructions | |
6933 | before the candidate delay slot. */ | |
6934 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6935 | return FALSE; | |
6936 | ||
6937 | /* Check for conflicts between the swapped sequence and the | |
6938 | target of the branch. */ | |
6939 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6940 | return FALSE; | |
6941 | ||
6942 | /* If the branch reads a register that the previous | |
6943 | instruction sets, we can not swap. */ | |
6944 | gpr_read = gpr_read_mask (ip); | |
6945 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6946 | if (gpr_read & prev_gpr_write) | |
6947 | return FALSE; | |
6948 | ||
9d5de888 CF |
6949 | fpr_read = fpr_read_mask (ip); |
6950 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6951 | if (fpr_read & prev_fpr_write) | |
6952 | return FALSE; | |
6953 | ||
a4e06468 RS |
6954 | /* If the branch writes a register that the previous |
6955 | instruction sets, we can not swap. */ | |
6956 | gpr_write = gpr_write_mask (ip); | |
6957 | if (gpr_write & prev_gpr_write) | |
6958 | return FALSE; | |
6959 | ||
6960 | /* If the branch writes a register that the previous | |
6961 | instruction reads, we can not swap. */ | |
6962 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6963 | if (gpr_write & prev_gpr_read) | |
6964 | return FALSE; | |
6965 | ||
6966 | /* If one instruction sets a condition code and the | |
6967 | other one uses a condition code, we can not swap. */ | |
6968 | pinfo = ip->insn_mo->pinfo; | |
6969 | if ((pinfo & INSN_READ_COND_CODE) | |
6970 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6971 | return FALSE; | |
6972 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6973 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6974 | return FALSE; | |
6975 | ||
6976 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6977 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6978 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6979 | return FALSE; |
a4e06468 | 6980 | |
df58fc94 RS |
6981 | /* If the previous instruction has an incorrect size for a fixed |
6982 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6983 | pinfo2 = ip->insn_mo->pinfo2; |
6984 | if (mips_opts.micromips | |
6985 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6986 | && insn_length (history) != 2) | |
6987 | return FALSE; | |
6988 | if (mips_opts.micromips | |
6989 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6990 | && insn_length (history) != 4) | |
6991 | return FALSE; | |
6992 | ||
33d64ca5 FN |
6993 | /* On the R5900 short loops need to be fixed by inserting a NOP in the |
6994 | branch delay slot. | |
6995 | ||
6996 | The short loop bug under certain conditions causes loops to execute | |
6997 | only once or twice. We must ensure that the assembler never | |
6998 | generates loops that satisfy all of the following conditions: | |
6999 | ||
7000 | - a loop consists of less than or equal to six instructions | |
7001 | (including the branch delay slot); | |
7002 | - a loop contains only one conditional branch instruction at the end | |
7003 | of the loop; | |
7004 | - a loop does not contain any other branch or jump instructions; | |
7005 | - a branch delay slot of the loop is not NOP (EE 2.9 or later). | |
7006 | ||
7007 | We need to do this because of a hardware bug in the R5900 chip. */ | |
27c634e0 | 7008 | if (mips_fix_r5900 |
e407c74b NC |
7009 | /* Check if instruction has a parameter, ignore "j $31". */ |
7010 | && (address_expr != NULL) | |
7011 | /* Parameter must be 16 bit. */ | |
7012 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
7013 | /* Branch to same segment. */ | |
41065f5e | 7014 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 7015 | /* Branch to same code fragment. */ |
41065f5e | 7016 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 7017 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 7018 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
7019 | /* Check if branch is really conditional. */ |
7020 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
7021 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
7022 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
7023 | { | |
7024 | int distance; | |
33d64ca5 FN |
7025 | /* Check if loop is shorter than or equal to 6 instructions |
7026 | including branch and delay slot. */ | |
41065f5e | 7027 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
7028 | if (distance <= 20) |
7029 | { | |
7030 | int i; | |
7031 | int rv; | |
7032 | ||
7033 | rv = FALSE; | |
7034 | /* When the loop includes branches or jumps, | |
7035 | it is not a short loop. */ | |
7036 | for (i = 0; i < (distance / 4); i++) | |
7037 | { | |
7038 | if ((history[i].cleared_p) | |
41065f5e | 7039 | || delayed_branch_p (&history[i])) |
e407c74b NC |
7040 | { |
7041 | rv = TRUE; | |
7042 | break; | |
7043 | } | |
7044 | } | |
535b785f | 7045 | if (!rv) |
e407c74b NC |
7046 | { |
7047 | /* Insert nop after branch to fix short loop. */ | |
7048 | return FALSE; | |
7049 | } | |
7050 | } | |
7051 | } | |
7052 | ||
a4e06468 RS |
7053 | return TRUE; |
7054 | } | |
7055 | ||
e407c74b NC |
7056 | /* Decide how we should add IP to the instruction stream. |
7057 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7058 | RELOC_TYPE. */ | |
a4e06468 RS |
7059 | |
7060 | static enum append_method | |
e407c74b | 7061 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7062 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7063 | { |
a4e06468 RS |
7064 | /* The relaxed version of a macro sequence must be inherently |
7065 | hazard-free. */ | |
7066 | if (mips_relax.sequence == 2) | |
7067 | return APPEND_ADD; | |
7068 | ||
3b821a28 | 7069 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7070 | if (mips_opts.noreorder) |
7071 | return APPEND_ADD; | |
7072 | ||
7073 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7074 | if (delayed_branch_p (ip)) |
a4e06468 | 7075 | { |
e407c74b NC |
7076 | if (!branch_likely_p (ip) |
7077 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7078 | return APPEND_SWAP; |
7079 | ||
7080 | if (mips_opts.mips16 | |
7081 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7082 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7083 | return APPEND_ADD_COMPACT; |
7084 | ||
7bd374a4 MR |
7085 | if (mips_opts.micromips |
7086 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7087 | || (!forced_insn_length | |
7088 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7089 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7090 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7091 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7092 | return APPEND_ADD_COMPACT; | |
7093 | ||
a4e06468 RS |
7094 | return APPEND_ADD_WITH_NOP; |
7095 | } | |
7096 | ||
a4e06468 RS |
7097 | return APPEND_ADD; |
7098 | } | |
7099 | ||
7bd374a4 MR |
7100 | /* IP is an instruction whose opcode we have just changed, END points |
7101 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7102 | new opcode's definition. */ | |
ceb94aa5 RS |
7103 | |
7104 | static void | |
7bd374a4 | 7105 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7106 | { |
7bd374a4 | 7107 | const struct mips_opcode *mo; |
ceb94aa5 | 7108 | |
ceb94aa5 | 7109 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7110 | if (mo->pinfo != INSN_MACRO |
7111 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7112 | { |
7113 | ip->insn_mo = mo; | |
7114 | return; | |
7115 | } | |
7116 | abort (); | |
7117 | } | |
7118 | ||
7bd374a4 MR |
7119 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7120 | Point IP->insn_mo to the new opcode's definition. */ | |
7121 | ||
7122 | static void | |
7123 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7124 | { | |
7125 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7126 | } | |
7127 | ||
7128 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7129 | Point IP->insn_mo to the new opcode's definition. */ | |
7130 | ||
7131 | static void | |
7132 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7133 | { | |
7134 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7135 | } | |
7136 | ||
df58fc94 RS |
7137 | /* For microMIPS macros, we need to generate a local number label |
7138 | as the target of branches. */ | |
7139 | #define MICROMIPS_LABEL_CHAR '\037' | |
7140 | static unsigned long micromips_target_label; | |
7141 | static char micromips_target_name[32]; | |
7142 | ||
7143 | static char * | |
7144 | micromips_label_name (void) | |
7145 | { | |
7146 | char *p = micromips_target_name; | |
7147 | char symbol_name_temporary[24]; | |
7148 | unsigned long l; | |
7149 | int i; | |
7150 | ||
7151 | if (*p) | |
7152 | return p; | |
7153 | ||
7154 | i = 0; | |
7155 | l = micromips_target_label; | |
7156 | #ifdef LOCAL_LABEL_PREFIX | |
7157 | *p++ = LOCAL_LABEL_PREFIX; | |
7158 | #endif | |
7159 | *p++ = 'L'; | |
7160 | *p++ = MICROMIPS_LABEL_CHAR; | |
7161 | do | |
7162 | { | |
7163 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7164 | l /= 10; | |
7165 | } | |
7166 | while (l != 0); | |
7167 | while (i > 0) | |
7168 | *p++ = symbol_name_temporary[--i]; | |
7169 | *p = '\0'; | |
7170 | ||
7171 | return micromips_target_name; | |
7172 | } | |
7173 | ||
7174 | static void | |
7175 | micromips_label_expr (expressionS *label_expr) | |
7176 | { | |
7177 | label_expr->X_op = O_symbol; | |
7178 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7179 | label_expr->X_add_number = 0; | |
7180 | } | |
7181 | ||
7182 | static void | |
7183 | micromips_label_inc (void) | |
7184 | { | |
7185 | micromips_target_label++; | |
7186 | *micromips_target_name = '\0'; | |
7187 | } | |
7188 | ||
7189 | static void | |
7190 | micromips_add_label (void) | |
7191 | { | |
7192 | symbolS *s; | |
7193 | ||
7194 | s = colon (micromips_label_name ()); | |
7195 | micromips_label_inc (); | |
f3ded42a | 7196 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7197 | } |
7198 | ||
7199 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7200 | corresponding to the requested one if any. Otherwise return | |
7201 | the reloc unchanged. */ | |
7202 | ||
7203 | static bfd_reloc_code_real_type | |
7204 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7205 | { | |
7206 | static const bfd_reloc_code_real_type relocs[][2] = | |
7207 | { | |
7208 | /* Keep sorted incrementally by the left-hand key. */ | |
7209 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7210 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7211 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7212 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7213 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7214 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7215 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7216 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7217 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7218 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7219 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7220 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7221 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7222 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7223 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7224 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7225 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7226 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7227 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7228 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7229 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7230 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7231 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7232 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7233 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7234 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7235 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7236 | }; | |
7237 | bfd_reloc_code_real_type r; | |
7238 | size_t i; | |
7239 | ||
7240 | if (!mips_opts.micromips) | |
7241 | return reloc; | |
7242 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7243 | { | |
7244 | r = relocs[i][0]; | |
7245 | if (r > reloc) | |
7246 | return reloc; | |
7247 | if (r == reloc) | |
7248 | return relocs[i][1]; | |
7249 | } | |
7250 | return reloc; | |
7251 | } | |
7252 | ||
b886a2ab RS |
7253 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7254 | Return true on success, storing the resolved value in RESULT. */ | |
7255 | ||
7256 | static bfd_boolean | |
7257 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7258 | offsetT *result) | |
7259 | { | |
7260 | switch (reloc) | |
7261 | { | |
7262 | case BFD_RELOC_MIPS_HIGHEST: | |
7263 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7264 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7265 | return TRUE; | |
7266 | ||
7267 | case BFD_RELOC_MIPS_HIGHER: | |
7268 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7269 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7270 | return TRUE; | |
7271 | ||
7272 | case BFD_RELOC_HI16_S: | |
41947d9e | 7273 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7274 | case BFD_RELOC_MICROMIPS_HI16_S: |
7275 | case BFD_RELOC_MIPS16_HI16_S: | |
7276 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7277 | return TRUE; | |
7278 | ||
7279 | case BFD_RELOC_HI16: | |
7280 | case BFD_RELOC_MICROMIPS_HI16: | |
7281 | case BFD_RELOC_MIPS16_HI16: | |
7282 | *result = (operand >> 16) & 0xffff; | |
7283 | return TRUE; | |
7284 | ||
7285 | case BFD_RELOC_LO16: | |
41947d9e | 7286 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7287 | case BFD_RELOC_MICROMIPS_LO16: |
7288 | case BFD_RELOC_MIPS16_LO16: | |
7289 | *result = operand & 0xffff; | |
7290 | return TRUE; | |
7291 | ||
7292 | case BFD_RELOC_UNUSED: | |
7293 | *result = operand; | |
7294 | return TRUE; | |
7295 | ||
7296 | default: | |
7297 | return FALSE; | |
7298 | } | |
7299 | } | |
7300 | ||
71400594 RS |
7301 | /* Output an instruction. IP is the instruction information. |
7302 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7303 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7304 | a macro expansion. */ | |
71400594 RS |
7305 | |
7306 | static void | |
7307 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7308 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7309 | { |
14fe068b | 7310 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7311 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7312 | enum append_method method; |
2309ddf2 | 7313 | bfd_boolean relax32; |
2b0c8b40 | 7314 | int branch_disp; |
71400594 | 7315 | |
2309ddf2 | 7316 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7317 | fix_loongson2f (ip); |
7318 | ||
738f4d98 | 7319 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7320 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7321 | |
df58fc94 | 7322 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7323 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7324 | |
7bd374a4 MR |
7325 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7326 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7327 | if (mips_opts.micromips |
7328 | && !expansionp | |
7bd374a4 MR |
7329 | && !(history[0].frag |
7330 | && history[0].frag->fr_type == rs_machine_dependent | |
7331 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7332 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7333 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7334 | && micromips_insn_length (ip->insn_mo) != 2) | |
7335 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7336 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7337 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7338 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7339 | |
15be625d CM |
7340 | if (address_expr == NULL) |
7341 | ip->complete_p = 1; | |
b886a2ab RS |
7342 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7343 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7344 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7345 | && address_expr->X_op == O_constant) |
7346 | { | |
15be625d CM |
7347 | switch (*reloc_type) |
7348 | { | |
15be625d | 7349 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7350 | { |
7351 | int shift; | |
7352 | ||
17c6c9d9 MR |
7353 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7354 | shift = (mips_opts.micromips | |
7355 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7356 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7357 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7358 | (unsigned long) address_expr->X_add_number); | |
7359 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7360 | & 0x3ffffff); | |
335574df | 7361 | ip->complete_p = 1; |
df58fc94 | 7362 | } |
15be625d CM |
7363 | break; |
7364 | ||
7365 | case BFD_RELOC_MIPS16_JMP: | |
7366 | if ((address_expr->X_add_number & 3) != 0) | |
7367 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7368 | (unsigned long) address_expr->X_add_number); | |
7369 | ip->insn_opcode |= | |
7370 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7371 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7372 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7373 | ip->complete_p = 1; |
15be625d CM |
7374 | break; |
7375 | ||
7376 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7377 | { |
7378 | int shift; | |
7379 | ||
7380 | shift = mips_opts.micromips ? 1 : 2; | |
7381 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7382 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7383 | (unsigned long) address_expr->X_add_number); | |
7384 | if (!mips_relax_branch) | |
7385 | { | |
7386 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7387 | & ~((1 << (shift + 16)) - 1)) | |
7388 | as_bad (_("branch address range overflow (0x%lx)"), | |
7389 | (unsigned long) address_expr->X_add_number); | |
7390 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7391 | & 0xffff); | |
7392 | } | |
df58fc94 | 7393 | } |
15be625d CM |
7394 | break; |
7395 | ||
7361da2c AB |
7396 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7397 | { | |
7398 | int shift; | |
7399 | ||
7400 | shift = 2; | |
7401 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7402 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7403 | (unsigned long) address_expr->X_add_number); | |
7404 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7405 | & ~((1 << (shift + 21)) - 1)) | |
7406 | as_bad (_("branch address range overflow (0x%lx)"), | |
7407 | (unsigned long) address_expr->X_add_number); | |
7408 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7409 | & 0x1fffff); | |
7410 | } | |
7411 | break; | |
7412 | ||
7413 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7414 | { | |
7415 | int shift; | |
7416 | ||
7417 | shift = 2; | |
7418 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7419 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7420 | (unsigned long) address_expr->X_add_number); | |
7421 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7422 | & ~((1 << (shift + 26)) - 1)) | |
7423 | as_bad (_("branch address range overflow (0x%lx)"), | |
7424 | (unsigned long) address_expr->X_add_number); | |
7425 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7426 | & 0x3ffffff); | |
7427 | } | |
7428 | break; | |
7429 | ||
15be625d | 7430 | default: |
b886a2ab RS |
7431 | { |
7432 | offsetT value; | |
7433 | ||
7434 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7435 | &value)) | |
7436 | { | |
7437 | ip->insn_opcode |= value & 0xffff; | |
7438 | ip->complete_p = 1; | |
7439 | } | |
7440 | } | |
7441 | break; | |
7442 | } | |
15be625d CM |
7443 | } |
7444 | ||
71400594 RS |
7445 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7446 | { | |
7447 | /* There are a lot of optimizations we could do that we don't. | |
7448 | In particular, we do not, in general, reorder instructions. | |
7449 | If you use gcc with optimization, it will reorder | |
7450 | instructions and generally do much more optimization then we | |
7451 | do here; repeating all that work in the assembler would only | |
7452 | benefit hand written assembly code, and does not seem worth | |
7453 | it. */ | |
7454 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7455 | ? nops_for_insn (0, history, NULL) |
7456 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7457 | if (nops > 0) |
252b5132 RH |
7458 | { |
7459 | fragS *old_frag; | |
7460 | unsigned long old_frag_offset; | |
7461 | int i; | |
252b5132 RH |
7462 | |
7463 | old_frag = frag_now; | |
7464 | old_frag_offset = frag_now_fix (); | |
7465 | ||
7466 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7467 | add_fixed_insn (NOP_INSN); |
7468 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7469 | |
7470 | if (listing) | |
7471 | { | |
7472 | listing_prev_line (); | |
7473 | /* We may be at the start of a variant frag. In case we | |
7474 | are, make sure there is enough space for the frag | |
7475 | after the frags created by listing_prev_line. The | |
7476 | argument to frag_grow here must be at least as large | |
7477 | as the argument to all other calls to frag_grow in | |
7478 | this file. We don't have to worry about being in the | |
7479 | middle of a variant frag, because the variants insert | |
7480 | all needed nop instructions themselves. */ | |
7481 | frag_grow (40); | |
7482 | } | |
7483 | ||
462427c4 | 7484 | mips_move_text_labels (); |
252b5132 RH |
7485 | |
7486 | #ifndef NO_ECOFF_DEBUGGING | |
7487 | if (ECOFF_DEBUGGING) | |
7488 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7489 | #endif | |
7490 | } | |
71400594 RS |
7491 | } |
7492 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7493 | { | |
932d1a1b RS |
7494 | int nops; |
7495 | ||
7496 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7497 | ignoring hazards generated by the first prev_nop_frag_since | |
7498 | instructions. */ | |
7499 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7500 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7501 | |
71400594 RS |
7502 | /* Enforce NOPS as a minimum. */ |
7503 | if (nops > prev_nop_frag_required) | |
7504 | prev_nop_frag_required = nops; | |
252b5132 | 7505 | |
71400594 RS |
7506 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7507 | { | |
7508 | /* Settle for the current number of nops. Update the history | |
7509 | accordingly (for the benefit of any future .set reorder code). */ | |
7510 | prev_nop_frag = NULL; | |
7511 | insert_into_history (prev_nop_frag_since, | |
7512 | prev_nop_frag_holds, NOP_INSN); | |
7513 | } | |
7514 | else | |
7515 | { | |
7516 | /* Allow this instruction to replace one of the nops that was | |
7517 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7518 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7519 | prev_nop_frag_holds--; |
7520 | prev_nop_frag_since++; | |
252b5132 RH |
7521 | } |
7522 | } | |
7523 | ||
e407c74b | 7524 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7525 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7526 | |
e410add4 RS |
7527 | dwarf2_emit_insn (0); |
7528 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7529 | so "move" the instruction address accordingly. | |
7530 | ||
7531 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7532 | entries. If this instruction is a branch that we are going to swap | |
7533 | with the previous instruction, the two instructions should be | |
7534 | treated as a unit, and the debug information for both instructions | |
7535 | should refer to the start of the branch sequence. Using the | |
7536 | current position is certainly wrong when swapping a 32-bit branch | |
7537 | and a 16-bit delay slot, since the current position would then be | |
7538 | in the middle of a branch. */ | |
7539 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7540 | |
df58fc94 RS |
7541 | relax32 = (mips_relax_branch |
7542 | /* Don't try branch relaxation within .set nomacro, or within | |
7543 | .set noat if we use $at for PIC computations. If it turns | |
7544 | out that the branch was out-of-range, we'll get an error. */ | |
7545 | && !mips_opts.warn_about_macros | |
7546 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7547 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7548 | as they have no complementing branches. */ | |
7549 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7550 | |
7551 | if (!HAVE_CODE_COMPRESSION | |
7552 | && address_expr | |
7553 | && relax32 | |
0b25d3e6 | 7554 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7555 | && delayed_branch_p (ip)) |
4a6a3df4 | 7556 | { |
895921c9 | 7557 | relaxed_branch = TRUE; |
1e915849 RS |
7558 | add_relaxed_insn (ip, (relaxed_branch_length |
7559 | (NULL, NULL, | |
11625dd8 RS |
7560 | uncond_branch_p (ip) ? -1 |
7561 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7562 | : 0)), 4, |
7563 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7564 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7565 | uncond_branch_p (ip), |
7566 | branch_likely_p (ip), | |
1e915849 RS |
7567 | pinfo & INSN_WRITE_GPR_31, |
7568 | 0), | |
7569 | address_expr->X_add_symbol, | |
7570 | address_expr->X_add_number); | |
4a6a3df4 AO |
7571 | *reloc_type = BFD_RELOC_UNUSED; |
7572 | } | |
df58fc94 RS |
7573 | else if (mips_opts.micromips |
7574 | && address_expr | |
7575 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7576 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7577 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7578 | /* Don't try branch relaxation when users specify | |
7579 | 16-bit/32-bit instructions. */ | |
7580 | && !forced_insn_length) | |
df58fc94 | 7581 | { |
7bd374a4 MR |
7582 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7583 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7584 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7585 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7586 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7587 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7588 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7589 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7590 | |
7591 | gas_assert (address_expr != NULL); | |
7592 | gas_assert (!mips_relax.sequence); | |
7593 | ||
2b0c8b40 | 7594 | relaxed_branch = TRUE; |
7bd374a4 MR |
7595 | if (nods) |
7596 | method = APPEND_ADD; | |
7597 | if (relax32) | |
7598 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7599 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7600 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7601 | mips_pic != NO_PIC, |
7bd374a4 | 7602 | uncond, compact, al, nods, |
40209cad | 7603 | relax32, 0, 0), |
df58fc94 RS |
7604 | address_expr->X_add_symbol, |
7605 | address_expr->X_add_number); | |
7606 | *reloc_type = BFD_RELOC_UNUSED; | |
7607 | } | |
7608 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7609 | { |
7fd53920 MR |
7610 | bfd_boolean require_unextended; |
7611 | bfd_boolean require_extended; | |
88a7ef16 MR |
7612 | symbolS *symbol; |
7613 | offsetT offset; | |
7614 | ||
7fd53920 MR |
7615 | if (forced_insn_length != 0) |
7616 | { | |
7617 | require_unextended = forced_insn_length == 2; | |
7618 | require_extended = forced_insn_length == 4; | |
7619 | } | |
7620 | else | |
7621 | { | |
7622 | require_unextended = (mips_opts.noautoextend | |
7623 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7624 | require_extended = 0; | |
7625 | } | |
7626 | ||
252b5132 | 7627 | /* We need to set up a variant frag. */ |
df58fc94 | 7628 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7629 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7630 | symbol created by `make_expr_symbol' may not get a necessary | |
7631 | external relocation produced. */ | |
7632 | if (address_expr->X_op == O_symbol) | |
7633 | { | |
7634 | symbol = address_expr->X_add_symbol; | |
7635 | offset = address_expr->X_add_number; | |
7636 | } | |
7637 | else | |
7638 | { | |
7639 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7640 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7641 | offset = 0; |
7642 | } | |
8507b6e7 | 7643 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7644 | RELAX_MIPS16_ENCODE |
7645 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7646 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7647 | mips_pic != NO_PIC, |
7648 | HAVE_32BIT_SYMBOLS, | |
7649 | mips_opts.warn_about_macros, | |
7fd53920 | 7650 | require_unextended, require_extended, |
11625dd8 | 7651 | delayed_branch_p (&history[0]), |
1e915849 | 7652 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7653 | symbol, offset); |
252b5132 | 7654 | } |
5c04167a | 7655 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7656 | { |
11625dd8 | 7657 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7658 | /* Make sure there is enough room to swap this instruction with |
7659 | a following jump instruction. */ | |
7660 | frag_grow (6); | |
1e915849 | 7661 | add_fixed_insn (ip); |
252b5132 RH |
7662 | } |
7663 | else | |
7664 | { | |
7665 | if (mips_opts.mips16 | |
7666 | && mips_opts.noreorder | |
11625dd8 | 7667 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7668 | as_warn (_("extended instruction in delay slot")); |
7669 | ||
4d7206a2 RS |
7670 | if (mips_relax.sequence) |
7671 | { | |
7672 | /* If we've reached the end of this frag, turn it into a variant | |
7673 | frag and record the information for the instructions we've | |
7674 | written so far. */ | |
7675 | if (frag_room () < 4) | |
7676 | relax_close_frag (); | |
df58fc94 | 7677 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7678 | } |
7679 | ||
584892a6 | 7680 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7681 | { |
7682 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7683 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7684 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7685 | mips_macro_warning.insns[0]++; | |
7686 | } | |
584892a6 | 7687 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7688 | { |
7689 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7690 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7691 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7692 | mips_macro_warning.insns[1]++; | |
7693 | } | |
584892a6 | 7694 | |
1e915849 RS |
7695 | if (mips_opts.mips16) |
7696 | { | |
7697 | ip->fixed_p = 1; | |
7698 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7699 | } | |
7700 | add_fixed_insn (ip); | |
252b5132 RH |
7701 | } |
7702 | ||
9fe77896 | 7703 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7704 | { |
df58fc94 | 7705 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7706 | reloc_howto_type *howto0; |
9fe77896 RS |
7707 | reloc_howto_type *howto; |
7708 | int i; | |
34ce925e | 7709 | |
df58fc94 RS |
7710 | /* Perform any necessary conversion to microMIPS relocations |
7711 | and find out how many relocations there actually are. */ | |
7712 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7713 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7714 | ||
9fe77896 RS |
7715 | /* In a compound relocation, it is the final (outermost) |
7716 | operator that determines the relocated field. */ | |
2309ddf2 | 7717 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7718 | if (!howto) |
7719 | abort (); | |
2309ddf2 MR |
7720 | |
7721 | if (i > 1) | |
7722 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7723 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7724 | bfd_get_reloc_size (howto), | |
7725 | address_expr, | |
2309ddf2 MR |
7726 | howto0 && howto0->pc_relative, |
7727 | final_type[0]); | |
ce8ad872 MR |
7728 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7729 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7730 | |
7731 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7732 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7733 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7734 | ||
7735 | /* These relocations can have an addend that won't fit in | |
7736 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7737 | if (GPR_SIZE == 64 |
9fe77896 RS |
7738 | && ! howto->partial_inplace |
7739 | && (reloc_type[0] == BFD_RELOC_16 | |
7740 | || reloc_type[0] == BFD_RELOC_32 | |
7741 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7742 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7743 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7744 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7745 | || reloc_type[0] == BFD_RELOC_64 | |
7746 | || reloc_type[0] == BFD_RELOC_CTOR | |
7747 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7748 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7749 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7750 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7751 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7752 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7753 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7754 | || hi16_reloc_p (reloc_type[0]) | |
7755 | || lo16_reloc_p (reloc_type[0]))) | |
7756 | ip->fixp[0]->fx_no_overflow = 1; | |
7757 | ||
ddaf2c41 MR |
7758 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7759 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7760 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7761 | ip->fixp[0]->fx_no_overflow = 1; | |
7762 | ||
9fe77896 RS |
7763 | if (mips_relax.sequence) |
7764 | { | |
7765 | if (mips_relax.first_fixup == 0) | |
7766 | mips_relax.first_fixup = ip->fixp[0]; | |
7767 | } | |
7768 | else if (reloc_needs_lo_p (*reloc_type)) | |
7769 | { | |
7770 | struct mips_hi_fixup *hi_fixup; | |
7771 | ||
7772 | /* Reuse the last entry if it already has a matching %lo. */ | |
7773 | hi_fixup = mips_hi_fixup_list; | |
7774 | if (hi_fixup == 0 | |
7775 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7776 | { |
325801bd | 7777 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7778 | hi_fixup->next = mips_hi_fixup_list; |
7779 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7780 | } |
9fe77896 RS |
7781 | hi_fixup->fixp = ip->fixp[0]; |
7782 | hi_fixup->seg = now_seg; | |
7783 | } | |
252b5132 | 7784 | |
9fe77896 RS |
7785 | /* Add fixups for the second and third relocations, if given. |
7786 | Note that the ABI allows the second relocation to be | |
7787 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7788 | moment we only use RSS_UNDEF, but we could add support | |
7789 | for the others if it ever becomes necessary. */ | |
7790 | for (i = 1; i < 3; i++) | |
7791 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7792 | { | |
7793 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7794 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7795 | FALSE, final_type[i]); |
f6688943 | 7796 | |
9fe77896 RS |
7797 | /* Use fx_tcbit to mark compound relocs. */ |
7798 | ip->fixp[0]->fx_tcbit = 1; | |
7799 | ip->fixp[i]->fx_tcbit = 1; | |
7800 | } | |
252b5132 | 7801 | } |
252b5132 RH |
7802 | |
7803 | /* Update the register mask information. */ | |
4c260379 RS |
7804 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7805 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7806 | |
a4e06468 | 7807 | switch (method) |
252b5132 | 7808 | { |
a4e06468 RS |
7809 | case APPEND_ADD: |
7810 | insert_into_history (0, 1, ip); | |
7811 | break; | |
7812 | ||
7813 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7814 | { |
7815 | struct mips_cl_insn *nop; | |
7816 | ||
7817 | insert_into_history (0, 1, ip); | |
7818 | nop = get_delay_slot_nop (ip); | |
7819 | add_fixed_insn (nop); | |
7820 | insert_into_history (0, 1, nop); | |
7821 | if (mips_relax.sequence) | |
7822 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7823 | } | |
a4e06468 RS |
7824 | break; |
7825 | ||
7826 | case APPEND_ADD_COMPACT: | |
7827 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7828 | if (mips_opts.mips16) |
7829 | { | |
7830 | ip->insn_opcode |= 0x0080; | |
7831 | find_altered_mips16_opcode (ip); | |
7832 | } | |
7833 | /* Convert microMIPS instructions. */ | |
7834 | else if (mips_opts.micromips) | |
7835 | { | |
7836 | /* jr16->jrc */ | |
7837 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7838 | ip->insn_opcode |= 0x0020; | |
7839 | /* b16->bc */ | |
7840 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7841 | ip->insn_opcode = 0x40e00000; | |
7842 | /* beqz16->beqzc, bnez16->bnezc */ | |
7843 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7844 | { | |
7845 | unsigned long regno; | |
7846 | ||
7847 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7848 | regno &= MICROMIPSOP_MASK_MD; | |
7849 | regno = micromips_to_32_reg_d_map[regno]; | |
7850 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7851 | | (regno << MICROMIPSOP_SH_RS) | |
7852 | | 0x40a00000) ^ 0x00400000; | |
7853 | } | |
7854 | /* beqz->beqzc, bnez->bnezc */ | |
7855 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7856 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7857 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7858 | | 0x40a00000) ^ 0x00400000; | |
7859 | /* beq $0->beqzc, bne $0->bnezc */ | |
7860 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7861 | ip->insn_opcode = (((ip->insn_opcode >> | |
7862 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7863 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7864 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7865 | | 0x40a00000) ^ 0x00400000; | |
7866 | else | |
7867 | abort (); | |
7868 | find_altered_micromips_opcode (ip); | |
7869 | } | |
7870 | else | |
7871 | abort (); | |
a4e06468 RS |
7872 | install_insn (ip); |
7873 | insert_into_history (0, 1, ip); | |
7874 | break; | |
7875 | ||
7876 | case APPEND_SWAP: | |
7877 | { | |
7878 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7879 | |
7880 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7881 | { |
7882 | /* Add the delay slot instruction to the end of the | |
7883 | current frag and shrink the fixed part of the | |
7884 | original frag. If the branch occupies the tail of | |
7885 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7886 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7887 | if (delay.frag == ip->frag) |
2b0c8b40 | 7888 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7889 | add_fixed_insn (&delay); |
7890 | } | |
7891 | else | |
7892 | { | |
5e35670b MR |
7893 | /* If this is not a relaxed branch and we are in the |
7894 | same frag, then just swap the instructions. */ | |
7895 | move_insn (ip, delay.frag, delay.where); | |
7896 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7897 | } |
7898 | history[0] = *ip; | |
7899 | delay.fixed_p = 1; | |
7900 | insert_into_history (0, 1, &delay); | |
7901 | } | |
7902 | break; | |
252b5132 RH |
7903 | } |
7904 | ||
13408f1e | 7905 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7906 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7907 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7908 | { |
7909 | unsigned int i; | |
7910 | ||
79850f26 | 7911 | mips_no_prev_insn (); |
13408f1e | 7912 | |
e407c74b | 7913 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7914 | history[i].cleared_p = 1; |
e407c74b NC |
7915 | } |
7916 | ||
df58fc94 RS |
7917 | /* We need to emit a label at the end of branch-likely macros. */ |
7918 | if (emit_branch_likely_macro) | |
7919 | { | |
7920 | emit_branch_likely_macro = FALSE; | |
7921 | micromips_add_label (); | |
7922 | } | |
7923 | ||
252b5132 RH |
7924 | /* We just output an insn, so the next one doesn't have a label. */ |
7925 | mips_clear_insn_labels (); | |
252b5132 RH |
7926 | } |
7927 | ||
e407c74b NC |
7928 | /* Forget that there was any previous instruction or label. |
7929 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7930 | |
7931 | static void | |
7d10b47d | 7932 | mips_no_prev_insn (void) |
252b5132 | 7933 | { |
7d10b47d RS |
7934 | prev_nop_frag = NULL; |
7935 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7936 | mips_clear_insn_labels (); |
7937 | } | |
7938 | ||
7d10b47d RS |
7939 | /* This function must be called before we emit something other than |
7940 | instructions. It is like mips_no_prev_insn except that it inserts | |
7941 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7942 | |
7d10b47d RS |
7943 | void |
7944 | mips_emit_delays (void) | |
252b5132 RH |
7945 | { |
7946 | if (! mips_opts.noreorder) | |
7947 | { | |
932d1a1b | 7948 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7949 | if (nops > 0) |
7950 | { | |
7d10b47d RS |
7951 | while (nops-- > 0) |
7952 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7953 | mips_move_text_labels (); |
7d10b47d RS |
7954 | } |
7955 | } | |
7956 | mips_no_prev_insn (); | |
7957 | } | |
7958 | ||
7959 | /* Start a (possibly nested) noreorder block. */ | |
7960 | ||
7961 | static void | |
7962 | start_noreorder (void) | |
7963 | { | |
7964 | if (mips_opts.noreorder == 0) | |
7965 | { | |
7966 | unsigned int i; | |
7967 | int nops; | |
7968 | ||
7969 | /* None of the instructions before the .set noreorder can be moved. */ | |
7970 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7971 | history[i].fixed_p = 1; | |
7972 | ||
7973 | /* Insert any nops that might be needed between the .set noreorder | |
7974 | block and the previous instructions. We will later remove any | |
7975 | nops that turn out not to be needed. */ | |
932d1a1b | 7976 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7977 | if (nops > 0) |
7978 | { | |
7979 | if (mips_optimize != 0) | |
252b5132 RH |
7980 | { |
7981 | /* Record the frag which holds the nop instructions, so | |
7982 | that we can remove them if we don't need them. */ | |
df58fc94 | 7983 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7984 | prev_nop_frag = frag_now; |
7985 | prev_nop_frag_holds = nops; | |
7986 | prev_nop_frag_required = 0; | |
7987 | prev_nop_frag_since = 0; | |
7988 | } | |
7989 | ||
7990 | for (; nops > 0; --nops) | |
1e915849 | 7991 | add_fixed_insn (NOP_INSN); |
252b5132 | 7992 | |
7d10b47d RS |
7993 | /* Move on to a new frag, so that it is safe to simply |
7994 | decrease the size of prev_nop_frag. */ | |
7995 | frag_wane (frag_now); | |
7996 | frag_new (0); | |
462427c4 | 7997 | mips_move_text_labels (); |
252b5132 | 7998 | } |
df58fc94 | 7999 | mips_mark_labels (); |
7d10b47d | 8000 | mips_clear_insn_labels (); |
252b5132 | 8001 | } |
7d10b47d RS |
8002 | mips_opts.noreorder++; |
8003 | mips_any_noreorder = 1; | |
8004 | } | |
252b5132 | 8005 | |
7d10b47d | 8006 | /* End a nested noreorder block. */ |
252b5132 | 8007 | |
7d10b47d RS |
8008 | static void |
8009 | end_noreorder (void) | |
8010 | { | |
8011 | mips_opts.noreorder--; | |
8012 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
8013 | { | |
8014 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
8015 | handling nop insertion the .set reorder way. */ | |
8016 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 8017 | * NOP_INSN_SIZE); |
7d10b47d RS |
8018 | insert_into_history (prev_nop_frag_since, |
8019 | prev_nop_frag_required, NOP_INSN); | |
8020 | prev_nop_frag = NULL; | |
8021 | } | |
252b5132 RH |
8022 | } |
8023 | ||
97d87491 RS |
8024 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
8025 | higher bits unset. */ | |
8026 | ||
8027 | static void | |
8028 | normalize_constant_expr (expressionS *ex) | |
8029 | { | |
8030 | if (ex->X_op == O_constant | |
8031 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8032 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8033 | - 0x80000000); | |
8034 | } | |
8035 | ||
8036 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
8037 | all higher bits unset. */ | |
8038 | ||
8039 | static void | |
8040 | normalize_address_expr (expressionS *ex) | |
8041 | { | |
8042 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8043 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8044 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8045 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8046 | - 0x80000000); | |
8047 | } | |
8048 | ||
8049 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8050 | Return true if the match was successful. | |
8051 | ||
8052 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8053 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8054 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8055 | as for mips_arg_info. */ | |
8056 | ||
8057 | static bfd_boolean | |
8058 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8059 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8060 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8061 | { |
8062 | const char *args; | |
8063 | struct mips_arg_info arg; | |
8064 | const struct mips_operand *operand; | |
8065 | char c; | |
8066 | ||
8067 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8068 | offset_expr.X_op = O_absent; |
8069 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8070 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8071 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8072 | ||
8073 | create_insn (insn, opcode); | |
60f20e8b RS |
8074 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8075 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8076 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8077 | else | |
8078 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8079 | memset (&arg, 0, sizeof (arg)); |
8080 | arg.insn = insn; | |
8081 | arg.token = tokens; | |
8082 | arg.argnum = 1; | |
8083 | arg.last_regno = ILLEGAL_REG; | |
8084 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8085 | arg.lax_match = lax_match; |
97d87491 RS |
8086 | for (args = opcode->args;; ++args) |
8087 | { | |
8088 | if (arg.token->type == OT_END) | |
8089 | { | |
8090 | /* Handle unary instructions in which only one operand is given. | |
8091 | The source is then the same as the destination. */ | |
8092 | if (arg.opnum == 1 && *args == ',') | |
8093 | { | |
8094 | operand = (mips_opts.micromips | |
8095 | ? decode_micromips_operand (args + 1) | |
8096 | : decode_mips_operand (args + 1)); | |
8097 | if (operand && mips_optional_operand_p (operand)) | |
8098 | { | |
8099 | arg.token = tokens; | |
8100 | arg.argnum = 1; | |
8101 | continue; | |
8102 | } | |
8103 | } | |
8104 | ||
8105 | /* Treat elided base registers as $0. */ | |
8106 | if (strcmp (args, "(b)") == 0) | |
8107 | args += 3; | |
8108 | ||
8109 | if (args[0] == '+') | |
8110 | switch (args[1]) | |
8111 | { | |
8112 | case 'K': | |
8113 | case 'N': | |
8114 | /* The register suffix is optional. */ | |
8115 | args += 2; | |
8116 | break; | |
8117 | } | |
8118 | ||
8119 | /* Fail the match if there were too few operands. */ | |
8120 | if (*args) | |
8121 | return FALSE; | |
8122 | ||
8123 | /* Successful match. */ | |
60f20e8b RS |
8124 | if (!complete_p) |
8125 | return TRUE; | |
e3de51ce | 8126 | clear_insn_error (); |
97d87491 RS |
8127 | if (arg.dest_regno == arg.last_regno |
8128 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8129 | { | |
8130 | if (arg.opnum == 2) | |
e3de51ce | 8131 | set_insn_error |
1661c76c | 8132 | (0, _("source and destination must be different")); |
97d87491 | 8133 | else if (arg.last_regno == 31) |
e3de51ce | 8134 | set_insn_error |
1661c76c | 8135 | (0, _("a destination register must be supplied")); |
97d87491 | 8136 | } |
173d3447 CF |
8137 | else if (arg.last_regno == 31 |
8138 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8139 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8140 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8141 | check_completed_insn (&arg); |
8142 | return TRUE; | |
8143 | } | |
8144 | ||
8145 | /* Fail the match if the line has too many operands. */ | |
8146 | if (*args == 0) | |
8147 | return FALSE; | |
8148 | ||
8149 | /* Handle characters that need to match exactly. */ | |
8150 | if (*args == '(' || *args == ')' || *args == ',') | |
8151 | { | |
8152 | if (match_char (&arg, *args)) | |
8153 | continue; | |
8154 | return FALSE; | |
8155 | } | |
8156 | if (*args == '#') | |
8157 | { | |
8158 | ++args; | |
8159 | if (arg.token->type == OT_DOUBLE_CHAR | |
8160 | && arg.token->u.ch == *args) | |
8161 | { | |
8162 | ++arg.token; | |
8163 | continue; | |
8164 | } | |
8165 | return FALSE; | |
8166 | } | |
8167 | ||
8168 | /* Handle special macro operands. Work out the properties of | |
8169 | other operands. */ | |
8170 | arg.opnum += 1; | |
97d87491 RS |
8171 | switch (*args) |
8172 | { | |
7361da2c AB |
8173 | case '-': |
8174 | switch (args[1]) | |
8175 | { | |
8176 | case 'A': | |
8177 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8178 | break; | |
8179 | ||
8180 | case 'B': | |
8181 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8182 | break; | |
8183 | } | |
8184 | break; | |
8185 | ||
97d87491 RS |
8186 | case '+': |
8187 | switch (args[1]) | |
8188 | { | |
97d87491 RS |
8189 | case 'i': |
8190 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8191 | break; | |
7361da2c AB |
8192 | |
8193 | case '\'': | |
8194 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8195 | break; | |
8196 | ||
8197 | case '\"': | |
8198 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8199 | break; | |
97d87491 RS |
8200 | } |
8201 | break; | |
8202 | ||
97d87491 | 8203 | case 'I': |
1a00e612 RS |
8204 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8205 | return FALSE; | |
8206 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8207 | if (GPR_SIZE == 32) |
97d87491 RS |
8208 | normalize_constant_expr (&imm_expr); |
8209 | continue; | |
8210 | ||
8211 | case 'A': | |
8212 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8213 | { | |
8214 | /* Assume that the offset has been elided and that what | |
8215 | we saw was a base register. The match will fail later | |
8216 | if that assumption turns out to be wrong. */ | |
8217 | offset_expr.X_op = O_constant; | |
8218 | offset_expr.X_add_number = 0; | |
8219 | } | |
97d87491 | 8220 | else |
1a00e612 RS |
8221 | { |
8222 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8223 | return FALSE; | |
8224 | normalize_address_expr (&offset_expr); | |
8225 | } | |
97d87491 RS |
8226 | continue; |
8227 | ||
8228 | case 'F': | |
8229 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8230 | 8, TRUE)) | |
1a00e612 | 8231 | return FALSE; |
97d87491 RS |
8232 | continue; |
8233 | ||
8234 | case 'L': | |
8235 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8236 | 8, FALSE)) | |
1a00e612 | 8237 | return FALSE; |
97d87491 RS |
8238 | continue; |
8239 | ||
8240 | case 'f': | |
8241 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8242 | 4, TRUE)) | |
1a00e612 | 8243 | return FALSE; |
97d87491 RS |
8244 | continue; |
8245 | ||
8246 | case 'l': | |
8247 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8248 | 4, FALSE)) | |
1a00e612 | 8249 | return FALSE; |
97d87491 RS |
8250 | continue; |
8251 | ||
97d87491 RS |
8252 | case 'p': |
8253 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8254 | break; | |
8255 | ||
8256 | case 'a': | |
8257 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8258 | break; | |
8259 | ||
8260 | case 'm': | |
8261 | gas_assert (mips_opts.micromips); | |
8262 | c = args[1]; | |
8263 | switch (c) | |
8264 | { | |
8265 | case 'D': | |
8266 | case 'E': | |
8267 | if (!forced_insn_length) | |
8268 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8269 | else if (c == 'D') | |
8270 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8271 | else | |
8272 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8273 | break; | |
8274 | } | |
8275 | break; | |
8276 | } | |
8277 | ||
8278 | operand = (mips_opts.micromips | |
8279 | ? decode_micromips_operand (args) | |
8280 | : decode_mips_operand (args)); | |
8281 | if (!operand) | |
8282 | abort (); | |
8283 | ||
8284 | /* Skip prefixes. */ | |
7361da2c | 8285 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8286 | args++; |
8287 | ||
8288 | if (mips_optional_operand_p (operand) | |
8289 | && args[1] == ',' | |
8290 | && (arg.token[0].type != OT_REG | |
8291 | || arg.token[1].type == OT_END)) | |
8292 | { | |
8293 | /* Assume that the register has been elided and is the | |
8294 | same as the first operand. */ | |
8295 | arg.token = tokens; | |
8296 | arg.argnum = 1; | |
8297 | } | |
8298 | ||
8299 | if (!match_operand (&arg, operand)) | |
8300 | return FALSE; | |
8301 | } | |
8302 | } | |
8303 | ||
8304 | /* Like match_insn, but for MIPS16. */ | |
8305 | ||
8306 | static bfd_boolean | |
8307 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8308 | struct mips_operand_token *tokens) |
97d87491 RS |
8309 | { |
8310 | const char *args; | |
8311 | const struct mips_operand *operand; | |
8312 | const struct mips_operand *ext_operand; | |
82d808ed | 8313 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8314 | int required_insn_length; |
97d87491 RS |
8315 | struct mips_arg_info arg; |
8316 | int relax_char; | |
8317 | ||
7fd53920 MR |
8318 | if (forced_insn_length) |
8319 | required_insn_length = forced_insn_length; | |
8320 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8321 | required_insn_length = 2; | |
8322 | else | |
8323 | required_insn_length = 0; | |
8324 | ||
97d87491 RS |
8325 | create_insn (insn, opcode); |
8326 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8327 | offset_expr.X_op = O_absent; |
8328 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8329 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8330 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8331 | relax_char = 0; | |
8332 | ||
8333 | memset (&arg, 0, sizeof (arg)); | |
8334 | arg.insn = insn; | |
8335 | arg.token = tokens; | |
8336 | arg.argnum = 1; | |
8337 | arg.last_regno = ILLEGAL_REG; | |
8338 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8339 | relax_char = 0; |
8340 | for (args = opcode->args;; ++args) | |
8341 | { | |
8342 | int c; | |
8343 | ||
8344 | if (arg.token->type == OT_END) | |
8345 | { | |
8346 | offsetT value; | |
8347 | ||
8348 | /* Handle unary instructions in which only one operand is given. | |
8349 | The source is then the same as the destination. */ | |
8350 | if (arg.opnum == 1 && *args == ',') | |
8351 | { | |
8352 | operand = decode_mips16_operand (args[1], FALSE); | |
8353 | if (operand && mips_optional_operand_p (operand)) | |
8354 | { | |
8355 | arg.token = tokens; | |
8356 | arg.argnum = 1; | |
8357 | continue; | |
8358 | } | |
8359 | } | |
8360 | ||
8361 | /* Fail the match if there were too few operands. */ | |
8362 | if (*args) | |
8363 | return FALSE; | |
8364 | ||
8365 | /* Successful match. Stuff the immediate value in now, if | |
8366 | we can. */ | |
e3de51ce | 8367 | clear_insn_error (); |
97d87491 RS |
8368 | if (opcode->pinfo == INSN_MACRO) |
8369 | { | |
8370 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8371 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8372 | } | |
8373 | else if (relax_char | |
8374 | && offset_expr.X_op == O_constant | |
82d808ed | 8375 | && !pcrel |
97d87491 RS |
8376 | && calculate_reloc (*offset_reloc, |
8377 | offset_expr.X_add_number, | |
8378 | &value)) | |
8379 | { | |
8380 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8381 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8382 | offset_expr.X_op = O_absent; |
8383 | *offset_reloc = BFD_RELOC_UNUSED; | |
8384 | } | |
8385 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8386 | { | |
7fd53920 | 8387 | if (required_insn_length == 2) |
e3de51ce | 8388 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8389 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8390 | { |
8391 | forced_insn_length = 4; | |
8392 | insn->insn_opcode |= MIPS16_EXTEND; | |
8393 | } | |
97d87491 RS |
8394 | } |
8395 | else if (relax_char) | |
8396 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8397 | ||
8398 | check_completed_insn (&arg); | |
8399 | return TRUE; | |
8400 | } | |
8401 | ||
8402 | /* Fail the match if the line has too many operands. */ | |
8403 | if (*args == 0) | |
8404 | return FALSE; | |
8405 | ||
8406 | /* Handle characters that need to match exactly. */ | |
8407 | if (*args == '(' || *args == ')' || *args == ',') | |
8408 | { | |
8409 | if (match_char (&arg, *args)) | |
8410 | continue; | |
8411 | return FALSE; | |
8412 | } | |
8413 | ||
8414 | arg.opnum += 1; | |
8415 | c = *args; | |
8416 | switch (c) | |
8417 | { | |
8418 | case 'p': | |
8419 | case 'q': | |
8420 | case 'A': | |
8421 | case 'B': | |
8422 | case 'E': | |
25499ac7 MR |
8423 | case 'V': |
8424 | case 'u': | |
97d87491 RS |
8425 | relax_char = c; |
8426 | break; | |
8427 | ||
8428 | case 'I': | |
1a00e612 RS |
8429 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8430 | return FALSE; | |
8431 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8432 | if (GPR_SIZE == 32) |
97d87491 RS |
8433 | normalize_constant_expr (&imm_expr); |
8434 | continue; | |
8435 | ||
8436 | case 'a': | |
8437 | case 'i': | |
8438 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8439 | break; |
8440 | } | |
8441 | ||
7fd53920 | 8442 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8443 | if (!operand) |
8444 | abort (); | |
8445 | ||
82d808ed MR |
8446 | if (operand->type == OP_PCREL) |
8447 | pcrel = TRUE; | |
8448 | else | |
97d87491 RS |
8449 | { |
8450 | ext_operand = decode_mips16_operand (c, TRUE); | |
8451 | if (operand != ext_operand) | |
8452 | { | |
8453 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8454 | { | |
8455 | offset_expr.X_op = O_constant; | |
8456 | offset_expr.X_add_number = 0; | |
8457 | relax_char = c; | |
8458 | continue; | |
8459 | } | |
8460 | ||
1a7bf198 | 8461 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8462 | return FALSE; |
8463 | ||
8464 | /* '8' is used for SLTI(U) and has traditionally not | |
8465 | been allowed to take relocation operators. */ | |
8466 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8467 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8468 | { |
8469 | match_not_constant (&arg); | |
8470 | return FALSE; | |
8471 | } | |
97d87491 | 8472 | |
c96425c5 MR |
8473 | if (offset_expr.X_op == O_big) |
8474 | { | |
8475 | match_out_of_range (&arg); | |
8476 | return FALSE; | |
8477 | } | |
8478 | ||
97d87491 RS |
8479 | relax_char = c; |
8480 | continue; | |
8481 | } | |
8482 | } | |
8483 | ||
8484 | if (mips_optional_operand_p (operand) | |
8485 | && args[1] == ',' | |
8486 | && (arg.token[0].type != OT_REG | |
8487 | || arg.token[1].type == OT_END)) | |
8488 | { | |
8489 | /* Assume that the register has been elided and is the | |
8490 | same as the first operand. */ | |
8491 | arg.token = tokens; | |
8492 | arg.argnum = 1; | |
8493 | } | |
8494 | ||
8495 | if (!match_operand (&arg, operand)) | |
8496 | return FALSE; | |
8497 | } | |
8498 | } | |
8499 | ||
60f20e8b RS |
8500 | /* Record that the current instruction is invalid for the current ISA. */ |
8501 | ||
8502 | static void | |
8503 | match_invalid_for_isa (void) | |
8504 | { | |
8505 | set_insn_error_ss | |
1661c76c | 8506 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8507 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8508 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8509 | } | |
8510 | ||
8511 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8512 | Return true if a definite match or failure was found, storing any match | |
8513 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8514 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8515 | tried and failed to match under normal conditions and now want to try a | |
8516 | more relaxed match. */ | |
8517 | ||
8518 | static bfd_boolean | |
8519 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8520 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8521 | int opcode_extra, bfd_boolean lax_match) | |
8522 | { | |
8523 | const struct mips_opcode *opcode; | |
8524 | const struct mips_opcode *invalid_delay_slot; | |
8525 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8526 | ||
8527 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8528 | current ISA or forced_length. */ | |
8529 | invalid_delay_slot = 0; | |
8530 | seen_valid_for_isa = FALSE; | |
8531 | seen_valid_for_size = FALSE; | |
8532 | opcode = first; | |
8533 | do | |
8534 | { | |
8535 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8536 | if (is_opcode_valid (opcode)) | |
8537 | { | |
8538 | seen_valid_for_isa = TRUE; | |
8539 | if (is_size_valid (opcode)) | |
8540 | { | |
8541 | bfd_boolean delay_slot_ok; | |
8542 | ||
8543 | seen_valid_for_size = TRUE; | |
8544 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8545 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8546 | lax_match, delay_slot_ok)) | |
8547 | { | |
8548 | if (!delay_slot_ok) | |
8549 | { | |
8550 | if (!invalid_delay_slot) | |
8551 | invalid_delay_slot = opcode; | |
8552 | } | |
8553 | else | |
8554 | return TRUE; | |
8555 | } | |
8556 | } | |
8557 | } | |
8558 | ++opcode; | |
8559 | } | |
8560 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8561 | ||
8562 | /* If the only matches we found had the wrong length for the delay slot, | |
8563 | pick the first such match. We'll issue an appropriate warning later. */ | |
8564 | if (invalid_delay_slot) | |
8565 | { | |
8566 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8567 | lax_match, TRUE)) | |
8568 | return TRUE; | |
8569 | abort (); | |
8570 | } | |
8571 | ||
8572 | /* Handle the case where we didn't try to match an instruction because | |
8573 | all the alternatives were incompatible with the current ISA. */ | |
8574 | if (!seen_valid_for_isa) | |
8575 | { | |
8576 | match_invalid_for_isa (); | |
8577 | return TRUE; | |
8578 | } | |
8579 | ||
8580 | /* Handle the case where we didn't try to match an instruction because | |
8581 | all the alternatives were of the wrong size. */ | |
8582 | if (!seen_valid_for_size) | |
8583 | { | |
8584 | if (mips_opts.insn32) | |
1661c76c | 8585 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8586 | else |
8587 | set_insn_error_i | |
1661c76c | 8588 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8589 | 8 * forced_insn_length); |
8590 | return TRUE; | |
8591 | } | |
8592 | ||
8593 | return FALSE; | |
8594 | } | |
8595 | ||
8596 | /* Like match_insns, but for MIPS16. */ | |
8597 | ||
8598 | static bfd_boolean | |
8599 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8600 | struct mips_operand_token *tokens) | |
8601 | { | |
8602 | const struct mips_opcode *opcode; | |
8603 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8604 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8605 | |
8606 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8607 | current ISA. There are no separate entries for extended forms so | |
8608 | we deal with forced_length later. */ | |
8609 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8610 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8611 | opcode = first; |
8612 | do | |
8613 | { | |
8614 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8615 | if (is_opcode_valid_16 (opcode)) | |
8616 | { | |
8617 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8618 | if (is_size_valid_16 (opcode)) |
8619 | { | |
8620 | seen_valid_for_size = TRUE; | |
8621 | if (match_mips16_insn (insn, opcode, tokens)) | |
8622 | return TRUE; | |
8623 | } | |
60f20e8b RS |
8624 | } |
8625 | ++opcode; | |
8626 | } | |
8627 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8628 | && strcmp (opcode->name, first->name) == 0); | |
8629 | ||
8630 | /* Handle the case where we didn't try to match an instruction because | |
8631 | all the alternatives were incompatible with the current ISA. */ | |
8632 | if (!seen_valid_for_isa) | |
8633 | { | |
8634 | match_invalid_for_isa (); | |
8635 | return TRUE; | |
8636 | } | |
8637 | ||
7fd53920 MR |
8638 | /* Handle the case where we didn't try to match an instruction because |
8639 | all the alternatives were of the wrong size. */ | |
8640 | if (!seen_valid_for_size) | |
8641 | { | |
8642 | if (forced_insn_length == 2) | |
8643 | set_insn_error | |
8644 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8645 | else | |
8646 | set_insn_error | |
8647 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8648 | return TRUE; | |
8649 | } | |
8650 | ||
60f20e8b RS |
8651 | return FALSE; |
8652 | } | |
8653 | ||
584892a6 RS |
8654 | /* Set up global variables for the start of a new macro. */ |
8655 | ||
8656 | static void | |
8657 | macro_start (void) | |
8658 | { | |
8659 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8660 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8661 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8662 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8663 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8664 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8665 | if (history[0].frag |
8666 | && history[0].frag->fr_type == rs_machine_dependent | |
8667 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8668 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8669 | mips_macro_warning.delay_slot_length = 0; | |
8670 | else | |
8671 | switch (history[0].insn_mo->pinfo2 | |
8672 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8673 | { | |
8674 | case INSN2_BRANCH_DELAY_32BIT: | |
8675 | mips_macro_warning.delay_slot_length = 4; | |
8676 | break; | |
8677 | case INSN2_BRANCH_DELAY_16BIT: | |
8678 | mips_macro_warning.delay_slot_length = 2; | |
8679 | break; | |
8680 | default: | |
8681 | mips_macro_warning.delay_slot_length = 0; | |
8682 | break; | |
8683 | } | |
df58fc94 | 8684 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8685 | } |
8686 | ||
df58fc94 RS |
8687 | /* Given that a macro is longer than one instruction or of the wrong size, |
8688 | return the appropriate warning for it. Return null if no warning is | |
8689 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8690 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8691 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8692 | |
8693 | static const char * | |
8694 | macro_warning (relax_substateT subtype) | |
8695 | { | |
8696 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8697 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8698 | " in a branch delay slot"); |
8699 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8700 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8701 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8702 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8703 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8704 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8705 | " in a 16-bit branch delay slot") |
1661c76c | 8706 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8707 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8708 | else |
8709 | return 0; | |
8710 | } | |
8711 | ||
8712 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8713 | ||
8714 | static void | |
8715 | macro_end (void) | |
8716 | { | |
df58fc94 RS |
8717 | /* Relaxation warning flags. */ |
8718 | relax_substateT subtype = 0; | |
8719 | ||
8720 | /* Check delay slot size requirements. */ | |
8721 | if (mips_macro_warning.delay_slot_length == 2) | |
8722 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8723 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8724 | { |
df58fc94 RS |
8725 | if (mips_macro_warning.delay_slot_length |
8726 | != mips_macro_warning.first_insn_sizes[0]) | |
8727 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8728 | if (mips_macro_warning.delay_slot_length | |
8729 | != mips_macro_warning.first_insn_sizes[1]) | |
8730 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8731 | } | |
584892a6 | 8732 | |
df58fc94 RS |
8733 | /* Check instruction count requirements. */ |
8734 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8735 | { | |
8736 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8737 | subtype |= RELAX_SECOND_LONGER; |
8738 | if (mips_opts.warn_about_macros) | |
8739 | subtype |= RELAX_NOMACRO; | |
8740 | if (mips_macro_warning.delay_slot_p) | |
8741 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8742 | } |
584892a6 | 8743 | |
df58fc94 RS |
8744 | /* If both alternatives fail to fill a delay slot correctly, |
8745 | emit the warning now. */ | |
8746 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8747 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8748 | { | |
8749 | relax_substateT s; | |
8750 | const char *msg; | |
8751 | ||
8752 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8753 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8754 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8755 | msg = macro_warning (s); | |
8756 | if (msg != NULL) | |
8757 | as_warn ("%s", msg); | |
8758 | subtype &= ~s; | |
8759 | } | |
8760 | ||
8761 | /* If both implementations are longer than 1 instruction, then emit the | |
8762 | warning now. */ | |
8763 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8764 | { | |
8765 | relax_substateT s; | |
8766 | const char *msg; | |
8767 | ||
8768 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8769 | msg = macro_warning (s); | |
8770 | if (msg != NULL) | |
8771 | as_warn ("%s", msg); | |
8772 | subtype &= ~s; | |
584892a6 | 8773 | } |
df58fc94 RS |
8774 | |
8775 | /* If any flags still set, then one implementation might need a warning | |
8776 | and the other either will need one of a different kind or none at all. | |
8777 | Pass any remaining flags over to relaxation. */ | |
8778 | if (mips_macro_warning.first_frag != NULL) | |
8779 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8780 | } |
8781 | ||
df58fc94 RS |
8782 | /* Instruction operand formats used in macros that vary between |
8783 | standard MIPS and microMIPS code. */ | |
8784 | ||
833794fc | 8785 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8786 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8787 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8788 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8789 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8790 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8791 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8792 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8793 | ||
833794fc | 8794 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8795 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8796 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8797 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8798 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8799 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8800 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8801 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8802 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8803 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8804 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8805 | ||
6e1304d8 RS |
8806 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8807 | The first argument in *ARGS will be either the code for a single | |
8808 | relocation or -1 followed by the three codes that make up a | |
8809 | composite relocation. */ | |
8810 | ||
8811 | static void | |
8812 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8813 | { | |
8814 | int i, next; | |
8815 | ||
8816 | next = va_arg (*args, int); | |
8817 | if (next >= 0) | |
8818 | r[0] = (bfd_reloc_code_real_type) next; | |
8819 | else | |
f2ae14a1 RS |
8820 | { |
8821 | for (i = 0; i < 3; i++) | |
8822 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8823 | /* This function is only used for 16-bit relocation fields. | |
8824 | To make the macro code simpler, treat an unrelocated value | |
8825 | in the same way as BFD_RELOC_LO16. */ | |
8826 | if (r[0] == BFD_RELOC_UNUSED) | |
8827 | r[0] = BFD_RELOC_LO16; | |
8828 | } | |
6e1304d8 RS |
8829 | } |
8830 | ||
252b5132 RH |
8831 | /* Build an instruction created by a macro expansion. This is passed |
8832 | a pointer to the count of instructions created so far, an | |
8833 | expression, the name of the instruction to build, an operand format | |
8834 | string, and corresponding arguments. */ | |
8835 | ||
252b5132 | 8836 | static void |
67c0d1eb | 8837 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8838 | { |
df58fc94 | 8839 | const struct mips_opcode *mo = NULL; |
f6688943 | 8840 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8841 | const struct mips_opcode *amo; |
e077a1c8 | 8842 | const struct mips_operand *operand; |
df58fc94 RS |
8843 | struct hash_control *hash; |
8844 | struct mips_cl_insn insn; | |
252b5132 | 8845 | va_list args; |
e077a1c8 | 8846 | unsigned int uval; |
252b5132 | 8847 | |
252b5132 | 8848 | va_start (args, fmt); |
252b5132 | 8849 | |
252b5132 RH |
8850 | if (mips_opts.mips16) |
8851 | { | |
03ea81db | 8852 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8853 | va_end (args); |
8854 | return; | |
8855 | } | |
8856 | ||
f6688943 TS |
8857 | r[0] = BFD_RELOC_UNUSED; |
8858 | r[1] = BFD_RELOC_UNUSED; | |
8859 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8860 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8861 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8862 | gas_assert (amo); | |
8863 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8864 | |
df58fc94 | 8865 | do |
8b082fb1 TS |
8866 | { |
8867 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8868 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8869 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8870 | slot instruction length requirement (if any) of the previous |
8871 | instruction. While doing this we record the first instruction | |
8872 | seen that matches all the other conditions and use it anyway | |
8873 | if the requirement cannot be met; we will issue an appropriate | |
8874 | warning later on. */ | |
8875 | if (strcmp (fmt, amo->args) == 0 | |
8876 | && amo->pinfo != INSN_MACRO | |
8877 | && is_opcode_valid (amo) | |
8878 | && is_size_valid (amo)) | |
8879 | { | |
8880 | if (is_delay_slot_valid (amo)) | |
8881 | { | |
8882 | mo = amo; | |
8883 | break; | |
8884 | } | |
8885 | else if (!mo) | |
8886 | mo = amo; | |
8887 | } | |
8b082fb1 | 8888 | |
df58fc94 RS |
8889 | ++amo; |
8890 | gas_assert (amo->name); | |
252b5132 | 8891 | } |
df58fc94 | 8892 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8893 | |
df58fc94 | 8894 | gas_assert (mo); |
1e915849 | 8895 | create_insn (&insn, mo); |
e077a1c8 | 8896 | for (; *fmt; ++fmt) |
252b5132 | 8897 | { |
e077a1c8 | 8898 | switch (*fmt) |
252b5132 | 8899 | { |
252b5132 RH |
8900 | case ',': |
8901 | case '(': | |
8902 | case ')': | |
252b5132 | 8903 | case 'z': |
e077a1c8 | 8904 | break; |
252b5132 RH |
8905 | |
8906 | case 'i': | |
8907 | case 'j': | |
6e1304d8 | 8908 | macro_read_relocs (&args, r); |
9c2799c2 | 8909 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8910 | || *r == BFD_RELOC_MIPS_HIGHER |
8911 | || *r == BFD_RELOC_HI16_S | |
8912 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
8913 | || *r == BFD_RELOC_MIPS_GOT_OFST |
8914 | || (mips_opts.micromips | |
8915 | && (*r == BFD_RELOC_16 | |
8916 | || *r == BFD_RELOC_MIPS_GOT16 | |
8917 | || *r == BFD_RELOC_MIPS_CALL16 | |
8918 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8919 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
8920 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
8921 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
8922 | || *r == BFD_RELOC_MIPS_SUB | |
8923 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
8924 | || *r == BFD_RELOC_MIPS_HIGHEST | |
8925 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
8926 | || *r == BFD_RELOC_MIPS_TLS_GD | |
8927 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
8928 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
8929 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
8930 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
8931 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
8932 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 8933 | break; |
e391c024 RS |
8934 | |
8935 | case 'o': | |
8936 | macro_read_relocs (&args, r); | |
e077a1c8 | 8937 | break; |
252b5132 RH |
8938 | |
8939 | case 'u': | |
6e1304d8 | 8940 | macro_read_relocs (&args, r); |
9c2799c2 | 8941 | gas_assert (ep != NULL |
90ecf173 MR |
8942 | && (ep->X_op == O_constant |
8943 | || (ep->X_op == O_symbol | |
8944 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8945 | || *r == BFD_RELOC_HI16_S | |
8946 | || *r == BFD_RELOC_HI16 | |
8947 | || *r == BFD_RELOC_GPREL16 | |
8948 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8949 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8950 | break; |
252b5132 RH |
8951 | |
8952 | case 'p': | |
9c2799c2 | 8953 | gas_assert (ep != NULL); |
bad36eac | 8954 | |
252b5132 RH |
8955 | /* |
8956 | * This allows macro() to pass an immediate expression for | |
8957 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8958 | * |
8959 | * We don't allow branch relaxation for these branches, as | |
8960 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8961 | */ |
8962 | if (ep->X_op == O_constant) | |
8963 | { | |
df58fc94 RS |
8964 | /* For microMIPS we always use relocations for branches. |
8965 | So we should not resolve immediate values. */ | |
8966 | gas_assert (!mips_opts.micromips); | |
8967 | ||
bad36eac DJ |
8968 | if ((ep->X_add_number & 3) != 0) |
8969 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8970 | (unsigned long) ep->X_add_number); | |
8971 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8972 | as_bad (_("branch address range overflow (0x%lx)"), | |
8973 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8974 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8975 | ep = NULL; | |
8976 | } | |
8977 | else | |
0b25d3e6 | 8978 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8979 | break; |
252b5132 RH |
8980 | |
8981 | case 'a': | |
9c2799c2 | 8982 | gas_assert (ep != NULL); |
f6688943 | 8983 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8984 | break; |
d43b4baf | 8985 | |
252b5132 | 8986 | default: |
e077a1c8 RS |
8987 | operand = (mips_opts.micromips |
8988 | ? decode_micromips_operand (fmt) | |
8989 | : decode_mips_operand (fmt)); | |
8990 | if (!operand) | |
8991 | abort (); | |
8992 | ||
8993 | uval = va_arg (args, int); | |
8994 | if (operand->type == OP_CLO_CLZ_DEST) | |
8995 | uval |= (uval << 5); | |
8996 | insn_insert_operand (&insn, operand, uval); | |
8997 | ||
7361da2c | 8998 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8999 | ++fmt; |
9000 | break; | |
252b5132 | 9001 | } |
252b5132 RH |
9002 | } |
9003 | va_end (args); | |
9c2799c2 | 9004 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9005 | |
df58fc94 | 9006 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9007 | } |
9008 | ||
9009 | static void | |
67c0d1eb | 9010 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 9011 | va_list *args) |
252b5132 | 9012 | { |
1e915849 | 9013 | struct mips_opcode *mo; |
252b5132 | 9014 | struct mips_cl_insn insn; |
e077a1c8 | 9015 | const struct mips_operand *operand; |
f6688943 TS |
9016 | bfd_reloc_code_real_type r[3] |
9017 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 9018 | |
1e915849 | 9019 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
9020 | gas_assert (mo); |
9021 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 9022 | |
1e915849 | 9023 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 9024 | { |
1e915849 | 9025 | ++mo; |
9c2799c2 NC |
9026 | gas_assert (mo->name); |
9027 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
9028 | } |
9029 | ||
1e915849 | 9030 | create_insn (&insn, mo); |
e077a1c8 | 9031 | for (; *fmt; ++fmt) |
252b5132 RH |
9032 | { |
9033 | int c; | |
9034 | ||
e077a1c8 | 9035 | c = *fmt; |
252b5132 RH |
9036 | switch (c) |
9037 | { | |
252b5132 RH |
9038 | case ',': |
9039 | case '(': | |
9040 | case ')': | |
e077a1c8 | 9041 | break; |
252b5132 | 9042 | |
d8722d76 | 9043 | case '.': |
252b5132 RH |
9044 | case 'S': |
9045 | case 'P': | |
9046 | case 'R': | |
e077a1c8 | 9047 | break; |
252b5132 RH |
9048 | |
9049 | case '<': | |
252b5132 | 9050 | case '5': |
d8722d76 | 9051 | case 'F': |
252b5132 RH |
9052 | case 'H': |
9053 | case 'W': | |
9054 | case 'D': | |
9055 | case 'j': | |
9056 | case '8': | |
9057 | case 'V': | |
9058 | case 'C': | |
9059 | case 'U': | |
9060 | case 'k': | |
9061 | case 'K': | |
9062 | case 'p': | |
9063 | case 'q': | |
9064 | { | |
b886a2ab RS |
9065 | offsetT value; |
9066 | ||
9c2799c2 | 9067 | gas_assert (ep != NULL); |
252b5132 RH |
9068 | |
9069 | if (ep->X_op != O_constant) | |
874e8986 | 9070 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9071 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9072 | { |
b886a2ab | 9073 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9074 | ep = NULL; |
f6688943 | 9075 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9076 | } |
9077 | } | |
e077a1c8 | 9078 | break; |
252b5132 | 9079 | |
e077a1c8 RS |
9080 | default: |
9081 | operand = decode_mips16_operand (c, FALSE); | |
9082 | if (!operand) | |
9083 | abort (); | |
252b5132 | 9084 | |
4a06e5a2 | 9085 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9086 | break; |
9087 | } | |
252b5132 RH |
9088 | } |
9089 | ||
9c2799c2 | 9090 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9091 | |
df58fc94 | 9092 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9093 | } |
9094 | ||
438c16b8 TS |
9095 | /* |
9096 | * Generate a "jalr" instruction with a relocation hint to the called | |
9097 | * function. This occurs in NewABI PIC code. | |
9098 | */ | |
9099 | static void | |
df58fc94 | 9100 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9101 | { |
df58fc94 RS |
9102 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9103 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9104 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9105 | const char *jalr; | |
685736be | 9106 | char *f = NULL; |
b34976b6 | 9107 | |
1180b5a4 | 9108 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9109 | { |
cc3d92a5 | 9110 | frag_grow (8); |
f21f8242 AO |
9111 | f = frag_more (0); |
9112 | } | |
2906b037 | 9113 | if (mips_opts.micromips) |
df58fc94 | 9114 | { |
833794fc MR |
9115 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9116 | ? "jalr" : "jalrs"); | |
e64af278 | 9117 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9118 | || mips_opts.insn32 |
e64af278 | 9119 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9120 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9121 | else | |
9122 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9123 | } | |
2906b037 MR |
9124 | else |
9125 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9126 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9127 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9128 | } |
9129 | ||
252b5132 RH |
9130 | /* |
9131 | * Generate a "lui" instruction. | |
9132 | */ | |
9133 | static void | |
67c0d1eb | 9134 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9135 | { |
9c2799c2 | 9136 | gas_assert (! mips_opts.mips16); |
252b5132 | 9137 | |
df58fc94 | 9138 | if (ep->X_op != O_constant) |
252b5132 | 9139 | { |
9c2799c2 | 9140 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9141 | /* _gp_disp is a special case, used from s_cpload. |
9142 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9143 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9144 | || (! HAVE_NEWABI |
aa6975fb ILT |
9145 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9146 | || (! mips_in_shared | |
bbe506e8 TS |
9147 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9148 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9149 | } |
9150 | ||
df58fc94 | 9151 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9152 | } |
9153 | ||
885add95 CD |
9154 | /* Generate a sequence of instructions to do a load or store from a constant |
9155 | offset off of a base register (breg) into/from a target register (treg), | |
9156 | using AT if necessary. */ | |
9157 | static void | |
67c0d1eb RS |
9158 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9159 | int treg, int breg, int dbl) | |
885add95 | 9160 | { |
9c2799c2 | 9161 | gas_assert (ep->X_op == O_constant); |
885add95 | 9162 | |
256ab948 | 9163 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9164 | if (!dbl) |
9165 | normalize_constant_expr (ep); | |
256ab948 | 9166 | |
67c1ffbe | 9167 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9168 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9169 | as_warn (_("operand overflow")); |
9170 | ||
9171 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9172 | { | |
9173 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9174 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9175 | } |
9176 | else | |
9177 | { | |
9178 | /* 32-bit offset, need multiple instructions and AT, like: | |
9179 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9180 | addu $tempreg,$tempreg,$breg | |
9181 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9182 | to handle the complete offset. */ | |
67c0d1eb RS |
9183 | macro_build_lui (ep, AT); |
9184 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9185 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9186 | |
741fe287 | 9187 | if (!mips_opts.at) |
1661c76c | 9188 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9189 | } |
9190 | } | |
9191 | ||
252b5132 RH |
9192 | /* set_at() |
9193 | * Generates code to set the $at register to true (one) | |
9194 | * if reg is less than the immediate expression. | |
9195 | */ | |
9196 | static void | |
67c0d1eb | 9197 | set_at (int reg, int unsignedp) |
252b5132 | 9198 | { |
b0e6f033 | 9199 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9200 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9201 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9202 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9203 | else |
9204 | { | |
bad1aba3 | 9205 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9206 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9207 | } |
9208 | } | |
9209 | ||
252b5132 RH |
9210 | /* Count the leading zeroes by performing a binary chop. This is a |
9211 | bulky bit of source, but performance is a LOT better for the | |
9212 | majority of values than a simple loop to count the bits: | |
9213 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9214 | if ((v) & (1 << (31 - lcnt))) | |
9215 | break; | |
9216 | However it is not code size friendly, and the gain will drop a bit | |
9217 | on certain cached systems. | |
9218 | */ | |
9219 | #define COUNT_TOP_ZEROES(v) \ | |
9220 | (((v) & ~0xffff) == 0 \ | |
9221 | ? ((v) & ~0xff) == 0 \ | |
9222 | ? ((v) & ~0xf) == 0 \ | |
9223 | ? ((v) & ~0x3) == 0 \ | |
9224 | ? ((v) & ~0x1) == 0 \ | |
9225 | ? !(v) \ | |
9226 | ? 32 \ | |
9227 | : 31 \ | |
9228 | : 30 \ | |
9229 | : ((v) & ~0x7) == 0 \ | |
9230 | ? 29 \ | |
9231 | : 28 \ | |
9232 | : ((v) & ~0x3f) == 0 \ | |
9233 | ? ((v) & ~0x1f) == 0 \ | |
9234 | ? 27 \ | |
9235 | : 26 \ | |
9236 | : ((v) & ~0x7f) == 0 \ | |
9237 | ? 25 \ | |
9238 | : 24 \ | |
9239 | : ((v) & ~0xfff) == 0 \ | |
9240 | ? ((v) & ~0x3ff) == 0 \ | |
9241 | ? ((v) & ~0x1ff) == 0 \ | |
9242 | ? 23 \ | |
9243 | : 22 \ | |
9244 | : ((v) & ~0x7ff) == 0 \ | |
9245 | ? 21 \ | |
9246 | : 20 \ | |
9247 | : ((v) & ~0x3fff) == 0 \ | |
9248 | ? ((v) & ~0x1fff) == 0 \ | |
9249 | ? 19 \ | |
9250 | : 18 \ | |
9251 | : ((v) & ~0x7fff) == 0 \ | |
9252 | ? 17 \ | |
9253 | : 16 \ | |
9254 | : ((v) & ~0xffffff) == 0 \ | |
9255 | ? ((v) & ~0xfffff) == 0 \ | |
9256 | ? ((v) & ~0x3ffff) == 0 \ | |
9257 | ? ((v) & ~0x1ffff) == 0 \ | |
9258 | ? 15 \ | |
9259 | : 14 \ | |
9260 | : ((v) & ~0x7ffff) == 0 \ | |
9261 | ? 13 \ | |
9262 | : 12 \ | |
9263 | : ((v) & ~0x3fffff) == 0 \ | |
9264 | ? ((v) & ~0x1fffff) == 0 \ | |
9265 | ? 11 \ | |
9266 | : 10 \ | |
9267 | : ((v) & ~0x7fffff) == 0 \ | |
9268 | ? 9 \ | |
9269 | : 8 \ | |
9270 | : ((v) & ~0xfffffff) == 0 \ | |
9271 | ? ((v) & ~0x3ffffff) == 0 \ | |
9272 | ? ((v) & ~0x1ffffff) == 0 \ | |
9273 | ? 7 \ | |
9274 | : 6 \ | |
9275 | : ((v) & ~0x7ffffff) == 0 \ | |
9276 | ? 5 \ | |
9277 | : 4 \ | |
9278 | : ((v) & ~0x3fffffff) == 0 \ | |
9279 | ? ((v) & ~0x1fffffff) == 0 \ | |
9280 | ? 3 \ | |
9281 | : 2 \ | |
9282 | : ((v) & ~0x7fffffff) == 0 \ | |
9283 | ? 1 \ | |
9284 | : 0) | |
9285 | ||
9286 | /* load_register() | |
67c1ffbe | 9287 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9288 | * an absolute expression value into a register. |
9289 | */ | |
9290 | static void | |
67c0d1eb | 9291 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9292 | { |
9293 | int freg; | |
9294 | expressionS hi32, lo32; | |
9295 | ||
9296 | if (ep->X_op != O_big) | |
9297 | { | |
9c2799c2 | 9298 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9299 | |
9300 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9301 | if (!dbl) |
9302 | normalize_constant_expr (ep); | |
256ab948 TS |
9303 | |
9304 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9305 | { |
9306 | /* We can handle 16 bit signed values with an addiu to | |
9307 | $zero. No need to ever use daddiu here, since $zero and | |
9308 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9309 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9310 | return; |
9311 | } | |
9312 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9313 | { | |
9314 | /* We can handle 16 bit unsigned values with an ori to | |
9315 | $zero. */ | |
67c0d1eb | 9316 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9317 | return; |
9318 | } | |
256ab948 | 9319 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9320 | { |
9321 | /* 32 bit values require an lui. */ | |
df58fc94 | 9322 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9323 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9324 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9325 | return; |
9326 | } | |
9327 | } | |
9328 | ||
9329 | /* The value is larger than 32 bits. */ | |
9330 | ||
bad1aba3 | 9331 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9332 | { |
55e08f71 NC |
9333 | char value[32]; |
9334 | ||
9335 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9336 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9337 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9338 | return; |
9339 | } | |
9340 | ||
9341 | if (ep->X_op != O_big) | |
9342 | { | |
9343 | hi32 = *ep; | |
9344 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9345 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9346 | hi32.X_add_number &= 0xffffffff; | |
9347 | lo32 = *ep; | |
9348 | lo32.X_add_number &= 0xffffffff; | |
9349 | } | |
9350 | else | |
9351 | { | |
9c2799c2 | 9352 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9353 | if (ep->X_add_number == 3) |
9354 | generic_bignum[3] = 0; | |
9355 | else if (ep->X_add_number > 4) | |
1661c76c | 9356 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9357 | lo32.X_op = O_constant; |
9358 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9359 | hi32.X_op = O_constant; | |
9360 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9361 | } | |
9362 | ||
9363 | if (hi32.X_add_number == 0) | |
9364 | freg = 0; | |
9365 | else | |
9366 | { | |
9367 | int shift, bit; | |
9368 | unsigned long hi, lo; | |
9369 | ||
956cd1d6 | 9370 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9371 | { |
9372 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9373 | { | |
67c0d1eb | 9374 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9375 | return; |
9376 | } | |
9377 | if (lo32.X_add_number & 0x80000000) | |
9378 | { | |
df58fc94 | 9379 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9380 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9381 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9382 | return; |
9383 | } | |
9384 | } | |
252b5132 RH |
9385 | |
9386 | /* Check for 16bit shifted constant. We know that hi32 is | |
9387 | non-zero, so start the mask on the first bit of the hi32 | |
9388 | value. */ | |
9389 | shift = 17; | |
9390 | do | |
beae10d5 KH |
9391 | { |
9392 | unsigned long himask, lomask; | |
9393 | ||
9394 | if (shift < 32) | |
9395 | { | |
9396 | himask = 0xffff >> (32 - shift); | |
9397 | lomask = (0xffff << shift) & 0xffffffff; | |
9398 | } | |
9399 | else | |
9400 | { | |
9401 | himask = 0xffff << (shift - 32); | |
9402 | lomask = 0; | |
9403 | } | |
9404 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9405 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9406 | { | |
9407 | expressionS tmp; | |
9408 | ||
9409 | tmp.X_op = O_constant; | |
9410 | if (shift < 32) | |
9411 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9412 | | (lo32.X_add_number >> shift)); | |
9413 | else | |
9414 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9415 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9416 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9417 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9418 | return; |
9419 | } | |
f9419b05 | 9420 | ++shift; |
beae10d5 KH |
9421 | } |
9422 | while (shift <= (64 - 16)); | |
252b5132 RH |
9423 | |
9424 | /* Find the bit number of the lowest one bit, and store the | |
9425 | shifted value in hi/lo. */ | |
9426 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9427 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9428 | if (lo != 0) | |
9429 | { | |
9430 | bit = 0; | |
9431 | while ((lo & 1) == 0) | |
9432 | { | |
9433 | lo >>= 1; | |
9434 | ++bit; | |
9435 | } | |
9436 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9437 | hi >>= bit; | |
9438 | } | |
9439 | else | |
9440 | { | |
9441 | bit = 32; | |
9442 | while ((hi & 1) == 0) | |
9443 | { | |
9444 | hi >>= 1; | |
9445 | ++bit; | |
9446 | } | |
9447 | lo = hi; | |
9448 | hi = 0; | |
9449 | } | |
9450 | ||
9451 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9452 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9453 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9454 | { |
9455 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9456 | if (shift != 0) |
beae10d5 | 9457 | { |
252b5132 RH |
9458 | expressionS tmp; |
9459 | ||
9460 | /* This instruction will set the register to be all | |
9461 | ones. */ | |
beae10d5 KH |
9462 | tmp.X_op = O_constant; |
9463 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9464 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9465 | if (bit != 0) |
9466 | { | |
9467 | bit += shift; | |
df58fc94 | 9468 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9469 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9470 | } |
df58fc94 | 9471 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9472 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9473 | return; |
9474 | } | |
9475 | } | |
252b5132 RH |
9476 | |
9477 | /* Sign extend hi32 before calling load_register, because we can | |
9478 | generally get better code when we load a sign extended value. */ | |
9479 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9480 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9481 | load_register (reg, &hi32, 0); |
252b5132 RH |
9482 | freg = reg; |
9483 | } | |
9484 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9485 | { | |
9486 | if (freg != 0) | |
9487 | { | |
df58fc94 | 9488 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9489 | freg = reg; |
9490 | } | |
9491 | } | |
9492 | else | |
9493 | { | |
9494 | expressionS mid16; | |
9495 | ||
956cd1d6 | 9496 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9497 | { |
df58fc94 RS |
9498 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9499 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9500 | return; |
9501 | } | |
252b5132 RH |
9502 | |
9503 | if (freg != 0) | |
9504 | { | |
df58fc94 | 9505 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9506 | freg = reg; |
9507 | } | |
9508 | mid16 = lo32; | |
9509 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9510 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9511 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9512 | freg = reg; |
9513 | } | |
9514 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9515 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9516 | } |
9517 | ||
269137b2 TS |
9518 | static inline void |
9519 | load_delay_nop (void) | |
9520 | { | |
9521 | if (!gpr_interlocks) | |
9522 | macro_build (NULL, "nop", ""); | |
9523 | } | |
9524 | ||
252b5132 RH |
9525 | /* Load an address into a register. */ |
9526 | ||
9527 | static void | |
67c0d1eb | 9528 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9529 | { |
252b5132 RH |
9530 | if (ep->X_op != O_constant |
9531 | && ep->X_op != O_symbol) | |
9532 | { | |
9533 | as_bad (_("expression too complex")); | |
9534 | ep->X_op = O_constant; | |
9535 | } | |
9536 | ||
9537 | if (ep->X_op == O_constant) | |
9538 | { | |
67c0d1eb | 9539 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9540 | return; |
9541 | } | |
9542 | ||
9543 | if (mips_pic == NO_PIC) | |
9544 | { | |
9545 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9546 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9547 | Otherwise we want |
9548 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9549 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9550 | If we have an addend, we always use the latter form. |
76b3015f | 9551 | |
d6bc6245 TS |
9552 | With 64bit address space and a usable $at we want |
9553 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9554 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9555 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9556 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9557 | dsll32 $reg,0 | |
3a482fd5 | 9558 | daddu $reg,$reg,$at |
76b3015f | 9559 | |
c03099e6 | 9560 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9561 | on superscalar processors. |
9562 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9563 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9564 | dsll $reg,16 | |
9565 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9566 | dsll $reg,16 | |
9567 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9568 | |
9569 | For GP relative symbols in 64bit address space we can use | |
9570 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9571 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9572 | { |
6caf9ef4 TS |
9573 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9574 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9575 | { | |
9576 | relax_start (ep->X_add_symbol); | |
9577 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9578 | mips_gp_register, BFD_RELOC_GPREL16); | |
9579 | relax_switch (); | |
9580 | } | |
d6bc6245 | 9581 | |
741fe287 | 9582 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9583 | { |
df58fc94 RS |
9584 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9585 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9586 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9587 | BFD_RELOC_MIPS_HIGHER); | |
9588 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9589 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9590 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9591 | *used_at = 1; |
9592 | } | |
9593 | else | |
9594 | { | |
df58fc94 | 9595 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9596 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9597 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9598 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9599 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9600 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9601 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9602 | } |
6caf9ef4 TS |
9603 | |
9604 | if (mips_relax.sequence) | |
9605 | relax_end (); | |
d6bc6245 | 9606 | } |
252b5132 RH |
9607 | else |
9608 | { | |
d6bc6245 | 9609 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9610 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9611 | { |
4d7206a2 | 9612 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9613 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9614 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9615 | relax_switch (); |
d6bc6245 | 9616 | } |
67c0d1eb RS |
9617 | macro_build_lui (ep, reg); |
9618 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9619 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9620 | if (mips_relax.sequence) |
9621 | relax_end (); | |
d6bc6245 | 9622 | } |
252b5132 | 9623 | } |
0a44bf69 | 9624 | else if (!mips_big_got) |
252b5132 RH |
9625 | { |
9626 | expressionS ex; | |
9627 | ||
9628 | /* If this is a reference to an external symbol, we want | |
9629 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9630 | Otherwise we want | |
9631 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9632 | nop | |
9633 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9634 | If there is a constant, it must be added in after. |
9635 | ||
ed6fb7bd | 9636 | If we have NewABI, we want |
f5040a92 AO |
9637 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9638 | unless we're referencing a global symbol with a non-zero | |
9639 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9640 | if (HAVE_NEWABI) |
9641 | { | |
f5040a92 AO |
9642 | if (ep->X_add_number) |
9643 | { | |
4d7206a2 | 9644 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9645 | ep->X_add_number = 0; |
4d7206a2 | 9646 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9647 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9648 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9649 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9650 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9651 | ex.X_op = O_constant; | |
67c0d1eb | 9652 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9653 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9654 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9655 | relax_switch (); |
f5040a92 | 9656 | } |
67c0d1eb | 9657 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9658 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9659 | if (mips_relax.sequence) |
9660 | relax_end (); | |
ed6fb7bd SC |
9661 | } |
9662 | else | |
9663 | { | |
f5040a92 AO |
9664 | ex.X_add_number = ep->X_add_number; |
9665 | ep->X_add_number = 0; | |
67c0d1eb RS |
9666 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9667 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9668 | load_delay_nop (); |
4d7206a2 RS |
9669 | relax_start (ep->X_add_symbol); |
9670 | relax_switch (); | |
67c0d1eb | 9671 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9672 | BFD_RELOC_LO16); |
4d7206a2 | 9673 | relax_end (); |
ed6fb7bd | 9674 | |
f5040a92 AO |
9675 | if (ex.X_add_number != 0) |
9676 | { | |
9677 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9678 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9679 | ex.X_op = O_constant; | |
67c0d1eb | 9680 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9681 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9682 | } |
252b5132 RH |
9683 | } |
9684 | } | |
0a44bf69 | 9685 | else if (mips_big_got) |
252b5132 RH |
9686 | { |
9687 | expressionS ex; | |
252b5132 RH |
9688 | |
9689 | /* This is the large GOT case. If this is a reference to an | |
9690 | external symbol, we want | |
9691 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9692 | addu $reg,$reg,$gp | |
9693 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9694 | |
9695 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9696 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9697 | nop | |
9698 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9699 | If there is a constant, it must be added in after. |
f5040a92 AO |
9700 | |
9701 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9702 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9703 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9704 | */ |
438c16b8 TS |
9705 | if (HAVE_NEWABI) |
9706 | { | |
4d7206a2 | 9707 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9708 | ep->X_add_number = 0; |
4d7206a2 | 9709 | relax_start (ep->X_add_symbol); |
df58fc94 | 9710 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9711 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9712 | reg, reg, mips_gp_register); | |
9713 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9714 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9715 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9716 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9717 | else if (ex.X_add_number) | |
9718 | { | |
9719 | ex.X_op = O_constant; | |
67c0d1eb RS |
9720 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9721 | BFD_RELOC_LO16); | |
f5040a92 AO |
9722 | } |
9723 | ||
9724 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9725 | relax_switch (); |
67c0d1eb | 9726 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9727 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9728 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9729 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9730 | relax_end (); |
438c16b8 | 9731 | } |
252b5132 | 9732 | else |
438c16b8 | 9733 | { |
f5040a92 AO |
9734 | ex.X_add_number = ep->X_add_number; |
9735 | ep->X_add_number = 0; | |
4d7206a2 | 9736 | relax_start (ep->X_add_symbol); |
df58fc94 | 9737 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9738 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9739 | reg, reg, mips_gp_register); | |
9740 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9741 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9742 | relax_switch (); |
9743 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9744 | { |
9745 | /* We need a nop before loading from $gp. This special | |
9746 | check is required because the lui which starts the main | |
9747 | instruction stream does not refer to $gp, and so will not | |
9748 | insert the nop which may be required. */ | |
67c0d1eb | 9749 | macro_build (NULL, "nop", ""); |
438c16b8 | 9750 | } |
67c0d1eb | 9751 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9752 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9753 | load_delay_nop (); |
67c0d1eb | 9754 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9755 | BFD_RELOC_LO16); |
4d7206a2 | 9756 | relax_end (); |
438c16b8 | 9757 | |
f5040a92 AO |
9758 | if (ex.X_add_number != 0) |
9759 | { | |
9760 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9761 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9762 | ex.X_op = O_constant; | |
67c0d1eb RS |
9763 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9764 | BFD_RELOC_LO16); | |
f5040a92 | 9765 | } |
252b5132 RH |
9766 | } |
9767 | } | |
252b5132 RH |
9768 | else |
9769 | abort (); | |
8fc2e39e | 9770 | |
741fe287 | 9771 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9772 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9773 | } |
9774 | ||
ea1fb5dc RS |
9775 | /* Move the contents of register SOURCE into register DEST. */ |
9776 | ||
9777 | static void | |
67c0d1eb | 9778 | move_register (int dest, int source) |
ea1fb5dc | 9779 | { |
df58fc94 RS |
9780 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9781 | instruction specifically requires a 32-bit one. */ | |
9782 | if (mips_opts.micromips | |
833794fc | 9783 | && !mips_opts.insn32 |
df58fc94 | 9784 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9785 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9786 | else |
40fc1451 | 9787 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9788 | } |
9789 | ||
4d7206a2 | 9790 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9791 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9792 | The two alternatives are: | |
4d7206a2 | 9793 | |
33eaf5de | 9794 | Global symbol Local symbol |
4d7206a2 RS |
9795 | ------------- ------------ |
9796 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9797 | ... ... | |
9798 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9799 | ||
9800 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9801 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9802 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9803 | |
9804 | static void | |
67c0d1eb | 9805 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9806 | { |
9807 | expressionS global; | |
9808 | ||
9809 | global = *local; | |
9810 | global.X_add_number = 0; | |
9811 | ||
9812 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9813 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9814 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9815 | relax_switch (); |
67c0d1eb RS |
9816 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9817 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9818 | relax_end (); |
9819 | } | |
9820 | ||
9821 | static void | |
67c0d1eb | 9822 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9823 | { |
9824 | expressionS global; | |
9825 | ||
9826 | global.X_op = O_constant; | |
9827 | global.X_op_symbol = NULL; | |
9828 | global.X_add_symbol = NULL; | |
9829 | global.X_add_number = local->X_add_number; | |
9830 | ||
9831 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9832 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9833 | dest, dest, BFD_RELOC_LO16); |
9834 | relax_switch (); | |
67c0d1eb | 9835 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9836 | relax_end (); |
9837 | } | |
9838 | ||
f6a22291 MR |
9839 | static void |
9840 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9841 | { | |
9842 | expressionS global; | |
9843 | int hold_mips_optimize; | |
9844 | ||
9845 | global.X_op = O_constant; | |
9846 | global.X_op_symbol = NULL; | |
9847 | global.X_add_symbol = NULL; | |
9848 | global.X_add_number = local->X_add_number; | |
9849 | ||
9850 | relax_start (local->X_add_symbol); | |
9851 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9852 | relax_switch (); | |
9853 | /* Set mips_optimize around the lui instruction to avoid | |
9854 | inserting an unnecessary nop after the lw. */ | |
9855 | hold_mips_optimize = mips_optimize; | |
9856 | mips_optimize = 2; | |
9857 | macro_build_lui (&global, tmp); | |
9858 | mips_optimize = hold_mips_optimize; | |
9859 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9860 | relax_end (); | |
9861 | ||
9862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9863 | } | |
9864 | ||
df58fc94 RS |
9865 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9866 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9867 | is its complementing branch with the original condition negated. | |
9868 | CALL is set if the original branch specified the link operation. | |
9869 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9870 | ||
9871 | Code like this is produced in the noreorder mode: | |
9872 | ||
9873 | BRNEG <args>, 1f | |
9874 | nop | |
9875 | b <sym> | |
9876 | delay slot (executed only if branch taken) | |
9877 | 1: | |
9878 | ||
9879 | or, if CALL is set: | |
9880 | ||
9881 | BRNEG <args>, 1f | |
9882 | nop | |
9883 | bal <sym> | |
9884 | delay slot (executed only if branch taken) | |
9885 | 1: | |
9886 | ||
9887 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9888 | so code produced is simply: | |
9889 | ||
9890 | BR <args>, <sym> | |
9891 | nop | |
9892 | ||
9893 | This function is used when producing code for the microMIPS ASE that | |
9894 | does not implement branch likely instructions in hardware. */ | |
9895 | ||
9896 | static void | |
9897 | macro_build_branch_likely (const char *br, const char *brneg, | |
9898 | int call, expressionS *ep, const char *fmt, | |
9899 | unsigned int sreg, unsigned int treg) | |
9900 | { | |
9901 | int noreorder = mips_opts.noreorder; | |
9902 | expressionS expr1; | |
9903 | ||
9904 | gas_assert (mips_opts.micromips); | |
9905 | start_noreorder (); | |
9906 | if (noreorder) | |
9907 | { | |
9908 | micromips_label_expr (&expr1); | |
9909 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9910 | macro_build (NULL, "nop", ""); | |
9911 | macro_build (ep, call ? "bal" : "b", "p"); | |
9912 | ||
9913 | /* Set to true so that append_insn adds a label. */ | |
9914 | emit_branch_likely_macro = TRUE; | |
9915 | } | |
9916 | else | |
9917 | { | |
9918 | macro_build (ep, br, fmt, sreg, treg); | |
9919 | macro_build (NULL, "nop", ""); | |
9920 | } | |
9921 | end_noreorder (); | |
9922 | } | |
9923 | ||
9924 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9925 | the condition code tested. EP specifies the branch target. */ | |
9926 | ||
9927 | static void | |
9928 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9929 | { | |
9930 | const int call = 0; | |
9931 | const char *brneg; | |
9932 | const char *br; | |
9933 | ||
9934 | switch (type) | |
9935 | { | |
9936 | case M_BC1FL: | |
9937 | br = "bc1f"; | |
9938 | brneg = "bc1t"; | |
9939 | break; | |
9940 | case M_BC1TL: | |
9941 | br = "bc1t"; | |
9942 | brneg = "bc1f"; | |
9943 | break; | |
9944 | case M_BC2FL: | |
9945 | br = "bc2f"; | |
9946 | brneg = "bc2t"; | |
9947 | break; | |
9948 | case M_BC2TL: | |
9949 | br = "bc2t"; | |
9950 | brneg = "bc2f"; | |
9951 | break; | |
9952 | default: | |
9953 | abort (); | |
9954 | } | |
9955 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9956 | } | |
9957 | ||
9958 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9959 | the register tested. EP specifies the branch target. */ | |
9960 | ||
9961 | static void | |
9962 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9963 | { | |
9964 | const char *brneg = NULL; | |
9965 | const char *br; | |
9966 | int call = 0; | |
9967 | ||
9968 | switch (type) | |
9969 | { | |
9970 | case M_BGEZ: | |
9971 | br = "bgez"; | |
9972 | break; | |
9973 | case M_BGEZL: | |
9974 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9975 | brneg = "bltz"; | |
9976 | break; | |
9977 | case M_BGEZALL: | |
9978 | gas_assert (mips_opts.micromips); | |
833794fc | 9979 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9980 | brneg = "bltz"; |
9981 | call = 1; | |
9982 | break; | |
9983 | case M_BGTZ: | |
9984 | br = "bgtz"; | |
9985 | break; | |
9986 | case M_BGTZL: | |
9987 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9988 | brneg = "blez"; | |
9989 | break; | |
9990 | case M_BLEZ: | |
9991 | br = "blez"; | |
9992 | break; | |
9993 | case M_BLEZL: | |
9994 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9995 | brneg = "bgtz"; | |
9996 | break; | |
9997 | case M_BLTZ: | |
9998 | br = "bltz"; | |
9999 | break; | |
10000 | case M_BLTZL: | |
10001 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
10002 | brneg = "bgez"; | |
10003 | break; | |
10004 | case M_BLTZALL: | |
10005 | gas_assert (mips_opts.micromips); | |
833794fc | 10006 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
10007 | brneg = "bgez"; |
10008 | call = 1; | |
10009 | break; | |
10010 | default: | |
10011 | abort (); | |
10012 | } | |
10013 | if (mips_opts.micromips && brneg) | |
10014 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
10015 | else | |
10016 | macro_build (ep, br, "s,p", sreg); | |
10017 | } | |
10018 | ||
10019 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
10020 | TREG as the registers tested. EP specifies the branch target. */ | |
10021 | ||
10022 | static void | |
10023 | macro_build_branch_rsrt (int type, expressionS *ep, | |
10024 | unsigned int sreg, unsigned int treg) | |
10025 | { | |
10026 | const char *brneg = NULL; | |
10027 | const int call = 0; | |
10028 | const char *br; | |
10029 | ||
10030 | switch (type) | |
10031 | { | |
10032 | case M_BEQ: | |
10033 | case M_BEQ_I: | |
10034 | br = "beq"; | |
10035 | break; | |
10036 | case M_BEQL: | |
10037 | case M_BEQL_I: | |
10038 | br = mips_opts.micromips ? "beq" : "beql"; | |
10039 | brneg = "bne"; | |
10040 | break; | |
10041 | case M_BNE: | |
10042 | case M_BNE_I: | |
10043 | br = "bne"; | |
10044 | break; | |
10045 | case M_BNEL: | |
10046 | case M_BNEL_I: | |
10047 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10048 | brneg = "beq"; | |
10049 | break; | |
10050 | default: | |
10051 | abort (); | |
10052 | } | |
10053 | if (mips_opts.micromips && brneg) | |
10054 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10055 | else | |
10056 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10057 | } | |
10058 | ||
f2ae14a1 RS |
10059 | /* Return the high part that should be loaded in order to make the low |
10060 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10061 | ||
10062 | static offsetT | |
10063 | offset_high_part (offsetT value, unsigned int offbits) | |
10064 | { | |
10065 | offsetT bias; | |
10066 | addressT low_mask; | |
10067 | ||
10068 | if (offbits == 0) | |
10069 | return value; | |
10070 | bias = 1 << (offbits - 1); | |
10071 | low_mask = bias * 2 - 1; | |
10072 | return (value + bias) & ~low_mask; | |
10073 | } | |
10074 | ||
10075 | /* Return true if the value stored in offset_expr and offset_reloc | |
10076 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10077 | amount that the caller wants to add without inducing overflow | |
10078 | and ALIGN is the known alignment of the value in bytes. */ | |
10079 | ||
10080 | static bfd_boolean | |
10081 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10082 | { | |
10083 | if (offbits == 16) | |
10084 | { | |
10085 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10086 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10087 | return TRUE; | |
10088 | ||
10089 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10090 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10091 | || gprel16_reloc_p (*offset_reloc)) | |
10092 | return TRUE; | |
10093 | } | |
10094 | if (offset_expr.X_op == O_constant | |
10095 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10096 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10097 | return TRUE; | |
10098 | return FALSE; | |
10099 | } | |
10100 | ||
252b5132 RH |
10101 | /* |
10102 | * Build macros | |
10103 | * This routine implements the seemingly endless macro or synthesized | |
10104 | * instructions and addressing modes in the mips assembly language. Many | |
10105 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10106 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10107 | * this verbose method. Others are not simple macros but are more like |
10108 | * optimizing code generation. | |
10109 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10110 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10111 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10112 | * of global optimization. We currently only optimize within a single macro. |
10113 | * For many of the load and store macros if the address is specified as a | |
10114 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10115 | * first load register 'at' with zero and use it as the base register. The | |
10116 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10117 | * we're missing. | |
10118 | */ | |
10119 | static void | |
833794fc | 10120 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10121 | { |
c0ebe874 RS |
10122 | const struct mips_operand_array *operands; |
10123 | unsigned int breg, i; | |
741fe287 | 10124 | unsigned int tempreg; |
252b5132 | 10125 | int mask; |
43841e91 | 10126 | int used_at = 0; |
df58fc94 | 10127 | expressionS label_expr; |
252b5132 | 10128 | expressionS expr1; |
df58fc94 | 10129 | expressionS *ep; |
252b5132 RH |
10130 | const char *s; |
10131 | const char *s2; | |
10132 | const char *fmt; | |
10133 | int likely = 0; | |
252b5132 | 10134 | int coproc = 0; |
7f3c4072 | 10135 | int offbits = 16; |
1abe91b1 | 10136 | int call = 0; |
df58fc94 RS |
10137 | int jals = 0; |
10138 | int dbl = 0; | |
10139 | int imm = 0; | |
10140 | int ust = 0; | |
10141 | int lp = 0; | |
f2ae14a1 | 10142 | bfd_boolean large_offset; |
252b5132 | 10143 | int off; |
252b5132 | 10144 | int hold_mips_optimize; |
f2ae14a1 | 10145 | unsigned int align; |
c0ebe874 | 10146 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10147 | |
9c2799c2 | 10148 | gas_assert (! mips_opts.mips16); |
252b5132 | 10149 | |
c0ebe874 RS |
10150 | operands = insn_operands (ip); |
10151 | for (i = 0; i < MAX_OPERANDS; i++) | |
10152 | if (operands->operand[i]) | |
10153 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10154 | else | |
10155 | op[i] = -1; | |
10156 | ||
252b5132 RH |
10157 | mask = ip->insn_mo->mask; |
10158 | ||
df58fc94 RS |
10159 | label_expr.X_op = O_constant; |
10160 | label_expr.X_op_symbol = NULL; | |
10161 | label_expr.X_add_symbol = NULL; | |
10162 | label_expr.X_add_number = 0; | |
10163 | ||
252b5132 RH |
10164 | expr1.X_op = O_constant; |
10165 | expr1.X_op_symbol = NULL; | |
10166 | expr1.X_add_symbol = NULL; | |
10167 | expr1.X_add_number = 1; | |
f2ae14a1 | 10168 | align = 1; |
252b5132 RH |
10169 | |
10170 | switch (mask) | |
10171 | { | |
10172 | case M_DABS: | |
10173 | dbl = 1; | |
1a0670f3 | 10174 | /* Fall through. */ |
252b5132 | 10175 | case M_ABS: |
df58fc94 RS |
10176 | /* bgez $a0,1f |
10177 | move v0,$a0 | |
10178 | sub v0,$zero,$a0 | |
10179 | 1: | |
10180 | */ | |
252b5132 | 10181 | |
7d10b47d | 10182 | start_noreorder (); |
252b5132 | 10183 | |
df58fc94 RS |
10184 | if (mips_opts.micromips) |
10185 | micromips_label_expr (&label_expr); | |
10186 | else | |
10187 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10188 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10189 | if (op[0] == op[1]) | |
a605d2b3 | 10190 | macro_build (NULL, "nop", ""); |
252b5132 | 10191 | else |
c0ebe874 RS |
10192 | move_register (op[0], op[1]); |
10193 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10194 | if (mips_opts.micromips) |
10195 | micromips_add_label (); | |
252b5132 | 10196 | |
7d10b47d | 10197 | end_noreorder (); |
8fc2e39e | 10198 | break; |
252b5132 RH |
10199 | |
10200 | case M_ADD_I: | |
10201 | s = "addi"; | |
10202 | s2 = "add"; | |
10203 | goto do_addi; | |
10204 | case M_ADDU_I: | |
10205 | s = "addiu"; | |
10206 | s2 = "addu"; | |
10207 | goto do_addi; | |
10208 | case M_DADD_I: | |
10209 | dbl = 1; | |
10210 | s = "daddi"; | |
10211 | s2 = "dadd"; | |
df58fc94 RS |
10212 | if (!mips_opts.micromips) |
10213 | goto do_addi; | |
b0e6f033 | 10214 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
10215 | && imm_expr.X_add_number < 0x200) |
10216 | { | |
b0e6f033 RS |
10217 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10218 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10219 | break; |
10220 | } | |
10221 | goto do_addi_i; | |
252b5132 RH |
10222 | case M_DADDU_I: |
10223 | dbl = 1; | |
10224 | s = "daddiu"; | |
10225 | s2 = "daddu"; | |
10226 | do_addi: | |
b0e6f033 | 10227 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10228 | && imm_expr.X_add_number < 0x8000) |
10229 | { | |
c0ebe874 | 10230 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10231 | break; |
252b5132 | 10232 | } |
df58fc94 | 10233 | do_addi_i: |
8fc2e39e | 10234 | used_at = 1; |
67c0d1eb | 10235 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10236 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10237 | break; |
10238 | ||
10239 | case M_AND_I: | |
10240 | s = "andi"; | |
10241 | s2 = "and"; | |
10242 | goto do_bit; | |
10243 | case M_OR_I: | |
10244 | s = "ori"; | |
10245 | s2 = "or"; | |
10246 | goto do_bit; | |
10247 | case M_NOR_I: | |
10248 | s = ""; | |
10249 | s2 = "nor"; | |
10250 | goto do_bit; | |
10251 | case M_XOR_I: | |
10252 | s = "xori"; | |
10253 | s2 = "xor"; | |
10254 | do_bit: | |
b0e6f033 | 10255 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10256 | && imm_expr.X_add_number < 0x10000) |
10257 | { | |
10258 | if (mask != M_NOR_I) | |
c0ebe874 | 10259 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10260 | else |
10261 | { | |
67c0d1eb | 10262 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10263 | op[0], op[1], BFD_RELOC_LO16); |
10264 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10265 | } |
8fc2e39e | 10266 | break; |
252b5132 RH |
10267 | } |
10268 | ||
8fc2e39e | 10269 | used_at = 1; |
bad1aba3 | 10270 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10271 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10272 | break; |
10273 | ||
8b082fb1 TS |
10274 | case M_BALIGN: |
10275 | switch (imm_expr.X_add_number) | |
10276 | { | |
10277 | case 0: | |
10278 | macro_build (NULL, "nop", ""); | |
10279 | break; | |
10280 | case 2: | |
c0ebe874 | 10281 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10282 | break; |
03f66e8a MR |
10283 | case 1: |
10284 | case 3: | |
c0ebe874 | 10285 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10286 | (int) imm_expr.X_add_number); |
8b082fb1 | 10287 | break; |
03f66e8a MR |
10288 | default: |
10289 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10290 | (unsigned long) imm_expr.X_add_number); | |
10291 | break; | |
8b082fb1 TS |
10292 | } |
10293 | break; | |
10294 | ||
df58fc94 RS |
10295 | case M_BC1FL: |
10296 | case M_BC1TL: | |
10297 | case M_BC2FL: | |
10298 | case M_BC2TL: | |
10299 | gas_assert (mips_opts.micromips); | |
10300 | macro_build_branch_ccl (mask, &offset_expr, | |
10301 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10302 | break; | |
10303 | ||
252b5132 | 10304 | case M_BEQ_I: |
252b5132 | 10305 | case M_BEQL_I: |
252b5132 | 10306 | case M_BNE_I: |
252b5132 | 10307 | case M_BNEL_I: |
b0e6f033 | 10308 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10309 | op[1] = 0; |
df58fc94 | 10310 | else |
252b5132 | 10311 | { |
c0ebe874 | 10312 | op[1] = AT; |
df58fc94 | 10313 | used_at = 1; |
bad1aba3 | 10314 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10315 | } |
df58fc94 RS |
10316 | /* Fall through. */ |
10317 | case M_BEQL: | |
10318 | case M_BNEL: | |
c0ebe874 | 10319 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10320 | break; |
10321 | ||
10322 | case M_BGEL: | |
10323 | likely = 1; | |
1a0670f3 | 10324 | /* Fall through. */ |
252b5132 | 10325 | case M_BGE: |
c0ebe874 RS |
10326 | if (op[1] == 0) |
10327 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10328 | else if (op[0] == 0) | |
10329 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10330 | else |
252b5132 | 10331 | { |
df58fc94 | 10332 | used_at = 1; |
c0ebe874 | 10333 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10334 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10335 | &offset_expr, AT, ZERO); | |
252b5132 | 10336 | } |
df58fc94 RS |
10337 | break; |
10338 | ||
10339 | case M_BGEZL: | |
10340 | case M_BGEZALL: | |
10341 | case M_BGTZL: | |
10342 | case M_BLEZL: | |
10343 | case M_BLTZL: | |
10344 | case M_BLTZALL: | |
c0ebe874 | 10345 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10346 | break; |
10347 | ||
10348 | case M_BGTL_I: | |
10349 | likely = 1; | |
1a0670f3 | 10350 | /* Fall through. */ |
252b5132 | 10351 | case M_BGT_I: |
90ecf173 | 10352 | /* Check for > max integer. */ |
b0e6f033 | 10353 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10354 | { |
10355 | do_false: | |
90ecf173 | 10356 | /* Result is always false. */ |
252b5132 | 10357 | if (! likely) |
a605d2b3 | 10358 | macro_build (NULL, "nop", ""); |
252b5132 | 10359 | else |
df58fc94 | 10360 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10361 | break; |
252b5132 | 10362 | } |
f9419b05 | 10363 | ++imm_expr.X_add_number; |
252b5132 RH |
10364 | /* FALLTHROUGH */ |
10365 | case M_BGE_I: | |
10366 | case M_BGEL_I: | |
10367 | if (mask == M_BGEL_I) | |
10368 | likely = 1; | |
b0e6f033 | 10369 | if (imm_expr.X_add_number == 0) |
252b5132 | 10370 | { |
df58fc94 | 10371 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10372 | &offset_expr, op[0]); |
8fc2e39e | 10373 | break; |
252b5132 | 10374 | } |
b0e6f033 | 10375 | if (imm_expr.X_add_number == 1) |
252b5132 | 10376 | { |
df58fc94 | 10377 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10378 | &offset_expr, op[0]); |
8fc2e39e | 10379 | break; |
252b5132 | 10380 | } |
b0e6f033 | 10381 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10382 | { |
10383 | do_true: | |
10384 | /* result is always true */ | |
1661c76c | 10385 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10386 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10387 | break; |
252b5132 | 10388 | } |
8fc2e39e | 10389 | used_at = 1; |
c0ebe874 | 10390 | set_at (op[0], 0); |
df58fc94 RS |
10391 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10392 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10393 | break; |
10394 | ||
10395 | case M_BGEUL: | |
10396 | likely = 1; | |
1a0670f3 | 10397 | /* Fall through. */ |
252b5132 | 10398 | case M_BGEU: |
c0ebe874 | 10399 | if (op[1] == 0) |
252b5132 | 10400 | goto do_true; |
c0ebe874 | 10401 | else if (op[0] == 0) |
df58fc94 | 10402 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10403 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10404 | else |
252b5132 | 10405 | { |
df58fc94 | 10406 | used_at = 1; |
c0ebe874 | 10407 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10408 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10409 | &offset_expr, AT, ZERO); | |
252b5132 | 10410 | } |
252b5132 RH |
10411 | break; |
10412 | ||
10413 | case M_BGTUL_I: | |
10414 | likely = 1; | |
1a0670f3 | 10415 | /* Fall through. */ |
252b5132 | 10416 | case M_BGTU_I: |
c0ebe874 | 10417 | if (op[0] == 0 |
bad1aba3 | 10418 | || (GPR_SIZE == 32 |
f01dc953 | 10419 | && imm_expr.X_add_number == -1)) |
252b5132 | 10420 | goto do_false; |
f9419b05 | 10421 | ++imm_expr.X_add_number; |
252b5132 RH |
10422 | /* FALLTHROUGH */ |
10423 | case M_BGEU_I: | |
10424 | case M_BGEUL_I: | |
10425 | if (mask == M_BGEUL_I) | |
10426 | likely = 1; | |
b0e6f033 | 10427 | if (imm_expr.X_add_number == 0) |
252b5132 | 10428 | goto do_true; |
b0e6f033 | 10429 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10430 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10431 | &offset_expr, op[0], ZERO); |
df58fc94 | 10432 | else |
252b5132 | 10433 | { |
df58fc94 | 10434 | used_at = 1; |
c0ebe874 | 10435 | set_at (op[0], 1); |
df58fc94 RS |
10436 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10437 | &offset_expr, AT, ZERO); | |
252b5132 | 10438 | } |
252b5132 RH |
10439 | break; |
10440 | ||
10441 | case M_BGTL: | |
10442 | likely = 1; | |
1a0670f3 | 10443 | /* Fall through. */ |
252b5132 | 10444 | case M_BGT: |
c0ebe874 RS |
10445 | if (op[1] == 0) |
10446 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10447 | else if (op[0] == 0) | |
10448 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10449 | else |
252b5132 | 10450 | { |
df58fc94 | 10451 | used_at = 1; |
c0ebe874 | 10452 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10453 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10454 | &offset_expr, AT, ZERO); | |
252b5132 | 10455 | } |
252b5132 RH |
10456 | break; |
10457 | ||
10458 | case M_BGTUL: | |
10459 | likely = 1; | |
1a0670f3 | 10460 | /* Fall through. */ |
252b5132 | 10461 | case M_BGTU: |
c0ebe874 | 10462 | if (op[1] == 0) |
df58fc94 | 10463 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10464 | &offset_expr, op[0], ZERO); |
10465 | else if (op[0] == 0) | |
df58fc94 RS |
10466 | goto do_false; |
10467 | else | |
252b5132 | 10468 | { |
df58fc94 | 10469 | used_at = 1; |
c0ebe874 | 10470 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10471 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10472 | &offset_expr, AT, ZERO); | |
252b5132 | 10473 | } |
252b5132 RH |
10474 | break; |
10475 | ||
10476 | case M_BLEL: | |
10477 | likely = 1; | |
1a0670f3 | 10478 | /* Fall through. */ |
252b5132 | 10479 | case M_BLE: |
c0ebe874 RS |
10480 | if (op[1] == 0) |
10481 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10482 | else if (op[0] == 0) | |
10483 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10484 | else |
252b5132 | 10485 | { |
df58fc94 | 10486 | used_at = 1; |
c0ebe874 | 10487 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10488 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10489 | &offset_expr, AT, ZERO); | |
252b5132 | 10490 | } |
252b5132 RH |
10491 | break; |
10492 | ||
10493 | case M_BLEL_I: | |
10494 | likely = 1; | |
1a0670f3 | 10495 | /* Fall through. */ |
252b5132 | 10496 | case M_BLE_I: |
b0e6f033 | 10497 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10498 | goto do_true; |
f9419b05 | 10499 | ++imm_expr.X_add_number; |
252b5132 RH |
10500 | /* FALLTHROUGH */ |
10501 | case M_BLT_I: | |
10502 | case M_BLTL_I: | |
10503 | if (mask == M_BLTL_I) | |
10504 | likely = 1; | |
b0e6f033 | 10505 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10506 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10507 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10508 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10509 | else |
252b5132 | 10510 | { |
df58fc94 | 10511 | used_at = 1; |
c0ebe874 | 10512 | set_at (op[0], 0); |
df58fc94 RS |
10513 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10514 | &offset_expr, AT, ZERO); | |
252b5132 | 10515 | } |
252b5132 RH |
10516 | break; |
10517 | ||
10518 | case M_BLEUL: | |
10519 | likely = 1; | |
1a0670f3 | 10520 | /* Fall through. */ |
252b5132 | 10521 | case M_BLEU: |
c0ebe874 | 10522 | if (op[1] == 0) |
df58fc94 | 10523 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10524 | &offset_expr, op[0], ZERO); |
10525 | else if (op[0] == 0) | |
df58fc94 RS |
10526 | goto do_true; |
10527 | else | |
252b5132 | 10528 | { |
df58fc94 | 10529 | used_at = 1; |
c0ebe874 | 10530 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10531 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10532 | &offset_expr, AT, ZERO); | |
252b5132 | 10533 | } |
252b5132 RH |
10534 | break; |
10535 | ||
10536 | case M_BLEUL_I: | |
10537 | likely = 1; | |
1a0670f3 | 10538 | /* Fall through. */ |
252b5132 | 10539 | case M_BLEU_I: |
c0ebe874 | 10540 | if (op[0] == 0 |
bad1aba3 | 10541 | || (GPR_SIZE == 32 |
f01dc953 | 10542 | && imm_expr.X_add_number == -1)) |
252b5132 | 10543 | goto do_true; |
f9419b05 | 10544 | ++imm_expr.X_add_number; |
252b5132 RH |
10545 | /* FALLTHROUGH */ |
10546 | case M_BLTU_I: | |
10547 | case M_BLTUL_I: | |
10548 | if (mask == M_BLTUL_I) | |
10549 | likely = 1; | |
b0e6f033 | 10550 | if (imm_expr.X_add_number == 0) |
252b5132 | 10551 | goto do_false; |
b0e6f033 | 10552 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10553 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10554 | &offset_expr, op[0], ZERO); |
df58fc94 | 10555 | else |
252b5132 | 10556 | { |
df58fc94 | 10557 | used_at = 1; |
c0ebe874 | 10558 | set_at (op[0], 1); |
df58fc94 RS |
10559 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10560 | &offset_expr, AT, ZERO); | |
252b5132 | 10561 | } |
252b5132 RH |
10562 | break; |
10563 | ||
10564 | case M_BLTL: | |
10565 | likely = 1; | |
1a0670f3 | 10566 | /* Fall through. */ |
252b5132 | 10567 | case M_BLT: |
c0ebe874 RS |
10568 | if (op[1] == 0) |
10569 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10570 | else if (op[0] == 0) | |
10571 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10572 | else |
252b5132 | 10573 | { |
df58fc94 | 10574 | used_at = 1; |
c0ebe874 | 10575 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10576 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10577 | &offset_expr, AT, ZERO); | |
252b5132 | 10578 | } |
252b5132 RH |
10579 | break; |
10580 | ||
10581 | case M_BLTUL: | |
10582 | likely = 1; | |
1a0670f3 | 10583 | /* Fall through. */ |
252b5132 | 10584 | case M_BLTU: |
c0ebe874 | 10585 | if (op[1] == 0) |
252b5132 | 10586 | goto do_false; |
c0ebe874 | 10587 | else if (op[0] == 0) |
df58fc94 | 10588 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10589 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10590 | else |
252b5132 | 10591 | { |
df58fc94 | 10592 | used_at = 1; |
c0ebe874 | 10593 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10594 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10595 | &offset_expr, AT, ZERO); | |
252b5132 | 10596 | } |
252b5132 RH |
10597 | break; |
10598 | ||
10599 | case M_DDIV_3: | |
10600 | dbl = 1; | |
1a0670f3 | 10601 | /* Fall through. */ |
252b5132 RH |
10602 | case M_DIV_3: |
10603 | s = "mflo"; | |
10604 | goto do_div3; | |
10605 | case M_DREM_3: | |
10606 | dbl = 1; | |
1a0670f3 | 10607 | /* Fall through. */ |
252b5132 RH |
10608 | case M_REM_3: |
10609 | s = "mfhi"; | |
10610 | do_div3: | |
c0ebe874 | 10611 | if (op[2] == 0) |
252b5132 | 10612 | { |
1661c76c | 10613 | as_warn (_("divide by zero")); |
252b5132 | 10614 | if (mips_trap) |
df58fc94 | 10615 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10616 | else |
df58fc94 | 10617 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10618 | break; |
252b5132 RH |
10619 | } |
10620 | ||
7d10b47d | 10621 | start_noreorder (); |
252b5132 RH |
10622 | if (mips_trap) |
10623 | { | |
c0ebe874 RS |
10624 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10625 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10626 | } |
10627 | else | |
10628 | { | |
df58fc94 RS |
10629 | if (mips_opts.micromips) |
10630 | micromips_label_expr (&label_expr); | |
10631 | else | |
10632 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10633 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10634 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10635 | macro_build (NULL, "break", BRK_FMT, 7); |
10636 | if (mips_opts.micromips) | |
10637 | micromips_add_label (); | |
252b5132 RH |
10638 | } |
10639 | expr1.X_add_number = -1; | |
8fc2e39e | 10640 | used_at = 1; |
f6a22291 | 10641 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10642 | if (mips_opts.micromips) |
10643 | micromips_label_expr (&label_expr); | |
10644 | else | |
10645 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10646 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10647 | if (dbl) |
10648 | { | |
10649 | expr1.X_add_number = 1; | |
f6a22291 | 10650 | load_register (AT, &expr1, dbl); |
df58fc94 | 10651 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10652 | } |
10653 | else | |
10654 | { | |
10655 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10656 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10657 | } |
10658 | if (mips_trap) | |
10659 | { | |
c0ebe874 | 10660 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10661 | /* We want to close the noreorder block as soon as possible, so |
10662 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10663 | end_noreorder (); |
252b5132 RH |
10664 | } |
10665 | else | |
10666 | { | |
df58fc94 RS |
10667 | if (mips_opts.micromips) |
10668 | micromips_label_expr (&label_expr); | |
10669 | else | |
10670 | label_expr.X_add_number = 8; | |
c0ebe874 | 10671 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10672 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10673 | |
10674 | /* We want to close the noreorder block as soon as possible, so | |
10675 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10676 | end_noreorder (); |
252b5132 | 10677 | |
df58fc94 | 10678 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10679 | } |
df58fc94 RS |
10680 | if (mips_opts.micromips) |
10681 | micromips_add_label (); | |
c0ebe874 | 10682 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10683 | break; |
10684 | ||
10685 | case M_DIV_3I: | |
10686 | s = "div"; | |
10687 | s2 = "mflo"; | |
10688 | goto do_divi; | |
10689 | case M_DIVU_3I: | |
10690 | s = "divu"; | |
10691 | s2 = "mflo"; | |
10692 | goto do_divi; | |
10693 | case M_REM_3I: | |
10694 | s = "div"; | |
10695 | s2 = "mfhi"; | |
10696 | goto do_divi; | |
10697 | case M_REMU_3I: | |
10698 | s = "divu"; | |
10699 | s2 = "mfhi"; | |
10700 | goto do_divi; | |
10701 | case M_DDIV_3I: | |
10702 | dbl = 1; | |
10703 | s = "ddiv"; | |
10704 | s2 = "mflo"; | |
10705 | goto do_divi; | |
10706 | case M_DDIVU_3I: | |
10707 | dbl = 1; | |
10708 | s = "ddivu"; | |
10709 | s2 = "mflo"; | |
10710 | goto do_divi; | |
10711 | case M_DREM_3I: | |
10712 | dbl = 1; | |
10713 | s = "ddiv"; | |
10714 | s2 = "mfhi"; | |
10715 | goto do_divi; | |
10716 | case M_DREMU_3I: | |
10717 | dbl = 1; | |
10718 | s = "ddivu"; | |
10719 | s2 = "mfhi"; | |
10720 | do_divi: | |
b0e6f033 | 10721 | if (imm_expr.X_add_number == 0) |
252b5132 | 10722 | { |
1661c76c | 10723 | as_warn (_("divide by zero")); |
252b5132 | 10724 | if (mips_trap) |
df58fc94 | 10725 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10726 | else |
df58fc94 | 10727 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10728 | break; |
252b5132 | 10729 | } |
b0e6f033 | 10730 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10731 | { |
10732 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10733 | move_register (op[0], op[1]); |
252b5132 | 10734 | else |
c0ebe874 | 10735 | move_register (op[0], ZERO); |
8fc2e39e | 10736 | break; |
252b5132 | 10737 | } |
b0e6f033 | 10738 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10739 | { |
10740 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10741 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10742 | else |
c0ebe874 | 10743 | move_register (op[0], ZERO); |
8fc2e39e | 10744 | break; |
252b5132 RH |
10745 | } |
10746 | ||
8fc2e39e | 10747 | used_at = 1; |
67c0d1eb | 10748 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10749 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10750 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10751 | break; |
10752 | ||
10753 | case M_DIVU_3: | |
10754 | s = "divu"; | |
10755 | s2 = "mflo"; | |
10756 | goto do_divu3; | |
10757 | case M_REMU_3: | |
10758 | s = "divu"; | |
10759 | s2 = "mfhi"; | |
10760 | goto do_divu3; | |
10761 | case M_DDIVU_3: | |
10762 | s = "ddivu"; | |
10763 | s2 = "mflo"; | |
10764 | goto do_divu3; | |
10765 | case M_DREMU_3: | |
10766 | s = "ddivu"; | |
10767 | s2 = "mfhi"; | |
10768 | do_divu3: | |
7d10b47d | 10769 | start_noreorder (); |
252b5132 RH |
10770 | if (mips_trap) |
10771 | { | |
c0ebe874 RS |
10772 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10773 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10774 | /* We want to close the noreorder block as soon as possible, so |
10775 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10776 | end_noreorder (); |
252b5132 RH |
10777 | } |
10778 | else | |
10779 | { | |
df58fc94 RS |
10780 | if (mips_opts.micromips) |
10781 | micromips_label_expr (&label_expr); | |
10782 | else | |
10783 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10784 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10785 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10786 | |
10787 | /* We want to close the noreorder block as soon as possible, so | |
10788 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10789 | end_noreorder (); |
df58fc94 RS |
10790 | macro_build (NULL, "break", BRK_FMT, 7); |
10791 | if (mips_opts.micromips) | |
10792 | micromips_add_label (); | |
252b5132 | 10793 | } |
c0ebe874 | 10794 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10795 | break; |
252b5132 | 10796 | |
1abe91b1 MR |
10797 | case M_DLCA_AB: |
10798 | dbl = 1; | |
1a0670f3 | 10799 | /* Fall through. */ |
1abe91b1 MR |
10800 | case M_LCA_AB: |
10801 | call = 1; | |
10802 | goto do_la; | |
252b5132 RH |
10803 | case M_DLA_AB: |
10804 | dbl = 1; | |
1a0670f3 | 10805 | /* Fall through. */ |
252b5132 | 10806 | case M_LA_AB: |
1abe91b1 | 10807 | do_la: |
252b5132 RH |
10808 | /* Load the address of a symbol into a register. If breg is not |
10809 | zero, we then add a base register to it. */ | |
10810 | ||
c0ebe874 | 10811 | breg = op[2]; |
bad1aba3 | 10812 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10813 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10814 | "instead")); | |
3bec30a8 | 10815 | |
90ecf173 | 10816 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10817 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10818 | "instead")); | |
3bec30a8 | 10819 | |
f2ae14a1 | 10820 | if (small_offset_p (0, align, 16)) |
0c11417f | 10821 | { |
c0ebe874 | 10822 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10823 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10824 | break; |
0c11417f MR |
10825 | } |
10826 | ||
c0ebe874 | 10827 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10828 | { |
10829 | tempreg = AT; | |
10830 | used_at = 1; | |
10831 | } | |
10832 | else | |
c0ebe874 | 10833 | tempreg = op[0]; |
afdbd6d0 | 10834 | |
252b5132 RH |
10835 | if (offset_expr.X_op != O_symbol |
10836 | && offset_expr.X_op != O_constant) | |
10837 | { | |
1661c76c | 10838 | as_bad (_("expression too complex")); |
252b5132 RH |
10839 | offset_expr.X_op = O_constant; |
10840 | } | |
10841 | ||
252b5132 | 10842 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10843 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10844 | else if (mips_pic == NO_PIC) |
10845 | { | |
d6bc6245 | 10846 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10847 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10848 | Otherwise we want |
10849 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10850 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10851 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10852 | so we may as well always use the latter form. |
76b3015f | 10853 | |
6caf9ef4 TS |
10854 | With 64bit address space and a usable $at we want |
10855 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10856 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10857 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10858 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10859 | dsll32 $tempreg,0 | |
10860 | daddu $tempreg,$tempreg,$at | |
10861 | ||
10862 | If $at is already in use, we use a path which is suboptimal | |
10863 | on superscalar processors. | |
10864 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10865 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10866 | dsll $tempreg,16 | |
10867 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10868 | dsll $tempreg,16 | |
10869 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10870 | ||
10871 | For GP relative symbols in 64bit address space we can use | |
10872 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10873 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10874 | { |
6caf9ef4 TS |
10875 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10876 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10877 | { | |
10878 | relax_start (offset_expr.X_add_symbol); | |
10879 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10880 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10881 | relax_switch (); | |
10882 | } | |
d6bc6245 | 10883 | |
741fe287 | 10884 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10885 | { |
df58fc94 | 10886 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10887 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10888 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10889 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10890 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10891 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10892 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10893 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10894 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10895 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10896 | used_at = 1; |
10897 | } | |
10898 | else | |
10899 | { | |
df58fc94 | 10900 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10901 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10902 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10903 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10904 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10905 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10906 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10907 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10908 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10909 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10910 | } |
6caf9ef4 TS |
10911 | |
10912 | if (mips_relax.sequence) | |
10913 | relax_end (); | |
98d3f06f KH |
10914 | } |
10915 | else | |
10916 | { | |
10917 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10918 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10919 | { |
4d7206a2 | 10920 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10921 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10922 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10923 | relax_switch (); |
98d3f06f | 10924 | } |
6943caf0 | 10925 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10926 | as_bad (_("offset too large")); |
67c0d1eb RS |
10927 | macro_build_lui (&offset_expr, tempreg); |
10928 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10929 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10930 | if (mips_relax.sequence) |
10931 | relax_end (); | |
98d3f06f | 10932 | } |
252b5132 | 10933 | } |
0a44bf69 | 10934 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10935 | { |
9117d219 NC |
10936 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10937 | ||
252b5132 RH |
10938 | /* If this is a reference to an external symbol, and there |
10939 | is no constant, we want | |
10940 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10941 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10942 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10943 | For a local symbol, we want |
10944 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10945 | nop | |
10946 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10947 | ||
10948 | If we have a small constant, and this is a reference to | |
10949 | an external symbol, we want | |
10950 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10951 | nop | |
10952 | addiu $tempreg,$tempreg,<constant> | |
10953 | For a local symbol, we want the same instruction | |
10954 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10955 | addiu instruction. | |
10956 | ||
10957 | If we have a large constant, and this is a reference to | |
10958 | an external symbol, we want | |
10959 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10960 | lui $at,<hiconstant> | |
10961 | addiu $at,$at,<loconstant> | |
10962 | addu $tempreg,$tempreg,$at | |
10963 | For a local symbol, we want the same instruction | |
10964 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10965 | addiu instruction. |
ed6fb7bd SC |
10966 | */ |
10967 | ||
4d7206a2 | 10968 | if (offset_expr.X_add_number == 0) |
252b5132 | 10969 | { |
0a44bf69 RS |
10970 | if (mips_pic == SVR4_PIC |
10971 | && breg == 0 | |
10972 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10973 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10974 | ||
10975 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10976 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10977 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10978 | if (breg != 0) |
252b5132 RH |
10979 | { |
10980 | /* We're going to put in an addu instruction using | |
10981 | tempreg, so we may as well insert the nop right | |
10982 | now. */ | |
269137b2 | 10983 | load_delay_nop (); |
252b5132 | 10984 | } |
4d7206a2 | 10985 | relax_switch (); |
67c0d1eb RS |
10986 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10987 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10988 | load_delay_nop (); |
67c0d1eb RS |
10989 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10990 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10991 | relax_end (); |
252b5132 RH |
10992 | /* FIXME: If breg == 0, and the next instruction uses |
10993 | $tempreg, then if this variant case is used an extra | |
10994 | nop will be generated. */ | |
10995 | } | |
4d7206a2 RS |
10996 | else if (offset_expr.X_add_number >= -0x8000 |
10997 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10998 | { |
67c0d1eb | 10999 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 11000 | load_delay_nop (); |
67c0d1eb | 11001 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
11002 | } |
11003 | else | |
11004 | { | |
4d7206a2 RS |
11005 | expr1.X_add_number = offset_expr.X_add_number; |
11006 | offset_expr.X_add_number = | |
43c0598f | 11007 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 11008 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 11009 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
11010 | /* If we are going to add in a base register, and the |
11011 | target register and the base register are the same, | |
11012 | then we are using AT as a temporary register. Since | |
11013 | we want to load the constant into AT, we add our | |
11014 | current AT (from the global offset table) and the | |
11015 | register into the register now, and pretend we were | |
11016 | not using a base register. */ | |
c0ebe874 | 11017 | if (breg == op[0]) |
252b5132 | 11018 | { |
269137b2 | 11019 | load_delay_nop (); |
67c0d1eb | 11020 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11021 | op[0], AT, breg); |
252b5132 | 11022 | breg = 0; |
c0ebe874 | 11023 | tempreg = op[0]; |
252b5132 | 11024 | } |
f6a22291 | 11025 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
11026 | used_at = 1; |
11027 | } | |
11028 | } | |
0a44bf69 | 11029 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 11030 | { |
67c0d1eb | 11031 | int add_breg_early = 0; |
f5040a92 AO |
11032 | |
11033 | /* If this is a reference to an external, and there is no | |
11034 | constant, or local symbol (*), with or without a | |
11035 | constant, we want | |
11036 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 11037 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11038 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
11039 | ||
11040 | If we have a small constant, and this is a reference to | |
11041 | an external symbol, we want | |
11042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11043 | addiu $tempreg,$tempreg,<constant> | |
11044 | ||
11045 | If we have a large constant, and this is a reference to | |
11046 | an external symbol, we want | |
11047 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11048 | lui $at,<hiconstant> | |
11049 | addiu $at,$at,<loconstant> | |
11050 | addu $tempreg,$tempreg,$at | |
11051 | ||
11052 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11053 | local symbols, even though it introduces an additional | |
11054 | instruction. */ | |
11055 | ||
f5040a92 AO |
11056 | if (offset_expr.X_add_number) |
11057 | { | |
4d7206a2 | 11058 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11059 | offset_expr.X_add_number = 0; |
11060 | ||
4d7206a2 | 11061 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11062 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11063 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11064 | |
11065 | if (expr1.X_add_number >= -0x8000 | |
11066 | && expr1.X_add_number < 0x8000) | |
11067 | { | |
67c0d1eb RS |
11068 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11069 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11070 | } |
ecd13cd3 | 11071 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11072 | { |
c0ebe874 RS |
11073 | unsigned int dreg; |
11074 | ||
f5040a92 AO |
11075 | /* If we are going to add in a base register, and the |
11076 | target register and the base register are the same, | |
11077 | then we are using AT as a temporary register. Since | |
11078 | we want to load the constant into AT, we add our | |
11079 | current AT (from the global offset table) and the | |
11080 | register into the register now, and pretend we were | |
11081 | not using a base register. */ | |
c0ebe874 | 11082 | if (breg != op[0]) |
f5040a92 AO |
11083 | dreg = tempreg; |
11084 | else | |
11085 | { | |
9c2799c2 | 11086 | gas_assert (tempreg == AT); |
67c0d1eb | 11087 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11088 | op[0], AT, breg); |
11089 | dreg = op[0]; | |
67c0d1eb | 11090 | add_breg_early = 1; |
f5040a92 AO |
11091 | } |
11092 | ||
f6a22291 | 11093 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11094 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11095 | dreg, dreg, AT); |
f5040a92 | 11096 | |
f5040a92 AO |
11097 | used_at = 1; |
11098 | } | |
11099 | else | |
11100 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11101 | ||
4d7206a2 | 11102 | relax_switch (); |
f5040a92 AO |
11103 | offset_expr.X_add_number = expr1.X_add_number; |
11104 | ||
67c0d1eb RS |
11105 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11106 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11107 | if (add_breg_early) | |
f5040a92 | 11108 | { |
67c0d1eb | 11109 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11110 | op[0], tempreg, breg); |
f5040a92 | 11111 | breg = 0; |
c0ebe874 | 11112 | tempreg = op[0]; |
f5040a92 | 11113 | } |
4d7206a2 | 11114 | relax_end (); |
f5040a92 | 11115 | } |
4d7206a2 | 11116 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11117 | { |
4d7206a2 | 11118 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11119 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11120 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11121 | relax_switch (); |
67c0d1eb RS |
11122 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11123 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11124 | relax_end (); |
f5040a92 | 11125 | } |
4d7206a2 | 11126 | else |
f5040a92 | 11127 | { |
67c0d1eb RS |
11128 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11129 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11130 | } |
11131 | } | |
0a44bf69 | 11132 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11133 | { |
67c0d1eb | 11134 | int gpdelay; |
9117d219 NC |
11135 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11136 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11137 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11138 | |
11139 | /* This is the large GOT case. If this is a reference to an | |
11140 | external symbol, and there is no constant, we want | |
11141 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11142 | addu $tempreg,$tempreg,$gp | |
11143 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11144 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11145 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11146 | addu $tempreg,$tempreg,$gp | |
11147 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11148 | For a local symbol, we want |
11149 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11150 | nop | |
11151 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11152 | ||
11153 | If we have a small constant, and this is a reference to | |
11154 | an external symbol, we want | |
11155 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11156 | addu $tempreg,$tempreg,$gp | |
11157 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11158 | nop | |
11159 | addiu $tempreg,$tempreg,<constant> | |
11160 | For a local symbol, we want | |
11161 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11162 | nop | |
11163 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11164 | ||
11165 | If we have a large constant, and this is a reference to | |
11166 | an external symbol, we want | |
11167 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11168 | addu $tempreg,$tempreg,$gp | |
11169 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11170 | lui $at,<hiconstant> | |
11171 | addiu $at,$at,<loconstant> | |
11172 | addu $tempreg,$tempreg,$at | |
11173 | For a local symbol, we want | |
11174 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11175 | lui $at,<hiconstant> | |
11176 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11177 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11178 | */ |
438c16b8 | 11179 | |
252b5132 RH |
11180 | expr1.X_add_number = offset_expr.X_add_number; |
11181 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11182 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11183 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11184 | if (expr1.X_add_number == 0 && breg == 0 |
11185 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11186 | { |
11187 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11188 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11189 | } | |
df58fc94 | 11190 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11191 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11192 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11193 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11194 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11195 | if (expr1.X_add_number == 0) |
11196 | { | |
67c0d1eb | 11197 | if (breg != 0) |
252b5132 RH |
11198 | { |
11199 | /* We're going to put in an addu instruction using | |
11200 | tempreg, so we may as well insert the nop right | |
11201 | now. */ | |
269137b2 | 11202 | load_delay_nop (); |
252b5132 | 11203 | } |
252b5132 RH |
11204 | } |
11205 | else if (expr1.X_add_number >= -0x8000 | |
11206 | && expr1.X_add_number < 0x8000) | |
11207 | { | |
269137b2 | 11208 | load_delay_nop (); |
67c0d1eb | 11209 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11210 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11211 | } |
11212 | else | |
11213 | { | |
c0ebe874 RS |
11214 | unsigned int dreg; |
11215 | ||
252b5132 RH |
11216 | /* If we are going to add in a base register, and the |
11217 | target register and the base register are the same, | |
11218 | then we are using AT as a temporary register. Since | |
11219 | we want to load the constant into AT, we add our | |
11220 | current AT (from the global offset table) and the | |
11221 | register into the register now, and pretend we were | |
11222 | not using a base register. */ | |
c0ebe874 | 11223 | if (breg != op[0]) |
67c0d1eb | 11224 | dreg = tempreg; |
252b5132 RH |
11225 | else |
11226 | { | |
9c2799c2 | 11227 | gas_assert (tempreg == AT); |
269137b2 | 11228 | load_delay_nop (); |
67c0d1eb | 11229 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11230 | op[0], AT, breg); |
11231 | dreg = op[0]; | |
252b5132 RH |
11232 | } |
11233 | ||
f6a22291 | 11234 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11235 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11236 | |
252b5132 RH |
11237 | used_at = 1; |
11238 | } | |
43c0598f | 11239 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11240 | relax_switch (); |
252b5132 | 11241 | |
67c0d1eb | 11242 | if (gpdelay) |
252b5132 RH |
11243 | { |
11244 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11245 | the first instruction on the main stream does not. */ |
67c0d1eb | 11246 | macro_build (NULL, "nop", ""); |
252b5132 | 11247 | } |
ed6fb7bd | 11248 | |
67c0d1eb RS |
11249 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11250 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11251 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11252 | && expr1.X_add_number < 0x8000) |
11253 | { | |
269137b2 | 11254 | load_delay_nop (); |
67c0d1eb RS |
11255 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11256 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11257 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11258 | register, the external symbol case ended with a load, |
11259 | so if the symbol turns out to not be external, and | |
11260 | the next instruction uses tempreg, an unnecessary nop | |
11261 | will be inserted. */ | |
252b5132 RH |
11262 | } |
11263 | else | |
11264 | { | |
c0ebe874 | 11265 | if (breg == op[0]) |
252b5132 RH |
11266 | { |
11267 | /* We must add in the base register now, as in the | |
f5040a92 | 11268 | external symbol case. */ |
9c2799c2 | 11269 | gas_assert (tempreg == AT); |
269137b2 | 11270 | load_delay_nop (); |
67c0d1eb | 11271 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11272 | op[0], AT, breg); |
11273 | tempreg = op[0]; | |
252b5132 | 11274 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11275 | it in in both cases. */ |
252b5132 RH |
11276 | breg = 0; |
11277 | } | |
11278 | ||
67c0d1eb RS |
11279 | macro_build_lui (&expr1, AT); |
11280 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11281 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11282 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11283 | tempreg, tempreg, AT); |
8fc2e39e | 11284 | used_at = 1; |
252b5132 | 11285 | } |
4d7206a2 | 11286 | relax_end (); |
252b5132 | 11287 | } |
0a44bf69 | 11288 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11289 | { |
f5040a92 AO |
11290 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11291 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11292 | int add_breg_early = 0; |
f5040a92 AO |
11293 | |
11294 | /* This is the large GOT case. If this is a reference to an | |
11295 | external symbol, and there is no constant, we want | |
11296 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11297 | add $tempreg,$tempreg,$gp | |
11298 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11299 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11300 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11301 | add $tempreg,$tempreg,$gp | |
11302 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11303 | ||
11304 | If we have a small constant, and this is a reference to | |
11305 | an external symbol, we want | |
11306 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11307 | add $tempreg,$tempreg,$gp | |
11308 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11309 | addi $tempreg,$tempreg,<constant> | |
11310 | ||
11311 | If we have a large constant, and this is a reference to | |
11312 | an external symbol, we want | |
11313 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11314 | addu $tempreg,$tempreg,$gp | |
11315 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11316 | lui $at,<hiconstant> | |
11317 | addi $at,$at,<loconstant> | |
11318 | add $tempreg,$tempreg,$at | |
11319 | ||
11320 | If we have NewABI, and we know it's a local symbol, we want | |
11321 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11322 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11323 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11324 | ||
4d7206a2 | 11325 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11326 | |
4d7206a2 | 11327 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11328 | offset_expr.X_add_number = 0; |
11329 | ||
1abe91b1 MR |
11330 | if (expr1.X_add_number == 0 && breg == 0 |
11331 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11332 | { |
11333 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11334 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11335 | } | |
df58fc94 | 11336 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11337 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11338 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11339 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11340 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11341 | |
11342 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11343 | ; |
f5040a92 AO |
11344 | else if (expr1.X_add_number >= -0x8000 |
11345 | && expr1.X_add_number < 0x8000) | |
11346 | { | |
67c0d1eb | 11347 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11348 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11349 | } |
ecd13cd3 | 11350 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11351 | { |
c0ebe874 RS |
11352 | unsigned int dreg; |
11353 | ||
f5040a92 AO |
11354 | /* If we are going to add in a base register, and the |
11355 | target register and the base register are the same, | |
11356 | then we are using AT as a temporary register. Since | |
11357 | we want to load the constant into AT, we add our | |
11358 | current AT (from the global offset table) and the | |
11359 | register into the register now, and pretend we were | |
11360 | not using a base register. */ | |
c0ebe874 | 11361 | if (breg != op[0]) |
f5040a92 AO |
11362 | dreg = tempreg; |
11363 | else | |
11364 | { | |
9c2799c2 | 11365 | gas_assert (tempreg == AT); |
67c0d1eb | 11366 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11367 | op[0], AT, breg); |
11368 | dreg = op[0]; | |
67c0d1eb | 11369 | add_breg_early = 1; |
f5040a92 AO |
11370 | } |
11371 | ||
f6a22291 | 11372 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11374 | |
f5040a92 AO |
11375 | used_at = 1; |
11376 | } | |
11377 | else | |
11378 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11379 | ||
4d7206a2 | 11380 | relax_switch (); |
f5040a92 | 11381 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11382 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11383 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11384 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11385 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11386 | if (add_breg_early) | |
f5040a92 | 11387 | { |
67c0d1eb | 11388 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11389 | op[0], tempreg, breg); |
f5040a92 | 11390 | breg = 0; |
c0ebe874 | 11391 | tempreg = op[0]; |
f5040a92 | 11392 | } |
4d7206a2 | 11393 | relax_end (); |
f5040a92 | 11394 | } |
252b5132 RH |
11395 | else |
11396 | abort (); | |
11397 | ||
11398 | if (breg != 0) | |
c0ebe874 | 11399 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11400 | break; |
11401 | ||
52b6b6b9 | 11402 | case M_MSGSND: |
df58fc94 | 11403 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11404 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11405 | break; |
52b6b6b9 JM |
11406 | |
11407 | case M_MSGLD: | |
df58fc94 | 11408 | gas_assert (!mips_opts.micromips); |
c8276761 | 11409 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11410 | break; |
52b6b6b9 JM |
11411 | |
11412 | case M_MSGLD_T: | |
df58fc94 | 11413 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11414 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11415 | break; |
52b6b6b9 JM |
11416 | |
11417 | case M_MSGWAIT: | |
df58fc94 | 11418 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11419 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11420 | break; |
52b6b6b9 JM |
11421 | |
11422 | case M_MSGWAIT_T: | |
df58fc94 | 11423 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11424 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11425 | break; |
52b6b6b9 | 11426 | |
252b5132 RH |
11427 | case M_J_A: |
11428 | /* The j instruction may not be used in PIC code, since it | |
11429 | requires an absolute address. We convert it to a b | |
11430 | instruction. */ | |
11431 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11432 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11433 | else |
67c0d1eb | 11434 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11435 | break; |
252b5132 RH |
11436 | |
11437 | /* The jal instructions must be handled as macros because when | |
11438 | generating PIC code they expand to multi-instruction | |
11439 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11440 | case M_JALS_1: |
c0ebe874 RS |
11441 | op[1] = op[0]; |
11442 | op[0] = RA; | |
df58fc94 RS |
11443 | /* Fall through. */ |
11444 | case M_JALS_2: | |
11445 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11446 | if (mips_opts.insn32) |
11447 | { | |
1661c76c | 11448 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11449 | break; |
11450 | } | |
df58fc94 RS |
11451 | jals = 1; |
11452 | goto jal; | |
252b5132 | 11453 | case M_JAL_1: |
c0ebe874 RS |
11454 | op[1] = op[0]; |
11455 | op[0] = RA; | |
252b5132 RH |
11456 | /* Fall through. */ |
11457 | case M_JAL_2: | |
df58fc94 | 11458 | jal: |
3e722fb5 | 11459 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11460 | { |
11461 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11462 | if (mips_opts.micromips |
833794fc | 11463 | && !mips_opts.insn32 |
c0ebe874 | 11464 | && op[0] == RA |
e64af278 | 11465 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11466 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11467 | else |
c0ebe874 | 11468 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11469 | } |
0a44bf69 | 11470 | else |
252b5132 | 11471 | { |
df58fc94 RS |
11472 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11473 | && mips_cprestore_offset >= 0); | |
11474 | ||
c0ebe874 | 11475 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11476 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11477 | |
833794fc MR |
11478 | s = ((mips_opts.micromips |
11479 | && !mips_opts.insn32 | |
11480 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11481 | ? "jalrs" : "jalr"); |
e64af278 | 11482 | if (mips_opts.micromips |
833794fc | 11483 | && !mips_opts.insn32 |
c0ebe874 | 11484 | && op[0] == RA |
e64af278 | 11485 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11486 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11487 | else |
c0ebe874 | 11488 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11489 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11490 | { |
6478892d | 11491 | if (mips_cprestore_offset < 0) |
1661c76c | 11492 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11493 | else |
11494 | { | |
90ecf173 | 11495 | if (!mips_frame_reg_valid) |
7a621144 | 11496 | { |
1661c76c | 11497 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11498 | /* Quiet this warning. */ |
11499 | mips_frame_reg_valid = 1; | |
11500 | } | |
90ecf173 | 11501 | if (!mips_cprestore_valid) |
7a621144 | 11502 | { |
1661c76c | 11503 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11504 | /* Quiet this warning. */ |
11505 | mips_cprestore_valid = 1; | |
11506 | } | |
d3fca0b5 MR |
11507 | if (mips_opts.noreorder) |
11508 | macro_build (NULL, "nop", ""); | |
6478892d | 11509 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11510 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11511 | mips_gp_register, |
256ab948 TS |
11512 | mips_frame_reg, |
11513 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11514 | } |
252b5132 RH |
11515 | } |
11516 | } | |
252b5132 | 11517 | |
8fc2e39e | 11518 | break; |
252b5132 | 11519 | |
df58fc94 RS |
11520 | case M_JALS_A: |
11521 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11522 | if (mips_opts.insn32) |
11523 | { | |
1661c76c | 11524 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11525 | break; |
11526 | } | |
df58fc94 RS |
11527 | jals = 1; |
11528 | /* Fall through. */ | |
252b5132 RH |
11529 | case M_JAL_A: |
11530 | if (mips_pic == NO_PIC) | |
df58fc94 | 11531 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11532 | else if (mips_pic == SVR4_PIC) |
11533 | { | |
11534 | /* If this is a reference to an external symbol, and we are | |
11535 | using a small GOT, we want | |
11536 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11537 | nop | |
f9419b05 | 11538 | jalr $ra,$25 |
252b5132 RH |
11539 | nop |
11540 | lw $gp,cprestore($sp) | |
11541 | The cprestore value is set using the .cprestore | |
11542 | pseudo-op. If we are using a big GOT, we want | |
11543 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11544 | addu $25,$25,$gp | |
11545 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11546 | nop | |
f9419b05 | 11547 | jalr $ra,$25 |
252b5132 RH |
11548 | nop |
11549 | lw $gp,cprestore($sp) | |
11550 | If the symbol is not external, we want | |
11551 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11552 | nop | |
11553 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11554 | jalr $ra,$25 |
252b5132 | 11555 | nop |
438c16b8 | 11556 | lw $gp,cprestore($sp) |
f5040a92 AO |
11557 | |
11558 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11559 | sequences above, minus nops, unless the symbol is local, | |
11560 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11561 | GOT_DISP. */ | |
438c16b8 | 11562 | if (HAVE_NEWABI) |
252b5132 | 11563 | { |
90ecf173 | 11564 | if (!mips_big_got) |
f5040a92 | 11565 | { |
4d7206a2 | 11566 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11567 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11568 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11569 | mips_gp_register); |
4d7206a2 | 11570 | relax_switch (); |
67c0d1eb RS |
11571 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11572 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11573 | mips_gp_register); |
11574 | relax_end (); | |
f5040a92 AO |
11575 | } |
11576 | else | |
11577 | { | |
4d7206a2 | 11578 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11579 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11580 | BFD_RELOC_MIPS_CALL_HI16); |
11581 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11582 | PIC_CALL_REG, mips_gp_register); | |
11583 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11584 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11585 | PIC_CALL_REG); | |
4d7206a2 | 11586 | relax_switch (); |
67c0d1eb RS |
11587 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11588 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11589 | mips_gp_register); | |
11590 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11591 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11592 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11593 | relax_end (); |
f5040a92 | 11594 | } |
684022ea | 11595 | |
df58fc94 | 11596 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11597 | } |
11598 | else | |
11599 | { | |
4d7206a2 | 11600 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11601 | if (!mips_big_got) |
438c16b8 | 11602 | { |
67c0d1eb RS |
11603 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11604 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11605 | mips_gp_register); |
269137b2 | 11606 | load_delay_nop (); |
4d7206a2 | 11607 | relax_switch (); |
438c16b8 | 11608 | } |
252b5132 | 11609 | else |
252b5132 | 11610 | { |
67c0d1eb RS |
11611 | int gpdelay; |
11612 | ||
11613 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11614 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11615 | BFD_RELOC_MIPS_CALL_HI16); |
11616 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11617 | PIC_CALL_REG, mips_gp_register); | |
11618 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11619 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11620 | PIC_CALL_REG); | |
269137b2 | 11621 | load_delay_nop (); |
4d7206a2 | 11622 | relax_switch (); |
67c0d1eb RS |
11623 | if (gpdelay) |
11624 | macro_build (NULL, "nop", ""); | |
252b5132 | 11625 | } |
67c0d1eb RS |
11626 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11627 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11628 | mips_gp_register); |
269137b2 | 11629 | load_delay_nop (); |
67c0d1eb RS |
11630 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11631 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11632 | relax_end (); |
df58fc94 | 11633 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11634 | |
6478892d | 11635 | if (mips_cprestore_offset < 0) |
1661c76c | 11636 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11637 | else |
11638 | { | |
90ecf173 | 11639 | if (!mips_frame_reg_valid) |
7a621144 | 11640 | { |
1661c76c | 11641 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11642 | /* Quiet this warning. */ |
11643 | mips_frame_reg_valid = 1; | |
11644 | } | |
90ecf173 | 11645 | if (!mips_cprestore_valid) |
7a621144 | 11646 | { |
1661c76c | 11647 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11648 | /* Quiet this warning. */ |
11649 | mips_cprestore_valid = 1; | |
11650 | } | |
6478892d | 11651 | if (mips_opts.noreorder) |
67c0d1eb | 11652 | macro_build (NULL, "nop", ""); |
6478892d | 11653 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11654 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11655 | mips_gp_register, |
256ab948 TS |
11656 | mips_frame_reg, |
11657 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11658 | } |
252b5132 RH |
11659 | } |
11660 | } | |
0a44bf69 | 11661 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11662 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11663 | else |
11664 | abort (); | |
11665 | ||
8fc2e39e | 11666 | break; |
252b5132 | 11667 | |
7f3c4072 | 11668 | case M_LBUE_AB: |
7f3c4072 CM |
11669 | s = "lbue"; |
11670 | fmt = "t,+j(b)"; | |
11671 | offbits = 9; | |
11672 | goto ld_st; | |
11673 | case M_LHUE_AB: | |
7f3c4072 CM |
11674 | s = "lhue"; |
11675 | fmt = "t,+j(b)"; | |
11676 | offbits = 9; | |
11677 | goto ld_st; | |
11678 | case M_LBE_AB: | |
7f3c4072 CM |
11679 | s = "lbe"; |
11680 | fmt = "t,+j(b)"; | |
11681 | offbits = 9; | |
11682 | goto ld_st; | |
11683 | case M_LHE_AB: | |
7f3c4072 CM |
11684 | s = "lhe"; |
11685 | fmt = "t,+j(b)"; | |
11686 | offbits = 9; | |
11687 | goto ld_st; | |
11688 | case M_LLE_AB: | |
7f3c4072 CM |
11689 | s = "lle"; |
11690 | fmt = "t,+j(b)"; | |
11691 | offbits = 9; | |
11692 | goto ld_st; | |
11693 | case M_LWE_AB: | |
7f3c4072 CM |
11694 | s = "lwe"; |
11695 | fmt = "t,+j(b)"; | |
11696 | offbits = 9; | |
11697 | goto ld_st; | |
11698 | case M_LWLE_AB: | |
7f3c4072 CM |
11699 | s = "lwle"; |
11700 | fmt = "t,+j(b)"; | |
11701 | offbits = 9; | |
11702 | goto ld_st; | |
11703 | case M_LWRE_AB: | |
7f3c4072 CM |
11704 | s = "lwre"; |
11705 | fmt = "t,+j(b)"; | |
11706 | offbits = 9; | |
11707 | goto ld_st; | |
11708 | case M_SBE_AB: | |
7f3c4072 CM |
11709 | s = "sbe"; |
11710 | fmt = "t,+j(b)"; | |
11711 | offbits = 9; | |
11712 | goto ld_st; | |
11713 | case M_SCE_AB: | |
7f3c4072 CM |
11714 | s = "sce"; |
11715 | fmt = "t,+j(b)"; | |
11716 | offbits = 9; | |
11717 | goto ld_st; | |
11718 | case M_SHE_AB: | |
7f3c4072 CM |
11719 | s = "she"; |
11720 | fmt = "t,+j(b)"; | |
11721 | offbits = 9; | |
11722 | goto ld_st; | |
11723 | case M_SWE_AB: | |
7f3c4072 CM |
11724 | s = "swe"; |
11725 | fmt = "t,+j(b)"; | |
11726 | offbits = 9; | |
11727 | goto ld_st; | |
11728 | case M_SWLE_AB: | |
7f3c4072 CM |
11729 | s = "swle"; |
11730 | fmt = "t,+j(b)"; | |
11731 | offbits = 9; | |
11732 | goto ld_st; | |
11733 | case M_SWRE_AB: | |
7f3c4072 CM |
11734 | s = "swre"; |
11735 | fmt = "t,+j(b)"; | |
11736 | offbits = 9; | |
11737 | goto ld_st; | |
dec0624d | 11738 | case M_ACLR_AB: |
dec0624d | 11739 | s = "aclr"; |
dec0624d | 11740 | fmt = "\\,~(b)"; |
7f3c4072 | 11741 | offbits = 12; |
dec0624d MR |
11742 | goto ld_st; |
11743 | case M_ASET_AB: | |
dec0624d | 11744 | s = "aset"; |
dec0624d | 11745 | fmt = "\\,~(b)"; |
7f3c4072 | 11746 | offbits = 12; |
dec0624d | 11747 | goto ld_st; |
252b5132 RH |
11748 | case M_LB_AB: |
11749 | s = "lb"; | |
df58fc94 | 11750 | fmt = "t,o(b)"; |
252b5132 RH |
11751 | goto ld; |
11752 | case M_LBU_AB: | |
11753 | s = "lbu"; | |
df58fc94 | 11754 | fmt = "t,o(b)"; |
252b5132 RH |
11755 | goto ld; |
11756 | case M_LH_AB: | |
11757 | s = "lh"; | |
df58fc94 | 11758 | fmt = "t,o(b)"; |
252b5132 RH |
11759 | goto ld; |
11760 | case M_LHU_AB: | |
11761 | s = "lhu"; | |
df58fc94 | 11762 | fmt = "t,o(b)"; |
252b5132 RH |
11763 | goto ld; |
11764 | case M_LW_AB: | |
11765 | s = "lw"; | |
df58fc94 | 11766 | fmt = "t,o(b)"; |
252b5132 RH |
11767 | goto ld; |
11768 | case M_LWC0_AB: | |
df58fc94 | 11769 | gas_assert (!mips_opts.micromips); |
252b5132 | 11770 | s = "lwc0"; |
df58fc94 | 11771 | fmt = "E,o(b)"; |
bdaaa2e1 | 11772 | /* Itbl support may require additional care here. */ |
252b5132 | 11773 | coproc = 1; |
df58fc94 | 11774 | goto ld_st; |
252b5132 RH |
11775 | case M_LWC1_AB: |
11776 | s = "lwc1"; | |
df58fc94 | 11777 | fmt = "T,o(b)"; |
bdaaa2e1 | 11778 | /* Itbl support may require additional care here. */ |
252b5132 | 11779 | coproc = 1; |
df58fc94 | 11780 | goto ld_st; |
252b5132 RH |
11781 | case M_LWC2_AB: |
11782 | s = "lwc2"; | |
df58fc94 | 11783 | fmt = COP12_FMT; |
7361da2c AB |
11784 | offbits = (mips_opts.micromips ? 12 |
11785 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11786 | : 16); | |
bdaaa2e1 | 11787 | /* Itbl support may require additional care here. */ |
252b5132 | 11788 | coproc = 1; |
df58fc94 | 11789 | goto ld_st; |
252b5132 | 11790 | case M_LWC3_AB: |
df58fc94 | 11791 | gas_assert (!mips_opts.micromips); |
252b5132 | 11792 | s = "lwc3"; |
df58fc94 | 11793 | fmt = "E,o(b)"; |
bdaaa2e1 | 11794 | /* Itbl support may require additional care here. */ |
252b5132 | 11795 | coproc = 1; |
df58fc94 | 11796 | goto ld_st; |
252b5132 RH |
11797 | case M_LWL_AB: |
11798 | s = "lwl"; | |
df58fc94 | 11799 | fmt = MEM12_FMT; |
7f3c4072 | 11800 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11801 | goto ld_st; |
252b5132 RH |
11802 | case M_LWR_AB: |
11803 | s = "lwr"; | |
df58fc94 | 11804 | fmt = MEM12_FMT; |
7f3c4072 | 11805 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11806 | goto ld_st; |
252b5132 | 11807 | case M_LDC1_AB: |
252b5132 | 11808 | s = "ldc1"; |
df58fc94 | 11809 | fmt = "T,o(b)"; |
bdaaa2e1 | 11810 | /* Itbl support may require additional care here. */ |
252b5132 | 11811 | coproc = 1; |
df58fc94 | 11812 | goto ld_st; |
252b5132 RH |
11813 | case M_LDC2_AB: |
11814 | s = "ldc2"; | |
df58fc94 | 11815 | fmt = COP12_FMT; |
7361da2c AB |
11816 | offbits = (mips_opts.micromips ? 12 |
11817 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11818 | : 16); | |
bdaaa2e1 | 11819 | /* Itbl support may require additional care here. */ |
252b5132 | 11820 | coproc = 1; |
df58fc94 | 11821 | goto ld_st; |
c77c0862 | 11822 | case M_LQC2_AB: |
c77c0862 | 11823 | s = "lqc2"; |
14daeee3 | 11824 | fmt = "+7,o(b)"; |
c77c0862 RS |
11825 | /* Itbl support may require additional care here. */ |
11826 | coproc = 1; | |
11827 | goto ld_st; | |
252b5132 RH |
11828 | case M_LDC3_AB: |
11829 | s = "ldc3"; | |
df58fc94 | 11830 | fmt = "E,o(b)"; |
bdaaa2e1 | 11831 | /* Itbl support may require additional care here. */ |
252b5132 | 11832 | coproc = 1; |
df58fc94 | 11833 | goto ld_st; |
252b5132 RH |
11834 | case M_LDL_AB: |
11835 | s = "ldl"; | |
df58fc94 | 11836 | fmt = MEM12_FMT; |
7f3c4072 | 11837 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11838 | goto ld_st; |
252b5132 RH |
11839 | case M_LDR_AB: |
11840 | s = "ldr"; | |
df58fc94 | 11841 | fmt = MEM12_FMT; |
7f3c4072 | 11842 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11843 | goto ld_st; |
252b5132 RH |
11844 | case M_LL_AB: |
11845 | s = "ll"; | |
7361da2c AB |
11846 | fmt = LL_SC_FMT; |
11847 | offbits = (mips_opts.micromips ? 12 | |
11848 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11849 | : 16); | |
252b5132 RH |
11850 | goto ld; |
11851 | case M_LLD_AB: | |
11852 | s = "lld"; | |
7361da2c AB |
11853 | fmt = LL_SC_FMT; |
11854 | offbits = (mips_opts.micromips ? 12 | |
11855 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11856 | : 16); | |
252b5132 RH |
11857 | goto ld; |
11858 | case M_LWU_AB: | |
11859 | s = "lwu"; | |
df58fc94 | 11860 | fmt = MEM12_FMT; |
7f3c4072 | 11861 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11862 | goto ld; |
11863 | case M_LWP_AB: | |
df58fc94 RS |
11864 | gas_assert (mips_opts.micromips); |
11865 | s = "lwp"; | |
11866 | fmt = "t,~(b)"; | |
7f3c4072 | 11867 | offbits = 12; |
df58fc94 RS |
11868 | lp = 1; |
11869 | goto ld; | |
11870 | case M_LDP_AB: | |
df58fc94 RS |
11871 | gas_assert (mips_opts.micromips); |
11872 | s = "ldp"; | |
11873 | fmt = "t,~(b)"; | |
7f3c4072 | 11874 | offbits = 12; |
df58fc94 RS |
11875 | lp = 1; |
11876 | goto ld; | |
11877 | case M_LWM_AB: | |
df58fc94 RS |
11878 | gas_assert (mips_opts.micromips); |
11879 | s = "lwm"; | |
11880 | fmt = "n,~(b)"; | |
7f3c4072 | 11881 | offbits = 12; |
df58fc94 RS |
11882 | goto ld_st; |
11883 | case M_LDM_AB: | |
df58fc94 RS |
11884 | gas_assert (mips_opts.micromips); |
11885 | s = "ldm"; | |
11886 | fmt = "n,~(b)"; | |
7f3c4072 | 11887 | offbits = 12; |
df58fc94 RS |
11888 | goto ld_st; |
11889 | ||
252b5132 | 11890 | ld: |
f19ccbda | 11891 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11892 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11893 | goto ld_st; |
252b5132 | 11894 | else |
c0ebe874 | 11895 | tempreg = op[0] + lp; |
df58fc94 RS |
11896 | goto ld_noat; |
11897 | ||
252b5132 RH |
11898 | case M_SB_AB: |
11899 | s = "sb"; | |
df58fc94 RS |
11900 | fmt = "t,o(b)"; |
11901 | goto ld_st; | |
252b5132 RH |
11902 | case M_SH_AB: |
11903 | s = "sh"; | |
df58fc94 RS |
11904 | fmt = "t,o(b)"; |
11905 | goto ld_st; | |
252b5132 RH |
11906 | case M_SW_AB: |
11907 | s = "sw"; | |
df58fc94 RS |
11908 | fmt = "t,o(b)"; |
11909 | goto ld_st; | |
252b5132 | 11910 | case M_SWC0_AB: |
df58fc94 | 11911 | gas_assert (!mips_opts.micromips); |
252b5132 | 11912 | s = "swc0"; |
df58fc94 | 11913 | fmt = "E,o(b)"; |
bdaaa2e1 | 11914 | /* Itbl support may require additional care here. */ |
252b5132 | 11915 | coproc = 1; |
df58fc94 | 11916 | goto ld_st; |
252b5132 RH |
11917 | case M_SWC1_AB: |
11918 | s = "swc1"; | |
df58fc94 | 11919 | fmt = "T,o(b)"; |
bdaaa2e1 | 11920 | /* Itbl support may require additional care here. */ |
252b5132 | 11921 | coproc = 1; |
df58fc94 | 11922 | goto ld_st; |
252b5132 RH |
11923 | case M_SWC2_AB: |
11924 | s = "swc2"; | |
df58fc94 | 11925 | fmt = COP12_FMT; |
7361da2c AB |
11926 | offbits = (mips_opts.micromips ? 12 |
11927 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11928 | : 16); | |
bdaaa2e1 | 11929 | /* Itbl support may require additional care here. */ |
252b5132 | 11930 | coproc = 1; |
df58fc94 | 11931 | goto ld_st; |
252b5132 | 11932 | case M_SWC3_AB: |
df58fc94 | 11933 | gas_assert (!mips_opts.micromips); |
252b5132 | 11934 | s = "swc3"; |
df58fc94 | 11935 | fmt = "E,o(b)"; |
bdaaa2e1 | 11936 | /* Itbl support may require additional care here. */ |
252b5132 | 11937 | coproc = 1; |
df58fc94 | 11938 | goto ld_st; |
252b5132 RH |
11939 | case M_SWL_AB: |
11940 | s = "swl"; | |
df58fc94 | 11941 | fmt = MEM12_FMT; |
7f3c4072 | 11942 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11943 | goto ld_st; |
252b5132 RH |
11944 | case M_SWR_AB: |
11945 | s = "swr"; | |
df58fc94 | 11946 | fmt = MEM12_FMT; |
7f3c4072 | 11947 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11948 | goto ld_st; |
252b5132 RH |
11949 | case M_SC_AB: |
11950 | s = "sc"; | |
7361da2c AB |
11951 | fmt = LL_SC_FMT; |
11952 | offbits = (mips_opts.micromips ? 12 | |
11953 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11954 | : 16); | |
df58fc94 | 11955 | goto ld_st; |
252b5132 RH |
11956 | case M_SCD_AB: |
11957 | s = "scd"; | |
7361da2c AB |
11958 | fmt = LL_SC_FMT; |
11959 | offbits = (mips_opts.micromips ? 12 | |
11960 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11961 | : 16); | |
df58fc94 | 11962 | goto ld_st; |
d43b4baf TS |
11963 | case M_CACHE_AB: |
11964 | s = "cache"; | |
7361da2c AB |
11965 | fmt = (mips_opts.micromips ? "k,~(b)" |
11966 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11967 | : "k,o(b)"); | |
11968 | offbits = (mips_opts.micromips ? 12 | |
11969 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11970 | : 16); | |
7f3c4072 CM |
11971 | goto ld_st; |
11972 | case M_CACHEE_AB: | |
7f3c4072 CM |
11973 | s = "cachee"; |
11974 | fmt = "k,+j(b)"; | |
11975 | offbits = 9; | |
df58fc94 | 11976 | goto ld_st; |
3eebd5eb MR |
11977 | case M_PREF_AB: |
11978 | s = "pref"; | |
7361da2c AB |
11979 | fmt = (mips_opts.micromips ? "k,~(b)" |
11980 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11981 | : "k,o(b)"); | |
11982 | offbits = (mips_opts.micromips ? 12 | |
11983 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11984 | : 16); | |
7f3c4072 CM |
11985 | goto ld_st; |
11986 | case M_PREFE_AB: | |
7f3c4072 CM |
11987 | s = "prefe"; |
11988 | fmt = "k,+j(b)"; | |
11989 | offbits = 9; | |
df58fc94 | 11990 | goto ld_st; |
252b5132 | 11991 | case M_SDC1_AB: |
252b5132 | 11992 | s = "sdc1"; |
df58fc94 | 11993 | fmt = "T,o(b)"; |
252b5132 | 11994 | coproc = 1; |
bdaaa2e1 | 11995 | /* Itbl support may require additional care here. */ |
df58fc94 | 11996 | goto ld_st; |
252b5132 RH |
11997 | case M_SDC2_AB: |
11998 | s = "sdc2"; | |
df58fc94 | 11999 | fmt = COP12_FMT; |
7361da2c AB |
12000 | offbits = (mips_opts.micromips ? 12 |
12001 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12002 | : 16); | |
c77c0862 RS |
12003 | /* Itbl support may require additional care here. */ |
12004 | coproc = 1; | |
12005 | goto ld_st; | |
12006 | case M_SQC2_AB: | |
c77c0862 | 12007 | s = "sqc2"; |
14daeee3 | 12008 | fmt = "+7,o(b)"; |
bdaaa2e1 | 12009 | /* Itbl support may require additional care here. */ |
252b5132 | 12010 | coproc = 1; |
df58fc94 | 12011 | goto ld_st; |
252b5132 | 12012 | case M_SDC3_AB: |
df58fc94 | 12013 | gas_assert (!mips_opts.micromips); |
252b5132 | 12014 | s = "sdc3"; |
df58fc94 | 12015 | fmt = "E,o(b)"; |
bdaaa2e1 | 12016 | /* Itbl support may require additional care here. */ |
252b5132 | 12017 | coproc = 1; |
df58fc94 | 12018 | goto ld_st; |
252b5132 RH |
12019 | case M_SDL_AB: |
12020 | s = "sdl"; | |
df58fc94 | 12021 | fmt = MEM12_FMT; |
7f3c4072 | 12022 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12023 | goto ld_st; |
252b5132 RH |
12024 | case M_SDR_AB: |
12025 | s = "sdr"; | |
df58fc94 | 12026 | fmt = MEM12_FMT; |
7f3c4072 | 12027 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12028 | goto ld_st; |
12029 | case M_SWP_AB: | |
df58fc94 RS |
12030 | gas_assert (mips_opts.micromips); |
12031 | s = "swp"; | |
12032 | fmt = "t,~(b)"; | |
7f3c4072 | 12033 | offbits = 12; |
df58fc94 RS |
12034 | goto ld_st; |
12035 | case M_SDP_AB: | |
df58fc94 RS |
12036 | gas_assert (mips_opts.micromips); |
12037 | s = "sdp"; | |
12038 | fmt = "t,~(b)"; | |
7f3c4072 | 12039 | offbits = 12; |
df58fc94 RS |
12040 | goto ld_st; |
12041 | case M_SWM_AB: | |
df58fc94 RS |
12042 | gas_assert (mips_opts.micromips); |
12043 | s = "swm"; | |
12044 | fmt = "n,~(b)"; | |
7f3c4072 | 12045 | offbits = 12; |
df58fc94 RS |
12046 | goto ld_st; |
12047 | case M_SDM_AB: | |
df58fc94 RS |
12048 | gas_assert (mips_opts.micromips); |
12049 | s = "sdm"; | |
12050 | fmt = "n,~(b)"; | |
7f3c4072 | 12051 | offbits = 12; |
df58fc94 RS |
12052 | |
12053 | ld_st: | |
8fc2e39e | 12054 | tempreg = AT; |
df58fc94 | 12055 | ld_noat: |
c0ebe874 | 12056 | breg = op[2]; |
f2ae14a1 RS |
12057 | if (small_offset_p (0, align, 16)) |
12058 | { | |
12059 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12060 | macros for o32 but which should act like normal instructions | |
12061 | otherwise. */ | |
12062 | if (offbits == 16) | |
c0ebe874 | 12063 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12064 | offset_reloc[1], offset_reloc[2], breg); |
12065 | else if (small_offset_p (0, align, offbits)) | |
12066 | { | |
12067 | if (offbits == 0) | |
c0ebe874 | 12068 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 12069 | else |
c0ebe874 | 12070 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12071 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12072 | } |
12073 | else | |
12074 | { | |
12075 | if (tempreg == AT) | |
12076 | used_at = 1; | |
12077 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12078 | tempreg, breg, -1, offset_reloc[0], | |
12079 | offset_reloc[1], offset_reloc[2]); | |
12080 | if (offbits == 0) | |
c0ebe874 | 12081 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 12082 | else |
c0ebe874 | 12083 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12084 | } |
12085 | break; | |
12086 | } | |
12087 | ||
12088 | if (tempreg == AT) | |
12089 | used_at = 1; | |
12090 | ||
252b5132 RH |
12091 | if (offset_expr.X_op != O_constant |
12092 | && offset_expr.X_op != O_symbol) | |
12093 | { | |
1661c76c | 12094 | as_bad (_("expression too complex")); |
252b5132 RH |
12095 | offset_expr.X_op = O_constant; |
12096 | } | |
12097 | ||
2051e8c4 MR |
12098 | if (HAVE_32BIT_ADDRESSES |
12099 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12100 | { |
12101 | char value [32]; | |
12102 | ||
12103 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12104 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12105 | } |
2051e8c4 | 12106 | |
252b5132 RH |
12107 | /* A constant expression in PIC code can be handled just as it |
12108 | is in non PIC code. */ | |
aed1a261 RS |
12109 | if (offset_expr.X_op == O_constant) |
12110 | { | |
f2ae14a1 RS |
12111 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12112 | offbits == 0 ? 16 : offbits); | |
12113 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12114 | |
f2ae14a1 RS |
12115 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12116 | if (breg != 0) | |
12117 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12118 | tempreg, tempreg, breg); | |
7f3c4072 | 12119 | if (offbits == 0) |
dd6a37e7 | 12120 | { |
f2ae14a1 | 12121 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12122 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12123 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 12124 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12125 | } |
7f3c4072 | 12126 | else if (offbits == 16) |
c0ebe874 | 12127 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12128 | else |
c0ebe874 | 12129 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12130 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12131 | } |
7f3c4072 | 12132 | else if (offbits != 16) |
df58fc94 | 12133 | { |
7f3c4072 | 12134 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12135 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12136 | register. */ |
12137 | load_address (tempreg, &offset_expr, &used_at); | |
12138 | if (breg != 0) | |
12139 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12140 | tempreg, tempreg, breg); | |
7f3c4072 | 12141 | if (offbits == 0) |
c0ebe874 | 12142 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12143 | else |
c0ebe874 | 12144 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12145 | } |
12146 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12147 | { |
12148 | /* If this is a reference to a GP relative symbol, and there | |
12149 | is no base register, we want | |
c0ebe874 | 12150 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12151 | Otherwise, if there is no base register, we want |
12152 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12153 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12154 | If we have a constant, we need two instructions anyhow, |
12155 | so we always use the latter form. | |
12156 | ||
12157 | If we have a base register, and this is a reference to a | |
12158 | GP relative symbol, we want | |
12159 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12160 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12161 | Otherwise we want |
12162 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12163 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12164 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12165 | With a constant we always use the latter case. |
76b3015f | 12166 | |
d6bc6245 TS |
12167 | With 64bit address space and no base register and $at usable, |
12168 | we want | |
12169 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12170 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12171 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12172 | dsll32 $tempreg,0 | |
12173 | daddu $tempreg,$at | |
c0ebe874 | 12174 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12175 | If we have a base register, we want |
12176 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12177 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12178 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12179 | daddu $at,$breg | |
12180 | dsll32 $tempreg,0 | |
12181 | daddu $tempreg,$at | |
c0ebe874 | 12182 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12183 | |
12184 | Without $at we can't generate the optimal path for superscalar | |
12185 | processors here since this would require two temporary registers. | |
12186 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12187 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12188 | dsll $tempreg,16 | |
12189 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12190 | dsll $tempreg,16 | |
c0ebe874 | 12191 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12192 | If we have a base register, we want |
12193 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12194 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12195 | dsll $tempreg,16 | |
12196 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12197 | dsll $tempreg,16 | |
12198 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12199 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12200 | |
6caf9ef4 | 12201 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12202 | the same sequence as in 32bit address space. */ |
12203 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12204 | { |
aed1a261 | 12205 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12206 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12207 | { | |
12208 | relax_start (offset_expr.X_add_symbol); | |
12209 | if (breg == 0) | |
12210 | { | |
c0ebe874 | 12211 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12212 | BFD_RELOC_GPREL16, mips_gp_register); |
12213 | } | |
12214 | else | |
12215 | { | |
12216 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12217 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12218 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12219 | BFD_RELOC_GPREL16, tempreg); |
12220 | } | |
12221 | relax_switch (); | |
12222 | } | |
d6bc6245 | 12223 | |
741fe287 | 12224 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12225 | { |
df58fc94 | 12226 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12227 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12228 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12229 | BFD_RELOC_HI16_S); |
12230 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12231 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12232 | if (breg != 0) |
67c0d1eb | 12233 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12234 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12235 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12236 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12237 | tempreg); |
d6bc6245 TS |
12238 | used_at = 1; |
12239 | } | |
12240 | else | |
12241 | { | |
df58fc94 | 12242 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12243 | BFD_RELOC_MIPS_HIGHEST); |
12244 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12245 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12246 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12247 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12248 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12249 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12250 | if (breg != 0) |
67c0d1eb | 12251 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12252 | tempreg, tempreg, breg); |
c0ebe874 | 12253 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12254 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12255 | } |
6caf9ef4 TS |
12256 | |
12257 | if (mips_relax.sequence) | |
12258 | relax_end (); | |
8fc2e39e | 12259 | break; |
d6bc6245 | 12260 | } |
256ab948 | 12261 | |
252b5132 RH |
12262 | if (breg == 0) |
12263 | { | |
67c0d1eb | 12264 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12265 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12266 | { |
4d7206a2 | 12267 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12268 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12269 | mips_gp_register); |
4d7206a2 | 12270 | relax_switch (); |
252b5132 | 12271 | } |
67c0d1eb | 12272 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12273 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12274 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12275 | if (mips_relax.sequence) |
12276 | relax_end (); | |
252b5132 RH |
12277 | } |
12278 | else | |
12279 | { | |
67c0d1eb | 12280 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12281 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12282 | { |
4d7206a2 | 12283 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12284 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12285 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12286 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12287 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12288 | relax_switch (); |
252b5132 | 12289 | } |
67c0d1eb RS |
12290 | macro_build_lui (&offset_expr, tempreg); |
12291 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12292 | tempreg, tempreg, breg); |
c0ebe874 | 12293 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12294 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12295 | if (mips_relax.sequence) |
12296 | relax_end (); | |
252b5132 RH |
12297 | } |
12298 | } | |
0a44bf69 | 12299 | else if (!mips_big_got) |
252b5132 | 12300 | { |
ed6fb7bd | 12301 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12302 | |
252b5132 RH |
12303 | /* If this is a reference to an external symbol, we want |
12304 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12305 | nop | |
c0ebe874 | 12306 | <op> op[0],0($tempreg) |
252b5132 RH |
12307 | Otherwise we want |
12308 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12309 | nop | |
12310 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12311 | <op> op[0],0($tempreg) |
f5040a92 AO |
12312 | |
12313 | For NewABI, we want | |
12314 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12315 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12316 | |
252b5132 RH |
12317 | If there is a base register, we add it to $tempreg before |
12318 | the <op>. If there is a constant, we stick it in the | |
12319 | <op> instruction. We don't handle constants larger than | |
12320 | 16 bits, because we have no way to load the upper 16 bits | |
12321 | (actually, we could handle them for the subset of cases | |
12322 | in which we are not using $at). */ | |
9c2799c2 | 12323 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12324 | if (HAVE_NEWABI) |
12325 | { | |
67c0d1eb RS |
12326 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12327 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12328 | if (breg != 0) |
67c0d1eb | 12329 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12330 | tempreg, tempreg, breg); |
c0ebe874 | 12331 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12332 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12333 | break; |
12334 | } | |
252b5132 RH |
12335 | expr1.X_add_number = offset_expr.X_add_number; |
12336 | offset_expr.X_add_number = 0; | |
12337 | if (expr1.X_add_number < -0x8000 | |
12338 | || expr1.X_add_number >= 0x8000) | |
12339 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12340 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12341 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12342 | load_delay_nop (); |
4d7206a2 RS |
12343 | relax_start (offset_expr.X_add_symbol); |
12344 | relax_switch (); | |
67c0d1eb RS |
12345 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12346 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12347 | relax_end (); |
252b5132 | 12348 | if (breg != 0) |
67c0d1eb | 12349 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12350 | tempreg, tempreg, breg); |
c0ebe874 | 12351 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12352 | } |
0a44bf69 | 12353 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12354 | { |
67c0d1eb | 12355 | int gpdelay; |
252b5132 RH |
12356 | |
12357 | /* If this is a reference to an external symbol, we want | |
12358 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12359 | addu $tempreg,$tempreg,$gp | |
12360 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12361 | <op> op[0],0($tempreg) |
252b5132 RH |
12362 | Otherwise we want |
12363 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12364 | nop | |
12365 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12366 | <op> op[0],0($tempreg) |
252b5132 RH |
12367 | If there is a base register, we add it to $tempreg before |
12368 | the <op>. If there is a constant, we stick it in the | |
12369 | <op> instruction. We don't handle constants larger than | |
12370 | 16 bits, because we have no way to load the upper 16 bits | |
12371 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12372 | in which we are not using $at). */ |
9c2799c2 | 12373 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12374 | expr1.X_add_number = offset_expr.X_add_number; |
12375 | offset_expr.X_add_number = 0; | |
12376 | if (expr1.X_add_number < -0x8000 | |
12377 | || expr1.X_add_number >= 0x8000) | |
12378 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12379 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12380 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12381 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12382 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12384 | mips_gp_register); | |
12385 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12386 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12387 | relax_switch (); |
67c0d1eb RS |
12388 | if (gpdelay) |
12389 | macro_build (NULL, "nop", ""); | |
12390 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12391 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12392 | load_delay_nop (); |
67c0d1eb RS |
12393 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12394 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12395 | relax_end (); |
12396 | ||
252b5132 | 12397 | if (breg != 0) |
67c0d1eb | 12398 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12399 | tempreg, tempreg, breg); |
c0ebe874 | 12400 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12401 | } |
0a44bf69 | 12402 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12403 | { |
f5040a92 AO |
12404 | /* If this is a reference to an external symbol, we want |
12405 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12406 | add $tempreg,$tempreg,$gp | |
12407 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12408 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12409 | Otherwise, for local symbols, we want: |
12410 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12411 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12412 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12413 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12414 | offset_expr.X_add_number = 0; |
12415 | if (expr1.X_add_number < -0x8000 | |
12416 | || expr1.X_add_number >= 0x8000) | |
12417 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12418 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12419 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12420 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12421 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12422 | mips_gp_register); | |
12423 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12424 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12425 | if (breg != 0) |
67c0d1eb | 12426 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12427 | tempreg, tempreg, breg); |
c0ebe874 | 12428 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12429 | |
4d7206a2 | 12430 | relax_switch (); |
f5040a92 | 12431 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12432 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12433 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12434 | if (breg != 0) |
67c0d1eb | 12435 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12436 | tempreg, tempreg, breg); |
c0ebe874 | 12437 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12438 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12439 | relax_end (); |
f5040a92 | 12440 | } |
252b5132 RH |
12441 | else |
12442 | abort (); | |
12443 | ||
252b5132 RH |
12444 | break; |
12445 | ||
833794fc MR |
12446 | case M_JRADDIUSP: |
12447 | gas_assert (mips_opts.micromips); | |
12448 | gas_assert (mips_opts.insn32); | |
12449 | start_noreorder (); | |
12450 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12451 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12452 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12453 | end_noreorder (); | |
12454 | break; | |
12455 | ||
12456 | case M_JRC: | |
12457 | gas_assert (mips_opts.micromips); | |
12458 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12459 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12460 | if (mips_opts.noreorder) |
12461 | macro_build (NULL, "nop", ""); | |
12462 | break; | |
12463 | ||
252b5132 RH |
12464 | case M_LI: |
12465 | case M_LI_S: | |
c0ebe874 | 12466 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12467 | break; |
252b5132 RH |
12468 | |
12469 | case M_DLI: | |
c0ebe874 | 12470 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12471 | break; |
252b5132 RH |
12472 | |
12473 | case M_LI_SS: | |
12474 | if (imm_expr.X_op == O_constant) | |
12475 | { | |
8fc2e39e | 12476 | used_at = 1; |
67c0d1eb | 12477 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12478 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12479 | break; |
12480 | } | |
12481 | else | |
12482 | { | |
b0e6f033 RS |
12483 | gas_assert (imm_expr.X_op == O_absent |
12484 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12485 | && strcmp (segment_name (S_GET_SEGMENT |
12486 | (offset_expr.X_add_symbol)), | |
12487 | ".lit4") == 0 | |
12488 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12489 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12490 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12491 | break; |
252b5132 RH |
12492 | } |
12493 | ||
12494 | case M_LI_D: | |
ca4e0257 RS |
12495 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12496 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12497 | order 32 bits of the value and the low order 32 bits are either | |
12498 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12499 | if (imm_expr.X_op == O_constant) |
252b5132 | 12500 | { |
bad1aba3 | 12501 | if (GPR_SIZE == 64) |
c0ebe874 | 12502 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12503 | else |
12504 | { | |
12505 | int hreg, lreg; | |
12506 | ||
12507 | if (target_big_endian) | |
12508 | { | |
c0ebe874 RS |
12509 | hreg = op[0]; |
12510 | lreg = op[0] + 1; | |
252b5132 RH |
12511 | } |
12512 | else | |
12513 | { | |
c0ebe874 RS |
12514 | hreg = op[0] + 1; |
12515 | lreg = op[0]; | |
252b5132 RH |
12516 | } |
12517 | ||
12518 | if (hreg <= 31) | |
67c0d1eb | 12519 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12520 | if (lreg <= 31) |
12521 | { | |
12522 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12523 | move_register (lreg, 0); |
252b5132 RH |
12524 | else |
12525 | { | |
9c2799c2 | 12526 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12527 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12528 | } |
12529 | } | |
12530 | } | |
8fc2e39e | 12531 | break; |
252b5132 | 12532 | } |
b0e6f033 | 12533 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12534 | |
12535 | /* We know that sym is in the .rdata section. First we get the | |
12536 | upper 16 bits of the address. */ | |
12537 | if (mips_pic == NO_PIC) | |
12538 | { | |
67c0d1eb | 12539 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12540 | used_at = 1; |
252b5132 | 12541 | } |
0a44bf69 | 12542 | else |
252b5132 | 12543 | { |
67c0d1eb RS |
12544 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12545 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12546 | used_at = 1; |
252b5132 | 12547 | } |
bdaaa2e1 | 12548 | |
252b5132 | 12549 | /* Now we load the register(s). */ |
bad1aba3 | 12550 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12551 | { |
12552 | used_at = 1; | |
c0ebe874 RS |
12553 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12554 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12555 | } |
252b5132 RH |
12556 | else |
12557 | { | |
8fc2e39e | 12558 | used_at = 1; |
c0ebe874 RS |
12559 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12560 | BFD_RELOC_LO16, AT); | |
12561 | if (op[0] != RA) | |
252b5132 RH |
12562 | { |
12563 | /* FIXME: How in the world do we deal with the possible | |
12564 | overflow here? */ | |
12565 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12566 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12567 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12568 | } |
12569 | } | |
252b5132 RH |
12570 | break; |
12571 | ||
12572 | case M_LI_DD: | |
ca4e0257 RS |
12573 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12574 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12575 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12576 | the value and the low order 32 bits are either zero or in | |
12577 | OFFSET_EXPR. */ | |
b0e6f033 | 12578 | if (imm_expr.X_op == O_constant) |
252b5132 | 12579 | { |
8fc2e39e | 12580 | used_at = 1; |
bad1aba3 | 12581 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12582 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12583 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12584 | else |
12585 | { | |
351cdf24 MF |
12586 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12587 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12588 | else if (FPR_SIZE != 32) | |
12589 | as_bad (_("Unable to generate `%s' compliant code " | |
12590 | "without mthc1"), | |
12591 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12592 | else | |
12593 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12594 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12595 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12596 | else |
12597 | { | |
9c2799c2 | 12598 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12599 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12600 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12601 | } |
12602 | } | |
12603 | break; | |
12604 | } | |
12605 | ||
b0e6f033 RS |
12606 | gas_assert (imm_expr.X_op == O_absent |
12607 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12608 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12609 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12610 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12611 | { |
12612 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12613 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12614 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12615 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12616 | } |
12617 | else | |
12618 | { | |
9c2799c2 | 12619 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12620 | used_at = 1; |
0a44bf69 | 12621 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12622 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12623 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12624 | else |
12625 | { | |
12626 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12627 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12628 | } |
bdaaa2e1 | 12629 | |
c0ebe874 | 12630 | op[2] = AT; |
f2ae14a1 RS |
12631 | offset_reloc[0] = BFD_RELOC_LO16; |
12632 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12633 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12634 | } |
f2ae14a1 RS |
12635 | align = 8; |
12636 | /* Fall through */ | |
c4a68bea | 12637 | |
252b5132 RH |
12638 | case M_L_DAB: |
12639 | /* | |
12640 | * The MIPS assembler seems to check for X_add_number not | |
12641 | * being double aligned and generating: | |
12642 | * lui at,%hi(foo+1) | |
12643 | * addu at,at,v1 | |
12644 | * addiu at,at,%lo(foo+1) | |
12645 | * lwc1 f2,0(at) | |
12646 | * lwc1 f3,4(at) | |
12647 | * But, the resulting address is the same after relocation so why | |
12648 | * generate the extra instruction? | |
12649 | */ | |
bdaaa2e1 | 12650 | /* Itbl support may require additional care here. */ |
252b5132 | 12651 | coproc = 1; |
df58fc94 | 12652 | fmt = "T,o(b)"; |
0aa27725 | 12653 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12654 | { |
12655 | s = "ldc1"; | |
df58fc94 | 12656 | goto ld_st; |
252b5132 | 12657 | } |
252b5132 | 12658 | s = "lwc1"; |
252b5132 RH |
12659 | goto ldd_std; |
12660 | ||
12661 | case M_S_DAB: | |
df58fc94 RS |
12662 | gas_assert (!mips_opts.micromips); |
12663 | /* Itbl support may require additional care here. */ | |
12664 | coproc = 1; | |
12665 | fmt = "T,o(b)"; | |
0aa27725 | 12666 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12667 | { |
12668 | s = "sdc1"; | |
df58fc94 | 12669 | goto ld_st; |
252b5132 | 12670 | } |
252b5132 | 12671 | s = "swc1"; |
252b5132 RH |
12672 | goto ldd_std; |
12673 | ||
e407c74b NC |
12674 | case M_LQ_AB: |
12675 | fmt = "t,o(b)"; | |
12676 | s = "lq"; | |
12677 | goto ld; | |
12678 | ||
12679 | case M_SQ_AB: | |
12680 | fmt = "t,o(b)"; | |
12681 | s = "sq"; | |
12682 | goto ld_st; | |
12683 | ||
252b5132 | 12684 | case M_LD_AB: |
df58fc94 | 12685 | fmt = "t,o(b)"; |
bad1aba3 | 12686 | if (GPR_SIZE == 64) |
252b5132 RH |
12687 | { |
12688 | s = "ld"; | |
12689 | goto ld; | |
12690 | } | |
252b5132 | 12691 | s = "lw"; |
252b5132 RH |
12692 | goto ldd_std; |
12693 | ||
12694 | case M_SD_AB: | |
df58fc94 | 12695 | fmt = "t,o(b)"; |
bad1aba3 | 12696 | if (GPR_SIZE == 64) |
252b5132 RH |
12697 | { |
12698 | s = "sd"; | |
df58fc94 | 12699 | goto ld_st; |
252b5132 | 12700 | } |
252b5132 | 12701 | s = "sw"; |
252b5132 RH |
12702 | |
12703 | ldd_std: | |
f2ae14a1 RS |
12704 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12705 | to adjust when loading from memory. We set coproc if we must | |
12706 | load $fn+1 first. */ | |
12707 | /* Itbl support may require additional care here. */ | |
12708 | if (!target_big_endian) | |
12709 | coproc = 0; | |
12710 | ||
c0ebe874 | 12711 | breg = op[2]; |
f2ae14a1 RS |
12712 | if (small_offset_p (0, align, 16)) |
12713 | { | |
12714 | ep = &offset_expr; | |
12715 | if (!small_offset_p (4, align, 16)) | |
12716 | { | |
12717 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12718 | -1, offset_reloc[0], offset_reloc[1], | |
12719 | offset_reloc[2]); | |
12720 | expr1.X_add_number = 0; | |
12721 | ep = &expr1; | |
12722 | breg = AT; | |
12723 | used_at = 1; | |
12724 | offset_reloc[0] = BFD_RELOC_LO16; | |
12725 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12726 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12727 | } | |
c0ebe874 | 12728 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12729 | { |
12730 | ep->X_add_number += 4; | |
c0ebe874 | 12731 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12732 | offset_reloc[1], offset_reloc[2], breg); |
12733 | ep->X_add_number -= 4; | |
c0ebe874 | 12734 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12735 | offset_reloc[1], offset_reloc[2], breg); |
12736 | } | |
12737 | else | |
12738 | { | |
c0ebe874 | 12739 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12740 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12741 | breg); | |
12742 | ep->X_add_number += 4; | |
c0ebe874 | 12743 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12744 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12745 | breg); | |
12746 | } | |
12747 | break; | |
12748 | } | |
12749 | ||
252b5132 RH |
12750 | if (offset_expr.X_op != O_symbol |
12751 | && offset_expr.X_op != O_constant) | |
12752 | { | |
1661c76c | 12753 | as_bad (_("expression too complex")); |
252b5132 RH |
12754 | offset_expr.X_op = O_constant; |
12755 | } | |
12756 | ||
2051e8c4 MR |
12757 | if (HAVE_32BIT_ADDRESSES |
12758 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12759 | { |
12760 | char value [32]; | |
12761 | ||
12762 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12763 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12764 | } |
2051e8c4 | 12765 | |
90ecf173 | 12766 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12767 | { |
12768 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12769 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12770 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12771 | If we have a base register, we use this |
12772 | addu $at,$breg,$gp | |
c0ebe874 RS |
12773 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12774 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12775 | If this is not a GP relative symbol, we want |
12776 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12777 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12778 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12779 | If there is a base register, we add it to $at after the |
12780 | lui instruction. If there is a constant, we always use | |
12781 | the last case. */ | |
39a59cf8 MR |
12782 | if (offset_expr.X_op == O_symbol |
12783 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12784 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12785 | { |
4d7206a2 | 12786 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12787 | if (breg == 0) |
12788 | { | |
c9914766 | 12789 | tempreg = mips_gp_register; |
252b5132 RH |
12790 | } |
12791 | else | |
12792 | { | |
67c0d1eb | 12793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12794 | AT, breg, mips_gp_register); |
252b5132 | 12795 | tempreg = AT; |
252b5132 RH |
12796 | used_at = 1; |
12797 | } | |
12798 | ||
beae10d5 | 12799 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12800 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12801 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12802 | offset_expr.X_add_number += 4; |
12803 | ||
12804 | /* Set mips_optimize to 2 to avoid inserting an | |
12805 | undesired nop. */ | |
12806 | hold_mips_optimize = mips_optimize; | |
12807 | mips_optimize = 2; | |
beae10d5 | 12808 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12809 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12810 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12811 | mips_optimize = hold_mips_optimize; |
12812 | ||
4d7206a2 | 12813 | relax_switch (); |
252b5132 | 12814 | |
0970e49e | 12815 | offset_expr.X_add_number -= 4; |
252b5132 | 12816 | } |
8fc2e39e | 12817 | used_at = 1; |
f2ae14a1 RS |
12818 | if (offset_high_part (offset_expr.X_add_number, 16) |
12819 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12820 | { | |
12821 | load_address (AT, &offset_expr, &used_at); | |
12822 | offset_expr.X_op = O_constant; | |
12823 | offset_expr.X_add_number = 0; | |
12824 | } | |
12825 | else | |
12826 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12827 | if (breg != 0) |
67c0d1eb | 12828 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12829 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12830 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12831 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12832 | /* FIXME: How do we handle overflow here? */ |
12833 | offset_expr.X_add_number += 4; | |
beae10d5 | 12834 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12835 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12836 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12837 | if (mips_relax.sequence) |
12838 | relax_end (); | |
bdaaa2e1 | 12839 | } |
0a44bf69 | 12840 | else if (!mips_big_got) |
252b5132 | 12841 | { |
252b5132 RH |
12842 | /* If this is a reference to an external symbol, we want |
12843 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12844 | nop | |
c0ebe874 RS |
12845 | <op> op[0],0($at) |
12846 | <op> op[0]+1,4($at) | |
252b5132 RH |
12847 | Otherwise we want |
12848 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12849 | nop | |
c0ebe874 RS |
12850 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12851 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12852 | If there is a base register we add it to $at before the |
12853 | lwc1 instructions. If there is a constant we include it | |
12854 | in the lwc1 instructions. */ | |
12855 | used_at = 1; | |
12856 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12857 | if (expr1.X_add_number < -0x8000 |
12858 | || expr1.X_add_number >= 0x8000 - 4) | |
12859 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12860 | load_got_offset (AT, &offset_expr); |
269137b2 | 12861 | load_delay_nop (); |
252b5132 | 12862 | if (breg != 0) |
67c0d1eb | 12863 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12864 | |
12865 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12866 | nop. */ | |
12867 | hold_mips_optimize = mips_optimize; | |
12868 | mips_optimize = 2; | |
4d7206a2 | 12869 | |
beae10d5 | 12870 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12871 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12872 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12873 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12874 | expr1.X_add_number += 4; |
c0ebe874 | 12875 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12876 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12877 | relax_switch (); |
c0ebe874 | 12878 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12879 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12880 | offset_expr.X_add_number += 4; |
c0ebe874 | 12881 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12882 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12883 | relax_end (); |
252b5132 | 12884 | |
4d7206a2 | 12885 | mips_optimize = hold_mips_optimize; |
252b5132 | 12886 | } |
0a44bf69 | 12887 | else if (mips_big_got) |
252b5132 | 12888 | { |
67c0d1eb | 12889 | int gpdelay; |
252b5132 RH |
12890 | |
12891 | /* If this is a reference to an external symbol, we want | |
12892 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12893 | addu $at,$at,$gp | |
12894 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12895 | nop | |
c0ebe874 RS |
12896 | <op> op[0],0($at) |
12897 | <op> op[0]+1,4($at) | |
252b5132 RH |
12898 | Otherwise we want |
12899 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12900 | nop | |
c0ebe874 RS |
12901 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12902 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12903 | If there is a base register we add it to $at before the |
12904 | lwc1 instructions. If there is a constant we include it | |
12905 | in the lwc1 instructions. */ | |
12906 | used_at = 1; | |
12907 | expr1.X_add_number = offset_expr.X_add_number; | |
12908 | offset_expr.X_add_number = 0; | |
12909 | if (expr1.X_add_number < -0x8000 | |
12910 | || expr1.X_add_number >= 0x8000 - 4) | |
12911 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12912 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12913 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12914 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12915 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12916 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12917 | AT, AT, mips_gp_register); |
67c0d1eb | 12918 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12919 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12920 | load_delay_nop (); |
252b5132 | 12921 | if (breg != 0) |
67c0d1eb | 12922 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12923 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12924 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12925 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12926 | expr1.X_add_number += 4; |
12927 | ||
12928 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12929 | nop. */ | |
12930 | hold_mips_optimize = mips_optimize; | |
12931 | mips_optimize = 2; | |
beae10d5 | 12932 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12933 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12934 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12935 | mips_optimize = hold_mips_optimize; |
12936 | expr1.X_add_number -= 4; | |
12937 | ||
4d7206a2 RS |
12938 | relax_switch (); |
12939 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12940 | if (gpdelay) |
12941 | macro_build (NULL, "nop", ""); | |
12942 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12943 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12944 | load_delay_nop (); |
252b5132 | 12945 | if (breg != 0) |
67c0d1eb | 12946 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12947 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12948 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12949 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12950 | offset_expr.X_add_number += 4; |
252b5132 RH |
12951 | |
12952 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12953 | nop. */ | |
12954 | hold_mips_optimize = mips_optimize; | |
12955 | mips_optimize = 2; | |
beae10d5 | 12956 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12957 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12958 | BFD_RELOC_LO16, AT); |
252b5132 | 12959 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12960 | relax_end (); |
252b5132 | 12961 | } |
252b5132 RH |
12962 | else |
12963 | abort (); | |
12964 | ||
252b5132 | 12965 | break; |
3739860c | 12966 | |
dd6a37e7 | 12967 | case M_SAA_AB: |
dd6a37e7 | 12968 | s = "saa"; |
0db377d0 | 12969 | goto saa_saad; |
dd6a37e7 | 12970 | case M_SAAD_AB: |
dd6a37e7 | 12971 | s = "saad"; |
0db377d0 MR |
12972 | saa_saad: |
12973 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12974 | offbits = 0; |
dd6a37e7 AP |
12975 | fmt = "t,(b)"; |
12976 | goto ld_st; | |
12977 | ||
252b5132 RH |
12978 | /* New code added to support COPZ instructions. |
12979 | This code builds table entries out of the macros in mip_opcodes. | |
12980 | R4000 uses interlocks to handle coproc delays. | |
12981 | Other chips (like the R3000) require nops to be inserted for delays. | |
12982 | ||
f72c8c98 | 12983 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12984 | In order to fill delay slots for non-interlocked chips, |
12985 | we must have a way to specify delays based on the coprocessor. | |
12986 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12987 | What are the side-effects of the cop instruction? | |
12988 | What cache support might we have and what are its effects? | |
12989 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12990 | What registers are read/set/modified? |
252b5132 RH |
12991 | |
12992 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12993 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12994 | |
12995 | case M_COP0: | |
12996 | s = "c0"; | |
12997 | goto copz; | |
12998 | case M_COP1: | |
12999 | s = "c1"; | |
13000 | goto copz; | |
13001 | case M_COP2: | |
13002 | s = "c2"; | |
13003 | goto copz; | |
13004 | case M_COP3: | |
13005 | s = "c3"; | |
13006 | copz: | |
df58fc94 | 13007 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
13008 | /* For now we just do C (same as Cz). The parameter will be |
13009 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 13010 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 13011 | break; |
252b5132 | 13012 | |
ea1fb5dc | 13013 | case M_MOVE: |
c0ebe874 | 13014 | move_register (op[0], op[1]); |
8fc2e39e | 13015 | break; |
ea1fb5dc | 13016 | |
833794fc MR |
13017 | case M_MOVEP: |
13018 | gas_assert (mips_opts.micromips); | |
13019 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
13020 | move_register (micromips_to_32_reg_h_map1[op[0]], |
13021 | micromips_to_32_reg_m_map[op[1]]); | |
13022 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
13023 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
13024 | break; |
13025 | ||
252b5132 RH |
13026 | case M_DMUL: |
13027 | dbl = 1; | |
1a0670f3 | 13028 | /* Fall through. */ |
252b5132 | 13029 | case M_MUL: |
e407c74b | 13030 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
13031 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
13032 | op[2]); | |
e407c74b NC |
13033 | else |
13034 | { | |
c0ebe874 RS |
13035 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
13036 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 13037 | } |
8fc2e39e | 13038 | break; |
252b5132 RH |
13039 | |
13040 | case M_DMUL_I: | |
13041 | dbl = 1; | |
1a0670f3 | 13042 | /* Fall through. */ |
252b5132 RH |
13043 | case M_MUL_I: |
13044 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13045 | not trying to be that fancy. GCC should do this for us | |
13046 | anyway. */ | |
8fc2e39e | 13047 | used_at = 1; |
67c0d1eb | 13048 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13049 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13050 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13051 | break; |
13052 | ||
13053 | case M_DMULO_I: | |
13054 | dbl = 1; | |
1a0670f3 | 13055 | /* Fall through. */ |
252b5132 RH |
13056 | case M_MULO_I: |
13057 | imm = 1; | |
13058 | goto do_mulo; | |
13059 | ||
13060 | case M_DMULO: | |
13061 | dbl = 1; | |
1a0670f3 | 13062 | /* Fall through. */ |
252b5132 RH |
13063 | case M_MULO: |
13064 | do_mulo: | |
7d10b47d | 13065 | start_noreorder (); |
8fc2e39e | 13066 | used_at = 1; |
252b5132 | 13067 | if (imm) |
67c0d1eb | 13068 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13069 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13070 | op[1], imm ? AT : op[2]); | |
13071 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13072 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13073 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13074 | if (mips_trap) |
c0ebe874 | 13075 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13076 | else |
13077 | { | |
df58fc94 RS |
13078 | if (mips_opts.micromips) |
13079 | micromips_label_expr (&label_expr); | |
13080 | else | |
13081 | label_expr.X_add_number = 8; | |
c0ebe874 | 13082 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13083 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13084 | macro_build (NULL, "break", BRK_FMT, 6); |
13085 | if (mips_opts.micromips) | |
13086 | micromips_add_label (); | |
252b5132 | 13087 | } |
7d10b47d | 13088 | end_noreorder (); |
c0ebe874 | 13089 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13090 | break; |
13091 | ||
13092 | case M_DMULOU_I: | |
13093 | dbl = 1; | |
1a0670f3 | 13094 | /* Fall through. */ |
252b5132 RH |
13095 | case M_MULOU_I: |
13096 | imm = 1; | |
13097 | goto do_mulou; | |
13098 | ||
13099 | case M_DMULOU: | |
13100 | dbl = 1; | |
1a0670f3 | 13101 | /* Fall through. */ |
252b5132 RH |
13102 | case M_MULOU: |
13103 | do_mulou: | |
7d10b47d | 13104 | start_noreorder (); |
8fc2e39e | 13105 | used_at = 1; |
252b5132 | 13106 | if (imm) |
67c0d1eb RS |
13107 | load_register (AT, &imm_expr, dbl); |
13108 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13109 | op[1], imm ? AT : op[2]); |
df58fc94 | 13110 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13111 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13112 | if (mips_trap) |
df58fc94 | 13113 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13114 | else |
13115 | { | |
df58fc94 RS |
13116 | if (mips_opts.micromips) |
13117 | micromips_label_expr (&label_expr); | |
13118 | else | |
13119 | label_expr.X_add_number = 8; | |
13120 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13121 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13122 | macro_build (NULL, "break", BRK_FMT, 6); |
13123 | if (mips_opts.micromips) | |
13124 | micromips_add_label (); | |
252b5132 | 13125 | } |
7d10b47d | 13126 | end_noreorder (); |
252b5132 RH |
13127 | break; |
13128 | ||
771c7ce4 | 13129 | case M_DROL: |
fef14a42 | 13130 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13131 | { |
c0ebe874 | 13132 | if (op[0] == op[1]) |
82dd0097 CD |
13133 | { |
13134 | tempreg = AT; | |
13135 | used_at = 1; | |
13136 | } | |
13137 | else | |
c0ebe874 RS |
13138 | tempreg = op[0]; |
13139 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13140 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13141 | break; |
82dd0097 | 13142 | } |
8fc2e39e | 13143 | used_at = 1; |
c0ebe874 RS |
13144 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13145 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13146 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13147 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13148 | break; |
13149 | ||
252b5132 | 13150 | case M_ROL: |
fef14a42 | 13151 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13152 | { |
c0ebe874 | 13153 | if (op[0] == op[1]) |
82dd0097 CD |
13154 | { |
13155 | tempreg = AT; | |
13156 | used_at = 1; | |
13157 | } | |
13158 | else | |
c0ebe874 RS |
13159 | tempreg = op[0]; |
13160 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13161 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13162 | break; |
82dd0097 | 13163 | } |
8fc2e39e | 13164 | used_at = 1; |
c0ebe874 RS |
13165 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13166 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13167 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13168 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13169 | break; |
13170 | ||
771c7ce4 TS |
13171 | case M_DROL_I: |
13172 | { | |
13173 | unsigned int rot; | |
e0471c16 TS |
13174 | const char *l; |
13175 | const char *rr; | |
771c7ce4 | 13176 | |
771c7ce4 | 13177 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13178 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13179 | { |
13180 | rot = (64 - rot) & 0x3f; | |
13181 | if (rot >= 32) | |
c0ebe874 | 13182 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13183 | else |
c0ebe874 | 13184 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13185 | break; |
60b63b72 | 13186 | } |
483fc7cd | 13187 | if (rot == 0) |
483fc7cd | 13188 | { |
c0ebe874 | 13189 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13190 | break; |
483fc7cd | 13191 | } |
82dd0097 | 13192 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13193 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13194 | rot &= 0x1f; |
8fc2e39e | 13195 | used_at = 1; |
c0ebe874 RS |
13196 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13197 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13198 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13199 | } |
13200 | break; | |
13201 | ||
252b5132 | 13202 | case M_ROL_I: |
771c7ce4 TS |
13203 | { |
13204 | unsigned int rot; | |
13205 | ||
771c7ce4 | 13206 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13207 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13208 | { |
c0ebe874 RS |
13209 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13210 | (32 - rot) & 0x1f); | |
8fc2e39e | 13211 | break; |
60b63b72 | 13212 | } |
483fc7cd | 13213 | if (rot == 0) |
483fc7cd | 13214 | { |
c0ebe874 | 13215 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13216 | break; |
483fc7cd | 13217 | } |
8fc2e39e | 13218 | used_at = 1; |
c0ebe874 RS |
13219 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13220 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13221 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13222 | } |
13223 | break; | |
13224 | ||
13225 | case M_DROR: | |
fef14a42 | 13226 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13227 | { |
c0ebe874 | 13228 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13229 | break; |
82dd0097 | 13230 | } |
8fc2e39e | 13231 | used_at = 1; |
c0ebe874 RS |
13232 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13233 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13234 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13235 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13236 | break; |
13237 | ||
13238 | case M_ROR: | |
fef14a42 | 13239 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13240 | { |
c0ebe874 | 13241 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13242 | break; |
82dd0097 | 13243 | } |
8fc2e39e | 13244 | used_at = 1; |
c0ebe874 RS |
13245 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13246 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13247 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13248 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13249 | break; |
13250 | ||
771c7ce4 TS |
13251 | case M_DROR_I: |
13252 | { | |
13253 | unsigned int rot; | |
e0471c16 TS |
13254 | const char *l; |
13255 | const char *rr; | |
771c7ce4 | 13256 | |
771c7ce4 | 13257 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13258 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13259 | { |
13260 | if (rot >= 32) | |
c0ebe874 | 13261 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13262 | else |
c0ebe874 | 13263 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13264 | break; |
82dd0097 | 13265 | } |
483fc7cd | 13266 | if (rot == 0) |
483fc7cd | 13267 | { |
c0ebe874 | 13268 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13269 | break; |
483fc7cd | 13270 | } |
91d6fa6a | 13271 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13272 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13273 | rot &= 0x1f; | |
8fc2e39e | 13274 | used_at = 1; |
c0ebe874 RS |
13275 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13276 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13277 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13278 | } |
13279 | break; | |
13280 | ||
252b5132 | 13281 | case M_ROR_I: |
771c7ce4 TS |
13282 | { |
13283 | unsigned int rot; | |
13284 | ||
771c7ce4 | 13285 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13286 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13287 | { |
c0ebe874 | 13288 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13289 | break; |
82dd0097 | 13290 | } |
483fc7cd | 13291 | if (rot == 0) |
483fc7cd | 13292 | { |
c0ebe874 | 13293 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13294 | break; |
483fc7cd | 13295 | } |
8fc2e39e | 13296 | used_at = 1; |
c0ebe874 RS |
13297 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13298 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13299 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13300 | } |
252b5132 RH |
13301 | break; |
13302 | ||
252b5132 | 13303 | case M_SEQ: |
c0ebe874 RS |
13304 | if (op[1] == 0) |
13305 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13306 | else if (op[2] == 0) | |
13307 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13308 | else |
13309 | { | |
c0ebe874 RS |
13310 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13311 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13312 | } |
8fc2e39e | 13313 | break; |
252b5132 RH |
13314 | |
13315 | case M_SEQ_I: | |
b0e6f033 | 13316 | if (imm_expr.X_add_number == 0) |
252b5132 | 13317 | { |
c0ebe874 | 13318 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13319 | break; |
252b5132 | 13320 | } |
c0ebe874 | 13321 | if (op[1] == 0) |
252b5132 | 13322 | { |
1661c76c | 13323 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13324 | ip->insn_mo->name); |
c0ebe874 | 13325 | move_register (op[0], 0); |
8fc2e39e | 13326 | break; |
252b5132 | 13327 | } |
dd3cbb7e NC |
13328 | if (CPU_HAS_SEQ (mips_opts.arch) |
13329 | && -512 <= imm_expr.X_add_number | |
13330 | && imm_expr.X_add_number < 512) | |
13331 | { | |
c0ebe874 | 13332 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13333 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13334 | break; |
13335 | } | |
b0e6f033 | 13336 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13337 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13338 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13339 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13340 | && imm_expr.X_add_number < 0) |
13341 | { | |
13342 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13343 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13344 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13345 | } |
dd3cbb7e NC |
13346 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13347 | { | |
13348 | used_at = 1; | |
bad1aba3 | 13349 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13350 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13351 | break; |
13352 | } | |
252b5132 RH |
13353 | else |
13354 | { | |
bad1aba3 | 13355 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13356 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13357 | used_at = 1; |
13358 | } | |
c0ebe874 | 13359 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13360 | break; |
252b5132 | 13361 | |
c0ebe874 | 13362 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13363 | s = "slt"; |
13364 | goto sge; | |
13365 | case M_SGEU: | |
13366 | s = "sltu"; | |
13367 | sge: | |
c0ebe874 RS |
13368 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13369 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13370 | break; |
252b5132 | 13371 | |
c0ebe874 | 13372 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13373 | case M_SGEU_I: |
b0e6f033 | 13374 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13375 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13376 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13377 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13378 | else |
13379 | { | |
bad1aba3 | 13380 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13381 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13382 | op[0], op[1], AT); |
252b5132 RH |
13383 | used_at = 1; |
13384 | } | |
c0ebe874 | 13385 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13386 | break; |
252b5132 | 13387 | |
c0ebe874 | 13388 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13389 | s = "slt"; |
13390 | goto sgt; | |
13391 | case M_SGTU: | |
13392 | s = "sltu"; | |
13393 | sgt: | |
c0ebe874 | 13394 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13395 | break; |
252b5132 | 13396 | |
c0ebe874 | 13397 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13398 | s = "slt"; |
13399 | goto sgti; | |
13400 | case M_SGTU_I: | |
13401 | s = "sltu"; | |
13402 | sgti: | |
8fc2e39e | 13403 | used_at = 1; |
bad1aba3 | 13404 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13405 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13406 | break; |
13407 | ||
c0ebe874 | 13408 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13409 | s = "slt"; |
13410 | goto sle; | |
13411 | case M_SLEU: | |
13412 | s = "sltu"; | |
13413 | sle: | |
c0ebe874 RS |
13414 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13415 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13416 | break; |
252b5132 | 13417 | |
c0ebe874 | 13418 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13419 | s = "slt"; |
13420 | goto slei; | |
13421 | case M_SLEU_I: | |
13422 | s = "sltu"; | |
13423 | slei: | |
8fc2e39e | 13424 | used_at = 1; |
bad1aba3 | 13425 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13426 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13427 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13428 | break; |
13429 | ||
13430 | case M_SLT_I: | |
b0e6f033 | 13431 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13432 | && imm_expr.X_add_number < 0x8000) |
13433 | { | |
c0ebe874 RS |
13434 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13435 | BFD_RELOC_LO16); | |
8fc2e39e | 13436 | break; |
252b5132 | 13437 | } |
8fc2e39e | 13438 | used_at = 1; |
bad1aba3 | 13439 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13440 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13441 | break; |
13442 | ||
13443 | case M_SLTU_I: | |
b0e6f033 | 13444 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13445 | && imm_expr.X_add_number < 0x8000) |
13446 | { | |
c0ebe874 | 13447 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13448 | BFD_RELOC_LO16); |
8fc2e39e | 13449 | break; |
252b5132 | 13450 | } |
8fc2e39e | 13451 | used_at = 1; |
bad1aba3 | 13452 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13453 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13454 | break; |
13455 | ||
13456 | case M_SNE: | |
c0ebe874 RS |
13457 | if (op[1] == 0) |
13458 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13459 | else if (op[2] == 0) | |
13460 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13461 | else |
13462 | { | |
c0ebe874 RS |
13463 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13464 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13465 | } |
8fc2e39e | 13466 | break; |
252b5132 RH |
13467 | |
13468 | case M_SNE_I: | |
b0e6f033 | 13469 | if (imm_expr.X_add_number == 0) |
252b5132 | 13470 | { |
c0ebe874 | 13471 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13472 | break; |
252b5132 | 13473 | } |
c0ebe874 | 13474 | if (op[1] == 0) |
252b5132 | 13475 | { |
1661c76c | 13476 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13477 | ip->insn_mo->name); |
bad1aba3 | 13478 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13479 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13480 | break; |
252b5132 | 13481 | } |
dd3cbb7e NC |
13482 | if (CPU_HAS_SEQ (mips_opts.arch) |
13483 | && -512 <= imm_expr.X_add_number | |
13484 | && imm_expr.X_add_number < 512) | |
13485 | { | |
c0ebe874 | 13486 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13487 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13488 | break; |
13489 | } | |
b0e6f033 | 13490 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13491 | && imm_expr.X_add_number < 0x10000) |
13492 | { | |
c0ebe874 RS |
13493 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13494 | BFD_RELOC_LO16); | |
252b5132 | 13495 | } |
b0e6f033 | 13496 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13497 | && imm_expr.X_add_number < 0) |
13498 | { | |
13499 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13500 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13501 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13502 | } |
dd3cbb7e NC |
13503 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13504 | { | |
13505 | used_at = 1; | |
bad1aba3 | 13506 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13507 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13508 | break; |
13509 | } | |
252b5132 RH |
13510 | else |
13511 | { | |
bad1aba3 | 13512 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13513 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13514 | used_at = 1; |
13515 | } | |
c0ebe874 | 13516 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13517 | break; |
252b5132 | 13518 | |
df58fc94 RS |
13519 | case M_SUB_I: |
13520 | s = "addi"; | |
13521 | s2 = "sub"; | |
13522 | goto do_subi; | |
13523 | case M_SUBU_I: | |
13524 | s = "addiu"; | |
13525 | s2 = "subu"; | |
13526 | goto do_subi; | |
252b5132 RH |
13527 | case M_DSUB_I: |
13528 | dbl = 1; | |
df58fc94 RS |
13529 | s = "daddi"; |
13530 | s2 = "dsub"; | |
13531 | if (!mips_opts.micromips) | |
13532 | goto do_subi; | |
b0e6f033 | 13533 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13534 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13535 | { |
b0e6f033 RS |
13536 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13537 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13538 | break; |
252b5132 | 13539 | } |
df58fc94 | 13540 | goto do_subi_i; |
252b5132 RH |
13541 | case M_DSUBU_I: |
13542 | dbl = 1; | |
df58fc94 RS |
13543 | s = "daddiu"; |
13544 | s2 = "dsubu"; | |
13545 | do_subi: | |
b0e6f033 | 13546 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13547 | && imm_expr.X_add_number <= 0x8000) |
13548 | { | |
13549 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13550 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13551 | break; |
252b5132 | 13552 | } |
df58fc94 | 13553 | do_subi_i: |
8fc2e39e | 13554 | used_at = 1; |
67c0d1eb | 13555 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13556 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13557 | break; |
13558 | ||
13559 | case M_TEQ_I: | |
13560 | s = "teq"; | |
13561 | goto trap; | |
13562 | case M_TGE_I: | |
13563 | s = "tge"; | |
13564 | goto trap; | |
13565 | case M_TGEU_I: | |
13566 | s = "tgeu"; | |
13567 | goto trap; | |
13568 | case M_TLT_I: | |
13569 | s = "tlt"; | |
13570 | goto trap; | |
13571 | case M_TLTU_I: | |
13572 | s = "tltu"; | |
13573 | goto trap; | |
13574 | case M_TNE_I: | |
13575 | s = "tne"; | |
13576 | trap: | |
8fc2e39e | 13577 | used_at = 1; |
bad1aba3 | 13578 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13579 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13580 | break; |
13581 | ||
252b5132 | 13582 | case M_TRUNCWS: |
43841e91 | 13583 | case M_TRUNCWD: |
df58fc94 | 13584 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13585 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13586 | used_at = 1; |
252b5132 RH |
13587 | |
13588 | /* | |
13589 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13590 | * or is there a reason for it? | |
13591 | */ | |
7d10b47d | 13592 | start_noreorder (); |
c0ebe874 RS |
13593 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13594 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13595 | macro_build (NULL, "nop", ""); |
252b5132 | 13596 | expr1.X_add_number = 3; |
c0ebe874 | 13597 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13598 | expr1.X_add_number = 2; |
67c0d1eb RS |
13599 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13600 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13601 | macro_build (NULL, "nop", ""); | |
13602 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13603 | op[0], op[1]); |
13604 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13605 | macro_build (NULL, "nop", ""); |
7d10b47d | 13606 | end_noreorder (); |
252b5132 RH |
13607 | break; |
13608 | ||
f2ae14a1 | 13609 | case M_ULH_AB: |
252b5132 | 13610 | s = "lb"; |
df58fc94 RS |
13611 | s2 = "lbu"; |
13612 | off = 1; | |
13613 | goto uld_st; | |
f2ae14a1 | 13614 | case M_ULHU_AB: |
252b5132 | 13615 | s = "lbu"; |
df58fc94 RS |
13616 | s2 = "lbu"; |
13617 | off = 1; | |
13618 | goto uld_st; | |
f2ae14a1 | 13619 | case M_ULW_AB: |
df58fc94 RS |
13620 | s = "lwl"; |
13621 | s2 = "lwr"; | |
7f3c4072 | 13622 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13623 | off = 3; |
13624 | goto uld_st; | |
f2ae14a1 | 13625 | case M_ULD_AB: |
252b5132 RH |
13626 | s = "ldl"; |
13627 | s2 = "ldr"; | |
7f3c4072 | 13628 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13629 | off = 7; |
df58fc94 | 13630 | goto uld_st; |
f2ae14a1 | 13631 | case M_USH_AB: |
df58fc94 RS |
13632 | s = "sb"; |
13633 | s2 = "sb"; | |
13634 | off = 1; | |
13635 | ust = 1; | |
13636 | goto uld_st; | |
f2ae14a1 | 13637 | case M_USW_AB: |
df58fc94 RS |
13638 | s = "swl"; |
13639 | s2 = "swr"; | |
7f3c4072 | 13640 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13641 | off = 3; |
df58fc94 RS |
13642 | ust = 1; |
13643 | goto uld_st; | |
f2ae14a1 | 13644 | case M_USD_AB: |
df58fc94 RS |
13645 | s = "sdl"; |
13646 | s2 = "sdr"; | |
7f3c4072 | 13647 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13648 | off = 7; |
13649 | ust = 1; | |
13650 | ||
13651 | uld_st: | |
c0ebe874 | 13652 | breg = op[2]; |
f2ae14a1 | 13653 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13654 | ep = &offset_expr; |
13655 | expr1.X_add_number = 0; | |
f2ae14a1 | 13656 | if (large_offset) |
df58fc94 RS |
13657 | { |
13658 | used_at = 1; | |
13659 | tempreg = AT; | |
f2ae14a1 RS |
13660 | if (small_offset_p (0, align, 16)) |
13661 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13662 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13663 | else | |
13664 | { | |
13665 | load_address (tempreg, ep, &used_at); | |
13666 | if (breg != 0) | |
13667 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13668 | tempreg, tempreg, breg); | |
13669 | } | |
13670 | offset_reloc[0] = BFD_RELOC_LO16; | |
13671 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13672 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13673 | breg = tempreg; |
c0ebe874 | 13674 | tempreg = op[0]; |
df58fc94 RS |
13675 | ep = &expr1; |
13676 | } | |
c0ebe874 | 13677 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13678 | { |
13679 | used_at = 1; | |
13680 | tempreg = AT; | |
13681 | } | |
252b5132 | 13682 | else |
c0ebe874 | 13683 | tempreg = op[0]; |
af22f5b2 | 13684 | |
df58fc94 RS |
13685 | if (off == 1) |
13686 | goto ulh_sh; | |
252b5132 | 13687 | |
90ecf173 | 13688 | if (!target_big_endian) |
df58fc94 | 13689 | ep->X_add_number += off; |
f2ae14a1 | 13690 | if (offbits == 12) |
c8276761 | 13691 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13692 | else |
13693 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13694 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13695 | |
90ecf173 | 13696 | if (!target_big_endian) |
df58fc94 | 13697 | ep->X_add_number -= off; |
252b5132 | 13698 | else |
df58fc94 | 13699 | ep->X_add_number += off; |
f2ae14a1 | 13700 | if (offbits == 12) |
df58fc94 | 13701 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13702 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13703 | else |
13704 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13705 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13706 | |
df58fc94 | 13707 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13708 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13709 | { |
13710 | /* Protect second load's delay slot. */ | |
13711 | load_delay_nop (); | |
c0ebe874 | 13712 | move_register (op[0], tempreg); |
df58fc94 | 13713 | } |
8fc2e39e | 13714 | break; |
252b5132 | 13715 | |
df58fc94 | 13716 | ulh_sh: |
d6bc6245 | 13717 | used_at = 1; |
df58fc94 RS |
13718 | if (target_big_endian == ust) |
13719 | ep->X_add_number += off; | |
c0ebe874 | 13720 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13721 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13722 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13723 | |
13724 | /* For halfword transfers we need a temporary register to shuffle | |
13725 | bytes. Unfortunately for M_USH_A we have none available before | |
13726 | the next store as AT holds the base address. We deal with this | |
13727 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13728 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13729 | if (ust) |
c0ebe874 | 13730 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13731 | |
13732 | if (target_big_endian == ust) | |
13733 | ep->X_add_number -= off; | |
252b5132 | 13734 | else |
df58fc94 | 13735 | ep->X_add_number += off; |
f2ae14a1 RS |
13736 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13737 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13738 | |
df58fc94 | 13739 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13740 | if (ust && large_offset) |
df58fc94 RS |
13741 | { |
13742 | if (target_big_endian) | |
13743 | ep->X_add_number += off; | |
13744 | else | |
13745 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13746 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13747 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13748 | } |
13749 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13750 | if (!ust || large_offset) |
df58fc94 | 13751 | { |
c0ebe874 | 13752 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13753 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13754 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13755 | } |
252b5132 RH |
13756 | break; |
13757 | ||
13758 | default: | |
13759 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13760 | are added dynamically. */ |
1661c76c | 13761 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13762 | break; |
13763 | } | |
741fe287 | 13764 | if (!mips_opts.at && used_at) |
1661c76c | 13765 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13766 | } |
13767 | ||
13768 | /* Implement macros in mips16 mode. */ | |
13769 | ||
13770 | static void | |
17a2f251 | 13771 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13772 | { |
c0ebe874 | 13773 | const struct mips_operand_array *operands; |
252b5132 | 13774 | int mask; |
c0ebe874 | 13775 | int tmp; |
252b5132 RH |
13776 | expressionS expr1; |
13777 | int dbl; | |
13778 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13779 | unsigned int op[MAX_OPERANDS]; |
13780 | unsigned int i; | |
252b5132 RH |
13781 | |
13782 | mask = ip->insn_mo->mask; | |
13783 | ||
c0ebe874 RS |
13784 | operands = insn_operands (ip); |
13785 | for (i = 0; i < MAX_OPERANDS; i++) | |
13786 | if (operands->operand[i]) | |
13787 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13788 | else | |
13789 | op[i] = -1; | |
252b5132 | 13790 | |
252b5132 RH |
13791 | expr1.X_op = O_constant; |
13792 | expr1.X_op_symbol = NULL; | |
13793 | expr1.X_add_symbol = NULL; | |
13794 | expr1.X_add_number = 1; | |
13795 | ||
13796 | dbl = 0; | |
13797 | ||
13798 | switch (mask) | |
13799 | { | |
13800 | default: | |
b37df7c4 | 13801 | abort (); |
252b5132 RH |
13802 | |
13803 | case M_DDIV_3: | |
13804 | dbl = 1; | |
1a0670f3 | 13805 | /* Fall through. */ |
252b5132 RH |
13806 | case M_DIV_3: |
13807 | s = "mflo"; | |
13808 | goto do_div3; | |
13809 | case M_DREM_3: | |
13810 | dbl = 1; | |
1a0670f3 | 13811 | /* Fall through. */ |
252b5132 RH |
13812 | case M_REM_3: |
13813 | s = "mfhi"; | |
13814 | do_div3: | |
7d10b47d | 13815 | start_noreorder (); |
d8722d76 | 13816 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13817 | expr1.X_add_number = 2; |
c0ebe874 | 13818 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13819 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13820 | |
252b5132 RH |
13821 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13822 | since that causes an overflow. We should do that as well, | |
13823 | but I don't see how to do the comparisons without a temporary | |
13824 | register. */ | |
7d10b47d | 13825 | end_noreorder (); |
c0ebe874 | 13826 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13827 | break; |
13828 | ||
13829 | case M_DIVU_3: | |
13830 | s = "divu"; | |
13831 | s2 = "mflo"; | |
13832 | goto do_divu3; | |
13833 | case M_REMU_3: | |
13834 | s = "divu"; | |
13835 | s2 = "mfhi"; | |
13836 | goto do_divu3; | |
13837 | case M_DDIVU_3: | |
13838 | s = "ddivu"; | |
13839 | s2 = "mflo"; | |
13840 | goto do_divu3; | |
13841 | case M_DREMU_3: | |
13842 | s = "ddivu"; | |
13843 | s2 = "mfhi"; | |
13844 | do_divu3: | |
7d10b47d | 13845 | start_noreorder (); |
d8722d76 | 13846 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13847 | expr1.X_add_number = 2; |
c0ebe874 | 13848 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13849 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13850 | end_noreorder (); |
c0ebe874 | 13851 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13852 | break; |
13853 | ||
13854 | case M_DMUL: | |
13855 | dbl = 1; | |
1a0670f3 | 13856 | /* Fall through. */ |
252b5132 | 13857 | case M_MUL: |
c0ebe874 RS |
13858 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13859 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13860 | break; |
252b5132 RH |
13861 | |
13862 | case M_DSUBU_I: | |
13863 | dbl = 1; | |
13864 | goto do_subu; | |
13865 | case M_SUBU_I: | |
13866 | do_subu: | |
252b5132 | 13867 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13868 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13869 | break; |
13870 | ||
13871 | case M_SUBU_I_2: | |
252b5132 | 13872 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13873 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13874 | break; |
13875 | ||
13876 | case M_DSUBU_I_2: | |
252b5132 | 13877 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13878 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13879 | break; |
13880 | ||
13881 | case M_BEQ: | |
13882 | s = "cmp"; | |
13883 | s2 = "bteqz"; | |
13884 | goto do_branch; | |
13885 | case M_BNE: | |
13886 | s = "cmp"; | |
13887 | s2 = "btnez"; | |
13888 | goto do_branch; | |
13889 | case M_BLT: | |
13890 | s = "slt"; | |
13891 | s2 = "btnez"; | |
13892 | goto do_branch; | |
13893 | case M_BLTU: | |
13894 | s = "sltu"; | |
13895 | s2 = "btnez"; | |
13896 | goto do_branch; | |
13897 | case M_BLE: | |
13898 | s = "slt"; | |
13899 | s2 = "bteqz"; | |
13900 | goto do_reverse_branch; | |
13901 | case M_BLEU: | |
13902 | s = "sltu"; | |
13903 | s2 = "bteqz"; | |
13904 | goto do_reverse_branch; | |
13905 | case M_BGE: | |
13906 | s = "slt"; | |
13907 | s2 = "bteqz"; | |
13908 | goto do_branch; | |
13909 | case M_BGEU: | |
13910 | s = "sltu"; | |
13911 | s2 = "bteqz"; | |
13912 | goto do_branch; | |
13913 | case M_BGT: | |
13914 | s = "slt"; | |
13915 | s2 = "btnez"; | |
13916 | goto do_reverse_branch; | |
13917 | case M_BGTU: | |
13918 | s = "sltu"; | |
13919 | s2 = "btnez"; | |
13920 | ||
13921 | do_reverse_branch: | |
c0ebe874 RS |
13922 | tmp = op[1]; |
13923 | op[1] = op[0]; | |
13924 | op[0] = tmp; | |
252b5132 RH |
13925 | |
13926 | do_branch: | |
c0ebe874 | 13927 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13928 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13929 | break; |
13930 | ||
13931 | case M_BEQ_I: | |
13932 | s = "cmpi"; | |
13933 | s2 = "bteqz"; | |
13934 | s3 = "x,U"; | |
13935 | goto do_branch_i; | |
13936 | case M_BNE_I: | |
13937 | s = "cmpi"; | |
13938 | s2 = "btnez"; | |
13939 | s3 = "x,U"; | |
13940 | goto do_branch_i; | |
13941 | case M_BLT_I: | |
13942 | s = "slti"; | |
13943 | s2 = "btnez"; | |
13944 | s3 = "x,8"; | |
13945 | goto do_branch_i; | |
13946 | case M_BLTU_I: | |
13947 | s = "sltiu"; | |
13948 | s2 = "btnez"; | |
13949 | s3 = "x,8"; | |
13950 | goto do_branch_i; | |
13951 | case M_BLE_I: | |
13952 | s = "slti"; | |
13953 | s2 = "btnez"; | |
13954 | s3 = "x,8"; | |
13955 | goto do_addone_branch_i; | |
13956 | case M_BLEU_I: | |
13957 | s = "sltiu"; | |
13958 | s2 = "btnez"; | |
13959 | s3 = "x,8"; | |
13960 | goto do_addone_branch_i; | |
13961 | case M_BGE_I: | |
13962 | s = "slti"; | |
13963 | s2 = "bteqz"; | |
13964 | s3 = "x,8"; | |
13965 | goto do_branch_i; | |
13966 | case M_BGEU_I: | |
13967 | s = "sltiu"; | |
13968 | s2 = "bteqz"; | |
13969 | s3 = "x,8"; | |
13970 | goto do_branch_i; | |
13971 | case M_BGT_I: | |
13972 | s = "slti"; | |
13973 | s2 = "bteqz"; | |
13974 | s3 = "x,8"; | |
13975 | goto do_addone_branch_i; | |
13976 | case M_BGTU_I: | |
13977 | s = "sltiu"; | |
13978 | s2 = "bteqz"; | |
13979 | s3 = "x,8"; | |
13980 | ||
13981 | do_addone_branch_i: | |
252b5132 RH |
13982 | ++imm_expr.X_add_number; |
13983 | ||
13984 | do_branch_i: | |
c0ebe874 | 13985 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13986 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13987 | break; |
13988 | ||
13989 | case M_ABS: | |
13990 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13991 | macro_build (&expr1, "slti", "x,8", op[1]); |
13992 | if (op[0] != op[1]) | |
13993 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13994 | expr1.X_add_number = 2; |
67c0d1eb | 13995 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13996 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13997 | break; |
252b5132 RH |
13998 | } |
13999 | } | |
14000 | ||
14daeee3 RS |
14001 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
14002 | opcode bits in *OPCODE_EXTRA. */ | |
14003 | ||
14004 | static struct mips_opcode * | |
14005 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 14006 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
14007 | { |
14008 | char *name, *dot, *p; | |
14009 | unsigned int mask, suffix; | |
da8bca91 | 14010 | ssize_t opend; |
14daeee3 RS |
14011 | struct mips_opcode *insn; |
14012 | ||
14013 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 14014 | name = xstrndup (start, length); |
14daeee3 RS |
14015 | |
14016 | /* Look up the instruction as-is. */ | |
14017 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 14018 | if (insn) |
e1fa0163 | 14019 | goto end; |
14daeee3 RS |
14020 | |
14021 | dot = strchr (name, '.'); | |
14022 | if (dot && dot[1]) | |
14023 | { | |
14024 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
14025 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
14026 | if (*p == 0 && mask != 0) | |
14027 | { | |
14028 | *dot = 0; | |
14029 | insn = (struct mips_opcode *) hash_find (hash, name); | |
14030 | *dot = '.'; | |
14031 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
14032 | { | |
14033 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 14034 | goto end; |
14daeee3 RS |
14035 | } |
14036 | } | |
14037 | } | |
14038 | ||
14039 | if (mips_opts.micromips) | |
14040 | { | |
14041 | /* See if there's an instruction size override suffix, | |
14042 | either `16' or `32', at the end of the mnemonic proper, | |
14043 | that defines the operation, i.e. before the first `.' | |
14044 | character if any. Strip it and retry. */ | |
14045 | opend = dot != NULL ? dot - name : length; | |
14046 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14047 | suffix = 2; | |
14048 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
14049 | suffix = 4; | |
14050 | else | |
14051 | suffix = 0; | |
14052 | if (suffix) | |
14053 | { | |
39334a61 | 14054 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14055 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14056 | if (insn) |
14daeee3 RS |
14057 | { |
14058 | forced_insn_length = suffix; | |
e1fa0163 | 14059 | goto end; |
14daeee3 RS |
14060 | } |
14061 | } | |
14062 | } | |
14063 | ||
e1fa0163 NC |
14064 | insn = NULL; |
14065 | end: | |
14066 | free (name); | |
14067 | return insn; | |
14daeee3 RS |
14068 | } |
14069 | ||
77bd4346 | 14070 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14071 | is a macro, set imm_expr and offset_expr to the values associated |
14072 | with "I" and "A" operands respectively. Otherwise store the value | |
14073 | of the relocatable field (if any) in offset_expr. In both cases | |
14074 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14075 | |
14076 | static void | |
60f20e8b | 14077 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14078 | { |
60f20e8b | 14079 | const struct mips_opcode *first, *past; |
df58fc94 | 14080 | struct hash_control *hash; |
a92713e6 | 14081 | char format; |
14daeee3 | 14082 | size_t end; |
a92713e6 | 14083 | struct mips_operand_token *tokens; |
14daeee3 | 14084 | unsigned int opcode_extra; |
252b5132 | 14085 | |
df58fc94 RS |
14086 | if (mips_opts.micromips) |
14087 | { | |
14088 | hash = micromips_op_hash; | |
14089 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14090 | } | |
14091 | else | |
14092 | { | |
14093 | hash = op_hash; | |
14094 | past = &mips_opcodes[NUMOPCODES]; | |
14095 | } | |
14096 | forced_insn_length = 0; | |
14daeee3 | 14097 | opcode_extra = 0; |
252b5132 | 14098 | |
df58fc94 | 14099 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14100 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14101 | continue; | |
bdaaa2e1 | 14102 | |
60f20e8b RS |
14103 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14104 | if (first == NULL) | |
252b5132 | 14105 | { |
1661c76c | 14106 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14107 | return; |
252b5132 RH |
14108 | } |
14109 | ||
60f20e8b | 14110 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14111 | format = 'f'; |
60f20e8b | 14112 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14113 | format = 'd'; |
14114 | else | |
14115 | format = 0; | |
14116 | tokens = mips_parse_arguments (str + end, format); | |
14117 | if (!tokens) | |
14118 | return; | |
14119 | ||
60f20e8b RS |
14120 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14121 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14122 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14123 | |
e3de51ce | 14124 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14125 | } |
14126 | ||
77bd4346 RS |
14127 | /* As for mips_ip, but used when assembling MIPS16 code. |
14128 | Also set forced_insn_length to the resulting instruction size in | |
14129 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14130 | |
14131 | static void | |
60f20e8b | 14132 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14133 | { |
1a00e612 | 14134 | char *end, *s, c; |
60f20e8b | 14135 | struct mips_opcode *first; |
a92713e6 | 14136 | struct mips_operand_token *tokens; |
3fb49709 | 14137 | unsigned int l; |
252b5132 | 14138 | |
25499ac7 | 14139 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14140 | ; |
1a00e612 RS |
14141 | end = s; |
14142 | c = *end; | |
3fb49709 MR |
14143 | |
14144 | l = 0; | |
1a00e612 | 14145 | switch (c) |
252b5132 RH |
14146 | { |
14147 | case '\0': | |
14148 | break; | |
14149 | ||
14150 | case ' ': | |
1a00e612 | 14151 | s++; |
252b5132 RH |
14152 | break; |
14153 | ||
14154 | case '.': | |
3fb49709 MR |
14155 | s++; |
14156 | if (*s == 't') | |
252b5132 | 14157 | { |
3fb49709 MR |
14158 | l = 2; |
14159 | s++; | |
252b5132 | 14160 | } |
3fb49709 | 14161 | else if (*s == 'e') |
252b5132 | 14162 | { |
3fb49709 MR |
14163 | l = 4; |
14164 | s++; | |
252b5132 | 14165 | } |
3fb49709 MR |
14166 | if (*s == '\0') |
14167 | break; | |
14168 | else if (*s++ == ' ') | |
14169 | break; | |
1661c76c | 14170 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14171 | return; |
14172 | } | |
3fb49709 | 14173 | forced_insn_length = l; |
252b5132 | 14174 | |
1a00e612 | 14175 | *end = 0; |
60f20e8b | 14176 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14177 | *end = c; |
14178 | ||
60f20e8b | 14179 | if (!first) |
252b5132 | 14180 | { |
1661c76c | 14181 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14182 | return; |
14183 | } | |
14184 | ||
a92713e6 RS |
14185 | tokens = mips_parse_arguments (s, 0); |
14186 | if (!tokens) | |
14187 | return; | |
14188 | ||
60f20e8b | 14189 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14190 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14191 | |
e3de51ce | 14192 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14193 | } |
14194 | ||
b886a2ab RS |
14195 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14196 | NBITS is the number of significant bits in VAL. */ | |
14197 | ||
14198 | static unsigned long | |
14199 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14200 | { | |
14201 | int extval; | |
25499ac7 MR |
14202 | |
14203 | extval = 0; | |
14204 | val &= (1U << nbits) - 1; | |
14205 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14206 | { |
14207 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14208 | val &= 0x1f; | |
14209 | } | |
14210 | else if (nbits == 15) | |
14211 | { | |
14212 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14213 | val &= 0xf; | |
14214 | } | |
25499ac7 | 14215 | else if (nbits == 6) |
b886a2ab RS |
14216 | { |
14217 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14218 | val = 0; | |
14219 | } | |
14220 | return (extval << 16) | val; | |
14221 | } | |
14222 | ||
3ccad066 RS |
14223 | /* Like decode_mips16_operand, but require the operand to be defined and |
14224 | require it to be an integer. */ | |
14225 | ||
14226 | static const struct mips_int_operand * | |
14227 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14228 | { | |
14229 | const struct mips_operand *operand; | |
14230 | ||
14231 | operand = decode_mips16_operand (type, extended_p); | |
14232 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14233 | abort (); | |
14234 | return (const struct mips_int_operand *) operand; | |
14235 | } | |
14236 | ||
14237 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14238 | ||
14239 | static bfd_boolean | |
14240 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14241 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14242 | { | |
14243 | int min_val, max_val; | |
14244 | ||
14245 | min_val = mips_int_operand_min (operand); | |
14246 | max_val = mips_int_operand_max (operand); | |
14247 | if (reloc != BFD_RELOC_UNUSED) | |
14248 | { | |
14249 | if (min_val < 0) | |
14250 | sval = SEXT_16BIT (sval); | |
14251 | else | |
14252 | sval &= 0xffff; | |
14253 | } | |
14254 | ||
14255 | return (sval >= min_val | |
14256 | && sval <= max_val | |
14257 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14258 | } | |
14259 | ||
5c04167a RS |
14260 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14261 | extending it if necessary. The instruction in *INSN may | |
14262 | already be extended. | |
14263 | ||
43c0598f RS |
14264 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14265 | if none. In the former case, VAL is a 16-bit number with no | |
14266 | defined signedness. | |
14267 | ||
14268 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14269 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14270 | |
14271 | static void | |
3b4dbbbf | 14272 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14273 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14274 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14275 | { |
3ccad066 RS |
14276 | const struct mips_int_operand *operand; |
14277 | unsigned int uval, length; | |
252b5132 | 14278 | |
3ccad066 RS |
14279 | operand = mips16_immed_operand (type, FALSE); |
14280 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14281 | { |
14282 | /* We need an extended instruction. */ | |
14283 | if (user_insn_length == 2) | |
14284 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14285 | else | |
14286 | *insn |= MIPS16_EXTEND; | |
14287 | } | |
14288 | else if (user_insn_length == 4) | |
14289 | { | |
14290 | /* The operand doesn't force an unextended instruction to be extended. | |
14291 | Warn if the user wanted an extended instruction anyway. */ | |
14292 | *insn |= MIPS16_EXTEND; | |
14293 | as_warn_where (file, line, | |
14294 | _("extended operand requested but not required")); | |
14295 | } | |
252b5132 | 14296 | |
3ccad066 RS |
14297 | length = mips16_opcode_length (*insn); |
14298 | if (length == 4) | |
252b5132 | 14299 | { |
3ccad066 RS |
14300 | operand = mips16_immed_operand (type, TRUE); |
14301 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14302 | as_bad_where (file, line, | |
14303 | _("operand value out of range for instruction")); | |
252b5132 | 14304 | } |
3ccad066 | 14305 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14306 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14307 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14308 | else |
3ccad066 | 14309 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14310 | } |
14311 | \f | |
d6f16593 | 14312 | struct percent_op_match |
ad8d3bb3 | 14313 | { |
5e0116d5 RS |
14314 | const char *str; |
14315 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14316 | }; |
14317 | ||
14318 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14319 | { |
5e0116d5 | 14320 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14321 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14322 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14323 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14324 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14325 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14326 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14327 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14328 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14329 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14330 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14331 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14332 | {"%half", BFD_RELOC_16}, |
14333 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14334 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14335 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14336 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14337 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14338 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14339 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14340 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14341 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14342 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14343 | {"%hi", BFD_RELOC_HI16_S}, |
14344 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14345 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14346 | }; |
14347 | ||
d6f16593 MR |
14348 | static const struct percent_op_match mips16_percent_op[] = |
14349 | { | |
14350 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14351 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14352 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14353 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14354 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14355 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14356 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14357 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14358 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14359 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14360 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14361 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14362 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14363 | }; |
14364 | ||
252b5132 | 14365 | |
5e0116d5 RS |
14366 | /* Return true if *STR points to a relocation operator. When returning true, |
14367 | move *STR over the operator and store its relocation code in *RELOC. | |
14368 | Leave both *STR and *RELOC alone when returning false. */ | |
14369 | ||
14370 | static bfd_boolean | |
17a2f251 | 14371 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14372 | { |
d6f16593 MR |
14373 | const struct percent_op_match *percent_op; |
14374 | size_t limit, i; | |
14375 | ||
14376 | if (mips_opts.mips16) | |
14377 | { | |
14378 | percent_op = mips16_percent_op; | |
14379 | limit = ARRAY_SIZE (mips16_percent_op); | |
14380 | } | |
14381 | else | |
14382 | { | |
14383 | percent_op = mips_percent_op; | |
14384 | limit = ARRAY_SIZE (mips_percent_op); | |
14385 | } | |
76b3015f | 14386 | |
d6f16593 | 14387 | for (i = 0; i < limit; i++) |
5e0116d5 | 14388 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14389 | { |
3f98094e DJ |
14390 | int len = strlen (percent_op[i].str); |
14391 | ||
14392 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14393 | continue; | |
14394 | ||
5e0116d5 RS |
14395 | *str += strlen (percent_op[i].str); |
14396 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14397 | |
5e0116d5 RS |
14398 | /* Check whether the output BFD supports this relocation. |
14399 | If not, issue an error and fall back on something safe. */ | |
14400 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14401 | { |
20203fb9 | 14402 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14403 | percent_op[i].str); |
01a3f561 | 14404 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14405 | } |
5e0116d5 | 14406 | return TRUE; |
394f9b3a | 14407 | } |
5e0116d5 | 14408 | return FALSE; |
394f9b3a | 14409 | } |
ad8d3bb3 | 14410 | |
ad8d3bb3 | 14411 | |
5e0116d5 RS |
14412 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14413 | expression in *EP and the relocations in the array starting | |
14414 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14415 | |
01a3f561 | 14416 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14417 | |
5e0116d5 | 14418 | static size_t |
17a2f251 TS |
14419 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14420 | char *str) | |
ad8d3bb3 | 14421 | { |
5e0116d5 RS |
14422 | bfd_reloc_code_real_type reversed_reloc[3]; |
14423 | size_t reloc_index, i; | |
09b8f35a RS |
14424 | int crux_depth, str_depth; |
14425 | char *crux; | |
5e0116d5 RS |
14426 | |
14427 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14428 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14429 | of the main expression and with CRUX_DEPTH containing the number | |
14430 | of open brackets at that point. */ | |
14431 | reloc_index = -1; | |
14432 | str_depth = 0; | |
14433 | do | |
fb1b3232 | 14434 | { |
09b8f35a RS |
14435 | reloc_index++; |
14436 | crux = str; | |
14437 | crux_depth = str_depth; | |
14438 | ||
14439 | /* Skip over whitespace and brackets, keeping count of the number | |
14440 | of brackets. */ | |
14441 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14442 | if (*str++ == '(') | |
14443 | str_depth++; | |
5e0116d5 | 14444 | } |
09b8f35a RS |
14445 | while (*str == '%' |
14446 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14447 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14448 | |
09b8f35a | 14449 | my_getExpression (ep, crux); |
5e0116d5 | 14450 | str = expr_end; |
394f9b3a | 14451 | |
5e0116d5 | 14452 | /* Match every open bracket. */ |
09b8f35a | 14453 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14454 | if (*str++ == ')') |
09b8f35a | 14455 | crux_depth--; |
394f9b3a | 14456 | |
09b8f35a | 14457 | if (crux_depth > 0) |
20203fb9 | 14458 | as_bad (_("unclosed '('")); |
394f9b3a | 14459 | |
5e0116d5 | 14460 | expr_end = str; |
252b5132 | 14461 | |
01a3f561 | 14462 | if (reloc_index != 0) |
64bdfcaf RS |
14463 | { |
14464 | prev_reloc_op_frag = frag_now; | |
14465 | for (i = 0; i < reloc_index; i++) | |
14466 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14467 | } | |
fb1b3232 | 14468 | |
5e0116d5 | 14469 | return reloc_index; |
252b5132 RH |
14470 | } |
14471 | ||
14472 | static void | |
17a2f251 | 14473 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14474 | { |
14475 | char *save_in; | |
14476 | ||
14477 | save_in = input_line_pointer; | |
14478 | input_line_pointer = str; | |
14479 | expression (ep); | |
14480 | expr_end = input_line_pointer; | |
14481 | input_line_pointer = save_in; | |
252b5132 RH |
14482 | } |
14483 | ||
6d4af3c2 | 14484 | const char * |
17a2f251 | 14485 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14486 | { |
499ac353 | 14487 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14488 | } |
14489 | ||
14490 | void | |
17a2f251 | 14491 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14492 | { |
14493 | if (target_big_endian) | |
14494 | number_to_chars_bigendian (buf, val, n); | |
14495 | else | |
14496 | number_to_chars_littleendian (buf, val, n); | |
14497 | } | |
14498 | \f | |
e013f690 TS |
14499 | static int support_64bit_objects(void) |
14500 | { | |
14501 | const char **list, **l; | |
aa3d8fdf | 14502 | int yes; |
e013f690 TS |
14503 | |
14504 | list = bfd_target_list (); | |
14505 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14506 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14507 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14508 | break; |
aa3d8fdf | 14509 | yes = (*l != NULL); |
e013f690 | 14510 | free (list); |
aa3d8fdf | 14511 | return yes; |
e013f690 TS |
14512 | } |
14513 | ||
316f5878 RS |
14514 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14515 | NEW_VALUE. Warn if another value was already specified. Note: | |
14516 | we have to defer parsing the -march and -mtune arguments in order | |
14517 | to handle 'from-abi' correctly, since the ABI might be specified | |
14518 | in a later argument. */ | |
14519 | ||
14520 | static void | |
17a2f251 | 14521 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14522 | { |
14523 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14524 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14525 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14526 | new_value); | |
14527 | ||
14528 | *string_ptr = new_value; | |
14529 | } | |
14530 | ||
252b5132 | 14531 | int |
17b9d67d | 14532 | md_parse_option (int c, const char *arg) |
252b5132 | 14533 | { |
c6278170 RS |
14534 | unsigned int i; |
14535 | ||
14536 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14537 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14538 | { | |
919731af | 14539 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14540 | c == mips_ases[i].option_on); |
14541 | return 1; | |
14542 | } | |
14543 | ||
252b5132 RH |
14544 | switch (c) |
14545 | { | |
119d663a NC |
14546 | case OPTION_CONSTRUCT_FLOATS: |
14547 | mips_disable_float_construction = 0; | |
14548 | break; | |
bdaaa2e1 | 14549 | |
119d663a NC |
14550 | case OPTION_NO_CONSTRUCT_FLOATS: |
14551 | mips_disable_float_construction = 1; | |
14552 | break; | |
bdaaa2e1 | 14553 | |
252b5132 RH |
14554 | case OPTION_TRAP: |
14555 | mips_trap = 1; | |
14556 | break; | |
14557 | ||
14558 | case OPTION_BREAK: | |
14559 | mips_trap = 0; | |
14560 | break; | |
14561 | ||
14562 | case OPTION_EB: | |
14563 | target_big_endian = 1; | |
14564 | break; | |
14565 | ||
14566 | case OPTION_EL: | |
14567 | target_big_endian = 0; | |
14568 | break; | |
14569 | ||
14570 | case 'O': | |
4ffff32f TS |
14571 | if (arg == NULL) |
14572 | mips_optimize = 1; | |
14573 | else if (arg[0] == '0') | |
14574 | mips_optimize = 0; | |
14575 | else if (arg[0] == '1') | |
252b5132 RH |
14576 | mips_optimize = 1; |
14577 | else | |
14578 | mips_optimize = 2; | |
14579 | break; | |
14580 | ||
14581 | case 'g': | |
14582 | if (arg == NULL) | |
14583 | mips_debug = 2; | |
14584 | else | |
14585 | mips_debug = atoi (arg); | |
252b5132 RH |
14586 | break; |
14587 | ||
14588 | case OPTION_MIPS1: | |
0b35dfee | 14589 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14590 | break; |
14591 | ||
14592 | case OPTION_MIPS2: | |
0b35dfee | 14593 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14594 | break; |
14595 | ||
14596 | case OPTION_MIPS3: | |
0b35dfee | 14597 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14598 | break; |
14599 | ||
14600 | case OPTION_MIPS4: | |
0b35dfee | 14601 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14602 | break; |
14603 | ||
84ea6cf2 | 14604 | case OPTION_MIPS5: |
0b35dfee | 14605 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14606 | break; |
14607 | ||
e7af610e | 14608 | case OPTION_MIPS32: |
0b35dfee | 14609 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14610 | break; |
14611 | ||
af7ee8bf | 14612 | case OPTION_MIPS32R2: |
0b35dfee | 14613 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14614 | break; |
14615 | ||
ae52f483 | 14616 | case OPTION_MIPS32R3: |
0ae19f05 | 14617 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14618 | break; |
14619 | ||
14620 | case OPTION_MIPS32R5: | |
0ae19f05 | 14621 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14622 | break; |
14623 | ||
7361da2c AB |
14624 | case OPTION_MIPS32R6: |
14625 | file_mips_opts.isa = ISA_MIPS32R6; | |
14626 | break; | |
14627 | ||
5f74bc13 | 14628 | case OPTION_MIPS64R2: |
0b35dfee | 14629 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14630 | break; |
14631 | ||
ae52f483 | 14632 | case OPTION_MIPS64R3: |
0ae19f05 | 14633 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14634 | break; |
14635 | ||
14636 | case OPTION_MIPS64R5: | |
0ae19f05 | 14637 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14638 | break; |
14639 | ||
7361da2c AB |
14640 | case OPTION_MIPS64R6: |
14641 | file_mips_opts.isa = ISA_MIPS64R6; | |
14642 | break; | |
14643 | ||
84ea6cf2 | 14644 | case OPTION_MIPS64: |
0b35dfee | 14645 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14646 | break; |
14647 | ||
ec68c924 | 14648 | case OPTION_MTUNE: |
316f5878 RS |
14649 | mips_set_option_string (&mips_tune_string, arg); |
14650 | break; | |
ec68c924 | 14651 | |
316f5878 RS |
14652 | case OPTION_MARCH: |
14653 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14654 | break; |
14655 | ||
14656 | case OPTION_M4650: | |
316f5878 RS |
14657 | mips_set_option_string (&mips_arch_string, "4650"); |
14658 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14659 | break; |
14660 | ||
14661 | case OPTION_NO_M4650: | |
14662 | break; | |
14663 | ||
14664 | case OPTION_M4010: | |
316f5878 RS |
14665 | mips_set_option_string (&mips_arch_string, "4010"); |
14666 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14667 | break; |
14668 | ||
14669 | case OPTION_NO_M4010: | |
14670 | break; | |
14671 | ||
14672 | case OPTION_M4100: | |
316f5878 RS |
14673 | mips_set_option_string (&mips_arch_string, "4100"); |
14674 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14675 | break; |
14676 | ||
14677 | case OPTION_NO_M4100: | |
14678 | break; | |
14679 | ||
252b5132 | 14680 | case OPTION_M3900: |
316f5878 RS |
14681 | mips_set_option_string (&mips_arch_string, "3900"); |
14682 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14683 | break; |
bdaaa2e1 | 14684 | |
252b5132 RH |
14685 | case OPTION_NO_M3900: |
14686 | break; | |
14687 | ||
df58fc94 | 14688 | case OPTION_MICROMIPS: |
919731af | 14689 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14690 | { |
14691 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14692 | return 0; | |
14693 | } | |
919731af | 14694 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14695 | mips_no_prev_insn (); |
14696 | break; | |
14697 | ||
14698 | case OPTION_NO_MICROMIPS: | |
919731af | 14699 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14700 | mips_no_prev_insn (); |
14701 | break; | |
14702 | ||
252b5132 | 14703 | case OPTION_MIPS16: |
919731af | 14704 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14705 | { |
14706 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14707 | return 0; | |
14708 | } | |
919731af | 14709 | file_mips_opts.mips16 = 1; |
7d10b47d | 14710 | mips_no_prev_insn (); |
252b5132 RH |
14711 | break; |
14712 | ||
14713 | case OPTION_NO_MIPS16: | |
919731af | 14714 | file_mips_opts.mips16 = 0; |
7d10b47d | 14715 | mips_no_prev_insn (); |
252b5132 RH |
14716 | break; |
14717 | ||
6a32d874 CM |
14718 | case OPTION_FIX_24K: |
14719 | mips_fix_24k = 1; | |
14720 | break; | |
14721 | ||
14722 | case OPTION_NO_FIX_24K: | |
14723 | mips_fix_24k = 0; | |
14724 | break; | |
14725 | ||
a8d14a88 CM |
14726 | case OPTION_FIX_RM7000: |
14727 | mips_fix_rm7000 = 1; | |
14728 | break; | |
14729 | ||
14730 | case OPTION_NO_FIX_RM7000: | |
14731 | mips_fix_rm7000 = 0; | |
14732 | break; | |
14733 | ||
c67a084a NC |
14734 | case OPTION_FIX_LOONGSON2F_JUMP: |
14735 | mips_fix_loongson2f_jump = TRUE; | |
14736 | break; | |
14737 | ||
14738 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14739 | mips_fix_loongson2f_jump = FALSE; | |
14740 | break; | |
14741 | ||
14742 | case OPTION_FIX_LOONGSON2F_NOP: | |
14743 | mips_fix_loongson2f_nop = TRUE; | |
14744 | break; | |
14745 | ||
14746 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14747 | mips_fix_loongson2f_nop = FALSE; | |
14748 | break; | |
14749 | ||
d766e8ec RS |
14750 | case OPTION_FIX_VR4120: |
14751 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14752 | break; |
14753 | ||
d766e8ec RS |
14754 | case OPTION_NO_FIX_VR4120: |
14755 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14756 | break; |
14757 | ||
7d8e00cf RS |
14758 | case OPTION_FIX_VR4130: |
14759 | mips_fix_vr4130 = 1; | |
14760 | break; | |
14761 | ||
14762 | case OPTION_NO_FIX_VR4130: | |
14763 | mips_fix_vr4130 = 0; | |
14764 | break; | |
14765 | ||
d954098f DD |
14766 | case OPTION_FIX_CN63XXP1: |
14767 | mips_fix_cn63xxp1 = TRUE; | |
14768 | break; | |
14769 | ||
14770 | case OPTION_NO_FIX_CN63XXP1: | |
14771 | mips_fix_cn63xxp1 = FALSE; | |
14772 | break; | |
14773 | ||
27c634e0 FN |
14774 | case OPTION_FIX_R5900: |
14775 | mips_fix_r5900 = TRUE; | |
14776 | mips_fix_r5900_explicit = TRUE; | |
14777 | break; | |
14778 | ||
14779 | case OPTION_NO_FIX_R5900: | |
14780 | mips_fix_r5900 = FALSE; | |
14781 | mips_fix_r5900_explicit = TRUE; | |
14782 | break; | |
14783 | ||
4a6a3df4 AO |
14784 | case OPTION_RELAX_BRANCH: |
14785 | mips_relax_branch = 1; | |
14786 | break; | |
14787 | ||
14788 | case OPTION_NO_RELAX_BRANCH: | |
14789 | mips_relax_branch = 0; | |
14790 | break; | |
14791 | ||
8b10b0b3 MR |
14792 | case OPTION_IGNORE_BRANCH_ISA: |
14793 | mips_ignore_branch_isa = TRUE; | |
14794 | break; | |
14795 | ||
14796 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14797 | mips_ignore_branch_isa = FALSE; | |
14798 | break; | |
14799 | ||
833794fc | 14800 | case OPTION_INSN32: |
919731af | 14801 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14802 | break; |
14803 | ||
14804 | case OPTION_NO_INSN32: | |
919731af | 14805 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14806 | break; |
14807 | ||
aa6975fb ILT |
14808 | case OPTION_MSHARED: |
14809 | mips_in_shared = TRUE; | |
14810 | break; | |
14811 | ||
14812 | case OPTION_MNO_SHARED: | |
14813 | mips_in_shared = FALSE; | |
14814 | break; | |
14815 | ||
aed1a261 | 14816 | case OPTION_MSYM32: |
919731af | 14817 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14818 | break; |
14819 | ||
14820 | case OPTION_MNO_SYM32: | |
919731af | 14821 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14822 | break; |
14823 | ||
252b5132 RH |
14824 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14825 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14826 | intended to be compatible with Irix 5. */ | |
14827 | case OPTION_CALL_SHARED: | |
252b5132 | 14828 | mips_pic = SVR4_PIC; |
143d77c5 | 14829 | mips_abicalls = TRUE; |
252b5132 RH |
14830 | break; |
14831 | ||
861fb55a | 14832 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14833 | mips_pic = NO_PIC; |
14834 | mips_abicalls = TRUE; | |
14835 | break; | |
14836 | ||
252b5132 | 14837 | case OPTION_NON_SHARED: |
252b5132 | 14838 | mips_pic = NO_PIC; |
143d77c5 | 14839 | mips_abicalls = FALSE; |
252b5132 RH |
14840 | break; |
14841 | ||
44075ae2 TS |
14842 | /* The -xgot option tells the assembler to use 32 bit offsets |
14843 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14844 | compatibility. */ |
14845 | case OPTION_XGOT: | |
14846 | mips_big_got = 1; | |
14847 | break; | |
14848 | ||
14849 | case 'G': | |
6caf9ef4 TS |
14850 | g_switch_value = atoi (arg); |
14851 | g_switch_seen = 1; | |
252b5132 RH |
14852 | break; |
14853 | ||
34ba82a8 TS |
14854 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14855 | and -mabi=64. */ | |
252b5132 | 14856 | case OPTION_32: |
f3ded42a | 14857 | mips_abi = O32_ABI; |
252b5132 RH |
14858 | break; |
14859 | ||
e013f690 | 14860 | case OPTION_N32: |
316f5878 | 14861 | mips_abi = N32_ABI; |
e013f690 | 14862 | break; |
252b5132 | 14863 | |
e013f690 | 14864 | case OPTION_64: |
316f5878 | 14865 | mips_abi = N64_ABI; |
f43abd2b | 14866 | if (!support_64bit_objects()) |
1661c76c | 14867 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14868 | break; |
14869 | ||
c97ef257 | 14870 | case OPTION_GP32: |
bad1aba3 | 14871 | file_mips_opts.gp = 32; |
c97ef257 AH |
14872 | break; |
14873 | ||
14874 | case OPTION_GP64: | |
bad1aba3 | 14875 | file_mips_opts.gp = 64; |
c97ef257 | 14876 | break; |
252b5132 | 14877 | |
ca4e0257 | 14878 | case OPTION_FP32: |
0b35dfee | 14879 | file_mips_opts.fp = 32; |
316f5878 RS |
14880 | break; |
14881 | ||
351cdf24 MF |
14882 | case OPTION_FPXX: |
14883 | file_mips_opts.fp = 0; | |
14884 | break; | |
14885 | ||
316f5878 | 14886 | case OPTION_FP64: |
0b35dfee | 14887 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14888 | break; |
14889 | ||
351cdf24 MF |
14890 | case OPTION_ODD_SPREG: |
14891 | file_mips_opts.oddspreg = 1; | |
14892 | break; | |
14893 | ||
14894 | case OPTION_NO_ODD_SPREG: | |
14895 | file_mips_opts.oddspreg = 0; | |
14896 | break; | |
14897 | ||
037b32b9 | 14898 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14899 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14900 | break; |
14901 | ||
14902 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14903 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14904 | break; |
14905 | ||
14906 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14907 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14908 | break; |
14909 | ||
14910 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14911 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14912 | break; |
14913 | ||
252b5132 | 14914 | case OPTION_MABI: |
e013f690 | 14915 | if (strcmp (arg, "32") == 0) |
316f5878 | 14916 | mips_abi = O32_ABI; |
e013f690 | 14917 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14918 | mips_abi = O64_ABI; |
e013f690 | 14919 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14920 | mips_abi = N32_ABI; |
e013f690 TS |
14921 | else if (strcmp (arg, "64") == 0) |
14922 | { | |
316f5878 | 14923 | mips_abi = N64_ABI; |
e013f690 | 14924 | if (! support_64bit_objects()) |
1661c76c | 14925 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14926 | "format")); |
14927 | } | |
14928 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14929 | mips_abi = EABI_ABI; |
e013f690 | 14930 | else |
da0e507f TS |
14931 | { |
14932 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14933 | return 0; | |
14934 | } | |
252b5132 RH |
14935 | break; |
14936 | ||
6b76fefe | 14937 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14938 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14939 | break; |
14940 | ||
9ee72ff1 | 14941 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14942 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14943 | break; |
14944 | ||
ecb4347a | 14945 | case OPTION_MDEBUG: |
b34976b6 | 14946 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14947 | break; |
14948 | ||
14949 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14950 | mips_flag_mdebug = FALSE; |
ecb4347a | 14951 | break; |
dcd410fe RO |
14952 | |
14953 | case OPTION_PDR: | |
14954 | mips_flag_pdr = TRUE; | |
14955 | break; | |
14956 | ||
14957 | case OPTION_NO_PDR: | |
14958 | mips_flag_pdr = FALSE; | |
14959 | break; | |
0a44bf69 RS |
14960 | |
14961 | case OPTION_MVXWORKS_PIC: | |
14962 | mips_pic = VXWORKS_PIC; | |
14963 | break; | |
ecb4347a | 14964 | |
ba92f887 MR |
14965 | case OPTION_NAN: |
14966 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14967 | mips_nan2008 = 1; |
ba92f887 | 14968 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14969 | mips_nan2008 = 0; |
ba92f887 MR |
14970 | else |
14971 | { | |
1661c76c | 14972 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14973 | return 0; |
14974 | } | |
14975 | break; | |
14976 | ||
252b5132 RH |
14977 | default: |
14978 | return 0; | |
14979 | } | |
14980 | ||
c67a084a NC |
14981 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14982 | ||
252b5132 RH |
14983 | return 1; |
14984 | } | |
316f5878 | 14985 | \f |
919731af | 14986 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14987 | |
316f5878 | 14988 | static void |
17a2f251 | 14989 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14990 | { |
14991 | if (info != 0) | |
fef14a42 | 14992 | mips_tune = info->cpu; |
316f5878 | 14993 | } |
80cc45a5 | 14994 | |
34ba82a8 | 14995 | |
252b5132 | 14996 | void |
17a2f251 | 14997 | mips_after_parse_args (void) |
e9670677 | 14998 | { |
fef14a42 TS |
14999 | const struct mips_cpu_info *arch_info = 0; |
15000 | const struct mips_cpu_info *tune_info = 0; | |
15001 | ||
e9670677 | 15002 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15003 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15004 | { |
6caf9ef4 | 15005 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 15006 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
15007 | g_switch_value = 0; |
15008 | } | |
15009 | ||
cac012d6 AO |
15010 | if (mips_abi == NO_ABI) |
15011 | mips_abi = MIPS_DEFAULT_ABI; | |
15012 | ||
919731af | 15013 | /* The following code determines the architecture. |
22923709 RS |
15014 | Similar code was added to GCC 3.3 (see override_options() in |
15015 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15016 | as much as possible. */ | |
e9670677 | 15017 | |
316f5878 | 15018 | if (mips_arch_string != 0) |
fef14a42 | 15019 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15020 | |
0b35dfee | 15021 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 15022 | { |
0b35dfee | 15023 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 15024 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15025 | the -march selection (if any). */ |
fef14a42 | 15026 | if (arch_info != 0) |
e9670677 | 15027 | { |
316f5878 RS |
15028 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15029 | There's no harm in specifying both as long as the ISA levels | |
15030 | are the same. */ | |
0b35dfee | 15031 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
15032 | as_bad (_("-%s conflicts with the other architecture options," |
15033 | " which imply -%s"), | |
0b35dfee | 15034 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 15035 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15036 | } |
316f5878 | 15037 | else |
0b35dfee | 15038 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
15039 | } |
15040 | ||
fef14a42 | 15041 | if (arch_info == 0) |
95bfe26e MF |
15042 | { |
15043 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15044 | gas_assert (arch_info); | |
15045 | } | |
e9670677 | 15046 | |
fef14a42 | 15047 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15048 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15049 | arch_info->name); |
15050 | ||
919731af | 15051 | file_mips_opts.arch = arch_info->cpu; |
15052 | file_mips_opts.isa = arch_info->isa; | |
15053 | ||
15054 | /* Set up initial mips_opts state. */ | |
15055 | mips_opts = file_mips_opts; | |
15056 | ||
27c634e0 FN |
15057 | /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ |
15058 | if (!mips_fix_r5900_explicit) | |
15059 | mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; | |
15060 | ||
919731af | 15061 | /* The register size inference code is now placed in |
15062 | file_mips_check_options. */ | |
fef14a42 | 15063 | |
0b35dfee | 15064 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15065 | processor. */ | |
fef14a42 TS |
15066 | if (mips_tune_string != 0) |
15067 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15068 | |
fef14a42 TS |
15069 | if (tune_info == 0) |
15070 | mips_set_tune (arch_info); | |
15071 | else | |
15072 | mips_set_tune (tune_info); | |
e9670677 | 15073 | |
ecb4347a | 15074 | if (mips_flag_mdebug < 0) |
e8044f35 | 15075 | mips_flag_mdebug = 0; |
e9670677 MR |
15076 | } |
15077 | \f | |
15078 | void | |
17a2f251 | 15079 | mips_init_after_args (void) |
252b5132 RH |
15080 | { |
15081 | /* initialize opcodes */ | |
15082 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15083 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15084 | } |
15085 | ||
15086 | long | |
17a2f251 | 15087 | md_pcrel_from (fixS *fixP) |
252b5132 | 15088 | { |
a7ebbfdf TS |
15089 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15090 | switch (fixP->fx_r_type) | |
15091 | { | |
df58fc94 RS |
15092 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15093 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15094 | /* Return the address of the delay slot. */ | |
15095 | return addr + 2; | |
15096 | ||
15097 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15098 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15099 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15100 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15101 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15102 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15103 | case BFD_RELOC_MIPS_JMP: |
15104 | /* Return the address of the delay slot. */ | |
15105 | return addr + 4; | |
df58fc94 | 15106 | |
51f6035b MR |
15107 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15108 | /* Return the aligned address of the doubleword containing | |
15109 | the instruction. */ | |
15110 | return addr & ~7; | |
15111 | ||
a7ebbfdf TS |
15112 | default: |
15113 | return addr; | |
15114 | } | |
252b5132 RH |
15115 | } |
15116 | ||
252b5132 RH |
15117 | /* This is called before the symbol table is processed. In order to |
15118 | work with gcc when using mips-tfile, we must keep all local labels. | |
15119 | However, in other cases, we want to discard them. If we were | |
15120 | called with -g, but we didn't see any debugging information, it may | |
15121 | mean that gcc is smuggling debugging information through to | |
15122 | mips-tfile, in which case we must generate all local labels. */ | |
15123 | ||
15124 | void | |
17a2f251 | 15125 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15126 | { |
15127 | #ifndef NO_ECOFF_DEBUGGING | |
15128 | if (ECOFF_DEBUGGING | |
15129 | && mips_debug != 0 | |
15130 | && ! ecoff_debugging_seen) | |
15131 | flag_keep_locals = 1; | |
15132 | #endif | |
15133 | } | |
15134 | ||
3b91255e | 15135 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15136 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15137 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15138 | relocation operators. | |
15139 | ||
15140 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15141 | expression if: | |
15142 | ||
15143 | (a) it refers to the same symbol; and | |
15144 | (b) the offset applied in the %lo() expression is no lower than | |
15145 | the offset applied in the %got() or %hi(). | |
15146 | ||
15147 | (b) allows us to cope with code like: | |
15148 | ||
15149 | lui $4,%hi(foo) | |
15150 | lh $4,%lo(foo+2)($4) | |
15151 | ||
15152 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15153 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15154 | the high 16 bits. | |
15155 | ||
15156 | When several %lo()s match a particular %got() or %hi(), we use the | |
15157 | following rules to distinguish them: | |
15158 | ||
15159 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15160 | higher offsets. | |
15161 | ||
15162 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15163 | that already have a matching %got() or %hi(). | |
15164 | ||
15165 | (3) later %lo()s are better than earlier %lo()s. | |
15166 | ||
15167 | These rules are applied in order. | |
15168 | ||
15169 | (1) means, among other things, that %lo()s with identical offsets are | |
15170 | chosen if they exist. | |
15171 | ||
15172 | (2) means that we won't associate several high-part relocations with | |
15173 | the same low-part relocation unless there's no alternative. Having | |
15174 | several high parts for the same low part is a GNU extension; this rule | |
15175 | allows careful users to avoid it. | |
15176 | ||
15177 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15178 | with the last high-part relocation being at the front of the list. | |
15179 | It therefore makes sense to choose the last matching low-part | |
15180 | relocation, all other things being equal. It's also easier | |
15181 | to code that way. */ | |
252b5132 RH |
15182 | |
15183 | void | |
17a2f251 | 15184 | mips_frob_file (void) |
252b5132 RH |
15185 | { |
15186 | struct mips_hi_fixup *l; | |
35903be0 | 15187 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15188 | |
15189 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15190 | { | |
15191 | segment_info_type *seginfo; | |
3b91255e RS |
15192 | bfd_boolean matched_lo_p; |
15193 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15194 | |
9c2799c2 | 15195 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15196 | |
5919d012 | 15197 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15198 | there isn't supposed to be a matching LO. Ignore %gots against |
15199 | constants; we'll report an error for those later. */ | |
738e5348 | 15200 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15201 | && !(l->fixp->fx_addsy |
9e009953 | 15202 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15203 | continue; |
15204 | ||
15205 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15206 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15207 | continue; |
15208 | ||
252b5132 | 15209 | seginfo = seg_info (l->seg); |
252b5132 | 15210 | |
3b91255e RS |
15211 | /* Set HI_POS to the position of this relocation in the chain. |
15212 | Set LO_POS to the position of the chosen low-part relocation. | |
15213 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15214 | relocation that matches an immediately-preceding high-part | |
15215 | relocation. */ | |
15216 | hi_pos = NULL; | |
15217 | lo_pos = NULL; | |
15218 | matched_lo_p = FALSE; | |
738e5348 | 15219 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15220 | |
3b91255e RS |
15221 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15222 | { | |
15223 | if (*pos == l->fixp) | |
15224 | hi_pos = pos; | |
15225 | ||
35903be0 | 15226 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15227 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15228 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15229 | && (lo_pos == NULL | |
15230 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15231 | || (!matched_lo_p | |
15232 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15233 | lo_pos = pos; | |
15234 | ||
15235 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15236 | && fixup_has_matching_lo_p (*pos)); | |
15237 | } | |
15238 | ||
15239 | /* If we found a match, remove the high-part relocation from its | |
15240 | current position and insert it before the low-part relocation. | |
15241 | Make the offsets match so that fixup_has_matching_lo_p() | |
15242 | will return true. | |
15243 | ||
15244 | We don't warn about unmatched high-part relocations since some | |
15245 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15246 | instructions. */ | |
15247 | if (lo_pos != NULL) | |
15248 | { | |
15249 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15250 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15251 | { |
3b91255e RS |
15252 | *hi_pos = l->fixp->fx_next; |
15253 | l->fixp->fx_next = *lo_pos; | |
15254 | *lo_pos = l->fixp; | |
252b5132 | 15255 | } |
252b5132 RH |
15256 | } |
15257 | } | |
15258 | } | |
15259 | ||
252b5132 | 15260 | int |
17a2f251 | 15261 | mips_force_relocation (fixS *fixp) |
252b5132 | 15262 | { |
ae6063d4 | 15263 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15264 | return 1; |
15265 | ||
df58fc94 RS |
15266 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15267 | so that the linker relaxation can update targets. */ | |
15268 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15269 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15270 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15271 | return 1; | |
15272 | ||
5caa2b07 MR |
15273 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15274 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15275 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15276 | and BAL to JALX conversion by the linker. */ | |
15277 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15278 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15279 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15280 | && fixp->fx_addsy | |
15281 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15282 | return 1; | |
15283 | ||
7361da2c | 15284 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15285 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15286 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15287 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15288 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15289 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15290 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15291 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15292 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15293 | return 1; | |
15294 | ||
3e722fb5 | 15295 | return 0; |
252b5132 RH |
15296 | } |
15297 | ||
b416ba9b MR |
15298 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15299 | ||
15300 | bfd_boolean | |
15301 | mips_force_relocation_abs (fixS *fixp) | |
15302 | { | |
15303 | if (generic_force_reloc (fixp)) | |
15304 | return TRUE; | |
15305 | ||
15306 | /* These relocations do not have enough bits in the in-place addend | |
15307 | to hold an arbitrary absolute section's offset. */ | |
15308 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15309 | return TRUE; | |
15310 | ||
15311 | return FALSE; | |
15312 | } | |
15313 | ||
b886a2ab RS |
15314 | /* Read the instruction associated with RELOC from BUF. */ |
15315 | ||
15316 | static unsigned int | |
15317 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15318 | { | |
15319 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15320 | return read_compressed_insn (buf, 4); | |
15321 | else | |
15322 | return read_insn (buf); | |
15323 | } | |
15324 | ||
15325 | /* Write instruction INSN to BUF, given that it has been relocated | |
15326 | by RELOC. */ | |
15327 | ||
15328 | static void | |
15329 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15330 | unsigned long insn) | |
15331 | { | |
15332 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15333 | write_compressed_insn (buf, insn, 4); | |
15334 | else | |
15335 | write_insn (buf, insn); | |
15336 | } | |
15337 | ||
9d862524 MR |
15338 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15339 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15340 | ||
15341 | static bfd_boolean | |
15342 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15343 | { | |
15344 | unsigned long opcode; | |
15345 | int other; | |
15346 | char *buf; | |
15347 | ||
15348 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15349 | return FALSE; | |
15350 | ||
15351 | other = S_GET_OTHER (fixP->fx_addsy); | |
15352 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15353 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15354 | switch (fixP->fx_r_type) | |
15355 | { | |
15356 | case BFD_RELOC_MIPS_JMP: | |
15357 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15358 | case BFD_RELOC_MICROMIPS_JMP: | |
15359 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15360 | default: | |
15361 | return FALSE; | |
15362 | } | |
15363 | } | |
15364 | ||
15365 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15366 | jump to a symbol in the same ISA mode. */ | |
15367 | ||
15368 | static bfd_boolean | |
15369 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15370 | { | |
15371 | unsigned long opcode; | |
15372 | int other; | |
15373 | char *buf; | |
15374 | ||
15375 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15376 | return FALSE; | |
15377 | ||
15378 | other = S_GET_OTHER (fixP->fx_addsy); | |
15379 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15380 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15381 | switch (fixP->fx_r_type) | |
15382 | { | |
15383 | case BFD_RELOC_MIPS_JMP: | |
15384 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15385 | case BFD_RELOC_MIPS16_JMP: | |
15386 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15387 | case BFD_RELOC_MICROMIPS_JMP: | |
15388 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15389 | default: | |
15390 | return FALSE; | |
15391 | } | |
15392 | } | |
15393 | ||
15394 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15395 | to a symbol whose value plus addend is not aligned according to the | |
15396 | ultimate (after linker relaxation) jump instruction's immediate field | |
15397 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15398 | regular MIPS code, to (1 << 2). */ | |
15399 | ||
15400 | static bfd_boolean | |
15401 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15402 | { | |
15403 | bfd_boolean micro_to_mips_p; | |
15404 | valueT val; | |
15405 | int other; | |
15406 | ||
15407 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15408 | return FALSE; | |
15409 | ||
15410 | other = S_GET_OTHER (fixP->fx_addsy); | |
15411 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15412 | val += fixP->fx_offset; | |
15413 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15414 | && !ELF_ST_IS_MICROMIPS (other)); | |
15415 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15416 | != ELF_ST_IS_COMPRESSED (other)); | |
15417 | } | |
15418 | ||
15419 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15420 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15421 | symbols check the ISA bit instead. |
15422 | ||
15423 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15424 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15425 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15426 | may be converted to JALX by the linker. */ |
9d862524 MR |
15427 | |
15428 | static bfd_boolean | |
15429 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15430 | { | |
15431 | bfd_boolean absolute_p; | |
15432 | unsigned long opcode; | |
15433 | asection *symsec; | |
15434 | valueT val; | |
15435 | int other; | |
15436 | char *buf; | |
15437 | ||
8b10b0b3 MR |
15438 | if (mips_ignore_branch_isa) |
15439 | return FALSE; | |
15440 | ||
9d862524 MR |
15441 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15442 | return FALSE; | |
15443 | ||
15444 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15445 | absolute_p = bfd_is_abs_section (symsec); | |
15446 | ||
15447 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15448 | other = S_GET_OTHER (fixP->fx_addsy); | |
15449 | ||
15450 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15451 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15452 | switch (fixP->fx_r_type) | |
15453 | { | |
15454 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15455 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15456 | && opcode != 0x0411); | |
15457 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15458 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15459 | && opcode != 0x4060); | |
9d862524 MR |
15460 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15461 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15462 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15463 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15464 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15465 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15466 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15467 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15468 | default: | |
15469 | abort (); | |
15470 | } | |
15471 | } | |
15472 | ||
15473 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15474 | branch instruction pointed to by FIXP is not aligned according to the | |
15475 | branch instruction's immediate field requirement. We need the addend | |
15476 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15477 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15478 | won't be set in the symbol's value then. */ | |
15479 | ||
15480 | static bfd_boolean | |
15481 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15482 | { | |
15483 | bfd_boolean absolute_p; | |
15484 | asection *symsec; | |
15485 | valueT isa_bit; | |
15486 | valueT val; | |
15487 | valueT off; | |
15488 | int other; | |
15489 | ||
15490 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15491 | return FALSE; | |
15492 | ||
15493 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15494 | absolute_p = bfd_is_abs_section (symsec); | |
15495 | ||
15496 | val = S_GET_VALUE (fixP->fx_addsy); | |
15497 | other = S_GET_OTHER (fixP->fx_addsy); | |
15498 | off = fixP->fx_offset; | |
15499 | ||
15500 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15501 | val |= ELF_ST_IS_COMPRESSED (other); | |
15502 | val += off; | |
15503 | return (val & 0x3) != isa_bit; | |
15504 | } | |
15505 | ||
15506 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15507 | and its calculated value VAL. */ | |
15508 | ||
15509 | static void | |
15510 | fix_validate_branch (fixS *fixP, valueT val) | |
15511 | { | |
15512 | if (fixP->fx_done && (val & 0x3) != 0) | |
15513 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15514 | _("branch to misaligned address (0x%lx)"), | |
15515 | (long) (val + md_pcrel_from (fixP))); | |
15516 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15517 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15518 | _("branch to a symbol in another ISA mode")); | |
15519 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15520 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15521 | _("branch to misaligned address (0x%lx)"), | |
15522 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15523 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15524 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15525 | _("cannot encode misaligned addend " | |
15526 | "in the relocatable field (0x%lx)"), | |
15527 | (long) fixP->fx_offset); | |
15528 | } | |
15529 | ||
252b5132 RH |
15530 | /* Apply a fixup to the object file. */ |
15531 | ||
94f592af | 15532 | void |
55cf6793 | 15533 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15534 | { |
4d68580a | 15535 | char *buf; |
b886a2ab | 15536 | unsigned long insn; |
a7ebbfdf | 15537 | reloc_howto_type *howto; |
252b5132 | 15538 | |
d56a8dda RS |
15539 | if (fixP->fx_pcrel) |
15540 | switch (fixP->fx_r_type) | |
15541 | { | |
15542 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15543 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15544 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15545 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15546 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15547 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15548 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15549 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15550 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15551 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15552 | case BFD_RELOC_HI16_S_PCREL: | |
15553 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15554 | break; |
15555 | ||
15556 | case BFD_RELOC_32: | |
15557 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15558 | break; | |
15559 | ||
15560 | default: | |
15561 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15562 | _("PC-relative reference to a different section")); | |
15563 | break; | |
15564 | } | |
15565 | ||
15566 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15567 | that have no MIPS ELF equivalent. */ | |
15568 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15569 | { | |
15570 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15571 | if (!howto) | |
15572 | return; | |
15573 | } | |
65551fa4 | 15574 | |
df58fc94 RS |
15575 | gas_assert (fixP->fx_size == 2 |
15576 | || fixP->fx_size == 4 | |
d56a8dda | 15577 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15578 | || fixP->fx_r_type == BFD_RELOC_16 |
15579 | || fixP->fx_r_type == BFD_RELOC_64 | |
15580 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15581 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15582 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15583 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15584 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15585 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15586 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15587 | |
4d68580a | 15588 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15589 | |
b1dca8ee RS |
15590 | /* Don't treat parts of a composite relocation as done. There are two |
15591 | reasons for this: | |
15592 | ||
15593 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15594 | should nevertheless be emitted if the first part is. | |
15595 | ||
15596 | (2) In normal usage, composite relocations are never assembly-time | |
15597 | constants. The easiest way of dealing with the pathological | |
15598 | exceptions is to generate a relocation against STN_UNDEF and | |
15599 | leave everything up to the linker. */ | |
3994f87e | 15600 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15601 | fixP->fx_done = 1; |
15602 | ||
15603 | switch (fixP->fx_r_type) | |
15604 | { | |
3f98094e DJ |
15605 | case BFD_RELOC_MIPS_TLS_GD: |
15606 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15607 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15608 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15609 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15610 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15611 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15612 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15613 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15614 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15615 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15616 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15617 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15618 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15619 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15620 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15621 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15622 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15623 | case BFD_RELOC_MIPS16_TLS_GD: |
15624 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15625 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15626 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15627 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15628 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15629 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15630 | if (fixP->fx_addsy) |
15631 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15632 | else | |
15633 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15634 | _("TLS relocation against a constant")); | |
15635 | break; | |
3f98094e | 15636 | |
252b5132 | 15637 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15638 | case BFD_RELOC_MIPS16_JMP: |
15639 | case BFD_RELOC_MICROMIPS_JMP: | |
15640 | { | |
15641 | int shift; | |
15642 | ||
15643 | gas_assert (!fixP->fx_done); | |
15644 | ||
15645 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15646 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15647 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15648 | shift = 1; | |
15649 | else | |
15650 | shift = 2; | |
15651 | ||
15652 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15653 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15654 | _("jump to a symbol in another ISA mode")); | |
15655 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15656 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15657 | _("JALX to a symbol in the same ISA mode")); | |
15658 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15659 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15660 | _("jump to misaligned address (0x%lx)"), | |
15661 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15662 | + fixP->fx_offset)); | |
15663 | else if (HAVE_IN_PLACE_ADDENDS | |
15664 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15666 | _("cannot encode misaligned addend " | |
15667 | "in the relocatable field (0x%lx)"), | |
15668 | (long) fixP->fx_offset); | |
15669 | } | |
15670 | /* Fall through. */ | |
15671 | ||
e369bcce TS |
15672 | case BFD_RELOC_MIPS_SHIFT5: |
15673 | case BFD_RELOC_MIPS_SHIFT6: | |
15674 | case BFD_RELOC_MIPS_GOT_DISP: | |
15675 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15676 | case BFD_RELOC_MIPS_GOT_OFST: | |
15677 | case BFD_RELOC_MIPS_SUB: | |
15678 | case BFD_RELOC_MIPS_INSERT_A: | |
15679 | case BFD_RELOC_MIPS_INSERT_B: | |
15680 | case BFD_RELOC_MIPS_DELETE: | |
15681 | case BFD_RELOC_MIPS_HIGHEST: | |
15682 | case BFD_RELOC_MIPS_HIGHER: | |
15683 | case BFD_RELOC_MIPS_SCN_DISP: | |
15684 | case BFD_RELOC_MIPS_REL16: | |
15685 | case BFD_RELOC_MIPS_RELGOT: | |
15686 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15687 | case BFD_RELOC_HI16: |
15688 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15689 | case BFD_RELOC_LO16: |
cdf6fd85 | 15690 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15691 | case BFD_RELOC_MIPS_LITERAL: |
15692 | case BFD_RELOC_MIPS_CALL16: | |
15693 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15694 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15695 | case BFD_RELOC_MIPS_GOT_HI16: |
15696 | case BFD_RELOC_MIPS_GOT_LO16: | |
15697 | case BFD_RELOC_MIPS_CALL_HI16: | |
15698 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15699 | case BFD_RELOC_HI16_S_PCREL: |
15700 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15701 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15702 | case BFD_RELOC_MIPS16_GOT16: |
15703 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15704 | case BFD_RELOC_MIPS16_HI16: |
15705 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15706 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15707 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15708 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15709 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15710 | case BFD_RELOC_MICROMIPS_SUB: | |
15711 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15712 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15713 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15714 | case BFD_RELOC_MICROMIPS_JALR: | |
15715 | case BFD_RELOC_MICROMIPS_HI16: | |
15716 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15717 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15718 | case BFD_RELOC_MICROMIPS_GPREL16: |
15719 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15720 | case BFD_RELOC_MICROMIPS_CALL16: | |
15721 | case BFD_RELOC_MICROMIPS_GOT16: | |
15722 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15723 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15724 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15725 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15726 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15727 | if (fixP->fx_done) |
15728 | { | |
15729 | offsetT value; | |
15730 | ||
15731 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15732 | { | |
15733 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15734 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15735 | insn |= mips16_immed_extend (value, 16); | |
15736 | else | |
15737 | insn |= (value & 0xffff); | |
15738 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15739 | } | |
15740 | else | |
15741 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15742 | _("unsupported constant in relocation")); |
b886a2ab | 15743 | } |
252b5132 RH |
15744 | break; |
15745 | ||
252b5132 RH |
15746 | case BFD_RELOC_64: |
15747 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15748 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15749 | if (fixP->fx_done) |
252b5132 RH |
15750 | { |
15751 | if (8 <= sizeof (valueT)) | |
4d68580a | 15752 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15753 | else |
15754 | { | |
a7ebbfdf | 15755 | valueT hiv; |
252b5132 | 15756 | |
a7ebbfdf | 15757 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15758 | hiv = 0xffffffff; |
15759 | else | |
15760 | hiv = 0; | |
4d68580a RS |
15761 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15762 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15763 | } |
15764 | } | |
15765 | break; | |
15766 | ||
056350c6 | 15767 | case BFD_RELOC_RVA: |
252b5132 | 15768 | case BFD_RELOC_32: |
b47468a6 | 15769 | case BFD_RELOC_32_PCREL: |
252b5132 | 15770 | case BFD_RELOC_16: |
d56a8dda | 15771 | case BFD_RELOC_8: |
252b5132 | 15772 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15773 | value now. This can happen if we have a .word which is not |
15774 | resolved when it appears but is later defined. */ | |
252b5132 | 15775 | if (fixP->fx_done) |
4d68580a | 15776 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15777 | break; |
15778 | ||
7361da2c | 15779 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15780 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15781 | if (!fixP->fx_done) |
15782 | break; | |
15783 | ||
15784 | if (*valP + 0x400000 <= 0x7fffff) | |
15785 | { | |
15786 | insn = read_insn (buf); | |
15787 | insn |= (*valP >> 2) & 0x1fffff; | |
15788 | write_insn (buf, insn); | |
15789 | } | |
15790 | else | |
15791 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15792 | _("branch out of range")); | |
15793 | break; | |
15794 | ||
7361da2c | 15795 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15796 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15797 | if (!fixP->fx_done) |
15798 | break; | |
7361da2c | 15799 | |
41947d9e MR |
15800 | if (*valP + 0x8000000 <= 0xfffffff) |
15801 | { | |
15802 | insn = read_insn (buf); | |
15803 | insn |= (*valP >> 2) & 0x3ffffff; | |
15804 | write_insn (buf, insn); | |
15805 | } | |
15806 | else | |
15807 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15808 | _("branch out of range")); | |
7361da2c AB |
15809 | break; |
15810 | ||
15811 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15812 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15813 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15814 | _("PC-relative access using misaligned symbol (%lx)"), |
15815 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15816 | if ((fixP->fx_offset & 0x7) != 0) | |
15817 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15818 | _("PC-relative access using misaligned offset (%lx)"), | |
15819 | (long) fixP->fx_offset); | |
41947d9e MR |
15820 | if (!fixP->fx_done) |
15821 | break; | |
7361da2c | 15822 | |
41947d9e MR |
15823 | if (*valP + 0x100000 <= 0x1fffff) |
15824 | { | |
15825 | insn = read_insn (buf); | |
15826 | insn |= (*valP >> 3) & 0x3ffff; | |
15827 | write_insn (buf, insn); | |
15828 | } | |
15829 | else | |
15830 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15831 | _("PC-relative access out of range")); | |
7361da2c AB |
15832 | break; |
15833 | ||
15834 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15835 | if ((*valP & 0x3) != 0) | |
15836 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15837 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15838 | (long) *valP); |
41947d9e MR |
15839 | if (!fixP->fx_done) |
15840 | break; | |
7361da2c | 15841 | |
41947d9e MR |
15842 | if (*valP + 0x100000 <= 0x1fffff) |
15843 | { | |
15844 | insn = read_insn (buf); | |
15845 | insn |= (*valP >> 2) & 0x7ffff; | |
15846 | write_insn (buf, insn); | |
15847 | } | |
15848 | else | |
15849 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15850 | _("PC-relative access out of range")); | |
7361da2c AB |
15851 | break; |
15852 | ||
252b5132 | 15853 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15854 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15855 | |
54f4ddb3 TS |
15856 | /* We need to save the bits in the instruction since fixup_segment() |
15857 | might be deleting the relocation entry (i.e., a branch within | |
15858 | the current segment). */ | |
a7ebbfdf | 15859 | if (! fixP->fx_done) |
bb2d6cd7 | 15860 | break; |
252b5132 | 15861 | |
54f4ddb3 | 15862 | /* Update old instruction data. */ |
4d68580a | 15863 | insn = read_insn (buf); |
252b5132 | 15864 | |
a7ebbfdf TS |
15865 | if (*valP + 0x20000 <= 0x3ffff) |
15866 | { | |
15867 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15868 | write_insn (buf, insn); |
a7ebbfdf | 15869 | } |
ce8ad872 | 15870 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15871 | && fixP->fx_done |
15872 | && fixP->fx_frag->fr_address >= text_section->vma | |
15873 | && (fixP->fx_frag->fr_address | |
587aac4e | 15874 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15875 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15876 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15877 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15878 | { |
15879 | /* The branch offset is too large. If this is an | |
15880 | unconditional branch, and we are not generating PIC code, | |
15881 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15882 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15883 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15884 | else |
a7ebbfdf TS |
15885 | insn = 0x08000000; /* j */ |
15886 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15887 | fixP->fx_done = 0; | |
15888 | fixP->fx_addsy = section_symbol (text_section); | |
15889 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15890 | write_insn (buf, insn); |
a7ebbfdf TS |
15891 | } |
15892 | else | |
15893 | { | |
15894 | /* If we got here, we have branch-relaxation disabled, | |
15895 | and there's nothing we can do to fix this instruction | |
15896 | without turning it into a longer sequence. */ | |
15897 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15898 | _("branch out of range")); |
252b5132 | 15899 | } |
252b5132 RH |
15900 | break; |
15901 | ||
c9775dde | 15902 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15903 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15904 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15905 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15906 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15907 | if (fix_bad_cross_mode_branch_p (fixP)) |
15908 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15909 | _("branch to a symbol in another ISA mode")); | |
15910 | else if (fixP->fx_addsy | |
15911 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15912 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15913 | && (fixP->fx_offset & 0x1) != 0) | |
15914 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15915 | _("branch to misaligned address (0x%lx)"), | |
15916 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15917 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15918 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15919 | _("cannot encode misaligned addend " | |
15920 | "in the relocatable field (0x%lx)"), | |
15921 | (long) fixP->fx_offset); | |
df58fc94 RS |
15922 | break; |
15923 | ||
252b5132 RH |
15924 | case BFD_RELOC_VTABLE_INHERIT: |
15925 | fixP->fx_done = 0; | |
15926 | if (fixP->fx_addsy | |
15927 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15928 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15929 | S_SET_WEAK (fixP->fx_addsy); | |
15930 | break; | |
15931 | ||
2f0c68f2 | 15932 | case BFD_RELOC_NONE: |
252b5132 RH |
15933 | case BFD_RELOC_VTABLE_ENTRY: |
15934 | fixP->fx_done = 0; | |
15935 | break; | |
15936 | ||
15937 | default: | |
b37df7c4 | 15938 | abort (); |
252b5132 | 15939 | } |
a7ebbfdf TS |
15940 | |
15941 | /* Remember value for tc_gen_reloc. */ | |
15942 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15943 | } |
15944 | ||
252b5132 | 15945 | static symbolS * |
17a2f251 | 15946 | get_symbol (void) |
252b5132 RH |
15947 | { |
15948 | int c; | |
15949 | char *name; | |
15950 | symbolS *p; | |
15951 | ||
d02603dc | 15952 | c = get_symbol_name (&name); |
252b5132 | 15953 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15954 | (void) restore_line_pointer (c); |
252b5132 RH |
15955 | return p; |
15956 | } | |
15957 | ||
742a56fe RS |
15958 | /* Align the current frag to a given power of two. If a particular |
15959 | fill byte should be used, FILL points to an integer that contains | |
15960 | that byte, otherwise FILL is null. | |
15961 | ||
462427c4 RS |
15962 | This function used to have the comment: |
15963 | ||
15964 | The MIPS assembler also automatically adjusts any preceding label. | |
15965 | ||
15966 | The implementation therefore applied the adjustment to a maximum of | |
15967 | one label. However, other label adjustments are applied to batches | |
15968 | of labels, and adjusting just one caused problems when new labels | |
15969 | were added for the sake of debugging or unwind information. | |
15970 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15971 | |
15972 | static void | |
462427c4 | 15973 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15974 | { |
7d10b47d | 15975 | mips_emit_delays (); |
df58fc94 | 15976 | mips_record_compressed_mode (); |
742a56fe RS |
15977 | if (fill == NULL && subseg_text_p (now_seg)) |
15978 | frag_align_code (to, 0); | |
15979 | else | |
15980 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15981 | record_alignment (now_seg, to); |
462427c4 | 15982 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15983 | } |
15984 | ||
15985 | /* Align to a given power of two. .align 0 turns off the automatic | |
15986 | alignment used by the data creating pseudo-ops. */ | |
15987 | ||
15988 | static void | |
17a2f251 | 15989 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15990 | { |
742a56fe | 15991 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15992 | long max_alignment = 28; |
252b5132 | 15993 | |
54f4ddb3 | 15994 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15995 | to the aligned address. |
54f4ddb3 | 15996 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15997 | a .align pseudo instruction. |
54f4ddb3 | 15998 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15999 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16000 | We don't. */ |
252b5132 RH |
16001 | |
16002 | temp = get_absolute_expression (); | |
16003 | if (temp > max_alignment) | |
1661c76c | 16004 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
16005 | else if (temp < 0) |
16006 | { | |
1661c76c | 16007 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
16008 | temp = 0; |
16009 | } | |
16010 | if (*input_line_pointer == ',') | |
16011 | { | |
f9419b05 | 16012 | ++input_line_pointer; |
742a56fe RS |
16013 | fill_value = get_absolute_expression (); |
16014 | fill_ptr = &fill_value; | |
252b5132 RH |
16015 | } |
16016 | else | |
742a56fe | 16017 | fill_ptr = 0; |
252b5132 RH |
16018 | if (temp) |
16019 | { | |
a8dbcb85 TS |
16020 | segment_info_type *si = seg_info (now_seg); |
16021 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16022 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16023 | auto_align = 1; |
462427c4 | 16024 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16025 | } |
16026 | else | |
16027 | { | |
16028 | auto_align = 0; | |
16029 | } | |
16030 | ||
16031 | demand_empty_rest_of_line (); | |
16032 | } | |
16033 | ||
252b5132 | 16034 | static void |
17a2f251 | 16035 | s_change_sec (int sec) |
252b5132 RH |
16036 | { |
16037 | segT seg; | |
16038 | ||
252b5132 RH |
16039 | /* The ELF backend needs to know that we are changing sections, so |
16040 | that .previous works correctly. We could do something like check | |
b6ff326e | 16041 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16042 | as it would not be appropriate to use it in the section changing |
16043 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16044 | This should be cleaner, somehow. */ | |
f3ded42a | 16045 | obj_elf_section_change_hook (); |
252b5132 | 16046 | |
7d10b47d | 16047 | mips_emit_delays (); |
6a32d874 | 16048 | |
252b5132 RH |
16049 | switch (sec) |
16050 | { | |
16051 | case 't': | |
16052 | s_text (0); | |
16053 | break; | |
16054 | case 'd': | |
16055 | s_data (0); | |
16056 | break; | |
16057 | case 'b': | |
16058 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16059 | demand_empty_rest_of_line (); | |
16060 | break; | |
16061 | ||
16062 | case 'r': | |
4d0d148d TS |
16063 | seg = subseg_new (RDATA_SECTION_NAME, |
16064 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16065 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16066 | | SEC_READONLY | SEC_RELOC | |
16067 | | SEC_DATA)); | |
16068 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16069 | record_alignment (seg, 4); | |
4d0d148d | 16070 | demand_empty_rest_of_line (); |
252b5132 RH |
16071 | break; |
16072 | ||
16073 | case 's': | |
4d0d148d | 16074 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16075 | bfd_set_section_flags (stdoutput, seg, |
16076 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16077 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16078 | record_alignment (seg, 4); | |
4d0d148d TS |
16079 | demand_empty_rest_of_line (); |
16080 | break; | |
998b3c36 MR |
16081 | |
16082 | case 'B': | |
16083 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16084 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16085 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16086 | record_alignment (seg, 4); | |
998b3c36 MR |
16087 | demand_empty_rest_of_line (); |
16088 | break; | |
252b5132 RH |
16089 | } |
16090 | ||
16091 | auto_align = 1; | |
16092 | } | |
b34976b6 | 16093 | |
cca86cc8 | 16094 | void |
17a2f251 | 16095 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16096 | { |
d02603dc | 16097 | char *saved_ilp; |
cca86cc8 | 16098 | char *section_name; |
d02603dc | 16099 | char c, endc; |
684022ea | 16100 | char next_c = 0; |
cca86cc8 SC |
16101 | int section_type; |
16102 | int section_flag; | |
16103 | int section_entry_size; | |
16104 | int section_alignment; | |
b34976b6 | 16105 | |
d02603dc NC |
16106 | saved_ilp = input_line_pointer; |
16107 | endc = get_symbol_name (§ion_name); | |
16108 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16109 | if (c) |
d02603dc | 16110 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16111 | |
4cf0dd0d TS |
16112 | /* Do we have .section Name<,"flags">? */ |
16113 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16114 | { |
d02603dc NC |
16115 | /* Just after name is now '\0'. */ |
16116 | (void) restore_line_pointer (endc); | |
16117 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16118 | obj_elf_section (ignore); |
16119 | return; | |
16120 | } | |
d02603dc NC |
16121 | |
16122 | section_name = xstrdup (section_name); | |
16123 | c = restore_line_pointer (endc); | |
16124 | ||
cca86cc8 SC |
16125 | input_line_pointer++; |
16126 | ||
16127 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16128 | if (c == ',') | |
16129 | section_type = get_absolute_expression (); | |
16130 | else | |
16131 | section_type = 0; | |
d02603dc | 16132 | |
cca86cc8 SC |
16133 | if (*input_line_pointer++ == ',') |
16134 | section_flag = get_absolute_expression (); | |
16135 | else | |
16136 | section_flag = 0; | |
d02603dc | 16137 | |
cca86cc8 SC |
16138 | if (*input_line_pointer++ == ',') |
16139 | section_entry_size = get_absolute_expression (); | |
16140 | else | |
16141 | section_entry_size = 0; | |
d02603dc | 16142 | |
cca86cc8 SC |
16143 | if (*input_line_pointer++ == ',') |
16144 | section_alignment = get_absolute_expression (); | |
16145 | else | |
16146 | section_alignment = 0; | |
d02603dc | 16147 | |
87975d2a AM |
16148 | /* FIXME: really ignore? */ |
16149 | (void) section_alignment; | |
cca86cc8 | 16150 | |
8ab8a5c8 RS |
16151 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16152 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16153 | traditionally had to fall back on the more common @progbits instead. | |
16154 | ||
16155 | There's nothing really harmful in this, since bfd will correct | |
16156 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16157 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16158 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16159 | ||
16160 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16161 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16162 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16163 | generic type-checking code. */ | |
16164 | if (section_type == SHT_MIPS_DWARF) | |
16165 | section_type = SHT_PROGBITS; | |
16166 | ||
a91e1603 | 16167 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16168 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16169 | |
16170 | if (now_seg->name != section_name) | |
16171 | free (section_name); | |
cca86cc8 | 16172 | } |
252b5132 RH |
16173 | |
16174 | void | |
17a2f251 | 16175 | mips_enable_auto_align (void) |
252b5132 RH |
16176 | { |
16177 | auto_align = 1; | |
16178 | } | |
16179 | ||
16180 | static void | |
17a2f251 | 16181 | s_cons (int log_size) |
252b5132 | 16182 | { |
a8dbcb85 TS |
16183 | segment_info_type *si = seg_info (now_seg); |
16184 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16185 | |
7d10b47d | 16186 | mips_emit_delays (); |
252b5132 | 16187 | if (log_size > 0 && auto_align) |
462427c4 | 16188 | mips_align (log_size, 0, l); |
252b5132 | 16189 | cons (1 << log_size); |
a1facbec | 16190 | mips_clear_insn_labels (); |
252b5132 RH |
16191 | } |
16192 | ||
16193 | static void | |
17a2f251 | 16194 | s_float_cons (int type) |
252b5132 | 16195 | { |
a8dbcb85 TS |
16196 | segment_info_type *si = seg_info (now_seg); |
16197 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16198 | |
7d10b47d | 16199 | mips_emit_delays (); |
252b5132 RH |
16200 | |
16201 | if (auto_align) | |
49309057 ILT |
16202 | { |
16203 | if (type == 'd') | |
462427c4 | 16204 | mips_align (3, 0, l); |
49309057 | 16205 | else |
462427c4 | 16206 | mips_align (2, 0, l); |
49309057 | 16207 | } |
252b5132 | 16208 | |
252b5132 | 16209 | float_cons (type); |
a1facbec | 16210 | mips_clear_insn_labels (); |
252b5132 RH |
16211 | } |
16212 | ||
16213 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16214 | permitted to say | |
16215 | .globl foo .text | |
16216 | where foo is an undefined symbol, to mean that foo should be | |
16217 | considered to be the address of a function. */ | |
16218 | ||
16219 | static void | |
17a2f251 | 16220 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16221 | { |
16222 | char *name; | |
16223 | int c; | |
16224 | symbolS *symbolP; | |
16225 | flagword flag; | |
16226 | ||
8a06b769 | 16227 | do |
252b5132 | 16228 | { |
d02603dc | 16229 | c = get_symbol_name (&name); |
8a06b769 TS |
16230 | symbolP = symbol_find_or_make (name); |
16231 | S_SET_EXTERNAL (symbolP); | |
16232 | ||
252b5132 | 16233 | *input_line_pointer = c; |
d02603dc | 16234 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16235 | |
8a06b769 TS |
16236 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16237 | being a function is apparently labelled as being an object. */ | |
16238 | flag = BSF_OBJECT; | |
252b5132 | 16239 | |
8a06b769 TS |
16240 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16241 | && (*input_line_pointer != ',')) | |
16242 | { | |
16243 | char *secname; | |
16244 | asection *sec; | |
16245 | ||
d02603dc | 16246 | c = get_symbol_name (&secname); |
8a06b769 TS |
16247 | sec = bfd_get_section_by_name (stdoutput, secname); |
16248 | if (sec == NULL) | |
16249 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16250 | (void) restore_line_pointer (c); |
8a06b769 TS |
16251 | |
16252 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16253 | flag = BSF_FUNCTION; | |
16254 | } | |
16255 | ||
16256 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16257 | ||
16258 | c = *input_line_pointer; | |
16259 | if (c == ',') | |
16260 | { | |
16261 | input_line_pointer++; | |
16262 | SKIP_WHITESPACE (); | |
16263 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16264 | c = '\n'; | |
16265 | } | |
16266 | } | |
16267 | while (c == ','); | |
252b5132 | 16268 | |
252b5132 RH |
16269 | demand_empty_rest_of_line (); |
16270 | } | |
16271 | ||
16272 | static void | |
17a2f251 | 16273 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16274 | { |
16275 | char *opt; | |
16276 | char c; | |
16277 | ||
d02603dc | 16278 | c = get_symbol_name (&opt); |
252b5132 RH |
16279 | |
16280 | if (*opt == 'O') | |
16281 | { | |
16282 | /* FIXME: What does this mean? */ | |
16283 | } | |
41a1578e | 16284 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16285 | { |
16286 | int i; | |
16287 | ||
16288 | i = atoi (opt + 3); | |
668c5ebc MR |
16289 | if (i != 0 && i != 2) |
16290 | as_bad (_(".option pic%d not supported"), i); | |
16291 | else if (mips_pic == VXWORKS_PIC) | |
16292 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16293 | else if (i == 0) | |
252b5132 RH |
16294 | mips_pic = NO_PIC; |
16295 | else if (i == 2) | |
143d77c5 | 16296 | { |
8b828383 | 16297 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16298 | mips_abicalls = TRUE; |
16299 | } | |
252b5132 | 16300 | |
4d0d148d | 16301 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16302 | { |
16303 | if (g_switch_seen && g_switch_value != 0) | |
16304 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16305 | g_switch_value = 0; | |
16306 | bfd_set_gp_size (stdoutput, 0); | |
16307 | } | |
16308 | } | |
16309 | else | |
1661c76c | 16310 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16311 | |
d02603dc | 16312 | (void) restore_line_pointer (c); |
252b5132 RH |
16313 | demand_empty_rest_of_line (); |
16314 | } | |
16315 | ||
16316 | /* This structure is used to hold a stack of .set values. */ | |
16317 | ||
e972090a NC |
16318 | struct mips_option_stack |
16319 | { | |
252b5132 RH |
16320 | struct mips_option_stack *next; |
16321 | struct mips_set_options options; | |
16322 | }; | |
16323 | ||
16324 | static struct mips_option_stack *mips_opts_stack; | |
16325 | ||
22522f88 MR |
16326 | /* Return status for .set/.module option handling. */ |
16327 | ||
16328 | enum code_option_type | |
16329 | { | |
16330 | /* Unrecognized option. */ | |
16331 | OPTION_TYPE_BAD = -1, | |
16332 | ||
16333 | /* Ordinary option. */ | |
16334 | OPTION_TYPE_NORMAL, | |
16335 | ||
16336 | /* ISA changing option. */ | |
16337 | OPTION_TYPE_ISA | |
16338 | }; | |
16339 | ||
16340 | /* Handle common .set/.module options. Return status indicating option | |
16341 | type. */ | |
16342 | ||
16343 | static enum code_option_type | |
919731af | 16344 | parse_code_option (char * name) |
252b5132 | 16345 | { |
22522f88 | 16346 | bfd_boolean isa_set = FALSE; |
c6278170 | 16347 | const struct mips_ase *ase; |
22522f88 | 16348 | |
919731af | 16349 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16350 | { |
16351 | char *s = name + 3; | |
16352 | ||
16353 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16354 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16355 | } |
252b5132 | 16356 | else if (strcmp (name, "at") == 0) |
919731af | 16357 | mips_opts.at = ATREG; |
252b5132 | 16358 | else if (strcmp (name, "noat") == 0) |
919731af | 16359 | mips_opts.at = ZERO; |
252b5132 | 16360 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16361 | mips_opts.nomove = 0; |
252b5132 | 16362 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16363 | mips_opts.nomove = 1; |
252b5132 | 16364 | else if (strcmp (name, "bopt") == 0) |
919731af | 16365 | mips_opts.nobopt = 0; |
252b5132 | 16366 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16367 | mips_opts.nobopt = 1; |
ad3fea08 | 16368 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16369 | mips_opts.gp = 32; |
ad3fea08 | 16370 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16371 | mips_opts.gp = 64; |
ad3fea08 | 16372 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16373 | mips_opts.fp = 32; |
351cdf24 MF |
16374 | else if (strcmp (name, "fp=xx") == 0) |
16375 | mips_opts.fp = 0; | |
ad3fea08 | 16376 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16377 | mips_opts.fp = 64; |
037b32b9 AN |
16378 | else if (strcmp (name, "softfloat") == 0) |
16379 | mips_opts.soft_float = 1; | |
16380 | else if (strcmp (name, "hardfloat") == 0) | |
16381 | mips_opts.soft_float = 0; | |
16382 | else if (strcmp (name, "singlefloat") == 0) | |
16383 | mips_opts.single_float = 1; | |
16384 | else if (strcmp (name, "doublefloat") == 0) | |
16385 | mips_opts.single_float = 0; | |
351cdf24 MF |
16386 | else if (strcmp (name, "nooddspreg") == 0) |
16387 | mips_opts.oddspreg = 0; | |
16388 | else if (strcmp (name, "oddspreg") == 0) | |
16389 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16390 | else if (strcmp (name, "mips16") == 0 |
16391 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16392 | mips_opts.mips16 = 1; |
252b5132 RH |
16393 | else if (strcmp (name, "nomips16") == 0 |
16394 | || strcmp (name, "noMIPS-16") == 0) | |
16395 | mips_opts.mips16 = 0; | |
df58fc94 | 16396 | else if (strcmp (name, "micromips") == 0) |
919731af | 16397 | mips_opts.micromips = 1; |
df58fc94 RS |
16398 | else if (strcmp (name, "nomicromips") == 0) |
16399 | mips_opts.micromips = 0; | |
c6278170 RS |
16400 | else if (name[0] == 'n' |
16401 | && name[1] == 'o' | |
16402 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16403 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16404 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16405 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16406 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16407 | { |
1a2c1fad CD |
16408 | /* Permit the user to change the ISA and architecture on the fly. |
16409 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16410 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16411 | { |
16412 | const struct mips_cpu_info *p; | |
16413 | ||
919731af | 16414 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16415 | if (!p) |
16416 | as_bad (_("unknown architecture %s"), name + 5); | |
16417 | else | |
16418 | { | |
16419 | mips_opts.arch = p->cpu; | |
16420 | mips_opts.isa = p->isa; | |
22522f88 | 16421 | isa_set = TRUE; |
1a2c1fad CD |
16422 | } |
16423 | } | |
81a21e38 TS |
16424 | else if (strncmp (name, "mips", 4) == 0) |
16425 | { | |
16426 | const struct mips_cpu_info *p; | |
16427 | ||
919731af | 16428 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16429 | if (!p) |
16430 | as_bad (_("unknown ISA level %s"), name + 4); | |
16431 | else | |
16432 | { | |
16433 | mips_opts.arch = p->cpu; | |
16434 | mips_opts.isa = p->isa; | |
22522f88 | 16435 | isa_set = TRUE; |
81a21e38 TS |
16436 | } |
16437 | } | |
af7ee8bf | 16438 | else |
81a21e38 | 16439 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16440 | } |
16441 | else if (strcmp (name, "autoextend") == 0) | |
16442 | mips_opts.noautoextend = 0; | |
16443 | else if (strcmp (name, "noautoextend") == 0) | |
16444 | mips_opts.noautoextend = 1; | |
833794fc MR |
16445 | else if (strcmp (name, "insn32") == 0) |
16446 | mips_opts.insn32 = TRUE; | |
16447 | else if (strcmp (name, "noinsn32") == 0) | |
16448 | mips_opts.insn32 = FALSE; | |
919731af | 16449 | else if (strcmp (name, "sym32") == 0) |
16450 | mips_opts.sym32 = TRUE; | |
16451 | else if (strcmp (name, "nosym32") == 0) | |
16452 | mips_opts.sym32 = FALSE; | |
16453 | else | |
22522f88 MR |
16454 | return OPTION_TYPE_BAD; |
16455 | ||
16456 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16457 | } |
16458 | ||
16459 | /* Handle the .set pseudo-op. */ | |
16460 | ||
16461 | static void | |
16462 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16463 | { | |
22522f88 | 16464 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16465 | char *name = input_line_pointer, ch; |
919731af | 16466 | |
16467 | file_mips_check_options (); | |
16468 | ||
16469 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16470 | ++input_line_pointer; | |
16471 | ch = *input_line_pointer; | |
16472 | *input_line_pointer = '\0'; | |
16473 | ||
16474 | if (strchr (name, ',')) | |
16475 | { | |
16476 | /* Generic ".set" directive; use the generic handler. */ | |
16477 | *input_line_pointer = ch; | |
16478 | input_line_pointer = name; | |
16479 | s_set (0); | |
16480 | return; | |
16481 | } | |
16482 | ||
16483 | if (strcmp (name, "reorder") == 0) | |
16484 | { | |
16485 | if (mips_opts.noreorder) | |
16486 | end_noreorder (); | |
16487 | } | |
16488 | else if (strcmp (name, "noreorder") == 0) | |
16489 | { | |
16490 | if (!mips_opts.noreorder) | |
16491 | start_noreorder (); | |
16492 | } | |
16493 | else if (strcmp (name, "macro") == 0) | |
16494 | mips_opts.warn_about_macros = 0; | |
16495 | else if (strcmp (name, "nomacro") == 0) | |
16496 | { | |
16497 | if (mips_opts.noreorder == 0) | |
16498 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16499 | mips_opts.warn_about_macros = 1; | |
16500 | } | |
16501 | else if (strcmp (name, "gp=default") == 0) | |
16502 | mips_opts.gp = file_mips_opts.gp; | |
16503 | else if (strcmp (name, "fp=default") == 0) | |
16504 | mips_opts.fp = file_mips_opts.fp; | |
16505 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16506 | { | |
16507 | mips_opts.isa = file_mips_opts.isa; | |
16508 | mips_opts.arch = file_mips_opts.arch; | |
16509 | mips_opts.gp = file_mips_opts.gp; | |
16510 | mips_opts.fp = file_mips_opts.fp; | |
16511 | } | |
252b5132 RH |
16512 | else if (strcmp (name, "push") == 0) |
16513 | { | |
16514 | struct mips_option_stack *s; | |
16515 | ||
325801bd | 16516 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16517 | s->next = mips_opts_stack; |
16518 | s->options = mips_opts; | |
16519 | mips_opts_stack = s; | |
16520 | } | |
16521 | else if (strcmp (name, "pop") == 0) | |
16522 | { | |
16523 | struct mips_option_stack *s; | |
16524 | ||
16525 | s = mips_opts_stack; | |
16526 | if (s == NULL) | |
16527 | as_bad (_(".set pop with no .set push")); | |
16528 | else | |
16529 | { | |
16530 | /* If we're changing the reorder mode we need to handle | |
16531 | delay slots correctly. */ | |
16532 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16533 | start_noreorder (); |
252b5132 | 16534 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16535 | end_noreorder (); |
252b5132 RH |
16536 | |
16537 | mips_opts = s->options; | |
16538 | mips_opts_stack = s->next; | |
16539 | free (s); | |
16540 | } | |
16541 | } | |
22522f88 MR |
16542 | else |
16543 | { | |
16544 | type = parse_code_option (name); | |
16545 | if (type == OPTION_TYPE_BAD) | |
16546 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16547 | } | |
919731af | 16548 | |
16549 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16550 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16551 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16552 | { |
919731af | 16553 | switch (mips_opts.isa) |
16554 | { | |
16555 | case 0: | |
16556 | break; | |
16557 | case ISA_MIPS1: | |
351cdf24 MF |
16558 | /* MIPS I cannot support FPXX. */ |
16559 | mips_opts.fp = 32; | |
16560 | /* fall-through. */ | |
919731af | 16561 | case ISA_MIPS2: |
16562 | case ISA_MIPS32: | |
16563 | case ISA_MIPS32R2: | |
16564 | case ISA_MIPS32R3: | |
16565 | case ISA_MIPS32R5: | |
16566 | mips_opts.gp = 32; | |
351cdf24 MF |
16567 | if (mips_opts.fp != 0) |
16568 | mips_opts.fp = 32; | |
919731af | 16569 | break; |
7361da2c AB |
16570 | case ISA_MIPS32R6: |
16571 | mips_opts.gp = 32; | |
16572 | mips_opts.fp = 64; | |
16573 | break; | |
919731af | 16574 | case ISA_MIPS3: |
16575 | case ISA_MIPS4: | |
16576 | case ISA_MIPS5: | |
16577 | case ISA_MIPS64: | |
16578 | case ISA_MIPS64R2: | |
16579 | case ISA_MIPS64R3: | |
16580 | case ISA_MIPS64R5: | |
7361da2c | 16581 | case ISA_MIPS64R6: |
919731af | 16582 | mips_opts.gp = 64; |
351cdf24 MF |
16583 | if (mips_opts.fp != 0) |
16584 | { | |
16585 | if (mips_opts.arch == CPU_R5900) | |
16586 | mips_opts.fp = 32; | |
16587 | else | |
16588 | mips_opts.fp = 64; | |
16589 | } | |
919731af | 16590 | break; |
16591 | default: | |
16592 | as_bad (_("unknown ISA level %s"), name + 4); | |
16593 | break; | |
16594 | } | |
e6559e01 | 16595 | } |
919731af | 16596 | |
16597 | mips_check_options (&mips_opts, FALSE); | |
16598 | ||
16599 | mips_check_isa_supports_ases (); | |
16600 | *input_line_pointer = ch; | |
16601 | demand_empty_rest_of_line (); | |
16602 | } | |
16603 | ||
16604 | /* Handle the .module pseudo-op. */ | |
16605 | ||
16606 | static void | |
16607 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16608 | { | |
16609 | char *name = input_line_pointer, ch; | |
16610 | ||
16611 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16612 | ++input_line_pointer; | |
16613 | ch = *input_line_pointer; | |
16614 | *input_line_pointer = '\0'; | |
16615 | ||
16616 | if (!file_mips_opts_checked) | |
252b5132 | 16617 | { |
22522f88 | 16618 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16619 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16620 | ||
16621 | /* Update module level settings from mips_opts. */ | |
16622 | file_mips_opts = mips_opts; | |
252b5132 | 16623 | } |
919731af | 16624 | else |
16625 | as_bad (_(".module is not permitted after generating code")); | |
16626 | ||
252b5132 RH |
16627 | *input_line_pointer = ch; |
16628 | demand_empty_rest_of_line (); | |
16629 | } | |
16630 | ||
16631 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16632 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16633 | ||
16634 | static void | |
17a2f251 | 16635 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16636 | { |
16637 | mips_pic = SVR4_PIC; | |
143d77c5 | 16638 | mips_abicalls = TRUE; |
4d0d148d TS |
16639 | |
16640 | if (g_switch_seen && g_switch_value != 0) | |
16641 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16642 | g_switch_value = 0; | |
16643 | ||
252b5132 RH |
16644 | bfd_set_gp_size (stdoutput, 0); |
16645 | demand_empty_rest_of_line (); | |
16646 | } | |
16647 | ||
16648 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16649 | PIC code. It sets the $gp register for the function based on the | |
16650 | function address, which is in the register named in the argument. | |
16651 | This uses a relocation against _gp_disp, which is handled specially | |
16652 | by the linker. The result is: | |
16653 | lui $gp,%hi(_gp_disp) | |
16654 | addiu $gp,$gp,%lo(_gp_disp) | |
16655 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16656 | The .cpload argument is normally $25 == $t9. |
16657 | ||
16658 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16659 | lui $gp,%hi(__gnu_local_gp) |
16660 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16661 | and the argument is ignored. This saves an instruction, but the |
16662 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16663 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16664 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16665 | |
16666 | static void | |
17a2f251 | 16667 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16668 | { |
16669 | expressionS ex; | |
aa6975fb ILT |
16670 | int reg; |
16671 | int in_shared; | |
252b5132 | 16672 | |
919731af | 16673 | file_mips_check_options (); |
16674 | ||
6478892d TS |
16675 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16676 | .cpload is ignored. */ | |
16677 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16678 | { |
16679 | s_ignore (0); | |
16680 | return; | |
16681 | } | |
16682 | ||
a276b80c MR |
16683 | if (mips_opts.mips16) |
16684 | { | |
16685 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16686 | ignore_rest_of_line (); | |
16687 | return; | |
16688 | } | |
16689 | ||
d3ecfc59 | 16690 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16691 | if (mips_opts.noreorder == 0) |
16692 | as_warn (_(".cpload not in noreorder section")); | |
16693 | ||
aa6975fb ILT |
16694 | reg = tc_get_register (0); |
16695 | ||
16696 | /* If we need to produce a 64-bit address, we are better off using | |
16697 | the default instruction sequence. */ | |
aed1a261 | 16698 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16699 | |
252b5132 | 16700 | ex.X_op = O_symbol; |
bbe506e8 TS |
16701 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16702 | "__gnu_local_gp"); | |
252b5132 RH |
16703 | ex.X_op_symbol = NULL; |
16704 | ex.X_add_number = 0; | |
16705 | ||
16706 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16707 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16708 | |
8a75745d MR |
16709 | mips_mark_labels (); |
16710 | mips_assembling_insn = TRUE; | |
16711 | ||
584892a6 | 16712 | macro_start (); |
67c0d1eb RS |
16713 | macro_build_lui (&ex, mips_gp_register); |
16714 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16715 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16716 | if (in_shared) |
16717 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16718 | mips_gp_register, reg); | |
584892a6 | 16719 | macro_end (); |
252b5132 | 16720 | |
8a75745d | 16721 | mips_assembling_insn = FALSE; |
252b5132 RH |
16722 | demand_empty_rest_of_line (); |
16723 | } | |
16724 | ||
6478892d TS |
16725 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16726 | .cpsetup $reg1, offset|$reg2, label | |
16727 | ||
16728 | If offset is given, this results in: | |
16729 | sd $gp, offset($sp) | |
956cd1d6 | 16730 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16731 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16732 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16733 | |
16734 | If $reg2 is given, this results in: | |
40fc1451 | 16735 | or $reg2, $gp, $0 |
956cd1d6 | 16736 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16737 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16738 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16739 | $reg1 is normally $25 == $t9. |
16740 | ||
16741 | The -mno-shared option replaces the last three instructions with | |
16742 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16743 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16744 | |
6478892d | 16745 | static void |
17a2f251 | 16746 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16747 | { |
16748 | expressionS ex_off; | |
16749 | expressionS ex_sym; | |
16750 | int reg1; | |
6478892d | 16751 | |
919731af | 16752 | file_mips_check_options (); |
16753 | ||
8586fc66 | 16754 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16755 | We also need NewABI support. */ |
16756 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16757 | { | |
16758 | s_ignore (0); | |
16759 | return; | |
16760 | } | |
16761 | ||
a276b80c MR |
16762 | if (mips_opts.mips16) |
16763 | { | |
16764 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16765 | ignore_rest_of_line (); | |
16766 | return; | |
16767 | } | |
16768 | ||
6478892d TS |
16769 | reg1 = tc_get_register (0); |
16770 | SKIP_WHITESPACE (); | |
16771 | if (*input_line_pointer != ',') | |
16772 | { | |
16773 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16774 | return; | |
16775 | } | |
16776 | else | |
80245285 | 16777 | ++input_line_pointer; |
6478892d TS |
16778 | SKIP_WHITESPACE (); |
16779 | if (*input_line_pointer == '$') | |
80245285 TS |
16780 | { |
16781 | mips_cpreturn_register = tc_get_register (0); | |
16782 | mips_cpreturn_offset = -1; | |
16783 | } | |
6478892d | 16784 | else |
80245285 TS |
16785 | { |
16786 | mips_cpreturn_offset = get_absolute_expression (); | |
16787 | mips_cpreturn_register = -1; | |
16788 | } | |
6478892d TS |
16789 | SKIP_WHITESPACE (); |
16790 | if (*input_line_pointer != ',') | |
16791 | { | |
16792 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16793 | return; | |
16794 | } | |
16795 | else | |
f9419b05 | 16796 | ++input_line_pointer; |
6478892d | 16797 | SKIP_WHITESPACE (); |
f21f8242 | 16798 | expression (&ex_sym); |
6478892d | 16799 | |
8a75745d MR |
16800 | mips_mark_labels (); |
16801 | mips_assembling_insn = TRUE; | |
16802 | ||
584892a6 | 16803 | macro_start (); |
6478892d TS |
16804 | if (mips_cpreturn_register == -1) |
16805 | { | |
16806 | ex_off.X_op = O_constant; | |
16807 | ex_off.X_add_symbol = NULL; | |
16808 | ex_off.X_op_symbol = NULL; | |
16809 | ex_off.X_add_number = mips_cpreturn_offset; | |
16810 | ||
67c0d1eb | 16811 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16812 | BFD_RELOC_LO16, SP); |
6478892d TS |
16813 | } |
16814 | else | |
40fc1451 | 16815 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16816 | |
aed1a261 | 16817 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16818 | { |
df58fc94 | 16819 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16820 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16821 | BFD_RELOC_HI16_S); | |
16822 | ||
16823 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16824 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16825 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16826 | ||
16827 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16828 | mips_gp_register, reg1); | |
16829 | } | |
16830 | else | |
16831 | { | |
16832 | expressionS ex; | |
16833 | ||
16834 | ex.X_op = O_symbol; | |
4184909a | 16835 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16836 | ex.X_op_symbol = NULL; |
16837 | ex.X_add_number = 0; | |
6e1304d8 | 16838 | |
aa6975fb ILT |
16839 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16840 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16841 | ||
16842 | macro_build_lui (&ex, mips_gp_register); | |
16843 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16844 | mips_gp_register, BFD_RELOC_LO16); | |
16845 | } | |
f21f8242 | 16846 | |
584892a6 | 16847 | macro_end (); |
6478892d | 16848 | |
8a75745d | 16849 | mips_assembling_insn = FALSE; |
6478892d TS |
16850 | demand_empty_rest_of_line (); |
16851 | } | |
16852 | ||
16853 | static void | |
17a2f251 | 16854 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16855 | { |
919731af | 16856 | file_mips_check_options (); |
16857 | ||
6478892d | 16858 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16859 | .cplocal is ignored. */ |
6478892d TS |
16860 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16861 | { | |
16862 | s_ignore (0); | |
16863 | return; | |
16864 | } | |
16865 | ||
a276b80c MR |
16866 | if (mips_opts.mips16) |
16867 | { | |
16868 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16869 | ignore_rest_of_line (); | |
16870 | return; | |
16871 | } | |
16872 | ||
6478892d | 16873 | mips_gp_register = tc_get_register (0); |
85b51719 | 16874 | demand_empty_rest_of_line (); |
6478892d TS |
16875 | } |
16876 | ||
252b5132 RH |
16877 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16878 | offset from $sp. The offset is remembered, and after making a PIC | |
16879 | call $gp is restored from that location. */ | |
16880 | ||
16881 | static void | |
17a2f251 | 16882 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16883 | { |
16884 | expressionS ex; | |
252b5132 | 16885 | |
919731af | 16886 | file_mips_check_options (); |
16887 | ||
6478892d | 16888 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16889 | .cprestore is ignored. */ |
6478892d | 16890 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16891 | { |
16892 | s_ignore (0); | |
16893 | return; | |
16894 | } | |
16895 | ||
a276b80c MR |
16896 | if (mips_opts.mips16) |
16897 | { | |
16898 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16899 | ignore_rest_of_line (); | |
16900 | return; | |
16901 | } | |
16902 | ||
252b5132 | 16903 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16904 | mips_cprestore_valid = 1; |
252b5132 RH |
16905 | |
16906 | ex.X_op = O_constant; | |
16907 | ex.X_add_symbol = NULL; | |
16908 | ex.X_op_symbol = NULL; | |
16909 | ex.X_add_number = mips_cprestore_offset; | |
16910 | ||
8a75745d MR |
16911 | mips_mark_labels (); |
16912 | mips_assembling_insn = TRUE; | |
16913 | ||
584892a6 | 16914 | macro_start (); |
67c0d1eb RS |
16915 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16916 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16917 | macro_end (); |
252b5132 | 16918 | |
8a75745d | 16919 | mips_assembling_insn = FALSE; |
252b5132 RH |
16920 | demand_empty_rest_of_line (); |
16921 | } | |
16922 | ||
6478892d | 16923 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16924 | was given in the preceding .cpsetup, it results in: |
6478892d | 16925 | ld $gp, offset($sp) |
76b3015f | 16926 | |
6478892d | 16927 | If a register $reg2 was given there, it results in: |
40fc1451 | 16928 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16929 | |
6478892d | 16930 | static void |
17a2f251 | 16931 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16932 | { |
16933 | expressionS ex; | |
6478892d | 16934 | |
919731af | 16935 | file_mips_check_options (); |
16936 | ||
6478892d TS |
16937 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16938 | We also need NewABI support. */ | |
16939 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16940 | { | |
16941 | s_ignore (0); | |
16942 | return; | |
16943 | } | |
16944 | ||
a276b80c MR |
16945 | if (mips_opts.mips16) |
16946 | { | |
16947 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16948 | ignore_rest_of_line (); | |
16949 | return; | |
16950 | } | |
16951 | ||
8a75745d MR |
16952 | mips_mark_labels (); |
16953 | mips_assembling_insn = TRUE; | |
16954 | ||
584892a6 | 16955 | macro_start (); |
6478892d TS |
16956 | if (mips_cpreturn_register == -1) |
16957 | { | |
16958 | ex.X_op = O_constant; | |
16959 | ex.X_add_symbol = NULL; | |
16960 | ex.X_op_symbol = NULL; | |
16961 | ex.X_add_number = mips_cpreturn_offset; | |
16962 | ||
67c0d1eb | 16963 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16964 | } |
16965 | else | |
40fc1451 SD |
16966 | move_register (mips_gp_register, mips_cpreturn_register); |
16967 | ||
584892a6 | 16968 | macro_end (); |
6478892d | 16969 | |
8a75745d | 16970 | mips_assembling_insn = FALSE; |
6478892d TS |
16971 | demand_empty_rest_of_line (); |
16972 | } | |
16973 | ||
d0f13682 CLT |
16974 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16975 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16976 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16977 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16978 | |
16979 | static void | |
d0f13682 CLT |
16980 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16981 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16982 | { |
16983 | expressionS ex; | |
16984 | char *p; | |
16985 | ||
16986 | expression (&ex); | |
16987 | ||
16988 | if (ex.X_op != O_symbol) | |
16989 | { | |
1661c76c | 16990 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16991 | ignore_rest_of_line (); |
16992 | } | |
16993 | ||
16994 | p = frag_more (bytes); | |
16995 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16996 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16997 | demand_empty_rest_of_line (); |
de64cffd | 16998 | mips_clear_insn_labels (); |
741d6ea8 JM |
16999 | } |
17000 | ||
17001 | /* Handle .dtprelword. */ | |
17002 | ||
17003 | static void | |
17004 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17005 | { | |
d0f13682 | 17006 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17007 | } |
17008 | ||
17009 | /* Handle .dtpreldword. */ | |
17010 | ||
17011 | static void | |
17012 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17013 | { | |
d0f13682 CLT |
17014 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17015 | } | |
17016 | ||
17017 | /* Handle .tprelword. */ | |
17018 | ||
17019 | static void | |
17020 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17021 | { | |
17022 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17023 | } | |
17024 | ||
17025 | /* Handle .tpreldword. */ | |
17026 | ||
17027 | static void | |
17028 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17029 | { | |
17030 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17031 | } |
17032 | ||
6478892d TS |
17033 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17034 | code. It sets the offset to use in gp_rel relocations. */ | |
17035 | ||
17036 | static void | |
17a2f251 | 17037 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17038 | { |
17039 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17040 | We also need NewABI support. */ | |
17041 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17042 | { | |
17043 | s_ignore (0); | |
17044 | return; | |
17045 | } | |
17046 | ||
def2e0dd | 17047 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17048 | |
17049 | demand_empty_rest_of_line (); | |
17050 | } | |
17051 | ||
252b5132 RH |
17052 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17053 | code. It generates a 32 bit GP relative reloc. */ | |
17054 | ||
17055 | static void | |
17a2f251 | 17056 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17057 | { |
a8dbcb85 TS |
17058 | segment_info_type *si; |
17059 | struct insn_label_list *l; | |
252b5132 RH |
17060 | expressionS ex; |
17061 | char *p; | |
17062 | ||
17063 | /* When not generating PIC code, this is treated as .word. */ | |
17064 | if (mips_pic != SVR4_PIC) | |
17065 | { | |
17066 | s_cons (2); | |
17067 | return; | |
17068 | } | |
17069 | ||
a8dbcb85 TS |
17070 | si = seg_info (now_seg); |
17071 | l = si->label_list; | |
7d10b47d | 17072 | mips_emit_delays (); |
252b5132 | 17073 | if (auto_align) |
462427c4 | 17074 | mips_align (2, 0, l); |
252b5132 RH |
17075 | |
17076 | expression (&ex); | |
a1facbec | 17077 | mips_clear_insn_labels (); |
252b5132 RH |
17078 | |
17079 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17080 | { | |
1661c76c | 17081 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17082 | ignore_rest_of_line (); |
17083 | } | |
17084 | ||
17085 | p = frag_more (4); | |
17a2f251 | 17086 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17087 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17088 | BFD_RELOC_GPREL32); |
252b5132 RH |
17089 | |
17090 | demand_empty_rest_of_line (); | |
17091 | } | |
17092 | ||
10181a0d | 17093 | static void |
17a2f251 | 17094 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17095 | { |
a8dbcb85 TS |
17096 | segment_info_type *si; |
17097 | struct insn_label_list *l; | |
10181a0d AO |
17098 | expressionS ex; |
17099 | char *p; | |
17100 | ||
17101 | /* When not generating PIC code, this is treated as .dword. */ | |
17102 | if (mips_pic != SVR4_PIC) | |
17103 | { | |
17104 | s_cons (3); | |
17105 | return; | |
17106 | } | |
17107 | ||
a8dbcb85 TS |
17108 | si = seg_info (now_seg); |
17109 | l = si->label_list; | |
7d10b47d | 17110 | mips_emit_delays (); |
10181a0d | 17111 | if (auto_align) |
462427c4 | 17112 | mips_align (3, 0, l); |
10181a0d AO |
17113 | |
17114 | expression (&ex); | |
a1facbec | 17115 | mips_clear_insn_labels (); |
10181a0d AO |
17116 | |
17117 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17118 | { | |
1661c76c | 17119 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17120 | ignore_rest_of_line (); |
17121 | } | |
17122 | ||
17123 | p = frag_more (8); | |
17a2f251 | 17124 | md_number_to_chars (p, 0, 8); |
a105a300 | 17125 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17126 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17127 | |
17128 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17129 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17130 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17131 | |
17132 | demand_empty_rest_of_line (); | |
17133 | } | |
17134 | ||
a3f278e2 CM |
17135 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17136 | tables. It generates a R_MIPS_EH reloc. */ | |
17137 | ||
17138 | static void | |
17139 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17140 | { | |
17141 | expressionS ex; | |
17142 | char *p; | |
17143 | ||
17144 | mips_emit_delays (); | |
17145 | ||
17146 | expression (&ex); | |
17147 | mips_clear_insn_labels (); | |
17148 | ||
17149 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17150 | { | |
1661c76c | 17151 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17152 | ignore_rest_of_line (); |
17153 | } | |
17154 | ||
17155 | p = frag_more (4); | |
17156 | md_number_to_chars (p, 0, 4); | |
17157 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17158 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17159 | |
17160 | demand_empty_rest_of_line (); | |
17161 | } | |
17162 | ||
252b5132 RH |
17163 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17164 | tables in SVR4 PIC code. */ | |
17165 | ||
17166 | static void | |
17a2f251 | 17167 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17168 | { |
252b5132 RH |
17169 | int reg; |
17170 | ||
919731af | 17171 | file_mips_check_options (); |
17172 | ||
10181a0d AO |
17173 | /* This is ignored when not generating SVR4 PIC code. */ |
17174 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17175 | { |
17176 | s_ignore (0); | |
17177 | return; | |
17178 | } | |
17179 | ||
8a75745d MR |
17180 | mips_mark_labels (); |
17181 | mips_assembling_insn = TRUE; | |
17182 | ||
252b5132 | 17183 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17184 | macro_start (); |
252b5132 | 17185 | reg = tc_get_register (0); |
67c0d1eb | 17186 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17187 | macro_end (); |
252b5132 | 17188 | |
8a75745d | 17189 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17190 | demand_empty_rest_of_line (); |
252b5132 RH |
17191 | } |
17192 | ||
17193 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17194 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17195 | such as generating jalx instructions when needed. We also make |
17196 | them odd for the duration of the assembly, in order to generate the | |
17197 | right sort of code. We will make them even in the adjust_symtab | |
17198 | routine, while leaving them marked. This is convenient for the | |
17199 | debugger and the disassembler. The linker knows to make them odd | |
17200 | again. */ | |
17201 | ||
17202 | static void | |
17a2f251 | 17203 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17204 | { |
7bb01e2d MR |
17205 | file_mips_check_options (); |
17206 | file_ase_mips16 |= mips_opts.mips16; | |
17207 | file_ase_micromips |= mips_opts.micromips; | |
17208 | ||
df58fc94 | 17209 | mips_mark_labels (); |
252b5132 RH |
17210 | |
17211 | demand_empty_rest_of_line (); | |
17212 | } | |
17213 | ||
ba92f887 MR |
17214 | /* Handle the .nan pseudo-op. */ |
17215 | ||
17216 | static void | |
17217 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17218 | { | |
17219 | static const char str_legacy[] = "legacy"; | |
17220 | static const char str_2008[] = "2008"; | |
17221 | size_t i; | |
17222 | ||
17223 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17224 | ||
17225 | if (i == sizeof (str_2008) - 1 | |
17226 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17227 | mips_nan2008 = 1; |
ba92f887 MR |
17228 | else if (i == sizeof (str_legacy) - 1 |
17229 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17230 | { |
17231 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17232 | mips_nan2008 = 0; | |
17233 | else | |
17234 | as_bad (_("`%s' does not support legacy NaN"), | |
17235 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17236 | } | |
ba92f887 | 17237 | else |
1661c76c | 17238 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17239 | |
17240 | input_line_pointer += i; | |
17241 | demand_empty_rest_of_line (); | |
17242 | } | |
17243 | ||
754e2bb9 RS |
17244 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17245 | implemented in a transparent way, so that removing them would not | |
17246 | have any effect on the generated instructions. However, s_stab | |
17247 | internally changes the section, so in practice we need to decide | |
17248 | now whether the preceding label marks compressed code. We do not | |
17249 | support changing the compression mode of a label after a .stab* | |
17250 | directive, such as in: | |
17251 | ||
17252 | foo: | |
134c0c8b | 17253 | .stabs ... |
754e2bb9 RS |
17254 | .set mips16 |
17255 | ||
17256 | so the current mode wins. */ | |
252b5132 RH |
17257 | |
17258 | static void | |
17a2f251 | 17259 | s_mips_stab (int type) |
252b5132 | 17260 | { |
42c0794e | 17261 | file_mips_check_options (); |
754e2bb9 | 17262 | mips_mark_labels (); |
252b5132 RH |
17263 | s_stab (type); |
17264 | } | |
17265 | ||
54f4ddb3 | 17266 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17267 | |
17268 | static void | |
17a2f251 | 17269 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17270 | { |
17271 | char *name; | |
17272 | int c; | |
17273 | symbolS *symbolP; | |
17274 | expressionS exp; | |
17275 | ||
d02603dc | 17276 | c = get_symbol_name (&name); |
252b5132 RH |
17277 | symbolP = symbol_find_or_make (name); |
17278 | S_SET_WEAK (symbolP); | |
17279 | *input_line_pointer = c; | |
17280 | ||
d02603dc | 17281 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17282 | |
17283 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17284 | { | |
17285 | if (S_IS_DEFINED (symbolP)) | |
17286 | { | |
20203fb9 | 17287 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17288 | S_GET_NAME (symbolP)); |
17289 | ignore_rest_of_line (); | |
17290 | return; | |
17291 | } | |
bdaaa2e1 | 17292 | |
252b5132 RH |
17293 | if (*input_line_pointer == ',') |
17294 | { | |
17295 | ++input_line_pointer; | |
17296 | SKIP_WHITESPACE (); | |
17297 | } | |
bdaaa2e1 | 17298 | |
252b5132 RH |
17299 | expression (&exp); |
17300 | if (exp.X_op != O_symbol) | |
17301 | { | |
20203fb9 | 17302 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17303 | ignore_rest_of_line (); |
252b5132 RH |
17304 | return; |
17305 | } | |
49309057 | 17306 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17307 | } |
17308 | ||
17309 | demand_empty_rest_of_line (); | |
17310 | } | |
17311 | ||
17312 | /* Parse a register string into a number. Called from the ECOFF code | |
17313 | to parse .frame. The argument is non-zero if this is the frame | |
17314 | register, so that we can record it in mips_frame_reg. */ | |
17315 | ||
17316 | int | |
17a2f251 | 17317 | tc_get_register (int frame) |
252b5132 | 17318 | { |
707bfff6 | 17319 | unsigned int reg; |
252b5132 RH |
17320 | |
17321 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17322 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17323 | reg = 0; | |
252b5132 | 17324 | if (frame) |
7a621144 DJ |
17325 | { |
17326 | mips_frame_reg = reg != 0 ? reg : SP; | |
17327 | mips_frame_reg_valid = 1; | |
17328 | mips_cprestore_valid = 0; | |
17329 | } | |
252b5132 RH |
17330 | return reg; |
17331 | } | |
17332 | ||
17333 | valueT | |
17a2f251 | 17334 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17335 | { |
17336 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17337 | ||
f3ded42a RS |
17338 | /* We don't need to align ELF sections to the full alignment. |
17339 | However, Irix 5 may prefer that we align them at least to a 16 | |
17340 | byte boundary. We don't bother to align the sections if we | |
17341 | are targeted for an embedded system. */ | |
17342 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17343 | return addr; | |
17344 | if (align > 4) | |
17345 | align = 4; | |
252b5132 | 17346 | |
8d3842cd | 17347 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17348 | } |
17349 | ||
17350 | /* Utility routine, called from above as well. If called while the | |
17351 | input file is still being read, it's only an approximation. (For | |
17352 | example, a symbol may later become defined which appeared to be | |
17353 | undefined earlier.) */ | |
17354 | ||
17355 | static int | |
17a2f251 | 17356 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17357 | { |
17358 | if (sym == 0) | |
17359 | return 0; | |
17360 | ||
4d0d148d | 17361 | if (g_switch_value > 0) |
252b5132 RH |
17362 | { |
17363 | const char *symname; | |
17364 | int change; | |
17365 | ||
c9914766 | 17366 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17367 | register. It can be if it is smaller than the -G size or if |
17368 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17369 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17370 | they can. */ |
17371 | symname = S_GET_NAME (sym); | |
17372 | if (symname != (const char *) NULL | |
17373 | && (strcmp (symname, "eprol") == 0 | |
17374 | || strcmp (symname, "etext") == 0 | |
17375 | || strcmp (symname, "_gp") == 0 | |
17376 | || strcmp (symname, "edata") == 0 | |
17377 | || strcmp (symname, "_fbss") == 0 | |
17378 | || strcmp (symname, "_fdata") == 0 | |
17379 | || strcmp (symname, "_ftext") == 0 | |
17380 | || strcmp (symname, "end") == 0 | |
17381 | || strcmp (symname, "_gp_disp") == 0)) | |
17382 | change = 1; | |
17383 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17384 | && (0 | |
17385 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17386 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17387 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17388 | <= g_switch_value)) | |
252b5132 RH |
17389 | #endif |
17390 | /* We must defer this decision until after the whole | |
17391 | file has been read, since there might be a .extern | |
17392 | after the first use of this symbol. */ | |
17393 | || (before_relaxing | |
17394 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17395 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17396 | #endif |
17397 | && S_GET_VALUE (sym) == 0) | |
17398 | || (S_GET_VALUE (sym) != 0 | |
17399 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17400 | change = 0; | |
17401 | else | |
17402 | { | |
17403 | const char *segname; | |
17404 | ||
17405 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17406 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17407 | && strcmp (segname, ".lit4") != 0); |
17408 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17409 | && strcmp (segname, ".sbss") != 0 |
17410 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17411 | && strncmp (segname, ".sbss.", 6) != 0 |
17412 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17413 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17414 | } |
17415 | return change; | |
17416 | } | |
17417 | else | |
c9914766 | 17418 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17419 | return 1; |
17420 | } | |
17421 | ||
5919d012 RS |
17422 | |
17423 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17424 | ||
17425 | static bfd_boolean | |
9e009953 | 17426 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17427 | { |
17428 | asection *symsec; | |
5919d012 RS |
17429 | |
17430 | /* Handle the case of a symbol equated to another symbol. */ | |
17431 | while (symbol_equated_reloc_p (sym)) | |
17432 | { | |
17433 | symbolS *n; | |
17434 | ||
5f0fe04b | 17435 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17436 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17437 | if (n == sym) | |
17438 | break; | |
17439 | sym = n; | |
17440 | } | |
17441 | ||
df1f3cda DD |
17442 | if (symbol_section_p (sym)) |
17443 | return TRUE; | |
17444 | ||
5919d012 RS |
17445 | symsec = S_GET_SEGMENT (sym); |
17446 | ||
5919d012 | 17447 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17448 | return (!bfd_is_und_section (symsec) |
17449 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17450 | && !bfd_is_com_section (symsec) |
5919d012 | 17451 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17452 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17453 | } |
14f72d45 MR |
17454 | \f |
17455 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17456 | convert a section-relative value VAL to the equivalent PC-relative | |
17457 | value. */ | |
17458 | ||
17459 | static offsetT | |
17460 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17461 | offsetT val, long stretch) | |
17462 | { | |
17463 | fragS *sym_frag; | |
17464 | addressT addr; | |
17465 | ||
17466 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17467 | ||
17468 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17469 | ||
17470 | /* If the relax_marker of the symbol fragment differs from the | |
17471 | relax_marker of this fragment, we have not yet adjusted the | |
17472 | symbol fragment fr_address. We want to add in STRETCH in | |
17473 | order to get a better estimate of the address. This | |
17474 | particularly matters because of the shift bits. */ | |
17475 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17476 | { | |
17477 | fragS *f; | |
17478 | ||
17479 | /* Adjust stretch for any alignment frag. Note that if have | |
17480 | been expanding the earlier code, the symbol may be | |
17481 | defined in what appears to be an earlier frag. FIXME: | |
17482 | This doesn't handle the fr_subtype field, which specifies | |
17483 | a maximum number of bytes to skip when doing an | |
17484 | alignment. */ | |
17485 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17486 | { | |
17487 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17488 | { | |
17489 | if (stretch < 0) | |
17490 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17491 | else | |
17492 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17493 | if (stretch == 0) | |
17494 | break; | |
17495 | } | |
17496 | } | |
17497 | if (f != NULL) | |
17498 | val += stretch; | |
17499 | } | |
17500 | ||
17501 | addr = fragp->fr_address + fragp->fr_fix; | |
17502 | ||
17503 | /* The base address rules are complicated. The base address of | |
17504 | a branch is the following instruction. The base address of a | |
17505 | PC relative load or add is the instruction itself, but if it | |
17506 | is in a delay slot (in which case it can not be extended) use | |
17507 | the address of the instruction whose delay slot it is in. */ | |
17508 | if (pcrel_op->include_isa_bit) | |
17509 | { | |
17510 | addr += 2; | |
17511 | ||
17512 | /* If we are currently assuming that this frag should be | |
17513 | extended, then the current address is two bytes higher. */ | |
17514 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17515 | addr += 2; | |
17516 | ||
17517 | /* Ignore the low bit in the target, since it will be set | |
17518 | for a text label. */ | |
17519 | val &= -2; | |
17520 | } | |
17521 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17522 | addr -= 4; | |
17523 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17524 | addr -= 2; | |
5919d012 | 17525 | |
14f72d45 MR |
17526 | val -= addr & -(1 << pcrel_op->align_log2); |
17527 | ||
17528 | return val; | |
17529 | } | |
5919d012 | 17530 | |
252b5132 RH |
17531 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17532 | extended opcode. SEC is the section the frag is in. */ | |
17533 | ||
17534 | static int | |
17a2f251 | 17535 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17536 | { |
3ccad066 | 17537 | const struct mips_int_operand *operand; |
252b5132 | 17538 | offsetT val; |
252b5132 | 17539 | segT symsec; |
14f72d45 | 17540 | int type; |
252b5132 RH |
17541 | |
17542 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17543 | return 0; | |
17544 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17545 | return 1; | |
17546 | ||
88a7ef16 | 17547 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17548 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17549 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17550 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17551 | || (operand->root.type == OP_PCREL | |
17552 | ? sec != symsec | |
17553 | : !bfd_is_abs_section (symsec))) | |
17554 | return 1; | |
252b5132 | 17555 | |
88a7ef16 | 17556 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17557 | |
3ccad066 | 17558 | if (operand->root.type == OP_PCREL) |
252b5132 | 17559 | { |
3ccad066 | 17560 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17561 | offsetT maxtiny; |
252b5132 | 17562 | |
1425c41d | 17563 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17564 | return 1; |
252b5132 | 17565 | |
88a7ef16 | 17566 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17567 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17568 | |
17569 | /* If any of the shifted bits are set, we must use an extended | |
17570 | opcode. If the address depends on the size of this | |
17571 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17572 | use an extended opcode. */ |
17573 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17574 | { |
17575 | fragp->fr_subtype = | |
1425c41d | 17576 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17577 | return 1; |
17578 | } | |
17579 | ||
17580 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17581 | is precisely the next value above maxtiny, then there is a |
17582 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17583 | la $4,foo |
17584 | .skip 1020 | |
17585 | .align 2 | |
17586 | foo: | |
17587 | In this case when the la is extended, foo is 0x3fc bytes | |
17588 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17589 | the la must be extended. To avoid this loop, we mark the | |
17590 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17591 | extended with the next value above maxtiny. */ |
17592 | maxtiny = mips_int_operand_max (operand); | |
17593 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17594 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17595 | { |
17596 | fragp->fr_subtype = | |
1425c41d | 17597 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17598 | return 1; |
17599 | } | |
17600 | } | |
252b5132 | 17601 | |
3ccad066 | 17602 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17603 | } |
17604 | ||
8507b6e7 MR |
17605 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17606 | macro expansion. SEC is the section the frag is in. We only | |
17607 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17608 | non-PIC code using 32-bit addressing. */ | |
17609 | ||
17610 | static int | |
17611 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17612 | { | |
17613 | const struct mips_pcrel_operand *pcrel_op; | |
17614 | const struct mips_int_operand *operand; | |
17615 | offsetT val; | |
17616 | segT symsec; | |
17617 | int type; | |
17618 | ||
17619 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17620 | ||
17621 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17622 | return 0; | |
17623 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17624 | return 0; | |
17625 | ||
17626 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17627 | switch (type) | |
17628 | { | |
17629 | case 'A': | |
17630 | case 'B': | |
17631 | case 'E': | |
17632 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17633 | if (bfd_is_abs_section (symsec)) | |
17634 | return 1; | |
17635 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17636 | return 0; | |
17637 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17638 | return 1; | |
17639 | ||
17640 | operand = mips16_immed_operand (type, TRUE); | |
17641 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17642 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17643 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17644 | ||
17645 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17646 | ||
17647 | default: | |
17648 | return 0; | |
17649 | } | |
17650 | } | |
17651 | ||
4a6a3df4 AO |
17652 | /* Compute the length of a branch sequence, and adjust the |
17653 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17654 | worst-case length is computed, with UPDATE being used to indicate | |
17655 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17656 | branch is to be computed. */ | |
17657 | static int | |
17a2f251 | 17658 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17659 | { |
b34976b6 | 17660 | bfd_boolean toofar; |
4a6a3df4 AO |
17661 | int length; |
17662 | ||
17663 | if (fragp | |
17664 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17665 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17666 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17667 | { | |
17668 | addressT addr; | |
17669 | offsetT val; | |
17670 | ||
17671 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17672 | ||
17673 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17674 | ||
17675 | val -= addr; | |
17676 | ||
17677 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17678 | } | |
4a6a3df4 | 17679 | else |
c1f61bd2 MR |
17680 | /* If the symbol is not defined or it's in a different segment, |
17681 | we emit the long sequence. */ | |
b34976b6 | 17682 | toofar = TRUE; |
4a6a3df4 AO |
17683 | |
17684 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17685 | fragp->fr_subtype | |
66b3e8da | 17686 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17687 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17688 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17689 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17690 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17691 | toofar); | |
17692 | ||
17693 | length = 4; | |
17694 | if (toofar) | |
17695 | { | |
17696 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17697 | length += 8; | |
17698 | ||
ce8ad872 | 17699 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17700 | { |
17701 | /* Additional space for PIC loading of target address. */ | |
17702 | length += 8; | |
17703 | if (mips_opts.isa == ISA_MIPS1) | |
17704 | /* Additional space for $at-stabilizing nop. */ | |
17705 | length += 4; | |
17706 | } | |
17707 | ||
17708 | /* If branch is conditional. */ | |
17709 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17710 | length += 8; | |
17711 | } | |
b34976b6 | 17712 | |
4a6a3df4 AO |
17713 | return length; |
17714 | } | |
17715 | ||
7bd374a4 MR |
17716 | /* Get a FRAG's branch instruction delay slot size, either from the |
17717 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17718 | or SHORT_INSN_SIZE otherwise. */ | |
17719 | ||
17720 | static int | |
17721 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17722 | { | |
17723 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17724 | ||
17725 | if (al) | |
17726 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17727 | else | |
17728 | return short_insn_size; | |
17729 | } | |
17730 | ||
df58fc94 RS |
17731 | /* Compute the length of a branch sequence, and adjust the |
17732 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17733 | worst-case length is computed, with UPDATE being used to indicate | |
17734 | whether an unconditional (-1), or regular (0) branch is to be | |
17735 | computed. */ | |
17736 | ||
17737 | static int | |
17738 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17739 | { | |
7bd374a4 MR |
17740 | bfd_boolean insn32 = TRUE; |
17741 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17742 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17743 | bfd_boolean al = TRUE; |
17744 | int short_insn_size; | |
df58fc94 RS |
17745 | bfd_boolean toofar; |
17746 | int length; | |
17747 | ||
7bd374a4 MR |
17748 | if (fragp) |
17749 | { | |
17750 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17751 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17752 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17753 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17754 | } | |
17755 | short_insn_size = insn32 ? 4 : 2; | |
17756 | ||
df58fc94 RS |
17757 | if (fragp |
17758 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17759 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17760 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17761 | { | |
17762 | addressT addr; | |
17763 | offsetT val; | |
17764 | ||
17765 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17766 | /* Ignore the low bit in the target, since it will be set | |
17767 | for a text label. */ | |
17768 | if ((val & 1) != 0) | |
17769 | --val; | |
17770 | ||
17771 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17772 | ||
17773 | val -= addr; | |
17774 | ||
17775 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17776 | } | |
df58fc94 | 17777 | else |
c1f61bd2 MR |
17778 | /* If the symbol is not defined or it's in a different segment, |
17779 | we emit the long sequence. */ | |
df58fc94 RS |
17780 | toofar = TRUE; |
17781 | ||
17782 | if (fragp && update | |
17783 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17784 | fragp->fr_subtype = (toofar | |
17785 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17786 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17787 | ||
17788 | length = 4; | |
17789 | if (toofar) | |
17790 | { | |
17791 | bfd_boolean compact_known = fragp != NULL; | |
17792 | bfd_boolean compact = FALSE; | |
17793 | bfd_boolean uncond; | |
17794 | ||
df58fc94 | 17795 | if (fragp) |
8484fb75 MR |
17796 | { |
17797 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17798 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17799 | } |
df58fc94 RS |
17800 | else |
17801 | uncond = update < 0; | |
17802 | ||
17803 | /* If label is out of range, we turn branch <br>: | |
17804 | ||
17805 | <br> label # 4 bytes | |
17806 | 0: | |
17807 | ||
17808 | into: | |
17809 | ||
17810 | j label # 4 bytes | |
8484fb75 MR |
17811 | nop # 2/4 bytes if |
17812 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17813 | 0: |
17814 | */ | |
ce8ad872 | 17815 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17816 | length += short_insn_size; |
df58fc94 RS |
17817 | |
17818 | /* If assembling PIC code, we further turn: | |
17819 | ||
17820 | j label # 4 bytes | |
17821 | ||
17822 | into: | |
17823 | ||
17824 | lw/ld at, %got(label)(gp) # 4 bytes | |
17825 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17826 | jr/c at # 2/4 bytes |
df58fc94 | 17827 | */ |
ce8ad872 | 17828 | if (pic) |
8484fb75 | 17829 | length += 4 + short_insn_size; |
df58fc94 | 17830 | |
7bd374a4 MR |
17831 | /* Add an extra nop if the jump has no compact form and we need |
17832 | to fill the delay slot. */ | |
ce8ad872 | 17833 | if ((!pic || al) && nods) |
7bd374a4 MR |
17834 | length += (fragp |
17835 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17836 | : short_insn_size); | |
17837 | ||
df58fc94 RS |
17838 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17839 | ||
17840 | <brneg> 0f # 4 bytes | |
8484fb75 | 17841 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17842 | */ |
17843 | if (!uncond) | |
8484fb75 | 17844 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17845 | } |
7bd374a4 MR |
17846 | else if (nods) |
17847 | { | |
17848 | /* Add an extra nop to fill the delay slot. */ | |
17849 | gas_assert (fragp); | |
17850 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17851 | } | |
df58fc94 RS |
17852 | |
17853 | return length; | |
17854 | } | |
17855 | ||
17856 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17857 | bit accordingly. */ | |
17858 | ||
17859 | static int | |
17860 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17861 | { | |
17862 | bfd_boolean toofar; | |
17863 | ||
df58fc94 RS |
17864 | if (fragp |
17865 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17866 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17867 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17868 | { | |
17869 | addressT addr; | |
17870 | offsetT val; | |
17871 | int type; | |
17872 | ||
17873 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17874 | /* Ignore the low bit in the target, since it will be set | |
17875 | for a text label. */ | |
17876 | if ((val & 1) != 0) | |
17877 | --val; | |
17878 | ||
17879 | /* Assume this is a 2-byte branch. */ | |
17880 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17881 | ||
17882 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17883 | long branches. */ | |
17884 | ||
17885 | val -= addr; | |
17886 | ||
17887 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17888 | if (type == 'D') | |
17889 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17890 | else if (type == 'E') | |
17891 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17892 | else | |
17893 | abort (); | |
17894 | } | |
17895 | else | |
17896 | /* If the symbol is not defined or it's in a different segment, | |
17897 | we emit a normal 32-bit branch. */ | |
17898 | toofar = TRUE; | |
17899 | ||
17900 | if (fragp && update | |
17901 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17902 | fragp->fr_subtype | |
17903 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17904 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17905 | ||
17906 | if (toofar) | |
17907 | return 4; | |
17908 | ||
17909 | return 2; | |
17910 | } | |
17911 | ||
252b5132 RH |
17912 | /* Estimate the size of a frag before relaxing. Unless this is the |
17913 | mips16, we are not really relaxing here, and the final size is | |
17914 | encoded in the subtype information. For the mips16, we have to | |
17915 | decide whether we are using an extended opcode or not. */ | |
17916 | ||
252b5132 | 17917 | int |
17a2f251 | 17918 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17919 | { |
5919d012 | 17920 | int change; |
252b5132 | 17921 | |
4a6a3df4 AO |
17922 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17923 | { | |
17924 | ||
b34976b6 AM |
17925 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17926 | ||
4a6a3df4 AO |
17927 | return fragp->fr_var; |
17928 | } | |
17929 | ||
252b5132 | 17930 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17931 | { |
17932 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17933 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17934 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 17935 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
17936 | else |
17937 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17938 | } | |
252b5132 | 17939 | |
df58fc94 RS |
17940 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17941 | { | |
17942 | int length = 4; | |
17943 | ||
17944 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17945 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17946 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17947 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17948 | fragp->fr_var = length; | |
17949 | ||
17950 | return length; | |
17951 | } | |
17952 | ||
ce8ad872 | 17953 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17954 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17955 | change = 0; | |
ce8ad872 MR |
17956 | else if (RELAX_PIC (fragp->fr_subtype)) |
17957 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17958 | else |
ce8ad872 | 17959 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17960 | |
17961 | if (change) | |
17962 | { | |
4d7206a2 | 17963 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17964 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17965 | } |
4d7206a2 RS |
17966 | else |
17967 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17968 | } |
17969 | ||
17970 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17971 | should be converted into a reloc against a section. */ |
252b5132 RH |
17972 | |
17973 | int | |
17a2f251 | 17974 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17975 | { |
252b5132 RH |
17976 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17977 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17978 | return 0; | |
a161fe53 | 17979 | |
252b5132 RH |
17980 | if (fixp->fx_addsy == NULL) |
17981 | return 1; | |
a161fe53 | 17982 | |
2f0c68f2 CM |
17983 | /* Allow relocs used for EH tables. */ |
17984 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17985 | return 1; | |
17986 | ||
de7e6852 RS |
17987 | /* If symbol SYM is in a mergeable section, relocations of the form |
17988 | SYM + 0 can usually be made section-relative. The mergeable data | |
17989 | is then identified by the section offset rather than by the symbol. | |
17990 | ||
17991 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17992 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17993 | need to recalculate the complete offset in order to correctly identify |
17994 | the merge data. | |
17995 | ||
33eaf5de | 17996 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17997 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17998 | placed anywhere. Rather than break backwards compatibility by changing | |
17999 | this, it seems better not to force the issue, and instead keep the | |
18000 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18001 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18002 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18003 | && HAVE_IN_PLACE_ADDENDS |
18004 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18005 | return 0; | |
18006 | ||
97f50151 MR |
18007 | /* There is no place to store an in-place offset for JALR relocations. */ |
18008 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
18009 | return 0; | |
18010 | ||
18011 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 18012 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
18013 | start address of the symbol's containing section. |
18014 | ||
18015 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
18016 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 18017 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 18018 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
18019 | return 0; |
18020 | ||
b314ec0e RS |
18021 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18022 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18023 | relocations against MIPS16 functions; in this case, the stub becomes | |
18024 | the function's canonical address. | |
18025 | ||
18026 | Floating-point stubs are stored in unique .mips16.call.* or | |
18027 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18028 | the first relocation in section S must be against F; this is how the | |
18029 | linker determines the target function. All relocations that might | |
18030 | resolve to T must also be against F. We therefore have the following | |
18031 | restrictions, which are given in an intentionally-redundant way: | |
18032 | ||
18033 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18034 | symbols. | |
18035 | ||
18036 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18037 | if that stub might be used. | |
18038 | ||
18039 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18040 | symbols. | |
18041 | ||
18042 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18043 | that stub might be used. | |
18044 | ||
18045 | There is a further restriction: | |
18046 | ||
df58fc94 | 18047 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 18048 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
18049 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
18050 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
18051 | against MIPS16 or microMIPS symbols because we need to keep the | |
18052 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
18053 | detection and JAL or BAL to JALX instruction conversion in the |
18054 | linker. | |
b314ec0e | 18055 | |
df58fc94 | 18056 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18057 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18058 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18059 | |
18060 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18061 | relocation against some symbol R, no relocation against R may be | |
18062 | reduced. (Note that this deals with (2) as well as (1) because | |
18063 | relocations against global symbols will never be reduced on ELF | |
18064 | targets.) This approach is a little simpler than trying to detect | |
18065 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18066 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18067 | if (fixp->fx_subsy == NULL |
30c09090 | 18068 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18069 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18070 | && (jmp_reloc_p (fixp->fx_r_type) |
18071 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18072 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18073 | return 0; |
a161fe53 | 18074 | |
252b5132 RH |
18075 | return 1; |
18076 | } | |
18077 | ||
18078 | /* Translate internal representation of relocation info to BFD target | |
18079 | format. */ | |
18080 | ||
18081 | arelent ** | |
17a2f251 | 18082 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18083 | { |
18084 | static arelent *retval[4]; | |
18085 | arelent *reloc; | |
18086 | bfd_reloc_code_real_type code; | |
18087 | ||
4b0cff4e | 18088 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18089 | reloc = retval[0] = XCNEW (arelent); |
18090 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18091 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18092 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18093 | ||
bad36eac DJ |
18094 | if (fixp->fx_pcrel) |
18095 | { | |
df58fc94 | 18096 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18097 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18098 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18099 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18100 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18101 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18102 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18103 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18104 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18105 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18106 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18107 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18108 | |
18109 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18110 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18111 | switch (fixp->fx_r_type) |
18112 | { | |
18113 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18114 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18115 | break; | |
18116 | default: | |
18117 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18118 | break; | |
18119 | } | |
bad36eac | 18120 | } |
17c6c9d9 MR |
18121 | else if (HAVE_IN_PLACE_ADDENDS |
18122 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18123 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18124 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18125 | { | |
18126 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18127 | addend accordingly. */ | |
18128 | reloc->addend = fixp->fx_addnumber >> 1; | |
18129 | } | |
bad36eac DJ |
18130 | else |
18131 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18132 | |
438c16b8 TS |
18133 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18134 | entry to be used in the relocation's section offset. */ | |
18135 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18136 | { |
18137 | reloc->address = reloc->addend; | |
18138 | reloc->addend = 0; | |
18139 | } | |
18140 | ||
252b5132 | 18141 | code = fixp->fx_r_type; |
252b5132 | 18142 | |
bad36eac | 18143 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18144 | if (reloc->howto == NULL) |
18145 | { | |
18146 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18147 | _("cannot represent %s relocation in this object file" |
18148 | " format"), | |
252b5132 RH |
18149 | bfd_get_reloc_code_name (code)); |
18150 | retval[0] = NULL; | |
18151 | } | |
18152 | ||
18153 | return retval; | |
18154 | } | |
18155 | ||
18156 | /* Relax a machine dependent frag. This returns the amount by which | |
18157 | the current size of the frag should change. */ | |
18158 | ||
18159 | int | |
17a2f251 | 18160 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18161 | { |
4a6a3df4 AO |
18162 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18163 | { | |
18164 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18165 | |
18166 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18167 | |
18168 | return fragp->fr_var - old_var; | |
18169 | } | |
18170 | ||
df58fc94 RS |
18171 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18172 | { | |
18173 | offsetT old_var = fragp->fr_var; | |
18174 | offsetT new_var = 4; | |
18175 | ||
18176 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18177 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18178 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18179 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18180 | fragp->fr_var = new_var; | |
18181 | ||
18182 | return new_var - old_var; | |
18183 | } | |
18184 | ||
252b5132 RH |
18185 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18186 | return 0; | |
18187 | ||
8507b6e7 | 18188 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18189 | { |
8507b6e7 MR |
18190 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18191 | { | |
18192 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18193 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18194 | } |
18195 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18196 | { | |
18197 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18198 | return -2; | |
18199 | } | |
18200 | else | |
18201 | return 0; | |
18202 | } | |
18203 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18204 | { | |
18205 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18206 | { | |
18207 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18208 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18209 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18210 | } |
18211 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18212 | { | |
18213 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18214 | return 2; | |
18215 | } | |
18216 | else | |
252b5132 | 18217 | return 0; |
252b5132 RH |
18218 | } |
18219 | else | |
18220 | { | |
8507b6e7 | 18221 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18222 | return 0; |
8507b6e7 MR |
18223 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18224 | { | |
18225 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18226 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18227 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18228 | } |
18229 | else | |
18230 | { | |
18231 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18232 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18233 | } |
252b5132 RH |
18234 | } |
18235 | ||
18236 | return 0; | |
18237 | } | |
18238 | ||
18239 | /* Convert a machine dependent frag. */ | |
18240 | ||
18241 | void | |
17a2f251 | 18242 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18243 | { |
4a6a3df4 AO |
18244 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18245 | { | |
4d68580a | 18246 | char *buf; |
4a6a3df4 | 18247 | unsigned long insn; |
4a6a3df4 | 18248 | fixS *fixp; |
b34976b6 | 18249 | |
4d68580a RS |
18250 | buf = fragp->fr_literal + fragp->fr_fix; |
18251 | insn = read_insn (buf); | |
b34976b6 | 18252 | |
4a6a3df4 AO |
18253 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18254 | { | |
18255 | /* We generate a fixup instead of applying it right now | |
18256 | because, if there are linker relaxations, we're going to | |
18257 | need the relocations. */ | |
bbd27b76 MR |
18258 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18259 | fragp->fr_symbol, fragp->fr_offset, | |
18260 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18261 | fixp->fx_file = fragp->fr_file; |
18262 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18263 | |
4d68580a | 18264 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18265 | } |
18266 | else | |
18267 | { | |
18268 | int i; | |
18269 | ||
18270 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18271 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18272 | |
18273 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18274 | goto uncond; | |
18275 | ||
18276 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18277 | { | |
18278 | /* Reverse the branch. */ | |
18279 | switch ((insn >> 28) & 0xf) | |
18280 | { | |
18281 | case 4: | |
56d438b1 CF |
18282 | if ((insn & 0xff000000) == 0x47000000 |
18283 | || (insn & 0xff600000) == 0x45600000) | |
18284 | { | |
18285 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18286 | reversed by tweaking bit 23. */ | |
18287 | insn ^= 0x00800000; | |
18288 | } | |
18289 | else | |
18290 | { | |
18291 | /* bc[0-3][tf]l? instructions can have the condition | |
18292 | reversed by tweaking a single TF bit, and their | |
18293 | opcodes all have 0x4???????. */ | |
18294 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18295 | insn ^= 0x00010000; | |
18296 | } | |
4a6a3df4 AO |
18297 | break; |
18298 | ||
18299 | case 0: | |
18300 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18301 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18302 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18303 | insn ^= 0x00010000; |
18304 | break; | |
b34976b6 | 18305 | |
4a6a3df4 AO |
18306 | case 1: |
18307 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18308 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18309 | insn ^= 0x04000000; |
18310 | break; | |
18311 | ||
18312 | default: | |
18313 | abort (); | |
18314 | } | |
18315 | } | |
18316 | ||
18317 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18318 | { | |
18319 | /* Clear the and-link bit. */ | |
9c2799c2 | 18320 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18321 | |
54f4ddb3 TS |
18322 | /* bltzal 0x04100000 bgezal 0x04110000 |
18323 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18324 | insn &= ~0x00100000; |
18325 | } | |
18326 | ||
18327 | /* Branch over the branch (if the branch was likely) or the | |
18328 | full jump (not likely case). Compute the offset from the | |
18329 | current instruction to branch to. */ | |
18330 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18331 | i = 16; | |
18332 | else | |
18333 | { | |
18334 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18335 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18336 | /* How many bytes in instructions from here to the end? */ |
18337 | i = fragp->fr_var - i; | |
18338 | } | |
18339 | /* Convert to instruction count. */ | |
18340 | i >>= 2; | |
18341 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18342 | i--; |
4a6a3df4 AO |
18343 | insn |= i; |
18344 | /* Branch over the jump. */ | |
4d68580a | 18345 | buf = write_insn (buf, insn); |
4a6a3df4 | 18346 | |
54f4ddb3 | 18347 | /* nop */ |
4d68580a | 18348 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18349 | |
18350 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18351 | { | |
18352 | /* beql $0, $0, 2f */ | |
18353 | insn = 0x50000000; | |
18354 | /* Compute the PC offset from the current instruction to | |
18355 | the end of the variable frag. */ | |
18356 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18357 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18358 | /* How many bytes in instructions from here to the end? */ |
18359 | i = fragp->fr_var - i; | |
18360 | /* Convert to instruction count. */ | |
18361 | i >>= 2; | |
18362 | /* Don't decrement i, because we want to branch over the | |
18363 | delay slot. */ | |
4a6a3df4 | 18364 | insn |= i; |
4a6a3df4 | 18365 | |
4d68580a RS |
18366 | buf = write_insn (buf, insn); |
18367 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18368 | } |
18369 | ||
18370 | uncond: | |
ce8ad872 | 18371 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18372 | { |
18373 | /* j or jal. */ | |
18374 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18375 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18376 | |
bbd27b76 MR |
18377 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18378 | fragp->fr_symbol, fragp->fr_offset, | |
18379 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18380 | fixp->fx_file = fragp->fr_file; |
18381 | fixp->fx_line = fragp->fr_line; | |
18382 | ||
4d68580a | 18383 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18384 | } |
18385 | else | |
18386 | { | |
66b3e8da MR |
18387 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18388 | ||
4a6a3df4 | 18389 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18390 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18391 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18392 | |
bbd27b76 MR |
18393 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18394 | fragp->fr_symbol, fragp->fr_offset, | |
18395 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18396 | fixp->fx_file = fragp->fr_file; |
18397 | fixp->fx_line = fragp->fr_line; | |
18398 | ||
4d68580a | 18399 | buf = write_insn (buf, insn); |
b34976b6 | 18400 | |
4a6a3df4 | 18401 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18402 | /* nop */ |
18403 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18404 | |
18405 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18406 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18407 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18408 | |
bbd27b76 MR |
18409 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18410 | fragp->fr_symbol, fragp->fr_offset, | |
18411 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18412 | fixp->fx_file = fragp->fr_file; |
18413 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18414 | |
4d68580a | 18415 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18416 | |
18417 | /* j(al)r $at. */ | |
18418 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18419 | insn = 0x0000f809; |
4a6a3df4 | 18420 | else |
66b3e8da MR |
18421 | insn = 0x00000008; |
18422 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18423 | |
4d68580a | 18424 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18425 | } |
18426 | } | |
18427 | ||
4a6a3df4 | 18428 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18429 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18430 | return; |
18431 | } | |
18432 | ||
df58fc94 RS |
18433 | /* Relax microMIPS branches. */ |
18434 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18435 | { | |
4d68580a | 18436 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18437 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18438 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18439 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18440 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18441 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18442 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18443 | bfd_boolean short_ds; |
df58fc94 | 18444 | unsigned long insn; |
df58fc94 RS |
18445 | fixS *fixp; |
18446 | ||
df58fc94 RS |
18447 | fragp->fr_fix += fragp->fr_var; |
18448 | ||
18449 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18450 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18451 | { | |
18452 | /* We generate a fixup instead of applying it right now, | |
18453 | because if there is linker relaxation, we're going to | |
18454 | need the relocations. */ | |
834a65aa MR |
18455 | switch (type) |
18456 | { | |
18457 | case 'D': | |
18458 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18459 | fragp->fr_symbol, fragp->fr_offset, | |
18460 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18461 | break; | |
18462 | case 'E': | |
18463 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18464 | fragp->fr_symbol, fragp->fr_offset, | |
18465 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18466 | break; | |
18467 | default: | |
18468 | abort (); | |
18469 | } | |
df58fc94 RS |
18470 | |
18471 | fixp->fx_file = fragp->fr_file; | |
18472 | fixp->fx_line = fragp->fr_line; | |
18473 | ||
18474 | /* These relocations can have an addend that won't fit in | |
18475 | 2 octets. */ | |
18476 | fixp->fx_no_overflow = 1; | |
18477 | ||
18478 | return; | |
18479 | } | |
18480 | ||
2309ddf2 | 18481 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18482 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18483 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18484 | { | |
18485 | /* We generate a fixup instead of applying it right now, | |
18486 | because if there is linker relaxation, we're going to | |
18487 | need the relocations. */ | |
bbd27b76 MR |
18488 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18489 | fragp->fr_symbol, fragp->fr_offset, | |
18490 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18491 | fixp->fx_file = fragp->fr_file; |
18492 | fixp->fx_line = fragp->fr_line; | |
18493 | ||
18494 | if (type == 0) | |
7bd374a4 MR |
18495 | { |
18496 | insn = read_compressed_insn (buf, 4); | |
18497 | buf += 4; | |
18498 | ||
18499 | if (nods) | |
18500 | { | |
18501 | /* Check the short-delay-slot bit. */ | |
18502 | if (!al || (insn & 0x02000000) != 0) | |
18503 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18504 | else | |
18505 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18506 | } | |
18507 | ||
18508 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18509 | return; | |
18510 | } | |
df58fc94 RS |
18511 | } |
18512 | ||
18513 | /* Relax 16-bit branches to 32-bit branches. */ | |
18514 | if (type != 0) | |
18515 | { | |
4d68580a | 18516 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18517 | |
18518 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18519 | insn = 0x94000000; /* beq */ | |
18520 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18521 | { | |
18522 | unsigned long regno; | |
18523 | ||
18524 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18525 | regno = micromips_to_32_reg_d_map [regno]; | |
18526 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18527 | insn |= regno << MICROMIPSOP_SH_RS; | |
18528 | } | |
18529 | else | |
18530 | abort (); | |
18531 | ||
18532 | /* Nothing else to do, just write it out. */ | |
18533 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18534 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18535 | { | |
4d68580a | 18536 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18537 | if (nods) |
18538 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18539 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18540 | return; |
18541 | } | |
18542 | } | |
18543 | else | |
4d68580a | 18544 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18545 | |
18546 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18547 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18548 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18549 | |
2309ddf2 | 18550 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18551 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18552 | |
18553 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18554 | { | |
18555 | symbolS *l; | |
18556 | ||
18557 | /* Reverse the branch. */ | |
18558 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18559 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18560 | insn ^= 0x20000000; | |
18561 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18562 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18563 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18564 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18565 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18566 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18567 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18568 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18569 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18570 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18571 | insn ^= 0x00400000; | |
18572 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18573 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18574 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18575 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18576 | insn ^= 0x00200000; | |
56d438b1 CF |
18577 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18578 | BNZ.df */ | |
18579 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18580 | BNZ.V */ | |
18581 | insn ^= 0x00800000; | |
df58fc94 RS |
18582 | else |
18583 | abort (); | |
18584 | ||
18585 | if (al) | |
18586 | { | |
18587 | /* Clear the and-link and short-delay-slot bits. */ | |
18588 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18589 | ||
18590 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18591 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18592 | insn &= ~0x02200000; | |
18593 | } | |
18594 | ||
18595 | /* Make a label at the end for use with the branch. */ | |
18596 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18597 | micromips_label_inc (); | |
f3ded42a | 18598 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18599 | |
18600 | /* Refer to it. */ | |
4d68580a RS |
18601 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18602 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18603 | fixp->fx_file = fragp->fr_file; |
18604 | fixp->fx_line = fragp->fr_line; | |
18605 | ||
18606 | /* Branch over the jump. */ | |
4d68580a | 18607 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18608 | |
df58fc94 | 18609 | if (!compact) |
8484fb75 MR |
18610 | { |
18611 | /* nop */ | |
18612 | if (insn32) | |
18613 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18614 | else | |
18615 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18616 | } | |
df58fc94 RS |
18617 | } |
18618 | ||
ce8ad872 | 18619 | if (!pic) |
df58fc94 | 18620 | { |
7bd374a4 MR |
18621 | unsigned long jal = (short_ds || nods |
18622 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18623 | |
df58fc94 RS |
18624 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18625 | insn = al ? jal : 0xd4000000; | |
18626 | ||
bbd27b76 MR |
18627 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18628 | fragp->fr_symbol, fragp->fr_offset, | |
18629 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18630 | fixp->fx_file = fragp->fr_file; |
18631 | fixp->fx_line = fragp->fr_line; | |
18632 | ||
4d68580a | 18633 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18634 | |
7bd374a4 | 18635 | if (compact || nods) |
8484fb75 MR |
18636 | { |
18637 | /* nop */ | |
18638 | if (insn32) | |
18639 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18640 | else | |
18641 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18642 | } | |
df58fc94 RS |
18643 | } |
18644 | else | |
18645 | { | |
18646 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18647 | ||
18648 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18649 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18650 | insn |= at << MICROMIPSOP_SH_RT; | |
18651 | ||
bbd27b76 MR |
18652 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18653 | fragp->fr_symbol, fragp->fr_offset, | |
18654 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18655 | fixp->fx_file = fragp->fr_file; |
18656 | fixp->fx_line = fragp->fr_line; | |
18657 | ||
4d68580a | 18658 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18659 | |
18660 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18661 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18662 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18663 | ||
bbd27b76 MR |
18664 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18665 | fragp->fr_symbol, fragp->fr_offset, | |
18666 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18667 | fixp->fx_file = fragp->fr_file; |
18668 | fixp->fx_line = fragp->fr_line; | |
18669 | ||
4d68580a | 18670 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18671 | |
8484fb75 MR |
18672 | if (insn32) |
18673 | { | |
18674 | /* jr/jalr $at */ | |
18675 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18676 | insn |= at << MICROMIPSOP_SH_RS; | |
18677 | ||
18678 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18679 | |
7bd374a4 | 18680 | if (compact || nods) |
8484fb75 MR |
18681 | /* nop */ |
18682 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18683 | } | |
18684 | else | |
18685 | { | |
18686 | /* jr/jrc/jalr/jalrs $at */ | |
18687 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18688 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18689 | |
18690 | insn = al ? jalr : jr; | |
18691 | insn |= at << MICROMIPSOP_SH_MJ; | |
18692 | ||
18693 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18694 | if (al && nods) |
18695 | { | |
18696 | /* nop */ | |
18697 | if (short_ds) | |
18698 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18699 | else | |
18700 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18701 | } | |
8484fb75 | 18702 | } |
df58fc94 RS |
18703 | } |
18704 | ||
4d68580a | 18705 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18706 | return; |
18707 | } | |
18708 | ||
252b5132 RH |
18709 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18710 | { | |
18711 | int type; | |
3ccad066 | 18712 | const struct mips_int_operand *operand; |
252b5132 | 18713 | offsetT val; |
5c04167a | 18714 | char *buf; |
8507b6e7 | 18715 | unsigned int user_length; |
9d862524 | 18716 | bfd_boolean need_reloc; |
252b5132 | 18717 | unsigned long insn; |
8507b6e7 | 18718 | bfd_boolean mac; |
5c04167a | 18719 | bfd_boolean ext; |
88a7ef16 | 18720 | segT symsec; |
252b5132 RH |
18721 | |
18722 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18723 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18724 | |
8507b6e7 | 18725 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18726 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18727 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18728 | |
18729 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18730 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18731 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18732 | ? asec != symsec |
18733 | : !bfd_is_abs_section (symsec))); | |
18734 | ||
8507b6e7 | 18735 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18736 | { |
3ccad066 | 18737 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18738 | |
3ccad066 | 18739 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18740 | |
14f72d45 | 18741 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18742 | { |
37b2d327 MR |
18743 | if (!mips_ignore_branch_isa |
18744 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
18745 | as_bad_where (fragp->fr_file, fragp->fr_line, |
18746 | _("branch to a symbol in another ISA mode")); | |
18747 | else if ((fragp->fr_offset & 0x1) != 0) | |
18748 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18749 | _("branch to misaligned address (0x%lx)"), | |
18750 | (long) val); | |
252b5132 | 18751 | } |
252b5132 | 18752 | |
14f72d45 | 18753 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18754 | |
18755 | /* Make sure the section winds up with the alignment we have | |
18756 | assumed. */ | |
3ccad066 RS |
18757 | if (operand->shift > 0) |
18758 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18759 | } |
18760 | ||
8507b6e7 MR |
18761 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18762 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18763 | { | |
18764 | if (mac) | |
18765 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18766 | _("macro instruction expanded into multiple " | |
18767 | "instructions in a branch delay slot")); | |
18768 | else if (ext) | |
18769 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18770 | _("extended instruction in a branch delay slot")); | |
18771 | } | |
18772 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18773 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18774 | _("macro instruction expanded into multiple " |
18775 | "instructions")); | |
252b5132 | 18776 | |
5c04167a | 18777 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18778 | |
4d68580a | 18779 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18780 | if (ext) |
18781 | insn |= MIPS16_EXTEND; | |
252b5132 | 18782 | |
5c04167a RS |
18783 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18784 | user_length = 4; | |
18785 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18786 | user_length = 2; | |
18787 | else | |
18788 | user_length = 0; | |
18789 | ||
8507b6e7 | 18790 | if (mac) |
c9775dde | 18791 | { |
8507b6e7 MR |
18792 | unsigned long reg; |
18793 | unsigned long new; | |
18794 | unsigned long op; | |
25499ac7 | 18795 | bfd_boolean e2; |
8507b6e7 MR |
18796 | |
18797 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18798 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18799 | |
25499ac7 MR |
18800 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
18801 | ||
8507b6e7 | 18802 | if (need_reloc) |
c9775dde | 18803 | { |
8507b6e7 MR |
18804 | fixS *fixp; |
18805 | ||
18806 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18807 | ||
18808 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18809 | fragp->fr_symbol, fragp->fr_offset, | |
18810 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18811 | fixp->fx_file = fragp->fr_file; | |
18812 | fixp->fx_line = fragp->fr_line; | |
18813 | ||
25499ac7 | 18814 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
18815 | fragp->fr_symbol, fragp->fr_offset, |
18816 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18817 | fixp->fx_file = fragp->fr_file; | |
18818 | fixp->fx_line = fragp->fr_line; | |
18819 | ||
18820 | val = 0; | |
18821 | } | |
18822 | ||
18823 | switch (insn & 0xf800) | |
18824 | { | |
18825 | case 0x0800: /* ADDIU */ | |
18826 | reg = (insn >> 8) & 0x7; | |
18827 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18828 | break; |
8507b6e7 MR |
18829 | case 0xb000: /* LW */ |
18830 | reg = (insn >> 8) & 0x7; | |
18831 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18832 | break; |
8507b6e7 MR |
18833 | case 0xf800: /* I64 */ |
18834 | reg = (insn >> 5) & 0x7; | |
18835 | switch (insn & 0x0700) | |
18836 | { | |
18837 | case 0x0400: /* LD */ | |
18838 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18839 | break; | |
18840 | case 0x0600: /* DADDIU */ | |
18841 | op = 0xf000fd00 | (reg << 5); | |
18842 | break; | |
18843 | default: | |
18844 | abort (); | |
18845 | } | |
18846 | break; | |
18847 | default: | |
18848 | abort (); | |
c9775dde | 18849 | } |
8507b6e7 | 18850 | |
25499ac7 | 18851 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
18852 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
18853 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
18854 | if (!e2) |
18855 | { | |
18856 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18857 | buf = write_compressed_insn (buf, new, 4); | |
18858 | } | |
8507b6e7 MR |
18859 | op |= mips16_immed_extend (val, 16); |
18860 | buf = write_compressed_insn (buf, op, 4); | |
18861 | ||
25499ac7 | 18862 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
18863 | } |
18864 | else | |
18865 | { | |
18866 | unsigned int length = ext ? 4 : 2; | |
18867 | ||
18868 | if (need_reloc) | |
c9775dde | 18869 | { |
8507b6e7 | 18870 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 18871 | fixS *fixp; |
c9775dde | 18872 | |
8507b6e7 MR |
18873 | switch (type) |
18874 | { | |
18875 | case 'p': | |
18876 | case 'q': | |
18877 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18878 | break; | |
18879 | default: | |
18880 | break; | |
18881 | } | |
18882 | if (mac || reloc == BFD_RELOC_NONE) | |
18883 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18884 | _("unsupported relocation")); | |
18885 | else if (ext) | |
18886 | { | |
bbd27b76 MR |
18887 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18888 | fragp->fr_symbol, fragp->fr_offset, | |
18889 | TRUE, reloc); | |
8507b6e7 MR |
18890 | fixp->fx_file = fragp->fr_file; |
18891 | fixp->fx_line = fragp->fr_line; | |
18892 | } | |
18893 | else | |
18894 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18895 | _("invalid unextended operand value")); | |
c9775dde | 18896 | } |
eefc3365 | 18897 | else |
8507b6e7 MR |
18898 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18899 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18900 | |
8507b6e7 MR |
18901 | gas_assert (mips16_opcode_length (insn) == length); |
18902 | write_compressed_insn (buf, insn, length); | |
18903 | fragp->fr_fix += length; | |
18904 | } | |
252b5132 RH |
18905 | } |
18906 | else | |
18907 | { | |
df58fc94 RS |
18908 | relax_substateT subtype = fragp->fr_subtype; |
18909 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18910 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18911 | int first, second; |
18912 | fixS *fixp; | |
252b5132 | 18913 | |
df58fc94 RS |
18914 | first = RELAX_FIRST (subtype); |
18915 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18916 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18917 | |
df58fc94 RS |
18918 | /* If the delay slot chosen does not match the size of the instruction, |
18919 | then emit a warning. */ | |
18920 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18921 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18922 | { | |
18923 | relax_substateT s; | |
18924 | const char *msg; | |
18925 | ||
18926 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18927 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18928 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18929 | msg = macro_warning (s); | |
18930 | if (msg != NULL) | |
db9b2be4 | 18931 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18932 | subtype &= ~s; |
18933 | } | |
18934 | ||
584892a6 | 18935 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18936 | if (use_second == second_longer) |
584892a6 | 18937 | { |
df58fc94 RS |
18938 | relax_substateT s; |
18939 | const char *msg; | |
18940 | ||
18941 | s = (subtype | |
18942 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18943 | msg = macro_warning (s); | |
18944 | if (msg != NULL) | |
db9b2be4 | 18945 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18946 | subtype &= ~s; |
584892a6 RS |
18947 | } |
18948 | ||
4d7206a2 RS |
18949 | /* Go through all the fixups for the first sequence. Disable them |
18950 | (by marking them as done) if we're going to use the second | |
18951 | sequence instead. */ | |
18952 | while (fixp | |
18953 | && fixp->fx_frag == fragp | |
18954 | && fixp->fx_where < fragp->fr_fix - second) | |
18955 | { | |
df58fc94 | 18956 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18957 | fixp->fx_done = 1; |
18958 | fixp = fixp->fx_next; | |
18959 | } | |
252b5132 | 18960 | |
4d7206a2 RS |
18961 | /* Go through the fixups for the second sequence. Disable them if |
18962 | we're going to use the first sequence, otherwise adjust their | |
18963 | addresses to account for the relaxation. */ | |
18964 | while (fixp && fixp->fx_frag == fragp) | |
18965 | { | |
df58fc94 | 18966 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18967 | fixp->fx_where -= first; |
18968 | else | |
18969 | fixp->fx_done = 1; | |
18970 | fixp = fixp->fx_next; | |
18971 | } | |
18972 | ||
18973 | /* Now modify the frag contents. */ | |
df58fc94 | 18974 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18975 | { |
18976 | char *start; | |
18977 | ||
18978 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18979 | memmove (start, start + first, second); | |
18980 | fragp->fr_fix -= first; | |
18981 | } | |
18982 | else | |
18983 | fragp->fr_fix -= second; | |
252b5132 RH |
18984 | } |
18985 | } | |
18986 | ||
252b5132 RH |
18987 | /* This function is called after the relocs have been generated. |
18988 | We've been storing mips16 text labels as odd. Here we convert them | |
18989 | back to even for the convenience of the debugger. */ | |
18990 | ||
18991 | void | |
17a2f251 | 18992 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18993 | { |
18994 | asymbol **syms; | |
18995 | unsigned int count, i; | |
18996 | ||
252b5132 RH |
18997 | syms = bfd_get_outsymbols (stdoutput); |
18998 | count = bfd_get_symcount (stdoutput); | |
18999 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
19000 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
19001 | && ((*syms)->value & 1) != 0) | |
19002 | { | |
19003 | (*syms)->value &= ~1; | |
19004 | /* If the symbol has an odd size, it was probably computed | |
19005 | incorrectly, so adjust that as well. */ | |
19006 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
19007 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
19008 | } | |
252b5132 RH |
19009 | } |
19010 | ||
a1facbec MR |
19011 | /* This function is called whenever a label is defined, including fake |
19012 | labels instantiated off the dot special symbol. It is used when | |
19013 | handling branch delays; if a branch has a label, we assume we cannot | |
19014 | move it. This also bumps the value of the symbol by 1 in compressed | |
19015 | code. */ | |
252b5132 | 19016 | |
e1b47bd5 | 19017 | static void |
a1facbec | 19018 | mips_record_label (symbolS *sym) |
252b5132 | 19019 | { |
a8dbcb85 | 19020 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
19021 | struct insn_label_list *l; |
19022 | ||
19023 | if (free_insn_labels == NULL) | |
325801bd | 19024 | l = XNEW (struct insn_label_list); |
252b5132 RH |
19025 | else |
19026 | { | |
19027 | l = free_insn_labels; | |
19028 | free_insn_labels = l->next; | |
19029 | } | |
19030 | ||
19031 | l->label = sym; | |
a8dbcb85 TS |
19032 | l->next = si->label_list; |
19033 | si->label_list = l; | |
a1facbec | 19034 | } |
07a53e5c | 19035 | |
a1facbec MR |
19036 | /* This function is called as tc_frob_label() whenever a label is defined |
19037 | and adds a DWARF-2 record we only want for true labels. */ | |
19038 | ||
19039 | void | |
19040 | mips_define_label (symbolS *sym) | |
19041 | { | |
19042 | mips_record_label (sym); | |
07a53e5c | 19043 | dwarf2_emit_label (sym); |
252b5132 | 19044 | } |
e1b47bd5 RS |
19045 | |
19046 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
19047 | is defined. */ | |
19048 | ||
19049 | void | |
19050 | mips_add_dot_label (symbolS *sym) | |
19051 | { | |
19052 | mips_record_label (sym); | |
19053 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
19054 | mips_compressed_mark_label (sym); | |
19055 | } | |
252b5132 | 19056 | \f |
351cdf24 MF |
19057 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19058 | static unsigned int | |
19059 | mips_convert_ase_flags (int ase) | |
19060 | { | |
19061 | unsigned int ext_ases = 0; | |
19062 | ||
19063 | if (ase & ASE_DSP) | |
19064 | ext_ases |= AFL_ASE_DSP; | |
19065 | if (ase & ASE_DSPR2) | |
19066 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19067 | if (ase & ASE_DSPR3) |
19068 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19069 | if (ase & ASE_EVA) |
19070 | ext_ases |= AFL_ASE_EVA; | |
19071 | if (ase & ASE_MCU) | |
19072 | ext_ases |= AFL_ASE_MCU; | |
19073 | if (ase & ASE_MDMX) | |
19074 | ext_ases |= AFL_ASE_MDMX; | |
19075 | if (ase & ASE_MIPS3D) | |
19076 | ext_ases |= AFL_ASE_MIPS3D; | |
19077 | if (ase & ASE_MT) | |
19078 | ext_ases |= AFL_ASE_MT; | |
19079 | if (ase & ASE_SMARTMIPS) | |
19080 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19081 | if (ase & ASE_VIRT) | |
19082 | ext_ases |= AFL_ASE_VIRT; | |
19083 | if (ase & ASE_MSA) | |
19084 | ext_ases |= AFL_ASE_MSA; | |
19085 | if (ase & ASE_XPA) | |
19086 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19087 | if (ase & ASE_MIPS16E2) |
19088 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19089 | if (ase & ASE_CRC) |
19090 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19091 | if (ase & ASE_GINV) |
19092 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19093 | if (ase & ASE_LOONGSON_MMI) |
19094 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19095 | if (ase & ASE_LOONGSON_CAM) |
19096 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
bdc6c06e CX |
19097 | if (ase & ASE_LOONGSON_EXT) |
19098 | ext_ases |= AFL_ASE_LOONGSON_EXT; | |
a693765e CX |
19099 | if (ase & ASE_LOONGSON_EXT2) |
19100 | ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
351cdf24 MF |
19101 | |
19102 | return ext_ases; | |
19103 | } | |
252b5132 RH |
19104 | /* Some special processing for a MIPS ELF file. */ |
19105 | ||
19106 | void | |
17a2f251 | 19107 | mips_elf_final_processing (void) |
252b5132 | 19108 | { |
351cdf24 MF |
19109 | int fpabi; |
19110 | Elf_Internal_ABIFlags_v0 flags; | |
19111 | ||
19112 | flags.version = 0; | |
19113 | flags.isa_rev = 0; | |
19114 | switch (file_mips_opts.isa) | |
19115 | { | |
19116 | case INSN_ISA1: | |
19117 | flags.isa_level = 1; | |
19118 | break; | |
19119 | case INSN_ISA2: | |
19120 | flags.isa_level = 2; | |
19121 | break; | |
19122 | case INSN_ISA3: | |
19123 | flags.isa_level = 3; | |
19124 | break; | |
19125 | case INSN_ISA4: | |
19126 | flags.isa_level = 4; | |
19127 | break; | |
19128 | case INSN_ISA5: | |
19129 | flags.isa_level = 5; | |
19130 | break; | |
19131 | case INSN_ISA32: | |
19132 | flags.isa_level = 32; | |
19133 | flags.isa_rev = 1; | |
19134 | break; | |
19135 | case INSN_ISA32R2: | |
19136 | flags.isa_level = 32; | |
19137 | flags.isa_rev = 2; | |
19138 | break; | |
19139 | case INSN_ISA32R3: | |
19140 | flags.isa_level = 32; | |
19141 | flags.isa_rev = 3; | |
19142 | break; | |
19143 | case INSN_ISA32R5: | |
19144 | flags.isa_level = 32; | |
19145 | flags.isa_rev = 5; | |
19146 | break; | |
09c14161 MF |
19147 | case INSN_ISA32R6: |
19148 | flags.isa_level = 32; | |
19149 | flags.isa_rev = 6; | |
19150 | break; | |
351cdf24 MF |
19151 | case INSN_ISA64: |
19152 | flags.isa_level = 64; | |
19153 | flags.isa_rev = 1; | |
19154 | break; | |
19155 | case INSN_ISA64R2: | |
19156 | flags.isa_level = 64; | |
19157 | flags.isa_rev = 2; | |
19158 | break; | |
19159 | case INSN_ISA64R3: | |
19160 | flags.isa_level = 64; | |
19161 | flags.isa_rev = 3; | |
19162 | break; | |
19163 | case INSN_ISA64R5: | |
19164 | flags.isa_level = 64; | |
19165 | flags.isa_rev = 5; | |
19166 | break; | |
09c14161 MF |
19167 | case INSN_ISA64R6: |
19168 | flags.isa_level = 64; | |
19169 | flags.isa_rev = 6; | |
19170 | break; | |
351cdf24 MF |
19171 | } |
19172 | ||
19173 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19174 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19175 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19176 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19177 | : AFL_REG_32; | |
19178 | flags.cpr2_size = AFL_REG_NONE; | |
19179 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19180 | Tag_GNU_MIPS_ABI_FP); | |
19181 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19182 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19183 | if (file_ase_mips16) | |
19184 | flags.ases |= AFL_ASE_MIPS16; | |
19185 | if (file_ase_micromips) | |
19186 | flags.ases |= AFL_ASE_MICROMIPS; | |
19187 | flags.flags1 = 0; | |
19188 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19189 | || file_mips_opts.fp == 64) | |
19190 | && file_mips_opts.oddspreg) | |
19191 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19192 | flags.flags2 = 0; | |
19193 | ||
19194 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19195 | ((Elf_External_ABIFlags_v0 *) | |
19196 | mips_flags_frag)); | |
19197 | ||
252b5132 | 19198 | /* Write out the register information. */ |
316f5878 | 19199 | if (mips_abi != N64_ABI) |
252b5132 RH |
19200 | { |
19201 | Elf32_RegInfo s; | |
19202 | ||
19203 | s.ri_gprmask = mips_gprmask; | |
19204 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19205 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19206 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19207 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19208 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19209 | ||
19210 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19211 | ((Elf32_External_RegInfo *) | |
19212 | mips_regmask_frag)); | |
19213 | } | |
19214 | else | |
19215 | { | |
19216 | Elf64_Internal_RegInfo s; | |
19217 | ||
19218 | s.ri_gprmask = mips_gprmask; | |
19219 | s.ri_pad = 0; | |
19220 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19221 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19222 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19223 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19224 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19225 | ||
19226 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19227 | ((Elf64_External_RegInfo *) | |
19228 | mips_regmask_frag)); | |
19229 | } | |
19230 | ||
19231 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19232 | sort of BFD interface for this. */ | |
19233 | if (mips_any_noreorder) | |
19234 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19235 | if (mips_pic != NO_PIC) | |
143d77c5 | 19236 | { |
8b828383 | 19237 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19238 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19239 | } | |
19240 | if (mips_abicalls) | |
19241 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19242 | |
b015e599 AP |
19243 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19244 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19245 | if (file_ase_mips16) |
19246 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19247 | if (file_ase_micromips) |
19248 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19249 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19250 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19251 | |
bdaaa2e1 | 19252 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19253 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19254 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19255 | else if (mips_abi == O64_ABI) |
252b5132 | 19256 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19257 | else if (mips_abi == EABI_ABI) |
252b5132 | 19258 | { |
bad1aba3 | 19259 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19260 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19261 | else | |
19262 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19263 | } | |
be00bddd | 19264 | |
defc8e2b | 19265 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19266 | |
19267 | if (mips_32bitmode) | |
19268 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19269 | |
7361da2c | 19270 | if (mips_nan2008 == 1) |
ba92f887 MR |
19271 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19272 | ||
ad3fea08 | 19273 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19274 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19275 | Tag_GNU_MIPS_ABI_FP); | |
19276 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19277 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19278 | } |
252b5132 | 19279 | \f |
beae10d5 | 19280 | typedef struct proc { |
9b2f1d35 EC |
19281 | symbolS *func_sym; |
19282 | symbolS *func_end_sym; | |
beae10d5 KH |
19283 | unsigned long reg_mask; |
19284 | unsigned long reg_offset; | |
19285 | unsigned long fpreg_mask; | |
19286 | unsigned long fpreg_offset; | |
19287 | unsigned long frame_offset; | |
19288 | unsigned long frame_reg; | |
19289 | unsigned long pc_reg; | |
19290 | } procS; | |
252b5132 RH |
19291 | |
19292 | static procS cur_proc; | |
19293 | static procS *cur_proc_ptr; | |
19294 | static int numprocs; | |
19295 | ||
df58fc94 RS |
19296 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19297 | as "2", and a normal nop as "0". */ | |
19298 | ||
19299 | #define NOP_OPCODE_MIPS 0 | |
19300 | #define NOP_OPCODE_MIPS16 1 | |
19301 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19302 | |
19303 | char | |
19304 | mips_nop_opcode (void) | |
19305 | { | |
df58fc94 RS |
19306 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19307 | return NOP_OPCODE_MICROMIPS; | |
19308 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19309 | return NOP_OPCODE_MIPS16; | |
19310 | else | |
19311 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19312 | } |
19313 | ||
df58fc94 RS |
19314 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19315 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19316 | |
0a9ef439 | 19317 | void |
17a2f251 | 19318 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19319 | { |
df58fc94 | 19320 | char nop_opcode; |
742a56fe | 19321 | char *p; |
c67a084a NC |
19322 | int bytes, size, excess; |
19323 | valueT opcode; | |
742a56fe | 19324 | |
0a9ef439 RH |
19325 | if (fragp->fr_type != rs_align_code) |
19326 | return; | |
19327 | ||
742a56fe | 19328 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19329 | nop_opcode = *p; |
19330 | switch (nop_opcode) | |
a19d8eb0 | 19331 | { |
df58fc94 RS |
19332 | case NOP_OPCODE_MICROMIPS: |
19333 | opcode = micromips_nop32_insn.insn_opcode; | |
19334 | size = 4; | |
19335 | break; | |
19336 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19337 | opcode = mips16_nop_insn.insn_opcode; |
19338 | size = 2; | |
df58fc94 RS |
19339 | break; |
19340 | case NOP_OPCODE_MIPS: | |
19341 | default: | |
c67a084a NC |
19342 | opcode = nop_insn.insn_opcode; |
19343 | size = 4; | |
df58fc94 | 19344 | break; |
c67a084a | 19345 | } |
a19d8eb0 | 19346 | |
c67a084a NC |
19347 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19348 | excess = bytes % size; | |
df58fc94 RS |
19349 | |
19350 | /* Handle the leading part if we're not inserting a whole number of | |
19351 | instructions, and make it the end of the fixed part of the frag. | |
19352 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19353 | and use zeroes otherwise. */ | |
19354 | gas_assert (excess < 4); | |
19355 | fragp->fr_fix += excess; | |
19356 | switch (excess) | |
c67a084a | 19357 | { |
df58fc94 RS |
19358 | case 3: |
19359 | *p++ = '\0'; | |
19360 | /* Fall through. */ | |
19361 | case 2: | |
833794fc | 19362 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19363 | { |
4d68580a | 19364 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19365 | break; |
19366 | } | |
19367 | *p++ = '\0'; | |
19368 | /* Fall through. */ | |
19369 | case 1: | |
19370 | *p++ = '\0'; | |
19371 | /* Fall through. */ | |
19372 | case 0: | |
19373 | break; | |
a19d8eb0 | 19374 | } |
c67a084a NC |
19375 | |
19376 | md_number_to_chars (p, opcode, size); | |
19377 | fragp->fr_var = size; | |
a19d8eb0 CP |
19378 | } |
19379 | ||
252b5132 | 19380 | static long |
17a2f251 | 19381 | get_number (void) |
252b5132 RH |
19382 | { |
19383 | int negative = 0; | |
19384 | long val = 0; | |
19385 | ||
19386 | if (*input_line_pointer == '-') | |
19387 | { | |
19388 | ++input_line_pointer; | |
19389 | negative = 1; | |
19390 | } | |
3882b010 | 19391 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19392 | as_bad (_("expected simple number")); |
252b5132 RH |
19393 | if (input_line_pointer[0] == '0') |
19394 | { | |
19395 | if (input_line_pointer[1] == 'x') | |
19396 | { | |
19397 | input_line_pointer += 2; | |
3882b010 | 19398 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19399 | { |
19400 | val <<= 4; | |
19401 | val |= hex_value (*input_line_pointer++); | |
19402 | } | |
19403 | return negative ? -val : val; | |
19404 | } | |
19405 | else | |
19406 | { | |
19407 | ++input_line_pointer; | |
3882b010 | 19408 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19409 | { |
19410 | val <<= 3; | |
19411 | val |= *input_line_pointer++ - '0'; | |
19412 | } | |
19413 | return negative ? -val : val; | |
19414 | } | |
19415 | } | |
3882b010 | 19416 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19417 | { |
19418 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19419 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19420 | as_warn (_("invalid number")); |
252b5132 RH |
19421 | return -1; |
19422 | } | |
3882b010 | 19423 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19424 | { |
19425 | val *= 10; | |
19426 | val += *input_line_pointer++ - '0'; | |
19427 | } | |
19428 | return negative ? -val : val; | |
19429 | } | |
19430 | ||
19431 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19432 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19433 | case .file implies DWARF-2. */ | |
19434 | ||
19435 | static void | |
17a2f251 | 19436 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19437 | { |
ecb4347a DJ |
19438 | static int first_file_directive = 0; |
19439 | ||
c5dd6aab DJ |
19440 | if (ECOFF_DEBUGGING) |
19441 | { | |
19442 | get_number (); | |
19443 | s_app_file (0); | |
19444 | } | |
19445 | else | |
ecb4347a DJ |
19446 | { |
19447 | char *filename; | |
19448 | ||
68d20676 | 19449 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19450 | |
19451 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19452 | directive even for stabs output. Make sure that this | |
19453 | ".file" is handled. Note that you need a version of GCC | |
19454 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19455 | if (filename != NULL && ! first_file_directive) | |
19456 | { | |
19457 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19458 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19459 | } |
19460 | first_file_directive = 1; | |
19461 | } | |
c5dd6aab DJ |
19462 | } |
19463 | ||
19464 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19465 | |
19466 | static void | |
17a2f251 | 19467 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19468 | { |
c5dd6aab DJ |
19469 | if (!ECOFF_DEBUGGING) |
19470 | dwarf2_directive_loc (0); | |
252b5132 RH |
19471 | } |
19472 | ||
252b5132 RH |
19473 | /* The .end directive. */ |
19474 | ||
19475 | static void | |
17a2f251 | 19476 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19477 | { |
19478 | symbolS *p; | |
252b5132 | 19479 | |
7a621144 DJ |
19480 | /* Following functions need their own .frame and .cprestore directives. */ |
19481 | mips_frame_reg_valid = 0; | |
19482 | mips_cprestore_valid = 0; | |
19483 | ||
252b5132 RH |
19484 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19485 | { | |
19486 | p = get_symbol (); | |
19487 | demand_empty_rest_of_line (); | |
19488 | } | |
19489 | else | |
19490 | p = NULL; | |
19491 | ||
14949570 | 19492 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19493 | as_warn (_(".end not in text section")); |
19494 | ||
19495 | if (!cur_proc_ptr) | |
19496 | { | |
1661c76c | 19497 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19498 | demand_empty_rest_of_line (); |
19499 | return; | |
19500 | } | |
19501 | ||
19502 | if (p != NULL) | |
19503 | { | |
9c2799c2 | 19504 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19505 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19506 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19507 | |
19508 | if (debug_type == DEBUG_STABS) | |
19509 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19510 | S_GET_NAME (p)); | |
252b5132 RH |
19511 | } |
19512 | else | |
19513 | as_warn (_(".end directive missing or unknown symbol")); | |
19514 | ||
9b2f1d35 EC |
19515 | /* Create an expression to calculate the size of the function. */ |
19516 | if (p && cur_proc_ptr) | |
19517 | { | |
19518 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19519 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19520 | |
19521 | obj->size = exp; | |
19522 | exp->X_op = O_subtract; | |
19523 | exp->X_add_symbol = symbol_temp_new_now (); | |
19524 | exp->X_op_symbol = p; | |
19525 | exp->X_add_number = 0; | |
19526 | ||
19527 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19528 | } | |
19529 | ||
5ff6a06c MR |
19530 | #ifdef md_flush_pending_output |
19531 | md_flush_pending_output (); | |
19532 | #endif | |
19533 | ||
ecb4347a | 19534 | /* Generate a .pdr section. */ |
f3ded42a | 19535 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19536 | { |
19537 | segT saved_seg = now_seg; | |
19538 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19539 | expressionS exp; |
19540 | char *fragp; | |
252b5132 | 19541 | |
9c2799c2 | 19542 | gas_assert (pdr_seg); |
ecb4347a | 19543 | subseg_set (pdr_seg, 0); |
252b5132 | 19544 | |
ecb4347a DJ |
19545 | /* Write the symbol. */ |
19546 | exp.X_op = O_symbol; | |
19547 | exp.X_add_symbol = p; | |
19548 | exp.X_add_number = 0; | |
19549 | emit_expr (&exp, 4); | |
252b5132 | 19550 | |
ecb4347a | 19551 | fragp = frag_more (7 * 4); |
252b5132 | 19552 | |
17a2f251 TS |
19553 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19554 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19555 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19556 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19557 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19558 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19559 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19560 | |
ecb4347a DJ |
19561 | subseg_set (saved_seg, saved_subseg); |
19562 | } | |
252b5132 RH |
19563 | |
19564 | cur_proc_ptr = NULL; | |
19565 | } | |
19566 | ||
19567 | /* The .aent and .ent directives. */ | |
19568 | ||
19569 | static void | |
17a2f251 | 19570 | s_mips_ent (int aent) |
252b5132 | 19571 | { |
252b5132 | 19572 | symbolS *symbolP; |
252b5132 RH |
19573 | |
19574 | symbolP = get_symbol (); | |
19575 | if (*input_line_pointer == ',') | |
f9419b05 | 19576 | ++input_line_pointer; |
252b5132 | 19577 | SKIP_WHITESPACE (); |
3882b010 | 19578 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19579 | || *input_line_pointer == '-') |
874e8986 | 19580 | get_number (); |
252b5132 | 19581 | |
14949570 | 19582 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19583 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19584 | |
19585 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19586 | as_warn (_("missing .end")); |
252b5132 RH |
19587 | |
19588 | if (!aent) | |
19589 | { | |
7a621144 DJ |
19590 | /* This function needs its own .frame and .cprestore directives. */ |
19591 | mips_frame_reg_valid = 0; | |
19592 | mips_cprestore_valid = 0; | |
19593 | ||
252b5132 RH |
19594 | cur_proc_ptr = &cur_proc; |
19595 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19596 | ||
9b2f1d35 | 19597 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19598 | |
f9419b05 | 19599 | ++numprocs; |
ecb4347a DJ |
19600 | |
19601 | if (debug_type == DEBUG_STABS) | |
19602 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19603 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19604 | } |
19605 | ||
7c0fc524 MR |
19606 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19607 | ||
252b5132 RH |
19608 | demand_empty_rest_of_line (); |
19609 | } | |
19610 | ||
19611 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19612 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19613 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19614 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19615 | symbol table (in the mdebug section). */ |
19616 | ||
19617 | static void | |
17a2f251 | 19618 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19619 | { |
f3ded42a RS |
19620 | if (ECOFF_DEBUGGING) |
19621 | s_ignore (ignore); | |
19622 | else | |
ecb4347a DJ |
19623 | { |
19624 | long val; | |
252b5132 | 19625 | |
ecb4347a DJ |
19626 | if (cur_proc_ptr == (procS *) NULL) |
19627 | { | |
19628 | as_warn (_(".frame outside of .ent")); | |
19629 | demand_empty_rest_of_line (); | |
19630 | return; | |
19631 | } | |
252b5132 | 19632 | |
ecb4347a DJ |
19633 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19634 | ||
19635 | SKIP_WHITESPACE (); | |
19636 | if (*input_line_pointer++ != ',' | |
19637 | || get_absolute_expression_and_terminator (&val) != ',') | |
19638 | { | |
1661c76c | 19639 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19640 | --input_line_pointer; |
19641 | demand_empty_rest_of_line (); | |
19642 | return; | |
19643 | } | |
252b5132 | 19644 | |
ecb4347a DJ |
19645 | cur_proc_ptr->frame_offset = val; |
19646 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19647 | |
252b5132 | 19648 | demand_empty_rest_of_line (); |
252b5132 | 19649 | } |
252b5132 RH |
19650 | } |
19651 | ||
bdaaa2e1 KH |
19652 | /* The .fmask and .mask directives. If the mdebug section is present |
19653 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19654 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19655 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19656 | make reference to the ecoff symbol table (in the mdebug section). */ |
19657 | ||
19658 | static void | |
17a2f251 | 19659 | s_mips_mask (int reg_type) |
252b5132 | 19660 | { |
f3ded42a RS |
19661 | if (ECOFF_DEBUGGING) |
19662 | s_ignore (reg_type); | |
19663 | else | |
252b5132 | 19664 | { |
ecb4347a | 19665 | long mask, off; |
252b5132 | 19666 | |
ecb4347a DJ |
19667 | if (cur_proc_ptr == (procS *) NULL) |
19668 | { | |
19669 | as_warn (_(".mask/.fmask outside of .ent")); | |
19670 | demand_empty_rest_of_line (); | |
19671 | return; | |
19672 | } | |
252b5132 | 19673 | |
ecb4347a DJ |
19674 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19675 | { | |
1661c76c | 19676 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19677 | --input_line_pointer; |
19678 | demand_empty_rest_of_line (); | |
19679 | return; | |
19680 | } | |
252b5132 | 19681 | |
ecb4347a DJ |
19682 | off = get_absolute_expression (); |
19683 | ||
19684 | if (reg_type == 'F') | |
19685 | { | |
19686 | cur_proc_ptr->fpreg_mask = mask; | |
19687 | cur_proc_ptr->fpreg_offset = off; | |
19688 | } | |
19689 | else | |
19690 | { | |
19691 | cur_proc_ptr->reg_mask = mask; | |
19692 | cur_proc_ptr->reg_offset = off; | |
19693 | } | |
19694 | ||
19695 | demand_empty_rest_of_line (); | |
252b5132 | 19696 | } |
252b5132 RH |
19697 | } |
19698 | ||
316f5878 RS |
19699 | /* A table describing all the processors gas knows about. Names are |
19700 | matched in the order listed. | |
e7af610e | 19701 | |
316f5878 RS |
19702 | To ease comparison, please keep this table in the same order as |
19703 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19704 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19705 | { | |
316f5878 | 19706 | /* Entries for generic ISAs */ |
d16afab6 RS |
19707 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19708 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19709 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19710 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19711 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19712 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19713 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19714 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19715 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19716 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19717 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19718 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19719 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19720 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19721 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19722 | |
19723 | /* MIPS I */ | |
d16afab6 RS |
19724 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19725 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19726 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19727 | |
19728 | /* MIPS II */ | |
d16afab6 | 19729 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19730 | |
19731 | /* MIPS III */ | |
d16afab6 RS |
19732 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19733 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19734 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19735 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19736 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19737 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19738 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19739 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19740 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19741 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19742 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19743 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19744 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19745 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 | 19746 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 19747 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
19748 | |
19749 | /* MIPS IV */ | |
d16afab6 RS |
19750 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19751 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19752 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19753 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19754 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19755 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19756 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19757 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19758 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19759 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19760 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19761 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19762 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19763 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19764 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19765 | |
19766 | /* MIPS 32 */ | |
d16afab6 RS |
19767 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19768 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19769 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19770 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19771 | |
19772 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19773 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19774 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19775 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19776 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19777 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19778 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19779 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19780 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19781 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19782 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19783 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19784 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19785 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19786 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19787 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19788 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19789 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19790 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19791 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19792 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19793 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19794 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19795 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19796 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19797 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19798 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19799 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19800 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19801 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19802 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19803 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19804 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19805 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19806 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19807 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19808 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19809 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19810 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19811 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19812 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19813 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19814 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19815 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19816 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19817 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19818 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19819 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19820 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19821 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19822 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19823 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19824 | /* interaptiv is the new name for 1004kf */ |
19825 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
38bf472a MR |
19826 | { "interaptiv-mr2", 0, |
19827 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
19828 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
c6e5c03a RS |
19829 | /* M5100 family */ |
19830 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19831 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19832 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19833 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19834 | |
316f5878 | 19835 | /* MIPS 64 */ |
d16afab6 RS |
19836 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19837 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19838 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19839 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19840 | |
c7a23324 | 19841 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19842 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19843 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19844 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19845 | |
ed163775 | 19846 | /* MIPS 64 Release 2 */ |
716c08de | 19847 | /* Loongson CPU core */ |
ac8cb70f | 19848 | /* -march=loongson3a is an alias of -march=gs464 for compatibility */ |
bdc6c06e | 19849 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, |
ac8cb70f CX |
19850 | ISA_MIPS64R2, CPU_GS464 }, |
19851 | { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
19852 | ISA_MIPS64R2, CPU_GS464 }, | |
bd782c07 CX |
19853 | { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
19854 | | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
9108bc33 CX |
19855 | { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
19856 | | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
ed163775 | 19857 | |
967344c6 | 19858 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19859 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19860 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19861 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19862 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19863 | |
52b6b6b9 | 19864 | /* RMI Xlr */ |
d16afab6 | 19865 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19866 | |
55a36193 MK |
19867 | /* Broadcom XLP. |
19868 | XLP is mostly like XLR, with the prominent exception that it is | |
19869 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19870 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19871 | |
a4968f42 | 19872 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19873 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19874 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19875 | |
316f5878 | 19876 | /* End marker */ |
d16afab6 | 19877 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19878 | }; |
e7af610e | 19879 | |
84ea6cf2 | 19880 | |
316f5878 RS |
19881 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19882 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19883 | |
316f5878 | 19884 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19885 | |
b34976b6 | 19886 | static bfd_boolean |
17a2f251 | 19887 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19888 | { |
19889 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19890 | given++, canonical++; | |
19891 | ||
19892 | return ((*given == 0 && *canonical == 0) | |
19893 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19894 | } | |
19895 | ||
19896 | ||
19897 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19898 | CPU name. We've traditionally allowed a lot of variation here. | |
19899 | ||
19900 | Note: this function is shared between GCC and GAS. */ | |
19901 | ||
b34976b6 | 19902 | static bfd_boolean |
17a2f251 | 19903 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19904 | { |
19905 | /* First see if the name matches exactly, or with a final "000" | |
19906 | turned into "k". */ | |
19907 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19908 | return TRUE; |
316f5878 RS |
19909 | |
19910 | /* If not, try comparing based on numerical designation alone. | |
19911 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19912 | if (TOLOWER (*given) == 'r') | |
19913 | given++; | |
19914 | if (!ISDIGIT (*given)) | |
b34976b6 | 19915 | return FALSE; |
316f5878 RS |
19916 | |
19917 | /* Skip over some well-known prefixes in the canonical name, | |
19918 | hoping to find a number there too. */ | |
19919 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19920 | canonical += 2; | |
19921 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19922 | canonical += 2; | |
19923 | else if (TOLOWER (canonical[0]) == 'r') | |
19924 | canonical += 1; | |
19925 | ||
19926 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19927 | } | |
19928 | ||
19929 | ||
19930 | /* Parse an option that takes the name of a processor as its argument. | |
19931 | OPTION is the name of the option and CPU_STRING is the argument. | |
19932 | Return the corresponding processor enumeration if the CPU_STRING is | |
19933 | recognized, otherwise report an error and return null. | |
19934 | ||
19935 | A similar function exists in GCC. */ | |
e7af610e NC |
19936 | |
19937 | static const struct mips_cpu_info * | |
17a2f251 | 19938 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19939 | { |
316f5878 | 19940 | const struct mips_cpu_info *p; |
e7af610e | 19941 | |
316f5878 RS |
19942 | /* 'from-abi' selects the most compatible architecture for the given |
19943 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19944 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19945 | version. Look first at the -mgp options, if given, otherwise base | |
19946 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19947 | |
316f5878 RS |
19948 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19949 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19950 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19951 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19952 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19953 | { | |
19954 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19955 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19956 | ||
19957 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19958 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19959 | ||
bad1aba3 | 19960 | if (file_mips_opts.gp >= 0) |
19961 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19962 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19963 | |
19964 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19965 | ? ISA_MIPS3 | |
19966 | : ISA_MIPS1); | |
19967 | } | |
19968 | ||
19969 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19970 | if (strcasecmp (cpu_string, "default") == 0) | |
19971 | return 0; | |
19972 | ||
19973 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19974 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19975 | return p; | |
19976 | ||
1661c76c | 19977 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19978 | return 0; |
e7af610e NC |
19979 | } |
19980 | ||
316f5878 RS |
19981 | /* Return the canonical processor information for ISA (a member of the |
19982 | ISA_MIPS* enumeration). */ | |
19983 | ||
e7af610e | 19984 | static const struct mips_cpu_info * |
17a2f251 | 19985 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19986 | { |
19987 | int i; | |
19988 | ||
19989 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19990 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19991 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19992 | return (&mips_cpu_info_table[i]); |
19993 | ||
e972090a | 19994 | return NULL; |
e7af610e | 19995 | } |
fef14a42 TS |
19996 | |
19997 | static const struct mips_cpu_info * | |
17a2f251 | 19998 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19999 | { |
20000 | int i; | |
20001 | ||
20002 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
20003 | if (arch == mips_cpu_info_table[i].cpu) | |
20004 | return (&mips_cpu_info_table[i]); | |
20005 | ||
20006 | return NULL; | |
20007 | } | |
316f5878 RS |
20008 | \f |
20009 | static void | |
17a2f251 | 20010 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
20011 | { |
20012 | if (*first_p) | |
20013 | { | |
20014 | fprintf (stream, "%24s", ""); | |
20015 | *col_p = 24; | |
20016 | } | |
20017 | else | |
20018 | { | |
20019 | fprintf (stream, ", "); | |
20020 | *col_p += 2; | |
20021 | } | |
e7af610e | 20022 | |
316f5878 RS |
20023 | if (*col_p + strlen (string) > 72) |
20024 | { | |
20025 | fprintf (stream, "\n%24s", ""); | |
20026 | *col_p = 24; | |
20027 | } | |
20028 | ||
20029 | fprintf (stream, "%s", string); | |
20030 | *col_p += strlen (string); | |
20031 | ||
20032 | *first_p = 0; | |
20033 | } | |
20034 | ||
20035 | void | |
17a2f251 | 20036 | md_show_usage (FILE *stream) |
e7af610e | 20037 | { |
316f5878 RS |
20038 | int column, first; |
20039 | size_t i; | |
20040 | ||
20041 | fprintf (stream, _("\ | |
20042 | MIPS options:\n\ | |
316f5878 RS |
20043 | -EB generate big endian output\n\ |
20044 | -EL generate little endian output\n\ | |
20045 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
20046 | -G NUM allow referencing objects up to NUM bytes\n\ | |
20047 | implicitly with the gp register [default 8]\n")); | |
20048 | fprintf (stream, _("\ | |
20049 | -mips1 generate MIPS ISA I instructions\n\ | |
20050 | -mips2 generate MIPS ISA II instructions\n\ | |
20051 | -mips3 generate MIPS ISA III instructions\n\ | |
20052 | -mips4 generate MIPS ISA IV instructions\n\ | |
20053 | -mips5 generate MIPS ISA V instructions\n\ | |
20054 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 20055 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
20056 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
20057 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 20058 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 20059 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 20060 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
20061 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
20062 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 20063 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
20064 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
20065 | ||
20066 | first = 1; | |
e7af610e NC |
20067 | |
20068 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20069 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20070 | show (stream, "from-abi", &column, &first); | |
20071 | fputc ('\n', stream); | |
e7af610e | 20072 | |
316f5878 RS |
20073 | fprintf (stream, _("\ |
20074 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20075 | -no-mCPU don't generate code specific to CPU.\n\ | |
20076 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20077 | ||
20078 | first = 1; | |
20079 | ||
20080 | show (stream, "3900", &column, &first); | |
20081 | show (stream, "4010", &column, &first); | |
20082 | show (stream, "4100", &column, &first); | |
20083 | show (stream, "4650", &column, &first); | |
20084 | fputc ('\n', stream); | |
20085 | ||
20086 | fprintf (stream, _("\ | |
20087 | -mips16 generate mips16 instructions\n\ | |
20088 | -no-mips16 do not generate mips16 instructions\n")); | |
20089 | fprintf (stream, _("\ | |
f866b262 MR |
20090 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20091 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20092 | fprintf (stream, _("\ | |
df58fc94 RS |
20093 | -mmicromips generate microMIPS instructions\n\ |
20094 | -mno-micromips do not generate microMIPS instructions\n")); | |
20095 | fprintf (stream, _("\ | |
e16bfa71 | 20096 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20097 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20098 | fprintf (stream, _("\ |
74cd071d CF |
20099 | -mdsp generate DSP instructions\n\ |
20100 | -mno-dsp do not generate DSP instructions\n")); | |
20101 | fprintf (stream, _("\ | |
8b082fb1 TS |
20102 | -mdspr2 generate DSP R2 instructions\n\ |
20103 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20104 | fprintf (stream, _("\ | |
8f4f9071 MF |
20105 | -mdspr3 generate DSP R3 instructions\n\ |
20106 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20107 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20108 | -mmt generate MT instructions\n\ |
20109 | -mno-mt do not generate MT instructions\n")); | |
20110 | fprintf (stream, _("\ | |
dec0624d MR |
20111 | -mmcu generate MCU instructions\n\ |
20112 | -mno-mcu do not generate MCU instructions\n")); | |
20113 | fprintf (stream, _("\ | |
56d438b1 CF |
20114 | -mmsa generate MSA instructions\n\ |
20115 | -mno-msa do not generate MSA instructions\n")); | |
20116 | fprintf (stream, _("\ | |
7d64c587 AB |
20117 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20118 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20119 | fprintf (stream, _("\ | |
b015e599 AP |
20120 | -mvirt generate Virtualization instructions\n\ |
20121 | -mno-virt do not generate Virtualization instructions\n")); | |
20122 | fprintf (stream, _("\ | |
730c3174 SE |
20123 | -mcrc generate CRC instructions\n\ |
20124 | -mno-crc do not generate CRC instructions\n")); | |
20125 | fprintf (stream, _("\ | |
6f20c942 FS |
20126 | -mginv generate Global INValidate (GINV) instructions\n\ |
20127 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20128 | fprintf (stream, _("\ | |
8095d2f7 CX |
20129 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20130 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20131 | fprintf (stream, _("\ | |
716c08de CX |
20132 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20133 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20134 | fprintf (stream, _("\ | |
bdc6c06e CX |
20135 | -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ |
20136 | -mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
20137 | fprintf (stream, _("\ | |
a693765e CX |
20138 | -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ |
20139 | -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
20140 | fprintf (stream, _("\ | |
833794fc MR |
20141 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20142 | -mno-insn32 generate all microMIPS instructions\n")); | |
20143 | fprintf (stream, _("\ | |
c67a084a NC |
20144 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20145 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 20146 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20147 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20148 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20149 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
27c634e0 | 20150 | -mfix-r5900 work around R5900 short loop errata\n\ |
316f5878 RS |
20151 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20152 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20153 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20154 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20155 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20156 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20157 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20158 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20159 | fprintf (stream, _("\ |
20160 | -mhard-float allow floating-point instructions\n\ | |
20161 | -msoft-float do not allow floating-point instructions\n\ | |
20162 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20163 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20164 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20165 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20166 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20167 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20168 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20169 | ||
20170 | first = 1; | |
20171 | ||
20172 | show (stream, "legacy", &column, &first); | |
20173 | show (stream, "2008", &column, &first); | |
20174 | ||
20175 | fputc ('\n', stream); | |
20176 | ||
316f5878 RS |
20177 | fprintf (stream, _("\ |
20178 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20179 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20180 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20181 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20182 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20183 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20184 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20185 | position dependent (non shared) code\n\ |
316f5878 RS |
20186 | -mabi=ABI create ABI conformant object file for:\n")); |
20187 | ||
20188 | first = 1; | |
20189 | ||
20190 | show (stream, "32", &column, &first); | |
20191 | show (stream, "o64", &column, &first); | |
20192 | show (stream, "n32", &column, &first); | |
20193 | show (stream, "64", &column, &first); | |
20194 | show (stream, "eabi", &column, &first); | |
20195 | ||
20196 | fputc ('\n', stream); | |
20197 | ||
20198 | fprintf (stream, _("\ | |
b4f6242e MR |
20199 | -32 create o32 ABI object file%s\n"), |
20200 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20201 | fprintf (stream, _("\ | |
20202 | -n32 create n32 ABI object file%s\n"), | |
20203 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20204 | fprintf (stream, _("\ | |
20205 | -64 create 64 ABI object file%s\n"), | |
20206 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20207 | } |
14e777e0 | 20208 | |
1575952e | 20209 | #ifdef TE_IRIX |
14e777e0 | 20210 | enum dwarf2_format |
413a266c | 20211 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20212 | { |
369943fe | 20213 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20214 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20215 | else |
20216 | return dwarf2_format_32bit; | |
20217 | } | |
1575952e | 20218 | #endif |
73369e65 EC |
20219 | |
20220 | int | |
20221 | mips_dwarf2_addr_size (void) | |
20222 | { | |
6b6b3450 | 20223 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20224 | return 8; |
73369e65 EC |
20225 | else |
20226 | return 4; | |
20227 | } | |
5862107c EC |
20228 | |
20229 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20230 | void | |
20231 | mips_cfi_frame_initial_instructions (void) | |
20232 | { | |
20233 | cfi_add_CFA_def_cfa_register (SP); | |
20234 | } | |
20235 | ||
707bfff6 TS |
20236 | int |
20237 | tc_mips_regname_to_dw2regnum (char *regname) | |
20238 | { | |
20239 | unsigned int regnum = -1; | |
20240 | unsigned int reg; | |
20241 | ||
20242 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20243 | regnum = reg; | |
20244 | ||
20245 | return regnum; | |
20246 | } | |
263b2574 | 20247 | |
20248 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20249 | Given a symbolic attribute NAME, return the proper integer value. | |
20250 | Returns -1 if the attribute is not known. */ | |
20251 | ||
20252 | int | |
20253 | mips_convert_symbolic_attribute (const char *name) | |
20254 | { | |
20255 | static const struct | |
20256 | { | |
20257 | const char * name; | |
20258 | const int tag; | |
20259 | } | |
20260 | attribute_table[] = | |
20261 | { | |
20262 | #define T(tag) {#tag, tag} | |
20263 | T (Tag_GNU_MIPS_ABI_FP), | |
20264 | T (Tag_GNU_MIPS_ABI_MSA), | |
20265 | #undef T | |
20266 | }; | |
20267 | unsigned int i; | |
20268 | ||
20269 | if (name == NULL) | |
20270 | return -1; | |
20271 | ||
20272 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20273 | if (streq (name, attribute_table[i].name)) | |
20274 | return attribute_table[i].tag; | |
20275 | ||
20276 | return -1; | |
20277 | } | |
fd5c94ab RS |
20278 | |
20279 | void | |
20280 | md_mips_end (void) | |
20281 | { | |
351cdf24 MF |
20282 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20283 | ||
fd5c94ab RS |
20284 | mips_emit_delays (); |
20285 | if (cur_proc_ptr) | |
20286 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20287 | |
20288 | /* Just in case no code was emitted, do the consistency check. */ | |
20289 | file_mips_check_options (); | |
351cdf24 MF |
20290 | |
20291 | /* Set a floating-point ABI if the user did not. */ | |
20292 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20293 | { | |
20294 | /* Perform consistency checks on the floating-point ABI. */ | |
20295 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20296 | Tag_GNU_MIPS_ABI_FP); | |
20297 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20298 | check_fpabi (fpabi); | |
20299 | } | |
20300 | else | |
20301 | { | |
20302 | /* Soft-float gets precedence over single-float, the two options should | |
20303 | not be used together so this should not matter. */ | |
20304 | if (file_mips_opts.soft_float == 1) | |
20305 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20306 | /* Single-float gets precedence over all double_float cases. */ | |
20307 | else if (file_mips_opts.single_float == 1) | |
20308 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20309 | else | |
20310 | { | |
20311 | switch (file_mips_opts.fp) | |
20312 | { | |
20313 | case 32: | |
20314 | if (file_mips_opts.gp == 32) | |
20315 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20316 | break; | |
20317 | case 0: | |
20318 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20319 | break; | |
20320 | case 64: | |
20321 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20322 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20323 | else if (file_mips_opts.gp == 32) | |
20324 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20325 | else | |
20326 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20327 | break; | |
20328 | } | |
20329 | } | |
20330 | ||
20331 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20332 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20333 | } | |
fd5c94ab | 20334 | } |
2f0c68f2 CM |
20335 | |
20336 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20337 | ||
20338 | bfd_reloc_code_real_type | |
20339 | mips_cfi_reloc_for_encoding (int encoding) | |
20340 | { | |
20341 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20342 | return BFD_RELOC_32_PCREL; | |
20343 | else return BFD_RELOC_NONE; | |
20344 | } |