Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
7f3c4072 | 219 | int ase_eva; |
ef2e4d86 | 220 | int ase_mt; |
dec0624d | 221 | int ase_mcu; |
b015e599 | 222 | int ase_virt; |
252b5132 RH |
223 | /* Whether we are assembling for the mips16 processor. 0 if we are |
224 | not, 1 if we are, and -1 if the value has not been initialized. | |
225 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
226 | -nomips16 command line options, and the default CPU. */ | |
227 | int mips16; | |
df58fc94 RS |
228 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
229 | 1 if we are, and -1 if the value has not been initialized. Changed | |
230 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
231 | and -mno-micromips command line options, and the default CPU. */ | |
232 | int micromips; | |
252b5132 RH |
233 | /* Non-zero if we should not reorder instructions. Changed by `.set |
234 | reorder' and `.set noreorder'. */ | |
235 | int noreorder; | |
741fe287 MR |
236 | /* Non-zero if we should not permit the register designated "assembler |
237 | temporary" to be used in instructions. The value is the register | |
238 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
239 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
240 | unsigned int at; | |
252b5132 RH |
241 | /* Non-zero if we should warn when a macro instruction expands into |
242 | more than one machine instruction. Changed by `.set nomacro' and | |
243 | `.set macro'. */ | |
244 | int warn_about_macros; | |
245 | /* Non-zero if we should not move instructions. Changed by `.set | |
246 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
247 | int nomove; | |
248 | /* Non-zero if we should not optimize branches by moving the target | |
249 | of the branch into the delay slot. Actually, we don't perform | |
250 | this optimization anyhow. Changed by `.set bopt' and `.set | |
251 | nobopt'. */ | |
252 | int nobopt; | |
253 | /* Non-zero if we should not autoextend mips16 instructions. | |
254 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
255 | int noautoextend; | |
a325df1d TS |
256 | /* Restrict general purpose registers and floating point registers |
257 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
258 | is passed but can changed if the assembler code uses .set mipsN. */ | |
259 | int gp32; | |
260 | int fp32; | |
fef14a42 TS |
261 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
262 | command line option, and the default CPU. */ | |
263 | int arch; | |
aed1a261 RS |
264 | /* True if ".set sym32" is in effect. */ |
265 | bfd_boolean sym32; | |
037b32b9 AN |
266 | /* True if floating-point operations are not allowed. Changed by .set |
267 | softfloat or .set hardfloat, by command line options -msoft-float or | |
268 | -mhard-float. The default is false. */ | |
269 | bfd_boolean soft_float; | |
270 | ||
271 | /* True if only single-precision floating-point operations are allowed. | |
272 | Changed by .set singlefloat or .set doublefloat, command-line options | |
273 | -msingle-float or -mdouble-float. The default is false. */ | |
274 | bfd_boolean single_float; | |
252b5132 RH |
275 | }; |
276 | ||
037b32b9 AN |
277 | /* This is the struct we use to hold the current set of options. Note |
278 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
279 | -1 to indicate that they have not been initialized. */ | |
280 | ||
a325df1d | 281 | /* True if -mgp32 was passed. */ |
a8e8e863 | 282 | static int file_mips_gp32 = -1; |
a325df1d TS |
283 | |
284 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 285 | static int file_mips_fp32 = -1; |
a325df1d | 286 | |
037b32b9 AN |
287 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
288 | static int file_mips_soft_float = 0; | |
289 | ||
290 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
291 | static int file_mips_single_float = 0; | |
252b5132 | 292 | |
e972090a NC |
293 | static struct mips_set_options mips_opts = |
294 | { | |
037b32b9 | 295 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
7f3c4072 CM |
296 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, |
297 | /* ase_eva */ -1, /* ase_mt */ -1, /* ase_mcu */ -1, | |
298 | /* ase_virt */ -1, /* mips16 */ -1, /* micromips */ -1, | |
b015e599 AP |
299 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
300 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
301 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
302 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 303 | }; |
252b5132 RH |
304 | |
305 | /* These variables are filled in with the masks of registers used. | |
306 | The object format code reads them and puts them in the appropriate | |
307 | place. */ | |
308 | unsigned long mips_gprmask; | |
309 | unsigned long mips_cprmask[4]; | |
310 | ||
311 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 312 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 313 | |
738f4d98 | 314 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
315 | static int file_ase_mips16; |
316 | ||
3994f87e TS |
317 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
318 | || mips_opts.isa == ISA_MIPS32R2 \ | |
319 | || mips_opts.isa == ISA_MIPS64 \ | |
320 | || mips_opts.isa == ISA_MIPS64R2) | |
321 | ||
df58fc94 RS |
322 | /* True if any microMIPS code was produced. */ |
323 | static int file_ase_micromips; | |
324 | ||
b12dd2e4 CF |
325 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
326 | #ifdef TE_IRIX | |
1180b5a4 | 327 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 328 | #else |
1180b5a4 RS |
329 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
330 | because there's no place for any addend, the only acceptable | |
331 | expression is a bare symbol. */ | |
332 | #define MIPS_JALR_HINT_P(EXPR) \ | |
333 | (!HAVE_IN_PLACE_ADDENDS \ | |
334 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
335 | #endif |
336 | ||
1f25f5d3 CD |
337 | /* True if -mips3d was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mips3d; | |
340 | ||
deec1734 CD |
341 | /* True if -mdmx was passed or implied by arguments passed on the |
342 | command line (e.g., by -march). */ | |
343 | static int file_ase_mdmx; | |
344 | ||
e16bfa71 TS |
345 | /* True if -msmartmips was passed or implied by arguments passed on the |
346 | command line (e.g., by -march). */ | |
347 | static int file_ase_smartmips; | |
348 | ||
ad3fea08 TS |
349 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
350 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 351 | |
74cd071d CF |
352 | /* True if -mdsp was passed or implied by arguments passed on the |
353 | command line (e.g., by -march). */ | |
354 | static int file_ase_dsp; | |
355 | ||
ad3fea08 | 356 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
357 | || mips_opts.isa == ISA_MIPS64R2 \ |
358 | || mips_opts.micromips) | |
ad3fea08 | 359 | |
65263ce3 TS |
360 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
361 | ||
8b082fb1 TS |
362 | /* True if -mdspr2 was passed or implied by arguments passed on the |
363 | command line (e.g., by -march). */ | |
364 | static int file_ase_dspr2; | |
365 | ||
366 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
367 | || mips_opts.isa == ISA_MIPS64R2 \ |
368 | || mips_opts.micromips) | |
8b082fb1 | 369 | |
7f3c4072 CM |
370 | /* True if -meva was passed or implied by arguments passed on the |
371 | command line (e.g., by -march). */ | |
372 | static int file_ase_eva; | |
373 | ||
374 | #define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
375 | || mips_opts.isa == ISA_MIPS64R2 \ | |
376 | || mips_opts.micromips) | |
377 | ||
ef2e4d86 CF |
378 | /* True if -mmt was passed or implied by arguments passed on the |
379 | command line (e.g., by -march). */ | |
380 | static int file_ase_mt; | |
381 | ||
ad3fea08 TS |
382 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
383 | || mips_opts.isa == ISA_MIPS64R2) | |
384 | ||
dec0624d | 385 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
386 | || mips_opts.isa == ISA_MIPS64R2 \ |
387 | || mips_opts.micromips) | |
dec0624d | 388 | |
b015e599 AP |
389 | /* True if -mvirt was passed or implied by arguments passed on the |
390 | command line (e.g., by -march). */ | |
391 | static int file_ase_virt; | |
392 | ||
393 | #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
f122319e CF |
394 | || mips_opts.isa == ISA_MIPS64R2 \ |
395 | || mips_opts.micromips) | |
b015e599 | 396 | |
f122319e CF |
397 | #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \ |
398 | || (mips_opts.micromips \ | |
399 | && ISA_HAS_64BIT_REGS (mips_opts.isa))) | |
b015e599 | 400 | |
ec68c924 | 401 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 402 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 403 | static const char *mips_arch_string; |
ec68c924 EC |
404 | |
405 | /* The argument of the -mtune= flag. The architecture for which we | |
406 | are optimizing. */ | |
407 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 408 | static const char *mips_tune_string; |
ec68c924 | 409 | |
316f5878 | 410 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
411 | static int mips_32bitmode = 0; |
412 | ||
316f5878 RS |
413 | /* True if the given ABI requires 32-bit registers. */ |
414 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
415 | ||
416 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
417 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
418 | ((ABI) == N32_ABI \ | |
419 | || (ABI) == N64_ABI \ | |
316f5878 RS |
420 | || (ABI) == O64_ABI) |
421 | ||
ad3fea08 | 422 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
423 | #define ISA_HAS_64BIT_REGS(ISA) \ |
424 | ((ISA) == ISA_MIPS3 \ | |
425 | || (ISA) == ISA_MIPS4 \ | |
426 | || (ISA) == ISA_MIPS5 \ | |
427 | || (ISA) == ISA_MIPS64 \ | |
428 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 429 | |
ad3fea08 TS |
430 | /* Return true if ISA supports 64 bit wide float registers. */ |
431 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
432 | ((ISA) == ISA_MIPS3 \ | |
433 | || (ISA) == ISA_MIPS4 \ | |
434 | || (ISA) == ISA_MIPS5 \ | |
435 | || (ISA) == ISA_MIPS32R2 \ | |
436 | || (ISA) == ISA_MIPS64 \ | |
437 | || (ISA) == ISA_MIPS64R2) | |
438 | ||
af7ee8bf CD |
439 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
440 | instructions. */ | |
707bfff6 | 441 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
442 | ((ISA) == ISA_MIPS64R2 \ |
443 | || (mips_opts.micromips \ | |
444 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
445 | ) | |
af7ee8bf CD |
446 | |
447 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
448 | instructions. */ | |
707bfff6 TS |
449 | #define ISA_HAS_ROR(ISA) \ |
450 | ((ISA) == ISA_MIPS32R2 \ | |
451 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
452 | || mips_opts.ase_smartmips \ |
453 | || mips_opts.micromips \ | |
454 | ) | |
707bfff6 | 455 | |
7455baf8 TS |
456 | /* Return true if ISA supports single-precision floats in odd registers. */ |
457 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
458 | ((ISA) == ISA_MIPS32 \ | |
459 | || (ISA) == ISA_MIPS32R2 \ | |
460 | || (ISA) == ISA_MIPS64 \ | |
461 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 462 | |
ad3fea08 TS |
463 | /* Return true if ISA supports move to/from high part of a 64-bit |
464 | floating-point register. */ | |
465 | #define ISA_HAS_MXHC1(ISA) \ | |
466 | ((ISA) == ISA_MIPS32R2 \ | |
467 | || (ISA) == ISA_MIPS64R2) | |
468 | ||
e013f690 | 469 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 470 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 471 | |
e013f690 | 472 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 473 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 474 | |
ad3fea08 TS |
475 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
476 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 477 | |
316f5878 | 478 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 479 | |
316f5878 | 480 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 481 | |
3b91255e RS |
482 | /* True if relocations are stored in-place. */ |
483 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
484 | ||
aed1a261 RS |
485 | /* The ABI-derived address size. */ |
486 | #define HAVE_64BIT_ADDRESSES \ | |
487 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
488 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 489 | |
aed1a261 RS |
490 | /* The size of symbolic constants (i.e., expressions of the form |
491 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
492 | #define HAVE_32BIT_SYMBOLS \ | |
493 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
494 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 495 | |
b7c7d6c1 TS |
496 | /* Addresses are loaded in different ways, depending on the address size |
497 | in use. The n32 ABI Documentation also mandates the use of additions | |
498 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 499 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 500 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
501 | |
502 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 503 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
504 | |
505 | #define ADDRESS_LOAD_INSN \ | |
506 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
507 | ||
508 | #define ADDRESS_STORE_INSN \ | |
509 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
510 | ||
a4672219 | 511 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
512 | #define CPU_HAS_MIPS16(cpu) \ |
513 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
514 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 515 | |
2309ddf2 | 516 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
517 | #define CPU_HAS_MICROMIPS(cpu) 0 |
518 | ||
60b63b72 RS |
519 | /* True if CPU has a dror instruction. */ |
520 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
521 | ||
522 | /* True if CPU has a ror instruction. */ | |
523 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
524 | ||
dd6a37e7 | 525 | /* True if CPU is in the Octeon family */ |
432233b3 | 526 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 527 | |
dd3cbb7e | 528 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 529 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 530 | |
0aa27725 RS |
531 | /* True, if CPU has support for ldc1 and sdc1. */ |
532 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
533 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
534 | ||
c8978940 CD |
535 | /* True if mflo and mfhi can be immediately followed by instructions |
536 | which write to the HI and LO registers. | |
537 | ||
538 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
539 | (at least) two instructions between the reads of HI/LO and | |
540 | instructions which write them, and later ISAs do not. Contradicting | |
541 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
542 | the UM for the NEC Vr5000) document needing the instructions between | |
543 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
544 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
545 | earlier-ISA CPUs for which CPU documentation declares that the | |
546 | instructions are really interlocked. */ | |
547 | #define hilo_interlocks \ | |
548 | (mips_opts.isa == ISA_MIPS32 \ | |
549 | || mips_opts.isa == ISA_MIPS32R2 \ | |
550 | || mips_opts.isa == ISA_MIPS64 \ | |
551 | || mips_opts.isa == ISA_MIPS64R2 \ | |
552 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 553 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
554 | || mips_opts.arch == CPU_R10000 \ |
555 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
556 | || mips_opts.arch == CPU_R14000 \ |
557 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 558 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 559 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 560 | || mips_opts.micromips \ |
c8978940 | 561 | ) |
252b5132 RH |
562 | |
563 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
564 | from the GPRs after they are loaded from memory, and thus does not |
565 | require nops to be inserted. This applies to instructions marked | |
566 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
567 | level I and microMIPS mode instructions are always interlocked. */ |
568 | #define gpr_interlocks \ | |
569 | (mips_opts.isa != ISA_MIPS1 \ | |
570 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 571 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
572 | || mips_opts.micromips \ |
573 | ) | |
252b5132 | 574 | |
81912461 ILT |
575 | /* Whether the processor uses hardware interlocks to avoid delays |
576 | required by coprocessor instructions, and thus does not require | |
577 | nops to be inserted. This applies to instructions marked | |
578 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
579 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
580 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
581 | levels I, II, and III and microMIPS mode instructions are always |
582 | interlocked. */ | |
bdaaa2e1 | 583 | /* Itbl support may require additional care here. */ |
81912461 ILT |
584 | #define cop_interlocks \ |
585 | ((mips_opts.isa != ISA_MIPS1 \ | |
586 | && mips_opts.isa != ISA_MIPS2 \ | |
587 | && mips_opts.isa != ISA_MIPS3) \ | |
588 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 589 | || mips_opts.micromips \ |
81912461 ILT |
590 | ) |
591 | ||
592 | /* Whether the processor uses hardware interlocks to protect reads | |
593 | from coprocessor registers after they are loaded from memory, and | |
594 | thus does not require nops to be inserted. This applies to | |
595 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
596 | requires at MIPS ISA level I and microMIPS mode instructions are |
597 | always interlocked. */ | |
598 | #define cop_mem_interlocks \ | |
599 | (mips_opts.isa != ISA_MIPS1 \ | |
600 | || mips_opts.micromips \ | |
601 | ) | |
252b5132 | 602 | |
6b76fefe CM |
603 | /* Is this a mfhi or mflo instruction? */ |
604 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
605 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
606 | ||
df58fc94 RS |
607 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
608 | has been selected. This implies, in particular, that addresses of text | |
609 | labels have their LSB set. */ | |
610 | #define HAVE_CODE_COMPRESSION \ | |
611 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
612 | ||
252b5132 RH |
613 | /* MIPS PIC level. */ |
614 | ||
a161fe53 | 615 | enum mips_pic_level mips_pic; |
252b5132 | 616 | |
c9914766 | 617 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 618 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 619 | static int mips_big_got = 0; |
252b5132 RH |
620 | |
621 | /* 1 if trap instructions should used for overflow rather than break | |
622 | instructions. */ | |
c9914766 | 623 | static int mips_trap = 0; |
252b5132 | 624 | |
119d663a | 625 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 626 | by assembling two single width halves into two single width floating |
119d663a NC |
627 | point registers which just happen to alias the double width destination |
628 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 629 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
630 | automatically at assemble time. */ |
631 | static int mips_disable_float_construction; | |
632 | ||
252b5132 RH |
633 | /* Non-zero if any .set noreorder directives were used. */ |
634 | ||
635 | static int mips_any_noreorder; | |
636 | ||
6b76fefe CM |
637 | /* Non-zero if nops should be inserted when the register referenced in |
638 | an mfhi/mflo instruction is read in the next two instructions. */ | |
639 | static int mips_7000_hilo_fix; | |
640 | ||
02ffd3e4 | 641 | /* The size of objects in the small data section. */ |
156c2f8b | 642 | static unsigned int g_switch_value = 8; |
252b5132 RH |
643 | /* Whether the -G option was used. */ |
644 | static int g_switch_seen = 0; | |
645 | ||
646 | #define N_RMASK 0xc4 | |
647 | #define N_VFP 0xd4 | |
648 | ||
649 | /* If we can determine in advance that GP optimization won't be | |
650 | possible, we can skip the relaxation stuff that tries to produce | |
651 | GP-relative references. This makes delay slot optimization work | |
652 | better. | |
653 | ||
654 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
655 | gcc output. It needs to guess right for gcc, otherwise gcc |
656 | will put what it thinks is a GP-relative instruction in a branch | |
657 | delay slot. | |
252b5132 RH |
658 | |
659 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
660 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 661 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
662 | |
663 | /* handle of the OPCODE hash table */ | |
664 | static struct hash_control *op_hash = NULL; | |
665 | ||
666 | /* The opcode hash table we use for the mips16. */ | |
667 | static struct hash_control *mips16_op_hash = NULL; | |
668 | ||
df58fc94 RS |
669 | /* The opcode hash table we use for the microMIPS ASE. */ |
670 | static struct hash_control *micromips_op_hash = NULL; | |
671 | ||
252b5132 RH |
672 | /* This array holds the chars that always start a comment. If the |
673 | pre-processor is disabled, these aren't very useful */ | |
674 | const char comment_chars[] = "#"; | |
675 | ||
676 | /* This array holds the chars that only start a comment at the beginning of | |
677 | a line. If the line seems to have the form '# 123 filename' | |
678 | .line and .file directives will appear in the pre-processed output */ | |
679 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
680 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 681 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
682 | /* Also note that C style comments are always supported. */ |
683 | const char line_comment_chars[] = "#"; | |
684 | ||
bdaaa2e1 | 685 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 686 | const char line_separator_chars[] = ";"; |
252b5132 RH |
687 | |
688 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
689 | const char EXP_CHARS[] = "eE"; | |
690 | ||
691 | /* Chars that mean this number is a floating point constant */ | |
692 | /* As in 0f12.456 */ | |
693 | /* or 0d1.2345e12 */ | |
694 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
695 | ||
696 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
697 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
698 | but nothing is ideal around here. | |
699 | */ | |
700 | ||
701 | static char *insn_error; | |
702 | ||
703 | static int auto_align = 1; | |
704 | ||
705 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
706 | offset in the stack frame from which to restore the $gp register. | |
707 | This is set by the .cprestore pseudo-op, and saved in this | |
708 | variable. */ | |
709 | static offsetT mips_cprestore_offset = -1; | |
710 | ||
67c1ffbe | 711 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 712 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 713 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
714 | static offsetT mips_cpreturn_offset = -1; |
715 | static int mips_cpreturn_register = -1; | |
716 | static int mips_gp_register = GP; | |
def2e0dd | 717 | static int mips_gprel_offset = 0; |
6478892d | 718 | |
7a621144 DJ |
719 | /* Whether mips_cprestore_offset has been set in the current function |
720 | (or whether it has already been warned about, if not). */ | |
721 | static int mips_cprestore_valid = 0; | |
722 | ||
252b5132 RH |
723 | /* This is the register which holds the stack frame, as set by the |
724 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
725 | static int mips_frame_reg = SP; | |
726 | ||
7a621144 DJ |
727 | /* Whether mips_frame_reg has been set in the current function |
728 | (or whether it has already been warned about, if not). */ | |
729 | static int mips_frame_reg_valid = 0; | |
730 | ||
252b5132 RH |
731 | /* To output NOP instructions correctly, we need to keep information |
732 | about the previous two instructions. */ | |
733 | ||
734 | /* Whether we are optimizing. The default value of 2 means to remove | |
735 | unneeded NOPs and swap branch instructions when possible. A value | |
736 | of 1 means to not swap branches. A value of 0 means to always | |
737 | insert NOPs. */ | |
738 | static int mips_optimize = 2; | |
739 | ||
740 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
741 | equivalent to seeing no -g option at all. */ | |
742 | static int mips_debug = 0; | |
743 | ||
7d8e00cf RS |
744 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
745 | #define MAX_VR4130_NOPS 4 | |
746 | ||
747 | /* The maximum number of NOPs needed to fill delay slots. */ | |
748 | #define MAX_DELAY_NOPS 2 | |
749 | ||
750 | /* The maximum number of NOPs needed for any purpose. */ | |
751 | #define MAX_NOPS 4 | |
71400594 RS |
752 | |
753 | /* A list of previous instructions, with index 0 being the most recent. | |
754 | We need to look back MAX_NOPS instructions when filling delay slots | |
755 | or working around processor errata. We need to look back one | |
756 | instruction further if we're thinking about using history[0] to | |
757 | fill a branch delay slot. */ | |
758 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 759 | |
1e915849 | 760 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
761 | static struct mips_cl_insn nop_insn; |
762 | static struct mips_cl_insn mips16_nop_insn; | |
763 | static struct mips_cl_insn micromips_nop16_insn; | |
764 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
765 | |
766 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
767 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
768 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
769 | ||
770 | /* The size of NOP_INSN in bytes. */ | |
771 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 772 | |
252b5132 RH |
773 | /* If this is set, it points to a frag holding nop instructions which |
774 | were inserted before the start of a noreorder section. If those | |
775 | nops turn out to be unnecessary, the size of the frag can be | |
776 | decreased. */ | |
777 | static fragS *prev_nop_frag; | |
778 | ||
779 | /* The number of nop instructions we created in prev_nop_frag. */ | |
780 | static int prev_nop_frag_holds; | |
781 | ||
782 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 783 | prev_nop_frag. */ |
252b5132 RH |
784 | static int prev_nop_frag_required; |
785 | ||
786 | /* The number of instructions we've seen since prev_nop_frag. */ | |
787 | static int prev_nop_frag_since; | |
788 | ||
789 | /* For ECOFF and ELF, relocations against symbols are done in two | |
790 | parts, with a HI relocation and a LO relocation. Each relocation | |
791 | has only 16 bits of space to store an addend. This means that in | |
792 | order for the linker to handle carries correctly, it must be able | |
793 | to locate both the HI and the LO relocation. This means that the | |
794 | relocations must appear in order in the relocation table. | |
795 | ||
796 | In order to implement this, we keep track of each unmatched HI | |
797 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 798 | corresponding LO relocation. */ |
252b5132 | 799 | |
e972090a NC |
800 | struct mips_hi_fixup |
801 | { | |
252b5132 RH |
802 | /* Next HI fixup. */ |
803 | struct mips_hi_fixup *next; | |
804 | /* This fixup. */ | |
805 | fixS *fixp; | |
806 | /* The section this fixup is in. */ | |
807 | segT seg; | |
808 | }; | |
809 | ||
810 | /* The list of unmatched HI relocs. */ | |
811 | ||
812 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
813 | ||
64bdfcaf RS |
814 | /* The frag containing the last explicit relocation operator. |
815 | Null if explicit relocations have not been used. */ | |
816 | ||
817 | static fragS *prev_reloc_op_frag; | |
818 | ||
252b5132 RH |
819 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
820 | ||
821 | #define X ILLEGAL_REG | |
e972090a NC |
822 | static const int mips32_to_16_reg_map[] = |
823 | { | |
252b5132 RH |
824 | X, X, 2, 3, 4, 5, 6, 7, |
825 | X, X, X, X, X, X, X, X, | |
826 | 0, 1, X, X, X, X, X, X, | |
827 | X, X, X, X, X, X, X, X | |
828 | }; | |
829 | #undef X | |
830 | ||
831 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
832 | ||
e972090a NC |
833 | static const unsigned int mips16_to_32_reg_map[] = |
834 | { | |
252b5132 RH |
835 | 16, 17, 2, 3, 4, 5, 6, 7 |
836 | }; | |
60b63b72 | 837 | |
df58fc94 RS |
838 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
839 | ||
840 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
841 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
842 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
843 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
844 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
845 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
846 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
847 | ||
848 | #define X ILLEGAL_REG | |
849 | /* reg type h: 4, 5, 6. */ | |
850 | static const int mips32_to_micromips_reg_h_map[] = | |
851 | { | |
852 | X, X, X, X, 4, 5, 6, X, | |
853 | X, X, X, X, X, X, X, X, | |
854 | X, X, X, X, X, X, X, X, | |
855 | X, X, X, X, X, X, X, X | |
856 | }; | |
857 | ||
858 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
859 | static const int mips32_to_micromips_reg_m_map[] = | |
860 | { | |
861 | 0, X, 2, 3, X, X, X, X, | |
862 | X, X, X, X, X, X, X, X, | |
863 | 4, 1, 5, 6, 7, X, X, X, | |
864 | X, X, X, X, X, X, X, X | |
865 | }; | |
866 | ||
867 | /* reg type q: 0, 2-7. 17. */ | |
868 | static const int mips32_to_micromips_reg_q_map[] = | |
869 | { | |
870 | 0, X, 2, 3, 4, 5, 6, 7, | |
871 | X, X, X, X, X, X, X, X, | |
872 | X, 1, X, X, X, X, X, X, | |
873 | X, X, X, X, X, X, X, X | |
874 | }; | |
875 | ||
876 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
877 | #undef X | |
878 | ||
879 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
880 | ||
881 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
882 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
883 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
884 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
885 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
886 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
887 | ||
888 | /* The microMIPS registers with type h. */ | |
889 | static const unsigned int micromips_to_32_reg_h_map[] = | |
890 | { | |
891 | 5, 5, 6, 4, 4, 4, 4, 4 | |
892 | }; | |
893 | ||
894 | /* The microMIPS registers with type i. */ | |
895 | static const unsigned int micromips_to_32_reg_i_map[] = | |
896 | { | |
897 | 6, 7, 7, 21, 22, 5, 6, 7 | |
898 | }; | |
899 | ||
900 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
901 | ||
902 | /* The microMIPS registers with type m. */ | |
903 | static const unsigned int micromips_to_32_reg_m_map[] = | |
904 | { | |
905 | 0, 17, 2, 3, 16, 18, 19, 20 | |
906 | }; | |
907 | ||
908 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
909 | ||
910 | /* The microMIPS registers with type q. */ | |
911 | static const unsigned int micromips_to_32_reg_q_map[] = | |
912 | { | |
913 | 0, 17, 2, 3, 4, 5, 6, 7 | |
914 | }; | |
915 | ||
916 | /* microMIPS imm type B. */ | |
917 | static const int micromips_imm_b_map[] = | |
918 | { | |
919 | 1, 4, 8, 12, 16, 20, 24, -1 | |
920 | }; | |
921 | ||
922 | /* microMIPS imm type C. */ | |
923 | static const int micromips_imm_c_map[] = | |
924 | { | |
925 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
926 | }; | |
927 | ||
71400594 RS |
928 | /* Classifies the kind of instructions we're interested in when |
929 | implementing -mfix-vr4120. */ | |
c67a084a NC |
930 | enum fix_vr4120_class |
931 | { | |
71400594 RS |
932 | FIX_VR4120_MACC, |
933 | FIX_VR4120_DMACC, | |
934 | FIX_VR4120_MULT, | |
935 | FIX_VR4120_DMULT, | |
936 | FIX_VR4120_DIV, | |
937 | FIX_VR4120_MTHILO, | |
938 | NUM_FIX_VR4120_CLASSES | |
939 | }; | |
940 | ||
c67a084a NC |
941 | /* ...likewise -mfix-loongson2f-jump. */ |
942 | static bfd_boolean mips_fix_loongson2f_jump; | |
943 | ||
944 | /* ...likewise -mfix-loongson2f-nop. */ | |
945 | static bfd_boolean mips_fix_loongson2f_nop; | |
946 | ||
947 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
948 | static bfd_boolean mips_fix_loongson2f; | |
949 | ||
71400594 RS |
950 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
951 | there must be at least one other instruction between an instruction | |
952 | of type X and an instruction of type Y. */ | |
953 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
954 | ||
955 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 956 | static int mips_fix_vr4120; |
4a6a3df4 | 957 | |
7d8e00cf RS |
958 | /* ...likewise -mfix-vr4130. */ |
959 | static int mips_fix_vr4130; | |
960 | ||
6a32d874 CM |
961 | /* ...likewise -mfix-24k. */ |
962 | static int mips_fix_24k; | |
963 | ||
d954098f DD |
964 | /* ...likewise -mfix-cn63xxp1 */ |
965 | static bfd_boolean mips_fix_cn63xxp1; | |
966 | ||
4a6a3df4 AO |
967 | /* We don't relax branches by default, since this causes us to expand |
968 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
969 | fail to compute the offset before expanding the macro to the most | |
970 | efficient expansion. */ | |
971 | ||
972 | static int mips_relax_branch; | |
252b5132 | 973 | \f |
4d7206a2 RS |
974 | /* The expansion of many macros depends on the type of symbol that |
975 | they refer to. For example, when generating position-dependent code, | |
976 | a macro that refers to a symbol may have two different expansions, | |
977 | one which uses GP-relative addresses and one which uses absolute | |
978 | addresses. When generating SVR4-style PIC, a macro may have | |
979 | different expansions for local and global symbols. | |
980 | ||
981 | We handle these situations by generating both sequences and putting | |
982 | them in variant frags. In position-dependent code, the first sequence | |
983 | will be the GP-relative one and the second sequence will be the | |
984 | absolute one. In SVR4 PIC, the first sequence will be for global | |
985 | symbols and the second will be for local symbols. | |
986 | ||
584892a6 RS |
987 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
988 | SECOND are the lengths of the two sequences in bytes. These fields | |
989 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
990 | the subtype has the following flags: | |
4d7206a2 | 991 | |
584892a6 RS |
992 | RELAX_USE_SECOND |
993 | Set if it has been decided that we should use the second | |
994 | sequence instead of the first. | |
995 | ||
996 | RELAX_SECOND_LONGER | |
997 | Set in the first variant frag if the macro's second implementation | |
998 | is longer than its first. This refers to the macro as a whole, | |
999 | not an individual relaxation. | |
1000 | ||
1001 | RELAX_NOMACRO | |
1002 | Set in the first variant frag if the macro appeared in a .set nomacro | |
1003 | block and if one alternative requires a warning but the other does not. | |
1004 | ||
1005 | RELAX_DELAY_SLOT | |
1006 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
1007 | delay slot. | |
4d7206a2 | 1008 | |
df58fc94 RS |
1009 | RELAX_DELAY_SLOT_16BIT |
1010 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1011 | 16-bit instruction. | |
1012 | ||
1013 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1014 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1015 | the macro is of the wrong size for the branch delay slot. | |
1016 | ||
1017 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1018 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1019 | the macro is of the wrong size for the branch delay slot. | |
1020 | ||
4d7206a2 RS |
1021 | The frag's "opcode" points to the first fixup for relaxable code. |
1022 | ||
1023 | Relaxable macros are generated using a sequence such as: | |
1024 | ||
1025 | relax_start (SYMBOL); | |
1026 | ... generate first expansion ... | |
1027 | relax_switch (); | |
1028 | ... generate second expansion ... | |
1029 | relax_end (); | |
1030 | ||
1031 | The code and fixups for the unwanted alternative are discarded | |
1032 | by md_convert_frag. */ | |
584892a6 | 1033 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1034 | |
584892a6 RS |
1035 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1036 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1037 | #define RELAX_USE_SECOND 0x10000 | |
1038 | #define RELAX_SECOND_LONGER 0x20000 | |
1039 | #define RELAX_NOMACRO 0x40000 | |
1040 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1041 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1042 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1043 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1044 | |
4a6a3df4 AO |
1045 | /* Branch without likely bit. If label is out of range, we turn: |
1046 | ||
1047 | beq reg1, reg2, label | |
1048 | delay slot | |
1049 | ||
1050 | into | |
1051 | ||
1052 | bne reg1, reg2, 0f | |
1053 | nop | |
1054 | j label | |
1055 | 0: delay slot | |
1056 | ||
1057 | with the following opcode replacements: | |
1058 | ||
1059 | beq <-> bne | |
1060 | blez <-> bgtz | |
1061 | bltz <-> bgez | |
1062 | bc1f <-> bc1t | |
1063 | ||
1064 | bltzal <-> bgezal (with jal label instead of j label) | |
1065 | ||
1066 | Even though keeping the delay slot instruction in the delay slot of | |
1067 | the branch would be more efficient, it would be very tricky to do | |
1068 | correctly, because we'd have to introduce a variable frag *after* | |
1069 | the delay slot instruction, and expand that instead. Let's do it | |
1070 | the easy way for now, even if the branch-not-taken case now costs | |
1071 | one additional instruction. Out-of-range branches are not supposed | |
1072 | to be common, anyway. | |
1073 | ||
1074 | Branch likely. If label is out of range, we turn: | |
1075 | ||
1076 | beql reg1, reg2, label | |
1077 | delay slot (annulled if branch not taken) | |
1078 | ||
1079 | into | |
1080 | ||
1081 | beql reg1, reg2, 1f | |
1082 | nop | |
1083 | beql $0, $0, 2f | |
1084 | nop | |
1085 | 1: j[al] label | |
1086 | delay slot (executed only if branch taken) | |
1087 | 2: | |
1088 | ||
1089 | It would be possible to generate a shorter sequence by losing the | |
1090 | likely bit, generating something like: | |
b34976b6 | 1091 | |
4a6a3df4 AO |
1092 | bne reg1, reg2, 0f |
1093 | nop | |
1094 | j[al] label | |
1095 | delay slot (executed only if branch taken) | |
1096 | 0: | |
1097 | ||
1098 | beql -> bne | |
1099 | bnel -> beq | |
1100 | blezl -> bgtz | |
1101 | bgtzl -> blez | |
1102 | bltzl -> bgez | |
1103 | bgezl -> bltz | |
1104 | bc1fl -> bc1t | |
1105 | bc1tl -> bc1f | |
1106 | ||
1107 | bltzall -> bgezal (with jal label instead of j label) | |
1108 | bgezall -> bltzal (ditto) | |
1109 | ||
1110 | ||
1111 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1112 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1113 | ((relax_substateT) \ | |
1114 | (0xc0000000 \ | |
1115 | | ((at) & 0x1f) \ | |
1116 | | ((toofar) ? 0x20 : 0) \ | |
1117 | | ((link) ? 0x40 : 0) \ | |
1118 | | ((likely) ? 0x80 : 0) \ | |
1119 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1120 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1121 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1122 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1123 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1124 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1125 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1126 | |
252b5132 RH |
1127 | /* For mips16 code, we use an entirely different form of relaxation. |
1128 | mips16 supports two versions of most instructions which take | |
1129 | immediate values: a small one which takes some small value, and a | |
1130 | larger one which takes a 16 bit value. Since branches also follow | |
1131 | this pattern, relaxing these values is required. | |
1132 | ||
1133 | We can assemble both mips16 and normal MIPS code in a single | |
1134 | object. Therefore, we need to support this type of relaxation at | |
1135 | the same time that we support the relaxation described above. We | |
1136 | use the high bit of the subtype field to distinguish these cases. | |
1137 | ||
1138 | The information we store for this type of relaxation is the | |
1139 | argument code found in the opcode file for this relocation, whether | |
1140 | the user explicitly requested a small or extended form, and whether | |
1141 | the relocation is in a jump or jal delay slot. That tells us the | |
1142 | size of the value, and how it should be stored. We also store | |
1143 | whether the fragment is considered to be extended or not. We also | |
1144 | store whether this is known to be a branch to a different section, | |
1145 | whether we have tried to relax this frag yet, and whether we have | |
1146 | ever extended a PC relative fragment because of a shift count. */ | |
1147 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1148 | (0x80000000 \ | |
1149 | | ((type) & 0xff) \ | |
1150 | | ((small) ? 0x100 : 0) \ | |
1151 | | ((ext) ? 0x200 : 0) \ | |
1152 | | ((dslot) ? 0x400 : 0) \ | |
1153 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1154 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1155 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1156 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1157 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1158 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1159 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1160 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1161 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1162 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1163 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1164 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1165 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1166 | |
df58fc94 RS |
1167 | /* For microMIPS code, we use relaxation similar to one we use for |
1168 | MIPS16 code. Some instructions that take immediate values support | |
1169 | two encodings: a small one which takes some small value, and a | |
1170 | larger one which takes a 16 bit value. As some branches also follow | |
1171 | this pattern, relaxing these values is required. | |
1172 | ||
1173 | We can assemble both microMIPS and normal MIPS code in a single | |
1174 | object. Therefore, we need to support this type of relaxation at | |
1175 | the same time that we support the relaxation described above. We | |
1176 | use one of the high bits of the subtype field to distinguish these | |
1177 | cases. | |
1178 | ||
1179 | The information we store for this type of relaxation is the argument | |
1180 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1181 | selected as the assembler temporary, whether the branch is |
1182 | unconditional, whether it is compact, whether it stores the link | |
1183 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1184 | branches to a sequence of instructions is enabled, and whether the | |
1185 | displacement of a branch is too large to fit as an immediate argument | |
1186 | of a 16-bit and a 32-bit branch, respectively. */ | |
1187 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1188 | relax32, toofar16, toofar32) \ | |
1189 | (0x40000000 \ | |
1190 | | ((type) & 0xff) \ | |
1191 | | (((at) & 0x1f) << 8) \ | |
1192 | | ((uncond) ? 0x2000 : 0) \ | |
1193 | | ((compact) ? 0x4000 : 0) \ | |
1194 | | ((link) ? 0x8000 : 0) \ | |
1195 | | ((relax32) ? 0x10000 : 0) \ | |
1196 | | ((toofar16) ? 0x20000 : 0) \ | |
1197 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1198 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1199 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1200 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1201 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1202 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1203 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1204 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1205 | ||
1206 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1207 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1208 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1209 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1210 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1211 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1212 | |
43c0598f RS |
1213 | /* Sign-extend 16-bit value X. */ |
1214 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1215 | ||
885add95 CD |
1216 | /* Is the given value a sign-extended 32-bit value? */ |
1217 | #define IS_SEXT_32BIT_NUM(x) \ | |
1218 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1219 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1220 | ||
1221 | /* Is the given value a sign-extended 16-bit value? */ | |
1222 | #define IS_SEXT_16BIT_NUM(x) \ | |
1223 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1224 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1225 | ||
df58fc94 RS |
1226 | /* Is the given value a sign-extended 12-bit value? */ |
1227 | #define IS_SEXT_12BIT_NUM(x) \ | |
1228 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1229 | ||
7f3c4072 CM |
1230 | /* Is the given value a sign-extended 9-bit value? */ |
1231 | #define IS_SEXT_9BIT_NUM(x) \ | |
1232 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1233 | ||
2051e8c4 MR |
1234 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1235 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1236 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1237 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1238 | ||
bf12938e RS |
1239 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1240 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1241 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1242 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1243 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1244 | ||
1245 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1246 | SHIFT places. */ | |
1247 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1248 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1249 | ||
1250 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1251 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1252 | ||
1253 | include/opcode/mips.h specifies operand fields using the macros | |
1254 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1255 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1256 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1257 | do \ | |
1258 | if (!(MICROMIPS)) \ | |
1259 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1260 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1261 | else \ | |
1262 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1263 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1264 | while (0) | |
bf12938e RS |
1265 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1266 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1267 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1268 | ||
1269 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1270 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1271 | (!(MICROMIPS) \ | |
1272 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1273 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1274 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1275 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1276 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1277 | MIPS16OP_MASK_##FIELD, \ | |
1278 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1279 | |
1280 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1281 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1282 | \f |
df58fc94 RS |
1283 | /* Whether or not we are emitting a branch-likely macro. */ |
1284 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1285 | ||
4d7206a2 RS |
1286 | /* Global variables used when generating relaxable macros. See the |
1287 | comment above RELAX_ENCODE for more details about how relaxation | |
1288 | is used. */ | |
1289 | static struct { | |
1290 | /* 0 if we're not emitting a relaxable macro. | |
1291 | 1 if we're emitting the first of the two relaxation alternatives. | |
1292 | 2 if we're emitting the second alternative. */ | |
1293 | int sequence; | |
1294 | ||
1295 | /* The first relaxable fixup in the current frag. (In other words, | |
1296 | the first fixup that refers to relaxable code.) */ | |
1297 | fixS *first_fixup; | |
1298 | ||
1299 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1300 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1301 | unsigned int sizes[2]; | |
1302 | ||
1303 | /* The symbol on which the choice of sequence depends. */ | |
1304 | symbolS *symbol; | |
1305 | } mips_relax; | |
252b5132 | 1306 | \f |
584892a6 RS |
1307 | /* Global variables used to decide whether a macro needs a warning. */ |
1308 | static struct { | |
1309 | /* True if the macro is in a branch delay slot. */ | |
1310 | bfd_boolean delay_slot_p; | |
1311 | ||
df58fc94 RS |
1312 | /* Set to the length in bytes required if the macro is in a delay slot |
1313 | that requires a specific length of instruction, otherwise zero. */ | |
1314 | unsigned int delay_slot_length; | |
1315 | ||
584892a6 RS |
1316 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1317 | in bytes and sizes[1] is the length of the second alternative. | |
1318 | For non-relaxable macros, both elements give the length of the | |
1319 | macro in bytes. */ | |
1320 | unsigned int sizes[2]; | |
1321 | ||
df58fc94 RS |
1322 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1323 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1324 | is the length of the first instruction of the second alternative. | |
1325 | For non-relaxable macros, both elements give the length of the first | |
1326 | instruction in bytes. | |
1327 | ||
1328 | Set to zero if we haven't yet seen the first instruction. */ | |
1329 | unsigned int first_insn_sizes[2]; | |
1330 | ||
1331 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1332 | first alternative and insns[1] is the number of instructions for the | |
1333 | second alternative. | |
1334 | ||
1335 | For non-relaxable macros, both elements give the number of | |
1336 | instructions for the macro. */ | |
1337 | unsigned int insns[2]; | |
1338 | ||
584892a6 RS |
1339 | /* The first variant frag for this macro. */ |
1340 | fragS *first_frag; | |
1341 | } mips_macro_warning; | |
1342 | \f | |
252b5132 RH |
1343 | /* Prototypes for static functions. */ |
1344 | ||
252b5132 RH |
1345 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1346 | ||
b34976b6 | 1347 | static void append_insn |
df58fc94 RS |
1348 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1349 | bfd_boolean expansionp); | |
7d10b47d | 1350 | static void mips_no_prev_insn (void); |
c67a084a | 1351 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1352 | static void mips16_macro_build |
03ea81db | 1353 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1354 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1355 | static void macro_start (void); |
1356 | static void macro_end (void); | |
17a2f251 TS |
1357 | static void macro (struct mips_cl_insn * ip); |
1358 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1359 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1360 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1361 | static void mips16_immed |
43c0598f RS |
1362 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1363 | unsigned int, unsigned long *); | |
5e0116d5 | 1364 | static size_t my_getSmallExpression |
17a2f251 TS |
1365 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1366 | static void my_getExpression (expressionS *, char *); | |
1367 | static void s_align (int); | |
1368 | static void s_change_sec (int); | |
1369 | static void s_change_section (int); | |
1370 | static void s_cons (int); | |
1371 | static void s_float_cons (int); | |
1372 | static void s_mips_globl (int); | |
1373 | static void s_option (int); | |
1374 | static void s_mipsset (int); | |
1375 | static void s_abicalls (int); | |
1376 | static void s_cpload (int); | |
1377 | static void s_cpsetup (int); | |
1378 | static void s_cplocal (int); | |
1379 | static void s_cprestore (int); | |
1380 | static void s_cpreturn (int); | |
741d6ea8 JM |
1381 | static void s_dtprelword (int); |
1382 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1383 | static void s_tprelword (int); |
1384 | static void s_tpreldword (int); | |
17a2f251 TS |
1385 | static void s_gpvalue (int); |
1386 | static void s_gpword (int); | |
1387 | static void s_gpdword (int); | |
a3f278e2 | 1388 | static void s_ehword (int); |
17a2f251 TS |
1389 | static void s_cpadd (int); |
1390 | static void s_insn (int); | |
1391 | static void md_obj_begin (void); | |
1392 | static void md_obj_end (void); | |
1393 | static void s_mips_ent (int); | |
1394 | static void s_mips_end (int); | |
1395 | static void s_mips_frame (int); | |
1396 | static void s_mips_mask (int reg_type); | |
1397 | static void s_mips_stab (int); | |
1398 | static void s_mips_weakext (int); | |
1399 | static void s_mips_file (int); | |
1400 | static void s_mips_loc (int); | |
1401 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1402 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1403 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1404 | static int validate_micromips_insn (const struct mips_opcode *); |
1405 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1406 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1407 | |
1408 | /* Table and functions used to map between CPU/ISA names, and | |
1409 | ISA levels, and CPU numbers. */ | |
1410 | ||
e972090a NC |
1411 | struct mips_cpu_info |
1412 | { | |
e7af610e | 1413 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1414 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1415 | int isa; /* ISA level. */ |
1416 | int cpu; /* CPU number (default CPU if ISA). */ | |
1417 | }; | |
1418 | ||
ad3fea08 TS |
1419 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1420 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1421 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1422 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1423 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1424 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1425 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1426 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
b015e599 | 1427 | #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */ |
7f3c4072 | 1428 | #define MIPS_CPU_ASE_EVA 0x0200 /* CPU implements EVA ASE */ |
ad3fea08 | 1429 | |
17a2f251 TS |
1430 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1431 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1432 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1433 | \f |
1434 | /* Pseudo-op table. | |
1435 | ||
1436 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1437 | should be defined here, but are currently unsupported: .alias, | |
1438 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1439 | ||
1440 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1441 | specific to the type of debugging information being generated, and | |
1442 | should be defined by the object format: .aent, .begin, .bend, | |
1443 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1444 | .vreg. | |
1445 | ||
1446 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1447 | not MIPS CPU specific, but are also not specific to the object file | |
1448 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1449 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1450 | |
e972090a NC |
1451 | static const pseudo_typeS mips_pseudo_table[] = |
1452 | { | |
beae10d5 | 1453 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1454 | {"option", s_option, 0}, |
1455 | {"set", s_mipsset, 0}, | |
1456 | {"rdata", s_change_sec, 'r'}, | |
1457 | {"sdata", s_change_sec, 's'}, | |
1458 | {"livereg", s_ignore, 0}, | |
1459 | {"abicalls", s_abicalls, 0}, | |
1460 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1461 | {"cpsetup", s_cpsetup, 0}, |
1462 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1463 | {"cprestore", s_cprestore, 0}, |
6478892d | 1464 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1465 | {"dtprelword", s_dtprelword, 0}, |
1466 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1467 | {"tprelword", s_tprelword, 0}, |
1468 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1469 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1470 | {"gpword", s_gpword, 0}, |
10181a0d | 1471 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1472 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1473 | {"cpadd", s_cpadd, 0}, |
1474 | {"insn", s_insn, 0}, | |
1475 | ||
beae10d5 | 1476 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1477 | chips. */ |
38a57ae7 | 1478 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1479 | {"bss", s_change_sec, 'b'}, |
1480 | {"err", s_err, 0}, | |
1481 | {"half", s_cons, 1}, | |
1482 | {"dword", s_cons, 3}, | |
1483 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1484 | {"origin", s_org, 0}, |
1485 | {"repeat", s_rept, 0}, | |
252b5132 | 1486 | |
998b3c36 MR |
1487 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1488 | {"sbss", s_change_sec, 'B'}, | |
1489 | ||
beae10d5 | 1490 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1491 | here for one reason or another. */ |
1492 | {"align", s_align, 0}, | |
1493 | {"byte", s_cons, 0}, | |
1494 | {"data", s_change_sec, 'd'}, | |
1495 | {"double", s_float_cons, 'd'}, | |
1496 | {"float", s_float_cons, 'f'}, | |
1497 | {"globl", s_mips_globl, 0}, | |
1498 | {"global", s_mips_globl, 0}, | |
1499 | {"hword", s_cons, 1}, | |
1500 | {"int", s_cons, 2}, | |
1501 | {"long", s_cons, 2}, | |
1502 | {"octa", s_cons, 4}, | |
1503 | {"quad", s_cons, 3}, | |
cca86cc8 | 1504 | {"section", s_change_section, 0}, |
252b5132 RH |
1505 | {"short", s_cons, 1}, |
1506 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1507 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1508 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1509 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1510 | {"text", s_change_sec, 't'}, |
1511 | {"word", s_cons, 2}, | |
add56521 | 1512 | |
add56521 | 1513 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1514 | |
43841e91 | 1515 | { NULL, NULL, 0 }, |
252b5132 RH |
1516 | }; |
1517 | ||
e972090a NC |
1518 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1519 | { | |
beae10d5 KH |
1520 | /* These pseudo-ops should be defined by the object file format. |
1521 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1522 | {"aent", s_mips_ent, 1}, |
1523 | {"bgnb", s_ignore, 0}, | |
1524 | {"end", s_mips_end, 0}, | |
1525 | {"endb", s_ignore, 0}, | |
1526 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1527 | {"file", s_mips_file, 0}, |
252b5132 RH |
1528 | {"fmask", s_mips_mask, 'F'}, |
1529 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1530 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1531 | {"mask", s_mips_mask, 'R'}, |
1532 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1533 | { NULL, NULL, 0 }, |
252b5132 RH |
1534 | }; |
1535 | ||
3ae8dd8d MR |
1536 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1537 | purpose of the `.dc.a' internal pseudo-op. */ | |
1538 | ||
1539 | int | |
1540 | mips_address_bytes (void) | |
1541 | { | |
1542 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1543 | } | |
1544 | ||
17a2f251 | 1545 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1546 | |
1547 | void | |
17a2f251 | 1548 | mips_pop_insert (void) |
252b5132 RH |
1549 | { |
1550 | pop_insert (mips_pseudo_table); | |
1551 | if (! ECOFF_DEBUGGING) | |
1552 | pop_insert (mips_nonecoff_pseudo_table); | |
1553 | } | |
1554 | \f | |
1555 | /* Symbols labelling the current insn. */ | |
1556 | ||
e972090a NC |
1557 | struct insn_label_list |
1558 | { | |
252b5132 RH |
1559 | struct insn_label_list *next; |
1560 | symbolS *label; | |
1561 | }; | |
1562 | ||
252b5132 | 1563 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1564 | #define label_list tc_segment_info_data.labels |
252b5132 | 1565 | |
17a2f251 | 1566 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1567 | static void mips_mark_labels (void); |
1568 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1569 | |
1570 | static inline void | |
17a2f251 | 1571 | mips_clear_insn_labels (void) |
252b5132 RH |
1572 | { |
1573 | register struct insn_label_list **pl; | |
a8dbcb85 | 1574 | segment_info_type *si; |
252b5132 | 1575 | |
a8dbcb85 TS |
1576 | if (now_seg) |
1577 | { | |
1578 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1579 | ; | |
1580 | ||
1581 | si = seg_info (now_seg); | |
1582 | *pl = si->label_list; | |
1583 | si->label_list = NULL; | |
1584 | } | |
252b5132 | 1585 | } |
a8dbcb85 | 1586 | |
df58fc94 RS |
1587 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1588 | ||
1589 | static inline void | |
1590 | mips_mark_labels (void) | |
1591 | { | |
1592 | if (HAVE_CODE_COMPRESSION) | |
1593 | mips_compressed_mark_labels (); | |
1594 | } | |
252b5132 RH |
1595 | \f |
1596 | static char *expr_end; | |
1597 | ||
1598 | /* Expressions which appear in instructions. These are set by | |
1599 | mips_ip. */ | |
1600 | ||
1601 | static expressionS imm_expr; | |
5f74bc13 | 1602 | static expressionS imm2_expr; |
252b5132 RH |
1603 | static expressionS offset_expr; |
1604 | ||
1605 | /* Relocs associated with imm_expr and offset_expr. */ | |
1606 | ||
f6688943 TS |
1607 | static bfd_reloc_code_real_type imm_reloc[3] |
1608 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1609 | static bfd_reloc_code_real_type offset_reloc[3] | |
1610 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1611 | |
df58fc94 RS |
1612 | /* This is set to the resulting size of the instruction to be produced |
1613 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1614 | explicit size is supplied. */ | |
252b5132 | 1615 | |
df58fc94 | 1616 | static unsigned int forced_insn_length; |
252b5132 | 1617 | |
e1b47bd5 RS |
1618 | /* True if we are assembling an instruction. All dot symbols defined during |
1619 | this time should be treated as code labels. */ | |
1620 | ||
1621 | static bfd_boolean mips_assembling_insn; | |
1622 | ||
7ed4a06a | 1623 | #ifdef OBJ_ELF |
ecb4347a DJ |
1624 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1625 | ECOFF debugging. */ | |
252b5132 RH |
1626 | |
1627 | static segT pdr_seg; | |
7ed4a06a | 1628 | #endif |
252b5132 | 1629 | |
e013f690 TS |
1630 | /* The default target format to use. */ |
1631 | ||
aeffff67 RS |
1632 | #if defined (TE_FreeBSD) |
1633 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1634 | #elif defined (TE_TMIPS) | |
1635 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1636 | #else | |
1637 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1638 | #endif | |
1639 | ||
e013f690 | 1640 | const char * |
17a2f251 | 1641 | mips_target_format (void) |
e013f690 TS |
1642 | { |
1643 | switch (OUTPUT_FLAVOR) | |
1644 | { | |
e013f690 TS |
1645 | case bfd_target_ecoff_flavour: |
1646 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1647 | case bfd_target_coff_flavour: | |
1648 | return "pe-mips"; | |
1649 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1650 | #ifdef TE_VXWORKS |
1651 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1652 | return (target_big_endian | |
1653 | ? "elf32-bigmips-vxworks" | |
1654 | : "elf32-littlemips-vxworks"); | |
1655 | #endif | |
e013f690 | 1656 | return (target_big_endian |
cfe86eaa | 1657 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1658 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1659 | : (HAVE_NEWABI |
aeffff67 RS |
1660 | ? ELF_TARGET ("elf32-n", "big") |
1661 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1662 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1663 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1664 | : (HAVE_NEWABI |
aeffff67 RS |
1665 | ? ELF_TARGET ("elf32-n", "little") |
1666 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1667 | default: |
1668 | abort (); | |
1669 | return NULL; | |
1670 | } | |
1671 | } | |
1672 | ||
df58fc94 RS |
1673 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1674 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1675 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1676 | major opcode) will require further modifications to the opcode | |
1677 | table. */ | |
1678 | ||
1679 | static inline unsigned int | |
1680 | micromips_insn_length (const struct mips_opcode *mo) | |
1681 | { | |
1682 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1683 | } | |
1684 | ||
5c04167a RS |
1685 | /* Return the length of MIPS16 instruction OPCODE. */ |
1686 | ||
1687 | static inline unsigned int | |
1688 | mips16_opcode_length (unsigned long opcode) | |
1689 | { | |
1690 | return (opcode >> 16) == 0 ? 2 : 4; | |
1691 | } | |
1692 | ||
1e915849 RS |
1693 | /* Return the length of instruction INSN. */ |
1694 | ||
1695 | static inline unsigned int | |
1696 | insn_length (const struct mips_cl_insn *insn) | |
1697 | { | |
df58fc94 RS |
1698 | if (mips_opts.micromips) |
1699 | return micromips_insn_length (insn->insn_mo); | |
1700 | else if (mips_opts.mips16) | |
5c04167a | 1701 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1702 | else |
1e915849 | 1703 | return 4; |
1e915849 RS |
1704 | } |
1705 | ||
1706 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1707 | ||
1708 | static void | |
1709 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1710 | { | |
1711 | size_t i; | |
1712 | ||
1713 | insn->insn_mo = mo; | |
1e915849 RS |
1714 | insn->insn_opcode = mo->match; |
1715 | insn->frag = NULL; | |
1716 | insn->where = 0; | |
1717 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1718 | insn->fixp[i] = NULL; | |
1719 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1720 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1721 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1722 | insn->complete_p = 0; |
e407c74b | 1723 | insn->cleared_p = 0; |
1e915849 RS |
1724 | } |
1725 | ||
df58fc94 | 1726 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1727 | |
1728 | static void | |
df58fc94 | 1729 | mips_record_compressed_mode (void) |
742a56fe RS |
1730 | { |
1731 | segment_info_type *si; | |
1732 | ||
1733 | si = seg_info (now_seg); | |
1734 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1735 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1736 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1737 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1738 | } |
1739 | ||
4d68580a RS |
1740 | /* Read a standard MIPS instruction from BUF. */ |
1741 | ||
1742 | static unsigned long | |
1743 | read_insn (char *buf) | |
1744 | { | |
1745 | if (target_big_endian) | |
1746 | return bfd_getb32 ((bfd_byte *) buf); | |
1747 | else | |
1748 | return bfd_getl32 ((bfd_byte *) buf); | |
1749 | } | |
1750 | ||
1751 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1752 | the next byte. */ | |
1753 | ||
1754 | static char * | |
1755 | write_insn (char *buf, unsigned int insn) | |
1756 | { | |
1757 | md_number_to_chars (buf, insn, 4); | |
1758 | return buf + 4; | |
1759 | } | |
1760 | ||
1761 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1762 | has length LENGTH. */ | |
1763 | ||
1764 | static unsigned long | |
1765 | read_compressed_insn (char *buf, unsigned int length) | |
1766 | { | |
1767 | unsigned long insn; | |
1768 | unsigned int i; | |
1769 | ||
1770 | insn = 0; | |
1771 | for (i = 0; i < length; i += 2) | |
1772 | { | |
1773 | insn <<= 16; | |
1774 | if (target_big_endian) | |
1775 | insn |= bfd_getb16 ((char *) buf); | |
1776 | else | |
1777 | insn |= bfd_getl16 ((char *) buf); | |
1778 | buf += 2; | |
1779 | } | |
1780 | return insn; | |
1781 | } | |
1782 | ||
5c04167a RS |
1783 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1784 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1785 | ||
1786 | static char * | |
1787 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1788 | { | |
1789 | unsigned int i; | |
1790 | ||
1791 | for (i = 0; i < length; i += 2) | |
1792 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1793 | return buf + length; | |
1794 | } | |
1795 | ||
1e915849 RS |
1796 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1797 | ||
1798 | static void | |
1799 | install_insn (const struct mips_cl_insn *insn) | |
1800 | { | |
1801 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1802 | if (HAVE_CODE_COMPRESSION) |
1803 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1804 | else |
4d68580a | 1805 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1806 | mips_record_compressed_mode (); |
1e915849 RS |
1807 | } |
1808 | ||
1809 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1810 | and install the opcode in the new location. */ | |
1811 | ||
1812 | static void | |
1813 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1814 | { | |
1815 | size_t i; | |
1816 | ||
1817 | insn->frag = frag; | |
1818 | insn->where = where; | |
1819 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1820 | if (insn->fixp[i] != NULL) | |
1821 | { | |
1822 | insn->fixp[i]->fx_frag = frag; | |
1823 | insn->fixp[i]->fx_where = where; | |
1824 | } | |
1825 | install_insn (insn); | |
1826 | } | |
1827 | ||
1828 | /* Add INSN to the end of the output. */ | |
1829 | ||
1830 | static void | |
1831 | add_fixed_insn (struct mips_cl_insn *insn) | |
1832 | { | |
1833 | char *f = frag_more (insn_length (insn)); | |
1834 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1835 | } | |
1836 | ||
1837 | /* Start a variant frag and move INSN to the start of the variant part, | |
1838 | marking it as fixed. The other arguments are as for frag_var. */ | |
1839 | ||
1840 | static void | |
1841 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1842 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1843 | { | |
1844 | frag_grow (max_chars); | |
1845 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1846 | insn->fixed_p = 1; | |
1847 | frag_var (rs_machine_dependent, max_chars, var, | |
1848 | subtype, symbol, offset, NULL); | |
1849 | } | |
1850 | ||
1851 | /* Insert N copies of INSN into the history buffer, starting at | |
1852 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1853 | ||
1854 | static void | |
1855 | insert_into_history (unsigned int first, unsigned int n, | |
1856 | const struct mips_cl_insn *insn) | |
1857 | { | |
1858 | if (mips_relax.sequence != 2) | |
1859 | { | |
1860 | unsigned int i; | |
1861 | ||
1862 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1863 | if (i >= first + n) | |
1864 | history[i] = history[i - n]; | |
1865 | else | |
1866 | history[i] = *insn; | |
1867 | } | |
1868 | } | |
1869 | ||
71400594 RS |
1870 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1871 | the idea is to make it obvious at a glance that each errata is | |
1872 | included. */ | |
1873 | ||
1874 | static void | |
1875 | init_vr4120_conflicts (void) | |
1876 | { | |
1877 | #define CONFLICT(FIRST, SECOND) \ | |
1878 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1879 | ||
1880 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1881 | CONFLICT (MACC, DIV); | |
1882 | CONFLICT (DMACC, DIV); | |
1883 | ||
1884 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1885 | CONFLICT (DMULT, DMULT); | |
1886 | CONFLICT (DMULT, DMACC); | |
1887 | CONFLICT (DMACC, DMULT); | |
1888 | CONFLICT (DMACC, DMACC); | |
1889 | ||
1890 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1891 | CONFLICT (MACC, MTHILO); | |
1892 | CONFLICT (DMACC, MTHILO); | |
1893 | ||
1894 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1895 | instruction is executed immediately after a MACC or DMACC | |
1896 | instruction, the result of [either instruction] is incorrect." */ | |
1897 | CONFLICT (MACC, MULT); | |
1898 | CONFLICT (MACC, DMULT); | |
1899 | CONFLICT (DMACC, MULT); | |
1900 | CONFLICT (DMACC, DMULT); | |
1901 | ||
1902 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1903 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1904 | DDIV or DDIVU instruction, the result of the MACC or | |
1905 | DMACC instruction is incorrect.". */ | |
1906 | CONFLICT (DMULT, MACC); | |
1907 | CONFLICT (DMULT, DMACC); | |
1908 | CONFLICT (DIV, MACC); | |
1909 | CONFLICT (DIV, DMACC); | |
1910 | ||
1911 | #undef CONFLICT | |
1912 | } | |
1913 | ||
707bfff6 TS |
1914 | struct regname { |
1915 | const char *name; | |
1916 | unsigned int num; | |
1917 | }; | |
1918 | ||
1919 | #define RTYPE_MASK 0x1ff00 | |
1920 | #define RTYPE_NUM 0x00100 | |
1921 | #define RTYPE_FPU 0x00200 | |
1922 | #define RTYPE_FCC 0x00400 | |
1923 | #define RTYPE_VEC 0x00800 | |
1924 | #define RTYPE_GP 0x01000 | |
1925 | #define RTYPE_CP0 0x02000 | |
1926 | #define RTYPE_PC 0x04000 | |
1927 | #define RTYPE_ACC 0x08000 | |
1928 | #define RTYPE_CCC 0x10000 | |
1929 | #define RNUM_MASK 0x000ff | |
1930 | #define RWARN 0x80000 | |
1931 | ||
1932 | #define GENERIC_REGISTER_NUMBERS \ | |
1933 | {"$0", RTYPE_NUM | 0}, \ | |
1934 | {"$1", RTYPE_NUM | 1}, \ | |
1935 | {"$2", RTYPE_NUM | 2}, \ | |
1936 | {"$3", RTYPE_NUM | 3}, \ | |
1937 | {"$4", RTYPE_NUM | 4}, \ | |
1938 | {"$5", RTYPE_NUM | 5}, \ | |
1939 | {"$6", RTYPE_NUM | 6}, \ | |
1940 | {"$7", RTYPE_NUM | 7}, \ | |
1941 | {"$8", RTYPE_NUM | 8}, \ | |
1942 | {"$9", RTYPE_NUM | 9}, \ | |
1943 | {"$10", RTYPE_NUM | 10}, \ | |
1944 | {"$11", RTYPE_NUM | 11}, \ | |
1945 | {"$12", RTYPE_NUM | 12}, \ | |
1946 | {"$13", RTYPE_NUM | 13}, \ | |
1947 | {"$14", RTYPE_NUM | 14}, \ | |
1948 | {"$15", RTYPE_NUM | 15}, \ | |
1949 | {"$16", RTYPE_NUM | 16}, \ | |
1950 | {"$17", RTYPE_NUM | 17}, \ | |
1951 | {"$18", RTYPE_NUM | 18}, \ | |
1952 | {"$19", RTYPE_NUM | 19}, \ | |
1953 | {"$20", RTYPE_NUM | 20}, \ | |
1954 | {"$21", RTYPE_NUM | 21}, \ | |
1955 | {"$22", RTYPE_NUM | 22}, \ | |
1956 | {"$23", RTYPE_NUM | 23}, \ | |
1957 | {"$24", RTYPE_NUM | 24}, \ | |
1958 | {"$25", RTYPE_NUM | 25}, \ | |
1959 | {"$26", RTYPE_NUM | 26}, \ | |
1960 | {"$27", RTYPE_NUM | 27}, \ | |
1961 | {"$28", RTYPE_NUM | 28}, \ | |
1962 | {"$29", RTYPE_NUM | 29}, \ | |
1963 | {"$30", RTYPE_NUM | 30}, \ | |
1964 | {"$31", RTYPE_NUM | 31} | |
1965 | ||
1966 | #define FPU_REGISTER_NAMES \ | |
1967 | {"$f0", RTYPE_FPU | 0}, \ | |
1968 | {"$f1", RTYPE_FPU | 1}, \ | |
1969 | {"$f2", RTYPE_FPU | 2}, \ | |
1970 | {"$f3", RTYPE_FPU | 3}, \ | |
1971 | {"$f4", RTYPE_FPU | 4}, \ | |
1972 | {"$f5", RTYPE_FPU | 5}, \ | |
1973 | {"$f6", RTYPE_FPU | 6}, \ | |
1974 | {"$f7", RTYPE_FPU | 7}, \ | |
1975 | {"$f8", RTYPE_FPU | 8}, \ | |
1976 | {"$f9", RTYPE_FPU | 9}, \ | |
1977 | {"$f10", RTYPE_FPU | 10}, \ | |
1978 | {"$f11", RTYPE_FPU | 11}, \ | |
1979 | {"$f12", RTYPE_FPU | 12}, \ | |
1980 | {"$f13", RTYPE_FPU | 13}, \ | |
1981 | {"$f14", RTYPE_FPU | 14}, \ | |
1982 | {"$f15", RTYPE_FPU | 15}, \ | |
1983 | {"$f16", RTYPE_FPU | 16}, \ | |
1984 | {"$f17", RTYPE_FPU | 17}, \ | |
1985 | {"$f18", RTYPE_FPU | 18}, \ | |
1986 | {"$f19", RTYPE_FPU | 19}, \ | |
1987 | {"$f20", RTYPE_FPU | 20}, \ | |
1988 | {"$f21", RTYPE_FPU | 21}, \ | |
1989 | {"$f22", RTYPE_FPU | 22}, \ | |
1990 | {"$f23", RTYPE_FPU | 23}, \ | |
1991 | {"$f24", RTYPE_FPU | 24}, \ | |
1992 | {"$f25", RTYPE_FPU | 25}, \ | |
1993 | {"$f26", RTYPE_FPU | 26}, \ | |
1994 | {"$f27", RTYPE_FPU | 27}, \ | |
1995 | {"$f28", RTYPE_FPU | 28}, \ | |
1996 | {"$f29", RTYPE_FPU | 29}, \ | |
1997 | {"$f30", RTYPE_FPU | 30}, \ | |
1998 | {"$f31", RTYPE_FPU | 31} | |
1999 | ||
2000 | #define FPU_CONDITION_CODE_NAMES \ | |
2001 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2002 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2003 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2004 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2005 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2006 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2007 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2008 | {"$fcc7", RTYPE_FCC | 7} | |
2009 | ||
2010 | #define COPROC_CONDITION_CODE_NAMES \ | |
2011 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2012 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2013 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2014 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2015 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2016 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2017 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2018 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2019 | ||
2020 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2021 | {"$a4", RTYPE_GP | 8}, \ | |
2022 | {"$a5", RTYPE_GP | 9}, \ | |
2023 | {"$a6", RTYPE_GP | 10}, \ | |
2024 | {"$a7", RTYPE_GP | 11}, \ | |
2025 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2026 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2027 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2028 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2029 | {"$t0", RTYPE_GP | 12}, \ | |
2030 | {"$t1", RTYPE_GP | 13}, \ | |
2031 | {"$t2", RTYPE_GP | 14}, \ | |
2032 | {"$t3", RTYPE_GP | 15} | |
2033 | ||
2034 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2035 | {"$t0", RTYPE_GP | 8}, \ | |
2036 | {"$t1", RTYPE_GP | 9}, \ | |
2037 | {"$t2", RTYPE_GP | 10}, \ | |
2038 | {"$t3", RTYPE_GP | 11}, \ | |
2039 | {"$t4", RTYPE_GP | 12}, \ | |
2040 | {"$t5", RTYPE_GP | 13}, \ | |
2041 | {"$t6", RTYPE_GP | 14}, \ | |
2042 | {"$t7", RTYPE_GP | 15}, \ | |
2043 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2044 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2045 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2046 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2047 | ||
2048 | /* Remaining symbolic register names */ | |
2049 | #define SYMBOLIC_REGISTER_NAMES \ | |
2050 | {"$zero", RTYPE_GP | 0}, \ | |
2051 | {"$at", RTYPE_GP | 1}, \ | |
2052 | {"$AT", RTYPE_GP | 1}, \ | |
2053 | {"$v0", RTYPE_GP | 2}, \ | |
2054 | {"$v1", RTYPE_GP | 3}, \ | |
2055 | {"$a0", RTYPE_GP | 4}, \ | |
2056 | {"$a1", RTYPE_GP | 5}, \ | |
2057 | {"$a2", RTYPE_GP | 6}, \ | |
2058 | {"$a3", RTYPE_GP | 7}, \ | |
2059 | {"$s0", RTYPE_GP | 16}, \ | |
2060 | {"$s1", RTYPE_GP | 17}, \ | |
2061 | {"$s2", RTYPE_GP | 18}, \ | |
2062 | {"$s3", RTYPE_GP | 19}, \ | |
2063 | {"$s4", RTYPE_GP | 20}, \ | |
2064 | {"$s5", RTYPE_GP | 21}, \ | |
2065 | {"$s6", RTYPE_GP | 22}, \ | |
2066 | {"$s7", RTYPE_GP | 23}, \ | |
2067 | {"$t8", RTYPE_GP | 24}, \ | |
2068 | {"$t9", RTYPE_GP | 25}, \ | |
2069 | {"$k0", RTYPE_GP | 26}, \ | |
2070 | {"$kt0", RTYPE_GP | 26}, \ | |
2071 | {"$k1", RTYPE_GP | 27}, \ | |
2072 | {"$kt1", RTYPE_GP | 27}, \ | |
2073 | {"$gp", RTYPE_GP | 28}, \ | |
2074 | {"$sp", RTYPE_GP | 29}, \ | |
2075 | {"$s8", RTYPE_GP | 30}, \ | |
2076 | {"$fp", RTYPE_GP | 30}, \ | |
2077 | {"$ra", RTYPE_GP | 31} | |
2078 | ||
2079 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2080 | {"$pc", RTYPE_PC | 0} | |
2081 | ||
2082 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2083 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2084 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2085 | {"$v2", RTYPE_VEC | 2}, \ | |
2086 | {"$v3", RTYPE_VEC | 3}, \ | |
2087 | {"$v4", RTYPE_VEC | 4}, \ | |
2088 | {"$v5", RTYPE_VEC | 5}, \ | |
2089 | {"$v6", RTYPE_VEC | 6}, \ | |
2090 | {"$v7", RTYPE_VEC | 7}, \ | |
2091 | {"$v8", RTYPE_VEC | 8}, \ | |
2092 | {"$v9", RTYPE_VEC | 9}, \ | |
2093 | {"$v10", RTYPE_VEC | 10}, \ | |
2094 | {"$v11", RTYPE_VEC | 11}, \ | |
2095 | {"$v12", RTYPE_VEC | 12}, \ | |
2096 | {"$v13", RTYPE_VEC | 13}, \ | |
2097 | {"$v14", RTYPE_VEC | 14}, \ | |
2098 | {"$v15", RTYPE_VEC | 15}, \ | |
2099 | {"$v16", RTYPE_VEC | 16}, \ | |
2100 | {"$v17", RTYPE_VEC | 17}, \ | |
2101 | {"$v18", RTYPE_VEC | 18}, \ | |
2102 | {"$v19", RTYPE_VEC | 19}, \ | |
2103 | {"$v20", RTYPE_VEC | 20}, \ | |
2104 | {"$v21", RTYPE_VEC | 21}, \ | |
2105 | {"$v22", RTYPE_VEC | 22}, \ | |
2106 | {"$v23", RTYPE_VEC | 23}, \ | |
2107 | {"$v24", RTYPE_VEC | 24}, \ | |
2108 | {"$v25", RTYPE_VEC | 25}, \ | |
2109 | {"$v26", RTYPE_VEC | 26}, \ | |
2110 | {"$v27", RTYPE_VEC | 27}, \ | |
2111 | {"$v28", RTYPE_VEC | 28}, \ | |
2112 | {"$v29", RTYPE_VEC | 29}, \ | |
2113 | {"$v30", RTYPE_VEC | 30}, \ | |
2114 | {"$v31", RTYPE_VEC | 31} | |
2115 | ||
2116 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2117 | {"$ac0", RTYPE_ACC | 0}, \ | |
2118 | {"$ac1", RTYPE_ACC | 1}, \ | |
2119 | {"$ac2", RTYPE_ACC | 2}, \ | |
2120 | {"$ac3", RTYPE_ACC | 3} | |
2121 | ||
2122 | static const struct regname reg_names[] = { | |
2123 | GENERIC_REGISTER_NUMBERS, | |
2124 | FPU_REGISTER_NAMES, | |
2125 | FPU_CONDITION_CODE_NAMES, | |
2126 | COPROC_CONDITION_CODE_NAMES, | |
2127 | ||
2128 | /* The $txx registers depends on the abi, | |
2129 | these will be added later into the symbol table from | |
2130 | one of the tables below once mips_abi is set after | |
2131 | parsing of arguments from the command line. */ | |
2132 | SYMBOLIC_REGISTER_NAMES, | |
2133 | ||
2134 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2135 | MDMX_VECTOR_REGISTER_NAMES, | |
2136 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2137 | {0, 0} | |
2138 | }; | |
2139 | ||
2140 | static const struct regname reg_names_o32[] = { | |
2141 | O32_SYMBOLIC_REGISTER_NAMES, | |
2142 | {0, 0} | |
2143 | }; | |
2144 | ||
2145 | static const struct regname reg_names_n32n64[] = { | |
2146 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2147 | {0, 0} | |
2148 | }; | |
2149 | ||
df58fc94 RS |
2150 | /* Check if S points at a valid register specifier according to TYPES. |
2151 | If so, then return 1, advance S to consume the specifier and store | |
2152 | the register's number in REGNOP, otherwise return 0. */ | |
2153 | ||
707bfff6 TS |
2154 | static int |
2155 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2156 | { | |
2157 | symbolS *symbolP; | |
2158 | char *e; | |
2159 | char save_c; | |
2160 | int reg = -1; | |
2161 | ||
2162 | /* Find end of name. */ | |
2163 | e = *s; | |
2164 | if (is_name_beginner (*e)) | |
2165 | ++e; | |
2166 | while (is_part_of_name (*e)) | |
2167 | ++e; | |
2168 | ||
2169 | /* Terminate name. */ | |
2170 | save_c = *e; | |
2171 | *e = '\0'; | |
2172 | ||
2173 | /* Look for a register symbol. */ | |
2174 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2175 | { | |
2176 | int r = S_GET_VALUE (symbolP); | |
2177 | if (r & types) | |
2178 | reg = r & RNUM_MASK; | |
2179 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2180 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2181 | reg = (r & RNUM_MASK) - 2; | |
2182 | } | |
2183 | /* Else see if this is a register defined in an itbl entry. */ | |
2184 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2185 | { | |
2186 | char *n = *s; | |
2187 | unsigned long r; | |
2188 | ||
2189 | if (*n == '$') | |
2190 | ++n; | |
2191 | if (itbl_get_reg_val (n, &r)) | |
2192 | reg = r & RNUM_MASK; | |
2193 | } | |
2194 | ||
2195 | /* Advance to next token if a register was recognised. */ | |
2196 | if (reg >= 0) | |
2197 | *s = e; | |
2198 | else if (types & RWARN) | |
20203fb9 | 2199 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2200 | |
2201 | *e = save_c; | |
2202 | if (regnop) | |
2203 | *regnop = reg; | |
2204 | return reg >= 0; | |
2205 | } | |
2206 | ||
df58fc94 RS |
2207 | /* Check if S points at a valid register list according to TYPES. |
2208 | If so, then return 1, advance S to consume the list and store | |
2209 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2210 | otherwise return 0. A valid list comprises a comma-separated | |
2211 | enumeration of valid single registers and/or dash-separated | |
2212 | contiguous register ranges as determined by their numbers. | |
2213 | ||
2214 | As a special exception if one of s0-s7 registers is specified as | |
2215 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2216 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2217 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2218 | |
2219 | static int | |
2220 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2221 | { | |
2222 | unsigned int reglist = 0; | |
2223 | unsigned int lastregno; | |
2224 | bfd_boolean ok = TRUE; | |
2225 | unsigned int regmask; | |
2309ddf2 | 2226 | char *s_endlist = *s; |
df58fc94 | 2227 | char *s_reset = *s; |
2309ddf2 | 2228 | unsigned int regno; |
df58fc94 RS |
2229 | |
2230 | while (reg_lookup (s, types, ®no)) | |
2231 | { | |
2232 | lastregno = regno; | |
2233 | if (**s == '-') | |
2234 | { | |
2235 | (*s)++; | |
2236 | ok = reg_lookup (s, types, &lastregno); | |
2237 | if (ok && lastregno < regno) | |
2238 | ok = FALSE; | |
2239 | if (!ok) | |
2240 | break; | |
2241 | } | |
2242 | ||
2243 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2244 | { | |
2245 | lastregno = S7; | |
2246 | reglist |= 1 << FP; | |
2247 | } | |
2248 | regmask = 1 << lastregno; | |
2249 | regmask = (regmask << 1) - 1; | |
2250 | regmask ^= (1 << regno) - 1; | |
2251 | reglist |= regmask; | |
2252 | ||
2309ddf2 | 2253 | s_endlist = *s; |
df58fc94 RS |
2254 | if (**s != ',') |
2255 | break; | |
2256 | (*s)++; | |
2257 | } | |
2258 | ||
2259 | if (ok) | |
2309ddf2 | 2260 | *s = s_endlist; |
df58fc94 RS |
2261 | else |
2262 | *s = s_reset; | |
2263 | if (reglistp) | |
2264 | *reglistp = reglist; | |
2265 | return ok && reglist != 0; | |
2266 | } | |
2267 | ||
d301a56b RS |
2268 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2269 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2270 | |
2271 | static bfd_boolean | |
f79e2745 | 2272 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2273 | { |
2274 | int isa = mips_opts.isa; | |
d301a56b | 2275 | int ase = 0; |
037b32b9 AN |
2276 | int fp_s, fp_d; |
2277 | ||
2278 | if (mips_opts.ase_mdmx) | |
d301a56b | 2279 | ase |= ASE_MDMX; |
037b32b9 | 2280 | if (mips_opts.ase_dsp) |
d301a56b | 2281 | ase |= ASE_DSP; |
037b32b9 | 2282 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
d301a56b | 2283 | ase |= ASE_DSP64; |
037b32b9 | 2284 | if (mips_opts.ase_dspr2) |
d301a56b | 2285 | ase |= ASE_DSPR2; |
7f3c4072 CM |
2286 | if (mips_opts.ase_eva) |
2287 | ase |= ASE_EVA; | |
037b32b9 | 2288 | if (mips_opts.ase_mt) |
d301a56b | 2289 | ase |= ASE_MT; |
037b32b9 | 2290 | if (mips_opts.ase_mips3d) |
d301a56b | 2291 | ase |= ASE_MIPS3D; |
037b32b9 | 2292 | if (mips_opts.ase_smartmips) |
d301a56b | 2293 | ase |= ASE_SMARTMIPS; |
dec0624d | 2294 | if (mips_opts.ase_mcu) |
d301a56b | 2295 | ase |= ASE_MCU; |
b015e599 | 2296 | if (mips_opts.ase_virt) |
d301a56b | 2297 | ase |= ASE_VIRT; |
b015e599 | 2298 | if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE) |
d301a56b | 2299 | ase |= ASE_VIRT64; |
037b32b9 | 2300 | |
d301a56b | 2301 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2302 | return FALSE; |
2303 | ||
2304 | /* Check whether the instruction or macro requires single-precision or | |
2305 | double-precision floating-point support. Note that this information is | |
2306 | stored differently in the opcode table for insns and macros. */ | |
2307 | if (mo->pinfo == INSN_MACRO) | |
2308 | { | |
2309 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2310 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2311 | } | |
2312 | else | |
2313 | { | |
2314 | fp_s = mo->pinfo & FP_S; | |
2315 | fp_d = mo->pinfo & FP_D; | |
2316 | } | |
2317 | ||
2318 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2319 | return FALSE; | |
2320 | ||
2321 | if (fp_s && mips_opts.soft_float) | |
2322 | return FALSE; | |
2323 | ||
2324 | return TRUE; | |
2325 | } | |
2326 | ||
2327 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2328 | selected ISA and architecture. */ | |
2329 | ||
2330 | static bfd_boolean | |
2331 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2332 | { | |
d301a56b | 2333 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2334 | } |
2335 | ||
df58fc94 RS |
2336 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2337 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2338 | ||
2339 | static bfd_boolean | |
2340 | is_size_valid (const struct mips_opcode *mo) | |
2341 | { | |
2342 | if (!mips_opts.micromips) | |
2343 | return TRUE; | |
2344 | ||
2345 | if (!forced_insn_length) | |
2346 | return TRUE; | |
2347 | if (mo->pinfo == INSN_MACRO) | |
2348 | return FALSE; | |
2349 | return forced_insn_length == micromips_insn_length (mo); | |
2350 | } | |
2351 | ||
2352 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2353 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2354 | ||
2355 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2356 | a macro expansion fails because it relies on a preceding 32-bit real | |
2357 | instruction to have matched and does not handle the operands correctly. | |
2358 | The only macros that may expand to 16-bit instructions are JAL that | |
2359 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2360 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2361 | a NOP. In all these cases the macros precede any corresponding real | |
2362 | instruction definitions in the opcode table, so they will match in the | |
2363 | second pass where the size of the delay slot is ignored and therefore | |
2364 | produce correct code. */ | |
df58fc94 RS |
2365 | |
2366 | static bfd_boolean | |
2367 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2368 | { | |
2369 | if (!mips_opts.micromips) | |
2370 | return TRUE; | |
2371 | ||
2372 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2373 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2374 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2375 | && micromips_insn_length (mo) != 4) | |
2376 | return FALSE; | |
2377 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2378 | && micromips_insn_length (mo) != 2) | |
2379 | return FALSE; | |
2380 | ||
2381 | return TRUE; | |
2382 | } | |
2383 | ||
707bfff6 TS |
2384 | /* This function is called once, at assembler startup time. It should set up |
2385 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2386 | |
252b5132 | 2387 | void |
17a2f251 | 2388 | md_begin (void) |
252b5132 | 2389 | { |
3994f87e | 2390 | const char *retval = NULL; |
156c2f8b | 2391 | int i = 0; |
252b5132 | 2392 | int broken = 0; |
1f25f5d3 | 2393 | |
0a44bf69 RS |
2394 | if (mips_pic != NO_PIC) |
2395 | { | |
2396 | if (g_switch_seen && g_switch_value != 0) | |
2397 | as_bad (_("-G may not be used in position-independent code")); | |
2398 | g_switch_value = 0; | |
2399 | } | |
2400 | ||
fef14a42 | 2401 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2402 | as_warn (_("Could not set architecture and machine")); |
2403 | ||
252b5132 RH |
2404 | op_hash = hash_new (); |
2405 | ||
2406 | for (i = 0; i < NUMOPCODES;) | |
2407 | { | |
2408 | const char *name = mips_opcodes[i].name; | |
2409 | ||
17a2f251 | 2410 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2411 | if (retval != NULL) |
2412 | { | |
2413 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2414 | mips_opcodes[i].name, retval); | |
2415 | /* Probably a memory allocation problem? Give up now. */ | |
2416 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2417 | } | |
2418 | do | |
2419 | { | |
2420 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2421 | { | |
2422 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2423 | broken = 1; | |
1e915849 RS |
2424 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2425 | { | |
2426 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2427 | if (mips_fix_loongson2f_nop) |
2428 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2429 | nop_insn.fixed_p = 1; |
2430 | } | |
252b5132 RH |
2431 | } |
2432 | ++i; | |
2433 | } | |
2434 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2435 | } | |
2436 | ||
2437 | mips16_op_hash = hash_new (); | |
2438 | ||
2439 | i = 0; | |
2440 | while (i < bfd_mips16_num_opcodes) | |
2441 | { | |
2442 | const char *name = mips16_opcodes[i].name; | |
2443 | ||
17a2f251 | 2444 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2445 | if (retval != NULL) |
2446 | as_fatal (_("internal: can't hash `%s': %s"), | |
2447 | mips16_opcodes[i].name, retval); | |
2448 | do | |
2449 | { | |
2450 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2451 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2452 | != mips16_opcodes[i].match)) | |
2453 | { | |
2454 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2455 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2456 | broken = 1; | |
2457 | } | |
1e915849 RS |
2458 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2459 | { | |
2460 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2461 | mips16_nop_insn.fixed_p = 1; | |
2462 | } | |
252b5132 RH |
2463 | ++i; |
2464 | } | |
2465 | while (i < bfd_mips16_num_opcodes | |
2466 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2467 | } | |
2468 | ||
df58fc94 RS |
2469 | micromips_op_hash = hash_new (); |
2470 | ||
2471 | i = 0; | |
2472 | while (i < bfd_micromips_num_opcodes) | |
2473 | { | |
2474 | const char *name = micromips_opcodes[i].name; | |
2475 | ||
2476 | retval = hash_insert (micromips_op_hash, name, | |
2477 | (void *) µmips_opcodes[i]); | |
2478 | if (retval != NULL) | |
2479 | as_fatal (_("internal: can't hash `%s': %s"), | |
2480 | micromips_opcodes[i].name, retval); | |
2481 | do | |
2482 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2483 | { | |
2484 | struct mips_cl_insn *micromips_nop_insn; | |
2485 | ||
2486 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2487 | broken = 1; | |
2488 | ||
2489 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2490 | micromips_nop_insn = µmips_nop16_insn; | |
2491 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2492 | micromips_nop_insn = µmips_nop32_insn; | |
2493 | else | |
2494 | continue; | |
2495 | ||
2496 | if (micromips_nop_insn->insn_mo == NULL | |
2497 | && strcmp (name, "nop") == 0) | |
2498 | { | |
2499 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2500 | micromips_nop_insn->fixed_p = 1; | |
2501 | } | |
2502 | } | |
2503 | while (++i < bfd_micromips_num_opcodes | |
2504 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2505 | } | |
2506 | ||
252b5132 RH |
2507 | if (broken) |
2508 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2509 | ||
2510 | /* We add all the general register names to the symbol table. This | |
2511 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2512 | for (i = 0; reg_names[i].name; i++) |
2513 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2514 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2515 | &zero_address_frag)); |
2516 | if (HAVE_NEWABI) | |
2517 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2518 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2519 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2520 | &zero_address_frag)); |
707bfff6 TS |
2521 | else |
2522 | for (i = 0; reg_names_o32[i].name; i++) | |
2523 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2524 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2525 | &zero_address_frag)); |
6047c971 | 2526 | |
7d10b47d | 2527 | mips_no_prev_insn (); |
252b5132 RH |
2528 | |
2529 | mips_gprmask = 0; | |
2530 | mips_cprmask[0] = 0; | |
2531 | mips_cprmask[1] = 0; | |
2532 | mips_cprmask[2] = 0; | |
2533 | mips_cprmask[3] = 0; | |
2534 | ||
2535 | /* set the default alignment for the text section (2**2) */ | |
2536 | record_alignment (text_section, 2); | |
2537 | ||
4d0d148d | 2538 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2539 | |
707bfff6 | 2540 | #ifdef OBJ_ELF |
f43abd2b | 2541 | if (IS_ELF) |
252b5132 | 2542 | { |
0a44bf69 RS |
2543 | /* On a native system other than VxWorks, sections must be aligned |
2544 | to 16 byte boundaries. When configured for an embedded ELF | |
2545 | target, we don't bother. */ | |
c41e87e3 CF |
2546 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2547 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2548 | { |
2549 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2550 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2551 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2552 | } | |
2553 | ||
2554 | /* Create a .reginfo section for register masks and a .mdebug | |
2555 | section for debugging information. */ | |
2556 | { | |
2557 | segT seg; | |
2558 | subsegT subseg; | |
2559 | flagword flags; | |
2560 | segT sec; | |
2561 | ||
2562 | seg = now_seg; | |
2563 | subseg = now_subseg; | |
2564 | ||
2565 | /* The ABI says this section should be loaded so that the | |
2566 | running program can access it. However, we don't load it | |
2567 | if we are configured for an embedded target */ | |
2568 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2569 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2570 | flags |= SEC_ALLOC | SEC_LOAD; |
2571 | ||
316f5878 | 2572 | if (mips_abi != N64_ABI) |
252b5132 RH |
2573 | { |
2574 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2575 | ||
195325d2 TS |
2576 | bfd_set_section_flags (stdoutput, sec, flags); |
2577 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2578 | |
252b5132 | 2579 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2580 | } |
2581 | else | |
2582 | { | |
2583 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2584 | .reginfo section. */ | |
2585 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2586 | bfd_set_section_flags (stdoutput, sec, flags); |
2587 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2588 | |
252b5132 RH |
2589 | /* Set up the option header. */ |
2590 | { | |
2591 | Elf_Internal_Options opthdr; | |
2592 | char *f; | |
2593 | ||
2594 | opthdr.kind = ODK_REGINFO; | |
2595 | opthdr.size = (sizeof (Elf_External_Options) | |
2596 | + sizeof (Elf64_External_RegInfo)); | |
2597 | opthdr.section = 0; | |
2598 | opthdr.info = 0; | |
2599 | f = frag_more (sizeof (Elf_External_Options)); | |
2600 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2601 | (Elf_External_Options *) f); | |
2602 | ||
2603 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2604 | } | |
252b5132 RH |
2605 | } |
2606 | ||
2607 | if (ECOFF_DEBUGGING) | |
2608 | { | |
2609 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2610 | (void) bfd_set_section_flags (stdoutput, sec, | |
2611 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2612 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2613 | } | |
f43abd2b | 2614 | else if (mips_flag_pdr) |
ecb4347a DJ |
2615 | { |
2616 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2617 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2618 | SEC_READONLY | SEC_RELOC | |
2619 | | SEC_DEBUGGING); | |
2620 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2621 | } | |
252b5132 RH |
2622 | |
2623 | subseg_set (seg, subseg); | |
2624 | } | |
2625 | } | |
707bfff6 | 2626 | #endif /* OBJ_ELF */ |
252b5132 RH |
2627 | |
2628 | if (! ECOFF_DEBUGGING) | |
2629 | md_obj_begin (); | |
71400594 RS |
2630 | |
2631 | if (mips_fix_vr4120) | |
2632 | init_vr4120_conflicts (); | |
252b5132 RH |
2633 | } |
2634 | ||
2635 | void | |
17a2f251 | 2636 | md_mips_end (void) |
252b5132 | 2637 | { |
02b1ab82 | 2638 | mips_emit_delays (); |
252b5132 RH |
2639 | if (! ECOFF_DEBUGGING) |
2640 | md_obj_end (); | |
2641 | } | |
2642 | ||
2643 | void | |
17a2f251 | 2644 | md_assemble (char *str) |
252b5132 RH |
2645 | { |
2646 | struct mips_cl_insn insn; | |
f6688943 TS |
2647 | bfd_reloc_code_real_type unused_reloc[3] |
2648 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2649 | |
2650 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2651 | imm2_expr.X_op = O_absent; |
252b5132 | 2652 | offset_expr.X_op = O_absent; |
f6688943 TS |
2653 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2654 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2655 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2656 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2657 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2658 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2659 | |
e1b47bd5 RS |
2660 | mips_mark_labels (); |
2661 | mips_assembling_insn = TRUE; | |
2662 | ||
252b5132 RH |
2663 | if (mips_opts.mips16) |
2664 | mips16_ip (str, &insn); | |
2665 | else | |
2666 | { | |
2667 | mips_ip (str, &insn); | |
beae10d5 KH |
2668 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2669 | str, insn.insn_opcode)); | |
252b5132 RH |
2670 | } |
2671 | ||
2672 | if (insn_error) | |
e1b47bd5 RS |
2673 | as_bad ("%s `%s'", insn_error, str); |
2674 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2675 | { |
584892a6 | 2676 | macro_start (); |
252b5132 RH |
2677 | if (mips_opts.mips16) |
2678 | mips16_macro (&insn); | |
2679 | else | |
2680 | macro (&insn); | |
584892a6 | 2681 | macro_end (); |
252b5132 RH |
2682 | } |
2683 | else | |
2684 | { | |
2685 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2686 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2687 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2688 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2689 | else |
df58fc94 | 2690 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2691 | } |
e1b47bd5 RS |
2692 | |
2693 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2694 | } |
2695 | ||
738e5348 RS |
2696 | /* Convenience functions for abstracting away the differences between |
2697 | MIPS16 and non-MIPS16 relocations. */ | |
2698 | ||
2699 | static inline bfd_boolean | |
2700 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2701 | { | |
2702 | switch (reloc) | |
2703 | { | |
2704 | case BFD_RELOC_MIPS16_JMP: | |
2705 | case BFD_RELOC_MIPS16_GPREL: | |
2706 | case BFD_RELOC_MIPS16_GOT16: | |
2707 | case BFD_RELOC_MIPS16_CALL16: | |
2708 | case BFD_RELOC_MIPS16_HI16_S: | |
2709 | case BFD_RELOC_MIPS16_HI16: | |
2710 | case BFD_RELOC_MIPS16_LO16: | |
2711 | return TRUE; | |
2712 | ||
2713 | default: | |
2714 | return FALSE; | |
2715 | } | |
2716 | } | |
2717 | ||
df58fc94 RS |
2718 | static inline bfd_boolean |
2719 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2720 | { | |
2721 | switch (reloc) | |
2722 | { | |
2723 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2724 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2725 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2726 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2727 | case BFD_RELOC_MICROMIPS_JMP: | |
2728 | case BFD_RELOC_MICROMIPS_HI16: | |
2729 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2730 | case BFD_RELOC_MICROMIPS_LO16: | |
2731 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2732 | case BFD_RELOC_MICROMIPS_GOT16: | |
2733 | case BFD_RELOC_MICROMIPS_CALL16: | |
2734 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2735 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2736 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2737 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2738 | case BFD_RELOC_MICROMIPS_SUB: | |
2739 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2740 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2741 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2742 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2743 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2744 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2745 | case BFD_RELOC_MICROMIPS_JALR: | |
2746 | return TRUE; | |
2747 | ||
2748 | default: | |
2749 | return FALSE; | |
2750 | } | |
2751 | } | |
2752 | ||
2309ddf2 MR |
2753 | static inline bfd_boolean |
2754 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2755 | { | |
2756 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2757 | } | |
2758 | ||
738e5348 RS |
2759 | static inline bfd_boolean |
2760 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2761 | { | |
2309ddf2 | 2762 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2763 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2764 | } |
2765 | ||
2766 | static inline bfd_boolean | |
2767 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2768 | { | |
2309ddf2 | 2769 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2770 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2771 | } |
2772 | ||
2773 | static inline bfd_boolean | |
2774 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2775 | { | |
2309ddf2 | 2776 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2777 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2778 | } | |
2779 | ||
df58fc94 RS |
2780 | static inline bfd_boolean |
2781 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2782 | { | |
2309ddf2 | 2783 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2784 | } |
2785 | ||
2de39019 CM |
2786 | /* Return true if RELOC is a PC-relative relocation that does not have |
2787 | full address range. */ | |
2788 | ||
2789 | static inline bfd_boolean | |
2790 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2791 | { | |
2792 | switch (reloc) | |
2793 | { | |
2794 | case BFD_RELOC_16_PCREL_S2: | |
2795 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2796 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2797 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2798 | return TRUE; | |
2799 | ||
b47468a6 CM |
2800 | case BFD_RELOC_32_PCREL: |
2801 | return HAVE_64BIT_ADDRESSES; | |
2802 | ||
2de39019 CM |
2803 | default: |
2804 | return FALSE; | |
2805 | } | |
2806 | } | |
b47468a6 | 2807 | |
5919d012 | 2808 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2809 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2810 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2811 | |
2812 | static inline bfd_boolean | |
17a2f251 | 2813 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2814 | { |
3b91255e | 2815 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2816 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2817 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2818 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2819 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2820 | } | |
2821 | ||
2822 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2823 | reloc_needs_lo_p. */ | |
2824 | ||
2825 | static inline bfd_reloc_code_real_type | |
2826 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2827 | { | |
df58fc94 RS |
2828 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2829 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2830 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2831 | } |
2832 | ||
2833 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2834 | relocation. */ | |
2835 | ||
2836 | static inline bfd_boolean | |
17a2f251 | 2837 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2838 | { |
2839 | return (fixp->fx_next != NULL | |
738e5348 | 2840 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2841 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2842 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2843 | } | |
2844 | ||
252b5132 RH |
2845 | /* This function returns true if modifying a register requires a |
2846 | delay. */ | |
2847 | ||
2848 | static int | |
17a2f251 | 2849 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2850 | { |
2851 | unsigned long prev_pinfo; | |
2852 | ||
47e39b9d | 2853 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2854 | if (! mips_opts.noreorder |
81912461 ILT |
2855 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2856 | && ! gpr_interlocks) | |
2857 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2858 | && ! cop_interlocks))) | |
252b5132 | 2859 | { |
81912461 ILT |
2860 | /* A load from a coprocessor or from memory. All load delays |
2861 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2862 | /* Itbl support may require additional care here. */ |
252b5132 | 2863 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2864 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2865 | return 1; |
2866 | } | |
2867 | ||
2868 | return 0; | |
2869 | } | |
2870 | ||
462427c4 RS |
2871 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2872 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2873 | |
2874 | static void | |
462427c4 | 2875 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2876 | { |
2877 | struct insn_label_list *l; | |
2878 | valueT val; | |
2879 | ||
462427c4 | 2880 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2881 | { |
9c2799c2 | 2882 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2883 | symbol_set_frag (l->label, frag_now); |
2884 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2885 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2886 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2887 | ++val; |
2888 | S_SET_VALUE (l->label, val); | |
2889 | } | |
2890 | } | |
2891 | ||
462427c4 RS |
2892 | /* Move all labels in insn_labels to the current insertion point |
2893 | and treat them as text labels. */ | |
2894 | ||
2895 | static void | |
2896 | mips_move_text_labels (void) | |
2897 | { | |
2898 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2899 | } | |
2900 | ||
5f0fe04b TS |
2901 | static bfd_boolean |
2902 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2903 | { | |
2904 | bfd_boolean linkonce = FALSE; | |
2905 | segT symseg = S_GET_SEGMENT (sym); | |
2906 | ||
2907 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2908 | { | |
2909 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2910 | linkonce = TRUE; | |
2911 | #ifdef OBJ_ELF | |
2912 | /* The GNU toolchain uses an extension for ELF: a section | |
2913 | beginning with the magic string .gnu.linkonce is a | |
2914 | linkonce section. */ | |
2915 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2916 | sizeof ".gnu.linkonce" - 1) == 0) | |
2917 | linkonce = TRUE; | |
2918 | #endif | |
2919 | } | |
2920 | return linkonce; | |
2921 | } | |
2922 | ||
e1b47bd5 | 2923 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2924 | linker to handle them specially, such as generating jalx instructions |
2925 | when needed. We also make them odd for the duration of the assembly, | |
2926 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2927 | in the adjust_symtab routine, while leaving them marked. This is |
2928 | convenient for the debugger and the disassembler. The linker knows | |
2929 | to make them odd again. */ | |
2930 | ||
2931 | static void | |
e1b47bd5 | 2932 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2933 | { |
df58fc94 | 2934 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2935 | |
a8dbcb85 | 2936 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2937 | if (IS_ELF) |
2938 | { | |
2939 | if (mips_opts.mips16) | |
2940 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2941 | else | |
2942 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2943 | } |
e1b47bd5 RS |
2944 | #endif |
2945 | if ((S_GET_VALUE (label) & 1) == 0 | |
2946 | /* Don't adjust the address if the label is global or weak, or | |
2947 | in a link-once section, since we'll be emitting symbol reloc | |
2948 | references to it which will be patched up by the linker, and | |
2949 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2950 | && !S_IS_WEAK (label) | |
2951 | && !S_IS_EXTERNAL (label) | |
2952 | && !s_is_linkonce (label, now_seg)) | |
2953 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2954 | } | |
2955 | ||
2956 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2957 | ||
2958 | static void | |
2959 | mips_compressed_mark_labels (void) | |
2960 | { | |
2961 | struct insn_label_list *l; | |
2962 | ||
2963 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2964 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2965 | } |
2966 | ||
4d7206a2 RS |
2967 | /* End the current frag. Make it a variant frag and record the |
2968 | relaxation info. */ | |
2969 | ||
2970 | static void | |
2971 | relax_close_frag (void) | |
2972 | { | |
584892a6 | 2973 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2974 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2975 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2976 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2977 | ||
2978 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2979 | mips_relax.first_fixup = 0; | |
2980 | } | |
2981 | ||
2982 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2983 | See the comment above RELAX_ENCODE for more details. */ | |
2984 | ||
2985 | static void | |
2986 | relax_start (symbolS *symbol) | |
2987 | { | |
9c2799c2 | 2988 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2989 | mips_relax.sequence = 1; |
2990 | mips_relax.symbol = symbol; | |
2991 | } | |
2992 | ||
2993 | /* Start generating the second version of a relaxable sequence. | |
2994 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2995 | |
2996 | static void | |
4d7206a2 RS |
2997 | relax_switch (void) |
2998 | { | |
9c2799c2 | 2999 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3000 | mips_relax.sequence = 2; |
3001 | } | |
3002 | ||
3003 | /* End the current relaxable sequence. */ | |
3004 | ||
3005 | static void | |
3006 | relax_end (void) | |
3007 | { | |
9c2799c2 | 3008 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3009 | relax_close_frag (); |
3010 | mips_relax.sequence = 0; | |
3011 | } | |
3012 | ||
11625dd8 RS |
3013 | /* Return true if IP is a delayed branch or jump. */ |
3014 | ||
3015 | static inline bfd_boolean | |
3016 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3017 | { | |
3018 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3019 | | INSN_COND_BRANCH_DELAY | |
3020 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3021 | } | |
3022 | ||
3023 | /* Return true if IP is a compact branch or jump. */ | |
3024 | ||
3025 | static inline bfd_boolean | |
3026 | compact_branch_p (const struct mips_cl_insn *ip) | |
3027 | { | |
3028 | if (mips_opts.mips16) | |
3029 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3030 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3031 | else | |
3032 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3033 | | INSN2_COND_BRANCH)) != 0; | |
3034 | } | |
3035 | ||
3036 | /* Return true if IP is an unconditional branch or jump. */ | |
3037 | ||
3038 | static inline bfd_boolean | |
3039 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3040 | { | |
3041 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3042 | || (mips_opts.mips16 | |
3043 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3044 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3045 | } | |
3046 | ||
3047 | /* Return true if IP is a branch-likely instruction. */ | |
3048 | ||
3049 | static inline bfd_boolean | |
3050 | branch_likely_p (const struct mips_cl_insn *ip) | |
3051 | { | |
3052 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3053 | } | |
3054 | ||
14fe068b RS |
3055 | /* Return the type of nop that should be used to fill the delay slot |
3056 | of delayed branch IP. */ | |
3057 | ||
3058 | static struct mips_cl_insn * | |
3059 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3060 | { | |
3061 | if (mips_opts.micromips | |
3062 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3063 | return µmips_nop32_insn; | |
3064 | return NOP_INSN; | |
3065 | } | |
3066 | ||
2309ddf2 | 3067 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3068 | |
3069 | static unsigned int | |
3070 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3071 | { | |
2309ddf2 | 3072 | unsigned long pinfo2; |
df58fc94 RS |
3073 | unsigned int mask; |
3074 | ||
3075 | mask = 0; | |
df58fc94 RS |
3076 | pinfo2 = ip->insn_mo->pinfo2; |
3077 | if (mips_opts.micromips) | |
3078 | { | |
df58fc94 RS |
3079 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3080 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3081 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3082 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3083 | if (pinfo2 & INSN2_MOD_SP) |
3084 | mask |= 1 << SP; | |
3085 | } | |
3086 | return mask; | |
3087 | } | |
3088 | ||
4c260379 RS |
3089 | /* Return the mask of core registers that IP reads. */ |
3090 | ||
3091 | static unsigned int | |
3092 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3093 | { | |
3094 | unsigned long pinfo, pinfo2; | |
3095 | unsigned int mask; | |
3096 | ||
df58fc94 | 3097 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3098 | pinfo = ip->insn_mo->pinfo; |
3099 | pinfo2 = ip->insn_mo->pinfo2; | |
3100 | if (mips_opts.mips16) | |
3101 | { | |
3102 | if (pinfo & MIPS16_INSN_READ_X) | |
3103 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3104 | if (pinfo & MIPS16_INSN_READ_Y) | |
3105 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3106 | if (pinfo & MIPS16_INSN_READ_T) | |
3107 | mask |= 1 << TREG; | |
3108 | if (pinfo & MIPS16_INSN_READ_SP) | |
3109 | mask |= 1 << SP; | |
3110 | if (pinfo & MIPS16_INSN_READ_31) | |
3111 | mask |= 1 << RA; | |
3112 | if (pinfo & MIPS16_INSN_READ_Z) | |
3113 | mask |= 1 << (mips16_to_32_reg_map | |
3114 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3115 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3116 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3117 | } | |
3118 | else | |
3119 | { | |
3120 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3121 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3122 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3123 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3124 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3125 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3126 | if (pinfo2 & INSN2_READ_GP) | |
3127 | mask |= 1 << GP; | |
3128 | if (pinfo2 & INSN2_READ_GPR_31) | |
3129 | mask |= 1 << RA; | |
4c260379 | 3130 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3131 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3132 | } |
2b0c8b40 MR |
3133 | if (mips_opts.micromips) |
3134 | { | |
3135 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3136 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3137 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3138 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3139 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3140 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3141 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3142 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3143 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3144 | { | |
3145 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3146 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3147 | } | |
3148 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3149 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3150 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3151 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3152 | } | |
fe35f09f RS |
3153 | /* Don't include register 0. */ |
3154 | return mask & ~1; | |
4c260379 RS |
3155 | } |
3156 | ||
3157 | /* Return the mask of core registers that IP writes. */ | |
3158 | ||
3159 | static unsigned int | |
3160 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3161 | { | |
3162 | unsigned long pinfo, pinfo2; | |
3163 | unsigned int mask; | |
3164 | ||
df58fc94 | 3165 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3166 | pinfo = ip->insn_mo->pinfo; |
3167 | pinfo2 = ip->insn_mo->pinfo2; | |
3168 | if (mips_opts.mips16) | |
3169 | { | |
3170 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3171 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3172 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3173 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3174 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3175 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3176 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3177 | mask |= 1 << TREG; | |
3178 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3179 | mask |= 1 << SP; | |
3180 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3181 | mask |= 1 << RA; | |
3182 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3183 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3184 | } | |
3185 | else | |
3186 | { | |
3187 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3188 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3189 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3190 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3191 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3192 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3193 | if (pinfo & INSN_WRITE_GPR_31) |
3194 | mask |= 1 << RA; | |
3195 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3196 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3197 | } |
2b0c8b40 MR |
3198 | if (mips_opts.micromips) |
3199 | { | |
3200 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3201 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3202 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3203 | { | |
3204 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3205 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3206 | } | |
3207 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3208 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3209 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3210 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3211 | } | |
fe35f09f RS |
3212 | /* Don't include register 0. */ |
3213 | return mask & ~1; | |
4c260379 RS |
3214 | } |
3215 | ||
3216 | /* Return the mask of floating-point registers that IP reads. */ | |
3217 | ||
3218 | static unsigned int | |
3219 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3220 | { | |
3221 | unsigned long pinfo, pinfo2; | |
3222 | unsigned int mask; | |
3223 | ||
3224 | mask = 0; | |
3225 | pinfo = ip->insn_mo->pinfo; | |
3226 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3227 | if (!mips_opts.mips16) |
df58fc94 RS |
3228 | { |
3229 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3230 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3231 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3232 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3233 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3234 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3235 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3236 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3237 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3238 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3239 | } |
3240 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3241 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3242 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3243 | mask |= mask << 1; | |
3244 | return mask; | |
3245 | } | |
3246 | ||
3247 | /* Return the mask of floating-point registers that IP writes. */ | |
3248 | ||
3249 | static unsigned int | |
3250 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3251 | { | |
3252 | unsigned long pinfo, pinfo2; | |
3253 | unsigned int mask; | |
3254 | ||
3255 | mask = 0; | |
3256 | pinfo = ip->insn_mo->pinfo; | |
3257 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3258 | if (!mips_opts.mips16) |
4c260379 RS |
3259 | { |
3260 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3261 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3262 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3263 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3264 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3265 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3266 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3267 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3268 | } |
3269 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3270 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3271 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3272 | mask |= mask << 1; | |
3273 | return mask; | |
3274 | } | |
3275 | ||
71400594 RS |
3276 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3277 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3278 | by VR4120 errata. */ | |
4d7206a2 | 3279 | |
71400594 RS |
3280 | static unsigned int |
3281 | classify_vr4120_insn (const char *name) | |
252b5132 | 3282 | { |
71400594 RS |
3283 | if (strncmp (name, "macc", 4) == 0) |
3284 | return FIX_VR4120_MACC; | |
3285 | if (strncmp (name, "dmacc", 5) == 0) | |
3286 | return FIX_VR4120_DMACC; | |
3287 | if (strncmp (name, "mult", 4) == 0) | |
3288 | return FIX_VR4120_MULT; | |
3289 | if (strncmp (name, "dmult", 5) == 0) | |
3290 | return FIX_VR4120_DMULT; | |
3291 | if (strstr (name, "div")) | |
3292 | return FIX_VR4120_DIV; | |
3293 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3294 | return FIX_VR4120_MTHILO; | |
3295 | return NUM_FIX_VR4120_CLASSES; | |
3296 | } | |
252b5132 | 3297 | |
ff239038 CM |
3298 | #define INSN_ERET 0x42000018 |
3299 | #define INSN_DERET 0x4200001f | |
3300 | ||
71400594 RS |
3301 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3302 | where INSN1 is the earlier instruction. Return the worst-case value | |
3303 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3304 | |
71400594 RS |
3305 | static unsigned int |
3306 | insns_between (const struct mips_cl_insn *insn1, | |
3307 | const struct mips_cl_insn *insn2) | |
3308 | { | |
3309 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3310 | unsigned int mask; |
71400594 RS |
3311 | |
3312 | /* This function needs to know which pinfo flags are set for INSN2 | |
3313 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3314 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3315 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3316 | pinfo1 = insn1->insn_mo->pinfo; |
3317 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3318 | |
4c260379 RS |
3319 | #define INSN2_USES_GPR(REG) \ |
3320 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3321 | |
3322 | /* For most targets, write-after-read dependencies on the HI and LO | |
3323 | registers must be separated by at least two instructions. */ | |
3324 | if (!hilo_interlocks) | |
252b5132 | 3325 | { |
71400594 RS |
3326 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3327 | return 2; | |
3328 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3329 | return 2; | |
3330 | } | |
3331 | ||
3332 | /* If we're working around r7000 errata, there must be two instructions | |
3333 | between an mfhi or mflo and any instruction that uses the result. */ | |
3334 | if (mips_7000_hilo_fix | |
df58fc94 | 3335 | && !mips_opts.micromips |
71400594 | 3336 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3337 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3338 | return 2; |
3339 | ||
ff239038 CM |
3340 | /* If we're working around 24K errata, one instruction is required |
3341 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3342 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3343 | { |
3344 | if (insn1->insn_opcode == INSN_ERET | |
3345 | || insn1->insn_opcode == INSN_DERET) | |
3346 | { | |
3347 | if (insn2 == NULL | |
3348 | || insn2->insn_opcode == INSN_ERET | |
3349 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3350 | || delayed_branch_p (insn2)) |
ff239038 CM |
3351 | return 1; |
3352 | } | |
3353 | } | |
3354 | ||
71400594 RS |
3355 | /* If working around VR4120 errata, check for combinations that need |
3356 | a single intervening instruction. */ | |
df58fc94 | 3357 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3358 | { |
3359 | unsigned int class1, class2; | |
252b5132 | 3360 | |
71400594 RS |
3361 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3362 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3363 | { |
71400594 RS |
3364 | if (insn2 == NULL) |
3365 | return 1; | |
3366 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3367 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3368 | return 1; | |
252b5132 | 3369 | } |
71400594 RS |
3370 | } |
3371 | ||
df58fc94 | 3372 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3373 | { |
3374 | /* Check for GPR or coprocessor load delays. All such delays | |
3375 | are on the RT register. */ | |
3376 | /* Itbl support may require additional care here. */ | |
3377 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3378 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3379 | { |
71400594 | 3380 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3381 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3382 | return 1; |
3383 | } | |
3384 | ||
3385 | /* Check for generic coprocessor hazards. | |
3386 | ||
3387 | This case is not handled very well. There is no special | |
3388 | knowledge of CP0 handling, and the coprocessors other than | |
3389 | the floating point unit are not distinguished at all. */ | |
3390 | /* Itbl support may require additional care here. FIXME! | |
3391 | Need to modify this to include knowledge about | |
3392 | user specified delays! */ | |
3393 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3394 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3395 | { | |
3396 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3397 | register. There must be a one instruction delay before INSN2 | |
3398 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3399 | mask = fpr_write_mask (insn1); |
3400 | if (mask != 0) | |
252b5132 | 3401 | { |
4c260379 | 3402 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3403 | return 1; |
252b5132 RH |
3404 | } |
3405 | else | |
3406 | { | |
71400594 RS |
3407 | /* Read-after-write dependencies on the control registers |
3408 | require a two-instruction gap. */ | |
3409 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3410 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3411 | return 2; | |
3412 | ||
3413 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3414 | also a coprocessor instruction, assume there must be | |
3415 | a one instruction gap. */ | |
3416 | if (pinfo2 & INSN_COP) | |
3417 | return 1; | |
252b5132 RH |
3418 | } |
3419 | } | |
6b76fefe | 3420 | |
71400594 RS |
3421 | /* Check for read-after-write dependencies on the coprocessor |
3422 | control registers in cases where INSN1 does not need a general | |
3423 | coprocessor delay. This means that INSN1 is a floating point | |
3424 | comparison instruction. */ | |
3425 | /* Itbl support may require additional care here. */ | |
3426 | else if (!cop_interlocks | |
3427 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3428 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3429 | return 1; | |
3430 | } | |
6b76fefe | 3431 | |
4c260379 | 3432 | #undef INSN2_USES_GPR |
6b76fefe | 3433 | |
71400594 RS |
3434 | return 0; |
3435 | } | |
6b76fefe | 3436 | |
7d8e00cf RS |
3437 | /* Return the number of nops that would be needed to work around the |
3438 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3439 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3440 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3441 | |
3442 | static int | |
932d1a1b | 3443 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3444 | const struct mips_cl_insn *insn) |
3445 | { | |
4c260379 RS |
3446 | int i, j; |
3447 | unsigned int mask; | |
7d8e00cf RS |
3448 | |
3449 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3450 | are not affected by the errata. */ | |
3451 | if (insn != 0 | |
3452 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3453 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3454 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3455 | return 0; | |
3456 | ||
3457 | /* Search for the first MFLO or MFHI. */ | |
3458 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3459 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3460 | { |
3461 | /* Extract the destination register. */ | |
4c260379 | 3462 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3463 | |
3464 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3465 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3466 | return 0; |
3467 | ||
3468 | /* ...or if any of the intervening instructions do. */ | |
3469 | for (j = 0; j < i; j++) | |
4c260379 | 3470 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3471 | return 0; |
3472 | ||
932d1a1b RS |
3473 | if (i >= ignore) |
3474 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3475 | } |
3476 | return 0; | |
3477 | } | |
3478 | ||
15be625d CM |
3479 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3480 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3481 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3482 | ||
3483 | /* Return the minimum alignment for this store instruction. */ | |
3484 | ||
3485 | static int | |
3486 | fix_24k_align_to (const struct mips_opcode *mo) | |
3487 | { | |
3488 | if (strcmp (mo->name, "sh") == 0) | |
3489 | return 2; | |
3490 | ||
3491 | if (strcmp (mo->name, "swc1") == 0 | |
3492 | || strcmp (mo->name, "swc2") == 0 | |
3493 | || strcmp (mo->name, "sw") == 0 | |
3494 | || strcmp (mo->name, "sc") == 0 | |
3495 | || strcmp (mo->name, "s.s") == 0) | |
3496 | return 4; | |
3497 | ||
3498 | if (strcmp (mo->name, "sdc1") == 0 | |
3499 | || strcmp (mo->name, "sdc2") == 0 | |
3500 | || strcmp (mo->name, "s.d") == 0) | |
3501 | return 8; | |
3502 | ||
3503 | /* sb, swl, swr */ | |
3504 | return 1; | |
3505 | } | |
3506 | ||
3507 | struct fix_24k_store_info | |
3508 | { | |
3509 | /* Immediate offset, if any, for this store instruction. */ | |
3510 | short off; | |
3511 | /* Alignment required by this store instruction. */ | |
3512 | int align_to; | |
3513 | /* True for register offsets. */ | |
3514 | int register_offset; | |
3515 | }; | |
3516 | ||
3517 | /* Comparison function used by qsort. */ | |
3518 | ||
3519 | static int | |
3520 | fix_24k_sort (const void *a, const void *b) | |
3521 | { | |
3522 | const struct fix_24k_store_info *pos1 = a; | |
3523 | const struct fix_24k_store_info *pos2 = b; | |
3524 | ||
3525 | return (pos1->off - pos2->off); | |
3526 | } | |
3527 | ||
3528 | /* INSN is a store instruction. Try to record the store information | |
3529 | in STINFO. Return false if the information isn't known. */ | |
3530 | ||
3531 | static bfd_boolean | |
3532 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3533 | const struct mips_cl_insn *insn) |
15be625d CM |
3534 | { |
3535 | /* The instruction must have a known offset. */ | |
3536 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3537 | return FALSE; | |
3538 | ||
3539 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3540 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3541 | return TRUE; | |
3542 | } | |
3543 | ||
932d1a1b RS |
3544 | /* Return the number of nops that would be needed to work around the 24k |
3545 | "lost data on stores during refill" errata if instruction INSN | |
3546 | immediately followed the 2 instructions described by HIST. | |
3547 | Ignore hazards that are contained within the first IGNORE | |
3548 | instructions of HIST. | |
3549 | ||
3550 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3551 | for the data cache refills and store data. The following describes | |
3552 | the scenario where the store data could be lost. | |
3553 | ||
3554 | * A data cache miss, due to either a load or a store, causing fill | |
3555 | data to be supplied by the memory subsystem | |
3556 | * The first three doublewords of fill data are returned and written | |
3557 | into the cache | |
3558 | * A sequence of four stores occurs in consecutive cycles around the | |
3559 | final doubleword of the fill: | |
3560 | * Store A | |
3561 | * Store B | |
3562 | * Store C | |
3563 | * Zero, One or more instructions | |
3564 | * Store D | |
3565 | ||
3566 | The four stores A-D must be to different doublewords of the line that | |
3567 | is being filled. The fourth instruction in the sequence above permits | |
3568 | the fill of the final doubleword to be transferred from the FSB into | |
3569 | the cache. In the sequence above, the stores may be either integer | |
3570 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3571 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3572 | different doublewords on the line. If the floating point unit is | |
3573 | running in 1:2 mode, it is not possible to create the sequence above | |
3574 | using only floating point store instructions. | |
15be625d CM |
3575 | |
3576 | In this case, the cache line being filled is incorrectly marked | |
3577 | invalid, thereby losing the data from any store to the line that | |
3578 | occurs between the original miss and the completion of the five | |
3579 | cycle sequence shown above. | |
3580 | ||
932d1a1b | 3581 | The workarounds are: |
15be625d | 3582 | |
932d1a1b RS |
3583 | * Run the data cache in write-through mode. |
3584 | * Insert a non-store instruction between | |
3585 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3586 | |
3587 | static int | |
932d1a1b | 3588 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3589 | const struct mips_cl_insn *insn) |
3590 | { | |
3591 | struct fix_24k_store_info pos[3]; | |
3592 | int align, i, base_offset; | |
3593 | ||
932d1a1b RS |
3594 | if (ignore >= 2) |
3595 | return 0; | |
3596 | ||
ab9794cf RS |
3597 | /* If the previous instruction wasn't a store, there's nothing to |
3598 | worry about. */ | |
15be625d CM |
3599 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3600 | return 0; | |
3601 | ||
ab9794cf RS |
3602 | /* If the instructions after the previous one are unknown, we have |
3603 | to assume the worst. */ | |
3604 | if (!insn) | |
15be625d CM |
3605 | return 1; |
3606 | ||
ab9794cf RS |
3607 | /* Check whether we are dealing with three consecutive stores. */ |
3608 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3609 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3610 | return 0; |
3611 | ||
3612 | /* If we don't know the relationship between the store addresses, | |
3613 | assume the worst. */ | |
ab9794cf | 3614 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3615 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3616 | return 1; | |
3617 | ||
3618 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3619 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3620 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3621 | return 1; | |
3622 | ||
3623 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3624 | ||
3625 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3626 | X bytes and such that the base register + X is known to be aligned | |
3627 | to align bytes. */ | |
3628 | ||
3629 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3630 | align = 8; | |
3631 | else | |
3632 | { | |
3633 | align = pos[0].align_to; | |
3634 | base_offset = pos[0].off; | |
3635 | for (i = 1; i < 3; i++) | |
3636 | if (align < pos[i].align_to) | |
3637 | { | |
3638 | align = pos[i].align_to; | |
3639 | base_offset = pos[i].off; | |
3640 | } | |
3641 | for (i = 0; i < 3; i++) | |
3642 | pos[i].off -= base_offset; | |
3643 | } | |
3644 | ||
3645 | pos[0].off &= ~align + 1; | |
3646 | pos[1].off &= ~align + 1; | |
3647 | pos[2].off &= ~align + 1; | |
3648 | ||
3649 | /* If any two stores write to the same chunk, they also write to the | |
3650 | same doubleword. The offsets are still sorted at this point. */ | |
3651 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3652 | return 0; | |
3653 | ||
3654 | /* A range of at least 9 bytes is needed for the stores to be in | |
3655 | non-overlapping doublewords. */ | |
3656 | if (pos[2].off - pos[0].off <= 8) | |
3657 | return 0; | |
3658 | ||
3659 | if (pos[2].off - pos[1].off >= 24 | |
3660 | || pos[1].off - pos[0].off >= 24 | |
3661 | || pos[2].off - pos[0].off >= 32) | |
3662 | return 0; | |
3663 | ||
3664 | return 1; | |
3665 | } | |
3666 | ||
71400594 | 3667 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3668 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3669 | where HIST[0] is the most recent instruction. Ignore hazards |
3670 | between INSN and the first IGNORE instructions in HIST. | |
3671 | ||
3672 | If INSN is null, return the worse-case number of nops for any | |
3673 | instruction. */ | |
bdaaa2e1 | 3674 | |
71400594 | 3675 | static int |
932d1a1b | 3676 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3677 | const struct mips_cl_insn *insn) |
3678 | { | |
3679 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3680 | |
71400594 | 3681 | nops = 0; |
932d1a1b | 3682 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3683 | { |
91d6fa6a | 3684 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3685 | if (tmp_nops > nops) |
3686 | nops = tmp_nops; | |
3687 | } | |
7d8e00cf | 3688 | |
df58fc94 | 3689 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3690 | { |
932d1a1b | 3691 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3692 | if (tmp_nops > nops) |
3693 | nops = tmp_nops; | |
3694 | } | |
3695 | ||
df58fc94 | 3696 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3697 | { |
932d1a1b | 3698 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3699 | if (tmp_nops > nops) |
3700 | nops = tmp_nops; | |
3701 | } | |
3702 | ||
71400594 RS |
3703 | return nops; |
3704 | } | |
252b5132 | 3705 | |
71400594 | 3706 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3707 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3708 | would be needed after the extended sequence, ignoring hazards |
3709 | in the first IGNORE instructions. */ | |
252b5132 | 3710 | |
71400594 | 3711 | static int |
932d1a1b RS |
3712 | nops_for_sequence (int num_insns, int ignore, |
3713 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3714 | { |
3715 | va_list args; | |
3716 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3717 | struct mips_cl_insn *cursor; | |
3718 | int nops; | |
3719 | ||
91d6fa6a | 3720 | va_start (args, hist); |
71400594 | 3721 | cursor = buffer + num_insns; |
91d6fa6a | 3722 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3723 | while (cursor > buffer) |
3724 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3725 | ||
932d1a1b | 3726 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3727 | va_end (args); |
3728 | return nops; | |
3729 | } | |
252b5132 | 3730 | |
71400594 RS |
3731 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3732 | worst-case delay for the branch target. */ | |
252b5132 | 3733 | |
71400594 | 3734 | static int |
932d1a1b | 3735 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3736 | const struct mips_cl_insn *insn) |
3737 | { | |
3738 | int nops, tmp_nops; | |
60b63b72 | 3739 | |
932d1a1b | 3740 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3741 | if (delayed_branch_p (insn)) |
71400594 | 3742 | { |
932d1a1b | 3743 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3744 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3745 | if (tmp_nops > nops) |
3746 | nops = tmp_nops; | |
3747 | } | |
11625dd8 | 3748 | else if (compact_branch_p (insn)) |
71400594 | 3749 | { |
932d1a1b | 3750 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3751 | if (tmp_nops > nops) |
3752 | nops = tmp_nops; | |
3753 | } | |
3754 | return nops; | |
3755 | } | |
3756 | ||
c67a084a NC |
3757 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3758 | ||
3759 | static void | |
3760 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3761 | { | |
df58fc94 | 3762 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3763 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3764 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3765 | } | |
3766 | ||
3767 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3768 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3769 | ||
3770 | static void | |
3771 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3772 | { | |
df58fc94 | 3773 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3774 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3775 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3776 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3777 | { | |
3778 | int sreg; | |
3779 | expressionS ep; | |
3780 | ||
3781 | if (! mips_opts.at) | |
3782 | return; | |
3783 | ||
df58fc94 | 3784 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3785 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3786 | return; | |
3787 | ||
3788 | ep.X_op = O_constant; | |
3789 | ep.X_add_number = 0xcfff0000; | |
3790 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3791 | ep.X_add_number = 0xffff; | |
3792 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3793 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3794 | } | |
3795 | } | |
3796 | ||
3797 | static void | |
3798 | fix_loongson2f (struct mips_cl_insn * ip) | |
3799 | { | |
3800 | if (mips_fix_loongson2f_nop) | |
3801 | fix_loongson2f_nop (ip); | |
3802 | ||
3803 | if (mips_fix_loongson2f_jump) | |
3804 | fix_loongson2f_jump (ip); | |
3805 | } | |
3806 | ||
a4e06468 RS |
3807 | /* IP is a branch that has a delay slot, and we need to fill it |
3808 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3809 | with the previous instruction. |
3810 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3811 | RELOC_TYPE. */ | |
a4e06468 RS |
3812 | |
3813 | static bfd_boolean | |
e407c74b NC |
3814 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3815 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3816 | { |
2b0c8b40 | 3817 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3818 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3819 | ||
3820 | /* -O2 and above is required for this optimization. */ | |
3821 | if (mips_optimize < 2) | |
3822 | return FALSE; | |
3823 | ||
3824 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3825 | if (mips_opts.nomove) | |
3826 | return FALSE; | |
3827 | ||
3828 | /* We can't swap if the previous instruction's position is fixed. */ | |
3829 | if (history[0].fixed_p) | |
3830 | return FALSE; | |
3831 | ||
3832 | /* If the previous previous insn was in a .set noreorder, we can't | |
3833 | swap. Actually, the MIPS assembler will swap in this situation. | |
3834 | However, gcc configured -with-gnu-as will generate code like | |
3835 | ||
3836 | .set noreorder | |
3837 | lw $4,XXX | |
3838 | .set reorder | |
3839 | INSN | |
3840 | bne $4,$0,foo | |
3841 | ||
3842 | in which we can not swap the bne and INSN. If gcc is not configured | |
3843 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3844 | if (history[1].noreorder_p) | |
3845 | return FALSE; | |
3846 | ||
87333bb7 MR |
3847 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3848 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3849 | if (mips_opts.mips16 && history[0].fixp[0]) |
3850 | return FALSE; | |
3851 | ||
3852 | /* If the branch is itself the target of a branch, we can not swap. | |
3853 | We cheat on this; all we check for is whether there is a label on | |
3854 | this instruction. If there are any branches to anything other than | |
3855 | a label, users must use .set noreorder. */ | |
3856 | if (seg_info (now_seg)->label_list) | |
3857 | return FALSE; | |
3858 | ||
3859 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3860 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3861 | MIPS16 code, which uses variant frags for different purposes. */ |
3862 | if (!mips_opts.mips16 | |
a4e06468 RS |
3863 | && history[0].frag |
3864 | && history[0].frag->fr_type == rs_machine_dependent) | |
3865 | return FALSE; | |
3866 | ||
bcd530a7 RS |
3867 | /* We do not swap with instructions that cannot architecturally |
3868 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3869 | also refrain from swapping with a trap instruction, since it | |
3870 | complicates trap handlers to have the trap instruction be in | |
3871 | a delay slot. */ | |
a4e06468 | 3872 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3873 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3874 | return FALSE; |
3875 | ||
3876 | /* Check for conflicts between the branch and the instructions | |
3877 | before the candidate delay slot. */ | |
3878 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3879 | return FALSE; | |
3880 | ||
3881 | /* Check for conflicts between the swapped sequence and the | |
3882 | target of the branch. */ | |
3883 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3884 | return FALSE; | |
3885 | ||
3886 | /* If the branch reads a register that the previous | |
3887 | instruction sets, we can not swap. */ | |
3888 | gpr_read = gpr_read_mask (ip); | |
3889 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3890 | if (gpr_read & prev_gpr_write) | |
3891 | return FALSE; | |
3892 | ||
3893 | /* If the branch writes a register that the previous | |
3894 | instruction sets, we can not swap. */ | |
3895 | gpr_write = gpr_write_mask (ip); | |
3896 | if (gpr_write & prev_gpr_write) | |
3897 | return FALSE; | |
3898 | ||
3899 | /* If the branch writes a register that the previous | |
3900 | instruction reads, we can not swap. */ | |
3901 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3902 | if (gpr_write & prev_gpr_read) | |
3903 | return FALSE; | |
3904 | ||
3905 | /* If one instruction sets a condition code and the | |
3906 | other one uses a condition code, we can not swap. */ | |
3907 | pinfo = ip->insn_mo->pinfo; | |
3908 | if ((pinfo & INSN_READ_COND_CODE) | |
3909 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3910 | return FALSE; | |
3911 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3912 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3913 | return FALSE; | |
3914 | ||
3915 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3916 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3917 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3918 | return FALSE; | |
2b0c8b40 MR |
3919 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3920 | return FALSE; | |
a4e06468 | 3921 | |
df58fc94 RS |
3922 | /* If the previous instruction has an incorrect size for a fixed |
3923 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3924 | pinfo2 = ip->insn_mo->pinfo2; |
3925 | if (mips_opts.micromips | |
3926 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3927 | && insn_length (history) != 2) | |
3928 | return FALSE; | |
3929 | if (mips_opts.micromips | |
3930 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3931 | && insn_length (history) != 4) | |
3932 | return FALSE; | |
3933 | ||
e407c74b NC |
3934 | /* On R5900 short loops need to be fixed by inserting a nop in |
3935 | the branch delay slots. | |
3936 | A short loop can be terminated too early. */ | |
3937 | if (mips_opts.arch == CPU_R5900 | |
3938 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3939 | && (address_expr != NULL) | |
3940 | /* Parameter must be 16 bit. */ | |
3941 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3942 | /* Branch to same segment. */ | |
3943 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3944 | /* Branch to same code fragment. */ | |
3945 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3946 | /* Can only calculate branch offset if value is known. */ | |
3947 | && symbol_constant_p(address_expr->X_add_symbol) | |
3948 | /* Check if branch is really conditional. */ | |
3949 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3950 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3951 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3952 | { | |
3953 | int distance; | |
3954 | /* Check if loop is shorter than 6 instructions including | |
3955 | branch and delay slot. */ | |
3956 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3957 | if (distance <= 20) | |
3958 | { | |
3959 | int i; | |
3960 | int rv; | |
3961 | ||
3962 | rv = FALSE; | |
3963 | /* When the loop includes branches or jumps, | |
3964 | it is not a short loop. */ | |
3965 | for (i = 0; i < (distance / 4); i++) | |
3966 | { | |
3967 | if ((history[i].cleared_p) | |
3968 | || delayed_branch_p(&history[i])) | |
3969 | { | |
3970 | rv = TRUE; | |
3971 | break; | |
3972 | } | |
3973 | } | |
3974 | if (rv == FALSE) | |
3975 | { | |
3976 | /* Insert nop after branch to fix short loop. */ | |
3977 | return FALSE; | |
3978 | } | |
3979 | } | |
3980 | } | |
3981 | ||
a4e06468 RS |
3982 | return TRUE; |
3983 | } | |
3984 | ||
e407c74b NC |
3985 | /* Decide how we should add IP to the instruction stream. |
3986 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3987 | RELOC_TYPE. */ | |
a4e06468 RS |
3988 | |
3989 | static enum append_method | |
e407c74b NC |
3990 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3991 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3992 | { |
3993 | unsigned long pinfo; | |
3994 | ||
3995 | /* The relaxed version of a macro sequence must be inherently | |
3996 | hazard-free. */ | |
3997 | if (mips_relax.sequence == 2) | |
3998 | return APPEND_ADD; | |
3999 | ||
4000 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4001 | if (mips_opts.noreorder) | |
4002 | return APPEND_ADD; | |
4003 | ||
4004 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4005 | if (delayed_branch_p (ip)) |
a4e06468 | 4006 | { |
e407c74b NC |
4007 | if (!branch_likely_p (ip) |
4008 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4009 | return APPEND_SWAP; |
4010 | ||
11625dd8 | 4011 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4012 | if (mips_opts.mips16 |
4013 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4014 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4015 | return APPEND_ADD_COMPACT; | |
4016 | ||
4017 | return APPEND_ADD_WITH_NOP; | |
4018 | } | |
4019 | ||
a4e06468 RS |
4020 | return APPEND_ADD; |
4021 | } | |
4022 | ||
ceb94aa5 RS |
4023 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4024 | Point IP->insn_mo to the new opcode's definition. */ | |
4025 | ||
4026 | static void | |
4027 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4028 | { | |
4029 | const struct mips_opcode *mo, *end; | |
4030 | ||
4031 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4032 | for (mo = ip->insn_mo; mo < end; mo++) | |
4033 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4034 | { | |
4035 | ip->insn_mo = mo; | |
4036 | return; | |
4037 | } | |
4038 | abort (); | |
4039 | } | |
4040 | ||
df58fc94 RS |
4041 | /* For microMIPS macros, we need to generate a local number label |
4042 | as the target of branches. */ | |
4043 | #define MICROMIPS_LABEL_CHAR '\037' | |
4044 | static unsigned long micromips_target_label; | |
4045 | static char micromips_target_name[32]; | |
4046 | ||
4047 | static char * | |
4048 | micromips_label_name (void) | |
4049 | { | |
4050 | char *p = micromips_target_name; | |
4051 | char symbol_name_temporary[24]; | |
4052 | unsigned long l; | |
4053 | int i; | |
4054 | ||
4055 | if (*p) | |
4056 | return p; | |
4057 | ||
4058 | i = 0; | |
4059 | l = micromips_target_label; | |
4060 | #ifdef LOCAL_LABEL_PREFIX | |
4061 | *p++ = LOCAL_LABEL_PREFIX; | |
4062 | #endif | |
4063 | *p++ = 'L'; | |
4064 | *p++ = MICROMIPS_LABEL_CHAR; | |
4065 | do | |
4066 | { | |
4067 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4068 | l /= 10; | |
4069 | } | |
4070 | while (l != 0); | |
4071 | while (i > 0) | |
4072 | *p++ = symbol_name_temporary[--i]; | |
4073 | *p = '\0'; | |
4074 | ||
4075 | return micromips_target_name; | |
4076 | } | |
4077 | ||
4078 | static void | |
4079 | micromips_label_expr (expressionS *label_expr) | |
4080 | { | |
4081 | label_expr->X_op = O_symbol; | |
4082 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4083 | label_expr->X_add_number = 0; | |
4084 | } | |
4085 | ||
4086 | static void | |
4087 | micromips_label_inc (void) | |
4088 | { | |
4089 | micromips_target_label++; | |
4090 | *micromips_target_name = '\0'; | |
4091 | } | |
4092 | ||
4093 | static void | |
4094 | micromips_add_label (void) | |
4095 | { | |
4096 | symbolS *s; | |
4097 | ||
4098 | s = colon (micromips_label_name ()); | |
4099 | micromips_label_inc (); | |
4100 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4101 | if (IS_ELF) | |
4102 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4103 | #else |
4104 | (void) s; | |
df58fc94 RS |
4105 | #endif |
4106 | } | |
4107 | ||
4108 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4109 | corresponding to the requested one if any. Otherwise return | |
4110 | the reloc unchanged. */ | |
4111 | ||
4112 | static bfd_reloc_code_real_type | |
4113 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4114 | { | |
4115 | static const bfd_reloc_code_real_type relocs[][2] = | |
4116 | { | |
4117 | /* Keep sorted incrementally by the left-hand key. */ | |
4118 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4119 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4120 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4121 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4122 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4123 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4124 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4125 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4126 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4127 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4128 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4129 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4130 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4131 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4132 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4133 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4134 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4135 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4136 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4137 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4138 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4139 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4140 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4141 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4142 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4143 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4144 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4145 | }; | |
4146 | bfd_reloc_code_real_type r; | |
4147 | size_t i; | |
4148 | ||
4149 | if (!mips_opts.micromips) | |
4150 | return reloc; | |
4151 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4152 | { | |
4153 | r = relocs[i][0]; | |
4154 | if (r > reloc) | |
4155 | return reloc; | |
4156 | if (r == reloc) | |
4157 | return relocs[i][1]; | |
4158 | } | |
4159 | return reloc; | |
4160 | } | |
4161 | ||
b886a2ab RS |
4162 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4163 | Return true on success, storing the resolved value in RESULT. */ | |
4164 | ||
4165 | static bfd_boolean | |
4166 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4167 | offsetT *result) | |
4168 | { | |
4169 | switch (reloc) | |
4170 | { | |
4171 | case BFD_RELOC_MIPS_HIGHEST: | |
4172 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4173 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4174 | return TRUE; | |
4175 | ||
4176 | case BFD_RELOC_MIPS_HIGHER: | |
4177 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4178 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4179 | return TRUE; | |
4180 | ||
4181 | case BFD_RELOC_HI16_S: | |
4182 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4183 | case BFD_RELOC_MIPS16_HI16_S: | |
4184 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4185 | return TRUE; | |
4186 | ||
4187 | case BFD_RELOC_HI16: | |
4188 | case BFD_RELOC_MICROMIPS_HI16: | |
4189 | case BFD_RELOC_MIPS16_HI16: | |
4190 | *result = (operand >> 16) & 0xffff; | |
4191 | return TRUE; | |
4192 | ||
4193 | case BFD_RELOC_LO16: | |
4194 | case BFD_RELOC_MICROMIPS_LO16: | |
4195 | case BFD_RELOC_MIPS16_LO16: | |
4196 | *result = operand & 0xffff; | |
4197 | return TRUE; | |
4198 | ||
4199 | case BFD_RELOC_UNUSED: | |
4200 | *result = operand; | |
4201 | return TRUE; | |
4202 | ||
4203 | default: | |
4204 | return FALSE; | |
4205 | } | |
4206 | } | |
4207 | ||
71400594 RS |
4208 | /* Output an instruction. IP is the instruction information. |
4209 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4210 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4211 | a macro expansion. */ | |
71400594 RS |
4212 | |
4213 | static void | |
4214 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4215 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4216 | { |
14fe068b | 4217 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4218 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4219 | enum append_method method; |
2309ddf2 | 4220 | bfd_boolean relax32; |
2b0c8b40 | 4221 | int branch_disp; |
71400594 | 4222 | |
2309ddf2 | 4223 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4224 | fix_loongson2f (ip); |
4225 | ||
738f4d98 | 4226 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4227 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4228 | |
df58fc94 | 4229 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4230 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4231 | |
4232 | if (mips_opts.micromips | |
4233 | && !expansionp | |
4234 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4235 | && micromips_insn_length (ip->insn_mo) != 2) | |
4236 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4237 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4238 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4239 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4240 | |
15be625d CM |
4241 | if (address_expr == NULL) |
4242 | ip->complete_p = 1; | |
b886a2ab RS |
4243 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4244 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4245 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4246 | && address_expr->X_op == O_constant) |
4247 | { | |
15be625d CM |
4248 | switch (*reloc_type) |
4249 | { | |
15be625d | 4250 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4251 | { |
4252 | int shift; | |
4253 | ||
4254 | shift = mips_opts.micromips ? 1 : 2; | |
4255 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4256 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4257 | (unsigned long) address_expr->X_add_number); | |
4258 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4259 | & 0x3ffffff); | |
335574df | 4260 | ip->complete_p = 1; |
df58fc94 | 4261 | } |
15be625d CM |
4262 | break; |
4263 | ||
4264 | case BFD_RELOC_MIPS16_JMP: | |
4265 | if ((address_expr->X_add_number & 3) != 0) | |
4266 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4267 | (unsigned long) address_expr->X_add_number); | |
4268 | ip->insn_opcode |= | |
4269 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4270 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4271 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4272 | ip->complete_p = 1; |
15be625d CM |
4273 | break; |
4274 | ||
4275 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4276 | { |
4277 | int shift; | |
4278 | ||
4279 | shift = mips_opts.micromips ? 1 : 2; | |
4280 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4281 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4282 | (unsigned long) address_expr->X_add_number); | |
4283 | if (!mips_relax_branch) | |
4284 | { | |
4285 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4286 | & ~((1 << (shift + 16)) - 1)) | |
4287 | as_bad (_("branch address range overflow (0x%lx)"), | |
4288 | (unsigned long) address_expr->X_add_number); | |
4289 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4290 | & 0xffff); | |
4291 | } | |
df58fc94 | 4292 | } |
15be625d CM |
4293 | break; |
4294 | ||
4295 | default: | |
b886a2ab RS |
4296 | { |
4297 | offsetT value; | |
4298 | ||
4299 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4300 | &value)) | |
4301 | { | |
4302 | ip->insn_opcode |= value & 0xffff; | |
4303 | ip->complete_p = 1; | |
4304 | } | |
4305 | } | |
4306 | break; | |
4307 | } | |
15be625d CM |
4308 | } |
4309 | ||
71400594 RS |
4310 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4311 | { | |
4312 | /* There are a lot of optimizations we could do that we don't. | |
4313 | In particular, we do not, in general, reorder instructions. | |
4314 | If you use gcc with optimization, it will reorder | |
4315 | instructions and generally do much more optimization then we | |
4316 | do here; repeating all that work in the assembler would only | |
4317 | benefit hand written assembly code, and does not seem worth | |
4318 | it. */ | |
4319 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4320 | ? nops_for_insn (0, history, NULL) |
4321 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4322 | if (nops > 0) |
252b5132 RH |
4323 | { |
4324 | fragS *old_frag; | |
4325 | unsigned long old_frag_offset; | |
4326 | int i; | |
252b5132 RH |
4327 | |
4328 | old_frag = frag_now; | |
4329 | old_frag_offset = frag_now_fix (); | |
4330 | ||
4331 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4332 | add_fixed_insn (NOP_INSN); |
4333 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4334 | |
4335 | if (listing) | |
4336 | { | |
4337 | listing_prev_line (); | |
4338 | /* We may be at the start of a variant frag. In case we | |
4339 | are, make sure there is enough space for the frag | |
4340 | after the frags created by listing_prev_line. The | |
4341 | argument to frag_grow here must be at least as large | |
4342 | as the argument to all other calls to frag_grow in | |
4343 | this file. We don't have to worry about being in the | |
4344 | middle of a variant frag, because the variants insert | |
4345 | all needed nop instructions themselves. */ | |
4346 | frag_grow (40); | |
4347 | } | |
4348 | ||
462427c4 | 4349 | mips_move_text_labels (); |
252b5132 RH |
4350 | |
4351 | #ifndef NO_ECOFF_DEBUGGING | |
4352 | if (ECOFF_DEBUGGING) | |
4353 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4354 | #endif | |
4355 | } | |
71400594 RS |
4356 | } |
4357 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4358 | { | |
932d1a1b RS |
4359 | int nops; |
4360 | ||
4361 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4362 | ignoring hazards generated by the first prev_nop_frag_since | |
4363 | instructions. */ | |
4364 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4365 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4366 | |
71400594 RS |
4367 | /* Enforce NOPS as a minimum. */ |
4368 | if (nops > prev_nop_frag_required) | |
4369 | prev_nop_frag_required = nops; | |
252b5132 | 4370 | |
71400594 RS |
4371 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4372 | { | |
4373 | /* Settle for the current number of nops. Update the history | |
4374 | accordingly (for the benefit of any future .set reorder code). */ | |
4375 | prev_nop_frag = NULL; | |
4376 | insert_into_history (prev_nop_frag_since, | |
4377 | prev_nop_frag_holds, NOP_INSN); | |
4378 | } | |
4379 | else | |
4380 | { | |
4381 | /* Allow this instruction to replace one of the nops that was | |
4382 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4383 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4384 | prev_nop_frag_holds--; |
4385 | prev_nop_frag_since++; | |
252b5132 RH |
4386 | } |
4387 | } | |
4388 | ||
e407c74b | 4389 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4390 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4391 | |
58e2ea4d | 4392 | #ifdef OBJ_ELF |
e410add4 RS |
4393 | dwarf2_emit_insn (0); |
4394 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4395 | so "move" the instruction address accordingly. | |
4396 | ||
4397 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4398 | entries. If this instruction is a branch that we are going to swap | |
4399 | with the previous instruction, the two instructions should be | |
4400 | treated as a unit, and the debug information for both instructions | |
4401 | should refer to the start of the branch sequence. Using the | |
4402 | current position is certainly wrong when swapping a 32-bit branch | |
4403 | and a 16-bit delay slot, since the current position would then be | |
4404 | in the middle of a branch. */ | |
4405 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d MR |
4406 | #endif |
4407 | ||
df58fc94 RS |
4408 | relax32 = (mips_relax_branch |
4409 | /* Don't try branch relaxation within .set nomacro, or within | |
4410 | .set noat if we use $at for PIC computations. If it turns | |
4411 | out that the branch was out-of-range, we'll get an error. */ | |
4412 | && !mips_opts.warn_about_macros | |
4413 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4414 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4415 | as they have no complementing branches. */ | |
4416 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4417 | |
4418 | if (!HAVE_CODE_COMPRESSION | |
4419 | && address_expr | |
4420 | && relax32 | |
0b25d3e6 | 4421 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4422 | && delayed_branch_p (ip)) |
4a6a3df4 | 4423 | { |
895921c9 | 4424 | relaxed_branch = TRUE; |
1e915849 RS |
4425 | add_relaxed_insn (ip, (relaxed_branch_length |
4426 | (NULL, NULL, | |
11625dd8 RS |
4427 | uncond_branch_p (ip) ? -1 |
4428 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4429 | : 0)), 4, |
4430 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4431 | (AT, |
11625dd8 RS |
4432 | uncond_branch_p (ip), |
4433 | branch_likely_p (ip), | |
1e915849 RS |
4434 | pinfo & INSN_WRITE_GPR_31, |
4435 | 0), | |
4436 | address_expr->X_add_symbol, | |
4437 | address_expr->X_add_number); | |
4a6a3df4 AO |
4438 | *reloc_type = BFD_RELOC_UNUSED; |
4439 | } | |
df58fc94 RS |
4440 | else if (mips_opts.micromips |
4441 | && address_expr | |
4442 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4443 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4444 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4445 | /* Don't try branch relaxation when users specify | |
4446 | 16-bit/32-bit instructions. */ | |
4447 | && !forced_insn_length) | |
df58fc94 RS |
4448 | { |
4449 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4450 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4451 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4452 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4453 | int al = pinfo & INSN_WRITE_GPR_31; |
4454 | int length32; | |
4455 | ||
4456 | gas_assert (address_expr != NULL); | |
4457 | gas_assert (!mips_relax.sequence); | |
4458 | ||
2b0c8b40 | 4459 | relaxed_branch = TRUE; |
df58fc94 RS |
4460 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4461 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4462 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4463 | relax32, 0, 0), | |
df58fc94 RS |
4464 | address_expr->X_add_symbol, |
4465 | address_expr->X_add_number); | |
4466 | *reloc_type = BFD_RELOC_UNUSED; | |
4467 | } | |
4468 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4469 | { |
4470 | /* We need to set up a variant frag. */ | |
df58fc94 | 4471 | gas_assert (address_expr != NULL); |
1e915849 RS |
4472 | add_relaxed_insn (ip, 4, 0, |
4473 | RELAX_MIPS16_ENCODE | |
4474 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4475 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4476 | delayed_branch_p (&history[0]), |
1e915849 RS |
4477 | history[0].mips16_absolute_jump_p), |
4478 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4479 | } |
5c04167a | 4480 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4481 | { |
11625dd8 | 4482 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4483 | /* Make sure there is enough room to swap this instruction with |
4484 | a following jump instruction. */ | |
4485 | frag_grow (6); | |
1e915849 | 4486 | add_fixed_insn (ip); |
252b5132 RH |
4487 | } |
4488 | else | |
4489 | { | |
4490 | if (mips_opts.mips16 | |
4491 | && mips_opts.noreorder | |
11625dd8 | 4492 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4493 | as_warn (_("extended instruction in delay slot")); |
4494 | ||
4d7206a2 RS |
4495 | if (mips_relax.sequence) |
4496 | { | |
4497 | /* If we've reached the end of this frag, turn it into a variant | |
4498 | frag and record the information for the instructions we've | |
4499 | written so far. */ | |
4500 | if (frag_room () < 4) | |
4501 | relax_close_frag (); | |
df58fc94 | 4502 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4503 | } |
4504 | ||
584892a6 | 4505 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4506 | { |
4507 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4508 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4509 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4510 | mips_macro_warning.insns[0]++; | |
4511 | } | |
584892a6 | 4512 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4513 | { |
4514 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4515 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4516 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4517 | mips_macro_warning.insns[1]++; | |
4518 | } | |
584892a6 | 4519 | |
1e915849 RS |
4520 | if (mips_opts.mips16) |
4521 | { | |
4522 | ip->fixed_p = 1; | |
4523 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4524 | } | |
4525 | add_fixed_insn (ip); | |
252b5132 RH |
4526 | } |
4527 | ||
9fe77896 | 4528 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4529 | { |
df58fc94 | 4530 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4531 | reloc_howto_type *howto0; |
9fe77896 RS |
4532 | reloc_howto_type *howto; |
4533 | int i; | |
34ce925e | 4534 | |
df58fc94 RS |
4535 | /* Perform any necessary conversion to microMIPS relocations |
4536 | and find out how many relocations there actually are. */ | |
4537 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4538 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4539 | ||
9fe77896 RS |
4540 | /* In a compound relocation, it is the final (outermost) |
4541 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4542 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4543 | ||
9fe77896 RS |
4544 | if (howto == NULL) |
4545 | { | |
4546 | /* To reproduce this failure try assembling gas/testsuites/ | |
4547 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4548 | assembler. */ | |
df58fc94 RS |
4549 | as_bad (_("Unsupported MIPS relocation number %d"), |
4550 | final_type[i - 1]); | |
9fe77896 RS |
4551 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4552 | } | |
2309ddf2 MR |
4553 | |
4554 | if (i > 1) | |
4555 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4556 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4557 | bfd_get_reloc_size (howto), | |
4558 | address_expr, | |
2309ddf2 MR |
4559 | howto0 && howto0->pc_relative, |
4560 | final_type[0]); | |
9fe77896 RS |
4561 | |
4562 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4563 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4564 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4565 | ||
4566 | /* These relocations can have an addend that won't fit in | |
4567 | 4 octets for 64bit assembly. */ | |
4568 | if (HAVE_64BIT_GPRS | |
4569 | && ! howto->partial_inplace | |
4570 | && (reloc_type[0] == BFD_RELOC_16 | |
4571 | || reloc_type[0] == BFD_RELOC_32 | |
4572 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4573 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4574 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4575 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4576 | || reloc_type[0] == BFD_RELOC_64 | |
4577 | || reloc_type[0] == BFD_RELOC_CTOR | |
4578 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4579 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4580 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4581 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4582 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4583 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4584 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4585 | || hi16_reloc_p (reloc_type[0]) | |
4586 | || lo16_reloc_p (reloc_type[0]))) | |
4587 | ip->fixp[0]->fx_no_overflow = 1; | |
4588 | ||
ddaf2c41 MR |
4589 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4590 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4591 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4592 | ip->fixp[0]->fx_no_overflow = 1; | |
4593 | ||
9fe77896 RS |
4594 | if (mips_relax.sequence) |
4595 | { | |
4596 | if (mips_relax.first_fixup == 0) | |
4597 | mips_relax.first_fixup = ip->fixp[0]; | |
4598 | } | |
4599 | else if (reloc_needs_lo_p (*reloc_type)) | |
4600 | { | |
4601 | struct mips_hi_fixup *hi_fixup; | |
4602 | ||
4603 | /* Reuse the last entry if it already has a matching %lo. */ | |
4604 | hi_fixup = mips_hi_fixup_list; | |
4605 | if (hi_fixup == 0 | |
4606 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4607 | { |
9fe77896 RS |
4608 | hi_fixup = ((struct mips_hi_fixup *) |
4609 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4610 | hi_fixup->next = mips_hi_fixup_list; | |
4611 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4612 | } |
9fe77896 RS |
4613 | hi_fixup->fixp = ip->fixp[0]; |
4614 | hi_fixup->seg = now_seg; | |
4615 | } | |
252b5132 | 4616 | |
9fe77896 RS |
4617 | /* Add fixups for the second and third relocations, if given. |
4618 | Note that the ABI allows the second relocation to be | |
4619 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4620 | moment we only use RSS_UNDEF, but we could add support | |
4621 | for the others if it ever becomes necessary. */ | |
4622 | for (i = 1; i < 3; i++) | |
4623 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4624 | { | |
4625 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4626 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4627 | FALSE, final_type[i]); |
f6688943 | 4628 | |
9fe77896 RS |
4629 | /* Use fx_tcbit to mark compound relocs. */ |
4630 | ip->fixp[0]->fx_tcbit = 1; | |
4631 | ip->fixp[i]->fx_tcbit = 1; | |
4632 | } | |
252b5132 | 4633 | } |
1e915849 | 4634 | install_insn (ip); |
252b5132 RH |
4635 | |
4636 | /* Update the register mask information. */ | |
4c260379 RS |
4637 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4638 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4639 | |
a4e06468 | 4640 | switch (method) |
252b5132 | 4641 | { |
a4e06468 RS |
4642 | case APPEND_ADD: |
4643 | insert_into_history (0, 1, ip); | |
4644 | break; | |
4645 | ||
4646 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4647 | { |
4648 | struct mips_cl_insn *nop; | |
4649 | ||
4650 | insert_into_history (0, 1, ip); | |
4651 | nop = get_delay_slot_nop (ip); | |
4652 | add_fixed_insn (nop); | |
4653 | insert_into_history (0, 1, nop); | |
4654 | if (mips_relax.sequence) | |
4655 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4656 | } | |
a4e06468 RS |
4657 | break; |
4658 | ||
4659 | case APPEND_ADD_COMPACT: | |
4660 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4661 | gas_assert (mips_opts.mips16); | |
4662 | ip->insn_opcode |= 0x0080; | |
4663 | find_altered_mips16_opcode (ip); | |
4664 | install_insn (ip); | |
4665 | insert_into_history (0, 1, ip); | |
4666 | break; | |
4667 | ||
4668 | case APPEND_SWAP: | |
4669 | { | |
4670 | struct mips_cl_insn delay = history[0]; | |
4671 | if (mips_opts.mips16) | |
4672 | { | |
4673 | know (delay.frag == ip->frag); | |
4674 | move_insn (ip, delay.frag, delay.where); | |
4675 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4676 | } | |
464ab0e5 | 4677 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4678 | { |
4679 | /* Add the delay slot instruction to the end of the | |
4680 | current frag and shrink the fixed part of the | |
4681 | original frag. If the branch occupies the tail of | |
4682 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4683 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4684 | if (delay.frag == ip->frag) |
2b0c8b40 | 4685 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4686 | add_fixed_insn (&delay); |
4687 | } | |
4688 | else | |
4689 | { | |
2b0c8b40 MR |
4690 | move_insn (&delay, ip->frag, |
4691 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4692 | move_insn (ip, history[0].frag, history[0].where); |
4693 | } | |
4694 | history[0] = *ip; | |
4695 | delay.fixed_p = 1; | |
4696 | insert_into_history (0, 1, &delay); | |
4697 | } | |
4698 | break; | |
252b5132 RH |
4699 | } |
4700 | ||
13408f1e | 4701 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4702 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4703 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4704 | { |
4705 | unsigned int i; | |
4706 | ||
79850f26 | 4707 | mips_no_prev_insn (); |
13408f1e | 4708 | |
e407c74b | 4709 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4710 | history[i].cleared_p = 1; |
e407c74b NC |
4711 | } |
4712 | ||
df58fc94 RS |
4713 | /* We need to emit a label at the end of branch-likely macros. */ |
4714 | if (emit_branch_likely_macro) | |
4715 | { | |
4716 | emit_branch_likely_macro = FALSE; | |
4717 | micromips_add_label (); | |
4718 | } | |
4719 | ||
252b5132 RH |
4720 | /* We just output an insn, so the next one doesn't have a label. */ |
4721 | mips_clear_insn_labels (); | |
252b5132 RH |
4722 | } |
4723 | ||
e407c74b NC |
4724 | /* Forget that there was any previous instruction or label. |
4725 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4726 | |
4727 | static void | |
7d10b47d | 4728 | mips_no_prev_insn (void) |
252b5132 | 4729 | { |
7d10b47d RS |
4730 | prev_nop_frag = NULL; |
4731 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4732 | mips_clear_insn_labels (); |
4733 | } | |
4734 | ||
7d10b47d RS |
4735 | /* This function must be called before we emit something other than |
4736 | instructions. It is like mips_no_prev_insn except that it inserts | |
4737 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4738 | |
7d10b47d RS |
4739 | void |
4740 | mips_emit_delays (void) | |
252b5132 RH |
4741 | { |
4742 | if (! mips_opts.noreorder) | |
4743 | { | |
932d1a1b | 4744 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4745 | if (nops > 0) |
4746 | { | |
7d10b47d RS |
4747 | while (nops-- > 0) |
4748 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4749 | mips_move_text_labels (); |
7d10b47d RS |
4750 | } |
4751 | } | |
4752 | mips_no_prev_insn (); | |
4753 | } | |
4754 | ||
4755 | /* Start a (possibly nested) noreorder block. */ | |
4756 | ||
4757 | static void | |
4758 | start_noreorder (void) | |
4759 | { | |
4760 | if (mips_opts.noreorder == 0) | |
4761 | { | |
4762 | unsigned int i; | |
4763 | int nops; | |
4764 | ||
4765 | /* None of the instructions before the .set noreorder can be moved. */ | |
4766 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4767 | history[i].fixed_p = 1; | |
4768 | ||
4769 | /* Insert any nops that might be needed between the .set noreorder | |
4770 | block and the previous instructions. We will later remove any | |
4771 | nops that turn out not to be needed. */ | |
932d1a1b | 4772 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4773 | if (nops > 0) |
4774 | { | |
4775 | if (mips_optimize != 0) | |
252b5132 RH |
4776 | { |
4777 | /* Record the frag which holds the nop instructions, so | |
4778 | that we can remove them if we don't need them. */ | |
df58fc94 | 4779 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4780 | prev_nop_frag = frag_now; |
4781 | prev_nop_frag_holds = nops; | |
4782 | prev_nop_frag_required = 0; | |
4783 | prev_nop_frag_since = 0; | |
4784 | } | |
4785 | ||
4786 | for (; nops > 0; --nops) | |
1e915849 | 4787 | add_fixed_insn (NOP_INSN); |
252b5132 | 4788 | |
7d10b47d RS |
4789 | /* Move on to a new frag, so that it is safe to simply |
4790 | decrease the size of prev_nop_frag. */ | |
4791 | frag_wane (frag_now); | |
4792 | frag_new (0); | |
462427c4 | 4793 | mips_move_text_labels (); |
252b5132 | 4794 | } |
df58fc94 | 4795 | mips_mark_labels (); |
7d10b47d | 4796 | mips_clear_insn_labels (); |
252b5132 | 4797 | } |
7d10b47d RS |
4798 | mips_opts.noreorder++; |
4799 | mips_any_noreorder = 1; | |
4800 | } | |
252b5132 | 4801 | |
7d10b47d | 4802 | /* End a nested noreorder block. */ |
252b5132 | 4803 | |
7d10b47d RS |
4804 | static void |
4805 | end_noreorder (void) | |
4806 | { | |
4807 | mips_opts.noreorder--; | |
4808 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4809 | { | |
4810 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4811 | handling nop insertion the .set reorder way. */ | |
4812 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4813 | * NOP_INSN_SIZE); |
7d10b47d RS |
4814 | insert_into_history (prev_nop_frag_since, |
4815 | prev_nop_frag_required, NOP_INSN); | |
4816 | prev_nop_frag = NULL; | |
4817 | } | |
252b5132 RH |
4818 | } |
4819 | ||
584892a6 RS |
4820 | /* Set up global variables for the start of a new macro. */ |
4821 | ||
4822 | static void | |
4823 | macro_start (void) | |
4824 | { | |
4825 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4826 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4827 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4828 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4829 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4830 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4831 | switch (history[0].insn_mo->pinfo2 |
4832 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4833 | { | |
4834 | case INSN2_BRANCH_DELAY_32BIT: | |
4835 | mips_macro_warning.delay_slot_length = 4; | |
4836 | break; | |
4837 | case INSN2_BRANCH_DELAY_16BIT: | |
4838 | mips_macro_warning.delay_slot_length = 2; | |
4839 | break; | |
4840 | default: | |
4841 | mips_macro_warning.delay_slot_length = 0; | |
4842 | break; | |
4843 | } | |
4844 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4845 | } |
4846 | ||
df58fc94 RS |
4847 | /* Given that a macro is longer than one instruction or of the wrong size, |
4848 | return the appropriate warning for it. Return null if no warning is | |
4849 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4850 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4851 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4852 | |
4853 | static const char * | |
4854 | macro_warning (relax_substateT subtype) | |
4855 | { | |
4856 | if (subtype & RELAX_DELAY_SLOT) | |
4857 | return _("Macro instruction expanded into multiple instructions" | |
4858 | " in a branch delay slot"); | |
4859 | else if (subtype & RELAX_NOMACRO) | |
4860 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4861 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4862 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4863 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4864 | ? _("Macro instruction expanded into a wrong size instruction" | |
4865 | " in a 16-bit branch delay slot") | |
4866 | : _("Macro instruction expanded into a wrong size instruction" | |
4867 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4868 | else |
4869 | return 0; | |
4870 | } | |
4871 | ||
4872 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4873 | ||
4874 | static void | |
4875 | macro_end (void) | |
4876 | { | |
df58fc94 RS |
4877 | /* Relaxation warning flags. */ |
4878 | relax_substateT subtype = 0; | |
4879 | ||
4880 | /* Check delay slot size requirements. */ | |
4881 | if (mips_macro_warning.delay_slot_length == 2) | |
4882 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4883 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4884 | { |
df58fc94 RS |
4885 | if (mips_macro_warning.delay_slot_length |
4886 | != mips_macro_warning.first_insn_sizes[0]) | |
4887 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4888 | if (mips_macro_warning.delay_slot_length | |
4889 | != mips_macro_warning.first_insn_sizes[1]) | |
4890 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4891 | } | |
584892a6 | 4892 | |
df58fc94 RS |
4893 | /* Check instruction count requirements. */ |
4894 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4895 | { | |
4896 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4897 | subtype |= RELAX_SECOND_LONGER; |
4898 | if (mips_opts.warn_about_macros) | |
4899 | subtype |= RELAX_NOMACRO; | |
4900 | if (mips_macro_warning.delay_slot_p) | |
4901 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4902 | } |
584892a6 | 4903 | |
df58fc94 RS |
4904 | /* If both alternatives fail to fill a delay slot correctly, |
4905 | emit the warning now. */ | |
4906 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4907 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4908 | { | |
4909 | relax_substateT s; | |
4910 | const char *msg; | |
4911 | ||
4912 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4913 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4914 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4915 | msg = macro_warning (s); | |
4916 | if (msg != NULL) | |
4917 | as_warn ("%s", msg); | |
4918 | subtype &= ~s; | |
4919 | } | |
4920 | ||
4921 | /* If both implementations are longer than 1 instruction, then emit the | |
4922 | warning now. */ | |
4923 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4924 | { | |
4925 | relax_substateT s; | |
4926 | const char *msg; | |
4927 | ||
4928 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4929 | msg = macro_warning (s); | |
4930 | if (msg != NULL) | |
4931 | as_warn ("%s", msg); | |
4932 | subtype &= ~s; | |
584892a6 | 4933 | } |
df58fc94 RS |
4934 | |
4935 | /* If any flags still set, then one implementation might need a warning | |
4936 | and the other either will need one of a different kind or none at all. | |
4937 | Pass any remaining flags over to relaxation. */ | |
4938 | if (mips_macro_warning.first_frag != NULL) | |
4939 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4940 | } |
4941 | ||
df58fc94 RS |
4942 | /* Instruction operand formats used in macros that vary between |
4943 | standard MIPS and microMIPS code. */ | |
4944 | ||
4945 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4946 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4947 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4948 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4949 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4950 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4951 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4952 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4953 | ||
4954 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4955 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4956 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4957 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4958 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4959 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4960 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4961 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4962 | ||
6e1304d8 RS |
4963 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4964 | The first argument in *ARGS will be either the code for a single | |
4965 | relocation or -1 followed by the three codes that make up a | |
4966 | composite relocation. */ | |
4967 | ||
4968 | static void | |
4969 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4970 | { | |
4971 | int i, next; | |
4972 | ||
4973 | next = va_arg (*args, int); | |
4974 | if (next >= 0) | |
4975 | r[0] = (bfd_reloc_code_real_type) next; | |
4976 | else | |
4977 | for (i = 0; i < 3; i++) | |
4978 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4979 | } | |
4980 | ||
252b5132 RH |
4981 | /* Build an instruction created by a macro expansion. This is passed |
4982 | a pointer to the count of instructions created so far, an | |
4983 | expression, the name of the instruction to build, an operand format | |
4984 | string, and corresponding arguments. */ | |
4985 | ||
252b5132 | 4986 | static void |
67c0d1eb | 4987 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4988 | { |
df58fc94 | 4989 | const struct mips_opcode *mo = NULL; |
f6688943 | 4990 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4991 | const struct mips_opcode *amo; |
4992 | struct hash_control *hash; | |
4993 | struct mips_cl_insn insn; | |
252b5132 | 4994 | va_list args; |
252b5132 | 4995 | |
252b5132 | 4996 | va_start (args, fmt); |
252b5132 | 4997 | |
252b5132 RH |
4998 | if (mips_opts.mips16) |
4999 | { | |
03ea81db | 5000 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5001 | va_end (args); |
5002 | return; | |
5003 | } | |
5004 | ||
f6688943 TS |
5005 | r[0] = BFD_RELOC_UNUSED; |
5006 | r[1] = BFD_RELOC_UNUSED; | |
5007 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5008 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5009 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5010 | gas_assert (amo); | |
5011 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5012 | |
df58fc94 | 5013 | do |
8b082fb1 TS |
5014 | { |
5015 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5016 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5017 | We try to match an instruction that fulfils the branch delay | |
5018 | slot instruction length requirement (if any) of the previous | |
5019 | instruction. While doing this we record the first instruction | |
5020 | seen that matches all the other conditions and use it anyway | |
5021 | if the requirement cannot be met; we will issue an appropriate | |
5022 | warning later on. */ | |
5023 | if (strcmp (fmt, amo->args) == 0 | |
5024 | && amo->pinfo != INSN_MACRO | |
5025 | && is_opcode_valid (amo) | |
5026 | && is_size_valid (amo)) | |
5027 | { | |
5028 | if (is_delay_slot_valid (amo)) | |
5029 | { | |
5030 | mo = amo; | |
5031 | break; | |
5032 | } | |
5033 | else if (!mo) | |
5034 | mo = amo; | |
5035 | } | |
8b082fb1 | 5036 | |
df58fc94 RS |
5037 | ++amo; |
5038 | gas_assert (amo->name); | |
252b5132 | 5039 | } |
df58fc94 | 5040 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5041 | |
df58fc94 | 5042 | gas_assert (mo); |
1e915849 | 5043 | create_insn (&insn, mo); |
252b5132 RH |
5044 | for (;;) |
5045 | { | |
5046 | switch (*fmt++) | |
5047 | { | |
5048 | case '\0': | |
5049 | break; | |
5050 | ||
5051 | case ',': | |
5052 | case '(': | |
5053 | case ')': | |
5054 | continue; | |
5055 | ||
5f74bc13 CD |
5056 | case '+': |
5057 | switch (*fmt++) | |
5058 | { | |
5059 | case 'A': | |
5060 | case 'E': | |
df58fc94 RS |
5061 | INSERT_OPERAND (mips_opts.micromips, |
5062 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5063 | continue; |
5064 | ||
5065 | case 'B': | |
5066 | case 'F': | |
5067 | /* Note that in the macro case, these arguments are already | |
5068 | in MSB form. (When handling the instruction in the | |
5069 | non-macro case, these arguments are sizes from which | |
5070 | MSB values must be calculated.) */ | |
df58fc94 RS |
5071 | INSERT_OPERAND (mips_opts.micromips, |
5072 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5073 | continue; |
5074 | ||
b015e599 AP |
5075 | case 'J': |
5076 | gas_assert (!mips_opts.micromips); | |
5077 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5078 | continue; | |
5079 | ||
5f74bc13 CD |
5080 | case 'C': |
5081 | case 'G': | |
5082 | case 'H': | |
5083 | /* Note that in the macro case, these arguments are already | |
5084 | in MSBD form. (When handling the instruction in the | |
5085 | non-macro case, these arguments are sizes from which | |
5086 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5087 | INSERT_OPERAND (mips_opts.micromips, |
5088 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5089 | continue; |
5090 | ||
dd3cbb7e | 5091 | case 'Q': |
df58fc94 RS |
5092 | gas_assert (!mips_opts.micromips); |
5093 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5094 | continue; |
5095 | ||
7f3c4072 CM |
5096 | case 'j': |
5097 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5098 | continue; | |
5099 | ||
5f74bc13 | 5100 | default: |
b37df7c4 | 5101 | abort (); |
5f74bc13 CD |
5102 | } |
5103 | continue; | |
5104 | ||
8b082fb1 | 5105 | case '2': |
03f66e8a | 5106 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5107 | continue; |
5108 | ||
df58fc94 RS |
5109 | case 'n': |
5110 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5111 | case 't': |
5112 | case 'w': | |
5113 | case 'E': | |
df58fc94 | 5114 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5115 | continue; |
5116 | ||
5117 | case 'c': | |
df58fc94 RS |
5118 | gas_assert (!mips_opts.micromips); |
5119 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5120 | continue; |
5121 | ||
252b5132 | 5122 | case 'W': |
df58fc94 RS |
5123 | gas_assert (!mips_opts.micromips); |
5124 | case 'T': | |
5125 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5126 | continue; |
5127 | ||
252b5132 | 5128 | case 'G': |
df58fc94 RS |
5129 | if (mips_opts.micromips) |
5130 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5131 | else | |
5132 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5133 | continue; | |
5134 | ||
af7ee8bf | 5135 | case 'K': |
df58fc94 RS |
5136 | gas_assert (!mips_opts.micromips); |
5137 | case 'd': | |
5138 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5139 | continue; |
5140 | ||
4372b673 | 5141 | case 'U': |
df58fc94 | 5142 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5143 | { |
5144 | int tmp = va_arg (args, int); | |
5145 | ||
df58fc94 RS |
5146 | INSERT_OPERAND (0, RT, insn, tmp); |
5147 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5148 | } |
df58fc94 | 5149 | continue; |
4372b673 | 5150 | |
252b5132 RH |
5151 | case 'V': |
5152 | case 'S': | |
df58fc94 RS |
5153 | gas_assert (!mips_opts.micromips); |
5154 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5155 | continue; |
5156 | ||
5157 | case 'z': | |
5158 | continue; | |
5159 | ||
5160 | case '<': | |
df58fc94 RS |
5161 | INSERT_OPERAND (mips_opts.micromips, |
5162 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5163 | continue; |
5164 | ||
5165 | case 'D': | |
df58fc94 RS |
5166 | gas_assert (!mips_opts.micromips); |
5167 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5168 | continue; |
5169 | ||
5170 | case 'B': | |
df58fc94 RS |
5171 | gas_assert (!mips_opts.micromips); |
5172 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5173 | continue; |
5174 | ||
4372b673 | 5175 | case 'J': |
df58fc94 RS |
5176 | gas_assert (!mips_opts.micromips); |
5177 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5178 | continue; |
5179 | ||
252b5132 | 5180 | case 'q': |
df58fc94 RS |
5181 | gas_assert (!mips_opts.micromips); |
5182 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5183 | continue; |
5184 | ||
5185 | case 'b': | |
5186 | case 's': | |
5187 | case 'r': | |
5188 | case 'v': | |
df58fc94 | 5189 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5190 | continue; |
5191 | ||
5192 | case 'i': | |
5193 | case 'j': | |
6e1304d8 | 5194 | macro_read_relocs (&args, r); |
9c2799c2 | 5195 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5196 | || *r == BFD_RELOC_MIPS_HIGHER |
5197 | || *r == BFD_RELOC_HI16_S | |
5198 | || *r == BFD_RELOC_LO16 | |
5199 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5200 | continue; | |
5201 | ||
5202 | case 'o': | |
5203 | macro_read_relocs (&args, r); | |
252b5132 RH |
5204 | continue; |
5205 | ||
5206 | case 'u': | |
6e1304d8 | 5207 | macro_read_relocs (&args, r); |
9c2799c2 | 5208 | gas_assert (ep != NULL |
90ecf173 MR |
5209 | && (ep->X_op == O_constant |
5210 | || (ep->X_op == O_symbol | |
5211 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5212 | || *r == BFD_RELOC_HI16_S | |
5213 | || *r == BFD_RELOC_HI16 | |
5214 | || *r == BFD_RELOC_GPREL16 | |
5215 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5216 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5217 | continue; |
5218 | ||
5219 | case 'p': | |
9c2799c2 | 5220 | gas_assert (ep != NULL); |
bad36eac | 5221 | |
252b5132 RH |
5222 | /* |
5223 | * This allows macro() to pass an immediate expression for | |
5224 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5225 | * |
5226 | * We don't allow branch relaxation for these branches, as | |
5227 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5228 | */ |
5229 | if (ep->X_op == O_constant) | |
5230 | { | |
df58fc94 RS |
5231 | /* For microMIPS we always use relocations for branches. |
5232 | So we should not resolve immediate values. */ | |
5233 | gas_assert (!mips_opts.micromips); | |
5234 | ||
bad36eac DJ |
5235 | if ((ep->X_add_number & 3) != 0) |
5236 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5237 | (unsigned long) ep->X_add_number); | |
5238 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5239 | as_bad (_("branch address range overflow (0x%lx)"), | |
5240 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5241 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5242 | ep = NULL; | |
5243 | } | |
5244 | else | |
0b25d3e6 | 5245 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5246 | continue; |
5247 | ||
5248 | case 'a': | |
9c2799c2 | 5249 | gas_assert (ep != NULL); |
f6688943 | 5250 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5251 | continue; |
5252 | ||
5253 | case 'C': | |
df58fc94 RS |
5254 | gas_assert (!mips_opts.micromips); |
5255 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5256 | continue; |
5257 | ||
d43b4baf | 5258 | case 'k': |
df58fc94 RS |
5259 | INSERT_OPERAND (mips_opts.micromips, |
5260 | CACHE, insn, va_arg (args, unsigned long)); | |
5261 | continue; | |
5262 | ||
5263 | case '|': | |
5264 | gas_assert (mips_opts.micromips); | |
5265 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5266 | continue; | |
5267 | ||
5268 | case '.': | |
5269 | gas_assert (mips_opts.micromips); | |
5270 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5271 | continue; | |
5272 | ||
dec0624d MR |
5273 | case '\\': |
5274 | INSERT_OPERAND (mips_opts.micromips, | |
5275 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5276 | continue; | |
5277 | ||
df58fc94 | 5278 | case '~': |
dec0624d MR |
5279 | INSERT_OPERAND (mips_opts.micromips, |
5280 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5281 | continue; |
5282 | ||
5283 | case 'N': | |
5284 | gas_assert (mips_opts.micromips); | |
5285 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5286 | continue; | |
5287 | ||
5288 | case 'm': /* Opcode extension character. */ | |
5289 | gas_assert (mips_opts.micromips); | |
5290 | switch (*fmt++) | |
5291 | { | |
5292 | case 'j': | |
5293 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5294 | break; | |
5295 | ||
5296 | case 'p': | |
5297 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5298 | break; | |
5299 | ||
5300 | case 'F': | |
5301 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5302 | break; | |
5303 | ||
5304 | default: | |
b37df7c4 | 5305 | abort (); |
df58fc94 | 5306 | } |
d43b4baf TS |
5307 | continue; |
5308 | ||
252b5132 | 5309 | default: |
b37df7c4 | 5310 | abort (); |
252b5132 RH |
5311 | } |
5312 | break; | |
5313 | } | |
5314 | va_end (args); | |
9c2799c2 | 5315 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5316 | |
df58fc94 | 5317 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5318 | } |
5319 | ||
5320 | static void | |
67c0d1eb | 5321 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5322 | va_list *args) |
252b5132 | 5323 | { |
1e915849 | 5324 | struct mips_opcode *mo; |
252b5132 | 5325 | struct mips_cl_insn insn; |
f6688943 TS |
5326 | bfd_reloc_code_real_type r[3] |
5327 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5328 | |
1e915849 | 5329 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5330 | gas_assert (mo); |
5331 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5332 | |
1e915849 | 5333 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5334 | { |
1e915849 | 5335 | ++mo; |
9c2799c2 NC |
5336 | gas_assert (mo->name); |
5337 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5338 | } |
5339 | ||
1e915849 | 5340 | create_insn (&insn, mo); |
252b5132 RH |
5341 | for (;;) |
5342 | { | |
5343 | int c; | |
5344 | ||
5345 | c = *fmt++; | |
5346 | switch (c) | |
5347 | { | |
5348 | case '\0': | |
5349 | break; | |
5350 | ||
5351 | case ',': | |
5352 | case '(': | |
5353 | case ')': | |
5354 | continue; | |
5355 | ||
5356 | case 'y': | |
5357 | case 'w': | |
03ea81db | 5358 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5359 | continue; |
5360 | ||
5361 | case 'x': | |
5362 | case 'v': | |
03ea81db | 5363 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5364 | continue; |
5365 | ||
5366 | case 'z': | |
03ea81db | 5367 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5368 | continue; |
5369 | ||
5370 | case 'Z': | |
03ea81db | 5371 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5372 | continue; |
5373 | ||
5374 | case '0': | |
5375 | case 'S': | |
5376 | case 'P': | |
5377 | case 'R': | |
5378 | continue; | |
5379 | ||
5380 | case 'X': | |
03ea81db | 5381 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5382 | continue; |
5383 | ||
5384 | case 'Y': | |
5385 | { | |
5386 | int regno; | |
5387 | ||
03ea81db | 5388 | regno = va_arg (*args, int); |
252b5132 | 5389 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5390 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5391 | } |
5392 | continue; | |
5393 | ||
5394 | case '<': | |
5395 | case '>': | |
5396 | case '4': | |
5397 | case '5': | |
5398 | case 'H': | |
5399 | case 'W': | |
5400 | case 'D': | |
5401 | case 'j': | |
5402 | case '8': | |
5403 | case 'V': | |
5404 | case 'C': | |
5405 | case 'U': | |
5406 | case 'k': | |
5407 | case 'K': | |
5408 | case 'p': | |
5409 | case 'q': | |
5410 | { | |
b886a2ab RS |
5411 | offsetT value; |
5412 | ||
9c2799c2 | 5413 | gas_assert (ep != NULL); |
252b5132 RH |
5414 | |
5415 | if (ep->X_op != O_constant) | |
874e8986 | 5416 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5417 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5418 | { |
b886a2ab | 5419 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5420 | ep = NULL; |
f6688943 | 5421 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5422 | } |
5423 | } | |
5424 | continue; | |
5425 | ||
5426 | case '6': | |
03ea81db | 5427 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5428 | continue; |
5429 | } | |
5430 | ||
5431 | break; | |
5432 | } | |
5433 | ||
9c2799c2 | 5434 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5435 | |
df58fc94 | 5436 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5437 | } |
5438 | ||
2051e8c4 MR |
5439 | /* |
5440 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5441 | * higher bits unset. | |
5442 | */ | |
9f872bbe | 5443 | static void |
2051e8c4 MR |
5444 | normalize_constant_expr (expressionS *ex) |
5445 | { | |
9ee2a2d4 | 5446 | if (ex->X_op == O_constant |
2051e8c4 MR |
5447 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5448 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5449 | - 0x80000000); | |
5450 | } | |
5451 | ||
5452 | /* | |
5453 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5454 | * all higher bits unset. | |
5455 | */ | |
5456 | static void | |
5457 | normalize_address_expr (expressionS *ex) | |
5458 | { | |
5459 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5460 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5461 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5462 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5463 | - 0x80000000); | |
5464 | } | |
5465 | ||
438c16b8 TS |
5466 | /* |
5467 | * Generate a "jalr" instruction with a relocation hint to the called | |
5468 | * function. This occurs in NewABI PIC code. | |
5469 | */ | |
5470 | static void | |
df58fc94 | 5471 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5472 | { |
df58fc94 RS |
5473 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5474 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5475 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5476 | const char *jalr; | |
685736be | 5477 | char *f = NULL; |
b34976b6 | 5478 | |
1180b5a4 | 5479 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5480 | { |
cc3d92a5 | 5481 | frag_grow (8); |
f21f8242 AO |
5482 | f = frag_more (0); |
5483 | } | |
2906b037 | 5484 | if (mips_opts.micromips) |
df58fc94 RS |
5485 | { |
5486 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5487 | if (MIPS_JALR_HINT_P (ep) |
5488 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5489 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5490 | else | |
5491 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5492 | } | |
2906b037 MR |
5493 | else |
5494 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5495 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5496 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5497 | } |
5498 | ||
252b5132 RH |
5499 | /* |
5500 | * Generate a "lui" instruction. | |
5501 | */ | |
5502 | static void | |
67c0d1eb | 5503 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5504 | { |
9c2799c2 | 5505 | gas_assert (! mips_opts.mips16); |
252b5132 | 5506 | |
df58fc94 | 5507 | if (ep->X_op != O_constant) |
252b5132 | 5508 | { |
9c2799c2 | 5509 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5510 | /* _gp_disp is a special case, used from s_cpload. |
5511 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5512 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5513 | || (! HAVE_NEWABI |
aa6975fb ILT |
5514 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5515 | || (! mips_in_shared | |
bbe506e8 TS |
5516 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5517 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5518 | } |
5519 | ||
df58fc94 | 5520 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5521 | } |
5522 | ||
885add95 CD |
5523 | /* Generate a sequence of instructions to do a load or store from a constant |
5524 | offset off of a base register (breg) into/from a target register (treg), | |
5525 | using AT if necessary. */ | |
5526 | static void | |
67c0d1eb RS |
5527 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5528 | int treg, int breg, int dbl) | |
885add95 | 5529 | { |
9c2799c2 | 5530 | gas_assert (ep->X_op == O_constant); |
885add95 | 5531 | |
256ab948 | 5532 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5533 | if (!dbl) |
5534 | normalize_constant_expr (ep); | |
256ab948 | 5535 | |
67c1ffbe | 5536 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5537 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5538 | as_warn (_("operand overflow")); |
5539 | ||
5540 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5541 | { | |
5542 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5543 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5544 | } |
5545 | else | |
5546 | { | |
5547 | /* 32-bit offset, need multiple instructions and AT, like: | |
5548 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5549 | addu $tempreg,$tempreg,$breg | |
5550 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5551 | to handle the complete offset. */ | |
67c0d1eb RS |
5552 | macro_build_lui (ep, AT); |
5553 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5554 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5555 | |
741fe287 | 5556 | if (!mips_opts.at) |
8fc2e39e | 5557 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5558 | } |
5559 | } | |
5560 | ||
252b5132 RH |
5561 | /* set_at() |
5562 | * Generates code to set the $at register to true (one) | |
5563 | * if reg is less than the immediate expression. | |
5564 | */ | |
5565 | static void | |
67c0d1eb | 5566 | set_at (int reg, int unsignedp) |
252b5132 RH |
5567 | { |
5568 | if (imm_expr.X_op == O_constant | |
5569 | && imm_expr.X_add_number >= -0x8000 | |
5570 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5571 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5572 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5573 | else |
5574 | { | |
67c0d1eb RS |
5575 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5576 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5577 | } |
5578 | } | |
5579 | ||
5580 | /* Warn if an expression is not a constant. */ | |
5581 | ||
5582 | static void | |
17a2f251 | 5583 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5584 | { |
5585 | if (ex->X_op == O_big) | |
5586 | as_bad (_("unsupported large constant")); | |
5587 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5588 | as_bad (_("Instruction %s requires absolute expression"), |
5589 | ip->insn_mo->name); | |
13757d0c | 5590 | |
9ee2a2d4 MR |
5591 | if (HAVE_32BIT_GPRS) |
5592 | normalize_constant_expr (ex); | |
252b5132 RH |
5593 | } |
5594 | ||
5595 | /* Count the leading zeroes by performing a binary chop. This is a | |
5596 | bulky bit of source, but performance is a LOT better for the | |
5597 | majority of values than a simple loop to count the bits: | |
5598 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5599 | if ((v) & (1 << (31 - lcnt))) | |
5600 | break; | |
5601 | However it is not code size friendly, and the gain will drop a bit | |
5602 | on certain cached systems. | |
5603 | */ | |
5604 | #define COUNT_TOP_ZEROES(v) \ | |
5605 | (((v) & ~0xffff) == 0 \ | |
5606 | ? ((v) & ~0xff) == 0 \ | |
5607 | ? ((v) & ~0xf) == 0 \ | |
5608 | ? ((v) & ~0x3) == 0 \ | |
5609 | ? ((v) & ~0x1) == 0 \ | |
5610 | ? !(v) \ | |
5611 | ? 32 \ | |
5612 | : 31 \ | |
5613 | : 30 \ | |
5614 | : ((v) & ~0x7) == 0 \ | |
5615 | ? 29 \ | |
5616 | : 28 \ | |
5617 | : ((v) & ~0x3f) == 0 \ | |
5618 | ? ((v) & ~0x1f) == 0 \ | |
5619 | ? 27 \ | |
5620 | : 26 \ | |
5621 | : ((v) & ~0x7f) == 0 \ | |
5622 | ? 25 \ | |
5623 | : 24 \ | |
5624 | : ((v) & ~0xfff) == 0 \ | |
5625 | ? ((v) & ~0x3ff) == 0 \ | |
5626 | ? ((v) & ~0x1ff) == 0 \ | |
5627 | ? 23 \ | |
5628 | : 22 \ | |
5629 | : ((v) & ~0x7ff) == 0 \ | |
5630 | ? 21 \ | |
5631 | : 20 \ | |
5632 | : ((v) & ~0x3fff) == 0 \ | |
5633 | ? ((v) & ~0x1fff) == 0 \ | |
5634 | ? 19 \ | |
5635 | : 18 \ | |
5636 | : ((v) & ~0x7fff) == 0 \ | |
5637 | ? 17 \ | |
5638 | : 16 \ | |
5639 | : ((v) & ~0xffffff) == 0 \ | |
5640 | ? ((v) & ~0xfffff) == 0 \ | |
5641 | ? ((v) & ~0x3ffff) == 0 \ | |
5642 | ? ((v) & ~0x1ffff) == 0 \ | |
5643 | ? 15 \ | |
5644 | : 14 \ | |
5645 | : ((v) & ~0x7ffff) == 0 \ | |
5646 | ? 13 \ | |
5647 | : 12 \ | |
5648 | : ((v) & ~0x3fffff) == 0 \ | |
5649 | ? ((v) & ~0x1fffff) == 0 \ | |
5650 | ? 11 \ | |
5651 | : 10 \ | |
5652 | : ((v) & ~0x7fffff) == 0 \ | |
5653 | ? 9 \ | |
5654 | : 8 \ | |
5655 | : ((v) & ~0xfffffff) == 0 \ | |
5656 | ? ((v) & ~0x3ffffff) == 0 \ | |
5657 | ? ((v) & ~0x1ffffff) == 0 \ | |
5658 | ? 7 \ | |
5659 | : 6 \ | |
5660 | : ((v) & ~0x7ffffff) == 0 \ | |
5661 | ? 5 \ | |
5662 | : 4 \ | |
5663 | : ((v) & ~0x3fffffff) == 0 \ | |
5664 | ? ((v) & ~0x1fffffff) == 0 \ | |
5665 | ? 3 \ | |
5666 | : 2 \ | |
5667 | : ((v) & ~0x7fffffff) == 0 \ | |
5668 | ? 1 \ | |
5669 | : 0) | |
5670 | ||
5671 | /* load_register() | |
67c1ffbe | 5672 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5673 | * an absolute expression value into a register. |
5674 | */ | |
5675 | static void | |
67c0d1eb | 5676 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5677 | { |
5678 | int freg; | |
5679 | expressionS hi32, lo32; | |
5680 | ||
5681 | if (ep->X_op != O_big) | |
5682 | { | |
9c2799c2 | 5683 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5684 | |
5685 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5686 | if (!dbl) |
5687 | normalize_constant_expr (ep); | |
256ab948 TS |
5688 | |
5689 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5690 | { |
5691 | /* We can handle 16 bit signed values with an addiu to | |
5692 | $zero. No need to ever use daddiu here, since $zero and | |
5693 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5694 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5695 | return; |
5696 | } | |
5697 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5698 | { | |
5699 | /* We can handle 16 bit unsigned values with an ori to | |
5700 | $zero. */ | |
67c0d1eb | 5701 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5702 | return; |
5703 | } | |
256ab948 | 5704 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5705 | { |
5706 | /* 32 bit values require an lui. */ | |
df58fc94 | 5707 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5708 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5709 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5710 | return; |
5711 | } | |
5712 | } | |
5713 | ||
5714 | /* The value is larger than 32 bits. */ | |
5715 | ||
2051e8c4 | 5716 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5717 | { |
55e08f71 NC |
5718 | char value[32]; |
5719 | ||
5720 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5721 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5722 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5723 | return; |
5724 | } | |
5725 | ||
5726 | if (ep->X_op != O_big) | |
5727 | { | |
5728 | hi32 = *ep; | |
5729 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5730 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5731 | hi32.X_add_number &= 0xffffffff; | |
5732 | lo32 = *ep; | |
5733 | lo32.X_add_number &= 0xffffffff; | |
5734 | } | |
5735 | else | |
5736 | { | |
9c2799c2 | 5737 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5738 | if (ep->X_add_number == 3) |
5739 | generic_bignum[3] = 0; | |
5740 | else if (ep->X_add_number > 4) | |
5741 | as_bad (_("Number larger than 64 bits")); | |
5742 | lo32.X_op = O_constant; | |
5743 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5744 | hi32.X_op = O_constant; | |
5745 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5746 | } | |
5747 | ||
5748 | if (hi32.X_add_number == 0) | |
5749 | freg = 0; | |
5750 | else | |
5751 | { | |
5752 | int shift, bit; | |
5753 | unsigned long hi, lo; | |
5754 | ||
956cd1d6 | 5755 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5756 | { |
5757 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5758 | { | |
67c0d1eb | 5759 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5760 | return; |
5761 | } | |
5762 | if (lo32.X_add_number & 0x80000000) | |
5763 | { | |
df58fc94 | 5764 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5765 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5766 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5767 | return; |
5768 | } | |
5769 | } | |
252b5132 RH |
5770 | |
5771 | /* Check for 16bit shifted constant. We know that hi32 is | |
5772 | non-zero, so start the mask on the first bit of the hi32 | |
5773 | value. */ | |
5774 | shift = 17; | |
5775 | do | |
beae10d5 KH |
5776 | { |
5777 | unsigned long himask, lomask; | |
5778 | ||
5779 | if (shift < 32) | |
5780 | { | |
5781 | himask = 0xffff >> (32 - shift); | |
5782 | lomask = (0xffff << shift) & 0xffffffff; | |
5783 | } | |
5784 | else | |
5785 | { | |
5786 | himask = 0xffff << (shift - 32); | |
5787 | lomask = 0; | |
5788 | } | |
5789 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5790 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5791 | { | |
5792 | expressionS tmp; | |
5793 | ||
5794 | tmp.X_op = O_constant; | |
5795 | if (shift < 32) | |
5796 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5797 | | (lo32.X_add_number >> shift)); | |
5798 | else | |
5799 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5800 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5801 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5802 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5803 | return; |
5804 | } | |
f9419b05 | 5805 | ++shift; |
beae10d5 KH |
5806 | } |
5807 | while (shift <= (64 - 16)); | |
252b5132 RH |
5808 | |
5809 | /* Find the bit number of the lowest one bit, and store the | |
5810 | shifted value in hi/lo. */ | |
5811 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5812 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5813 | if (lo != 0) | |
5814 | { | |
5815 | bit = 0; | |
5816 | while ((lo & 1) == 0) | |
5817 | { | |
5818 | lo >>= 1; | |
5819 | ++bit; | |
5820 | } | |
5821 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5822 | hi >>= bit; | |
5823 | } | |
5824 | else | |
5825 | { | |
5826 | bit = 32; | |
5827 | while ((hi & 1) == 0) | |
5828 | { | |
5829 | hi >>= 1; | |
5830 | ++bit; | |
5831 | } | |
5832 | lo = hi; | |
5833 | hi = 0; | |
5834 | } | |
5835 | ||
5836 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5837 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5838 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5839 | { |
5840 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5841 | if (shift != 0) |
beae10d5 | 5842 | { |
252b5132 RH |
5843 | expressionS tmp; |
5844 | ||
5845 | /* This instruction will set the register to be all | |
5846 | ones. */ | |
beae10d5 KH |
5847 | tmp.X_op = O_constant; |
5848 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5849 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5850 | if (bit != 0) |
5851 | { | |
5852 | bit += shift; | |
df58fc94 | 5853 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5854 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5855 | } |
df58fc94 | 5856 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5857 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5858 | return; |
5859 | } | |
5860 | } | |
252b5132 RH |
5861 | |
5862 | /* Sign extend hi32 before calling load_register, because we can | |
5863 | generally get better code when we load a sign extended value. */ | |
5864 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5865 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5866 | load_register (reg, &hi32, 0); |
252b5132 RH |
5867 | freg = reg; |
5868 | } | |
5869 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5870 | { | |
5871 | if (freg != 0) | |
5872 | { | |
df58fc94 | 5873 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5874 | freg = reg; |
5875 | } | |
5876 | } | |
5877 | else | |
5878 | { | |
5879 | expressionS mid16; | |
5880 | ||
956cd1d6 | 5881 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5882 | { |
df58fc94 RS |
5883 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5884 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5885 | return; |
5886 | } | |
252b5132 RH |
5887 | |
5888 | if (freg != 0) | |
5889 | { | |
df58fc94 | 5890 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5891 | freg = reg; |
5892 | } | |
5893 | mid16 = lo32; | |
5894 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5895 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5896 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5897 | freg = reg; |
5898 | } | |
5899 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5900 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5901 | } |
5902 | ||
269137b2 TS |
5903 | static inline void |
5904 | load_delay_nop (void) | |
5905 | { | |
5906 | if (!gpr_interlocks) | |
5907 | macro_build (NULL, "nop", ""); | |
5908 | } | |
5909 | ||
252b5132 RH |
5910 | /* Load an address into a register. */ |
5911 | ||
5912 | static void | |
67c0d1eb | 5913 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5914 | { |
252b5132 RH |
5915 | if (ep->X_op != O_constant |
5916 | && ep->X_op != O_symbol) | |
5917 | { | |
5918 | as_bad (_("expression too complex")); | |
5919 | ep->X_op = O_constant; | |
5920 | } | |
5921 | ||
5922 | if (ep->X_op == O_constant) | |
5923 | { | |
67c0d1eb | 5924 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5925 | return; |
5926 | } | |
5927 | ||
5928 | if (mips_pic == NO_PIC) | |
5929 | { | |
5930 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5931 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5932 | Otherwise we want |
5933 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5934 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5935 | If we have an addend, we always use the latter form. |
76b3015f | 5936 | |
d6bc6245 TS |
5937 | With 64bit address space and a usable $at we want |
5938 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5939 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5940 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5941 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5942 | dsll32 $reg,0 | |
3a482fd5 | 5943 | daddu $reg,$reg,$at |
76b3015f | 5944 | |
c03099e6 | 5945 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5946 | on superscalar processors. |
5947 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5948 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5949 | dsll $reg,16 | |
5950 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5951 | dsll $reg,16 | |
5952 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5953 | |
5954 | For GP relative symbols in 64bit address space we can use | |
5955 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5956 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5957 | { |
6caf9ef4 TS |
5958 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5959 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5960 | { | |
5961 | relax_start (ep->X_add_symbol); | |
5962 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5963 | mips_gp_register, BFD_RELOC_GPREL16); | |
5964 | relax_switch (); | |
5965 | } | |
d6bc6245 | 5966 | |
741fe287 | 5967 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5968 | { |
df58fc94 RS |
5969 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5970 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5971 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5972 | BFD_RELOC_MIPS_HIGHER); | |
5973 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5974 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5975 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5976 | *used_at = 1; |
5977 | } | |
5978 | else | |
5979 | { | |
df58fc94 | 5980 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5981 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5982 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5983 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5984 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5985 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5986 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5987 | } |
6caf9ef4 TS |
5988 | |
5989 | if (mips_relax.sequence) | |
5990 | relax_end (); | |
d6bc6245 | 5991 | } |
252b5132 RH |
5992 | else |
5993 | { | |
d6bc6245 | 5994 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5995 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5996 | { |
4d7206a2 | 5997 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5998 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5999 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6000 | relax_switch (); |
d6bc6245 | 6001 | } |
67c0d1eb RS |
6002 | macro_build_lui (ep, reg); |
6003 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6004 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6005 | if (mips_relax.sequence) |
6006 | relax_end (); | |
d6bc6245 | 6007 | } |
252b5132 | 6008 | } |
0a44bf69 | 6009 | else if (!mips_big_got) |
252b5132 RH |
6010 | { |
6011 | expressionS ex; | |
6012 | ||
6013 | /* If this is a reference to an external symbol, we want | |
6014 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6015 | Otherwise we want | |
6016 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6017 | nop | |
6018 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6019 | If there is a constant, it must be added in after. |
6020 | ||
ed6fb7bd | 6021 | If we have NewABI, we want |
f5040a92 AO |
6022 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6023 | unless we're referencing a global symbol with a non-zero | |
6024 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6025 | if (HAVE_NEWABI) |
6026 | { | |
f5040a92 AO |
6027 | if (ep->X_add_number) |
6028 | { | |
4d7206a2 | 6029 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6030 | ep->X_add_number = 0; |
4d7206a2 | 6031 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6032 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6033 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6034 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6035 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6036 | ex.X_op = O_constant; | |
67c0d1eb | 6037 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6038 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6039 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6040 | relax_switch (); |
f5040a92 | 6041 | } |
67c0d1eb | 6042 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6043 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6044 | if (mips_relax.sequence) |
6045 | relax_end (); | |
ed6fb7bd SC |
6046 | } |
6047 | else | |
6048 | { | |
f5040a92 AO |
6049 | ex.X_add_number = ep->X_add_number; |
6050 | ep->X_add_number = 0; | |
67c0d1eb RS |
6051 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6052 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6053 | load_delay_nop (); |
4d7206a2 RS |
6054 | relax_start (ep->X_add_symbol); |
6055 | relax_switch (); | |
67c0d1eb | 6056 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6057 | BFD_RELOC_LO16); |
4d7206a2 | 6058 | relax_end (); |
ed6fb7bd | 6059 | |
f5040a92 AO |
6060 | if (ex.X_add_number != 0) |
6061 | { | |
6062 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6063 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6064 | ex.X_op = O_constant; | |
67c0d1eb | 6065 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6066 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6067 | } |
252b5132 RH |
6068 | } |
6069 | } | |
0a44bf69 | 6070 | else if (mips_big_got) |
252b5132 RH |
6071 | { |
6072 | expressionS ex; | |
252b5132 RH |
6073 | |
6074 | /* This is the large GOT case. If this is a reference to an | |
6075 | external symbol, we want | |
6076 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6077 | addu $reg,$reg,$gp | |
6078 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6079 | |
6080 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6081 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6082 | nop | |
6083 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6084 | If there is a constant, it must be added in after. |
f5040a92 AO |
6085 | |
6086 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6087 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6088 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6089 | */ |
438c16b8 TS |
6090 | if (HAVE_NEWABI) |
6091 | { | |
4d7206a2 | 6092 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6093 | ep->X_add_number = 0; |
4d7206a2 | 6094 | relax_start (ep->X_add_symbol); |
df58fc94 | 6095 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6096 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6097 | reg, reg, mips_gp_register); | |
6098 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6099 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6100 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6101 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6102 | else if (ex.X_add_number) | |
6103 | { | |
6104 | ex.X_op = O_constant; | |
67c0d1eb RS |
6105 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6106 | BFD_RELOC_LO16); | |
f5040a92 AO |
6107 | } |
6108 | ||
6109 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6110 | relax_switch (); |
67c0d1eb | 6111 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6112 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6113 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6114 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6115 | relax_end (); |
438c16b8 | 6116 | } |
252b5132 | 6117 | else |
438c16b8 | 6118 | { |
f5040a92 AO |
6119 | ex.X_add_number = ep->X_add_number; |
6120 | ep->X_add_number = 0; | |
4d7206a2 | 6121 | relax_start (ep->X_add_symbol); |
df58fc94 | 6122 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6123 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6124 | reg, reg, mips_gp_register); | |
6125 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6126 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6127 | relax_switch (); |
6128 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6129 | { |
6130 | /* We need a nop before loading from $gp. This special | |
6131 | check is required because the lui which starts the main | |
6132 | instruction stream does not refer to $gp, and so will not | |
6133 | insert the nop which may be required. */ | |
67c0d1eb | 6134 | macro_build (NULL, "nop", ""); |
438c16b8 | 6135 | } |
67c0d1eb | 6136 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6137 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6138 | load_delay_nop (); |
67c0d1eb | 6139 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6140 | BFD_RELOC_LO16); |
4d7206a2 | 6141 | relax_end (); |
438c16b8 | 6142 | |
f5040a92 AO |
6143 | if (ex.X_add_number != 0) |
6144 | { | |
6145 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6146 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6147 | ex.X_op = O_constant; | |
67c0d1eb RS |
6148 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6149 | BFD_RELOC_LO16); | |
f5040a92 | 6150 | } |
252b5132 RH |
6151 | } |
6152 | } | |
252b5132 RH |
6153 | else |
6154 | abort (); | |
8fc2e39e | 6155 | |
741fe287 | 6156 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6157 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6158 | } |
6159 | ||
ea1fb5dc RS |
6160 | /* Move the contents of register SOURCE into register DEST. */ |
6161 | ||
6162 | static void | |
67c0d1eb | 6163 | move_register (int dest, int source) |
ea1fb5dc | 6164 | { |
df58fc94 RS |
6165 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6166 | instruction specifically requires a 32-bit one. */ | |
6167 | if (mips_opts.micromips | |
6168 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6169 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6170 | else |
6171 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6172 | dest, source, 0); | |
ea1fb5dc RS |
6173 | } |
6174 | ||
4d7206a2 | 6175 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6176 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6177 | The two alternatives are: | |
4d7206a2 RS |
6178 | |
6179 | Global symbol Local sybmol | |
6180 | ------------- ------------ | |
6181 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6182 | ... ... | |
6183 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6184 | ||
6185 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6186 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6187 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6188 | |
6189 | static void | |
67c0d1eb | 6190 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6191 | { |
6192 | expressionS global; | |
6193 | ||
6194 | global = *local; | |
6195 | global.X_add_number = 0; | |
6196 | ||
6197 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6198 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6199 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6200 | relax_switch (); |
67c0d1eb RS |
6201 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6202 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6203 | relax_end (); |
6204 | } | |
6205 | ||
6206 | static void | |
67c0d1eb | 6207 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6208 | { |
6209 | expressionS global; | |
6210 | ||
6211 | global.X_op = O_constant; | |
6212 | global.X_op_symbol = NULL; | |
6213 | global.X_add_symbol = NULL; | |
6214 | global.X_add_number = local->X_add_number; | |
6215 | ||
6216 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6217 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6218 | dest, dest, BFD_RELOC_LO16); |
6219 | relax_switch (); | |
67c0d1eb | 6220 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6221 | relax_end (); |
6222 | } | |
6223 | ||
f6a22291 MR |
6224 | static void |
6225 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6226 | { | |
6227 | expressionS global; | |
6228 | int hold_mips_optimize; | |
6229 | ||
6230 | global.X_op = O_constant; | |
6231 | global.X_op_symbol = NULL; | |
6232 | global.X_add_symbol = NULL; | |
6233 | global.X_add_number = local->X_add_number; | |
6234 | ||
6235 | relax_start (local->X_add_symbol); | |
6236 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6237 | relax_switch (); | |
6238 | /* Set mips_optimize around the lui instruction to avoid | |
6239 | inserting an unnecessary nop after the lw. */ | |
6240 | hold_mips_optimize = mips_optimize; | |
6241 | mips_optimize = 2; | |
6242 | macro_build_lui (&global, tmp); | |
6243 | mips_optimize = hold_mips_optimize; | |
6244 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6245 | relax_end (); | |
6246 | ||
6247 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6248 | } | |
6249 | ||
df58fc94 RS |
6250 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6251 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6252 | is its complementing branch with the original condition negated. | |
6253 | CALL is set if the original branch specified the link operation. | |
6254 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6255 | ||
6256 | Code like this is produced in the noreorder mode: | |
6257 | ||
6258 | BRNEG <args>, 1f | |
6259 | nop | |
6260 | b <sym> | |
6261 | delay slot (executed only if branch taken) | |
6262 | 1: | |
6263 | ||
6264 | or, if CALL is set: | |
6265 | ||
6266 | BRNEG <args>, 1f | |
6267 | nop | |
6268 | bal <sym> | |
6269 | delay slot (executed only if branch taken) | |
6270 | 1: | |
6271 | ||
6272 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6273 | so code produced is simply: | |
6274 | ||
6275 | BR <args>, <sym> | |
6276 | nop | |
6277 | ||
6278 | This function is used when producing code for the microMIPS ASE that | |
6279 | does not implement branch likely instructions in hardware. */ | |
6280 | ||
6281 | static void | |
6282 | macro_build_branch_likely (const char *br, const char *brneg, | |
6283 | int call, expressionS *ep, const char *fmt, | |
6284 | unsigned int sreg, unsigned int treg) | |
6285 | { | |
6286 | int noreorder = mips_opts.noreorder; | |
6287 | expressionS expr1; | |
6288 | ||
6289 | gas_assert (mips_opts.micromips); | |
6290 | start_noreorder (); | |
6291 | if (noreorder) | |
6292 | { | |
6293 | micromips_label_expr (&expr1); | |
6294 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6295 | macro_build (NULL, "nop", ""); | |
6296 | macro_build (ep, call ? "bal" : "b", "p"); | |
6297 | ||
6298 | /* Set to true so that append_insn adds a label. */ | |
6299 | emit_branch_likely_macro = TRUE; | |
6300 | } | |
6301 | else | |
6302 | { | |
6303 | macro_build (ep, br, fmt, sreg, treg); | |
6304 | macro_build (NULL, "nop", ""); | |
6305 | } | |
6306 | end_noreorder (); | |
6307 | } | |
6308 | ||
6309 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6310 | the condition code tested. EP specifies the branch target. */ | |
6311 | ||
6312 | static void | |
6313 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6314 | { | |
6315 | const int call = 0; | |
6316 | const char *brneg; | |
6317 | const char *br; | |
6318 | ||
6319 | switch (type) | |
6320 | { | |
6321 | case M_BC1FL: | |
6322 | br = "bc1f"; | |
6323 | brneg = "bc1t"; | |
6324 | break; | |
6325 | case M_BC1TL: | |
6326 | br = "bc1t"; | |
6327 | brneg = "bc1f"; | |
6328 | break; | |
6329 | case M_BC2FL: | |
6330 | br = "bc2f"; | |
6331 | brneg = "bc2t"; | |
6332 | break; | |
6333 | case M_BC2TL: | |
6334 | br = "bc2t"; | |
6335 | brneg = "bc2f"; | |
6336 | break; | |
6337 | default: | |
6338 | abort (); | |
6339 | } | |
6340 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6341 | } | |
6342 | ||
6343 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6344 | the register tested. EP specifies the branch target. */ | |
6345 | ||
6346 | static void | |
6347 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6348 | { | |
6349 | const char *brneg = NULL; | |
6350 | const char *br; | |
6351 | int call = 0; | |
6352 | ||
6353 | switch (type) | |
6354 | { | |
6355 | case M_BGEZ: | |
6356 | br = "bgez"; | |
6357 | break; | |
6358 | case M_BGEZL: | |
6359 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6360 | brneg = "bltz"; | |
6361 | break; | |
6362 | case M_BGEZALL: | |
6363 | gas_assert (mips_opts.micromips); | |
6364 | br = "bgezals"; | |
6365 | brneg = "bltz"; | |
6366 | call = 1; | |
6367 | break; | |
6368 | case M_BGTZ: | |
6369 | br = "bgtz"; | |
6370 | break; | |
6371 | case M_BGTZL: | |
6372 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6373 | brneg = "blez"; | |
6374 | break; | |
6375 | case M_BLEZ: | |
6376 | br = "blez"; | |
6377 | break; | |
6378 | case M_BLEZL: | |
6379 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6380 | brneg = "bgtz"; | |
6381 | break; | |
6382 | case M_BLTZ: | |
6383 | br = "bltz"; | |
6384 | break; | |
6385 | case M_BLTZL: | |
6386 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6387 | brneg = "bgez"; | |
6388 | break; | |
6389 | case M_BLTZALL: | |
6390 | gas_assert (mips_opts.micromips); | |
6391 | br = "bltzals"; | |
6392 | brneg = "bgez"; | |
6393 | call = 1; | |
6394 | break; | |
6395 | default: | |
6396 | abort (); | |
6397 | } | |
6398 | if (mips_opts.micromips && brneg) | |
6399 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6400 | else | |
6401 | macro_build (ep, br, "s,p", sreg); | |
6402 | } | |
6403 | ||
6404 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6405 | TREG as the registers tested. EP specifies the branch target. */ | |
6406 | ||
6407 | static void | |
6408 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6409 | unsigned int sreg, unsigned int treg) | |
6410 | { | |
6411 | const char *brneg = NULL; | |
6412 | const int call = 0; | |
6413 | const char *br; | |
6414 | ||
6415 | switch (type) | |
6416 | { | |
6417 | case M_BEQ: | |
6418 | case M_BEQ_I: | |
6419 | br = "beq"; | |
6420 | break; | |
6421 | case M_BEQL: | |
6422 | case M_BEQL_I: | |
6423 | br = mips_opts.micromips ? "beq" : "beql"; | |
6424 | brneg = "bne"; | |
6425 | break; | |
6426 | case M_BNE: | |
6427 | case M_BNE_I: | |
6428 | br = "bne"; | |
6429 | break; | |
6430 | case M_BNEL: | |
6431 | case M_BNEL_I: | |
6432 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6433 | brneg = "beq"; | |
6434 | break; | |
6435 | default: | |
6436 | abort (); | |
6437 | } | |
6438 | if (mips_opts.micromips && brneg) | |
6439 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6440 | else | |
6441 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6442 | } | |
6443 | ||
252b5132 RH |
6444 | /* |
6445 | * Build macros | |
6446 | * This routine implements the seemingly endless macro or synthesized | |
6447 | * instructions and addressing modes in the mips assembly language. Many | |
6448 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6449 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6450 | * this verbose method. Others are not simple macros but are more like |
6451 | * optimizing code generation. | |
6452 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6453 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6454 | * The ensuing load upper instructions are ommited. This implies some kind |
6455 | * of global optimization. We currently only optimize within a single macro. | |
6456 | * For many of the load and store macros if the address is specified as a | |
6457 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6458 | * first load register 'at' with zero and use it as the base register. The | |
6459 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6460 | * we're missing. | |
6461 | */ | |
6462 | static void | |
17a2f251 | 6463 | macro (struct mips_cl_insn *ip) |
252b5132 | 6464 | { |
741fe287 MR |
6465 | unsigned int treg, sreg, dreg, breg; |
6466 | unsigned int tempreg; | |
252b5132 | 6467 | int mask; |
43841e91 | 6468 | int used_at = 0; |
df58fc94 | 6469 | expressionS label_expr; |
252b5132 | 6470 | expressionS expr1; |
df58fc94 | 6471 | expressionS *ep; |
252b5132 RH |
6472 | const char *s; |
6473 | const char *s2; | |
6474 | const char *fmt; | |
6475 | int likely = 0; | |
252b5132 | 6476 | int coproc = 0; |
7f3c4072 | 6477 | int offbits = 16; |
1abe91b1 | 6478 | int call = 0; |
df58fc94 RS |
6479 | int jals = 0; |
6480 | int dbl = 0; | |
6481 | int imm = 0; | |
6482 | int ust = 0; | |
6483 | int lp = 0; | |
6484 | int ab = 0; | |
252b5132 | 6485 | int off; |
67c0d1eb | 6486 | offsetT maxnum; |
252b5132 | 6487 | bfd_reloc_code_real_type r; |
252b5132 RH |
6488 | int hold_mips_optimize; |
6489 | ||
9c2799c2 | 6490 | gas_assert (! mips_opts.mips16); |
252b5132 | 6491 | |
df58fc94 RS |
6492 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6493 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6494 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6495 | mask = ip->insn_mo->mask; |
6496 | ||
df58fc94 RS |
6497 | label_expr.X_op = O_constant; |
6498 | label_expr.X_op_symbol = NULL; | |
6499 | label_expr.X_add_symbol = NULL; | |
6500 | label_expr.X_add_number = 0; | |
6501 | ||
252b5132 RH |
6502 | expr1.X_op = O_constant; |
6503 | expr1.X_op_symbol = NULL; | |
6504 | expr1.X_add_symbol = NULL; | |
6505 | expr1.X_add_number = 1; | |
6506 | ||
6507 | switch (mask) | |
6508 | { | |
6509 | case M_DABS: | |
6510 | dbl = 1; | |
6511 | case M_ABS: | |
df58fc94 RS |
6512 | /* bgez $a0,1f |
6513 | move v0,$a0 | |
6514 | sub v0,$zero,$a0 | |
6515 | 1: | |
6516 | */ | |
252b5132 | 6517 | |
7d10b47d | 6518 | start_noreorder (); |
252b5132 | 6519 | |
df58fc94 RS |
6520 | if (mips_opts.micromips) |
6521 | micromips_label_expr (&label_expr); | |
6522 | else | |
6523 | label_expr.X_add_number = 8; | |
6524 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6525 | if (dreg == sreg) |
a605d2b3 | 6526 | macro_build (NULL, "nop", ""); |
252b5132 | 6527 | else |
67c0d1eb RS |
6528 | move_register (dreg, sreg); |
6529 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6530 | if (mips_opts.micromips) |
6531 | micromips_add_label (); | |
252b5132 | 6532 | |
7d10b47d | 6533 | end_noreorder (); |
8fc2e39e | 6534 | break; |
252b5132 RH |
6535 | |
6536 | case M_ADD_I: | |
6537 | s = "addi"; | |
6538 | s2 = "add"; | |
6539 | goto do_addi; | |
6540 | case M_ADDU_I: | |
6541 | s = "addiu"; | |
6542 | s2 = "addu"; | |
6543 | goto do_addi; | |
6544 | case M_DADD_I: | |
6545 | dbl = 1; | |
6546 | s = "daddi"; | |
6547 | s2 = "dadd"; | |
df58fc94 RS |
6548 | if (!mips_opts.micromips) |
6549 | goto do_addi; | |
6550 | if (imm_expr.X_op == O_constant | |
6551 | && imm_expr.X_add_number >= -0x200 | |
6552 | && imm_expr.X_add_number < 0x200) | |
6553 | { | |
6554 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6555 | break; | |
6556 | } | |
6557 | goto do_addi_i; | |
252b5132 RH |
6558 | case M_DADDU_I: |
6559 | dbl = 1; | |
6560 | s = "daddiu"; | |
6561 | s2 = "daddu"; | |
6562 | do_addi: | |
6563 | if (imm_expr.X_op == O_constant | |
6564 | && imm_expr.X_add_number >= -0x8000 | |
6565 | && imm_expr.X_add_number < 0x8000) | |
6566 | { | |
67c0d1eb | 6567 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6568 | break; |
252b5132 | 6569 | } |
df58fc94 | 6570 | do_addi_i: |
8fc2e39e | 6571 | used_at = 1; |
67c0d1eb RS |
6572 | load_register (AT, &imm_expr, dbl); |
6573 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6574 | break; |
6575 | ||
6576 | case M_AND_I: | |
6577 | s = "andi"; | |
6578 | s2 = "and"; | |
6579 | goto do_bit; | |
6580 | case M_OR_I: | |
6581 | s = "ori"; | |
6582 | s2 = "or"; | |
6583 | goto do_bit; | |
6584 | case M_NOR_I: | |
6585 | s = ""; | |
6586 | s2 = "nor"; | |
6587 | goto do_bit; | |
6588 | case M_XOR_I: | |
6589 | s = "xori"; | |
6590 | s2 = "xor"; | |
6591 | do_bit: | |
6592 | if (imm_expr.X_op == O_constant | |
6593 | && imm_expr.X_add_number >= 0 | |
6594 | && imm_expr.X_add_number < 0x10000) | |
6595 | { | |
6596 | if (mask != M_NOR_I) | |
67c0d1eb | 6597 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6598 | else |
6599 | { | |
67c0d1eb RS |
6600 | macro_build (&imm_expr, "ori", "t,r,i", |
6601 | treg, sreg, BFD_RELOC_LO16); | |
6602 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6603 | } |
8fc2e39e | 6604 | break; |
252b5132 RH |
6605 | } |
6606 | ||
8fc2e39e | 6607 | used_at = 1; |
67c0d1eb RS |
6608 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6609 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6610 | break; |
6611 | ||
8b082fb1 TS |
6612 | case M_BALIGN: |
6613 | switch (imm_expr.X_add_number) | |
6614 | { | |
6615 | case 0: | |
6616 | macro_build (NULL, "nop", ""); | |
6617 | break; | |
6618 | case 2: | |
6619 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6620 | break; | |
03f66e8a MR |
6621 | case 1: |
6622 | case 3: | |
8b082fb1 | 6623 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6624 | (int) imm_expr.X_add_number); |
8b082fb1 | 6625 | break; |
03f66e8a MR |
6626 | default: |
6627 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6628 | (unsigned long) imm_expr.X_add_number); | |
6629 | break; | |
8b082fb1 TS |
6630 | } |
6631 | break; | |
6632 | ||
df58fc94 RS |
6633 | case M_BC1FL: |
6634 | case M_BC1TL: | |
6635 | case M_BC2FL: | |
6636 | case M_BC2TL: | |
6637 | gas_assert (mips_opts.micromips); | |
6638 | macro_build_branch_ccl (mask, &offset_expr, | |
6639 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6640 | break; | |
6641 | ||
252b5132 | 6642 | case M_BEQ_I: |
252b5132 | 6643 | case M_BEQL_I: |
252b5132 | 6644 | case M_BNE_I: |
252b5132 | 6645 | case M_BNEL_I: |
252b5132 | 6646 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6647 | treg = 0; |
6648 | else | |
252b5132 | 6649 | { |
df58fc94 RS |
6650 | treg = AT; |
6651 | used_at = 1; | |
6652 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6653 | } |
df58fc94 RS |
6654 | /* Fall through. */ |
6655 | case M_BEQL: | |
6656 | case M_BNEL: | |
6657 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6658 | break; |
6659 | ||
6660 | case M_BGEL: | |
6661 | likely = 1; | |
6662 | case M_BGE: | |
6663 | if (treg == 0) | |
df58fc94 RS |
6664 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6665 | else if (sreg == 0) | |
6666 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6667 | else | |
252b5132 | 6668 | { |
df58fc94 RS |
6669 | used_at = 1; |
6670 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6671 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6672 | &offset_expr, AT, ZERO); | |
252b5132 | 6673 | } |
df58fc94 RS |
6674 | break; |
6675 | ||
6676 | case M_BGEZL: | |
6677 | case M_BGEZALL: | |
6678 | case M_BGTZL: | |
6679 | case M_BLEZL: | |
6680 | case M_BLTZL: | |
6681 | case M_BLTZALL: | |
6682 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6683 | break; |
6684 | ||
6685 | case M_BGTL_I: | |
6686 | likely = 1; | |
6687 | case M_BGT_I: | |
90ecf173 | 6688 | /* Check for > max integer. */ |
252b5132 | 6689 | maxnum = 0x7fffffff; |
ca4e0257 | 6690 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6691 | { |
6692 | maxnum <<= 16; | |
6693 | maxnum |= 0xffff; | |
6694 | maxnum <<= 16; | |
6695 | maxnum |= 0xffff; | |
6696 | } | |
6697 | if (imm_expr.X_op == O_constant | |
6698 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6699 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6700 | { |
6701 | do_false: | |
90ecf173 | 6702 | /* Result is always false. */ |
252b5132 | 6703 | if (! likely) |
a605d2b3 | 6704 | macro_build (NULL, "nop", ""); |
252b5132 | 6705 | else |
df58fc94 | 6706 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6707 | break; |
252b5132 RH |
6708 | } |
6709 | if (imm_expr.X_op != O_constant) | |
6710 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6711 | ++imm_expr.X_add_number; |
252b5132 RH |
6712 | /* FALLTHROUGH */ |
6713 | case M_BGE_I: | |
6714 | case M_BGEL_I: | |
6715 | if (mask == M_BGEL_I) | |
6716 | likely = 1; | |
6717 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6718 | { | |
df58fc94 RS |
6719 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6720 | &offset_expr, sreg); | |
8fc2e39e | 6721 | break; |
252b5132 RH |
6722 | } |
6723 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6724 | { | |
df58fc94 RS |
6725 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6726 | &offset_expr, sreg); | |
8fc2e39e | 6727 | break; |
252b5132 RH |
6728 | } |
6729 | maxnum = 0x7fffffff; | |
ca4e0257 | 6730 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6731 | { |
6732 | maxnum <<= 16; | |
6733 | maxnum |= 0xffff; | |
6734 | maxnum <<= 16; | |
6735 | maxnum |= 0xffff; | |
6736 | } | |
6737 | maxnum = - maxnum - 1; | |
6738 | if (imm_expr.X_op == O_constant | |
6739 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6740 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6741 | { |
6742 | do_true: | |
6743 | /* result is always true */ | |
6744 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6745 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6746 | break; |
252b5132 | 6747 | } |
8fc2e39e | 6748 | used_at = 1; |
67c0d1eb | 6749 | set_at (sreg, 0); |
df58fc94 RS |
6750 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6751 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6752 | break; |
6753 | ||
6754 | case M_BGEUL: | |
6755 | likely = 1; | |
6756 | case M_BGEU: | |
6757 | if (treg == 0) | |
6758 | goto do_true; | |
df58fc94 RS |
6759 | else if (sreg == 0) |
6760 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6761 | &offset_expr, ZERO, treg); | |
6762 | else | |
252b5132 | 6763 | { |
df58fc94 RS |
6764 | used_at = 1; |
6765 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6766 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6767 | &offset_expr, AT, ZERO); | |
252b5132 | 6768 | } |
252b5132 RH |
6769 | break; |
6770 | ||
6771 | case M_BGTUL_I: | |
6772 | likely = 1; | |
6773 | case M_BGTU_I: | |
6774 | if (sreg == 0 | |
ca4e0257 | 6775 | || (HAVE_32BIT_GPRS |
252b5132 | 6776 | && imm_expr.X_op == O_constant |
f01dc953 | 6777 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6778 | goto do_false; |
6779 | if (imm_expr.X_op != O_constant) | |
6780 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6781 | ++imm_expr.X_add_number; |
252b5132 RH |
6782 | /* FALLTHROUGH */ |
6783 | case M_BGEU_I: | |
6784 | case M_BGEUL_I: | |
6785 | if (mask == M_BGEUL_I) | |
6786 | likely = 1; | |
6787 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6788 | goto do_true; | |
df58fc94 RS |
6789 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6790 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6791 | &offset_expr, sreg, ZERO); | |
6792 | else | |
252b5132 | 6793 | { |
df58fc94 RS |
6794 | used_at = 1; |
6795 | set_at (sreg, 1); | |
6796 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6797 | &offset_expr, AT, ZERO); | |
252b5132 | 6798 | } |
252b5132 RH |
6799 | break; |
6800 | ||
6801 | case M_BGTL: | |
6802 | likely = 1; | |
6803 | case M_BGT: | |
6804 | if (treg == 0) | |
df58fc94 RS |
6805 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6806 | else if (sreg == 0) | |
6807 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6808 | else | |
252b5132 | 6809 | { |
df58fc94 RS |
6810 | used_at = 1; |
6811 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6812 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6813 | &offset_expr, AT, ZERO); | |
252b5132 | 6814 | } |
252b5132 RH |
6815 | break; |
6816 | ||
6817 | case M_BGTUL: | |
6818 | likely = 1; | |
6819 | case M_BGTU: | |
6820 | if (treg == 0) | |
df58fc94 RS |
6821 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6822 | &offset_expr, sreg, ZERO); | |
6823 | else if (sreg == 0) | |
6824 | goto do_false; | |
6825 | else | |
252b5132 | 6826 | { |
df58fc94 RS |
6827 | used_at = 1; |
6828 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6829 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6830 | &offset_expr, AT, ZERO); | |
252b5132 | 6831 | } |
252b5132 RH |
6832 | break; |
6833 | ||
6834 | case M_BLEL: | |
6835 | likely = 1; | |
6836 | case M_BLE: | |
6837 | if (treg == 0) | |
df58fc94 RS |
6838 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6839 | else if (sreg == 0) | |
6840 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6841 | else | |
252b5132 | 6842 | { |
df58fc94 RS |
6843 | used_at = 1; |
6844 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6845 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6846 | &offset_expr, AT, ZERO); | |
252b5132 | 6847 | } |
252b5132 RH |
6848 | break; |
6849 | ||
6850 | case M_BLEL_I: | |
6851 | likely = 1; | |
6852 | case M_BLE_I: | |
6853 | maxnum = 0x7fffffff; | |
ca4e0257 | 6854 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6855 | { |
6856 | maxnum <<= 16; | |
6857 | maxnum |= 0xffff; | |
6858 | maxnum <<= 16; | |
6859 | maxnum |= 0xffff; | |
6860 | } | |
6861 | if (imm_expr.X_op == O_constant | |
6862 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6863 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6864 | goto do_true; |
6865 | if (imm_expr.X_op != O_constant) | |
6866 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6867 | ++imm_expr.X_add_number; |
252b5132 RH |
6868 | /* FALLTHROUGH */ |
6869 | case M_BLT_I: | |
6870 | case M_BLTL_I: | |
6871 | if (mask == M_BLTL_I) | |
6872 | likely = 1; | |
6873 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6874 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6875 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6876 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6877 | else | |
252b5132 | 6878 | { |
df58fc94 RS |
6879 | used_at = 1; |
6880 | set_at (sreg, 0); | |
6881 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6882 | &offset_expr, AT, ZERO); | |
252b5132 | 6883 | } |
252b5132 RH |
6884 | break; |
6885 | ||
6886 | case M_BLEUL: | |
6887 | likely = 1; | |
6888 | case M_BLEU: | |
6889 | if (treg == 0) | |
df58fc94 RS |
6890 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6891 | &offset_expr, sreg, ZERO); | |
6892 | else if (sreg == 0) | |
6893 | goto do_true; | |
6894 | else | |
252b5132 | 6895 | { |
df58fc94 RS |
6896 | used_at = 1; |
6897 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6898 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6899 | &offset_expr, AT, ZERO); | |
252b5132 | 6900 | } |
252b5132 RH |
6901 | break; |
6902 | ||
6903 | case M_BLEUL_I: | |
6904 | likely = 1; | |
6905 | case M_BLEU_I: | |
6906 | if (sreg == 0 | |
ca4e0257 | 6907 | || (HAVE_32BIT_GPRS |
252b5132 | 6908 | && imm_expr.X_op == O_constant |
f01dc953 | 6909 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6910 | goto do_true; |
6911 | if (imm_expr.X_op != O_constant) | |
6912 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6913 | ++imm_expr.X_add_number; |
252b5132 RH |
6914 | /* FALLTHROUGH */ |
6915 | case M_BLTU_I: | |
6916 | case M_BLTUL_I: | |
6917 | if (mask == M_BLTUL_I) | |
6918 | likely = 1; | |
6919 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6920 | goto do_false; | |
df58fc94 RS |
6921 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6922 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6923 | &offset_expr, sreg, ZERO); | |
6924 | else | |
252b5132 | 6925 | { |
df58fc94 RS |
6926 | used_at = 1; |
6927 | set_at (sreg, 1); | |
6928 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6929 | &offset_expr, AT, ZERO); | |
252b5132 | 6930 | } |
252b5132 RH |
6931 | break; |
6932 | ||
6933 | case M_BLTL: | |
6934 | likely = 1; | |
6935 | case M_BLT: | |
6936 | if (treg == 0) | |
df58fc94 RS |
6937 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6938 | else if (sreg == 0) | |
6939 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6940 | else | |
252b5132 | 6941 | { |
df58fc94 RS |
6942 | used_at = 1; |
6943 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6944 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6945 | &offset_expr, AT, ZERO); | |
252b5132 | 6946 | } |
252b5132 RH |
6947 | break; |
6948 | ||
6949 | case M_BLTUL: | |
6950 | likely = 1; | |
6951 | case M_BLTU: | |
6952 | if (treg == 0) | |
6953 | goto do_false; | |
df58fc94 RS |
6954 | else if (sreg == 0) |
6955 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6956 | &offset_expr, ZERO, treg); | |
6957 | else | |
252b5132 | 6958 | { |
df58fc94 RS |
6959 | used_at = 1; |
6960 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6961 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6962 | &offset_expr, AT, ZERO); | |
252b5132 | 6963 | } |
252b5132 RH |
6964 | break; |
6965 | ||
5f74bc13 CD |
6966 | case M_DEXT: |
6967 | { | |
d5818fca MR |
6968 | /* Use unsigned arithmetic. */ |
6969 | addressT pos; | |
6970 | addressT size; | |
5f74bc13 | 6971 | |
90ecf173 | 6972 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6973 | { |
6974 | as_bad (_("Unsupported large constant")); | |
6975 | pos = size = 1; | |
6976 | } | |
6977 | else | |
6978 | { | |
d5818fca MR |
6979 | pos = imm_expr.X_add_number; |
6980 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6981 | } |
6982 | ||
6983 | if (pos > 63) | |
6984 | { | |
d5818fca | 6985 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6986 | pos = 1; |
6987 | } | |
90ecf173 | 6988 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6989 | { |
6990 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6991 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6992 | size = 1; |
6993 | } | |
6994 | ||
6995 | if (size <= 32 && pos < 32) | |
6996 | { | |
6997 | s = "dext"; | |
6998 | fmt = "t,r,+A,+C"; | |
6999 | } | |
7000 | else if (size <= 32) | |
7001 | { | |
7002 | s = "dextu"; | |
7003 | fmt = "t,r,+E,+H"; | |
7004 | } | |
7005 | else | |
7006 | { | |
7007 | s = "dextm"; | |
7008 | fmt = "t,r,+A,+G"; | |
7009 | } | |
d5818fca MR |
7010 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7011 | (int) (size - 1)); | |
5f74bc13 | 7012 | } |
8fc2e39e | 7013 | break; |
5f74bc13 CD |
7014 | |
7015 | case M_DINS: | |
7016 | { | |
d5818fca MR |
7017 | /* Use unsigned arithmetic. */ |
7018 | addressT pos; | |
7019 | addressT size; | |
5f74bc13 | 7020 | |
90ecf173 | 7021 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7022 | { |
7023 | as_bad (_("Unsupported large constant")); | |
7024 | pos = size = 1; | |
7025 | } | |
7026 | else | |
7027 | { | |
d5818fca MR |
7028 | pos = imm_expr.X_add_number; |
7029 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7030 | } |
7031 | ||
7032 | if (pos > 63) | |
7033 | { | |
d5818fca | 7034 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7035 | pos = 1; |
7036 | } | |
90ecf173 | 7037 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7038 | { |
7039 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7040 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7041 | size = 1; |
7042 | } | |
7043 | ||
7044 | if (pos < 32 && (pos + size - 1) < 32) | |
7045 | { | |
7046 | s = "dins"; | |
7047 | fmt = "t,r,+A,+B"; | |
7048 | } | |
7049 | else if (pos >= 32) | |
7050 | { | |
7051 | s = "dinsu"; | |
7052 | fmt = "t,r,+E,+F"; | |
7053 | } | |
7054 | else | |
7055 | { | |
7056 | s = "dinsm"; | |
7057 | fmt = "t,r,+A,+F"; | |
7058 | } | |
750bdd57 AS |
7059 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7060 | (int) (pos + size - 1)); | |
5f74bc13 | 7061 | } |
8fc2e39e | 7062 | break; |
5f74bc13 | 7063 | |
252b5132 RH |
7064 | case M_DDIV_3: |
7065 | dbl = 1; | |
7066 | case M_DIV_3: | |
7067 | s = "mflo"; | |
7068 | goto do_div3; | |
7069 | case M_DREM_3: | |
7070 | dbl = 1; | |
7071 | case M_REM_3: | |
7072 | s = "mfhi"; | |
7073 | do_div3: | |
7074 | if (treg == 0) | |
7075 | { | |
7076 | as_warn (_("Divide by zero.")); | |
7077 | if (mips_trap) | |
df58fc94 | 7078 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7079 | else |
df58fc94 | 7080 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7081 | break; |
252b5132 RH |
7082 | } |
7083 | ||
7d10b47d | 7084 | start_noreorder (); |
252b5132 RH |
7085 | if (mips_trap) |
7086 | { | |
df58fc94 | 7087 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7088 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7089 | } |
7090 | else | |
7091 | { | |
df58fc94 RS |
7092 | if (mips_opts.micromips) |
7093 | micromips_label_expr (&label_expr); | |
7094 | else | |
7095 | label_expr.X_add_number = 8; | |
7096 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7097 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7098 | macro_build (NULL, "break", BRK_FMT, 7); |
7099 | if (mips_opts.micromips) | |
7100 | micromips_add_label (); | |
252b5132 RH |
7101 | } |
7102 | expr1.X_add_number = -1; | |
8fc2e39e | 7103 | used_at = 1; |
f6a22291 | 7104 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7105 | if (mips_opts.micromips) |
7106 | micromips_label_expr (&label_expr); | |
7107 | else | |
7108 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7109 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7110 | if (dbl) |
7111 | { | |
7112 | expr1.X_add_number = 1; | |
f6a22291 | 7113 | load_register (AT, &expr1, dbl); |
df58fc94 | 7114 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7115 | } |
7116 | else | |
7117 | { | |
7118 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7119 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7120 | } |
7121 | if (mips_trap) | |
7122 | { | |
df58fc94 | 7123 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7124 | /* We want to close the noreorder block as soon as possible, so |
7125 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7126 | end_noreorder (); |
252b5132 RH |
7127 | } |
7128 | else | |
7129 | { | |
df58fc94 RS |
7130 | if (mips_opts.micromips) |
7131 | micromips_label_expr (&label_expr); | |
7132 | else | |
7133 | label_expr.X_add_number = 8; | |
7134 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7135 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7136 | |
7137 | /* We want to close the noreorder block as soon as possible, so | |
7138 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7139 | end_noreorder (); |
252b5132 | 7140 | |
df58fc94 | 7141 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7142 | } |
df58fc94 RS |
7143 | if (mips_opts.micromips) |
7144 | micromips_add_label (); | |
7145 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7146 | break; |
7147 | ||
7148 | case M_DIV_3I: | |
7149 | s = "div"; | |
7150 | s2 = "mflo"; | |
7151 | goto do_divi; | |
7152 | case M_DIVU_3I: | |
7153 | s = "divu"; | |
7154 | s2 = "mflo"; | |
7155 | goto do_divi; | |
7156 | case M_REM_3I: | |
7157 | s = "div"; | |
7158 | s2 = "mfhi"; | |
7159 | goto do_divi; | |
7160 | case M_REMU_3I: | |
7161 | s = "divu"; | |
7162 | s2 = "mfhi"; | |
7163 | goto do_divi; | |
7164 | case M_DDIV_3I: | |
7165 | dbl = 1; | |
7166 | s = "ddiv"; | |
7167 | s2 = "mflo"; | |
7168 | goto do_divi; | |
7169 | case M_DDIVU_3I: | |
7170 | dbl = 1; | |
7171 | s = "ddivu"; | |
7172 | s2 = "mflo"; | |
7173 | goto do_divi; | |
7174 | case M_DREM_3I: | |
7175 | dbl = 1; | |
7176 | s = "ddiv"; | |
7177 | s2 = "mfhi"; | |
7178 | goto do_divi; | |
7179 | case M_DREMU_3I: | |
7180 | dbl = 1; | |
7181 | s = "ddivu"; | |
7182 | s2 = "mfhi"; | |
7183 | do_divi: | |
7184 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7185 | { | |
7186 | as_warn (_("Divide by zero.")); | |
7187 | if (mips_trap) | |
df58fc94 | 7188 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7189 | else |
df58fc94 | 7190 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7191 | break; |
252b5132 RH |
7192 | } |
7193 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7194 | { | |
7195 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7196 | move_register (dreg, sreg); |
252b5132 | 7197 | else |
c80c840e | 7198 | move_register (dreg, ZERO); |
8fc2e39e | 7199 | break; |
252b5132 RH |
7200 | } |
7201 | if (imm_expr.X_op == O_constant | |
7202 | && imm_expr.X_add_number == -1 | |
7203 | && s[strlen (s) - 1] != 'u') | |
7204 | { | |
7205 | if (strcmp (s2, "mflo") == 0) | |
7206 | { | |
67c0d1eb | 7207 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7208 | } |
7209 | else | |
c80c840e | 7210 | move_register (dreg, ZERO); |
8fc2e39e | 7211 | break; |
252b5132 RH |
7212 | } |
7213 | ||
8fc2e39e | 7214 | used_at = 1; |
67c0d1eb RS |
7215 | load_register (AT, &imm_expr, dbl); |
7216 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7217 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7218 | break; |
7219 | ||
7220 | case M_DIVU_3: | |
7221 | s = "divu"; | |
7222 | s2 = "mflo"; | |
7223 | goto do_divu3; | |
7224 | case M_REMU_3: | |
7225 | s = "divu"; | |
7226 | s2 = "mfhi"; | |
7227 | goto do_divu3; | |
7228 | case M_DDIVU_3: | |
7229 | s = "ddivu"; | |
7230 | s2 = "mflo"; | |
7231 | goto do_divu3; | |
7232 | case M_DREMU_3: | |
7233 | s = "ddivu"; | |
7234 | s2 = "mfhi"; | |
7235 | do_divu3: | |
7d10b47d | 7236 | start_noreorder (); |
252b5132 RH |
7237 | if (mips_trap) |
7238 | { | |
df58fc94 | 7239 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7240 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7241 | /* We want to close the noreorder block as soon as possible, so |
7242 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7243 | end_noreorder (); |
252b5132 RH |
7244 | } |
7245 | else | |
7246 | { | |
df58fc94 RS |
7247 | if (mips_opts.micromips) |
7248 | micromips_label_expr (&label_expr); | |
7249 | else | |
7250 | label_expr.X_add_number = 8; | |
7251 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7252 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7253 | |
7254 | /* We want to close the noreorder block as soon as possible, so | |
7255 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7256 | end_noreorder (); |
df58fc94 RS |
7257 | macro_build (NULL, "break", BRK_FMT, 7); |
7258 | if (mips_opts.micromips) | |
7259 | micromips_add_label (); | |
252b5132 | 7260 | } |
df58fc94 | 7261 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7262 | break; |
252b5132 | 7263 | |
1abe91b1 MR |
7264 | case M_DLCA_AB: |
7265 | dbl = 1; | |
7266 | case M_LCA_AB: | |
7267 | call = 1; | |
7268 | goto do_la; | |
252b5132 RH |
7269 | case M_DLA_AB: |
7270 | dbl = 1; | |
7271 | case M_LA_AB: | |
1abe91b1 | 7272 | do_la: |
252b5132 RH |
7273 | /* Load the address of a symbol into a register. If breg is not |
7274 | zero, we then add a base register to it. */ | |
7275 | ||
3bec30a8 TS |
7276 | if (dbl && HAVE_32BIT_GPRS) |
7277 | as_warn (_("dla used to load 32-bit register")); | |
7278 | ||
90ecf173 | 7279 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7280 | as_warn (_("la used to load 64-bit address")); |
7281 | ||
0c11417f MR |
7282 | if (offset_expr.X_op == O_constant |
7283 | && offset_expr.X_add_number >= -0x8000 | |
7284 | && offset_expr.X_add_number < 0x8000) | |
7285 | { | |
aed1a261 | 7286 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7287 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7288 | break; |
0c11417f MR |
7289 | } |
7290 | ||
741fe287 | 7291 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7292 | { |
7293 | tempreg = AT; | |
7294 | used_at = 1; | |
7295 | } | |
7296 | else | |
7297 | { | |
7298 | tempreg = treg; | |
afdbd6d0 CD |
7299 | } |
7300 | ||
252b5132 RH |
7301 | if (offset_expr.X_op != O_symbol |
7302 | && offset_expr.X_op != O_constant) | |
7303 | { | |
f71d0d44 | 7304 | as_bad (_("Expression too complex")); |
252b5132 RH |
7305 | offset_expr.X_op = O_constant; |
7306 | } | |
7307 | ||
252b5132 | 7308 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7309 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7310 | else if (mips_pic == NO_PIC) |
7311 | { | |
d6bc6245 | 7312 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7313 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7314 | Otherwise we want |
7315 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7316 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7317 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7318 | so we may as well always use the latter form. |
76b3015f | 7319 | |
6caf9ef4 TS |
7320 | With 64bit address space and a usable $at we want |
7321 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7322 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7323 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7324 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7325 | dsll32 $tempreg,0 | |
7326 | daddu $tempreg,$tempreg,$at | |
7327 | ||
7328 | If $at is already in use, we use a path which is suboptimal | |
7329 | on superscalar processors. | |
7330 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7331 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7332 | dsll $tempreg,16 | |
7333 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7334 | dsll $tempreg,16 | |
7335 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7336 | ||
7337 | For GP relative symbols in 64bit address space we can use | |
7338 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7339 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7340 | { |
6caf9ef4 TS |
7341 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7342 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7343 | { | |
7344 | relax_start (offset_expr.X_add_symbol); | |
7345 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7346 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7347 | relax_switch (); | |
7348 | } | |
d6bc6245 | 7349 | |
741fe287 | 7350 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7351 | { |
df58fc94 | 7352 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7353 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7354 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7355 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7356 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7357 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7358 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7359 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7360 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7361 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7362 | used_at = 1; |
7363 | } | |
7364 | else | |
7365 | { | |
df58fc94 | 7366 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7367 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7368 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7369 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7370 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7371 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7372 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7373 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7374 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7375 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7376 | } |
6caf9ef4 TS |
7377 | |
7378 | if (mips_relax.sequence) | |
7379 | relax_end (); | |
98d3f06f KH |
7380 | } |
7381 | else | |
7382 | { | |
7383 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7384 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7385 | { |
4d7206a2 | 7386 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7387 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7388 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7389 | relax_switch (); |
98d3f06f | 7390 | } |
6943caf0 | 7391 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7392 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7393 | macro_build_lui (&offset_expr, tempreg); |
7394 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7395 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7396 | if (mips_relax.sequence) |
7397 | relax_end (); | |
98d3f06f | 7398 | } |
252b5132 | 7399 | } |
0a44bf69 | 7400 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7401 | { |
9117d219 NC |
7402 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7403 | ||
252b5132 RH |
7404 | /* If this is a reference to an external symbol, and there |
7405 | is no constant, we want | |
7406 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7407 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7408 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7409 | For a local symbol, we want |
7410 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7411 | nop | |
7412 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7413 | ||
7414 | If we have a small constant, and this is a reference to | |
7415 | an external symbol, we want | |
7416 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7417 | nop | |
7418 | addiu $tempreg,$tempreg,<constant> | |
7419 | For a local symbol, we want the same instruction | |
7420 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7421 | addiu instruction. | |
7422 | ||
7423 | If we have a large constant, and this is a reference to | |
7424 | an external symbol, we want | |
7425 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7426 | lui $at,<hiconstant> | |
7427 | addiu $at,$at,<loconstant> | |
7428 | addu $tempreg,$tempreg,$at | |
7429 | For a local symbol, we want the same instruction | |
7430 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7431 | addiu instruction. |
ed6fb7bd SC |
7432 | */ |
7433 | ||
4d7206a2 | 7434 | if (offset_expr.X_add_number == 0) |
252b5132 | 7435 | { |
0a44bf69 RS |
7436 | if (mips_pic == SVR4_PIC |
7437 | && breg == 0 | |
7438 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7439 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7440 | ||
7441 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7442 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7443 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7444 | if (breg != 0) |
252b5132 RH |
7445 | { |
7446 | /* We're going to put in an addu instruction using | |
7447 | tempreg, so we may as well insert the nop right | |
7448 | now. */ | |
269137b2 | 7449 | load_delay_nop (); |
252b5132 | 7450 | } |
4d7206a2 | 7451 | relax_switch (); |
67c0d1eb RS |
7452 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7453 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7454 | load_delay_nop (); |
67c0d1eb RS |
7455 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7456 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7457 | relax_end (); |
252b5132 RH |
7458 | /* FIXME: If breg == 0, and the next instruction uses |
7459 | $tempreg, then if this variant case is used an extra | |
7460 | nop will be generated. */ | |
7461 | } | |
4d7206a2 RS |
7462 | else if (offset_expr.X_add_number >= -0x8000 |
7463 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7464 | { |
67c0d1eb | 7465 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7466 | load_delay_nop (); |
67c0d1eb | 7467 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7468 | } |
7469 | else | |
7470 | { | |
4d7206a2 RS |
7471 | expr1.X_add_number = offset_expr.X_add_number; |
7472 | offset_expr.X_add_number = | |
43c0598f | 7473 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7474 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7475 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7476 | /* If we are going to add in a base register, and the |
7477 | target register and the base register are the same, | |
7478 | then we are using AT as a temporary register. Since | |
7479 | we want to load the constant into AT, we add our | |
7480 | current AT (from the global offset table) and the | |
7481 | register into the register now, and pretend we were | |
7482 | not using a base register. */ | |
67c0d1eb | 7483 | if (breg == treg) |
252b5132 | 7484 | { |
269137b2 | 7485 | load_delay_nop (); |
67c0d1eb | 7486 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7487 | treg, AT, breg); |
252b5132 RH |
7488 | breg = 0; |
7489 | tempreg = treg; | |
252b5132 | 7490 | } |
f6a22291 | 7491 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7492 | used_at = 1; |
7493 | } | |
7494 | } | |
0a44bf69 | 7495 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7496 | { |
67c0d1eb | 7497 | int add_breg_early = 0; |
f5040a92 AO |
7498 | |
7499 | /* If this is a reference to an external, and there is no | |
7500 | constant, or local symbol (*), with or without a | |
7501 | constant, we want | |
7502 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7503 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7504 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7505 | ||
7506 | If we have a small constant, and this is a reference to | |
7507 | an external symbol, we want | |
7508 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7509 | addiu $tempreg,$tempreg,<constant> | |
7510 | ||
7511 | If we have a large constant, and this is a reference to | |
7512 | an external symbol, we want | |
7513 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7514 | lui $at,<hiconstant> | |
7515 | addiu $at,$at,<loconstant> | |
7516 | addu $tempreg,$tempreg,$at | |
7517 | ||
7518 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7519 | local symbols, even though it introduces an additional | |
7520 | instruction. */ | |
7521 | ||
f5040a92 AO |
7522 | if (offset_expr.X_add_number) |
7523 | { | |
4d7206a2 | 7524 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7525 | offset_expr.X_add_number = 0; |
7526 | ||
4d7206a2 | 7527 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7528 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7529 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7530 | |
7531 | if (expr1.X_add_number >= -0x8000 | |
7532 | && expr1.X_add_number < 0x8000) | |
7533 | { | |
67c0d1eb RS |
7534 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7535 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7536 | } |
ecd13cd3 | 7537 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7538 | { |
f5040a92 AO |
7539 | /* If we are going to add in a base register, and the |
7540 | target register and the base register are the same, | |
7541 | then we are using AT as a temporary register. Since | |
7542 | we want to load the constant into AT, we add our | |
7543 | current AT (from the global offset table) and the | |
7544 | register into the register now, and pretend we were | |
7545 | not using a base register. */ | |
7546 | if (breg != treg) | |
7547 | dreg = tempreg; | |
7548 | else | |
7549 | { | |
9c2799c2 | 7550 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7552 | treg, AT, breg); | |
f5040a92 | 7553 | dreg = treg; |
67c0d1eb | 7554 | add_breg_early = 1; |
f5040a92 AO |
7555 | } |
7556 | ||
f6a22291 | 7557 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7558 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7559 | dreg, dreg, AT); |
f5040a92 | 7560 | |
f5040a92 AO |
7561 | used_at = 1; |
7562 | } | |
7563 | else | |
7564 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7565 | ||
4d7206a2 | 7566 | relax_switch (); |
f5040a92 AO |
7567 | offset_expr.X_add_number = expr1.X_add_number; |
7568 | ||
67c0d1eb RS |
7569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7570 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7571 | if (add_breg_early) | |
f5040a92 | 7572 | { |
67c0d1eb | 7573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7574 | treg, tempreg, breg); |
f5040a92 AO |
7575 | breg = 0; |
7576 | tempreg = treg; | |
7577 | } | |
4d7206a2 | 7578 | relax_end (); |
f5040a92 | 7579 | } |
4d7206a2 | 7580 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7581 | { |
4d7206a2 | 7582 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7583 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7584 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7585 | relax_switch (); |
67c0d1eb RS |
7586 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7587 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7588 | relax_end (); |
f5040a92 | 7589 | } |
4d7206a2 | 7590 | else |
f5040a92 | 7591 | { |
67c0d1eb RS |
7592 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7593 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7594 | } |
7595 | } | |
0a44bf69 | 7596 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7597 | { |
67c0d1eb | 7598 | int gpdelay; |
9117d219 NC |
7599 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7600 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7601 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7602 | |
7603 | /* This is the large GOT case. If this is a reference to an | |
7604 | external symbol, and there is no constant, we want | |
7605 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7606 | addu $tempreg,$tempreg,$gp | |
7607 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7608 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7609 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7610 | addu $tempreg,$tempreg,$gp | |
7611 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7612 | For a local symbol, we want |
7613 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7614 | nop | |
7615 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7616 | ||
7617 | If we have a small constant, and this is a reference to | |
7618 | an external symbol, we want | |
7619 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7620 | addu $tempreg,$tempreg,$gp | |
7621 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7622 | nop | |
7623 | addiu $tempreg,$tempreg,<constant> | |
7624 | For a local symbol, we want | |
7625 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7626 | nop | |
7627 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7628 | ||
7629 | If we have a large constant, and this is a reference to | |
7630 | an external symbol, we want | |
7631 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7632 | addu $tempreg,$tempreg,$gp | |
7633 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7634 | lui $at,<hiconstant> | |
7635 | addiu $at,$at,<loconstant> | |
7636 | addu $tempreg,$tempreg,$at | |
7637 | For a local symbol, we want | |
7638 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7639 | lui $at,<hiconstant> | |
7640 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7641 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7642 | */ |
438c16b8 | 7643 | |
252b5132 RH |
7644 | expr1.X_add_number = offset_expr.X_add_number; |
7645 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7646 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7647 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7648 | if (expr1.X_add_number == 0 && breg == 0 |
7649 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7650 | { |
7651 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7652 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7653 | } | |
df58fc94 | 7654 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7655 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7656 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7657 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7658 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7659 | if (expr1.X_add_number == 0) |
7660 | { | |
67c0d1eb | 7661 | if (breg != 0) |
252b5132 RH |
7662 | { |
7663 | /* We're going to put in an addu instruction using | |
7664 | tempreg, so we may as well insert the nop right | |
7665 | now. */ | |
269137b2 | 7666 | load_delay_nop (); |
252b5132 | 7667 | } |
252b5132 RH |
7668 | } |
7669 | else if (expr1.X_add_number >= -0x8000 | |
7670 | && expr1.X_add_number < 0x8000) | |
7671 | { | |
269137b2 | 7672 | load_delay_nop (); |
67c0d1eb | 7673 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7674 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7675 | } |
7676 | else | |
7677 | { | |
252b5132 RH |
7678 | /* If we are going to add in a base register, and the |
7679 | target register and the base register are the same, | |
7680 | then we are using AT as a temporary register. Since | |
7681 | we want to load the constant into AT, we add our | |
7682 | current AT (from the global offset table) and the | |
7683 | register into the register now, and pretend we were | |
7684 | not using a base register. */ | |
7685 | if (breg != treg) | |
67c0d1eb | 7686 | dreg = tempreg; |
252b5132 RH |
7687 | else |
7688 | { | |
9c2799c2 | 7689 | gas_assert (tempreg == AT); |
269137b2 | 7690 | load_delay_nop (); |
67c0d1eb | 7691 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7692 | treg, AT, breg); |
252b5132 | 7693 | dreg = treg; |
252b5132 RH |
7694 | } |
7695 | ||
f6a22291 | 7696 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7698 | |
252b5132 RH |
7699 | used_at = 1; |
7700 | } | |
43c0598f | 7701 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7702 | relax_switch (); |
252b5132 | 7703 | |
67c0d1eb | 7704 | if (gpdelay) |
252b5132 RH |
7705 | { |
7706 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7707 | the first instruction on the main stream does not. */ |
67c0d1eb | 7708 | macro_build (NULL, "nop", ""); |
252b5132 | 7709 | } |
ed6fb7bd | 7710 | |
67c0d1eb RS |
7711 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7712 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7713 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7714 | && expr1.X_add_number < 0x8000) |
7715 | { | |
269137b2 | 7716 | load_delay_nop (); |
67c0d1eb RS |
7717 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7718 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7719 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7720 | register, the external symbol case ended with a load, |
7721 | so if the symbol turns out to not be external, and | |
7722 | the next instruction uses tempreg, an unnecessary nop | |
7723 | will be inserted. */ | |
252b5132 RH |
7724 | } |
7725 | else | |
7726 | { | |
7727 | if (breg == treg) | |
7728 | { | |
7729 | /* We must add in the base register now, as in the | |
f5040a92 | 7730 | external symbol case. */ |
9c2799c2 | 7731 | gas_assert (tempreg == AT); |
269137b2 | 7732 | load_delay_nop (); |
67c0d1eb | 7733 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7734 | treg, AT, breg); |
252b5132 RH |
7735 | tempreg = treg; |
7736 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7737 | it in in both cases. */ |
252b5132 RH |
7738 | breg = 0; |
7739 | } | |
7740 | ||
67c0d1eb RS |
7741 | macro_build_lui (&expr1, AT); |
7742 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7743 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7744 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7745 | tempreg, tempreg, AT); |
8fc2e39e | 7746 | used_at = 1; |
252b5132 | 7747 | } |
4d7206a2 | 7748 | relax_end (); |
252b5132 | 7749 | } |
0a44bf69 | 7750 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7751 | { |
f5040a92 AO |
7752 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7753 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7754 | int add_breg_early = 0; |
f5040a92 AO |
7755 | |
7756 | /* This is the large GOT case. If this is a reference to an | |
7757 | external symbol, and there is no constant, we want | |
7758 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7759 | add $tempreg,$tempreg,$gp | |
7760 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7761 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7762 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7763 | add $tempreg,$tempreg,$gp | |
7764 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7765 | ||
7766 | If we have a small constant, and this is a reference to | |
7767 | an external symbol, we want | |
7768 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7769 | add $tempreg,$tempreg,$gp | |
7770 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7771 | addi $tempreg,$tempreg,<constant> | |
7772 | ||
7773 | If we have a large constant, and this is a reference to | |
7774 | an external symbol, we want | |
7775 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7776 | addu $tempreg,$tempreg,$gp | |
7777 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7778 | lui $at,<hiconstant> | |
7779 | addi $at,$at,<loconstant> | |
7780 | add $tempreg,$tempreg,$at | |
7781 | ||
7782 | If we have NewABI, and we know it's a local symbol, we want | |
7783 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7784 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7785 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7786 | ||
4d7206a2 | 7787 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7788 | |
4d7206a2 | 7789 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7790 | offset_expr.X_add_number = 0; |
7791 | ||
1abe91b1 MR |
7792 | if (expr1.X_add_number == 0 && breg == 0 |
7793 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7794 | { |
7795 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7796 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7797 | } | |
df58fc94 | 7798 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7799 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7800 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7801 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7802 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7803 | |
7804 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7805 | ; |
f5040a92 AO |
7806 | else if (expr1.X_add_number >= -0x8000 |
7807 | && expr1.X_add_number < 0x8000) | |
7808 | { | |
67c0d1eb | 7809 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7810 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7811 | } |
ecd13cd3 | 7812 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7813 | { |
f5040a92 AO |
7814 | /* If we are going to add in a base register, and the |
7815 | target register and the base register are the same, | |
7816 | then we are using AT as a temporary register. Since | |
7817 | we want to load the constant into AT, we add our | |
7818 | current AT (from the global offset table) and the | |
7819 | register into the register now, and pretend we were | |
7820 | not using a base register. */ | |
7821 | if (breg != treg) | |
7822 | dreg = tempreg; | |
7823 | else | |
7824 | { | |
9c2799c2 | 7825 | gas_assert (tempreg == AT); |
67c0d1eb | 7826 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7827 | treg, AT, breg); |
f5040a92 | 7828 | dreg = treg; |
67c0d1eb | 7829 | add_breg_early = 1; |
f5040a92 AO |
7830 | } |
7831 | ||
f6a22291 | 7832 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7833 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7834 | |
f5040a92 AO |
7835 | used_at = 1; |
7836 | } | |
7837 | else | |
7838 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7839 | ||
4d7206a2 | 7840 | relax_switch (); |
f5040a92 | 7841 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7842 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7843 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7844 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7845 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7846 | if (add_breg_early) | |
f5040a92 | 7847 | { |
67c0d1eb | 7848 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7849 | treg, tempreg, breg); |
f5040a92 AO |
7850 | breg = 0; |
7851 | tempreg = treg; | |
7852 | } | |
4d7206a2 | 7853 | relax_end (); |
f5040a92 | 7854 | } |
252b5132 RH |
7855 | else |
7856 | abort (); | |
7857 | ||
7858 | if (breg != 0) | |
aed1a261 | 7859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7860 | break; |
7861 | ||
52b6b6b9 | 7862 | case M_MSGSND: |
df58fc94 | 7863 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7864 | { |
7865 | unsigned long temp = (treg << 16) | (0x01); | |
7866 | macro_build (NULL, "c2", "C", temp); | |
7867 | } | |
c7af4273 | 7868 | break; |
52b6b6b9 JM |
7869 | |
7870 | case M_MSGLD: | |
df58fc94 | 7871 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7872 | { |
7873 | unsigned long temp = (0x02); | |
7874 | macro_build (NULL, "c2", "C", temp); | |
7875 | } | |
c7af4273 | 7876 | break; |
52b6b6b9 JM |
7877 | |
7878 | case M_MSGLD_T: | |
df58fc94 | 7879 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7880 | { |
7881 | unsigned long temp = (treg << 16) | (0x02); | |
7882 | macro_build (NULL, "c2", "C", temp); | |
7883 | } | |
c7af4273 | 7884 | break; |
52b6b6b9 JM |
7885 | |
7886 | case M_MSGWAIT: | |
df58fc94 | 7887 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7888 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7889 | break; |
52b6b6b9 JM |
7890 | |
7891 | case M_MSGWAIT_T: | |
df58fc94 | 7892 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7893 | { |
7894 | unsigned long temp = (treg << 16) | 0x03; | |
7895 | macro_build (NULL, "c2", "C", temp); | |
7896 | } | |
c7af4273 | 7897 | break; |
52b6b6b9 | 7898 | |
252b5132 RH |
7899 | case M_J_A: |
7900 | /* The j instruction may not be used in PIC code, since it | |
7901 | requires an absolute address. We convert it to a b | |
7902 | instruction. */ | |
7903 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7904 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7905 | else |
67c0d1eb | 7906 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7907 | break; |
252b5132 RH |
7908 | |
7909 | /* The jal instructions must be handled as macros because when | |
7910 | generating PIC code they expand to multi-instruction | |
7911 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7912 | case M_JALS_1: |
7913 | dreg = RA; | |
7914 | /* Fall through. */ | |
7915 | case M_JALS_2: | |
7916 | gas_assert (mips_opts.micromips); | |
7917 | jals = 1; | |
7918 | goto jal; | |
252b5132 RH |
7919 | case M_JAL_1: |
7920 | dreg = RA; | |
7921 | /* Fall through. */ | |
7922 | case M_JAL_2: | |
df58fc94 | 7923 | jal: |
3e722fb5 | 7924 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7925 | { |
7926 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7927 | if (mips_opts.micromips |
7928 | && dreg == RA | |
7929 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7930 | macro_build (NULL, s, "mj", sreg); |
7931 | else | |
7932 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7933 | } | |
0a44bf69 | 7934 | else |
252b5132 | 7935 | { |
df58fc94 RS |
7936 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7937 | && mips_cprestore_offset >= 0); | |
7938 | ||
252b5132 RH |
7939 | if (sreg != PIC_CALL_REG) |
7940 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7941 | |
df58fc94 RS |
7942 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7943 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7944 | if (mips_opts.micromips |
7945 | && dreg == RA | |
7946 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7947 | macro_build (NULL, s, "mj", sreg); |
7948 | else | |
7949 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7950 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7951 | { |
6478892d TS |
7952 | if (mips_cprestore_offset < 0) |
7953 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7954 | else | |
7955 | { | |
90ecf173 | 7956 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7957 | { |
7958 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7959 | /* Quiet this warning. */ | |
7960 | mips_frame_reg_valid = 1; | |
7961 | } | |
90ecf173 | 7962 | if (!mips_cprestore_valid) |
7a621144 DJ |
7963 | { |
7964 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7965 | /* Quiet this warning. */ | |
7966 | mips_cprestore_valid = 1; | |
7967 | } | |
d3fca0b5 MR |
7968 | if (mips_opts.noreorder) |
7969 | macro_build (NULL, "nop", ""); | |
6478892d | 7970 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7971 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7972 | mips_gp_register, |
256ab948 TS |
7973 | mips_frame_reg, |
7974 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7975 | } |
252b5132 RH |
7976 | } |
7977 | } | |
252b5132 | 7978 | |
8fc2e39e | 7979 | break; |
252b5132 | 7980 | |
df58fc94 RS |
7981 | case M_JALS_A: |
7982 | gas_assert (mips_opts.micromips); | |
7983 | jals = 1; | |
7984 | /* Fall through. */ | |
252b5132 RH |
7985 | case M_JAL_A: |
7986 | if (mips_pic == NO_PIC) | |
df58fc94 | 7987 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7988 | else if (mips_pic == SVR4_PIC) |
7989 | { | |
7990 | /* If this is a reference to an external symbol, and we are | |
7991 | using a small GOT, we want | |
7992 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7993 | nop | |
f9419b05 | 7994 | jalr $ra,$25 |
252b5132 RH |
7995 | nop |
7996 | lw $gp,cprestore($sp) | |
7997 | The cprestore value is set using the .cprestore | |
7998 | pseudo-op. If we are using a big GOT, we want | |
7999 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8000 | addu $25,$25,$gp | |
8001 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8002 | nop | |
f9419b05 | 8003 | jalr $ra,$25 |
252b5132 RH |
8004 | nop |
8005 | lw $gp,cprestore($sp) | |
8006 | If the symbol is not external, we want | |
8007 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8008 | nop | |
8009 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8010 | jalr $ra,$25 |
252b5132 | 8011 | nop |
438c16b8 | 8012 | lw $gp,cprestore($sp) |
f5040a92 AO |
8013 | |
8014 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8015 | sequences above, minus nops, unless the symbol is local, | |
8016 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8017 | GOT_DISP. */ | |
438c16b8 | 8018 | if (HAVE_NEWABI) |
252b5132 | 8019 | { |
90ecf173 | 8020 | if (!mips_big_got) |
f5040a92 | 8021 | { |
4d7206a2 | 8022 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8023 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8024 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8025 | mips_gp_register); |
4d7206a2 | 8026 | relax_switch (); |
67c0d1eb RS |
8027 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8028 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8029 | mips_gp_register); |
8030 | relax_end (); | |
f5040a92 AO |
8031 | } |
8032 | else | |
8033 | { | |
4d7206a2 | 8034 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8035 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8036 | BFD_RELOC_MIPS_CALL_HI16); |
8037 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8038 | PIC_CALL_REG, mips_gp_register); | |
8039 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8040 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8041 | PIC_CALL_REG); | |
4d7206a2 | 8042 | relax_switch (); |
67c0d1eb RS |
8043 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8044 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8045 | mips_gp_register); | |
8046 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8047 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8048 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8049 | relax_end (); |
f5040a92 | 8050 | } |
684022ea | 8051 | |
df58fc94 | 8052 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8053 | } |
8054 | else | |
8055 | { | |
4d7206a2 | 8056 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8057 | if (!mips_big_got) |
438c16b8 | 8058 | { |
67c0d1eb RS |
8059 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8060 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8061 | mips_gp_register); |
269137b2 | 8062 | load_delay_nop (); |
4d7206a2 | 8063 | relax_switch (); |
438c16b8 | 8064 | } |
252b5132 | 8065 | else |
252b5132 | 8066 | { |
67c0d1eb RS |
8067 | int gpdelay; |
8068 | ||
8069 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8070 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8071 | BFD_RELOC_MIPS_CALL_HI16); |
8072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8073 | PIC_CALL_REG, mips_gp_register); | |
8074 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8075 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8076 | PIC_CALL_REG); | |
269137b2 | 8077 | load_delay_nop (); |
4d7206a2 | 8078 | relax_switch (); |
67c0d1eb RS |
8079 | if (gpdelay) |
8080 | macro_build (NULL, "nop", ""); | |
252b5132 | 8081 | } |
67c0d1eb RS |
8082 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8083 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8084 | mips_gp_register); |
269137b2 | 8085 | load_delay_nop (); |
67c0d1eb RS |
8086 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8087 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8088 | relax_end (); |
df58fc94 | 8089 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8090 | |
6478892d TS |
8091 | if (mips_cprestore_offset < 0) |
8092 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8093 | else | |
8094 | { | |
90ecf173 | 8095 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8096 | { |
8097 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8098 | /* Quiet this warning. */ | |
8099 | mips_frame_reg_valid = 1; | |
8100 | } | |
90ecf173 | 8101 | if (!mips_cprestore_valid) |
7a621144 DJ |
8102 | { |
8103 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8104 | /* Quiet this warning. */ | |
8105 | mips_cprestore_valid = 1; | |
8106 | } | |
6478892d | 8107 | if (mips_opts.noreorder) |
67c0d1eb | 8108 | macro_build (NULL, "nop", ""); |
6478892d | 8109 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8110 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8111 | mips_gp_register, |
256ab948 TS |
8112 | mips_frame_reg, |
8113 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8114 | } |
252b5132 RH |
8115 | } |
8116 | } | |
0a44bf69 RS |
8117 | else if (mips_pic == VXWORKS_PIC) |
8118 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8119 | else |
8120 | abort (); | |
8121 | ||
8fc2e39e | 8122 | break; |
252b5132 | 8123 | |
7f3c4072 CM |
8124 | case M_LBUE_AB: |
8125 | ab = 1; | |
8126 | case M_LBUE_OB: | |
8127 | s = "lbue"; | |
8128 | fmt = "t,+j(b)"; | |
8129 | offbits = 9; | |
8130 | goto ld_st; | |
8131 | case M_LHUE_AB: | |
8132 | ab = 1; | |
8133 | case M_LHUE_OB: | |
8134 | s = "lhue"; | |
8135 | fmt = "t,+j(b)"; | |
8136 | offbits = 9; | |
8137 | goto ld_st; | |
8138 | case M_LBE_AB: | |
8139 | ab = 1; | |
8140 | case M_LBE_OB: | |
8141 | s = "lbe"; | |
8142 | fmt = "t,+j(b)"; | |
8143 | offbits = 9; | |
8144 | goto ld_st; | |
8145 | case M_LHE_AB: | |
8146 | ab = 1; | |
8147 | case M_LHE_OB: | |
8148 | s = "lhe"; | |
8149 | fmt = "t,+j(b)"; | |
8150 | offbits = 9; | |
8151 | goto ld_st; | |
8152 | case M_LLE_AB: | |
8153 | ab = 1; | |
8154 | case M_LLE_OB: | |
8155 | s = "lle"; | |
8156 | fmt = "t,+j(b)"; | |
8157 | offbits = 9; | |
8158 | goto ld_st; | |
8159 | case M_LWE_AB: | |
8160 | ab = 1; | |
8161 | case M_LWE_OB: | |
8162 | s = "lwe"; | |
8163 | fmt = "t,+j(b)"; | |
8164 | offbits = 9; | |
8165 | goto ld_st; | |
8166 | case M_LWLE_AB: | |
8167 | ab = 1; | |
8168 | case M_LWLE_OB: | |
8169 | s = "lwle"; | |
8170 | fmt = "t,+j(b)"; | |
8171 | offbits = 9; | |
8172 | goto ld_st; | |
8173 | case M_LWRE_AB: | |
8174 | ab = 1; | |
8175 | case M_LWRE_OB: | |
8176 | s = "lwre"; | |
8177 | fmt = "t,+j(b)"; | |
8178 | offbits = 9; | |
8179 | goto ld_st; | |
8180 | case M_SBE_AB: | |
8181 | ab = 1; | |
8182 | case M_SBE_OB: | |
8183 | s = "sbe"; | |
8184 | fmt = "t,+j(b)"; | |
8185 | offbits = 9; | |
8186 | goto ld_st; | |
8187 | case M_SCE_AB: | |
8188 | ab = 1; | |
8189 | case M_SCE_OB: | |
8190 | s = "sce"; | |
8191 | fmt = "t,+j(b)"; | |
8192 | offbits = 9; | |
8193 | goto ld_st; | |
8194 | case M_SHE_AB: | |
8195 | ab = 1; | |
8196 | case M_SHE_OB: | |
8197 | s = "she"; | |
8198 | fmt = "t,+j(b)"; | |
8199 | offbits = 9; | |
8200 | goto ld_st; | |
8201 | case M_SWE_AB: | |
8202 | ab = 1; | |
8203 | case M_SWE_OB: | |
8204 | s = "swe"; | |
8205 | fmt = "t,+j(b)"; | |
8206 | offbits = 9; | |
8207 | goto ld_st; | |
8208 | case M_SWLE_AB: | |
8209 | ab = 1; | |
8210 | case M_SWLE_OB: | |
8211 | s = "swle"; | |
8212 | fmt = "t,+j(b)"; | |
8213 | offbits = 9; | |
8214 | goto ld_st; | |
8215 | case M_SWRE_AB: | |
8216 | ab = 1; | |
8217 | case M_SWRE_OB: | |
8218 | s = "swre"; | |
8219 | fmt = "t,+j(b)"; | |
8220 | offbits = 9; | |
8221 | goto ld_st; | |
dec0624d MR |
8222 | case M_ACLR_AB: |
8223 | ab = 1; | |
8224 | case M_ACLR_OB: | |
8225 | s = "aclr"; | |
8226 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8227 | fmt = "\\,~(b)"; | |
7f3c4072 | 8228 | offbits = 12; |
dec0624d MR |
8229 | goto ld_st; |
8230 | case M_ASET_AB: | |
8231 | ab = 1; | |
8232 | case M_ASET_OB: | |
8233 | s = "aset"; | |
8234 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8235 | fmt = "\\,~(b)"; | |
7f3c4072 | 8236 | offbits = 12; |
dec0624d | 8237 | goto ld_st; |
252b5132 | 8238 | case M_LB_AB: |
df58fc94 | 8239 | ab = 1; |
252b5132 | 8240 | s = "lb"; |
df58fc94 | 8241 | fmt = "t,o(b)"; |
252b5132 RH |
8242 | goto ld; |
8243 | case M_LBU_AB: | |
df58fc94 | 8244 | ab = 1; |
252b5132 | 8245 | s = "lbu"; |
df58fc94 | 8246 | fmt = "t,o(b)"; |
252b5132 RH |
8247 | goto ld; |
8248 | case M_LH_AB: | |
df58fc94 | 8249 | ab = 1; |
252b5132 | 8250 | s = "lh"; |
df58fc94 | 8251 | fmt = "t,o(b)"; |
252b5132 RH |
8252 | goto ld; |
8253 | case M_LHU_AB: | |
df58fc94 | 8254 | ab = 1; |
252b5132 | 8255 | s = "lhu"; |
df58fc94 | 8256 | fmt = "t,o(b)"; |
252b5132 RH |
8257 | goto ld; |
8258 | case M_LW_AB: | |
df58fc94 | 8259 | ab = 1; |
252b5132 | 8260 | s = "lw"; |
df58fc94 | 8261 | fmt = "t,o(b)"; |
252b5132 RH |
8262 | goto ld; |
8263 | case M_LWC0_AB: | |
df58fc94 RS |
8264 | ab = 1; |
8265 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8266 | s = "lwc0"; |
df58fc94 | 8267 | fmt = "E,o(b)"; |
bdaaa2e1 | 8268 | /* Itbl support may require additional care here. */ |
252b5132 | 8269 | coproc = 1; |
df58fc94 | 8270 | goto ld_st; |
252b5132 | 8271 | case M_LWC1_AB: |
df58fc94 | 8272 | ab = 1; |
252b5132 | 8273 | s = "lwc1"; |
df58fc94 | 8274 | fmt = "T,o(b)"; |
bdaaa2e1 | 8275 | /* Itbl support may require additional care here. */ |
252b5132 | 8276 | coproc = 1; |
df58fc94 | 8277 | goto ld_st; |
252b5132 | 8278 | case M_LWC2_AB: |
df58fc94 RS |
8279 | ab = 1; |
8280 | case M_LWC2_OB: | |
252b5132 | 8281 | s = "lwc2"; |
df58fc94 | 8282 | fmt = COP12_FMT; |
7f3c4072 | 8283 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8284 | /* Itbl support may require additional care here. */ |
252b5132 | 8285 | coproc = 1; |
df58fc94 | 8286 | goto ld_st; |
252b5132 | 8287 | case M_LWC3_AB: |
df58fc94 RS |
8288 | ab = 1; |
8289 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8290 | s = "lwc3"; |
df58fc94 | 8291 | fmt = "E,o(b)"; |
bdaaa2e1 | 8292 | /* Itbl support may require additional care here. */ |
252b5132 | 8293 | coproc = 1; |
df58fc94 | 8294 | goto ld_st; |
252b5132 | 8295 | case M_LWL_AB: |
df58fc94 RS |
8296 | ab = 1; |
8297 | case M_LWL_OB: | |
252b5132 | 8298 | s = "lwl"; |
df58fc94 | 8299 | fmt = MEM12_FMT; |
7f3c4072 | 8300 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8301 | goto ld_st; |
252b5132 | 8302 | case M_LWR_AB: |
df58fc94 RS |
8303 | ab = 1; |
8304 | case M_LWR_OB: | |
252b5132 | 8305 | s = "lwr"; |
df58fc94 | 8306 | fmt = MEM12_FMT; |
7f3c4072 | 8307 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8308 | goto ld_st; |
252b5132 | 8309 | case M_LDC1_AB: |
df58fc94 | 8310 | ab = 1; |
252b5132 | 8311 | s = "ldc1"; |
df58fc94 | 8312 | fmt = "T,o(b)"; |
bdaaa2e1 | 8313 | /* Itbl support may require additional care here. */ |
252b5132 | 8314 | coproc = 1; |
df58fc94 | 8315 | goto ld_st; |
252b5132 | 8316 | case M_LDC2_AB: |
df58fc94 RS |
8317 | ab = 1; |
8318 | case M_LDC2_OB: | |
252b5132 | 8319 | s = "ldc2"; |
df58fc94 | 8320 | fmt = COP12_FMT; |
7f3c4072 | 8321 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8322 | /* Itbl support may require additional care here. */ |
252b5132 | 8323 | coproc = 1; |
df58fc94 | 8324 | goto ld_st; |
c77c0862 RS |
8325 | case M_LQC2_AB: |
8326 | ab = 1; | |
8327 | s = "lqc2"; | |
8328 | fmt = "E,o(b)"; | |
8329 | /* Itbl support may require additional care here. */ | |
8330 | coproc = 1; | |
8331 | goto ld_st; | |
252b5132 | 8332 | case M_LDC3_AB: |
df58fc94 | 8333 | ab = 1; |
252b5132 | 8334 | s = "ldc3"; |
df58fc94 | 8335 | fmt = "E,o(b)"; |
bdaaa2e1 | 8336 | /* Itbl support may require additional care here. */ |
252b5132 | 8337 | coproc = 1; |
df58fc94 | 8338 | goto ld_st; |
252b5132 | 8339 | case M_LDL_AB: |
df58fc94 RS |
8340 | ab = 1; |
8341 | case M_LDL_OB: | |
252b5132 | 8342 | s = "ldl"; |
df58fc94 | 8343 | fmt = MEM12_FMT; |
7f3c4072 | 8344 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8345 | goto ld_st; |
252b5132 | 8346 | case M_LDR_AB: |
df58fc94 RS |
8347 | ab = 1; |
8348 | case M_LDR_OB: | |
252b5132 | 8349 | s = "ldr"; |
df58fc94 | 8350 | fmt = MEM12_FMT; |
7f3c4072 | 8351 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8352 | goto ld_st; |
252b5132 | 8353 | case M_LL_AB: |
df58fc94 RS |
8354 | ab = 1; |
8355 | case M_LL_OB: | |
252b5132 | 8356 | s = "ll"; |
df58fc94 | 8357 | fmt = MEM12_FMT; |
7f3c4072 | 8358 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8359 | goto ld; |
8360 | case M_LLD_AB: | |
df58fc94 RS |
8361 | ab = 1; |
8362 | case M_LLD_OB: | |
252b5132 | 8363 | s = "lld"; |
df58fc94 | 8364 | fmt = MEM12_FMT; |
7f3c4072 | 8365 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8366 | goto ld; |
8367 | case M_LWU_AB: | |
df58fc94 RS |
8368 | ab = 1; |
8369 | case M_LWU_OB: | |
252b5132 | 8370 | s = "lwu"; |
df58fc94 | 8371 | fmt = MEM12_FMT; |
7f3c4072 | 8372 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8373 | goto ld; |
8374 | case M_LWP_AB: | |
8375 | ab = 1; | |
8376 | case M_LWP_OB: | |
8377 | gas_assert (mips_opts.micromips); | |
8378 | s = "lwp"; | |
8379 | fmt = "t,~(b)"; | |
7f3c4072 | 8380 | offbits = 12; |
df58fc94 RS |
8381 | lp = 1; |
8382 | goto ld; | |
8383 | case M_LDP_AB: | |
8384 | ab = 1; | |
8385 | case M_LDP_OB: | |
8386 | gas_assert (mips_opts.micromips); | |
8387 | s = "ldp"; | |
8388 | fmt = "t,~(b)"; | |
7f3c4072 | 8389 | offbits = 12; |
df58fc94 RS |
8390 | lp = 1; |
8391 | goto ld; | |
8392 | case M_LWM_AB: | |
8393 | ab = 1; | |
8394 | case M_LWM_OB: | |
8395 | gas_assert (mips_opts.micromips); | |
8396 | s = "lwm"; | |
8397 | fmt = "n,~(b)"; | |
7f3c4072 | 8398 | offbits = 12; |
df58fc94 RS |
8399 | goto ld_st; |
8400 | case M_LDM_AB: | |
8401 | ab = 1; | |
8402 | case M_LDM_OB: | |
8403 | gas_assert (mips_opts.micromips); | |
8404 | s = "ldm"; | |
8405 | fmt = "n,~(b)"; | |
7f3c4072 | 8406 | offbits = 12; |
df58fc94 RS |
8407 | goto ld_st; |
8408 | ||
252b5132 | 8409 | ld: |
f19ccbda MR |
8410 | /* We don't want to use $0 as tempreg. */ |
8411 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8412 | goto ld_st; |
252b5132 | 8413 | else |
df58fc94 RS |
8414 | tempreg = treg + lp; |
8415 | goto ld_noat; | |
8416 | ||
252b5132 | 8417 | case M_SB_AB: |
df58fc94 | 8418 | ab = 1; |
252b5132 | 8419 | s = "sb"; |
df58fc94 RS |
8420 | fmt = "t,o(b)"; |
8421 | goto ld_st; | |
252b5132 | 8422 | case M_SH_AB: |
df58fc94 | 8423 | ab = 1; |
252b5132 | 8424 | s = "sh"; |
df58fc94 RS |
8425 | fmt = "t,o(b)"; |
8426 | goto ld_st; | |
252b5132 | 8427 | case M_SW_AB: |
df58fc94 | 8428 | ab = 1; |
252b5132 | 8429 | s = "sw"; |
df58fc94 RS |
8430 | fmt = "t,o(b)"; |
8431 | goto ld_st; | |
252b5132 | 8432 | case M_SWC0_AB: |
df58fc94 RS |
8433 | ab = 1; |
8434 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8435 | s = "swc0"; |
df58fc94 | 8436 | fmt = "E,o(b)"; |
bdaaa2e1 | 8437 | /* Itbl support may require additional care here. */ |
252b5132 | 8438 | coproc = 1; |
df58fc94 | 8439 | goto ld_st; |
252b5132 | 8440 | case M_SWC1_AB: |
df58fc94 | 8441 | ab = 1; |
252b5132 | 8442 | s = "swc1"; |
df58fc94 | 8443 | fmt = "T,o(b)"; |
bdaaa2e1 | 8444 | /* Itbl support may require additional care here. */ |
252b5132 | 8445 | coproc = 1; |
df58fc94 | 8446 | goto ld_st; |
252b5132 | 8447 | case M_SWC2_AB: |
df58fc94 RS |
8448 | ab = 1; |
8449 | case M_SWC2_OB: | |
252b5132 | 8450 | s = "swc2"; |
df58fc94 | 8451 | fmt = COP12_FMT; |
7f3c4072 | 8452 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8453 | /* Itbl support may require additional care here. */ |
252b5132 | 8454 | coproc = 1; |
df58fc94 | 8455 | goto ld_st; |
252b5132 | 8456 | case M_SWC3_AB: |
df58fc94 RS |
8457 | ab = 1; |
8458 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8459 | s = "swc3"; |
df58fc94 | 8460 | fmt = "E,o(b)"; |
bdaaa2e1 | 8461 | /* Itbl support may require additional care here. */ |
252b5132 | 8462 | coproc = 1; |
df58fc94 | 8463 | goto ld_st; |
252b5132 | 8464 | case M_SWL_AB: |
df58fc94 RS |
8465 | ab = 1; |
8466 | case M_SWL_OB: | |
252b5132 | 8467 | s = "swl"; |
df58fc94 | 8468 | fmt = MEM12_FMT; |
7f3c4072 | 8469 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8470 | goto ld_st; |
252b5132 | 8471 | case M_SWR_AB: |
df58fc94 RS |
8472 | ab = 1; |
8473 | case M_SWR_OB: | |
252b5132 | 8474 | s = "swr"; |
df58fc94 | 8475 | fmt = MEM12_FMT; |
7f3c4072 | 8476 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8477 | goto ld_st; |
252b5132 | 8478 | case M_SC_AB: |
df58fc94 RS |
8479 | ab = 1; |
8480 | case M_SC_OB: | |
252b5132 | 8481 | s = "sc"; |
df58fc94 | 8482 | fmt = MEM12_FMT; |
7f3c4072 | 8483 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8484 | goto ld_st; |
252b5132 | 8485 | case M_SCD_AB: |
df58fc94 RS |
8486 | ab = 1; |
8487 | case M_SCD_OB: | |
252b5132 | 8488 | s = "scd"; |
df58fc94 | 8489 | fmt = MEM12_FMT; |
7f3c4072 | 8490 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8491 | goto ld_st; |
d43b4baf | 8492 | case M_CACHE_AB: |
df58fc94 RS |
8493 | ab = 1; |
8494 | case M_CACHE_OB: | |
d43b4baf | 8495 | s = "cache"; |
df58fc94 | 8496 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8497 | offbits = (mips_opts.micromips ? 12 : 16); |
8498 | goto ld_st; | |
8499 | case M_CACHEE_AB: | |
8500 | ab = 1; | |
8501 | case M_CACHEE_OB: | |
8502 | s = "cachee"; | |
8503 | fmt = "k,+j(b)"; | |
8504 | offbits = 9; | |
df58fc94 | 8505 | goto ld_st; |
3eebd5eb | 8506 | case M_PREF_AB: |
df58fc94 RS |
8507 | ab = 1; |
8508 | case M_PREF_OB: | |
3eebd5eb | 8509 | s = "pref"; |
df58fc94 | 8510 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8511 | offbits = (mips_opts.micromips ? 12 : 16); |
8512 | goto ld_st; | |
8513 | case M_PREFE_AB: | |
8514 | ab = 1; | |
8515 | case M_PREFE_OB: | |
8516 | s = "prefe"; | |
8517 | fmt = "k,+j(b)"; | |
8518 | offbits = 9; | |
df58fc94 | 8519 | goto ld_st; |
252b5132 | 8520 | case M_SDC1_AB: |
df58fc94 | 8521 | ab = 1; |
252b5132 | 8522 | s = "sdc1"; |
df58fc94 | 8523 | fmt = "T,o(b)"; |
252b5132 | 8524 | coproc = 1; |
bdaaa2e1 | 8525 | /* Itbl support may require additional care here. */ |
df58fc94 | 8526 | goto ld_st; |
252b5132 | 8527 | case M_SDC2_AB: |
df58fc94 RS |
8528 | ab = 1; |
8529 | case M_SDC2_OB: | |
252b5132 | 8530 | s = "sdc2"; |
df58fc94 | 8531 | fmt = COP12_FMT; |
7f3c4072 | 8532 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8533 | /* Itbl support may require additional care here. */ |
8534 | coproc = 1; | |
8535 | goto ld_st; | |
8536 | case M_SQC2_AB: | |
8537 | ab = 1; | |
8538 | s = "sqc2"; | |
8539 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8540 | /* Itbl support may require additional care here. */ |
252b5132 | 8541 | coproc = 1; |
df58fc94 | 8542 | goto ld_st; |
252b5132 | 8543 | case M_SDC3_AB: |
df58fc94 RS |
8544 | ab = 1; |
8545 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8546 | s = "sdc3"; |
df58fc94 | 8547 | fmt = "E,o(b)"; |
bdaaa2e1 | 8548 | /* Itbl support may require additional care here. */ |
252b5132 | 8549 | coproc = 1; |
df58fc94 | 8550 | goto ld_st; |
252b5132 | 8551 | case M_SDL_AB: |
df58fc94 RS |
8552 | ab = 1; |
8553 | case M_SDL_OB: | |
252b5132 | 8554 | s = "sdl"; |
df58fc94 | 8555 | fmt = MEM12_FMT; |
7f3c4072 | 8556 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8557 | goto ld_st; |
252b5132 | 8558 | case M_SDR_AB: |
df58fc94 RS |
8559 | ab = 1; |
8560 | case M_SDR_OB: | |
252b5132 | 8561 | s = "sdr"; |
df58fc94 | 8562 | fmt = MEM12_FMT; |
7f3c4072 | 8563 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8564 | goto ld_st; |
8565 | case M_SWP_AB: | |
8566 | ab = 1; | |
8567 | case M_SWP_OB: | |
8568 | gas_assert (mips_opts.micromips); | |
8569 | s = "swp"; | |
8570 | fmt = "t,~(b)"; | |
7f3c4072 | 8571 | offbits = 12; |
df58fc94 RS |
8572 | goto ld_st; |
8573 | case M_SDP_AB: | |
8574 | ab = 1; | |
8575 | case M_SDP_OB: | |
8576 | gas_assert (mips_opts.micromips); | |
8577 | s = "sdp"; | |
8578 | fmt = "t,~(b)"; | |
7f3c4072 | 8579 | offbits = 12; |
df58fc94 RS |
8580 | goto ld_st; |
8581 | case M_SWM_AB: | |
8582 | ab = 1; | |
8583 | case M_SWM_OB: | |
8584 | gas_assert (mips_opts.micromips); | |
8585 | s = "swm"; | |
8586 | fmt = "n,~(b)"; | |
7f3c4072 | 8587 | offbits = 12; |
df58fc94 RS |
8588 | goto ld_st; |
8589 | case M_SDM_AB: | |
8590 | ab = 1; | |
8591 | case M_SDM_OB: | |
8592 | gas_assert (mips_opts.micromips); | |
8593 | s = "sdm"; | |
8594 | fmt = "n,~(b)"; | |
7f3c4072 | 8595 | offbits = 12; |
df58fc94 RS |
8596 | |
8597 | ld_st: | |
8fc2e39e TS |
8598 | tempreg = AT; |
8599 | used_at = 1; | |
df58fc94 | 8600 | ld_noat: |
252b5132 RH |
8601 | if (offset_expr.X_op != O_constant |
8602 | && offset_expr.X_op != O_symbol) | |
8603 | { | |
f71d0d44 | 8604 | as_bad (_("Expression too complex")); |
252b5132 RH |
8605 | offset_expr.X_op = O_constant; |
8606 | } | |
8607 | ||
2051e8c4 MR |
8608 | if (HAVE_32BIT_ADDRESSES |
8609 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8610 | { |
8611 | char value [32]; | |
8612 | ||
8613 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8614 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8615 | } |
2051e8c4 | 8616 | |
252b5132 RH |
8617 | /* A constant expression in PIC code can be handled just as it |
8618 | is in non PIC code. */ | |
aed1a261 RS |
8619 | if (offset_expr.X_op == O_constant) |
8620 | { | |
df58fc94 RS |
8621 | int hipart = 0; |
8622 | ||
842f8b2a | 8623 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8624 | normalize_address_expr (&expr1); |
7f3c4072 CM |
8625 | if ((offbits == 0 || offbits == 16) |
8626 | && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) | |
842f8b2a MR |
8627 | { |
8628 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8629 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8630 | hipart = 1; |
8631 | } | |
7f3c4072 | 8632 | else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) |
df58fc94 RS |
8633 | { |
8634 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8635 | & ~(bfd_vma) 0xfff); | |
8636 | hipart = 1; | |
8637 | } | |
7f3c4072 CM |
8638 | else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number)) |
8639 | { | |
8640 | expr1.X_add_number = ((expr1.X_add_number + 0x100) | |
8641 | & ~(bfd_vma) 0x1ff); | |
8642 | hipart = 1; | |
8643 | } | |
df58fc94 RS |
8644 | if (hipart) |
8645 | { | |
842f8b2a MR |
8646 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8647 | if (breg != 0) | |
8648 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8649 | tempreg, tempreg, breg); | |
8650 | breg = tempreg; | |
8651 | } | |
7f3c4072 | 8652 | if (offbits == 0) |
dd6a37e7 AP |
8653 | { |
8654 | if (offset_expr.X_add_number == 0) | |
8655 | tempreg = breg; | |
8656 | else | |
8657 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8658 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8659 | macro_build (NULL, s, fmt, treg, tempreg); | |
8660 | } | |
7f3c4072 | 8661 | else if (offbits == 16) |
df58fc94 RS |
8662 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8663 | else | |
8664 | macro_build (NULL, s, fmt, | |
8665 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8666 | } | |
7f3c4072 | 8667 | else if (offbits != 16) |
df58fc94 | 8668 | { |
7f3c4072 CM |
8669 | /* The offset field is too narrow to be used for a low-part |
8670 | relocation, so load the whole address into the auxillary | |
8671 | register. In the case of "A(b)" addresses, we first load | |
8672 | absolute address "A" into the register and then add base | |
8673 | register "b". In the case of "o(b)" addresses, we simply | |
8674 | need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8675 | offset_reloc already contains the relocations associated |
8676 | with "o". */ | |
8677 | if (ab) | |
8678 | { | |
8679 | load_address (tempreg, &offset_expr, &used_at); | |
8680 | if (breg != 0) | |
8681 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8682 | tempreg, tempreg, breg); | |
8683 | } | |
8684 | else | |
8685 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8686 | tempreg, breg, -1, | |
8687 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8688 | expr1.X_add_number = 0; | |
7f3c4072 | 8689 | if (offbits == 0) |
dd6a37e7 AP |
8690 | macro_build (NULL, s, fmt, treg, tempreg); |
8691 | else | |
8692 | macro_build (NULL, s, fmt, | |
8693 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8694 | } |
8695 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8696 | { |
8697 | /* If this is a reference to a GP relative symbol, and there | |
8698 | is no base register, we want | |
cdf6fd85 | 8699 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8700 | Otherwise, if there is no base register, we want |
8701 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8702 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8703 | If we have a constant, we need two instructions anyhow, | |
8704 | so we always use the latter form. | |
8705 | ||
8706 | If we have a base register, and this is a reference to a | |
8707 | GP relative symbol, we want | |
8708 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8709 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8710 | Otherwise we want |
8711 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8712 | addu $tempreg,$tempreg,$breg | |
8713 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8714 | With a constant we always use the latter case. |
76b3015f | 8715 | |
d6bc6245 TS |
8716 | With 64bit address space and no base register and $at usable, |
8717 | we want | |
8718 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8719 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8720 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8721 | dsll32 $tempreg,0 | |
8722 | daddu $tempreg,$at | |
8723 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8724 | If we have a base register, we want | |
8725 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8726 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8727 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8728 | daddu $at,$breg | |
8729 | dsll32 $tempreg,0 | |
8730 | daddu $tempreg,$at | |
8731 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8732 | ||
8733 | Without $at we can't generate the optimal path for superscalar | |
8734 | processors here since this would require two temporary registers. | |
8735 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8736 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8737 | dsll $tempreg,16 | |
8738 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8739 | dsll $tempreg,16 | |
8740 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8741 | If we have a base register, we want | |
8742 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8743 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8744 | dsll $tempreg,16 | |
8745 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8746 | dsll $tempreg,16 | |
8747 | daddu $tempreg,$tempreg,$breg | |
8748 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8749 | |
6caf9ef4 | 8750 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8751 | the same sequence as in 32bit address space. */ |
8752 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8753 | { |
aed1a261 | 8754 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8755 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8756 | { | |
8757 | relax_start (offset_expr.X_add_symbol); | |
8758 | if (breg == 0) | |
8759 | { | |
8760 | macro_build (&offset_expr, s, fmt, treg, | |
8761 | BFD_RELOC_GPREL16, mips_gp_register); | |
8762 | } | |
8763 | else | |
8764 | { | |
8765 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8766 | tempreg, breg, mips_gp_register); | |
8767 | macro_build (&offset_expr, s, fmt, treg, | |
8768 | BFD_RELOC_GPREL16, tempreg); | |
8769 | } | |
8770 | relax_switch (); | |
8771 | } | |
d6bc6245 | 8772 | |
741fe287 | 8773 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8774 | { |
df58fc94 | 8775 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8776 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8777 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8778 | BFD_RELOC_HI16_S); |
8779 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8780 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8781 | if (breg != 0) |
67c0d1eb | 8782 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8783 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8784 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8785 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8786 | tempreg); | |
d6bc6245 TS |
8787 | used_at = 1; |
8788 | } | |
8789 | else | |
8790 | { | |
df58fc94 | 8791 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8792 | BFD_RELOC_MIPS_HIGHEST); |
8793 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8794 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8795 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8796 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8797 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8798 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8799 | if (breg != 0) |
67c0d1eb | 8800 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8801 | tempreg, tempreg, breg); |
67c0d1eb | 8802 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8803 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8804 | } |
6caf9ef4 TS |
8805 | |
8806 | if (mips_relax.sequence) | |
8807 | relax_end (); | |
8fc2e39e | 8808 | break; |
d6bc6245 | 8809 | } |
256ab948 | 8810 | |
252b5132 RH |
8811 | if (breg == 0) |
8812 | { | |
67c0d1eb | 8813 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8814 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8815 | { |
4d7206a2 | 8816 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8817 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8818 | mips_gp_register); | |
4d7206a2 | 8819 | relax_switch (); |
252b5132 | 8820 | } |
67c0d1eb RS |
8821 | macro_build_lui (&offset_expr, tempreg); |
8822 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8823 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8824 | if (mips_relax.sequence) |
8825 | relax_end (); | |
252b5132 RH |
8826 | } |
8827 | else | |
8828 | { | |
67c0d1eb | 8829 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8830 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8831 | { |
4d7206a2 | 8832 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8833 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8834 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8835 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8836 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8837 | relax_switch (); |
252b5132 | 8838 | } |
67c0d1eb RS |
8839 | macro_build_lui (&offset_expr, tempreg); |
8840 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8841 | tempreg, tempreg, breg); |
67c0d1eb | 8842 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8843 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8844 | if (mips_relax.sequence) |
8845 | relax_end (); | |
252b5132 RH |
8846 | } |
8847 | } | |
0a44bf69 | 8848 | else if (!mips_big_got) |
252b5132 | 8849 | { |
ed6fb7bd | 8850 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8851 | |
252b5132 RH |
8852 | /* If this is a reference to an external symbol, we want |
8853 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8854 | nop | |
8855 | <op> $treg,0($tempreg) | |
8856 | Otherwise we want | |
8857 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8858 | nop | |
8859 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8860 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8861 | |
8862 | For NewABI, we want | |
8863 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8864 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8865 | ||
252b5132 RH |
8866 | If there is a base register, we add it to $tempreg before |
8867 | the <op>. If there is a constant, we stick it in the | |
8868 | <op> instruction. We don't handle constants larger than | |
8869 | 16 bits, because we have no way to load the upper 16 bits | |
8870 | (actually, we could handle them for the subset of cases | |
8871 | in which we are not using $at). */ | |
9c2799c2 | 8872 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8873 | if (HAVE_NEWABI) |
8874 | { | |
67c0d1eb RS |
8875 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8876 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8877 | if (breg != 0) |
67c0d1eb | 8878 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8879 | tempreg, tempreg, breg); |
67c0d1eb | 8880 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8881 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8882 | break; |
8883 | } | |
252b5132 RH |
8884 | expr1.X_add_number = offset_expr.X_add_number; |
8885 | offset_expr.X_add_number = 0; | |
8886 | if (expr1.X_add_number < -0x8000 | |
8887 | || expr1.X_add_number >= 0x8000) | |
8888 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8889 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8890 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8891 | load_delay_nop (); |
4d7206a2 RS |
8892 | relax_start (offset_expr.X_add_symbol); |
8893 | relax_switch (); | |
67c0d1eb RS |
8894 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8895 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8896 | relax_end (); |
252b5132 | 8897 | if (breg != 0) |
67c0d1eb | 8898 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8899 | tempreg, tempreg, breg); |
67c0d1eb | 8900 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8901 | } |
0a44bf69 | 8902 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8903 | { |
67c0d1eb | 8904 | int gpdelay; |
252b5132 RH |
8905 | |
8906 | /* If this is a reference to an external symbol, we want | |
8907 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8908 | addu $tempreg,$tempreg,$gp | |
8909 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8910 | <op> $treg,0($tempreg) | |
8911 | Otherwise we want | |
8912 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8913 | nop | |
8914 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8915 | <op> $treg,0($tempreg) | |
8916 | If there is a base register, we add it to $tempreg before | |
8917 | the <op>. If there is a constant, we stick it in the | |
8918 | <op> instruction. We don't handle constants larger than | |
8919 | 16 bits, because we have no way to load the upper 16 bits | |
8920 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8921 | in which we are not using $at). */ |
9c2799c2 | 8922 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8923 | expr1.X_add_number = offset_expr.X_add_number; |
8924 | offset_expr.X_add_number = 0; | |
8925 | if (expr1.X_add_number < -0x8000 | |
8926 | || expr1.X_add_number >= 0x8000) | |
8927 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8928 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8929 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8930 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8931 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8932 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8933 | mips_gp_register); | |
8934 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8935 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8936 | relax_switch (); |
67c0d1eb RS |
8937 | if (gpdelay) |
8938 | macro_build (NULL, "nop", ""); | |
8939 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8940 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8941 | load_delay_nop (); |
67c0d1eb RS |
8942 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8943 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8944 | relax_end (); |
8945 | ||
252b5132 | 8946 | if (breg != 0) |
67c0d1eb | 8947 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8948 | tempreg, tempreg, breg); |
67c0d1eb | 8949 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8950 | } |
0a44bf69 | 8951 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8952 | { |
f5040a92 AO |
8953 | /* If this is a reference to an external symbol, we want |
8954 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8955 | add $tempreg,$tempreg,$gp | |
8956 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8957 | <op> $treg,<ofst>($tempreg) | |
8958 | Otherwise, for local symbols, we want: | |
8959 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8960 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8961 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8962 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8963 | offset_expr.X_add_number = 0; |
8964 | if (expr1.X_add_number < -0x8000 | |
8965 | || expr1.X_add_number >= 0x8000) | |
8966 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8967 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8968 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8969 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8970 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8971 | mips_gp_register); | |
8972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8973 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8974 | if (breg != 0) |
67c0d1eb | 8975 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8976 | tempreg, tempreg, breg); |
67c0d1eb | 8977 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8978 | |
4d7206a2 | 8979 | relax_switch (); |
f5040a92 | 8980 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8981 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8982 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8983 | if (breg != 0) |
67c0d1eb | 8984 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8985 | tempreg, tempreg, breg); |
67c0d1eb | 8986 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8987 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8988 | relax_end (); |
f5040a92 | 8989 | } |
252b5132 RH |
8990 | else |
8991 | abort (); | |
8992 | ||
252b5132 RH |
8993 | break; |
8994 | ||
8995 | case M_LI: | |
8996 | case M_LI_S: | |
67c0d1eb | 8997 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8998 | break; |
252b5132 RH |
8999 | |
9000 | case M_DLI: | |
67c0d1eb | 9001 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9002 | break; |
252b5132 RH |
9003 | |
9004 | case M_LI_SS: | |
9005 | if (imm_expr.X_op == O_constant) | |
9006 | { | |
8fc2e39e | 9007 | used_at = 1; |
67c0d1eb RS |
9008 | load_register (AT, &imm_expr, 0); |
9009 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9010 | break; |
9011 | } | |
9012 | else | |
9013 | { | |
9c2799c2 | 9014 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9015 | && strcmp (segment_name (S_GET_SEGMENT |
9016 | (offset_expr.X_add_symbol)), | |
9017 | ".lit4") == 0 | |
9018 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9019 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9020 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9021 | break; |
252b5132 RH |
9022 | } |
9023 | ||
9024 | case M_LI_D: | |
ca4e0257 RS |
9025 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9026 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9027 | order 32 bits of the value and the low order 32 bits are either | |
9028 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9029 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9030 | { | |
ca4e0257 | 9031 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9032 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9033 | else |
9034 | { | |
9035 | int hreg, lreg; | |
9036 | ||
9037 | if (target_big_endian) | |
9038 | { | |
9039 | hreg = treg; | |
9040 | lreg = treg + 1; | |
9041 | } | |
9042 | else | |
9043 | { | |
9044 | hreg = treg + 1; | |
9045 | lreg = treg; | |
9046 | } | |
9047 | ||
9048 | if (hreg <= 31) | |
67c0d1eb | 9049 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9050 | if (lreg <= 31) |
9051 | { | |
9052 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9053 | move_register (lreg, 0); |
252b5132 RH |
9054 | else |
9055 | { | |
9c2799c2 | 9056 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9057 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9058 | } |
9059 | } | |
9060 | } | |
8fc2e39e | 9061 | break; |
252b5132 RH |
9062 | } |
9063 | ||
9064 | /* We know that sym is in the .rdata section. First we get the | |
9065 | upper 16 bits of the address. */ | |
9066 | if (mips_pic == NO_PIC) | |
9067 | { | |
67c0d1eb | 9068 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9069 | used_at = 1; |
252b5132 | 9070 | } |
0a44bf69 | 9071 | else |
252b5132 | 9072 | { |
67c0d1eb RS |
9073 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9074 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9075 | used_at = 1; |
252b5132 | 9076 | } |
bdaaa2e1 | 9077 | |
252b5132 | 9078 | /* Now we load the register(s). */ |
ca4e0257 | 9079 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9080 | { |
9081 | used_at = 1; | |
9082 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9083 | } | |
252b5132 RH |
9084 | else |
9085 | { | |
8fc2e39e | 9086 | used_at = 1; |
67c0d1eb | 9087 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9088 | if (treg != RA) |
252b5132 RH |
9089 | { |
9090 | /* FIXME: How in the world do we deal with the possible | |
9091 | overflow here? */ | |
9092 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9093 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9094 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9095 | } |
9096 | } | |
252b5132 RH |
9097 | break; |
9098 | ||
9099 | case M_LI_DD: | |
ca4e0257 RS |
9100 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9101 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9102 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9103 | the value and the low order 32 bits are either zero or in | |
9104 | OFFSET_EXPR. */ | |
252b5132 RH |
9105 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9106 | { | |
8fc2e39e | 9107 | used_at = 1; |
67c0d1eb | 9108 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9109 | if (HAVE_64BIT_FPRS) |
9110 | { | |
9c2799c2 | 9111 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9112 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9113 | } |
252b5132 RH |
9114 | else |
9115 | { | |
67c0d1eb | 9116 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9117 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9118 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9119 | else |
9120 | { | |
9c2799c2 | 9121 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9122 | load_register (AT, &offset_expr, 0); |
9123 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9124 | } |
9125 | } | |
9126 | break; | |
9127 | } | |
9128 | ||
9c2799c2 | 9129 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9130 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9131 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9132 | if (strcmp (s, ".lit8") == 0) | |
9133 | { | |
0aa27725 | 9134 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9135 | { |
67c0d1eb | 9136 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 9137 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9138 | break; |
252b5132 | 9139 | } |
c9914766 | 9140 | breg = mips_gp_register; |
252b5132 RH |
9141 | r = BFD_RELOC_MIPS_LITERAL; |
9142 | goto dob; | |
9143 | } | |
9144 | else | |
9145 | { | |
9c2799c2 | 9146 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9147 | used_at = 1; |
0a44bf69 | 9148 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9149 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9150 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9151 | else |
9152 | { | |
9153 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9154 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9155 | } |
bdaaa2e1 | 9156 | |
0aa27725 | 9157 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9158 | { |
67c0d1eb RS |
9159 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9160 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9161 | break; |
9162 | } | |
9163 | breg = AT; | |
9164 | r = BFD_RELOC_LO16; | |
9165 | goto dob; | |
9166 | } | |
9167 | ||
9168 | case M_L_DOB: | |
252b5132 RH |
9169 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9170 | to adjust when loading from memory. */ | |
9171 | r = BFD_RELOC_LO16; | |
9172 | dob: | |
df58fc94 | 9173 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9174 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9175 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9176 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9177 | /* FIXME: A possible overflow which I don't know how to deal |
9178 | with. */ | |
9179 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9180 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9181 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9182 | break; |
9183 | ||
c4a68bea | 9184 | case M_S_DOB: |
df58fc94 | 9185 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9186 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9187 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9188 | to adjust when storing to memory. */ | |
9189 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9190 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9191 | offset_expr.X_add_number += 4; | |
9192 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9193 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9194 | break; | |
9195 | ||
252b5132 | 9196 | case M_L_DAB: |
df58fc94 | 9197 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9198 | /* |
9199 | * The MIPS assembler seems to check for X_add_number not | |
9200 | * being double aligned and generating: | |
9201 | * lui at,%hi(foo+1) | |
9202 | * addu at,at,v1 | |
9203 | * addiu at,at,%lo(foo+1) | |
9204 | * lwc1 f2,0(at) | |
9205 | * lwc1 f3,4(at) | |
9206 | * But, the resulting address is the same after relocation so why | |
9207 | * generate the extra instruction? | |
9208 | */ | |
bdaaa2e1 | 9209 | /* Itbl support may require additional care here. */ |
252b5132 | 9210 | coproc = 1; |
df58fc94 | 9211 | fmt = "T,o(b)"; |
0aa27725 | 9212 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9213 | { |
9214 | s = "ldc1"; | |
df58fc94 | 9215 | goto ld_st; |
252b5132 | 9216 | } |
252b5132 | 9217 | s = "lwc1"; |
252b5132 RH |
9218 | goto ldd_std; |
9219 | ||
9220 | case M_S_DAB: | |
df58fc94 RS |
9221 | gas_assert (!mips_opts.micromips); |
9222 | /* Itbl support may require additional care here. */ | |
9223 | coproc = 1; | |
9224 | fmt = "T,o(b)"; | |
0aa27725 | 9225 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9226 | { |
9227 | s = "sdc1"; | |
df58fc94 | 9228 | goto ld_st; |
252b5132 | 9229 | } |
252b5132 | 9230 | s = "swc1"; |
252b5132 RH |
9231 | goto ldd_std; |
9232 | ||
e407c74b NC |
9233 | case M_LQ_AB: |
9234 | fmt = "t,o(b)"; | |
9235 | s = "lq"; | |
9236 | goto ld; | |
9237 | ||
9238 | case M_SQ_AB: | |
9239 | fmt = "t,o(b)"; | |
9240 | s = "sq"; | |
9241 | goto ld_st; | |
9242 | ||
252b5132 | 9243 | case M_LD_AB: |
df58fc94 | 9244 | fmt = "t,o(b)"; |
ca4e0257 | 9245 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9246 | { |
9247 | s = "ld"; | |
9248 | goto ld; | |
9249 | } | |
252b5132 | 9250 | s = "lw"; |
252b5132 RH |
9251 | goto ldd_std; |
9252 | ||
9253 | case M_SD_AB: | |
df58fc94 | 9254 | fmt = "t,o(b)"; |
ca4e0257 | 9255 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9256 | { |
9257 | s = "sd"; | |
df58fc94 | 9258 | goto ld_st; |
252b5132 | 9259 | } |
252b5132 | 9260 | s = "sw"; |
252b5132 RH |
9261 | |
9262 | ldd_std: | |
9263 | if (offset_expr.X_op != O_symbol | |
9264 | && offset_expr.X_op != O_constant) | |
9265 | { | |
f71d0d44 | 9266 | as_bad (_("Expression too complex")); |
252b5132 RH |
9267 | offset_expr.X_op = O_constant; |
9268 | } | |
9269 | ||
2051e8c4 MR |
9270 | if (HAVE_32BIT_ADDRESSES |
9271 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9272 | { |
9273 | char value [32]; | |
9274 | ||
9275 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9276 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9277 | } |
2051e8c4 | 9278 | |
252b5132 RH |
9279 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9280 | to adjust when loading from memory. We set coproc if we must | |
9281 | load $fn+1 first. */ | |
bdaaa2e1 | 9282 | /* Itbl support may require additional care here. */ |
90ecf173 | 9283 | if (!target_big_endian) |
252b5132 RH |
9284 | coproc = 0; |
9285 | ||
90ecf173 | 9286 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9287 | { |
9288 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9289 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9290 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9291 | If we have a base register, we use this |
9292 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9293 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9294 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9295 | If this is not a GP relative symbol, we want |
9296 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9297 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9298 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9299 | If there is a base register, we add it to $at after the | |
9300 | lui instruction. If there is a constant, we always use | |
9301 | the last case. */ | |
39a59cf8 MR |
9302 | if (offset_expr.X_op == O_symbol |
9303 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9304 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9305 | { |
4d7206a2 | 9306 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9307 | if (breg == 0) |
9308 | { | |
c9914766 | 9309 | tempreg = mips_gp_register; |
252b5132 RH |
9310 | } |
9311 | else | |
9312 | { | |
67c0d1eb | 9313 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9314 | AT, breg, mips_gp_register); |
252b5132 | 9315 | tempreg = AT; |
252b5132 RH |
9316 | used_at = 1; |
9317 | } | |
9318 | ||
beae10d5 | 9319 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9320 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9321 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9322 | offset_expr.X_add_number += 4; |
9323 | ||
9324 | /* Set mips_optimize to 2 to avoid inserting an | |
9325 | undesired nop. */ | |
9326 | hold_mips_optimize = mips_optimize; | |
9327 | mips_optimize = 2; | |
beae10d5 | 9328 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9329 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9330 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9331 | mips_optimize = hold_mips_optimize; |
9332 | ||
4d7206a2 | 9333 | relax_switch (); |
252b5132 | 9334 | |
0970e49e | 9335 | offset_expr.X_add_number -= 4; |
252b5132 | 9336 | } |
8fc2e39e | 9337 | used_at = 1; |
67c0d1eb | 9338 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9339 | if (breg != 0) |
67c0d1eb | 9340 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9341 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9342 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9343 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9344 | /* FIXME: How do we handle overflow here? */ |
9345 | offset_expr.X_add_number += 4; | |
beae10d5 | 9346 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9347 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9348 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9349 | if (mips_relax.sequence) |
9350 | relax_end (); | |
bdaaa2e1 | 9351 | } |
0a44bf69 | 9352 | else if (!mips_big_got) |
252b5132 | 9353 | { |
252b5132 RH |
9354 | /* If this is a reference to an external symbol, we want |
9355 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9356 | nop | |
9357 | <op> $treg,0($at) | |
9358 | <op> $treg+1,4($at) | |
9359 | Otherwise we want | |
9360 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9361 | nop | |
9362 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9363 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9364 | If there is a base register we add it to $at before the | |
9365 | lwc1 instructions. If there is a constant we include it | |
9366 | in the lwc1 instructions. */ | |
9367 | used_at = 1; | |
9368 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9369 | if (expr1.X_add_number < -0x8000 |
9370 | || expr1.X_add_number >= 0x8000 - 4) | |
9371 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9372 | load_got_offset (AT, &offset_expr); |
269137b2 | 9373 | load_delay_nop (); |
252b5132 | 9374 | if (breg != 0) |
67c0d1eb | 9375 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9376 | |
9377 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9378 | nop. */ | |
9379 | hold_mips_optimize = mips_optimize; | |
9380 | mips_optimize = 2; | |
4d7206a2 | 9381 | |
beae10d5 | 9382 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9383 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9384 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9385 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9386 | expr1.X_add_number += 4; |
67c0d1eb RS |
9387 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9388 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9389 | relax_switch (); |
67c0d1eb RS |
9390 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9391 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9392 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9393 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9394 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9395 | relax_end (); |
252b5132 | 9396 | |
4d7206a2 | 9397 | mips_optimize = hold_mips_optimize; |
252b5132 | 9398 | } |
0a44bf69 | 9399 | else if (mips_big_got) |
252b5132 | 9400 | { |
67c0d1eb | 9401 | int gpdelay; |
252b5132 RH |
9402 | |
9403 | /* If this is a reference to an external symbol, we want | |
9404 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9405 | addu $at,$at,$gp | |
9406 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9407 | nop | |
9408 | <op> $treg,0($at) | |
9409 | <op> $treg+1,4($at) | |
9410 | Otherwise we want | |
9411 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9412 | nop | |
9413 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9414 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9415 | If there is a base register we add it to $at before the | |
9416 | lwc1 instructions. If there is a constant we include it | |
9417 | in the lwc1 instructions. */ | |
9418 | used_at = 1; | |
9419 | expr1.X_add_number = offset_expr.X_add_number; | |
9420 | offset_expr.X_add_number = 0; | |
9421 | if (expr1.X_add_number < -0x8000 | |
9422 | || expr1.X_add_number >= 0x8000 - 4) | |
9423 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9424 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9425 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9426 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9427 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9428 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9429 | AT, AT, mips_gp_register); |
67c0d1eb | 9430 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9431 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9432 | load_delay_nop (); |
252b5132 | 9433 | if (breg != 0) |
67c0d1eb | 9434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9435 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9436 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9437 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9438 | expr1.X_add_number += 4; |
9439 | ||
9440 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9441 | nop. */ | |
9442 | hold_mips_optimize = mips_optimize; | |
9443 | mips_optimize = 2; | |
beae10d5 | 9444 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9445 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9446 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9447 | mips_optimize = hold_mips_optimize; |
9448 | expr1.X_add_number -= 4; | |
9449 | ||
4d7206a2 RS |
9450 | relax_switch (); |
9451 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9452 | if (gpdelay) |
9453 | macro_build (NULL, "nop", ""); | |
9454 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9455 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9456 | load_delay_nop (); |
252b5132 | 9457 | if (breg != 0) |
67c0d1eb | 9458 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9459 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9460 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9461 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9462 | offset_expr.X_add_number += 4; |
252b5132 RH |
9463 | |
9464 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9465 | nop. */ | |
9466 | hold_mips_optimize = mips_optimize; | |
9467 | mips_optimize = 2; | |
beae10d5 | 9468 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9469 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9470 | BFD_RELOC_LO16, AT); | |
252b5132 | 9471 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9472 | relax_end (); |
252b5132 | 9473 | } |
252b5132 RH |
9474 | else |
9475 | abort (); | |
9476 | ||
252b5132 RH |
9477 | break; |
9478 | ||
9479 | case M_LD_OB: | |
704897fb | 9480 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9481 | goto sd_ob; |
9482 | case M_SD_OB: | |
704897fb | 9483 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9484 | sd_ob: |
4614d845 MR |
9485 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9486 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9487 | breg); | |
704897fb MR |
9488 | if (!HAVE_64BIT_GPRS) |
9489 | { | |
9490 | offset_expr.X_add_number += 4; | |
9491 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9492 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9493 | breg); | |
704897fb | 9494 | } |
8fc2e39e | 9495 | break; |
252b5132 | 9496 | |
dd6a37e7 AP |
9497 | |
9498 | case M_SAA_AB: | |
9499 | ab = 1; | |
9500 | case M_SAA_OB: | |
9501 | s = "saa"; | |
7f3c4072 | 9502 | offbits = 0; |
dd6a37e7 AP |
9503 | fmt = "t,(b)"; |
9504 | goto ld_st; | |
9505 | case M_SAAD_AB: | |
9506 | ab = 1; | |
9507 | case M_SAAD_OB: | |
9508 | s = "saad"; | |
7f3c4072 | 9509 | offbits = 0; |
dd6a37e7 AP |
9510 | fmt = "t,(b)"; |
9511 | goto ld_st; | |
9512 | ||
252b5132 RH |
9513 | /* New code added to support COPZ instructions. |
9514 | This code builds table entries out of the macros in mip_opcodes. | |
9515 | R4000 uses interlocks to handle coproc delays. | |
9516 | Other chips (like the R3000) require nops to be inserted for delays. | |
9517 | ||
f72c8c98 | 9518 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9519 | In order to fill delay slots for non-interlocked chips, |
9520 | we must have a way to specify delays based on the coprocessor. | |
9521 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9522 | What are the side-effects of the cop instruction? | |
9523 | What cache support might we have and what are its effects? | |
9524 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9525 | What registers are read/set/modified? |
252b5132 RH |
9526 | |
9527 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9528 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9529 | |
9530 | case M_COP0: | |
9531 | s = "c0"; | |
9532 | goto copz; | |
9533 | case M_COP1: | |
9534 | s = "c1"; | |
9535 | goto copz; | |
9536 | case M_COP2: | |
9537 | s = "c2"; | |
9538 | goto copz; | |
9539 | case M_COP3: | |
9540 | s = "c3"; | |
9541 | copz: | |
df58fc94 | 9542 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9543 | /* For now we just do C (same as Cz). The parameter will be |
9544 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9545 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9546 | break; |
252b5132 | 9547 | |
ea1fb5dc | 9548 | case M_MOVE: |
67c0d1eb | 9549 | move_register (dreg, sreg); |
8fc2e39e | 9550 | break; |
ea1fb5dc | 9551 | |
252b5132 RH |
9552 | case M_DMUL: |
9553 | dbl = 1; | |
9554 | case M_MUL: | |
e407c74b NC |
9555 | if (mips_opts.arch == CPU_R5900) |
9556 | { | |
9557 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9558 | } | |
9559 | else | |
9560 | { | |
67c0d1eb | 9561 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9562 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9563 | } |
8fc2e39e | 9564 | break; |
252b5132 RH |
9565 | |
9566 | case M_DMUL_I: | |
9567 | dbl = 1; | |
9568 | case M_MUL_I: | |
9569 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9570 | not trying to be that fancy. GCC should do this for us | |
9571 | anyway. */ | |
8fc2e39e | 9572 | used_at = 1; |
67c0d1eb RS |
9573 | load_register (AT, &imm_expr, dbl); |
9574 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9575 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9576 | break; |
9577 | ||
9578 | case M_DMULO_I: | |
9579 | dbl = 1; | |
9580 | case M_MULO_I: | |
9581 | imm = 1; | |
9582 | goto do_mulo; | |
9583 | ||
9584 | case M_DMULO: | |
9585 | dbl = 1; | |
9586 | case M_MULO: | |
9587 | do_mulo: | |
7d10b47d | 9588 | start_noreorder (); |
8fc2e39e | 9589 | used_at = 1; |
252b5132 | 9590 | if (imm) |
67c0d1eb RS |
9591 | load_register (AT, &imm_expr, dbl); |
9592 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9593 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9594 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9595 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9596 | if (mips_trap) |
df58fc94 | 9597 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9598 | else |
9599 | { | |
df58fc94 RS |
9600 | if (mips_opts.micromips) |
9601 | micromips_label_expr (&label_expr); | |
9602 | else | |
9603 | label_expr.X_add_number = 8; | |
9604 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9605 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9606 | macro_build (NULL, "break", BRK_FMT, 6); |
9607 | if (mips_opts.micromips) | |
9608 | micromips_add_label (); | |
252b5132 | 9609 | } |
7d10b47d | 9610 | end_noreorder (); |
df58fc94 | 9611 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9612 | break; |
9613 | ||
9614 | case M_DMULOU_I: | |
9615 | dbl = 1; | |
9616 | case M_MULOU_I: | |
9617 | imm = 1; | |
9618 | goto do_mulou; | |
9619 | ||
9620 | case M_DMULOU: | |
9621 | dbl = 1; | |
9622 | case M_MULOU: | |
9623 | do_mulou: | |
7d10b47d | 9624 | start_noreorder (); |
8fc2e39e | 9625 | used_at = 1; |
252b5132 | 9626 | if (imm) |
67c0d1eb RS |
9627 | load_register (AT, &imm_expr, dbl); |
9628 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9629 | sreg, imm ? AT : treg); |
df58fc94 RS |
9630 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9631 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9632 | if (mips_trap) |
df58fc94 | 9633 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9634 | else |
9635 | { | |
df58fc94 RS |
9636 | if (mips_opts.micromips) |
9637 | micromips_label_expr (&label_expr); | |
9638 | else | |
9639 | label_expr.X_add_number = 8; | |
9640 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9641 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9642 | macro_build (NULL, "break", BRK_FMT, 6); |
9643 | if (mips_opts.micromips) | |
9644 | micromips_add_label (); | |
252b5132 | 9645 | } |
7d10b47d | 9646 | end_noreorder (); |
252b5132 RH |
9647 | break; |
9648 | ||
771c7ce4 | 9649 | case M_DROL: |
fef14a42 | 9650 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9651 | { |
9652 | if (dreg == sreg) | |
9653 | { | |
9654 | tempreg = AT; | |
9655 | used_at = 1; | |
9656 | } | |
9657 | else | |
9658 | { | |
9659 | tempreg = dreg; | |
82dd0097 | 9660 | } |
67c0d1eb RS |
9661 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9662 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9663 | break; |
82dd0097 | 9664 | } |
8fc2e39e | 9665 | used_at = 1; |
c80c840e | 9666 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9667 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9668 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9669 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9670 | break; |
9671 | ||
252b5132 | 9672 | case M_ROL: |
fef14a42 | 9673 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9674 | { |
9675 | if (dreg == sreg) | |
9676 | { | |
9677 | tempreg = AT; | |
9678 | used_at = 1; | |
9679 | } | |
9680 | else | |
9681 | { | |
9682 | tempreg = dreg; | |
82dd0097 | 9683 | } |
67c0d1eb RS |
9684 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9685 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9686 | break; |
82dd0097 | 9687 | } |
8fc2e39e | 9688 | used_at = 1; |
c80c840e | 9689 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9690 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9691 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9692 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9693 | break; |
9694 | ||
771c7ce4 TS |
9695 | case M_DROL_I: |
9696 | { | |
9697 | unsigned int rot; | |
91d6fa6a NC |
9698 | char *l; |
9699 | char *rr; | |
771c7ce4 TS |
9700 | |
9701 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9702 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9703 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9704 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9705 | { |
9706 | rot = (64 - rot) & 0x3f; | |
9707 | if (rot >= 32) | |
df58fc94 | 9708 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9709 | else |
df58fc94 | 9710 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9711 | break; |
60b63b72 | 9712 | } |
483fc7cd | 9713 | if (rot == 0) |
483fc7cd | 9714 | { |
df58fc94 | 9715 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9716 | break; |
483fc7cd | 9717 | } |
82dd0097 | 9718 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9719 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9720 | rot &= 0x1f; |
8fc2e39e | 9721 | used_at = 1; |
df58fc94 RS |
9722 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9723 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9724 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9725 | } |
9726 | break; | |
9727 | ||
252b5132 | 9728 | case M_ROL_I: |
771c7ce4 TS |
9729 | { |
9730 | unsigned int rot; | |
9731 | ||
9732 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9733 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9734 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9735 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9736 | { |
df58fc94 | 9737 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9738 | break; |
60b63b72 | 9739 | } |
483fc7cd | 9740 | if (rot == 0) |
483fc7cd | 9741 | { |
df58fc94 | 9742 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9743 | break; |
483fc7cd | 9744 | } |
8fc2e39e | 9745 | used_at = 1; |
df58fc94 RS |
9746 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9747 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9748 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9749 | } |
9750 | break; | |
9751 | ||
9752 | case M_DROR: | |
fef14a42 | 9753 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9754 | { |
67c0d1eb | 9755 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9756 | break; |
82dd0097 | 9757 | } |
8fc2e39e | 9758 | used_at = 1; |
c80c840e | 9759 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9760 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9761 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9762 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9763 | break; |
9764 | ||
9765 | case M_ROR: | |
fef14a42 | 9766 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9767 | { |
67c0d1eb | 9768 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9769 | break; |
82dd0097 | 9770 | } |
8fc2e39e | 9771 | used_at = 1; |
c80c840e | 9772 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9773 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9774 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9775 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9776 | break; |
9777 | ||
771c7ce4 TS |
9778 | case M_DROR_I: |
9779 | { | |
9780 | unsigned int rot; | |
91d6fa6a NC |
9781 | char *l; |
9782 | char *rr; | |
771c7ce4 TS |
9783 | |
9784 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9785 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9786 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9787 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9788 | { |
9789 | if (rot >= 32) | |
df58fc94 | 9790 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9791 | else |
df58fc94 | 9792 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9793 | break; |
82dd0097 | 9794 | } |
483fc7cd | 9795 | if (rot == 0) |
483fc7cd | 9796 | { |
df58fc94 | 9797 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9798 | break; |
483fc7cd | 9799 | } |
91d6fa6a | 9800 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9801 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9802 | rot &= 0x1f; | |
8fc2e39e | 9803 | used_at = 1; |
df58fc94 RS |
9804 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9805 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9806 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9807 | } |
9808 | break; | |
9809 | ||
252b5132 | 9810 | case M_ROR_I: |
771c7ce4 TS |
9811 | { |
9812 | unsigned int rot; | |
9813 | ||
9814 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9815 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9816 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9817 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9818 | { |
df58fc94 | 9819 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9820 | break; |
82dd0097 | 9821 | } |
483fc7cd | 9822 | if (rot == 0) |
483fc7cd | 9823 | { |
df58fc94 | 9824 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9825 | break; |
483fc7cd | 9826 | } |
8fc2e39e | 9827 | used_at = 1; |
df58fc94 RS |
9828 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9829 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9830 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9831 | } |
252b5132 RH |
9832 | break; |
9833 | ||
252b5132 RH |
9834 | case M_SEQ: |
9835 | if (sreg == 0) | |
67c0d1eb | 9836 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9837 | else if (treg == 0) |
67c0d1eb | 9838 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9839 | else |
9840 | { | |
67c0d1eb RS |
9841 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9842 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9843 | } |
8fc2e39e | 9844 | break; |
252b5132 RH |
9845 | |
9846 | case M_SEQ_I: | |
9847 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9848 | { | |
67c0d1eb | 9849 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9850 | break; |
252b5132 RH |
9851 | } |
9852 | if (sreg == 0) | |
9853 | { | |
9854 | as_warn (_("Instruction %s: result is always false"), | |
9855 | ip->insn_mo->name); | |
67c0d1eb | 9856 | move_register (dreg, 0); |
8fc2e39e | 9857 | break; |
252b5132 | 9858 | } |
dd3cbb7e NC |
9859 | if (CPU_HAS_SEQ (mips_opts.arch) |
9860 | && -512 <= imm_expr.X_add_number | |
9861 | && imm_expr.X_add_number < 512) | |
9862 | { | |
9863 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9864 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9865 | break; |
9866 | } | |
252b5132 RH |
9867 | if (imm_expr.X_op == O_constant |
9868 | && imm_expr.X_add_number >= 0 | |
9869 | && imm_expr.X_add_number < 0x10000) | |
9870 | { | |
67c0d1eb | 9871 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9872 | } |
9873 | else if (imm_expr.X_op == O_constant | |
9874 | && imm_expr.X_add_number > -0x8000 | |
9875 | && imm_expr.X_add_number < 0) | |
9876 | { | |
9877 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9878 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9879 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9880 | } |
dd3cbb7e NC |
9881 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9882 | { | |
9883 | used_at = 1; | |
9884 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9885 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9886 | break; | |
9887 | } | |
252b5132 RH |
9888 | else |
9889 | { | |
67c0d1eb RS |
9890 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9891 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9892 | used_at = 1; |
9893 | } | |
67c0d1eb | 9894 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9895 | break; |
252b5132 RH |
9896 | |
9897 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9898 | s = "slt"; | |
9899 | goto sge; | |
9900 | case M_SGEU: | |
9901 | s = "sltu"; | |
9902 | sge: | |
67c0d1eb RS |
9903 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9904 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9905 | break; |
252b5132 RH |
9906 | |
9907 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9908 | case M_SGEU_I: | |
9909 | if (imm_expr.X_op == O_constant | |
9910 | && imm_expr.X_add_number >= -0x8000 | |
9911 | && imm_expr.X_add_number < 0x8000) | |
9912 | { | |
67c0d1eb RS |
9913 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9914 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9915 | } |
9916 | else | |
9917 | { | |
67c0d1eb RS |
9918 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9919 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9920 | dreg, sreg, AT); | |
252b5132 RH |
9921 | used_at = 1; |
9922 | } | |
67c0d1eb | 9923 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9924 | break; |
252b5132 RH |
9925 | |
9926 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9927 | s = "slt"; | |
9928 | goto sgt; | |
9929 | case M_SGTU: | |
9930 | s = "sltu"; | |
9931 | sgt: | |
67c0d1eb | 9932 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9933 | break; |
252b5132 RH |
9934 | |
9935 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9936 | s = "slt"; | |
9937 | goto sgti; | |
9938 | case M_SGTU_I: | |
9939 | s = "sltu"; | |
9940 | sgti: | |
8fc2e39e | 9941 | used_at = 1; |
67c0d1eb RS |
9942 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9943 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9944 | break; |
9945 | ||
2396cfb9 | 9946 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9947 | s = "slt"; |
9948 | goto sle; | |
9949 | case M_SLEU: | |
9950 | s = "sltu"; | |
9951 | sle: | |
67c0d1eb RS |
9952 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9953 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9954 | break; |
252b5132 | 9955 | |
2396cfb9 | 9956 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9957 | s = "slt"; |
9958 | goto slei; | |
9959 | case M_SLEU_I: | |
9960 | s = "sltu"; | |
9961 | slei: | |
8fc2e39e | 9962 | used_at = 1; |
67c0d1eb RS |
9963 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9964 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9965 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9966 | break; |
9967 | ||
9968 | case M_SLT_I: | |
9969 | if (imm_expr.X_op == O_constant | |
9970 | && imm_expr.X_add_number >= -0x8000 | |
9971 | && imm_expr.X_add_number < 0x8000) | |
9972 | { | |
67c0d1eb | 9973 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9974 | break; |
252b5132 | 9975 | } |
8fc2e39e | 9976 | used_at = 1; |
67c0d1eb RS |
9977 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9978 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9979 | break; |
9980 | ||
9981 | case M_SLTU_I: | |
9982 | if (imm_expr.X_op == O_constant | |
9983 | && imm_expr.X_add_number >= -0x8000 | |
9984 | && imm_expr.X_add_number < 0x8000) | |
9985 | { | |
67c0d1eb | 9986 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9987 | BFD_RELOC_LO16); |
8fc2e39e | 9988 | break; |
252b5132 | 9989 | } |
8fc2e39e | 9990 | used_at = 1; |
67c0d1eb RS |
9991 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9992 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9993 | break; |
9994 | ||
9995 | case M_SNE: | |
9996 | if (sreg == 0) | |
67c0d1eb | 9997 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9998 | else if (treg == 0) |
67c0d1eb | 9999 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10000 | else |
10001 | { | |
67c0d1eb RS |
10002 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10003 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10004 | } |
8fc2e39e | 10005 | break; |
252b5132 RH |
10006 | |
10007 | case M_SNE_I: | |
10008 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10009 | { | |
67c0d1eb | 10010 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10011 | break; |
252b5132 RH |
10012 | } |
10013 | if (sreg == 0) | |
10014 | { | |
10015 | as_warn (_("Instruction %s: result is always true"), | |
10016 | ip->insn_mo->name); | |
67c0d1eb RS |
10017 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10018 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10019 | break; |
252b5132 | 10020 | } |
dd3cbb7e NC |
10021 | if (CPU_HAS_SEQ (mips_opts.arch) |
10022 | && -512 <= imm_expr.X_add_number | |
10023 | && imm_expr.X_add_number < 512) | |
10024 | { | |
10025 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10026 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10027 | break; |
10028 | } | |
252b5132 RH |
10029 | if (imm_expr.X_op == O_constant |
10030 | && imm_expr.X_add_number >= 0 | |
10031 | && imm_expr.X_add_number < 0x10000) | |
10032 | { | |
67c0d1eb | 10033 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10034 | } |
10035 | else if (imm_expr.X_op == O_constant | |
10036 | && imm_expr.X_add_number > -0x8000 | |
10037 | && imm_expr.X_add_number < 0) | |
10038 | { | |
10039 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10040 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10041 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10042 | } |
dd3cbb7e NC |
10043 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10044 | { | |
10045 | used_at = 1; | |
10046 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10047 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10048 | break; | |
10049 | } | |
252b5132 RH |
10050 | else |
10051 | { | |
67c0d1eb RS |
10052 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10053 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10054 | used_at = 1; |
10055 | } | |
67c0d1eb | 10056 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10057 | break; |
252b5132 | 10058 | |
df58fc94 RS |
10059 | case M_SUB_I: |
10060 | s = "addi"; | |
10061 | s2 = "sub"; | |
10062 | goto do_subi; | |
10063 | case M_SUBU_I: | |
10064 | s = "addiu"; | |
10065 | s2 = "subu"; | |
10066 | goto do_subi; | |
252b5132 RH |
10067 | case M_DSUB_I: |
10068 | dbl = 1; | |
df58fc94 RS |
10069 | s = "daddi"; |
10070 | s2 = "dsub"; | |
10071 | if (!mips_opts.micromips) | |
10072 | goto do_subi; | |
252b5132 | 10073 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10074 | && imm_expr.X_add_number > -0x200 |
10075 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10076 | { |
df58fc94 | 10077 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10078 | break; |
252b5132 | 10079 | } |
df58fc94 | 10080 | goto do_subi_i; |
252b5132 RH |
10081 | case M_DSUBU_I: |
10082 | dbl = 1; | |
df58fc94 RS |
10083 | s = "daddiu"; |
10084 | s2 = "dsubu"; | |
10085 | do_subi: | |
252b5132 RH |
10086 | if (imm_expr.X_op == O_constant |
10087 | && imm_expr.X_add_number > -0x8000 | |
10088 | && imm_expr.X_add_number <= 0x8000) | |
10089 | { | |
10090 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10091 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10092 | break; |
252b5132 | 10093 | } |
df58fc94 | 10094 | do_subi_i: |
8fc2e39e | 10095 | used_at = 1; |
67c0d1eb | 10096 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10097 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10098 | break; |
10099 | ||
10100 | case M_TEQ_I: | |
10101 | s = "teq"; | |
10102 | goto trap; | |
10103 | case M_TGE_I: | |
10104 | s = "tge"; | |
10105 | goto trap; | |
10106 | case M_TGEU_I: | |
10107 | s = "tgeu"; | |
10108 | goto trap; | |
10109 | case M_TLT_I: | |
10110 | s = "tlt"; | |
10111 | goto trap; | |
10112 | case M_TLTU_I: | |
10113 | s = "tltu"; | |
10114 | goto trap; | |
10115 | case M_TNE_I: | |
10116 | s = "tne"; | |
10117 | trap: | |
8fc2e39e | 10118 | used_at = 1; |
67c0d1eb RS |
10119 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10120 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10121 | break; |
10122 | ||
252b5132 | 10123 | case M_TRUNCWS: |
43841e91 | 10124 | case M_TRUNCWD: |
df58fc94 | 10125 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10126 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10127 | used_at = 1; |
252b5132 RH |
10128 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10129 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10130 | ||
10131 | /* | |
10132 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10133 | * or is there a reason for it? | |
10134 | */ | |
7d10b47d | 10135 | start_noreorder (); |
67c0d1eb RS |
10136 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10137 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10138 | macro_build (NULL, "nop", ""); | |
252b5132 | 10139 | expr1.X_add_number = 3; |
67c0d1eb | 10140 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10141 | expr1.X_add_number = 2; |
67c0d1eb RS |
10142 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10143 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10144 | macro_build (NULL, "nop", ""); | |
10145 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10146 | dreg, sreg); | |
10147 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10148 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10149 | end_noreorder (); |
252b5132 RH |
10150 | break; |
10151 | ||
df58fc94 RS |
10152 | case M_ULH_A: |
10153 | ab = 1; | |
252b5132 RH |
10154 | case M_ULH: |
10155 | s = "lb"; | |
df58fc94 RS |
10156 | s2 = "lbu"; |
10157 | off = 1; | |
10158 | goto uld_st; | |
10159 | case M_ULHU_A: | |
10160 | ab = 1; | |
252b5132 RH |
10161 | case M_ULHU: |
10162 | s = "lbu"; | |
df58fc94 RS |
10163 | s2 = "lbu"; |
10164 | off = 1; | |
10165 | goto uld_st; | |
10166 | case M_ULW_A: | |
10167 | ab = 1; | |
10168 | case M_ULW: | |
10169 | s = "lwl"; | |
10170 | s2 = "lwr"; | |
7f3c4072 | 10171 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10172 | off = 3; |
10173 | goto uld_st; | |
10174 | case M_ULD_A: | |
10175 | ab = 1; | |
252b5132 RH |
10176 | case M_ULD: |
10177 | s = "ldl"; | |
10178 | s2 = "ldr"; | |
7f3c4072 | 10179 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10180 | off = 7; |
df58fc94 RS |
10181 | goto uld_st; |
10182 | case M_USH_A: | |
10183 | ab = 1; | |
10184 | case M_USH: | |
10185 | s = "sb"; | |
10186 | s2 = "sb"; | |
10187 | off = 1; | |
10188 | ust = 1; | |
10189 | goto uld_st; | |
10190 | case M_USW_A: | |
10191 | ab = 1; | |
10192 | case M_USW: | |
10193 | s = "swl"; | |
10194 | s2 = "swr"; | |
7f3c4072 | 10195 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10196 | off = 3; |
df58fc94 RS |
10197 | ust = 1; |
10198 | goto uld_st; | |
10199 | case M_USD_A: | |
10200 | ab = 1; | |
10201 | case M_USD: | |
10202 | s = "sdl"; | |
10203 | s2 = "sdr"; | |
7f3c4072 | 10204 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10205 | off = 7; |
10206 | ust = 1; | |
10207 | ||
10208 | uld_st: | |
10209 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10210 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10211 | |
10212 | ep = &offset_expr; | |
10213 | expr1.X_add_number = 0; | |
10214 | if (ab) | |
10215 | { | |
10216 | used_at = 1; | |
10217 | tempreg = AT; | |
10218 | load_address (tempreg, ep, &used_at); | |
10219 | if (breg != 0) | |
10220 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10221 | tempreg, tempreg, breg); | |
10222 | breg = tempreg; | |
10223 | tempreg = treg; | |
10224 | ep = &expr1; | |
10225 | } | |
7f3c4072 | 10226 | else if (offbits == 12 |
df58fc94 RS |
10227 | && (offset_expr.X_op != O_constant |
10228 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10229 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10230 | { | |
10231 | used_at = 1; | |
10232 | tempreg = AT; | |
10233 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10234 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10235 | breg = tempreg; | |
10236 | tempreg = treg; | |
10237 | ep = &expr1; | |
10238 | } | |
10239 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10240 | { |
10241 | used_at = 1; | |
10242 | tempreg = AT; | |
10243 | } | |
252b5132 | 10244 | else |
df58fc94 | 10245 | tempreg = treg; |
af22f5b2 | 10246 | |
df58fc94 RS |
10247 | if (off == 1) |
10248 | goto ulh_sh; | |
252b5132 | 10249 | |
90ecf173 | 10250 | if (!target_big_endian) |
df58fc94 | 10251 | ep->X_add_number += off; |
7f3c4072 | 10252 | if (offbits != 12) |
df58fc94 | 10253 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 | 10254 | else |
df58fc94 RS |
10255 | macro_build (NULL, s, "t,~(b)", |
10256 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10257 | ||
90ecf173 | 10258 | if (!target_big_endian) |
df58fc94 | 10259 | ep->X_add_number -= off; |
252b5132 | 10260 | else |
df58fc94 | 10261 | ep->X_add_number += off; |
7f3c4072 | 10262 | if (offbits != 12) |
df58fc94 RS |
10263 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
10264 | else | |
10265 | macro_build (NULL, s2, "t,~(b)", | |
10266 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10267 | |
df58fc94 RS |
10268 | /* If necessary, move the result in tempreg to the final destination. */ |
10269 | if (!ust && treg != tempreg) | |
10270 | { | |
10271 | /* Protect second load's delay slot. */ | |
10272 | load_delay_nop (); | |
10273 | move_register (treg, tempreg); | |
10274 | } | |
8fc2e39e | 10275 | break; |
252b5132 | 10276 | |
df58fc94 | 10277 | ulh_sh: |
d6bc6245 | 10278 | used_at = 1; |
df58fc94 RS |
10279 | if (target_big_endian == ust) |
10280 | ep->X_add_number += off; | |
10281 | tempreg = ust || ab ? treg : AT; | |
10282 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10283 | ||
10284 | /* For halfword transfers we need a temporary register to shuffle | |
10285 | bytes. Unfortunately for M_USH_A we have none available before | |
10286 | the next store as AT holds the base address. We deal with this | |
10287 | case by clobbering TREG and then restoring it as with ULH. */ | |
10288 | tempreg = ust == ab ? treg : AT; | |
10289 | if (ust) | |
10290 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10291 | ||
10292 | if (target_big_endian == ust) | |
10293 | ep->X_add_number -= off; | |
252b5132 | 10294 | else |
df58fc94 RS |
10295 | ep->X_add_number += off; |
10296 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10297 | |
df58fc94 RS |
10298 | /* For M_USH_A re-retrieve the LSB. */ |
10299 | if (ust && ab) | |
10300 | { | |
10301 | if (target_big_endian) | |
10302 | ep->X_add_number += off; | |
10303 | else | |
10304 | ep->X_add_number -= off; | |
10305 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10306 | } | |
10307 | /* For ULH and M_USH_A OR the LSB in. */ | |
10308 | if (!ust || ab) | |
10309 | { | |
10310 | tempreg = !ab ? AT : treg; | |
10311 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10312 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10313 | } | |
252b5132 RH |
10314 | break; |
10315 | ||
10316 | default: | |
10317 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10318 | are added dynamically. */ |
252b5132 RH |
10319 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10320 | break; | |
10321 | } | |
741fe287 | 10322 | if (!mips_opts.at && used_at) |
8fc2e39e | 10323 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10324 | } |
10325 | ||
10326 | /* Implement macros in mips16 mode. */ | |
10327 | ||
10328 | static void | |
17a2f251 | 10329 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10330 | { |
10331 | int mask; | |
10332 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10333 | expressionS expr1; |
10334 | int dbl; | |
10335 | const char *s, *s2, *s3; | |
10336 | ||
10337 | mask = ip->insn_mo->mask; | |
10338 | ||
bf12938e RS |
10339 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10340 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10341 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10342 | |
252b5132 RH |
10343 | expr1.X_op = O_constant; |
10344 | expr1.X_op_symbol = NULL; | |
10345 | expr1.X_add_symbol = NULL; | |
10346 | expr1.X_add_number = 1; | |
10347 | ||
10348 | dbl = 0; | |
10349 | ||
10350 | switch (mask) | |
10351 | { | |
10352 | default: | |
b37df7c4 | 10353 | abort (); |
252b5132 RH |
10354 | |
10355 | case M_DDIV_3: | |
10356 | dbl = 1; | |
10357 | case M_DIV_3: | |
10358 | s = "mflo"; | |
10359 | goto do_div3; | |
10360 | case M_DREM_3: | |
10361 | dbl = 1; | |
10362 | case M_REM_3: | |
10363 | s = "mfhi"; | |
10364 | do_div3: | |
7d10b47d | 10365 | start_noreorder (); |
67c0d1eb | 10366 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10367 | expr1.X_add_number = 2; |
67c0d1eb RS |
10368 | macro_build (&expr1, "bnez", "x,p", yreg); |
10369 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10370 | |
252b5132 RH |
10371 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10372 | since that causes an overflow. We should do that as well, | |
10373 | but I don't see how to do the comparisons without a temporary | |
10374 | register. */ | |
7d10b47d | 10375 | end_noreorder (); |
67c0d1eb | 10376 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10377 | break; |
10378 | ||
10379 | case M_DIVU_3: | |
10380 | s = "divu"; | |
10381 | s2 = "mflo"; | |
10382 | goto do_divu3; | |
10383 | case M_REMU_3: | |
10384 | s = "divu"; | |
10385 | s2 = "mfhi"; | |
10386 | goto do_divu3; | |
10387 | case M_DDIVU_3: | |
10388 | s = "ddivu"; | |
10389 | s2 = "mflo"; | |
10390 | goto do_divu3; | |
10391 | case M_DREMU_3: | |
10392 | s = "ddivu"; | |
10393 | s2 = "mfhi"; | |
10394 | do_divu3: | |
7d10b47d | 10395 | start_noreorder (); |
67c0d1eb | 10396 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10397 | expr1.X_add_number = 2; |
67c0d1eb RS |
10398 | macro_build (&expr1, "bnez", "x,p", yreg); |
10399 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10400 | end_noreorder (); |
67c0d1eb | 10401 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10402 | break; |
10403 | ||
10404 | case M_DMUL: | |
10405 | dbl = 1; | |
10406 | case M_MUL: | |
67c0d1eb RS |
10407 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10408 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10409 | break; |
252b5132 RH |
10410 | |
10411 | case M_DSUBU_I: | |
10412 | dbl = 1; | |
10413 | goto do_subu; | |
10414 | case M_SUBU_I: | |
10415 | do_subu: | |
10416 | if (imm_expr.X_op != O_constant) | |
10417 | as_bad (_("Unsupported large constant")); | |
10418 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10419 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10420 | break; |
10421 | ||
10422 | case M_SUBU_I_2: | |
10423 | if (imm_expr.X_op != O_constant) | |
10424 | as_bad (_("Unsupported large constant")); | |
10425 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10426 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10427 | break; |
10428 | ||
10429 | case M_DSUBU_I_2: | |
10430 | if (imm_expr.X_op != O_constant) | |
10431 | as_bad (_("Unsupported large constant")); | |
10432 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10433 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10434 | break; |
10435 | ||
10436 | case M_BEQ: | |
10437 | s = "cmp"; | |
10438 | s2 = "bteqz"; | |
10439 | goto do_branch; | |
10440 | case M_BNE: | |
10441 | s = "cmp"; | |
10442 | s2 = "btnez"; | |
10443 | goto do_branch; | |
10444 | case M_BLT: | |
10445 | s = "slt"; | |
10446 | s2 = "btnez"; | |
10447 | goto do_branch; | |
10448 | case M_BLTU: | |
10449 | s = "sltu"; | |
10450 | s2 = "btnez"; | |
10451 | goto do_branch; | |
10452 | case M_BLE: | |
10453 | s = "slt"; | |
10454 | s2 = "bteqz"; | |
10455 | goto do_reverse_branch; | |
10456 | case M_BLEU: | |
10457 | s = "sltu"; | |
10458 | s2 = "bteqz"; | |
10459 | goto do_reverse_branch; | |
10460 | case M_BGE: | |
10461 | s = "slt"; | |
10462 | s2 = "bteqz"; | |
10463 | goto do_branch; | |
10464 | case M_BGEU: | |
10465 | s = "sltu"; | |
10466 | s2 = "bteqz"; | |
10467 | goto do_branch; | |
10468 | case M_BGT: | |
10469 | s = "slt"; | |
10470 | s2 = "btnez"; | |
10471 | goto do_reverse_branch; | |
10472 | case M_BGTU: | |
10473 | s = "sltu"; | |
10474 | s2 = "btnez"; | |
10475 | ||
10476 | do_reverse_branch: | |
10477 | tmp = xreg; | |
10478 | xreg = yreg; | |
10479 | yreg = tmp; | |
10480 | ||
10481 | do_branch: | |
67c0d1eb RS |
10482 | macro_build (NULL, s, "x,y", xreg, yreg); |
10483 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10484 | break; |
10485 | ||
10486 | case M_BEQ_I: | |
10487 | s = "cmpi"; | |
10488 | s2 = "bteqz"; | |
10489 | s3 = "x,U"; | |
10490 | goto do_branch_i; | |
10491 | case M_BNE_I: | |
10492 | s = "cmpi"; | |
10493 | s2 = "btnez"; | |
10494 | s3 = "x,U"; | |
10495 | goto do_branch_i; | |
10496 | case M_BLT_I: | |
10497 | s = "slti"; | |
10498 | s2 = "btnez"; | |
10499 | s3 = "x,8"; | |
10500 | goto do_branch_i; | |
10501 | case M_BLTU_I: | |
10502 | s = "sltiu"; | |
10503 | s2 = "btnez"; | |
10504 | s3 = "x,8"; | |
10505 | goto do_branch_i; | |
10506 | case M_BLE_I: | |
10507 | s = "slti"; | |
10508 | s2 = "btnez"; | |
10509 | s3 = "x,8"; | |
10510 | goto do_addone_branch_i; | |
10511 | case M_BLEU_I: | |
10512 | s = "sltiu"; | |
10513 | s2 = "btnez"; | |
10514 | s3 = "x,8"; | |
10515 | goto do_addone_branch_i; | |
10516 | case M_BGE_I: | |
10517 | s = "slti"; | |
10518 | s2 = "bteqz"; | |
10519 | s3 = "x,8"; | |
10520 | goto do_branch_i; | |
10521 | case M_BGEU_I: | |
10522 | s = "sltiu"; | |
10523 | s2 = "bteqz"; | |
10524 | s3 = "x,8"; | |
10525 | goto do_branch_i; | |
10526 | case M_BGT_I: | |
10527 | s = "slti"; | |
10528 | s2 = "bteqz"; | |
10529 | s3 = "x,8"; | |
10530 | goto do_addone_branch_i; | |
10531 | case M_BGTU_I: | |
10532 | s = "sltiu"; | |
10533 | s2 = "bteqz"; | |
10534 | s3 = "x,8"; | |
10535 | ||
10536 | do_addone_branch_i: | |
10537 | if (imm_expr.X_op != O_constant) | |
10538 | as_bad (_("Unsupported large constant")); | |
10539 | ++imm_expr.X_add_number; | |
10540 | ||
10541 | do_branch_i: | |
67c0d1eb RS |
10542 | macro_build (&imm_expr, s, s3, xreg); |
10543 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10544 | break; |
10545 | ||
10546 | case M_ABS: | |
10547 | expr1.X_add_number = 0; | |
67c0d1eb | 10548 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10549 | if (xreg != yreg) |
67c0d1eb | 10550 | move_register (xreg, yreg); |
252b5132 | 10551 | expr1.X_add_number = 2; |
67c0d1eb RS |
10552 | macro_build (&expr1, "bteqz", "p"); |
10553 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10554 | } |
10555 | } | |
10556 | ||
10557 | /* For consistency checking, verify that all bits are specified either | |
10558 | by the match/mask part of the instruction definition, or by the | |
10559 | operand list. */ | |
10560 | static int | |
17a2f251 | 10561 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10562 | { |
10563 | const char *p = opc->args; | |
10564 | char c; | |
10565 | unsigned long used_bits = opc->mask; | |
10566 | ||
10567 | if ((used_bits & opc->match) != opc->match) | |
10568 | { | |
10569 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10570 | opc->name, opc->args); | |
10571 | return 0; | |
10572 | } | |
10573 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10574 | while (*p) | |
10575 | switch (c = *p++) | |
10576 | { | |
10577 | case ',': break; | |
10578 | case '(': break; | |
10579 | case ')': break; | |
af7ee8bf CD |
10580 | case '+': |
10581 | switch (c = *p++) | |
10582 | { | |
9bcd4f99 TS |
10583 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10584 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10585 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10586 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10587 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10588 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10589 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10590 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10591 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10592 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10593 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10594 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10595 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10596 | case 'I': break; | |
b015e599 | 10597 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10598 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10599 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10600 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10601 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10602 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10603 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10604 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10605 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10606 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10607 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10608 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10609 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10610 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10611 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10612 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
7f3c4072 | 10613 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10614 | |
af7ee8bf CD |
10615 | default: |
10616 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10617 | c, opc->name, opc->args); | |
10618 | return 0; | |
10619 | } | |
10620 | break; | |
252b5132 RH |
10621 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10622 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10623 | case 'A': break; | |
4372b673 | 10624 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10625 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10626 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10627 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10628 | case 'F': break; | |
10629 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10630 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10631 | case 'I': break; |
e972090a | 10632 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10633 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10634 | case 'L': break; |
10635 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10636 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10637 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10638 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10639 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10640 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10641 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10642 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10643 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10644 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10645 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10646 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10647 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10648 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10649 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10650 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10651 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10652 | case 'f': break; | |
10653 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10654 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10655 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10656 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10657 | case 'l': break; | |
10658 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10659 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10660 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10661 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10662 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10663 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10664 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10665 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10666 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10667 | case 'x': break; | |
10668 | case 'z': break; | |
10669 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10670 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10671 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10672 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10673 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10674 | case '[': break; | |
10675 | case ']': break; | |
620edafd | 10676 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10677 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10678 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10679 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10680 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10681 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10682 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10683 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10684 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10685 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10686 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10687 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10688 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10689 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10690 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10691 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10692 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10693 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10694 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10695 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10696 | default: |
10697 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10698 | c, opc->name, opc->args); | |
10699 | return 0; | |
10700 | } | |
10701 | #undef USE_BITS | |
10702 | if (used_bits != 0xffffffff) | |
10703 | { | |
10704 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10705 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10706 | return 0; | |
10707 | } | |
10708 | return 1; | |
10709 | } | |
10710 | ||
df58fc94 RS |
10711 | /* For consistency checking, verify that the length implied matches the |
10712 | major opcode and that all bits are specified either by the match/mask | |
10713 | part of the instruction definition, or by the operand list. */ | |
10714 | ||
10715 | static int | |
10716 | validate_micromips_insn (const struct mips_opcode *opc) | |
10717 | { | |
10718 | unsigned long match = opc->match; | |
10719 | unsigned long mask = opc->mask; | |
10720 | const char *p = opc->args; | |
10721 | unsigned long insn_bits; | |
10722 | unsigned long used_bits; | |
10723 | unsigned long major; | |
10724 | unsigned int length; | |
10725 | char e; | |
10726 | char c; | |
10727 | ||
10728 | if ((mask & match) != match) | |
10729 | { | |
10730 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10731 | opc->name, opc->args); | |
10732 | return 0; | |
10733 | } | |
10734 | length = micromips_insn_length (opc); | |
10735 | if (length != 2 && length != 4) | |
10736 | { | |
10737 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10738 | "%s %s"), length, opc->name, opc->args); | |
10739 | return 0; | |
10740 | } | |
10741 | major = match >> (10 + 8 * (length - 2)); | |
10742 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10743 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10744 | { | |
10745 | as_bad (_("Internal error: bad microMIPS opcode " | |
10746 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10747 | return 0; | |
10748 | } | |
10749 | ||
10750 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10751 | insn_bits = 1 << 4 * length; | |
10752 | insn_bits <<= 4 * length; | |
10753 | insn_bits -= 1; | |
10754 | used_bits = mask; | |
10755 | #define USE_BITS(field) \ | |
10756 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10757 | while (*p) | |
10758 | switch (c = *p++) | |
10759 | { | |
10760 | case ',': break; | |
10761 | case '(': break; | |
10762 | case ')': break; | |
10763 | case '+': | |
10764 | e = c; | |
10765 | switch (c = *p++) | |
10766 | { | |
10767 | case 'A': USE_BITS (EXTLSB); break; | |
10768 | case 'B': USE_BITS (INSMSB); break; | |
10769 | case 'C': USE_BITS (EXTMSBD); break; | |
10770 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10771 | case 'E': USE_BITS (EXTLSB); break; | |
10772 | case 'F': USE_BITS (INSMSB); break; | |
10773 | case 'G': USE_BITS (EXTMSBD); break; | |
10774 | case 'H': USE_BITS (EXTMSBD); break; | |
7f3c4072 | 10775 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
10776 | default: |
10777 | as_bad (_("Internal error: bad mips opcode " | |
10778 | "(unknown extension operand type `%c%c'): %s %s"), | |
10779 | e, c, opc->name, opc->args); | |
10780 | return 0; | |
10781 | } | |
10782 | break; | |
10783 | case 'm': | |
10784 | e = c; | |
10785 | switch (c = *p++) | |
10786 | { | |
10787 | case 'A': USE_BITS (IMMA); break; | |
10788 | case 'B': USE_BITS (IMMB); break; | |
10789 | case 'C': USE_BITS (IMMC); break; | |
10790 | case 'D': USE_BITS (IMMD); break; | |
10791 | case 'E': USE_BITS (IMME); break; | |
10792 | case 'F': USE_BITS (IMMF); break; | |
10793 | case 'G': USE_BITS (IMMG); break; | |
10794 | case 'H': USE_BITS (IMMH); break; | |
10795 | case 'I': USE_BITS (IMMI); break; | |
10796 | case 'J': USE_BITS (IMMJ); break; | |
10797 | case 'L': USE_BITS (IMML); break; | |
10798 | case 'M': USE_BITS (IMMM); break; | |
10799 | case 'N': USE_BITS (IMMN); break; | |
10800 | case 'O': USE_BITS (IMMO); break; | |
10801 | case 'P': USE_BITS (IMMP); break; | |
10802 | case 'Q': USE_BITS (IMMQ); break; | |
10803 | case 'U': USE_BITS (IMMU); break; | |
10804 | case 'W': USE_BITS (IMMW); break; | |
10805 | case 'X': USE_BITS (IMMX); break; | |
10806 | case 'Y': USE_BITS (IMMY); break; | |
10807 | case 'Z': break; | |
10808 | case 'a': break; | |
10809 | case 'b': USE_BITS (MB); break; | |
10810 | case 'c': USE_BITS (MC); break; | |
10811 | case 'd': USE_BITS (MD); break; | |
10812 | case 'e': USE_BITS (ME); break; | |
10813 | case 'f': USE_BITS (MF); break; | |
10814 | case 'g': USE_BITS (MG); break; | |
10815 | case 'h': USE_BITS (MH); break; | |
10816 | case 'i': USE_BITS (MI); break; | |
10817 | case 'j': USE_BITS (MJ); break; | |
10818 | case 'l': USE_BITS (ML); break; | |
10819 | case 'm': USE_BITS (MM); break; | |
10820 | case 'n': USE_BITS (MN); break; | |
10821 | case 'p': USE_BITS (MP); break; | |
10822 | case 'q': USE_BITS (MQ); break; | |
10823 | case 'r': break; | |
10824 | case 's': break; | |
10825 | case 't': break; | |
10826 | case 'x': break; | |
10827 | case 'y': break; | |
10828 | case 'z': break; | |
10829 | default: | |
10830 | as_bad (_("Internal error: bad mips opcode " | |
10831 | "(unknown extension operand type `%c%c'): %s %s"), | |
10832 | e, c, opc->name, opc->args); | |
10833 | return 0; | |
10834 | } | |
10835 | break; | |
10836 | case '.': USE_BITS (OFFSET10); break; | |
10837 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10838 | case '2': USE_BITS (BP); break; |
10839 | case '3': USE_BITS (SA3); break; | |
10840 | case '4': USE_BITS (SA4); break; | |
10841 | case '5': USE_BITS (IMM8); break; | |
10842 | case '6': USE_BITS (RS); break; | |
10843 | case '7': USE_BITS (DSPACC); break; | |
10844 | case '8': USE_BITS (WRDSP); break; | |
10845 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10846 | case '<': USE_BITS (SHAMT); break; |
10847 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10848 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10849 | case 'B': USE_BITS (CODE10); break; |
10850 | case 'C': USE_BITS (COPZ); break; | |
10851 | case 'D': USE_BITS (FD); break; | |
10852 | case 'E': USE_BITS (RT); break; | |
10853 | case 'G': USE_BITS (RS); break; | |
444d75be | 10854 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10855 | case 'K': USE_BITS (RS); break; |
10856 | case 'M': USE_BITS (CCC); break; | |
10857 | case 'N': USE_BITS (BCC); break; | |
10858 | case 'R': USE_BITS (FR); break; | |
10859 | case 'S': USE_BITS (FS); break; | |
10860 | case 'T': USE_BITS (FT); break; | |
10861 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10862 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10863 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10864 | case 'a': USE_BITS (TARGET); break; |
10865 | case 'b': USE_BITS (RS); break; | |
10866 | case 'c': USE_BITS (CODE); break; | |
10867 | case 'd': USE_BITS (RD); break; | |
10868 | case 'h': USE_BITS (PREFX); break; | |
10869 | case 'i': USE_BITS (IMMEDIATE); break; | |
10870 | case 'j': USE_BITS (DELTA); break; | |
10871 | case 'k': USE_BITS (CACHE); break; | |
10872 | case 'n': USE_BITS (RT); break; | |
10873 | case 'o': USE_BITS (DELTA); break; | |
10874 | case 'p': USE_BITS (DELTA); break; | |
10875 | case 'q': USE_BITS (CODE2); break; | |
10876 | case 'r': USE_BITS (RS); break; | |
10877 | case 's': USE_BITS (RS); break; | |
10878 | case 't': USE_BITS (RT); break; | |
10879 | case 'u': USE_BITS (IMMEDIATE); break; | |
10880 | case 'v': USE_BITS (RS); break; | |
10881 | case 'w': USE_BITS (RT); break; | |
10882 | case 'y': USE_BITS (RS3); break; | |
10883 | case 'z': break; | |
10884 | case '|': USE_BITS (TRAP); break; | |
10885 | case '~': USE_BITS (OFFSET12); break; | |
10886 | default: | |
10887 | as_bad (_("Internal error: bad microMIPS opcode " | |
10888 | "(unknown operand type `%c'): %s %s"), | |
10889 | c, opc->name, opc->args); | |
10890 | return 0; | |
10891 | } | |
10892 | #undef USE_BITS | |
10893 | if (used_bits != insn_bits) | |
10894 | { | |
10895 | if (~used_bits & insn_bits) | |
10896 | as_bad (_("Internal error: bad microMIPS opcode " | |
10897 | "(bits 0x%lx undefined): %s %s"), | |
10898 | ~used_bits & insn_bits, opc->name, opc->args); | |
10899 | if (used_bits & ~insn_bits) | |
10900 | as_bad (_("Internal error: bad microMIPS opcode " | |
10901 | "(bits 0x%lx defined): %s %s"), | |
10902 | used_bits & ~insn_bits, opc->name, opc->args); | |
10903 | return 0; | |
10904 | } | |
10905 | return 1; | |
10906 | } | |
10907 | ||
9bcd4f99 TS |
10908 | /* UDI immediates. */ |
10909 | struct mips_immed { | |
10910 | char type; | |
10911 | unsigned int shift; | |
10912 | unsigned long mask; | |
10913 | const char * desc; | |
10914 | }; | |
10915 | ||
10916 | static const struct mips_immed mips_immed[] = { | |
10917 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10918 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10919 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10920 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10921 | { 0,0,0,0 } | |
10922 | }; | |
10923 | ||
7455baf8 TS |
10924 | /* Check whether an odd floating-point register is allowed. */ |
10925 | static int | |
10926 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10927 | { | |
10928 | const char *s = insn->name; | |
10929 | ||
10930 | if (insn->pinfo == INSN_MACRO) | |
10931 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10932 | return 1; | |
10933 | ||
e407c74b | 10934 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10935 | { |
10936 | /* Allow odd registers for single-precision ops. */ | |
10937 | switch (insn->pinfo & (FP_S | FP_D)) | |
10938 | { | |
10939 | case FP_S: | |
10940 | case 0: | |
10941 | return 1; /* both single precision - ok */ | |
10942 | case FP_D: | |
10943 | return 0; /* both double precision - fail */ | |
10944 | default: | |
10945 | break; | |
10946 | } | |
10947 | ||
10948 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10949 | s = strchr (insn->name, '.'); | |
10950 | if (argnum == 2) | |
10951 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10952 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10953 | } | |
10954 | ||
10955 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10956 | if ((insn->pinfo & FP_S) | |
10957 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10958 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10959 | return 1; | |
10960 | ||
10961 | return 0; | |
10962 | } | |
10963 | ||
df58fc94 RS |
10964 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10965 | taking bits from BIT up. */ | |
10966 | static int | |
10967 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10968 | { | |
10969 | return (ep->X_op == O_constant | |
10970 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10971 | && ep->X_add_number >= min << bit | |
10972 | && ep->X_add_number < max << bit); | |
10973 | } | |
10974 | ||
252b5132 RH |
10975 | /* This routine assembles an instruction into its binary format. As a |
10976 | side effect, it sets one of the global variables imm_reloc or | |
10977 | offset_reloc to the type of relocation to do if one of the operands | |
10978 | is an address expression. */ | |
10979 | ||
10980 | static void | |
17a2f251 | 10981 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10982 | { |
df58fc94 RS |
10983 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10984 | bfd_boolean need_delay_slot_ok = TRUE; | |
10985 | struct mips_opcode *firstinsn = NULL; | |
10986 | const struct mips_opcode *past; | |
10987 | struct hash_control *hash; | |
252b5132 RH |
10988 | char *s; |
10989 | const char *args; | |
43841e91 | 10990 | char c = 0; |
252b5132 RH |
10991 | struct mips_opcode *insn; |
10992 | char *argsStart; | |
10993 | unsigned int regno; | |
34224acf | 10994 | unsigned int lastregno; |
df58fc94 | 10995 | unsigned int destregno = 0; |
af7ee8bf | 10996 | unsigned int lastpos = 0; |
071742cf | 10997 | unsigned int limlo, limhi; |
f02d8318 | 10998 | int sizelo; |
252b5132 | 10999 | char *s_reset; |
74cd071d | 11000 | offsetT min_range, max_range; |
df58fc94 | 11001 | long opend; |
a40bc9dd | 11002 | char *name; |
707bfff6 TS |
11003 | int argnum; |
11004 | unsigned int rtype; | |
df58fc94 | 11005 | char *dot; |
a40bc9dd | 11006 | long end; |
252b5132 RH |
11007 | |
11008 | insn_error = NULL; | |
11009 | ||
df58fc94 RS |
11010 | if (mips_opts.micromips) |
11011 | { | |
11012 | hash = micromips_op_hash; | |
11013 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11014 | } | |
11015 | else | |
11016 | { | |
11017 | hash = op_hash; | |
11018 | past = &mips_opcodes[NUMOPCODES]; | |
11019 | } | |
11020 | forced_insn_length = 0; | |
252b5132 | 11021 | insn = NULL; |
252b5132 | 11022 | |
df58fc94 | 11023 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11024 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11025 | continue; | |
bdaaa2e1 | 11026 | |
a40bc9dd RS |
11027 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11028 | name = alloca (end + 1); | |
11029 | memcpy (name, str, end); | |
11030 | name[end] = '\0'; | |
252b5132 | 11031 | |
df58fc94 RS |
11032 | for (;;) |
11033 | { | |
11034 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11035 | ||
11036 | if (insn != NULL || !mips_opts.micromips) | |
11037 | break; | |
11038 | if (forced_insn_length) | |
11039 | break; | |
11040 | ||
11041 | /* See if there's an instruction size override suffix, | |
11042 | either `16' or `32', at the end of the mnemonic proper, | |
11043 | that defines the operation, i.e. before the first `.' | |
11044 | character if any. Strip it and retry. */ | |
11045 | dot = strchr (name, '.'); | |
11046 | opend = dot != NULL ? dot - name : end; | |
11047 | if (opend < 3) | |
11048 | break; | |
11049 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11050 | forced_insn_length = 2; | |
11051 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11052 | forced_insn_length = 4; | |
11053 | else | |
11054 | break; | |
11055 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11056 | } | |
252b5132 RH |
11057 | if (insn == NULL) |
11058 | { | |
a40bc9dd RS |
11059 | insn_error = _("Unrecognized opcode"); |
11060 | return; | |
252b5132 RH |
11061 | } |
11062 | ||
df58fc94 RS |
11063 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11064 | we make up to two passes over the relevant fragment of the opcode | |
11065 | table. First we try instructions that meet the delay slot's length | |
11066 | requirement. If none matched, then we retry with the remaining ones | |
11067 | and if one matches, then we use it and then issue an appropriate | |
11068 | warning later on. */ | |
a40bc9dd | 11069 | argsStart = s = str + end; |
252b5132 RH |
11070 | for (;;) |
11071 | { | |
df58fc94 RS |
11072 | bfd_boolean delay_slot_ok; |
11073 | bfd_boolean size_ok; | |
b34976b6 | 11074 | bfd_boolean ok; |
252b5132 | 11075 | |
a40bc9dd | 11076 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11077 | |
f79e2745 | 11078 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11079 | size_ok = is_size_valid (insn); |
11080 | delay_slot_ok = is_delay_slot_valid (insn); | |
11081 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11082 | { |
df58fc94 RS |
11083 | firstinsn = insn; |
11084 | wrong_delay_slot_insns = TRUE; | |
11085 | } | |
11086 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11087 | { | |
11088 | static char buf[256]; | |
11089 | ||
11090 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11091 | { |
11092 | ++insn; | |
11093 | continue; | |
11094 | } | |
df58fc94 | 11095 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11096 | { |
df58fc94 RS |
11097 | gas_assert (firstinsn); |
11098 | need_delay_slot_ok = FALSE; | |
11099 | past = insn + 1; | |
11100 | insn = firstinsn; | |
11101 | continue; | |
252b5132 | 11102 | } |
df58fc94 RS |
11103 | |
11104 | if (insn_error) | |
11105 | return; | |
11106 | ||
11107 | if (!ok) | |
7bd942df | 11108 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11109 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11110 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11111 | else | |
11112 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11113 | 8 * forced_insn_length); | |
11114 | insn_error = buf; | |
11115 | ||
11116 | return; | |
252b5132 RH |
11117 | } |
11118 | ||
1e915849 | 11119 | create_insn (ip, insn); |
268f6bed | 11120 | insn_error = NULL; |
707bfff6 | 11121 | argnum = 1; |
24864476 | 11122 | lastregno = 0xffffffff; |
252b5132 RH |
11123 | for (args = insn->args;; ++args) |
11124 | { | |
deec1734 CD |
11125 | int is_mdmx; |
11126 | ||
ad8d3bb3 | 11127 | s += strspn (s, " \t"); |
deec1734 | 11128 | is_mdmx = 0; |
252b5132 RH |
11129 | switch (*args) |
11130 | { | |
11131 | case '\0': /* end of args */ | |
11132 | if (*s == '\0') | |
11133 | return; | |
11134 | break; | |
11135 | ||
03f66e8a MR |
11136 | case '2': |
11137 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11138 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11139 | my_getExpression (&imm_expr, s); |
11140 | check_absolute_expr (ip, &imm_expr); | |
11141 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11142 | && (unsigned long) imm_expr.X_add_number != 3) | |
11143 | { | |
11144 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11145 | (unsigned long) imm_expr.X_add_number); | |
11146 | } | |
03f66e8a MR |
11147 | INSERT_OPERAND (mips_opts.micromips, |
11148 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11149 | imm_expr.X_op = O_absent; |
11150 | s = expr_end; | |
11151 | continue; | |
11152 | ||
03f66e8a MR |
11153 | case '3': |
11154 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11155 | code) or 21 (for microMIPS code). */ | |
11156 | { | |
11157 | unsigned long mask = (mips_opts.micromips | |
11158 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11159 | ||
11160 | my_getExpression (&imm_expr, s); | |
11161 | check_absolute_expr (ip, &imm_expr); | |
11162 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11163 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11164 | mask, (unsigned long) imm_expr.X_add_number); | |
11165 | INSERT_OPERAND (mips_opts.micromips, | |
11166 | SA3, *ip, imm_expr.X_add_number); | |
11167 | imm_expr.X_op = O_absent; | |
11168 | s = expr_end; | |
11169 | } | |
74cd071d CF |
11170 | continue; |
11171 | ||
03f66e8a MR |
11172 | case '4': |
11173 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11174 | code) or 21 (for microMIPS code). */ | |
11175 | { | |
11176 | unsigned long mask = (mips_opts.micromips | |
11177 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11178 | ||
11179 | my_getExpression (&imm_expr, s); | |
11180 | check_absolute_expr (ip, &imm_expr); | |
11181 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11182 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11183 | mask, (unsigned long) imm_expr.X_add_number); | |
11184 | INSERT_OPERAND (mips_opts.micromips, | |
11185 | SA4, *ip, imm_expr.X_add_number); | |
11186 | imm_expr.X_op = O_absent; | |
11187 | s = expr_end; | |
11188 | } | |
74cd071d CF |
11189 | continue; |
11190 | ||
03f66e8a MR |
11191 | case '5': |
11192 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11193 | code) or 16 (for microMIPS code). */ | |
11194 | { | |
11195 | unsigned long mask = (mips_opts.micromips | |
11196 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11197 | ||
11198 | my_getExpression (&imm_expr, s); | |
11199 | check_absolute_expr (ip, &imm_expr); | |
11200 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11201 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11202 | mask, (unsigned long) imm_expr.X_add_number); | |
11203 | INSERT_OPERAND (mips_opts.micromips, | |
11204 | IMM8, *ip, imm_expr.X_add_number); | |
11205 | imm_expr.X_op = O_absent; | |
11206 | s = expr_end; | |
11207 | } | |
74cd071d CF |
11208 | continue; |
11209 | ||
03f66e8a MR |
11210 | case '6': |
11211 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11212 | code) or 21 (for microMIPS code). */ | |
11213 | { | |
11214 | unsigned long mask = (mips_opts.micromips | |
11215 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11216 | ||
11217 | my_getExpression (&imm_expr, s); | |
11218 | check_absolute_expr (ip, &imm_expr); | |
11219 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11220 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11221 | mask, (unsigned long) imm_expr.X_add_number); | |
11222 | INSERT_OPERAND (mips_opts.micromips, | |
11223 | RS, *ip, imm_expr.X_add_number); | |
11224 | imm_expr.X_op = O_absent; | |
11225 | s = expr_end; | |
11226 | } | |
74cd071d CF |
11227 | continue; |
11228 | ||
90ecf173 | 11229 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11230 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11231 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11232 | { |
11233 | regno = s[3] - '0'; | |
11234 | s += 4; | |
03f66e8a | 11235 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11236 | continue; |
11237 | } | |
11238 | else | |
11239 | as_bad (_("Invalid dsp acc register")); | |
11240 | break; | |
11241 | ||
03f66e8a MR |
11242 | case '8': |
11243 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11244 | code) or 14 (for microMIPS code). */ | |
11245 | { | |
11246 | unsigned long mask = (mips_opts.micromips | |
11247 | ? MICROMIPSOP_MASK_WRDSP | |
11248 | : OP_MASK_WRDSP); | |
11249 | ||
11250 | my_getExpression (&imm_expr, s); | |
11251 | check_absolute_expr (ip, &imm_expr); | |
11252 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11253 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11254 | mask, (unsigned long) imm_expr.X_add_number); | |
11255 | INSERT_OPERAND (mips_opts.micromips, | |
11256 | WRDSP, *ip, imm_expr.X_add_number); | |
11257 | imm_expr.X_op = O_absent; | |
11258 | s = expr_end; | |
11259 | } | |
74cd071d CF |
11260 | continue; |
11261 | ||
90ecf173 | 11262 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11263 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11264 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11265 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11266 | { |
11267 | regno = s[3] - '0'; | |
11268 | s += 4; | |
df58fc94 | 11269 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11270 | continue; |
11271 | } | |
11272 | else | |
11273 | as_bad (_("Invalid dsp acc register")); | |
11274 | break; | |
11275 | ||
03f66e8a MR |
11276 | case '0': |
11277 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11278 | code) or 20 (for microMIPS code). */ | |
11279 | { | |
11280 | long mask = (mips_opts.micromips | |
11281 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11282 | ||
11283 | my_getExpression (&imm_expr, s); | |
11284 | check_absolute_expr (ip, &imm_expr); | |
11285 | min_range = -((mask + 1) >> 1); | |
11286 | max_range = ((mask + 1) >> 1) - 1; | |
11287 | if (imm_expr.X_add_number < min_range | |
11288 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11289 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11290 | (long) min_range, (long) max_range, | |
11291 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11292 | INSERT_OPERAND (mips_opts.micromips, |
11293 | DSPSFT, *ip, imm_expr.X_add_number); | |
11294 | imm_expr.X_op = O_absent; | |
11295 | s = expr_end; | |
11296 | } | |
74cd071d CF |
11297 | continue; |
11298 | ||
90ecf173 | 11299 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11300 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11301 | my_getExpression (&imm_expr, s); |
11302 | check_absolute_expr (ip, &imm_expr); | |
11303 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11304 | { | |
a9e24354 TS |
11305 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11306 | OP_MASK_RDDSP, | |
11307 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11308 | } |
df58fc94 | 11309 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11310 | imm_expr.X_op = O_absent; |
11311 | s = expr_end; | |
11312 | continue; | |
11313 | ||
90ecf173 | 11314 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11315 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11316 | my_getExpression (&imm_expr, s); |
11317 | check_absolute_expr (ip, &imm_expr); | |
11318 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11319 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11320 | if (imm_expr.X_add_number < min_range || | |
11321 | imm_expr.X_add_number > max_range) | |
11322 | { | |
a9e24354 TS |
11323 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11324 | (long) min_range, (long) max_range, | |
11325 | (long) imm_expr.X_add_number); | |
74cd071d | 11326 | } |
df58fc94 | 11327 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11328 | imm_expr.X_op = O_absent; |
11329 | s = expr_end; | |
11330 | continue; | |
11331 | ||
90ecf173 | 11332 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11333 | { |
11334 | long mask = (mips_opts.micromips | |
11335 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11336 | ||
11337 | my_getExpression (&imm_expr, s); | |
11338 | check_absolute_expr (ip, &imm_expr); | |
11339 | min_range = -((mask + 1) >> 1); | |
11340 | max_range = ((mask + 1) >> 1) - 1; | |
11341 | if (imm_expr.X_add_number < min_range | |
11342 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11343 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11344 | (long) min_range, (long) max_range, | |
11345 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11346 | INSERT_OPERAND (mips_opts.micromips, |
11347 | IMM10, *ip, imm_expr.X_add_number); | |
11348 | imm_expr.X_op = O_absent; | |
11349 | s = expr_end; | |
11350 | } | |
11351 | continue; | |
11352 | ||
11353 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11354 | gas_assert (mips_opts.micromips); | |
11355 | my_getExpression (&imm_expr, s); | |
11356 | check_absolute_expr (ip, &imm_expr); | |
11357 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11358 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11359 | MICROMIPSOP_MASK_RD, | |
11360 | (unsigned long) imm_expr.X_add_number); | |
11361 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11362 | imm_expr.X_op = O_absent; |
11363 | s = expr_end; | |
11364 | continue; | |
11365 | ||
a9e24354 | 11366 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11367 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11368 | my_getExpression (&imm_expr, s); |
11369 | check_absolute_expr (ip, &imm_expr); | |
11370 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11371 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11372 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11373 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11374 | imm_expr.X_op = O_absent; |
11375 | s = expr_end; | |
11376 | continue; | |
11377 | ||
a9e24354 | 11378 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11379 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11380 | my_getExpression (&imm_expr, s); |
11381 | check_absolute_expr (ip, &imm_expr); | |
11382 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11383 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11384 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11385 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11386 | imm_expr.X_op = O_absent; |
11387 | s = expr_end; | |
11388 | continue; | |
11389 | ||
90ecf173 | 11390 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11391 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11392 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11393 | s[3] >= '0' && s[3] <= '3') | |
11394 | { | |
11395 | regno = s[3] - '0'; | |
11396 | s += 4; | |
df58fc94 | 11397 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11398 | continue; |
11399 | } | |
11400 | else | |
11401 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11402 | break; | |
11403 | ||
90ecf173 | 11404 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11405 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11406 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11407 | s[3] >= '0' && s[3] <= '3') | |
11408 | { | |
11409 | regno = s[3] - '0'; | |
11410 | s += 4; | |
df58fc94 | 11411 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11412 | continue; |
11413 | } | |
11414 | else | |
11415 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11416 | break; | |
11417 | ||
dec0624d MR |
11418 | case '\\': /* 3-bit bit position. */ |
11419 | { | |
2906b037 MR |
11420 | unsigned long mask = (mips_opts.micromips |
11421 | ? MICROMIPSOP_MASK_3BITPOS | |
11422 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11423 | |
11424 | my_getExpression (&imm_expr, s); | |
11425 | check_absolute_expr (ip, &imm_expr); | |
11426 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11427 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11428 | ip->insn_mo->name, | |
11429 | mask, (unsigned long) imm_expr.X_add_number); | |
11430 | INSERT_OPERAND (mips_opts.micromips, | |
11431 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11432 | imm_expr.X_op = O_absent; | |
11433 | s = expr_end; | |
11434 | } | |
11435 | continue; | |
11436 | ||
252b5132 | 11437 | case ',': |
a339155f | 11438 | ++argnum; |
252b5132 RH |
11439 | if (*s++ == *args) |
11440 | continue; | |
11441 | s--; | |
11442 | switch (*++args) | |
11443 | { | |
11444 | case 'r': | |
11445 | case 'v': | |
df58fc94 | 11446 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11447 | continue; |
11448 | ||
11449 | case 'w': | |
df58fc94 | 11450 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11451 | continue; |
11452 | ||
252b5132 | 11453 | case 'W': |
df58fc94 RS |
11454 | gas_assert (!mips_opts.micromips); |
11455 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11456 | continue; |
11457 | ||
11458 | case 'V': | |
df58fc94 | 11459 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11460 | continue; |
11461 | } | |
11462 | break; | |
11463 | ||
11464 | case '(': | |
11465 | /* Handle optional base register. | |
11466 | Either the base register is omitted or | |
bdaaa2e1 | 11467 | we must have a left paren. */ |
252b5132 RH |
11468 | /* This is dependent on the next operand specifier |
11469 | is a base register specification. */ | |
df58fc94 RS |
11470 | gas_assert (args[1] == 'b' |
11471 | || (mips_opts.micromips | |
11472 | && args[1] == 'm' | |
11473 | && (args[2] == 'l' || args[2] == 'n' | |
11474 | || args[2] == 's' || args[2] == 'a'))); | |
11475 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11476 | return; |
df58fc94 | 11477 | /* Fall through. */ |
252b5132 | 11478 | |
90ecf173 | 11479 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11480 | if (*s++ == *args) |
11481 | continue; | |
11482 | break; | |
11483 | ||
11484 | case '[': /* These must match exactly. */ | |
60b63b72 | 11485 | case ']': |
df58fc94 | 11486 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11487 | if (*s++ == *args) |
11488 | continue; | |
11489 | break; | |
11490 | ||
af7ee8bf CD |
11491 | case '+': /* Opcode extension character. */ |
11492 | switch (*++args) | |
11493 | { | |
9bcd4f99 TS |
11494 | case '1': /* UDI immediates. */ |
11495 | case '2': | |
11496 | case '3': | |
11497 | case '4': | |
df58fc94 | 11498 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11499 | { |
11500 | const struct mips_immed *imm = mips_immed; | |
11501 | ||
11502 | while (imm->type && imm->type != *args) | |
11503 | ++imm; | |
11504 | if (! imm->type) | |
b37df7c4 | 11505 | abort (); |
9bcd4f99 TS |
11506 | my_getExpression (&imm_expr, s); |
11507 | check_absolute_expr (ip, &imm_expr); | |
11508 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11509 | { | |
11510 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11511 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11512 | (unsigned long) imm_expr.X_add_number, | |
11513 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11514 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11515 | } |
11516 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11517 | << imm->shift); | |
11518 | imm_expr.X_op = O_absent; | |
11519 | s = expr_end; | |
11520 | } | |
11521 | continue; | |
90ecf173 | 11522 | |
b015e599 AP |
11523 | case 'J': /* 10-bit hypcall code. */ |
11524 | gas_assert (!mips_opts.micromips); | |
11525 | { | |
11526 | unsigned long mask = OP_MASK_CODE10; | |
11527 | ||
11528 | my_getExpression (&imm_expr, s); | |
11529 | check_absolute_expr (ip, &imm_expr); | |
11530 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11531 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11532 | ip->insn_mo->name, | |
11533 | mask, (unsigned long) imm_expr.X_add_number); | |
11534 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11535 | imm_expr.X_op = O_absent; | |
11536 | s = expr_end; | |
11537 | } | |
11538 | continue; | |
11539 | ||
071742cf CD |
11540 | case 'A': /* ins/ext position, becomes LSB. */ |
11541 | limlo = 0; | |
11542 | limhi = 31; | |
5f74bc13 CD |
11543 | goto do_lsb; |
11544 | case 'E': | |
11545 | limlo = 32; | |
11546 | limhi = 63; | |
11547 | goto do_lsb; | |
90ecf173 | 11548 | do_lsb: |
071742cf CD |
11549 | my_getExpression (&imm_expr, s); |
11550 | check_absolute_expr (ip, &imm_expr); | |
11551 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11552 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11553 | { | |
11554 | as_bad (_("Improper position (%lu)"), | |
11555 | (unsigned long) imm_expr.X_add_number); | |
11556 | imm_expr.X_add_number = limlo; | |
11557 | } | |
11558 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11559 | INSERT_OPERAND (mips_opts.micromips, |
11560 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11561 | imm_expr.X_op = O_absent; |
11562 | s = expr_end; | |
11563 | continue; | |
11564 | ||
11565 | case 'B': /* ins size, becomes MSB. */ | |
11566 | limlo = 1; | |
11567 | limhi = 32; | |
5f74bc13 CD |
11568 | goto do_msb; |
11569 | case 'F': | |
11570 | limlo = 33; | |
11571 | limhi = 64; | |
11572 | goto do_msb; | |
90ecf173 | 11573 | do_msb: |
071742cf CD |
11574 | my_getExpression (&imm_expr, s); |
11575 | check_absolute_expr (ip, &imm_expr); | |
11576 | /* Check for negative input so that small negative numbers | |
11577 | will not succeed incorrectly. The checks against | |
11578 | (pos+size) transitively check "size" itself, | |
11579 | assuming that "pos" is reasonable. */ | |
11580 | if ((long) imm_expr.X_add_number < 0 | |
11581 | || ((unsigned long) imm_expr.X_add_number | |
11582 | + lastpos) < limlo | |
11583 | || ((unsigned long) imm_expr.X_add_number | |
11584 | + lastpos) > limhi) | |
11585 | { | |
11586 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11587 | (unsigned long) imm_expr.X_add_number, | |
11588 | (unsigned long) lastpos); | |
11589 | imm_expr.X_add_number = limlo - lastpos; | |
11590 | } | |
df58fc94 RS |
11591 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11592 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11593 | imm_expr.X_op = O_absent; |
11594 | s = expr_end; | |
11595 | continue; | |
11596 | ||
11597 | case 'C': /* ext size, becomes MSBD. */ | |
11598 | limlo = 1; | |
11599 | limhi = 32; | |
f02d8318 | 11600 | sizelo = 1; |
5f74bc13 CD |
11601 | goto do_msbd; |
11602 | case 'G': | |
11603 | limlo = 33; | |
11604 | limhi = 64; | |
f02d8318 | 11605 | sizelo = 33; |
5f74bc13 CD |
11606 | goto do_msbd; |
11607 | case 'H': | |
11608 | limlo = 33; | |
11609 | limhi = 64; | |
f02d8318 | 11610 | sizelo = 1; |
5f74bc13 | 11611 | goto do_msbd; |
90ecf173 | 11612 | do_msbd: |
071742cf CD |
11613 | my_getExpression (&imm_expr, s); |
11614 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11615 | /* The checks against (pos+size) don't transitively check |
11616 | "size" itself, assuming that "pos" is reasonable. | |
11617 | We also need to check the lower bound of "size". */ | |
11618 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11619 | || ((unsigned long) imm_expr.X_add_number |
11620 | + lastpos) < limlo | |
11621 | || ((unsigned long) imm_expr.X_add_number | |
11622 | + lastpos) > limhi) | |
11623 | { | |
11624 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11625 | (unsigned long) imm_expr.X_add_number, | |
11626 | (unsigned long) lastpos); | |
11627 | imm_expr.X_add_number = limlo - lastpos; | |
11628 | } | |
df58fc94 RS |
11629 | INSERT_OPERAND (mips_opts.micromips, |
11630 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11631 | imm_expr.X_op = O_absent; |
11632 | s = expr_end; | |
11633 | continue; | |
af7ee8bf | 11634 | |
bbcc0807 CD |
11635 | case 'D': |
11636 | /* +D is for disassembly only; never match. */ | |
11637 | break; | |
11638 | ||
5f74bc13 CD |
11639 | case 'I': |
11640 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11641 | my_getExpression (&imm2_expr, s); | |
11642 | if (imm2_expr.X_op != O_big | |
11643 | && imm2_expr.X_op != O_constant) | |
11644 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11645 | if (HAVE_32BIT_GPRS) |
11646 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11647 | s = expr_end; |
11648 | continue; | |
11649 | ||
707bfff6 | 11650 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11651 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11652 | /* +T is for disassembly only; never match. */ |
11653 | break; | |
11654 | ||
707bfff6 | 11655 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11656 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11657 | if (s[0] == '$' && ISDIGIT (s[1])) |
11658 | { | |
11659 | ++s; | |
11660 | regno = 0; | |
11661 | do | |
11662 | { | |
11663 | regno *= 10; | |
11664 | regno += *s - '0'; | |
11665 | ++s; | |
11666 | } | |
11667 | while (ISDIGIT (*s)); | |
11668 | if (regno > 31) | |
11669 | as_bad (_("Invalid register number (%d)"), regno); | |
11670 | else | |
11671 | { | |
df58fc94 | 11672 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11673 | continue; |
11674 | } | |
11675 | } | |
11676 | else | |
11677 | as_bad (_("Invalid coprocessor 0 register number")); | |
11678 | break; | |
11679 | ||
bb35fb24 NC |
11680 | case 'x': |
11681 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11682 | is not in the valid range. */ | |
df58fc94 | 11683 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11684 | my_getExpression (&imm_expr, s); |
11685 | check_absolute_expr (ip, &imm_expr); | |
11686 | if ((unsigned) imm_expr.X_add_number > 31) | |
11687 | { | |
11688 | as_bad (_("Improper bit index (%lu)"), | |
11689 | (unsigned long) imm_expr.X_add_number); | |
11690 | imm_expr.X_add_number = 0; | |
11691 | } | |
df58fc94 | 11692 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11693 | imm_expr.X_op = O_absent; |
11694 | s = expr_end; | |
11695 | continue; | |
11696 | ||
11697 | case 'X': | |
11698 | /* bbit[01] bit index when bbit is used but we generate | |
11699 | bbit[01]32 because the index is over 32. Move to the | |
11700 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11701 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11702 | my_getExpression (&imm_expr, s); |
11703 | check_absolute_expr (ip, &imm_expr); | |
11704 | if ((unsigned) imm_expr.X_add_number < 32 | |
11705 | || (unsigned) imm_expr.X_add_number > 63) | |
11706 | break; | |
df58fc94 | 11707 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11708 | imm_expr.X_op = O_absent; |
11709 | s = expr_end; | |
11710 | continue; | |
11711 | ||
11712 | case 'p': | |
11713 | /* cins, cins32, exts and exts32 position field. Give error | |
11714 | if it's not in the valid range. */ | |
df58fc94 | 11715 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11716 | my_getExpression (&imm_expr, s); |
11717 | check_absolute_expr (ip, &imm_expr); | |
11718 | if ((unsigned) imm_expr.X_add_number > 31) | |
11719 | { | |
11720 | as_bad (_("Improper position (%lu)"), | |
11721 | (unsigned long) imm_expr.X_add_number); | |
11722 | imm_expr.X_add_number = 0; | |
11723 | } | |
11724 | /* Make the pos explicit to simplify +S. */ | |
11725 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11726 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11727 | imm_expr.X_op = O_absent; |
11728 | s = expr_end; | |
11729 | continue; | |
11730 | ||
11731 | case 'P': | |
11732 | /* cins, cins32, exts and exts32 position field. Move to | |
11733 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11734 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11735 | my_getExpression (&imm_expr, s); |
11736 | check_absolute_expr (ip, &imm_expr); | |
11737 | if ((unsigned) imm_expr.X_add_number < 32 | |
11738 | || (unsigned) imm_expr.X_add_number > 63) | |
11739 | break; | |
11740 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11741 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11742 | imm_expr.X_op = O_absent; |
11743 | s = expr_end; | |
11744 | continue; | |
11745 | ||
11746 | case 's': | |
11747 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11748 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11749 | my_getExpression (&imm_expr, s); |
11750 | check_absolute_expr (ip, &imm_expr); | |
11751 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11752 | { | |
11753 | as_bad (_("Improper size (%lu)"), | |
11754 | (unsigned long) imm_expr.X_add_number); | |
11755 | imm_expr.X_add_number = 0; | |
11756 | } | |
df58fc94 | 11757 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11758 | imm_expr.X_op = O_absent; |
11759 | s = expr_end; | |
11760 | continue; | |
11761 | ||
11762 | case 'S': | |
11763 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11764 | length-minus-one field. */ | |
df58fc94 | 11765 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11766 | my_getExpression (&imm_expr, s); |
11767 | check_absolute_expr (ip, &imm_expr); | |
11768 | if ((long) imm_expr.X_add_number < 0 | |
11769 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11770 | { | |
11771 | as_bad (_("Improper size (%lu)"), | |
11772 | (unsigned long) imm_expr.X_add_number); | |
11773 | imm_expr.X_add_number = 0; | |
11774 | } | |
df58fc94 | 11775 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11776 | imm_expr.X_op = O_absent; |
11777 | s = expr_end; | |
11778 | continue; | |
11779 | ||
dd3cbb7e NC |
11780 | case 'Q': |
11781 | /* seqi/snei immediate field. */ | |
df58fc94 | 11782 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11783 | my_getExpression (&imm_expr, s); |
11784 | check_absolute_expr (ip, &imm_expr); | |
11785 | if ((long) imm_expr.X_add_number < -512 | |
11786 | || (long) imm_expr.X_add_number >= 512) | |
11787 | { | |
11788 | as_bad (_("Improper immediate (%ld)"), | |
11789 | (long) imm_expr.X_add_number); | |
11790 | imm_expr.X_add_number = 0; | |
11791 | } | |
df58fc94 | 11792 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11793 | imm_expr.X_op = O_absent; |
11794 | s = expr_end; | |
11795 | continue; | |
11796 | ||
98675402 | 11797 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11798 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11799 | my_getExpression (&imm_expr, s); |
11800 | check_absolute_expr (ip, &imm_expr); | |
11801 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11802 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11803 | if (imm_expr.X_add_number < min_range | |
11804 | || imm_expr.X_add_number > max_range) | |
11805 | { | |
c95354ed | 11806 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11807 | (long) min_range, (long) max_range, |
11808 | (long) imm_expr.X_add_number); | |
11809 | } | |
df58fc94 | 11810 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11811 | imm_expr.X_op = O_absent; |
11812 | s = expr_end; | |
11813 | continue; | |
11814 | ||
11815 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11816 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11817 | my_getExpression (&imm_expr, s); |
11818 | check_absolute_expr (ip, &imm_expr); | |
11819 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11820 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11821 | if (imm_expr.X_add_number < min_range | |
11822 | || imm_expr.X_add_number > max_range) | |
11823 | { | |
c95354ed | 11824 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11825 | (long) min_range, (long) max_range, |
11826 | (long) imm_expr.X_add_number); | |
11827 | } | |
df58fc94 | 11828 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11829 | imm_expr.X_op = O_absent; |
11830 | s = expr_end; | |
11831 | continue; | |
11832 | ||
11833 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11834 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11835 | my_getExpression (&imm_expr, s); |
11836 | check_absolute_expr (ip, &imm_expr); | |
11837 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11838 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11839 | /* We check the offset range before adjusted. */ |
11840 | min_range <<= 4; | |
11841 | max_range <<= 4; | |
98675402 RS |
11842 | if (imm_expr.X_add_number < min_range |
11843 | || imm_expr.X_add_number > max_range) | |
11844 | { | |
c95354ed | 11845 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11846 | (long) min_range, (long) max_range, |
11847 | (long) imm_expr.X_add_number); | |
11848 | } | |
c95354ed MX |
11849 | if (imm_expr.X_add_number & 0xf) |
11850 | { | |
11851 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11852 | (long) imm_expr.X_add_number); | |
11853 | } | |
11854 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11855 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11856 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11857 | imm_expr.X_op = O_absent; |
11858 | s = expr_end; | |
11859 | continue; | |
11860 | ||
11861 | case 'z': | |
df58fc94 | 11862 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11863 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11864 | break; | |
11865 | if (regno == AT && mips_opts.at) | |
11866 | { | |
11867 | if (mips_opts.at == ATREG) | |
11868 | as_warn (_("used $at without \".set noat\"")); | |
11869 | else | |
11870 | as_warn (_("used $%u with \".set at=$%u\""), | |
11871 | regno, mips_opts.at); | |
11872 | } | |
df58fc94 | 11873 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11874 | continue; |
11875 | ||
11876 | case 'Z': | |
df58fc94 | 11877 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11878 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11879 | break; | |
df58fc94 | 11880 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11881 | continue; |
11882 | ||
7f3c4072 CM |
11883 | case 'j': |
11884 | { | |
11885 | int shift = 8; | |
11886 | size_t i; | |
11887 | /* Check whether there is only a single bracketed expression | |
11888 | left. If so, it must be the base register and the | |
11889 | constant must be zero. */ | |
11890 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11891 | continue; | |
11892 | ||
11893 | /* If this value won't fit into the offset, then go find | |
11894 | a macro that will generate a 16- or 32-bit offset code | |
11895 | pattern. */ | |
11896 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11897 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11898 | || imm_expr.X_add_number >= 1 << shift | |
11899 | || imm_expr.X_add_number < -1 << shift)) | |
11900 | || i > 0) | |
11901 | { | |
11902 | imm_expr.X_op = O_absent; | |
11903 | break; | |
11904 | } | |
11905 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
11906 | imm_expr.X_add_number); | |
11907 | imm_expr.X_op = O_absent; | |
11908 | s = expr_end; | |
11909 | } | |
11910 | continue; | |
11911 | ||
af7ee8bf | 11912 | default: |
df58fc94 | 11913 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11914 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11915 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11916 | *args, insn->name, insn->args); |
af7ee8bf CD |
11917 | /* Further processing is fruitless. */ |
11918 | return; | |
11919 | } | |
11920 | break; | |
11921 | ||
df58fc94 | 11922 | case '.': /* 10-bit offset. */ |
df58fc94 | 11923 | gas_assert (mips_opts.micromips); |
dec0624d | 11924 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11925 | { |
11926 | int shift = *args == '.' ? 9 : 11; | |
11927 | size_t i; | |
11928 | ||
11929 | /* Check whether there is only a single bracketed expression | |
11930 | left. If so, it must be the base register and the | |
11931 | constant must be zero. */ | |
11932 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11933 | continue; | |
11934 | ||
11935 | /* If this value won't fit into the offset, then go find | |
11936 | a macro that will generate a 16- or 32-bit offset code | |
11937 | pattern. */ | |
11938 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11939 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11940 | || imm_expr.X_add_number >= 1 << shift | |
11941 | || imm_expr.X_add_number < -1 << shift)) | |
11942 | || i > 0) | |
11943 | { | |
11944 | imm_expr.X_op = O_absent; | |
11945 | break; | |
11946 | } | |
11947 | if (shift == 9) | |
11948 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11949 | else | |
dec0624d MR |
11950 | INSERT_OPERAND (mips_opts.micromips, |
11951 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11952 | imm_expr.X_op = O_absent; |
11953 | s = expr_end; | |
11954 | } | |
11955 | continue; | |
11956 | ||
252b5132 RH |
11957 | case '<': /* must be at least one digit */ |
11958 | /* | |
11959 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11960 | * than 31 or less than 0, then the shift amount should be |
11961 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11962 | * We issue a warning and mask out all but the low 5 bits. |
11963 | */ | |
11964 | my_getExpression (&imm_expr, s); | |
11965 | check_absolute_expr (ip, &imm_expr); | |
11966 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11967 | as_warn (_("Improper shift amount (%lu)"), |
11968 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11969 | INSERT_OPERAND (mips_opts.micromips, |
11970 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11971 | imm_expr.X_op = O_absent; |
11972 | s = expr_end; | |
11973 | continue; | |
11974 | ||
11975 | case '>': /* shift amount minus 32 */ | |
11976 | my_getExpression (&imm_expr, s); | |
11977 | check_absolute_expr (ip, &imm_expr); | |
11978 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11979 | || (unsigned long) imm_expr.X_add_number > 63) | |
11980 | break; | |
df58fc94 RS |
11981 | INSERT_OPERAND (mips_opts.micromips, |
11982 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11983 | imm_expr.X_op = O_absent; |
11984 | s = expr_end; | |
11985 | continue; | |
11986 | ||
90ecf173 MR |
11987 | case 'k': /* CACHE code. */ |
11988 | case 'h': /* PREFX code. */ | |
11989 | case '1': /* SYNC type. */ | |
252b5132 RH |
11990 | my_getExpression (&imm_expr, s); |
11991 | check_absolute_expr (ip, &imm_expr); | |
11992 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11993 | as_warn (_("Invalid value for `%s' (%lu)"), |
11994 | ip->insn_mo->name, | |
11995 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11996 | switch (*args) |
d954098f | 11997 | { |
df58fc94 RS |
11998 | case 'k': |
11999 | if (mips_fix_cn63xxp1 | |
12000 | && !mips_opts.micromips | |
12001 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12002 | switch (imm_expr.X_add_number) |
12003 | { | |
12004 | case 5: | |
12005 | case 25: | |
12006 | case 26: | |
12007 | case 27: | |
12008 | case 28: | |
12009 | case 29: | |
12010 | case 30: | |
12011 | case 31: /* These are ok. */ | |
12012 | break; | |
12013 | ||
12014 | default: /* The rest must be changed to 28. */ | |
12015 | imm_expr.X_add_number = 28; | |
12016 | break; | |
12017 | } | |
df58fc94 RS |
12018 | INSERT_OPERAND (mips_opts.micromips, |
12019 | CACHE, *ip, imm_expr.X_add_number); | |
12020 | break; | |
12021 | case 'h': | |
12022 | INSERT_OPERAND (mips_opts.micromips, | |
12023 | PREFX, *ip, imm_expr.X_add_number); | |
12024 | break; | |
12025 | case '1': | |
12026 | INSERT_OPERAND (mips_opts.micromips, | |
12027 | STYPE, *ip, imm_expr.X_add_number); | |
12028 | break; | |
d954098f | 12029 | } |
252b5132 RH |
12030 | imm_expr.X_op = O_absent; |
12031 | s = expr_end; | |
12032 | continue; | |
12033 | ||
90ecf173 | 12034 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12035 | { |
12036 | unsigned long mask = (mips_opts.micromips | |
12037 | ? MICROMIPSOP_MASK_CODE | |
12038 | : OP_MASK_CODE); | |
12039 | ||
12040 | my_getExpression (&imm_expr, s); | |
12041 | check_absolute_expr (ip, &imm_expr); | |
12042 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12043 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12044 | ip->insn_mo->name, | |
12045 | mask, (unsigned long) imm_expr.X_add_number); | |
12046 | INSERT_OPERAND (mips_opts.micromips, | |
12047 | CODE, *ip, imm_expr.X_add_number); | |
12048 | imm_expr.X_op = O_absent; | |
12049 | s = expr_end; | |
12050 | } | |
252b5132 RH |
12051 | continue; |
12052 | ||
90ecf173 | 12053 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12054 | { |
12055 | unsigned long mask = (mips_opts.micromips | |
12056 | ? MICROMIPSOP_MASK_CODE2 | |
12057 | : OP_MASK_CODE2); | |
12058 | ||
12059 | my_getExpression (&imm_expr, s); | |
12060 | check_absolute_expr (ip, &imm_expr); | |
12061 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12062 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12063 | ip->insn_mo->name, | |
12064 | mask, (unsigned long) imm_expr.X_add_number); | |
12065 | INSERT_OPERAND (mips_opts.micromips, | |
12066 | CODE2, *ip, imm_expr.X_add_number); | |
12067 | imm_expr.X_op = O_absent; | |
12068 | s = expr_end; | |
12069 | } | |
252b5132 RH |
12070 | continue; |
12071 | ||
df58fc94 RS |
12072 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12073 | { | |
12074 | unsigned long mask = (mips_opts.micromips | |
12075 | ? MICROMIPSOP_MASK_CODE10 | |
12076 | : OP_MASK_CODE20); | |
12077 | ||
12078 | my_getExpression (&imm_expr, s); | |
12079 | check_absolute_expr (ip, &imm_expr); | |
12080 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12081 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12082 | ip->insn_mo->name, | |
12083 | mask, (unsigned long) imm_expr.X_add_number); | |
12084 | if (mips_opts.micromips) | |
12085 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12086 | else | |
12087 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12088 | imm_expr.X_op = O_absent; | |
12089 | s = expr_end; | |
12090 | } | |
252b5132 RH |
12091 | continue; |
12092 | ||
df58fc94 RS |
12093 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12094 | { | |
12095 | unsigned long mask = (mips_opts.micromips | |
12096 | ? MICROMIPSOP_MASK_COPZ | |
12097 | : OP_MASK_COPZ); | |
12098 | ||
12099 | my_getExpression (&imm_expr, s); | |
12100 | check_absolute_expr (ip, &imm_expr); | |
12101 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12102 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12103 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12104 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12105 | INSERT_OPERAND (mips_opts.micromips, |
12106 | COPZ, *ip, imm_expr.X_add_number); | |
12107 | imm_expr.X_op = O_absent; | |
12108 | s = expr_end; | |
12109 | } | |
beae10d5 | 12110 | continue; |
252b5132 | 12111 | |
df58fc94 RS |
12112 | case 'J': /* 19-bit WAIT code. */ |
12113 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12114 | my_getExpression (&imm_expr, s); |
12115 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12116 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12117 | { |
12118 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12119 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12120 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12121 | } | |
12122 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12123 | imm_expr.X_op = O_absent; |
12124 | s = expr_end; | |
12125 | continue; | |
12126 | ||
707bfff6 | 12127 | case 'P': /* Performance register. */ |
df58fc94 | 12128 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12129 | my_getExpression (&imm_expr, s); |
252b5132 | 12130 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12131 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12132 | as_warn (_("Invalid performance register (%lu)"), |
12133 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12134 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12135 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12136 | as_warn (_("Invalid performance register (%lu)"), | |
12137 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12138 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12139 | imm_expr.X_op = O_absent; |
12140 | s = expr_end; | |
12141 | continue; | |
252b5132 | 12142 | |
707bfff6 | 12143 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12144 | { |
12145 | unsigned long opcode = ip->insn_opcode; | |
12146 | unsigned long mask; | |
12147 | unsigned int types; | |
12148 | int cop0; | |
12149 | ||
12150 | if (mips_opts.micromips) | |
12151 | { | |
12152 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12153 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12154 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12155 | opcode &= mask; | |
12156 | switch (opcode) | |
12157 | { | |
12158 | case 0x000000fc: /* mfc0 */ | |
12159 | case 0x000002fc: /* mtc0 */ | |
12160 | case 0x580000fc: /* dmfc0 */ | |
12161 | case 0x580002fc: /* dmtc0 */ | |
12162 | cop0 = 1; | |
12163 | break; | |
12164 | default: | |
12165 | cop0 = 0; | |
12166 | break; | |
12167 | } | |
12168 | } | |
12169 | else | |
12170 | { | |
12171 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12172 | cop0 = opcode == OP_OP_COP0; | |
12173 | } | |
12174 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12175 | ok = reg_lookup (&s, types, ®no); | |
12176 | if (mips_opts.micromips) | |
12177 | INSERT_OPERAND (1, RS, *ip, regno); | |
12178 | else | |
12179 | INSERT_OPERAND (0, RD, *ip, regno); | |
12180 | if (ok) | |
12181 | { | |
12182 | lastregno = regno; | |
12183 | continue; | |
12184 | } | |
12185 | } | |
12186 | break; | |
707bfff6 | 12187 | |
df58fc94 RS |
12188 | case 'y': /* ALNV.PS source register. */ |
12189 | gas_assert (mips_opts.micromips); | |
12190 | goto do_reg; | |
12191 | case 'x': /* Ignore register name. */ | |
12192 | case 'U': /* Destination register (CLO/CLZ). */ | |
12193 | case 'g': /* Coprocessor destination register. */ | |
12194 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12195 | case 'b': /* Base register. */ |
12196 | case 'd': /* Destination register. */ | |
12197 | case 's': /* Source register. */ | |
12198 | case 't': /* Target register. */ | |
12199 | case 'r': /* Both target and source. */ | |
12200 | case 'v': /* Both dest and source. */ | |
12201 | case 'w': /* Both dest and target. */ | |
12202 | case 'E': /* Coprocessor target register. */ | |
12203 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12204 | case 'z': /* Must be zero register. */ |
df58fc94 | 12205 | do_reg: |
90ecf173 | 12206 | s_reset = s; |
707bfff6 TS |
12207 | if (*args == 'E' || *args == 'K') |
12208 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12209 | else | |
12210 | { | |
12211 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12212 | if (regno == AT && mips_opts.at) |
12213 | { | |
12214 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12215 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12216 | else |
f71d0d44 | 12217 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12218 | regno, mips_opts.at); |
12219 | } | |
707bfff6 TS |
12220 | } |
12221 | if (ok) | |
252b5132 | 12222 | { |
252b5132 RH |
12223 | c = *args; |
12224 | if (*s == ' ') | |
f9419b05 | 12225 | ++s; |
252b5132 RH |
12226 | if (args[1] != *s) |
12227 | { | |
12228 | if (c == 'r' || c == 'v' || c == 'w') | |
12229 | { | |
12230 | regno = lastregno; | |
12231 | s = s_reset; | |
f9419b05 | 12232 | ++args; |
252b5132 RH |
12233 | } |
12234 | } | |
12235 | /* 'z' only matches $0. */ | |
12236 | if (c == 'z' && regno != 0) | |
12237 | break; | |
12238 | ||
24864476 | 12239 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12240 | { |
12241 | if (regno == lastregno) | |
90ecf173 MR |
12242 | { |
12243 | insn_error | |
f71d0d44 | 12244 | = _("Source and destination must be different"); |
e7c604dd | 12245 | continue; |
90ecf173 | 12246 | } |
24864476 | 12247 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12248 | { |
12249 | insn_error | |
f71d0d44 | 12250 | = _("A destination register must be supplied"); |
e7c604dd | 12251 | continue; |
90ecf173 | 12252 | } |
e7c604dd | 12253 | } |
90ecf173 MR |
12254 | /* Now that we have assembled one operand, we use the args |
12255 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12256 | switch (c) |
12257 | { | |
12258 | case 'r': | |
12259 | case 's': | |
12260 | case 'v': | |
12261 | case 'b': | |
df58fc94 | 12262 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12263 | break; |
df58fc94 | 12264 | |
af7ee8bf | 12265 | case 'K': |
df58fc94 RS |
12266 | if (mips_opts.micromips) |
12267 | INSERT_OPERAND (1, RS, *ip, regno); | |
12268 | else | |
12269 | INSERT_OPERAND (0, RD, *ip, regno); | |
12270 | break; | |
12271 | ||
12272 | case 'd': | |
ef2e4d86 | 12273 | case 'g': |
df58fc94 | 12274 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12275 | break; |
df58fc94 | 12276 | |
4372b673 | 12277 | case 'U': |
df58fc94 RS |
12278 | gas_assert (!mips_opts.micromips); |
12279 | INSERT_OPERAND (0, RD, *ip, regno); | |
12280 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12281 | break; |
df58fc94 | 12282 | |
252b5132 RH |
12283 | case 'w': |
12284 | case 't': | |
12285 | case 'E': | |
df58fc94 RS |
12286 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12287 | break; | |
12288 | ||
12289 | case 'y': | |
12290 | gas_assert (mips_opts.micromips); | |
12291 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12292 | break; |
df58fc94 | 12293 | |
252b5132 RH |
12294 | case 'x': |
12295 | /* This case exists because on the r3000 trunc | |
12296 | expands into a macro which requires a gp | |
12297 | register. On the r6000 or r4000 it is | |
12298 | assembled into a single instruction which | |
12299 | ignores the register. Thus the insn version | |
12300 | is MIPS_ISA2 and uses 'x', and the macro | |
12301 | version is MIPS_ISA1 and uses 't'. */ | |
12302 | break; | |
df58fc94 | 12303 | |
252b5132 RH |
12304 | case 'z': |
12305 | /* This case is for the div instruction, which | |
12306 | acts differently if the destination argument | |
12307 | is $0. This only matches $0, and is checked | |
12308 | outside the switch. */ | |
12309 | break; | |
252b5132 RH |
12310 | } |
12311 | lastregno = regno; | |
12312 | continue; | |
12313 | } | |
252b5132 RH |
12314 | switch (*args++) |
12315 | { | |
12316 | case 'r': | |
12317 | case 'v': | |
df58fc94 | 12318 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12319 | continue; |
df58fc94 | 12320 | |
252b5132 | 12321 | case 'w': |
df58fc94 | 12322 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12323 | continue; |
12324 | } | |
12325 | break; | |
12326 | ||
deec1734 | 12327 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12328 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12329 | my_getExpression (&imm_expr, s); |
12330 | check_absolute_expr (ip, &imm_expr); | |
12331 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12332 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12333 | (long) imm_expr.X_add_number); |
df58fc94 | 12334 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12335 | imm_expr.X_op = O_absent; |
12336 | s = expr_end; | |
12337 | continue; | |
12338 | ||
12339 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12340 | if (s[0] != '$') | |
12341 | { | |
12342 | /* MDMX Immediate. */ | |
df58fc94 | 12343 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12344 | my_getExpression (&imm_expr, s); |
12345 | check_absolute_expr (ip, &imm_expr); | |
12346 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12347 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12348 | (long) imm_expr.X_add_number); | |
df58fc94 | 12349 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12350 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12351 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12352 | else | |
12353 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12354 | imm_expr.X_op = O_absent; |
12355 | s = expr_end; | |
12356 | continue; | |
12357 | } | |
12358 | /* Not MDMX Immediate. Fall through. */ | |
12359 | case 'X': /* MDMX destination register. */ | |
12360 | case 'Y': /* MDMX source register. */ | |
12361 | case 'Z': /* MDMX target register. */ | |
12362 | is_mdmx = 1; | |
df58fc94 RS |
12363 | case 'W': |
12364 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12365 | case 'D': /* Floating point destination register. */ |
12366 | case 'S': /* Floating point source register. */ | |
12367 | case 'T': /* Floating point target register. */ | |
12368 | case 'R': /* Floating point source register. */ | |
252b5132 | 12369 | case 'V': |
707bfff6 TS |
12370 | rtype = RTYPE_FPU; |
12371 | if (is_mdmx | |
12372 | || (mips_opts.ase_mdmx | |
12373 | && (ip->insn_mo->pinfo & FP_D) | |
12374 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12375 | | INSN_COPROC_MEMORY_DELAY | |
12376 | | INSN_LOAD_COPROC_DELAY | |
12377 | | INSN_LOAD_MEMORY_DELAY | |
12378 | | INSN_STORE_MEMORY)))) | |
12379 | rtype |= RTYPE_VEC; | |
252b5132 | 12380 | s_reset = s; |
707bfff6 | 12381 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12382 | { |
252b5132 | 12383 | if ((regno & 1) != 0 |
ca4e0257 | 12384 | && HAVE_32BIT_FPRS |
90ecf173 | 12385 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12386 | as_warn (_("Float register should be even, was %d"), |
12387 | regno); | |
12388 | ||
12389 | c = *args; | |
12390 | if (*s == ' ') | |
f9419b05 | 12391 | ++s; |
252b5132 RH |
12392 | if (args[1] != *s) |
12393 | { | |
12394 | if (c == 'V' || c == 'W') | |
12395 | { | |
12396 | regno = lastregno; | |
12397 | s = s_reset; | |
f9419b05 | 12398 | ++args; |
252b5132 RH |
12399 | } |
12400 | } | |
12401 | switch (c) | |
12402 | { | |
12403 | case 'D': | |
deec1734 | 12404 | case 'X': |
df58fc94 | 12405 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12406 | break; |
df58fc94 | 12407 | |
252b5132 RH |
12408 | case 'V': |
12409 | case 'S': | |
deec1734 | 12410 | case 'Y': |
df58fc94 | 12411 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12412 | break; |
df58fc94 | 12413 | |
deec1734 CD |
12414 | case 'Q': |
12415 | /* This is like 'Z', but also needs to fix the MDMX | |
12416 | vector/scalar select bits. Note that the | |
12417 | scalar immediate case is handled above. */ | |
12418 | if (*s == '[') | |
12419 | { | |
12420 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12421 | int max_el = (is_qh ? 3 : 7); | |
12422 | s++; | |
12423 | my_getExpression(&imm_expr, s); | |
12424 | check_absolute_expr (ip, &imm_expr); | |
12425 | s = expr_end; | |
12426 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12427 | as_bad (_("Bad element selector %ld"), |
12428 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12429 | imm_expr.X_add_number &= max_el; |
12430 | ip->insn_opcode |= (imm_expr.X_add_number | |
12431 | << (OP_SH_VSEL + | |
12432 | (is_qh ? 2 : 1))); | |
01a3f561 | 12433 | imm_expr.X_op = O_absent; |
deec1734 | 12434 | if (*s != ']') |
20203fb9 | 12435 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12436 | else |
12437 | s++; | |
12438 | } | |
12439 | else | |
12440 | { | |
12441 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12442 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12443 | << OP_SH_VSEL); | |
12444 | else | |
12445 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12446 | OP_SH_VSEL); | |
12447 | } | |
90ecf173 | 12448 | /* Fall through. */ |
252b5132 RH |
12449 | case 'W': |
12450 | case 'T': | |
deec1734 | 12451 | case 'Z': |
df58fc94 | 12452 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12453 | break; |
df58fc94 | 12454 | |
252b5132 | 12455 | case 'R': |
df58fc94 | 12456 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12457 | break; |
12458 | } | |
12459 | lastregno = regno; | |
12460 | continue; | |
12461 | } | |
12462 | ||
252b5132 RH |
12463 | switch (*args++) |
12464 | { | |
12465 | case 'V': | |
df58fc94 | 12466 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12467 | continue; |
df58fc94 | 12468 | |
252b5132 | 12469 | case 'W': |
df58fc94 | 12470 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12471 | continue; |
12472 | } | |
12473 | break; | |
12474 | ||
12475 | case 'I': | |
12476 | my_getExpression (&imm_expr, s); | |
12477 | if (imm_expr.X_op != O_big | |
12478 | && imm_expr.X_op != O_constant) | |
12479 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12480 | if (HAVE_32BIT_GPRS) |
12481 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12482 | s = expr_end; |
12483 | continue; | |
12484 | ||
12485 | case 'A': | |
12486 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12487 | normalize_address_expr (&offset_expr); |
f6688943 | 12488 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12489 | s = expr_end; |
12490 | continue; | |
12491 | ||
12492 | case 'F': | |
12493 | case 'L': | |
12494 | case 'f': | |
12495 | case 'l': | |
12496 | { | |
12497 | int f64; | |
ca4e0257 | 12498 | int using_gprs; |
252b5132 RH |
12499 | char *save_in; |
12500 | char *err; | |
12501 | unsigned char temp[8]; | |
12502 | int len; | |
12503 | unsigned int length; | |
12504 | segT seg; | |
12505 | subsegT subseg; | |
12506 | char *p; | |
12507 | ||
12508 | /* These only appear as the last operand in an | |
12509 | instruction, and every instruction that accepts | |
12510 | them in any variant accepts them in all variants. | |
12511 | This means we don't have to worry about backing out | |
12512 | any changes if the instruction does not match. | |
12513 | ||
12514 | The difference between them is the size of the | |
12515 | floating point constant and where it goes. For 'F' | |
12516 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12517 | is 32 bits. Where the constant is placed is based | |
12518 | on how the MIPS assembler does things: | |
12519 | F -- .rdata | |
12520 | L -- .lit8 | |
12521 | f -- immediate value | |
12522 | l -- .lit4 | |
12523 | ||
12524 | The .lit4 and .lit8 sections are only used if | |
12525 | permitted by the -G argument. | |
12526 | ||
ca4e0257 RS |
12527 | The code below needs to know whether the target register |
12528 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12529 | 'F' are used with GPR-based instructions and 'l' and | |
12530 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12531 | |
12532 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12533 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12534 | |
12535 | save_in = input_line_pointer; | |
12536 | input_line_pointer = s; | |
12537 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12538 | length = len; | |
12539 | s = input_line_pointer; | |
12540 | input_line_pointer = save_in; | |
12541 | if (err != NULL && *err != '\0') | |
12542 | { | |
12543 | as_bad (_("Bad floating point constant: %s"), err); | |
12544 | memset (temp, '\0', sizeof temp); | |
12545 | length = f64 ? 8 : 4; | |
12546 | } | |
12547 | ||
9c2799c2 | 12548 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12549 | |
12550 | if (*args == 'f' | |
12551 | || (*args == 'l' | |
3e722fb5 | 12552 | && (g_switch_value < 4 |
252b5132 RH |
12553 | || (temp[0] == 0 && temp[1] == 0) |
12554 | || (temp[2] == 0 && temp[3] == 0)))) | |
12555 | { | |
12556 | imm_expr.X_op = O_constant; | |
90ecf173 | 12557 | if (!target_big_endian) |
252b5132 RH |
12558 | imm_expr.X_add_number = bfd_getl32 (temp); |
12559 | else | |
12560 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12561 | } | |
12562 | else if (length > 4 | |
90ecf173 | 12563 | && !mips_disable_float_construction |
ca4e0257 RS |
12564 | /* Constants can only be constructed in GPRs and |
12565 | copied to FPRs if the GPRs are at least as wide | |
12566 | as the FPRs. Force the constant into memory if | |
12567 | we are using 64-bit FPRs but the GPRs are only | |
12568 | 32 bits wide. */ | |
12569 | && (using_gprs | |
90ecf173 | 12570 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12571 | && ((temp[0] == 0 && temp[1] == 0) |
12572 | || (temp[2] == 0 && temp[3] == 0)) | |
12573 | && ((temp[4] == 0 && temp[5] == 0) | |
12574 | || (temp[6] == 0 && temp[7] == 0))) | |
12575 | { | |
ca4e0257 | 12576 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12577 | instructions. If using 32-bit registers, set |
12578 | imm_expr to the high order 32 bits and offset_expr to | |
12579 | the low order 32 bits. Otherwise, set imm_expr to | |
12580 | the entire 64 bit constant. */ | |
ca4e0257 | 12581 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12582 | { |
12583 | imm_expr.X_op = O_constant; | |
12584 | offset_expr.X_op = O_constant; | |
90ecf173 | 12585 | if (!target_big_endian) |
252b5132 RH |
12586 | { |
12587 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12588 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12589 | } | |
12590 | else | |
12591 | { | |
12592 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12593 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12594 | } | |
12595 | if (offset_expr.X_add_number == 0) | |
12596 | offset_expr.X_op = O_absent; | |
12597 | } | |
12598 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12599 | { | |
12600 | imm_expr.X_op = O_constant; | |
90ecf173 | 12601 | if (!target_big_endian) |
252b5132 RH |
12602 | imm_expr.X_add_number = bfd_getl64 (temp); |
12603 | else | |
12604 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12605 | } | |
12606 | else | |
12607 | { | |
12608 | imm_expr.X_op = O_big; | |
12609 | imm_expr.X_add_number = 4; | |
90ecf173 | 12610 | if (!target_big_endian) |
252b5132 RH |
12611 | { |
12612 | generic_bignum[0] = bfd_getl16 (temp); | |
12613 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12614 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12615 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12616 | } | |
12617 | else | |
12618 | { | |
12619 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12620 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12621 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12622 | generic_bignum[3] = bfd_getb16 (temp); | |
12623 | } | |
12624 | } | |
12625 | } | |
12626 | else | |
12627 | { | |
12628 | const char *newname; | |
12629 | segT new_seg; | |
12630 | ||
12631 | /* Switch to the right section. */ | |
12632 | seg = now_seg; | |
12633 | subseg = now_subseg; | |
12634 | switch (*args) | |
12635 | { | |
12636 | default: /* unused default case avoids warnings. */ | |
12637 | case 'L': | |
12638 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12639 | if (g_switch_value >= 8) |
252b5132 RH |
12640 | newname = ".lit8"; |
12641 | break; | |
12642 | case 'F': | |
3e722fb5 | 12643 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12644 | break; |
12645 | case 'l': | |
9c2799c2 | 12646 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12647 | newname = ".lit4"; |
12648 | break; | |
12649 | } | |
12650 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12651 | if (IS_ELF) |
252b5132 RH |
12652 | bfd_set_section_flags (stdoutput, new_seg, |
12653 | (SEC_ALLOC | |
12654 | | SEC_LOAD | |
12655 | | SEC_READONLY | |
12656 | | SEC_DATA)); | |
12657 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12658 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12659 | record_alignment (new_seg, 4); |
12660 | else | |
12661 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12662 | if (seg == now_seg) | |
12663 | as_bad (_("Can't use floating point insn in this section")); | |
12664 | ||
df58fc94 RS |
12665 | /* Set the argument to the current address in the |
12666 | section. */ | |
12667 | offset_expr.X_op = O_symbol; | |
12668 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12669 | offset_expr.X_add_number = 0; | |
12670 | ||
12671 | /* Put the floating point number into the section. */ | |
12672 | p = frag_more ((int) length); | |
12673 | memcpy (p, temp, length); | |
12674 | ||
12675 | /* Switch back to the original section. */ | |
12676 | subseg_set (seg, subseg); | |
12677 | } | |
12678 | } | |
12679 | continue; | |
12680 | ||
12681 | case 'i': /* 16-bit unsigned immediate. */ | |
12682 | case 'j': /* 16-bit signed immediate. */ | |
12683 | *imm_reloc = BFD_RELOC_LO16; | |
12684 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12685 | { | |
12686 | int more; | |
12687 | offsetT minval, maxval; | |
12688 | ||
12689 | more = (insn + 1 < past | |
12690 | && strcmp (insn->name, insn[1].name) == 0); | |
12691 | ||
12692 | /* If the expression was written as an unsigned number, | |
12693 | only treat it as signed if there are no more | |
12694 | alternatives. */ | |
12695 | if (more | |
12696 | && *args == 'j' | |
12697 | && sizeof (imm_expr.X_add_number) <= 4 | |
12698 | && imm_expr.X_op == O_constant | |
12699 | && imm_expr.X_add_number < 0 | |
12700 | && imm_expr.X_unsigned | |
12701 | && HAVE_64BIT_GPRS) | |
12702 | break; | |
12703 | ||
12704 | /* For compatibility with older assemblers, we accept | |
12705 | 0x8000-0xffff as signed 16-bit numbers when only | |
12706 | signed numbers are allowed. */ | |
12707 | if (*args == 'i') | |
12708 | minval = 0, maxval = 0xffff; | |
12709 | else if (more) | |
12710 | minval = -0x8000, maxval = 0x7fff; | |
12711 | else | |
12712 | minval = -0x8000, maxval = 0xffff; | |
12713 | ||
12714 | if (imm_expr.X_op != O_constant | |
12715 | || imm_expr.X_add_number < minval | |
12716 | || imm_expr.X_add_number > maxval) | |
12717 | { | |
12718 | if (more) | |
12719 | break; | |
12720 | if (imm_expr.X_op == O_constant | |
12721 | || imm_expr.X_op == O_big) | |
12722 | as_bad (_("Expression out of range")); | |
12723 | } | |
12724 | } | |
12725 | s = expr_end; | |
12726 | continue; | |
12727 | ||
12728 | case 'o': /* 16-bit offset. */ | |
12729 | offset_reloc[0] = BFD_RELOC_LO16; | |
12730 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12731 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12732 | ||
12733 | /* Check whether there is only a single bracketed expression | |
12734 | left. If so, it must be the base register and the | |
12735 | constant must be zero. */ | |
12736 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12737 | { | |
12738 | offset_expr.X_op = O_constant; | |
12739 | offset_expr.X_add_number = 0; | |
12740 | continue; | |
12741 | } | |
12742 | ||
12743 | /* If this value won't fit into a 16 bit offset, then go | |
12744 | find a macro that will generate the 32 bit offset | |
12745 | code pattern. */ | |
12746 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12747 | && (offset_expr.X_op != O_constant | |
12748 | || offset_expr.X_add_number >= 0x8000 | |
12749 | || offset_expr.X_add_number < -0x8000)) | |
12750 | break; | |
12751 | ||
12752 | s = expr_end; | |
12753 | continue; | |
12754 | ||
12755 | case 'p': /* PC-relative offset. */ | |
12756 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12757 | my_getExpression (&offset_expr, s); | |
12758 | s = expr_end; | |
12759 | continue; | |
12760 | ||
12761 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12762 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12763 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12764 | && imm_expr.X_op == O_constant | |
12765 | && (imm_expr.X_add_number < 0 | |
12766 | || imm_expr.X_add_number >= 0x10000)) | |
12767 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12768 | (unsigned long) imm_expr.X_add_number); | |
12769 | s = expr_end; | |
12770 | continue; | |
12771 | ||
12772 | case 'a': /* 26-bit address. */ | |
12773 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12774 | my_getExpression (&offset_expr, s); | |
12775 | s = expr_end; | |
12776 | continue; | |
12777 | ||
12778 | case 'N': /* 3-bit branch condition code. */ | |
12779 | case 'M': /* 3-bit compare condition code. */ | |
12780 | rtype = RTYPE_CCC; | |
12781 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12782 | rtype |= RTYPE_FCC; | |
12783 | if (!reg_lookup (&s, rtype, ®no)) | |
12784 | break; | |
12785 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12786 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12787 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12788 | && (regno & 1) != 0) | |
12789 | as_warn (_("Condition code register should be even for %s, " | |
12790 | "was %d"), | |
12791 | str, regno); | |
12792 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12793 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12794 | && (regno & 3) != 0) | |
12795 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12796 | "was %d"), | |
12797 | str, regno); | |
12798 | if (*args == 'N') | |
12799 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12800 | else | |
12801 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12802 | continue; | |
12803 | ||
12804 | case 'H': | |
12805 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12806 | s += 2; | |
12807 | if (ISDIGIT (*s)) | |
12808 | { | |
12809 | c = 0; | |
12810 | do | |
12811 | { | |
12812 | c *= 10; | |
12813 | c += *s - '0'; | |
12814 | ++s; | |
12815 | } | |
12816 | while (ISDIGIT (*s)); | |
12817 | } | |
12818 | else | |
12819 | c = 8; /* Invalid sel value. */ | |
12820 | ||
12821 | if (c > 7) | |
12822 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12823 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12824 | continue; | |
12825 | ||
12826 | case 'e': | |
12827 | gas_assert (!mips_opts.micromips); | |
12828 | /* Must be at least one digit. */ | |
12829 | my_getExpression (&imm_expr, s); | |
12830 | check_absolute_expr (ip, &imm_expr); | |
12831 | ||
12832 | if ((unsigned long) imm_expr.X_add_number | |
12833 | > (unsigned long) OP_MASK_VECBYTE) | |
12834 | { | |
12835 | as_bad (_("bad byte vector index (%ld)"), | |
12836 | (long) imm_expr.X_add_number); | |
12837 | imm_expr.X_add_number = 0; | |
12838 | } | |
12839 | ||
12840 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12841 | imm_expr.X_op = O_absent; | |
12842 | s = expr_end; | |
12843 | continue; | |
12844 | ||
12845 | case '%': | |
12846 | gas_assert (!mips_opts.micromips); | |
12847 | my_getExpression (&imm_expr, s); | |
12848 | check_absolute_expr (ip, &imm_expr); | |
12849 | ||
12850 | if ((unsigned long) imm_expr.X_add_number | |
12851 | > (unsigned long) OP_MASK_VECALIGN) | |
12852 | { | |
12853 | as_bad (_("bad byte vector index (%ld)"), | |
12854 | (long) imm_expr.X_add_number); | |
12855 | imm_expr.X_add_number = 0; | |
12856 | } | |
12857 | ||
12858 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12859 | imm_expr.X_op = O_absent; | |
12860 | s = expr_end; | |
12861 | continue; | |
12862 | ||
12863 | case 'm': /* Opcode extension character. */ | |
12864 | gas_assert (mips_opts.micromips); | |
12865 | c = *++args; | |
12866 | switch (c) | |
12867 | { | |
12868 | case 'r': | |
12869 | if (strncmp (s, "$pc", 3) == 0) | |
12870 | { | |
12871 | s += 3; | |
12872 | continue; | |
12873 | } | |
12874 | break; | |
12875 | ||
12876 | case 'a': | |
12877 | case 'b': | |
12878 | case 'c': | |
12879 | case 'd': | |
12880 | case 'e': | |
12881 | case 'f': | |
12882 | case 'g': | |
12883 | case 'h': | |
12884 | case 'i': | |
12885 | case 'j': | |
12886 | case 'l': | |
12887 | case 'm': | |
12888 | case 'n': | |
12889 | case 'p': | |
12890 | case 'q': | |
12891 | case 's': | |
12892 | case 't': | |
12893 | case 'x': | |
12894 | case 'y': | |
12895 | case 'z': | |
12896 | s_reset = s; | |
12897 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12898 | if (regno == AT && mips_opts.at) | |
12899 | { | |
12900 | if (mips_opts.at == ATREG) | |
12901 | as_warn (_("Used $at without \".set noat\"")); | |
12902 | else | |
12903 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12904 | regno, mips_opts.at); | |
12905 | } | |
12906 | if (!ok) | |
12907 | { | |
12908 | if (c == 'c') | |
12909 | { | |
12910 | gas_assert (args[1] == ','); | |
12911 | regno = lastregno; | |
12912 | ++args; | |
12913 | } | |
12914 | else if (c == 't') | |
12915 | { | |
12916 | gas_assert (args[1] == ','); | |
12917 | ++args; | |
12918 | continue; /* Nothing to do. */ | |
12919 | } | |
12920 | else | |
12921 | break; | |
12922 | } | |
12923 | ||
12924 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12925 | { | |
12926 | if (regno == lastregno) | |
12927 | { | |
12928 | insn_error | |
12929 | = _("Source and destination must be different"); | |
12930 | continue; | |
12931 | } | |
12932 | if (regno == 31 && lastregno == 0xffffffff) | |
12933 | { | |
12934 | insn_error | |
12935 | = _("A destination register must be supplied"); | |
12936 | continue; | |
12937 | } | |
12938 | } | |
12939 | ||
12940 | if (*s == ' ') | |
12941 | ++s; | |
12942 | if (args[1] != *s) | |
12943 | { | |
12944 | if (c == 'e') | |
12945 | { | |
12946 | gas_assert (args[1] == ','); | |
12947 | regno = lastregno; | |
12948 | s = s_reset; | |
12949 | ++args; | |
12950 | } | |
12951 | else if (c == 't') | |
12952 | { | |
12953 | gas_assert (args[1] == ','); | |
12954 | s = s_reset; | |
12955 | ++args; | |
12956 | continue; /* Nothing to do. */ | |
12957 | } | |
12958 | } | |
12959 | ||
12960 | /* Make sure regno is the same as lastregno. */ | |
12961 | if (c == 't' && regno != lastregno) | |
12962 | break; | |
12963 | ||
12964 | /* Make sure regno is the same as destregno. */ | |
12965 | if (c == 'x' && regno != destregno) | |
12966 | break; | |
12967 | ||
12968 | /* We need to save regno, before regno maps to the | |
12969 | microMIPS register encoding. */ | |
12970 | lastregno = regno; | |
12971 | ||
12972 | if (c == 'f') | |
12973 | destregno = regno; | |
12974 | ||
12975 | switch (c) | |
12976 | { | |
12977 | case 'a': | |
12978 | if (regno != GP) | |
12979 | regno = ILLEGAL_REG; | |
12980 | break; | |
12981 | ||
12982 | case 'b': | |
12983 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12984 | break; | |
12985 | ||
12986 | case 'c': | |
12987 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12988 | break; | |
12989 | ||
12990 | case 'd': | |
12991 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12992 | break; | |
12993 | ||
12994 | case 'e': | |
12995 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12996 | break; | |
12997 | ||
12998 | case 'f': | |
12999 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13000 | break; | |
13001 | ||
13002 | case 'g': | |
13003 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13004 | break; | |
13005 | ||
13006 | case 'h': | |
13007 | regno = mips32_to_micromips_reg_h_map[regno]; | |
13008 | break; | |
13009 | ||
13010 | case 'i': | |
13011 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
13012 | { | |
13013 | case 4: | |
13014 | if (regno == 21) | |
13015 | regno = 3; | |
13016 | else if (regno == 22) | |
13017 | regno = 4; | |
13018 | else if (regno == 5) | |
13019 | regno = 5; | |
13020 | else if (regno == 6) | |
13021 | regno = 6; | |
13022 | else if (regno == 7) | |
13023 | regno = 7; | |
13024 | else | |
13025 | regno = ILLEGAL_REG; | |
13026 | break; | |
13027 | ||
13028 | case 5: | |
13029 | if (regno == 6) | |
13030 | regno = 0; | |
13031 | else if (regno == 7) | |
13032 | regno = 1; | |
13033 | else | |
13034 | regno = ILLEGAL_REG; | |
13035 | break; | |
13036 | ||
13037 | case 6: | |
13038 | if (regno == 7) | |
13039 | regno = 2; | |
13040 | else | |
13041 | regno = ILLEGAL_REG; | |
13042 | break; | |
13043 | ||
13044 | default: | |
13045 | regno = ILLEGAL_REG; | |
13046 | break; | |
13047 | } | |
13048 | break; | |
13049 | ||
13050 | case 'l': | |
13051 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13052 | break; | |
13053 | ||
13054 | case 'm': | |
13055 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13056 | break; | |
13057 | ||
13058 | case 'n': | |
13059 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13060 | break; | |
13061 | ||
13062 | case 'q': | |
13063 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13064 | break; | |
13065 | ||
13066 | case 's': | |
13067 | if (regno != SP) | |
13068 | regno = ILLEGAL_REG; | |
13069 | break; | |
13070 | ||
13071 | case 'y': | |
13072 | if (regno != 31) | |
13073 | regno = ILLEGAL_REG; | |
13074 | break; | |
13075 | ||
13076 | case 'z': | |
13077 | if (regno != ZERO) | |
13078 | regno = ILLEGAL_REG; | |
13079 | break; | |
13080 | ||
13081 | case 'j': /* Do nothing. */ | |
13082 | case 'p': | |
13083 | case 't': | |
13084 | case 'x': | |
13085 | break; | |
13086 | ||
13087 | default: | |
b37df7c4 | 13088 | abort (); |
df58fc94 RS |
13089 | } |
13090 | ||
13091 | if (regno == ILLEGAL_REG) | |
13092 | break; | |
13093 | ||
13094 | switch (c) | |
13095 | { | |
13096 | case 'b': | |
13097 | INSERT_OPERAND (1, MB, *ip, regno); | |
13098 | break; | |
13099 | ||
13100 | case 'c': | |
13101 | INSERT_OPERAND (1, MC, *ip, regno); | |
13102 | break; | |
13103 | ||
13104 | case 'd': | |
13105 | INSERT_OPERAND (1, MD, *ip, regno); | |
13106 | break; | |
13107 | ||
13108 | case 'e': | |
13109 | INSERT_OPERAND (1, ME, *ip, regno); | |
13110 | break; | |
13111 | ||
13112 | case 'f': | |
13113 | INSERT_OPERAND (1, MF, *ip, regno); | |
13114 | break; | |
13115 | ||
13116 | case 'g': | |
13117 | INSERT_OPERAND (1, MG, *ip, regno); | |
13118 | break; | |
13119 | ||
13120 | case 'h': | |
13121 | INSERT_OPERAND (1, MH, *ip, regno); | |
13122 | break; | |
13123 | ||
13124 | case 'i': | |
13125 | INSERT_OPERAND (1, MI, *ip, regno); | |
13126 | break; | |
13127 | ||
13128 | case 'j': | |
13129 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13130 | break; | |
13131 | ||
13132 | case 'l': | |
13133 | INSERT_OPERAND (1, ML, *ip, regno); | |
13134 | break; | |
13135 | ||
13136 | case 'm': | |
13137 | INSERT_OPERAND (1, MM, *ip, regno); | |
13138 | break; | |
13139 | ||
13140 | case 'n': | |
13141 | INSERT_OPERAND (1, MN, *ip, regno); | |
13142 | break; | |
13143 | ||
13144 | case 'p': | |
13145 | INSERT_OPERAND (1, MP, *ip, regno); | |
13146 | break; | |
13147 | ||
13148 | case 'q': | |
13149 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13150 | break; | |
13151 | ||
13152 | case 'a': /* Do nothing. */ | |
13153 | case 's': /* Do nothing. */ | |
13154 | case 't': /* Do nothing. */ | |
13155 | case 'x': /* Do nothing. */ | |
13156 | case 'y': /* Do nothing. */ | |
13157 | case 'z': /* Do nothing. */ | |
13158 | break; | |
13159 | ||
13160 | default: | |
b37df7c4 | 13161 | abort (); |
df58fc94 RS |
13162 | } |
13163 | continue; | |
13164 | ||
13165 | case 'A': | |
13166 | { | |
13167 | bfd_reloc_code_real_type r[3]; | |
13168 | expressionS ep; | |
13169 | int imm; | |
13170 | ||
13171 | /* Check whether there is only a single bracketed | |
13172 | expression left. If so, it must be the base register | |
13173 | and the constant must be zero. */ | |
13174 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13175 | { | |
13176 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13177 | continue; | |
13178 | } | |
13179 | ||
13180 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13181 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13182 | break; | |
13183 | ||
13184 | imm = ep.X_add_number >> 2; | |
13185 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13186 | } | |
13187 | s = expr_end; | |
13188 | continue; | |
13189 | ||
13190 | case 'B': | |
13191 | { | |
13192 | bfd_reloc_code_real_type r[3]; | |
13193 | expressionS ep; | |
13194 | int imm; | |
13195 | ||
13196 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13197 | || ep.X_op != O_constant) | |
13198 | break; | |
13199 | ||
13200 | for (imm = 0; imm < 8; imm++) | |
13201 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13202 | break; | |
13203 | if (imm >= 8) | |
13204 | break; | |
13205 | ||
13206 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13207 | } | |
13208 | s = expr_end; | |
13209 | continue; | |
13210 | ||
13211 | case 'C': | |
13212 | { | |
13213 | bfd_reloc_code_real_type r[3]; | |
13214 | expressionS ep; | |
13215 | int imm; | |
13216 | ||
13217 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13218 | || ep.X_op != O_constant) | |
13219 | break; | |
13220 | ||
13221 | for (imm = 0; imm < 16; imm++) | |
13222 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13223 | break; | |
13224 | if (imm >= 16) | |
13225 | break; | |
13226 | ||
13227 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13228 | } | |
13229 | s = expr_end; | |
13230 | continue; | |
13231 | ||
13232 | case 'D': /* pc relative offset */ | |
13233 | case 'E': /* pc relative offset */ | |
13234 | my_getExpression (&offset_expr, s); | |
13235 | if (offset_expr.X_op == O_register) | |
13236 | break; | |
13237 | ||
40209cad MR |
13238 | if (!forced_insn_length) |
13239 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13240 | else if (c == 'D') | |
13241 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13242 | else | |
13243 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13244 | s = expr_end; |
13245 | continue; | |
13246 | ||
13247 | case 'F': | |
13248 | { | |
13249 | bfd_reloc_code_real_type r[3]; | |
13250 | expressionS ep; | |
13251 | int imm; | |
13252 | ||
13253 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13254 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13255 | break; | |
13256 | ||
13257 | imm = ep.X_add_number; | |
13258 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13259 | } | |
13260 | s = expr_end; | |
13261 | continue; | |
13262 | ||
13263 | case 'G': | |
13264 | { | |
13265 | bfd_reloc_code_real_type r[3]; | |
13266 | expressionS ep; | |
13267 | int imm; | |
13268 | ||
13269 | /* Check whether there is only a single bracketed | |
13270 | expression left. If so, it must be the base register | |
13271 | and the constant must be zero. */ | |
13272 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13273 | { | |
13274 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13275 | continue; | |
13276 | } | |
13277 | ||
13278 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13279 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13280 | break; | |
13281 | ||
13282 | imm = ep.X_add_number & 15; | |
13283 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13284 | } | |
13285 | s = expr_end; | |
13286 | continue; | |
13287 | ||
13288 | case 'H': | |
13289 | { | |
13290 | bfd_reloc_code_real_type r[3]; | |
13291 | expressionS ep; | |
13292 | int imm; | |
13293 | ||
13294 | /* Check whether there is only a single bracketed | |
13295 | expression left. If so, it must be the base register | |
13296 | and the constant must be zero. */ | |
13297 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13298 | { | |
13299 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13300 | continue; | |
13301 | } | |
13302 | ||
13303 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13304 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13305 | break; | |
13306 | ||
13307 | imm = ep.X_add_number >> 1; | |
13308 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13309 | } | |
13310 | s = expr_end; | |
13311 | continue; | |
13312 | ||
13313 | case 'I': | |
13314 | { | |
13315 | bfd_reloc_code_real_type r[3]; | |
13316 | expressionS ep; | |
13317 | int imm; | |
13318 | ||
13319 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13320 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13321 | break; | |
13322 | ||
13323 | imm = ep.X_add_number & 127; | |
13324 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13325 | } | |
13326 | s = expr_end; | |
13327 | continue; | |
13328 | ||
13329 | case 'J': | |
13330 | { | |
13331 | bfd_reloc_code_real_type r[3]; | |
13332 | expressionS ep; | |
13333 | int imm; | |
13334 | ||
13335 | /* Check whether there is only a single bracketed | |
13336 | expression left. If so, it must be the base register | |
13337 | and the constant must be zero. */ | |
13338 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13339 | { | |
13340 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13341 | continue; | |
13342 | } | |
13343 | ||
13344 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13345 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13346 | break; | |
13347 | ||
13348 | imm = ep.X_add_number >> 2; | |
13349 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13350 | } | |
13351 | s = expr_end; | |
13352 | continue; | |
13353 | ||
13354 | case 'L': | |
13355 | { | |
13356 | bfd_reloc_code_real_type r[3]; | |
13357 | expressionS ep; | |
13358 | int imm; | |
13359 | ||
13360 | /* Check whether there is only a single bracketed | |
13361 | expression left. If so, it must be the base register | |
13362 | and the constant must be zero. */ | |
13363 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13364 | { | |
13365 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13366 | continue; | |
13367 | } | |
13368 | ||
13369 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13370 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13371 | break; | |
13372 | ||
13373 | imm = ep.X_add_number; | |
13374 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13375 | } | |
13376 | s = expr_end; | |
13377 | continue; | |
13378 | ||
13379 | case 'M': | |
13380 | { | |
13381 | bfd_reloc_code_real_type r[3]; | |
13382 | expressionS ep; | |
13383 | int imm; | |
13384 | ||
13385 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13386 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13387 | break; | |
13388 | ||
13389 | imm = ep.X_add_number & 7; | |
13390 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13391 | } | |
13392 | s = expr_end; | |
13393 | continue; | |
13394 | ||
13395 | case 'N': /* Register list for lwm and swm. */ | |
13396 | { | |
13397 | /* A comma-separated list of registers and/or | |
13398 | dash-separated contiguous ranges including | |
13399 | both ra and a set of one or more registers | |
13400 | starting at s0 up to s3 which have to be | |
13401 | consecutive, e.g.: | |
13402 | ||
13403 | s0, ra | |
13404 | s0, s1, ra, s2, s3 | |
13405 | s0-s2, ra | |
13406 | ||
13407 | and any permutations of these. */ | |
13408 | unsigned int reglist; | |
13409 | int imm; | |
13410 | ||
13411 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13412 | break; | |
13413 | ||
13414 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13415 | break; | |
13416 | ||
13417 | reglist = (reglist >> 17) & 7; | |
13418 | reglist += 1; | |
13419 | if ((reglist & -reglist) != reglist) | |
13420 | break; | |
252b5132 | 13421 | |
df58fc94 RS |
13422 | imm = ffs (reglist) - 1; |
13423 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13424 | } | |
13425 | continue; | |
252b5132 | 13426 | |
df58fc94 RS |
13427 | case 'O': /* sdbbp 4-bit code. */ |
13428 | { | |
13429 | bfd_reloc_code_real_type r[3]; | |
13430 | expressionS ep; | |
13431 | int imm; | |
13432 | ||
13433 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13434 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13435 | break; | |
13436 | ||
13437 | imm = ep.X_add_number; | |
13438 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13439 | } |
df58fc94 RS |
13440 | s = expr_end; |
13441 | continue; | |
252b5132 | 13442 | |
df58fc94 RS |
13443 | case 'P': |
13444 | { | |
13445 | bfd_reloc_code_real_type r[3]; | |
13446 | expressionS ep; | |
13447 | int imm; | |
5e0116d5 | 13448 | |
df58fc94 RS |
13449 | if (my_getSmallExpression (&ep, r, s) > 0 |
13450 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13451 | break; | |
5e0116d5 | 13452 | |
df58fc94 RS |
13453 | imm = ep.X_add_number >> 2; |
13454 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13455 | } | |
13456 | s = expr_end; | |
13457 | continue; | |
5e0116d5 | 13458 | |
df58fc94 RS |
13459 | case 'Q': |
13460 | { | |
13461 | bfd_reloc_code_real_type r[3]; | |
13462 | expressionS ep; | |
13463 | int imm; | |
5e0116d5 | 13464 | |
df58fc94 RS |
13465 | if (my_getSmallExpression (&ep, r, s) > 0 |
13466 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13467 | break; | |
252b5132 | 13468 | |
df58fc94 RS |
13469 | imm = ep.X_add_number >> 2; |
13470 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13471 | } | |
13472 | s = expr_end; | |
13473 | continue; | |
4614d845 | 13474 | |
df58fc94 RS |
13475 | case 'U': |
13476 | { | |
13477 | bfd_reloc_code_real_type r[3]; | |
13478 | expressionS ep; | |
13479 | int imm; | |
13480 | ||
13481 | /* Check whether there is only a single bracketed | |
13482 | expression left. If so, it must be the base register | |
13483 | and the constant must be zero. */ | |
13484 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13485 | { | |
13486 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13487 | continue; | |
13488 | } | |
13489 | ||
13490 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13491 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13492 | break; | |
13493 | ||
13494 | imm = ep.X_add_number >> 2; | |
13495 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13496 | } | |
13497 | s = expr_end; | |
5e0116d5 | 13498 | continue; |
252b5132 | 13499 | |
df58fc94 RS |
13500 | case 'W': |
13501 | { | |
13502 | bfd_reloc_code_real_type r[3]; | |
13503 | expressionS ep; | |
13504 | int imm; | |
252b5132 | 13505 | |
df58fc94 RS |
13506 | if (my_getSmallExpression (&ep, r, s) > 0 |
13507 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13508 | break; | |
252b5132 | 13509 | |
df58fc94 RS |
13510 | imm = ep.X_add_number >> 2; |
13511 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13512 | } | |
13513 | s = expr_end; | |
13514 | continue; | |
252b5132 | 13515 | |
df58fc94 RS |
13516 | case 'X': |
13517 | { | |
13518 | bfd_reloc_code_real_type r[3]; | |
13519 | expressionS ep; | |
13520 | int imm; | |
252b5132 | 13521 | |
df58fc94 RS |
13522 | if (my_getSmallExpression (&ep, r, s) > 0 |
13523 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13524 | break; | |
252b5132 | 13525 | |
df58fc94 RS |
13526 | imm = ep.X_add_number; |
13527 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13528 | } | |
13529 | s = expr_end; | |
13530 | continue; | |
252b5132 | 13531 | |
df58fc94 RS |
13532 | case 'Y': |
13533 | { | |
13534 | bfd_reloc_code_real_type r[3]; | |
13535 | expressionS ep; | |
13536 | int imm; | |
156c2f8b | 13537 | |
df58fc94 RS |
13538 | if (my_getSmallExpression (&ep, r, s) > 0 |
13539 | || expr_const_in_range (&ep, -2, 2, 2) | |
13540 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13541 | break; | |
156c2f8b | 13542 | |
df58fc94 RS |
13543 | imm = ep.X_add_number >> 2; |
13544 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13545 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13546 | } | |
13547 | s = expr_end; | |
13548 | continue; | |
60b63b72 | 13549 | |
df58fc94 RS |
13550 | case 'Z': |
13551 | { | |
13552 | bfd_reloc_code_real_type r[3]; | |
13553 | expressionS ep; | |
13554 | ||
13555 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13556 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13557 | break; | |
13558 | } | |
13559 | s = expr_end; | |
13560 | continue; | |
13561 | ||
13562 | default: | |
13563 | as_bad (_("Internal error: bad microMIPS opcode " | |
13564 | "(unknown extension operand type `m%c'): %s %s"), | |
13565 | *args, insn->name, insn->args); | |
13566 | /* Further processing is fruitless. */ | |
13567 | return; | |
60b63b72 | 13568 | } |
df58fc94 | 13569 | break; |
60b63b72 | 13570 | |
df58fc94 RS |
13571 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13572 | gas_assert (mips_opts.micromips); | |
13573 | { | |
13574 | /* A comma-separated list of registers and/or | |
13575 | dash-separated contiguous ranges including | |
13576 | at least one of ra and a set of one or more | |
13577 | registers starting at s0 up to s7 and then | |
13578 | s8 which have to be consecutive, e.g.: | |
13579 | ||
13580 | ra | |
13581 | s0 | |
13582 | ra, s0, s1, s2 | |
13583 | s0-s8 | |
13584 | s0-s5, ra | |
13585 | ||
13586 | and any permutations of these. */ | |
13587 | unsigned int reglist; | |
13588 | int imm; | |
13589 | int ra; | |
13590 | ||
13591 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13592 | break; | |
13593 | ||
13594 | if ((reglist & 0x3f00ffff) != 0) | |
13595 | break; | |
13596 | ||
13597 | ra = (reglist >> 27) & 0x10; | |
13598 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13599 | reglist += 1; | |
13600 | if ((reglist & -reglist) != reglist) | |
13601 | break; | |
13602 | ||
13603 | imm = (ffs (reglist) - 1) | ra; | |
13604 | INSERT_OPERAND (1, RT, *ip, imm); | |
13605 | imm_expr.X_op = O_absent; | |
13606 | } | |
60b63b72 RS |
13607 | continue; |
13608 | ||
df58fc94 RS |
13609 | case '|': /* 4-bit trap code. */ |
13610 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13611 | my_getExpression (&imm_expr, s); |
13612 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13613 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13614 | > MICROMIPSOP_MASK_TRAP) |
13615 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13616 | (unsigned long) imm_expr.X_add_number, | |
13617 | ip->insn_mo->name); | |
13618 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13619 | imm_expr.X_op = O_absent; |
13620 | s = expr_end; | |
13621 | continue; | |
13622 | ||
252b5132 | 13623 | default: |
f71d0d44 | 13624 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13625 | abort (); |
252b5132 RH |
13626 | } |
13627 | break; | |
13628 | } | |
13629 | /* Args don't match. */ | |
df58fc94 RS |
13630 | s = argsStart; |
13631 | insn_error = _("Illegal operands"); | |
13632 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13633 | { |
13634 | ++insn; | |
252b5132 RH |
13635 | continue; |
13636 | } | |
df58fc94 RS |
13637 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13638 | { | |
13639 | gas_assert (firstinsn); | |
13640 | need_delay_slot_ok = FALSE; | |
13641 | past = insn + 1; | |
13642 | insn = firstinsn; | |
13643 | continue; | |
13644 | } | |
252b5132 RH |
13645 | return; |
13646 | } | |
13647 | } | |
13648 | ||
0499d65b TS |
13649 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13650 | ||
252b5132 RH |
13651 | /* This routine assembles an instruction into its binary format when |
13652 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13653 | global variables imm_reloc or offset_reloc to the type of relocation |
13654 | to do if one of the operands is an address expression. It also sets | |
13655 | forced_insn_length to the resulting instruction size in bytes if the | |
13656 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13657 | |
13658 | static void | |
17a2f251 | 13659 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13660 | { |
13661 | char *s; | |
13662 | const char *args; | |
13663 | struct mips_opcode *insn; | |
13664 | char *argsstart; | |
13665 | unsigned int regno; | |
13666 | unsigned int lastregno = 0; | |
13667 | char *s_reset; | |
d6f16593 | 13668 | size_t i; |
252b5132 RH |
13669 | |
13670 | insn_error = NULL; | |
13671 | ||
df58fc94 | 13672 | forced_insn_length = 0; |
252b5132 | 13673 | |
3882b010 | 13674 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13675 | ; |
13676 | switch (*s) | |
13677 | { | |
13678 | case '\0': | |
13679 | break; | |
13680 | ||
13681 | case ' ': | |
13682 | *s++ = '\0'; | |
13683 | break; | |
13684 | ||
13685 | case '.': | |
13686 | if (s[1] == 't' && s[2] == ' ') | |
13687 | { | |
13688 | *s = '\0'; | |
df58fc94 | 13689 | forced_insn_length = 2; |
252b5132 RH |
13690 | s += 3; |
13691 | break; | |
13692 | } | |
13693 | else if (s[1] == 'e' && s[2] == ' ') | |
13694 | { | |
13695 | *s = '\0'; | |
df58fc94 | 13696 | forced_insn_length = 4; |
252b5132 RH |
13697 | s += 3; |
13698 | break; | |
13699 | } | |
13700 | /* Fall through. */ | |
13701 | default: | |
13702 | insn_error = _("unknown opcode"); | |
13703 | return; | |
13704 | } | |
13705 | ||
df58fc94 RS |
13706 | if (mips_opts.noautoextend && !forced_insn_length) |
13707 | forced_insn_length = 2; | |
252b5132 RH |
13708 | |
13709 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13710 | { | |
13711 | insn_error = _("unrecognized opcode"); | |
13712 | return; | |
13713 | } | |
13714 | ||
13715 | argsstart = s; | |
13716 | for (;;) | |
13717 | { | |
9b3f89ee TS |
13718 | bfd_boolean ok; |
13719 | ||
9c2799c2 | 13720 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13721 | |
037b32b9 | 13722 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13723 | if (! ok) |
13724 | { | |
13725 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13726 | && strcmp (insn->name, insn[1].name) == 0) | |
13727 | { | |
13728 | ++insn; | |
13729 | continue; | |
13730 | } | |
13731 | else | |
13732 | { | |
13733 | if (!insn_error) | |
13734 | { | |
13735 | static char buf[100]; | |
13736 | sprintf (buf, | |
7bd942df | 13737 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13738 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13739 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13740 | insn_error = buf; | |
13741 | } | |
13742 | return; | |
13743 | } | |
13744 | } | |
13745 | ||
1e915849 | 13746 | create_insn (ip, insn); |
252b5132 | 13747 | imm_expr.X_op = O_absent; |
f6688943 TS |
13748 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13749 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13750 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13751 | imm2_expr.X_op = O_absent; |
252b5132 | 13752 | offset_expr.X_op = O_absent; |
f6688943 TS |
13753 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13754 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13755 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13756 | for (args = insn->args; 1; ++args) |
13757 | { | |
13758 | int c; | |
13759 | ||
13760 | if (*s == ' ') | |
13761 | ++s; | |
13762 | ||
13763 | /* In this switch statement we call break if we did not find | |
13764 | a match, continue if we did find a match, or return if we | |
13765 | are done. */ | |
13766 | ||
13767 | c = *args; | |
13768 | switch (c) | |
13769 | { | |
13770 | case '\0': | |
13771 | if (*s == '\0') | |
13772 | { | |
b886a2ab RS |
13773 | offsetT value; |
13774 | ||
252b5132 RH |
13775 | /* Stuff the immediate value in now, if we can. */ |
13776 | if (imm_expr.X_op == O_constant | |
f6688943 | 13777 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13778 | && insn->pinfo != INSN_MACRO |
13779 | && calculate_reloc (*offset_reloc, | |
13780 | imm_expr.X_add_number, &value)) | |
252b5132 | 13781 | { |
c4e7957c | 13782 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13783 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13784 | &ip->insn_opcode); |
252b5132 | 13785 | imm_expr.X_op = O_absent; |
f6688943 | 13786 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13787 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13788 | } |
13789 | ||
13790 | return; | |
13791 | } | |
13792 | break; | |
13793 | ||
13794 | case ',': | |
13795 | if (*s++ == c) | |
13796 | continue; | |
13797 | s--; | |
13798 | switch (*++args) | |
13799 | { | |
13800 | case 'v': | |
bf12938e | 13801 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13802 | continue; |
13803 | case 'w': | |
bf12938e | 13804 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13805 | continue; |
13806 | } | |
13807 | break; | |
13808 | ||
13809 | case '(': | |
13810 | case ')': | |
13811 | if (*s++ == c) | |
13812 | continue; | |
13813 | break; | |
13814 | ||
13815 | case 'v': | |
13816 | case 'w': | |
13817 | if (s[0] != '$') | |
13818 | { | |
13819 | if (c == 'v') | |
bf12938e | 13820 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13821 | else |
bf12938e | 13822 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13823 | ++args; |
13824 | continue; | |
13825 | } | |
13826 | /* Fall through. */ | |
13827 | case 'x': | |
13828 | case 'y': | |
13829 | case 'z': | |
13830 | case 'Z': | |
13831 | case '0': | |
13832 | case 'S': | |
13833 | case 'R': | |
13834 | case 'X': | |
13835 | case 'Y': | |
707bfff6 TS |
13836 | s_reset = s; |
13837 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13838 | { |
707bfff6 | 13839 | if (c == 'v' || c == 'w') |
85b51719 | 13840 | { |
707bfff6 | 13841 | if (c == 'v') |
a9e24354 | 13842 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13843 | else |
a9e24354 | 13844 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13845 | ++args; |
13846 | continue; | |
85b51719 | 13847 | } |
707bfff6 | 13848 | break; |
252b5132 RH |
13849 | } |
13850 | ||
13851 | if (*s == ' ') | |
13852 | ++s; | |
13853 | if (args[1] != *s) | |
13854 | { | |
13855 | if (c == 'v' || c == 'w') | |
13856 | { | |
13857 | regno = mips16_to_32_reg_map[lastregno]; | |
13858 | s = s_reset; | |
f9419b05 | 13859 | ++args; |
252b5132 RH |
13860 | } |
13861 | } | |
13862 | ||
13863 | switch (c) | |
13864 | { | |
13865 | case 'x': | |
13866 | case 'y': | |
13867 | case 'z': | |
13868 | case 'v': | |
13869 | case 'w': | |
13870 | case 'Z': | |
13871 | regno = mips32_to_16_reg_map[regno]; | |
13872 | break; | |
13873 | ||
13874 | case '0': | |
13875 | if (regno != 0) | |
13876 | regno = ILLEGAL_REG; | |
13877 | break; | |
13878 | ||
13879 | case 'S': | |
13880 | if (regno != SP) | |
13881 | regno = ILLEGAL_REG; | |
13882 | break; | |
13883 | ||
13884 | case 'R': | |
13885 | if (regno != RA) | |
13886 | regno = ILLEGAL_REG; | |
13887 | break; | |
13888 | ||
13889 | case 'X': | |
13890 | case 'Y': | |
741fe287 MR |
13891 | if (regno == AT && mips_opts.at) |
13892 | { | |
13893 | if (mips_opts.at == ATREG) | |
13894 | as_warn (_("used $at without \".set noat\"")); | |
13895 | else | |
13896 | as_warn (_("used $%u with \".set at=$%u\""), | |
13897 | regno, mips_opts.at); | |
13898 | } | |
252b5132 RH |
13899 | break; |
13900 | ||
13901 | default: | |
b37df7c4 | 13902 | abort (); |
252b5132 RH |
13903 | } |
13904 | ||
13905 | if (regno == ILLEGAL_REG) | |
13906 | break; | |
13907 | ||
13908 | switch (c) | |
13909 | { | |
13910 | case 'x': | |
13911 | case 'v': | |
bf12938e | 13912 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13913 | break; |
13914 | case 'y': | |
13915 | case 'w': | |
bf12938e | 13916 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13917 | break; |
13918 | case 'z': | |
bf12938e | 13919 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13920 | break; |
13921 | case 'Z': | |
bf12938e | 13922 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13923 | case '0': |
13924 | case 'S': | |
13925 | case 'R': | |
13926 | break; | |
13927 | case 'X': | |
bf12938e | 13928 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13929 | break; |
13930 | case 'Y': | |
13931 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13932 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13933 | break; |
13934 | default: | |
b37df7c4 | 13935 | abort (); |
252b5132 RH |
13936 | } |
13937 | ||
13938 | lastregno = regno; | |
13939 | continue; | |
13940 | ||
13941 | case 'P': | |
13942 | if (strncmp (s, "$pc", 3) == 0) | |
13943 | { | |
13944 | s += 3; | |
13945 | continue; | |
13946 | } | |
13947 | break; | |
13948 | ||
252b5132 RH |
13949 | case '5': |
13950 | case 'H': | |
13951 | case 'W': | |
13952 | case 'D': | |
13953 | case 'j': | |
252b5132 RH |
13954 | case 'V': |
13955 | case 'C': | |
13956 | case 'U': | |
13957 | case 'k': | |
13958 | case 'K': | |
d6f16593 MR |
13959 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13960 | if (i > 0) | |
252b5132 | 13961 | { |
d6f16593 | 13962 | if (imm_expr.X_op != O_constant) |
252b5132 | 13963 | { |
df58fc94 | 13964 | forced_insn_length = 4; |
5c04167a | 13965 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13966 | } |
d6f16593 MR |
13967 | else |
13968 | { | |
13969 | /* We need to relax this instruction. */ | |
13970 | *offset_reloc = *imm_reloc; | |
13971 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13972 | } | |
13973 | s = expr_end; | |
13974 | continue; | |
252b5132 | 13975 | } |
d6f16593 MR |
13976 | *imm_reloc = BFD_RELOC_UNUSED; |
13977 | /* Fall through. */ | |
13978 | case '<': | |
13979 | case '>': | |
13980 | case '[': | |
13981 | case ']': | |
13982 | case '4': | |
13983 | case '8': | |
13984 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13985 | if (imm_expr.X_op == O_register) |
13986 | { | |
13987 | /* What we thought was an expression turned out to | |
13988 | be a register. */ | |
13989 | ||
13990 | if (s[0] == '(' && args[1] == '(') | |
13991 | { | |
13992 | /* It looks like the expression was omitted | |
13993 | before a register indirection, which means | |
13994 | that the expression is implicitly zero. We | |
13995 | still set up imm_expr, so that we handle | |
13996 | explicit extensions correctly. */ | |
13997 | imm_expr.X_op = O_constant; | |
13998 | imm_expr.X_add_number = 0; | |
f6688943 | 13999 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14000 | continue; |
14001 | } | |
14002 | ||
14003 | break; | |
14004 | } | |
14005 | ||
14006 | /* We need to relax this instruction. */ | |
f6688943 | 14007 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14008 | s = expr_end; |
14009 | continue; | |
14010 | ||
14011 | case 'p': | |
14012 | case 'q': | |
14013 | case 'A': | |
14014 | case 'B': | |
14015 | case 'E': | |
14016 | /* We use offset_reloc rather than imm_reloc for the PC | |
14017 | relative operands. This lets macros with both | |
14018 | immediate and address operands work correctly. */ | |
14019 | my_getExpression (&offset_expr, s); | |
14020 | ||
14021 | if (offset_expr.X_op == O_register) | |
14022 | break; | |
14023 | ||
14024 | /* We need to relax this instruction. */ | |
f6688943 | 14025 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14026 | s = expr_end; |
14027 | continue; | |
14028 | ||
14029 | case '6': /* break code */ | |
14030 | my_getExpression (&imm_expr, s); | |
14031 | check_absolute_expr (ip, &imm_expr); | |
14032 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14033 | as_warn (_("Invalid value for `%s' (%lu)"), |
14034 | ip->insn_mo->name, | |
14035 | (unsigned long) imm_expr.X_add_number); | |
14036 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14037 | imm_expr.X_op = O_absent; |
14038 | s = expr_end; | |
14039 | continue; | |
14040 | ||
14041 | case 'a': /* 26 bit address */ | |
14042 | my_getExpression (&offset_expr, s); | |
14043 | s = expr_end; | |
f6688943 | 14044 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14045 | ip->insn_opcode <<= 16; |
14046 | continue; | |
14047 | ||
14048 | case 'l': /* register list for entry macro */ | |
14049 | case 'L': /* register list for exit macro */ | |
14050 | { | |
14051 | int mask; | |
14052 | ||
14053 | if (c == 'l') | |
14054 | mask = 0; | |
14055 | else | |
14056 | mask = 7 << 3; | |
14057 | while (*s != '\0') | |
14058 | { | |
707bfff6 | 14059 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14060 | |
14061 | while (*s == ' ' || *s == ',') | |
14062 | ++s; | |
707bfff6 | 14063 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14064 | freg = 0; |
707bfff6 TS |
14065 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14066 | freg = 1; | |
252b5132 RH |
14067 | else |
14068 | { | |
707bfff6 TS |
14069 | as_bad (_("can't parse register list")); |
14070 | break; | |
252b5132 RH |
14071 | } |
14072 | if (*s == ' ') | |
14073 | ++s; | |
14074 | if (*s != '-') | |
14075 | reg2 = reg1; | |
14076 | else | |
14077 | { | |
14078 | ++s; | |
707bfff6 TS |
14079 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14080 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14081 | { |
707bfff6 TS |
14082 | as_bad (_("invalid register list")); |
14083 | break; | |
252b5132 RH |
14084 | } |
14085 | } | |
14086 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14087 | { | |
14088 | mask &= ~ (7 << 3); | |
14089 | mask |= 5 << 3; | |
14090 | } | |
14091 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14092 | { | |
14093 | mask &= ~ (7 << 3); | |
14094 | mask |= 6 << 3; | |
14095 | } | |
14096 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14097 | mask |= (reg2 - 3) << 3; | |
14098 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14099 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14100 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14101 | mask |= 1; |
14102 | else | |
14103 | { | |
14104 | as_bad (_("invalid register list")); | |
14105 | break; | |
14106 | } | |
14107 | } | |
14108 | /* The mask is filled in in the opcode table for the | |
14109 | benefit of the disassembler. We remove it before | |
14110 | applying the actual mask. */ | |
14111 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14112 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14113 | } | |
14114 | continue; | |
14115 | ||
0499d65b TS |
14116 | case 'm': /* Register list for save insn. */ |
14117 | case 'M': /* Register list for restore insn. */ | |
14118 | { | |
5c04167a | 14119 | int opcode = ip->insn_opcode; |
0499d65b | 14120 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14121 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14122 | |
14123 | while (*s != '\0') | |
14124 | { | |
14125 | unsigned int reg1, reg2; | |
14126 | ||
14127 | SKIP_SPACE_TABS (s); | |
14128 | while (*s == ',') | |
14129 | ++s; | |
14130 | SKIP_SPACE_TABS (s); | |
14131 | ||
14132 | my_getExpression (&imm_expr, s); | |
14133 | if (imm_expr.X_op == O_constant) | |
14134 | { | |
14135 | /* Handle the frame size. */ | |
14136 | if (seen_framesz) | |
14137 | { | |
14138 | as_bad (_("more than one frame size in list")); | |
14139 | break; | |
14140 | } | |
14141 | seen_framesz = 1; | |
14142 | framesz = imm_expr.X_add_number; | |
14143 | imm_expr.X_op = O_absent; | |
14144 | s = expr_end; | |
14145 | continue; | |
14146 | } | |
14147 | ||
707bfff6 | 14148 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14149 | { |
14150 | as_bad (_("can't parse register list")); | |
14151 | break; | |
14152 | } | |
0499d65b | 14153 | |
707bfff6 TS |
14154 | while (*s == ' ') |
14155 | ++s; | |
14156 | ||
0499d65b TS |
14157 | if (*s != '-') |
14158 | reg2 = reg1; | |
14159 | else | |
14160 | { | |
14161 | ++s; | |
707bfff6 TS |
14162 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14163 | || reg2 < reg1) | |
0499d65b TS |
14164 | { |
14165 | as_bad (_("can't parse register list")); | |
14166 | break; | |
14167 | } | |
0499d65b TS |
14168 | } |
14169 | ||
14170 | while (reg1 <= reg2) | |
14171 | { | |
14172 | if (reg1 >= 4 && reg1 <= 7) | |
14173 | { | |
3a93f742 | 14174 | if (!seen_framesz) |
0499d65b | 14175 | /* args $a0-$a3 */ |
91d6fa6a | 14176 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14177 | else |
14178 | /* statics $a0-$a3 */ | |
14179 | statics |= 1 << (reg1 - 4); | |
14180 | } | |
14181 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14182 | { | |
14183 | /* $s0-$s8 */ | |
14184 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14185 | } | |
14186 | else if (reg1 == 31) | |
14187 | { | |
14188 | /* Add $ra to insn. */ | |
14189 | opcode |= 0x40; | |
14190 | } | |
14191 | else | |
14192 | { | |
14193 | as_bad (_("unexpected register in list")); | |
14194 | break; | |
14195 | } | |
14196 | if (++reg1 == 24) | |
14197 | reg1 = 30; | |
14198 | } | |
14199 | } | |
14200 | ||
14201 | /* Encode args/statics combination. */ | |
91d6fa6a | 14202 | if (nargs & statics) |
0499d65b | 14203 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14204 | else if (nargs == 0xf) |
0499d65b TS |
14205 | /* All $a0-$a3 are args. */ |
14206 | opcode |= MIPS16_ALL_ARGS << 16; | |
14207 | else if (statics == 0xf) | |
14208 | /* All $a0-$a3 are statics. */ | |
14209 | opcode |= MIPS16_ALL_STATICS << 16; | |
14210 | else | |
14211 | { | |
14212 | int narg = 0, nstat = 0; | |
14213 | ||
14214 | /* Count arg registers. */ | |
91d6fa6a | 14215 | while (nargs & 0x1) |
0499d65b | 14216 | { |
91d6fa6a | 14217 | nargs >>= 1; |
0499d65b TS |
14218 | narg++; |
14219 | } | |
91d6fa6a | 14220 | if (nargs != 0) |
0499d65b TS |
14221 | as_bad (_("invalid arg register list")); |
14222 | ||
14223 | /* Count static registers. */ | |
14224 | while (statics & 0x8) | |
14225 | { | |
14226 | statics = (statics << 1) & 0xf; | |
14227 | nstat++; | |
14228 | } | |
14229 | if (statics != 0) | |
14230 | as_bad (_("invalid static register list")); | |
14231 | ||
14232 | /* Encode args/statics. */ | |
14233 | opcode |= ((narg << 2) | nstat) << 16; | |
14234 | } | |
14235 | ||
14236 | /* Encode $s0/$s1. */ | |
14237 | if (sregs & (1 << 0)) /* $s0 */ | |
14238 | opcode |= 0x20; | |
14239 | if (sregs & (1 << 1)) /* $s1 */ | |
14240 | opcode |= 0x10; | |
14241 | sregs >>= 2; | |
14242 | ||
14243 | if (sregs != 0) | |
14244 | { | |
14245 | /* Count regs $s2-$s8. */ | |
14246 | int nsreg = 0; | |
14247 | while (sregs & 1) | |
14248 | { | |
14249 | sregs >>= 1; | |
14250 | nsreg++; | |
14251 | } | |
14252 | if (sregs != 0) | |
14253 | as_bad (_("invalid static register list")); | |
14254 | /* Encode $s2-$s8. */ | |
14255 | opcode |= nsreg << 24; | |
14256 | } | |
14257 | ||
14258 | /* Encode frame size. */ | |
14259 | if (!seen_framesz) | |
14260 | as_bad (_("missing frame size")); | |
14261 | else if ((framesz & 7) != 0 || framesz < 0 | |
14262 | || framesz > 0xff * 8) | |
14263 | as_bad (_("invalid frame size")); | |
14264 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14265 | { | |
14266 | framesz /= 8; | |
14267 | opcode |= (((framesz & 0xf0) << 16) | |
14268 | | (framesz & 0x0f)); | |
14269 | } | |
14270 | ||
14271 | /* Finally build the instruction. */ | |
14272 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14273 | opcode |= MIPS16_EXTEND; |
14274 | ip->insn_opcode = opcode; | |
0499d65b TS |
14275 | } |
14276 | continue; | |
14277 | ||
252b5132 RH |
14278 | case 'e': /* extend code */ |
14279 | my_getExpression (&imm_expr, s); | |
14280 | check_absolute_expr (ip, &imm_expr); | |
14281 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14282 | { | |
14283 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14284 | ip->insn_mo->name, | |
14285 | (unsigned long) imm_expr.X_add_number); | |
14286 | imm_expr.X_add_number &= 0x7ff; | |
14287 | } | |
14288 | ip->insn_opcode |= imm_expr.X_add_number; | |
14289 | imm_expr.X_op = O_absent; | |
14290 | s = expr_end; | |
14291 | continue; | |
14292 | ||
14293 | default: | |
b37df7c4 | 14294 | abort (); |
252b5132 RH |
14295 | } |
14296 | break; | |
14297 | } | |
14298 | ||
14299 | /* Args don't match. */ | |
14300 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14301 | strcmp (insn->name, insn[1].name) == 0) | |
14302 | { | |
14303 | ++insn; | |
14304 | s = argsstart; | |
14305 | continue; | |
14306 | } | |
14307 | ||
14308 | insn_error = _("illegal operands"); | |
14309 | ||
14310 | return; | |
14311 | } | |
14312 | } | |
14313 | ||
14314 | /* This structure holds information we know about a mips16 immediate | |
14315 | argument type. */ | |
14316 | ||
e972090a NC |
14317 | struct mips16_immed_operand |
14318 | { | |
252b5132 RH |
14319 | /* The type code used in the argument string in the opcode table. */ |
14320 | int type; | |
14321 | /* The number of bits in the short form of the opcode. */ | |
14322 | int nbits; | |
14323 | /* The number of bits in the extended form of the opcode. */ | |
14324 | int extbits; | |
14325 | /* The amount by which the short form is shifted when it is used; | |
14326 | for example, the sw instruction has a shift count of 2. */ | |
14327 | int shift; | |
14328 | /* The amount by which the short form is shifted when it is stored | |
14329 | into the instruction code. */ | |
14330 | int op_shift; | |
14331 | /* Non-zero if the short form is unsigned. */ | |
14332 | int unsp; | |
14333 | /* Non-zero if the extended form is unsigned. */ | |
14334 | int extu; | |
14335 | /* Non-zero if the value is PC relative. */ | |
14336 | int pcrel; | |
14337 | }; | |
14338 | ||
14339 | /* The mips16 immediate operand types. */ | |
14340 | ||
14341 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14342 | { | |
14343 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14344 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14345 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14346 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14347 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14348 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14349 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14350 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14351 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14352 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14353 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14354 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14355 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14356 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14357 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14358 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14359 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14360 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14361 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14362 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14363 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14364 | }; | |
14365 | ||
14366 | #define MIPS16_NUM_IMMED \ | |
14367 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14368 | ||
b886a2ab RS |
14369 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14370 | NBITS is the number of significant bits in VAL. */ | |
14371 | ||
14372 | static unsigned long | |
14373 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14374 | { | |
14375 | int extval; | |
14376 | if (nbits == 16) | |
14377 | { | |
14378 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14379 | val &= 0x1f; | |
14380 | } | |
14381 | else if (nbits == 15) | |
14382 | { | |
14383 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14384 | val &= 0xf; | |
14385 | } | |
14386 | else | |
14387 | { | |
14388 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14389 | val = 0; | |
14390 | } | |
14391 | return (extval << 16) | val; | |
14392 | } | |
14393 | ||
5c04167a RS |
14394 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14395 | extending it if necessary. The instruction in *INSN may | |
14396 | already be extended. | |
14397 | ||
43c0598f RS |
14398 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14399 | if none. In the former case, VAL is a 16-bit number with no | |
14400 | defined signedness. | |
14401 | ||
14402 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14403 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14404 | |
14405 | static void | |
43c0598f RS |
14406 | mips16_immed (char *file, unsigned int line, int type, |
14407 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14408 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14409 | { |
3994f87e | 14410 | const struct mips16_immed_operand *op; |
252b5132 | 14411 | int mintiny, maxtiny; |
252b5132 RH |
14412 | |
14413 | op = mips16_immed_operands; | |
14414 | while (op->type != type) | |
14415 | { | |
14416 | ++op; | |
9c2799c2 | 14417 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14418 | } |
14419 | ||
14420 | if (op->unsp) | |
14421 | { | |
14422 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14423 | { | |
14424 | mintiny = 1; | |
14425 | maxtiny = 1 << op->nbits; | |
14426 | } | |
14427 | else | |
14428 | { | |
14429 | mintiny = 0; | |
14430 | maxtiny = (1 << op->nbits) - 1; | |
14431 | } | |
43c0598f RS |
14432 | if (reloc != BFD_RELOC_UNUSED) |
14433 | val &= 0xffff; | |
252b5132 RH |
14434 | } |
14435 | else | |
14436 | { | |
14437 | mintiny = - (1 << (op->nbits - 1)); | |
14438 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14439 | if (reloc != BFD_RELOC_UNUSED) |
14440 | val = SEXT_16BIT (val); | |
252b5132 RH |
14441 | } |
14442 | ||
14443 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14444 | if (type == 'p' || type == 'q') | |
14445 | val /= 2; | |
14446 | ||
14447 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14448 | || val < (mintiny << op->shift) | |
14449 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14450 | { |
14451 | /* We need an extended instruction. */ | |
14452 | if (user_insn_length == 2) | |
14453 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14454 | else | |
14455 | *insn |= MIPS16_EXTEND; | |
14456 | } | |
14457 | else if (user_insn_length == 4) | |
14458 | { | |
14459 | /* The operand doesn't force an unextended instruction to be extended. | |
14460 | Warn if the user wanted an extended instruction anyway. */ | |
14461 | *insn |= MIPS16_EXTEND; | |
14462 | as_warn_where (file, line, | |
14463 | _("extended operand requested but not required")); | |
14464 | } | |
252b5132 | 14465 | |
5c04167a | 14466 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14467 | { |
14468 | int insnval; | |
14469 | ||
252b5132 RH |
14470 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14471 | insnval <<= op->op_shift; | |
14472 | *insn |= insnval; | |
14473 | } | |
14474 | else | |
14475 | { | |
14476 | long minext, maxext; | |
252b5132 | 14477 | |
43c0598f | 14478 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14479 | { |
43c0598f RS |
14480 | if (op->extu) |
14481 | { | |
14482 | minext = 0; | |
14483 | maxext = (1 << op->extbits) - 1; | |
14484 | } | |
14485 | else | |
14486 | { | |
14487 | minext = - (1 << (op->extbits - 1)); | |
14488 | maxext = (1 << (op->extbits - 1)) - 1; | |
14489 | } | |
14490 | if (val < minext || val > maxext) | |
14491 | as_bad_where (file, line, | |
14492 | _("operand value out of range for instruction")); | |
252b5132 | 14493 | } |
252b5132 | 14494 | |
b886a2ab | 14495 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14496 | } |
14497 | } | |
14498 | \f | |
d6f16593 | 14499 | struct percent_op_match |
ad8d3bb3 | 14500 | { |
5e0116d5 RS |
14501 | const char *str; |
14502 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14503 | }; |
14504 | ||
14505 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14506 | { |
5e0116d5 | 14507 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14508 | #ifdef OBJ_ELF |
5e0116d5 RS |
14509 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14510 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14511 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14512 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14513 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14514 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14515 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14516 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14517 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14518 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14519 | {"%half", BFD_RELOC_16}, | |
14520 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14521 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14522 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14523 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14524 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14525 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14526 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14527 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14528 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14529 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14530 | #endif |
5e0116d5 | 14531 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14532 | }; |
14533 | ||
d6f16593 MR |
14534 | static const struct percent_op_match mips16_percent_op[] = |
14535 | { | |
14536 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14537 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14538 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14539 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14540 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14541 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14542 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14543 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14544 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14545 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14546 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14547 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14548 | }; |
14549 | ||
252b5132 | 14550 | |
5e0116d5 RS |
14551 | /* Return true if *STR points to a relocation operator. When returning true, |
14552 | move *STR over the operator and store its relocation code in *RELOC. | |
14553 | Leave both *STR and *RELOC alone when returning false. */ | |
14554 | ||
14555 | static bfd_boolean | |
17a2f251 | 14556 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14557 | { |
d6f16593 MR |
14558 | const struct percent_op_match *percent_op; |
14559 | size_t limit, i; | |
14560 | ||
14561 | if (mips_opts.mips16) | |
14562 | { | |
14563 | percent_op = mips16_percent_op; | |
14564 | limit = ARRAY_SIZE (mips16_percent_op); | |
14565 | } | |
14566 | else | |
14567 | { | |
14568 | percent_op = mips_percent_op; | |
14569 | limit = ARRAY_SIZE (mips_percent_op); | |
14570 | } | |
76b3015f | 14571 | |
d6f16593 | 14572 | for (i = 0; i < limit; i++) |
5e0116d5 | 14573 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14574 | { |
3f98094e DJ |
14575 | int len = strlen (percent_op[i].str); |
14576 | ||
14577 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14578 | continue; | |
14579 | ||
5e0116d5 RS |
14580 | *str += strlen (percent_op[i].str); |
14581 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14582 | |
5e0116d5 RS |
14583 | /* Check whether the output BFD supports this relocation. |
14584 | If not, issue an error and fall back on something safe. */ | |
14585 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14586 | { |
20203fb9 | 14587 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14588 | percent_op[i].str); |
01a3f561 | 14589 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14590 | } |
5e0116d5 | 14591 | return TRUE; |
394f9b3a | 14592 | } |
5e0116d5 | 14593 | return FALSE; |
394f9b3a | 14594 | } |
ad8d3bb3 | 14595 | |
ad8d3bb3 | 14596 | |
5e0116d5 RS |
14597 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14598 | expression in *EP and the relocations in the array starting | |
14599 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14600 | |
01a3f561 | 14601 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14602 | |
5e0116d5 | 14603 | static size_t |
17a2f251 TS |
14604 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14605 | char *str) | |
ad8d3bb3 | 14606 | { |
5e0116d5 RS |
14607 | bfd_reloc_code_real_type reversed_reloc[3]; |
14608 | size_t reloc_index, i; | |
09b8f35a RS |
14609 | int crux_depth, str_depth; |
14610 | char *crux; | |
5e0116d5 RS |
14611 | |
14612 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14613 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14614 | of the main expression and with CRUX_DEPTH containing the number | |
14615 | of open brackets at that point. */ | |
14616 | reloc_index = -1; | |
14617 | str_depth = 0; | |
14618 | do | |
fb1b3232 | 14619 | { |
09b8f35a RS |
14620 | reloc_index++; |
14621 | crux = str; | |
14622 | crux_depth = str_depth; | |
14623 | ||
14624 | /* Skip over whitespace and brackets, keeping count of the number | |
14625 | of brackets. */ | |
14626 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14627 | if (*str++ == '(') | |
14628 | str_depth++; | |
5e0116d5 | 14629 | } |
09b8f35a RS |
14630 | while (*str == '%' |
14631 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14632 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14633 | |
09b8f35a | 14634 | my_getExpression (ep, crux); |
5e0116d5 | 14635 | str = expr_end; |
394f9b3a | 14636 | |
5e0116d5 | 14637 | /* Match every open bracket. */ |
09b8f35a | 14638 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14639 | if (*str++ == ')') |
09b8f35a | 14640 | crux_depth--; |
394f9b3a | 14641 | |
09b8f35a | 14642 | if (crux_depth > 0) |
20203fb9 | 14643 | as_bad (_("unclosed '('")); |
394f9b3a | 14644 | |
5e0116d5 | 14645 | expr_end = str; |
252b5132 | 14646 | |
01a3f561 | 14647 | if (reloc_index != 0) |
64bdfcaf RS |
14648 | { |
14649 | prev_reloc_op_frag = frag_now; | |
14650 | for (i = 0; i < reloc_index; i++) | |
14651 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14652 | } | |
fb1b3232 | 14653 | |
5e0116d5 | 14654 | return reloc_index; |
252b5132 RH |
14655 | } |
14656 | ||
14657 | static void | |
17a2f251 | 14658 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14659 | { |
14660 | char *save_in; | |
14661 | ||
14662 | save_in = input_line_pointer; | |
14663 | input_line_pointer = str; | |
14664 | expression (ep); | |
14665 | expr_end = input_line_pointer; | |
14666 | input_line_pointer = save_in; | |
252b5132 RH |
14667 | } |
14668 | ||
252b5132 | 14669 | char * |
17a2f251 | 14670 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14671 | { |
499ac353 | 14672 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14673 | } |
14674 | ||
14675 | void | |
17a2f251 | 14676 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14677 | { |
14678 | if (target_big_endian) | |
14679 | number_to_chars_bigendian (buf, val, n); | |
14680 | else | |
14681 | number_to_chars_littleendian (buf, val, n); | |
14682 | } | |
14683 | \f | |
ae948b86 | 14684 | #ifdef OBJ_ELF |
e013f690 TS |
14685 | static int support_64bit_objects(void) |
14686 | { | |
14687 | const char **list, **l; | |
aa3d8fdf | 14688 | int yes; |
e013f690 TS |
14689 | |
14690 | list = bfd_target_list (); | |
14691 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14692 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14693 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14694 | break; |
aa3d8fdf | 14695 | yes = (*l != NULL); |
e013f690 | 14696 | free (list); |
aa3d8fdf | 14697 | return yes; |
e013f690 | 14698 | } |
ae948b86 | 14699 | #endif /* OBJ_ELF */ |
e013f690 | 14700 | |
78849248 | 14701 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14702 | |
23fce1e3 NC |
14703 | enum options |
14704 | { | |
14705 | OPTION_MARCH = OPTION_MD_BASE, | |
14706 | OPTION_MTUNE, | |
14707 | OPTION_MIPS1, | |
14708 | OPTION_MIPS2, | |
14709 | OPTION_MIPS3, | |
14710 | OPTION_MIPS4, | |
14711 | OPTION_MIPS5, | |
14712 | OPTION_MIPS32, | |
14713 | OPTION_MIPS64, | |
14714 | OPTION_MIPS32R2, | |
14715 | OPTION_MIPS64R2, | |
14716 | OPTION_MIPS16, | |
14717 | OPTION_NO_MIPS16, | |
14718 | OPTION_MIPS3D, | |
14719 | OPTION_NO_MIPS3D, | |
14720 | OPTION_MDMX, | |
14721 | OPTION_NO_MDMX, | |
14722 | OPTION_DSP, | |
14723 | OPTION_NO_DSP, | |
14724 | OPTION_MT, | |
14725 | OPTION_NO_MT, | |
b015e599 AP |
14726 | OPTION_VIRT, |
14727 | OPTION_NO_VIRT, | |
23fce1e3 NC |
14728 | OPTION_SMARTMIPS, |
14729 | OPTION_NO_SMARTMIPS, | |
14730 | OPTION_DSPR2, | |
14731 | OPTION_NO_DSPR2, | |
7f3c4072 CM |
14732 | OPTION_EVA, |
14733 | OPTION_NO_EVA, | |
df58fc94 RS |
14734 | OPTION_MICROMIPS, |
14735 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14736 | OPTION_MCU, |
14737 | OPTION_NO_MCU, | |
23fce1e3 NC |
14738 | OPTION_COMPAT_ARCH_BASE, |
14739 | OPTION_M4650, | |
14740 | OPTION_NO_M4650, | |
14741 | OPTION_M4010, | |
14742 | OPTION_NO_M4010, | |
14743 | OPTION_M4100, | |
14744 | OPTION_NO_M4100, | |
14745 | OPTION_M3900, | |
14746 | OPTION_NO_M3900, | |
14747 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14748 | OPTION_MNO_7000_HILO_FIX, |
14749 | OPTION_FIX_24K, | |
14750 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14751 | OPTION_FIX_LOONGSON2F_JUMP, |
14752 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14753 | OPTION_FIX_LOONGSON2F_NOP, | |
14754 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14755 | OPTION_FIX_VR4120, |
14756 | OPTION_NO_FIX_VR4120, | |
14757 | OPTION_FIX_VR4130, | |
14758 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14759 | OPTION_FIX_CN63XXP1, |
14760 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14761 | OPTION_TRAP, |
14762 | OPTION_BREAK, | |
14763 | OPTION_EB, | |
14764 | OPTION_EL, | |
14765 | OPTION_FP32, | |
14766 | OPTION_GP32, | |
14767 | OPTION_CONSTRUCT_FLOATS, | |
14768 | OPTION_NO_CONSTRUCT_FLOATS, | |
14769 | OPTION_FP64, | |
14770 | OPTION_GP64, | |
14771 | OPTION_RELAX_BRANCH, | |
14772 | OPTION_NO_RELAX_BRANCH, | |
14773 | OPTION_MSHARED, | |
14774 | OPTION_MNO_SHARED, | |
14775 | OPTION_MSYM32, | |
14776 | OPTION_MNO_SYM32, | |
14777 | OPTION_SOFT_FLOAT, | |
14778 | OPTION_HARD_FLOAT, | |
14779 | OPTION_SINGLE_FLOAT, | |
14780 | OPTION_DOUBLE_FLOAT, | |
14781 | OPTION_32, | |
14782 | #ifdef OBJ_ELF | |
14783 | OPTION_CALL_SHARED, | |
14784 | OPTION_CALL_NONPIC, | |
14785 | OPTION_NON_SHARED, | |
14786 | OPTION_XGOT, | |
14787 | OPTION_MABI, | |
14788 | OPTION_N32, | |
14789 | OPTION_64, | |
14790 | OPTION_MDEBUG, | |
14791 | OPTION_NO_MDEBUG, | |
14792 | OPTION_PDR, | |
14793 | OPTION_NO_PDR, | |
14794 | OPTION_MVXWORKS_PIC, | |
14795 | #endif /* OBJ_ELF */ | |
14796 | OPTION_END_OF_ENUM | |
14797 | }; | |
14798 | ||
e972090a NC |
14799 | struct option md_longopts[] = |
14800 | { | |
f9b4148d | 14801 | /* Options which specify architecture. */ |
f9b4148d | 14802 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14803 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14804 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14805 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14806 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14807 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14808 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14809 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14810 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14811 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14812 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14813 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14814 | |
14815 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14816 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14817 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14818 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14819 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14820 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14821 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14822 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14823 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14824 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14825 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14826 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14827 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14828 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14829 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
7f3c4072 CM |
14830 | {"meva", no_argument, NULL, OPTION_EVA}, |
14831 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
df58fc94 RS |
14832 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14833 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14834 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14835 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
b015e599 AP |
14836 | {"mvirt", no_argument, NULL, OPTION_VIRT}, |
14837 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
f9b4148d CD |
14838 | |
14839 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14840 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14841 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14842 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14843 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14844 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14845 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14846 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14847 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14848 | ||
14849 | /* Options which enable bug fixes. */ | |
f9b4148d | 14850 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14851 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14852 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14853 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14854 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14855 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14856 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14857 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14858 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14859 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14860 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14861 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14862 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14863 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14864 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14865 | |
14866 | /* Miscellaneous options. */ | |
252b5132 RH |
14867 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14868 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14869 | {"break", no_argument, NULL, OPTION_BREAK}, |
14870 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14871 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14872 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14873 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14874 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14875 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14876 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14877 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14878 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14879 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14880 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14881 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14882 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14883 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14884 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14885 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14886 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14887 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14888 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14889 | |
14890 | /* Strictly speaking this next option is ELF specific, | |
14891 | but we allow it for other ports as well in order to | |
14892 | make testing easier. */ | |
14893 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14894 | |
f9b4148d | 14895 | /* ELF-specific options. */ |
156c2f8b | 14896 | #ifdef OBJ_ELF |
156c2f8b NC |
14897 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14898 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14899 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14900 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14901 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14902 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14903 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14904 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14905 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14906 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14907 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14908 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14909 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14910 | #endif /* OBJ_ELF */ |
f9b4148d | 14911 | |
252b5132 RH |
14912 | {NULL, no_argument, NULL, 0} |
14913 | }; | |
156c2f8b | 14914 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14915 | |
316f5878 RS |
14916 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14917 | NEW_VALUE. Warn if another value was already specified. Note: | |
14918 | we have to defer parsing the -march and -mtune arguments in order | |
14919 | to handle 'from-abi' correctly, since the ABI might be specified | |
14920 | in a later argument. */ | |
14921 | ||
14922 | static void | |
17a2f251 | 14923 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14924 | { |
14925 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14926 | as_warn (_("A different %s was already specified, is now %s"), | |
14927 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14928 | new_value); | |
14929 | ||
14930 | *string_ptr = new_value; | |
14931 | } | |
14932 | ||
252b5132 | 14933 | int |
17a2f251 | 14934 | md_parse_option (int c, char *arg) |
252b5132 RH |
14935 | { |
14936 | switch (c) | |
14937 | { | |
119d663a NC |
14938 | case OPTION_CONSTRUCT_FLOATS: |
14939 | mips_disable_float_construction = 0; | |
14940 | break; | |
bdaaa2e1 | 14941 | |
119d663a NC |
14942 | case OPTION_NO_CONSTRUCT_FLOATS: |
14943 | mips_disable_float_construction = 1; | |
14944 | break; | |
bdaaa2e1 | 14945 | |
252b5132 RH |
14946 | case OPTION_TRAP: |
14947 | mips_trap = 1; | |
14948 | break; | |
14949 | ||
14950 | case OPTION_BREAK: | |
14951 | mips_trap = 0; | |
14952 | break; | |
14953 | ||
14954 | case OPTION_EB: | |
14955 | target_big_endian = 1; | |
14956 | break; | |
14957 | ||
14958 | case OPTION_EL: | |
14959 | target_big_endian = 0; | |
14960 | break; | |
14961 | ||
14962 | case 'O': | |
4ffff32f TS |
14963 | if (arg == NULL) |
14964 | mips_optimize = 1; | |
14965 | else if (arg[0] == '0') | |
14966 | mips_optimize = 0; | |
14967 | else if (arg[0] == '1') | |
252b5132 RH |
14968 | mips_optimize = 1; |
14969 | else | |
14970 | mips_optimize = 2; | |
14971 | break; | |
14972 | ||
14973 | case 'g': | |
14974 | if (arg == NULL) | |
14975 | mips_debug = 2; | |
14976 | else | |
14977 | mips_debug = atoi (arg); | |
252b5132 RH |
14978 | break; |
14979 | ||
14980 | case OPTION_MIPS1: | |
316f5878 | 14981 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14982 | break; |
14983 | ||
14984 | case OPTION_MIPS2: | |
316f5878 | 14985 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14986 | break; |
14987 | ||
14988 | case OPTION_MIPS3: | |
316f5878 | 14989 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14990 | break; |
14991 | ||
14992 | case OPTION_MIPS4: | |
316f5878 | 14993 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14994 | break; |
14995 | ||
84ea6cf2 | 14996 | case OPTION_MIPS5: |
316f5878 | 14997 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14998 | break; |
14999 | ||
e7af610e | 15000 | case OPTION_MIPS32: |
316f5878 | 15001 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
15002 | break; |
15003 | ||
af7ee8bf CD |
15004 | case OPTION_MIPS32R2: |
15005 | file_mips_isa = ISA_MIPS32R2; | |
15006 | break; | |
15007 | ||
5f74bc13 CD |
15008 | case OPTION_MIPS64R2: |
15009 | file_mips_isa = ISA_MIPS64R2; | |
15010 | break; | |
15011 | ||
84ea6cf2 | 15012 | case OPTION_MIPS64: |
316f5878 | 15013 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
15014 | break; |
15015 | ||
ec68c924 | 15016 | case OPTION_MTUNE: |
316f5878 RS |
15017 | mips_set_option_string (&mips_tune_string, arg); |
15018 | break; | |
ec68c924 | 15019 | |
316f5878 RS |
15020 | case OPTION_MARCH: |
15021 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
15022 | break; |
15023 | ||
15024 | case OPTION_M4650: | |
316f5878 RS |
15025 | mips_set_option_string (&mips_arch_string, "4650"); |
15026 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
15027 | break; |
15028 | ||
15029 | case OPTION_NO_M4650: | |
15030 | break; | |
15031 | ||
15032 | case OPTION_M4010: | |
316f5878 RS |
15033 | mips_set_option_string (&mips_arch_string, "4010"); |
15034 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
15035 | break; |
15036 | ||
15037 | case OPTION_NO_M4010: | |
15038 | break; | |
15039 | ||
15040 | case OPTION_M4100: | |
316f5878 RS |
15041 | mips_set_option_string (&mips_arch_string, "4100"); |
15042 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
15043 | break; |
15044 | ||
15045 | case OPTION_NO_M4100: | |
15046 | break; | |
15047 | ||
252b5132 | 15048 | case OPTION_M3900: |
316f5878 RS |
15049 | mips_set_option_string (&mips_arch_string, "3900"); |
15050 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 15051 | break; |
bdaaa2e1 | 15052 | |
252b5132 RH |
15053 | case OPTION_NO_M3900: |
15054 | break; | |
15055 | ||
deec1734 CD |
15056 | case OPTION_MDMX: |
15057 | mips_opts.ase_mdmx = 1; | |
15058 | break; | |
15059 | ||
15060 | case OPTION_NO_MDMX: | |
15061 | mips_opts.ase_mdmx = 0; | |
15062 | break; | |
15063 | ||
74cd071d CF |
15064 | case OPTION_DSP: |
15065 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 15066 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
15067 | break; |
15068 | ||
15069 | case OPTION_NO_DSP: | |
8b082fb1 TS |
15070 | mips_opts.ase_dsp = 0; |
15071 | mips_opts.ase_dspr2 = 0; | |
15072 | break; | |
15073 | ||
15074 | case OPTION_DSPR2: | |
15075 | mips_opts.ase_dspr2 = 1; | |
15076 | mips_opts.ase_dsp = 1; | |
15077 | break; | |
15078 | ||
15079 | case OPTION_NO_DSPR2: | |
15080 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
15081 | mips_opts.ase_dsp = 0; |
15082 | break; | |
15083 | ||
7f3c4072 CM |
15084 | case OPTION_EVA: |
15085 | mips_opts.ase_eva = 1; | |
15086 | break; | |
15087 | ||
15088 | case OPTION_NO_EVA: | |
15089 | mips_opts.ase_eva = 0; | |
15090 | break; | |
15091 | ||
ef2e4d86 CF |
15092 | case OPTION_MT: |
15093 | mips_opts.ase_mt = 1; | |
15094 | break; | |
15095 | ||
15096 | case OPTION_NO_MT: | |
15097 | mips_opts.ase_mt = 0; | |
15098 | break; | |
15099 | ||
dec0624d MR |
15100 | case OPTION_MCU: |
15101 | mips_opts.ase_mcu = 1; | |
15102 | break; | |
15103 | ||
15104 | case OPTION_NO_MCU: | |
15105 | mips_opts.ase_mcu = 0; | |
15106 | break; | |
15107 | ||
df58fc94 RS |
15108 | case OPTION_MICROMIPS: |
15109 | if (mips_opts.mips16 == 1) | |
15110 | { | |
15111 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15112 | return 0; | |
15113 | } | |
15114 | mips_opts.micromips = 1; | |
15115 | mips_no_prev_insn (); | |
15116 | break; | |
15117 | ||
15118 | case OPTION_NO_MICROMIPS: | |
15119 | mips_opts.micromips = 0; | |
15120 | mips_no_prev_insn (); | |
15121 | break; | |
15122 | ||
b015e599 AP |
15123 | case OPTION_VIRT: |
15124 | mips_opts.ase_virt = 1; | |
15125 | break; | |
15126 | ||
15127 | case OPTION_NO_VIRT: | |
15128 | mips_opts.ase_virt = 0; | |
15129 | break; | |
15130 | ||
252b5132 | 15131 | case OPTION_MIPS16: |
df58fc94 RS |
15132 | if (mips_opts.micromips == 1) |
15133 | { | |
15134 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15135 | return 0; | |
15136 | } | |
252b5132 | 15137 | mips_opts.mips16 = 1; |
7d10b47d | 15138 | mips_no_prev_insn (); |
252b5132 RH |
15139 | break; |
15140 | ||
15141 | case OPTION_NO_MIPS16: | |
15142 | mips_opts.mips16 = 0; | |
7d10b47d | 15143 | mips_no_prev_insn (); |
252b5132 RH |
15144 | break; |
15145 | ||
1f25f5d3 CD |
15146 | case OPTION_MIPS3D: |
15147 | mips_opts.ase_mips3d = 1; | |
15148 | break; | |
15149 | ||
15150 | case OPTION_NO_MIPS3D: | |
15151 | mips_opts.ase_mips3d = 0; | |
15152 | break; | |
15153 | ||
e16bfa71 TS |
15154 | case OPTION_SMARTMIPS: |
15155 | mips_opts.ase_smartmips = 1; | |
15156 | break; | |
15157 | ||
15158 | case OPTION_NO_SMARTMIPS: | |
15159 | mips_opts.ase_smartmips = 0; | |
15160 | break; | |
15161 | ||
6a32d874 CM |
15162 | case OPTION_FIX_24K: |
15163 | mips_fix_24k = 1; | |
15164 | break; | |
15165 | ||
15166 | case OPTION_NO_FIX_24K: | |
15167 | mips_fix_24k = 0; | |
15168 | break; | |
15169 | ||
c67a084a NC |
15170 | case OPTION_FIX_LOONGSON2F_JUMP: |
15171 | mips_fix_loongson2f_jump = TRUE; | |
15172 | break; | |
15173 | ||
15174 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15175 | mips_fix_loongson2f_jump = FALSE; | |
15176 | break; | |
15177 | ||
15178 | case OPTION_FIX_LOONGSON2F_NOP: | |
15179 | mips_fix_loongson2f_nop = TRUE; | |
15180 | break; | |
15181 | ||
15182 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15183 | mips_fix_loongson2f_nop = FALSE; | |
15184 | break; | |
15185 | ||
d766e8ec RS |
15186 | case OPTION_FIX_VR4120: |
15187 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15188 | break; |
15189 | ||
d766e8ec RS |
15190 | case OPTION_NO_FIX_VR4120: |
15191 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15192 | break; |
15193 | ||
7d8e00cf RS |
15194 | case OPTION_FIX_VR4130: |
15195 | mips_fix_vr4130 = 1; | |
15196 | break; | |
15197 | ||
15198 | case OPTION_NO_FIX_VR4130: | |
15199 | mips_fix_vr4130 = 0; | |
15200 | break; | |
15201 | ||
d954098f DD |
15202 | case OPTION_FIX_CN63XXP1: |
15203 | mips_fix_cn63xxp1 = TRUE; | |
15204 | break; | |
15205 | ||
15206 | case OPTION_NO_FIX_CN63XXP1: | |
15207 | mips_fix_cn63xxp1 = FALSE; | |
15208 | break; | |
15209 | ||
4a6a3df4 AO |
15210 | case OPTION_RELAX_BRANCH: |
15211 | mips_relax_branch = 1; | |
15212 | break; | |
15213 | ||
15214 | case OPTION_NO_RELAX_BRANCH: | |
15215 | mips_relax_branch = 0; | |
15216 | break; | |
15217 | ||
aa6975fb ILT |
15218 | case OPTION_MSHARED: |
15219 | mips_in_shared = TRUE; | |
15220 | break; | |
15221 | ||
15222 | case OPTION_MNO_SHARED: | |
15223 | mips_in_shared = FALSE; | |
15224 | break; | |
15225 | ||
aed1a261 RS |
15226 | case OPTION_MSYM32: |
15227 | mips_opts.sym32 = TRUE; | |
15228 | break; | |
15229 | ||
15230 | case OPTION_MNO_SYM32: | |
15231 | mips_opts.sym32 = FALSE; | |
15232 | break; | |
15233 | ||
0f074f60 | 15234 | #ifdef OBJ_ELF |
252b5132 RH |
15235 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15236 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15237 | intended to be compatible with Irix 5. */ | |
15238 | case OPTION_CALL_SHARED: | |
f43abd2b | 15239 | if (!IS_ELF) |
252b5132 RH |
15240 | { |
15241 | as_bad (_("-call_shared is supported only for ELF format")); | |
15242 | return 0; | |
15243 | } | |
15244 | mips_pic = SVR4_PIC; | |
143d77c5 | 15245 | mips_abicalls = TRUE; |
252b5132 RH |
15246 | break; |
15247 | ||
861fb55a DJ |
15248 | case OPTION_CALL_NONPIC: |
15249 | if (!IS_ELF) | |
15250 | { | |
15251 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
15252 | return 0; | |
15253 | } | |
15254 | mips_pic = NO_PIC; | |
15255 | mips_abicalls = TRUE; | |
15256 | break; | |
15257 | ||
252b5132 | 15258 | case OPTION_NON_SHARED: |
f43abd2b | 15259 | if (!IS_ELF) |
252b5132 RH |
15260 | { |
15261 | as_bad (_("-non_shared is supported only for ELF format")); | |
15262 | return 0; | |
15263 | } | |
15264 | mips_pic = NO_PIC; | |
143d77c5 | 15265 | mips_abicalls = FALSE; |
252b5132 RH |
15266 | break; |
15267 | ||
44075ae2 TS |
15268 | /* The -xgot option tells the assembler to use 32 bit offsets |
15269 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15270 | compatibility. */ |
15271 | case OPTION_XGOT: | |
15272 | mips_big_got = 1; | |
15273 | break; | |
0f074f60 | 15274 | #endif /* OBJ_ELF */ |
252b5132 RH |
15275 | |
15276 | case 'G': | |
6caf9ef4 TS |
15277 | g_switch_value = atoi (arg); |
15278 | g_switch_seen = 1; | |
252b5132 RH |
15279 | break; |
15280 | ||
34ba82a8 TS |
15281 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15282 | and -mabi=64. */ | |
252b5132 | 15283 | case OPTION_32: |
23fce1e3 NC |
15284 | if (IS_ELF) |
15285 | mips_abi = O32_ABI; | |
15286 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15287 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15288 | break; |
15289 | ||
23fce1e3 | 15290 | #ifdef OBJ_ELF |
e013f690 | 15291 | case OPTION_N32: |
f43abd2b | 15292 | if (!IS_ELF) |
34ba82a8 TS |
15293 | { |
15294 | as_bad (_("-n32 is supported for ELF format only")); | |
15295 | return 0; | |
15296 | } | |
316f5878 | 15297 | mips_abi = N32_ABI; |
e013f690 | 15298 | break; |
252b5132 | 15299 | |
e013f690 | 15300 | case OPTION_64: |
f43abd2b | 15301 | if (!IS_ELF) |
34ba82a8 TS |
15302 | { |
15303 | as_bad (_("-64 is supported for ELF format only")); | |
15304 | return 0; | |
15305 | } | |
316f5878 | 15306 | mips_abi = N64_ABI; |
f43abd2b | 15307 | if (!support_64bit_objects()) |
e013f690 | 15308 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15309 | break; |
ae948b86 | 15310 | #endif /* OBJ_ELF */ |
252b5132 | 15311 | |
c97ef257 | 15312 | case OPTION_GP32: |
a325df1d | 15313 | file_mips_gp32 = 1; |
c97ef257 AH |
15314 | break; |
15315 | ||
15316 | case OPTION_GP64: | |
a325df1d | 15317 | file_mips_gp32 = 0; |
c97ef257 | 15318 | break; |
252b5132 | 15319 | |
ca4e0257 | 15320 | case OPTION_FP32: |
a325df1d | 15321 | file_mips_fp32 = 1; |
316f5878 RS |
15322 | break; |
15323 | ||
15324 | case OPTION_FP64: | |
15325 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15326 | break; |
15327 | ||
037b32b9 AN |
15328 | case OPTION_SINGLE_FLOAT: |
15329 | file_mips_single_float = 1; | |
15330 | break; | |
15331 | ||
15332 | case OPTION_DOUBLE_FLOAT: | |
15333 | file_mips_single_float = 0; | |
15334 | break; | |
15335 | ||
15336 | case OPTION_SOFT_FLOAT: | |
15337 | file_mips_soft_float = 1; | |
15338 | break; | |
15339 | ||
15340 | case OPTION_HARD_FLOAT: | |
15341 | file_mips_soft_float = 0; | |
15342 | break; | |
15343 | ||
ae948b86 | 15344 | #ifdef OBJ_ELF |
252b5132 | 15345 | case OPTION_MABI: |
f43abd2b | 15346 | if (!IS_ELF) |
34ba82a8 TS |
15347 | { |
15348 | as_bad (_("-mabi is supported for ELF format only")); | |
15349 | return 0; | |
15350 | } | |
e013f690 | 15351 | if (strcmp (arg, "32") == 0) |
316f5878 | 15352 | mips_abi = O32_ABI; |
e013f690 | 15353 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15354 | mips_abi = O64_ABI; |
e013f690 | 15355 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15356 | mips_abi = N32_ABI; |
e013f690 TS |
15357 | else if (strcmp (arg, "64") == 0) |
15358 | { | |
316f5878 | 15359 | mips_abi = N64_ABI; |
e013f690 TS |
15360 | if (! support_64bit_objects()) |
15361 | as_fatal (_("No compiled in support for 64 bit object file " | |
15362 | "format")); | |
15363 | } | |
15364 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15365 | mips_abi = EABI_ABI; |
e013f690 | 15366 | else |
da0e507f TS |
15367 | { |
15368 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15369 | return 0; | |
15370 | } | |
252b5132 | 15371 | break; |
e013f690 | 15372 | #endif /* OBJ_ELF */ |
252b5132 | 15373 | |
6b76fefe | 15374 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15375 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15376 | break; |
15377 | ||
9ee72ff1 | 15378 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15379 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15380 | break; |
15381 | ||
ecb4347a DJ |
15382 | #ifdef OBJ_ELF |
15383 | case OPTION_MDEBUG: | |
b34976b6 | 15384 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15385 | break; |
15386 | ||
15387 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15388 | mips_flag_mdebug = FALSE; |
ecb4347a | 15389 | break; |
dcd410fe RO |
15390 | |
15391 | case OPTION_PDR: | |
15392 | mips_flag_pdr = TRUE; | |
15393 | break; | |
15394 | ||
15395 | case OPTION_NO_PDR: | |
15396 | mips_flag_pdr = FALSE; | |
15397 | break; | |
0a44bf69 RS |
15398 | |
15399 | case OPTION_MVXWORKS_PIC: | |
15400 | mips_pic = VXWORKS_PIC; | |
15401 | break; | |
ecb4347a DJ |
15402 | #endif /* OBJ_ELF */ |
15403 | ||
252b5132 RH |
15404 | default: |
15405 | return 0; | |
15406 | } | |
15407 | ||
c67a084a NC |
15408 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15409 | ||
252b5132 RH |
15410 | return 1; |
15411 | } | |
316f5878 RS |
15412 | \f |
15413 | /* Set up globals to generate code for the ISA or processor | |
15414 | described by INFO. */ | |
252b5132 | 15415 | |
252b5132 | 15416 | static void |
17a2f251 | 15417 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15418 | { |
316f5878 | 15419 | if (info != 0) |
252b5132 | 15420 | { |
fef14a42 TS |
15421 | file_mips_arch = info->cpu; |
15422 | mips_opts.arch = info->cpu; | |
316f5878 | 15423 | mips_opts.isa = info->isa; |
252b5132 | 15424 | } |
252b5132 RH |
15425 | } |
15426 | ||
252b5132 | 15427 | |
316f5878 | 15428 | /* Likewise for tuning. */ |
252b5132 | 15429 | |
316f5878 | 15430 | static void |
17a2f251 | 15431 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15432 | { |
15433 | if (info != 0) | |
fef14a42 | 15434 | mips_tune = info->cpu; |
316f5878 | 15435 | } |
80cc45a5 | 15436 | |
34ba82a8 | 15437 | |
252b5132 | 15438 | void |
17a2f251 | 15439 | mips_after_parse_args (void) |
e9670677 | 15440 | { |
fef14a42 TS |
15441 | const struct mips_cpu_info *arch_info = 0; |
15442 | const struct mips_cpu_info *tune_info = 0; | |
15443 | ||
e9670677 | 15444 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15445 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15446 | { |
6caf9ef4 | 15447 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15448 | as_bad (_("-G not supported in this configuration.")); |
15449 | g_switch_value = 0; | |
15450 | } | |
15451 | ||
cac012d6 AO |
15452 | if (mips_abi == NO_ABI) |
15453 | mips_abi = MIPS_DEFAULT_ABI; | |
15454 | ||
22923709 RS |
15455 | /* The following code determines the architecture and register size. |
15456 | Similar code was added to GCC 3.3 (see override_options() in | |
15457 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15458 | as much as possible. */ | |
e9670677 | 15459 | |
316f5878 | 15460 | if (mips_arch_string != 0) |
fef14a42 | 15461 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15462 | |
316f5878 | 15463 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15464 | { |
316f5878 | 15465 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15466 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15467 | the -march selection (if any). */ |
fef14a42 | 15468 | if (arch_info != 0) |
e9670677 | 15469 | { |
316f5878 RS |
15470 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15471 | There's no harm in specifying both as long as the ISA levels | |
15472 | are the same. */ | |
fef14a42 | 15473 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15474 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15475 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15476 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15477 | } |
316f5878 | 15478 | else |
fef14a42 | 15479 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15480 | } |
15481 | ||
fef14a42 | 15482 | if (arch_info == 0) |
95bfe26e MF |
15483 | { |
15484 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15485 | gas_assert (arch_info); | |
15486 | } | |
e9670677 | 15487 | |
fef14a42 | 15488 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15489 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15490 | arch_info->name); |
15491 | ||
15492 | mips_set_architecture (arch_info); | |
15493 | ||
15494 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15495 | if (mips_tune_string != 0) | |
15496 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15497 | |
fef14a42 TS |
15498 | if (tune_info == 0) |
15499 | mips_set_tune (arch_info); | |
15500 | else | |
15501 | mips_set_tune (tune_info); | |
e9670677 | 15502 | |
316f5878 | 15503 | if (file_mips_gp32 >= 0) |
e9670677 | 15504 | { |
316f5878 RS |
15505 | /* The user specified the size of the integer registers. Make sure |
15506 | it agrees with the ABI and ISA. */ | |
15507 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15508 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15509 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15510 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15511 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15512 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15513 | } |
15514 | else | |
15515 | { | |
316f5878 RS |
15516 | /* Infer the integer register size from the ABI and processor. |
15517 | Restrict ourselves to 32-bit registers if that's all the | |
15518 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15519 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15520 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15521 | } |
15522 | ||
ad3fea08 TS |
15523 | switch (file_mips_fp32) |
15524 | { | |
15525 | default: | |
15526 | case -1: | |
15527 | /* No user specified float register size. | |
15528 | ??? GAS treats single-float processors as though they had 64-bit | |
15529 | float registers (although it complains when double-precision | |
15530 | instructions are used). As things stand, saying they have 32-bit | |
15531 | registers would lead to spurious "register must be even" messages. | |
15532 | So here we assume float registers are never smaller than the | |
15533 | integer ones. */ | |
15534 | if (file_mips_gp32 == 0) | |
15535 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15536 | file_mips_fp32 = 0; | |
15537 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15538 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15539 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15540 | file_mips_fp32 = 0; | |
15541 | else | |
15542 | /* 32-bit float registers. */ | |
15543 | file_mips_fp32 = 1; | |
15544 | break; | |
15545 | ||
15546 | /* The user specified the size of the float registers. Check if it | |
15547 | agrees with the ABI and ISA. */ | |
15548 | case 0: | |
15549 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15550 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15551 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15552 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15553 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15554 | break; | |
15555 | case 1: | |
15556 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15557 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15558 | break; | |
15559 | } | |
e9670677 | 15560 | |
316f5878 | 15561 | /* End of GCC-shared inference code. */ |
e9670677 | 15562 | |
17a2f251 TS |
15563 | /* This flag is set when we have a 64-bit capable CPU but use only |
15564 | 32-bit wide registers. Note that EABI does not use it. */ | |
15565 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15566 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15567 | || mips_abi == O32_ABI)) | |
316f5878 | 15568 | mips_32bitmode = 1; |
e9670677 MR |
15569 | |
15570 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15571 | as_bad (_("trap exception not supported at ISA 1")); | |
15572 | ||
e9670677 MR |
15573 | /* If the selected architecture includes support for ASEs, enable |
15574 | generation of code for them. */ | |
a4672219 | 15575 | if (mips_opts.mips16 == -1) |
fef14a42 | 15576 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15577 | if (mips_opts.micromips == -1) |
15578 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15579 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15580 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15581 | && file_mips_fp32 == 0) ? 1 : 0; |
15582 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15583 | as_bad (_("-mfp32 used with -mips3d")); | |
15584 | ||
ffdefa66 | 15585 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15586 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15587 | && file_mips_fp32 == 0) ? 1 : 0; |
15588 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15589 | as_bad (_("-mfp32 used with -mdmx")); | |
15590 | ||
15591 | if (mips_opts.ase_smartmips == -1) | |
15592 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15593 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15594 | as_warn (_("%s ISA does not support SmartMIPS"), |
15595 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15596 | |
74cd071d | 15597 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15598 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15599 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15600 | as_warn (_("%s ISA does not support DSP ASE"), |
15601 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15602 | |
8b082fb1 TS |
15603 | if (mips_opts.ase_dspr2 == -1) |
15604 | { | |
15605 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15606 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15607 | } | |
15608 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15609 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15610 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15611 | |
7f3c4072 CM |
15612 | if (mips_opts.ase_eva == -1) |
15613 | mips_opts.ase_eva = (arch_info->flags & MIPS_CPU_ASE_EVA) ? 1 : 0; | |
15614 | if (mips_opts.ase_eva && !ISA_SUPPORTS_EVA_ASE) | |
15615 | as_warn (_("%s ISA does not support EVA ASE"), | |
15616 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15617 | ||
ef2e4d86 | 15618 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15619 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15620 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15621 | as_warn (_("%s ISA does not support MT ASE"), |
15622 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15623 | |
dec0624d MR |
15624 | if (mips_opts.ase_mcu == -1) |
15625 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15626 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15627 | as_warn (_("%s ISA does not support MCU ASE"), | |
15628 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15629 | ||
b015e599 AP |
15630 | if (mips_opts.ase_virt == -1) |
15631 | mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0; | |
15632 | if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE) | |
15633 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
15634 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15635 | ||
e9670677 | 15636 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15637 | file_ase_mips3d = mips_opts.ase_mips3d; |
15638 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15639 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15640 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15641 | file_ase_dspr2 = mips_opts.ase_dspr2; |
7f3c4072 | 15642 | file_ase_eva = mips_opts.ase_eva; |
ef2e4d86 | 15643 | file_ase_mt = mips_opts.ase_mt; |
b015e599 | 15644 | file_ase_virt = mips_opts.ase_virt; |
e9670677 MR |
15645 | mips_opts.gp32 = file_mips_gp32; |
15646 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15647 | mips_opts.soft_float = file_mips_soft_float; |
15648 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15649 | |
ecb4347a DJ |
15650 | if (mips_flag_mdebug < 0) |
15651 | { | |
15652 | #ifdef OBJ_MAYBE_ECOFF | |
15653 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15654 | mips_flag_mdebug = 1; | |
15655 | else | |
15656 | #endif /* OBJ_MAYBE_ECOFF */ | |
15657 | mips_flag_mdebug = 0; | |
15658 | } | |
e9670677 MR |
15659 | } |
15660 | \f | |
15661 | void | |
17a2f251 | 15662 | mips_init_after_args (void) |
252b5132 RH |
15663 | { |
15664 | /* initialize opcodes */ | |
15665 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15666 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15667 | } |
15668 | ||
15669 | long | |
17a2f251 | 15670 | md_pcrel_from (fixS *fixP) |
252b5132 | 15671 | { |
a7ebbfdf TS |
15672 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15673 | switch (fixP->fx_r_type) | |
15674 | { | |
df58fc94 RS |
15675 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15676 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15677 | /* Return the address of the delay slot. */ | |
15678 | return addr + 2; | |
15679 | ||
15680 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15681 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15682 | case BFD_RELOC_16_PCREL_S2: |
15683 | case BFD_RELOC_MIPS_JMP: | |
15684 | /* Return the address of the delay slot. */ | |
15685 | return addr + 4; | |
df58fc94 | 15686 | |
b47468a6 CM |
15687 | case BFD_RELOC_32_PCREL: |
15688 | return addr; | |
15689 | ||
a7ebbfdf | 15690 | default: |
58ea3d6a | 15691 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15692 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15693 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15694 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15695 | return addr; |
15696 | } | |
252b5132 RH |
15697 | } |
15698 | ||
252b5132 RH |
15699 | /* This is called before the symbol table is processed. In order to |
15700 | work with gcc when using mips-tfile, we must keep all local labels. | |
15701 | However, in other cases, we want to discard them. If we were | |
15702 | called with -g, but we didn't see any debugging information, it may | |
15703 | mean that gcc is smuggling debugging information through to | |
15704 | mips-tfile, in which case we must generate all local labels. */ | |
15705 | ||
15706 | void | |
17a2f251 | 15707 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15708 | { |
15709 | #ifndef NO_ECOFF_DEBUGGING | |
15710 | if (ECOFF_DEBUGGING | |
15711 | && mips_debug != 0 | |
15712 | && ! ecoff_debugging_seen) | |
15713 | flag_keep_locals = 1; | |
15714 | #endif | |
15715 | } | |
15716 | ||
3b91255e | 15717 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15718 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15719 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15720 | relocation operators. | |
15721 | ||
15722 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15723 | expression if: | |
15724 | ||
15725 | (a) it refers to the same symbol; and | |
15726 | (b) the offset applied in the %lo() expression is no lower than | |
15727 | the offset applied in the %got() or %hi(). | |
15728 | ||
15729 | (b) allows us to cope with code like: | |
15730 | ||
15731 | lui $4,%hi(foo) | |
15732 | lh $4,%lo(foo+2)($4) | |
15733 | ||
15734 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15735 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15736 | the high 16 bits. | |
15737 | ||
15738 | When several %lo()s match a particular %got() or %hi(), we use the | |
15739 | following rules to distinguish them: | |
15740 | ||
15741 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15742 | higher offsets. | |
15743 | ||
15744 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15745 | that already have a matching %got() or %hi(). | |
15746 | ||
15747 | (3) later %lo()s are better than earlier %lo()s. | |
15748 | ||
15749 | These rules are applied in order. | |
15750 | ||
15751 | (1) means, among other things, that %lo()s with identical offsets are | |
15752 | chosen if they exist. | |
15753 | ||
15754 | (2) means that we won't associate several high-part relocations with | |
15755 | the same low-part relocation unless there's no alternative. Having | |
15756 | several high parts for the same low part is a GNU extension; this rule | |
15757 | allows careful users to avoid it. | |
15758 | ||
15759 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15760 | with the last high-part relocation being at the front of the list. | |
15761 | It therefore makes sense to choose the last matching low-part | |
15762 | relocation, all other things being equal. It's also easier | |
15763 | to code that way. */ | |
252b5132 RH |
15764 | |
15765 | void | |
17a2f251 | 15766 | mips_frob_file (void) |
252b5132 RH |
15767 | { |
15768 | struct mips_hi_fixup *l; | |
35903be0 | 15769 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15770 | |
15771 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15772 | { | |
15773 | segment_info_type *seginfo; | |
3b91255e RS |
15774 | bfd_boolean matched_lo_p; |
15775 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15776 | |
9c2799c2 | 15777 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15778 | |
5919d012 | 15779 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15780 | there isn't supposed to be a matching LO. Ignore %gots against |
15781 | constants; we'll report an error for those later. */ | |
738e5348 | 15782 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15783 | && !(l->fixp->fx_addsy |
15784 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15785 | continue; |
15786 | ||
15787 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15788 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15789 | continue; |
15790 | ||
252b5132 | 15791 | seginfo = seg_info (l->seg); |
252b5132 | 15792 | |
3b91255e RS |
15793 | /* Set HI_POS to the position of this relocation in the chain. |
15794 | Set LO_POS to the position of the chosen low-part relocation. | |
15795 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15796 | relocation that matches an immediately-preceding high-part | |
15797 | relocation. */ | |
15798 | hi_pos = NULL; | |
15799 | lo_pos = NULL; | |
15800 | matched_lo_p = FALSE; | |
738e5348 | 15801 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15802 | |
3b91255e RS |
15803 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15804 | { | |
15805 | if (*pos == l->fixp) | |
15806 | hi_pos = pos; | |
15807 | ||
35903be0 | 15808 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15809 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15810 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15811 | && (lo_pos == NULL | |
15812 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15813 | || (!matched_lo_p | |
15814 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15815 | lo_pos = pos; | |
15816 | ||
15817 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15818 | && fixup_has_matching_lo_p (*pos)); | |
15819 | } | |
15820 | ||
15821 | /* If we found a match, remove the high-part relocation from its | |
15822 | current position and insert it before the low-part relocation. | |
15823 | Make the offsets match so that fixup_has_matching_lo_p() | |
15824 | will return true. | |
15825 | ||
15826 | We don't warn about unmatched high-part relocations since some | |
15827 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15828 | instructions. */ | |
15829 | if (lo_pos != NULL) | |
15830 | { | |
15831 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15832 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15833 | { |
3b91255e RS |
15834 | *hi_pos = l->fixp->fx_next; |
15835 | l->fixp->fx_next = *lo_pos; | |
15836 | *lo_pos = l->fixp; | |
252b5132 | 15837 | } |
252b5132 RH |
15838 | } |
15839 | } | |
15840 | } | |
15841 | ||
252b5132 | 15842 | int |
17a2f251 | 15843 | mips_force_relocation (fixS *fixp) |
252b5132 | 15844 | { |
ae6063d4 | 15845 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15846 | return 1; |
15847 | ||
df58fc94 RS |
15848 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15849 | so that the linker relaxation can update targets. */ | |
15850 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15851 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15852 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15853 | return 1; | |
15854 | ||
3e722fb5 | 15855 | return 0; |
252b5132 RH |
15856 | } |
15857 | ||
b886a2ab RS |
15858 | /* Read the instruction associated with RELOC from BUF. */ |
15859 | ||
15860 | static unsigned int | |
15861 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15862 | { | |
15863 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15864 | return read_compressed_insn (buf, 4); | |
15865 | else | |
15866 | return read_insn (buf); | |
15867 | } | |
15868 | ||
15869 | /* Write instruction INSN to BUF, given that it has been relocated | |
15870 | by RELOC. */ | |
15871 | ||
15872 | static void | |
15873 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15874 | unsigned long insn) | |
15875 | { | |
15876 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15877 | write_compressed_insn (buf, insn, 4); | |
15878 | else | |
15879 | write_insn (buf, insn); | |
15880 | } | |
15881 | ||
252b5132 RH |
15882 | /* Apply a fixup to the object file. */ |
15883 | ||
94f592af | 15884 | void |
55cf6793 | 15885 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15886 | { |
4d68580a | 15887 | char *buf; |
b886a2ab | 15888 | unsigned long insn; |
a7ebbfdf | 15889 | reloc_howto_type *howto; |
252b5132 | 15890 | |
a7ebbfdf TS |
15891 | /* We ignore generic BFD relocations we don't know about. */ |
15892 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15893 | if (! howto) | |
15894 | return; | |
65551fa4 | 15895 | |
df58fc94 RS |
15896 | gas_assert (fixP->fx_size == 2 |
15897 | || fixP->fx_size == 4 | |
90ecf173 MR |
15898 | || fixP->fx_r_type == BFD_RELOC_16 |
15899 | || fixP->fx_r_type == BFD_RELOC_64 | |
15900 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15901 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15902 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15903 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15904 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15905 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15906 | |
4d68580a | 15907 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15908 | |
df58fc94 RS |
15909 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15910 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15911 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15912 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15913 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15914 | |
15915 | /* Don't treat parts of a composite relocation as done. There are two | |
15916 | reasons for this: | |
15917 | ||
15918 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15919 | should nevertheless be emitted if the first part is. | |
15920 | ||
15921 | (2) In normal usage, composite relocations are never assembly-time | |
15922 | constants. The easiest way of dealing with the pathological | |
15923 | exceptions is to generate a relocation against STN_UNDEF and | |
15924 | leave everything up to the linker. */ | |
3994f87e | 15925 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15926 | fixP->fx_done = 1; |
15927 | ||
15928 | switch (fixP->fx_r_type) | |
15929 | { | |
3f98094e DJ |
15930 | case BFD_RELOC_MIPS_TLS_GD: |
15931 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15932 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15933 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15934 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15935 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15936 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15937 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15938 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15939 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15940 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15941 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15942 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15943 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15944 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15945 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15946 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15947 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15948 | case BFD_RELOC_MIPS16_TLS_GD: |
15949 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15950 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15951 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15952 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15953 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15954 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15955 | if (!fixP->fx_addsy) |
15956 | { | |
15957 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15958 | _("TLS relocation against a constant")); | |
15959 | break; | |
15960 | } | |
3f98094e DJ |
15961 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15962 | /* fall through */ | |
15963 | ||
252b5132 | 15964 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15965 | case BFD_RELOC_MIPS_SHIFT5: |
15966 | case BFD_RELOC_MIPS_SHIFT6: | |
15967 | case BFD_RELOC_MIPS_GOT_DISP: | |
15968 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15969 | case BFD_RELOC_MIPS_GOT_OFST: | |
15970 | case BFD_RELOC_MIPS_SUB: | |
15971 | case BFD_RELOC_MIPS_INSERT_A: | |
15972 | case BFD_RELOC_MIPS_INSERT_B: | |
15973 | case BFD_RELOC_MIPS_DELETE: | |
15974 | case BFD_RELOC_MIPS_HIGHEST: | |
15975 | case BFD_RELOC_MIPS_HIGHER: | |
15976 | case BFD_RELOC_MIPS_SCN_DISP: | |
15977 | case BFD_RELOC_MIPS_REL16: | |
15978 | case BFD_RELOC_MIPS_RELGOT: | |
15979 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15980 | case BFD_RELOC_HI16: |
15981 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15982 | case BFD_RELOC_LO16: |
cdf6fd85 | 15983 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15984 | case BFD_RELOC_MIPS_LITERAL: |
15985 | case BFD_RELOC_MIPS_CALL16: | |
15986 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15987 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15988 | case BFD_RELOC_MIPS_GOT_HI16: |
15989 | case BFD_RELOC_MIPS_GOT_LO16: | |
15990 | case BFD_RELOC_MIPS_CALL_HI16: | |
15991 | case BFD_RELOC_MIPS_CALL_LO16: | |
15992 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15993 | case BFD_RELOC_MIPS16_GOT16: |
15994 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15995 | case BFD_RELOC_MIPS16_HI16: |
15996 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15997 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15998 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15999 | case BFD_RELOC_MICROMIPS_JMP: |
16000 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
16001 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
16002 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
16003 | case BFD_RELOC_MICROMIPS_SUB: | |
16004 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
16005 | case BFD_RELOC_MICROMIPS_HIGHER: | |
16006 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
16007 | case BFD_RELOC_MICROMIPS_JALR: | |
16008 | case BFD_RELOC_MICROMIPS_HI16: | |
16009 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 16010 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
16011 | case BFD_RELOC_MICROMIPS_GPREL16: |
16012 | case BFD_RELOC_MICROMIPS_LITERAL: | |
16013 | case BFD_RELOC_MICROMIPS_CALL16: | |
16014 | case BFD_RELOC_MICROMIPS_GOT16: | |
16015 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
16016 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
16017 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
16018 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 16019 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
16020 | if (fixP->fx_done) |
16021 | { | |
16022 | offsetT value; | |
16023 | ||
16024 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
16025 | { | |
16026 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
16027 | if (mips16_reloc_p (fixP->fx_r_type)) | |
16028 | insn |= mips16_immed_extend (value, 16); | |
16029 | else | |
16030 | insn |= (value & 0xffff); | |
16031 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
16032 | } | |
16033 | else | |
16034 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16035 | _("Unsupported constant in relocation")); | |
16036 | } | |
252b5132 RH |
16037 | break; |
16038 | ||
252b5132 RH |
16039 | case BFD_RELOC_64: |
16040 | /* This is handled like BFD_RELOC_32, but we output a sign | |
16041 | extended value if we are only 32 bits. */ | |
3e722fb5 | 16042 | if (fixP->fx_done) |
252b5132 RH |
16043 | { |
16044 | if (8 <= sizeof (valueT)) | |
4d68580a | 16045 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
16046 | else |
16047 | { | |
a7ebbfdf | 16048 | valueT hiv; |
252b5132 | 16049 | |
a7ebbfdf | 16050 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
16051 | hiv = 0xffffffff; |
16052 | else | |
16053 | hiv = 0; | |
4d68580a RS |
16054 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
16055 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
16056 | } |
16057 | } | |
16058 | break; | |
16059 | ||
056350c6 | 16060 | case BFD_RELOC_RVA: |
252b5132 | 16061 | case BFD_RELOC_32: |
b47468a6 | 16062 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
16063 | case BFD_RELOC_16: |
16064 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
16065 | value now. This can happen if we have a .word which is not |
16066 | resolved when it appears but is later defined. */ | |
252b5132 | 16067 | if (fixP->fx_done) |
4d68580a | 16068 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
16069 | break; |
16070 | ||
252b5132 | 16071 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 16072 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 16073 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 16074 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 16075 | |
54f4ddb3 TS |
16076 | /* We need to save the bits in the instruction since fixup_segment() |
16077 | might be deleting the relocation entry (i.e., a branch within | |
16078 | the current segment). */ | |
a7ebbfdf | 16079 | if (! fixP->fx_done) |
bb2d6cd7 | 16080 | break; |
252b5132 | 16081 | |
54f4ddb3 | 16082 | /* Update old instruction data. */ |
4d68580a | 16083 | insn = read_insn (buf); |
252b5132 | 16084 | |
a7ebbfdf TS |
16085 | if (*valP + 0x20000 <= 0x3ffff) |
16086 | { | |
16087 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16088 | write_insn (buf, insn); |
a7ebbfdf TS |
16089 | } |
16090 | else if (mips_pic == NO_PIC | |
16091 | && fixP->fx_done | |
16092 | && fixP->fx_frag->fr_address >= text_section->vma | |
16093 | && (fixP->fx_frag->fr_address | |
587aac4e | 16094 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
16095 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16096 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16097 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16098 | { |
16099 | /* The branch offset is too large. If this is an | |
16100 | unconditional branch, and we are not generating PIC code, | |
16101 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16102 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16103 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16104 | else |
a7ebbfdf TS |
16105 | insn = 0x08000000; /* j */ |
16106 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16107 | fixP->fx_done = 0; | |
16108 | fixP->fx_addsy = section_symbol (text_section); | |
16109 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16110 | write_insn (buf, insn); |
a7ebbfdf TS |
16111 | } |
16112 | else | |
16113 | { | |
16114 | /* If we got here, we have branch-relaxation disabled, | |
16115 | and there's nothing we can do to fix this instruction | |
16116 | without turning it into a longer sequence. */ | |
16117 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16118 | _("Branch out of range")); | |
252b5132 | 16119 | } |
252b5132 RH |
16120 | break; |
16121 | ||
df58fc94 RS |
16122 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16123 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16124 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
16125 | /* We adjust the offset back to even. */ | |
16126 | if ((*valP & 0x1) != 0) | |
16127 | --(*valP); | |
16128 | ||
16129 | if (! fixP->fx_done) | |
16130 | break; | |
16131 | ||
16132 | /* Should never visit here, because we keep the relocation. */ | |
16133 | abort (); | |
16134 | break; | |
16135 | ||
252b5132 RH |
16136 | case BFD_RELOC_VTABLE_INHERIT: |
16137 | fixP->fx_done = 0; | |
16138 | if (fixP->fx_addsy | |
16139 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16140 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16141 | S_SET_WEAK (fixP->fx_addsy); | |
16142 | break; | |
16143 | ||
16144 | case BFD_RELOC_VTABLE_ENTRY: | |
16145 | fixP->fx_done = 0; | |
16146 | break; | |
16147 | ||
16148 | default: | |
b37df7c4 | 16149 | abort (); |
252b5132 | 16150 | } |
a7ebbfdf TS |
16151 | |
16152 | /* Remember value for tc_gen_reloc. */ | |
16153 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16154 | } |
16155 | ||
252b5132 | 16156 | static symbolS * |
17a2f251 | 16157 | get_symbol (void) |
252b5132 RH |
16158 | { |
16159 | int c; | |
16160 | char *name; | |
16161 | symbolS *p; | |
16162 | ||
16163 | name = input_line_pointer; | |
16164 | c = get_symbol_end (); | |
16165 | p = (symbolS *) symbol_find_or_make (name); | |
16166 | *input_line_pointer = c; | |
16167 | return p; | |
16168 | } | |
16169 | ||
742a56fe RS |
16170 | /* Align the current frag to a given power of two. If a particular |
16171 | fill byte should be used, FILL points to an integer that contains | |
16172 | that byte, otherwise FILL is null. | |
16173 | ||
462427c4 RS |
16174 | This function used to have the comment: |
16175 | ||
16176 | The MIPS assembler also automatically adjusts any preceding label. | |
16177 | ||
16178 | The implementation therefore applied the adjustment to a maximum of | |
16179 | one label. However, other label adjustments are applied to batches | |
16180 | of labels, and adjusting just one caused problems when new labels | |
16181 | were added for the sake of debugging or unwind information. | |
16182 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16183 | |
16184 | static void | |
462427c4 | 16185 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16186 | { |
7d10b47d | 16187 | mips_emit_delays (); |
df58fc94 | 16188 | mips_record_compressed_mode (); |
742a56fe RS |
16189 | if (fill == NULL && subseg_text_p (now_seg)) |
16190 | frag_align_code (to, 0); | |
16191 | else | |
16192 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16193 | record_alignment (now_seg, to); |
462427c4 | 16194 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16195 | } |
16196 | ||
16197 | /* Align to a given power of two. .align 0 turns off the automatic | |
16198 | alignment used by the data creating pseudo-ops. */ | |
16199 | ||
16200 | static void | |
17a2f251 | 16201 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16202 | { |
742a56fe | 16203 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16204 | long max_alignment = 28; |
252b5132 | 16205 | |
54f4ddb3 | 16206 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16207 | to the aligned address. |
54f4ddb3 | 16208 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16209 | a .align pseudo instruction. |
54f4ddb3 | 16210 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16211 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16212 | We don't. */ |
252b5132 RH |
16213 | |
16214 | temp = get_absolute_expression (); | |
16215 | if (temp > max_alignment) | |
16216 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16217 | else if (temp < 0) | |
16218 | { | |
16219 | as_warn (_("Alignment negative: 0 assumed.")); | |
16220 | temp = 0; | |
16221 | } | |
16222 | if (*input_line_pointer == ',') | |
16223 | { | |
f9419b05 | 16224 | ++input_line_pointer; |
742a56fe RS |
16225 | fill_value = get_absolute_expression (); |
16226 | fill_ptr = &fill_value; | |
252b5132 RH |
16227 | } |
16228 | else | |
742a56fe | 16229 | fill_ptr = 0; |
252b5132 RH |
16230 | if (temp) |
16231 | { | |
a8dbcb85 TS |
16232 | segment_info_type *si = seg_info (now_seg); |
16233 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16234 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16235 | auto_align = 1; |
462427c4 | 16236 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16237 | } |
16238 | else | |
16239 | { | |
16240 | auto_align = 0; | |
16241 | } | |
16242 | ||
16243 | demand_empty_rest_of_line (); | |
16244 | } | |
16245 | ||
252b5132 | 16246 | static void |
17a2f251 | 16247 | s_change_sec (int sec) |
252b5132 RH |
16248 | { |
16249 | segT seg; | |
16250 | ||
252b5132 RH |
16251 | #ifdef OBJ_ELF |
16252 | /* The ELF backend needs to know that we are changing sections, so | |
16253 | that .previous works correctly. We could do something like check | |
b6ff326e | 16254 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16255 | as it would not be appropriate to use it in the section changing |
16256 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16257 | This should be cleaner, somehow. */ | |
f43abd2b TS |
16258 | if (IS_ELF) |
16259 | obj_elf_section_change_hook (); | |
252b5132 RH |
16260 | #endif |
16261 | ||
7d10b47d | 16262 | mips_emit_delays (); |
6a32d874 | 16263 | |
252b5132 RH |
16264 | switch (sec) |
16265 | { | |
16266 | case 't': | |
16267 | s_text (0); | |
16268 | break; | |
16269 | case 'd': | |
16270 | s_data (0); | |
16271 | break; | |
16272 | case 'b': | |
16273 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16274 | demand_empty_rest_of_line (); | |
16275 | break; | |
16276 | ||
16277 | case 'r': | |
4d0d148d TS |
16278 | seg = subseg_new (RDATA_SECTION_NAME, |
16279 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16280 | if (IS_ELF) |
252b5132 | 16281 | { |
4d0d148d TS |
16282 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16283 | | SEC_READONLY | SEC_RELOC | |
16284 | | SEC_DATA)); | |
c41e87e3 | 16285 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16286 | record_alignment (seg, 4); |
252b5132 | 16287 | } |
4d0d148d | 16288 | demand_empty_rest_of_line (); |
252b5132 RH |
16289 | break; |
16290 | ||
16291 | case 's': | |
4d0d148d | 16292 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16293 | if (IS_ELF) |
252b5132 | 16294 | { |
4d0d148d TS |
16295 | bfd_set_section_flags (stdoutput, seg, |
16296 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16297 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16298 | record_alignment (seg, 4); |
252b5132 | 16299 | } |
4d0d148d TS |
16300 | demand_empty_rest_of_line (); |
16301 | break; | |
998b3c36 MR |
16302 | |
16303 | case 'B': | |
16304 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16305 | if (IS_ELF) | |
16306 | { | |
16307 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16308 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16309 | record_alignment (seg, 4); | |
16310 | } | |
16311 | demand_empty_rest_of_line (); | |
16312 | break; | |
252b5132 RH |
16313 | } |
16314 | ||
16315 | auto_align = 1; | |
16316 | } | |
b34976b6 | 16317 | |
cca86cc8 | 16318 | void |
17a2f251 | 16319 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16320 | { |
7ed4a06a | 16321 | #ifdef OBJ_ELF |
cca86cc8 SC |
16322 | char *section_name; |
16323 | char c; | |
684022ea | 16324 | char next_c = 0; |
cca86cc8 SC |
16325 | int section_type; |
16326 | int section_flag; | |
16327 | int section_entry_size; | |
16328 | int section_alignment; | |
b34976b6 | 16329 | |
f43abd2b | 16330 | if (!IS_ELF) |
7ed4a06a TS |
16331 | return; |
16332 | ||
cca86cc8 SC |
16333 | section_name = input_line_pointer; |
16334 | c = get_symbol_end (); | |
a816d1ed AO |
16335 | if (c) |
16336 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16337 | |
4cf0dd0d TS |
16338 | /* Do we have .section Name<,"flags">? */ |
16339 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16340 | { |
4cf0dd0d TS |
16341 | /* just after name is now '\0'. */ |
16342 | *input_line_pointer = c; | |
cca86cc8 SC |
16343 | input_line_pointer = section_name; |
16344 | obj_elf_section (ignore); | |
16345 | return; | |
16346 | } | |
16347 | input_line_pointer++; | |
16348 | ||
16349 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16350 | if (c == ',') | |
16351 | section_type = get_absolute_expression (); | |
16352 | else | |
16353 | section_type = 0; | |
16354 | if (*input_line_pointer++ == ',') | |
16355 | section_flag = get_absolute_expression (); | |
16356 | else | |
16357 | section_flag = 0; | |
16358 | if (*input_line_pointer++ == ',') | |
16359 | section_entry_size = get_absolute_expression (); | |
16360 | else | |
16361 | section_entry_size = 0; | |
16362 | if (*input_line_pointer++ == ',') | |
16363 | section_alignment = get_absolute_expression (); | |
16364 | else | |
16365 | section_alignment = 0; | |
87975d2a AM |
16366 | /* FIXME: really ignore? */ |
16367 | (void) section_alignment; | |
cca86cc8 | 16368 | |
a816d1ed AO |
16369 | section_name = xstrdup (section_name); |
16370 | ||
8ab8a5c8 RS |
16371 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16372 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16373 | traditionally had to fall back on the more common @progbits instead. | |
16374 | ||
16375 | There's nothing really harmful in this, since bfd will correct | |
16376 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16377 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16378 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16379 | ||
16380 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16381 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16382 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16383 | generic type-checking code. */ | |
16384 | if (section_type == SHT_MIPS_DWARF) | |
16385 | section_type = SHT_PROGBITS; | |
16386 | ||
cca86cc8 SC |
16387 | obj_elf_change_section (section_name, section_type, section_flag, |
16388 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16389 | |
16390 | if (now_seg->name != section_name) | |
16391 | free (section_name); | |
7ed4a06a | 16392 | #endif /* OBJ_ELF */ |
cca86cc8 | 16393 | } |
252b5132 RH |
16394 | |
16395 | void | |
17a2f251 | 16396 | mips_enable_auto_align (void) |
252b5132 RH |
16397 | { |
16398 | auto_align = 1; | |
16399 | } | |
16400 | ||
16401 | static void | |
17a2f251 | 16402 | s_cons (int log_size) |
252b5132 | 16403 | { |
a8dbcb85 TS |
16404 | segment_info_type *si = seg_info (now_seg); |
16405 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16406 | |
7d10b47d | 16407 | mips_emit_delays (); |
252b5132 | 16408 | if (log_size > 0 && auto_align) |
462427c4 | 16409 | mips_align (log_size, 0, l); |
252b5132 | 16410 | cons (1 << log_size); |
a1facbec | 16411 | mips_clear_insn_labels (); |
252b5132 RH |
16412 | } |
16413 | ||
16414 | static void | |
17a2f251 | 16415 | s_float_cons (int type) |
252b5132 | 16416 | { |
a8dbcb85 TS |
16417 | segment_info_type *si = seg_info (now_seg); |
16418 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16419 | |
7d10b47d | 16420 | mips_emit_delays (); |
252b5132 RH |
16421 | |
16422 | if (auto_align) | |
49309057 ILT |
16423 | { |
16424 | if (type == 'd') | |
462427c4 | 16425 | mips_align (3, 0, l); |
49309057 | 16426 | else |
462427c4 | 16427 | mips_align (2, 0, l); |
49309057 | 16428 | } |
252b5132 | 16429 | |
252b5132 | 16430 | float_cons (type); |
a1facbec | 16431 | mips_clear_insn_labels (); |
252b5132 RH |
16432 | } |
16433 | ||
16434 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16435 | permitted to say | |
16436 | .globl foo .text | |
16437 | where foo is an undefined symbol, to mean that foo should be | |
16438 | considered to be the address of a function. */ | |
16439 | ||
16440 | static void | |
17a2f251 | 16441 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16442 | { |
16443 | char *name; | |
16444 | int c; | |
16445 | symbolS *symbolP; | |
16446 | flagword flag; | |
16447 | ||
8a06b769 | 16448 | do |
252b5132 | 16449 | { |
8a06b769 | 16450 | name = input_line_pointer; |
252b5132 | 16451 | c = get_symbol_end (); |
8a06b769 TS |
16452 | symbolP = symbol_find_or_make (name); |
16453 | S_SET_EXTERNAL (symbolP); | |
16454 | ||
252b5132 | 16455 | *input_line_pointer = c; |
8a06b769 | 16456 | SKIP_WHITESPACE (); |
252b5132 | 16457 | |
8a06b769 TS |
16458 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16459 | being a function is apparently labelled as being an object. */ | |
16460 | flag = BSF_OBJECT; | |
252b5132 | 16461 | |
8a06b769 TS |
16462 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16463 | && (*input_line_pointer != ',')) | |
16464 | { | |
16465 | char *secname; | |
16466 | asection *sec; | |
16467 | ||
16468 | secname = input_line_pointer; | |
16469 | c = get_symbol_end (); | |
16470 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16471 | if (sec == NULL) | |
16472 | as_bad (_("%s: no such section"), secname); | |
16473 | *input_line_pointer = c; | |
16474 | ||
16475 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16476 | flag = BSF_FUNCTION; | |
16477 | } | |
16478 | ||
16479 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16480 | ||
16481 | c = *input_line_pointer; | |
16482 | if (c == ',') | |
16483 | { | |
16484 | input_line_pointer++; | |
16485 | SKIP_WHITESPACE (); | |
16486 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16487 | c = '\n'; | |
16488 | } | |
16489 | } | |
16490 | while (c == ','); | |
252b5132 | 16491 | |
252b5132 RH |
16492 | demand_empty_rest_of_line (); |
16493 | } | |
16494 | ||
16495 | static void | |
17a2f251 | 16496 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16497 | { |
16498 | char *opt; | |
16499 | char c; | |
16500 | ||
16501 | opt = input_line_pointer; | |
16502 | c = get_symbol_end (); | |
16503 | ||
16504 | if (*opt == 'O') | |
16505 | { | |
16506 | /* FIXME: What does this mean? */ | |
16507 | } | |
16508 | else if (strncmp (opt, "pic", 3) == 0) | |
16509 | { | |
16510 | int i; | |
16511 | ||
16512 | i = atoi (opt + 3); | |
16513 | if (i == 0) | |
16514 | mips_pic = NO_PIC; | |
16515 | else if (i == 2) | |
143d77c5 | 16516 | { |
8b828383 | 16517 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16518 | mips_abicalls = TRUE; |
16519 | } | |
252b5132 RH |
16520 | else |
16521 | as_bad (_(".option pic%d not supported"), i); | |
16522 | ||
4d0d148d | 16523 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16524 | { |
16525 | if (g_switch_seen && g_switch_value != 0) | |
16526 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16527 | g_switch_value = 0; | |
16528 | bfd_set_gp_size (stdoutput, 0); | |
16529 | } | |
16530 | } | |
16531 | else | |
16532 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16533 | ||
16534 | *input_line_pointer = c; | |
16535 | demand_empty_rest_of_line (); | |
16536 | } | |
16537 | ||
16538 | /* This structure is used to hold a stack of .set values. */ | |
16539 | ||
e972090a NC |
16540 | struct mips_option_stack |
16541 | { | |
252b5132 RH |
16542 | struct mips_option_stack *next; |
16543 | struct mips_set_options options; | |
16544 | }; | |
16545 | ||
16546 | static struct mips_option_stack *mips_opts_stack; | |
16547 | ||
16548 | /* Handle the .set pseudo-op. */ | |
16549 | ||
16550 | static void | |
17a2f251 | 16551 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16552 | { |
16553 | char *name = input_line_pointer, ch; | |
16554 | ||
16555 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16556 | ++input_line_pointer; |
252b5132 RH |
16557 | ch = *input_line_pointer; |
16558 | *input_line_pointer = '\0'; | |
16559 | ||
16560 | if (strcmp (name, "reorder") == 0) | |
16561 | { | |
7d10b47d RS |
16562 | if (mips_opts.noreorder) |
16563 | end_noreorder (); | |
252b5132 RH |
16564 | } |
16565 | else if (strcmp (name, "noreorder") == 0) | |
16566 | { | |
7d10b47d RS |
16567 | if (!mips_opts.noreorder) |
16568 | start_noreorder (); | |
252b5132 | 16569 | } |
741fe287 MR |
16570 | else if (strncmp (name, "at=", 3) == 0) |
16571 | { | |
16572 | char *s = name + 3; | |
16573 | ||
16574 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16575 | as_bad (_("Unrecognized register name `%s'"), s); | |
16576 | } | |
252b5132 RH |
16577 | else if (strcmp (name, "at") == 0) |
16578 | { | |
741fe287 | 16579 | mips_opts.at = ATREG; |
252b5132 RH |
16580 | } |
16581 | else if (strcmp (name, "noat") == 0) | |
16582 | { | |
741fe287 | 16583 | mips_opts.at = ZERO; |
252b5132 RH |
16584 | } |
16585 | else if (strcmp (name, "macro") == 0) | |
16586 | { | |
16587 | mips_opts.warn_about_macros = 0; | |
16588 | } | |
16589 | else if (strcmp (name, "nomacro") == 0) | |
16590 | { | |
16591 | if (mips_opts.noreorder == 0) | |
16592 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16593 | mips_opts.warn_about_macros = 1; | |
16594 | } | |
16595 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16596 | { | |
16597 | mips_opts.nomove = 0; | |
16598 | } | |
16599 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16600 | { | |
16601 | mips_opts.nomove = 1; | |
16602 | } | |
16603 | else if (strcmp (name, "bopt") == 0) | |
16604 | { | |
16605 | mips_opts.nobopt = 0; | |
16606 | } | |
16607 | else if (strcmp (name, "nobopt") == 0) | |
16608 | { | |
16609 | mips_opts.nobopt = 1; | |
16610 | } | |
ad3fea08 TS |
16611 | else if (strcmp (name, "gp=default") == 0) |
16612 | mips_opts.gp32 = file_mips_gp32; | |
16613 | else if (strcmp (name, "gp=32") == 0) | |
16614 | mips_opts.gp32 = 1; | |
16615 | else if (strcmp (name, "gp=64") == 0) | |
16616 | { | |
16617 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16618 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16619 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16620 | mips_opts.gp32 = 0; | |
16621 | } | |
16622 | else if (strcmp (name, "fp=default") == 0) | |
16623 | mips_opts.fp32 = file_mips_fp32; | |
16624 | else if (strcmp (name, "fp=32") == 0) | |
16625 | mips_opts.fp32 = 1; | |
16626 | else if (strcmp (name, "fp=64") == 0) | |
16627 | { | |
16628 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16629 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16630 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16631 | mips_opts.fp32 = 0; | |
16632 | } | |
037b32b9 AN |
16633 | else if (strcmp (name, "softfloat") == 0) |
16634 | mips_opts.soft_float = 1; | |
16635 | else if (strcmp (name, "hardfloat") == 0) | |
16636 | mips_opts.soft_float = 0; | |
16637 | else if (strcmp (name, "singlefloat") == 0) | |
16638 | mips_opts.single_float = 1; | |
16639 | else if (strcmp (name, "doublefloat") == 0) | |
16640 | mips_opts.single_float = 0; | |
252b5132 RH |
16641 | else if (strcmp (name, "mips16") == 0 |
16642 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16643 | { |
16644 | if (mips_opts.micromips == 1) | |
16645 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16646 | mips_opts.mips16 = 1; | |
16647 | } | |
252b5132 RH |
16648 | else if (strcmp (name, "nomips16") == 0 |
16649 | || strcmp (name, "noMIPS-16") == 0) | |
16650 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16651 | else if (strcmp (name, "micromips") == 0) |
16652 | { | |
16653 | if (mips_opts.mips16 == 1) | |
16654 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16655 | mips_opts.micromips = 1; | |
16656 | } | |
16657 | else if (strcmp (name, "nomicromips") == 0) | |
16658 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16659 | else if (strcmp (name, "smartmips") == 0) |
16660 | { | |
ad3fea08 | 16661 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16662 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16663 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16664 | mips_opts.ase_smartmips = 1; | |
16665 | } | |
16666 | else if (strcmp (name, "nosmartmips") == 0) | |
16667 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16668 | else if (strcmp (name, "mips3d") == 0) |
16669 | mips_opts.ase_mips3d = 1; | |
16670 | else if (strcmp (name, "nomips3d") == 0) | |
16671 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16672 | else if (strcmp (name, "mdmx") == 0) |
16673 | mips_opts.ase_mdmx = 1; | |
16674 | else if (strcmp (name, "nomdmx") == 0) | |
16675 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16676 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16677 | { |
16678 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16679 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16680 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16681 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16682 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16683 | } |
74cd071d | 16684 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16685 | { |
16686 | mips_opts.ase_dsp = 0; | |
16687 | mips_opts.ase_dspr2 = 0; | |
16688 | } | |
16689 | else if (strcmp (name, "dspr2") == 0) | |
16690 | { | |
16691 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16692 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16693 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16694 | mips_opts.ase_dspr2 = 1; | |
16695 | mips_opts.ase_dsp = 1; | |
16696 | } | |
16697 | else if (strcmp (name, "nodspr2") == 0) | |
16698 | { | |
16699 | mips_opts.ase_dspr2 = 0; | |
16700 | mips_opts.ase_dsp = 0; | |
16701 | } | |
7f3c4072 CM |
16702 | else if (strcmp (name, "eva") == 0) |
16703 | { | |
16704 | if (!ISA_SUPPORTS_EVA_ASE) | |
16705 | as_warn (_("%s ISA does not support EVA ASE"), | |
16706 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
16707 | mips_opts.ase_eva = 1; | |
16708 | } | |
16709 | else if (strcmp (name, "noeva") == 0) | |
16710 | mips_opts.ase_eva = 0; | |
ef2e4d86 | 16711 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16712 | { |
16713 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16714 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16715 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16716 | mips_opts.ase_mt = 1; | |
16717 | } | |
ef2e4d86 CF |
16718 | else if (strcmp (name, "nomt") == 0) |
16719 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16720 | else if (strcmp (name, "mcu") == 0) |
16721 | mips_opts.ase_mcu = 1; | |
16722 | else if (strcmp (name, "nomcu") == 0) | |
16723 | mips_opts.ase_mcu = 0; | |
b015e599 AP |
16724 | else if (strcmp (name, "virt") == 0) |
16725 | { | |
16726 | if (!ISA_SUPPORTS_VIRT_ASE) | |
16727 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
16728 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
16729 | mips_opts.ase_virt = 1; | |
16730 | } | |
16731 | else if (strcmp (name, "novirt") == 0) | |
16732 | mips_opts.ase_virt = 0; | |
1a2c1fad | 16733 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16734 | { |
af7ee8bf | 16735 | int reset = 0; |
252b5132 | 16736 | |
1a2c1fad CD |
16737 | /* Permit the user to change the ISA and architecture on the fly. |
16738 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16739 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16740 | { |
16741 | reset = 1; | |
16742 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16743 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16744 | } |
16745 | else if (strncmp (name, "arch=", 5) == 0) | |
16746 | { | |
16747 | const struct mips_cpu_info *p; | |
16748 | ||
16749 | p = mips_parse_cpu("internal use", name + 5); | |
16750 | if (!p) | |
16751 | as_bad (_("unknown architecture %s"), name + 5); | |
16752 | else | |
16753 | { | |
16754 | mips_opts.arch = p->cpu; | |
16755 | mips_opts.isa = p->isa; | |
16756 | } | |
16757 | } | |
81a21e38 TS |
16758 | else if (strncmp (name, "mips", 4) == 0) |
16759 | { | |
16760 | const struct mips_cpu_info *p; | |
16761 | ||
16762 | p = mips_parse_cpu("internal use", name); | |
16763 | if (!p) | |
16764 | as_bad (_("unknown ISA level %s"), name + 4); | |
16765 | else | |
16766 | { | |
16767 | mips_opts.arch = p->cpu; | |
16768 | mips_opts.isa = p->isa; | |
16769 | } | |
16770 | } | |
af7ee8bf | 16771 | else |
81a21e38 | 16772 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16773 | |
16774 | switch (mips_opts.isa) | |
98d3f06f KH |
16775 | { |
16776 | case 0: | |
98d3f06f | 16777 | break; |
af7ee8bf CD |
16778 | case ISA_MIPS1: |
16779 | case ISA_MIPS2: | |
16780 | case ISA_MIPS32: | |
16781 | case ISA_MIPS32R2: | |
98d3f06f KH |
16782 | mips_opts.gp32 = 1; |
16783 | mips_opts.fp32 = 1; | |
16784 | break; | |
af7ee8bf CD |
16785 | case ISA_MIPS3: |
16786 | case ISA_MIPS4: | |
16787 | case ISA_MIPS5: | |
16788 | case ISA_MIPS64: | |
5f74bc13 | 16789 | case ISA_MIPS64R2: |
98d3f06f | 16790 | mips_opts.gp32 = 0; |
e407c74b NC |
16791 | if (mips_opts.arch == CPU_R5900) |
16792 | { | |
16793 | mips_opts.fp32 = 1; | |
16794 | } | |
16795 | else | |
16796 | { | |
98d3f06f | 16797 | mips_opts.fp32 = 0; |
e407c74b | 16798 | } |
98d3f06f KH |
16799 | break; |
16800 | default: | |
16801 | as_bad (_("unknown ISA level %s"), name + 4); | |
16802 | break; | |
16803 | } | |
af7ee8bf | 16804 | if (reset) |
98d3f06f | 16805 | { |
af7ee8bf CD |
16806 | mips_opts.gp32 = file_mips_gp32; |
16807 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16808 | } |
252b5132 RH |
16809 | } |
16810 | else if (strcmp (name, "autoextend") == 0) | |
16811 | mips_opts.noautoextend = 0; | |
16812 | else if (strcmp (name, "noautoextend") == 0) | |
16813 | mips_opts.noautoextend = 1; | |
16814 | else if (strcmp (name, "push") == 0) | |
16815 | { | |
16816 | struct mips_option_stack *s; | |
16817 | ||
16818 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16819 | s->next = mips_opts_stack; | |
16820 | s->options = mips_opts; | |
16821 | mips_opts_stack = s; | |
16822 | } | |
16823 | else if (strcmp (name, "pop") == 0) | |
16824 | { | |
16825 | struct mips_option_stack *s; | |
16826 | ||
16827 | s = mips_opts_stack; | |
16828 | if (s == NULL) | |
16829 | as_bad (_(".set pop with no .set push")); | |
16830 | else | |
16831 | { | |
16832 | /* If we're changing the reorder mode we need to handle | |
16833 | delay slots correctly. */ | |
16834 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16835 | start_noreorder (); |
252b5132 | 16836 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16837 | end_noreorder (); |
252b5132 RH |
16838 | |
16839 | mips_opts = s->options; | |
16840 | mips_opts_stack = s->next; | |
16841 | free (s); | |
16842 | } | |
16843 | } | |
aed1a261 RS |
16844 | else if (strcmp (name, "sym32") == 0) |
16845 | mips_opts.sym32 = TRUE; | |
16846 | else if (strcmp (name, "nosym32") == 0) | |
16847 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16848 | else if (strchr (name, ',')) |
16849 | { | |
16850 | /* Generic ".set" directive; use the generic handler. */ | |
16851 | *input_line_pointer = ch; | |
16852 | input_line_pointer = name; | |
16853 | s_set (0); | |
16854 | return; | |
16855 | } | |
252b5132 RH |
16856 | else |
16857 | { | |
16858 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16859 | } | |
16860 | *input_line_pointer = ch; | |
16861 | demand_empty_rest_of_line (); | |
16862 | } | |
16863 | ||
16864 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16865 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16866 | ||
16867 | static void | |
17a2f251 | 16868 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16869 | { |
16870 | mips_pic = SVR4_PIC; | |
143d77c5 | 16871 | mips_abicalls = TRUE; |
4d0d148d TS |
16872 | |
16873 | if (g_switch_seen && g_switch_value != 0) | |
16874 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16875 | g_switch_value = 0; | |
16876 | ||
252b5132 RH |
16877 | bfd_set_gp_size (stdoutput, 0); |
16878 | demand_empty_rest_of_line (); | |
16879 | } | |
16880 | ||
16881 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16882 | PIC code. It sets the $gp register for the function based on the | |
16883 | function address, which is in the register named in the argument. | |
16884 | This uses a relocation against _gp_disp, which is handled specially | |
16885 | by the linker. The result is: | |
16886 | lui $gp,%hi(_gp_disp) | |
16887 | addiu $gp,$gp,%lo(_gp_disp) | |
16888 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16889 | The .cpload argument is normally $25 == $t9. |
16890 | ||
16891 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16892 | lui $gp,%hi(__gnu_local_gp) |
16893 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16894 | and the argument is ignored. This saves an instruction, but the |
16895 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16896 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16897 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16898 | |
16899 | static void | |
17a2f251 | 16900 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16901 | { |
16902 | expressionS ex; | |
aa6975fb ILT |
16903 | int reg; |
16904 | int in_shared; | |
252b5132 | 16905 | |
6478892d TS |
16906 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16907 | .cpload is ignored. */ | |
16908 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16909 | { |
16910 | s_ignore (0); | |
16911 | return; | |
16912 | } | |
16913 | ||
a276b80c MR |
16914 | if (mips_opts.mips16) |
16915 | { | |
16916 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16917 | ignore_rest_of_line (); | |
16918 | return; | |
16919 | } | |
16920 | ||
d3ecfc59 | 16921 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16922 | if (mips_opts.noreorder == 0) |
16923 | as_warn (_(".cpload not in noreorder section")); | |
16924 | ||
aa6975fb ILT |
16925 | reg = tc_get_register (0); |
16926 | ||
16927 | /* If we need to produce a 64-bit address, we are better off using | |
16928 | the default instruction sequence. */ | |
aed1a261 | 16929 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16930 | |
252b5132 | 16931 | ex.X_op = O_symbol; |
bbe506e8 TS |
16932 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16933 | "__gnu_local_gp"); | |
252b5132 RH |
16934 | ex.X_op_symbol = NULL; |
16935 | ex.X_add_number = 0; | |
16936 | ||
16937 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16938 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16939 | |
8a75745d MR |
16940 | mips_mark_labels (); |
16941 | mips_assembling_insn = TRUE; | |
16942 | ||
584892a6 | 16943 | macro_start (); |
67c0d1eb RS |
16944 | macro_build_lui (&ex, mips_gp_register); |
16945 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16946 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16947 | if (in_shared) |
16948 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16949 | mips_gp_register, reg); | |
584892a6 | 16950 | macro_end (); |
252b5132 | 16951 | |
8a75745d | 16952 | mips_assembling_insn = FALSE; |
252b5132 RH |
16953 | demand_empty_rest_of_line (); |
16954 | } | |
16955 | ||
6478892d TS |
16956 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16957 | .cpsetup $reg1, offset|$reg2, label | |
16958 | ||
16959 | If offset is given, this results in: | |
16960 | sd $gp, offset($sp) | |
956cd1d6 | 16961 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16962 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16963 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16964 | |
16965 | If $reg2 is given, this results in: | |
16966 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16967 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16968 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16969 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16970 | $reg1 is normally $25 == $t9. |
16971 | ||
16972 | The -mno-shared option replaces the last three instructions with | |
16973 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16974 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16975 | |
6478892d | 16976 | static void |
17a2f251 | 16977 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16978 | { |
16979 | expressionS ex_off; | |
16980 | expressionS ex_sym; | |
16981 | int reg1; | |
6478892d | 16982 | |
8586fc66 | 16983 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16984 | We also need NewABI support. */ |
16985 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16986 | { | |
16987 | s_ignore (0); | |
16988 | return; | |
16989 | } | |
16990 | ||
a276b80c MR |
16991 | if (mips_opts.mips16) |
16992 | { | |
16993 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16994 | ignore_rest_of_line (); | |
16995 | return; | |
16996 | } | |
16997 | ||
6478892d TS |
16998 | reg1 = tc_get_register (0); |
16999 | SKIP_WHITESPACE (); | |
17000 | if (*input_line_pointer != ',') | |
17001 | { | |
17002 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17003 | return; | |
17004 | } | |
17005 | else | |
80245285 | 17006 | ++input_line_pointer; |
6478892d TS |
17007 | SKIP_WHITESPACE (); |
17008 | if (*input_line_pointer == '$') | |
80245285 TS |
17009 | { |
17010 | mips_cpreturn_register = tc_get_register (0); | |
17011 | mips_cpreturn_offset = -1; | |
17012 | } | |
6478892d | 17013 | else |
80245285 TS |
17014 | { |
17015 | mips_cpreturn_offset = get_absolute_expression (); | |
17016 | mips_cpreturn_register = -1; | |
17017 | } | |
6478892d TS |
17018 | SKIP_WHITESPACE (); |
17019 | if (*input_line_pointer != ',') | |
17020 | { | |
17021 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17022 | return; | |
17023 | } | |
17024 | else | |
f9419b05 | 17025 | ++input_line_pointer; |
6478892d | 17026 | SKIP_WHITESPACE (); |
f21f8242 | 17027 | expression (&ex_sym); |
6478892d | 17028 | |
8a75745d MR |
17029 | mips_mark_labels (); |
17030 | mips_assembling_insn = TRUE; | |
17031 | ||
584892a6 | 17032 | macro_start (); |
6478892d TS |
17033 | if (mips_cpreturn_register == -1) |
17034 | { | |
17035 | ex_off.X_op = O_constant; | |
17036 | ex_off.X_add_symbol = NULL; | |
17037 | ex_off.X_op_symbol = NULL; | |
17038 | ex_off.X_add_number = mips_cpreturn_offset; | |
17039 | ||
67c0d1eb | 17040 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 17041 | BFD_RELOC_LO16, SP); |
6478892d TS |
17042 | } |
17043 | else | |
67c0d1eb | 17044 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 17045 | mips_gp_register, 0); |
6478892d | 17046 | |
aed1a261 | 17047 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 17048 | { |
df58fc94 | 17049 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
17050 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
17051 | BFD_RELOC_HI16_S); | |
17052 | ||
17053 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
17054 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
17055 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
17056 | ||
17057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
17058 | mips_gp_register, reg1); | |
17059 | } | |
17060 | else | |
17061 | { | |
17062 | expressionS ex; | |
17063 | ||
17064 | ex.X_op = O_symbol; | |
4184909a | 17065 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
17066 | ex.X_op_symbol = NULL; |
17067 | ex.X_add_number = 0; | |
6e1304d8 | 17068 | |
aa6975fb ILT |
17069 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
17070 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
17071 | ||
17072 | macro_build_lui (&ex, mips_gp_register); | |
17073 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17074 | mips_gp_register, BFD_RELOC_LO16); | |
17075 | } | |
f21f8242 | 17076 | |
584892a6 | 17077 | macro_end (); |
6478892d | 17078 | |
8a75745d | 17079 | mips_assembling_insn = FALSE; |
6478892d TS |
17080 | demand_empty_rest_of_line (); |
17081 | } | |
17082 | ||
17083 | static void | |
17a2f251 | 17084 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17085 | { |
17086 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 17087 | .cplocal is ignored. */ |
6478892d TS |
17088 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17089 | { | |
17090 | s_ignore (0); | |
17091 | return; | |
17092 | } | |
17093 | ||
a276b80c MR |
17094 | if (mips_opts.mips16) |
17095 | { | |
17096 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17097 | ignore_rest_of_line (); | |
17098 | return; | |
17099 | } | |
17100 | ||
6478892d | 17101 | mips_gp_register = tc_get_register (0); |
85b51719 | 17102 | demand_empty_rest_of_line (); |
6478892d TS |
17103 | } |
17104 | ||
252b5132 RH |
17105 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17106 | offset from $sp. The offset is remembered, and after making a PIC | |
17107 | call $gp is restored from that location. */ | |
17108 | ||
17109 | static void | |
17a2f251 | 17110 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17111 | { |
17112 | expressionS ex; | |
252b5132 | 17113 | |
6478892d | 17114 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17115 | .cprestore is ignored. */ |
6478892d | 17116 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17117 | { |
17118 | s_ignore (0); | |
17119 | return; | |
17120 | } | |
17121 | ||
a276b80c MR |
17122 | if (mips_opts.mips16) |
17123 | { | |
17124 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17125 | ignore_rest_of_line (); | |
17126 | return; | |
17127 | } | |
17128 | ||
252b5132 | 17129 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17130 | mips_cprestore_valid = 1; |
252b5132 RH |
17131 | |
17132 | ex.X_op = O_constant; | |
17133 | ex.X_add_symbol = NULL; | |
17134 | ex.X_op_symbol = NULL; | |
17135 | ex.X_add_number = mips_cprestore_offset; | |
17136 | ||
8a75745d MR |
17137 | mips_mark_labels (); |
17138 | mips_assembling_insn = TRUE; | |
17139 | ||
584892a6 | 17140 | macro_start (); |
67c0d1eb RS |
17141 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17142 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17143 | macro_end (); |
252b5132 | 17144 | |
8a75745d | 17145 | mips_assembling_insn = FALSE; |
252b5132 RH |
17146 | demand_empty_rest_of_line (); |
17147 | } | |
17148 | ||
6478892d | 17149 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17150 | was given in the preceding .cpsetup, it results in: |
6478892d | 17151 | ld $gp, offset($sp) |
76b3015f | 17152 | |
6478892d | 17153 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
17154 | daddu $gp, $reg2, $0 */ |
17155 | ||
6478892d | 17156 | static void |
17a2f251 | 17157 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17158 | { |
17159 | expressionS ex; | |
6478892d TS |
17160 | |
17161 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
17162 | We also need NewABI support. */ | |
17163 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17164 | { | |
17165 | s_ignore (0); | |
17166 | return; | |
17167 | } | |
17168 | ||
a276b80c MR |
17169 | if (mips_opts.mips16) |
17170 | { | |
17171 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17172 | ignore_rest_of_line (); | |
17173 | return; | |
17174 | } | |
17175 | ||
8a75745d MR |
17176 | mips_mark_labels (); |
17177 | mips_assembling_insn = TRUE; | |
17178 | ||
584892a6 | 17179 | macro_start (); |
6478892d TS |
17180 | if (mips_cpreturn_register == -1) |
17181 | { | |
17182 | ex.X_op = O_constant; | |
17183 | ex.X_add_symbol = NULL; | |
17184 | ex.X_op_symbol = NULL; | |
17185 | ex.X_add_number = mips_cpreturn_offset; | |
17186 | ||
67c0d1eb | 17187 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17188 | } |
17189 | else | |
67c0d1eb | 17190 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 17191 | mips_cpreturn_register, 0); |
584892a6 | 17192 | macro_end (); |
6478892d | 17193 | |
8a75745d | 17194 | mips_assembling_insn = FALSE; |
6478892d TS |
17195 | demand_empty_rest_of_line (); |
17196 | } | |
17197 | ||
d0f13682 CLT |
17198 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17199 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17200 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17201 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17202 | |
17203 | static void | |
d0f13682 CLT |
17204 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17205 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17206 | { |
17207 | expressionS ex; | |
17208 | char *p; | |
17209 | ||
17210 | expression (&ex); | |
17211 | ||
17212 | if (ex.X_op != O_symbol) | |
17213 | { | |
d0f13682 | 17214 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17215 | ignore_rest_of_line (); |
17216 | } | |
17217 | ||
17218 | p = frag_more (bytes); | |
17219 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17220 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17221 | demand_empty_rest_of_line (); |
de64cffd | 17222 | mips_clear_insn_labels (); |
741d6ea8 JM |
17223 | } |
17224 | ||
17225 | /* Handle .dtprelword. */ | |
17226 | ||
17227 | static void | |
17228 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17229 | { | |
d0f13682 | 17230 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17231 | } |
17232 | ||
17233 | /* Handle .dtpreldword. */ | |
17234 | ||
17235 | static void | |
17236 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17237 | { | |
d0f13682 CLT |
17238 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17239 | } | |
17240 | ||
17241 | /* Handle .tprelword. */ | |
17242 | ||
17243 | static void | |
17244 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17245 | { | |
17246 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17247 | } | |
17248 | ||
17249 | /* Handle .tpreldword. */ | |
17250 | ||
17251 | static void | |
17252 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17253 | { | |
17254 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17255 | } |
17256 | ||
6478892d TS |
17257 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17258 | code. It sets the offset to use in gp_rel relocations. */ | |
17259 | ||
17260 | static void | |
17a2f251 | 17261 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17262 | { |
17263 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17264 | We also need NewABI support. */ | |
17265 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17266 | { | |
17267 | s_ignore (0); | |
17268 | return; | |
17269 | } | |
17270 | ||
def2e0dd | 17271 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17272 | |
17273 | demand_empty_rest_of_line (); | |
17274 | } | |
17275 | ||
252b5132 RH |
17276 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17277 | code. It generates a 32 bit GP relative reloc. */ | |
17278 | ||
17279 | static void | |
17a2f251 | 17280 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17281 | { |
a8dbcb85 TS |
17282 | segment_info_type *si; |
17283 | struct insn_label_list *l; | |
252b5132 RH |
17284 | expressionS ex; |
17285 | char *p; | |
17286 | ||
17287 | /* When not generating PIC code, this is treated as .word. */ | |
17288 | if (mips_pic != SVR4_PIC) | |
17289 | { | |
17290 | s_cons (2); | |
17291 | return; | |
17292 | } | |
17293 | ||
a8dbcb85 TS |
17294 | si = seg_info (now_seg); |
17295 | l = si->label_list; | |
7d10b47d | 17296 | mips_emit_delays (); |
252b5132 | 17297 | if (auto_align) |
462427c4 | 17298 | mips_align (2, 0, l); |
252b5132 RH |
17299 | |
17300 | expression (&ex); | |
a1facbec | 17301 | mips_clear_insn_labels (); |
252b5132 RH |
17302 | |
17303 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17304 | { | |
17305 | as_bad (_("Unsupported use of .gpword")); | |
17306 | ignore_rest_of_line (); | |
17307 | } | |
17308 | ||
17309 | p = frag_more (4); | |
17a2f251 | 17310 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17311 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17312 | BFD_RELOC_GPREL32); |
252b5132 RH |
17313 | |
17314 | demand_empty_rest_of_line (); | |
17315 | } | |
17316 | ||
10181a0d | 17317 | static void |
17a2f251 | 17318 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17319 | { |
a8dbcb85 TS |
17320 | segment_info_type *si; |
17321 | struct insn_label_list *l; | |
10181a0d AO |
17322 | expressionS ex; |
17323 | char *p; | |
17324 | ||
17325 | /* When not generating PIC code, this is treated as .dword. */ | |
17326 | if (mips_pic != SVR4_PIC) | |
17327 | { | |
17328 | s_cons (3); | |
17329 | return; | |
17330 | } | |
17331 | ||
a8dbcb85 TS |
17332 | si = seg_info (now_seg); |
17333 | l = si->label_list; | |
7d10b47d | 17334 | mips_emit_delays (); |
10181a0d | 17335 | if (auto_align) |
462427c4 | 17336 | mips_align (3, 0, l); |
10181a0d AO |
17337 | |
17338 | expression (&ex); | |
a1facbec | 17339 | mips_clear_insn_labels (); |
10181a0d AO |
17340 | |
17341 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17342 | { | |
17343 | as_bad (_("Unsupported use of .gpdword")); | |
17344 | ignore_rest_of_line (); | |
17345 | } | |
17346 | ||
17347 | p = frag_more (8); | |
17a2f251 | 17348 | md_number_to_chars (p, 0, 8); |
a105a300 | 17349 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17350 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17351 | |
17352 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17353 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17354 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17355 | |
17356 | demand_empty_rest_of_line (); | |
17357 | } | |
17358 | ||
a3f278e2 CM |
17359 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17360 | tables. It generates a R_MIPS_EH reloc. */ | |
17361 | ||
17362 | static void | |
17363 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17364 | { | |
17365 | expressionS ex; | |
17366 | char *p; | |
17367 | ||
17368 | mips_emit_delays (); | |
17369 | ||
17370 | expression (&ex); | |
17371 | mips_clear_insn_labels (); | |
17372 | ||
17373 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17374 | { | |
17375 | as_bad (_("Unsupported use of .ehword")); | |
17376 | ignore_rest_of_line (); | |
17377 | } | |
17378 | ||
17379 | p = frag_more (4); | |
17380 | md_number_to_chars (p, 0, 4); | |
17381 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17382 | BFD_RELOC_MIPS_EH); | |
17383 | ||
17384 | demand_empty_rest_of_line (); | |
17385 | } | |
17386 | ||
252b5132 RH |
17387 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17388 | tables in SVR4 PIC code. */ | |
17389 | ||
17390 | static void | |
17a2f251 | 17391 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17392 | { |
252b5132 RH |
17393 | int reg; |
17394 | ||
10181a0d AO |
17395 | /* This is ignored when not generating SVR4 PIC code. */ |
17396 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17397 | { |
17398 | s_ignore (0); | |
17399 | return; | |
17400 | } | |
17401 | ||
8a75745d MR |
17402 | mips_mark_labels (); |
17403 | mips_assembling_insn = TRUE; | |
17404 | ||
252b5132 | 17405 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17406 | macro_start (); |
252b5132 | 17407 | reg = tc_get_register (0); |
67c0d1eb | 17408 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17409 | macro_end (); |
252b5132 | 17410 | |
8a75745d | 17411 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17412 | demand_empty_rest_of_line (); |
252b5132 RH |
17413 | } |
17414 | ||
17415 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17416 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17417 | such as generating jalx instructions when needed. We also make |
17418 | them odd for the duration of the assembly, in order to generate the | |
17419 | right sort of code. We will make them even in the adjust_symtab | |
17420 | routine, while leaving them marked. This is convenient for the | |
17421 | debugger and the disassembler. The linker knows to make them odd | |
17422 | again. */ | |
17423 | ||
17424 | static void | |
17a2f251 | 17425 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17426 | { |
df58fc94 | 17427 | mips_mark_labels (); |
252b5132 RH |
17428 | |
17429 | demand_empty_rest_of_line (); | |
17430 | } | |
17431 | ||
754e2bb9 RS |
17432 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17433 | implemented in a transparent way, so that removing them would not | |
17434 | have any effect on the generated instructions. However, s_stab | |
17435 | internally changes the section, so in practice we need to decide | |
17436 | now whether the preceding label marks compressed code. We do not | |
17437 | support changing the compression mode of a label after a .stab* | |
17438 | directive, such as in: | |
17439 | ||
17440 | foo: | |
17441 | .stabs ... | |
17442 | .set mips16 | |
17443 | ||
17444 | so the current mode wins. */ | |
252b5132 RH |
17445 | |
17446 | static void | |
17a2f251 | 17447 | s_mips_stab (int type) |
252b5132 | 17448 | { |
754e2bb9 | 17449 | mips_mark_labels (); |
252b5132 RH |
17450 | s_stab (type); |
17451 | } | |
17452 | ||
54f4ddb3 | 17453 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17454 | |
17455 | static void | |
17a2f251 | 17456 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17457 | { |
17458 | char *name; | |
17459 | int c; | |
17460 | symbolS *symbolP; | |
17461 | expressionS exp; | |
17462 | ||
17463 | name = input_line_pointer; | |
17464 | c = get_symbol_end (); | |
17465 | symbolP = symbol_find_or_make (name); | |
17466 | S_SET_WEAK (symbolP); | |
17467 | *input_line_pointer = c; | |
17468 | ||
17469 | SKIP_WHITESPACE (); | |
17470 | ||
17471 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17472 | { | |
17473 | if (S_IS_DEFINED (symbolP)) | |
17474 | { | |
20203fb9 | 17475 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17476 | S_GET_NAME (symbolP)); |
17477 | ignore_rest_of_line (); | |
17478 | return; | |
17479 | } | |
bdaaa2e1 | 17480 | |
252b5132 RH |
17481 | if (*input_line_pointer == ',') |
17482 | { | |
17483 | ++input_line_pointer; | |
17484 | SKIP_WHITESPACE (); | |
17485 | } | |
bdaaa2e1 | 17486 | |
252b5132 RH |
17487 | expression (&exp); |
17488 | if (exp.X_op != O_symbol) | |
17489 | { | |
20203fb9 | 17490 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17491 | ignore_rest_of_line (); |
252b5132 RH |
17492 | return; |
17493 | } | |
49309057 | 17494 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17495 | } |
17496 | ||
17497 | demand_empty_rest_of_line (); | |
17498 | } | |
17499 | ||
17500 | /* Parse a register string into a number. Called from the ECOFF code | |
17501 | to parse .frame. The argument is non-zero if this is the frame | |
17502 | register, so that we can record it in mips_frame_reg. */ | |
17503 | ||
17504 | int | |
17a2f251 | 17505 | tc_get_register (int frame) |
252b5132 | 17506 | { |
707bfff6 | 17507 | unsigned int reg; |
252b5132 RH |
17508 | |
17509 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17510 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17511 | reg = 0; | |
252b5132 | 17512 | if (frame) |
7a621144 DJ |
17513 | { |
17514 | mips_frame_reg = reg != 0 ? reg : SP; | |
17515 | mips_frame_reg_valid = 1; | |
17516 | mips_cprestore_valid = 0; | |
17517 | } | |
252b5132 RH |
17518 | return reg; |
17519 | } | |
17520 | ||
17521 | valueT | |
17a2f251 | 17522 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17523 | { |
17524 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17525 | ||
b4c71f56 TS |
17526 | if (IS_ELF) |
17527 | { | |
17528 | /* We don't need to align ELF sections to the full alignment. | |
17529 | However, Irix 5 may prefer that we align them at least to a 16 | |
17530 | byte boundary. We don't bother to align the sections if we | |
17531 | are targeted for an embedded system. */ | |
c41e87e3 | 17532 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17533 | return addr; |
17534 | if (align > 4) | |
17535 | align = 4; | |
17536 | } | |
252b5132 RH |
17537 | |
17538 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17539 | } | |
17540 | ||
17541 | /* Utility routine, called from above as well. If called while the | |
17542 | input file is still being read, it's only an approximation. (For | |
17543 | example, a symbol may later become defined which appeared to be | |
17544 | undefined earlier.) */ | |
17545 | ||
17546 | static int | |
17a2f251 | 17547 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17548 | { |
17549 | if (sym == 0) | |
17550 | return 0; | |
17551 | ||
4d0d148d | 17552 | if (g_switch_value > 0) |
252b5132 RH |
17553 | { |
17554 | const char *symname; | |
17555 | int change; | |
17556 | ||
c9914766 | 17557 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17558 | register. It can be if it is smaller than the -G size or if |
17559 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17560 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17561 | they can. */ |
17562 | symname = S_GET_NAME (sym); | |
17563 | if (symname != (const char *) NULL | |
17564 | && (strcmp (symname, "eprol") == 0 | |
17565 | || strcmp (symname, "etext") == 0 | |
17566 | || strcmp (symname, "_gp") == 0 | |
17567 | || strcmp (symname, "edata") == 0 | |
17568 | || strcmp (symname, "_fbss") == 0 | |
17569 | || strcmp (symname, "_fdata") == 0 | |
17570 | || strcmp (symname, "_ftext") == 0 | |
17571 | || strcmp (symname, "end") == 0 | |
17572 | || strcmp (symname, "_gp_disp") == 0)) | |
17573 | change = 1; | |
17574 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17575 | && (0 | |
17576 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17577 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17578 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17579 | <= g_switch_value)) | |
252b5132 RH |
17580 | #endif |
17581 | /* We must defer this decision until after the whole | |
17582 | file has been read, since there might be a .extern | |
17583 | after the first use of this symbol. */ | |
17584 | || (before_relaxing | |
17585 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17586 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17587 | #endif |
17588 | && S_GET_VALUE (sym) == 0) | |
17589 | || (S_GET_VALUE (sym) != 0 | |
17590 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17591 | change = 0; | |
17592 | else | |
17593 | { | |
17594 | const char *segname; | |
17595 | ||
17596 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17597 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17598 | && strcmp (segname, ".lit4") != 0); |
17599 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17600 | && strcmp (segname, ".sbss") != 0 |
17601 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17602 | && strncmp (segname, ".sbss.", 6) != 0 |
17603 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17604 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17605 | } |
17606 | return change; | |
17607 | } | |
17608 | else | |
c9914766 | 17609 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17610 | return 1; |
17611 | } | |
17612 | ||
5919d012 RS |
17613 | |
17614 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17615 | ||
17616 | static bfd_boolean | |
17a2f251 | 17617 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17618 | { |
17619 | asection *symsec; | |
5919d012 RS |
17620 | |
17621 | /* Handle the case of a symbol equated to another symbol. */ | |
17622 | while (symbol_equated_reloc_p (sym)) | |
17623 | { | |
17624 | symbolS *n; | |
17625 | ||
5f0fe04b | 17626 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17627 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17628 | if (n == sym) | |
17629 | break; | |
17630 | sym = n; | |
17631 | } | |
17632 | ||
df1f3cda DD |
17633 | if (symbol_section_p (sym)) |
17634 | return TRUE; | |
17635 | ||
5919d012 RS |
17636 | symsec = S_GET_SEGMENT (sym); |
17637 | ||
5919d012 | 17638 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17639 | return (!bfd_is_und_section (symsec) |
17640 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17641 | && !bfd_is_com_section (symsec) |
17642 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17643 | #ifdef OBJ_ELF |
17644 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17645 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17646 | #endif |
17647 | ); | |
17648 | } | |
17649 | ||
17650 | ||
252b5132 RH |
17651 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17652 | extended opcode. SEC is the section the frag is in. */ | |
17653 | ||
17654 | static int | |
17a2f251 | 17655 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17656 | { |
17657 | int type; | |
3994f87e | 17658 | const struct mips16_immed_operand *op; |
252b5132 RH |
17659 | offsetT val; |
17660 | int mintiny, maxtiny; | |
17661 | segT symsec; | |
98aa84af | 17662 | fragS *sym_frag; |
252b5132 RH |
17663 | |
17664 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17665 | return 0; | |
17666 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17667 | return 1; | |
17668 | ||
17669 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17670 | op = mips16_immed_operands; | |
17671 | while (op->type != type) | |
17672 | { | |
17673 | ++op; | |
9c2799c2 | 17674 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17675 | } |
17676 | ||
17677 | if (op->unsp) | |
17678 | { | |
17679 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17680 | { | |
17681 | mintiny = 1; | |
17682 | maxtiny = 1 << op->nbits; | |
17683 | } | |
17684 | else | |
17685 | { | |
17686 | mintiny = 0; | |
17687 | maxtiny = (1 << op->nbits) - 1; | |
17688 | } | |
17689 | } | |
17690 | else | |
17691 | { | |
17692 | mintiny = - (1 << (op->nbits - 1)); | |
17693 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17694 | } | |
17695 | ||
98aa84af | 17696 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17697 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17698 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17699 | |
17700 | if (op->pcrel) | |
17701 | { | |
17702 | addressT addr; | |
17703 | ||
17704 | /* We won't have the section when we are called from | |
17705 | mips_relax_frag. However, we will always have been called | |
17706 | from md_estimate_size_before_relax first. If this is a | |
17707 | branch to a different section, we mark it as such. If SEC is | |
17708 | NULL, and the frag is not marked, then it must be a branch to | |
17709 | the same section. */ | |
17710 | if (sec == NULL) | |
17711 | { | |
17712 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17713 | return 1; | |
17714 | } | |
17715 | else | |
17716 | { | |
98aa84af | 17717 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17718 | if (symsec != sec) |
17719 | { | |
17720 | fragp->fr_subtype = | |
17721 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17722 | ||
17723 | /* FIXME: We should support this, and let the linker | |
17724 | catch branches and loads that are out of range. */ | |
17725 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17726 | _("unsupported PC relative reference to different section")); | |
17727 | ||
17728 | return 1; | |
17729 | } | |
98aa84af AM |
17730 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17731 | /* Assume non-extended on the first relaxation pass. | |
17732 | The address we have calculated will be bogus if this is | |
17733 | a forward branch to another frag, as the forward frag | |
17734 | will have fr_address == 0. */ | |
17735 | return 0; | |
252b5132 RH |
17736 | } |
17737 | ||
17738 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17739 | the same section. If the relax_marker of the symbol fragment |
17740 | differs from the relax_marker of this fragment, we have not | |
17741 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17742 | in STRETCH in order to get a better estimate of the address. |
17743 | This particularly matters because of the shift bits. */ | |
17744 | if (stretch != 0 | |
98aa84af | 17745 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17746 | { |
17747 | fragS *f; | |
17748 | ||
17749 | /* Adjust stretch for any alignment frag. Note that if have | |
17750 | been expanding the earlier code, the symbol may be | |
17751 | defined in what appears to be an earlier frag. FIXME: | |
17752 | This doesn't handle the fr_subtype field, which specifies | |
17753 | a maximum number of bytes to skip when doing an | |
17754 | alignment. */ | |
98aa84af | 17755 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17756 | { |
17757 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17758 | { | |
17759 | if (stretch < 0) | |
17760 | stretch = - ((- stretch) | |
17761 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17762 | else | |
17763 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17764 | if (stretch == 0) | |
17765 | break; | |
17766 | } | |
17767 | } | |
17768 | if (f != NULL) | |
17769 | val += stretch; | |
17770 | } | |
17771 | ||
17772 | addr = fragp->fr_address + fragp->fr_fix; | |
17773 | ||
17774 | /* The base address rules are complicated. The base address of | |
17775 | a branch is the following instruction. The base address of a | |
17776 | PC relative load or add is the instruction itself, but if it | |
17777 | is in a delay slot (in which case it can not be extended) use | |
17778 | the address of the instruction whose delay slot it is in. */ | |
17779 | if (type == 'p' || type == 'q') | |
17780 | { | |
17781 | addr += 2; | |
17782 | ||
17783 | /* If we are currently assuming that this frag should be | |
17784 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17785 | higher. */ |
252b5132 RH |
17786 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17787 | addr += 2; | |
17788 | ||
17789 | /* Ignore the low bit in the target, since it will be set | |
17790 | for a text label. */ | |
17791 | if ((val & 1) != 0) | |
17792 | --val; | |
17793 | } | |
17794 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17795 | addr -= 4; | |
17796 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17797 | addr -= 2; | |
17798 | ||
17799 | val -= addr & ~ ((1 << op->shift) - 1); | |
17800 | ||
17801 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17802 | if (type == 'p' || type == 'q') | |
17803 | val /= 2; | |
17804 | ||
17805 | /* If any of the shifted bits are set, we must use an extended | |
17806 | opcode. If the address depends on the size of this | |
17807 | instruction, this can lead to a loop, so we arrange to always | |
17808 | use an extended opcode. We only check this when we are in | |
17809 | the main relaxation loop, when SEC is NULL. */ | |
17810 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17811 | { | |
17812 | fragp->fr_subtype = | |
17813 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17814 | return 1; | |
17815 | } | |
17816 | ||
17817 | /* If we are about to mark a frag as extended because the value | |
17818 | is precisely maxtiny + 1, then there is a chance of an | |
17819 | infinite loop as in the following code: | |
17820 | la $4,foo | |
17821 | .skip 1020 | |
17822 | .align 2 | |
17823 | foo: | |
17824 | In this case when the la is extended, foo is 0x3fc bytes | |
17825 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17826 | the la must be extended. To avoid this loop, we mark the | |
17827 | frag as extended if it was small, and is about to become | |
17828 | extended with a value of maxtiny + 1. */ | |
17829 | if (val == ((maxtiny + 1) << op->shift) | |
17830 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17831 | && sec == NULL) | |
17832 | { | |
17833 | fragp->fr_subtype = | |
17834 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17835 | return 1; | |
17836 | } | |
17837 | } | |
17838 | else if (symsec != absolute_section && sec != NULL) | |
17839 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17840 | ||
17841 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17842 | || val < (mintiny << op->shift) | |
17843 | || val > (maxtiny << op->shift)) | |
17844 | return 1; | |
17845 | else | |
17846 | return 0; | |
17847 | } | |
17848 | ||
4a6a3df4 AO |
17849 | /* Compute the length of a branch sequence, and adjust the |
17850 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17851 | worst-case length is computed, with UPDATE being used to indicate | |
17852 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17853 | branch is to be computed. */ | |
17854 | static int | |
17a2f251 | 17855 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17856 | { |
b34976b6 | 17857 | bfd_boolean toofar; |
4a6a3df4 AO |
17858 | int length; |
17859 | ||
17860 | if (fragp | |
17861 | && S_IS_DEFINED (fragp->fr_symbol) | |
17862 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17863 | { | |
17864 | addressT addr; | |
17865 | offsetT val; | |
17866 | ||
17867 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17868 | ||
17869 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17870 | ||
17871 | val -= addr; | |
17872 | ||
17873 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17874 | } | |
17875 | else if (fragp) | |
17876 | /* If the symbol is not defined or it's in a different segment, | |
17877 | assume the user knows what's going on and emit a short | |
17878 | branch. */ | |
b34976b6 | 17879 | toofar = FALSE; |
4a6a3df4 | 17880 | else |
b34976b6 | 17881 | toofar = TRUE; |
4a6a3df4 AO |
17882 | |
17883 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17884 | fragp->fr_subtype | |
66b3e8da MR |
17885 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17886 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17887 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17888 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17889 | toofar); | |
17890 | ||
17891 | length = 4; | |
17892 | if (toofar) | |
17893 | { | |
17894 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17895 | length += 8; | |
17896 | ||
17897 | if (mips_pic != NO_PIC) | |
17898 | { | |
17899 | /* Additional space for PIC loading of target address. */ | |
17900 | length += 8; | |
17901 | if (mips_opts.isa == ISA_MIPS1) | |
17902 | /* Additional space for $at-stabilizing nop. */ | |
17903 | length += 4; | |
17904 | } | |
17905 | ||
17906 | /* If branch is conditional. */ | |
17907 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17908 | length += 8; | |
17909 | } | |
b34976b6 | 17910 | |
4a6a3df4 AO |
17911 | return length; |
17912 | } | |
17913 | ||
df58fc94 RS |
17914 | /* Compute the length of a branch sequence, and adjust the |
17915 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17916 | worst-case length is computed, with UPDATE being used to indicate | |
17917 | whether an unconditional (-1), or regular (0) branch is to be | |
17918 | computed. */ | |
17919 | ||
17920 | static int | |
17921 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17922 | { | |
17923 | bfd_boolean toofar; | |
17924 | int length; | |
17925 | ||
17926 | if (fragp | |
17927 | && S_IS_DEFINED (fragp->fr_symbol) | |
17928 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17929 | { | |
17930 | addressT addr; | |
17931 | offsetT val; | |
17932 | ||
17933 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17934 | /* Ignore the low bit in the target, since it will be set | |
17935 | for a text label. */ | |
17936 | if ((val & 1) != 0) | |
17937 | --val; | |
17938 | ||
17939 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17940 | ||
17941 | val -= addr; | |
17942 | ||
17943 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17944 | } | |
17945 | else if (fragp) | |
17946 | /* If the symbol is not defined or it's in a different segment, | |
17947 | assume the user knows what's going on and emit a short | |
17948 | branch. */ | |
17949 | toofar = FALSE; | |
17950 | else | |
17951 | toofar = TRUE; | |
17952 | ||
17953 | if (fragp && update | |
17954 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17955 | fragp->fr_subtype = (toofar | |
17956 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17957 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17958 | ||
17959 | length = 4; | |
17960 | if (toofar) | |
17961 | { | |
17962 | bfd_boolean compact_known = fragp != NULL; | |
17963 | bfd_boolean compact = FALSE; | |
17964 | bfd_boolean uncond; | |
17965 | ||
17966 | if (compact_known) | |
17967 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17968 | if (fragp) | |
17969 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17970 | else | |
17971 | uncond = update < 0; | |
17972 | ||
17973 | /* If label is out of range, we turn branch <br>: | |
17974 | ||
17975 | <br> label # 4 bytes | |
17976 | 0: | |
17977 | ||
17978 | into: | |
17979 | ||
17980 | j label # 4 bytes | |
17981 | nop # 2 bytes if compact && !PIC | |
17982 | 0: | |
17983 | */ | |
17984 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17985 | length += 2; | |
17986 | ||
17987 | /* If assembling PIC code, we further turn: | |
17988 | ||
17989 | j label # 4 bytes | |
17990 | ||
17991 | into: | |
17992 | ||
17993 | lw/ld at, %got(label)(gp) # 4 bytes | |
17994 | d/addiu at, %lo(label) # 4 bytes | |
17995 | jr/c at # 2 bytes | |
17996 | */ | |
17997 | if (mips_pic != NO_PIC) | |
17998 | length += 6; | |
17999 | ||
18000 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
18001 | ||
18002 | <brneg> 0f # 4 bytes | |
18003 | nop # 2 bytes if !compact | |
18004 | */ | |
18005 | if (!uncond) | |
18006 | length += (compact_known && compact) ? 4 : 6; | |
18007 | } | |
18008 | ||
18009 | return length; | |
18010 | } | |
18011 | ||
18012 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
18013 | bit accordingly. */ | |
18014 | ||
18015 | static int | |
18016 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
18017 | { | |
18018 | bfd_boolean toofar; | |
18019 | ||
df58fc94 RS |
18020 | if (fragp |
18021 | && S_IS_DEFINED (fragp->fr_symbol) | |
18022 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
18023 | { | |
18024 | addressT addr; | |
18025 | offsetT val; | |
18026 | int type; | |
18027 | ||
18028 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18029 | /* Ignore the low bit in the target, since it will be set | |
18030 | for a text label. */ | |
18031 | if ((val & 1) != 0) | |
18032 | --val; | |
18033 | ||
18034 | /* Assume this is a 2-byte branch. */ | |
18035 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
18036 | ||
18037 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
18038 | long branches. */ | |
18039 | ||
18040 | val -= addr; | |
18041 | ||
18042 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
18043 | if (type == 'D') | |
18044 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
18045 | else if (type == 'E') | |
18046 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
18047 | else | |
18048 | abort (); | |
18049 | } | |
18050 | else | |
18051 | /* If the symbol is not defined or it's in a different segment, | |
18052 | we emit a normal 32-bit branch. */ | |
18053 | toofar = TRUE; | |
18054 | ||
18055 | if (fragp && update | |
18056 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18057 | fragp->fr_subtype | |
18058 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
18059 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
18060 | ||
18061 | if (toofar) | |
18062 | return 4; | |
18063 | ||
18064 | return 2; | |
18065 | } | |
18066 | ||
252b5132 RH |
18067 | /* Estimate the size of a frag before relaxing. Unless this is the |
18068 | mips16, we are not really relaxing here, and the final size is | |
18069 | encoded in the subtype information. For the mips16, we have to | |
18070 | decide whether we are using an extended opcode or not. */ | |
18071 | ||
252b5132 | 18072 | int |
17a2f251 | 18073 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 18074 | { |
5919d012 | 18075 | int change; |
252b5132 | 18076 | |
4a6a3df4 AO |
18077 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18078 | { | |
18079 | ||
b34976b6 AM |
18080 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18081 | ||
4a6a3df4 AO |
18082 | return fragp->fr_var; |
18083 | } | |
18084 | ||
252b5132 | 18085 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
18086 | /* We don't want to modify the EXTENDED bit here; it might get us |
18087 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18088 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 18089 | |
df58fc94 RS |
18090 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18091 | { | |
18092 | int length = 4; | |
18093 | ||
18094 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18095 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18096 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18097 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18098 | fragp->fr_var = length; | |
18099 | ||
18100 | return length; | |
18101 | } | |
18102 | ||
252b5132 | 18103 | if (mips_pic == NO_PIC) |
5919d012 | 18104 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 18105 | else if (mips_pic == SVR4_PIC) |
5919d012 | 18106 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
18107 | else if (mips_pic == VXWORKS_PIC) |
18108 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
18109 | change = 0; | |
252b5132 RH |
18110 | else |
18111 | abort (); | |
18112 | ||
18113 | if (change) | |
18114 | { | |
4d7206a2 | 18115 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18116 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18117 | } |
4d7206a2 RS |
18118 | else |
18119 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18120 | } |
18121 | ||
18122 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18123 | should be converted into a reloc against a section. */ |
252b5132 RH |
18124 | |
18125 | int | |
17a2f251 | 18126 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18127 | { |
252b5132 RH |
18128 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18129 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18130 | return 0; | |
a161fe53 | 18131 | |
252b5132 RH |
18132 | if (fixp->fx_addsy == NULL) |
18133 | return 1; | |
a161fe53 | 18134 | |
de7e6852 RS |
18135 | /* If symbol SYM is in a mergeable section, relocations of the form |
18136 | SYM + 0 can usually be made section-relative. The mergeable data | |
18137 | is then identified by the section offset rather than by the symbol. | |
18138 | ||
18139 | However, if we're generating REL LO16 relocations, the offset is split | |
18140 | between the LO16 and parterning high part relocation. The linker will | |
18141 | need to recalculate the complete offset in order to correctly identify | |
18142 | the merge data. | |
18143 | ||
18144 | The linker has traditionally not looked for the parterning high part | |
18145 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
18146 | placed anywhere. Rather than break backwards compatibility by changing | |
18147 | this, it seems better not to force the issue, and instead keep the | |
18148 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18149 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18150 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18151 | && HAVE_IN_PLACE_ADDENDS |
18152 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18153 | return 0; | |
18154 | ||
ce70d90a | 18155 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
18156 | Likewise an in-range offset of limited PC-relative relocations may |
18157 | overflow the in-place relocatable field if recalculated against the | |
18158 | start address of the symbol's containing section. */ | |
ce70d90a | 18159 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
18160 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
18161 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
18162 | return 0; |
18163 | ||
252b5132 | 18164 | #ifdef OBJ_ELF |
b314ec0e RS |
18165 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18166 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18167 | relocations against MIPS16 functions; in this case, the stub becomes | |
18168 | the function's canonical address. | |
18169 | ||
18170 | Floating-point stubs are stored in unique .mips16.call.* or | |
18171 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18172 | the first relocation in section S must be against F; this is how the | |
18173 | linker determines the target function. All relocations that might | |
18174 | resolve to T must also be against F. We therefore have the following | |
18175 | restrictions, which are given in an intentionally-redundant way: | |
18176 | ||
18177 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18178 | symbols. | |
18179 | ||
18180 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18181 | if that stub might be used. | |
18182 | ||
18183 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18184 | symbols. | |
18185 | ||
18186 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18187 | that stub might be used. | |
18188 | ||
18189 | There is a further restriction: | |
18190 | ||
df58fc94 RS |
18191 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
18192 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
18193 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
18194 | encode the low bit. |
18195 | ||
df58fc94 RS |
18196 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
18197 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
18198 | such relocations on REL targets. | |
b314ec0e RS |
18199 | |
18200 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18201 | relocation against some symbol R, no relocation against R may be | |
18202 | reduced. (Note that this deals with (2) as well as (1) because | |
18203 | relocations against global symbols will never be reduced on ELF | |
18204 | targets.) This approach is a little simpler than trying to detect | |
18205 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18206 | that we have for MIPS16 symbols. */ | |
f43abd2b | 18207 | if (IS_ELF |
b314ec0e | 18208 | && fixp->fx_subsy == NULL |
30c09090 | 18209 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
18210 | || *symbol_get_tc (fixp->fx_addsy) |
18211 | || (HAVE_IN_PLACE_ADDENDS | |
18212 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
18213 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
18214 | return 0; |
18215 | #endif | |
a161fe53 | 18216 | |
252b5132 RH |
18217 | return 1; |
18218 | } | |
18219 | ||
18220 | /* Translate internal representation of relocation info to BFD target | |
18221 | format. */ | |
18222 | ||
18223 | arelent ** | |
17a2f251 | 18224 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18225 | { |
18226 | static arelent *retval[4]; | |
18227 | arelent *reloc; | |
18228 | bfd_reloc_code_real_type code; | |
18229 | ||
4b0cff4e TS |
18230 | memset (retval, 0, sizeof(retval)); |
18231 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18232 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18233 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18234 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18235 | ||
bad36eac DJ |
18236 | if (fixp->fx_pcrel) |
18237 | { | |
df58fc94 RS |
18238 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18239 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18240 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18241 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18242 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18243 | |
18244 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18245 | Relocations want only the symbol offset. */ | |
18246 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 18247 | if (!IS_ELF) |
bad36eac DJ |
18248 | { |
18249 | /* A gruesome hack which is a result of the gruesome gas | |
18250 | reloc handling. What's worse, for COFF (as opposed to | |
18251 | ECOFF), we might need yet another copy of reloc->address. | |
18252 | See bfd_install_relocation. */ | |
18253 | reloc->addend += reloc->address; | |
18254 | } | |
18255 | } | |
18256 | else | |
18257 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18258 | |
438c16b8 TS |
18259 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18260 | entry to be used in the relocation's section offset. */ | |
18261 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18262 | { |
18263 | reloc->address = reloc->addend; | |
18264 | reloc->addend = 0; | |
18265 | } | |
18266 | ||
252b5132 | 18267 | code = fixp->fx_r_type; |
252b5132 | 18268 | |
bad36eac | 18269 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18270 | if (reloc->howto == NULL) |
18271 | { | |
18272 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18273 | _("Can not represent %s relocation in this object file format"), | |
18274 | bfd_get_reloc_code_name (code)); | |
18275 | retval[0] = NULL; | |
18276 | } | |
18277 | ||
18278 | return retval; | |
18279 | } | |
18280 | ||
18281 | /* Relax a machine dependent frag. This returns the amount by which | |
18282 | the current size of the frag should change. */ | |
18283 | ||
18284 | int | |
17a2f251 | 18285 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18286 | { |
4a6a3df4 AO |
18287 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18288 | { | |
18289 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18290 | |
18291 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18292 | |
18293 | return fragp->fr_var - old_var; | |
18294 | } | |
18295 | ||
df58fc94 RS |
18296 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18297 | { | |
18298 | offsetT old_var = fragp->fr_var; | |
18299 | offsetT new_var = 4; | |
18300 | ||
18301 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18302 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18303 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18304 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18305 | fragp->fr_var = new_var; | |
18306 | ||
18307 | return new_var - old_var; | |
18308 | } | |
18309 | ||
252b5132 RH |
18310 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18311 | return 0; | |
18312 | ||
c4e7957c | 18313 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18314 | { |
18315 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18316 | return 0; | |
18317 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18318 | return 2; | |
18319 | } | |
18320 | else | |
18321 | { | |
18322 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18323 | return 0; | |
18324 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18325 | return -2; | |
18326 | } | |
18327 | ||
18328 | return 0; | |
18329 | } | |
18330 | ||
18331 | /* Convert a machine dependent frag. */ | |
18332 | ||
18333 | void | |
17a2f251 | 18334 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18335 | { |
4a6a3df4 AO |
18336 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18337 | { | |
4d68580a | 18338 | char *buf; |
4a6a3df4 AO |
18339 | unsigned long insn; |
18340 | expressionS exp; | |
18341 | fixS *fixp; | |
b34976b6 | 18342 | |
4d68580a RS |
18343 | buf = fragp->fr_literal + fragp->fr_fix; |
18344 | insn = read_insn (buf); | |
b34976b6 | 18345 | |
4a6a3df4 AO |
18346 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18347 | { | |
18348 | /* We generate a fixup instead of applying it right now | |
18349 | because, if there are linker relaxations, we're going to | |
18350 | need the relocations. */ | |
18351 | exp.X_op = O_symbol; | |
18352 | exp.X_add_symbol = fragp->fr_symbol; | |
18353 | exp.X_add_number = fragp->fr_offset; | |
18354 | ||
4d68580a RS |
18355 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18356 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18357 | fixp->fx_file = fragp->fr_file; |
18358 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18359 | |
4d68580a | 18360 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18361 | } |
18362 | else | |
18363 | { | |
18364 | int i; | |
18365 | ||
18366 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18367 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18368 | |
18369 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18370 | goto uncond; | |
18371 | ||
18372 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18373 | { | |
18374 | /* Reverse the branch. */ | |
18375 | switch ((insn >> 28) & 0xf) | |
18376 | { | |
18377 | case 4: | |
3bf0dbfb MR |
18378 | /* bc[0-3][tf]l? instructions can have the condition |
18379 | reversed by tweaking a single TF bit, and their | |
18380 | opcodes all have 0x4???????. */ | |
18381 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18382 | insn ^= 0x00010000; |
18383 | break; | |
18384 | ||
18385 | case 0: | |
18386 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18387 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18388 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18389 | insn ^= 0x00010000; |
18390 | break; | |
b34976b6 | 18391 | |
4a6a3df4 AO |
18392 | case 1: |
18393 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18394 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18395 | insn ^= 0x04000000; |
18396 | break; | |
18397 | ||
18398 | default: | |
18399 | abort (); | |
18400 | } | |
18401 | } | |
18402 | ||
18403 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18404 | { | |
18405 | /* Clear the and-link bit. */ | |
9c2799c2 | 18406 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18407 | |
54f4ddb3 TS |
18408 | /* bltzal 0x04100000 bgezal 0x04110000 |
18409 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18410 | insn &= ~0x00100000; |
18411 | } | |
18412 | ||
18413 | /* Branch over the branch (if the branch was likely) or the | |
18414 | full jump (not likely case). Compute the offset from the | |
18415 | current instruction to branch to. */ | |
18416 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18417 | i = 16; | |
18418 | else | |
18419 | { | |
18420 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18421 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18422 | /* How many bytes in instructions from here to the end? */ |
18423 | i = fragp->fr_var - i; | |
18424 | } | |
18425 | /* Convert to instruction count. */ | |
18426 | i >>= 2; | |
18427 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18428 | i--; |
4a6a3df4 AO |
18429 | insn |= i; |
18430 | /* Branch over the jump. */ | |
4d68580a | 18431 | buf = write_insn (buf, insn); |
4a6a3df4 | 18432 | |
54f4ddb3 | 18433 | /* nop */ |
4d68580a | 18434 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18435 | |
18436 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18437 | { | |
18438 | /* beql $0, $0, 2f */ | |
18439 | insn = 0x50000000; | |
18440 | /* Compute the PC offset from the current instruction to | |
18441 | the end of the variable frag. */ | |
18442 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18443 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18444 | /* How many bytes in instructions from here to the end? */ |
18445 | i = fragp->fr_var - i; | |
18446 | /* Convert to instruction count. */ | |
18447 | i >>= 2; | |
18448 | /* Don't decrement i, because we want to branch over the | |
18449 | delay slot. */ | |
4a6a3df4 | 18450 | insn |= i; |
4a6a3df4 | 18451 | |
4d68580a RS |
18452 | buf = write_insn (buf, insn); |
18453 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18454 | } |
18455 | ||
18456 | uncond: | |
18457 | if (mips_pic == NO_PIC) | |
18458 | { | |
18459 | /* j or jal. */ | |
18460 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18461 | ? 0x0c000000 : 0x08000000); | |
18462 | exp.X_op = O_symbol; | |
18463 | exp.X_add_symbol = fragp->fr_symbol; | |
18464 | exp.X_add_number = fragp->fr_offset; | |
18465 | ||
4d68580a RS |
18466 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18467 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18468 | fixp->fx_file = fragp->fr_file; |
18469 | fixp->fx_line = fragp->fr_line; | |
18470 | ||
4d68580a | 18471 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18472 | } |
18473 | else | |
18474 | { | |
66b3e8da MR |
18475 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18476 | ||
4a6a3df4 | 18477 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18478 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18479 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18480 | exp.X_op = O_symbol; |
18481 | exp.X_add_symbol = fragp->fr_symbol; | |
18482 | exp.X_add_number = fragp->fr_offset; | |
18483 | ||
18484 | if (fragp->fr_offset) | |
18485 | { | |
18486 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18487 | exp.X_add_number = 0; | |
18488 | } | |
18489 | ||
4d68580a RS |
18490 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18491 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18492 | fixp->fx_file = fragp->fr_file; |
18493 | fixp->fx_line = fragp->fr_line; | |
18494 | ||
4d68580a | 18495 | buf = write_insn (buf, insn); |
b34976b6 | 18496 | |
4a6a3df4 | 18497 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18498 | /* nop */ |
18499 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18500 | |
18501 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18502 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18503 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18504 | |
4d68580a RS |
18505 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18506 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18507 | fixp->fx_file = fragp->fr_file; |
18508 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18509 | |
4d68580a | 18510 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18511 | |
18512 | /* j(al)r $at. */ | |
18513 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18514 | insn = 0x0000f809; |
4a6a3df4 | 18515 | else |
66b3e8da MR |
18516 | insn = 0x00000008; |
18517 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18518 | |
4d68580a | 18519 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18520 | } |
18521 | } | |
18522 | ||
4a6a3df4 | 18523 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18524 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18525 | return; |
18526 | } | |
18527 | ||
df58fc94 RS |
18528 | /* Relax microMIPS branches. */ |
18529 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18530 | { | |
4d68580a | 18531 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18532 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18533 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18534 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18535 | bfd_boolean short_ds; |
df58fc94 RS |
18536 | unsigned long insn; |
18537 | expressionS exp; | |
18538 | fixS *fixp; | |
18539 | ||
18540 | exp.X_op = O_symbol; | |
18541 | exp.X_add_symbol = fragp->fr_symbol; | |
18542 | exp.X_add_number = fragp->fr_offset; | |
18543 | ||
18544 | fragp->fr_fix += fragp->fr_var; | |
18545 | ||
18546 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18547 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18548 | { | |
18549 | /* We generate a fixup instead of applying it right now, | |
18550 | because if there is linker relaxation, we're going to | |
18551 | need the relocations. */ | |
18552 | if (type == 'D') | |
4d68580a | 18553 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18554 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18555 | else if (type == 'E') | |
4d68580a | 18556 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18557 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18558 | else | |
18559 | abort (); | |
18560 | ||
18561 | fixp->fx_file = fragp->fr_file; | |
18562 | fixp->fx_line = fragp->fr_line; | |
18563 | ||
18564 | /* These relocations can have an addend that won't fit in | |
18565 | 2 octets. */ | |
18566 | fixp->fx_no_overflow = 1; | |
18567 | ||
18568 | return; | |
18569 | } | |
18570 | ||
2309ddf2 | 18571 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18572 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18573 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18574 | { | |
18575 | /* We generate a fixup instead of applying it right now, | |
18576 | because if there is linker relaxation, we're going to | |
18577 | need the relocations. */ | |
4d68580a RS |
18578 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18579 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18580 | fixp->fx_file = fragp->fr_file; |
18581 | fixp->fx_line = fragp->fr_line; | |
18582 | ||
18583 | if (type == 0) | |
18584 | return; | |
18585 | } | |
18586 | ||
18587 | /* Relax 16-bit branches to 32-bit branches. */ | |
18588 | if (type != 0) | |
18589 | { | |
4d68580a | 18590 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18591 | |
18592 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18593 | insn = 0x94000000; /* beq */ | |
18594 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18595 | { | |
18596 | unsigned long regno; | |
18597 | ||
18598 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18599 | regno = micromips_to_32_reg_d_map [regno]; | |
18600 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18601 | insn |= regno << MICROMIPSOP_SH_RS; | |
18602 | } | |
18603 | else | |
18604 | abort (); | |
18605 | ||
18606 | /* Nothing else to do, just write it out. */ | |
18607 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18608 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18609 | { | |
4d68580a RS |
18610 | buf = write_compressed_insn (buf, insn, 4); |
18611 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18612 | return; |
18613 | } | |
18614 | } | |
18615 | else | |
4d68580a | 18616 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18617 | |
18618 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18619 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18620 | _("Relaxed out-of-range branch into a jump")); | |
18621 | ||
2309ddf2 MR |
18622 | /* Set the short-delay-slot bit. */ |
18623 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18624 | |
18625 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18626 | { | |
18627 | symbolS *l; | |
18628 | ||
18629 | /* Reverse the branch. */ | |
18630 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18631 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18632 | insn ^= 0x20000000; | |
18633 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18634 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18635 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18636 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18637 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18638 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18639 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18640 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18641 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18642 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18643 | insn ^= 0x00400000; | |
18644 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18645 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18646 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18647 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18648 | insn ^= 0x00200000; | |
18649 | else | |
18650 | abort (); | |
18651 | ||
18652 | if (al) | |
18653 | { | |
18654 | /* Clear the and-link and short-delay-slot bits. */ | |
18655 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18656 | ||
18657 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18658 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18659 | insn &= ~0x02200000; | |
18660 | } | |
18661 | ||
18662 | /* Make a label at the end for use with the branch. */ | |
18663 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18664 | micromips_label_inc (); | |
18665 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18666 | if (IS_ELF) | |
18667 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18668 | #endif | |
18669 | ||
18670 | /* Refer to it. */ | |
4d68580a RS |
18671 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18672 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18673 | fixp->fx_file = fragp->fr_file; |
18674 | fixp->fx_line = fragp->fr_line; | |
18675 | ||
18676 | /* Branch over the jump. */ | |
4d68580a | 18677 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18678 | if (!compact) |
4d68580a RS |
18679 | /* nop */ |
18680 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18681 | } |
18682 | ||
18683 | if (mips_pic == NO_PIC) | |
18684 | { | |
2309ddf2 MR |
18685 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18686 | ||
df58fc94 RS |
18687 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18688 | insn = al ? jal : 0xd4000000; | |
18689 | ||
4d68580a RS |
18690 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18691 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18692 | fixp->fx_file = fragp->fr_file; |
18693 | fixp->fx_line = fragp->fr_line; | |
18694 | ||
4d68580a | 18695 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18696 | if (compact) |
4d68580a RS |
18697 | /* nop */ |
18698 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18699 | } |
18700 | else | |
18701 | { | |
18702 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18703 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18704 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18705 | |
18706 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18707 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18708 | insn |= at << MICROMIPSOP_SH_RT; | |
18709 | ||
18710 | if (exp.X_add_number) | |
18711 | { | |
18712 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18713 | exp.X_add_number = 0; | |
18714 | } | |
18715 | ||
4d68580a RS |
18716 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18717 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18718 | fixp->fx_file = fragp->fr_file; |
18719 | fixp->fx_line = fragp->fr_line; | |
18720 | ||
4d68580a | 18721 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18722 | |
18723 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18724 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18725 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18726 | ||
4d68580a RS |
18727 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18728 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18729 | fixp->fx_file = fragp->fr_file; |
18730 | fixp->fx_line = fragp->fr_line; | |
18731 | ||
4d68580a | 18732 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18733 | |
18734 | /* jr/jrc/jalr/jalrs $at */ | |
18735 | insn = al ? jalr : jr; | |
18736 | insn |= at << MICROMIPSOP_SH_MJ; | |
18737 | ||
4d68580a | 18738 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18739 | } |
18740 | ||
4d68580a | 18741 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18742 | return; |
18743 | } | |
18744 | ||
252b5132 RH |
18745 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18746 | { | |
18747 | int type; | |
3994f87e | 18748 | const struct mips16_immed_operand *op; |
252b5132 | 18749 | offsetT val; |
5c04167a RS |
18750 | char *buf; |
18751 | unsigned int user_length, length; | |
252b5132 | 18752 | unsigned long insn; |
5c04167a | 18753 | bfd_boolean ext; |
252b5132 RH |
18754 | |
18755 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18756 | op = mips16_immed_operands; | |
18757 | while (op->type != type) | |
18758 | ++op; | |
18759 | ||
5c04167a | 18760 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18761 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18762 | if (op->pcrel) |
18763 | { | |
18764 | addressT addr; | |
18765 | ||
18766 | addr = fragp->fr_address + fragp->fr_fix; | |
18767 | ||
18768 | /* The rules for the base address of a PC relative reloc are | |
18769 | complicated; see mips16_extended_frag. */ | |
18770 | if (type == 'p' || type == 'q') | |
18771 | { | |
18772 | addr += 2; | |
18773 | if (ext) | |
18774 | addr += 2; | |
18775 | /* Ignore the low bit in the target, since it will be | |
18776 | set for a text label. */ | |
18777 | if ((val & 1) != 0) | |
18778 | --val; | |
18779 | } | |
18780 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18781 | addr -= 4; | |
18782 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18783 | addr -= 2; | |
18784 | ||
18785 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18786 | val -= addr; | |
18787 | ||
18788 | /* Make sure the section winds up with the alignment we have | |
18789 | assumed. */ | |
18790 | if (op->shift > 0) | |
18791 | record_alignment (asec, op->shift); | |
18792 | } | |
18793 | ||
18794 | if (ext | |
18795 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18796 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18797 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18798 | _("extended instruction in delay slot")); | |
18799 | ||
5c04167a | 18800 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18801 | |
4d68580a | 18802 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18803 | if (ext) |
18804 | insn |= MIPS16_EXTEND; | |
252b5132 | 18805 | |
5c04167a RS |
18806 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18807 | user_length = 4; | |
18808 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18809 | user_length = 2; | |
18810 | else | |
18811 | user_length = 0; | |
18812 | ||
43c0598f | 18813 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18814 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18815 | |
5c04167a RS |
18816 | length = (ext ? 4 : 2); |
18817 | gas_assert (mips16_opcode_length (insn) == length); | |
18818 | write_compressed_insn (buf, insn, length); | |
18819 | fragp->fr_fix += length; | |
252b5132 RH |
18820 | } |
18821 | else | |
18822 | { | |
df58fc94 RS |
18823 | relax_substateT subtype = fragp->fr_subtype; |
18824 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18825 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18826 | int first, second; |
18827 | fixS *fixp; | |
252b5132 | 18828 | |
df58fc94 RS |
18829 | first = RELAX_FIRST (subtype); |
18830 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18831 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18832 | |
df58fc94 RS |
18833 | /* If the delay slot chosen does not match the size of the instruction, |
18834 | then emit a warning. */ | |
18835 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18836 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18837 | { | |
18838 | relax_substateT s; | |
18839 | const char *msg; | |
18840 | ||
18841 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18842 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18843 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18844 | msg = macro_warning (s); | |
18845 | if (msg != NULL) | |
db9b2be4 | 18846 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18847 | subtype &= ~s; |
18848 | } | |
18849 | ||
584892a6 | 18850 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18851 | if (use_second == second_longer) |
584892a6 | 18852 | { |
df58fc94 RS |
18853 | relax_substateT s; |
18854 | const char *msg; | |
18855 | ||
18856 | s = (subtype | |
18857 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18858 | msg = macro_warning (s); | |
18859 | if (msg != NULL) | |
db9b2be4 | 18860 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18861 | subtype &= ~s; |
584892a6 RS |
18862 | } |
18863 | ||
4d7206a2 RS |
18864 | /* Go through all the fixups for the first sequence. Disable them |
18865 | (by marking them as done) if we're going to use the second | |
18866 | sequence instead. */ | |
18867 | while (fixp | |
18868 | && fixp->fx_frag == fragp | |
18869 | && fixp->fx_where < fragp->fr_fix - second) | |
18870 | { | |
df58fc94 | 18871 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18872 | fixp->fx_done = 1; |
18873 | fixp = fixp->fx_next; | |
18874 | } | |
252b5132 | 18875 | |
4d7206a2 RS |
18876 | /* Go through the fixups for the second sequence. Disable them if |
18877 | we're going to use the first sequence, otherwise adjust their | |
18878 | addresses to account for the relaxation. */ | |
18879 | while (fixp && fixp->fx_frag == fragp) | |
18880 | { | |
df58fc94 | 18881 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18882 | fixp->fx_where -= first; |
18883 | else | |
18884 | fixp->fx_done = 1; | |
18885 | fixp = fixp->fx_next; | |
18886 | } | |
18887 | ||
18888 | /* Now modify the frag contents. */ | |
df58fc94 | 18889 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18890 | { |
18891 | char *start; | |
18892 | ||
18893 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18894 | memmove (start, start + first, second); | |
18895 | fragp->fr_fix -= first; | |
18896 | } | |
18897 | else | |
18898 | fragp->fr_fix -= second; | |
252b5132 RH |
18899 | } |
18900 | } | |
18901 | ||
18902 | #ifdef OBJ_ELF | |
18903 | ||
18904 | /* This function is called after the relocs have been generated. | |
18905 | We've been storing mips16 text labels as odd. Here we convert them | |
18906 | back to even for the convenience of the debugger. */ | |
18907 | ||
18908 | void | |
17a2f251 | 18909 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18910 | { |
18911 | asymbol **syms; | |
18912 | unsigned int count, i; | |
18913 | ||
f43abd2b | 18914 | if (!IS_ELF) |
252b5132 RH |
18915 | return; |
18916 | ||
18917 | syms = bfd_get_outsymbols (stdoutput); | |
18918 | count = bfd_get_symcount (stdoutput); | |
18919 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18920 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18921 | && ((*syms)->value & 1) != 0) | |
18922 | { | |
18923 | (*syms)->value &= ~1; | |
18924 | /* If the symbol has an odd size, it was probably computed | |
18925 | incorrectly, so adjust that as well. */ | |
18926 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18927 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18928 | } | |
252b5132 RH |
18929 | } |
18930 | ||
18931 | #endif | |
18932 | ||
a1facbec MR |
18933 | /* This function is called whenever a label is defined, including fake |
18934 | labels instantiated off the dot special symbol. It is used when | |
18935 | handling branch delays; if a branch has a label, we assume we cannot | |
18936 | move it. This also bumps the value of the symbol by 1 in compressed | |
18937 | code. */ | |
252b5132 | 18938 | |
e1b47bd5 | 18939 | static void |
a1facbec | 18940 | mips_record_label (symbolS *sym) |
252b5132 | 18941 | { |
a8dbcb85 | 18942 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18943 | struct insn_label_list *l; |
18944 | ||
18945 | if (free_insn_labels == NULL) | |
18946 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18947 | else | |
18948 | { | |
18949 | l = free_insn_labels; | |
18950 | free_insn_labels = l->next; | |
18951 | } | |
18952 | ||
18953 | l->label = sym; | |
a8dbcb85 TS |
18954 | l->next = si->label_list; |
18955 | si->label_list = l; | |
a1facbec | 18956 | } |
07a53e5c | 18957 | |
a1facbec MR |
18958 | /* This function is called as tc_frob_label() whenever a label is defined |
18959 | and adds a DWARF-2 record we only want for true labels. */ | |
18960 | ||
18961 | void | |
18962 | mips_define_label (symbolS *sym) | |
18963 | { | |
18964 | mips_record_label (sym); | |
07a53e5c RH |
18965 | #ifdef OBJ_ELF |
18966 | dwarf2_emit_label (sym); | |
18967 | #endif | |
252b5132 | 18968 | } |
e1b47bd5 RS |
18969 | |
18970 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18971 | is defined. */ | |
18972 | ||
18973 | void | |
18974 | mips_add_dot_label (symbolS *sym) | |
18975 | { | |
18976 | mips_record_label (sym); | |
18977 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18978 | mips_compressed_mark_label (sym); | |
18979 | } | |
252b5132 RH |
18980 | \f |
18981 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18982 | ||
18983 | /* Some special processing for a MIPS ELF file. */ | |
18984 | ||
18985 | void | |
17a2f251 | 18986 | mips_elf_final_processing (void) |
252b5132 RH |
18987 | { |
18988 | /* Write out the register information. */ | |
316f5878 | 18989 | if (mips_abi != N64_ABI) |
252b5132 RH |
18990 | { |
18991 | Elf32_RegInfo s; | |
18992 | ||
18993 | s.ri_gprmask = mips_gprmask; | |
18994 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18995 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18996 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18997 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18998 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18999 | ||
19000 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19001 | ((Elf32_External_RegInfo *) | |
19002 | mips_regmask_frag)); | |
19003 | } | |
19004 | else | |
19005 | { | |
19006 | Elf64_Internal_RegInfo s; | |
19007 | ||
19008 | s.ri_gprmask = mips_gprmask; | |
19009 | s.ri_pad = 0; | |
19010 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19011 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19012 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19013 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19014 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19015 | ||
19016 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19017 | ((Elf64_External_RegInfo *) | |
19018 | mips_regmask_frag)); | |
19019 | } | |
19020 | ||
19021 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19022 | sort of BFD interface for this. */ | |
19023 | if (mips_any_noreorder) | |
19024 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19025 | if (mips_pic != NO_PIC) | |
143d77c5 | 19026 | { |
8b828383 | 19027 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19028 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19029 | } | |
19030 | if (mips_abicalls) | |
19031 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19032 | |
b015e599 AP |
19033 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19034 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19035 | if (file_ase_mips16) |
19036 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19037 | if (file_ase_micromips) |
19038 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
19039 | #if 0 /* XXX FIXME */ |
19040 | if (file_ase_mips3d) | |
19041 | elf_elfheader (stdoutput)->e_flags |= ???; | |
19042 | #endif | |
deec1734 CD |
19043 | if (file_ase_mdmx) |
19044 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 19045 | |
bdaaa2e1 | 19046 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19047 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19048 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19049 | else if (mips_abi == O64_ABI) |
252b5132 | 19050 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19051 | else if (mips_abi == EABI_ABI) |
252b5132 | 19052 | { |
316f5878 | 19053 | if (!file_mips_gp32) |
252b5132 RH |
19054 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19055 | else | |
19056 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19057 | } | |
316f5878 | 19058 | else if (mips_abi == N32_ABI) |
be00bddd TS |
19059 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
19060 | ||
c9914766 | 19061 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
19062 | |
19063 | if (mips_32bitmode) | |
19064 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
19065 | |
19066 | #if 0 /* XXX FIXME */ | |
19067 | /* 32 bit code with 64 bit FP registers. */ | |
19068 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19069 | elf_elfheader (stdoutput)->e_flags |= ???; | |
19070 | #endif | |
252b5132 RH |
19071 | } |
19072 | ||
19073 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
19074 | \f | |
beae10d5 | 19075 | typedef struct proc { |
9b2f1d35 EC |
19076 | symbolS *func_sym; |
19077 | symbolS *func_end_sym; | |
beae10d5 KH |
19078 | unsigned long reg_mask; |
19079 | unsigned long reg_offset; | |
19080 | unsigned long fpreg_mask; | |
19081 | unsigned long fpreg_offset; | |
19082 | unsigned long frame_offset; | |
19083 | unsigned long frame_reg; | |
19084 | unsigned long pc_reg; | |
19085 | } procS; | |
252b5132 RH |
19086 | |
19087 | static procS cur_proc; | |
19088 | static procS *cur_proc_ptr; | |
19089 | static int numprocs; | |
19090 | ||
df58fc94 RS |
19091 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19092 | as "2", and a normal nop as "0". */ | |
19093 | ||
19094 | #define NOP_OPCODE_MIPS 0 | |
19095 | #define NOP_OPCODE_MIPS16 1 | |
19096 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19097 | |
19098 | char | |
19099 | mips_nop_opcode (void) | |
19100 | { | |
df58fc94 RS |
19101 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19102 | return NOP_OPCODE_MICROMIPS; | |
19103 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19104 | return NOP_OPCODE_MIPS16; | |
19105 | else | |
19106 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19107 | } |
19108 | ||
df58fc94 RS |
19109 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19110 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19111 | |
0a9ef439 | 19112 | void |
17a2f251 | 19113 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19114 | { |
df58fc94 | 19115 | char nop_opcode; |
742a56fe | 19116 | char *p; |
c67a084a NC |
19117 | int bytes, size, excess; |
19118 | valueT opcode; | |
742a56fe | 19119 | |
0a9ef439 RH |
19120 | if (fragp->fr_type != rs_align_code) |
19121 | return; | |
19122 | ||
742a56fe | 19123 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19124 | nop_opcode = *p; |
19125 | switch (nop_opcode) | |
a19d8eb0 | 19126 | { |
df58fc94 RS |
19127 | case NOP_OPCODE_MICROMIPS: |
19128 | opcode = micromips_nop32_insn.insn_opcode; | |
19129 | size = 4; | |
19130 | break; | |
19131 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19132 | opcode = mips16_nop_insn.insn_opcode; |
19133 | size = 2; | |
df58fc94 RS |
19134 | break; |
19135 | case NOP_OPCODE_MIPS: | |
19136 | default: | |
c67a084a NC |
19137 | opcode = nop_insn.insn_opcode; |
19138 | size = 4; | |
df58fc94 | 19139 | break; |
c67a084a | 19140 | } |
a19d8eb0 | 19141 | |
c67a084a NC |
19142 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19143 | excess = bytes % size; | |
df58fc94 RS |
19144 | |
19145 | /* Handle the leading part if we're not inserting a whole number of | |
19146 | instructions, and make it the end of the fixed part of the frag. | |
19147 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19148 | and use zeroes otherwise. */ | |
19149 | gas_assert (excess < 4); | |
19150 | fragp->fr_fix += excess; | |
19151 | switch (excess) | |
c67a084a | 19152 | { |
df58fc94 RS |
19153 | case 3: |
19154 | *p++ = '\0'; | |
19155 | /* Fall through. */ | |
19156 | case 2: | |
19157 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
19158 | { | |
4d68580a | 19159 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19160 | break; |
19161 | } | |
19162 | *p++ = '\0'; | |
19163 | /* Fall through. */ | |
19164 | case 1: | |
19165 | *p++ = '\0'; | |
19166 | /* Fall through. */ | |
19167 | case 0: | |
19168 | break; | |
a19d8eb0 | 19169 | } |
c67a084a NC |
19170 | |
19171 | md_number_to_chars (p, opcode, size); | |
19172 | fragp->fr_var = size; | |
a19d8eb0 CP |
19173 | } |
19174 | ||
252b5132 | 19175 | static void |
17a2f251 | 19176 | md_obj_begin (void) |
252b5132 RH |
19177 | { |
19178 | } | |
19179 | ||
19180 | static void | |
17a2f251 | 19181 | md_obj_end (void) |
252b5132 | 19182 | { |
54f4ddb3 | 19183 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 19184 | if (cur_proc_ptr) |
9a41af64 | 19185 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
19186 | } |
19187 | ||
19188 | static long | |
17a2f251 | 19189 | get_number (void) |
252b5132 RH |
19190 | { |
19191 | int negative = 0; | |
19192 | long val = 0; | |
19193 | ||
19194 | if (*input_line_pointer == '-') | |
19195 | { | |
19196 | ++input_line_pointer; | |
19197 | negative = 1; | |
19198 | } | |
3882b010 | 19199 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19200 | as_bad (_("expected simple number")); |
252b5132 RH |
19201 | if (input_line_pointer[0] == '0') |
19202 | { | |
19203 | if (input_line_pointer[1] == 'x') | |
19204 | { | |
19205 | input_line_pointer += 2; | |
3882b010 | 19206 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19207 | { |
19208 | val <<= 4; | |
19209 | val |= hex_value (*input_line_pointer++); | |
19210 | } | |
19211 | return negative ? -val : val; | |
19212 | } | |
19213 | else | |
19214 | { | |
19215 | ++input_line_pointer; | |
3882b010 | 19216 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19217 | { |
19218 | val <<= 3; | |
19219 | val |= *input_line_pointer++ - '0'; | |
19220 | } | |
19221 | return negative ? -val : val; | |
19222 | } | |
19223 | } | |
3882b010 | 19224 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19225 | { |
19226 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19227 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19228 | as_warn (_("invalid number")); |
252b5132 RH |
19229 | return -1; |
19230 | } | |
3882b010 | 19231 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19232 | { |
19233 | val *= 10; | |
19234 | val += *input_line_pointer++ - '0'; | |
19235 | } | |
19236 | return negative ? -val : val; | |
19237 | } | |
19238 | ||
19239 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19240 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19241 | case .file implies DWARF-2. */ | |
19242 | ||
19243 | static void | |
17a2f251 | 19244 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19245 | { |
ecb4347a DJ |
19246 | static int first_file_directive = 0; |
19247 | ||
c5dd6aab DJ |
19248 | if (ECOFF_DEBUGGING) |
19249 | { | |
19250 | get_number (); | |
19251 | s_app_file (0); | |
19252 | } | |
19253 | else | |
ecb4347a DJ |
19254 | { |
19255 | char *filename; | |
19256 | ||
19257 | filename = dwarf2_directive_file (0); | |
19258 | ||
19259 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19260 | directive even for stabs output. Make sure that this | |
19261 | ".file" is handled. Note that you need a version of GCC | |
19262 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19263 | if (filename != NULL && ! first_file_directive) | |
19264 | { | |
19265 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19266 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19267 | } |
19268 | first_file_directive = 1; | |
19269 | } | |
c5dd6aab DJ |
19270 | } |
19271 | ||
19272 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19273 | |
19274 | static void | |
17a2f251 | 19275 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19276 | { |
c5dd6aab DJ |
19277 | if (!ECOFF_DEBUGGING) |
19278 | dwarf2_directive_loc (0); | |
252b5132 RH |
19279 | } |
19280 | ||
252b5132 RH |
19281 | /* The .end directive. */ |
19282 | ||
19283 | static void | |
17a2f251 | 19284 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19285 | { |
19286 | symbolS *p; | |
252b5132 | 19287 | |
7a621144 DJ |
19288 | /* Following functions need their own .frame and .cprestore directives. */ |
19289 | mips_frame_reg_valid = 0; | |
19290 | mips_cprestore_valid = 0; | |
19291 | ||
252b5132 RH |
19292 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19293 | { | |
19294 | p = get_symbol (); | |
19295 | demand_empty_rest_of_line (); | |
19296 | } | |
19297 | else | |
19298 | p = NULL; | |
19299 | ||
14949570 | 19300 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19301 | as_warn (_(".end not in text section")); |
19302 | ||
19303 | if (!cur_proc_ptr) | |
19304 | { | |
19305 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19306 | demand_empty_rest_of_line (); | |
19307 | return; | |
19308 | } | |
19309 | ||
19310 | if (p != NULL) | |
19311 | { | |
9c2799c2 | 19312 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19313 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19314 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19315 | |
19316 | if (debug_type == DEBUG_STABS) | |
19317 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19318 | S_GET_NAME (p)); | |
252b5132 RH |
19319 | } |
19320 | else | |
19321 | as_warn (_(".end directive missing or unknown symbol")); | |
19322 | ||
2132e3a3 | 19323 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19324 | /* Create an expression to calculate the size of the function. */ |
19325 | if (p && cur_proc_ptr) | |
19326 | { | |
19327 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19328 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19329 | ||
19330 | obj->size = exp; | |
19331 | exp->X_op = O_subtract; | |
19332 | exp->X_add_symbol = symbol_temp_new_now (); | |
19333 | exp->X_op_symbol = p; | |
19334 | exp->X_add_number = 0; | |
19335 | ||
19336 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19337 | } | |
19338 | ||
ecb4347a | 19339 | /* Generate a .pdr section. */ |
f43abd2b | 19340 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19341 | { |
19342 | segT saved_seg = now_seg; | |
19343 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19344 | expressionS exp; |
19345 | char *fragp; | |
252b5132 | 19346 | |
252b5132 | 19347 | #ifdef md_flush_pending_output |
ecb4347a | 19348 | md_flush_pending_output (); |
252b5132 RH |
19349 | #endif |
19350 | ||
9c2799c2 | 19351 | gas_assert (pdr_seg); |
ecb4347a | 19352 | subseg_set (pdr_seg, 0); |
252b5132 | 19353 | |
ecb4347a DJ |
19354 | /* Write the symbol. */ |
19355 | exp.X_op = O_symbol; | |
19356 | exp.X_add_symbol = p; | |
19357 | exp.X_add_number = 0; | |
19358 | emit_expr (&exp, 4); | |
252b5132 | 19359 | |
ecb4347a | 19360 | fragp = frag_more (7 * 4); |
252b5132 | 19361 | |
17a2f251 TS |
19362 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19363 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19364 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19365 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19366 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19367 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19368 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19369 | |
ecb4347a DJ |
19370 | subseg_set (saved_seg, saved_subseg); |
19371 | } | |
19372 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19373 | |
19374 | cur_proc_ptr = NULL; | |
19375 | } | |
19376 | ||
19377 | /* The .aent and .ent directives. */ | |
19378 | ||
19379 | static void | |
17a2f251 | 19380 | s_mips_ent (int aent) |
252b5132 | 19381 | { |
252b5132 | 19382 | symbolS *symbolP; |
252b5132 RH |
19383 | |
19384 | symbolP = get_symbol (); | |
19385 | if (*input_line_pointer == ',') | |
f9419b05 | 19386 | ++input_line_pointer; |
252b5132 | 19387 | SKIP_WHITESPACE (); |
3882b010 | 19388 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19389 | || *input_line_pointer == '-') |
874e8986 | 19390 | get_number (); |
252b5132 | 19391 | |
14949570 | 19392 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19393 | as_warn (_(".ent or .aent not in text section.")); |
19394 | ||
19395 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19396 | as_warn (_("missing .end")); |
252b5132 RH |
19397 | |
19398 | if (!aent) | |
19399 | { | |
7a621144 DJ |
19400 | /* This function needs its own .frame and .cprestore directives. */ |
19401 | mips_frame_reg_valid = 0; | |
19402 | mips_cprestore_valid = 0; | |
19403 | ||
252b5132 RH |
19404 | cur_proc_ptr = &cur_proc; |
19405 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19406 | ||
9b2f1d35 | 19407 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19408 | |
f9419b05 | 19409 | ++numprocs; |
ecb4347a DJ |
19410 | |
19411 | if (debug_type == DEBUG_STABS) | |
19412 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19413 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19414 | } |
19415 | ||
7c0fc524 MR |
19416 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19417 | ||
252b5132 RH |
19418 | demand_empty_rest_of_line (); |
19419 | } | |
19420 | ||
19421 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19422 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19423 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19424 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19425 | symbol table (in the mdebug section). */ |
19426 | ||
19427 | static void | |
17a2f251 | 19428 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19429 | { |
ecb4347a | 19430 | #ifdef OBJ_ELF |
f43abd2b | 19431 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19432 | { |
19433 | long val; | |
252b5132 | 19434 | |
ecb4347a DJ |
19435 | if (cur_proc_ptr == (procS *) NULL) |
19436 | { | |
19437 | as_warn (_(".frame outside of .ent")); | |
19438 | demand_empty_rest_of_line (); | |
19439 | return; | |
19440 | } | |
252b5132 | 19441 | |
ecb4347a DJ |
19442 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19443 | ||
19444 | SKIP_WHITESPACE (); | |
19445 | if (*input_line_pointer++ != ',' | |
19446 | || get_absolute_expression_and_terminator (&val) != ',') | |
19447 | { | |
19448 | as_warn (_("Bad .frame directive")); | |
19449 | --input_line_pointer; | |
19450 | demand_empty_rest_of_line (); | |
19451 | return; | |
19452 | } | |
252b5132 | 19453 | |
ecb4347a DJ |
19454 | cur_proc_ptr->frame_offset = val; |
19455 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19456 | |
252b5132 | 19457 | demand_empty_rest_of_line (); |
252b5132 | 19458 | } |
ecb4347a DJ |
19459 | else |
19460 | #endif /* OBJ_ELF */ | |
19461 | s_ignore (ignore); | |
252b5132 RH |
19462 | } |
19463 | ||
bdaaa2e1 KH |
19464 | /* The .fmask and .mask directives. If the mdebug section is present |
19465 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19466 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19467 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19468 | make reference to the ecoff symbol table (in the mdebug section). */ |
19469 | ||
19470 | static void | |
17a2f251 | 19471 | s_mips_mask (int reg_type) |
252b5132 | 19472 | { |
ecb4347a | 19473 | #ifdef OBJ_ELF |
f43abd2b | 19474 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19475 | { |
ecb4347a | 19476 | long mask, off; |
252b5132 | 19477 | |
ecb4347a DJ |
19478 | if (cur_proc_ptr == (procS *) NULL) |
19479 | { | |
19480 | as_warn (_(".mask/.fmask outside of .ent")); | |
19481 | demand_empty_rest_of_line (); | |
19482 | return; | |
19483 | } | |
252b5132 | 19484 | |
ecb4347a DJ |
19485 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19486 | { | |
19487 | as_warn (_("Bad .mask/.fmask directive")); | |
19488 | --input_line_pointer; | |
19489 | demand_empty_rest_of_line (); | |
19490 | return; | |
19491 | } | |
252b5132 | 19492 | |
ecb4347a DJ |
19493 | off = get_absolute_expression (); |
19494 | ||
19495 | if (reg_type == 'F') | |
19496 | { | |
19497 | cur_proc_ptr->fpreg_mask = mask; | |
19498 | cur_proc_ptr->fpreg_offset = off; | |
19499 | } | |
19500 | else | |
19501 | { | |
19502 | cur_proc_ptr->reg_mask = mask; | |
19503 | cur_proc_ptr->reg_offset = off; | |
19504 | } | |
19505 | ||
19506 | demand_empty_rest_of_line (); | |
252b5132 RH |
19507 | } |
19508 | else | |
ecb4347a DJ |
19509 | #endif /* OBJ_ELF */ |
19510 | s_ignore (reg_type); | |
252b5132 RH |
19511 | } |
19512 | ||
316f5878 RS |
19513 | /* A table describing all the processors gas knows about. Names are |
19514 | matched in the order listed. | |
e7af610e | 19515 | |
316f5878 RS |
19516 | To ease comparison, please keep this table in the same order as |
19517 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19518 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19519 | { | |
316f5878 | 19520 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19521 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19522 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19523 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19524 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19525 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19526 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19527 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19528 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19529 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19530 | |
19531 | /* MIPS I */ | |
ad3fea08 TS |
19532 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19533 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19534 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19535 | |
19536 | /* MIPS II */ | |
ad3fea08 | 19537 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19538 | |
19539 | /* MIPS III */ | |
ad3fea08 TS |
19540 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19541 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19542 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19543 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19544 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19545 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19546 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19547 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19548 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19549 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19550 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19551 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19552 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19553 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19554 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19555 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19556 | |
19557 | /* MIPS IV */ | |
ad3fea08 TS |
19558 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19559 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19560 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19561 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19562 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19563 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19564 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19565 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19566 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19567 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19568 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19569 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19570 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19571 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19572 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19573 | |
19574 | /* MIPS 32 */ | |
ad3fea08 TS |
19575 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19576 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19577 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19578 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19579 | ||
19580 | /* MIPS 32 Release 2 */ | |
19581 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19582 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19583 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19584 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19585 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19586 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19587 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19588 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19589 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19590 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19591 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19592 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19593 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19594 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19595 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19596 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19597 | /* Deprecated forms of the above. */ | |
19598 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19599 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19600 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19601 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19602 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19603 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19604 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19605 | /* Deprecated forms of the above. */ | |
19606 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19607 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19608 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19609 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19610 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19611 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19612 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19613 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19614 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19615 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19616 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19617 | /* Deprecated forms of the above. */ | |
19618 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19619 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19620 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19621 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19622 | /* 34Kn is a 34kc without DSP. */ |
19623 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19624 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19625 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19626 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19627 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19628 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19629 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19630 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19631 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19632 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19633 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19634 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19635 | /* Deprecated forms of the above. */ | |
19636 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19637 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19638 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19639 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19640 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19641 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19642 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19643 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19644 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19645 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19646 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19647 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19648 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19649 | |
316f5878 | 19650 | /* MIPS 64 */ |
ad3fea08 TS |
19651 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19652 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19653 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19654 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19655 | |
c7a23324 | 19656 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19657 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19658 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19659 | /* Broadcom SB-1A CPU core */ |
19660 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19661 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19662 | |
19663 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19664 | |
ed163775 MR |
19665 | /* MIPS 64 Release 2 */ |
19666 | ||
967344c6 AN |
19667 | /* Cavium Networks Octeon CPU core */ |
19668 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19669 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19670 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19671 | |
52b6b6b9 JM |
19672 | /* RMI Xlr */ |
19673 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19674 | ||
55a36193 MK |
19675 | /* Broadcom XLP. |
19676 | XLP is mostly like XLR, with the prominent exception that it is | |
19677 | MIPS64R2 rather than MIPS64. */ | |
19678 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19679 | ||
316f5878 RS |
19680 | /* End marker */ |
19681 | { NULL, 0, 0, 0 } | |
19682 | }; | |
e7af610e | 19683 | |
84ea6cf2 | 19684 | |
316f5878 RS |
19685 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19686 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19687 | |
316f5878 | 19688 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19689 | |
b34976b6 | 19690 | static bfd_boolean |
17a2f251 | 19691 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19692 | { |
19693 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19694 | given++, canonical++; | |
19695 | ||
19696 | return ((*given == 0 && *canonical == 0) | |
19697 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19698 | } | |
19699 | ||
19700 | ||
19701 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19702 | CPU name. We've traditionally allowed a lot of variation here. | |
19703 | ||
19704 | Note: this function is shared between GCC and GAS. */ | |
19705 | ||
b34976b6 | 19706 | static bfd_boolean |
17a2f251 | 19707 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19708 | { |
19709 | /* First see if the name matches exactly, or with a final "000" | |
19710 | turned into "k". */ | |
19711 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19712 | return TRUE; |
316f5878 RS |
19713 | |
19714 | /* If not, try comparing based on numerical designation alone. | |
19715 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19716 | if (TOLOWER (*given) == 'r') | |
19717 | given++; | |
19718 | if (!ISDIGIT (*given)) | |
b34976b6 | 19719 | return FALSE; |
316f5878 RS |
19720 | |
19721 | /* Skip over some well-known prefixes in the canonical name, | |
19722 | hoping to find a number there too. */ | |
19723 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19724 | canonical += 2; | |
19725 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19726 | canonical += 2; | |
19727 | else if (TOLOWER (canonical[0]) == 'r') | |
19728 | canonical += 1; | |
19729 | ||
19730 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19731 | } | |
19732 | ||
19733 | ||
19734 | /* Parse an option that takes the name of a processor as its argument. | |
19735 | OPTION is the name of the option and CPU_STRING is the argument. | |
19736 | Return the corresponding processor enumeration if the CPU_STRING is | |
19737 | recognized, otherwise report an error and return null. | |
19738 | ||
19739 | A similar function exists in GCC. */ | |
e7af610e NC |
19740 | |
19741 | static const struct mips_cpu_info * | |
17a2f251 | 19742 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19743 | { |
316f5878 | 19744 | const struct mips_cpu_info *p; |
e7af610e | 19745 | |
316f5878 RS |
19746 | /* 'from-abi' selects the most compatible architecture for the given |
19747 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19748 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19749 | version. Look first at the -mgp options, if given, otherwise base | |
19750 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19751 | |
316f5878 RS |
19752 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19753 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19754 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19755 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19756 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19757 | { | |
19758 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19759 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19760 | ||
19761 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19762 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19763 | ||
19764 | if (file_mips_gp32 >= 0) | |
19765 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19766 | ||
19767 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19768 | ? ISA_MIPS3 | |
19769 | : ISA_MIPS1); | |
19770 | } | |
19771 | ||
19772 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19773 | if (strcasecmp (cpu_string, "default") == 0) | |
19774 | return 0; | |
19775 | ||
19776 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19777 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19778 | return p; | |
19779 | ||
20203fb9 | 19780 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19781 | return 0; |
e7af610e NC |
19782 | } |
19783 | ||
316f5878 RS |
19784 | /* Return the canonical processor information for ISA (a member of the |
19785 | ISA_MIPS* enumeration). */ | |
19786 | ||
e7af610e | 19787 | static const struct mips_cpu_info * |
17a2f251 | 19788 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19789 | { |
19790 | int i; | |
19791 | ||
19792 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19793 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19794 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19795 | return (&mips_cpu_info_table[i]); |
19796 | ||
e972090a | 19797 | return NULL; |
e7af610e | 19798 | } |
fef14a42 TS |
19799 | |
19800 | static const struct mips_cpu_info * | |
17a2f251 | 19801 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19802 | { |
19803 | int i; | |
19804 | ||
19805 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19806 | if (arch == mips_cpu_info_table[i].cpu) | |
19807 | return (&mips_cpu_info_table[i]); | |
19808 | ||
19809 | return NULL; | |
19810 | } | |
316f5878 RS |
19811 | \f |
19812 | static void | |
17a2f251 | 19813 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19814 | { |
19815 | if (*first_p) | |
19816 | { | |
19817 | fprintf (stream, "%24s", ""); | |
19818 | *col_p = 24; | |
19819 | } | |
19820 | else | |
19821 | { | |
19822 | fprintf (stream, ", "); | |
19823 | *col_p += 2; | |
19824 | } | |
e7af610e | 19825 | |
316f5878 RS |
19826 | if (*col_p + strlen (string) > 72) |
19827 | { | |
19828 | fprintf (stream, "\n%24s", ""); | |
19829 | *col_p = 24; | |
19830 | } | |
19831 | ||
19832 | fprintf (stream, "%s", string); | |
19833 | *col_p += strlen (string); | |
19834 | ||
19835 | *first_p = 0; | |
19836 | } | |
19837 | ||
19838 | void | |
17a2f251 | 19839 | md_show_usage (FILE *stream) |
e7af610e | 19840 | { |
316f5878 RS |
19841 | int column, first; |
19842 | size_t i; | |
19843 | ||
19844 | fprintf (stream, _("\ | |
19845 | MIPS options:\n\ | |
316f5878 RS |
19846 | -EB generate big endian output\n\ |
19847 | -EL generate little endian output\n\ | |
19848 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19849 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19850 | implicitly with the gp register [default 8]\n")); | |
19851 | fprintf (stream, _("\ | |
19852 | -mips1 generate MIPS ISA I instructions\n\ | |
19853 | -mips2 generate MIPS ISA II instructions\n\ | |
19854 | -mips3 generate MIPS ISA III instructions\n\ | |
19855 | -mips4 generate MIPS ISA IV instructions\n\ | |
19856 | -mips5 generate MIPS ISA V instructions\n\ | |
19857 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19858 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19859 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19860 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19861 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19862 | ||
19863 | first = 1; | |
e7af610e NC |
19864 | |
19865 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19866 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19867 | show (stream, "from-abi", &column, &first); | |
19868 | fputc ('\n', stream); | |
e7af610e | 19869 | |
316f5878 RS |
19870 | fprintf (stream, _("\ |
19871 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19872 | -no-mCPU don't generate code specific to CPU.\n\ | |
19873 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19874 | ||
19875 | first = 1; | |
19876 | ||
19877 | show (stream, "3900", &column, &first); | |
19878 | show (stream, "4010", &column, &first); | |
19879 | show (stream, "4100", &column, &first); | |
19880 | show (stream, "4650", &column, &first); | |
19881 | fputc ('\n', stream); | |
19882 | ||
19883 | fprintf (stream, _("\ | |
19884 | -mips16 generate mips16 instructions\n\ | |
19885 | -no-mips16 do not generate mips16 instructions\n")); | |
19886 | fprintf (stream, _("\ | |
df58fc94 RS |
19887 | -mmicromips generate microMIPS instructions\n\ |
19888 | -mno-micromips do not generate microMIPS instructions\n")); | |
19889 | fprintf (stream, _("\ | |
e16bfa71 TS |
19890 | -msmartmips generate smartmips instructions\n\ |
19891 | -mno-smartmips do not generate smartmips instructions\n")); | |
19892 | fprintf (stream, _("\ | |
74cd071d CF |
19893 | -mdsp generate DSP instructions\n\ |
19894 | -mno-dsp do not generate DSP instructions\n")); | |
19895 | fprintf (stream, _("\ | |
8b082fb1 TS |
19896 | -mdspr2 generate DSP R2 instructions\n\ |
19897 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19898 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19899 | -mmt generate MT instructions\n\ |
19900 | -mno-mt do not generate MT instructions\n")); | |
19901 | fprintf (stream, _("\ | |
dec0624d MR |
19902 | -mmcu generate MCU instructions\n\ |
19903 | -mno-mcu do not generate MCU instructions\n")); | |
19904 | fprintf (stream, _("\ | |
b015e599 AP |
19905 | -mvirt generate Virtualization instructions\n\ |
19906 | -mno-virt do not generate Virtualization instructions\n")); | |
19907 | fprintf (stream, _("\ | |
c67a084a NC |
19908 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19909 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19910 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19911 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19912 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19913 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19914 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19915 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19916 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19917 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19918 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19919 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19920 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19921 | fprintf (stream, _("\ |
19922 | -mhard-float allow floating-point instructions\n\ | |
19923 | -msoft-float do not allow floating-point instructions\n\ | |
19924 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19925 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19926 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19927 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19928 | )); |
316f5878 RS |
19929 | #ifdef OBJ_ELF |
19930 | fprintf (stream, _("\ | |
19931 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19932 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19933 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19934 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19935 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19936 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19937 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19938 | position dependent (non shared) code\n\ |
316f5878 RS |
19939 | -mabi=ABI create ABI conformant object file for:\n")); |
19940 | ||
19941 | first = 1; | |
19942 | ||
19943 | show (stream, "32", &column, &first); | |
19944 | show (stream, "o64", &column, &first); | |
19945 | show (stream, "n32", &column, &first); | |
19946 | show (stream, "64", &column, &first); | |
19947 | show (stream, "eabi", &column, &first); | |
19948 | ||
19949 | fputc ('\n', stream); | |
19950 | ||
19951 | fprintf (stream, _("\ | |
19952 | -32 create o32 ABI object file (default)\n\ | |
19953 | -n32 create n32 ABI object file\n\ | |
19954 | -64 create 64 ABI object file\n")); | |
19955 | #endif | |
e7af610e | 19956 | } |
14e777e0 | 19957 | |
1575952e | 19958 | #ifdef TE_IRIX |
14e777e0 | 19959 | enum dwarf2_format |
413a266c | 19960 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19961 | { |
369943fe | 19962 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19963 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19964 | else |
19965 | return dwarf2_format_32bit; | |
19966 | } | |
1575952e | 19967 | #endif |
73369e65 EC |
19968 | |
19969 | int | |
19970 | mips_dwarf2_addr_size (void) | |
19971 | { | |
6b6b3450 | 19972 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19973 | return 8; |
73369e65 EC |
19974 | else |
19975 | return 4; | |
19976 | } | |
5862107c EC |
19977 | |
19978 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19979 | void | |
19980 | mips_cfi_frame_initial_instructions (void) | |
19981 | { | |
19982 | cfi_add_CFA_def_cfa_register (SP); | |
19983 | } | |
19984 | ||
707bfff6 TS |
19985 | int |
19986 | tc_mips_regname_to_dw2regnum (char *regname) | |
19987 | { | |
19988 | unsigned int regnum = -1; | |
19989 | unsigned int reg; | |
19990 | ||
19991 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19992 | regnum = reg; | |
19993 | ||
19994 | return regnum; | |
19995 | } |