Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
98d3f06f | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
252b5132 RH |
105 | /* The name of the readonly data section. */ |
106 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
107 | ? ".data" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
109 | ? ".rdata" \ | |
056350c6 NC |
110 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
111 | ? ".rdata" \ | |
252b5132 RH |
112 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
113 | ? ".rodata" \ | |
114 | : (abort (), "")) | |
115 | ||
a325df1d TS |
116 | /* The ABI to use. */ |
117 | enum mips_abi_level | |
118 | { | |
119 | NO_ABI = 0, | |
120 | O32_ABI, | |
121 | O64_ABI, | |
122 | N32_ABI, | |
123 | N64_ABI, | |
124 | EABI_ABI | |
125 | }; | |
126 | ||
127 | /* MIPS ABI we are using for this output file. */ | |
128 | static enum mips_abi_level file_mips_abi = NO_ABI; | |
129 | ||
252b5132 RH |
130 | /* This is the set of options which may be modified by the .set |
131 | pseudo-op. We use a struct so that .set push and .set pop are more | |
132 | reliable. */ | |
133 | ||
e972090a NC |
134 | struct mips_set_options |
135 | { | |
252b5132 RH |
136 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
137 | if it has not been initialized. Changed by `.set mipsN', and the | |
138 | -mipsN command line option, and the default CPU. */ | |
139 | int isa; | |
1f25f5d3 CD |
140 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
141 | if they have not been initialized. Changed by `.set <asename>', by | |
142 | command line options, and based on the default architecture. */ | |
143 | int ase_mips3d; | |
252b5132 RH |
144 | /* Whether we are assembling for the mips16 processor. 0 if we are |
145 | not, 1 if we are, and -1 if the value has not been initialized. | |
146 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
147 | -nomips16 command line options, and the default CPU. */ | |
148 | int mips16; | |
149 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
150 | reorder' and `.set noreorder'. */ | |
151 | int noreorder; | |
152 | /* Non-zero if we should not permit the $at ($1) register to be used | |
153 | in instructions. Changed by `.set at' and `.set noat'. */ | |
154 | int noat; | |
155 | /* Non-zero if we should warn when a macro instruction expands into | |
156 | more than one machine instruction. Changed by `.set nomacro' and | |
157 | `.set macro'. */ | |
158 | int warn_about_macros; | |
159 | /* Non-zero if we should not move instructions. Changed by `.set | |
160 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
161 | int nomove; | |
162 | /* Non-zero if we should not optimize branches by moving the target | |
163 | of the branch into the delay slot. Actually, we don't perform | |
164 | this optimization anyhow. Changed by `.set bopt' and `.set | |
165 | nobopt'. */ | |
166 | int nobopt; | |
167 | /* Non-zero if we should not autoextend mips16 instructions. | |
168 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
169 | int noautoextend; | |
a325df1d TS |
170 | /* Restrict general purpose registers and floating point registers |
171 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
172 | is passed but can changed if the assembler code uses .set mipsN. */ | |
173 | int gp32; | |
174 | int fp32; | |
175 | /* The ABI currently in use. This is changed by .set mipsN to loosen | |
176 | restrictions and doesn't affect the whole file. */ | |
177 | enum mips_abi_level abi; | |
252b5132 RH |
178 | }; |
179 | ||
a325df1d | 180 | /* True if -mgp32 was passed. */ |
a8e8e863 | 181 | static int file_mips_gp32 = -1; |
a325df1d TS |
182 | |
183 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 184 | static int file_mips_fp32 = -1; |
a325df1d | 185 | |
252b5132 | 186 | /* This is the struct we use to hold the current set of options. Note |
e7af610e NC |
187 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
188 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 189 | |
e972090a NC |
190 | static struct mips_set_options mips_opts = |
191 | { | |
1f25f5d3 | 192 | ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI |
e7af610e | 193 | }; |
252b5132 RH |
194 | |
195 | /* These variables are filled in with the masks of registers used. | |
196 | The object format code reads them and puts them in the appropriate | |
197 | place. */ | |
198 | unsigned long mips_gprmask; | |
199 | unsigned long mips_cprmask[4]; | |
200 | ||
201 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 202 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 203 | |
1f25f5d3 CD |
204 | /* True if -mips3d was passed or implied by arguments passed on the |
205 | command line (e.g., by -march). */ | |
206 | static int file_ase_mips3d; | |
207 | ||
ec68c924 | 208 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 209 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 210 | |
ec68c924 EC |
211 | /* The argument of the -march= flag. The architecture we are assembling. */ |
212 | static int mips_arch = CPU_UNKNOWN; | |
213 | ||
214 | /* The argument of the -mtune= flag. The architecture for which we | |
215 | are optimizing. */ | |
216 | static int mips_tune = CPU_UNKNOWN; | |
217 | ||
2f4dcb11 | 218 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
219 | static int mips_eabi64 = 0; |
220 | ||
221 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 222 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
223 | static int mips_32bitmode = 0; |
224 | ||
9ce8a5dd GRK |
225 | /* Some ISA's have delay slots for instructions which read or write |
226 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 227 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
228 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
229 | delay slot in this ISA. The uses of this macro assume that any | |
230 | ISA that has delay slots for one of these, has them for all. They | |
231 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 232 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 233 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
234 | (ISA) == ISA_MIPS1 \ |
235 | || (ISA) == ISA_MIPS2 \ | |
236 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
237 | ) |
238 | ||
bdaaa2e1 | 239 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 240 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS3 \ |
242 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 243 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 244 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
245 | ) |
246 | ||
e013f690 | 247 | #define HAVE_32BIT_GPRS \ |
a325df1d TS |
248 | (mips_opts.gp32 \ |
249 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 250 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 251 | |
e013f690 | 252 | #define HAVE_32BIT_FPRS \ |
a325df1d TS |
253 | (mips_opts.fp32 \ |
254 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 255 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
256 | |
257 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
258 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
259 | ||
a325df1d | 260 | #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI) |
e013f690 | 261 | |
a325df1d | 262 | #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI) |
e013f690 TS |
263 | |
264 | /* We can only have 64bit addresses if the object file format | |
265 | supports it. */ | |
afdbd6d0 CD |
266 | #define HAVE_32BIT_ADDRESSES \ |
267 | (HAVE_32BIT_GPRS \ | |
268 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
269 | || ! HAVE_64BIT_OBJECTS) \ | |
270 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
271 | |
272 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 273 | |
1f25f5d3 CD |
274 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
275 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
276 | ) | |
277 | ||
bdaaa2e1 | 278 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 279 | reads from the HI and LO registers, and thus does not |
ec68c924 | 280 | require nops to be inserted. */ |
252b5132 | 281 | |
ec68c924 | 282 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
0a758a12 | 283 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
284 | ) |
285 | ||
286 | /* Whether the processor uses hardware interlocks to protect reads | |
287 | from the GPRs, and thus does not require nops to be inserted. */ | |
288 | #define gpr_interlocks \ | |
e7af610e | 289 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 290 | || mips_arch == CPU_R3900) |
252b5132 RH |
291 | |
292 | /* As with other "interlocks" this is used by hardware that has FP | |
293 | (co-processor) interlocks. */ | |
bdaaa2e1 | 294 | /* Itbl support may require additional care here. */ |
ec68c924 | 295 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
0a758a12 | 296 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
297 | ) |
298 | ||
6b76fefe CM |
299 | /* Is this a mfhi or mflo instruction? */ |
300 | #define MF_HILO_INSN(PINFO) \ | |
301 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
302 | ||
252b5132 RH |
303 | /* MIPS PIC level. */ |
304 | ||
e972090a NC |
305 | enum mips_pic_level |
306 | { | |
252b5132 RH |
307 | /* Do not generate PIC code. */ |
308 | NO_PIC, | |
309 | ||
310 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
311 | not sure what it is supposed to do. */ | |
312 | IRIX4_PIC, | |
313 | ||
314 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
315 | SVR4_PIC, | |
316 | ||
317 | /* Generate PIC code without using a global offset table: the data | |
318 | segment has a maximum size of 64K, all data references are off | |
319 | the $gp register, and all text references are PC relative. This | |
320 | is used on some embedded systems. */ | |
321 | EMBEDDED_PIC | |
322 | }; | |
323 | ||
324 | static enum mips_pic_level mips_pic; | |
325 | ||
39c0a331 L |
326 | /* Warn about all NOPS that the assembler generates. */ |
327 | static int warn_nops = 0; | |
328 | ||
252b5132 RH |
329 | /* 1 if we should generate 32 bit offsets from the GP register in |
330 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
331 | static int mips_big_got; | |
332 | ||
333 | /* 1 if trap instructions should used for overflow rather than break | |
334 | instructions. */ | |
335 | static int mips_trap; | |
336 | ||
119d663a | 337 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 338 | by assembling two single width halves into two single width floating |
119d663a NC |
339 | point registers which just happen to alias the double width destination |
340 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 341 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
342 | automatically at assemble time. */ |
343 | static int mips_disable_float_construction; | |
344 | ||
252b5132 RH |
345 | /* Non-zero if any .set noreorder directives were used. */ |
346 | ||
347 | static int mips_any_noreorder; | |
348 | ||
6b76fefe CM |
349 | /* Non-zero if nops should be inserted when the register referenced in |
350 | an mfhi/mflo instruction is read in the next two instructions. */ | |
351 | static int mips_7000_hilo_fix; | |
352 | ||
252b5132 | 353 | /* The size of the small data section. */ |
156c2f8b | 354 | static unsigned int g_switch_value = 8; |
252b5132 RH |
355 | /* Whether the -G option was used. */ |
356 | static int g_switch_seen = 0; | |
357 | ||
358 | #define N_RMASK 0xc4 | |
359 | #define N_VFP 0xd4 | |
360 | ||
361 | /* If we can determine in advance that GP optimization won't be | |
362 | possible, we can skip the relaxation stuff that tries to produce | |
363 | GP-relative references. This makes delay slot optimization work | |
364 | better. | |
365 | ||
366 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
367 | gcc output. It needs to guess right for gcc, otherwise gcc |
368 | will put what it thinks is a GP-relative instruction in a branch | |
369 | delay slot. | |
252b5132 RH |
370 | |
371 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
372 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
373 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
374 | ||
375 | /* handle of the OPCODE hash table */ | |
376 | static struct hash_control *op_hash = NULL; | |
377 | ||
378 | /* The opcode hash table we use for the mips16. */ | |
379 | static struct hash_control *mips16_op_hash = NULL; | |
380 | ||
381 | /* This array holds the chars that always start a comment. If the | |
382 | pre-processor is disabled, these aren't very useful */ | |
383 | const char comment_chars[] = "#"; | |
384 | ||
385 | /* This array holds the chars that only start a comment at the beginning of | |
386 | a line. If the line seems to have the form '# 123 filename' | |
387 | .line and .file directives will appear in the pre-processed output */ | |
388 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
389 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 390 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
391 | /* Also note that C style comments are always supported. */ |
392 | const char line_comment_chars[] = "#"; | |
393 | ||
bdaaa2e1 | 394 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 395 | const char line_separator_chars[] = ";"; |
252b5132 RH |
396 | |
397 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
398 | const char EXP_CHARS[] = "eE"; | |
399 | ||
400 | /* Chars that mean this number is a floating point constant */ | |
401 | /* As in 0f12.456 */ | |
402 | /* or 0d1.2345e12 */ | |
403 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
404 | ||
405 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
406 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
407 | but nothing is ideal around here. | |
408 | */ | |
409 | ||
410 | static char *insn_error; | |
411 | ||
412 | static int auto_align = 1; | |
413 | ||
414 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
415 | offset in the stack frame from which to restore the $gp register. | |
416 | This is set by the .cprestore pseudo-op, and saved in this | |
417 | variable. */ | |
418 | static offsetT mips_cprestore_offset = -1; | |
419 | ||
6478892d TS |
420 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
421 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 422 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
423 | static offsetT mips_cpreturn_offset = -1; |
424 | static int mips_cpreturn_register = -1; | |
425 | static int mips_gp_register = GP; | |
426 | ||
7a621144 DJ |
427 | /* Whether mips_cprestore_offset has been set in the current function |
428 | (or whether it has already been warned about, if not). */ | |
429 | static int mips_cprestore_valid = 0; | |
430 | ||
252b5132 RH |
431 | /* This is the register which holds the stack frame, as set by the |
432 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
433 | static int mips_frame_reg = SP; | |
434 | ||
7a621144 DJ |
435 | /* Whether mips_frame_reg has been set in the current function |
436 | (or whether it has already been warned about, if not). */ | |
437 | static int mips_frame_reg_valid = 0; | |
438 | ||
252b5132 RH |
439 | /* To output NOP instructions correctly, we need to keep information |
440 | about the previous two instructions. */ | |
441 | ||
442 | /* Whether we are optimizing. The default value of 2 means to remove | |
443 | unneeded NOPs and swap branch instructions when possible. A value | |
444 | of 1 means to not swap branches. A value of 0 means to always | |
445 | insert NOPs. */ | |
446 | static int mips_optimize = 2; | |
447 | ||
448 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
449 | equivalent to seeing no -g option at all. */ | |
450 | static int mips_debug = 0; | |
451 | ||
452 | /* The previous instruction. */ | |
453 | static struct mips_cl_insn prev_insn; | |
454 | ||
455 | /* The instruction before prev_insn. */ | |
456 | static struct mips_cl_insn prev_prev_insn; | |
457 | ||
458 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
459 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 460 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
461 | |
462 | /* Non-zero if prev_insn is valid. */ | |
463 | static int prev_insn_valid; | |
464 | ||
465 | /* The frag for the previous instruction. */ | |
466 | static struct frag *prev_insn_frag; | |
467 | ||
468 | /* The offset into prev_insn_frag for the previous instruction. */ | |
469 | static long prev_insn_where; | |
470 | ||
471 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 472 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
473 | |
474 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 475 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
476 | |
477 | /* Non-zero if the previous instruction was in a delay slot. */ | |
478 | static int prev_insn_is_delay_slot; | |
479 | ||
480 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
481 | static int prev_insn_unreordered; | |
482 | ||
483 | /* Non-zero if the previous instruction uses an extend opcode (if | |
484 | mips16). */ | |
485 | static int prev_insn_extended; | |
486 | ||
487 | /* Non-zero if the previous previous instruction was in a .set | |
488 | noreorder. */ | |
489 | static int prev_prev_insn_unreordered; | |
490 | ||
491 | /* If this is set, it points to a frag holding nop instructions which | |
492 | were inserted before the start of a noreorder section. If those | |
493 | nops turn out to be unnecessary, the size of the frag can be | |
494 | decreased. */ | |
495 | static fragS *prev_nop_frag; | |
496 | ||
497 | /* The number of nop instructions we created in prev_nop_frag. */ | |
498 | static int prev_nop_frag_holds; | |
499 | ||
500 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 501 | prev_nop_frag. */ |
252b5132 RH |
502 | static int prev_nop_frag_required; |
503 | ||
504 | /* The number of instructions we've seen since prev_nop_frag. */ | |
505 | static int prev_nop_frag_since; | |
506 | ||
507 | /* For ECOFF and ELF, relocations against symbols are done in two | |
508 | parts, with a HI relocation and a LO relocation. Each relocation | |
509 | has only 16 bits of space to store an addend. This means that in | |
510 | order for the linker to handle carries correctly, it must be able | |
511 | to locate both the HI and the LO relocation. This means that the | |
512 | relocations must appear in order in the relocation table. | |
513 | ||
514 | In order to implement this, we keep track of each unmatched HI | |
515 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 516 | corresponding LO relocation. */ |
252b5132 | 517 | |
e972090a NC |
518 | struct mips_hi_fixup |
519 | { | |
252b5132 RH |
520 | /* Next HI fixup. */ |
521 | struct mips_hi_fixup *next; | |
522 | /* This fixup. */ | |
523 | fixS *fixp; | |
524 | /* The section this fixup is in. */ | |
525 | segT seg; | |
526 | }; | |
527 | ||
528 | /* The list of unmatched HI relocs. */ | |
529 | ||
530 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
531 | ||
532 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
533 | ||
534 | #define X ILLEGAL_REG | |
e972090a NC |
535 | static const int mips32_to_16_reg_map[] = |
536 | { | |
252b5132 RH |
537 | X, X, 2, 3, 4, 5, 6, 7, |
538 | X, X, X, X, X, X, X, X, | |
539 | 0, 1, X, X, X, X, X, X, | |
540 | X, X, X, X, X, X, X, X | |
541 | }; | |
542 | #undef X | |
543 | ||
544 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
545 | ||
e972090a NC |
546 | static const unsigned int mips16_to_32_reg_map[] = |
547 | { | |
252b5132 RH |
548 | 16, 17, 2, 3, 4, 5, 6, 7 |
549 | }; | |
550 | \f | |
551 | /* Since the MIPS does not have multiple forms of PC relative | |
552 | instructions, we do not have to do relaxing as is done on other | |
553 | platforms. However, we do have to handle GP relative addressing | |
554 | correctly, which turns out to be a similar problem. | |
555 | ||
556 | Every macro that refers to a symbol can occur in (at least) two | |
557 | forms, one with GP relative addressing and one without. For | |
558 | example, loading a global variable into a register generally uses | |
559 | a macro instruction like this: | |
560 | lw $4,i | |
561 | If i can be addressed off the GP register (this is true if it is in | |
562 | the .sbss or .sdata section, or if it is known to be smaller than | |
563 | the -G argument) this will generate the following instruction: | |
564 | lw $4,i($gp) | |
565 | This instruction will use a GPREL reloc. If i can not be addressed | |
566 | off the GP register, the following instruction sequence will be used: | |
567 | lui $at,i | |
568 | lw $4,i($at) | |
569 | In this case the first instruction will have a HI16 reloc, and the | |
570 | second reloc will have a LO16 reloc. Both relocs will be against | |
571 | the symbol i. | |
572 | ||
573 | The issue here is that we may not know whether i is GP addressable | |
574 | until after we see the instruction that uses it. Therefore, we | |
575 | want to be able to choose the final instruction sequence only at | |
576 | the end of the assembly. This is similar to the way other | |
577 | platforms choose the size of a PC relative instruction only at the | |
578 | end of assembly. | |
579 | ||
580 | When generating position independent code we do not use GP | |
581 | addressing in quite the same way, but the issue still arises as | |
582 | external symbols and local symbols must be handled differently. | |
583 | ||
584 | We handle these issues by actually generating both possible | |
585 | instruction sequences. The longer one is put in a frag_var with | |
586 | type rs_machine_dependent. We encode what to do with the frag in | |
587 | the subtype field. We encode (1) the number of existing bytes to | |
588 | replace, (2) the number of new bytes to use, (3) the offset from | |
589 | the start of the existing bytes to the first reloc we must generate | |
590 | (that is, the offset is applied from the start of the existing | |
591 | bytes after they are replaced by the new bytes, if any), (4) the | |
592 | offset from the start of the existing bytes to the second reloc, | |
593 | (5) whether a third reloc is needed (the third reloc is always four | |
594 | bytes after the second reloc), and (6) whether to warn if this | |
595 | variant is used (this is sometimes needed if .set nomacro or .set | |
596 | noat is in effect). All these numbers are reasonably small. | |
597 | ||
598 | Generating two instruction sequences must be handled carefully to | |
599 | ensure that delay slots are handled correctly. Fortunately, there | |
600 | are a limited number of cases. When the second instruction | |
601 | sequence is generated, append_insn is directed to maintain the | |
602 | existing delay slot information, so it continues to apply to any | |
603 | code after the second instruction sequence. This means that the | |
604 | second instruction sequence must not impose any requirements not | |
605 | required by the first instruction sequence. | |
606 | ||
607 | These variant frags are then handled in functions called by the | |
608 | machine independent code. md_estimate_size_before_relax returns | |
609 | the final size of the frag. md_convert_frag sets up the final form | |
610 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
611 | one if needed. */ | |
612 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
613 | ((relax_substateT) \ | |
614 | (((old) << 23) \ | |
615 | | ((new) << 16) \ | |
616 | | (((reloc1) + 64) << 9) \ | |
617 | | (((reloc2) + 64) << 2) \ | |
618 | | ((reloc3) ? (1 << 1) : 0) \ | |
619 | | ((warn) ? 1 : 0))) | |
620 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
621 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
622 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
623 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
624 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
625 | #define RELAX_WARN(i) ((i) & 1) | |
626 | ||
627 | /* For mips16 code, we use an entirely different form of relaxation. | |
628 | mips16 supports two versions of most instructions which take | |
629 | immediate values: a small one which takes some small value, and a | |
630 | larger one which takes a 16 bit value. Since branches also follow | |
631 | this pattern, relaxing these values is required. | |
632 | ||
633 | We can assemble both mips16 and normal MIPS code in a single | |
634 | object. Therefore, we need to support this type of relaxation at | |
635 | the same time that we support the relaxation described above. We | |
636 | use the high bit of the subtype field to distinguish these cases. | |
637 | ||
638 | The information we store for this type of relaxation is the | |
639 | argument code found in the opcode file for this relocation, whether | |
640 | the user explicitly requested a small or extended form, and whether | |
641 | the relocation is in a jump or jal delay slot. That tells us the | |
642 | size of the value, and how it should be stored. We also store | |
643 | whether the fragment is considered to be extended or not. We also | |
644 | store whether this is known to be a branch to a different section, | |
645 | whether we have tried to relax this frag yet, and whether we have | |
646 | ever extended a PC relative fragment because of a shift count. */ | |
647 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
648 | (0x80000000 \ | |
649 | | ((type) & 0xff) \ | |
650 | | ((small) ? 0x100 : 0) \ | |
651 | | ((ext) ? 0x200 : 0) \ | |
652 | | ((dslot) ? 0x400 : 0) \ | |
653 | | ((jal_dslot) ? 0x800 : 0)) | |
654 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
655 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
656 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
657 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
658 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
659 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
660 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
661 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
662 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
663 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
664 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
665 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
666 | \f | |
667 | /* Prototypes for static functions. */ | |
668 | ||
669 | #ifdef __STDC__ | |
670 | #define internalError() \ | |
671 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
672 | #else | |
673 | #define internalError() as_fatal (_("MIPS internal Error")); | |
674 | #endif | |
675 | ||
676 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
677 | ||
678 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
679 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 680 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
681 | static void mips16_mark_labels PARAMS ((void)); |
682 | static void append_insn PARAMS ((char *place, | |
683 | struct mips_cl_insn * ip, | |
684 | expressionS * p, | |
f6688943 | 685 | bfd_reloc_code_real_type *r, |
252b5132 RH |
686 | boolean)); |
687 | static void mips_no_prev_insn PARAMS ((int)); | |
688 | static void mips_emit_delays PARAMS ((boolean)); | |
689 | #ifdef USE_STDARG | |
690 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
691 | const char *name, const char *fmt, | |
692 | ...)); | |
693 | #else | |
694 | static void macro_build (); | |
695 | #endif | |
696 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
697 | const char *, const char *, | |
698 | va_list)); | |
699 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
700 | expressionS * ep, int regnum)); | |
701 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
702 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
703 | expressionS *)); | |
704 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
d6bc6245 | 705 | static void load_address PARAMS ((int *, int, expressionS *, int, int *)); |
ea1fb5dc | 706 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
707 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
708 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
709 | #ifdef LOSING_COMPILER | |
710 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
711 | #endif | |
712 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
713 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
714 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
715 | boolean, boolean, unsigned long *, | |
716 | boolean *, unsigned short *)); | |
394f9b3a | 717 | static int my_getPercentOp PARAMS ((char **, unsigned int *, int *)); |
ad8d3bb3 TS |
718 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
719 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
720 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
ae948b86 | 721 | #ifdef OBJ_ELF |
e013f690 | 722 | static int support_64bit_objects PARAMS((void)); |
ae948b86 | 723 | #endif |
252b5132 RH |
724 | static symbolS *get_symbol PARAMS ((void)); |
725 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
726 | static void s_align PARAMS ((int)); | |
727 | static void s_change_sec PARAMS ((int)); | |
728 | static void s_cons PARAMS ((int)); | |
729 | static void s_float_cons PARAMS ((int)); | |
730 | static void s_mips_globl PARAMS ((int)); | |
731 | static void s_option PARAMS ((int)); | |
732 | static void s_mipsset PARAMS ((int)); | |
733 | static void s_abicalls PARAMS ((int)); | |
734 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
735 | static void s_cpsetup PARAMS ((int)); |
736 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 737 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
738 | static void s_cpreturn PARAMS ((int)); |
739 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
740 | static void s_gpword PARAMS ((int)); |
741 | static void s_cpadd PARAMS ((int)); | |
742 | static void s_insn PARAMS ((int)); | |
743 | static void md_obj_begin PARAMS ((void)); | |
744 | static void md_obj_end PARAMS ((void)); | |
745 | static long get_number PARAMS ((void)); | |
746 | static void s_mips_ent PARAMS ((int)); | |
747 | static void s_mips_end PARAMS ((int)); | |
748 | static void s_mips_frame PARAMS ((int)); | |
749 | static void s_mips_mask PARAMS ((int)); | |
750 | static void s_mips_stab PARAMS ((int)); | |
751 | static void s_mips_weakext PARAMS ((int)); | |
752 | static void s_file PARAMS ((int)); | |
753 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
754 | static const char *mips_isa_to_str PARAMS ((int)); |
755 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 756 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e87a0284 | 757 | static void show PARAMS ((FILE *, char *, int *, int *)); |
add55e1f RS |
758 | #ifdef OBJ_ELF |
759 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); | |
760 | #endif | |
e7af610e | 761 | |
ad8d3bb3 | 762 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 763 | |
ad8d3bb3 | 764 | enum small_ex_type |
fb1b3232 TS |
765 | { |
766 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
767 | S_EX_REGISTER, |
768 | ||
769 | /* Direct relocation creation by %percent_op(). */ | |
770 | S_EX_HALF, | |
fb1b3232 | 771 | S_EX_HI, |
ad8d3bb3 TS |
772 | S_EX_LO, |
773 | S_EX_GP_REL, | |
774 | S_EX_GOT, | |
775 | S_EX_CALL16, | |
776 | S_EX_GOT_DISP, | |
777 | S_EX_GOT_PAGE, | |
778 | S_EX_GOT_OFST, | |
779 | S_EX_GOT_HI, | |
780 | S_EX_GOT_LO, | |
781 | S_EX_NEG, | |
fb1b3232 TS |
782 | S_EX_HIGHER, |
783 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
784 | S_EX_CALL_HI, |
785 | S_EX_CALL_LO | |
fb1b3232 TS |
786 | }; |
787 | ||
e7af610e NC |
788 | /* Table and functions used to map between CPU/ISA names, and |
789 | ISA levels, and CPU numbers. */ | |
790 | ||
e972090a NC |
791 | struct mips_cpu_info |
792 | { | |
e7af610e NC |
793 | const char *name; /* CPU or ISA name. */ |
794 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
795 | int isa; /* ISA level. */ | |
796 | int cpu; /* CPU number (default CPU if ISA). */ | |
797 | }; | |
798 | ||
799 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
800 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
801 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
802 | \f |
803 | /* Pseudo-op table. | |
804 | ||
805 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
806 | should be defined here, but are currently unsupported: .alias, | |
807 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
808 | ||
809 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
810 | specific to the type of debugging information being generated, and | |
811 | should be defined by the object format: .aent, .begin, .bend, | |
812 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
813 | .vreg. | |
814 | ||
815 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
816 | not MIPS CPU specific, but are also not specific to the object file | |
817 | format. This file is probably the best place to define them, but | |
818 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
819 | .struct. */ | |
820 | ||
e972090a NC |
821 | static const pseudo_typeS mips_pseudo_table[] = |
822 | { | |
beae10d5 | 823 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
824 | {"option", s_option, 0}, |
825 | {"set", s_mipsset, 0}, | |
826 | {"rdata", s_change_sec, 'r'}, | |
827 | {"sdata", s_change_sec, 's'}, | |
828 | {"livereg", s_ignore, 0}, | |
829 | {"abicalls", s_abicalls, 0}, | |
830 | {"cpload", s_cpload, 0}, | |
6478892d TS |
831 | {"cpsetup", s_cpsetup, 0}, |
832 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 833 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
834 | {"cpreturn", s_cpreturn, 0}, |
835 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
836 | {"gpword", s_gpword, 0}, |
837 | {"cpadd", s_cpadd, 0}, | |
838 | {"insn", s_insn, 0}, | |
839 | ||
beae10d5 | 840 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
841 | chips. */ |
842 | {"asciiz", stringer, 1}, | |
843 | {"bss", s_change_sec, 'b'}, | |
844 | {"err", s_err, 0}, | |
845 | {"half", s_cons, 1}, | |
846 | {"dword", s_cons, 3}, | |
847 | {"weakext", s_mips_weakext, 0}, | |
848 | ||
beae10d5 | 849 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
850 | here for one reason or another. */ |
851 | {"align", s_align, 0}, | |
852 | {"byte", s_cons, 0}, | |
853 | {"data", s_change_sec, 'd'}, | |
854 | {"double", s_float_cons, 'd'}, | |
855 | {"float", s_float_cons, 'f'}, | |
856 | {"globl", s_mips_globl, 0}, | |
857 | {"global", s_mips_globl, 0}, | |
858 | {"hword", s_cons, 1}, | |
859 | {"int", s_cons, 2}, | |
860 | {"long", s_cons, 2}, | |
861 | {"octa", s_cons, 4}, | |
862 | {"quad", s_cons, 3}, | |
863 | {"short", s_cons, 1}, | |
864 | {"single", s_float_cons, 'f'}, | |
865 | {"stabn", s_mips_stab, 'n'}, | |
866 | {"text", s_change_sec, 't'}, | |
867 | {"word", s_cons, 2}, | |
add56521 L |
868 | |
869 | #ifdef MIPS_STABS_ELF | |
870 | { "extern", ecoff_directive_extern, 0}, | |
871 | #endif | |
872 | ||
43841e91 | 873 | { NULL, NULL, 0 }, |
252b5132 RH |
874 | }; |
875 | ||
e972090a NC |
876 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
877 | { | |
beae10d5 KH |
878 | /* These pseudo-ops should be defined by the object file format. |
879 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
880 | {"aent", s_mips_ent, 1}, |
881 | {"bgnb", s_ignore, 0}, | |
882 | {"end", s_mips_end, 0}, | |
883 | {"endb", s_ignore, 0}, | |
884 | {"ent", s_mips_ent, 0}, | |
885 | {"file", s_file, 0}, | |
886 | {"fmask", s_mips_mask, 'F'}, | |
887 | {"frame", s_mips_frame, 0}, | |
888 | {"loc", s_ignore, 0}, | |
889 | {"mask", s_mips_mask, 'R'}, | |
890 | {"verstamp", s_ignore, 0}, | |
43841e91 | 891 | { NULL, NULL, 0 }, |
252b5132 RH |
892 | }; |
893 | ||
894 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
895 | ||
896 | void | |
897 | mips_pop_insert () | |
898 | { | |
899 | pop_insert (mips_pseudo_table); | |
900 | if (! ECOFF_DEBUGGING) | |
901 | pop_insert (mips_nonecoff_pseudo_table); | |
902 | } | |
903 | \f | |
904 | /* Symbols labelling the current insn. */ | |
905 | ||
e972090a NC |
906 | struct insn_label_list |
907 | { | |
252b5132 RH |
908 | struct insn_label_list *next; |
909 | symbolS *label; | |
910 | }; | |
911 | ||
912 | static struct insn_label_list *insn_labels; | |
913 | static struct insn_label_list *free_insn_labels; | |
914 | ||
915 | static void mips_clear_insn_labels PARAMS ((void)); | |
916 | ||
917 | static inline void | |
918 | mips_clear_insn_labels () | |
919 | { | |
920 | register struct insn_label_list **pl; | |
921 | ||
922 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
923 | ; | |
924 | *pl = insn_labels; | |
925 | insn_labels = NULL; | |
926 | } | |
927 | \f | |
928 | static char *expr_end; | |
929 | ||
930 | /* Expressions which appear in instructions. These are set by | |
931 | mips_ip. */ | |
932 | ||
933 | static expressionS imm_expr; | |
934 | static expressionS offset_expr; | |
935 | ||
936 | /* Relocs associated with imm_expr and offset_expr. */ | |
937 | ||
f6688943 TS |
938 | static bfd_reloc_code_real_type imm_reloc[3] |
939 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
940 | static bfd_reloc_code_real_type offset_reloc[3] | |
941 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
942 | |
943 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
944 | ||
945 | static boolean imm_unmatched_hi; | |
946 | ||
947 | /* These are set by mips16_ip if an explicit extension is used. */ | |
948 | ||
949 | static boolean mips16_small, mips16_ext; | |
950 | ||
951 | #ifdef MIPS_STABS_ELF | |
952 | /* The pdr segment for per procedure frame/regmask info */ | |
953 | ||
954 | static segT pdr_seg; | |
955 | #endif | |
956 | ||
e7af610e NC |
957 | static const char * |
958 | mips_isa_to_str (isa) | |
959 | int isa; | |
960 | { | |
961 | const struct mips_cpu_info *ci; | |
962 | static char s[20]; | |
963 | ||
964 | ci = mips_cpu_info_from_isa (isa); | |
965 | if (ci != NULL) | |
966 | return (ci->name); | |
967 | ||
968 | sprintf (s, "ISA#%d", isa); | |
969 | return s; | |
970 | } | |
971 | ||
972 | static const char * | |
156c2f8b NC |
973 | mips_cpu_to_str (cpu) |
974 | int cpu; | |
975 | { | |
e7af610e | 976 | const struct mips_cpu_info *ci; |
156c2f8b | 977 | static char s[16]; |
e7af610e NC |
978 | |
979 | ci = mips_cpu_info_from_cpu (cpu); | |
980 | if (ci != NULL) | |
981 | return (ci->name); | |
982 | ||
983 | sprintf (s, "CPU#%d", cpu); | |
984 | return s; | |
156c2f8b NC |
985 | } |
986 | ||
e013f690 TS |
987 | /* The default target format to use. */ |
988 | ||
989 | const char * | |
990 | mips_target_format () | |
991 | { | |
992 | switch (OUTPUT_FLAVOR) | |
993 | { | |
994 | case bfd_target_aout_flavour: | |
995 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
996 | case bfd_target_ecoff_flavour: | |
997 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
998 | case bfd_target_coff_flavour: | |
999 | return "pe-mips"; | |
1000 | case bfd_target_elf_flavour: | |
1001 | #ifdef TE_TMIPS | |
1002 | /* This is traditional mips */ | |
1003 | return (target_big_endian | |
1004 | ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips" | |
1005 | : "elf32-tradbigmips") | |
1006 | : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips" | |
1007 | : "elf32-tradlittlemips")); | |
1008 | #else | |
1009 | return (target_big_endian | |
1010 | ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips") | |
1011 | : (HAVE_64BIT_OBJECTS ? "elf64-littlemips" | |
1012 | : "elf32-littlemips")); | |
1013 | #endif | |
1014 | default: | |
1015 | abort (); | |
1016 | return NULL; | |
1017 | } | |
1018 | } | |
1019 | ||
156c2f8b NC |
1020 | /* This function is called once, at assembler startup time. It should |
1021 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1022 | ||
252b5132 RH |
1023 | void |
1024 | md_begin () | |
1025 | { | |
252b5132 | 1026 | register const char *retval = NULL; |
156c2f8b | 1027 | int i = 0; |
252b5132 RH |
1028 | const char *cpu; |
1029 | char *a = NULL; | |
1030 | int broken = 0; | |
1031 | int mips_isa_from_cpu; | |
e7af610e NC |
1032 | int target_cpu_had_mips16 = 0; |
1033 | const struct mips_cpu_info *ci; | |
252b5132 | 1034 | |
056350c6 NC |
1035 | /* GP relative stuff not working for PE */ |
1036 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
1037 | && g_switch_value != 0) | |
1038 | { | |
1039 | if (g_switch_seen) | |
1040 | as_bad (_("-G not supported in this configuration.")); | |
1041 | g_switch_value = 0; | |
1042 | } | |
1043 | ||
252b5132 RH |
1044 | cpu = TARGET_CPU; |
1045 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
1046 | { | |
1047 | a = xmalloc (sizeof TARGET_CPU); | |
1048 | strcpy (a, TARGET_CPU); | |
1049 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
1050 | cpu = a; | |
1051 | } | |
1052 | ||
e7af610e | 1053 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 1054 | { |
e7af610e NC |
1055 | target_cpu_had_mips16 = 1; |
1056 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
1057 | } |
1058 | ||
e7af610e NC |
1059 | if (mips_opts.mips16 < 0) |
1060 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 1061 | |
6dce9e24 TS |
1062 | /* Backward compatibility for historic -mcpu= option. Check for |
1063 | incompatible options, warn if -mcpu is used. */ | |
1064 | if (mips_cpu != CPU_UNKNOWN | |
1065 | && mips_arch != CPU_UNKNOWN | |
1066 | && mips_cpu != mips_arch) | |
1067 | { | |
1068 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
1069 | "Use -mtune instead of -mcpu.")); | |
1070 | } | |
1071 | ||
1072 | if (mips_cpu != CPU_UNKNOWN | |
1073 | && mips_tune != CPU_UNKNOWN | |
1074 | && mips_cpu != mips_tune) | |
1075 | { | |
1076 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
1077 | "Use -march instead of -mcpu.")); | |
1078 | } | |
1079 | ||
a8e8e863 DJ |
1080 | #if 1 |
1081 | /* For backward compatibility, let -mipsN set various defaults. */ | |
1082 | /* This code should go away, to be replaced with something rather more | |
1083 | draconian. Until GCC 3.1 has been released for some reasonable | |
1084 | amount of time, however, we need to support this. */ | |
1085 | if (mips_opts.isa != ISA_UNKNOWN) | |
1086 | { | |
1087 | /* Translate -mipsN to the appropriate settings of file_mips_gp32 | |
1088 | and file_mips_fp32. Tag binaries as using the mipsN ISA. */ | |
1089 | if (file_mips_gp32 < 0) | |
1090 | { | |
1091 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1092 | file_mips_gp32 = 0; | |
1093 | else | |
1094 | file_mips_gp32 = 1; | |
1095 | } | |
1096 | if (file_mips_fp32 < 0) | |
1097 | { | |
1098 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1099 | file_mips_fp32 = 0; | |
1100 | else | |
1101 | file_mips_fp32 = 1; | |
1102 | } | |
1103 | ||
1104 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1105 | assert (ci != NULL); | |
1106 | /* -mipsN has higher priority than -mcpu but lower than -march. */ | |
1107 | if (mips_arch == CPU_UNKNOWN) | |
1108 | mips_arch = ci->cpu; | |
1109 | ||
1110 | /* Default mips_abi. */ | |
1111 | if (mips_opts.abi == NO_ABI) | |
1112 | { | |
1113 | if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2) | |
1114 | mips_opts.abi = O32_ABI; | |
1115 | else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4) | |
1116 | mips_opts.abi = O64_ABI; | |
1117 | } | |
1118 | } | |
1119 | ||
6dce9e24 TS |
1120 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) |
1121 | { | |
1122 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1123 | assert (ci != NULL); | |
1124 | mips_arch = ci->cpu; | |
1125 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1126 | "-mtune instead.")); | |
1127 | } | |
1128 | ||
a8e8e863 DJ |
1129 | /* Set tune from -mcpu, not from -mipsN. */ |
1130 | if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1131 | { | |
1132 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1133 | assert (ci != NULL); | |
1134 | mips_tune = ci->cpu; | |
1135 | } | |
1136 | ||
ec68c924 | 1137 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
1138 | specified on the command line, or some other value if one was. |
1139 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1140 | the command line, or will be set otherwise if one was. */ | |
a8e8e863 DJ |
1141 | |
1142 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) | |
1143 | /* Handled above. */; | |
1144 | #else | |
1145 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1146 | { | |
1147 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1148 | assert (ci != NULL); | |
1149 | mips_arch = ci->cpu; | |
1150 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1151 | "-mtune instead.")); | |
1152 | } | |
1153 | ||
1154 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was | |
1155 | specified on the command line, or some other value if one was. | |
1156 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1157 | the command line, or will be set otherwise if one was. */ | |
1158 | ||
ec68c924 | 1159 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 1160 | { |
1ff54a84 TS |
1161 | /* We have to check if the isa is the default isa of arch. Otherwise |
1162 | we'll get invalid object file headers. */ | |
1163 | ci = mips_cpu_info_from_cpu (mips_arch); | |
1164 | assert (ci != NULL); | |
1165 | if (mips_opts.isa != ci->isa) | |
1166 | { | |
1167 | /* This really should be an error instead of a warning, but old | |
1168 | compilers only have -mcpu which sets both arch and tune. For | |
1169 | now, we discard arch and preserve tune. */ | |
1170 | as_warn (_("The -march option is incompatible to -mipsN and " | |
1171 | "therefore ignored.")); | |
1172 | if (mips_tune == CPU_UNKNOWN) | |
1173 | mips_tune = mips_arch; | |
1174 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1175 | assert (ci != NULL); | |
1176 | mips_arch = ci->cpu; | |
1177 | } | |
252b5132 | 1178 | } |
a8e8e863 | 1179 | #endif |
ec68c924 | 1180 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1181 | { |
ec68c924 EC |
1182 | /* We have ARCH, we need ISA. */ |
1183 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1184 | assert (ci != NULL); |
1185 | mips_opts.isa = ci->isa; | |
1186 | } | |
ec68c924 | 1187 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1188 | { |
ec68c924 | 1189 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1190 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1191 | assert (ci != NULL); | |
ec68c924 EC |
1192 | mips_arch = ci->cpu; |
1193 | } | |
e7af610e NC |
1194 | else |
1195 | { | |
ec68c924 | 1196 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1197 | ci = mips_cpu_info_from_name (cpu); |
1198 | if (ci == NULL) | |
beae10d5 | 1199 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1200 | assert (ci != NULL); |
1201 | mips_opts.isa = ci->isa; | |
ec68c924 | 1202 | mips_arch = ci->cpu; |
252b5132 RH |
1203 | } |
1204 | ||
ec68c924 EC |
1205 | if (mips_tune == CPU_UNKNOWN) |
1206 | mips_tune = mips_arch; | |
1207 | ||
1208 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1209 | assert (ci != NULL); |
1210 | mips_isa_from_cpu = ci->isa; | |
1211 | ||
252b5132 | 1212 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1213 | if necessary. */ |
252b5132 RH |
1214 | cpu = NULL; |
1215 | if (a != NULL) | |
1216 | { | |
156c2f8b NC |
1217 | free (a); |
1218 | a = NULL; | |
252b5132 RH |
1219 | } |
1220 | ||
e7af610e | 1221 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1222 | as_bad (_("trap exception not supported at ISA 1")); |
1223 | ||
1224 | /* Set the EABI kind based on the ISA before the user gets | |
1225 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1226 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1227 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
a325df1d | 1228 | && mips_opts.abi == EABI_ABI) |
252b5132 RH |
1229 | mips_eabi64 = 1; |
1230 | ||
e7af610e NC |
1231 | /* If they asked for mips1 or mips2 and a cpu that is |
1232 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1233 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1234 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1235 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1236 | mips_32bitmode = 1; | |
252b5132 | 1237 | |
1f25f5d3 CD |
1238 | /* If the selected architecture includes support for ASEs, enable |
1239 | generation of code for them. */ | |
1240 | if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch)) | |
1241 | mips_opts.ase_mips3d = 1; | |
1242 | ||
ec68c924 | 1243 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1244 | as_warn (_("Could not set architecture and machine")); |
1245 | ||
a8e8e863 DJ |
1246 | if (file_mips_gp32 < 0) |
1247 | file_mips_gp32 = 0; | |
1248 | if (file_mips_fp32 < 0) | |
1249 | file_mips_fp32 = 0; | |
1250 | ||
252b5132 | 1251 | file_mips_isa = mips_opts.isa; |
a325df1d | 1252 | file_mips_abi = mips_opts.abi; |
1f25f5d3 | 1253 | file_ase_mips3d = mips_opts.ase_mips3d; |
a325df1d TS |
1254 | mips_opts.gp32 = file_mips_gp32; |
1255 | mips_opts.fp32 = file_mips_fp32; | |
252b5132 RH |
1256 | |
1257 | op_hash = hash_new (); | |
1258 | ||
1259 | for (i = 0; i < NUMOPCODES;) | |
1260 | { | |
1261 | const char *name = mips_opcodes[i].name; | |
1262 | ||
1263 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1264 | if (retval != NULL) | |
1265 | { | |
1266 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1267 | mips_opcodes[i].name, retval); | |
1268 | /* Probably a memory allocation problem? Give up now. */ | |
1269 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1270 | } | |
1271 | do | |
1272 | { | |
1273 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1274 | { | |
1275 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1276 | broken = 1; | |
1277 | } | |
1278 | ++i; | |
1279 | } | |
1280 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1281 | } | |
1282 | ||
1283 | mips16_op_hash = hash_new (); | |
1284 | ||
1285 | i = 0; | |
1286 | while (i < bfd_mips16_num_opcodes) | |
1287 | { | |
1288 | const char *name = mips16_opcodes[i].name; | |
1289 | ||
1290 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1291 | if (retval != NULL) | |
1292 | as_fatal (_("internal: can't hash `%s': %s"), | |
1293 | mips16_opcodes[i].name, retval); | |
1294 | do | |
1295 | { | |
1296 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1297 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1298 | != mips16_opcodes[i].match)) | |
1299 | { | |
1300 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1301 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1302 | broken = 1; | |
1303 | } | |
1304 | ++i; | |
1305 | } | |
1306 | while (i < bfd_mips16_num_opcodes | |
1307 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1308 | } | |
1309 | ||
1310 | if (broken) | |
1311 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1312 | ||
1313 | /* We add all the general register names to the symbol table. This | |
1314 | helps us detect invalid uses of them. */ | |
1315 | for (i = 0; i < 32; i++) | |
1316 | { | |
1317 | char buf[5]; | |
1318 | ||
1319 | sprintf (buf, "$%d", i); | |
1320 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1321 | &zero_address_frag)); | |
1322 | } | |
1323 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1324 | &zero_address_frag)); | |
1325 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1326 | &zero_address_frag)); | |
1327 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1328 | &zero_address_frag)); | |
1329 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1330 | &zero_address_frag)); | |
1331 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1332 | &zero_address_frag)); | |
1333 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1334 | &zero_address_frag)); | |
1335 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1336 | &zero_address_frag)); | |
1337 | ||
1338 | mips_no_prev_insn (false); | |
1339 | ||
1340 | mips_gprmask = 0; | |
1341 | mips_cprmask[0] = 0; | |
1342 | mips_cprmask[1] = 0; | |
1343 | mips_cprmask[2] = 0; | |
1344 | mips_cprmask[3] = 0; | |
1345 | ||
1346 | /* set the default alignment for the text section (2**2) */ | |
1347 | record_alignment (text_section, 2); | |
1348 | ||
1349 | if (USE_GLOBAL_POINTER_OPT) | |
1350 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1351 | ||
1352 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1353 | { | |
1354 | /* On a native system, sections must be aligned to 16 byte | |
1355 | boundaries. When configured for an embedded ELF target, we | |
1356 | don't bother. */ | |
1357 | if (strcmp (TARGET_OS, "elf") != 0) | |
1358 | { | |
1359 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1360 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1361 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1362 | } | |
1363 | ||
1364 | /* Create a .reginfo section for register masks and a .mdebug | |
1365 | section for debugging information. */ | |
1366 | { | |
1367 | segT seg; | |
1368 | subsegT subseg; | |
1369 | flagword flags; | |
1370 | segT sec; | |
1371 | ||
1372 | seg = now_seg; | |
1373 | subseg = now_subseg; | |
1374 | ||
1375 | /* The ABI says this section should be loaded so that the | |
1376 | running program can access it. However, we don't load it | |
1377 | if we are configured for an embedded target */ | |
1378 | flags = SEC_READONLY | SEC_DATA; | |
1379 | if (strcmp (TARGET_OS, "elf") != 0) | |
1380 | flags |= SEC_ALLOC | SEC_LOAD; | |
1381 | ||
195325d2 | 1382 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
1383 | { |
1384 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1385 | ||
195325d2 TS |
1386 | bfd_set_section_flags (stdoutput, sec, flags); |
1387 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1388 | |
252b5132 RH |
1389 | #ifdef OBJ_ELF |
1390 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1391 | #endif | |
1392 | } | |
1393 | else | |
1394 | { | |
1395 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1396 | .reginfo section. */ | |
1397 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1398 | bfd_set_section_flags (stdoutput, sec, flags); |
1399 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1400 | |
1401 | #ifdef OBJ_ELF | |
1402 | /* Set up the option header. */ | |
1403 | { | |
1404 | Elf_Internal_Options opthdr; | |
1405 | char *f; | |
1406 | ||
1407 | opthdr.kind = ODK_REGINFO; | |
1408 | opthdr.size = (sizeof (Elf_External_Options) | |
1409 | + sizeof (Elf64_External_RegInfo)); | |
1410 | opthdr.section = 0; | |
1411 | opthdr.info = 0; | |
1412 | f = frag_more (sizeof (Elf_External_Options)); | |
1413 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1414 | (Elf_External_Options *) f); | |
1415 | ||
1416 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1417 | } | |
1418 | #endif | |
1419 | } | |
1420 | ||
1421 | if (ECOFF_DEBUGGING) | |
1422 | { | |
1423 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1424 | (void) bfd_set_section_flags (stdoutput, sec, | |
1425 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1426 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1427 | } | |
1428 | ||
1429 | #ifdef MIPS_STABS_ELF | |
1430 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1431 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1432 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1433 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1434 | #endif | |
1435 | ||
1436 | subseg_set (seg, subseg); | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | if (! ECOFF_DEBUGGING) | |
1441 | md_obj_begin (); | |
1442 | } | |
1443 | ||
1444 | void | |
1445 | md_mips_end () | |
1446 | { | |
1447 | if (! ECOFF_DEBUGGING) | |
1448 | md_obj_end (); | |
1449 | } | |
1450 | ||
1451 | void | |
1452 | md_assemble (str) | |
1453 | char *str; | |
1454 | { | |
1455 | struct mips_cl_insn insn; | |
f6688943 TS |
1456 | bfd_reloc_code_real_type unused_reloc[3] |
1457 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1458 | |
1459 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1460 | imm_unmatched_hi = false; |
1461 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1462 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1463 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1464 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1465 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1466 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1467 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1468 | |
1469 | if (mips_opts.mips16) | |
1470 | mips16_ip (str, &insn); | |
1471 | else | |
1472 | { | |
1473 | mips_ip (str, &insn); | |
beae10d5 KH |
1474 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1475 | str, insn.insn_opcode)); | |
252b5132 RH |
1476 | } |
1477 | ||
1478 | if (insn_error) | |
1479 | { | |
1480 | as_bad ("%s `%s'", insn_error, str); | |
1481 | return; | |
1482 | } | |
1483 | ||
1484 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1485 | { | |
1486 | if (mips_opts.mips16) | |
1487 | mips16_macro (&insn); | |
1488 | else | |
1489 | macro (&insn); | |
1490 | } | |
1491 | else | |
1492 | { | |
1493 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1494 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1495 | else if (offset_expr.X_op != O_absent) |
c4e7957c | 1496 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
252b5132 | 1497 | else |
c4e7957c | 1498 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1499 | } |
1500 | } | |
1501 | ||
1502 | /* See whether instruction IP reads register REG. CLASS is the type | |
1503 | of register. */ | |
1504 | ||
1505 | static int | |
1506 | insn_uses_reg (ip, reg, class) | |
1507 | struct mips_cl_insn *ip; | |
1508 | unsigned int reg; | |
1509 | enum mips_regclass class; | |
1510 | { | |
1511 | if (class == MIPS16_REG) | |
1512 | { | |
1513 | assert (mips_opts.mips16); | |
1514 | reg = mips16_to_32_reg_map[reg]; | |
1515 | class = MIPS_GR_REG; | |
1516 | } | |
1517 | ||
1518 | /* Don't report on general register 0, since it never changes. */ | |
1519 | if (class == MIPS_GR_REG && reg == 0) | |
1520 | return 0; | |
1521 | ||
1522 | if (class == MIPS_FP_REG) | |
1523 | { | |
1524 | assert (! mips_opts.mips16); | |
1525 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1526 | This is not optimal, because it will introduce an unnecessary | |
1527 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1528 | need to distinguish reading both $f0 and $f1 or just one of | |
1529 | them. Note that we don't have to check the other way, | |
1530 | because there is no instruction that sets both $f0 and $f1 | |
1531 | and requires a delay. */ | |
1532 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1533 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1534 | == (reg &~ (unsigned) 1))) | |
1535 | return 1; | |
1536 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1537 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1538 | == (reg &~ (unsigned) 1))) | |
1539 | return 1; | |
1540 | } | |
1541 | else if (! mips_opts.mips16) | |
1542 | { | |
1543 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1544 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1545 | return 1; | |
1546 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1547 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1548 | return 1; | |
1549 | } | |
1550 | else | |
1551 | { | |
1552 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1553 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1554 | & MIPS16OP_MASK_RX)] | |
1555 | == reg)) | |
1556 | return 1; | |
1557 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1558 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1559 | & MIPS16OP_MASK_RY)] | |
1560 | == reg)) | |
1561 | return 1; | |
1562 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1563 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1564 | & MIPS16OP_MASK_MOVE32Z)] | |
1565 | == reg)) | |
1566 | return 1; | |
1567 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1568 | return 1; | |
1569 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1570 | return 1; | |
1571 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1572 | return 1; | |
1573 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1574 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1575 | & MIPS16OP_MASK_REGR32) == reg) | |
1576 | return 1; | |
1577 | } | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | /* This function returns true if modifying a register requires a | |
1583 | delay. */ | |
1584 | ||
1585 | static int | |
1586 | reg_needs_delay (reg) | |
156c2f8b | 1587 | unsigned int reg; |
252b5132 RH |
1588 | { |
1589 | unsigned long prev_pinfo; | |
1590 | ||
1591 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1592 | if (! mips_opts.noreorder | |
9ce8a5dd | 1593 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1594 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1595 | || (! gpr_interlocks | |
1596 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1597 | { | |
1598 | /* A load from a coprocessor or from memory. All load | |
1599 | delays delay the use of general register rt for one | |
1600 | instruction on the r3000. The r6000 and r4000 use | |
1601 | interlocks. */ | |
bdaaa2e1 | 1602 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1603 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1604 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1605 | return 1; | |
1606 | } | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1612 | handle them specially, such as generating jalx instructions when | |
1613 | needed. We also make them odd for the duration of the assembly, in | |
1614 | order to generate the right sort of code. We will make them even | |
1615 | in the adjust_symtab routine, while leaving them marked. This is | |
1616 | convenient for the debugger and the disassembler. The linker knows | |
1617 | to make them odd again. */ | |
1618 | ||
1619 | static void | |
1620 | mips16_mark_labels () | |
1621 | { | |
1622 | if (mips_opts.mips16) | |
1623 | { | |
1624 | struct insn_label_list *l; | |
98aa84af | 1625 | valueT val; |
252b5132 RH |
1626 | |
1627 | for (l = insn_labels; l != NULL; l = l->next) | |
1628 | { | |
1629 | #ifdef OBJ_ELF | |
1630 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1631 | S_SET_OTHER (l->label, STO_MIPS16); | |
1632 | #endif | |
98aa84af AM |
1633 | val = S_GET_VALUE (l->label); |
1634 | if ((val & 1) == 0) | |
1635 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1636 | } |
1637 | } | |
1638 | } | |
1639 | ||
1640 | /* Output an instruction. PLACE is where to put the instruction; if | |
1641 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1642 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1643 | used with RELOC_TYPE. */ | |
1644 | ||
1645 | static void | |
1646 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1647 | char *place; | |
1648 | struct mips_cl_insn *ip; | |
1649 | expressionS *address_expr; | |
f6688943 | 1650 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1651 | boolean unmatched_hi; |
1652 | { | |
1653 | register unsigned long prev_pinfo, pinfo; | |
1654 | char *f; | |
f6688943 | 1655 | fixS *fixp[3]; |
252b5132 RH |
1656 | int nops = 0; |
1657 | ||
1658 | /* Mark instruction labels in mips16 mode. */ | |
1659 | if (mips_opts.mips16) | |
1660 | mips16_mark_labels (); | |
1661 | ||
1662 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1663 | pinfo = ip->insn_mo->pinfo; | |
1664 | ||
1665 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1666 | { | |
1667 | int prev_prev_nop; | |
1668 | ||
1669 | /* If the previous insn required any delay slots, see if we need | |
1670 | to insert a NOP or two. There are eight kinds of possible | |
1671 | hazards, of which an instruction can have at most one type. | |
1672 | (1) a load from memory delay | |
1673 | (2) a load from a coprocessor delay | |
1674 | (3) an unconditional branch delay | |
1675 | (4) a conditional branch delay | |
1676 | (5) a move to coprocessor register delay | |
1677 | (6) a load coprocessor register from memory delay | |
1678 | (7) a coprocessor condition code delay | |
1679 | (8) a HI/LO special register delay | |
1680 | ||
1681 | There are a lot of optimizations we could do that we don't. | |
1682 | In particular, we do not, in general, reorder instructions. | |
1683 | If you use gcc with optimization, it will reorder | |
1684 | instructions and generally do much more optimization then we | |
1685 | do here; repeating all that work in the assembler would only | |
1686 | benefit hand written assembly code, and does not seem worth | |
1687 | it. */ | |
1688 | ||
1689 | /* This is how a NOP is emitted. */ | |
1690 | #define emit_nop() \ | |
1691 | (mips_opts.mips16 \ | |
1692 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1693 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1694 | ||
1695 | /* The previous insn might require a delay slot, depending upon | |
1696 | the contents of the current insn. */ | |
1697 | if (! mips_opts.mips16 | |
9ce8a5dd | 1698 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1699 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1700 | && ! cop_interlocks) | |
1701 | || (! gpr_interlocks | |
1702 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1703 | { | |
1704 | /* A load from a coprocessor or from memory. All load | |
1705 | delays delay the use of general register rt for one | |
1706 | instruction on the r3000. The r6000 and r4000 use | |
1707 | interlocks. */ | |
beae10d5 | 1708 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1709 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1710 | if (mips_optimize == 0 | |
1711 | || insn_uses_reg (ip, | |
1712 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1713 | & OP_MASK_RT), | |
1714 | MIPS_GR_REG)) | |
1715 | ++nops; | |
1716 | } | |
1717 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1718 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1719 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1720 | && ! cop_interlocks) |
e7af610e | 1721 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1722 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1723 | { | |
1724 | /* A generic coprocessor delay. The previous instruction | |
1725 | modified a coprocessor general or control register. If | |
1726 | it modified a control register, we need to avoid any | |
1727 | coprocessor instruction (this is probably not always | |
1728 | required, but it sometimes is). If it modified a general | |
1729 | register, we avoid using that register. | |
1730 | ||
1731 | On the r6000 and r4000 loading a coprocessor register | |
1732 | from memory is interlocked, and does not require a delay. | |
1733 | ||
1734 | This case is not handled very well. There is no special | |
1735 | knowledge of CP0 handling, and the coprocessors other | |
1736 | than the floating point unit are not distinguished at | |
1737 | all. */ | |
1738 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1739 | Need to modify this to include knowledge about |
252b5132 RH |
1740 | user specified delays! */ |
1741 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1742 | { | |
1743 | if (mips_optimize == 0 | |
1744 | || insn_uses_reg (ip, | |
1745 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1746 | & OP_MASK_FT), | |
1747 | MIPS_FP_REG)) | |
1748 | ++nops; | |
1749 | } | |
1750 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1751 | { | |
1752 | if (mips_optimize == 0 | |
1753 | || insn_uses_reg (ip, | |
1754 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1755 | & OP_MASK_FS), | |
1756 | MIPS_FP_REG)) | |
1757 | ++nops; | |
1758 | } | |
1759 | else | |
1760 | { | |
1761 | /* We don't know exactly what the previous instruction | |
1762 | does. If the current instruction uses a coprocessor | |
1763 | register, we must insert a NOP. If previous | |
1764 | instruction may set the condition codes, and the | |
1765 | current instruction uses them, we must insert two | |
1766 | NOPS. */ | |
bdaaa2e1 | 1767 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1768 | if (mips_optimize == 0 |
1769 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1770 | && (pinfo & INSN_READ_COND_CODE))) | |
1771 | nops += 2; | |
1772 | else if (pinfo & INSN_COP) | |
1773 | ++nops; | |
1774 | } | |
1775 | } | |
1776 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1777 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1778 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1779 | && ! cop_interlocks) | |
1780 | { | |
1781 | /* The previous instruction sets the coprocessor condition | |
1782 | codes, but does not require a general coprocessor delay | |
1783 | (this means it is a floating point comparison | |
1784 | instruction). If this instruction uses the condition | |
1785 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1786 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1787 | if (mips_optimize == 0 |
1788 | || (pinfo & INSN_READ_COND_CODE)) | |
1789 | ++nops; | |
1790 | } | |
6b76fefe CM |
1791 | |
1792 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1793 | previous insn was an mfhi/mflo and the current insn | |
1794 | reads the register that the mfhi/mflo wrote to, then | |
1795 | insert two nops. */ | |
1796 | ||
1797 | else if (mips_7000_hilo_fix | |
1798 | && MF_HILO_INSN (prev_pinfo) | |
1799 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1800 | & OP_MASK_RD), |
1801 | MIPS_GR_REG)) | |
6b76fefe CM |
1802 | { |
1803 | nops += 2; | |
1804 | } | |
1805 | ||
1806 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1807 | 2nd previous insn was an mfhi/mflo and the current insn | |
1808 | reads the register that the mfhi/mflo wrote to, then | |
1809 | insert one nop. */ | |
1810 | ||
1811 | else if (mips_7000_hilo_fix | |
1812 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1813 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1814 | & OP_MASK_RD), | |
1815 | MIPS_GR_REG)) | |
bdaaa2e1 | 1816 | |
6b76fefe CM |
1817 | { |
1818 | nops += 1; | |
1819 | } | |
bdaaa2e1 | 1820 | |
252b5132 RH |
1821 | else if (prev_pinfo & INSN_READ_LO) |
1822 | { | |
1823 | /* The previous instruction reads the LO register; if the | |
1824 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1825 | insert two NOPS. Some newer processors have interlocks. |
1826 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1827 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1828 | though the tx39's divide insns still do require the |
1829 | delay. */ | |
252b5132 | 1830 | if (! (hilo_interlocks |
ec68c924 | 1831 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1832 | && (mips_optimize == 0 |
1833 | || (pinfo & INSN_WRITE_LO))) | |
1834 | nops += 2; | |
1835 | /* Most mips16 branch insns don't have a delay slot. | |
1836 | If a read from LO is immediately followed by a branch | |
1837 | to a write to LO we have a read followed by a write | |
1838 | less than 2 insns away. We assume the target of | |
1839 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1840 | between a read and an immediately following branch. */ |
252b5132 RH |
1841 | else if (mips_opts.mips16 |
1842 | && (mips_optimize == 0 | |
1843 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1844 | nops += 1; | |
1845 | } | |
1846 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1847 | { | |
1848 | /* The previous instruction reads the HI register; if the | |
1849 | current instruction writes to the HI register, we must | |
1850 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1851 | Also the note tx39's multiply above. */ |
252b5132 | 1852 | if (! (hilo_interlocks |
ec68c924 | 1853 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1854 | && (mips_optimize == 0 |
1855 | || (pinfo & INSN_WRITE_HI))) | |
1856 | nops += 2; | |
1857 | /* Most mips16 branch insns don't have a delay slot. | |
1858 | If a read from HI is immediately followed by a branch | |
1859 | to a write to HI we have a read followed by a write | |
1860 | less than 2 insns away. We assume the target of | |
1861 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1862 | between a read and an immediately following branch. */ |
252b5132 RH |
1863 | else if (mips_opts.mips16 |
1864 | && (mips_optimize == 0 | |
1865 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1866 | nops += 1; | |
1867 | } | |
1868 | ||
1869 | /* If the previous instruction was in a noreorder section, then | |
1870 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1871 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1872 | if (prev_insn_unreordered) |
1873 | nops = 0; | |
1874 | ||
1875 | /* There are two cases which require two intervening | |
1876 | instructions: 1) setting the condition codes using a move to | |
1877 | coprocessor instruction which requires a general coprocessor | |
1878 | delay and then reading the condition codes 2) reading the HI | |
1879 | or LO register and then writing to it (except on processors | |
1880 | which have interlocks). If we are not already emitting a NOP | |
1881 | instruction, we must check for these cases compared to the | |
1882 | instruction previous to the previous instruction. */ | |
1883 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1884 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1885 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1886 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1887 | && (pinfo & INSN_READ_COND_CODE) | |
1888 | && ! cop_interlocks) | |
1889 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1890 | && (pinfo & INSN_WRITE_LO) | |
1891 | && ! (hilo_interlocks | |
ec68c924 | 1892 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1893 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1894 | && (pinfo & INSN_WRITE_HI) | |
1895 | && ! (hilo_interlocks | |
ec68c924 | 1896 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1897 | prev_prev_nop = 1; |
1898 | else | |
1899 | prev_prev_nop = 0; | |
1900 | ||
1901 | if (prev_prev_insn_unreordered) | |
1902 | prev_prev_nop = 0; | |
1903 | ||
1904 | if (prev_prev_nop && nops == 0) | |
1905 | ++nops; | |
1906 | ||
1907 | /* If we are being given a nop instruction, don't bother with | |
1908 | one of the nops we would otherwise output. This will only | |
1909 | happen when a nop instruction is used with mips_optimize set | |
1910 | to 0. */ | |
1911 | if (nops > 0 | |
1912 | && ! mips_opts.noreorder | |
156c2f8b | 1913 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1914 | --nops; |
1915 | ||
1916 | /* Now emit the right number of NOP instructions. */ | |
1917 | if (nops > 0 && ! mips_opts.noreorder) | |
1918 | { | |
1919 | fragS *old_frag; | |
1920 | unsigned long old_frag_offset; | |
1921 | int i; | |
1922 | struct insn_label_list *l; | |
1923 | ||
1924 | old_frag = frag_now; | |
1925 | old_frag_offset = frag_now_fix (); | |
1926 | ||
1927 | for (i = 0; i < nops; i++) | |
1928 | emit_nop (); | |
1929 | ||
1930 | if (listing) | |
1931 | { | |
1932 | listing_prev_line (); | |
1933 | /* We may be at the start of a variant frag. In case we | |
1934 | are, make sure there is enough space for the frag | |
1935 | after the frags created by listing_prev_line. The | |
1936 | argument to frag_grow here must be at least as large | |
1937 | as the argument to all other calls to frag_grow in | |
1938 | this file. We don't have to worry about being in the | |
1939 | middle of a variant frag, because the variants insert | |
1940 | all needed nop instructions themselves. */ | |
1941 | frag_grow (40); | |
1942 | } | |
1943 | ||
1944 | for (l = insn_labels; l != NULL; l = l->next) | |
1945 | { | |
98aa84af AM |
1946 | valueT val; |
1947 | ||
252b5132 | 1948 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1949 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1950 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1951 | /* mips16 text labels are stored as odd. */ |
1952 | if (mips_opts.mips16) | |
98aa84af AM |
1953 | val += 1; |
1954 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
1955 | } |
1956 | ||
1957 | #ifndef NO_ECOFF_DEBUGGING | |
1958 | if (ECOFF_DEBUGGING) | |
1959 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1960 | #endif | |
1961 | } | |
1962 | else if (prev_nop_frag != NULL) | |
1963 | { | |
1964 | /* We have a frag holding nops we may be able to remove. If | |
1965 | we don't need any nops, we can decrease the size of | |
1966 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1967 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1968 | if (prev_nop_frag_since == 0) |
1969 | { | |
1970 | if (nops == 0) | |
1971 | { | |
1972 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1973 | --prev_nop_frag_holds; | |
1974 | } | |
1975 | else | |
1976 | prev_nop_frag_required += nops; | |
1977 | } | |
1978 | else | |
1979 | { | |
1980 | if (prev_prev_nop == 0) | |
1981 | { | |
1982 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1983 | --prev_nop_frag_holds; | |
1984 | } | |
1985 | else | |
1986 | ++prev_nop_frag_required; | |
1987 | } | |
1988 | ||
1989 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1990 | prev_nop_frag = NULL; | |
1991 | ||
1992 | ++prev_nop_frag_since; | |
1993 | ||
1994 | /* Sanity check: by the time we reach the second instruction | |
1995 | after prev_nop_frag, we should have used up all the nops | |
1996 | one way or another. */ | |
1997 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1998 | } | |
1999 | } | |
2000 | ||
f6688943 | 2001 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
2002 | { |
2003 | /* We need to set up a variant frag. */ | |
2004 | assert (mips_opts.mips16 && address_expr != NULL); | |
2005 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2006 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2007 | mips16_small, mips16_ext, |
2008 | (prev_pinfo | |
2009 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2010 | (*prev_insn_reloc_type |
252b5132 | 2011 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2012 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2013 | } |
2014 | else if (place != NULL) | |
2015 | f = place; | |
2016 | else if (mips_opts.mips16 | |
2017 | && ! ip->use_extend | |
f6688943 | 2018 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2019 | { |
2020 | /* Make sure there is enough room to swap this instruction with | |
2021 | a following jump instruction. */ | |
2022 | frag_grow (6); | |
2023 | f = frag_more (2); | |
2024 | } | |
2025 | else | |
2026 | { | |
2027 | if (mips_opts.mips16 | |
2028 | && mips_opts.noreorder | |
2029 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2030 | as_warn (_("extended instruction in delay slot")); | |
2031 | ||
2032 | f = frag_more (4); | |
2033 | } | |
2034 | ||
f6688943 TS |
2035 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2036 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2037 | { |
2038 | if (address_expr->X_op == O_constant) | |
2039 | { | |
4db1a35d | 2040 | valueT tmp; |
f6688943 TS |
2041 | |
2042 | switch (*reloc_type) | |
252b5132 RH |
2043 | { |
2044 | case BFD_RELOC_32: | |
2045 | ip->insn_opcode |= address_expr->X_add_number; | |
2046 | break; | |
2047 | ||
f6688943 TS |
2048 | case BFD_RELOC_MIPS_HIGHEST: |
2049 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2050 | tmp >>= 16; | |
2051 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2052 | break; | |
2053 | ||
2054 | case BFD_RELOC_MIPS_HIGHER: | |
2055 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2056 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2057 | break; | |
2058 | ||
2059 | case BFD_RELOC_HI16_S: | |
2060 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2061 | >> 16) & 0xffff; | |
2062 | break; | |
2063 | ||
2064 | case BFD_RELOC_HI16: | |
2065 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2066 | break; | |
2067 | ||
252b5132 RH |
2068 | case BFD_RELOC_LO16: |
2069 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
2070 | break; | |
2071 | ||
2072 | case BFD_RELOC_MIPS_JMP: | |
2073 | if ((address_expr->X_add_number & 3) != 0) | |
2074 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2075 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2076 | if (address_expr->X_add_number & ~0xfffffff |
2077 | || address_expr->X_add_number > 0x7fffffc) | |
2078 | as_bad (_("jump address range overflow (0x%lx)"), | |
2079 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2080 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2081 | break; | |
2082 | ||
2083 | case BFD_RELOC_MIPS16_JMP: | |
2084 | if ((address_expr->X_add_number & 3) != 0) | |
2085 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2086 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2087 | if (address_expr->X_add_number & ~0xfffffff |
2088 | || address_expr->X_add_number > 0x7fffffc) | |
2089 | as_bad (_("jump address range overflow (0x%lx)"), | |
2090 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2091 | ip->insn_opcode |= |
2092 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2093 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2094 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2095 | break; | |
2096 | ||
cb56d3d3 | 2097 | case BFD_RELOC_16_PCREL: |
233b8738 | 2098 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
2099 | break; |
2100 | ||
252b5132 RH |
2101 | case BFD_RELOC_16_PCREL_S2: |
2102 | goto need_reloc; | |
2103 | ||
2104 | default: | |
2105 | internalError (); | |
2106 | } | |
2107 | } | |
2108 | else | |
2109 | { | |
2110 | need_reloc: | |
f6688943 | 2111 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2112 | if (place == NULL) |
2113 | { | |
f6688943 TS |
2114 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2115 | address_expr, | |
2116 | (*reloc_type == BFD_RELOC_16_PCREL | |
2117 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
2118 | reloc_type[0]); | |
2119 | ||
b6ff326e | 2120 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2121 | 4 octets for 64bit assembly. */ |
2122 | if (HAVE_64BIT_GPRS && | |
2123 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
2124 | || *reloc_type == BFD_RELOC_32 |
2125 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2126 | || *reloc_type == BFD_RELOC_HI16_S | |
2127 | || *reloc_type == BFD_RELOC_LO16 | |
2128 | || *reloc_type == BFD_RELOC_GPREL16 | |
2129 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2130 | || *reloc_type == BFD_RELOC_GPREL32 | |
2131 | || *reloc_type == BFD_RELOC_64 | |
2132 | || *reloc_type == BFD_RELOC_CTOR | |
2133 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2134 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2135 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2136 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2137 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2138 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2139 | fixp[0]->fx_no_overflow = 1; |
2140 | ||
252b5132 RH |
2141 | if (unmatched_hi) |
2142 | { | |
2143 | struct mips_hi_fixup *hi_fixup; | |
2144 | ||
f6688943 | 2145 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2146 | hi_fixup = ((struct mips_hi_fixup *) |
2147 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2148 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2149 | hi_fixup->seg = now_seg; |
2150 | hi_fixup->next = mips_hi_fixup_list; | |
2151 | mips_hi_fixup_list = hi_fixup; | |
2152 | } | |
f6688943 TS |
2153 | |
2154 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2155 | { | |
2156 | /* FIXME: This symbol can be one of | |
2157 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2158 | address_expr->X_op = O_absent; | |
2159 | address_expr->X_add_symbol = 0; | |
2160 | address_expr->X_add_number = 0; | |
2161 | ||
2162 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2163 | 4, address_expr, false, | |
2164 | reloc_type[1]); | |
2165 | ||
b6ff326e | 2166 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2167 | 4 octets for 64bit assembly. */ |
2168 | if (HAVE_64BIT_GPRS && | |
2169 | (*reloc_type == BFD_RELOC_16 | |
2170 | || *reloc_type == BFD_RELOC_32 | |
2171 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2172 | || *reloc_type == BFD_RELOC_HI16_S | |
2173 | || *reloc_type == BFD_RELOC_LO16 | |
2174 | || *reloc_type == BFD_RELOC_GPREL16 | |
2175 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2176 | || *reloc_type == BFD_RELOC_GPREL32 | |
2177 | || *reloc_type == BFD_RELOC_64 | |
2178 | || *reloc_type == BFD_RELOC_CTOR | |
2179 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2180 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2181 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2182 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2183 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2184 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2185 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
2186 | |
2187 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2188 | { | |
2189 | address_expr->X_op = O_absent; | |
2190 | address_expr->X_add_symbol = 0; | |
2191 | address_expr->X_add_number = 0; | |
2192 | ||
2193 | fixp[2] = fix_new_exp (frag_now, | |
2194 | f - frag_now->fr_literal, 4, | |
2195 | address_expr, false, | |
2196 | reloc_type[2]); | |
2197 | ||
b6ff326e | 2198 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2199 | 4 octets for 64bit assembly. */ |
2200 | if (HAVE_64BIT_GPRS && | |
2201 | (*reloc_type == BFD_RELOC_16 | |
2202 | || *reloc_type == BFD_RELOC_32 | |
2203 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2204 | || *reloc_type == BFD_RELOC_HI16_S | |
2205 | || *reloc_type == BFD_RELOC_LO16 | |
2206 | || *reloc_type == BFD_RELOC_GPREL16 | |
2207 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2208 | || *reloc_type == BFD_RELOC_GPREL32 | |
2209 | || *reloc_type == BFD_RELOC_64 | |
2210 | || *reloc_type == BFD_RELOC_CTOR | |
2211 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2212 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2213 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2214 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2215 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2216 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2217 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2218 | } |
2219 | } | |
252b5132 RH |
2220 | } |
2221 | } | |
2222 | } | |
2223 | ||
2224 | if (! mips_opts.mips16) | |
2225 | md_number_to_chars (f, ip->insn_opcode, 4); | |
f6688943 | 2226 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2227 | { |
2228 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2229 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | if (ip->use_extend) | |
2234 | { | |
2235 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2236 | f += 2; | |
2237 | } | |
2238 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2239 | } | |
2240 | ||
2241 | /* Update the register mask information. */ | |
2242 | if (! mips_opts.mips16) | |
2243 | { | |
2244 | if (pinfo & INSN_WRITE_GPR_D) | |
2245 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2246 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2247 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2248 | if (pinfo & INSN_READ_GPR_S) | |
2249 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2250 | if (pinfo & INSN_WRITE_GPR_31) | |
2251 | mips_gprmask |= 1 << 31; | |
2252 | if (pinfo & INSN_WRITE_FPR_D) | |
2253 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2254 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2255 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2256 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2257 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2258 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2259 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2260 | if (pinfo & INSN_COP) | |
2261 | { | |
bdaaa2e1 KH |
2262 | /* We don't keep enough information to sort these cases out. |
2263 | The itbl support does keep this information however, although | |
2264 | we currently don't support itbl fprmats as part of the cop | |
2265 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2266 | } |
2267 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2268 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2269 | } |
2270 | else | |
2271 | { | |
2272 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2273 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2274 | & MIPS16OP_MASK_RX); | |
2275 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2276 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2277 | & MIPS16OP_MASK_RY); | |
2278 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2279 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2280 | & MIPS16OP_MASK_RZ); | |
2281 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2282 | mips_gprmask |= 1 << TREG; | |
2283 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2284 | mips_gprmask |= 1 << SP; | |
2285 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2286 | mips_gprmask |= 1 << RA; | |
2287 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2288 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2289 | if (pinfo & MIPS16_INSN_READ_Z) | |
2290 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2291 | & MIPS16OP_MASK_MOVE32Z); | |
2292 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2293 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2294 | & MIPS16OP_MASK_REGR32); | |
2295 | } | |
2296 | ||
2297 | if (place == NULL && ! mips_opts.noreorder) | |
2298 | { | |
2299 | /* Filling the branch delay slot is more complex. We try to | |
2300 | switch the branch with the previous instruction, which we can | |
2301 | do if the previous instruction does not set up a condition | |
2302 | that the branch tests and if the branch is not itself the | |
2303 | target of any branch. */ | |
2304 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2305 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2306 | { | |
2307 | if (mips_optimize < 2 | |
2308 | /* If we have seen .set volatile or .set nomove, don't | |
2309 | optimize. */ | |
2310 | || mips_opts.nomove != 0 | |
2311 | /* If we had to emit any NOP instructions, then we | |
2312 | already know we can not swap. */ | |
2313 | || nops != 0 | |
2314 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2315 | swap. */ |
252b5132 RH |
2316 | || ! prev_insn_valid |
2317 | /* If the previous insn is already in a branch delay | |
2318 | slot, then we can not swap. */ | |
2319 | || prev_insn_is_delay_slot | |
2320 | /* If the previous previous insn was in a .set | |
2321 | noreorder, we can't swap. Actually, the MIPS | |
2322 | assembler will swap in this situation. However, gcc | |
2323 | configured -with-gnu-as will generate code like | |
2324 | .set noreorder | |
2325 | lw $4,XXX | |
2326 | .set reorder | |
2327 | INSN | |
2328 | bne $4,$0,foo | |
2329 | in which we can not swap the bne and INSN. If gcc is | |
2330 | not configured -with-gnu-as, it does not output the | |
2331 | .set pseudo-ops. We don't have to check | |
2332 | prev_insn_unreordered, because prev_insn_valid will | |
2333 | be 0 in that case. We don't want to use | |
2334 | prev_prev_insn_valid, because we do want to be able | |
2335 | to swap at the start of a function. */ | |
2336 | || prev_prev_insn_unreordered | |
2337 | /* If the branch is itself the target of a branch, we | |
2338 | can not swap. We cheat on this; all we check for is | |
2339 | whether there is a label on this instruction. If | |
2340 | there are any branches to anything other than a | |
2341 | label, users must use .set noreorder. */ | |
2342 | || insn_labels != NULL | |
2343 | /* If the previous instruction is in a variant frag, we | |
2344 | can not do the swap. This does not apply to the | |
2345 | mips16, which uses variant frags for different | |
2346 | purposes. */ | |
2347 | || (! mips_opts.mips16 | |
2348 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2349 | /* If the branch reads the condition codes, we don't | |
2350 | even try to swap, because in the sequence | |
2351 | ctc1 $X,$31 | |
2352 | INSN | |
2353 | INSN | |
2354 | bc1t LABEL | |
2355 | we can not swap, and I don't feel like handling that | |
2356 | case. */ | |
2357 | || (! mips_opts.mips16 | |
9ce8a5dd | 2358 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2359 | && (pinfo & INSN_READ_COND_CODE)) |
2360 | /* We can not swap with an instruction that requires a | |
2361 | delay slot, becase the target of the branch might | |
2362 | interfere with that instruction. */ | |
2363 | || (! mips_opts.mips16 | |
9ce8a5dd | 2364 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2365 | && (prev_pinfo |
bdaaa2e1 | 2366 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2367 | & (INSN_LOAD_COPROC_DELAY |
2368 | | INSN_COPROC_MOVE_DELAY | |
2369 | | INSN_WRITE_COND_CODE))) | |
2370 | || (! (hilo_interlocks | |
ec68c924 | 2371 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2372 | && (prev_pinfo |
2373 | & (INSN_READ_LO | |
2374 | | INSN_READ_HI))) | |
2375 | || (! mips_opts.mips16 | |
2376 | && ! gpr_interlocks | |
2377 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2378 | || (! mips_opts.mips16 | |
e7af610e | 2379 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2380 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2381 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2382 | /* We can not swap with a branch instruction. */ | |
2383 | || (prev_pinfo | |
2384 | & (INSN_UNCOND_BRANCH_DELAY | |
2385 | | INSN_COND_BRANCH_DELAY | |
2386 | | INSN_COND_BRANCH_LIKELY)) | |
2387 | /* We do not swap with a trap instruction, since it | |
2388 | complicates trap handlers to have the trap | |
2389 | instruction be in a delay slot. */ | |
2390 | || (prev_pinfo & INSN_TRAP) | |
2391 | /* If the branch reads a register that the previous | |
2392 | instruction sets, we can not swap. */ | |
2393 | || (! mips_opts.mips16 | |
2394 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2395 | && insn_uses_reg (ip, | |
2396 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2397 | & OP_MASK_RT), | |
2398 | MIPS_GR_REG)) | |
2399 | || (! mips_opts.mips16 | |
2400 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2401 | && insn_uses_reg (ip, | |
2402 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2403 | & OP_MASK_RD), | |
2404 | MIPS_GR_REG)) | |
2405 | || (mips_opts.mips16 | |
2406 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2407 | && insn_uses_reg (ip, | |
2408 | ((prev_insn.insn_opcode | |
2409 | >> MIPS16OP_SH_RX) | |
2410 | & MIPS16OP_MASK_RX), | |
2411 | MIPS16_REG)) | |
2412 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2413 | && insn_uses_reg (ip, | |
2414 | ((prev_insn.insn_opcode | |
2415 | >> MIPS16OP_SH_RY) | |
2416 | & MIPS16OP_MASK_RY), | |
2417 | MIPS16_REG)) | |
2418 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2419 | && insn_uses_reg (ip, | |
2420 | ((prev_insn.insn_opcode | |
2421 | >> MIPS16OP_SH_RZ) | |
2422 | & MIPS16OP_MASK_RZ), | |
2423 | MIPS16_REG)) | |
2424 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2425 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2426 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2427 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2428 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2429 | && insn_uses_reg (ip, | |
2430 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2431 | insn_opcode), | |
2432 | MIPS_GR_REG)))) | |
2433 | /* If the branch writes a register that the previous | |
2434 | instruction sets, we can not swap (we know that | |
2435 | branches write only to RD or to $31). */ | |
2436 | || (! mips_opts.mips16 | |
2437 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2438 | && (((pinfo & INSN_WRITE_GPR_D) | |
2439 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2440 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2441 | || ((pinfo & INSN_WRITE_GPR_31) | |
2442 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2443 | & OP_MASK_RT) | |
2444 | == 31)))) | |
2445 | || (! mips_opts.mips16 | |
2446 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2447 | && (((pinfo & INSN_WRITE_GPR_D) | |
2448 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2449 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2450 | || ((pinfo & INSN_WRITE_GPR_31) | |
2451 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2452 | & OP_MASK_RD) | |
2453 | == 31)))) | |
2454 | || (mips_opts.mips16 | |
2455 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2456 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2457 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2458 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2459 | == RA)))) | |
2460 | /* If the branch writes a register that the previous | |
2461 | instruction reads, we can not swap (we know that | |
2462 | branches only write to RD or to $31). */ | |
2463 | || (! mips_opts.mips16 | |
2464 | && (pinfo & INSN_WRITE_GPR_D) | |
2465 | && insn_uses_reg (&prev_insn, | |
2466 | ((ip->insn_opcode >> OP_SH_RD) | |
2467 | & OP_MASK_RD), | |
2468 | MIPS_GR_REG)) | |
2469 | || (! mips_opts.mips16 | |
2470 | && (pinfo & INSN_WRITE_GPR_31) | |
2471 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2472 | || (mips_opts.mips16 | |
2473 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2474 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2475 | /* If we are generating embedded PIC code, the branch | |
2476 | might be expanded into a sequence which uses $at, so | |
2477 | we can't swap with an instruction which reads it. */ | |
2478 | || (mips_pic == EMBEDDED_PIC | |
2479 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2480 | /* If the previous previous instruction has a load | |
2481 | delay, and sets a register that the branch reads, we | |
2482 | can not swap. */ | |
2483 | || (! mips_opts.mips16 | |
9ce8a5dd | 2484 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2485 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2486 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2487 | || (! gpr_interlocks | |
2488 | && (prev_prev_insn.insn_mo->pinfo | |
2489 | & INSN_LOAD_MEMORY_DELAY))) | |
2490 | && insn_uses_reg (ip, | |
2491 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2492 | & OP_MASK_RT), | |
2493 | MIPS_GR_REG)) | |
2494 | /* If one instruction sets a condition code and the | |
2495 | other one uses a condition code, we can not swap. */ | |
2496 | || ((pinfo & INSN_READ_COND_CODE) | |
2497 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2498 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2499 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2500 | /* If the previous instruction uses the PC, we can not | |
2501 | swap. */ | |
2502 | || (mips_opts.mips16 | |
2503 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2504 | /* If the previous instruction was extended, we can not | |
2505 | swap. */ | |
2506 | || (mips_opts.mips16 && prev_insn_extended) | |
2507 | /* If the previous instruction had a fixup in mips16 | |
2508 | mode, we can not swap. This normally means that the | |
2509 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2510 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2511 | /* If the previous instruction is a sync, sync.l, or |
2512 | sync.p, we can not swap. */ | |
f173e82e | 2513 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2514 | { |
2515 | /* We could do even better for unconditional branches to | |
2516 | portions of this object file; we could pick up the | |
2517 | instruction at the destination, put it in the delay | |
2518 | slot, and bump the destination address. */ | |
2519 | emit_nop (); | |
2520 | /* Update the previous insn information. */ | |
2521 | prev_prev_insn = *ip; | |
2522 | prev_insn.insn_mo = &dummy_opcode; | |
2523 | } | |
2524 | else | |
2525 | { | |
2526 | /* It looks like we can actually do the swap. */ | |
2527 | if (! mips_opts.mips16) | |
2528 | { | |
2529 | char *prev_f; | |
2530 | char temp[4]; | |
2531 | ||
2532 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2533 | memcpy (temp, prev_f, 4); | |
2534 | memcpy (prev_f, f, 4); | |
2535 | memcpy (f, temp, 4); | |
f6688943 TS |
2536 | if (prev_insn_fixp[0]) |
2537 | { | |
2538 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2539 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2540 | } | |
2541 | if (prev_insn_fixp[1]) | |
2542 | { | |
2543 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2544 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2545 | } | |
2546 | if (prev_insn_fixp[2]) | |
252b5132 | 2547 | { |
f6688943 TS |
2548 | prev_insn_fixp[2]->fx_frag = frag_now; |
2549 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2550 | } |
f6688943 | 2551 | if (fixp[0]) |
252b5132 | 2552 | { |
f6688943 TS |
2553 | fixp[0]->fx_frag = prev_insn_frag; |
2554 | fixp[0]->fx_where = prev_insn_where; | |
2555 | } | |
2556 | if (fixp[1]) | |
2557 | { | |
2558 | fixp[1]->fx_frag = prev_insn_frag; | |
2559 | fixp[1]->fx_where = prev_insn_where; | |
2560 | } | |
2561 | if (fixp[2]) | |
2562 | { | |
2563 | fixp[2]->fx_frag = prev_insn_frag; | |
2564 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2565 | } |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | char *prev_f; | |
2570 | char temp[2]; | |
2571 | ||
f6688943 TS |
2572 | assert (prev_insn_fixp[0] == NULL); |
2573 | assert (prev_insn_fixp[1] == NULL); | |
2574 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2575 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2576 | memcpy (temp, prev_f, 2); | |
2577 | memcpy (prev_f, f, 2); | |
f6688943 | 2578 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2579 | { |
f6688943 | 2580 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2581 | memcpy (f, temp, 2); |
2582 | } | |
2583 | else | |
2584 | { | |
2585 | memcpy (f, f + 2, 2); | |
2586 | memcpy (f + 2, temp, 2); | |
2587 | } | |
f6688943 TS |
2588 | if (fixp[0]) |
2589 | { | |
2590 | fixp[0]->fx_frag = prev_insn_frag; | |
2591 | fixp[0]->fx_where = prev_insn_where; | |
2592 | } | |
2593 | if (fixp[1]) | |
2594 | { | |
2595 | fixp[1]->fx_frag = prev_insn_frag; | |
2596 | fixp[1]->fx_where = prev_insn_where; | |
2597 | } | |
2598 | if (fixp[2]) | |
252b5132 | 2599 | { |
f6688943 TS |
2600 | fixp[2]->fx_frag = prev_insn_frag; |
2601 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2602 | } |
2603 | } | |
2604 | ||
2605 | /* Update the previous insn information; leave prev_insn | |
2606 | unchanged. */ | |
2607 | prev_prev_insn = *ip; | |
2608 | } | |
2609 | prev_insn_is_delay_slot = 1; | |
2610 | ||
2611 | /* If that was an unconditional branch, forget the previous | |
2612 | insn information. */ | |
2613 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2614 | { | |
2615 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2616 | prev_insn.insn_mo = &dummy_opcode; | |
2617 | } | |
2618 | ||
f6688943 TS |
2619 | prev_insn_fixp[0] = NULL; |
2620 | prev_insn_fixp[1] = NULL; | |
2621 | prev_insn_fixp[2] = NULL; | |
2622 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2623 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2624 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2625 | prev_insn_extended = 0; |
2626 | } | |
2627 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2628 | { | |
2629 | /* We don't yet optimize a branch likely. What we should do | |
2630 | is look at the target, copy the instruction found there | |
2631 | into the delay slot, and increment the branch to jump to | |
2632 | the next instruction. */ | |
2633 | emit_nop (); | |
2634 | /* Update the previous insn information. */ | |
2635 | prev_prev_insn = *ip; | |
2636 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2637 | prev_insn_fixp[0] = NULL; |
2638 | prev_insn_fixp[1] = NULL; | |
2639 | prev_insn_fixp[2] = NULL; | |
2640 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2641 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2642 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2643 | prev_insn_extended = 0; |
2644 | } | |
2645 | else | |
2646 | { | |
2647 | /* Update the previous insn information. */ | |
2648 | if (nops > 0) | |
2649 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2650 | else | |
2651 | prev_prev_insn = prev_insn; | |
2652 | prev_insn = *ip; | |
2653 | ||
2654 | /* Any time we see a branch, we always fill the delay slot | |
2655 | immediately; since this insn is not a branch, we know it | |
2656 | is not in a delay slot. */ | |
2657 | prev_insn_is_delay_slot = 0; | |
2658 | ||
f6688943 TS |
2659 | prev_insn_fixp[0] = fixp[0]; |
2660 | prev_insn_fixp[1] = fixp[1]; | |
2661 | prev_insn_fixp[2] = fixp[2]; | |
2662 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2663 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2664 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2665 | if (mips_opts.mips16) |
2666 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2667 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2668 | } |
2669 | ||
2670 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2671 | prev_insn_unreordered = 0; | |
2672 | prev_insn_frag = frag_now; | |
2673 | prev_insn_where = f - frag_now->fr_literal; | |
2674 | prev_insn_valid = 1; | |
2675 | } | |
2676 | else if (place == NULL) | |
2677 | { | |
2678 | /* We need to record a bit of information even when we are not | |
2679 | reordering, in order to determine the base address for mips16 | |
2680 | PC relative relocs. */ | |
2681 | prev_prev_insn = prev_insn; | |
2682 | prev_insn = *ip; | |
f6688943 TS |
2683 | prev_insn_reloc_type[0] = reloc_type[0]; |
2684 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2685 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2686 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2687 | prev_insn_unreordered = 1; | |
2688 | } | |
2689 | ||
2690 | /* We just output an insn, so the next one doesn't have a label. */ | |
2691 | mips_clear_insn_labels (); | |
2692 | ||
2693 | /* We must ensure that a fixup associated with an unmatched %hi | |
2694 | reloc does not become a variant frag. Otherwise, the | |
2695 | rearrangement of %hi relocs in frob_file may confuse | |
2696 | tc_gen_reloc. */ | |
2697 | if (unmatched_hi) | |
2698 | { | |
2699 | frag_wane (frag_now); | |
2700 | frag_new (0); | |
2701 | } | |
2702 | } | |
2703 | ||
2704 | /* This function forgets that there was any previous instruction or | |
2705 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2706 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2707 | |
2708 | static void | |
2709 | mips_no_prev_insn (preserve) | |
2710 | int preserve; | |
2711 | { | |
2712 | if (! preserve) | |
2713 | { | |
2714 | prev_insn.insn_mo = &dummy_opcode; | |
2715 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2716 | prev_nop_frag = NULL; | |
2717 | prev_nop_frag_holds = 0; | |
2718 | prev_nop_frag_required = 0; | |
2719 | prev_nop_frag_since = 0; | |
2720 | } | |
2721 | prev_insn_valid = 0; | |
2722 | prev_insn_is_delay_slot = 0; | |
2723 | prev_insn_unreordered = 0; | |
2724 | prev_insn_extended = 0; | |
f6688943 TS |
2725 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2726 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2727 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2728 | prev_prev_insn_unreordered = 0; |
2729 | mips_clear_insn_labels (); | |
2730 | } | |
2731 | ||
2732 | /* This function must be called whenever we turn on noreorder or emit | |
2733 | something other than instructions. It inserts any NOPS which might | |
2734 | be needed by the previous instruction, and clears the information | |
2735 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2736 | instructions are to follow. */ |
252b5132 RH |
2737 | |
2738 | static void | |
2739 | mips_emit_delays (insns) | |
2740 | boolean insns; | |
2741 | { | |
2742 | if (! mips_opts.noreorder) | |
2743 | { | |
2744 | int nops; | |
2745 | ||
2746 | nops = 0; | |
2747 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2748 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2749 | && (! cop_interlocks |
2750 | && (prev_insn.insn_mo->pinfo | |
2751 | & (INSN_LOAD_COPROC_DELAY | |
2752 | | INSN_COPROC_MOVE_DELAY | |
2753 | | INSN_WRITE_COND_CODE)))) | |
2754 | || (! hilo_interlocks | |
2755 | && (prev_insn.insn_mo->pinfo | |
2756 | & (INSN_READ_LO | |
2757 | | INSN_READ_HI))) | |
2758 | || (! mips_opts.mips16 | |
2759 | && ! gpr_interlocks | |
bdaaa2e1 | 2760 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2761 | & INSN_LOAD_MEMORY_DELAY)) |
2762 | || (! mips_opts.mips16 | |
e7af610e | 2763 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2764 | && (prev_insn.insn_mo->pinfo |
2765 | & INSN_COPROC_MEMORY_DELAY))) | |
2766 | { | |
beae10d5 | 2767 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2768 | ++nops; |
2769 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2770 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2771 | && (! cop_interlocks |
2772 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2773 | || (! hilo_interlocks | |
2774 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2775 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2776 | ++nops; | |
2777 | ||
2778 | if (prev_insn_unreordered) | |
2779 | nops = 0; | |
2780 | } | |
2781 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2782 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2783 | && (! cop_interlocks |
2784 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2785 | || (! hilo_interlocks | |
2786 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2787 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2788 | { | |
beae10d5 | 2789 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2790 | if (! prev_prev_insn_unreordered) |
2791 | ++nops; | |
2792 | } | |
2793 | ||
2794 | if (nops > 0) | |
2795 | { | |
2796 | struct insn_label_list *l; | |
2797 | ||
2798 | if (insns) | |
2799 | { | |
2800 | /* Record the frag which holds the nop instructions, so | |
2801 | that we can remove them if we don't need them. */ | |
2802 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2803 | prev_nop_frag = frag_now; | |
2804 | prev_nop_frag_holds = nops; | |
2805 | prev_nop_frag_required = 0; | |
2806 | prev_nop_frag_since = 0; | |
2807 | } | |
2808 | ||
2809 | for (; nops > 0; --nops) | |
2810 | emit_nop (); | |
2811 | ||
2812 | if (insns) | |
2813 | { | |
2814 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2815 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2816 | frag_wane (frag_now); |
2817 | frag_new (0); | |
2818 | } | |
2819 | ||
2820 | for (l = insn_labels; l != NULL; l = l->next) | |
2821 | { | |
98aa84af AM |
2822 | valueT val; |
2823 | ||
252b5132 | 2824 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2825 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2826 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2827 | /* mips16 text labels are stored as odd. */ |
2828 | if (mips_opts.mips16) | |
98aa84af AM |
2829 | val += 1; |
2830 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
2831 | } |
2832 | } | |
2833 | } | |
2834 | ||
2835 | /* Mark instruction labels in mips16 mode. */ | |
2836 | if (mips_opts.mips16 && insns) | |
2837 | mips16_mark_labels (); | |
2838 | ||
2839 | mips_no_prev_insn (insns); | |
2840 | } | |
2841 | ||
2842 | /* Build an instruction created by a macro expansion. This is passed | |
2843 | a pointer to the count of instructions created so far, an | |
2844 | expression, the name of the instruction to build, an operand format | |
2845 | string, and corresponding arguments. */ | |
2846 | ||
2847 | #ifdef USE_STDARG | |
2848 | static void | |
2849 | macro_build (char *place, | |
2850 | int *counter, | |
2851 | expressionS * ep, | |
2852 | const char *name, | |
2853 | const char *fmt, | |
2854 | ...) | |
2855 | #else | |
2856 | static void | |
2857 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2858 | char *place; | |
2859 | int *counter; | |
2860 | expressionS *ep; | |
2861 | const char *name; | |
2862 | const char *fmt; | |
2863 | va_dcl | |
2864 | #endif | |
2865 | { | |
2866 | struct mips_cl_insn insn; | |
f6688943 | 2867 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2868 | va_list args; |
252b5132 RH |
2869 | |
2870 | #ifdef USE_STDARG | |
2871 | va_start (args, fmt); | |
2872 | #else | |
2873 | va_start (args); | |
2874 | #endif | |
2875 | ||
2876 | /* | |
2877 | * If the macro is about to expand into a second instruction, | |
2878 | * print a warning if needed. We need to pass ip as a parameter | |
2879 | * to generate a better warning message here... | |
2880 | */ | |
2881 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2882 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2883 | ||
80cc45a5 EC |
2884 | /* |
2885 | * If the macro is about to expand into a second instruction, | |
2886 | * and it is in a delay slot, print a warning. | |
2887 | */ | |
2888 | if (place == NULL | |
2889 | && *counter == 1 | |
2890 | && mips_opts.noreorder | |
2891 | && (prev_prev_insn.insn_mo->pinfo | |
2892 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2893 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2894 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2895 | ||
252b5132 RH |
2896 | if (place == NULL) |
2897 | *counter += 1; /* bump instruction counter */ | |
2898 | ||
2899 | if (mips_opts.mips16) | |
2900 | { | |
2901 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2902 | va_end (args); | |
2903 | return; | |
2904 | } | |
2905 | ||
f6688943 TS |
2906 | r[0] = BFD_RELOC_UNUSED; |
2907 | r[1] = BFD_RELOC_UNUSED; | |
2908 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2909 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2910 | assert (insn.insn_mo); | |
2911 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2912 | ||
2913 | /* Search until we get a match for NAME. */ | |
2914 | while (1) | |
2915 | { | |
98d3f06f | 2916 | /* It is assumed here that macros will never generate |
af55c2e6 | 2917 | MIPS-3D instructions. */ |
252b5132 RH |
2918 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2919 | && insn.insn_mo->pinfo != INSN_MACRO | |
af55c2e6 | 2920 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2921 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2922 | break; |
2923 | ||
2924 | ++insn.insn_mo; | |
2925 | assert (insn.insn_mo->name); | |
2926 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2927 | } | |
2928 | ||
2929 | insn.insn_opcode = insn.insn_mo->match; | |
2930 | for (;;) | |
2931 | { | |
2932 | switch (*fmt++) | |
2933 | { | |
2934 | case '\0': | |
2935 | break; | |
2936 | ||
2937 | case ',': | |
2938 | case '(': | |
2939 | case ')': | |
2940 | continue; | |
2941 | ||
2942 | case 't': | |
2943 | case 'w': | |
2944 | case 'E': | |
38487616 | 2945 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2946 | continue; |
2947 | ||
2948 | case 'c': | |
38487616 TS |
2949 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2950 | continue; | |
2951 | ||
252b5132 RH |
2952 | case 'T': |
2953 | case 'W': | |
38487616 | 2954 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2955 | continue; |
2956 | ||
2957 | case 'd': | |
2958 | case 'G': | |
38487616 | 2959 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2960 | continue; |
2961 | ||
4372b673 NC |
2962 | case 'U': |
2963 | { | |
2964 | int tmp = va_arg (args, int); | |
2965 | ||
38487616 TS |
2966 | insn.insn_opcode |= tmp << OP_SH_RT; |
2967 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2968 | continue; |
4372b673 NC |
2969 | } |
2970 | ||
252b5132 RH |
2971 | case 'V': |
2972 | case 'S': | |
38487616 | 2973 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2974 | continue; |
2975 | ||
2976 | case 'z': | |
2977 | continue; | |
2978 | ||
2979 | case '<': | |
38487616 | 2980 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2981 | continue; |
2982 | ||
2983 | case 'D': | |
38487616 | 2984 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2985 | continue; |
2986 | ||
2987 | case 'B': | |
38487616 | 2988 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2989 | continue; |
2990 | ||
4372b673 | 2991 | case 'J': |
38487616 | 2992 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2993 | continue; |
2994 | ||
252b5132 | 2995 | case 'q': |
38487616 | 2996 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2997 | continue; |
2998 | ||
2999 | case 'b': | |
3000 | case 's': | |
3001 | case 'r': | |
3002 | case 'v': | |
38487616 | 3003 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3004 | continue; |
3005 | ||
3006 | case 'i': | |
3007 | case 'j': | |
3008 | case 'o': | |
f6688943 | 3009 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3010 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3011 | || *r == BFD_RELOC_MIPS_LITERAL |
3012 | || *r == BFD_RELOC_MIPS_HIGHER | |
3013 | || *r == BFD_RELOC_HI16_S | |
3014 | || *r == BFD_RELOC_LO16 | |
3015 | || *r == BFD_RELOC_MIPS_GOT16 | |
3016 | || *r == BFD_RELOC_MIPS_CALL16 | |
3017 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
3018 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3019 | || (ep->X_op == O_subtract |
f6688943 | 3020 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3021 | continue; |
3022 | ||
3023 | case 'u': | |
f6688943 | 3024 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3025 | assert (ep != NULL |
3026 | && (ep->X_op == O_constant | |
3027 | || (ep->X_op == O_symbol | |
f6688943 TS |
3028 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3029 | || *r == BFD_RELOC_HI16_S | |
3030 | || *r == BFD_RELOC_HI16 | |
3031 | || *r == BFD_RELOC_GPREL16 | |
3032 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3033 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3034 | || (ep->X_op == O_subtract |
f6688943 | 3035 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3036 | continue; |
3037 | ||
3038 | case 'p': | |
3039 | assert (ep != NULL); | |
3040 | /* | |
3041 | * This allows macro() to pass an immediate expression for | |
3042 | * creating short branches without creating a symbol. | |
3043 | * Note that the expression still might come from the assembly | |
3044 | * input, in which case the value is not checked for range nor | |
3045 | * is a relocation entry generated (yuck). | |
3046 | */ | |
3047 | if (ep->X_op == O_constant) | |
3048 | { | |
3049 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3050 | ep = NULL; | |
3051 | } | |
3052 | else | |
cb56d3d3 | 3053 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 3054 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 3055 | else |
f6688943 | 3056 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
3057 | continue; |
3058 | ||
3059 | case 'a': | |
3060 | assert (ep != NULL); | |
f6688943 | 3061 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3062 | continue; |
3063 | ||
3064 | case 'C': | |
3065 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3066 | continue; | |
3067 | ||
3068 | default: | |
3069 | internalError (); | |
3070 | } | |
3071 | break; | |
3072 | } | |
3073 | va_end (args); | |
f6688943 | 3074 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3075 | |
3076 | append_insn (place, &insn, ep, r, false); | |
3077 | } | |
3078 | ||
3079 | static void | |
3080 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3081 | char *place; | |
43841e91 | 3082 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3083 | expressionS *ep; |
3084 | const char *name; | |
3085 | const char *fmt; | |
3086 | va_list args; | |
3087 | { | |
3088 | struct mips_cl_insn insn; | |
f6688943 TS |
3089 | bfd_reloc_code_real_type r[3] |
3090 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3091 | |
252b5132 RH |
3092 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3093 | assert (insn.insn_mo); | |
3094 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3095 | ||
3096 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3097 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3098 | { | |
3099 | ++insn.insn_mo; | |
3100 | assert (insn.insn_mo->name); | |
3101 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3102 | } | |
3103 | ||
3104 | insn.insn_opcode = insn.insn_mo->match; | |
3105 | insn.use_extend = false; | |
3106 | ||
3107 | for (;;) | |
3108 | { | |
3109 | int c; | |
3110 | ||
3111 | c = *fmt++; | |
3112 | switch (c) | |
3113 | { | |
3114 | case '\0': | |
3115 | break; | |
3116 | ||
3117 | case ',': | |
3118 | case '(': | |
3119 | case ')': | |
3120 | continue; | |
3121 | ||
3122 | case 'y': | |
3123 | case 'w': | |
3124 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3125 | continue; | |
3126 | ||
3127 | case 'x': | |
3128 | case 'v': | |
3129 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3130 | continue; | |
3131 | ||
3132 | case 'z': | |
3133 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3134 | continue; | |
3135 | ||
3136 | case 'Z': | |
3137 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3138 | continue; | |
3139 | ||
3140 | case '0': | |
3141 | case 'S': | |
3142 | case 'P': | |
3143 | case 'R': | |
3144 | continue; | |
3145 | ||
3146 | case 'X': | |
3147 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3148 | continue; | |
3149 | ||
3150 | case 'Y': | |
3151 | { | |
3152 | int regno; | |
3153 | ||
3154 | regno = va_arg (args, int); | |
3155 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3156 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3157 | } | |
3158 | continue; | |
3159 | ||
3160 | case '<': | |
3161 | case '>': | |
3162 | case '4': | |
3163 | case '5': | |
3164 | case 'H': | |
3165 | case 'W': | |
3166 | case 'D': | |
3167 | case 'j': | |
3168 | case '8': | |
3169 | case 'V': | |
3170 | case 'C': | |
3171 | case 'U': | |
3172 | case 'k': | |
3173 | case 'K': | |
3174 | case 'p': | |
3175 | case 'q': | |
3176 | { | |
3177 | assert (ep != NULL); | |
3178 | ||
3179 | if (ep->X_op != O_constant) | |
874e8986 | 3180 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3181 | else |
3182 | { | |
c4e7957c TS |
3183 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
3184 | false, &insn.insn_opcode, &insn.use_extend, | |
3185 | &insn.extend); | |
252b5132 | 3186 | ep = NULL; |
f6688943 | 3187 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3188 | } |
3189 | } | |
3190 | continue; | |
3191 | ||
3192 | case '6': | |
3193 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3194 | continue; | |
3195 | } | |
3196 | ||
3197 | break; | |
3198 | } | |
3199 | ||
f6688943 | 3200 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3201 | |
3202 | append_insn (place, &insn, ep, r, false); | |
3203 | } | |
3204 | ||
3205 | /* | |
3206 | * Generate a "lui" instruction. | |
3207 | */ | |
3208 | static void | |
3209 | macro_build_lui (place, counter, ep, regnum) | |
3210 | char *place; | |
3211 | int *counter; | |
3212 | expressionS *ep; | |
3213 | int regnum; | |
3214 | { | |
3215 | expressionS high_expr; | |
3216 | struct mips_cl_insn insn; | |
f6688943 TS |
3217 | bfd_reloc_code_real_type r[3] |
3218 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3219 | CONST char *name = "lui"; |
3220 | CONST char *fmt = "t,u"; | |
3221 | ||
3222 | assert (! mips_opts.mips16); | |
3223 | ||
3224 | if (place == NULL) | |
3225 | high_expr = *ep; | |
3226 | else | |
3227 | { | |
3228 | high_expr.X_op = O_constant; | |
3229 | high_expr.X_add_number = ep->X_add_number; | |
3230 | } | |
3231 | ||
3232 | if (high_expr.X_op == O_constant) | |
3233 | { | |
3234 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3235 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3236 | >> 16) & 0xffff; | |
f6688943 | 3237 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3238 | } |
f6688943 | 3239 | else if (! HAVE_NEWABI) |
252b5132 RH |
3240 | { |
3241 | assert (ep->X_op == O_symbol); | |
3242 | /* _gp_disp is a special case, used from s_cpload. */ | |
3243 | assert (mips_pic == NO_PIC | |
3244 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3245 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3246 | } |
3247 | ||
3248 | /* | |
3249 | * If the macro is about to expand into a second instruction, | |
3250 | * print a warning if needed. We need to pass ip as a parameter | |
3251 | * to generate a better warning message here... | |
3252 | */ | |
3253 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3254 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3255 | ||
3256 | if (place == NULL) | |
3257 | *counter += 1; /* bump instruction counter */ | |
3258 | ||
3259 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3260 | assert (insn.insn_mo); | |
3261 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3262 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3263 | ||
3264 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3265 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3266 | { |
3267 | insn.insn_opcode |= high_expr.X_add_number; | |
3268 | append_insn (place, &insn, NULL, r, false); | |
3269 | } | |
3270 | else | |
3271 | append_insn (place, &insn, &high_expr, r, false); | |
3272 | } | |
3273 | ||
3274 | /* set_at() | |
3275 | * Generates code to set the $at register to true (one) | |
3276 | * if reg is less than the immediate expression. | |
3277 | */ | |
3278 | static void | |
3279 | set_at (counter, reg, unsignedp) | |
3280 | int *counter; | |
3281 | int reg; | |
3282 | int unsignedp; | |
3283 | { | |
3284 | if (imm_expr.X_op == O_constant | |
3285 | && imm_expr.X_add_number >= -0x8000 | |
3286 | && imm_expr.X_add_number < 0x8000) | |
3287 | macro_build ((char *) NULL, counter, &imm_expr, | |
3288 | unsignedp ? "sltiu" : "slti", | |
3289 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3290 | else | |
3291 | { | |
4d34fb5f | 3292 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3293 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3294 | unsignedp ? "sltu" : "slt", |
3295 | "d,v,t", AT, reg, AT); | |
3296 | } | |
3297 | } | |
3298 | ||
3299 | /* Warn if an expression is not a constant. */ | |
3300 | ||
3301 | static void | |
3302 | check_absolute_expr (ip, ex) | |
3303 | struct mips_cl_insn *ip; | |
3304 | expressionS *ex; | |
3305 | { | |
3306 | if (ex->X_op == O_big) | |
3307 | as_bad (_("unsupported large constant")); | |
3308 | else if (ex->X_op != O_constant) | |
3309 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3310 | } | |
3311 | ||
3312 | /* Count the leading zeroes by performing a binary chop. This is a | |
3313 | bulky bit of source, but performance is a LOT better for the | |
3314 | majority of values than a simple loop to count the bits: | |
3315 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3316 | if ((v) & (1 << (31 - lcnt))) | |
3317 | break; | |
3318 | However it is not code size friendly, and the gain will drop a bit | |
3319 | on certain cached systems. | |
3320 | */ | |
3321 | #define COUNT_TOP_ZEROES(v) \ | |
3322 | (((v) & ~0xffff) == 0 \ | |
3323 | ? ((v) & ~0xff) == 0 \ | |
3324 | ? ((v) & ~0xf) == 0 \ | |
3325 | ? ((v) & ~0x3) == 0 \ | |
3326 | ? ((v) & ~0x1) == 0 \ | |
3327 | ? !(v) \ | |
3328 | ? 32 \ | |
3329 | : 31 \ | |
3330 | : 30 \ | |
3331 | : ((v) & ~0x7) == 0 \ | |
3332 | ? 29 \ | |
3333 | : 28 \ | |
3334 | : ((v) & ~0x3f) == 0 \ | |
3335 | ? ((v) & ~0x1f) == 0 \ | |
3336 | ? 27 \ | |
3337 | : 26 \ | |
3338 | : ((v) & ~0x7f) == 0 \ | |
3339 | ? 25 \ | |
3340 | : 24 \ | |
3341 | : ((v) & ~0xfff) == 0 \ | |
3342 | ? ((v) & ~0x3ff) == 0 \ | |
3343 | ? ((v) & ~0x1ff) == 0 \ | |
3344 | ? 23 \ | |
3345 | : 22 \ | |
3346 | : ((v) & ~0x7ff) == 0 \ | |
3347 | ? 21 \ | |
3348 | : 20 \ | |
3349 | : ((v) & ~0x3fff) == 0 \ | |
3350 | ? ((v) & ~0x1fff) == 0 \ | |
3351 | ? 19 \ | |
3352 | : 18 \ | |
3353 | : ((v) & ~0x7fff) == 0 \ | |
3354 | ? 17 \ | |
3355 | : 16 \ | |
3356 | : ((v) & ~0xffffff) == 0 \ | |
3357 | ? ((v) & ~0xfffff) == 0 \ | |
3358 | ? ((v) & ~0x3ffff) == 0 \ | |
3359 | ? ((v) & ~0x1ffff) == 0 \ | |
3360 | ? 15 \ | |
3361 | : 14 \ | |
3362 | : ((v) & ~0x7ffff) == 0 \ | |
3363 | ? 13 \ | |
3364 | : 12 \ | |
3365 | : ((v) & ~0x3fffff) == 0 \ | |
3366 | ? ((v) & ~0x1fffff) == 0 \ | |
3367 | ? 11 \ | |
3368 | : 10 \ | |
3369 | : ((v) & ~0x7fffff) == 0 \ | |
3370 | ? 9 \ | |
3371 | : 8 \ | |
3372 | : ((v) & ~0xfffffff) == 0 \ | |
3373 | ? ((v) & ~0x3ffffff) == 0 \ | |
3374 | ? ((v) & ~0x1ffffff) == 0 \ | |
3375 | ? 7 \ | |
3376 | : 6 \ | |
3377 | : ((v) & ~0x7ffffff) == 0 \ | |
3378 | ? 5 \ | |
3379 | : 4 \ | |
3380 | : ((v) & ~0x3fffffff) == 0 \ | |
3381 | ? ((v) & ~0x1fffffff) == 0 \ | |
3382 | ? 3 \ | |
3383 | : 2 \ | |
3384 | : ((v) & ~0x7fffffff) == 0 \ | |
3385 | ? 1 \ | |
3386 | : 0) | |
3387 | ||
6373ee54 CD |
3388 | /* Is the given value a sign-extended 32-bit value? */ |
3389 | #define IS_SEXT_32BIT_NUM(x) \ | |
3390 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
3391 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
3392 | ||
252b5132 RH |
3393 | /* load_register() |
3394 | * This routine generates the least number of instructions neccessary to load | |
3395 | * an absolute expression value into a register. | |
3396 | */ | |
3397 | static void | |
3398 | load_register (counter, reg, ep, dbl) | |
3399 | int *counter; | |
3400 | int reg; | |
3401 | expressionS *ep; | |
3402 | int dbl; | |
3403 | { | |
3404 | int freg; | |
3405 | expressionS hi32, lo32; | |
3406 | ||
3407 | if (ep->X_op != O_big) | |
3408 | { | |
3409 | assert (ep->X_op == O_constant); | |
3410 | if (ep->X_add_number < 0x8000 | |
3411 | && (ep->X_add_number >= 0 | |
3412 | || (ep->X_add_number >= -0x8000 | |
3413 | && (! dbl | |
3414 | || ! ep->X_unsigned | |
3415 | || sizeof (ep->X_add_number) > 4)))) | |
3416 | { | |
3417 | /* We can handle 16 bit signed values with an addiu to | |
3418 | $zero. No need to ever use daddiu here, since $zero and | |
3419 | the result are always correct in 32 bit mode. */ | |
3420 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3421 | (int) BFD_RELOC_LO16); | |
3422 | return; | |
3423 | } | |
3424 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3425 | { | |
3426 | /* We can handle 16 bit unsigned values with an ori to | |
3427 | $zero. */ | |
3428 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3429 | (int) BFD_RELOC_LO16); | |
3430 | return; | |
3431 | } | |
6373ee54 | 3432 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3433 | && (! dbl |
3434 | || ! ep->X_unsigned | |
3435 | || sizeof (ep->X_add_number) > 4 | |
3436 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3437 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3438 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3439 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3440 | && ! dbl |
3441 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3442 | == ~ (offsetT) 0xffffffff))) | |
3443 | { | |
3444 | /* 32 bit values require an lui. */ | |
3445 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3446 | (int) BFD_RELOC_HI16); | |
3447 | if ((ep->X_add_number & 0xffff) != 0) | |
3448 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3449 | (int) BFD_RELOC_LO16); | |
3450 | return; | |
3451 | } | |
3452 | } | |
3453 | ||
3454 | /* The value is larger than 32 bits. */ | |
3455 | ||
ca4e0257 | 3456 | if (HAVE_32BIT_GPRS) |
252b5132 | 3457 | { |
956cd1d6 TS |
3458 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3459 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3460 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3461 | (int) BFD_RELOC_LO16); | |
3462 | return; | |
3463 | } | |
3464 | ||
3465 | if (ep->X_op != O_big) | |
3466 | { | |
3467 | hi32 = *ep; | |
3468 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3469 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3470 | hi32.X_add_number &= 0xffffffff; | |
3471 | lo32 = *ep; | |
3472 | lo32.X_add_number &= 0xffffffff; | |
3473 | } | |
3474 | else | |
3475 | { | |
3476 | assert (ep->X_add_number > 2); | |
3477 | if (ep->X_add_number == 3) | |
3478 | generic_bignum[3] = 0; | |
3479 | else if (ep->X_add_number > 4) | |
3480 | as_bad (_("Number larger than 64 bits")); | |
3481 | lo32.X_op = O_constant; | |
3482 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3483 | hi32.X_op = O_constant; | |
3484 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3485 | } | |
3486 | ||
3487 | if (hi32.X_add_number == 0) | |
3488 | freg = 0; | |
3489 | else | |
3490 | { | |
3491 | int shift, bit; | |
3492 | unsigned long hi, lo; | |
3493 | ||
956cd1d6 | 3494 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3495 | { |
3496 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3497 | { | |
3498 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3499 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3500 | return; |
3501 | } | |
3502 | if (lo32.X_add_number & 0x80000000) | |
3503 | { | |
3504 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3505 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3506 | if (lo32.X_add_number & 0xffff) |
3507 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3508 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3509 | return; |
3510 | } | |
3511 | } | |
252b5132 RH |
3512 | |
3513 | /* Check for 16bit shifted constant. We know that hi32 is | |
3514 | non-zero, so start the mask on the first bit of the hi32 | |
3515 | value. */ | |
3516 | shift = 17; | |
3517 | do | |
beae10d5 KH |
3518 | { |
3519 | unsigned long himask, lomask; | |
3520 | ||
3521 | if (shift < 32) | |
3522 | { | |
3523 | himask = 0xffff >> (32 - shift); | |
3524 | lomask = (0xffff << shift) & 0xffffffff; | |
3525 | } | |
3526 | else | |
3527 | { | |
3528 | himask = 0xffff << (shift - 32); | |
3529 | lomask = 0; | |
3530 | } | |
3531 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3532 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3533 | { | |
3534 | expressionS tmp; | |
3535 | ||
3536 | tmp.X_op = O_constant; | |
3537 | if (shift < 32) | |
3538 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3539 | | (lo32.X_add_number >> shift)); | |
3540 | else | |
3541 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3542 | macro_build ((char *) NULL, counter, &tmp, | |
3543 | "ori", "t,r,i", reg, 0, | |
3544 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3545 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3546 | (shift >= 32) ? "dsll32" : "dsll", |
3547 | "d,w,<", reg, reg, | |
3548 | (shift >= 32) ? shift - 32 : shift); | |
3549 | return; | |
3550 | } | |
3551 | shift++; | |
3552 | } | |
3553 | while (shift <= (64 - 16)); | |
252b5132 RH |
3554 | |
3555 | /* Find the bit number of the lowest one bit, and store the | |
3556 | shifted value in hi/lo. */ | |
3557 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3558 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3559 | if (lo != 0) | |
3560 | { | |
3561 | bit = 0; | |
3562 | while ((lo & 1) == 0) | |
3563 | { | |
3564 | lo >>= 1; | |
3565 | ++bit; | |
3566 | } | |
3567 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3568 | hi >>= bit; | |
3569 | } | |
3570 | else | |
3571 | { | |
3572 | bit = 32; | |
3573 | while ((hi & 1) == 0) | |
3574 | { | |
3575 | hi >>= 1; | |
3576 | ++bit; | |
3577 | } | |
3578 | lo = hi; | |
3579 | hi = 0; | |
3580 | } | |
3581 | ||
3582 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3583 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3584 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3585 | { |
3586 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3587 | if (shift != 0) |
beae10d5 | 3588 | { |
252b5132 RH |
3589 | expressionS tmp; |
3590 | ||
3591 | /* This instruction will set the register to be all | |
3592 | ones. */ | |
beae10d5 KH |
3593 | tmp.X_op = O_constant; |
3594 | tmp.X_add_number = (offsetT) -1; | |
3595 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3596 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3597 | if (bit != 0) |
3598 | { | |
3599 | bit += shift; | |
2396cfb9 | 3600 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3601 | (bit >= 32) ? "dsll32" : "dsll", |
3602 | "d,w,<", reg, reg, | |
3603 | (bit >= 32) ? bit - 32 : bit); | |
3604 | } | |
2396cfb9 | 3605 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3606 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3607 | "d,w,<", reg, reg, |
252b5132 | 3608 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3609 | return; |
3610 | } | |
3611 | } | |
252b5132 RH |
3612 | |
3613 | /* Sign extend hi32 before calling load_register, because we can | |
3614 | generally get better code when we load a sign extended value. */ | |
3615 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3616 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3617 | load_register (counter, reg, &hi32, 0); |
3618 | freg = reg; | |
3619 | } | |
3620 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3621 | { | |
3622 | if (freg != 0) | |
3623 | { | |
2396cfb9 TS |
3624 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3625 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3626 | freg = reg; |
3627 | } | |
3628 | } | |
3629 | else | |
3630 | { | |
3631 | expressionS mid16; | |
3632 | ||
956cd1d6 | 3633 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3634 | { |
252b5132 RH |
3635 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3636 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3637 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3638 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3639 | return; |
3640 | } | |
252b5132 RH |
3641 | |
3642 | if (freg != 0) | |
3643 | { | |
956cd1d6 TS |
3644 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3645 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3646 | freg = reg; |
3647 | } | |
3648 | mid16 = lo32; | |
3649 | mid16.X_add_number >>= 16; | |
3650 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3651 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3652 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3653 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3654 | freg = reg; |
3655 | } | |
3656 | if ((lo32.X_add_number & 0xffff) != 0) | |
3657 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3658 | (int) BFD_RELOC_LO16); | |
3659 | } | |
3660 | ||
3661 | /* Load an address into a register. */ | |
3662 | ||
3663 | static void | |
d6bc6245 | 3664 | load_address (counter, reg, ep, dbl, used_at) |
252b5132 RH |
3665 | int *counter; |
3666 | int reg; | |
3667 | expressionS *ep; | |
d6bc6245 TS |
3668 | int dbl; |
3669 | int *used_at; | |
252b5132 RH |
3670 | { |
3671 | char *p; | |
3672 | ||
3673 | if (ep->X_op != O_constant | |
3674 | && ep->X_op != O_symbol) | |
3675 | { | |
3676 | as_bad (_("expression too complex")); | |
3677 | ep->X_op = O_constant; | |
3678 | } | |
3679 | ||
3680 | if (ep->X_op == O_constant) | |
3681 | { | |
d6bc6245 | 3682 | load_register (counter, reg, ep, dbl); |
252b5132 RH |
3683 | return; |
3684 | } | |
3685 | ||
3686 | if (mips_pic == NO_PIC) | |
3687 | { | |
3688 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3689 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3690 | Otherwise we want |
3691 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3692 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3693 | If we have an addend, we always use the latter form. |
76b3015f | 3694 | |
d6bc6245 TS |
3695 | With 64bit address space and a usable $at we want |
3696 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3697 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3698 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3699 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3700 | dsll32 $reg,0 | |
3701 | dadd $reg,$reg,$at | |
76b3015f | 3702 | |
d6bc6245 TS |
3703 | If $at is already in use, we use an path which is suboptimal |
3704 | on superscalar processors. | |
3705 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3706 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3707 | dsll $reg,16 | |
3708 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3709 | dsll $reg,16 | |
3710 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3711 | */ | |
956cd1d6 | 3712 | if (dbl) |
d6bc6245 TS |
3713 | { |
3714 | p = NULL; | |
3715 | ||
3716 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
3717 | hold the data for such large chunks. */ | |
3718 | ||
3719 | if (*used_at == 0) | |
3720 | { | |
3721 | macro_build (p, counter, ep, "lui", "t,u", | |
3722 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3723 | macro_build (p, counter, ep, "lui", "t,u", | |
3724 | AT, (int) BFD_RELOC_HI16_S); | |
3725 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3726 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3727 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3728 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3729 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3730 | "d,w,<", reg, reg, 0); | |
3731 | macro_build (p, counter, (expressionS *) NULL, "dadd", | |
3732 | "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3733 | *used_at = 1; |
3734 | } | |
3735 | else | |
3736 | { | |
3737 | macro_build (p, counter, ep, "lui", "t,u", | |
3738 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3739 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3740 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3741 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3742 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3743 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3744 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3745 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3746 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3747 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3748 | reg, reg, (int) BFD_RELOC_LO16); | |
3749 | } | |
3750 | } | |
252b5132 RH |
3751 | else |
3752 | { | |
d6bc6245 TS |
3753 | p = NULL; |
3754 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET | |
3755 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3756 | { | |
3757 | frag_grow (20); | |
3758 | macro_build ((char *) NULL, counter, ep, | |
cdf6fd85 TS |
3759 | dbl ? "daddiu" : "addiu", "t,r,j", reg, GP, |
3760 | (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3761 | p = frag_var (rs_machine_dependent, 8, 0, |
3762 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3763 | mips_opts.warn_about_macros), | |
956cd1d6 | 3764 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3765 | } |
3766 | macro_build_lui (p, counter, ep, reg); | |
3767 | if (p != NULL) | |
3768 | p += 4; | |
956cd1d6 | 3769 | macro_build (p, counter, ep, dbl ? "daddiu" : "addiu", |
d6bc6245 TS |
3770 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3771 | } | |
252b5132 RH |
3772 | } |
3773 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3774 | { | |
3775 | expressionS ex; | |
3776 | ||
3777 | /* If this is a reference to an external symbol, we want | |
3778 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3779 | Otherwise we want | |
3780 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3781 | nop | |
3782 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3783 | If there is a constant, it must be added in after. */ | |
3784 | ex.X_add_number = ep->X_add_number; | |
3785 | ep->X_add_number = 0; | |
3786 | frag_grow (20); | |
3787 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3788 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3789 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3790 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3791 | p = frag_var (rs_machine_dependent, 4, 0, | |
3792 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3793 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3794 | macro_build (p, counter, ep, | |
ca4e0257 | 3795 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3796 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3797 | if (ex.X_add_number != 0) | |
3798 | { | |
3799 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3800 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3801 | ex.X_op = O_constant; | |
3802 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3803 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3804 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3805 | } | |
3806 | } | |
3807 | else if (mips_pic == SVR4_PIC) | |
3808 | { | |
3809 | expressionS ex; | |
3810 | int off; | |
3811 | ||
3812 | /* This is the large GOT case. If this is a reference to an | |
3813 | external symbol, we want | |
3814 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3815 | addu $reg,$reg,$gp | |
3816 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3817 | Otherwise, for a reference to a local symbol, we want | |
3818 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3819 | nop | |
3820 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3821 | If there is a constant, it must be added in after. */ | |
3822 | ex.X_add_number = ep->X_add_number; | |
3823 | ep->X_add_number = 0; | |
3824 | if (reg_needs_delay (GP)) | |
3825 | off = 4; | |
3826 | else | |
3827 | off = 0; | |
3828 | frag_grow (32); | |
3829 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3830 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3831 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
956cd1d6 TS |
3832 | dbl ? "daddu" : "addu", "d,v,t", reg, reg, GP); |
3833 | macro_build ((char *) NULL, counter, ep, dbl ? "ld" : "lw", | |
252b5132 RH |
3834 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3835 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3836 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3837 | mips_opts.warn_about_macros), | |
956cd1d6 | 3838 | ep->X_add_symbol, 0, NULL); |
252b5132 RH |
3839 | if (off > 0) |
3840 | { | |
3841 | /* We need a nop before loading from $gp. This special | |
3842 | check is required because the lui which starts the main | |
3843 | instruction stream does not refer to $gp, and so will not | |
3844 | insert the nop which may be required. */ | |
3845 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3846 | p += 4; | |
3847 | } | |
956cd1d6 | 3848 | macro_build (p, counter, ep, dbl ? "ld" : "lw", |
252b5132 RH |
3849 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3850 | p += 4; | |
3851 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3852 | p += 4; | |
956cd1d6 | 3853 | macro_build (p, counter, ep, dbl ? "daddiu" : "addiu", |
252b5132 RH |
3854 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3855 | if (ex.X_add_number != 0) | |
3856 | { | |
3857 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3858 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3859 | ex.X_op = O_constant; | |
956cd1d6 | 3860 | macro_build ((char *) NULL, counter, &ex, dbl ? "daddiu" : "addiu", |
252b5132 RH |
3861 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3862 | } | |
3863 | } | |
3864 | else if (mips_pic == EMBEDDED_PIC) | |
3865 | { | |
3866 | /* We always do | |
cdf6fd85 | 3867 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 3868 | */ |
cdf6fd85 TS |
3869 | macro_build ((char *) NULL, counter, ep, dbl ? "daddiu" : "addiu", |
3870 | "t,r,j", reg, GP, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
3871 | } |
3872 | else | |
3873 | abort (); | |
3874 | } | |
3875 | ||
ea1fb5dc RS |
3876 | /* Move the contents of register SOURCE into register DEST. */ |
3877 | ||
3878 | static void | |
3879 | move_register (counter, dest, source) | |
3880 | int *counter; | |
3881 | int dest; | |
3882 | int source; | |
3883 | { | |
3884 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3885 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3886 | "d,v,t", dest, source, 0); | |
3887 | } | |
3888 | ||
252b5132 RH |
3889 | /* |
3890 | * Build macros | |
3891 | * This routine implements the seemingly endless macro or synthesized | |
3892 | * instructions and addressing modes in the mips assembly language. Many | |
3893 | * of these macros are simple and are similar to each other. These could | |
3894 | * probably be handled by some kind of table or grammer aproach instead of | |
3895 | * this verbose method. Others are not simple macros but are more like | |
3896 | * optimizing code generation. | |
3897 | * One interesting optimization is when several store macros appear | |
3898 | * consecutivly that would load AT with the upper half of the same address. | |
3899 | * The ensuing load upper instructions are ommited. This implies some kind | |
3900 | * of global optimization. We currently only optimize within a single macro. | |
3901 | * For many of the load and store macros if the address is specified as a | |
3902 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3903 | * first load register 'at' with zero and use it as the base register. The | |
3904 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3905 | * we're missing. | |
3906 | */ | |
3907 | static void | |
3908 | macro (ip) | |
3909 | struct mips_cl_insn *ip; | |
3910 | { | |
3911 | register int treg, sreg, dreg, breg; | |
3912 | int tempreg; | |
3913 | int mask; | |
3914 | int icnt = 0; | |
43841e91 | 3915 | int used_at = 0; |
252b5132 RH |
3916 | expressionS expr1; |
3917 | const char *s; | |
3918 | const char *s2; | |
3919 | const char *fmt; | |
3920 | int likely = 0; | |
3921 | int dbl = 0; | |
3922 | int coproc = 0; | |
3923 | int lr = 0; | |
3924 | int imm = 0; | |
3925 | offsetT maxnum; | |
3926 | int off; | |
3927 | bfd_reloc_code_real_type r; | |
3928 | char *p; | |
3929 | int hold_mips_optimize; | |
3930 | ||
3931 | assert (! mips_opts.mips16); | |
3932 | ||
3933 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3934 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3935 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3936 | mask = ip->insn_mo->mask; | |
3937 | ||
3938 | expr1.X_op = O_constant; | |
3939 | expr1.X_op_symbol = NULL; | |
3940 | expr1.X_add_symbol = NULL; | |
3941 | expr1.X_add_number = 1; | |
3942 | ||
3943 | switch (mask) | |
3944 | { | |
3945 | case M_DABS: | |
3946 | dbl = 1; | |
3947 | case M_ABS: | |
3948 | /* bgez $a0,.+12 | |
3949 | move v0,$a0 | |
3950 | sub v0,$zero,$a0 | |
3951 | */ | |
3952 | ||
3953 | mips_emit_delays (true); | |
3954 | ++mips_opts.noreorder; | |
3955 | mips_any_noreorder = 1; | |
3956 | ||
3957 | expr1.X_add_number = 8; | |
3958 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3959 | if (dreg == sreg) | |
2396cfb9 TS |
3960 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
3961 | 0); | |
252b5132 | 3962 | else |
ea1fb5dc | 3963 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 3964 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 3965 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
3966 | |
3967 | --mips_opts.noreorder; | |
3968 | return; | |
3969 | ||
3970 | case M_ADD_I: | |
3971 | s = "addi"; | |
3972 | s2 = "add"; | |
3973 | goto do_addi; | |
3974 | case M_ADDU_I: | |
3975 | s = "addiu"; | |
3976 | s2 = "addu"; | |
3977 | goto do_addi; | |
3978 | case M_DADD_I: | |
3979 | dbl = 1; | |
3980 | s = "daddi"; | |
3981 | s2 = "dadd"; | |
3982 | goto do_addi; | |
3983 | case M_DADDU_I: | |
3984 | dbl = 1; | |
3985 | s = "daddiu"; | |
3986 | s2 = "daddu"; | |
3987 | do_addi: | |
3988 | if (imm_expr.X_op == O_constant | |
3989 | && imm_expr.X_add_number >= -0x8000 | |
3990 | && imm_expr.X_add_number < 0x8000) | |
3991 | { | |
3992 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3993 | (int) BFD_RELOC_LO16); | |
3994 | return; | |
3995 | } | |
3996 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
3997 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
3998 | treg, sreg, AT); | |
252b5132 RH |
3999 | break; |
4000 | ||
4001 | case M_AND_I: | |
4002 | s = "andi"; | |
4003 | s2 = "and"; | |
4004 | goto do_bit; | |
4005 | case M_OR_I: | |
4006 | s = "ori"; | |
4007 | s2 = "or"; | |
4008 | goto do_bit; | |
4009 | case M_NOR_I: | |
4010 | s = ""; | |
4011 | s2 = "nor"; | |
4012 | goto do_bit; | |
4013 | case M_XOR_I: | |
4014 | s = "xori"; | |
4015 | s2 = "xor"; | |
4016 | do_bit: | |
4017 | if (imm_expr.X_op == O_constant | |
4018 | && imm_expr.X_add_number >= 0 | |
4019 | && imm_expr.X_add_number < 0x10000) | |
4020 | { | |
4021 | if (mask != M_NOR_I) | |
4022 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4023 | sreg, (int) BFD_RELOC_LO16); | |
4024 | else | |
4025 | { | |
4026 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4027 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4029 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4030 | } |
4031 | return; | |
4032 | } | |
4033 | ||
d6bc6245 | 4034 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4035 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4036 | treg, sreg, AT); | |
252b5132 RH |
4037 | break; |
4038 | ||
4039 | case M_BEQ_I: | |
4040 | s = "beq"; | |
4041 | goto beq_i; | |
4042 | case M_BEQL_I: | |
4043 | s = "beql"; | |
4044 | likely = 1; | |
4045 | goto beq_i; | |
4046 | case M_BNE_I: | |
4047 | s = "bne"; | |
4048 | goto beq_i; | |
4049 | case M_BNEL_I: | |
4050 | s = "bnel"; | |
4051 | likely = 1; | |
4052 | beq_i: | |
4053 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4054 | { | |
4055 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4056 | 0); | |
4057 | return; | |
4058 | } | |
4d34fb5f | 4059 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4060 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4061 | break; | |
4062 | ||
4063 | case M_BGEL: | |
4064 | likely = 1; | |
4065 | case M_BGE: | |
4066 | if (treg == 0) | |
4067 | { | |
4068 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4069 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4070 | return; |
4071 | } | |
4072 | if (sreg == 0) | |
4073 | { | |
4074 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4075 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4076 | return; |
4077 | } | |
2396cfb9 TS |
4078 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4079 | AT, sreg, treg); | |
252b5132 | 4080 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4081 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4082 | break; |
4083 | ||
4084 | case M_BGTL_I: | |
4085 | likely = 1; | |
4086 | case M_BGT_I: | |
4087 | /* check for > max integer */ | |
4088 | maxnum = 0x7fffffff; | |
ca4e0257 | 4089 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4090 | { |
4091 | maxnum <<= 16; | |
4092 | maxnum |= 0xffff; | |
4093 | maxnum <<= 16; | |
4094 | maxnum |= 0xffff; | |
4095 | } | |
4096 | if (imm_expr.X_op == O_constant | |
4097 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4098 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4099 | { |
4100 | do_false: | |
4101 | /* result is always false */ | |
4102 | if (! likely) | |
4103 | { | |
39c0a331 L |
4104 | if (warn_nops) |
4105 | as_warn (_("Branch %s is always false (nop)"), | |
4106 | ip->insn_mo->name); | |
2396cfb9 TS |
4107 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4108 | "", 0); | |
252b5132 RH |
4109 | } |
4110 | else | |
4111 | { | |
39c0a331 L |
4112 | if (warn_nops) |
4113 | as_warn (_("Branch likely %s is always false"), | |
4114 | ip->insn_mo->name); | |
252b5132 RH |
4115 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4116 | "s,t,p", 0, 0); | |
4117 | } | |
4118 | return; | |
4119 | } | |
4120 | if (imm_expr.X_op != O_constant) | |
4121 | as_bad (_("Unsupported large constant")); | |
4122 | imm_expr.X_add_number++; | |
4123 | /* FALLTHROUGH */ | |
4124 | case M_BGE_I: | |
4125 | case M_BGEL_I: | |
4126 | if (mask == M_BGEL_I) | |
4127 | likely = 1; | |
4128 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4129 | { | |
4130 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4131 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4132 | return; |
4133 | } | |
4134 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4135 | { | |
4136 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4137 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4138 | return; |
4139 | } | |
4140 | maxnum = 0x7fffffff; | |
ca4e0257 | 4141 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4142 | { |
4143 | maxnum <<= 16; | |
4144 | maxnum |= 0xffff; | |
4145 | maxnum <<= 16; | |
4146 | maxnum |= 0xffff; | |
4147 | } | |
4148 | maxnum = - maxnum - 1; | |
4149 | if (imm_expr.X_op == O_constant | |
4150 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4151 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4152 | { |
4153 | do_true: | |
4154 | /* result is always true */ | |
4155 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4156 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4157 | return; | |
4158 | } | |
4159 | set_at (&icnt, sreg, 0); | |
4160 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4161 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4162 | break; |
4163 | ||
4164 | case M_BGEUL: | |
4165 | likely = 1; | |
4166 | case M_BGEU: | |
4167 | if (treg == 0) | |
4168 | goto do_true; | |
4169 | if (sreg == 0) | |
4170 | { | |
4171 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4172 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4173 | return; |
4174 | } | |
2396cfb9 TS |
4175 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4176 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4177 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4178 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4179 | break; |
4180 | ||
4181 | case M_BGTUL_I: | |
4182 | likely = 1; | |
4183 | case M_BGTU_I: | |
4184 | if (sreg == 0 | |
ca4e0257 | 4185 | || (HAVE_32BIT_GPRS |
252b5132 | 4186 | && imm_expr.X_op == O_constant |
956cd1d6 | 4187 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4188 | goto do_false; |
4189 | if (imm_expr.X_op != O_constant) | |
4190 | as_bad (_("Unsupported large constant")); | |
4191 | imm_expr.X_add_number++; | |
4192 | /* FALLTHROUGH */ | |
4193 | case M_BGEU_I: | |
4194 | case M_BGEUL_I: | |
4195 | if (mask == M_BGEUL_I) | |
4196 | likely = 1; | |
4197 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4198 | goto do_true; | |
4199 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4200 | { | |
4201 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4202 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4203 | return; |
4204 | } | |
4205 | set_at (&icnt, sreg, 1); | |
4206 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4207 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4208 | break; |
4209 | ||
4210 | case M_BGTL: | |
4211 | likely = 1; | |
4212 | case M_BGT: | |
4213 | if (treg == 0) | |
4214 | { | |
4215 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4216 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4217 | return; |
4218 | } | |
4219 | if (sreg == 0) | |
4220 | { | |
4221 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4222 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4223 | return; |
4224 | } | |
2396cfb9 TS |
4225 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4226 | AT, treg, sreg); | |
252b5132 | 4227 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4228 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4229 | break; |
4230 | ||
4231 | case M_BGTUL: | |
4232 | likely = 1; | |
4233 | case M_BGTU: | |
4234 | if (treg == 0) | |
4235 | { | |
4236 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4237 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4238 | return; |
4239 | } | |
4240 | if (sreg == 0) | |
4241 | goto do_false; | |
2396cfb9 TS |
4242 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4243 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4244 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4245 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4246 | break; |
4247 | ||
4248 | case M_BLEL: | |
4249 | likely = 1; | |
4250 | case M_BLE: | |
4251 | if (treg == 0) | |
4252 | { | |
4253 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4254 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4255 | return; |
4256 | } | |
4257 | if (sreg == 0) | |
4258 | { | |
4259 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4260 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4261 | return; |
4262 | } | |
2396cfb9 TS |
4263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4264 | AT, treg, sreg); | |
252b5132 | 4265 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4266 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4267 | break; |
4268 | ||
4269 | case M_BLEL_I: | |
4270 | likely = 1; | |
4271 | case M_BLE_I: | |
4272 | maxnum = 0x7fffffff; | |
ca4e0257 | 4273 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4274 | { |
4275 | maxnum <<= 16; | |
4276 | maxnum |= 0xffff; | |
4277 | maxnum <<= 16; | |
4278 | maxnum |= 0xffff; | |
4279 | } | |
4280 | if (imm_expr.X_op == O_constant | |
4281 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4282 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4283 | goto do_true; |
4284 | if (imm_expr.X_op != O_constant) | |
4285 | as_bad (_("Unsupported large constant")); | |
4286 | imm_expr.X_add_number++; | |
4287 | /* FALLTHROUGH */ | |
4288 | case M_BLT_I: | |
4289 | case M_BLTL_I: | |
4290 | if (mask == M_BLTL_I) | |
4291 | likely = 1; | |
4292 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4293 | { | |
4294 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4295 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4296 | return; |
4297 | } | |
4298 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4299 | { | |
4300 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4301 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4302 | return; |
4303 | } | |
4304 | set_at (&icnt, sreg, 0); | |
4305 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4306 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4307 | break; |
4308 | ||
4309 | case M_BLEUL: | |
4310 | likely = 1; | |
4311 | case M_BLEU: | |
4312 | if (treg == 0) | |
4313 | { | |
4314 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4315 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4316 | return; |
4317 | } | |
4318 | if (sreg == 0) | |
4319 | goto do_true; | |
2396cfb9 TS |
4320 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4321 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4322 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4323 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4324 | break; |
4325 | ||
4326 | case M_BLEUL_I: | |
4327 | likely = 1; | |
4328 | case M_BLEU_I: | |
4329 | if (sreg == 0 | |
ca4e0257 | 4330 | || (HAVE_32BIT_GPRS |
252b5132 | 4331 | && imm_expr.X_op == O_constant |
956cd1d6 | 4332 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4333 | goto do_true; |
4334 | if (imm_expr.X_op != O_constant) | |
4335 | as_bad (_("Unsupported large constant")); | |
4336 | imm_expr.X_add_number++; | |
4337 | /* FALLTHROUGH */ | |
4338 | case M_BLTU_I: | |
4339 | case M_BLTUL_I: | |
4340 | if (mask == M_BLTUL_I) | |
4341 | likely = 1; | |
4342 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4343 | goto do_false; | |
4344 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4345 | { | |
4346 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4347 | likely ? "beql" : "beq", | |
4348 | "s,t,p", sreg, 0); | |
4349 | return; | |
4350 | } | |
4351 | set_at (&icnt, sreg, 1); | |
4352 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4353 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4354 | break; |
4355 | ||
4356 | case M_BLTL: | |
4357 | likely = 1; | |
4358 | case M_BLT: | |
4359 | if (treg == 0) | |
4360 | { | |
4361 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4362 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4363 | return; |
4364 | } | |
4365 | if (sreg == 0) | |
4366 | { | |
4367 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4368 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4369 | return; |
4370 | } | |
2396cfb9 TS |
4371 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4372 | AT, sreg, treg); | |
252b5132 | 4373 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4374 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4375 | break; |
4376 | ||
4377 | case M_BLTUL: | |
4378 | likely = 1; | |
4379 | case M_BLTU: | |
4380 | if (treg == 0) | |
4381 | goto do_false; | |
4382 | if (sreg == 0) | |
4383 | { | |
4384 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4385 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4386 | return; |
4387 | } | |
2396cfb9 TS |
4388 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4389 | "d,v,t", AT, sreg, | |
252b5132 RH |
4390 | treg); |
4391 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4392 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4393 | break; |
4394 | ||
4395 | case M_DDIV_3: | |
4396 | dbl = 1; | |
4397 | case M_DIV_3: | |
4398 | s = "mflo"; | |
4399 | goto do_div3; | |
4400 | case M_DREM_3: | |
4401 | dbl = 1; | |
4402 | case M_REM_3: | |
4403 | s = "mfhi"; | |
4404 | do_div3: | |
4405 | if (treg == 0) | |
4406 | { | |
4407 | as_warn (_("Divide by zero.")); | |
4408 | if (mips_trap) | |
2396cfb9 TS |
4409 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4410 | "s,t", 0, 0); | |
252b5132 | 4411 | else |
2396cfb9 TS |
4412 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4413 | "c", 7); | |
252b5132 RH |
4414 | return; |
4415 | } | |
4416 | ||
4417 | mips_emit_delays (true); | |
4418 | ++mips_opts.noreorder; | |
4419 | mips_any_noreorder = 1; | |
4420 | if (mips_trap) | |
4421 | { | |
2396cfb9 TS |
4422 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4423 | "s,t", treg, 0); | |
4424 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 4425 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4426 | } |
4427 | else | |
4428 | { | |
4429 | expr1.X_add_number = 8; | |
4430 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4431 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4432 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4433 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4434 | "c", 7); | |
252b5132 RH |
4435 | } |
4436 | expr1.X_add_number = -1; | |
4437 | macro_build ((char *) NULL, &icnt, &expr1, | |
4438 | dbl ? "daddiu" : "addiu", | |
4439 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4440 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4441 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4442 | if (dbl) | |
4443 | { | |
4444 | expr1.X_add_number = 1; | |
4445 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4446 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4447 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4448 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4449 | } |
4450 | else | |
4451 | { | |
4452 | expr1.X_add_number = 0x80000000; | |
4453 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4454 | (int) BFD_RELOC_HI16); | |
4455 | } | |
4456 | if (mips_trap) | |
4457 | { | |
2396cfb9 TS |
4458 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4459 | "s,t", sreg, AT); | |
252b5132 RH |
4460 | /* We want to close the noreorder block as soon as possible, so |
4461 | that later insns are available for delay slot filling. */ | |
4462 | --mips_opts.noreorder; | |
4463 | } | |
4464 | else | |
4465 | { | |
4466 | expr1.X_add_number = 8; | |
4467 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4468 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4469 | 0); | |
252b5132 RH |
4470 | |
4471 | /* We want to close the noreorder block as soon as possible, so | |
4472 | that later insns are available for delay slot filling. */ | |
4473 | --mips_opts.noreorder; | |
4474 | ||
2396cfb9 TS |
4475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4476 | "c", 6); | |
252b5132 | 4477 | } |
2396cfb9 | 4478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4479 | break; |
4480 | ||
4481 | case M_DIV_3I: | |
4482 | s = "div"; | |
4483 | s2 = "mflo"; | |
4484 | goto do_divi; | |
4485 | case M_DIVU_3I: | |
4486 | s = "divu"; | |
4487 | s2 = "mflo"; | |
4488 | goto do_divi; | |
4489 | case M_REM_3I: | |
4490 | s = "div"; | |
4491 | s2 = "mfhi"; | |
4492 | goto do_divi; | |
4493 | case M_REMU_3I: | |
4494 | s = "divu"; | |
4495 | s2 = "mfhi"; | |
4496 | goto do_divi; | |
4497 | case M_DDIV_3I: | |
4498 | dbl = 1; | |
4499 | s = "ddiv"; | |
4500 | s2 = "mflo"; | |
4501 | goto do_divi; | |
4502 | case M_DDIVU_3I: | |
4503 | dbl = 1; | |
4504 | s = "ddivu"; | |
4505 | s2 = "mflo"; | |
4506 | goto do_divi; | |
4507 | case M_DREM_3I: | |
4508 | dbl = 1; | |
4509 | s = "ddiv"; | |
4510 | s2 = "mfhi"; | |
4511 | goto do_divi; | |
4512 | case M_DREMU_3I: | |
4513 | dbl = 1; | |
4514 | s = "ddivu"; | |
4515 | s2 = "mfhi"; | |
4516 | do_divi: | |
4517 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4518 | { | |
4519 | as_warn (_("Divide by zero.")); | |
4520 | if (mips_trap) | |
2396cfb9 TS |
4521 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4522 | "s,t", 0, 0); | |
252b5132 | 4523 | else |
2396cfb9 TS |
4524 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4525 | "c", 7); | |
252b5132 RH |
4526 | return; |
4527 | } | |
4528 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4529 | { | |
4530 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4531 | move_register (&icnt, dreg, sreg); |
252b5132 | 4532 | else |
ea1fb5dc | 4533 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4534 | return; |
4535 | } | |
4536 | if (imm_expr.X_op == O_constant | |
4537 | && imm_expr.X_add_number == -1 | |
4538 | && s[strlen (s) - 1] != 'u') | |
4539 | { | |
4540 | if (strcmp (s2, "mflo") == 0) | |
4541 | { | |
2396cfb9 TS |
4542 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4543 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4544 | } |
4545 | else | |
ea1fb5dc | 4546 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4547 | return; |
4548 | } | |
4549 | ||
4550 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4551 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4552 | sreg, AT); | |
4553 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4554 | break; |
4555 | ||
4556 | case M_DIVU_3: | |
4557 | s = "divu"; | |
4558 | s2 = "mflo"; | |
4559 | goto do_divu3; | |
4560 | case M_REMU_3: | |
4561 | s = "divu"; | |
4562 | s2 = "mfhi"; | |
4563 | goto do_divu3; | |
4564 | case M_DDIVU_3: | |
4565 | s = "ddivu"; | |
4566 | s2 = "mflo"; | |
4567 | goto do_divu3; | |
4568 | case M_DREMU_3: | |
4569 | s = "ddivu"; | |
4570 | s2 = "mfhi"; | |
4571 | do_divu3: | |
4572 | mips_emit_delays (true); | |
4573 | ++mips_opts.noreorder; | |
4574 | mips_any_noreorder = 1; | |
4575 | if (mips_trap) | |
4576 | { | |
2396cfb9 TS |
4577 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4578 | "s,t", treg, 0); | |
4579 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", | |
4580 | sreg, treg); | |
252b5132 RH |
4581 | /* We want to close the noreorder block as soon as possible, so |
4582 | that later insns are available for delay slot filling. */ | |
4583 | --mips_opts.noreorder; | |
4584 | } | |
4585 | else | |
4586 | { | |
4587 | expr1.X_add_number = 8; | |
4588 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4589 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4590 | sreg, treg); | |
252b5132 RH |
4591 | |
4592 | /* We want to close the noreorder block as soon as possible, so | |
4593 | that later insns are available for delay slot filling. */ | |
4594 | --mips_opts.noreorder; | |
2396cfb9 TS |
4595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4596 | "c", 7); | |
252b5132 | 4597 | } |
2396cfb9 | 4598 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4599 | return; |
4600 | ||
4601 | case M_DLA_AB: | |
4602 | dbl = 1; | |
4603 | case M_LA_AB: | |
4604 | /* Load the address of a symbol into a register. If breg is not | |
4605 | zero, we then add a base register to it. */ | |
4606 | ||
3bec30a8 TS |
4607 | if (dbl && HAVE_32BIT_GPRS) |
4608 | as_warn (_("dla used to load 32-bit register")); | |
4609 | ||
c90bbe5b | 4610 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4611 | as_warn (_("la used to load 64-bit address")); |
4612 | ||
afdbd6d0 CD |
4613 | if (treg == breg) |
4614 | { | |
4615 | tempreg = AT; | |
4616 | used_at = 1; | |
4617 | } | |
4618 | else | |
4619 | { | |
4620 | tempreg = treg; | |
4621 | used_at = 0; | |
4622 | } | |
4623 | ||
252b5132 RH |
4624 | /* When generating embedded PIC code, we permit expressions of |
4625 | the form | |
afdbd6d0 CD |
4626 | la $treg,foo-bar |
4627 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4628 | where bar is an address in the current section. These are used |
252b5132 RH |
4629 | when getting the addresses of functions. We don't permit |
4630 | X_add_number to be non-zero, because if the symbol is | |
4631 | external the relaxing code needs to know that any addend is | |
4632 | purely the offset to X_op_symbol. */ | |
4633 | if (mips_pic == EMBEDDED_PIC | |
4634 | && offset_expr.X_op == O_subtract | |
49309057 | 4635 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4636 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4637 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4638 | && (S_GET_SEGMENT | |
4639 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4640 | ->X_add_symbol) | |
bb2d6cd7 | 4641 | == now_seg))) |
bb2d6cd7 GK |
4642 | && (offset_expr.X_add_number == 0 |
4643 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4644 | { |
afdbd6d0 CD |
4645 | if (breg == 0) |
4646 | { | |
4647 | tempreg = treg; | |
4648 | used_at = 0; | |
4649 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4650 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4651 | } | |
4652 | else | |
4653 | { | |
4654 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4655 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4656 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4657 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4658 | "d,v,t", tempreg, tempreg, breg); |
4659 | } | |
252b5132 | 4660 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4661 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4662 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4663 | if (! used_at) | |
4664 | return; | |
4665 | break; | |
252b5132 RH |
4666 | } |
4667 | ||
4668 | if (offset_expr.X_op != O_symbol | |
4669 | && offset_expr.X_op != O_constant) | |
4670 | { | |
4671 | as_bad (_("expression too complex")); | |
4672 | offset_expr.X_op = O_constant; | |
4673 | } | |
4674 | ||
252b5132 | 4675 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4676 | load_register (&icnt, tempreg, &offset_expr, |
4677 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4678 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4679 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4680 | else if (mips_pic == NO_PIC) |
4681 | { | |
d6bc6245 | 4682 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4683 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4684 | Otherwise we want |
4685 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4686 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4687 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4688 | so we may as well always use the latter form. |
76b3015f | 4689 | |
d6bc6245 TS |
4690 | With 64bit address space and a usable $at we want |
4691 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4692 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4693 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4694 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4695 | dsll32 $tempreg,0 | |
4696 | dadd $tempreg,$tempreg,$at | |
76b3015f | 4697 | |
d6bc6245 TS |
4698 | If $at is already in use, we use an path which is suboptimal |
4699 | on superscalar processors. | |
4700 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4701 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4702 | dsll $tempreg,16 | |
4703 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4704 | dsll $tempreg,16 | |
4705 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4706 | */ | |
4707 | p = NULL; | |
4708 | if (HAVE_64BIT_ADDRESSES) | |
252b5132 | 4709 | { |
d6bc6245 TS |
4710 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4711 | hold the data for such large chunks. */ | |
4712 | ||
98d3f06f KH |
4713 | if (used_at == 0) |
4714 | { | |
4715 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4716 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4717 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4718 | AT, (int) BFD_RELOC_HI16_S); | |
4719 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4720 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4721 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4722 | AT, AT, (int) BFD_RELOC_LO16); | |
4723 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4724 | "d,w,<", tempreg, tempreg, 0); | |
4725 | macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t", | |
4726 | tempreg, tempreg, AT); | |
4727 | used_at = 1; | |
4728 | } | |
4729 | else | |
4730 | { | |
4731 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4732 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4733 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4734 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4735 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4736 | tempreg, tempreg, 16); | |
4737 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4738 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4739 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4740 | tempreg, tempreg, 16); | |
4741 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4742 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4743 | } | |
4744 | } | |
4745 | else | |
4746 | { | |
4747 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4748 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4749 | { | |
4750 | frag_grow (20); | |
4751 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
4752 | "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16); | |
4753 | p = frag_var (rs_machine_dependent, 8, 0, | |
4754 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4755 | mips_opts.warn_about_macros), | |
4756 | offset_expr.X_add_symbol, 0, NULL); | |
4757 | } | |
4758 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4759 | if (p != NULL) | |
4760 | p += 4; | |
4761 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4762 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4763 | } | |
252b5132 RH |
4764 | } |
4765 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4766 | { | |
9117d219 NC |
4767 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4768 | ||
252b5132 RH |
4769 | /* If this is a reference to an external symbol, and there |
4770 | is no constant, we want | |
4771 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4772 | or if tempreg is PIC_CALL_REG |
4773 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4774 | For a local symbol, we want |
4775 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4776 | nop | |
4777 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4778 | ||
4779 | If we have a small constant, and this is a reference to | |
4780 | an external symbol, we want | |
4781 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4782 | nop | |
4783 | addiu $tempreg,$tempreg,<constant> | |
4784 | For a local symbol, we want the same instruction | |
4785 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4786 | addiu instruction. | |
4787 | ||
4788 | If we have a large constant, and this is a reference to | |
4789 | an external symbol, we want | |
4790 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4791 | lui $at,<hiconstant> | |
4792 | addiu $at,$at,<loconstant> | |
4793 | addu $tempreg,$tempreg,$at | |
4794 | For a local symbol, we want the same instruction | |
4795 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4796 | addiu instruction. */ | |
4797 | expr1.X_add_number = offset_expr.X_add_number; | |
4798 | offset_expr.X_add_number = 0; | |
4799 | frag_grow (32); | |
9117d219 NC |
4800 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4801 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4d34fb5f TS |
4802 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4803 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
9117d219 | 4804 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4805 | if (expr1.X_add_number == 0) |
4806 | { | |
4807 | int off; | |
4808 | ||
4809 | if (breg == 0) | |
4810 | off = 0; | |
4811 | else | |
4812 | { | |
4813 | /* We're going to put in an addu instruction using | |
4814 | tempreg, so we may as well insert the nop right | |
4815 | now. */ | |
4816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4817 | "nop", ""); | |
4818 | off = 4; | |
4819 | } | |
4820 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4821 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4822 | (breg == 0 | |
4823 | ? mips_opts.warn_about_macros | |
4824 | : 0)), | |
c4e7957c | 4825 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4826 | if (breg == 0) |
4827 | { | |
4828 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4829 | p += 4; | |
4830 | } | |
4831 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4832 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4833 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4834 | /* FIXME: If breg == 0, and the next instruction uses | |
4835 | $tempreg, then if this variant case is used an extra | |
4836 | nop will be generated. */ | |
4837 | } | |
4838 | else if (expr1.X_add_number >= -0x8000 | |
4839 | && expr1.X_add_number < 0x8000) | |
4840 | { | |
4841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4842 | "nop", ""); | |
4843 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4844 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 4845 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
4846 | frag_var (rs_machine_dependent, 0, 0, |
4847 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4848 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4849 | } |
4850 | else | |
4851 | { | |
4852 | int off1; | |
4853 | ||
4854 | /* If we are going to add in a base register, and the | |
4855 | target register and the base register are the same, | |
4856 | then we are using AT as a temporary register. Since | |
4857 | we want to load the constant into AT, we add our | |
4858 | current AT (from the global offset table) and the | |
4859 | register into the register now, and pretend we were | |
4860 | not using a base register. */ | |
4861 | if (breg != treg) | |
4862 | off1 = 0; | |
4863 | else | |
4864 | { | |
4865 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4866 | "nop", ""); | |
4867 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4868 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4869 | "d,v,t", treg, AT, breg); |
4870 | breg = 0; | |
4871 | tempreg = treg; | |
4872 | off1 = -8; | |
4873 | } | |
4874 | ||
4875 | /* Set mips_optimize around the lui instruction to avoid | |
4876 | inserting an unnecessary nop after the lw. */ | |
4877 | hold_mips_optimize = mips_optimize; | |
4878 | mips_optimize = 2; | |
c4e7957c | 4879 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4880 | mips_optimize = hold_mips_optimize; |
4881 | ||
4882 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4883 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4884 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4886 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 4887 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
4888 | frag_var (rs_machine_dependent, 0, 0, |
4889 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4890 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4891 | used_at = 1; |
4892 | } | |
4893 | } | |
4894 | else if (mips_pic == SVR4_PIC) | |
4895 | { | |
4896 | int gpdel; | |
9117d219 NC |
4897 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4898 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4899 | |
4900 | /* This is the large GOT case. If this is a reference to an | |
4901 | external symbol, and there is no constant, we want | |
4902 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4903 | addu $tempreg,$tempreg,$gp | |
4904 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4905 | or if tempreg is PIC_CALL_REG |
4906 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4907 | addu $tempreg,$tempreg,$gp | |
4908 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4909 | For a local symbol, we want |
4910 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4911 | nop | |
4912 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4913 | ||
4914 | If we have a small constant, and this is a reference to | |
4915 | an external symbol, we want | |
4916 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4917 | addu $tempreg,$tempreg,$gp | |
4918 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4919 | nop | |
4920 | addiu $tempreg,$tempreg,<constant> | |
4921 | For a local symbol, we want | |
4922 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4923 | nop | |
4924 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4925 | ||
4926 | If we have a large constant, and this is a reference to | |
4927 | an external symbol, we want | |
4928 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4929 | addu $tempreg,$tempreg,$gp | |
4930 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4931 | lui $at,<hiconstant> | |
4932 | addiu $at,$at,<loconstant> | |
4933 | addu $tempreg,$tempreg,$at | |
4934 | For a local symbol, we want | |
4935 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4936 | lui $at,<hiconstant> | |
4937 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4938 | addu $tempreg,$tempreg,$at | |
4939 | */ | |
4940 | expr1.X_add_number = offset_expr.X_add_number; | |
4941 | offset_expr.X_add_number = 0; | |
4942 | frag_grow (52); | |
4943 | if (reg_needs_delay (GP)) | |
4944 | gpdel = 4; | |
4945 | else | |
4946 | gpdel = 0; | |
9117d219 NC |
4947 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4948 | { | |
4949 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4950 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4951 | } | |
252b5132 | 4952 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4953 | tempreg, lui_reloc_type); |
252b5132 | 4954 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 4955 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4956 | "d,v,t", tempreg, tempreg, GP); |
4957 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4d34fb5f | 4958 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 4959 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4960 | if (expr1.X_add_number == 0) |
4961 | { | |
4962 | int off; | |
4963 | ||
4964 | if (breg == 0) | |
4965 | off = 0; | |
4966 | else | |
4967 | { | |
4968 | /* We're going to put in an addu instruction using | |
4969 | tempreg, so we may as well insert the nop right | |
4970 | now. */ | |
4971 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4972 | "nop", ""); | |
4973 | off = 4; | |
4974 | } | |
4975 | ||
4976 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4977 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4978 | 8 + gpdel, 0, | |
4979 | (breg == 0 | |
4980 | ? mips_opts.warn_about_macros | |
4981 | : 0)), | |
c4e7957c | 4982 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4983 | } |
4984 | else if (expr1.X_add_number >= -0x8000 | |
4985 | && expr1.X_add_number < 0x8000) | |
4986 | { | |
4987 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4988 | "nop", ""); | |
4989 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4990 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4991 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4992 | ||
4993 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4994 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4995 | (breg == 0 | |
4996 | ? mips_opts.warn_about_macros | |
4997 | : 0)), | |
c4e7957c | 4998 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4999 | } |
5000 | else | |
5001 | { | |
5002 | int adj, dreg; | |
5003 | ||
5004 | /* If we are going to add in a base register, and the | |
5005 | target register and the base register are the same, | |
5006 | then we are using AT as a temporary register. Since | |
5007 | we want to load the constant into AT, we add our | |
5008 | current AT (from the global offset table) and the | |
5009 | register into the register now, and pretend we were | |
5010 | not using a base register. */ | |
5011 | if (breg != treg) | |
5012 | { | |
5013 | adj = 0; | |
5014 | dreg = tempreg; | |
5015 | } | |
5016 | else | |
5017 | { | |
5018 | assert (tempreg == AT); | |
5019 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5020 | "nop", ""); | |
5021 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5022 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5023 | "d,v,t", treg, AT, breg); |
5024 | dreg = treg; | |
5025 | adj = 8; | |
5026 | } | |
5027 | ||
5028 | /* Set mips_optimize around the lui instruction to avoid | |
5029 | inserting an unnecessary nop after the lw. */ | |
5030 | hold_mips_optimize = mips_optimize; | |
5031 | mips_optimize = 2; | |
c4e7957c | 5032 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5033 | mips_optimize = hold_mips_optimize; |
5034 | ||
5035 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5036 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5037 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5039 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5040 | "d,v,t", dreg, dreg, AT); |
5041 | ||
5042 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5043 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5044 | 8 + gpdel, 0, | |
5045 | (breg == 0 | |
5046 | ? mips_opts.warn_about_macros | |
5047 | : 0)), | |
c4e7957c | 5048 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5049 | |
5050 | used_at = 1; | |
5051 | } | |
5052 | ||
5053 | if (gpdel > 0) | |
5054 | { | |
5055 | /* This is needed because this instruction uses $gp, but | |
5056 | the first instruction on the main stream does not. */ | |
5057 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5058 | p += 4; | |
5059 | } | |
5060 | macro_build (p, &icnt, &offset_expr, | |
4d34fb5f | 5061 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5062 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5063 | p += 4; | |
5064 | if (expr1.X_add_number >= -0x8000 | |
5065 | && expr1.X_add_number < 0x8000) | |
5066 | { | |
5067 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5068 | p += 4; | |
5069 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5070 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5071 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5072 | /* FIXME: If add_number is 0, and there was no base | |
5073 | register, the external symbol case ended with a load, | |
5074 | so if the symbol turns out to not be external, and | |
5075 | the next instruction uses tempreg, an unnecessary nop | |
5076 | will be inserted. */ | |
5077 | } | |
5078 | else | |
5079 | { | |
5080 | if (breg == treg) | |
5081 | { | |
5082 | /* We must add in the base register now, as in the | |
5083 | external symbol case. */ | |
5084 | assert (tempreg == AT); | |
5085 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5086 | p += 4; | |
5087 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5088 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5089 | "d,v,t", treg, AT, breg); |
5090 | p += 4; | |
5091 | tempreg = treg; | |
5092 | /* We set breg to 0 because we have arranged to add | |
5093 | it in in both cases. */ | |
5094 | breg = 0; | |
5095 | } | |
5096 | ||
5097 | macro_build_lui (p, &icnt, &expr1, AT); | |
5098 | p += 4; | |
5099 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5100 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5101 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5102 | p += 4; | |
5103 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5104 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5105 | "d,v,t", tempreg, tempreg, AT); |
5106 | p += 4; | |
5107 | } | |
5108 | } | |
5109 | else if (mips_pic == EMBEDDED_PIC) | |
5110 | { | |
5111 | /* We use | |
cdf6fd85 | 5112 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5113 | */ |
5114 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5115 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
cdf6fd85 | 5116 | "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
5117 | } |
5118 | else | |
5119 | abort (); | |
5120 | ||
5121 | if (breg != 0) | |
4d34fb5f TS |
5122 | { |
5123 | char *s; | |
5124 | ||
5125 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5126 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5127 | else | |
5128 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5129 | ||
5130 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5131 | "d,v,t", treg, tempreg, breg); | |
5132 | } | |
252b5132 RH |
5133 | |
5134 | if (! used_at) | |
5135 | return; | |
5136 | ||
5137 | break; | |
5138 | ||
5139 | case M_J_A: | |
5140 | /* The j instruction may not be used in PIC code, since it | |
5141 | requires an absolute address. We convert it to a b | |
5142 | instruction. */ | |
5143 | if (mips_pic == NO_PIC) | |
5144 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5145 | else | |
5146 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5147 | return; | |
5148 | ||
5149 | /* The jal instructions must be handled as macros because when | |
5150 | generating PIC code they expand to multi-instruction | |
5151 | sequences. Normally they are simple instructions. */ | |
5152 | case M_JAL_1: | |
5153 | dreg = RA; | |
5154 | /* Fall through. */ | |
5155 | case M_JAL_2: | |
5156 | if (mips_pic == NO_PIC | |
5157 | || mips_pic == EMBEDDED_PIC) | |
5158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5159 | "d,s", dreg, sreg); | |
5160 | else if (mips_pic == SVR4_PIC) | |
5161 | { | |
5162 | if (sreg != PIC_CALL_REG) | |
5163 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5164 | |
252b5132 RH |
5165 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5166 | "d,s", dreg, sreg); | |
6478892d | 5167 | if (! HAVE_NEWABI) |
252b5132 | 5168 | { |
6478892d TS |
5169 | if (mips_cprestore_offset < 0) |
5170 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5171 | else | |
5172 | { | |
7a621144 DJ |
5173 | if (! mips_frame_reg_valid) |
5174 | { | |
5175 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5176 | /* Quiet this warning. */ | |
5177 | mips_frame_reg_valid = 1; | |
5178 | } | |
5179 | if (! mips_cprestore_valid) | |
5180 | { | |
5181 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5182 | /* Quiet this warning. */ | |
5183 | mips_cprestore_valid = 1; | |
5184 | } | |
6478892d TS |
5185 | expr1.X_add_number = mips_cprestore_offset; |
5186 | macro_build ((char *) NULL, &icnt, &expr1, | |
5187 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
5188 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
5189 | } | |
252b5132 RH |
5190 | } |
5191 | } | |
5192 | else | |
5193 | abort (); | |
5194 | ||
5195 | return; | |
5196 | ||
5197 | case M_JAL_A: | |
5198 | if (mips_pic == NO_PIC) | |
5199 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5200 | else if (mips_pic == SVR4_PIC) | |
5201 | { | |
5202 | /* If this is a reference to an external symbol, and we are | |
5203 | using a small GOT, we want | |
5204 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5205 | nop | |
5206 | jalr $25 | |
5207 | nop | |
5208 | lw $gp,cprestore($sp) | |
5209 | The cprestore value is set using the .cprestore | |
5210 | pseudo-op. If we are using a big GOT, we want | |
5211 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5212 | addu $25,$25,$gp | |
5213 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5214 | nop | |
5215 | jalr $25 | |
5216 | nop | |
5217 | lw $gp,cprestore($sp) | |
5218 | If the symbol is not external, we want | |
5219 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5220 | nop | |
5221 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
5222 | jalr $25 | |
5223 | nop | |
5224 | lw $gp,cprestore($sp) */ | |
5225 | frag_grow (40); | |
5226 | if (! mips_big_got) | |
5227 | { | |
5228 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5229 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5230 | "t,o(b)", PIC_CALL_REG, |
5231 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
5232 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5233 | "nop", ""); | |
5234 | p = frag_var (rs_machine_dependent, 4, 0, | |
5235 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
c4e7957c | 5236 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5237 | } |
5238 | else | |
5239 | { | |
5240 | int gpdel; | |
5241 | ||
5242 | if (reg_needs_delay (GP)) | |
5243 | gpdel = 4; | |
5244 | else | |
5245 | gpdel = 0; | |
5246 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5247 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
5248 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5249 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5250 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
5251 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5252 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5253 | "t,o(b)", PIC_CALL_REG, |
5254 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5255 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5256 | "nop", ""); | |
5257 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5258 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
5259 | 0, 0), | |
c4e7957c | 5260 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5261 | if (gpdel > 0) |
5262 | { | |
5263 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5264 | p += 4; | |
5265 | } | |
5266 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5267 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5268 | "t,o(b)", PIC_CALL_REG, |
5269 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
5270 | p += 4; | |
5271 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5272 | p += 4; | |
bdaaa2e1 | 5273 | } |
252b5132 | 5274 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5275 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5276 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
5277 | (int) BFD_RELOC_LO16); | |
5278 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5279 | "jalr", "s", PIC_CALL_REG); | |
6478892d | 5280 | if (! HAVE_NEWABI) |
252b5132 | 5281 | { |
6478892d TS |
5282 | if (mips_cprestore_offset < 0) |
5283 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5284 | else | |
5285 | { | |
7a621144 DJ |
5286 | if (! mips_frame_reg_valid) |
5287 | { | |
5288 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5289 | /* Quiet this warning. */ | |
5290 | mips_frame_reg_valid = 1; | |
5291 | } | |
5292 | if (! mips_cprestore_valid) | |
5293 | { | |
5294 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5295 | /* Quiet this warning. */ | |
5296 | mips_cprestore_valid = 1; | |
5297 | } | |
6478892d TS |
5298 | if (mips_opts.noreorder) |
5299 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5300 | "nop", ""); |
6478892d TS |
5301 | expr1.X_add_number = mips_cprestore_offset; |
5302 | macro_build ((char *) NULL, &icnt, &expr1, | |
5303 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
5304 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
5305 | } | |
252b5132 RH |
5306 | } |
5307 | } | |
5308 | else if (mips_pic == EMBEDDED_PIC) | |
5309 | { | |
5310 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5311 | /* The linker may expand the call to a longer sequence which | |
5312 | uses $at, so we must break rather than return. */ | |
5313 | break; | |
5314 | } | |
5315 | else | |
5316 | abort (); | |
5317 | ||
5318 | return; | |
5319 | ||
5320 | case M_LB_AB: | |
5321 | s = "lb"; | |
5322 | goto ld; | |
5323 | case M_LBU_AB: | |
5324 | s = "lbu"; | |
5325 | goto ld; | |
5326 | case M_LH_AB: | |
5327 | s = "lh"; | |
5328 | goto ld; | |
5329 | case M_LHU_AB: | |
5330 | s = "lhu"; | |
5331 | goto ld; | |
5332 | case M_LW_AB: | |
5333 | s = "lw"; | |
5334 | goto ld; | |
5335 | case M_LWC0_AB: | |
5336 | s = "lwc0"; | |
bdaaa2e1 | 5337 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5338 | coproc = 1; |
5339 | goto ld; | |
5340 | case M_LWC1_AB: | |
5341 | s = "lwc1"; | |
bdaaa2e1 | 5342 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5343 | coproc = 1; |
5344 | goto ld; | |
5345 | case M_LWC2_AB: | |
5346 | s = "lwc2"; | |
bdaaa2e1 | 5347 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5348 | coproc = 1; |
5349 | goto ld; | |
5350 | case M_LWC3_AB: | |
5351 | s = "lwc3"; | |
bdaaa2e1 | 5352 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5353 | coproc = 1; |
5354 | goto ld; | |
5355 | case M_LWL_AB: | |
5356 | s = "lwl"; | |
5357 | lr = 1; | |
5358 | goto ld; | |
5359 | case M_LWR_AB: | |
5360 | s = "lwr"; | |
5361 | lr = 1; | |
5362 | goto ld; | |
5363 | case M_LDC1_AB: | |
ec68c924 | 5364 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5365 | { |
5366 | as_bad (_("opcode not supported on this processor")); | |
5367 | return; | |
5368 | } | |
5369 | s = "ldc1"; | |
bdaaa2e1 | 5370 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5371 | coproc = 1; |
5372 | goto ld; | |
5373 | case M_LDC2_AB: | |
5374 | s = "ldc2"; | |
bdaaa2e1 | 5375 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5376 | coproc = 1; |
5377 | goto ld; | |
5378 | case M_LDC3_AB: | |
5379 | s = "ldc3"; | |
bdaaa2e1 | 5380 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5381 | coproc = 1; |
5382 | goto ld; | |
5383 | case M_LDL_AB: | |
5384 | s = "ldl"; | |
5385 | lr = 1; | |
5386 | goto ld; | |
5387 | case M_LDR_AB: | |
5388 | s = "ldr"; | |
5389 | lr = 1; | |
5390 | goto ld; | |
5391 | case M_LL_AB: | |
5392 | s = "ll"; | |
5393 | goto ld; | |
5394 | case M_LLD_AB: | |
5395 | s = "lld"; | |
5396 | goto ld; | |
5397 | case M_LWU_AB: | |
5398 | s = "lwu"; | |
5399 | ld: | |
5400 | if (breg == treg || coproc || lr) | |
5401 | { | |
5402 | tempreg = AT; | |
5403 | used_at = 1; | |
5404 | } | |
5405 | else | |
5406 | { | |
5407 | tempreg = treg; | |
5408 | used_at = 0; | |
5409 | } | |
5410 | goto ld_st; | |
5411 | case M_SB_AB: | |
5412 | s = "sb"; | |
5413 | goto st; | |
5414 | case M_SH_AB: | |
5415 | s = "sh"; | |
5416 | goto st; | |
5417 | case M_SW_AB: | |
5418 | s = "sw"; | |
5419 | goto st; | |
5420 | case M_SWC0_AB: | |
5421 | s = "swc0"; | |
bdaaa2e1 | 5422 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5423 | coproc = 1; |
5424 | goto st; | |
5425 | case M_SWC1_AB: | |
5426 | s = "swc1"; | |
bdaaa2e1 | 5427 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5428 | coproc = 1; |
5429 | goto st; | |
5430 | case M_SWC2_AB: | |
5431 | s = "swc2"; | |
bdaaa2e1 | 5432 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5433 | coproc = 1; |
5434 | goto st; | |
5435 | case M_SWC3_AB: | |
5436 | s = "swc3"; | |
bdaaa2e1 | 5437 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5438 | coproc = 1; |
5439 | goto st; | |
5440 | case M_SWL_AB: | |
5441 | s = "swl"; | |
5442 | goto st; | |
5443 | case M_SWR_AB: | |
5444 | s = "swr"; | |
5445 | goto st; | |
5446 | case M_SC_AB: | |
5447 | s = "sc"; | |
5448 | goto st; | |
5449 | case M_SCD_AB: | |
5450 | s = "scd"; | |
5451 | goto st; | |
5452 | case M_SDC1_AB: | |
ec68c924 | 5453 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5454 | { |
5455 | as_bad (_("opcode not supported on this processor")); | |
5456 | return; | |
5457 | } | |
5458 | s = "sdc1"; | |
5459 | coproc = 1; | |
bdaaa2e1 | 5460 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5461 | goto st; |
5462 | case M_SDC2_AB: | |
5463 | s = "sdc2"; | |
bdaaa2e1 | 5464 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5465 | coproc = 1; |
5466 | goto st; | |
5467 | case M_SDC3_AB: | |
5468 | s = "sdc3"; | |
bdaaa2e1 | 5469 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5470 | coproc = 1; |
5471 | goto st; | |
5472 | case M_SDL_AB: | |
5473 | s = "sdl"; | |
5474 | goto st; | |
5475 | case M_SDR_AB: | |
5476 | s = "sdr"; | |
5477 | st: | |
5478 | tempreg = AT; | |
5479 | used_at = 1; | |
5480 | ld_st: | |
bdaaa2e1 | 5481 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5482 | if (mask == M_LWC1_AB |
5483 | || mask == M_SWC1_AB | |
5484 | || mask == M_LDC1_AB | |
5485 | || mask == M_SDC1_AB | |
5486 | || mask == M_L_DAB | |
5487 | || mask == M_S_DAB) | |
5488 | fmt = "T,o(b)"; | |
5489 | else if (coproc) | |
5490 | fmt = "E,o(b)"; | |
5491 | else | |
5492 | fmt = "t,o(b)"; | |
5493 | ||
afdbd6d0 CD |
5494 | /* For embedded PIC, we allow loads where the offset is calculated |
5495 | by subtracting a symbol in the current segment from an unknown | |
5496 | symbol, relative to a base register, e.g.: | |
5497 | <op> $treg, <sym>-<localsym>($breg) | |
5498 | This is used by the compiler for switch statements. */ | |
76b3015f | 5499 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5500 | && offset_expr.X_op == O_subtract |
5501 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5502 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5503 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5504 | && (S_GET_SEGMENT | |
5505 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5506 | ->X_add_symbol) | |
5507 | == now_seg))) | |
5508 | && breg != 0 | |
5509 | && (offset_expr.X_add_number == 0 | |
5510 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5511 | { | |
5512 | /* For this case, we output the instructions: | |
5513 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5514 | addiu $tempreg,$tempreg,$breg | |
5515 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5516 | If the relocation would fit entirely in 16 bits, it would be | |
5517 | nice to emit: | |
5518 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5519 | instead, but that seems quite difficult. */ | |
5520 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5521 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5522 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5523 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5524 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5525 | ? "addu" : "daddu"), | |
5526 | "d,v,t", tempreg, tempreg, breg); | |
5527 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5528 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5529 | if (! used_at) | |
5530 | return; | |
5531 | break; | |
5532 | } | |
5533 | ||
252b5132 RH |
5534 | if (offset_expr.X_op != O_constant |
5535 | && offset_expr.X_op != O_symbol) | |
5536 | { | |
5537 | as_bad (_("expression too complex")); | |
5538 | offset_expr.X_op = O_constant; | |
5539 | } | |
5540 | ||
5541 | /* A constant expression in PIC code can be handled just as it | |
5542 | is in non PIC code. */ | |
5543 | if (mips_pic == NO_PIC | |
5544 | || offset_expr.X_op == O_constant) | |
5545 | { | |
5546 | /* If this is a reference to a GP relative symbol, and there | |
5547 | is no base register, we want | |
cdf6fd85 | 5548 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5549 | Otherwise, if there is no base register, we want |
5550 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5551 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5552 | If we have a constant, we need two instructions anyhow, | |
5553 | so we always use the latter form. | |
5554 | ||
5555 | If we have a base register, and this is a reference to a | |
5556 | GP relative symbol, we want | |
5557 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5558 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5559 | Otherwise we want |
5560 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5561 | addu $tempreg,$tempreg,$breg | |
5562 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5563 | With a constant we always use the latter case. |
76b3015f | 5564 | |
d6bc6245 TS |
5565 | With 64bit address space and no base register and $at usable, |
5566 | we want | |
5567 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5568 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5569 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5570 | dsll32 $tempreg,0 | |
5571 | daddu $tempreg,$at | |
5572 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5573 | If we have a base register, we want | |
5574 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5575 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5576 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5577 | daddu $at,$breg | |
5578 | dsll32 $tempreg,0 | |
5579 | daddu $tempreg,$at | |
5580 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5581 | ||
5582 | Without $at we can't generate the optimal path for superscalar | |
5583 | processors here since this would require two temporary registers. | |
5584 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5585 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5586 | dsll $tempreg,16 | |
5587 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5588 | dsll $tempreg,16 | |
5589 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5590 | If we have a base register, we want | |
5591 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5592 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5593 | dsll $tempreg,16 | |
5594 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5595 | dsll $tempreg,16 | |
5596 | daddu $tempreg,$tempreg,$breg | |
5597 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5598 | |
5599 | If we have 64-bit addresses, as an optimization, for | |
5600 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5601 | addresses) we fall back to the 32-bit address generation | |
5602 | mechanism since it is more efficient. This code should | |
5603 | probably attempt to generate 64-bit constants more | |
5604 | efficiently in general. | |
d6bc6245 | 5605 | */ |
6373ee54 CD |
5606 | if (HAVE_64BIT_ADDRESSES |
5607 | && !(offset_expr.X_op == O_constant | |
5608 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number))) | |
d6bc6245 TS |
5609 | { |
5610 | p = NULL; | |
5611 | ||
5612 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5613 | hold the data for such large chunks. */ | |
5614 | ||
5615 | if (used_at == 0) | |
5616 | { | |
5617 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5618 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5619 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5620 | AT, (int) BFD_RELOC_HI16_S); | |
5621 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5622 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5623 | if (breg != 0) | |
2396cfb9 TS |
5624 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5625 | "d,v,t", AT, AT, breg); | |
5626 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5627 | "d,w,<", tempreg, tempreg, 0); | |
5628 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5629 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5630 | macro_build (p, &icnt, &offset_expr, s, |
5631 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5632 | used_at = 1; | |
5633 | } | |
5634 | else | |
5635 | { | |
5636 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5637 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5638 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5639 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5640 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5641 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5642 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5643 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5644 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5645 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5646 | if (breg != 0) |
2396cfb9 TS |
5647 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5648 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5649 | macro_build (p, &icnt, &offset_expr, s, |
5650 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5651 | } | |
5652 | ||
5653 | return; | |
5654 | } | |
76b3015f | 5655 | |
252b5132 RH |
5656 | if (breg == 0) |
5657 | { | |
e7d556df | 5658 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5659 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5660 | p = NULL; | |
5661 | else | |
5662 | { | |
5663 | frag_grow (20); | |
5664 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5665 | treg, (int) BFD_RELOC_GPREL16, GP); |
252b5132 RH |
5666 | p = frag_var (rs_machine_dependent, 8, 0, |
5667 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5668 | (mips_opts.warn_about_macros | |
5669 | || (used_at | |
5670 | && mips_opts.noat))), | |
956cd1d6 | 5671 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5672 | used_at = 0; |
5673 | } | |
5674 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5675 | if (p != NULL) | |
5676 | p += 4; | |
5677 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5678 | (int) BFD_RELOC_LO16, tempreg); | |
5679 | } | |
5680 | else | |
5681 | { | |
e7d556df | 5682 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5683 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5684 | p = NULL; | |
5685 | else | |
5686 | { | |
5687 | frag_grow (28); | |
5688 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5689 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5690 | "d,v,t", tempreg, breg, GP); |
5691 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5692 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5693 | p = frag_var (rs_machine_dependent, 12, 0, |
5694 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5695 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5696 | } |
5697 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5698 | if (p != NULL) | |
5699 | p += 4; | |
5700 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5701 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5702 | "d,v,t", tempreg, tempreg, breg); |
5703 | if (p != NULL) | |
5704 | p += 4; | |
5705 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5706 | (int) BFD_RELOC_LO16, tempreg); | |
5707 | } | |
5708 | } | |
5709 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5710 | { | |
5711 | /* If this is a reference to an external symbol, we want | |
5712 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5713 | nop | |
5714 | <op> $treg,0($tempreg) | |
5715 | Otherwise we want | |
5716 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5717 | nop | |
5718 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5719 | <op> $treg,0($tempreg) | |
5720 | If there is a base register, we add it to $tempreg before | |
5721 | the <op>. If there is a constant, we stick it in the | |
5722 | <op> instruction. We don't handle constants larger than | |
5723 | 16 bits, because we have no way to load the upper 16 bits | |
5724 | (actually, we could handle them for the subset of cases | |
5725 | in which we are not using $at). */ | |
5726 | assert (offset_expr.X_op == O_symbol); | |
5727 | expr1.X_add_number = offset_expr.X_add_number; | |
5728 | offset_expr.X_add_number = 0; | |
5729 | if (expr1.X_add_number < -0x8000 | |
5730 | || expr1.X_add_number >= 0x8000) | |
5731 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5732 | frag_grow (20); | |
5733 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5734 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5735 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5736 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5737 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5738 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5739 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5740 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5741 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5742 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5743 | if (breg != 0) | |
5744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5745 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5746 | "d,v,t", tempreg, tempreg, breg); |
5747 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5748 | (int) BFD_RELOC_LO16, tempreg); | |
5749 | } | |
5750 | else if (mips_pic == SVR4_PIC) | |
5751 | { | |
5752 | int gpdel; | |
5753 | ||
5754 | /* If this is a reference to an external symbol, we want | |
5755 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5756 | addu $tempreg,$tempreg,$gp | |
5757 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5758 | <op> $treg,0($tempreg) | |
5759 | Otherwise we want | |
5760 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5761 | nop | |
5762 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5763 | <op> $treg,0($tempreg) | |
5764 | If there is a base register, we add it to $tempreg before | |
5765 | the <op>. If there is a constant, we stick it in the | |
5766 | <op> instruction. We don't handle constants larger than | |
5767 | 16 bits, because we have no way to load the upper 16 bits | |
5768 | (actually, we could handle them for the subset of cases | |
5769 | in which we are not using $at). */ | |
5770 | assert (offset_expr.X_op == O_symbol); | |
5771 | expr1.X_add_number = offset_expr.X_add_number; | |
5772 | offset_expr.X_add_number = 0; | |
5773 | if (expr1.X_add_number < -0x8000 | |
5774 | || expr1.X_add_number >= 0x8000) | |
5775 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5776 | if (reg_needs_delay (GP)) | |
5777 | gpdel = 4; | |
5778 | else | |
5779 | gpdel = 0; | |
5780 | frag_grow (36); | |
5781 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5782 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5783 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5784 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5785 | "d,v,t", tempreg, tempreg, GP); |
5786 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5787 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5788 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5789 | tempreg); | |
5790 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5791 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 5792 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5793 | if (gpdel > 0) |
5794 | { | |
5795 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5796 | p += 4; | |
5797 | } | |
5798 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5799 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5800 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5801 | p += 4; | |
5802 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5803 | p += 4; | |
5804 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5805 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5806 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5807 | if (breg != 0) | |
5808 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5809 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5810 | "d,v,t", tempreg, tempreg, breg); |
5811 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5812 | (int) BFD_RELOC_LO16, tempreg); | |
5813 | } | |
5814 | else if (mips_pic == EMBEDDED_PIC) | |
5815 | { | |
5816 | /* If there is no base register, we want | |
cdf6fd85 | 5817 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5818 | If there is a base register, we want |
5819 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5820 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5821 | */ |
5822 | assert (offset_expr.X_op == O_symbol); | |
5823 | if (breg == 0) | |
5824 | { | |
5825 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5826 | treg, (int) BFD_RELOC_GPREL16, GP); |
252b5132 RH |
5827 | used_at = 0; |
5828 | } | |
5829 | else | |
5830 | { | |
5831 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5832 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5833 | "d,v,t", tempreg, breg, GP); |
5834 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5835 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5836 | } |
5837 | } | |
5838 | else | |
5839 | abort (); | |
5840 | ||
5841 | if (! used_at) | |
5842 | return; | |
5843 | ||
5844 | break; | |
5845 | ||
5846 | case M_LI: | |
5847 | case M_LI_S: | |
5848 | load_register (&icnt, treg, &imm_expr, 0); | |
5849 | return; | |
5850 | ||
5851 | case M_DLI: | |
5852 | load_register (&icnt, treg, &imm_expr, 1); | |
5853 | return; | |
5854 | ||
5855 | case M_LI_SS: | |
5856 | if (imm_expr.X_op == O_constant) | |
5857 | { | |
5858 | load_register (&icnt, AT, &imm_expr, 0); | |
5859 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5860 | "mtc1", "t,G", AT, treg); | |
5861 | break; | |
5862 | } | |
5863 | else | |
5864 | { | |
5865 | assert (offset_expr.X_op == O_symbol | |
5866 | && strcmp (segment_name (S_GET_SEGMENT | |
5867 | (offset_expr.X_add_symbol)), | |
5868 | ".lit4") == 0 | |
5869 | && offset_expr.X_add_number == 0); | |
5870 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5871 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5872 | return; | |
5873 | } | |
5874 | ||
5875 | case M_LI_D: | |
ca4e0257 RS |
5876 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
5877 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
5878 | order 32 bits of the value and the low order 32 bits are either | |
5879 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
5880 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5881 | { | |
ca4e0257 | 5882 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5883 | load_register (&icnt, treg, &imm_expr, 1); |
5884 | else | |
5885 | { | |
5886 | int hreg, lreg; | |
5887 | ||
5888 | if (target_big_endian) | |
5889 | { | |
5890 | hreg = treg; | |
5891 | lreg = treg + 1; | |
5892 | } | |
5893 | else | |
5894 | { | |
5895 | hreg = treg + 1; | |
5896 | lreg = treg; | |
5897 | } | |
5898 | ||
5899 | if (hreg <= 31) | |
5900 | load_register (&icnt, hreg, &imm_expr, 0); | |
5901 | if (lreg <= 31) | |
5902 | { | |
5903 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 5904 | move_register (&icnt, lreg, 0); |
252b5132 RH |
5905 | else |
5906 | { | |
5907 | assert (offset_expr.X_op == O_constant); | |
5908 | load_register (&icnt, lreg, &offset_expr, 0); | |
5909 | } | |
5910 | } | |
5911 | } | |
5912 | return; | |
5913 | } | |
5914 | ||
5915 | /* We know that sym is in the .rdata section. First we get the | |
5916 | upper 16 bits of the address. */ | |
5917 | if (mips_pic == NO_PIC) | |
5918 | { | |
956cd1d6 | 5919 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
5920 | } |
5921 | else if (mips_pic == SVR4_PIC) | |
5922 | { | |
5923 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5924 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5925 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5926 | } | |
5927 | else if (mips_pic == EMBEDDED_PIC) | |
5928 | { | |
5929 | /* For embedded PIC we pick up the entire address off $gp in | |
5930 | a single instruction. */ | |
5931 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5932 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
cdf6fd85 | 5933 | "t,r,j", AT, GP, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
5934 | offset_expr.X_op = O_constant; |
5935 | offset_expr.X_add_number = 0; | |
5936 | } | |
5937 | else | |
5938 | abort (); | |
bdaaa2e1 | 5939 | |
252b5132 | 5940 | /* Now we load the register(s). */ |
ca4e0257 | 5941 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5942 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5943 | treg, (int) BFD_RELOC_LO16, AT); | |
5944 | else | |
5945 | { | |
5946 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5947 | treg, (int) BFD_RELOC_LO16, AT); | |
5948 | if (treg != 31) | |
5949 | { | |
5950 | /* FIXME: How in the world do we deal with the possible | |
5951 | overflow here? */ | |
5952 | offset_expr.X_add_number += 4; | |
5953 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5954 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5955 | } | |
5956 | } | |
5957 | ||
5958 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5959 | does not become a variant frag. */ | |
5960 | frag_wane (frag_now); | |
5961 | frag_new (0); | |
5962 | ||
5963 | break; | |
5964 | ||
5965 | case M_LI_DD: | |
ca4e0257 RS |
5966 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
5967 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
5968 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
5969 | the value and the low order 32 bits are either zero or in | |
5970 | OFFSET_EXPR. */ | |
252b5132 RH |
5971 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5972 | { | |
ca4e0257 RS |
5973 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
5974 | if (HAVE_64BIT_FPRS) | |
5975 | { | |
5976 | assert (HAVE_64BIT_GPRS); | |
5977 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5978 | "dmtc1", "t,S", AT, treg); | |
5979 | } | |
252b5132 RH |
5980 | else |
5981 | { | |
5982 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5983 | "mtc1", "t,G", AT, treg + 1); | |
5984 | if (offset_expr.X_op == O_absent) | |
5985 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5986 | "mtc1", "t,G", 0, treg); | |
5987 | else | |
5988 | { | |
5989 | assert (offset_expr.X_op == O_constant); | |
5990 | load_register (&icnt, AT, &offset_expr, 0); | |
5991 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5992 | "mtc1", "t,G", AT, treg); | |
5993 | } | |
5994 | } | |
5995 | break; | |
5996 | } | |
5997 | ||
5998 | assert (offset_expr.X_op == O_symbol | |
5999 | && offset_expr.X_add_number == 0); | |
6000 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6001 | if (strcmp (s, ".lit8") == 0) | |
6002 | { | |
e7af610e | 6003 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6004 | { |
6005 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6006 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
6007 | return; | |
6008 | } | |
6009 | breg = GP; | |
6010 | r = BFD_RELOC_MIPS_LITERAL; | |
6011 | goto dob; | |
6012 | } | |
6013 | else | |
6014 | { | |
6015 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6016 | if (mips_pic == SVR4_PIC) | |
6017 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6018 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6019 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6020 | else | |
6021 | { | |
6022 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6023 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6024 | } |
bdaaa2e1 | 6025 | |
e7af610e | 6026 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6027 | { |
6028 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6029 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6030 | ||
6031 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6032 | that this does not become a variant frag. */ | |
6033 | frag_wane (frag_now); | |
6034 | frag_new (0); | |
6035 | ||
6036 | break; | |
6037 | } | |
6038 | breg = AT; | |
6039 | r = BFD_RELOC_LO16; | |
6040 | goto dob; | |
6041 | } | |
6042 | ||
6043 | case M_L_DOB: | |
ec68c924 | 6044 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6045 | { |
6046 | as_bad (_("opcode not supported on this processor")); | |
6047 | return; | |
6048 | } | |
6049 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6050 | to adjust when loading from memory. */ | |
6051 | r = BFD_RELOC_LO16; | |
6052 | dob: | |
e7af610e | 6053 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6054 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6055 | target_big_endian ? treg + 1 : treg, | |
6056 | (int) r, breg); | |
6057 | /* FIXME: A possible overflow which I don't know how to deal | |
6058 | with. */ | |
6059 | offset_expr.X_add_number += 4; | |
6060 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6061 | target_big_endian ? treg : treg + 1, | |
6062 | (int) r, breg); | |
6063 | ||
6064 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6065 | does not become a variant frag. */ | |
6066 | frag_wane (frag_now); | |
6067 | frag_new (0); | |
6068 | ||
6069 | if (breg != AT) | |
6070 | return; | |
6071 | break; | |
6072 | ||
6073 | case M_L_DAB: | |
6074 | /* | |
6075 | * The MIPS assembler seems to check for X_add_number not | |
6076 | * being double aligned and generating: | |
6077 | * lui at,%hi(foo+1) | |
6078 | * addu at,at,v1 | |
6079 | * addiu at,at,%lo(foo+1) | |
6080 | * lwc1 f2,0(at) | |
6081 | * lwc1 f3,4(at) | |
6082 | * But, the resulting address is the same after relocation so why | |
6083 | * generate the extra instruction? | |
6084 | */ | |
ec68c924 | 6085 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6086 | { |
6087 | as_bad (_("opcode not supported on this processor")); | |
6088 | return; | |
6089 | } | |
bdaaa2e1 | 6090 | /* Itbl support may require additional care here. */ |
252b5132 | 6091 | coproc = 1; |
e7af610e | 6092 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6093 | { |
6094 | s = "ldc1"; | |
6095 | goto ld; | |
6096 | } | |
6097 | ||
6098 | s = "lwc1"; | |
6099 | fmt = "T,o(b)"; | |
6100 | goto ldd_std; | |
6101 | ||
6102 | case M_S_DAB: | |
ec68c924 | 6103 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6104 | { |
6105 | as_bad (_("opcode not supported on this processor")); | |
6106 | return; | |
6107 | } | |
6108 | ||
e7af610e | 6109 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6110 | { |
6111 | s = "sdc1"; | |
6112 | goto st; | |
6113 | } | |
6114 | ||
6115 | s = "swc1"; | |
6116 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6117 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6118 | coproc = 1; |
6119 | goto ldd_std; | |
6120 | ||
6121 | case M_LD_AB: | |
ca4e0257 | 6122 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6123 | { |
6124 | s = "ld"; | |
6125 | goto ld; | |
6126 | } | |
6127 | ||
6128 | s = "lw"; | |
6129 | fmt = "t,o(b)"; | |
6130 | goto ldd_std; | |
6131 | ||
6132 | case M_SD_AB: | |
ca4e0257 | 6133 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6134 | { |
6135 | s = "sd"; | |
6136 | goto st; | |
6137 | } | |
6138 | ||
6139 | s = "sw"; | |
6140 | fmt = "t,o(b)"; | |
6141 | ||
6142 | ldd_std: | |
afdbd6d0 CD |
6143 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6144 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6145 | This is not currently done by the compiler, and assembly coders | |
6146 | writing embedded-pic code can cope. */ | |
6147 | ||
252b5132 RH |
6148 | if (offset_expr.X_op != O_symbol |
6149 | && offset_expr.X_op != O_constant) | |
6150 | { | |
6151 | as_bad (_("expression too complex")); | |
6152 | offset_expr.X_op = O_constant; | |
6153 | } | |
6154 | ||
6155 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6156 | to adjust when loading from memory. We set coproc if we must | |
6157 | load $fn+1 first. */ | |
bdaaa2e1 | 6158 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6159 | if (! target_big_endian) |
6160 | coproc = 0; | |
6161 | ||
6162 | if (mips_pic == NO_PIC | |
6163 | || offset_expr.X_op == O_constant) | |
6164 | { | |
6165 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6166 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6167 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6168 | If we have a base register, we use this |
6169 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6170 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6171 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6172 | If this is not a GP relative symbol, we want |
6173 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6174 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6175 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6176 | If there is a base register, we add it to $at after the | |
6177 | lui instruction. If there is a constant, we always use | |
6178 | the last case. */ | |
e7d556df | 6179 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6180 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6181 | { | |
6182 | p = NULL; | |
6183 | used_at = 1; | |
6184 | } | |
6185 | else | |
6186 | { | |
6187 | int off; | |
6188 | ||
6189 | if (breg == 0) | |
6190 | { | |
6191 | frag_grow (28); | |
6192 | tempreg = GP; | |
6193 | off = 0; | |
6194 | used_at = 0; | |
6195 | } | |
6196 | else | |
6197 | { | |
6198 | frag_grow (36); | |
6199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6200 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6201 | "d,v,t", AT, breg, GP); |
6202 | tempreg = AT; | |
6203 | off = 4; | |
6204 | used_at = 1; | |
6205 | } | |
6206 | ||
beae10d5 | 6207 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6208 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6209 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6210 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6211 | offset_expr.X_add_number += 4; |
6212 | ||
6213 | /* Set mips_optimize to 2 to avoid inserting an | |
6214 | undesired nop. */ | |
6215 | hold_mips_optimize = mips_optimize; | |
6216 | mips_optimize = 2; | |
beae10d5 | 6217 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6218 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6219 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6220 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6221 | mips_optimize = hold_mips_optimize; |
6222 | ||
6223 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6224 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6225 | used_at && mips_opts.noat), | |
956cd1d6 | 6226 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6227 | |
6228 | /* We just generated two relocs. When tc_gen_reloc | |
6229 | handles this case, it will skip the first reloc and | |
6230 | handle the second. The second reloc already has an | |
6231 | extra addend of 4, which we added above. We must | |
6232 | subtract it out, and then subtract another 4 to make | |
6233 | the first reloc come out right. The second reloc | |
6234 | will come out right because we are going to add 4 to | |
6235 | offset_expr when we build its instruction below. | |
6236 | ||
6237 | If we have a symbol, then we don't want to include | |
6238 | the offset, because it will wind up being included | |
6239 | when we generate the reloc. */ | |
6240 | ||
6241 | if (offset_expr.X_op == O_constant) | |
6242 | offset_expr.X_add_number -= 8; | |
6243 | else | |
6244 | { | |
6245 | offset_expr.X_add_number = -4; | |
6246 | offset_expr.X_op = O_constant; | |
6247 | } | |
6248 | } | |
6249 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6250 | if (p != NULL) | |
6251 | p += 4; | |
6252 | if (breg != 0) | |
6253 | { | |
6254 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6255 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6256 | "d,v,t", AT, breg, AT); |
6257 | if (p != NULL) | |
6258 | p += 4; | |
6259 | } | |
beae10d5 | 6260 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6261 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6262 | coproc ? treg + 1 : treg, | |
6263 | (int) BFD_RELOC_LO16, AT); | |
6264 | if (p != NULL) | |
6265 | p += 4; | |
6266 | /* FIXME: How do we handle overflow here? */ | |
6267 | offset_expr.X_add_number += 4; | |
beae10d5 | 6268 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6269 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6270 | coproc ? treg : treg + 1, | |
6271 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6272 | } |
252b5132 RH |
6273 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6274 | { | |
6275 | int off; | |
6276 | ||
6277 | /* If this is a reference to an external symbol, we want | |
6278 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6279 | nop | |
6280 | <op> $treg,0($at) | |
6281 | <op> $treg+1,4($at) | |
6282 | Otherwise we want | |
6283 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6284 | nop | |
6285 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6286 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6287 | If there is a base register we add it to $at before the | |
6288 | lwc1 instructions. If there is a constant we include it | |
6289 | in the lwc1 instructions. */ | |
6290 | used_at = 1; | |
6291 | expr1.X_add_number = offset_expr.X_add_number; | |
6292 | offset_expr.X_add_number = 0; | |
6293 | if (expr1.X_add_number < -0x8000 | |
6294 | || expr1.X_add_number >= 0x8000 - 4) | |
6295 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6296 | if (breg == 0) | |
6297 | off = 0; | |
6298 | else | |
6299 | off = 4; | |
6300 | frag_grow (24 + off); | |
6301 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6302 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6303 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6304 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6305 | if (breg != 0) | |
6306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6307 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6308 | "d,v,t", AT, breg, AT); |
beae10d5 | 6309 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6310 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6311 | coproc ? treg + 1 : treg, | |
6312 | (int) BFD_RELOC_LO16, AT); | |
6313 | expr1.X_add_number += 4; | |
6314 | ||
6315 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6316 | nop. */ | |
6317 | hold_mips_optimize = mips_optimize; | |
6318 | mips_optimize = 2; | |
beae10d5 | 6319 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6320 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6321 | coproc ? treg : treg + 1, | |
6322 | (int) BFD_RELOC_LO16, AT); | |
6323 | mips_optimize = hold_mips_optimize; | |
6324 | ||
6325 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6326 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6327 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6328 | } |
6329 | else if (mips_pic == SVR4_PIC) | |
6330 | { | |
6331 | int gpdel, off; | |
6332 | ||
6333 | /* If this is a reference to an external symbol, we want | |
6334 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6335 | addu $at,$at,$gp | |
6336 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6337 | nop | |
6338 | <op> $treg,0($at) | |
6339 | <op> $treg+1,4($at) | |
6340 | Otherwise we want | |
6341 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6342 | nop | |
6343 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6344 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6345 | If there is a base register we add it to $at before the | |
6346 | lwc1 instructions. If there is a constant we include it | |
6347 | in the lwc1 instructions. */ | |
6348 | used_at = 1; | |
6349 | expr1.X_add_number = offset_expr.X_add_number; | |
6350 | offset_expr.X_add_number = 0; | |
6351 | if (expr1.X_add_number < -0x8000 | |
6352 | || expr1.X_add_number >= 0x8000 - 4) | |
6353 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6354 | if (reg_needs_delay (GP)) | |
6355 | gpdel = 4; | |
6356 | else | |
6357 | gpdel = 0; | |
6358 | if (breg == 0) | |
6359 | off = 0; | |
6360 | else | |
6361 | off = 4; | |
6362 | frag_grow (56); | |
6363 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6364 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6365 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6366 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6367 | "d,v,t", AT, AT, GP); |
6368 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6369 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6370 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6371 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6372 | if (breg != 0) | |
6373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6374 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6375 | "d,v,t", AT, breg, AT); |
beae10d5 | 6376 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6377 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6378 | coproc ? treg + 1 : treg, | |
6379 | (int) BFD_RELOC_LO16, AT); | |
6380 | expr1.X_add_number += 4; | |
6381 | ||
6382 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6383 | nop. */ | |
6384 | hold_mips_optimize = mips_optimize; | |
6385 | mips_optimize = 2; | |
beae10d5 | 6386 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6387 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6388 | coproc ? treg : treg + 1, | |
6389 | (int) BFD_RELOC_LO16, AT); | |
6390 | mips_optimize = hold_mips_optimize; | |
6391 | expr1.X_add_number -= 4; | |
6392 | ||
6393 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6394 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6395 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6396 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6397 | if (gpdel > 0) |
6398 | { | |
6399 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6400 | p += 4; | |
6401 | } | |
6402 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6403 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6404 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6405 | p += 4; | |
6406 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6407 | p += 4; | |
6408 | if (breg != 0) | |
6409 | { | |
6410 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6411 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6412 | "d,v,t", AT, breg, AT); |
6413 | p += 4; | |
6414 | } | |
beae10d5 | 6415 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6416 | macro_build (p, &icnt, &expr1, s, fmt, |
6417 | coproc ? treg + 1 : treg, | |
6418 | (int) BFD_RELOC_LO16, AT); | |
6419 | p += 4; | |
6420 | expr1.X_add_number += 4; | |
6421 | ||
6422 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6423 | nop. */ | |
6424 | hold_mips_optimize = mips_optimize; | |
6425 | mips_optimize = 2; | |
beae10d5 | 6426 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6427 | macro_build (p, &icnt, &expr1, s, fmt, |
6428 | coproc ? treg : treg + 1, | |
6429 | (int) BFD_RELOC_LO16, AT); | |
6430 | mips_optimize = hold_mips_optimize; | |
6431 | } | |
6432 | else if (mips_pic == EMBEDDED_PIC) | |
6433 | { | |
6434 | /* If there is no base register, we use | |
cdf6fd85 TS |
6435 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6436 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6437 | If we have a base register, we use |
6438 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6439 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6440 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6441 | */ |
6442 | if (breg == 0) | |
6443 | { | |
6444 | tempreg = GP; | |
6445 | used_at = 0; | |
6446 | } | |
6447 | else | |
6448 | { | |
6449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6450 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6451 | "d,v,t", AT, breg, GP); |
6452 | tempreg = AT; | |
6453 | used_at = 1; | |
6454 | } | |
6455 | ||
beae10d5 | 6456 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6457 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6458 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6459 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6460 | offset_expr.X_add_number += 4; |
beae10d5 | 6461 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6462 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6463 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6464 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6465 | } |
6466 | else | |
6467 | abort (); | |
6468 | ||
6469 | if (! used_at) | |
6470 | return; | |
6471 | ||
6472 | break; | |
6473 | ||
6474 | case M_LD_OB: | |
6475 | s = "lw"; | |
6476 | goto sd_ob; | |
6477 | case M_SD_OB: | |
6478 | s = "sw"; | |
6479 | sd_ob: | |
ca4e0257 | 6480 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6481 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6482 | (int) BFD_RELOC_LO16, breg); | |
6483 | offset_expr.X_add_number += 4; | |
6484 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6485 | (int) BFD_RELOC_LO16, breg); | |
6486 | return; | |
6487 | ||
6488 | /* New code added to support COPZ instructions. | |
6489 | This code builds table entries out of the macros in mip_opcodes. | |
6490 | R4000 uses interlocks to handle coproc delays. | |
6491 | Other chips (like the R3000) require nops to be inserted for delays. | |
6492 | ||
f72c8c98 | 6493 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6494 | In order to fill delay slots for non-interlocked chips, |
6495 | we must have a way to specify delays based on the coprocessor. | |
6496 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6497 | What are the side-effects of the cop instruction? | |
6498 | What cache support might we have and what are its effects? | |
6499 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6500 | What registers are read/set/modified? |
252b5132 RH |
6501 | |
6502 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6503 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6504 | |
6505 | case M_COP0: | |
6506 | s = "c0"; | |
6507 | goto copz; | |
6508 | case M_COP1: | |
6509 | s = "c1"; | |
6510 | goto copz; | |
6511 | case M_COP2: | |
6512 | s = "c2"; | |
6513 | goto copz; | |
6514 | case M_COP3: | |
6515 | s = "c3"; | |
6516 | copz: | |
6517 | /* For now we just do C (same as Cz). The parameter will be | |
6518 | stored in insn_opcode by mips_ip. */ | |
6519 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6520 | ip->insn_opcode); | |
6521 | return; | |
6522 | ||
ea1fb5dc RS |
6523 | case M_MOVE: |
6524 | move_register (&icnt, dreg, sreg); | |
6525 | return; | |
6526 | ||
252b5132 RH |
6527 | #ifdef LOSING_COMPILER |
6528 | default: | |
6529 | /* Try and see if this is a new itbl instruction. | |
6530 | This code builds table entries out of the macros in mip_opcodes. | |
6531 | FIXME: For now we just assemble the expression and pass it's | |
6532 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6533 | We may want to have the assembler assemble this value, |
252b5132 RH |
6534 | so that we gain the assembler's knowledge of delay slots, |
6535 | symbols, etc. | |
6536 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6537 | if (itbl_have_entries |
252b5132 | 6538 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6539 | { |
252b5132 RH |
6540 | s = ip->insn_mo->name; |
6541 | s2 = "cop3"; | |
6542 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6543 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6544 | return; | |
beae10d5 | 6545 | } |
252b5132 RH |
6546 | macro2 (ip); |
6547 | return; | |
6548 | } | |
6549 | if (mips_opts.noat) | |
6550 | as_warn (_("Macro used $at after \".set noat\"")); | |
6551 | } | |
bdaaa2e1 | 6552 | |
252b5132 RH |
6553 | static void |
6554 | macro2 (ip) | |
6555 | struct mips_cl_insn *ip; | |
6556 | { | |
6557 | register int treg, sreg, dreg, breg; | |
6558 | int tempreg; | |
6559 | int mask; | |
6560 | int icnt = 0; | |
6561 | int used_at; | |
6562 | expressionS expr1; | |
6563 | const char *s; | |
6564 | const char *s2; | |
6565 | const char *fmt; | |
6566 | int likely = 0; | |
6567 | int dbl = 0; | |
6568 | int coproc = 0; | |
6569 | int lr = 0; | |
6570 | int imm = 0; | |
6571 | int off; | |
6572 | offsetT maxnum; | |
6573 | bfd_reloc_code_real_type r; | |
6574 | char *p; | |
bdaaa2e1 | 6575 | |
252b5132 RH |
6576 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6577 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6578 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6579 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6580 | |
252b5132 RH |
6581 | expr1.X_op = O_constant; |
6582 | expr1.X_op_symbol = NULL; | |
6583 | expr1.X_add_symbol = NULL; | |
6584 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6585 | |
252b5132 RH |
6586 | switch (mask) |
6587 | { | |
6588 | #endif /* LOSING_COMPILER */ | |
6589 | ||
6590 | case M_DMUL: | |
6591 | dbl = 1; | |
6592 | case M_MUL: | |
2396cfb9 TS |
6593 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6594 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6596 | dreg); | |
252b5132 RH |
6597 | return; |
6598 | ||
6599 | case M_DMUL_I: | |
6600 | dbl = 1; | |
6601 | case M_MUL_I: | |
6602 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6603 | not trying to be that fancy. GCC should do this for us | |
6604 | anyway. */ | |
6605 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6606 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6607 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6608 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6609 | dreg); | |
252b5132 RH |
6610 | break; |
6611 | ||
6612 | case M_DMULO_I: | |
6613 | dbl = 1; | |
6614 | case M_MULO_I: | |
6615 | imm = 1; | |
6616 | goto do_mulo; | |
6617 | ||
6618 | case M_DMULO: | |
6619 | dbl = 1; | |
6620 | case M_MULO: | |
6621 | do_mulo: | |
6622 | mips_emit_delays (true); | |
6623 | ++mips_opts.noreorder; | |
6624 | mips_any_noreorder = 1; | |
6625 | if (imm) | |
6626 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6627 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6628 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6629 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6630 | dreg); | |
6631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 6632 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31); |
2396cfb9 TS |
6633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6634 | AT); | |
252b5132 | 6635 | if (mips_trap) |
2396cfb9 TS |
6636 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6637 | dreg, AT); | |
252b5132 RH |
6638 | else |
6639 | { | |
6640 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6641 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6642 | AT); | |
6643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6644 | 0); | |
6645 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6646 | "c", 6); | |
252b5132 RH |
6647 | } |
6648 | --mips_opts.noreorder; | |
2396cfb9 | 6649 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6650 | break; |
6651 | ||
6652 | case M_DMULOU_I: | |
6653 | dbl = 1; | |
6654 | case M_MULOU_I: | |
6655 | imm = 1; | |
6656 | goto do_mulou; | |
6657 | ||
6658 | case M_DMULOU: | |
6659 | dbl = 1; | |
6660 | case M_MULOU: | |
6661 | do_mulou: | |
6662 | mips_emit_delays (true); | |
6663 | ++mips_opts.noreorder; | |
6664 | mips_any_noreorder = 1; | |
6665 | if (imm) | |
6666 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6667 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6668 | dbl ? "dmultu" : "multu", |
6669 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6671 | AT); | |
6672 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6673 | dreg); | |
252b5132 | 6674 | if (mips_trap) |
2396cfb9 TS |
6675 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6676 | AT, 0); | |
252b5132 RH |
6677 | else |
6678 | { | |
6679 | expr1.X_add_number = 8; | |
6680 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6681 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6682 | 0); | |
6683 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6684 | "c", 6); | |
252b5132 RH |
6685 | } |
6686 | --mips_opts.noreorder; | |
6687 | break; | |
6688 | ||
771c7ce4 TS |
6689 | case M_DROL: |
6690 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6691 | "d,v,t", AT, 0, treg); | |
6692 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6693 | "d,t,s", AT, sreg, AT); | |
6694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6695 | "d,t,s", dreg, sreg, treg); | |
6696 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6697 | "d,v,t", dreg, dreg, AT); | |
6698 | break; | |
6699 | ||
252b5132 | 6700 | case M_ROL: |
2396cfb9 TS |
6701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6702 | "d,v,t", AT, 0, treg); | |
6703 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6704 | "d,t,s", AT, sreg, AT); | |
6705 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6706 | "d,t,s", dreg, sreg, treg); | |
6707 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6708 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6709 | break; |
6710 | ||
771c7ce4 TS |
6711 | case M_DROL_I: |
6712 | { | |
6713 | unsigned int rot; | |
6714 | char *l, *r; | |
6715 | ||
6716 | if (imm_expr.X_op != O_constant) | |
6717 | as_bad (_("rotate count too large")); | |
6718 | rot = imm_expr.X_add_number & 0x3f; | |
6719 | if (! rot) | |
6720 | break; | |
6721 | l = (rot < 0x20) ? "dsll" : "dsll32"; | |
6722 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6723 | rot &= 0x1f; | |
6724 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6725 | "d,w,<", AT, sreg, rot); | |
6726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6727 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6728 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6729 | "d,v,t", dreg, dreg, AT); | |
6730 | } | |
6731 | break; | |
6732 | ||
252b5132 | 6733 | case M_ROL_I: |
771c7ce4 TS |
6734 | { |
6735 | unsigned int rot; | |
6736 | ||
6737 | if (imm_expr.X_op != O_constant) | |
6738 | as_bad (_("rotate count too large")); | |
6739 | rot = imm_expr.X_add_number & 0x1f; | |
6740 | if (! rot) | |
6741 | break; | |
6742 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6743 | "d,w,<", AT, sreg, rot); | |
6744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6745 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6746 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6747 | "d,v,t", dreg, dreg, AT); | |
6748 | } | |
6749 | break; | |
6750 | ||
6751 | case M_DROR: | |
6752 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6753 | "d,v,t", AT, 0, treg); | |
6754 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6755 | "d,t,s", AT, sreg, AT); | |
6756 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6757 | "d,t,s", dreg, sreg, treg); | |
6758 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6759 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6760 | break; |
6761 | ||
6762 | case M_ROR: | |
2396cfb9 TS |
6763 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6764 | "d,v,t", AT, 0, treg); | |
6765 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6766 | "d,t,s", AT, sreg, AT); | |
6767 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6768 | "d,t,s", dreg, sreg, treg); | |
6769 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6770 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6771 | break; |
6772 | ||
771c7ce4 TS |
6773 | case M_DROR_I: |
6774 | { | |
6775 | unsigned int rot; | |
6776 | char *l, *r; | |
6777 | ||
6778 | if (imm_expr.X_op != O_constant) | |
6779 | as_bad (_("rotate count too large")); | |
6780 | rot = imm_expr.X_add_number & 0x3f; | |
6781 | if (! rot) | |
6782 | break; | |
6783 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; | |
6784 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6785 | rot &= 0x1f; | |
6786 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6787 | "d,w,<", AT, sreg, rot); | |
6788 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6789 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6791 | "d,v,t", dreg, dreg, AT); | |
6792 | } | |
6793 | break; | |
6794 | ||
252b5132 | 6795 | case M_ROR_I: |
771c7ce4 TS |
6796 | { |
6797 | unsigned int rot; | |
6798 | ||
6799 | if (imm_expr.X_op != O_constant) | |
6800 | as_bad (_("rotate count too large")); | |
6801 | rot = imm_expr.X_add_number & 0x1f; | |
6802 | if (! rot) | |
6803 | break; | |
6804 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6805 | "d,w,<", AT, sreg, rot); | |
6806 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6807 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6808 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6809 | "d,v,t", dreg, dreg, AT); | |
6810 | } | |
252b5132 RH |
6811 | break; |
6812 | ||
6813 | case M_S_DOB: | |
ec68c924 | 6814 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6815 | { |
6816 | as_bad (_("opcode not supported on this processor")); | |
6817 | return; | |
6818 | } | |
e7af610e | 6819 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6820 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6821 | to adjust when storing to memory. */ | |
6822 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6823 | target_big_endian ? treg + 1 : treg, | |
6824 | (int) BFD_RELOC_LO16, breg); | |
6825 | offset_expr.X_add_number += 4; | |
6826 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6827 | target_big_endian ? treg : treg + 1, | |
6828 | (int) BFD_RELOC_LO16, breg); | |
6829 | return; | |
6830 | ||
6831 | case M_SEQ: | |
6832 | if (sreg == 0) | |
6833 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6834 | treg, (int) BFD_RELOC_LO16); | |
6835 | else if (treg == 0) | |
6836 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6837 | sreg, (int) BFD_RELOC_LO16); | |
6838 | else | |
6839 | { | |
2396cfb9 TS |
6840 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6841 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
6842 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6843 | dreg, (int) BFD_RELOC_LO16); | |
6844 | } | |
6845 | return; | |
6846 | ||
6847 | case M_SEQ_I: | |
6848 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6849 | { | |
6850 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6851 | sreg, (int) BFD_RELOC_LO16); | |
6852 | return; | |
6853 | } | |
6854 | if (sreg == 0) | |
6855 | { | |
6856 | as_warn (_("Instruction %s: result is always false"), | |
6857 | ip->insn_mo->name); | |
ea1fb5dc | 6858 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6859 | return; |
6860 | } | |
6861 | if (imm_expr.X_op == O_constant | |
6862 | && imm_expr.X_add_number >= 0 | |
6863 | && imm_expr.X_add_number < 0x10000) | |
6864 | { | |
6865 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6866 | sreg, (int) BFD_RELOC_LO16); | |
6867 | used_at = 0; | |
6868 | } | |
6869 | else if (imm_expr.X_op == O_constant | |
6870 | && imm_expr.X_add_number > -0x8000 | |
6871 | && imm_expr.X_add_number < 0) | |
6872 | { | |
6873 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6874 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6875 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6876 | "t,r,j", dreg, sreg, |
6877 | (int) BFD_RELOC_LO16); | |
6878 | used_at = 0; | |
6879 | } | |
6880 | else | |
6881 | { | |
4d34fb5f | 6882 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6883 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6884 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6885 | used_at = 1; |
6886 | } | |
6887 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6888 | (int) BFD_RELOC_LO16); | |
6889 | if (used_at) | |
6890 | break; | |
6891 | return; | |
6892 | ||
6893 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6894 | s = "slt"; | |
6895 | goto sge; | |
6896 | case M_SGEU: | |
6897 | s = "sltu"; | |
6898 | sge: | |
2396cfb9 TS |
6899 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6900 | dreg, sreg, treg); | |
252b5132 RH |
6901 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6902 | (int) BFD_RELOC_LO16); | |
6903 | return; | |
6904 | ||
6905 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6906 | case M_SGEU_I: | |
6907 | if (imm_expr.X_op == O_constant | |
6908 | && imm_expr.X_add_number >= -0x8000 | |
6909 | && imm_expr.X_add_number < 0x8000) | |
6910 | { | |
6911 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6912 | mask == M_SGE_I ? "slti" : "sltiu", | |
6913 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6914 | used_at = 0; | |
6915 | } | |
6916 | else | |
6917 | { | |
4d34fb5f | 6918 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6919 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6920 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
6921 | AT); | |
252b5132 RH |
6922 | used_at = 1; |
6923 | } | |
6924 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6925 | (int) BFD_RELOC_LO16); | |
6926 | if (used_at) | |
6927 | break; | |
6928 | return; | |
6929 | ||
6930 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6931 | s = "slt"; | |
6932 | goto sgt; | |
6933 | case M_SGTU: | |
6934 | s = "sltu"; | |
6935 | sgt: | |
2396cfb9 TS |
6936 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6937 | dreg, treg, sreg); | |
252b5132 RH |
6938 | return; |
6939 | ||
6940 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6941 | s = "slt"; | |
6942 | goto sgti; | |
6943 | case M_SGTU_I: | |
6944 | s = "sltu"; | |
6945 | sgti: | |
4d34fb5f | 6946 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6947 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6948 | dreg, AT, sreg); | |
252b5132 RH |
6949 | break; |
6950 | ||
2396cfb9 | 6951 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
6952 | s = "slt"; |
6953 | goto sle; | |
6954 | case M_SLEU: | |
6955 | s = "sltu"; | |
6956 | sle: | |
2396cfb9 TS |
6957 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6958 | dreg, treg, sreg); | |
252b5132 RH |
6959 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6960 | (int) BFD_RELOC_LO16); | |
6961 | return; | |
6962 | ||
2396cfb9 | 6963 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
6964 | s = "slt"; |
6965 | goto slei; | |
6966 | case M_SLEU_I: | |
6967 | s = "sltu"; | |
6968 | slei: | |
4d34fb5f | 6969 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6970 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6971 | dreg, AT, sreg); | |
252b5132 RH |
6972 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6973 | (int) BFD_RELOC_LO16); | |
6974 | break; | |
6975 | ||
6976 | case M_SLT_I: | |
6977 | if (imm_expr.X_op == O_constant | |
6978 | && imm_expr.X_add_number >= -0x8000 | |
6979 | && imm_expr.X_add_number < 0x8000) | |
6980 | { | |
6981 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6982 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6983 | return; | |
6984 | } | |
4d34fb5f | 6985 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6986 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
6987 | dreg, sreg, AT); | |
252b5132 RH |
6988 | break; |
6989 | ||
6990 | case M_SLTU_I: | |
6991 | if (imm_expr.X_op == O_constant | |
6992 | && imm_expr.X_add_number >= -0x8000 | |
6993 | && imm_expr.X_add_number < 0x8000) | |
6994 | { | |
6995 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6996 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6997 | return; | |
6998 | } | |
4d34fb5f | 6999 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7001 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7002 | break; |
7003 | ||
7004 | case M_SNE: | |
7005 | if (sreg == 0) | |
2396cfb9 TS |
7006 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7007 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7008 | else if (treg == 0) |
2396cfb9 TS |
7009 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7010 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7011 | else |
7012 | { | |
2396cfb9 TS |
7013 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7014 | "d,v,t", dreg, sreg, treg); | |
7015 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7016 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7017 | } |
7018 | return; | |
7019 | ||
7020 | case M_SNE_I: | |
7021 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7022 | { | |
2396cfb9 TS |
7023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7024 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7025 | return; |
7026 | } | |
7027 | if (sreg == 0) | |
7028 | { | |
7029 | as_warn (_("Instruction %s: result is always true"), | |
7030 | ip->insn_mo->name); | |
7031 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7032 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7033 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7034 | return; | |
7035 | } | |
7036 | if (imm_expr.X_op == O_constant | |
7037 | && imm_expr.X_add_number >= 0 | |
7038 | && imm_expr.X_add_number < 0x10000) | |
7039 | { | |
7040 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7041 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7042 | used_at = 0; | |
7043 | } | |
7044 | else if (imm_expr.X_op == O_constant | |
7045 | && imm_expr.X_add_number > -0x8000 | |
7046 | && imm_expr.X_add_number < 0) | |
7047 | { | |
7048 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7049 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7050 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7051 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7052 | used_at = 0; | |
7053 | } | |
7054 | else | |
7055 | { | |
4d34fb5f | 7056 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7057 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7058 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7059 | used_at = 1; |
7060 | } | |
2396cfb9 TS |
7061 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7062 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7063 | if (used_at) |
7064 | break; | |
7065 | return; | |
7066 | ||
7067 | case M_DSUB_I: | |
7068 | dbl = 1; | |
7069 | case M_SUB_I: | |
7070 | if (imm_expr.X_op == O_constant | |
7071 | && imm_expr.X_add_number > -0x8000 | |
7072 | && imm_expr.X_add_number <= 0x8000) | |
7073 | { | |
7074 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7075 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7076 | dbl ? "daddi" : "addi", | |
7077 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7078 | return; | |
7079 | } | |
7080 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7081 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7082 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7083 | break; |
7084 | ||
7085 | case M_DSUBU_I: | |
7086 | dbl = 1; | |
7087 | case M_SUBU_I: | |
7088 | if (imm_expr.X_op == O_constant | |
7089 | && imm_expr.X_add_number > -0x8000 | |
7090 | && imm_expr.X_add_number <= 0x8000) | |
7091 | { | |
7092 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7093 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7094 | dbl ? "daddiu" : "addiu", | |
7095 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7096 | return; | |
7097 | } | |
7098 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7099 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7100 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7101 | break; |
7102 | ||
7103 | case M_TEQ_I: | |
7104 | s = "teq"; | |
7105 | goto trap; | |
7106 | case M_TGE_I: | |
7107 | s = "tge"; | |
7108 | goto trap; | |
7109 | case M_TGEU_I: | |
7110 | s = "tgeu"; | |
7111 | goto trap; | |
7112 | case M_TLT_I: | |
7113 | s = "tlt"; | |
7114 | goto trap; | |
7115 | case M_TLTU_I: | |
7116 | s = "tltu"; | |
7117 | goto trap; | |
7118 | case M_TNE_I: | |
7119 | s = "tne"; | |
7120 | trap: | |
4d34fb5f | 7121 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7122 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7123 | AT); | |
252b5132 RH |
7124 | break; |
7125 | ||
252b5132 | 7126 | case M_TRUNCWS: |
43841e91 | 7127 | case M_TRUNCWD: |
e7af610e | 7128 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7129 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7130 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7131 | ||
7132 | /* | |
7133 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7134 | * or is there a reason for it? | |
7135 | */ | |
7136 | mips_emit_delays (true); | |
7137 | ++mips_opts.noreorder; | |
7138 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7139 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
7140 | treg, 31); | |
7141 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", | |
7142 | treg, 31); | |
7143 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
252b5132 RH |
7144 | expr1.X_add_number = 3; |
7145 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7146 | (int) BFD_RELOC_LO16); | |
7147 | expr1.X_add_number = 2; | |
7148 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7149 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
7150 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
7151 | AT, 31); | |
7152 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
7153 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7154 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 TS |
7155 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
7156 | treg, 31); | |
7157 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
252b5132 RH |
7158 | --mips_opts.noreorder; |
7159 | break; | |
7160 | ||
7161 | case M_ULH: | |
7162 | s = "lb"; | |
7163 | goto ulh; | |
7164 | case M_ULHU: | |
7165 | s = "lbu"; | |
7166 | ulh: | |
7167 | if (offset_expr.X_add_number >= 0x7fff) | |
7168 | as_bad (_("operand overflow")); | |
7169 | /* avoid load delay */ | |
7170 | if (! target_big_endian) | |
7171 | offset_expr.X_add_number += 1; | |
7172 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7173 | (int) BFD_RELOC_LO16, breg); | |
7174 | if (! target_big_endian) | |
7175 | offset_expr.X_add_number -= 1; | |
7176 | else | |
7177 | offset_expr.X_add_number += 1; | |
7178 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
7179 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7180 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7181 | treg, treg, 8); | |
7182 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7183 | treg, treg, AT); | |
252b5132 RH |
7184 | break; |
7185 | ||
7186 | case M_ULD: | |
7187 | s = "ldl"; | |
7188 | s2 = "ldr"; | |
7189 | off = 7; | |
7190 | goto ulw; | |
7191 | case M_ULW: | |
7192 | s = "lwl"; | |
7193 | s2 = "lwr"; | |
7194 | off = 3; | |
7195 | ulw: | |
7196 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7197 | as_bad (_("operand overflow")); | |
7198 | if (! target_big_endian) | |
7199 | offset_expr.X_add_number += off; | |
7200 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7201 | (int) BFD_RELOC_LO16, breg); | |
7202 | if (! target_big_endian) | |
7203 | offset_expr.X_add_number -= off; | |
7204 | else | |
7205 | offset_expr.X_add_number += off; | |
7206 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7207 | (int) BFD_RELOC_LO16, breg); | |
7208 | return; | |
7209 | ||
7210 | case M_ULD_A: | |
7211 | s = "ldl"; | |
7212 | s2 = "ldr"; | |
7213 | off = 7; | |
7214 | goto ulwa; | |
7215 | case M_ULW_A: | |
7216 | s = "lwl"; | |
7217 | s2 = "lwr"; | |
7218 | off = 3; | |
7219 | ulwa: | |
d6bc6245 TS |
7220 | used_at = 1; |
7221 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7222 | if (breg != 0) |
7223 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7224 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7225 | "d,v,t", AT, AT, breg); |
7226 | if (! target_big_endian) | |
7227 | expr1.X_add_number = off; | |
7228 | else | |
7229 | expr1.X_add_number = 0; | |
7230 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7231 | (int) BFD_RELOC_LO16, AT); | |
7232 | if (! target_big_endian) | |
7233 | expr1.X_add_number = 0; | |
7234 | else | |
7235 | expr1.X_add_number = off; | |
7236 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7237 | (int) BFD_RELOC_LO16, AT); | |
7238 | break; | |
7239 | ||
7240 | case M_ULH_A: | |
7241 | case M_ULHU_A: | |
d6bc6245 TS |
7242 | used_at = 1; |
7243 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7244 | if (breg != 0) |
7245 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7246 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7247 | "d,v,t", AT, AT, breg); |
7248 | if (target_big_endian) | |
7249 | expr1.X_add_number = 0; | |
7250 | macro_build ((char *) NULL, &icnt, &expr1, | |
7251 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7252 | (int) BFD_RELOC_LO16, AT); | |
7253 | if (target_big_endian) | |
7254 | expr1.X_add_number = 1; | |
7255 | else | |
7256 | expr1.X_add_number = 0; | |
7257 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7258 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7259 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7260 | treg, treg, 8); | |
7261 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7262 | treg, treg, AT); | |
252b5132 RH |
7263 | break; |
7264 | ||
7265 | case M_USH: | |
7266 | if (offset_expr.X_add_number >= 0x7fff) | |
7267 | as_bad (_("operand overflow")); | |
7268 | if (target_big_endian) | |
7269 | offset_expr.X_add_number += 1; | |
7270 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
7271 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7272 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7273 | AT, treg, 8); | |
252b5132 RH |
7274 | if (target_big_endian) |
7275 | offset_expr.X_add_number -= 1; | |
7276 | else | |
7277 | offset_expr.X_add_number += 1; | |
7278 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
7279 | (int) BFD_RELOC_LO16, breg); | |
7280 | break; | |
7281 | ||
7282 | case M_USD: | |
7283 | s = "sdl"; | |
7284 | s2 = "sdr"; | |
7285 | off = 7; | |
7286 | goto usw; | |
7287 | case M_USW: | |
7288 | s = "swl"; | |
7289 | s2 = "swr"; | |
7290 | off = 3; | |
7291 | usw: | |
7292 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7293 | as_bad (_("operand overflow")); | |
7294 | if (! target_big_endian) | |
7295 | offset_expr.X_add_number += off; | |
7296 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7297 | (int) BFD_RELOC_LO16, breg); | |
7298 | if (! target_big_endian) | |
7299 | offset_expr.X_add_number -= off; | |
7300 | else | |
7301 | offset_expr.X_add_number += off; | |
7302 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7303 | (int) BFD_RELOC_LO16, breg); | |
7304 | return; | |
7305 | ||
7306 | case M_USD_A: | |
7307 | s = "sdl"; | |
7308 | s2 = "sdr"; | |
7309 | off = 7; | |
7310 | goto uswa; | |
7311 | case M_USW_A: | |
7312 | s = "swl"; | |
7313 | s2 = "swr"; | |
7314 | off = 3; | |
7315 | uswa: | |
d6bc6245 TS |
7316 | used_at = 1; |
7317 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7318 | if (breg != 0) |
7319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7320 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7321 | "d,v,t", AT, AT, breg); |
7322 | if (! target_big_endian) | |
7323 | expr1.X_add_number = off; | |
7324 | else | |
7325 | expr1.X_add_number = 0; | |
7326 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7327 | (int) BFD_RELOC_LO16, AT); | |
7328 | if (! target_big_endian) | |
7329 | expr1.X_add_number = 0; | |
7330 | else | |
7331 | expr1.X_add_number = off; | |
7332 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7333 | (int) BFD_RELOC_LO16, AT); | |
7334 | break; | |
7335 | ||
7336 | case M_USH_A: | |
d6bc6245 TS |
7337 | used_at = 1; |
7338 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7339 | if (breg != 0) |
7340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7341 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7342 | "d,v,t", AT, AT, breg); |
7343 | if (! target_big_endian) | |
7344 | expr1.X_add_number = 0; | |
7345 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7346 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7347 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7348 | treg, treg, 8); | |
252b5132 RH |
7349 | if (! target_big_endian) |
7350 | expr1.X_add_number = 1; | |
7351 | else | |
7352 | expr1.X_add_number = 0; | |
7353 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7354 | (int) BFD_RELOC_LO16, AT); | |
7355 | if (! target_big_endian) | |
7356 | expr1.X_add_number = 0; | |
7357 | else | |
7358 | expr1.X_add_number = 1; | |
7359 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7360 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7361 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7362 | treg, treg, 8); | |
7363 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7364 | treg, treg, AT); | |
252b5132 RH |
7365 | break; |
7366 | ||
7367 | default: | |
7368 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7369 | are added dynamically. */ |
252b5132 RH |
7370 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7371 | break; | |
7372 | } | |
7373 | if (mips_opts.noat) | |
7374 | as_warn (_("Macro used $at after \".set noat\"")); | |
7375 | } | |
7376 | ||
7377 | /* Implement macros in mips16 mode. */ | |
7378 | ||
7379 | static void | |
7380 | mips16_macro (ip) | |
7381 | struct mips_cl_insn *ip; | |
7382 | { | |
7383 | int mask; | |
7384 | int xreg, yreg, zreg, tmp; | |
7385 | int icnt; | |
7386 | expressionS expr1; | |
7387 | int dbl; | |
7388 | const char *s, *s2, *s3; | |
7389 | ||
7390 | mask = ip->insn_mo->mask; | |
7391 | ||
7392 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7393 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7394 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7395 | ||
7396 | icnt = 0; | |
7397 | ||
7398 | expr1.X_op = O_constant; | |
7399 | expr1.X_op_symbol = NULL; | |
7400 | expr1.X_add_symbol = NULL; | |
7401 | expr1.X_add_number = 1; | |
7402 | ||
7403 | dbl = 0; | |
7404 | ||
7405 | switch (mask) | |
7406 | { | |
7407 | default: | |
7408 | internalError (); | |
7409 | ||
7410 | case M_DDIV_3: | |
7411 | dbl = 1; | |
7412 | case M_DIV_3: | |
7413 | s = "mflo"; | |
7414 | goto do_div3; | |
7415 | case M_DREM_3: | |
7416 | dbl = 1; | |
7417 | case M_REM_3: | |
7418 | s = "mfhi"; | |
7419 | do_div3: | |
7420 | mips_emit_delays (true); | |
7421 | ++mips_opts.noreorder; | |
7422 | mips_any_noreorder = 1; | |
2396cfb9 | 7423 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7424 | dbl ? "ddiv" : "div", |
7425 | "0,x,y", xreg, yreg); | |
7426 | expr1.X_add_number = 2; | |
7427 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7428 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7429 | 7); | |
bdaaa2e1 | 7430 | |
252b5132 RH |
7431 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7432 | since that causes an overflow. We should do that as well, | |
7433 | but I don't see how to do the comparisons without a temporary | |
7434 | register. */ | |
7435 | --mips_opts.noreorder; | |
2396cfb9 | 7436 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7437 | break; |
7438 | ||
7439 | case M_DIVU_3: | |
7440 | s = "divu"; | |
7441 | s2 = "mflo"; | |
7442 | goto do_divu3; | |
7443 | case M_REMU_3: | |
7444 | s = "divu"; | |
7445 | s2 = "mfhi"; | |
7446 | goto do_divu3; | |
7447 | case M_DDIVU_3: | |
7448 | s = "ddivu"; | |
7449 | s2 = "mflo"; | |
7450 | goto do_divu3; | |
7451 | case M_DREMU_3: | |
7452 | s = "ddivu"; | |
7453 | s2 = "mfhi"; | |
7454 | do_divu3: | |
7455 | mips_emit_delays (true); | |
7456 | ++mips_opts.noreorder; | |
7457 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7458 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7459 | xreg, yreg); | |
252b5132 RH |
7460 | expr1.X_add_number = 2; |
7461 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7463 | "6", 7); | |
252b5132 | 7464 | --mips_opts.noreorder; |
2396cfb9 | 7465 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7466 | break; |
7467 | ||
7468 | case M_DMUL: | |
7469 | dbl = 1; | |
7470 | case M_MUL: | |
2396cfb9 | 7471 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7472 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7473 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7474 | zreg); | |
252b5132 RH |
7475 | return; |
7476 | ||
7477 | case M_DSUBU_I: | |
7478 | dbl = 1; | |
7479 | goto do_subu; | |
7480 | case M_SUBU_I: | |
7481 | do_subu: | |
7482 | if (imm_expr.X_op != O_constant) | |
7483 | as_bad (_("Unsupported large constant")); | |
7484 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7485 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7486 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7487 | break; |
7488 | ||
7489 | case M_SUBU_I_2: | |
7490 | if (imm_expr.X_op != O_constant) | |
7491 | as_bad (_("Unsupported large constant")); | |
7492 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7493 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7494 | "x,k", xreg); | |
7495 | break; | |
7496 | ||
7497 | case M_DSUBU_I_2: | |
7498 | if (imm_expr.X_op != O_constant) | |
7499 | as_bad (_("Unsupported large constant")); | |
7500 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7501 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7502 | "y,j", yreg); | |
7503 | break; | |
7504 | ||
7505 | case M_BEQ: | |
7506 | s = "cmp"; | |
7507 | s2 = "bteqz"; | |
7508 | goto do_branch; | |
7509 | case M_BNE: | |
7510 | s = "cmp"; | |
7511 | s2 = "btnez"; | |
7512 | goto do_branch; | |
7513 | case M_BLT: | |
7514 | s = "slt"; | |
7515 | s2 = "btnez"; | |
7516 | goto do_branch; | |
7517 | case M_BLTU: | |
7518 | s = "sltu"; | |
7519 | s2 = "btnez"; | |
7520 | goto do_branch; | |
7521 | case M_BLE: | |
7522 | s = "slt"; | |
7523 | s2 = "bteqz"; | |
7524 | goto do_reverse_branch; | |
7525 | case M_BLEU: | |
7526 | s = "sltu"; | |
7527 | s2 = "bteqz"; | |
7528 | goto do_reverse_branch; | |
7529 | case M_BGE: | |
7530 | s = "slt"; | |
7531 | s2 = "bteqz"; | |
7532 | goto do_branch; | |
7533 | case M_BGEU: | |
7534 | s = "sltu"; | |
7535 | s2 = "bteqz"; | |
7536 | goto do_branch; | |
7537 | case M_BGT: | |
7538 | s = "slt"; | |
7539 | s2 = "btnez"; | |
7540 | goto do_reverse_branch; | |
7541 | case M_BGTU: | |
7542 | s = "sltu"; | |
7543 | s2 = "btnez"; | |
7544 | ||
7545 | do_reverse_branch: | |
7546 | tmp = xreg; | |
7547 | xreg = yreg; | |
7548 | yreg = tmp; | |
7549 | ||
7550 | do_branch: | |
7551 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7552 | xreg, yreg); | |
7553 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7554 | break; | |
7555 | ||
7556 | case M_BEQ_I: | |
7557 | s = "cmpi"; | |
7558 | s2 = "bteqz"; | |
7559 | s3 = "x,U"; | |
7560 | goto do_branch_i; | |
7561 | case M_BNE_I: | |
7562 | s = "cmpi"; | |
7563 | s2 = "btnez"; | |
7564 | s3 = "x,U"; | |
7565 | goto do_branch_i; | |
7566 | case M_BLT_I: | |
7567 | s = "slti"; | |
7568 | s2 = "btnez"; | |
7569 | s3 = "x,8"; | |
7570 | goto do_branch_i; | |
7571 | case M_BLTU_I: | |
7572 | s = "sltiu"; | |
7573 | s2 = "btnez"; | |
7574 | s3 = "x,8"; | |
7575 | goto do_branch_i; | |
7576 | case M_BLE_I: | |
7577 | s = "slti"; | |
7578 | s2 = "btnez"; | |
7579 | s3 = "x,8"; | |
7580 | goto do_addone_branch_i; | |
7581 | case M_BLEU_I: | |
7582 | s = "sltiu"; | |
7583 | s2 = "btnez"; | |
7584 | s3 = "x,8"; | |
7585 | goto do_addone_branch_i; | |
7586 | case M_BGE_I: | |
7587 | s = "slti"; | |
7588 | s2 = "bteqz"; | |
7589 | s3 = "x,8"; | |
7590 | goto do_branch_i; | |
7591 | case M_BGEU_I: | |
7592 | s = "sltiu"; | |
7593 | s2 = "bteqz"; | |
7594 | s3 = "x,8"; | |
7595 | goto do_branch_i; | |
7596 | case M_BGT_I: | |
7597 | s = "slti"; | |
7598 | s2 = "bteqz"; | |
7599 | s3 = "x,8"; | |
7600 | goto do_addone_branch_i; | |
7601 | case M_BGTU_I: | |
7602 | s = "sltiu"; | |
7603 | s2 = "bteqz"; | |
7604 | s3 = "x,8"; | |
7605 | ||
7606 | do_addone_branch_i: | |
7607 | if (imm_expr.X_op != O_constant) | |
7608 | as_bad (_("Unsupported large constant")); | |
7609 | ++imm_expr.X_add_number; | |
7610 | ||
7611 | do_branch_i: | |
7612 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7613 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7614 | break; | |
7615 | ||
7616 | case M_ABS: | |
7617 | expr1.X_add_number = 0; | |
98d3f06f | 7618 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7619 | if (xreg != yreg) |
ea1fb5dc | 7620 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7621 | expr1.X_add_number = 2; |
7622 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7624 | "neg", "x,w", xreg, xreg); | |
7625 | } | |
7626 | } | |
7627 | ||
7628 | /* For consistency checking, verify that all bits are specified either | |
7629 | by the match/mask part of the instruction definition, or by the | |
7630 | operand list. */ | |
7631 | static int | |
7632 | validate_mips_insn (opc) | |
7633 | const struct mips_opcode *opc; | |
7634 | { | |
7635 | const char *p = opc->args; | |
7636 | char c; | |
7637 | unsigned long used_bits = opc->mask; | |
7638 | ||
7639 | if ((used_bits & opc->match) != opc->match) | |
7640 | { | |
7641 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7642 | opc->name, opc->args); | |
7643 | return 0; | |
7644 | } | |
7645 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7646 | while (*p) | |
7647 | switch (c = *p++) | |
7648 | { | |
7649 | case ',': break; | |
7650 | case '(': break; | |
7651 | case ')': break; | |
7652 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7653 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7654 | case 'A': break; | |
4372b673 | 7655 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7656 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7657 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7658 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7659 | case 'F': break; | |
7660 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7661 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7662 | case 'I': break; |
e972090a | 7663 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7664 | case 'L': break; |
7665 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7666 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7667 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7668 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7669 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7670 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7671 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7672 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7673 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7674 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7675 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7676 | case 'f': break; | |
7677 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7678 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7679 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7680 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7681 | case 'l': break; | |
7682 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7683 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7684 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7685 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7686 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7687 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7688 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7689 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7690 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7691 | case 'x': break; | |
7692 | case 'z': break; | |
7693 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7694 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7695 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7696 | default: |
7697 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7698 | c, opc->name, opc->args); | |
7699 | return 0; | |
7700 | } | |
7701 | #undef USE_BITS | |
7702 | if (used_bits != 0xffffffff) | |
7703 | { | |
7704 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7705 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7706 | return 0; | |
7707 | } | |
7708 | return 1; | |
7709 | } | |
7710 | ||
7711 | /* This routine assembles an instruction into its binary format. As a | |
7712 | side effect, it sets one of the global variables imm_reloc or | |
7713 | offset_reloc to the type of relocation to do if one of the operands | |
7714 | is an address expression. */ | |
7715 | ||
7716 | static void | |
7717 | mips_ip (str, ip) | |
7718 | char *str; | |
7719 | struct mips_cl_insn *ip; | |
7720 | { | |
7721 | char *s; | |
7722 | const char *args; | |
43841e91 | 7723 | char c = 0; |
252b5132 RH |
7724 | struct mips_opcode *insn; |
7725 | char *argsStart; | |
7726 | unsigned int regno; | |
7727 | unsigned int lastregno = 0; | |
7728 | char *s_reset; | |
7729 | char save_c = 0; | |
252b5132 RH |
7730 | |
7731 | insn_error = NULL; | |
7732 | ||
7733 | /* If the instruction contains a '.', we first try to match an instruction | |
7734 | including the '.'. Then we try again without the '.'. */ | |
7735 | insn = NULL; | |
3882b010 | 7736 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7737 | continue; |
7738 | ||
7739 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7740 | the call to hash_find. Save the character we replaced just in case we | |
7741 | have to re-parse the instruction. */ | |
3882b010 | 7742 | if (ISSPACE (*s)) |
252b5132 RH |
7743 | { |
7744 | save_c = *s; | |
7745 | *s++ = '\0'; | |
7746 | } | |
bdaaa2e1 | 7747 | |
252b5132 RH |
7748 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7749 | ||
7750 | /* If we didn't find the instruction in the opcode table, try again, but | |
7751 | this time with just the instruction up to, but not including the | |
7752 | first '.'. */ | |
7753 | if (insn == NULL) | |
7754 | { | |
bdaaa2e1 | 7755 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7756 | if (save_c) |
7757 | *(--s) = save_c; | |
7758 | ||
7759 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7760 | for (s = str; |
7761 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7762 | ++s) | |
252b5132 RH |
7763 | continue; |
7764 | ||
7765 | /* If we did not find a '.', then we can quit now. */ | |
7766 | if (*s != '.') | |
7767 | { | |
7768 | insn_error = "unrecognized opcode"; | |
7769 | return; | |
7770 | } | |
7771 | ||
7772 | /* Lookup the instruction in the hash table. */ | |
7773 | *s++ = '\0'; | |
7774 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7775 | { | |
7776 | insn_error = "unrecognized opcode"; | |
7777 | return; | |
7778 | } | |
252b5132 RH |
7779 | } |
7780 | ||
7781 | argsStart = s; | |
7782 | for (;;) | |
7783 | { | |
252b5132 RH |
7784 | boolean ok; |
7785 | ||
7786 | assert (strcmp (insn->name, str) == 0); | |
7787 | ||
1f25f5d3 CD |
7788 | if (OPCODE_IS_MEMBER (insn, |
7789 | (mips_opts.isa | |
98d3f06f | 7790 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 7791 | mips_arch)) |
252b5132 | 7792 | ok = true; |
bdaaa2e1 | 7793 | else |
252b5132 | 7794 | ok = false; |
bdaaa2e1 | 7795 | |
252b5132 RH |
7796 | if (insn->pinfo != INSN_MACRO) |
7797 | { | |
ec68c924 | 7798 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7799 | ok = false; |
7800 | } | |
7801 | ||
7802 | if (! ok) | |
7803 | { | |
7804 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7805 | && strcmp (insn->name, insn[1].name) == 0) | |
7806 | { | |
7807 | ++insn; | |
7808 | continue; | |
7809 | } | |
252b5132 | 7810 | else |
beae10d5 | 7811 | { |
268f6bed L |
7812 | if (!insn_error) |
7813 | { | |
7814 | static char buf[100]; | |
7815 | sprintf (buf, | |
7816 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7817 | mips_cpu_to_str (mips_arch), |
268f6bed | 7818 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7819 | |
268f6bed L |
7820 | insn_error = buf; |
7821 | } | |
7822 | if (save_c) | |
7823 | *(--s) = save_c; | |
2bd7f1f3 | 7824 | return; |
252b5132 | 7825 | } |
252b5132 RH |
7826 | } |
7827 | ||
7828 | ip->insn_mo = insn; | |
7829 | ip->insn_opcode = insn->match; | |
268f6bed | 7830 | insn_error = NULL; |
252b5132 RH |
7831 | for (args = insn->args;; ++args) |
7832 | { | |
ad8d3bb3 | 7833 | s += strspn (s, " \t"); |
252b5132 RH |
7834 | switch (*args) |
7835 | { | |
7836 | case '\0': /* end of args */ | |
7837 | if (*s == '\0') | |
7838 | return; | |
7839 | break; | |
7840 | ||
7841 | case ',': | |
7842 | if (*s++ == *args) | |
7843 | continue; | |
7844 | s--; | |
7845 | switch (*++args) | |
7846 | { | |
7847 | case 'r': | |
7848 | case 'v': | |
38487616 | 7849 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7850 | continue; |
7851 | ||
7852 | case 'w': | |
38487616 TS |
7853 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7854 | continue; | |
7855 | ||
252b5132 | 7856 | case 'W': |
38487616 | 7857 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7858 | continue; |
7859 | ||
7860 | case 'V': | |
38487616 | 7861 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7862 | continue; |
7863 | } | |
7864 | break; | |
7865 | ||
7866 | case '(': | |
7867 | /* Handle optional base register. | |
7868 | Either the base register is omitted or | |
bdaaa2e1 | 7869 | we must have a left paren. */ |
252b5132 RH |
7870 | /* This is dependent on the next operand specifier |
7871 | is a base register specification. */ | |
7872 | assert (args[1] == 'b' || args[1] == '5' | |
7873 | || args[1] == '-' || args[1] == '4'); | |
7874 | if (*s == '\0') | |
7875 | return; | |
7876 | ||
7877 | case ')': /* these must match exactly */ | |
7878 | if (*s++ == *args) | |
7879 | continue; | |
7880 | break; | |
7881 | ||
7882 | case '<': /* must be at least one digit */ | |
7883 | /* | |
7884 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
7885 | * than 31 or less than 0, then the shift amount should be |
7886 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
7887 | * We issue a warning and mask out all but the low 5 bits. |
7888 | */ | |
7889 | my_getExpression (&imm_expr, s); | |
7890 | check_absolute_expr (ip, &imm_expr); | |
7891 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7892 | { | |
7893 | as_warn (_("Improper shift amount (%ld)"), | |
7894 | (long) imm_expr.X_add_number); | |
38487616 | 7895 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 7896 | } |
38487616 | 7897 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
7898 | imm_expr.X_op = O_absent; |
7899 | s = expr_end; | |
7900 | continue; | |
7901 | ||
7902 | case '>': /* shift amount minus 32 */ | |
7903 | my_getExpression (&imm_expr, s); | |
7904 | check_absolute_expr (ip, &imm_expr); | |
7905 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7906 | || (unsigned long) imm_expr.X_add_number > 63) | |
7907 | break; | |
38487616 | 7908 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
7909 | imm_expr.X_op = O_absent; |
7910 | s = expr_end; | |
7911 | continue; | |
7912 | ||
252b5132 RH |
7913 | case 'k': /* cache code */ |
7914 | case 'h': /* prefx code */ | |
7915 | my_getExpression (&imm_expr, s); | |
7916 | check_absolute_expr (ip, &imm_expr); | |
7917 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7918 | { | |
7919 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7920 | ip->insn_mo->name, | |
7921 | (unsigned long) imm_expr.X_add_number); | |
7922 | imm_expr.X_add_number &= 0x1f; | |
7923 | } | |
7924 | if (*args == 'k') | |
7925 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7926 | else | |
7927 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7928 | imm_expr.X_op = O_absent; | |
7929 | s = expr_end; | |
7930 | continue; | |
7931 | ||
7932 | case 'c': /* break code */ | |
7933 | my_getExpression (&imm_expr, s); | |
7934 | check_absolute_expr (ip, &imm_expr); | |
7935 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7936 | { | |
7937 | as_warn (_("Illegal break code (%ld)"), | |
7938 | (long) imm_expr.X_add_number); | |
38487616 | 7939 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 7940 | } |
38487616 | 7941 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
7942 | imm_expr.X_op = O_absent; |
7943 | s = expr_end; | |
7944 | continue; | |
7945 | ||
7946 | case 'q': /* lower break code */ | |
7947 | my_getExpression (&imm_expr, s); | |
7948 | check_absolute_expr (ip, &imm_expr); | |
7949 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7950 | { | |
7951 | as_warn (_("Illegal lower break code (%ld)"), | |
7952 | (long) imm_expr.X_add_number); | |
38487616 | 7953 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 7954 | } |
38487616 | 7955 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
7956 | imm_expr.X_op = O_absent; |
7957 | s = expr_end; | |
7958 | continue; | |
7959 | ||
4372b673 | 7960 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7961 | my_getExpression (&imm_expr, s); |
156c2f8b | 7962 | check_absolute_expr (ip, &imm_expr); |
38487616 | 7963 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 7964 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 7965 | (long) imm_expr.X_add_number); |
38487616 | 7966 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
7967 | imm_expr.X_op = O_absent; |
7968 | s = expr_end; | |
7969 | continue; | |
7970 | ||
98d3f06f | 7971 | case 'C': /* Coprocessor code */ |
beae10d5 | 7972 | my_getExpression (&imm_expr, s); |
252b5132 | 7973 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 7974 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 7975 | { |
beae10d5 | 7976 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7977 | (long) imm_expr.X_add_number); |
98d3f06f | 7978 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 7979 | } |
beae10d5 KH |
7980 | ip->insn_opcode |= imm_expr.X_add_number; |
7981 | imm_expr.X_op = O_absent; | |
7982 | s = expr_end; | |
7983 | continue; | |
252b5132 | 7984 | |
4372b673 NC |
7985 | case 'J': /* 19-bit wait code. */ |
7986 | my_getExpression (&imm_expr, s); | |
7987 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 7988 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
7989 | as_warn (_("Illegal 19-bit code (%ld)"), |
7990 | (long) imm_expr.X_add_number); | |
38487616 | 7991 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
7992 | imm_expr.X_op = O_absent; |
7993 | s = expr_end; | |
7994 | continue; | |
7995 | ||
252b5132 | 7996 | case 'P': /* Performance register */ |
beae10d5 | 7997 | my_getExpression (&imm_expr, s); |
252b5132 | 7998 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7999 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8000 | { |
38487616 | 8001 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 8002 | (long) imm_expr.X_add_number); |
38487616 | 8003 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8004 | } |
38487616 | 8005 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8006 | imm_expr.X_op = O_absent; |
8007 | s = expr_end; | |
8008 | continue; | |
252b5132 RH |
8009 | |
8010 | case 'b': /* base register */ | |
8011 | case 'd': /* destination register */ | |
8012 | case 's': /* source register */ | |
8013 | case 't': /* target register */ | |
8014 | case 'r': /* both target and source */ | |
8015 | case 'v': /* both dest and source */ | |
8016 | case 'w': /* both dest and target */ | |
8017 | case 'E': /* coprocessor target register */ | |
8018 | case 'G': /* coprocessor destination register */ | |
8019 | case 'x': /* ignore register name */ | |
8020 | case 'z': /* must be zero register */ | |
4372b673 | 8021 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8022 | s_reset = s; |
8023 | if (s[0] == '$') | |
8024 | { | |
8025 | ||
3882b010 | 8026 | if (ISDIGIT (s[1])) |
252b5132 RH |
8027 | { |
8028 | ++s; | |
8029 | regno = 0; | |
8030 | do | |
8031 | { | |
8032 | regno *= 10; | |
8033 | regno += *s - '0'; | |
8034 | ++s; | |
8035 | } | |
3882b010 | 8036 | while (ISDIGIT (*s)); |
252b5132 RH |
8037 | if (regno > 31) |
8038 | as_bad (_("Invalid register number (%d)"), regno); | |
8039 | } | |
8040 | else if (*args == 'E' || *args == 'G') | |
8041 | goto notreg; | |
8042 | else | |
8043 | { | |
8044 | if (s[1] == 'f' && s[2] == 'p') | |
8045 | { | |
8046 | s += 3; | |
8047 | regno = FP; | |
8048 | } | |
8049 | else if (s[1] == 's' && s[2] == 'p') | |
8050 | { | |
8051 | s += 3; | |
8052 | regno = SP; | |
8053 | } | |
8054 | else if (s[1] == 'g' && s[2] == 'p') | |
8055 | { | |
8056 | s += 3; | |
8057 | regno = GP; | |
8058 | } | |
8059 | else if (s[1] == 'a' && s[2] == 't') | |
8060 | { | |
8061 | s += 3; | |
8062 | regno = AT; | |
8063 | } | |
8064 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8065 | { | |
8066 | s += 4; | |
8067 | regno = KT0; | |
8068 | } | |
8069 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8070 | { | |
8071 | s += 4; | |
8072 | regno = KT1; | |
8073 | } | |
8074 | else if (itbl_have_entries) | |
8075 | { | |
8076 | char *p, *n; | |
d7ba4a77 | 8077 | unsigned long r; |
252b5132 | 8078 | |
d7ba4a77 | 8079 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8080 | n = itbl_get_field (&p); /* n is name */ |
8081 | ||
d7ba4a77 ILT |
8082 | /* See if this is a register defined in an |
8083 | itbl entry. */ | |
8084 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8085 | { |
8086 | /* Get_field advances to the start of | |
8087 | the next field, so we need to back | |
d7ba4a77 | 8088 | rack to the end of the last field. */ |
bdaaa2e1 | 8089 | if (p) |
252b5132 | 8090 | s = p - 1; |
bdaaa2e1 | 8091 | else |
d7ba4a77 | 8092 | s = strchr (s, '\0'); |
252b5132 RH |
8093 | regno = r; |
8094 | } | |
8095 | else | |
8096 | goto notreg; | |
beae10d5 | 8097 | } |
252b5132 RH |
8098 | else |
8099 | goto notreg; | |
8100 | } | |
8101 | if (regno == AT | |
8102 | && ! mips_opts.noat | |
8103 | && *args != 'E' | |
8104 | && *args != 'G') | |
8105 | as_warn (_("Used $at without \".set noat\"")); | |
8106 | c = *args; | |
8107 | if (*s == ' ') | |
8108 | s++; | |
8109 | if (args[1] != *s) | |
8110 | { | |
8111 | if (c == 'r' || c == 'v' || c == 'w') | |
8112 | { | |
8113 | regno = lastregno; | |
8114 | s = s_reset; | |
8115 | args++; | |
8116 | } | |
8117 | } | |
8118 | /* 'z' only matches $0. */ | |
8119 | if (c == 'z' && regno != 0) | |
8120 | break; | |
8121 | ||
bdaaa2e1 KH |
8122 | /* Now that we have assembled one operand, we use the args string |
8123 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8124 | switch (c) |
8125 | { | |
8126 | case 'r': | |
8127 | case 's': | |
8128 | case 'v': | |
8129 | case 'b': | |
38487616 | 8130 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8131 | break; |
8132 | case 'd': | |
8133 | case 'G': | |
38487616 | 8134 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8135 | break; |
4372b673 | 8136 | case 'U': |
38487616 TS |
8137 | ip->insn_opcode |= regno << OP_SH_RD; |
8138 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8139 | break; |
252b5132 RH |
8140 | case 'w': |
8141 | case 't': | |
8142 | case 'E': | |
38487616 | 8143 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8144 | break; |
8145 | case 'x': | |
8146 | /* This case exists because on the r3000 trunc | |
8147 | expands into a macro which requires a gp | |
8148 | register. On the r6000 or r4000 it is | |
8149 | assembled into a single instruction which | |
8150 | ignores the register. Thus the insn version | |
8151 | is MIPS_ISA2 and uses 'x', and the macro | |
8152 | version is MIPS_ISA1 and uses 't'. */ | |
8153 | break; | |
8154 | case 'z': | |
8155 | /* This case is for the div instruction, which | |
8156 | acts differently if the destination argument | |
8157 | is $0. This only matches $0, and is checked | |
8158 | outside the switch. */ | |
8159 | break; | |
8160 | case 'D': | |
8161 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8162 | break; | |
8163 | /* What about all other operands like 'i', which | |
8164 | can be specified in the opcode table? */ | |
8165 | } | |
8166 | lastregno = regno; | |
8167 | continue; | |
8168 | } | |
8169 | notreg: | |
8170 | switch (*args++) | |
8171 | { | |
8172 | case 'r': | |
8173 | case 'v': | |
38487616 | 8174 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8175 | continue; |
8176 | case 'w': | |
38487616 | 8177 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8178 | continue; |
8179 | } | |
8180 | break; | |
8181 | ||
8182 | case 'D': /* floating point destination register */ | |
8183 | case 'S': /* floating point source register */ | |
8184 | case 'T': /* floating point target register */ | |
8185 | case 'R': /* floating point source register */ | |
8186 | case 'V': | |
8187 | case 'W': | |
8188 | s_reset = s; | |
3882b010 L |
8189 | if (s[0] == '$' && s[1] == 'f' |
8190 | && ISDIGIT (s[2])) | |
252b5132 RH |
8191 | { |
8192 | s += 2; | |
8193 | regno = 0; | |
8194 | do | |
8195 | { | |
8196 | regno *= 10; | |
8197 | regno += *s - '0'; | |
8198 | ++s; | |
8199 | } | |
3882b010 | 8200 | while (ISDIGIT (*s)); |
252b5132 RH |
8201 | |
8202 | if (regno > 31) | |
8203 | as_bad (_("Invalid float register number (%d)"), regno); | |
8204 | ||
8205 | if ((regno & 1) != 0 | |
ca4e0257 | 8206 | && HAVE_32BIT_FPRS |
252b5132 RH |
8207 | && ! (strcmp (str, "mtc1") == 0 |
8208 | || strcmp (str, "mfc1") == 0 | |
8209 | || strcmp (str, "lwc1") == 0 | |
8210 | || strcmp (str, "swc1") == 0 | |
8211 | || strcmp (str, "l.s") == 0 | |
8212 | || strcmp (str, "s.s") == 0)) | |
8213 | as_warn (_("Float register should be even, was %d"), | |
8214 | regno); | |
8215 | ||
8216 | c = *args; | |
8217 | if (*s == ' ') | |
8218 | s++; | |
8219 | if (args[1] != *s) | |
8220 | { | |
8221 | if (c == 'V' || c == 'W') | |
8222 | { | |
8223 | regno = lastregno; | |
8224 | s = s_reset; | |
8225 | args++; | |
8226 | } | |
8227 | } | |
8228 | switch (c) | |
8229 | { | |
8230 | case 'D': | |
38487616 | 8231 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8232 | break; |
8233 | case 'V': | |
8234 | case 'S': | |
38487616 | 8235 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 RH |
8236 | break; |
8237 | case 'W': | |
8238 | case 'T': | |
38487616 | 8239 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8240 | break; |
8241 | case 'R': | |
38487616 | 8242 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8243 | break; |
8244 | } | |
8245 | lastregno = regno; | |
8246 | continue; | |
8247 | } | |
8248 | ||
252b5132 RH |
8249 | switch (*args++) |
8250 | { | |
8251 | case 'V': | |
38487616 | 8252 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8253 | continue; |
8254 | case 'W': | |
38487616 | 8255 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8256 | continue; |
8257 | } | |
8258 | break; | |
8259 | ||
8260 | case 'I': | |
8261 | my_getExpression (&imm_expr, s); | |
8262 | if (imm_expr.X_op != O_big | |
8263 | && imm_expr.X_op != O_constant) | |
8264 | insn_error = _("absolute expression required"); | |
8265 | s = expr_end; | |
8266 | continue; | |
8267 | ||
8268 | case 'A': | |
8269 | my_getExpression (&offset_expr, s); | |
f6688943 | 8270 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8271 | s = expr_end; |
8272 | continue; | |
8273 | ||
8274 | case 'F': | |
8275 | case 'L': | |
8276 | case 'f': | |
8277 | case 'l': | |
8278 | { | |
8279 | int f64; | |
ca4e0257 | 8280 | int using_gprs; |
252b5132 RH |
8281 | char *save_in; |
8282 | char *err; | |
8283 | unsigned char temp[8]; | |
8284 | int len; | |
8285 | unsigned int length; | |
8286 | segT seg; | |
8287 | subsegT subseg; | |
8288 | char *p; | |
8289 | ||
8290 | /* These only appear as the last operand in an | |
8291 | instruction, and every instruction that accepts | |
8292 | them in any variant accepts them in all variants. | |
8293 | This means we don't have to worry about backing out | |
8294 | any changes if the instruction does not match. | |
8295 | ||
8296 | The difference between them is the size of the | |
8297 | floating point constant and where it goes. For 'F' | |
8298 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8299 | is 32 bits. Where the constant is placed is based | |
8300 | on how the MIPS assembler does things: | |
8301 | F -- .rdata | |
8302 | L -- .lit8 | |
8303 | f -- immediate value | |
8304 | l -- .lit4 | |
8305 | ||
8306 | The .lit4 and .lit8 sections are only used if | |
8307 | permitted by the -G argument. | |
8308 | ||
8309 | When generating embedded PIC code, we use the | |
8310 | .lit8 section but not the .lit4 section (we can do | |
8311 | .lit4 inline easily; we need to put .lit8 | |
8312 | somewhere in the data segment, and using .lit8 | |
8313 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8314 | .lit8 entries). |
8315 | ||
8316 | The code below needs to know whether the target register | |
8317 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8318 | 'F' are used with GPR-based instructions and 'l' and | |
8319 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8320 | |
8321 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8322 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8323 | |
8324 | save_in = input_line_pointer; | |
8325 | input_line_pointer = s; | |
8326 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8327 | length = len; | |
8328 | s = input_line_pointer; | |
8329 | input_line_pointer = save_in; | |
8330 | if (err != NULL && *err != '\0') | |
8331 | { | |
8332 | as_bad (_("Bad floating point constant: %s"), err); | |
8333 | memset (temp, '\0', sizeof temp); | |
8334 | length = f64 ? 8 : 4; | |
8335 | } | |
8336 | ||
156c2f8b | 8337 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8338 | |
8339 | if (*args == 'f' | |
8340 | || (*args == 'l' | |
8341 | && (! USE_GLOBAL_POINTER_OPT | |
8342 | || mips_pic == EMBEDDED_PIC | |
8343 | || g_switch_value < 4 | |
8344 | || (temp[0] == 0 && temp[1] == 0) | |
8345 | || (temp[2] == 0 && temp[3] == 0)))) | |
8346 | { | |
8347 | imm_expr.X_op = O_constant; | |
8348 | if (! target_big_endian) | |
8349 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8350 | else | |
8351 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8352 | } | |
8353 | else if (length > 4 | |
119d663a | 8354 | && ! mips_disable_float_construction |
ca4e0257 RS |
8355 | /* Constants can only be constructed in GPRs and |
8356 | copied to FPRs if the GPRs are at least as wide | |
8357 | as the FPRs. Force the constant into memory if | |
8358 | we are using 64-bit FPRs but the GPRs are only | |
8359 | 32 bits wide. */ | |
8360 | && (using_gprs | |
8361 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8362 | && ((temp[0] == 0 && temp[1] == 0) |
8363 | || (temp[2] == 0 && temp[3] == 0)) | |
8364 | && ((temp[4] == 0 && temp[5] == 0) | |
8365 | || (temp[6] == 0 && temp[7] == 0))) | |
8366 | { | |
ca4e0257 RS |
8367 | /* The value is simple enough to load with a couple of |
8368 | instructions. If using 32-bit registers, set | |
8369 | imm_expr to the high order 32 bits and offset_expr to | |
8370 | the low order 32 bits. Otherwise, set imm_expr to | |
8371 | the entire 64 bit constant. */ | |
8372 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8373 | { |
8374 | imm_expr.X_op = O_constant; | |
8375 | offset_expr.X_op = O_constant; | |
8376 | if (! target_big_endian) | |
8377 | { | |
8378 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8379 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8380 | } | |
8381 | else | |
8382 | { | |
8383 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8384 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8385 | } | |
8386 | if (offset_expr.X_add_number == 0) | |
8387 | offset_expr.X_op = O_absent; | |
8388 | } | |
8389 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8390 | { | |
8391 | imm_expr.X_op = O_constant; | |
8392 | if (! target_big_endian) | |
8393 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8394 | else | |
8395 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8396 | } | |
8397 | else | |
8398 | { | |
8399 | imm_expr.X_op = O_big; | |
8400 | imm_expr.X_add_number = 4; | |
8401 | if (! target_big_endian) | |
8402 | { | |
8403 | generic_bignum[0] = bfd_getl16 (temp); | |
8404 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8405 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8406 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8407 | } | |
8408 | else | |
8409 | { | |
8410 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8411 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8412 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8413 | generic_bignum[3] = bfd_getb16 (temp); | |
8414 | } | |
8415 | } | |
8416 | } | |
8417 | else | |
8418 | { | |
8419 | const char *newname; | |
8420 | segT new_seg; | |
8421 | ||
8422 | /* Switch to the right section. */ | |
8423 | seg = now_seg; | |
8424 | subseg = now_subseg; | |
8425 | switch (*args) | |
8426 | { | |
8427 | default: /* unused default case avoids warnings. */ | |
8428 | case 'L': | |
8429 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8430 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8431 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8432 | newname = ".lit8"; |
8433 | break; | |
8434 | case 'F': | |
bb2d6cd7 GK |
8435 | if (mips_pic == EMBEDDED_PIC) |
8436 | newname = ".lit8"; | |
8437 | else | |
8438 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8439 | break; |
8440 | case 'l': | |
8441 | assert (!USE_GLOBAL_POINTER_OPT | |
8442 | || g_switch_value >= 4); | |
8443 | newname = ".lit4"; | |
8444 | break; | |
8445 | } | |
8446 | new_seg = subseg_new (newname, (subsegT) 0); | |
8447 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8448 | bfd_set_section_flags (stdoutput, new_seg, | |
8449 | (SEC_ALLOC | |
8450 | | SEC_LOAD | |
8451 | | SEC_READONLY | |
8452 | | SEC_DATA)); | |
8453 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8454 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8455 | && strcmp (TARGET_OS, "elf") != 0) | |
8456 | record_alignment (new_seg, 4); | |
8457 | else | |
8458 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8459 | if (seg == now_seg) | |
8460 | as_bad (_("Can't use floating point insn in this section")); | |
8461 | ||
8462 | /* Set the argument to the current address in the | |
8463 | section. */ | |
8464 | offset_expr.X_op = O_symbol; | |
8465 | offset_expr.X_add_symbol = | |
8466 | symbol_new ("L0\001", now_seg, | |
8467 | (valueT) frag_now_fix (), frag_now); | |
8468 | offset_expr.X_add_number = 0; | |
8469 | ||
8470 | /* Put the floating point number into the section. */ | |
8471 | p = frag_more ((int) length); | |
8472 | memcpy (p, temp, length); | |
8473 | ||
8474 | /* Switch back to the original section. */ | |
8475 | subseg_set (seg, subseg); | |
8476 | } | |
8477 | } | |
8478 | continue; | |
8479 | ||
8480 | case 'i': /* 16 bit unsigned immediate */ | |
8481 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8482 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8483 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8484 | if (c != S_EX_NONE) |
252b5132 | 8485 | { |
fb1b3232 | 8486 | if (c != S_EX_LO) |
252b5132 RH |
8487 | { |
8488 | if (imm_expr.X_op == O_constant) | |
8489 | imm_expr.X_add_number = | |
8490 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8491 | #ifdef OBJ_ELF |
fb1b3232 | 8492 | else if (c == S_EX_HIGHEST) |
98d3f06f | 8493 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8494 | else if (c == S_EX_HIGHER) |
98d3f06f | 8495 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8496 | else if (c == S_EX_GP_REL) |
8497 | { | |
8498 | /* This occurs in NewABI only. */ | |
8499 | c = my_getSmallExpression (&imm_expr, s); | |
8500 | if (c != S_EX_NEG) | |
8501 | as_bad (_("bad composition of relocations")); | |
8502 | else | |
8503 | { | |
8504 | c = my_getSmallExpression (&imm_expr, s); | |
8505 | if (c != S_EX_LO) | |
8506 | as_bad (_("bad composition of relocations")); | |
8507 | else | |
8508 | { | |
8509 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8510 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8511 | imm_reloc[2] = BFD_RELOC_LO16; | |
8512 | } | |
8513 | } | |
8514 | } | |
8515 | #endif | |
fb1b3232 | 8516 | else if (c == S_EX_HI) |
252b5132 | 8517 | { |
f6688943 | 8518 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8519 | imm_unmatched_hi = true; |
8520 | } | |
8521 | else | |
f6688943 | 8522 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8523 | } |
8524 | else if (imm_expr.X_op == O_constant) | |
8525 | imm_expr.X_add_number &= 0xffff; | |
8526 | } | |
8527 | if (*args == 'i') | |
8528 | { | |
fb1b3232 | 8529 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8530 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8531 | || imm_expr.X_add_number >= 0x10000) |
8532 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8533 | { |
8534 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8535 | !strcmp (insn->name, insn[1].name)) | |
8536 | break; | |
2ae7e77b AH |
8537 | if (imm_expr.X_op == O_constant |
8538 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8539 | as_bad (_("16 bit expression not in range 0..65535")); |
8540 | } | |
8541 | } | |
8542 | else | |
8543 | { | |
8544 | int more; | |
8545 | offsetT max; | |
8546 | ||
8547 | /* The upper bound should be 0x8000, but | |
8548 | unfortunately the MIPS assembler accepts numbers | |
8549 | from 0x8000 to 0xffff and sign extends them, and | |
8550 | we want to be compatible. We only permit this | |
8551 | extended range for an instruction which does not | |
8552 | provide any further alternates, since those | |
8553 | alternates may handle other cases. People should | |
8554 | use the numbers they mean, rather than relying on | |
8555 | a mysterious sign extension. */ | |
8556 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8557 | strcmp (insn->name, insn[1].name) == 0); | |
8558 | if (more) | |
8559 | max = 0x8000; | |
8560 | else | |
8561 | max = 0x10000; | |
fb1b3232 | 8562 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8563 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8564 | || imm_expr.X_add_number >= max) |
8565 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8566 | || (more |
8567 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8568 | && HAVE_64BIT_GPRS |
252b5132 RH |
8569 | && imm_expr.X_unsigned |
8570 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8571 | { | |
8572 | if (more) | |
8573 | break; | |
2ae7e77b AH |
8574 | if (imm_expr.X_op == O_constant |
8575 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8576 | as_bad (_("16 bit expression not in range -32768..32767")); |
8577 | } | |
8578 | } | |
8579 | s = expr_end; | |
8580 | continue; | |
8581 | ||
8582 | case 'o': /* 16 bit offset */ | |
8583 | c = my_getSmallExpression (&offset_expr, s); | |
8584 | ||
8585 | /* If this value won't fit into a 16 bit offset, then go | |
8586 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8587 | code pattern. */ |
fb1b3232 | 8588 | if (c == S_EX_NONE |
252b5132 RH |
8589 | && (offset_expr.X_op != O_constant |
8590 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8591 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8592 | break; |
8593 | ||
fb1b3232 | 8594 | if (c == S_EX_HI) |
252b5132 RH |
8595 | { |
8596 | if (offset_expr.X_op != O_constant) | |
8597 | break; | |
8598 | offset_expr.X_add_number = | |
8599 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8600 | } | |
f6688943 | 8601 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8602 | s = expr_end; |
8603 | continue; | |
8604 | ||
8605 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8606 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8607 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8608 | else |
f6688943 | 8609 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8610 | my_getExpression (&offset_expr, s); |
8611 | s = expr_end; | |
8612 | continue; | |
8613 | ||
8614 | case 'u': /* upper 16 bits */ | |
8615 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8616 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8617 | if (c != S_EX_NONE) |
252b5132 | 8618 | { |
fb1b3232 | 8619 | if (c != S_EX_LO) |
252b5132 RH |
8620 | { |
8621 | if (imm_expr.X_op == O_constant) | |
8622 | imm_expr.X_add_number = | |
8623 | (imm_expr.X_add_number >> 16) & 0xffff; | |
fb1b3232 | 8624 | else if (c == S_EX_HI) |
252b5132 | 8625 | { |
f6688943 | 8626 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8627 | imm_unmatched_hi = true; |
8628 | } | |
645dc66c TS |
8629 | #ifdef OBJ_ELF |
8630 | else if (c == S_EX_HIGHEST) | |
98d3f06f | 8631 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
ad8d3bb3 TS |
8632 | else if (c == S_EX_GP_REL) |
8633 | { | |
8634 | /* This occurs in NewABI only. */ | |
8635 | c = my_getSmallExpression (&imm_expr, s); | |
8636 | if (c != S_EX_NEG) | |
8637 | as_bad (_("bad composition of relocations")); | |
8638 | else | |
8639 | { | |
8640 | c = my_getSmallExpression (&imm_expr, s); | |
8641 | if (c != S_EX_HI) | |
8642 | as_bad (_("bad composition of relocations")); | |
8643 | else | |
8644 | { | |
8645 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8646 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8647 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8648 | } | |
8649 | } | |
8650 | } | |
8651 | #endif | |
252b5132 | 8652 | else |
f6688943 | 8653 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8654 | } |
8655 | else if (imm_expr.X_op == O_constant) | |
8656 | imm_expr.X_add_number &= 0xffff; | |
8657 | } | |
8658 | if (imm_expr.X_op == O_constant | |
8659 | && (imm_expr.X_add_number < 0 | |
8660 | || imm_expr.X_add_number >= 0x10000)) | |
8661 | as_bad (_("lui expression not in range 0..65535")); | |
8662 | s = expr_end; | |
8663 | continue; | |
8664 | ||
8665 | case 'a': /* 26 bit address */ | |
8666 | my_getExpression (&offset_expr, s); | |
8667 | s = expr_end; | |
f6688943 | 8668 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8669 | continue; |
8670 | ||
8671 | case 'N': /* 3 bit branch condition code */ | |
8672 | case 'M': /* 3 bit compare condition code */ | |
8673 | if (strncmp (s, "$fcc", 4) != 0) | |
8674 | break; | |
8675 | s += 4; | |
8676 | regno = 0; | |
8677 | do | |
8678 | { | |
8679 | regno *= 10; | |
8680 | regno += *s - '0'; | |
8681 | ++s; | |
8682 | } | |
3882b010 | 8683 | while (ISDIGIT (*s)); |
252b5132 RH |
8684 | if (regno > 7) |
8685 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8686 | if (*args == 'N') | |
8687 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8688 | else | |
8689 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8690 | continue; |
252b5132 | 8691 | |
156c2f8b NC |
8692 | case 'H': |
8693 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8694 | s += 2; | |
3882b010 | 8695 | if (ISDIGIT (*s)) |
156c2f8b NC |
8696 | { |
8697 | c = 0; | |
8698 | do | |
8699 | { | |
8700 | c *= 10; | |
8701 | c += *s - '0'; | |
8702 | ++s; | |
8703 | } | |
3882b010 | 8704 | while (ISDIGIT (*s)); |
156c2f8b NC |
8705 | } |
8706 | else | |
8707 | c = 8; /* Invalid sel value. */ | |
8708 | ||
8709 | if (c > 7) | |
8710 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8711 | ip->insn_opcode |= c; | |
8712 | continue; | |
8713 | ||
252b5132 RH |
8714 | default: |
8715 | as_bad (_("bad char = '%c'\n"), *args); | |
8716 | internalError (); | |
8717 | } | |
8718 | break; | |
8719 | } | |
8720 | /* Args don't match. */ | |
8721 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8722 | !strcmp (insn->name, insn[1].name)) | |
8723 | { | |
8724 | ++insn; | |
8725 | s = argsStart; | |
268f6bed | 8726 | insn_error = _("illegal operands"); |
252b5132 RH |
8727 | continue; |
8728 | } | |
268f6bed L |
8729 | if (save_c) |
8730 | *(--s) = save_c; | |
252b5132 RH |
8731 | insn_error = _("illegal operands"); |
8732 | return; | |
8733 | } | |
8734 | } | |
8735 | ||
8736 | /* This routine assembles an instruction into its binary format when | |
8737 | assembling for the mips16. As a side effect, it sets one of the | |
8738 | global variables imm_reloc or offset_reloc to the type of | |
8739 | relocation to do if one of the operands is an address expression. | |
8740 | It also sets mips16_small and mips16_ext if the user explicitly | |
8741 | requested a small or extended instruction. */ | |
8742 | ||
8743 | static void | |
8744 | mips16_ip (str, ip) | |
8745 | char *str; | |
8746 | struct mips_cl_insn *ip; | |
8747 | { | |
8748 | char *s; | |
8749 | const char *args; | |
8750 | struct mips_opcode *insn; | |
8751 | char *argsstart; | |
8752 | unsigned int regno; | |
8753 | unsigned int lastregno = 0; | |
8754 | char *s_reset; | |
8755 | ||
8756 | insn_error = NULL; | |
8757 | ||
8758 | mips16_small = false; | |
8759 | mips16_ext = false; | |
8760 | ||
3882b010 | 8761 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8762 | ; |
8763 | switch (*s) | |
8764 | { | |
8765 | case '\0': | |
8766 | break; | |
8767 | ||
8768 | case ' ': | |
8769 | *s++ = '\0'; | |
8770 | break; | |
8771 | ||
8772 | case '.': | |
8773 | if (s[1] == 't' && s[2] == ' ') | |
8774 | { | |
8775 | *s = '\0'; | |
8776 | mips16_small = true; | |
8777 | s += 3; | |
8778 | break; | |
8779 | } | |
8780 | else if (s[1] == 'e' && s[2] == ' ') | |
8781 | { | |
8782 | *s = '\0'; | |
8783 | mips16_ext = true; | |
8784 | s += 3; | |
8785 | break; | |
8786 | } | |
8787 | /* Fall through. */ | |
8788 | default: | |
8789 | insn_error = _("unknown opcode"); | |
8790 | return; | |
8791 | } | |
8792 | ||
8793 | if (mips_opts.noautoextend && ! mips16_ext) | |
8794 | mips16_small = true; | |
8795 | ||
8796 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8797 | { | |
8798 | insn_error = _("unrecognized opcode"); | |
8799 | return; | |
8800 | } | |
8801 | ||
8802 | argsstart = s; | |
8803 | for (;;) | |
8804 | { | |
8805 | assert (strcmp (insn->name, str) == 0); | |
8806 | ||
8807 | ip->insn_mo = insn; | |
8808 | ip->insn_opcode = insn->match; | |
8809 | ip->use_extend = false; | |
8810 | imm_expr.X_op = O_absent; | |
f6688943 TS |
8811 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8812 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8813 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 8814 | offset_expr.X_op = O_absent; |
f6688943 TS |
8815 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8816 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8817 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8818 | for (args = insn->args; 1; ++args) |
8819 | { | |
8820 | int c; | |
8821 | ||
8822 | if (*s == ' ') | |
8823 | ++s; | |
8824 | ||
8825 | /* In this switch statement we call break if we did not find | |
8826 | a match, continue if we did find a match, or return if we | |
8827 | are done. */ | |
8828 | ||
8829 | c = *args; | |
8830 | switch (c) | |
8831 | { | |
8832 | case '\0': | |
8833 | if (*s == '\0') | |
8834 | { | |
8835 | /* Stuff the immediate value in now, if we can. */ | |
8836 | if (imm_expr.X_op == O_constant | |
f6688943 | 8837 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
8838 | && insn->pinfo != INSN_MACRO) |
8839 | { | |
c4e7957c | 8840 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
8841 | imm_expr.X_add_number, true, mips16_small, |
8842 | mips16_ext, &ip->insn_opcode, | |
8843 | &ip->use_extend, &ip->extend); | |
8844 | imm_expr.X_op = O_absent; | |
f6688943 | 8845 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
8846 | } |
8847 | ||
8848 | return; | |
8849 | } | |
8850 | break; | |
8851 | ||
8852 | case ',': | |
8853 | if (*s++ == c) | |
8854 | continue; | |
8855 | s--; | |
8856 | switch (*++args) | |
8857 | { | |
8858 | case 'v': | |
8859 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8860 | continue; | |
8861 | case 'w': | |
8862 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8863 | continue; | |
8864 | } | |
8865 | break; | |
8866 | ||
8867 | case '(': | |
8868 | case ')': | |
8869 | if (*s++ == c) | |
8870 | continue; | |
8871 | break; | |
8872 | ||
8873 | case 'v': | |
8874 | case 'w': | |
8875 | if (s[0] != '$') | |
8876 | { | |
8877 | if (c == 'v') | |
8878 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8879 | else | |
8880 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8881 | ++args; | |
8882 | continue; | |
8883 | } | |
8884 | /* Fall through. */ | |
8885 | case 'x': | |
8886 | case 'y': | |
8887 | case 'z': | |
8888 | case 'Z': | |
8889 | case '0': | |
8890 | case 'S': | |
8891 | case 'R': | |
8892 | case 'X': | |
8893 | case 'Y': | |
8894 | if (s[0] != '$') | |
8895 | break; | |
8896 | s_reset = s; | |
3882b010 | 8897 | if (ISDIGIT (s[1])) |
252b5132 RH |
8898 | { |
8899 | ++s; | |
8900 | regno = 0; | |
8901 | do | |
8902 | { | |
8903 | regno *= 10; | |
8904 | regno += *s - '0'; | |
8905 | ++s; | |
8906 | } | |
3882b010 | 8907 | while (ISDIGIT (*s)); |
252b5132 RH |
8908 | if (regno > 31) |
8909 | { | |
8910 | as_bad (_("invalid register number (%d)"), regno); | |
8911 | regno = 2; | |
8912 | } | |
8913 | } | |
8914 | else | |
8915 | { | |
8916 | if (s[1] == 'f' && s[2] == 'p') | |
8917 | { | |
8918 | s += 3; | |
8919 | regno = FP; | |
8920 | } | |
8921 | else if (s[1] == 's' && s[2] == 'p') | |
8922 | { | |
8923 | s += 3; | |
8924 | regno = SP; | |
8925 | } | |
8926 | else if (s[1] == 'g' && s[2] == 'p') | |
8927 | { | |
8928 | s += 3; | |
8929 | regno = GP; | |
8930 | } | |
8931 | else if (s[1] == 'a' && s[2] == 't') | |
8932 | { | |
8933 | s += 3; | |
8934 | regno = AT; | |
8935 | } | |
8936 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8937 | { | |
8938 | s += 4; | |
8939 | regno = KT0; | |
8940 | } | |
8941 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8942 | { | |
8943 | s += 4; | |
8944 | regno = KT1; | |
8945 | } | |
8946 | else | |
8947 | break; | |
8948 | } | |
8949 | ||
8950 | if (*s == ' ') | |
8951 | ++s; | |
8952 | if (args[1] != *s) | |
8953 | { | |
8954 | if (c == 'v' || c == 'w') | |
8955 | { | |
8956 | regno = mips16_to_32_reg_map[lastregno]; | |
8957 | s = s_reset; | |
8958 | args++; | |
8959 | } | |
8960 | } | |
8961 | ||
8962 | switch (c) | |
8963 | { | |
8964 | case 'x': | |
8965 | case 'y': | |
8966 | case 'z': | |
8967 | case 'v': | |
8968 | case 'w': | |
8969 | case 'Z': | |
8970 | regno = mips32_to_16_reg_map[regno]; | |
8971 | break; | |
8972 | ||
8973 | case '0': | |
8974 | if (regno != 0) | |
8975 | regno = ILLEGAL_REG; | |
8976 | break; | |
8977 | ||
8978 | case 'S': | |
8979 | if (regno != SP) | |
8980 | regno = ILLEGAL_REG; | |
8981 | break; | |
8982 | ||
8983 | case 'R': | |
8984 | if (regno != RA) | |
8985 | regno = ILLEGAL_REG; | |
8986 | break; | |
8987 | ||
8988 | case 'X': | |
8989 | case 'Y': | |
8990 | if (regno == AT && ! mips_opts.noat) | |
8991 | as_warn (_("used $at without \".set noat\"")); | |
8992 | break; | |
8993 | ||
8994 | default: | |
8995 | internalError (); | |
8996 | } | |
8997 | ||
8998 | if (regno == ILLEGAL_REG) | |
8999 | break; | |
9000 | ||
9001 | switch (c) | |
9002 | { | |
9003 | case 'x': | |
9004 | case 'v': | |
9005 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9006 | break; | |
9007 | case 'y': | |
9008 | case 'w': | |
9009 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9010 | break; | |
9011 | case 'z': | |
9012 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9013 | break; | |
9014 | case 'Z': | |
9015 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9016 | case '0': | |
9017 | case 'S': | |
9018 | case 'R': | |
9019 | break; | |
9020 | case 'X': | |
9021 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9022 | break; | |
9023 | case 'Y': | |
9024 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9025 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9026 | break; | |
9027 | default: | |
9028 | internalError (); | |
9029 | } | |
9030 | ||
9031 | lastregno = regno; | |
9032 | continue; | |
9033 | ||
9034 | case 'P': | |
9035 | if (strncmp (s, "$pc", 3) == 0) | |
9036 | { | |
9037 | s += 3; | |
9038 | continue; | |
9039 | } | |
9040 | break; | |
9041 | ||
9042 | case '<': | |
9043 | case '>': | |
9044 | case '[': | |
9045 | case ']': | |
9046 | case '4': | |
9047 | case '5': | |
9048 | case 'H': | |
9049 | case 'W': | |
9050 | case 'D': | |
9051 | case 'j': | |
9052 | case '8': | |
9053 | case 'V': | |
9054 | case 'C': | |
9055 | case 'U': | |
9056 | case 'k': | |
9057 | case 'K': | |
9058 | if (s[0] == '%' | |
9059 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9060 | { | |
9061 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9062 | and generate the appropriate reloc. If the text | |
9063 | inside %gprel is not a symbol name with an | |
9064 | optional offset, then we generate a normal reloc | |
9065 | and will probably fail later. */ | |
9066 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9067 | if (imm_expr.X_op == O_symbol) | |
9068 | { | |
9069 | mips16_ext = true; | |
f6688943 | 9070 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
9071 | s = expr_end; |
9072 | ip->use_extend = true; | |
9073 | ip->extend = 0; | |
9074 | continue; | |
9075 | } | |
9076 | } | |
9077 | else | |
9078 | { | |
9079 | /* Just pick up a normal expression. */ | |
9080 | my_getExpression (&imm_expr, s); | |
9081 | } | |
9082 | ||
9083 | if (imm_expr.X_op == O_register) | |
9084 | { | |
9085 | /* What we thought was an expression turned out to | |
9086 | be a register. */ | |
9087 | ||
9088 | if (s[0] == '(' && args[1] == '(') | |
9089 | { | |
9090 | /* It looks like the expression was omitted | |
9091 | before a register indirection, which means | |
9092 | that the expression is implicitly zero. We | |
9093 | still set up imm_expr, so that we handle | |
9094 | explicit extensions correctly. */ | |
9095 | imm_expr.X_op = O_constant; | |
9096 | imm_expr.X_add_number = 0; | |
f6688943 | 9097 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9098 | continue; |
9099 | } | |
9100 | ||
9101 | break; | |
9102 | } | |
9103 | ||
9104 | /* We need to relax this instruction. */ | |
f6688943 | 9105 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9106 | s = expr_end; |
9107 | continue; | |
9108 | ||
9109 | case 'p': | |
9110 | case 'q': | |
9111 | case 'A': | |
9112 | case 'B': | |
9113 | case 'E': | |
9114 | /* We use offset_reloc rather than imm_reloc for the PC | |
9115 | relative operands. This lets macros with both | |
9116 | immediate and address operands work correctly. */ | |
9117 | my_getExpression (&offset_expr, s); | |
9118 | ||
9119 | if (offset_expr.X_op == O_register) | |
9120 | break; | |
9121 | ||
9122 | /* We need to relax this instruction. */ | |
f6688943 | 9123 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9124 | s = expr_end; |
9125 | continue; | |
9126 | ||
9127 | case '6': /* break code */ | |
9128 | my_getExpression (&imm_expr, s); | |
9129 | check_absolute_expr (ip, &imm_expr); | |
9130 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9131 | { | |
9132 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9133 | ip->insn_mo->name, | |
9134 | (unsigned long) imm_expr.X_add_number); | |
9135 | imm_expr.X_add_number &= 0x3f; | |
9136 | } | |
9137 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9138 | imm_expr.X_op = O_absent; | |
9139 | s = expr_end; | |
9140 | continue; | |
9141 | ||
9142 | case 'a': /* 26 bit address */ | |
9143 | my_getExpression (&offset_expr, s); | |
9144 | s = expr_end; | |
f6688943 | 9145 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9146 | ip->insn_opcode <<= 16; |
9147 | continue; | |
9148 | ||
9149 | case 'l': /* register list for entry macro */ | |
9150 | case 'L': /* register list for exit macro */ | |
9151 | { | |
9152 | int mask; | |
9153 | ||
9154 | if (c == 'l') | |
9155 | mask = 0; | |
9156 | else | |
9157 | mask = 7 << 3; | |
9158 | while (*s != '\0') | |
9159 | { | |
9160 | int freg, reg1, reg2; | |
9161 | ||
9162 | while (*s == ' ' || *s == ',') | |
9163 | ++s; | |
9164 | if (*s != '$') | |
9165 | { | |
9166 | as_bad (_("can't parse register list")); | |
9167 | break; | |
9168 | } | |
9169 | ++s; | |
9170 | if (*s != 'f') | |
9171 | freg = 0; | |
9172 | else | |
9173 | { | |
9174 | freg = 1; | |
9175 | ++s; | |
9176 | } | |
9177 | reg1 = 0; | |
3882b010 | 9178 | while (ISDIGIT (*s)) |
252b5132 RH |
9179 | { |
9180 | reg1 *= 10; | |
9181 | reg1 += *s - '0'; | |
9182 | ++s; | |
9183 | } | |
9184 | if (*s == ' ') | |
9185 | ++s; | |
9186 | if (*s != '-') | |
9187 | reg2 = reg1; | |
9188 | else | |
9189 | { | |
9190 | ++s; | |
9191 | if (*s != '$') | |
9192 | break; | |
9193 | ++s; | |
9194 | if (freg) | |
9195 | { | |
9196 | if (*s == 'f') | |
9197 | ++s; | |
9198 | else | |
9199 | { | |
9200 | as_bad (_("invalid register list")); | |
9201 | break; | |
9202 | } | |
9203 | } | |
9204 | reg2 = 0; | |
3882b010 | 9205 | while (ISDIGIT (*s)) |
252b5132 RH |
9206 | { |
9207 | reg2 *= 10; | |
9208 | reg2 += *s - '0'; | |
9209 | ++s; | |
9210 | } | |
9211 | } | |
9212 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9213 | { | |
9214 | mask &= ~ (7 << 3); | |
9215 | mask |= 5 << 3; | |
9216 | } | |
9217 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9218 | { | |
9219 | mask &= ~ (7 << 3); | |
9220 | mask |= 6 << 3; | |
9221 | } | |
9222 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9223 | mask |= (reg2 - 3) << 3; | |
9224 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9225 | mask |= (reg2 - 15) << 1; | |
9226 | else if (reg1 == 31 && reg2 == 31) | |
9227 | mask |= 1; | |
9228 | else | |
9229 | { | |
9230 | as_bad (_("invalid register list")); | |
9231 | break; | |
9232 | } | |
9233 | } | |
9234 | /* The mask is filled in in the opcode table for the | |
9235 | benefit of the disassembler. We remove it before | |
9236 | applying the actual mask. */ | |
9237 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9238 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9239 | } | |
9240 | continue; | |
9241 | ||
9242 | case 'e': /* extend code */ | |
9243 | my_getExpression (&imm_expr, s); | |
9244 | check_absolute_expr (ip, &imm_expr); | |
9245 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9246 | { | |
9247 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9248 | ip->insn_mo->name, | |
9249 | (unsigned long) imm_expr.X_add_number); | |
9250 | imm_expr.X_add_number &= 0x7ff; | |
9251 | } | |
9252 | ip->insn_opcode |= imm_expr.X_add_number; | |
9253 | imm_expr.X_op = O_absent; | |
9254 | s = expr_end; | |
9255 | continue; | |
9256 | ||
9257 | default: | |
9258 | internalError (); | |
9259 | } | |
9260 | break; | |
9261 | } | |
9262 | ||
9263 | /* Args don't match. */ | |
9264 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9265 | strcmp (insn->name, insn[1].name) == 0) | |
9266 | { | |
9267 | ++insn; | |
9268 | s = argsstart; | |
9269 | continue; | |
9270 | } | |
9271 | ||
9272 | insn_error = _("illegal operands"); | |
9273 | ||
9274 | return; | |
9275 | } | |
9276 | } | |
9277 | ||
9278 | /* This structure holds information we know about a mips16 immediate | |
9279 | argument type. */ | |
9280 | ||
e972090a NC |
9281 | struct mips16_immed_operand |
9282 | { | |
252b5132 RH |
9283 | /* The type code used in the argument string in the opcode table. */ |
9284 | int type; | |
9285 | /* The number of bits in the short form of the opcode. */ | |
9286 | int nbits; | |
9287 | /* The number of bits in the extended form of the opcode. */ | |
9288 | int extbits; | |
9289 | /* The amount by which the short form is shifted when it is used; | |
9290 | for example, the sw instruction has a shift count of 2. */ | |
9291 | int shift; | |
9292 | /* The amount by which the short form is shifted when it is stored | |
9293 | into the instruction code. */ | |
9294 | int op_shift; | |
9295 | /* Non-zero if the short form is unsigned. */ | |
9296 | int unsp; | |
9297 | /* Non-zero if the extended form is unsigned. */ | |
9298 | int extu; | |
9299 | /* Non-zero if the value is PC relative. */ | |
9300 | int pcrel; | |
9301 | }; | |
9302 | ||
9303 | /* The mips16 immediate operand types. */ | |
9304 | ||
9305 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9306 | { | |
9307 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9308 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9309 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9310 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9311 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9312 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9313 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9314 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9315 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9316 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9317 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9318 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9319 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9320 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9321 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9322 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9323 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9324 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9325 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9326 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9327 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9328 | }; | |
9329 | ||
9330 | #define MIPS16_NUM_IMMED \ | |
9331 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9332 | ||
9333 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9334 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9335 | whether an extended value is needed; if one is needed, it sets | |
9336 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9337 | If SMALL is true, an unextended opcode was explicitly requested. | |
9338 | If EXT is true, an extended opcode was explicitly requested. If | |
9339 | WARN is true, warn if EXT does not match reality. */ | |
9340 | ||
9341 | static void | |
9342 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9343 | extend) | |
9344 | char *file; | |
9345 | unsigned int line; | |
9346 | int type; | |
9347 | offsetT val; | |
9348 | boolean warn; | |
9349 | boolean small; | |
9350 | boolean ext; | |
9351 | unsigned long *insn; | |
9352 | boolean *use_extend; | |
9353 | unsigned short *extend; | |
9354 | { | |
9355 | register const struct mips16_immed_operand *op; | |
9356 | int mintiny, maxtiny; | |
9357 | boolean needext; | |
9358 | ||
9359 | op = mips16_immed_operands; | |
9360 | while (op->type != type) | |
9361 | { | |
9362 | ++op; | |
9363 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9364 | } | |
9365 | ||
9366 | if (op->unsp) | |
9367 | { | |
9368 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9369 | { | |
9370 | mintiny = 1; | |
9371 | maxtiny = 1 << op->nbits; | |
9372 | } | |
9373 | else | |
9374 | { | |
9375 | mintiny = 0; | |
9376 | maxtiny = (1 << op->nbits) - 1; | |
9377 | } | |
9378 | } | |
9379 | else | |
9380 | { | |
9381 | mintiny = - (1 << (op->nbits - 1)); | |
9382 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9383 | } | |
9384 | ||
9385 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9386 | if (type == 'p' || type == 'q') | |
9387 | val /= 2; | |
9388 | ||
9389 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9390 | || val < (mintiny << op->shift) | |
9391 | || val > (maxtiny << op->shift)) | |
9392 | needext = true; | |
9393 | else | |
9394 | needext = false; | |
9395 | ||
9396 | if (warn && ext && ! needext) | |
beae10d5 KH |
9397 | as_warn_where (file, line, |
9398 | _("extended operand requested but not required")); | |
252b5132 RH |
9399 | if (small && needext) |
9400 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9401 | ||
9402 | if (small || (! ext && ! needext)) | |
9403 | { | |
9404 | int insnval; | |
9405 | ||
9406 | *use_extend = false; | |
9407 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9408 | insnval <<= op->op_shift; | |
9409 | *insn |= insnval; | |
9410 | } | |
9411 | else | |
9412 | { | |
9413 | long minext, maxext; | |
9414 | int extval; | |
9415 | ||
9416 | if (op->extu) | |
9417 | { | |
9418 | minext = 0; | |
9419 | maxext = (1 << op->extbits) - 1; | |
9420 | } | |
9421 | else | |
9422 | { | |
9423 | minext = - (1 << (op->extbits - 1)); | |
9424 | maxext = (1 << (op->extbits - 1)) - 1; | |
9425 | } | |
9426 | if (val < minext || val > maxext) | |
9427 | as_bad_where (file, line, | |
9428 | _("operand value out of range for instruction")); | |
9429 | ||
9430 | *use_extend = true; | |
9431 | if (op->extbits == 16) | |
9432 | { | |
9433 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9434 | val &= 0x1f; | |
9435 | } | |
9436 | else if (op->extbits == 15) | |
9437 | { | |
9438 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9439 | val &= 0xf; | |
9440 | } | |
9441 | else | |
9442 | { | |
9443 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9444 | val = 0; | |
9445 | } | |
9446 | ||
9447 | *extend = (unsigned short) extval; | |
9448 | *insn |= val; | |
9449 | } | |
9450 | } | |
9451 | \f | |
ad8d3bb3 TS |
9452 | static struct percent_op_match |
9453 | { | |
9454 | const char *str; | |
9455 | const enum small_ex_type type; | |
9456 | } percent_op[] = | |
9457 | { | |
ad8d3bb3 TS |
9458 | {"%lo", S_EX_LO}, |
9459 | #ifdef OBJ_ELF | |
394f9b3a TS |
9460 | {"%call_hi", S_EX_CALL_HI}, |
9461 | {"%call_lo", S_EX_CALL_LO}, | |
ad8d3bb3 TS |
9462 | {"%call16", S_EX_CALL16}, |
9463 | {"%got_disp", S_EX_GOT_DISP}, | |
9464 | {"%got_page", S_EX_GOT_PAGE}, | |
9465 | {"%got_ofst", S_EX_GOT_OFST}, | |
9466 | {"%got_hi", S_EX_GOT_HI}, | |
9467 | {"%got_lo", S_EX_GOT_LO}, | |
394f9b3a TS |
9468 | {"%got", S_EX_GOT}, |
9469 | {"%gp_rel", S_EX_GP_REL}, | |
9470 | {"%half", S_EX_HALF}, | |
ad8d3bb3 | 9471 | {"%highest", S_EX_HIGHEST}, |
394f9b3a TS |
9472 | {"%higher", S_EX_HIGHER}, |
9473 | {"%neg", S_EX_NEG}, | |
ad8d3bb3 | 9474 | #endif |
394f9b3a | 9475 | {"%hi", S_EX_HI} |
ad8d3bb3 TS |
9476 | }; |
9477 | ||
9478 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9479 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9480 | can be nested, this is handled by blanking the innermost, parsing the | |
9481 | rest by subsequent calls. */ | |
252b5132 RH |
9482 | |
9483 | static int | |
ad8d3bb3 TS |
9484 | my_getSmallParser (str, len, nestlevel) |
9485 | char **str; | |
9486 | unsigned int *len; | |
9487 | int *nestlevel; | |
252b5132 | 9488 | { |
ad8d3bb3 TS |
9489 | *len = 0; |
9490 | *str += strspn (*str, " \t"); | |
394f9b3a | 9491 | /* Check for expression in parentheses. */ |
ad8d3bb3 | 9492 | if (**str == '(') |
252b5132 | 9493 | { |
ad8d3bb3 TS |
9494 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9495 | char *e; | |
9496 | ||
9497 | /* Check for base register. */ | |
9498 | if (b[0] == '$') | |
9499 | { | |
9500 | if (strchr (b, ')') | |
9501 | && (e = b + strcspn (b, ") \t")) | |
9502 | && e - b > 1 && e - b < 4) | |
9503 | { | |
98d3f06f KH |
9504 | if ((e - b == 3 |
9505 | && ((b[1] == 'f' && b[2] == 'p') | |
9506 | || (b[1] == 's' && b[2] == 'p') | |
9507 | || (b[1] == 'g' && b[2] == 'p') | |
9508 | || (b[1] == 'a' && b[2] == 't') | |
9509 | || (ISDIGIT (b[1]) | |
9510 | && ISDIGIT (b[2])))) | |
9511 | || (ISDIGIT (b[1]))) | |
9512 | { | |
9513 | *len = strcspn (*str, ")") + 1; | |
9514 | return S_EX_REGISTER; | |
9515 | } | |
ad8d3bb3 TS |
9516 | } |
9517 | } | |
394f9b3a | 9518 | /* Check for percent_op (in parentheses). */ |
ad8d3bb3 TS |
9519 | else if (b[0] == '%') |
9520 | { | |
9521 | *str = b; | |
394f9b3a | 9522 | return my_getPercentOp (str, len, nestlevel); |
ad8d3bb3 | 9523 | } |
76b3015f | 9524 | |
394f9b3a TS |
9525 | /* Some other expression in the parentheses, which can contain |
9526 | parentheses itself. Attempt to find the matching one. */ | |
9527 | { | |
9528 | int pcnt = 1; | |
9529 | char *s; | |
9530 | ||
9531 | *len = 1; | |
9532 | for (s = *str + 1; *s && pcnt; s++, (*len)++) | |
9533 | { | |
9534 | if (*s == '(') | |
9535 | pcnt++; | |
9536 | else if (*s == ')') | |
9537 | pcnt--; | |
9538 | } | |
9539 | } | |
fb1b3232 | 9540 | } |
394f9b3a | 9541 | /* Check for percent_op (outside of parentheses). */ |
ad8d3bb3 | 9542 | else if (*str[0] == '%') |
394f9b3a TS |
9543 | return my_getPercentOp (str, len, nestlevel); |
9544 | ||
9545 | /* Any other expression. */ | |
9546 | return S_EX_NONE; | |
9547 | } | |
ad8d3bb3 | 9548 | |
394f9b3a TS |
9549 | static int |
9550 | my_getPercentOp (str, len, nestlevel) | |
9551 | char **str; | |
9552 | unsigned int *len; | |
9553 | int *nestlevel; | |
9554 | { | |
9555 | char *tmp = *str + 1; | |
9556 | unsigned int i = 0; | |
ad8d3bb3 | 9557 | |
394f9b3a TS |
9558 | while (ISALPHA (*tmp) || *tmp == '_') |
9559 | { | |
9560 | *tmp = TOLOWER (*tmp); | |
9561 | tmp++; | |
9562 | } | |
9563 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9564 | { | |
9565 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
98d3f06f | 9566 | i++; |
394f9b3a | 9567 | else |
ad8d3bb3 | 9568 | { |
394f9b3a | 9569 | int type = percent_op[i].type; |
ad8d3bb3 | 9570 | |
394f9b3a TS |
9571 | /* Only %hi and %lo are allowed for OldABI. */ |
9572 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9573 | return S_EX_NONE; | |
ad8d3bb3 | 9574 | |
394f9b3a TS |
9575 | *len = strlen (percent_op[i].str); |
9576 | (*nestlevel)++; | |
9577 | return type; | |
ad8d3bb3 | 9578 | } |
fb1b3232 | 9579 | } |
ad8d3bb3 TS |
9580 | return S_EX_NONE; |
9581 | } | |
9582 | ||
9583 | static int | |
9584 | my_getSmallExpression (ep, str) | |
9585 | expressionS *ep; | |
9586 | char *str; | |
9587 | { | |
9588 | static char *oldstr = NULL; | |
9589 | int c = S_EX_NONE; | |
9590 | int oldc; | |
394f9b3a | 9591 | int nestlevel = -1; |
ad8d3bb3 TS |
9592 | unsigned int len; |
9593 | ||
394f9b3a TS |
9594 | /* Don't update oldstr if the last call had nested percent_op's. We need |
9595 | it to parse the outer ones later. */ | |
ad8d3bb3 TS |
9596 | if (! oldstr) |
9597 | oldstr = str; | |
76b3015f | 9598 | |
ad8d3bb3 | 9599 | do |
fb1b3232 | 9600 | { |
ad8d3bb3 | 9601 | oldc = c; |
394f9b3a | 9602 | c = my_getSmallParser (&str, &len, &nestlevel); |
ad8d3bb3 TS |
9603 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
9604 | str += len; | |
fb1b3232 | 9605 | } |
ad8d3bb3 TS |
9606 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9607 | ||
394f9b3a | 9608 | if (nestlevel >= 0) |
fb1b3232 | 9609 | { |
394f9b3a TS |
9610 | /* A percent_op was encountered. Don't try to get an expression if |
9611 | it is already blanked out. */ | |
ad8d3bb3 TS |
9612 | if (*(str + strspn (str + 1, " )")) != ')') |
9613 | { | |
9614 | char save; | |
9615 | ||
394f9b3a | 9616 | /* Let my_getExpression() stop at the closing parenthesis. */ |
ad8d3bb3 TS |
9617 | save = *(str + len); |
9618 | *(str + len) = '\0'; | |
9619 | my_getExpression (ep, str); | |
9620 | *(str + len) = save; | |
9621 | } | |
394f9b3a | 9622 | if (nestlevel > 0) |
ad8d3bb3 | 9623 | { |
394f9b3a TS |
9624 | /* Blank out including the % sign and the proper matching |
9625 | parenthesis. */ | |
9626 | int pcnt = 1; | |
9627 | char *s = strrchr (oldstr, '%'); | |
9628 | char *end; | |
9629 | ||
9630 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) | |
9631 | { | |
9632 | if (*end == '(') | |
9633 | pcnt++; | |
9634 | else if (*end == ')') | |
9635 | pcnt--; | |
9636 | } | |
9637 | ||
9638 | memset (s, ' ', end - s); | |
ad8d3bb3 TS |
9639 | str = oldstr; |
9640 | } | |
9641 | else | |
394f9b3a TS |
9642 | expr_end = str + len; |
9643 | ||
ad8d3bb3 | 9644 | c = oldc; |
fb1b3232 | 9645 | } |
ad8d3bb3 | 9646 | else if (c == S_EX_NONE) |
fb1b3232 | 9647 | { |
ad8d3bb3 | 9648 | my_getExpression (ep, str); |
fb1b3232 | 9649 | } |
ad8d3bb3 | 9650 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9651 | { |
ad8d3bb3 TS |
9652 | ep->X_op = O_constant; |
9653 | expr_end = str; | |
9654 | ep->X_add_symbol = NULL; | |
9655 | ep->X_op_symbol = NULL; | |
9656 | ep->X_add_number = 0; | |
fb1b3232 | 9657 | } |
fb1b3232 TS |
9658 | else |
9659 | { | |
98d3f06f | 9660 | as_fatal (_("internal error")); |
fb1b3232 | 9661 | } |
252b5132 | 9662 | |
394f9b3a TS |
9663 | if (nestlevel <= 0) |
9664 | /* All percent_op's have been handled. */ | |
ad8d3bb3 | 9665 | oldstr = NULL; |
fb1b3232 | 9666 | |
fb1b3232 | 9667 | return c; |
252b5132 RH |
9668 | } |
9669 | ||
9670 | static void | |
9671 | my_getExpression (ep, str) | |
9672 | expressionS *ep; | |
9673 | char *str; | |
9674 | { | |
9675 | char *save_in; | |
98aa84af | 9676 | valueT val; |
252b5132 RH |
9677 | |
9678 | save_in = input_line_pointer; | |
9679 | input_line_pointer = str; | |
9680 | expression (ep); | |
9681 | expr_end = input_line_pointer; | |
9682 | input_line_pointer = save_in; | |
9683 | ||
9684 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9685 | then we bump the value of the symbol by 1 since that is how other | |
9686 | text symbols are handled. We don't bother to handle complex | |
9687 | expressions, just `.' plus or minus a constant. */ | |
9688 | if (mips_opts.mips16 | |
9689 | && ep->X_op == O_symbol | |
9690 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9691 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9692 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9693 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9694 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9695 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9696 | } |
9697 | ||
9698 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9699 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9700 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9701 | returned, or NULL on OK. */ |
9702 | ||
9703 | char * | |
9704 | md_atof (type, litP, sizeP) | |
9705 | int type; | |
9706 | char *litP; | |
9707 | int *sizeP; | |
9708 | { | |
9709 | int prec; | |
9710 | LITTLENUM_TYPE words[4]; | |
9711 | char *t; | |
9712 | int i; | |
9713 | ||
9714 | switch (type) | |
9715 | { | |
9716 | case 'f': | |
9717 | prec = 2; | |
9718 | break; | |
9719 | ||
9720 | case 'd': | |
9721 | prec = 4; | |
9722 | break; | |
9723 | ||
9724 | default: | |
9725 | *sizeP = 0; | |
9726 | return _("bad call to md_atof"); | |
9727 | } | |
9728 | ||
9729 | t = atof_ieee (input_line_pointer, type, words); | |
9730 | if (t) | |
9731 | input_line_pointer = t; | |
9732 | ||
9733 | *sizeP = prec * 2; | |
9734 | ||
9735 | if (! target_big_endian) | |
9736 | { | |
9737 | for (i = prec - 1; i >= 0; i--) | |
9738 | { | |
9739 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9740 | litP += 2; | |
9741 | } | |
9742 | } | |
9743 | else | |
9744 | { | |
9745 | for (i = 0; i < prec; i++) | |
9746 | { | |
9747 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9748 | litP += 2; | |
9749 | } | |
9750 | } | |
bdaaa2e1 | 9751 | |
252b5132 RH |
9752 | return NULL; |
9753 | } | |
9754 | ||
9755 | void | |
9756 | md_number_to_chars (buf, val, n) | |
9757 | char *buf; | |
9758 | valueT val; | |
9759 | int n; | |
9760 | { | |
9761 | if (target_big_endian) | |
9762 | number_to_chars_bigendian (buf, val, n); | |
9763 | else | |
9764 | number_to_chars_littleendian (buf, val, n); | |
9765 | } | |
9766 | \f | |
ae948b86 | 9767 | #ifdef OBJ_ELF |
e013f690 TS |
9768 | static int support_64bit_objects(void) |
9769 | { | |
9770 | const char **list, **l; | |
9771 | ||
9772 | list = bfd_target_list (); | |
9773 | for (l = list; *l != NULL; l++) | |
9774 | #ifdef TE_TMIPS | |
9775 | /* This is traditional mips */ | |
9776 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9777 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9778 | #else | |
9779 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9780 | || strcmp (*l, "elf64-littlemips") == 0) | |
9781 | #endif | |
9782 | break; | |
9783 | free (list); | |
9784 | return (*l != NULL); | |
9785 | } | |
ae948b86 | 9786 | #endif /* OBJ_ELF */ |
e013f690 | 9787 | |
39c0a331 | 9788 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 9789 | |
e972090a NC |
9790 | struct option md_longopts[] = |
9791 | { | |
252b5132 RH |
9792 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
9793 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9794 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9795 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9796 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9797 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9798 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
9799 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
9800 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
9801 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
9802 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
9803 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
9804 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
9805 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
9806 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
9807 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 9808 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 9809 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
9810 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9811 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 9812 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
9813 | {"break", no_argument, NULL, OPTION_BREAK}, |
9814 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 9815 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 9816 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 9817 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 9818 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 9819 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 9820 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 9821 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 9822 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 9823 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 9824 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
ae948b86 | 9825 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16) |
6b76fefe | 9826 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
ae948b86 TS |
9827 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
9828 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
9829 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 9830 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 9831 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 9832 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 9833 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 9834 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 9835 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 9836 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 9837 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 9838 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
ae948b86 TS |
9839 | #define OPTION_MCPU (OPTION_MD_BASE + 23) |
9840 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
9841 | #define OPTION_M4650 (OPTION_MD_BASE + 24) | |
9842 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
9843 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
9844 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
9845 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
9846 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9847 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
9848 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
9849 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
9850 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9851 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
9852 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
9853 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
9854 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9855 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
9856 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
9857 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
9858 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
9859 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
9860 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
9861 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
9862 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
156c2f8b | 9863 | #ifdef OBJ_ELF |
1f25f5d3 | 9864 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) |
156c2f8b | 9865 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
9866 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
9867 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 9868 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 9869 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 9870 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 9871 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
9872 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
9873 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
9874 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 9875 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 9876 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 9877 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 9878 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 9879 | {"64", no_argument, NULL, OPTION_64}, |
ae948b86 | 9880 | #endif /* OBJ_ELF */ |
252b5132 RH |
9881 | {NULL, no_argument, NULL, 0} |
9882 | }; | |
156c2f8b | 9883 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
9884 | |
9885 | int | |
9886 | md_parse_option (c, arg) | |
9887 | int c; | |
9888 | char *arg; | |
9889 | { | |
9890 | switch (c) | |
9891 | { | |
119d663a NC |
9892 | case OPTION_CONSTRUCT_FLOATS: |
9893 | mips_disable_float_construction = 0; | |
9894 | break; | |
bdaaa2e1 | 9895 | |
119d663a NC |
9896 | case OPTION_NO_CONSTRUCT_FLOATS: |
9897 | mips_disable_float_construction = 1; | |
9898 | break; | |
bdaaa2e1 | 9899 | |
252b5132 RH |
9900 | case OPTION_TRAP: |
9901 | mips_trap = 1; | |
9902 | break; | |
9903 | ||
9904 | case OPTION_BREAK: | |
9905 | mips_trap = 0; | |
9906 | break; | |
9907 | ||
9908 | case OPTION_EB: | |
9909 | target_big_endian = 1; | |
9910 | break; | |
9911 | ||
9912 | case OPTION_EL: | |
9913 | target_big_endian = 0; | |
9914 | break; | |
9915 | ||
39c0a331 L |
9916 | case 'n': |
9917 | warn_nops = 1; | |
9918 | break; | |
9919 | ||
252b5132 RH |
9920 | case 'O': |
9921 | if (arg && arg[1] == '0') | |
9922 | mips_optimize = 1; | |
9923 | else | |
9924 | mips_optimize = 2; | |
9925 | break; | |
9926 | ||
9927 | case 'g': | |
9928 | if (arg == NULL) | |
9929 | mips_debug = 2; | |
9930 | else | |
9931 | mips_debug = atoi (arg); | |
9932 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9933 | optimizations which limit full symbolic debugging. We take | |
9934 | that to be equivalent to -O0. */ | |
9935 | if (mips_debug == 2) | |
9936 | mips_optimize = 1; | |
9937 | break; | |
9938 | ||
9939 | case OPTION_MIPS1: | |
e7af610e | 9940 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
9941 | break; |
9942 | ||
9943 | case OPTION_MIPS2: | |
e7af610e | 9944 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
9945 | break; |
9946 | ||
9947 | case OPTION_MIPS3: | |
e7af610e | 9948 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
9949 | break; |
9950 | ||
9951 | case OPTION_MIPS4: | |
e7af610e NC |
9952 | mips_opts.isa = ISA_MIPS4; |
9953 | break; | |
9954 | ||
84ea6cf2 NC |
9955 | case OPTION_MIPS5: |
9956 | mips_opts.isa = ISA_MIPS5; | |
9957 | break; | |
9958 | ||
e7af610e NC |
9959 | case OPTION_MIPS32: |
9960 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
9961 | break; |
9962 | ||
84ea6cf2 NC |
9963 | case OPTION_MIPS64: |
9964 | mips_opts.isa = ISA_MIPS64; | |
9965 | break; | |
9966 | ||
ec68c924 EC |
9967 | case OPTION_MTUNE: |
9968 | case OPTION_MARCH: | |
252b5132 RH |
9969 | case OPTION_MCPU: |
9970 | { | |
ec68c924 EC |
9971 | int cpu = CPU_UNKNOWN; |
9972 | ||
e7af610e | 9973 | /* Identify the processor type. */ |
ec68c924 | 9974 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 9975 | { |
e7af610e | 9976 | const struct mips_cpu_info *ci; |
252b5132 | 9977 | |
e7af610e NC |
9978 | ci = mips_cpu_info_from_name (arg); |
9979 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
9980 | { |
9981 | switch (c) | |
9982 | { | |
9983 | case OPTION_MTUNE: | |
9984 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
9985 | break; | |
9986 | case OPTION_MARCH: | |
9987 | as_fatal (_("invalid architecture -march=%s"), arg); | |
9988 | break; | |
9989 | case OPTION_MCPU: | |
9990 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
9991 | break; | |
9992 | } | |
9993 | } | |
e7af610e | 9994 | else |
98d3f06f | 9995 | cpu = ci->cpu; |
ec68c924 EC |
9996 | } |
9997 | ||
9998 | switch (c) | |
9999 | { | |
10000 | case OPTION_MTUNE: | |
6dce9e24 | 10001 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
98d3f06f KH |
10002 | as_warn (_("A different -mtune= was already specified, is now " |
10003 | "-mtune=%s"), arg); | |
ec68c924 EC |
10004 | mips_tune = cpu; |
10005 | break; | |
10006 | case OPTION_MARCH: | |
6dce9e24 | 10007 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
98d3f06f KH |
10008 | as_warn (_("A different -march= was already specified, is now " |
10009 | "-march=%s"), arg); | |
ec68c924 EC |
10010 | mips_arch = cpu; |
10011 | break; | |
10012 | case OPTION_MCPU: | |
6dce9e24 | 10013 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
98d3f06f KH |
10014 | as_warn (_("A different -mcpu= was already specified, is now " |
10015 | "-mcpu=%s"), arg); | |
ec68c924 | 10016 | mips_cpu = cpu; |
252b5132 RH |
10017 | } |
10018 | } | |
10019 | break; | |
10020 | ||
10021 | case OPTION_M4650: | |
6dce9e24 TS |
10022 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
10023 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
98d3f06f KH |
10024 | as_warn (_("A different -march= or -mtune= was already specified, " |
10025 | "is now -m4650")); | |
ec68c924 EC |
10026 | mips_arch = CPU_R4650; |
10027 | mips_tune = CPU_R4650; | |
252b5132 RH |
10028 | break; |
10029 | ||
10030 | case OPTION_NO_M4650: | |
10031 | break; | |
10032 | ||
10033 | case OPTION_M4010: | |
6dce9e24 TS |
10034 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
10035 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
98d3f06f KH |
10036 | as_warn (_("A different -march= or -mtune= was already specified, " |
10037 | "is now -m4010")); | |
ec68c924 EC |
10038 | mips_arch = CPU_R4010; |
10039 | mips_tune = CPU_R4010; | |
252b5132 RH |
10040 | break; |
10041 | ||
10042 | case OPTION_NO_M4010: | |
10043 | break; | |
10044 | ||
10045 | case OPTION_M4100: | |
6dce9e24 TS |
10046 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
10047 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
98d3f06f KH |
10048 | as_warn (_("A different -march= or -mtune= was already specified, " |
10049 | "is now -m4100")); | |
ec68c924 EC |
10050 | mips_arch = CPU_VR4100; |
10051 | mips_tune = CPU_VR4100; | |
252b5132 RH |
10052 | break; |
10053 | ||
10054 | case OPTION_NO_M4100: | |
10055 | break; | |
10056 | ||
252b5132 | 10057 | case OPTION_M3900: |
6dce9e24 TS |
10058 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
10059 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
98d3f06f KH |
10060 | as_warn (_("A different -march= or -mtune= was already specified, " |
10061 | "is now -m3900")); | |
ec68c924 EC |
10062 | mips_arch = CPU_R3900; |
10063 | mips_tune = CPU_R3900; | |
252b5132 | 10064 | break; |
bdaaa2e1 | 10065 | |
252b5132 RH |
10066 | case OPTION_NO_M3900: |
10067 | break; | |
10068 | ||
10069 | case OPTION_MIPS16: | |
10070 | mips_opts.mips16 = 1; | |
10071 | mips_no_prev_insn (false); | |
10072 | break; | |
10073 | ||
10074 | case OPTION_NO_MIPS16: | |
10075 | mips_opts.mips16 = 0; | |
10076 | mips_no_prev_insn (false); | |
10077 | break; | |
10078 | ||
1f25f5d3 CD |
10079 | case OPTION_MIPS3D: |
10080 | mips_opts.ase_mips3d = 1; | |
10081 | break; | |
10082 | ||
10083 | case OPTION_NO_MIPS3D: | |
10084 | mips_opts.ase_mips3d = 0; | |
10085 | break; | |
10086 | ||
252b5132 RH |
10087 | case OPTION_MEMBEDDED_PIC: |
10088 | mips_pic = EMBEDDED_PIC; | |
10089 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10090 | { | |
10091 | as_bad (_("-G may not be used with embedded PIC code")); | |
10092 | return 0; | |
10093 | } | |
10094 | g_switch_value = 0x7fffffff; | |
10095 | break; | |
10096 | ||
0f074f60 | 10097 | #ifdef OBJ_ELF |
252b5132 RH |
10098 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10099 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10100 | intended to be compatible with Irix 5. */ | |
10101 | case OPTION_CALL_SHARED: | |
10102 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10103 | { | |
10104 | as_bad (_("-call_shared is supported only for ELF format")); | |
10105 | return 0; | |
10106 | } | |
10107 | mips_pic = SVR4_PIC; | |
10108 | if (g_switch_seen && g_switch_value != 0) | |
10109 | { | |
10110 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10111 | return 0; | |
10112 | } | |
10113 | g_switch_value = 0; | |
10114 | break; | |
10115 | ||
10116 | case OPTION_NON_SHARED: | |
10117 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10118 | { | |
10119 | as_bad (_("-non_shared is supported only for ELF format")); | |
10120 | return 0; | |
10121 | } | |
10122 | mips_pic = NO_PIC; | |
10123 | break; | |
10124 | ||
10125 | /* The -xgot option tells the assembler to use 32 offsets when | |
10126 | accessing the got in SVR4_PIC mode. It is for Irix | |
10127 | compatibility. */ | |
10128 | case OPTION_XGOT: | |
10129 | mips_big_got = 1; | |
10130 | break; | |
0f074f60 | 10131 | #endif /* OBJ_ELF */ |
252b5132 RH |
10132 | |
10133 | case 'G': | |
10134 | if (! USE_GLOBAL_POINTER_OPT) | |
10135 | { | |
10136 | as_bad (_("-G is not supported for this configuration")); | |
10137 | return 0; | |
10138 | } | |
10139 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10140 | { | |
10141 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10142 | return 0; | |
10143 | } | |
10144 | else | |
10145 | g_switch_value = atoi (arg); | |
10146 | g_switch_seen = 1; | |
10147 | break; | |
10148 | ||
0f074f60 | 10149 | #ifdef OBJ_ELF |
34ba82a8 TS |
10150 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10151 | and -mabi=64. */ | |
252b5132 | 10152 | case OPTION_32: |
34ba82a8 TS |
10153 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10154 | { | |
10155 | as_bad (_("-32 is supported for ELF format only")); | |
10156 | return 0; | |
10157 | } | |
a325df1d | 10158 | mips_opts.abi = O32_ABI; |
252b5132 RH |
10159 | break; |
10160 | ||
e013f690 | 10161 | case OPTION_N32: |
34ba82a8 TS |
10162 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10163 | { | |
10164 | as_bad (_("-n32 is supported for ELF format only")); | |
10165 | return 0; | |
10166 | } | |
a325df1d | 10167 | mips_opts.abi = N32_ABI; |
e013f690 | 10168 | break; |
252b5132 | 10169 | |
e013f690 | 10170 | case OPTION_64: |
34ba82a8 TS |
10171 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10172 | { | |
10173 | as_bad (_("-64 is supported for ELF format only")); | |
10174 | return 0; | |
10175 | } | |
a325df1d | 10176 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10177 | if (! support_64bit_objects()) |
10178 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10179 | break; |
ae948b86 | 10180 | #endif /* OBJ_ELF */ |
252b5132 | 10181 | |
c97ef257 | 10182 | case OPTION_GP32: |
a325df1d TS |
10183 | file_mips_gp32 = 1; |
10184 | if (mips_opts.abi != O32_ABI) | |
10185 | mips_opts.abi = NO_ABI; | |
c97ef257 AH |
10186 | break; |
10187 | ||
10188 | case OPTION_GP64: | |
a325df1d TS |
10189 | file_mips_gp32 = 0; |
10190 | if (mips_opts.abi == O32_ABI) | |
10191 | mips_opts.abi = NO_ABI; | |
c97ef257 | 10192 | break; |
252b5132 | 10193 | |
ca4e0257 | 10194 | case OPTION_FP32: |
a325df1d TS |
10195 | file_mips_fp32 = 1; |
10196 | if (mips_opts.abi != O32_ABI) | |
10197 | mips_opts.abi = NO_ABI; | |
ca4e0257 RS |
10198 | break; |
10199 | ||
ae948b86 | 10200 | #ifdef OBJ_ELF |
252b5132 | 10201 | case OPTION_MABI: |
34ba82a8 TS |
10202 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10203 | { | |
10204 | as_bad (_("-mabi is supported for ELF format only")); | |
10205 | return 0; | |
10206 | } | |
e013f690 | 10207 | if (strcmp (arg, "32") == 0) |
a325df1d | 10208 | mips_opts.abi = O32_ABI; |
e013f690 | 10209 | else if (strcmp (arg, "o64") == 0) |
a325df1d | 10210 | mips_opts.abi = O64_ABI; |
e013f690 | 10211 | else if (strcmp (arg, "n32") == 0) |
a325df1d | 10212 | mips_opts.abi = N32_ABI; |
e013f690 TS |
10213 | else if (strcmp (arg, "64") == 0) |
10214 | { | |
a325df1d | 10215 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10216 | if (! support_64bit_objects()) |
10217 | as_fatal (_("No compiled in support for 64 bit object file " | |
10218 | "format")); | |
10219 | } | |
10220 | else if (strcmp (arg, "eabi") == 0) | |
a325df1d | 10221 | mips_opts.abi = EABI_ABI; |
e013f690 | 10222 | else |
da0e507f TS |
10223 | { |
10224 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10225 | return 0; | |
10226 | } | |
252b5132 | 10227 | break; |
e013f690 | 10228 | #endif /* OBJ_ELF */ |
252b5132 | 10229 | |
6b76fefe CM |
10230 | case OPTION_M7000_HILO_FIX: |
10231 | mips_7000_hilo_fix = true; | |
10232 | break; | |
10233 | ||
10234 | case OPTION_NO_M7000_HILO_FIX: | |
10235 | mips_7000_hilo_fix = false; | |
10236 | break; | |
10237 | ||
252b5132 RH |
10238 | default: |
10239 | return 0; | |
10240 | } | |
10241 | ||
10242 | return 1; | |
10243 | } | |
10244 | ||
252b5132 RH |
10245 | static void |
10246 | show (stream, string, col_p, first_p) | |
10247 | FILE *stream; | |
10248 | char *string; | |
10249 | int *col_p; | |
10250 | int *first_p; | |
10251 | { | |
10252 | if (*first_p) | |
10253 | { | |
10254 | fprintf (stream, "%24s", ""); | |
10255 | *col_p = 24; | |
10256 | } | |
10257 | else | |
10258 | { | |
10259 | fprintf (stream, ", "); | |
10260 | *col_p += 2; | |
10261 | } | |
10262 | ||
10263 | if (*col_p + strlen (string) > 72) | |
10264 | { | |
10265 | fprintf (stream, "\n%24s", ""); | |
10266 | *col_p = 24; | |
10267 | } | |
10268 | ||
10269 | fprintf (stream, "%s", string); | |
10270 | *col_p += strlen (string); | |
10271 | ||
10272 | *first_p = 0; | |
10273 | } | |
10274 | ||
252b5132 RH |
10275 | void |
10276 | md_show_usage (stream) | |
10277 | FILE *stream; | |
10278 | { | |
10279 | int column, first; | |
10280 | ||
beae10d5 | 10281 | fprintf (stream, _("\ |
252b5132 RH |
10282 | MIPS options:\n\ |
10283 | -membedded-pic generate embedded position independent code\n\ | |
10284 | -EB generate big endian output\n\ | |
10285 | -EL generate little endian output\n\ | |
9a41af64 | 10286 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
10287 | -G NUM allow referencing objects up to NUM bytes\n\ |
10288 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 10289 | fprintf (stream, _("\ |
252b5132 RH |
10290 | -mips1 generate MIPS ISA I instructions\n\ |
10291 | -mips2 generate MIPS ISA II instructions\n\ | |
10292 | -mips3 generate MIPS ISA III instructions\n\ | |
10293 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 10294 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 10295 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 10296 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 10297 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
10298 | |
10299 | first = 1; | |
10300 | ||
10301 | show (stream, "2000", &column, &first); | |
10302 | show (stream, "3000", &column, &first); | |
10303 | show (stream, "3900", &column, &first); | |
10304 | show (stream, "4000", &column, &first); | |
10305 | show (stream, "4010", &column, &first); | |
10306 | show (stream, "4100", &column, &first); | |
10307 | show (stream, "4111", &column, &first); | |
10308 | show (stream, "4300", &column, &first); | |
10309 | show (stream, "4400", &column, &first); | |
10310 | show (stream, "4600", &column, &first); | |
10311 | show (stream, "4650", &column, &first); | |
10312 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
10313 | show (stream, "5200", &column, &first); |
10314 | show (stream, "5230", &column, &first); | |
10315 | show (stream, "5231", &column, &first); | |
10316 | show (stream, "5261", &column, &first); | |
10317 | show (stream, "5721", &column, &first); | |
252b5132 RH |
10318 | show (stream, "6000", &column, &first); |
10319 | show (stream, "8000", &column, &first); | |
10320 | show (stream, "10000", &column, &first); | |
d1cf510e | 10321 | show (stream, "12000", &column, &first); |
2e4acd24 | 10322 | show (stream, "sb1", &column, &first); |
252b5132 RH |
10323 | fputc ('\n', stream); |
10324 | ||
10325 | fprintf (stream, _("\ | |
ec68c924 | 10326 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
10327 | -no-mCPU don't generate code specific to CPU.\n\ |
10328 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
10329 | ||
10330 | first = 1; | |
10331 | ||
10332 | show (stream, "3900", &column, &first); | |
10333 | show (stream, "4010", &column, &first); | |
10334 | show (stream, "4100", &column, &first); | |
10335 | show (stream, "4650", &column, &first); | |
10336 | fputc ('\n', stream); | |
10337 | ||
beae10d5 | 10338 | fprintf (stream, _("\ |
252b5132 RH |
10339 | -mips16 generate mips16 instructions\n\ |
10340 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 10341 | fprintf (stream, _("\ |
ca4e0257 RS |
10342 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
10343 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
10344 | -O0 remove unneeded NOPs, do not swap branches\n\ |
10345 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 10346 | -n warn about NOPs generated from macros\n\ |
119d663a | 10347 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
10348 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
10349 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
10350 | #ifdef OBJ_ELF | |
beae10d5 | 10351 | fprintf (stream, _("\ |
252b5132 RH |
10352 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
10353 | -non_shared do not generate position independent code\n\ | |
10354 | -xgot assume a 32 bit GOT\n\ | |
34ba82a8 TS |
10355 | -mabi=ABI create ABI conformant object file for:\n")); |
10356 | ||
10357 | first = 1; | |
10358 | ||
10359 | show (stream, "32", &column, &first); | |
10360 | show (stream, "o64", &column, &first); | |
10361 | show (stream, "n32", &column, &first); | |
10362 | show (stream, "64", &column, &first); | |
10363 | show (stream, "eabi", &column, &first); | |
80cc45a5 | 10364 | |
34ba82a8 TS |
10365 | fputc ('\n', stream); |
10366 | ||
10367 | fprintf (stream, _("\ | |
e013f690 TS |
10368 | -32 create o32 ABI object file (default)\n\ |
10369 | -n32 create n32 ABI object file\n\ | |
10370 | -64 create 64 ABI object file\n")); | |
252b5132 RH |
10371 | #endif |
10372 | } | |
10373 | \f | |
10374 | void | |
10375 | mips_init_after_args () | |
10376 | { | |
10377 | /* initialize opcodes */ | |
10378 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10379 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10380 | } |
10381 | ||
10382 | long | |
10383 | md_pcrel_from (fixP) | |
10384 | fixS *fixP; | |
10385 | { | |
10386 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10387 | && fixP->fx_addsy != (symbolS *) NULL | |
10388 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10389 | { | |
6478892d TS |
10390 | /* This makes a branch to an undefined symbol be a branch to the |
10391 | current location. */ | |
cb56d3d3 | 10392 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 10393 | return 4; |
cb56d3d3 | 10394 | else |
6478892d | 10395 | return 1; |
252b5132 RH |
10396 | } |
10397 | ||
10398 | /* return the address of the delay slot */ | |
10399 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10400 | } | |
10401 | ||
252b5132 RH |
10402 | /* This is called before the symbol table is processed. In order to |
10403 | work with gcc when using mips-tfile, we must keep all local labels. | |
10404 | However, in other cases, we want to discard them. If we were | |
10405 | called with -g, but we didn't see any debugging information, it may | |
10406 | mean that gcc is smuggling debugging information through to | |
10407 | mips-tfile, in which case we must generate all local labels. */ | |
10408 | ||
10409 | void | |
10410 | mips_frob_file_before_adjust () | |
10411 | { | |
10412 | #ifndef NO_ECOFF_DEBUGGING | |
10413 | if (ECOFF_DEBUGGING | |
10414 | && mips_debug != 0 | |
10415 | && ! ecoff_debugging_seen) | |
10416 | flag_keep_locals = 1; | |
10417 | #endif | |
10418 | } | |
10419 | ||
10420 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10421 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10422 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10423 | explicit use of the %hi modifier. */ | |
10424 | ||
10425 | void | |
10426 | mips_frob_file () | |
10427 | { | |
10428 | struct mips_hi_fixup *l; | |
10429 | ||
10430 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10431 | { | |
10432 | segment_info_type *seginfo; | |
10433 | int pass; | |
10434 | ||
10435 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10436 | ||
10437 | /* Check quickly whether the next fixup happens to be a matching | |
10438 | %lo. */ | |
10439 | if (l->fixp->fx_next != NULL | |
10440 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10441 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10442 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10443 | continue; | |
10444 | ||
10445 | /* Look through the fixups for this segment for a matching %lo. | |
10446 | When we find one, move the %hi just in front of it. We do | |
10447 | this in two passes. In the first pass, we try to find a | |
10448 | unique %lo. In the second pass, we permit multiple %hi | |
10449 | relocs for a single %lo (this is a GNU extension). */ | |
10450 | seginfo = seg_info (l->seg); | |
10451 | for (pass = 0; pass < 2; pass++) | |
10452 | { | |
10453 | fixS *f, *prev; | |
10454 | ||
10455 | prev = NULL; | |
10456 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10457 | { | |
10458 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10459 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10460 | && f->fx_addsy == l->fixp->fx_addsy | |
10461 | && f->fx_offset == l->fixp->fx_offset | |
10462 | && (pass == 1 | |
10463 | || prev == NULL | |
10464 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10465 | || prev->fx_addsy != f->fx_addsy | |
10466 | || prev->fx_offset != f->fx_offset)) | |
10467 | { | |
10468 | fixS **pf; | |
10469 | ||
10470 | /* Move l->fixp before f. */ | |
10471 | for (pf = &seginfo->fix_root; | |
10472 | *pf != l->fixp; | |
10473 | pf = &(*pf)->fx_next) | |
10474 | assert (*pf != NULL); | |
10475 | ||
10476 | *pf = l->fixp->fx_next; | |
10477 | ||
10478 | l->fixp->fx_next = f; | |
10479 | if (prev == NULL) | |
10480 | seginfo->fix_root = l->fixp; | |
10481 | else | |
10482 | prev->fx_next = l->fixp; | |
10483 | ||
10484 | break; | |
10485 | } | |
10486 | ||
10487 | prev = f; | |
10488 | } | |
10489 | ||
10490 | if (f != NULL) | |
10491 | break; | |
10492 | ||
10493 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10494 | can leave a %hi without a %lo. */ | |
10495 | if (pass == 1) | |
10496 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10497 | _("Unmatched %%hi reloc")); | |
10498 | #endif | |
10499 | } | |
10500 | } | |
10501 | } | |
10502 | ||
10503 | /* When generating embedded PIC code we need to use a special | |
10504 | relocation to represent the difference of two symbols in the .text | |
10505 | section (switch tables use a difference of this sort). See | |
10506 | include/coff/mips.h for details. This macro checks whether this | |
10507 | fixup requires the special reloc. */ | |
10508 | #define SWITCH_TABLE(fixp) \ | |
10509 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10510 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10511 | && (fixp)->fx_addsy != NULL \ |
10512 | && (fixp)->fx_subsy != NULL \ | |
10513 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10514 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10515 | ||
10516 | /* When generating embedded PIC code we must keep all PC relative | |
10517 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10518 | to keep relocations for switch table entries. |
10519 | ||
10520 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10521 | We have to prevent gas from dropping them. */ | |
252b5132 | 10522 | |
252b5132 RH |
10523 | int |
10524 | mips_force_relocation (fixp) | |
10525 | fixS *fixp; | |
10526 | { | |
10527 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10528 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10529 | return 1; | |
10530 | ||
f6688943 TS |
10531 | if (HAVE_NEWABI |
10532 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10533 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10534 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10535 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10536 | return 1; | |
10537 | ||
252b5132 RH |
10538 | return (mips_pic == EMBEDDED_PIC |
10539 | && (fixp->fx_pcrel | |
10540 | || SWITCH_TABLE (fixp) | |
10541 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10542 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10543 | } | |
10544 | ||
add55e1f RS |
10545 | #ifdef OBJ_ELF |
10546 | static int | |
10547 | mips_need_elf_addend_fixup (fixP) | |
10548 | fixS *fixP; | |
10549 | { | |
2d2bf3e0 CD |
10550 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
10551 | return 1; | |
b25a253c CD |
10552 | if (mips_pic == EMBEDDED_PIC |
10553 | && S_IS_WEAK (fixP->fx_addsy)) | |
10554 | return 1; | |
10555 | if (mips_pic != EMBEDDED_PIC | |
10556 | && (S_IS_WEAK (fixP->fx_addsy) | |
10557 | || S_IS_EXTERN (fixP->fx_addsy)) | |
2d2bf3e0 CD |
10558 | && !S_IS_COMMON (fixP->fx_addsy)) |
10559 | return 1; | |
10560 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
10561 | && (((bfd_get_section_flags (stdoutput, | |
10562 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10563 | & SEC_LINK_ONCE) != 0) | |
10564 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10565 | ".gnu.linkonce", | |
10566 | sizeof (".gnu.linkonce") - 1))) | |
10567 | return 1; | |
10568 | return 0; | |
add55e1f RS |
10569 | } |
10570 | #endif | |
10571 | ||
252b5132 RH |
10572 | /* Apply a fixup to the object file. */ |
10573 | ||
94f592af NC |
10574 | void |
10575 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 10576 | fixS *fixP; |
98d3f06f | 10577 | valueT *valP; |
94f592af | 10578 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 10579 | { |
874e8986 | 10580 | bfd_byte *buf; |
98aa84af AM |
10581 | long insn; |
10582 | valueT value; | |
252b5132 RH |
10583 | |
10584 | assert (fixP->fx_size == 4 | |
10585 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10586 | || fixP->fx_r_type == BFD_RELOC_32 |
10587 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10588 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10589 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10590 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 10591 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 10592 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 10593 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10594 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10595 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10596 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10597 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10598 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10599 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10600 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 RH |
10601 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10602 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
10603 | ||
98d3f06f | 10604 | value = *valP; |
252b5132 RH |
10605 | |
10606 | /* If we aren't adjusting this fixup to be against the section | |
10607 | symbol, we need to adjust the value. */ | |
10608 | #ifdef OBJ_ELF | |
10609 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10610 | { |
add55e1f | 10611 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af AM |
10612 | { |
10613 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
94f592af | 10614 | |
98aa84af | 10615 | value -= symval; |
add55e1f | 10616 | if (value != 0 && ! fixP->fx_pcrel) |
98aa84af AM |
10617 | { |
10618 | /* In this case, the bfd_install_relocation routine will | |
10619 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10620 | the addend to appear in the object file. */ |
98aa84af | 10621 | value -= symval; |
7461da6e RS |
10622 | |
10623 | /* Make sure the addend is still non-zero. If it became zero | |
10624 | after the last operation, set it to a spurious value and | |
10625 | subtract the same value from the object file's contents. */ | |
10626 | if (value == 0) | |
10627 | { | |
10628 | value = 8; | |
10629 | ||
10630 | /* The in-place addends for LO16 relocations are signed; | |
10631 | leave the matching HI16 in-place addends as zero. */ | |
10632 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10633 | { | |
10634 | reloc_howto_type *howto; | |
10635 | bfd_vma contents, mask, field; | |
10636 | ||
10637 | howto = bfd_reloc_type_lookup (stdoutput, | |
10638 | fixP->fx_r_type); | |
10639 | ||
10640 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
10641 | + fixP->fx_where, | |
10642 | fixP->fx_size * 8, | |
10643 | target_big_endian); | |
10644 | ||
10645 | /* MASK has bits set where the relocation should go. | |
10646 | FIELD is -value, shifted into the appropriate place | |
10647 | for this relocation. */ | |
10648 | mask = 1 << (howto->bitsize - 1); | |
10649 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10650 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10651 | ||
10652 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10653 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10654 | fixP->fx_size * 8, | |
10655 | target_big_endian); | |
10656 | } | |
10657 | } | |
98aa84af AM |
10658 | } |
10659 | } | |
252b5132 | 10660 | |
bb2d6cd7 GK |
10661 | /* This code was generated using trial and error and so is |
10662 | fragile and not trustworthy. If you change it, you should | |
10663 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10664 | they still pass. */ | |
10665 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10666 | { | |
10667 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10668 | ||
10669 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10670 | This gives the right results, but it can't possibly | |
10671 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10672 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10673 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10674 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10675 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10676 | } | |
10677 | } | |
10678 | #endif | |
252b5132 | 10679 | |
94f592af | 10680 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 RH |
10681 | |
10682 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
10683 | fixP->fx_done = 1; | |
10684 | ||
10685 | switch (fixP->fx_r_type) | |
10686 | { | |
10687 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10688 | case BFD_RELOC_MIPS_SHIFT5: |
10689 | case BFD_RELOC_MIPS_SHIFT6: | |
10690 | case BFD_RELOC_MIPS_GOT_DISP: | |
10691 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10692 | case BFD_RELOC_MIPS_GOT_OFST: | |
10693 | case BFD_RELOC_MIPS_SUB: | |
10694 | case BFD_RELOC_MIPS_INSERT_A: | |
10695 | case BFD_RELOC_MIPS_INSERT_B: | |
10696 | case BFD_RELOC_MIPS_DELETE: | |
10697 | case BFD_RELOC_MIPS_HIGHEST: | |
10698 | case BFD_RELOC_MIPS_HIGHER: | |
10699 | case BFD_RELOC_MIPS_SCN_DISP: | |
10700 | case BFD_RELOC_MIPS_REL16: | |
10701 | case BFD_RELOC_MIPS_RELGOT: | |
10702 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10703 | case BFD_RELOC_HI16: |
10704 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10705 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10706 | case BFD_RELOC_MIPS_LITERAL: |
10707 | case BFD_RELOC_MIPS_CALL16: | |
10708 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10709 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10710 | case BFD_RELOC_MIPS_GOT_HI16: |
10711 | case BFD_RELOC_MIPS_GOT_LO16: | |
10712 | case BFD_RELOC_MIPS_CALL_HI16: | |
10713 | case BFD_RELOC_MIPS_CALL_LO16: | |
10714 | case BFD_RELOC_MIPS16_GPREL: | |
10715 | if (fixP->fx_pcrel) | |
10716 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10717 | _("Invalid PC relative reloc")); | |
10718 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10719 | break; | |
10720 | ||
10721 | case BFD_RELOC_MIPS16_JMP: | |
10722 | /* We currently always generate a reloc against a symbol, which | |
10723 | means that we don't want an addend even if the symbol is | |
10724 | defined. */ | |
10725 | fixP->fx_addnumber = 0; | |
10726 | break; | |
10727 | ||
10728 | case BFD_RELOC_PCREL_HI16_S: | |
10729 | /* The addend for this is tricky if it is internal, so we just | |
10730 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10731 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10732 | && !fixP->fx_done |
10733 | && value != 0) | |
10734 | break; | |
10735 | if (fixP->fx_addsy | |
10736 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10737 | { |
10738 | /* For an external symbol adjust by the address to make it | |
10739 | pcrel_offset. We use the address of the RELLO reloc | |
10740 | which follows this one. */ | |
10741 | value += (fixP->fx_next->fx_frag->fr_address | |
10742 | + fixP->fx_next->fx_where); | |
10743 | } | |
e7d556df | 10744 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 10745 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10746 | if (target_big_endian) |
10747 | buf += 2; | |
874e8986 | 10748 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10749 | break; |
10750 | ||
10751 | case BFD_RELOC_PCREL_LO16: | |
10752 | /* The addend for this is tricky if it is internal, so we just | |
10753 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10754 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10755 | && !fixP->fx_done |
10756 | && value != 0) | |
10757 | break; | |
10758 | if (fixP->fx_addsy | |
10759 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 10760 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 10761 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10762 | if (target_big_endian) |
10763 | buf += 2; | |
874e8986 | 10764 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10765 | break; |
10766 | ||
10767 | case BFD_RELOC_64: | |
10768 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10769 | extended value if we are only 32 bits. */ | |
10770 | if (fixP->fx_done | |
10771 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10772 | { | |
10773 | if (8 <= sizeof (valueT)) | |
10774 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10775 | value, 8); | |
10776 | else | |
10777 | { | |
10778 | long w1, w2; | |
10779 | long hiv; | |
10780 | ||
10781 | w1 = w2 = fixP->fx_where; | |
10782 | if (target_big_endian) | |
10783 | w1 += 4; | |
10784 | else | |
10785 | w2 += 4; | |
10786 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10787 | if ((value & 0x80000000) != 0) | |
10788 | hiv = 0xffffffff; | |
10789 | else | |
10790 | hiv = 0; | |
10791 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10792 | } | |
10793 | } | |
10794 | break; | |
10795 | ||
056350c6 | 10796 | case BFD_RELOC_RVA: |
252b5132 RH |
10797 | case BFD_RELOC_32: |
10798 | /* If we are deleting this reloc entry, we must fill in the | |
10799 | value now. This can happen if we have a .word which is not | |
10800 | resolved when it appears but is later defined. We also need | |
10801 | to fill in the value if this is an embedded PIC switch table | |
10802 | entry. */ | |
10803 | if (fixP->fx_done | |
10804 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10805 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10806 | value, 4); | |
10807 | break; | |
10808 | ||
10809 | case BFD_RELOC_16: | |
10810 | /* If we are deleting this reloc entry, we must fill in the | |
10811 | value now. */ | |
10812 | assert (fixP->fx_size == 2); | |
10813 | if (fixP->fx_done) | |
10814 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10815 | value, 2); | |
10816 | break; | |
10817 | ||
10818 | case BFD_RELOC_LO16: | |
10819 | /* When handling an embedded PIC switch statement, we can wind | |
10820 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10821 | if (fixP->fx_done) | |
10822 | { | |
98aa84af | 10823 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
10824 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10825 | _("relocation overflow")); | |
874e8986 | 10826 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10827 | if (target_big_endian) |
10828 | buf += 2; | |
874e8986 | 10829 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10830 | } |
10831 | break; | |
10832 | ||
10833 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
10834 | if ((value & 0x3) != 0) |
10835 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10836 | _("Branch to odd address (%lx)"), (long) value); | |
10837 | ||
10838 | /* Fall through. */ | |
10839 | ||
10840 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
10841 | /* |
10842 | * We need to save the bits in the instruction since fixup_segment() | |
10843 | * might be deleting the relocation entry (i.e., a branch within | |
10844 | * the current segment). | |
10845 | */ | |
bb2d6cd7 GK |
10846 | if (!fixP->fx_done && value != 0) |
10847 | break; | |
10848 | /* If 'value' is zero, the remaining reloc code won't actually | |
10849 | do the store, so it must be done here. This is probably | |
10850 | a bug somewhere. */ | |
b25a253c CD |
10851 | if (!fixP->fx_done |
10852 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
10853 | || fixP->fx_addsy == NULL /* ??? */ | |
10854 | || ! S_IS_DEFINED (fixP->fx_addsy))) | |
bb2d6cd7 | 10855 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 10856 | |
98aa84af | 10857 | value = (offsetT) value >> 2; |
252b5132 RH |
10858 | |
10859 | /* update old instruction data */ | |
874e8986 | 10860 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
10861 | if (target_big_endian) |
10862 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10863 | else | |
10864 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
10865 | ||
98aa84af | 10866 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
10867 | insn |= value & 0xffff; |
10868 | else | |
10869 | { | |
10870 | /* The branch offset is too large. If this is an | |
10871 | unconditional branch, and we are not generating PIC code, | |
10872 | we can convert it to an absolute jump instruction. */ | |
10873 | if (mips_pic == NO_PIC | |
10874 | && fixP->fx_done | |
10875 | && fixP->fx_frag->fr_address >= text_section->vma | |
10876 | && (fixP->fx_frag->fr_address | |
10877 | < text_section->vma + text_section->_raw_size) | |
10878 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10879 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10880 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10881 | { | |
10882 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10883 | insn = 0x0c000000; /* jal */ | |
10884 | else | |
10885 | insn = 0x08000000; /* j */ | |
10886 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10887 | fixP->fx_done = 0; | |
10888 | fixP->fx_addsy = section_symbol (text_section); | |
10889 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10890 | } | |
10891 | else | |
10892 | { | |
10893 | /* FIXME. It would be possible in principle to handle | |
10894 | conditional branches which overflow. They could be | |
10895 | transformed into a branch around a jump. This would | |
10896 | require setting up variant frags for each different | |
10897 | branch type. The native MIPS assembler attempts to | |
10898 | handle these cases, but it appears to do it | |
10899 | incorrectly. */ | |
10900 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10901 | _("Branch out of range")); | |
10902 | } | |
10903 | } | |
10904 | ||
10905 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
10906 | break; | |
10907 | ||
10908 | case BFD_RELOC_VTABLE_INHERIT: | |
10909 | fixP->fx_done = 0; | |
10910 | if (fixP->fx_addsy | |
10911 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10912 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10913 | S_SET_WEAK (fixP->fx_addsy); | |
10914 | break; | |
10915 | ||
10916 | case BFD_RELOC_VTABLE_ENTRY: | |
10917 | fixP->fx_done = 0; | |
10918 | break; | |
10919 | ||
10920 | default: | |
10921 | internalError (); | |
10922 | } | |
252b5132 RH |
10923 | } |
10924 | ||
10925 | #if 0 | |
10926 | void | |
10927 | printInsn (oc) | |
10928 | unsigned long oc; | |
10929 | { | |
10930 | const struct mips_opcode *p; | |
10931 | int treg, sreg, dreg, shamt; | |
10932 | short imm; | |
10933 | const char *args; | |
10934 | int i; | |
10935 | ||
10936 | for (i = 0; i < NUMOPCODES; ++i) | |
10937 | { | |
10938 | p = &mips_opcodes[i]; | |
10939 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10940 | { | |
10941 | printf ("%08lx %s\t", oc, p->name); | |
10942 | treg = (oc >> 16) & 0x1f; | |
10943 | sreg = (oc >> 21) & 0x1f; | |
10944 | dreg = (oc >> 11) & 0x1f; | |
10945 | shamt = (oc >> 6) & 0x1f; | |
10946 | imm = oc; | |
10947 | for (args = p->args;; ++args) | |
10948 | { | |
10949 | switch (*args) | |
10950 | { | |
10951 | case '\0': | |
10952 | printf ("\n"); | |
10953 | break; | |
10954 | ||
10955 | case ',': | |
10956 | case '(': | |
10957 | case ')': | |
10958 | printf ("%c", *args); | |
10959 | continue; | |
10960 | ||
10961 | case 'r': | |
10962 | assert (treg == sreg); | |
10963 | printf ("$%d,$%d", treg, sreg); | |
10964 | continue; | |
10965 | ||
10966 | case 'd': | |
10967 | case 'G': | |
10968 | printf ("$%d", dreg); | |
10969 | continue; | |
10970 | ||
10971 | case 't': | |
10972 | case 'E': | |
10973 | printf ("$%d", treg); | |
10974 | continue; | |
10975 | ||
10976 | case 'k': | |
10977 | printf ("0x%x", treg); | |
10978 | continue; | |
10979 | ||
10980 | case 'b': | |
10981 | case 's': | |
10982 | printf ("$%d", sreg); | |
10983 | continue; | |
10984 | ||
10985 | case 'a': | |
10986 | printf ("0x%08lx", oc & 0x1ffffff); | |
10987 | continue; | |
10988 | ||
10989 | case 'i': | |
10990 | case 'j': | |
10991 | case 'o': | |
10992 | case 'u': | |
10993 | printf ("%d", imm); | |
10994 | continue; | |
10995 | ||
10996 | case '<': | |
10997 | case '>': | |
10998 | printf ("$%d", shamt); | |
10999 | continue; | |
11000 | ||
11001 | default: | |
11002 | internalError (); | |
11003 | } | |
11004 | break; | |
11005 | } | |
11006 | return; | |
11007 | } | |
11008 | } | |
11009 | printf (_("%08lx UNDEFINED\n"), oc); | |
11010 | } | |
11011 | #endif | |
11012 | ||
11013 | static symbolS * | |
11014 | get_symbol () | |
11015 | { | |
11016 | int c; | |
11017 | char *name; | |
11018 | symbolS *p; | |
11019 | ||
11020 | name = input_line_pointer; | |
11021 | c = get_symbol_end (); | |
11022 | p = (symbolS *) symbol_find_or_make (name); | |
11023 | *input_line_pointer = c; | |
11024 | return p; | |
11025 | } | |
11026 | ||
11027 | /* Align the current frag to a given power of two. The MIPS assembler | |
11028 | also automatically adjusts any preceding label. */ | |
11029 | ||
11030 | static void | |
11031 | mips_align (to, fill, label) | |
11032 | int to; | |
11033 | int fill; | |
11034 | symbolS *label; | |
11035 | { | |
11036 | mips_emit_delays (false); | |
11037 | frag_align (to, fill, 0); | |
11038 | record_alignment (now_seg, to); | |
11039 | if (label != NULL) | |
11040 | { | |
11041 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11042 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11043 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11044 | } | |
11045 | } | |
11046 | ||
11047 | /* Align to a given power of two. .align 0 turns off the automatic | |
11048 | alignment used by the data creating pseudo-ops. */ | |
11049 | ||
11050 | static void | |
11051 | s_align (x) | |
43841e91 | 11052 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11053 | { |
11054 | register int temp; | |
11055 | register long temp_fill; | |
11056 | long max_alignment = 15; | |
11057 | ||
11058 | /* | |
11059 | ||
11060 | o Note that the assembler pulls down any immediately preceeding label | |
11061 | to the aligned address. | |
11062 | o It's not documented but auto alignment is reinstated by | |
11063 | a .align pseudo instruction. | |
11064 | o Note also that after auto alignment is turned off the mips assembler | |
11065 | issues an error on attempt to assemble an improperly aligned data item. | |
11066 | We don't. | |
11067 | ||
11068 | */ | |
11069 | ||
11070 | temp = get_absolute_expression (); | |
11071 | if (temp > max_alignment) | |
11072 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11073 | else if (temp < 0) | |
11074 | { | |
11075 | as_warn (_("Alignment negative: 0 assumed.")); | |
11076 | temp = 0; | |
11077 | } | |
11078 | if (*input_line_pointer == ',') | |
11079 | { | |
11080 | input_line_pointer++; | |
11081 | temp_fill = get_absolute_expression (); | |
11082 | } | |
11083 | else | |
11084 | temp_fill = 0; | |
11085 | if (temp) | |
11086 | { | |
11087 | auto_align = 1; | |
11088 | mips_align (temp, (int) temp_fill, | |
11089 | insn_labels != NULL ? insn_labels->label : NULL); | |
11090 | } | |
11091 | else | |
11092 | { | |
11093 | auto_align = 0; | |
11094 | } | |
11095 | ||
11096 | demand_empty_rest_of_line (); | |
11097 | } | |
11098 | ||
11099 | void | |
11100 | mips_flush_pending_output () | |
11101 | { | |
11102 | mips_emit_delays (false); | |
11103 | mips_clear_insn_labels (); | |
11104 | } | |
11105 | ||
11106 | static void | |
11107 | s_change_sec (sec) | |
11108 | int sec; | |
11109 | { | |
11110 | segT seg; | |
11111 | ||
11112 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11113 | .sdata and .sbss sections. We change the .data and .rdata | |
11114 | pseudo-ops to use .sdata. */ | |
11115 | if (mips_pic == EMBEDDED_PIC | |
11116 | && (sec == 'd' || sec == 'r')) | |
11117 | sec = 's'; | |
11118 | ||
11119 | #ifdef OBJ_ELF | |
11120 | /* The ELF backend needs to know that we are changing sections, so | |
11121 | that .previous works correctly. We could do something like check | |
b6ff326e | 11122 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11123 | as it would not be appropriate to use it in the section changing |
11124 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11125 | This should be cleaner, somehow. */ | |
11126 | obj_elf_section_change_hook (); | |
11127 | #endif | |
11128 | ||
11129 | mips_emit_delays (false); | |
11130 | switch (sec) | |
11131 | { | |
11132 | case 't': | |
11133 | s_text (0); | |
11134 | break; | |
11135 | case 'd': | |
11136 | s_data (0); | |
11137 | break; | |
11138 | case 'b': | |
11139 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11140 | demand_empty_rest_of_line (); | |
11141 | break; | |
11142 | ||
11143 | case 'r': | |
11144 | if (USE_GLOBAL_POINTER_OPT) | |
11145 | { | |
11146 | seg = subseg_new (RDATA_SECTION_NAME, | |
11147 | (subsegT) get_absolute_expression ()); | |
11148 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11149 | { | |
11150 | bfd_set_section_flags (stdoutput, seg, | |
11151 | (SEC_ALLOC | |
11152 | | SEC_LOAD | |
11153 | | SEC_READONLY | |
11154 | | SEC_RELOC | |
11155 | | SEC_DATA)); | |
11156 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11157 | record_alignment (seg, 4); |
252b5132 RH |
11158 | } |
11159 | demand_empty_rest_of_line (); | |
11160 | } | |
11161 | else | |
11162 | { | |
11163 | as_bad (_("No read only data section in this object file format")); | |
11164 | demand_empty_rest_of_line (); | |
11165 | return; | |
11166 | } | |
11167 | break; | |
11168 | ||
11169 | case 's': | |
11170 | if (USE_GLOBAL_POINTER_OPT) | |
11171 | { | |
11172 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11173 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11174 | { | |
11175 | bfd_set_section_flags (stdoutput, seg, | |
11176 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11177 | | SEC_DATA); | |
11178 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11179 | record_alignment (seg, 4); |
252b5132 RH |
11180 | } |
11181 | demand_empty_rest_of_line (); | |
11182 | break; | |
11183 | } | |
11184 | else | |
11185 | { | |
11186 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11187 | demand_empty_rest_of_line (); | |
11188 | return; | |
11189 | } | |
11190 | } | |
11191 | ||
11192 | auto_align = 1; | |
11193 | } | |
11194 | ||
11195 | void | |
11196 | mips_enable_auto_align () | |
11197 | { | |
11198 | auto_align = 1; | |
11199 | } | |
11200 | ||
11201 | static void | |
11202 | s_cons (log_size) | |
11203 | int log_size; | |
11204 | { | |
11205 | symbolS *label; | |
11206 | ||
11207 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11208 | mips_emit_delays (false); | |
11209 | if (log_size > 0 && auto_align) | |
11210 | mips_align (log_size, 0, label); | |
11211 | mips_clear_insn_labels (); | |
11212 | cons (1 << log_size); | |
11213 | } | |
11214 | ||
11215 | static void | |
11216 | s_float_cons (type) | |
11217 | int type; | |
11218 | { | |
11219 | symbolS *label; | |
11220 | ||
11221 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11222 | ||
11223 | mips_emit_delays (false); | |
11224 | ||
11225 | if (auto_align) | |
49309057 ILT |
11226 | { |
11227 | if (type == 'd') | |
11228 | mips_align (3, 0, label); | |
11229 | else | |
11230 | mips_align (2, 0, label); | |
11231 | } | |
252b5132 RH |
11232 | |
11233 | mips_clear_insn_labels (); | |
11234 | ||
11235 | float_cons (type); | |
11236 | } | |
11237 | ||
11238 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11239 | permitted to say | |
11240 | .globl foo .text | |
11241 | where foo is an undefined symbol, to mean that foo should be | |
11242 | considered to be the address of a function. */ | |
11243 | ||
11244 | static void | |
11245 | s_mips_globl (x) | |
43841e91 | 11246 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11247 | { |
11248 | char *name; | |
11249 | int c; | |
11250 | symbolS *symbolP; | |
11251 | flagword flag; | |
11252 | ||
11253 | name = input_line_pointer; | |
11254 | c = get_symbol_end (); | |
11255 | symbolP = symbol_find_or_make (name); | |
11256 | *input_line_pointer = c; | |
11257 | SKIP_WHITESPACE (); | |
11258 | ||
11259 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11260 | being a function is apparently labelled as being an object. */ | |
11261 | flag = BSF_OBJECT; | |
11262 | ||
11263 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11264 | { | |
11265 | char *secname; | |
11266 | asection *sec; | |
11267 | ||
11268 | secname = input_line_pointer; | |
11269 | c = get_symbol_end (); | |
11270 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11271 | if (sec == NULL) | |
11272 | as_bad (_("%s: no such section"), secname); | |
11273 | *input_line_pointer = c; | |
11274 | ||
11275 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11276 | flag = BSF_FUNCTION; | |
11277 | } | |
11278 | ||
49309057 | 11279 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11280 | |
11281 | S_SET_EXTERNAL (symbolP); | |
11282 | demand_empty_rest_of_line (); | |
11283 | } | |
11284 | ||
11285 | static void | |
11286 | s_option (x) | |
43841e91 | 11287 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11288 | { |
11289 | char *opt; | |
11290 | char c; | |
11291 | ||
11292 | opt = input_line_pointer; | |
11293 | c = get_symbol_end (); | |
11294 | ||
11295 | if (*opt == 'O') | |
11296 | { | |
11297 | /* FIXME: What does this mean? */ | |
11298 | } | |
11299 | else if (strncmp (opt, "pic", 3) == 0) | |
11300 | { | |
11301 | int i; | |
11302 | ||
11303 | i = atoi (opt + 3); | |
11304 | if (i == 0) | |
11305 | mips_pic = NO_PIC; | |
11306 | else if (i == 2) | |
11307 | mips_pic = SVR4_PIC; | |
11308 | else | |
11309 | as_bad (_(".option pic%d not supported"), i); | |
11310 | ||
11311 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11312 | { | |
11313 | if (g_switch_seen && g_switch_value != 0) | |
11314 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11315 | g_switch_value = 0; | |
11316 | bfd_set_gp_size (stdoutput, 0); | |
11317 | } | |
11318 | } | |
11319 | else | |
11320 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11321 | ||
11322 | *input_line_pointer = c; | |
11323 | demand_empty_rest_of_line (); | |
11324 | } | |
11325 | ||
11326 | /* This structure is used to hold a stack of .set values. */ | |
11327 | ||
e972090a NC |
11328 | struct mips_option_stack |
11329 | { | |
252b5132 RH |
11330 | struct mips_option_stack *next; |
11331 | struct mips_set_options options; | |
11332 | }; | |
11333 | ||
11334 | static struct mips_option_stack *mips_opts_stack; | |
11335 | ||
11336 | /* Handle the .set pseudo-op. */ | |
11337 | ||
11338 | static void | |
11339 | s_mipsset (x) | |
43841e91 | 11340 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11341 | { |
11342 | char *name = input_line_pointer, ch; | |
11343 | ||
11344 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11345 | input_line_pointer++; | |
11346 | ch = *input_line_pointer; | |
11347 | *input_line_pointer = '\0'; | |
11348 | ||
11349 | if (strcmp (name, "reorder") == 0) | |
11350 | { | |
11351 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11352 | { | |
11353 | /* If we still have pending nops, we can discard them. The | |
11354 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11355 | needed. */ |
252b5132 RH |
11356 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11357 | * (mips_opts.mips16 ? 2 : 4)); | |
11358 | prev_nop_frag = NULL; | |
11359 | } | |
11360 | mips_opts.noreorder = 0; | |
11361 | } | |
11362 | else if (strcmp (name, "noreorder") == 0) | |
11363 | { | |
11364 | mips_emit_delays (true); | |
11365 | mips_opts.noreorder = 1; | |
11366 | mips_any_noreorder = 1; | |
11367 | } | |
11368 | else if (strcmp (name, "at") == 0) | |
11369 | { | |
11370 | mips_opts.noat = 0; | |
11371 | } | |
11372 | else if (strcmp (name, "noat") == 0) | |
11373 | { | |
11374 | mips_opts.noat = 1; | |
11375 | } | |
11376 | else if (strcmp (name, "macro") == 0) | |
11377 | { | |
11378 | mips_opts.warn_about_macros = 0; | |
11379 | } | |
11380 | else if (strcmp (name, "nomacro") == 0) | |
11381 | { | |
11382 | if (mips_opts.noreorder == 0) | |
11383 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11384 | mips_opts.warn_about_macros = 1; | |
11385 | } | |
11386 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11387 | { | |
11388 | mips_opts.nomove = 0; | |
11389 | } | |
11390 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11391 | { | |
11392 | mips_opts.nomove = 1; | |
11393 | } | |
11394 | else if (strcmp (name, "bopt") == 0) | |
11395 | { | |
11396 | mips_opts.nobopt = 0; | |
11397 | } | |
11398 | else if (strcmp (name, "nobopt") == 0) | |
11399 | { | |
11400 | mips_opts.nobopt = 1; | |
11401 | } | |
11402 | else if (strcmp (name, "mips16") == 0 | |
11403 | || strcmp (name, "MIPS-16") == 0) | |
11404 | mips_opts.mips16 = 1; | |
11405 | else if (strcmp (name, "nomips16") == 0 | |
11406 | || strcmp (name, "noMIPS-16") == 0) | |
11407 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11408 | else if (strcmp (name, "mips3d") == 0) |
11409 | mips_opts.ase_mips3d = 1; | |
11410 | else if (strcmp (name, "nomips3d") == 0) | |
11411 | mips_opts.ase_mips3d = 0; | |
252b5132 RH |
11412 | else if (strncmp (name, "mips", 4) == 0) |
11413 | { | |
11414 | int isa; | |
11415 | ||
11416 | /* Permit the user to change the ISA on the fly. Needless to | |
11417 | say, misuse can cause serious problems. */ | |
11418 | isa = atoi (name + 4); | |
553178e4 | 11419 | switch (isa) |
98d3f06f KH |
11420 | { |
11421 | case 0: | |
11422 | mips_opts.gp32 = file_mips_gp32; | |
11423 | mips_opts.fp32 = file_mips_fp32; | |
11424 | mips_opts.abi = file_mips_abi; | |
11425 | break; | |
11426 | case 1: | |
11427 | case 2: | |
11428 | case 32: | |
11429 | mips_opts.gp32 = 1; | |
11430 | mips_opts.fp32 = 1; | |
11431 | break; | |
11432 | case 3: | |
11433 | case 4: | |
11434 | case 5: | |
11435 | case 64: | |
11436 | /* Loosen ABI register width restriction. */ | |
11437 | if (mips_opts.abi == O32_ABI) | |
11438 | mips_opts.abi = NO_ABI; | |
11439 | mips_opts.gp32 = 0; | |
11440 | mips_opts.fp32 = 0; | |
11441 | break; | |
11442 | default: | |
11443 | as_bad (_("unknown ISA level %s"), name + 4); | |
11444 | break; | |
11445 | } | |
553178e4 | 11446 | |
e7af610e | 11447 | switch (isa) |
98d3f06f KH |
11448 | { |
11449 | case 0: mips_opts.isa = file_mips_isa; break; | |
11450 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11451 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11452 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
11453 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
11454 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
11455 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
11456 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
11457 | default: as_bad (_("unknown ISA level %s"), name + 4); break; | |
11458 | } | |
252b5132 RH |
11459 | } |
11460 | else if (strcmp (name, "autoextend") == 0) | |
11461 | mips_opts.noautoextend = 0; | |
11462 | else if (strcmp (name, "noautoextend") == 0) | |
11463 | mips_opts.noautoextend = 1; | |
11464 | else if (strcmp (name, "push") == 0) | |
11465 | { | |
11466 | struct mips_option_stack *s; | |
11467 | ||
11468 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11469 | s->next = mips_opts_stack; | |
11470 | s->options = mips_opts; | |
11471 | mips_opts_stack = s; | |
11472 | } | |
11473 | else if (strcmp (name, "pop") == 0) | |
11474 | { | |
11475 | struct mips_option_stack *s; | |
11476 | ||
11477 | s = mips_opts_stack; | |
11478 | if (s == NULL) | |
11479 | as_bad (_(".set pop with no .set push")); | |
11480 | else | |
11481 | { | |
11482 | /* If we're changing the reorder mode we need to handle | |
11483 | delay slots correctly. */ | |
11484 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11485 | mips_emit_delays (true); | |
11486 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11487 | { | |
11488 | if (prev_nop_frag != NULL) | |
11489 | { | |
11490 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11491 | * (mips_opts.mips16 ? 2 : 4)); | |
11492 | prev_nop_frag = NULL; | |
11493 | } | |
11494 | } | |
11495 | ||
11496 | mips_opts = s->options; | |
11497 | mips_opts_stack = s->next; | |
11498 | free (s); | |
11499 | } | |
11500 | } | |
11501 | else | |
11502 | { | |
11503 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11504 | } | |
11505 | *input_line_pointer = ch; | |
11506 | demand_empty_rest_of_line (); | |
11507 | } | |
11508 | ||
11509 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11510 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11511 | ||
11512 | static void | |
11513 | s_abicalls (ignore) | |
43841e91 | 11514 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11515 | { |
11516 | mips_pic = SVR4_PIC; | |
11517 | if (USE_GLOBAL_POINTER_OPT) | |
11518 | { | |
11519 | if (g_switch_seen && g_switch_value != 0) | |
11520 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11521 | g_switch_value = 0; | |
11522 | } | |
11523 | bfd_set_gp_size (stdoutput, 0); | |
11524 | demand_empty_rest_of_line (); | |
11525 | } | |
11526 | ||
11527 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11528 | PIC code. It sets the $gp register for the function based on the | |
11529 | function address, which is in the register named in the argument. | |
11530 | This uses a relocation against _gp_disp, which is handled specially | |
11531 | by the linker. The result is: | |
11532 | lui $gp,%hi(_gp_disp) | |
11533 | addiu $gp,$gp,%lo(_gp_disp) | |
11534 | addu $gp,$gp,.cpload argument | |
11535 | The .cpload argument is normally $25 == $t9. */ | |
11536 | ||
11537 | static void | |
11538 | s_cpload (ignore) | |
43841e91 | 11539 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11540 | { |
11541 | expressionS ex; | |
11542 | int icnt = 0; | |
11543 | ||
6478892d TS |
11544 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11545 | .cpload is ignored. */ | |
11546 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11547 | { |
11548 | s_ignore (0); | |
11549 | return; | |
11550 | } | |
11551 | ||
d3ecfc59 | 11552 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11553 | if (mips_opts.noreorder == 0) |
11554 | as_warn (_(".cpload not in noreorder section")); | |
11555 | ||
11556 | ex.X_op = O_symbol; | |
11557 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11558 | ex.X_op_symbol = NULL; | |
11559 | ex.X_add_number = 0; | |
11560 | ||
11561 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11562 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11563 | |
c4e7957c | 11564 | macro_build_lui (NULL, &icnt, &ex, GP); |
252b5132 RH |
11565 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, |
11566 | (int) BFD_RELOC_LO16); | |
11567 | ||
11568 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
11569 | GP, GP, tc_get_register (0)); | |
11570 | ||
11571 | demand_empty_rest_of_line (); | |
11572 | } | |
11573 | ||
6478892d TS |
11574 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11575 | .cpsetup $reg1, offset|$reg2, label | |
11576 | ||
11577 | If offset is given, this results in: | |
11578 | sd $gp, offset($sp) | |
956cd1d6 TS |
11579 | lui $gp, %hi(%neg(%gp_rel(label))) |
11580 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11581 | addu $gp, $gp, $reg1 |
11582 | ||
11583 | If $reg2 is given, this results in: | |
11584 | daddu $reg2, $gp, $0 | |
956cd1d6 TS |
11585 | lui $gp, %hi(%neg(%gp_rel(label))) |
11586 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11587 | addu $gp, $gp, $reg1 |
11588 | */ | |
11589 | static void | |
11590 | s_cpsetup (ignore) | |
11591 | int ignore ATTRIBUTE_UNUSED; | |
11592 | { | |
11593 | expressionS ex_off; | |
11594 | expressionS ex_sym; | |
11595 | int reg1; | |
11596 | int icnt = 0; | |
11597 | char *sym; | |
11598 | ||
8586fc66 | 11599 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11600 | We also need NewABI support. */ |
11601 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11602 | { | |
11603 | s_ignore (0); | |
11604 | return; | |
11605 | } | |
11606 | ||
11607 | reg1 = tc_get_register (0); | |
11608 | SKIP_WHITESPACE (); | |
11609 | if (*input_line_pointer != ',') | |
11610 | { | |
11611 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11612 | return; | |
11613 | } | |
11614 | else | |
11615 | input_line_pointer++; | |
11616 | SKIP_WHITESPACE (); | |
11617 | if (*input_line_pointer == '$') | |
11618 | mips_cpreturn_register = tc_get_register (0); | |
11619 | else | |
11620 | mips_cpreturn_offset = get_absolute_expression (); | |
11621 | SKIP_WHITESPACE (); | |
11622 | if (*input_line_pointer != ',') | |
11623 | { | |
11624 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11625 | return; | |
11626 | } | |
11627 | else | |
11628 | input_line_pointer++; | |
11629 | SKIP_WHITESPACE (); | |
11630 | sym = input_line_pointer; | |
11631 | while (ISALNUM (*input_line_pointer)) | |
11632 | input_line_pointer++; | |
11633 | *input_line_pointer = 0; | |
11634 | ||
11635 | ex_sym.X_op = O_symbol; | |
11636 | ex_sym.X_add_symbol = symbol_find_or_make (sym); | |
11637 | ex_sym.X_op_symbol = NULL; | |
11638 | ex_sym.X_add_number = 0; | |
11639 | ||
11640 | if (mips_cpreturn_register == -1) | |
11641 | { | |
11642 | ex_off.X_op = O_constant; | |
11643 | ex_off.X_add_symbol = NULL; | |
11644 | ex_off.X_op_symbol = NULL; | |
11645 | ex_off.X_add_number = mips_cpreturn_offset; | |
11646 | ||
11647 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11648 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11649 | } | |
11650 | else | |
11651 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11652 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11653 | ||
11654 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, | |
11655 | (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11656 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11657 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
6478892d TS |
11658 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
11659 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11660 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11661 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16); | |
11662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
11663 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
11664 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
11665 | |
11666 | demand_empty_rest_of_line (); | |
11667 | } | |
11668 | ||
11669 | static void | |
11670 | s_cplocal (ignore) | |
11671 | int ignore ATTRIBUTE_UNUSED; | |
11672 | { | |
11673 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11674 | .cplocal is ignored. */ | |
11675 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11676 | { | |
11677 | s_ignore (0); | |
11678 | return; | |
11679 | } | |
11680 | ||
11681 | mips_gp_register = tc_get_register (0); | |
11682 | } | |
11683 | ||
252b5132 RH |
11684 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11685 | offset from $sp. The offset is remembered, and after making a PIC | |
11686 | call $gp is restored from that location. */ | |
11687 | ||
11688 | static void | |
11689 | s_cprestore (ignore) | |
43841e91 | 11690 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11691 | { |
11692 | expressionS ex; | |
11693 | int icnt = 0; | |
11694 | ||
6478892d TS |
11695 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11696 | .cprestore is ignored. */ | |
11697 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11698 | { |
11699 | s_ignore (0); | |
11700 | return; | |
11701 | } | |
11702 | ||
11703 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11704 | mips_cprestore_valid = 1; |
252b5132 RH |
11705 | |
11706 | ex.X_op = O_constant; | |
11707 | ex.X_add_symbol = NULL; | |
11708 | ex.X_op_symbol = NULL; | |
11709 | ex.X_add_number = mips_cprestore_offset; | |
11710 | ||
11711 | macro_build ((char *) NULL, &icnt, &ex, | |
ca4e0257 | 11712 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
252b5132 RH |
11713 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
11714 | ||
11715 | demand_empty_rest_of_line (); | |
11716 | } | |
11717 | ||
6478892d TS |
11718 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11719 | was given in the preceeding .gpsetup, it results in: | |
11720 | ld $gp, offset($sp) | |
76b3015f | 11721 | |
6478892d TS |
11722 | If a register $reg2 was given there, it results in: |
11723 | daddiu $gp, $gp, $reg2 | |
11724 | */ | |
11725 | static void | |
11726 | s_cpreturn (ignore) | |
11727 | int ignore ATTRIBUTE_UNUSED; | |
11728 | { | |
11729 | expressionS ex; | |
11730 | int icnt = 0; | |
11731 | ||
11732 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11733 | We also need NewABI support. */ | |
11734 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11735 | { | |
11736 | s_ignore (0); | |
11737 | return; | |
11738 | } | |
11739 | ||
11740 | if (mips_cpreturn_register == -1) | |
11741 | { | |
11742 | ex.X_op = O_constant; | |
11743 | ex.X_add_symbol = NULL; | |
11744 | ex.X_op_symbol = NULL; | |
11745 | ex.X_add_number = mips_cpreturn_offset; | |
11746 | ||
11747 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11748 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11749 | } | |
11750 | else | |
11751 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11752 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
11753 | ||
11754 | demand_empty_rest_of_line (); | |
11755 | } | |
11756 | ||
11757 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11758 | code. It sets the offset to use in gp_rel relocations. */ | |
11759 | ||
11760 | static void | |
11761 | s_gpvalue (ignore) | |
11762 | int ignore ATTRIBUTE_UNUSED; | |
11763 | { | |
11764 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11765 | We also need NewABI support. */ | |
11766 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11767 | { | |
11768 | s_ignore (0); | |
11769 | return; | |
11770 | } | |
11771 | ||
11772 | mips_cpreturn_offset = get_absolute_expression (); | |
11773 | ||
11774 | demand_empty_rest_of_line (); | |
11775 | } | |
11776 | ||
252b5132 RH |
11777 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11778 | code. It generates a 32 bit GP relative reloc. */ | |
11779 | ||
11780 | static void | |
11781 | s_gpword (ignore) | |
43841e91 | 11782 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11783 | { |
11784 | symbolS *label; | |
11785 | expressionS ex; | |
11786 | char *p; | |
11787 | ||
11788 | /* When not generating PIC code, this is treated as .word. */ | |
11789 | if (mips_pic != SVR4_PIC) | |
11790 | { | |
11791 | s_cons (2); | |
11792 | return; | |
11793 | } | |
11794 | ||
11795 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11796 | mips_emit_delays (true); | |
11797 | if (auto_align) | |
11798 | mips_align (2, 0, label); | |
11799 | mips_clear_insn_labels (); | |
11800 | ||
11801 | expression (&ex); | |
11802 | ||
11803 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11804 | { | |
11805 | as_bad (_("Unsupported use of .gpword")); | |
11806 | ignore_rest_of_line (); | |
11807 | } | |
11808 | ||
11809 | p = frag_more (4); | |
11810 | md_number_to_chars (p, (valueT) 0, 4); | |
11811 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
cdf6fd85 | 11812 | BFD_RELOC_GPREL32); |
252b5132 RH |
11813 | |
11814 | demand_empty_rest_of_line (); | |
11815 | } | |
11816 | ||
11817 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
11818 | tables in SVR4 PIC code. */ | |
11819 | ||
11820 | static void | |
11821 | s_cpadd (ignore) | |
43841e91 | 11822 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11823 | { |
11824 | int icnt = 0; | |
11825 | int reg; | |
11826 | ||
6478892d TS |
11827 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
11828 | code. */ | |
11829 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11830 | { |
11831 | s_ignore (0); | |
11832 | return; | |
11833 | } | |
11834 | ||
11835 | /* Add $gp to the register named as an argument. */ | |
11836 | reg = tc_get_register (0); | |
11837 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 11838 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
11839 | "d,v,t", reg, reg, GP); |
11840 | ||
bdaaa2e1 | 11841 | demand_empty_rest_of_line (); |
252b5132 RH |
11842 | } |
11843 | ||
11844 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
11845 | mips16 mode. This permits the linker to handle them specially, | |
11846 | such as generating jalx instructions when needed. We also make | |
11847 | them odd for the duration of the assembly, in order to generate the | |
11848 | right sort of code. We will make them even in the adjust_symtab | |
11849 | routine, while leaving them marked. This is convenient for the | |
11850 | debugger and the disassembler. The linker knows to make them odd | |
11851 | again. */ | |
11852 | ||
11853 | static void | |
11854 | s_insn (ignore) | |
43841e91 | 11855 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11856 | { |
11857 | if (mips_opts.mips16) | |
11858 | mips16_mark_labels (); | |
11859 | ||
11860 | demand_empty_rest_of_line (); | |
11861 | } | |
11862 | ||
11863 | /* Handle a .stabn directive. We need these in order to mark a label | |
11864 | as being a mips16 text label correctly. Sometimes the compiler | |
11865 | will emit a label, followed by a .stabn, and then switch sections. | |
11866 | If the label and .stabn are in mips16 mode, then the label is | |
11867 | really a mips16 text label. */ | |
11868 | ||
11869 | static void | |
11870 | s_mips_stab (type) | |
11871 | int type; | |
11872 | { | |
11873 | if (type == 'n' && mips_opts.mips16) | |
11874 | mips16_mark_labels (); | |
11875 | ||
11876 | s_stab (type); | |
11877 | } | |
11878 | ||
11879 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
11880 | */ | |
11881 | ||
11882 | static void | |
11883 | s_mips_weakext (ignore) | |
43841e91 | 11884 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11885 | { |
11886 | char *name; | |
11887 | int c; | |
11888 | symbolS *symbolP; | |
11889 | expressionS exp; | |
11890 | ||
11891 | name = input_line_pointer; | |
11892 | c = get_symbol_end (); | |
11893 | symbolP = symbol_find_or_make (name); | |
11894 | S_SET_WEAK (symbolP); | |
11895 | *input_line_pointer = c; | |
11896 | ||
11897 | SKIP_WHITESPACE (); | |
11898 | ||
11899 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11900 | { | |
11901 | if (S_IS_DEFINED (symbolP)) | |
11902 | { | |
956cd1d6 | 11903 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
11904 | S_GET_NAME (symbolP)); |
11905 | ignore_rest_of_line (); | |
11906 | return; | |
11907 | } | |
bdaaa2e1 | 11908 | |
252b5132 RH |
11909 | if (*input_line_pointer == ',') |
11910 | { | |
11911 | ++input_line_pointer; | |
11912 | SKIP_WHITESPACE (); | |
11913 | } | |
bdaaa2e1 | 11914 | |
252b5132 RH |
11915 | expression (&exp); |
11916 | if (exp.X_op != O_symbol) | |
11917 | { | |
11918 | as_bad ("bad .weakext directive"); | |
98d3f06f | 11919 | ignore_rest_of_line (); |
252b5132 RH |
11920 | return; |
11921 | } | |
49309057 | 11922 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
11923 | } |
11924 | ||
11925 | demand_empty_rest_of_line (); | |
11926 | } | |
11927 | ||
11928 | /* Parse a register string into a number. Called from the ECOFF code | |
11929 | to parse .frame. The argument is non-zero if this is the frame | |
11930 | register, so that we can record it in mips_frame_reg. */ | |
11931 | ||
11932 | int | |
11933 | tc_get_register (frame) | |
11934 | int frame; | |
11935 | { | |
11936 | int reg; | |
11937 | ||
11938 | SKIP_WHITESPACE (); | |
11939 | if (*input_line_pointer++ != '$') | |
11940 | { | |
11941 | as_warn (_("expected `$'")); | |
11942 | reg = 0; | |
11943 | } | |
3882b010 | 11944 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
11945 | { |
11946 | reg = get_absolute_expression (); | |
11947 | if (reg < 0 || reg >= 32) | |
11948 | { | |
11949 | as_warn (_("Bad register number")); | |
11950 | reg = 0; | |
11951 | } | |
11952 | } | |
11953 | else | |
11954 | { | |
11955 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
11956 | reg = FP; | |
11957 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
11958 | reg = SP; | |
11959 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
11960 | reg = GP; | |
11961 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
11962 | reg = AT; | |
11963 | else | |
11964 | { | |
11965 | as_warn (_("Unrecognized register name")); | |
11966 | reg = 0; | |
11967 | } | |
11968 | input_line_pointer += 2; | |
11969 | } | |
11970 | if (frame) | |
7a621144 DJ |
11971 | { |
11972 | mips_frame_reg = reg != 0 ? reg : SP; | |
11973 | mips_frame_reg_valid = 1; | |
11974 | mips_cprestore_valid = 0; | |
11975 | } | |
252b5132 RH |
11976 | return reg; |
11977 | } | |
11978 | ||
11979 | valueT | |
11980 | md_section_align (seg, addr) | |
11981 | asection *seg; | |
11982 | valueT addr; | |
11983 | { | |
11984 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11985 | ||
11986 | #ifdef OBJ_ELF | |
11987 | /* We don't need to align ELF sections to the full alignment. | |
11988 | However, Irix 5 may prefer that we align them at least to a 16 | |
11989 | byte boundary. We don't bother to align the sections if we are | |
11990 | targeted for an embedded system. */ | |
11991 | if (strcmp (TARGET_OS, "elf") == 0) | |
11992 | return addr; | |
11993 | if (align > 4) | |
11994 | align = 4; | |
11995 | #endif | |
11996 | ||
11997 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
11998 | } | |
11999 | ||
12000 | /* Utility routine, called from above as well. If called while the | |
12001 | input file is still being read, it's only an approximation. (For | |
12002 | example, a symbol may later become defined which appeared to be | |
12003 | undefined earlier.) */ | |
12004 | ||
12005 | static int | |
12006 | nopic_need_relax (sym, before_relaxing) | |
12007 | symbolS *sym; | |
12008 | int before_relaxing; | |
12009 | { | |
12010 | if (sym == 0) | |
12011 | return 0; | |
12012 | ||
6478892d | 12013 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12014 | { |
12015 | const char *symname; | |
12016 | int change; | |
12017 | ||
12018 | /* Find out whether this symbol can be referenced off the GP | |
12019 | register. It can be if it is smaller than the -G size or if | |
12020 | it is in the .sdata or .sbss section. Certain symbols can | |
12021 | not be referenced off the GP, although it appears as though | |
12022 | they can. */ | |
12023 | symname = S_GET_NAME (sym); | |
12024 | if (symname != (const char *) NULL | |
12025 | && (strcmp (symname, "eprol") == 0 | |
12026 | || strcmp (symname, "etext") == 0 | |
12027 | || strcmp (symname, "_gp") == 0 | |
12028 | || strcmp (symname, "edata") == 0 | |
12029 | || strcmp (symname, "_fbss") == 0 | |
12030 | || strcmp (symname, "_fdata") == 0 | |
12031 | || strcmp (symname, "_ftext") == 0 | |
12032 | || strcmp (symname, "end") == 0 | |
12033 | || strcmp (symname, "_gp_disp") == 0)) | |
12034 | change = 1; | |
12035 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12036 | && (0 | |
12037 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12038 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12039 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12040 | <= g_switch_value)) | |
252b5132 RH |
12041 | #endif |
12042 | /* We must defer this decision until after the whole | |
12043 | file has been read, since there might be a .extern | |
12044 | after the first use of this symbol. */ | |
12045 | || (before_relaxing | |
12046 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12047 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12048 | #endif |
12049 | && S_GET_VALUE (sym) == 0) | |
12050 | || (S_GET_VALUE (sym) != 0 | |
12051 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12052 | change = 0; | |
12053 | else | |
12054 | { | |
12055 | const char *segname; | |
12056 | ||
12057 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12058 | assert (strcmp (segname, ".lit8") != 0 | |
12059 | && strcmp (segname, ".lit4") != 0); | |
12060 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12061 | && strcmp (segname, ".sbss") != 0 |
12062 | && strncmp (segname, ".sdata.", 7) != 0 | |
12063 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12064 | } |
12065 | return change; | |
12066 | } | |
12067 | else | |
12068 | /* We are not optimizing for the GP register. */ | |
12069 | return 1; | |
12070 | } | |
12071 | ||
12072 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
12073 | extended opcode. SEC is the section the frag is in. */ | |
12074 | ||
12075 | static int | |
12076 | mips16_extended_frag (fragp, sec, stretch) | |
12077 | fragS *fragp; | |
12078 | asection *sec; | |
12079 | long stretch; | |
12080 | { | |
12081 | int type; | |
12082 | register const struct mips16_immed_operand *op; | |
12083 | offsetT val; | |
12084 | int mintiny, maxtiny; | |
12085 | segT symsec; | |
98aa84af | 12086 | fragS *sym_frag; |
252b5132 RH |
12087 | |
12088 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12089 | return 0; | |
12090 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12091 | return 1; | |
12092 | ||
12093 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12094 | op = mips16_immed_operands; | |
12095 | while (op->type != type) | |
12096 | { | |
12097 | ++op; | |
12098 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12099 | } | |
12100 | ||
12101 | if (op->unsp) | |
12102 | { | |
12103 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12104 | { | |
12105 | mintiny = 1; | |
12106 | maxtiny = 1 << op->nbits; | |
12107 | } | |
12108 | else | |
12109 | { | |
12110 | mintiny = 0; | |
12111 | maxtiny = (1 << op->nbits) - 1; | |
12112 | } | |
12113 | } | |
12114 | else | |
12115 | { | |
12116 | mintiny = - (1 << (op->nbits - 1)); | |
12117 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12118 | } | |
12119 | ||
98aa84af | 12120 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12121 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12122 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12123 | |
12124 | if (op->pcrel) | |
12125 | { | |
12126 | addressT addr; | |
12127 | ||
12128 | /* We won't have the section when we are called from | |
12129 | mips_relax_frag. However, we will always have been called | |
12130 | from md_estimate_size_before_relax first. If this is a | |
12131 | branch to a different section, we mark it as such. If SEC is | |
12132 | NULL, and the frag is not marked, then it must be a branch to | |
12133 | the same section. */ | |
12134 | if (sec == NULL) | |
12135 | { | |
12136 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12137 | return 1; | |
12138 | } | |
12139 | else | |
12140 | { | |
98aa84af | 12141 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12142 | if (symsec != sec) |
12143 | { | |
12144 | fragp->fr_subtype = | |
12145 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12146 | ||
12147 | /* FIXME: We should support this, and let the linker | |
12148 | catch branches and loads that are out of range. */ | |
12149 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12150 | _("unsupported PC relative reference to different section")); | |
12151 | ||
12152 | return 1; | |
12153 | } | |
98aa84af AM |
12154 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12155 | /* Assume non-extended on the first relaxation pass. | |
12156 | The address we have calculated will be bogus if this is | |
12157 | a forward branch to another frag, as the forward frag | |
12158 | will have fr_address == 0. */ | |
12159 | return 0; | |
252b5132 RH |
12160 | } |
12161 | ||
12162 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12163 | the same section. If the relax_marker of the symbol fragment |
12164 | differs from the relax_marker of this fragment, we have not | |
12165 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12166 | in STRETCH in order to get a better estimate of the address. |
12167 | This particularly matters because of the shift bits. */ | |
12168 | if (stretch != 0 | |
98aa84af | 12169 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12170 | { |
12171 | fragS *f; | |
12172 | ||
12173 | /* Adjust stretch for any alignment frag. Note that if have | |
12174 | been expanding the earlier code, the symbol may be | |
12175 | defined in what appears to be an earlier frag. FIXME: | |
12176 | This doesn't handle the fr_subtype field, which specifies | |
12177 | a maximum number of bytes to skip when doing an | |
12178 | alignment. */ | |
98aa84af | 12179 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12180 | { |
12181 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12182 | { | |
12183 | if (stretch < 0) | |
12184 | stretch = - ((- stretch) | |
12185 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12186 | else | |
12187 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12188 | if (stretch == 0) | |
12189 | break; | |
12190 | } | |
12191 | } | |
12192 | if (f != NULL) | |
12193 | val += stretch; | |
12194 | } | |
12195 | ||
12196 | addr = fragp->fr_address + fragp->fr_fix; | |
12197 | ||
12198 | /* The base address rules are complicated. The base address of | |
12199 | a branch is the following instruction. The base address of a | |
12200 | PC relative load or add is the instruction itself, but if it | |
12201 | is in a delay slot (in which case it can not be extended) use | |
12202 | the address of the instruction whose delay slot it is in. */ | |
12203 | if (type == 'p' || type == 'q') | |
12204 | { | |
12205 | addr += 2; | |
12206 | ||
12207 | /* If we are currently assuming that this frag should be | |
12208 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12209 | higher. */ |
252b5132 RH |
12210 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12211 | addr += 2; | |
12212 | ||
12213 | /* Ignore the low bit in the target, since it will be set | |
12214 | for a text label. */ | |
12215 | if ((val & 1) != 0) | |
12216 | --val; | |
12217 | } | |
12218 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12219 | addr -= 4; | |
12220 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12221 | addr -= 2; | |
12222 | ||
12223 | val -= addr & ~ ((1 << op->shift) - 1); | |
12224 | ||
12225 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12226 | if (type == 'p' || type == 'q') | |
12227 | val /= 2; | |
12228 | ||
12229 | /* If any of the shifted bits are set, we must use an extended | |
12230 | opcode. If the address depends on the size of this | |
12231 | instruction, this can lead to a loop, so we arrange to always | |
12232 | use an extended opcode. We only check this when we are in | |
12233 | the main relaxation loop, when SEC is NULL. */ | |
12234 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12235 | { | |
12236 | fragp->fr_subtype = | |
12237 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12238 | return 1; | |
12239 | } | |
12240 | ||
12241 | /* If we are about to mark a frag as extended because the value | |
12242 | is precisely maxtiny + 1, then there is a chance of an | |
12243 | infinite loop as in the following code: | |
12244 | la $4,foo | |
12245 | .skip 1020 | |
12246 | .align 2 | |
12247 | foo: | |
12248 | In this case when the la is extended, foo is 0x3fc bytes | |
12249 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12250 | the la must be extended. To avoid this loop, we mark the | |
12251 | frag as extended if it was small, and is about to become | |
12252 | extended with a value of maxtiny + 1. */ | |
12253 | if (val == ((maxtiny + 1) << op->shift) | |
12254 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12255 | && sec == NULL) | |
12256 | { | |
12257 | fragp->fr_subtype = | |
12258 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12259 | return 1; | |
12260 | } | |
12261 | } | |
12262 | else if (symsec != absolute_section && sec != NULL) | |
12263 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12264 | ||
12265 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12266 | || val < (mintiny << op->shift) | |
12267 | || val > (maxtiny << op->shift)) | |
12268 | return 1; | |
12269 | else | |
12270 | return 0; | |
12271 | } | |
12272 | ||
12273 | /* Estimate the size of a frag before relaxing. Unless this is the | |
12274 | mips16, we are not really relaxing here, and the final size is | |
12275 | encoded in the subtype information. For the mips16, we have to | |
12276 | decide whether we are using an extended opcode or not. */ | |
12277 | ||
252b5132 RH |
12278 | int |
12279 | md_estimate_size_before_relax (fragp, segtype) | |
12280 | fragS *fragp; | |
12281 | asection *segtype; | |
12282 | { | |
43841e91 | 12283 | int change = 0; |
8614eeee | 12284 | boolean linkonce = false; |
252b5132 RH |
12285 | |
12286 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
177b4a6a AO |
12287 | /* We don't want to modify the EXTENDED bit here; it might get us |
12288 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12289 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12290 | |
12291 | if (mips_pic == NO_PIC) | |
12292 | { | |
12293 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
12294 | } | |
12295 | else if (mips_pic == SVR4_PIC) | |
12296 | { | |
12297 | symbolS *sym; | |
12298 | asection *symsec; | |
12299 | ||
12300 | sym = fragp->fr_symbol; | |
12301 | ||
12302 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 12303 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
12304 | { |
12305 | symbolS *n; | |
12306 | ||
12307 | /* It's possible to get a loop here in a badly written | |
12308 | program. */ | |
49309057 | 12309 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
12310 | if (n == sym) |
12311 | break; | |
12312 | sym = n; | |
12313 | } | |
12314 | ||
12315 | symsec = S_GET_SEGMENT (sym); | |
12316 | ||
8614eeee UC |
12317 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
12318 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
12319 | { |
12320 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12321 | != 0) | |
12322 | linkonce = true; | |
12323 | ||
12324 | /* The GNU toolchain uses an extension for ELF: a section | |
12325 | beginning with the magic string .gnu.linkonce is a linkonce | |
12326 | section. */ | |
12327 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12328 | sizeof ".gnu.linkonce" - 1) == 0) | |
12329 | linkonce = true; | |
12330 | } | |
8614eeee | 12331 | |
252b5132 RH |
12332 | /* This must duplicate the test in adjust_reloc_syms. */ |
12333 | change = (symsec != &bfd_und_section | |
12334 | && symsec != &bfd_abs_section | |
426b0403 | 12335 | && ! bfd_is_com_section (symsec) |
8614eeee | 12336 | && !linkonce |
426b0403 | 12337 | #ifdef OBJ_ELF |
ea4ff978 | 12338 | /* A global or weak symbol is treated as external. */ |
9151e8bf | 12339 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
b25a253c CD |
12340 | || (! S_IS_WEAK (sym) |
12341 | && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC))) | |
426b0403 AM |
12342 | #endif |
12343 | ); | |
252b5132 RH |
12344 | } |
12345 | else | |
12346 | abort (); | |
12347 | ||
12348 | if (change) | |
12349 | { | |
12350 | /* Record the offset to the first reloc in the fr_opcode field. | |
12351 | This lets md_convert_frag and tc_gen_reloc know that the code | |
12352 | must be expanded. */ | |
12353 | fragp->fr_opcode = (fragp->fr_literal | |
12354 | + fragp->fr_fix | |
12355 | - RELAX_OLD (fragp->fr_subtype) | |
12356 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
12357 | /* FIXME: This really needs as_warn_where. */ | |
12358 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
12359 | as_warn (_("AT used after \".set noat\" or macro used after " |
12360 | "\".set nomacro\"")); | |
12361 | ||
12362 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
12363 | } |
12364 | ||
9a41af64 | 12365 | return 0; |
252b5132 RH |
12366 | } |
12367 | ||
12368 | /* This is called to see whether a reloc against a defined symbol | |
12369 | should be converted into a reloc against a section. Don't adjust | |
12370 | MIPS16 jump relocations, so we don't have to worry about the format | |
12371 | of the offset in the .o file. Don't adjust relocations against | |
12372 | mips16 symbols, so that the linker can find them if it needs to set | |
12373 | up a stub. */ | |
12374 | ||
12375 | int | |
12376 | mips_fix_adjustable (fixp) | |
12377 | fixS *fixp; | |
12378 | { | |
ea4ff978 L |
12379 | #ifdef OBJ_ELF |
12380 | /* Prevent all adjustments to global symbols. */ | |
46bac6de | 12381 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
b25a253c | 12382 | && mips_pic != EMBEDDED_PIC |
46bac6de | 12383 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) |
ea4ff978 L |
12384 | return 0; |
12385 | #endif | |
252b5132 RH |
12386 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12387 | return 0; | |
12388 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12389 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12390 | return 0; | |
12391 | if (fixp->fx_addsy == NULL) | |
12392 | return 1; | |
12393 | #ifdef OBJ_ELF | |
12394 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12395 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12396 | && fixp->fx_subsy == NULL) | |
12397 | return 0; | |
12398 | #endif | |
12399 | return 1; | |
12400 | } | |
12401 | ||
12402 | /* Translate internal representation of relocation info to BFD target | |
12403 | format. */ | |
12404 | ||
12405 | arelent ** | |
12406 | tc_gen_reloc (section, fixp) | |
43841e91 | 12407 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
12408 | fixS *fixp; |
12409 | { | |
12410 | static arelent *retval[4]; | |
12411 | arelent *reloc; | |
12412 | bfd_reloc_code_real_type code; | |
12413 | ||
12414 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
12415 | retval[1] = NULL; | |
12416 | ||
49309057 ILT |
12417 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12418 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12419 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12420 | ||
12421 | if (mips_pic == EMBEDDED_PIC | |
12422 | && SWITCH_TABLE (fixp)) | |
12423 | { | |
12424 | /* For a switch table entry we use a special reloc. The addend | |
12425 | is actually the difference between the reloc address and the | |
12426 | subtrahend. */ | |
12427 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12428 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12429 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12430 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12431 | } | |
12432 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
12433 | { | |
4514d474 CD |
12434 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12435 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12436 | else |
4514d474 CD |
12437 | { |
12438 | /* We use a special addend for an internal RELLO reloc. */ | |
12439 | if (symbol_section_p (fixp->fx_addsy)) | |
12440 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12441 | else | |
12442 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12443 | } | |
252b5132 RH |
12444 | } |
12445 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12446 | { | |
12447 | assert (fixp->fx_next != NULL | |
12448 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
12449 | |
12450 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 12451 | accordingly. */ |
4514d474 CD |
12452 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12453 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 12454 | else |
4514d474 CD |
12455 | { |
12456 | /* We use a special addend for an internal RELHI reloc. */ | |
12457 | if (symbol_section_p (fixp->fx_addsy)) | |
12458 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
12459 | + fixp->fx_next->fx_where | |
12460 | - S_GET_VALUE (fixp->fx_subsy)); | |
12461 | else | |
12462 | reloc->addend = (fixp->fx_addnumber | |
12463 | + fixp->fx_next->fx_frag->fr_address | |
12464 | + fixp->fx_next->fx_where); | |
12465 | } | |
252b5132 | 12466 | } |
4514d474 CD |
12467 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12468 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12469 | else |
12470 | { | |
12471 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12472 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12473 | handling. */ | |
12474 | reloc->addend = reloc->address; | |
12475 | else | |
12476 | reloc->addend = -reloc->address; | |
12477 | } | |
12478 | ||
12479 | /* If this is a variant frag, we may need to adjust the existing | |
12480 | reloc and generate a new one. */ | |
12481 | if (fixp->fx_frag->fr_opcode != NULL | |
cdf6fd85 | 12482 | && (fixp->fx_r_type == BFD_RELOC_GPREL16 |
252b5132 RH |
12483 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
12484 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12485 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12486 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12487 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d TS |
12488 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
12489 | && ! HAVE_NEWABI) | |
252b5132 RH |
12490 | { |
12491 | arelent *reloc2; | |
12492 | ||
12493 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12494 | ||
12495 | /* If this is not the last reloc in this frag, then we have two | |
12496 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12497 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12498 | the second one handle all of them. */ | |
12499 | if (fixp->fx_next != NULL | |
12500 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12501 | { | |
cdf6fd85 TS |
12502 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12503 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
12504 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
12505 | && (fixp->fx_next->fx_r_type | |
12506 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12507 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12508 | && (fixp->fx_next->fx_r_type | |
12509 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12510 | retval[0] = NULL; | |
12511 | return retval; | |
12512 | } | |
12513 | ||
12514 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12515 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12516 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12517 | retval[2] = NULL; | |
49309057 ILT |
12518 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12519 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12520 | reloc2->address = (reloc->address |
12521 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12522 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12523 | reloc2->addend = fixp->fx_addnumber; | |
12524 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12525 | assert (reloc2->howto != NULL); | |
12526 | ||
12527 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12528 | { | |
12529 | arelent *reloc3; | |
12530 | ||
12531 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12532 | retval[3] = NULL; | |
12533 | *reloc3 = *reloc2; | |
12534 | reloc3->address += 4; | |
12535 | } | |
12536 | ||
12537 | if (mips_pic == NO_PIC) | |
12538 | { | |
cdf6fd85 | 12539 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
12540 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
12541 | } | |
12542 | else if (mips_pic == SVR4_PIC) | |
12543 | { | |
12544 | switch (fixp->fx_r_type) | |
12545 | { | |
12546 | default: | |
12547 | abort (); | |
12548 | case BFD_RELOC_MIPS_GOT16: | |
12549 | break; | |
12550 | case BFD_RELOC_MIPS_CALL16: | |
12551 | case BFD_RELOC_MIPS_GOT_LO16: | |
12552 | case BFD_RELOC_MIPS_CALL_LO16: | |
12553 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12554 | break; | |
12555 | } | |
12556 | } | |
12557 | else | |
12558 | abort (); | |
12559 | } | |
12560 | ||
12561 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
12562 | to be used in the relocation's section offset. */ | |
12563 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12564 | { | |
12565 | reloc->address = reloc->addend; | |
12566 | reloc->addend = 0; | |
12567 | } | |
12568 | ||
12569 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12570 | fixup_segment converted a non-PC relative reloc into a PC | |
12571 | relative reloc. In such a case, we need to convert the reloc | |
12572 | code. */ | |
12573 | code = fixp->fx_r_type; | |
12574 | if (fixp->fx_pcrel) | |
12575 | { | |
12576 | switch (code) | |
12577 | { | |
12578 | case BFD_RELOC_8: | |
12579 | code = BFD_RELOC_8_PCREL; | |
12580 | break; | |
12581 | case BFD_RELOC_16: | |
12582 | code = BFD_RELOC_16_PCREL; | |
12583 | break; | |
12584 | case BFD_RELOC_32: | |
12585 | code = BFD_RELOC_32_PCREL; | |
12586 | break; | |
12587 | case BFD_RELOC_64: | |
12588 | code = BFD_RELOC_64_PCREL; | |
12589 | break; | |
12590 | case BFD_RELOC_8_PCREL: | |
12591 | case BFD_RELOC_16_PCREL: | |
12592 | case BFD_RELOC_32_PCREL: | |
12593 | case BFD_RELOC_64_PCREL: | |
12594 | case BFD_RELOC_16_PCREL_S2: | |
12595 | case BFD_RELOC_PCREL_HI16_S: | |
12596 | case BFD_RELOC_PCREL_LO16: | |
12597 | break; | |
12598 | default: | |
12599 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12600 | _("Cannot make %s relocation PC relative"), | |
12601 | bfd_get_reloc_code_name (code)); | |
12602 | } | |
12603 | } | |
12604 | ||
add55e1f RS |
12605 | #ifdef OBJ_ELF |
12606 | /* md_apply_fix3 has a double-subtraction hack to get | |
12607 | bfd_install_relocation to behave nicely. GPREL relocations are | |
12608 | handled correctly without this hack, so undo it here. We can't | |
12609 | stop md_apply_fix3 from subtracting twice in the first place since | |
12610 | the fake addend is required for variant frags above. */ | |
12611 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
d11008e1 | 12612 | && code == BFD_RELOC_GPREL16 |
add55e1f RS |
12613 | && reloc->addend != 0 |
12614 | && mips_need_elf_addend_fixup (fixp)) | |
12615 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
12616 | #endif | |
12617 | ||
252b5132 RH |
12618 | /* To support a PC relative reloc when generating embedded PIC code |
12619 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12620 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12621 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12622 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12623 | && code == BFD_RELOC_16_PCREL_S2 |
12624 | && mips_pic != EMBEDDED_PIC) | |
12625 | reloc->howto = NULL; | |
12626 | else | |
12627 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12628 | ||
12629 | if (reloc->howto == NULL) | |
12630 | { | |
12631 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12632 | _("Can not represent %s relocation in this object file format"), | |
12633 | bfd_get_reloc_code_name (code)); | |
12634 | retval[0] = NULL; | |
12635 | } | |
12636 | ||
12637 | return retval; | |
12638 | } | |
12639 | ||
12640 | /* Relax a machine dependent frag. This returns the amount by which | |
12641 | the current size of the frag should change. */ | |
12642 | ||
12643 | int | |
12644 | mips_relax_frag (fragp, stretch) | |
12645 | fragS *fragp; | |
12646 | long stretch; | |
12647 | { | |
12648 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12649 | return 0; | |
12650 | ||
c4e7957c | 12651 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12652 | { |
12653 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12654 | return 0; | |
12655 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12656 | return 2; | |
12657 | } | |
12658 | else | |
12659 | { | |
12660 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12661 | return 0; | |
12662 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12663 | return -2; | |
12664 | } | |
12665 | ||
12666 | return 0; | |
12667 | } | |
12668 | ||
12669 | /* Convert a machine dependent frag. */ | |
12670 | ||
12671 | void | |
12672 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12673 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12674 | segT asec; |
12675 | fragS *fragp; | |
12676 | { | |
12677 | int old, new; | |
12678 | char *fixptr; | |
12679 | ||
12680 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12681 | { | |
12682 | int type; | |
12683 | register const struct mips16_immed_operand *op; | |
12684 | boolean small, ext; | |
12685 | offsetT val; | |
12686 | bfd_byte *buf; | |
12687 | unsigned long insn; | |
12688 | boolean use_extend; | |
12689 | unsigned short extend; | |
12690 | ||
12691 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12692 | op = mips16_immed_operands; | |
12693 | while (op->type != type) | |
12694 | ++op; | |
12695 | ||
12696 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12697 | { | |
12698 | small = false; | |
12699 | ext = true; | |
12700 | } | |
12701 | else | |
12702 | { | |
12703 | small = true; | |
12704 | ext = false; | |
12705 | } | |
12706 | ||
6386f3a7 | 12707 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12708 | val = S_GET_VALUE (fragp->fr_symbol); |
12709 | if (op->pcrel) | |
12710 | { | |
12711 | addressT addr; | |
12712 | ||
12713 | addr = fragp->fr_address + fragp->fr_fix; | |
12714 | ||
12715 | /* The rules for the base address of a PC relative reloc are | |
12716 | complicated; see mips16_extended_frag. */ | |
12717 | if (type == 'p' || type == 'q') | |
12718 | { | |
12719 | addr += 2; | |
12720 | if (ext) | |
12721 | addr += 2; | |
12722 | /* Ignore the low bit in the target, since it will be | |
12723 | set for a text label. */ | |
12724 | if ((val & 1) != 0) | |
12725 | --val; | |
12726 | } | |
12727 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12728 | addr -= 4; | |
12729 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12730 | addr -= 2; | |
12731 | ||
12732 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12733 | val -= addr; | |
12734 | ||
12735 | /* Make sure the section winds up with the alignment we have | |
12736 | assumed. */ | |
12737 | if (op->shift > 0) | |
12738 | record_alignment (asec, op->shift); | |
12739 | } | |
12740 | ||
12741 | if (ext | |
12742 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12743 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12744 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12745 | _("extended instruction in delay slot")); | |
12746 | ||
12747 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
12748 | ||
12749 | if (target_big_endian) | |
12750 | insn = bfd_getb16 (buf); | |
12751 | else | |
12752 | insn = bfd_getl16 (buf); | |
12753 | ||
12754 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
12755 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
12756 | small, ext, &insn, &use_extend, &extend); | |
12757 | ||
12758 | if (use_extend) | |
12759 | { | |
874e8986 | 12760 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
12761 | fragp->fr_fix += 2; |
12762 | buf += 2; | |
12763 | } | |
12764 | ||
874e8986 | 12765 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
12766 | fragp->fr_fix += 2; |
12767 | buf += 2; | |
12768 | } | |
12769 | else | |
12770 | { | |
12771 | if (fragp->fr_opcode == NULL) | |
12772 | return; | |
12773 | ||
12774 | old = RELAX_OLD (fragp->fr_subtype); | |
12775 | new = RELAX_NEW (fragp->fr_subtype); | |
12776 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
12777 | ||
12778 | if (new > 0) | |
12779 | memcpy (fixptr - old, fixptr, new); | |
12780 | ||
12781 | fragp->fr_fix += new - old; | |
12782 | } | |
12783 | } | |
12784 | ||
12785 | #ifdef OBJ_ELF | |
12786 | ||
12787 | /* This function is called after the relocs have been generated. | |
12788 | We've been storing mips16 text labels as odd. Here we convert them | |
12789 | back to even for the convenience of the debugger. */ | |
12790 | ||
12791 | void | |
12792 | mips_frob_file_after_relocs () | |
12793 | { | |
12794 | asymbol **syms; | |
12795 | unsigned int count, i; | |
12796 | ||
12797 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
12798 | return; | |
12799 | ||
12800 | syms = bfd_get_outsymbols (stdoutput); | |
12801 | count = bfd_get_symcount (stdoutput); | |
12802 | for (i = 0; i < count; i++, syms++) | |
12803 | { | |
12804 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
12805 | && ((*syms)->value & 1) != 0) | |
12806 | { | |
12807 | (*syms)->value &= ~1; | |
12808 | /* If the symbol has an odd size, it was probably computed | |
12809 | incorrectly, so adjust that as well. */ | |
12810 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
12811 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
12812 | } | |
12813 | } | |
12814 | } | |
12815 | ||
12816 | #endif | |
12817 | ||
12818 | /* This function is called whenever a label is defined. It is used | |
12819 | when handling branch delays; if a branch has a label, we assume we | |
12820 | can not move it. */ | |
12821 | ||
12822 | void | |
12823 | mips_define_label (sym) | |
12824 | symbolS *sym; | |
12825 | { | |
12826 | struct insn_label_list *l; | |
12827 | ||
12828 | if (free_insn_labels == NULL) | |
12829 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
12830 | else | |
12831 | { | |
12832 | l = free_insn_labels; | |
12833 | free_insn_labels = l->next; | |
12834 | } | |
12835 | ||
12836 | l->label = sym; | |
12837 | l->next = insn_labels; | |
12838 | insn_labels = l; | |
12839 | } | |
12840 | \f | |
12841 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12842 | ||
12843 | /* Some special processing for a MIPS ELF file. */ | |
12844 | ||
12845 | void | |
12846 | mips_elf_final_processing () | |
12847 | { | |
12848 | /* Write out the register information. */ | |
195325d2 | 12849 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
12850 | { |
12851 | Elf32_RegInfo s; | |
12852 | ||
12853 | s.ri_gprmask = mips_gprmask; | |
12854 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12855 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12856 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12857 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12858 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12859 | ||
12860 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
12861 | ((Elf32_External_RegInfo *) | |
12862 | mips_regmask_frag)); | |
12863 | } | |
12864 | else | |
12865 | { | |
12866 | Elf64_Internal_RegInfo s; | |
12867 | ||
12868 | s.ri_gprmask = mips_gprmask; | |
12869 | s.ri_pad = 0; | |
12870 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12871 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12872 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12873 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12874 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12875 | ||
12876 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
12877 | ((Elf64_External_RegInfo *) | |
12878 | mips_regmask_frag)); | |
12879 | } | |
12880 | ||
12881 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
12882 | sort of BFD interface for this. */ | |
12883 | if (mips_any_noreorder) | |
12884 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
12885 | if (mips_pic != NO_PIC) | |
12886 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
12887 | ||
98d3f06f | 12888 | /* Set MIPS ELF flags for ASEs. */ |
1f25f5d3 CD |
12889 | #if 0 /* XXX FIXME */ |
12890 | if (file_ase_mips3d) | |
12891 | elf_elfheader (stdoutput)->e_flags |= ???; | |
12892 | #endif | |
12893 | ||
bdaaa2e1 | 12894 | /* Set the MIPS ELF ABI flags. */ |
a325df1d | 12895 | if (file_mips_abi == NO_ABI) |
252b5132 | 12896 | ; |
a325df1d | 12897 | else if (file_mips_abi == O32_ABI) |
252b5132 | 12898 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
a325df1d | 12899 | else if (file_mips_abi == O64_ABI) |
252b5132 | 12900 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
a325df1d | 12901 | else if (file_mips_abi == EABI_ABI) |
252b5132 RH |
12902 | { |
12903 | if (mips_eabi64) | |
12904 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
12905 | else | |
12906 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
12907 | } | |
a325df1d | 12908 | else if (file_mips_abi == N32_ABI) |
be00bddd TS |
12909 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
12910 | ||
12911 | /* Nothing to do for "64". */ | |
252b5132 RH |
12912 | |
12913 | if (mips_32bitmode) | |
12914 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
12915 | } | |
12916 | ||
12917 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
12918 | \f | |
beae10d5 KH |
12919 | typedef struct proc { |
12920 | symbolS *isym; | |
12921 | unsigned long reg_mask; | |
12922 | unsigned long reg_offset; | |
12923 | unsigned long fpreg_mask; | |
12924 | unsigned long fpreg_offset; | |
12925 | unsigned long frame_offset; | |
12926 | unsigned long frame_reg; | |
12927 | unsigned long pc_reg; | |
12928 | } procS; | |
252b5132 RH |
12929 | |
12930 | static procS cur_proc; | |
12931 | static procS *cur_proc_ptr; | |
12932 | static int numprocs; | |
12933 | ||
0a9ef439 | 12934 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 12935 | |
0a9ef439 RH |
12936 | void |
12937 | mips_handle_align (fragp) | |
12938 | fragS *fragp; | |
a19d8eb0 | 12939 | { |
0a9ef439 RH |
12940 | if (fragp->fr_type != rs_align_code) |
12941 | return; | |
12942 | ||
12943 | if (mips_opts.mips16) | |
a19d8eb0 CP |
12944 | { |
12945 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
12946 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
12947 | ||
0a9ef439 RH |
12948 | int bytes; |
12949 | char *p; | |
a19d8eb0 | 12950 | |
0a9ef439 RH |
12951 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
12952 | p = fragp->fr_literal + fragp->fr_fix; | |
12953 | ||
12954 | if (bytes & 1) | |
12955 | { | |
12956 | *p++ = 0; | |
12957 | fragp->fr_fix += 1; | |
12958 | } | |
12959 | ||
12960 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
12961 | fragp->fr_var = 2; | |
a19d8eb0 CP |
12962 | } |
12963 | ||
0a9ef439 | 12964 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
12965 | } |
12966 | ||
252b5132 RH |
12967 | static void |
12968 | md_obj_begin () | |
12969 | { | |
12970 | } | |
12971 | ||
12972 | static void | |
12973 | md_obj_end () | |
12974 | { | |
12975 | /* check for premature end, nesting errors, etc */ | |
12976 | if (cur_proc_ptr) | |
9a41af64 | 12977 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
12978 | } |
12979 | ||
12980 | static long | |
12981 | get_number () | |
12982 | { | |
12983 | int negative = 0; | |
12984 | long val = 0; | |
12985 | ||
12986 | if (*input_line_pointer == '-') | |
12987 | { | |
12988 | ++input_line_pointer; | |
12989 | negative = 1; | |
12990 | } | |
3882b010 | 12991 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 12992 | as_bad (_("expected simple number")); |
252b5132 RH |
12993 | if (input_line_pointer[0] == '0') |
12994 | { | |
12995 | if (input_line_pointer[1] == 'x') | |
12996 | { | |
12997 | input_line_pointer += 2; | |
3882b010 | 12998 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
12999 | { |
13000 | val <<= 4; | |
13001 | val |= hex_value (*input_line_pointer++); | |
13002 | } | |
13003 | return negative ? -val : val; | |
13004 | } | |
13005 | else | |
13006 | { | |
13007 | ++input_line_pointer; | |
3882b010 | 13008 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13009 | { |
13010 | val <<= 3; | |
13011 | val |= *input_line_pointer++ - '0'; | |
13012 | } | |
13013 | return negative ? -val : val; | |
13014 | } | |
13015 | } | |
3882b010 | 13016 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13017 | { |
13018 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13019 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13020 | as_warn (_("invalid number")); |
252b5132 RH |
13021 | return -1; |
13022 | } | |
3882b010 | 13023 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13024 | { |
13025 | val *= 10; | |
13026 | val += *input_line_pointer++ - '0'; | |
13027 | } | |
13028 | return negative ? -val : val; | |
13029 | } | |
13030 | ||
13031 | /* The .file directive; just like the usual .file directive, but there | |
13032 | is an initial number which is the ECOFF file index. */ | |
13033 | ||
13034 | static void | |
13035 | s_file (x) | |
43841e91 | 13036 | int x ATTRIBUTE_UNUSED; |
252b5132 | 13037 | { |
874e8986 | 13038 | get_number (); |
252b5132 RH |
13039 | s_app_file (0); |
13040 | } | |
13041 | ||
252b5132 RH |
13042 | /* The .end directive. */ |
13043 | ||
13044 | static void | |
13045 | s_mips_end (x) | |
43841e91 | 13046 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
13047 | { |
13048 | symbolS *p; | |
13049 | int maybe_text; | |
13050 | ||
7a621144 DJ |
13051 | /* Following functions need their own .frame and .cprestore directives. */ |
13052 | mips_frame_reg_valid = 0; | |
13053 | mips_cprestore_valid = 0; | |
13054 | ||
252b5132 RH |
13055 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13056 | { | |
13057 | p = get_symbol (); | |
13058 | demand_empty_rest_of_line (); | |
13059 | } | |
13060 | else | |
13061 | p = NULL; | |
13062 | ||
13063 | #ifdef BFD_ASSEMBLER | |
13064 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13065 | maybe_text = 1; | |
13066 | else | |
13067 | maybe_text = 0; | |
13068 | #else | |
13069 | if (now_seg != data_section && now_seg != bss_section) | |
13070 | maybe_text = 1; | |
13071 | else | |
13072 | maybe_text = 0; | |
13073 | #endif | |
13074 | ||
13075 | if (!maybe_text) | |
13076 | as_warn (_(".end not in text section")); | |
13077 | ||
13078 | if (!cur_proc_ptr) | |
13079 | { | |
13080 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13081 | demand_empty_rest_of_line (); | |
13082 | return; | |
13083 | } | |
13084 | ||
13085 | if (p != NULL) | |
13086 | { | |
13087 | assert (S_GET_NAME (p)); | |
13088 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13089 | as_warn (_(".end symbol does not match .ent symbol.")); | |
13090 | } | |
13091 | else | |
13092 | as_warn (_(".end directive missing or unknown symbol")); | |
13093 | ||
13094 | #ifdef MIPS_STABS_ELF | |
13095 | { | |
13096 | segT saved_seg = now_seg; | |
13097 | subsegT saved_subseg = now_subseg; | |
252b5132 | 13098 | valueT dot; |
252b5132 RH |
13099 | expressionS exp; |
13100 | char *fragp; | |
13101 | ||
13102 | dot = frag_now_fix (); | |
13103 | ||
13104 | #ifdef md_flush_pending_output | |
13105 | md_flush_pending_output (); | |
13106 | #endif | |
13107 | ||
13108 | assert (pdr_seg); | |
13109 | subseg_set (pdr_seg, 0); | |
13110 | ||
beae10d5 | 13111 | /* Write the symbol. */ |
252b5132 RH |
13112 | exp.X_op = O_symbol; |
13113 | exp.X_add_symbol = p; | |
13114 | exp.X_add_number = 0; | |
13115 | emit_expr (&exp, 4); | |
13116 | ||
beae10d5 | 13117 | fragp = frag_more (7 * 4); |
252b5132 | 13118 | |
beae10d5 KH |
13119 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
13120 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
13121 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
13122 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
13123 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
13124 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
13125 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
13126 | |
13127 | subseg_set (saved_seg, saved_subseg); | |
13128 | } | |
13129 | #endif | |
13130 | ||
13131 | cur_proc_ptr = NULL; | |
13132 | } | |
13133 | ||
13134 | /* The .aent and .ent directives. */ | |
13135 | ||
13136 | static void | |
13137 | s_mips_ent (aent) | |
13138 | int aent; | |
13139 | { | |
252b5132 RH |
13140 | symbolS *symbolP; |
13141 | int maybe_text; | |
13142 | ||
13143 | symbolP = get_symbol (); | |
13144 | if (*input_line_pointer == ',') | |
13145 | input_line_pointer++; | |
13146 | SKIP_WHITESPACE (); | |
3882b010 | 13147 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13148 | || *input_line_pointer == '-') |
874e8986 | 13149 | get_number (); |
252b5132 RH |
13150 | |
13151 | #ifdef BFD_ASSEMBLER | |
13152 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13153 | maybe_text = 1; | |
13154 | else | |
13155 | maybe_text = 0; | |
13156 | #else | |
13157 | if (now_seg != data_section && now_seg != bss_section) | |
13158 | maybe_text = 1; | |
13159 | else | |
13160 | maybe_text = 0; | |
13161 | #endif | |
13162 | ||
13163 | if (!maybe_text) | |
13164 | as_warn (_(".ent or .aent not in text section.")); | |
13165 | ||
13166 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13167 | as_warn (_("missing .end")); |
252b5132 RH |
13168 | |
13169 | if (!aent) | |
13170 | { | |
7a621144 DJ |
13171 | /* This function needs its own .frame and .cprestore directives. */ |
13172 | mips_frame_reg_valid = 0; | |
13173 | mips_cprestore_valid = 0; | |
13174 | ||
252b5132 RH |
13175 | cur_proc_ptr = &cur_proc; |
13176 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13177 | ||
13178 | cur_proc_ptr->isym = symbolP; | |
13179 | ||
49309057 | 13180 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
13181 | |
13182 | numprocs++; | |
13183 | } | |
13184 | ||
13185 | demand_empty_rest_of_line (); | |
13186 | } | |
13187 | ||
13188 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13189 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13190 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13191 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13192 | symbol table (in the mdebug section). */ |
13193 | ||
13194 | static void | |
13195 | s_mips_frame (ignore) | |
2b3c5a5d | 13196 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
13197 | { |
13198 | #ifdef MIPS_STABS_ELF | |
13199 | ||
13200 | long val; | |
13201 | ||
beae10d5 | 13202 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
13203 | { |
13204 | as_warn (_(".frame outside of .ent")); | |
13205 | demand_empty_rest_of_line (); | |
13206 | return; | |
13207 | } | |
13208 | ||
13209 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
13210 | ||
13211 | SKIP_WHITESPACE (); | |
13212 | if (*input_line_pointer++ != ',' | |
13213 | || get_absolute_expression_and_terminator (&val) != ',') | |
13214 | { | |
13215 | as_warn (_("Bad .frame directive")); | |
13216 | --input_line_pointer; | |
13217 | demand_empty_rest_of_line (); | |
13218 | return; | |
13219 | } | |
13220 | ||
13221 | cur_proc_ptr->frame_offset = val; | |
13222 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
13223 | ||
13224 | demand_empty_rest_of_line (); | |
13225 | #else | |
13226 | s_ignore (ignore); | |
13227 | #endif /* MIPS_STABS_ELF */ | |
13228 | } | |
13229 | ||
bdaaa2e1 KH |
13230 | /* The .fmask and .mask directives. If the mdebug section is present |
13231 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13232 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13233 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13234 | make reference to the ecoff symbol table (in the mdebug section). */ |
13235 | ||
13236 | static void | |
13237 | s_mips_mask (reg_type) | |
13238 | char reg_type; | |
13239 | { | |
13240 | #ifdef MIPS_STABS_ELF | |
13241 | long mask, off; | |
bdaaa2e1 | 13242 | |
252b5132 RH |
13243 | if (cur_proc_ptr == (procS *) NULL) |
13244 | { | |
13245 | as_warn (_(".mask/.fmask outside of .ent")); | |
13246 | demand_empty_rest_of_line (); | |
13247 | return; | |
13248 | } | |
13249 | ||
13250 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
13251 | { | |
13252 | as_warn (_("Bad .mask/.fmask directive")); | |
13253 | --input_line_pointer; | |
13254 | demand_empty_rest_of_line (); | |
13255 | return; | |
13256 | } | |
13257 | ||
13258 | off = get_absolute_expression (); | |
13259 | ||
13260 | if (reg_type == 'F') | |
13261 | { | |
13262 | cur_proc_ptr->fpreg_mask = mask; | |
13263 | cur_proc_ptr->fpreg_offset = off; | |
13264 | } | |
13265 | else | |
13266 | { | |
13267 | cur_proc_ptr->reg_mask = mask; | |
13268 | cur_proc_ptr->reg_offset = off; | |
13269 | } | |
13270 | ||
13271 | demand_empty_rest_of_line (); | |
13272 | #else | |
13273 | s_ignore (reg_type); | |
13274 | #endif /* MIPS_STABS_ELF */ | |
13275 | } | |
13276 | ||
13277 | /* The .loc directive. */ | |
13278 | ||
13279 | #if 0 | |
13280 | static void | |
13281 | s_loc (x) | |
13282 | int x; | |
13283 | { | |
13284 | symbolS *symbolP; | |
13285 | int lineno; | |
13286 | int addroff; | |
13287 | ||
13288 | assert (now_seg == text_section); | |
13289 | ||
13290 | lineno = get_number (); | |
13291 | addroff = frag_now_fix (); | |
13292 | ||
13293 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13294 | S_SET_TYPE (symbolP, N_SLINE); | |
13295 | S_SET_OTHER (symbolP, 0); | |
13296 | S_SET_DESC (symbolP, lineno); | |
13297 | symbolP->sy_segment = now_seg; | |
13298 | } | |
13299 | #endif | |
e7af610e NC |
13300 | |
13301 | /* CPU name/ISA/number mapping table. | |
13302 | ||
13303 | Entries are grouped by type. The first matching CPU or ISA entry | |
13304 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
13305 | for that type. Entries after that within the type are sorted | |
13306 | alphabetically. | |
13307 | ||
13308 | Case is ignored in comparison, so put the canonical entry in the | |
13309 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
13310 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13311 | { | |
e7af610e NC |
13312 | /* MIPS1 ISA */ |
13313 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
13314 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
13315 | ||
13316 | /* MIPS2 ISA */ | |
13317 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
13318 | ||
13319 | /* MIPS3 ISA */ | |
13320 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
13321 | ||
13322 | /* MIPS4 ISA */ | |
13323 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
13324 | ||
84ea6cf2 NC |
13325 | /* MIPS5 ISA */ |
13326 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
13327 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
13328 | ||
e7af610e NC |
13329 | /* MIPS32 ISA */ |
13330 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
3c02b2ab | 13331 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
e7af610e | 13332 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
3c02b2ab EC |
13333 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
13334 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13335 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13336 | ||
13337 | /* For historical reasons. */ | |
13338 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, | |
e7af610e | 13339 | |
84ea6cf2 | 13340 | /* MIPS64 ISA */ |
3c02b2ab | 13341 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
84ea6cf2 | 13342 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
3c02b2ab EC |
13343 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
13344 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
13345 | |
13346 | /* R2000 CPU */ | |
13347 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13348 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13349 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13350 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13351 | ||
13352 | /* R3000 CPU */ | |
13353 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13354 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13355 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13356 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13357 | ||
13358 | /* TX3900 CPU */ | |
13359 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
13360 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 13361 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
13362 | |
13363 | /* R4000 CPU */ | |
13364 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13365 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13366 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
13367 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
13368 | ||
13369 | /* R4010 CPU */ | |
13370 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13371 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13372 | ||
13373 | /* R4400 CPU */ | |
13374 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13375 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13376 | ||
13377 | /* R4600 CPU */ | |
13378 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13379 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13380 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13381 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13382 | ||
13383 | /* R4650 CPU */ | |
13384 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13385 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13386 | ||
13387 | /* R6000 CPU */ | |
13388 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13389 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13390 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13391 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13392 | ||
13393 | /* R8000 CPU */ | |
13394 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13395 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13396 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13397 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13398 | ||
13399 | /* R10000 CPU */ | |
13400 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13401 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13402 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13403 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13404 | ||
d1cf510e NC |
13405 | /* R12000 CPU */ |
13406 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13407 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13408 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13409 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13410 | ||
e7af610e NC |
13411 | /* VR4100 CPU */ |
13412 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13413 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13414 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13415 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13416 | ||
13417 | /* VR4111 CPU */ | |
13418 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13419 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13420 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13421 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13422 | ||
13423 | /* VR4300 CPU */ | |
13424 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13425 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13426 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13427 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13428 | ||
13429 | /* VR5000 CPU */ | |
13430 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13431 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13432 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
13433 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13434 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13435 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 13436 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13437 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13438 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13439 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13440 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13441 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13442 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13443 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13444 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
13445 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
13446 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
13447 | ||
2e4acd24 | 13448 | /* Broadcom SB-1 CPU */ |
c6c98b38 | 13449 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, |
e972090a | 13450 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
13451 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
13452 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
13453 | ||
beae10d5 | 13454 | /* End marker. */ |
e7af610e NC |
13455 | { NULL, 0, 0, 0, }, |
13456 | }; | |
13457 | ||
13458 | static const struct mips_cpu_info * | |
13459 | mips_cpu_info_from_name (name) | |
13460 | const char *name; | |
13461 | { | |
13462 | int i; | |
13463 | ||
13464 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 13465 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
13466 | return (&mips_cpu_info_table[i]); |
13467 | ||
e972090a | 13468 | return NULL; |
e7af610e NC |
13469 | } |
13470 | ||
13471 | static const struct mips_cpu_info * | |
13472 | mips_cpu_info_from_isa (isa) | |
13473 | int isa; | |
13474 | { | |
13475 | int i; | |
13476 | ||
13477 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13478 | if (mips_cpu_info_table[i].is_isa | |
13479 | && isa == mips_cpu_info_table[i].isa) | |
13480 | return (&mips_cpu_info_table[i]); | |
13481 | ||
e972090a | 13482 | return NULL; |
e7af610e NC |
13483 | } |
13484 | ||
13485 | static const struct mips_cpu_info * | |
13486 | mips_cpu_info_from_cpu (cpu) | |
13487 | int cpu; | |
13488 | { | |
13489 | int i; | |
13490 | ||
13491 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13492 | if (!mips_cpu_info_table[i].is_isa | |
13493 | && cpu == mips_cpu_info_table[i].cpu) | |
13494 | return (&mips_cpu_info_table[i]); | |
13495 | ||
e972090a | 13496 | return NULL; |
e7af610e | 13497 | } |