Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
ec2655a6 | 3 | 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
741fe287 | 92 | #define ATREG 1 |
252b5132 RH |
93 | #define TREG 24 |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
741fe287 MR |
104 | #define AT mips_opts.at |
105 | ||
252b5132 RH |
106 | /* Allow override of standard little-endian ECOFF format. */ |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
8b082fb1 | 198 | int ase_dspr2; |
ef2e4d86 | 199 | int ase_mt; |
252b5132 RH |
200 | /* Whether we are assembling for the mips16 processor. 0 if we are |
201 | not, 1 if we are, and -1 if the value has not been initialized. | |
202 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
203 | -nomips16 command line options, and the default CPU. */ | |
204 | int mips16; | |
205 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
206 | reorder' and `.set noreorder'. */ | |
207 | int noreorder; | |
741fe287 MR |
208 | /* Non-zero if we should not permit the register designated "assembler |
209 | temporary" to be used in instructions. The value is the register | |
210 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
211 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
212 | unsigned int at; | |
252b5132 RH |
213 | /* Non-zero if we should warn when a macro instruction expands into |
214 | more than one machine instruction. Changed by `.set nomacro' and | |
215 | `.set macro'. */ | |
216 | int warn_about_macros; | |
217 | /* Non-zero if we should not move instructions. Changed by `.set | |
218 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
219 | int nomove; | |
220 | /* Non-zero if we should not optimize branches by moving the target | |
221 | of the branch into the delay slot. Actually, we don't perform | |
222 | this optimization anyhow. Changed by `.set bopt' and `.set | |
223 | nobopt'. */ | |
224 | int nobopt; | |
225 | /* Non-zero if we should not autoextend mips16 instructions. | |
226 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
227 | int noautoextend; | |
a325df1d TS |
228 | /* Restrict general purpose registers and floating point registers |
229 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
230 | is passed but can changed if the assembler code uses .set mipsN. */ | |
231 | int gp32; | |
232 | int fp32; | |
fef14a42 TS |
233 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
234 | command line option, and the default CPU. */ | |
235 | int arch; | |
aed1a261 RS |
236 | /* True if ".set sym32" is in effect. */ |
237 | bfd_boolean sym32; | |
252b5132 RH |
238 | }; |
239 | ||
a325df1d | 240 | /* True if -mgp32 was passed. */ |
a8e8e863 | 241 | static int file_mips_gp32 = -1; |
a325df1d TS |
242 | |
243 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 244 | static int file_mips_fp32 = -1; |
a325df1d | 245 | |
252b5132 | 246 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 247 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 248 | -1 to indicate that they have not been initialized. */ |
252b5132 | 249 | |
e972090a NC |
250 | static struct mips_set_options mips_opts = |
251 | { | |
741fe287 | 252 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, ATREG, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 253 | }; |
252b5132 RH |
254 | |
255 | /* These variables are filled in with the masks of registers used. | |
256 | The object format code reads them and puts them in the appropriate | |
257 | place. */ | |
258 | unsigned long mips_gprmask; | |
259 | unsigned long mips_cprmask[4]; | |
260 | ||
261 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 262 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 263 | |
a4672219 TS |
264 | /* True if -mips16 was passed or implied by arguments passed on the |
265 | command line (e.g., by -march). */ | |
266 | static int file_ase_mips16; | |
267 | ||
3994f87e TS |
268 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
269 | || mips_opts.isa == ISA_MIPS32R2 \ | |
270 | || mips_opts.isa == ISA_MIPS64 \ | |
271 | || mips_opts.isa == ISA_MIPS64R2) | |
272 | ||
1f25f5d3 CD |
273 | /* True if -mips3d was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_mips3d; | |
276 | ||
deec1734 CD |
277 | /* True if -mdmx was passed or implied by arguments passed on the |
278 | command line (e.g., by -march). */ | |
279 | static int file_ase_mdmx; | |
280 | ||
e16bfa71 TS |
281 | /* True if -msmartmips was passed or implied by arguments passed on the |
282 | command line (e.g., by -march). */ | |
283 | static int file_ase_smartmips; | |
284 | ||
ad3fea08 TS |
285 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
286 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 287 | |
74cd071d CF |
288 | /* True if -mdsp was passed or implied by arguments passed on the |
289 | command line (e.g., by -march). */ | |
290 | static int file_ase_dsp; | |
291 | ||
ad3fea08 TS |
292 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
293 | || mips_opts.isa == ISA_MIPS64R2) | |
294 | ||
65263ce3 TS |
295 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
296 | ||
8b082fb1 TS |
297 | /* True if -mdspr2 was passed or implied by arguments passed on the |
298 | command line (e.g., by -march). */ | |
299 | static int file_ase_dspr2; | |
300 | ||
301 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
302 | || mips_opts.isa == ISA_MIPS64R2) | |
303 | ||
ef2e4d86 CF |
304 | /* True if -mmt was passed or implied by arguments passed on the |
305 | command line (e.g., by -march). */ | |
306 | static int file_ase_mt; | |
307 | ||
ad3fea08 TS |
308 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
309 | || mips_opts.isa == ISA_MIPS64R2) | |
310 | ||
ec68c924 | 311 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 312 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 313 | static const char *mips_arch_string; |
ec68c924 EC |
314 | |
315 | /* The argument of the -mtune= flag. The architecture for which we | |
316 | are optimizing. */ | |
317 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 318 | static const char *mips_tune_string; |
ec68c924 | 319 | |
316f5878 | 320 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
321 | static int mips_32bitmode = 0; |
322 | ||
316f5878 RS |
323 | /* True if the given ABI requires 32-bit registers. */ |
324 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
325 | ||
326 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
327 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
328 | ((ABI) == N32_ABI \ | |
329 | || (ABI) == N64_ABI \ | |
316f5878 RS |
330 | || (ABI) == O64_ABI) |
331 | ||
ad3fea08 | 332 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
333 | #define ISA_HAS_64BIT_REGS(ISA) \ |
334 | ((ISA) == ISA_MIPS3 \ | |
335 | || (ISA) == ISA_MIPS4 \ | |
336 | || (ISA) == ISA_MIPS5 \ | |
337 | || (ISA) == ISA_MIPS64 \ | |
338 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 339 | |
ad3fea08 TS |
340 | /* Return true if ISA supports 64 bit wide float registers. */ |
341 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
342 | ((ISA) == ISA_MIPS3 \ | |
343 | || (ISA) == ISA_MIPS4 \ | |
344 | || (ISA) == ISA_MIPS5 \ | |
345 | || (ISA) == ISA_MIPS32R2 \ | |
346 | || (ISA) == ISA_MIPS64 \ | |
347 | || (ISA) == ISA_MIPS64R2) | |
348 | ||
af7ee8bf CD |
349 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
350 | instructions. */ | |
707bfff6 TS |
351 | #define ISA_HAS_DROR(ISA) \ |
352 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
353 | |
354 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
355 | instructions. */ | |
707bfff6 TS |
356 | #define ISA_HAS_ROR(ISA) \ |
357 | ((ISA) == ISA_MIPS32R2 \ | |
358 | || (ISA) == ISA_MIPS64R2 \ | |
359 | || mips_opts.ase_smartmips) | |
360 | ||
7455baf8 TS |
361 | /* Return true if ISA supports single-precision floats in odd registers. */ |
362 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
363 | ((ISA) == ISA_MIPS32 \ | |
364 | || (ISA) == ISA_MIPS32R2 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
366 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 367 | |
ad3fea08 TS |
368 | /* Return true if ISA supports move to/from high part of a 64-bit |
369 | floating-point register. */ | |
370 | #define ISA_HAS_MXHC1(ISA) \ | |
371 | ((ISA) == ISA_MIPS32R2 \ | |
372 | || (ISA) == ISA_MIPS64R2) | |
373 | ||
e013f690 | 374 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 375 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 376 | |
e013f690 | 377 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 378 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 379 | |
ad3fea08 TS |
380 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
381 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 382 | |
316f5878 | 383 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 384 | |
316f5878 | 385 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 386 | |
3b91255e RS |
387 | /* True if relocations are stored in-place. */ |
388 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
389 | ||
aed1a261 RS |
390 | /* The ABI-derived address size. */ |
391 | #define HAVE_64BIT_ADDRESSES \ | |
392 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
393 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 394 | |
aed1a261 RS |
395 | /* The size of symbolic constants (i.e., expressions of the form |
396 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
397 | #define HAVE_32BIT_SYMBOLS \ | |
398 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
399 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 400 | |
b7c7d6c1 TS |
401 | /* Addresses are loaded in different ways, depending on the address size |
402 | in use. The n32 ABI Documentation also mandates the use of additions | |
403 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 404 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 405 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
406 | |
407 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 408 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
409 | |
410 | #define ADDRESS_LOAD_INSN \ | |
411 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
412 | ||
413 | #define ADDRESS_STORE_INSN \ | |
414 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
415 | ||
a4672219 | 416 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
417 | #define CPU_HAS_MIPS16(cpu) \ |
418 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
419 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 420 | |
60b63b72 RS |
421 | /* True if CPU has a dror instruction. */ |
422 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
423 | ||
424 | /* True if CPU has a ror instruction. */ | |
425 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
426 | ||
c8978940 CD |
427 | /* True if mflo and mfhi can be immediately followed by instructions |
428 | which write to the HI and LO registers. | |
429 | ||
430 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
431 | (at least) two instructions between the reads of HI/LO and | |
432 | instructions which write them, and later ISAs do not. Contradicting | |
433 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
434 | the UM for the NEC Vr5000) document needing the instructions between | |
435 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
436 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
437 | earlier-ISA CPUs for which CPU documentation declares that the | |
438 | instructions are really interlocked. */ | |
439 | #define hilo_interlocks \ | |
440 | (mips_opts.isa == ISA_MIPS32 \ | |
441 | || mips_opts.isa == ISA_MIPS32R2 \ | |
442 | || mips_opts.isa == ISA_MIPS64 \ | |
443 | || mips_opts.isa == ISA_MIPS64R2 \ | |
444 | || mips_opts.arch == CPU_R4010 \ | |
445 | || mips_opts.arch == CPU_R10000 \ | |
446 | || mips_opts.arch == CPU_R12000 \ | |
447 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
448 | || mips_opts.arch == CPU_VR5500 \ |
449 | ) | |
252b5132 RH |
450 | |
451 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
452 | from the GPRs after they are loaded from memory, and thus does not |
453 | require nops to be inserted. This applies to instructions marked | |
454 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
455 | level I. */ | |
252b5132 | 456 | #define gpr_interlocks \ |
e7af610e | 457 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 458 | || mips_opts.arch == CPU_R3900) |
252b5132 | 459 | |
81912461 ILT |
460 | /* Whether the processor uses hardware interlocks to avoid delays |
461 | required by coprocessor instructions, and thus does not require | |
462 | nops to be inserted. This applies to instructions marked | |
463 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
464 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
465 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
466 | levels I, II, and III. */ | |
bdaaa2e1 | 467 | /* Itbl support may require additional care here. */ |
81912461 ILT |
468 | #define cop_interlocks \ |
469 | ((mips_opts.isa != ISA_MIPS1 \ | |
470 | && mips_opts.isa != ISA_MIPS2 \ | |
471 | && mips_opts.isa != ISA_MIPS3) \ | |
472 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
473 | ) |
474 | ||
475 | /* Whether the processor uses hardware interlocks to protect reads | |
476 | from coprocessor registers after they are loaded from memory, and | |
477 | thus does not require nops to be inserted. This applies to | |
478 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
479 | requires at MIPS ISA level I. */ | |
480 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 481 | |
6b76fefe CM |
482 | /* Is this a mfhi or mflo instruction? */ |
483 | #define MF_HILO_INSN(PINFO) \ | |
484 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
485 | ||
252b5132 RH |
486 | /* MIPS PIC level. */ |
487 | ||
a161fe53 | 488 | enum mips_pic_level mips_pic; |
252b5132 | 489 | |
c9914766 | 490 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 491 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 492 | static int mips_big_got = 0; |
252b5132 RH |
493 | |
494 | /* 1 if trap instructions should used for overflow rather than break | |
495 | instructions. */ | |
c9914766 | 496 | static int mips_trap = 0; |
252b5132 | 497 | |
119d663a | 498 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 499 | by assembling two single width halves into two single width floating |
119d663a NC |
500 | point registers which just happen to alias the double width destination |
501 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 502 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
503 | automatically at assemble time. */ |
504 | static int mips_disable_float_construction; | |
505 | ||
252b5132 RH |
506 | /* Non-zero if any .set noreorder directives were used. */ |
507 | ||
508 | static int mips_any_noreorder; | |
509 | ||
6b76fefe CM |
510 | /* Non-zero if nops should be inserted when the register referenced in |
511 | an mfhi/mflo instruction is read in the next two instructions. */ | |
512 | static int mips_7000_hilo_fix; | |
513 | ||
02ffd3e4 | 514 | /* The size of objects in the small data section. */ |
156c2f8b | 515 | static unsigned int g_switch_value = 8; |
252b5132 RH |
516 | /* Whether the -G option was used. */ |
517 | static int g_switch_seen = 0; | |
518 | ||
519 | #define N_RMASK 0xc4 | |
520 | #define N_VFP 0xd4 | |
521 | ||
522 | /* If we can determine in advance that GP optimization won't be | |
523 | possible, we can skip the relaxation stuff that tries to produce | |
524 | GP-relative references. This makes delay slot optimization work | |
525 | better. | |
526 | ||
527 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
528 | gcc output. It needs to guess right for gcc, otherwise gcc |
529 | will put what it thinks is a GP-relative instruction in a branch | |
530 | delay slot. | |
252b5132 RH |
531 | |
532 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
533 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 534 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
535 | |
536 | /* handle of the OPCODE hash table */ | |
537 | static struct hash_control *op_hash = NULL; | |
538 | ||
539 | /* The opcode hash table we use for the mips16. */ | |
540 | static struct hash_control *mips16_op_hash = NULL; | |
541 | ||
542 | /* This array holds the chars that always start a comment. If the | |
543 | pre-processor is disabled, these aren't very useful */ | |
544 | const char comment_chars[] = "#"; | |
545 | ||
546 | /* This array holds the chars that only start a comment at the beginning of | |
547 | a line. If the line seems to have the form '# 123 filename' | |
548 | .line and .file directives will appear in the pre-processed output */ | |
549 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
550 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 551 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
552 | /* Also note that C style comments are always supported. */ |
553 | const char line_comment_chars[] = "#"; | |
554 | ||
bdaaa2e1 | 555 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 556 | const char line_separator_chars[] = ";"; |
252b5132 RH |
557 | |
558 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
559 | const char EXP_CHARS[] = "eE"; | |
560 | ||
561 | /* Chars that mean this number is a floating point constant */ | |
562 | /* As in 0f12.456 */ | |
563 | /* or 0d1.2345e12 */ | |
564 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
565 | ||
566 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
567 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
568 | but nothing is ideal around here. | |
569 | */ | |
570 | ||
571 | static char *insn_error; | |
572 | ||
573 | static int auto_align = 1; | |
574 | ||
575 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
576 | offset in the stack frame from which to restore the $gp register. | |
577 | This is set by the .cprestore pseudo-op, and saved in this | |
578 | variable. */ | |
579 | static offsetT mips_cprestore_offset = -1; | |
580 | ||
67c1ffbe | 581 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 582 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 583 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
584 | static offsetT mips_cpreturn_offset = -1; |
585 | static int mips_cpreturn_register = -1; | |
586 | static int mips_gp_register = GP; | |
def2e0dd | 587 | static int mips_gprel_offset = 0; |
6478892d | 588 | |
7a621144 DJ |
589 | /* Whether mips_cprestore_offset has been set in the current function |
590 | (or whether it has already been warned about, if not). */ | |
591 | static int mips_cprestore_valid = 0; | |
592 | ||
252b5132 RH |
593 | /* This is the register which holds the stack frame, as set by the |
594 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
595 | static int mips_frame_reg = SP; | |
596 | ||
7a621144 DJ |
597 | /* Whether mips_frame_reg has been set in the current function |
598 | (or whether it has already been warned about, if not). */ | |
599 | static int mips_frame_reg_valid = 0; | |
600 | ||
252b5132 RH |
601 | /* To output NOP instructions correctly, we need to keep information |
602 | about the previous two instructions. */ | |
603 | ||
604 | /* Whether we are optimizing. The default value of 2 means to remove | |
605 | unneeded NOPs and swap branch instructions when possible. A value | |
606 | of 1 means to not swap branches. A value of 0 means to always | |
607 | insert NOPs. */ | |
608 | static int mips_optimize = 2; | |
609 | ||
610 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
611 | equivalent to seeing no -g option at all. */ | |
612 | static int mips_debug = 0; | |
613 | ||
7d8e00cf RS |
614 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
615 | #define MAX_VR4130_NOPS 4 | |
616 | ||
617 | /* The maximum number of NOPs needed to fill delay slots. */ | |
618 | #define MAX_DELAY_NOPS 2 | |
619 | ||
620 | /* The maximum number of NOPs needed for any purpose. */ | |
621 | #define MAX_NOPS 4 | |
71400594 RS |
622 | |
623 | /* A list of previous instructions, with index 0 being the most recent. | |
624 | We need to look back MAX_NOPS instructions when filling delay slots | |
625 | or working around processor errata. We need to look back one | |
626 | instruction further if we're thinking about using history[0] to | |
627 | fill a branch delay slot. */ | |
628 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 629 | |
1e915849 RS |
630 | /* Nop instructions used by emit_nop. */ |
631 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
632 | ||
633 | /* The appropriate nop for the current mode. */ | |
634 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 635 | |
252b5132 RH |
636 | /* If this is set, it points to a frag holding nop instructions which |
637 | were inserted before the start of a noreorder section. If those | |
638 | nops turn out to be unnecessary, the size of the frag can be | |
639 | decreased. */ | |
640 | static fragS *prev_nop_frag; | |
641 | ||
642 | /* The number of nop instructions we created in prev_nop_frag. */ | |
643 | static int prev_nop_frag_holds; | |
644 | ||
645 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 646 | prev_nop_frag. */ |
252b5132 RH |
647 | static int prev_nop_frag_required; |
648 | ||
649 | /* The number of instructions we've seen since prev_nop_frag. */ | |
650 | static int prev_nop_frag_since; | |
651 | ||
652 | /* For ECOFF and ELF, relocations against symbols are done in two | |
653 | parts, with a HI relocation and a LO relocation. Each relocation | |
654 | has only 16 bits of space to store an addend. This means that in | |
655 | order for the linker to handle carries correctly, it must be able | |
656 | to locate both the HI and the LO relocation. This means that the | |
657 | relocations must appear in order in the relocation table. | |
658 | ||
659 | In order to implement this, we keep track of each unmatched HI | |
660 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 661 | corresponding LO relocation. */ |
252b5132 | 662 | |
e972090a NC |
663 | struct mips_hi_fixup |
664 | { | |
252b5132 RH |
665 | /* Next HI fixup. */ |
666 | struct mips_hi_fixup *next; | |
667 | /* This fixup. */ | |
668 | fixS *fixp; | |
669 | /* The section this fixup is in. */ | |
670 | segT seg; | |
671 | }; | |
672 | ||
673 | /* The list of unmatched HI relocs. */ | |
674 | ||
675 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
676 | ||
64bdfcaf RS |
677 | /* The frag containing the last explicit relocation operator. |
678 | Null if explicit relocations have not been used. */ | |
679 | ||
680 | static fragS *prev_reloc_op_frag; | |
681 | ||
252b5132 RH |
682 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
683 | ||
684 | #define X ILLEGAL_REG | |
e972090a NC |
685 | static const int mips32_to_16_reg_map[] = |
686 | { | |
252b5132 RH |
687 | X, X, 2, 3, 4, 5, 6, 7, |
688 | X, X, X, X, X, X, X, X, | |
689 | 0, 1, X, X, X, X, X, X, | |
690 | X, X, X, X, X, X, X, X | |
691 | }; | |
692 | #undef X | |
693 | ||
694 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
695 | ||
e972090a NC |
696 | static const unsigned int mips16_to_32_reg_map[] = |
697 | { | |
252b5132 RH |
698 | 16, 17, 2, 3, 4, 5, 6, 7 |
699 | }; | |
60b63b72 | 700 | |
71400594 RS |
701 | /* Classifies the kind of instructions we're interested in when |
702 | implementing -mfix-vr4120. */ | |
703 | enum fix_vr4120_class { | |
704 | FIX_VR4120_MACC, | |
705 | FIX_VR4120_DMACC, | |
706 | FIX_VR4120_MULT, | |
707 | FIX_VR4120_DMULT, | |
708 | FIX_VR4120_DIV, | |
709 | FIX_VR4120_MTHILO, | |
710 | NUM_FIX_VR4120_CLASSES | |
711 | }; | |
712 | ||
713 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
714 | there must be at least one other instruction between an instruction | |
715 | of type X and an instruction of type Y. */ | |
716 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
717 | ||
718 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 719 | static int mips_fix_vr4120; |
4a6a3df4 | 720 | |
7d8e00cf RS |
721 | /* ...likewise -mfix-vr4130. */ |
722 | static int mips_fix_vr4130; | |
723 | ||
4a6a3df4 AO |
724 | /* We don't relax branches by default, since this causes us to expand |
725 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
726 | fail to compute the offset before expanding the macro to the most | |
727 | efficient expansion. */ | |
728 | ||
729 | static int mips_relax_branch; | |
252b5132 | 730 | \f |
4d7206a2 RS |
731 | /* The expansion of many macros depends on the type of symbol that |
732 | they refer to. For example, when generating position-dependent code, | |
733 | a macro that refers to a symbol may have two different expansions, | |
734 | one which uses GP-relative addresses and one which uses absolute | |
735 | addresses. When generating SVR4-style PIC, a macro may have | |
736 | different expansions for local and global symbols. | |
737 | ||
738 | We handle these situations by generating both sequences and putting | |
739 | them in variant frags. In position-dependent code, the first sequence | |
740 | will be the GP-relative one and the second sequence will be the | |
741 | absolute one. In SVR4 PIC, the first sequence will be for global | |
742 | symbols and the second will be for local symbols. | |
743 | ||
584892a6 RS |
744 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
745 | SECOND are the lengths of the two sequences in bytes. These fields | |
746 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
747 | the subtype has the following flags: | |
4d7206a2 | 748 | |
584892a6 RS |
749 | RELAX_USE_SECOND |
750 | Set if it has been decided that we should use the second | |
751 | sequence instead of the first. | |
752 | ||
753 | RELAX_SECOND_LONGER | |
754 | Set in the first variant frag if the macro's second implementation | |
755 | is longer than its first. This refers to the macro as a whole, | |
756 | not an individual relaxation. | |
757 | ||
758 | RELAX_NOMACRO | |
759 | Set in the first variant frag if the macro appeared in a .set nomacro | |
760 | block and if one alternative requires a warning but the other does not. | |
761 | ||
762 | RELAX_DELAY_SLOT | |
763 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
764 | delay slot. | |
4d7206a2 RS |
765 | |
766 | The frag's "opcode" points to the first fixup for relaxable code. | |
767 | ||
768 | Relaxable macros are generated using a sequence such as: | |
769 | ||
770 | relax_start (SYMBOL); | |
771 | ... generate first expansion ... | |
772 | relax_switch (); | |
773 | ... generate second expansion ... | |
774 | relax_end (); | |
775 | ||
776 | The code and fixups for the unwanted alternative are discarded | |
777 | by md_convert_frag. */ | |
584892a6 | 778 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 779 | |
584892a6 RS |
780 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
781 | #define RELAX_SECOND(X) ((X) & 0xff) | |
782 | #define RELAX_USE_SECOND 0x10000 | |
783 | #define RELAX_SECOND_LONGER 0x20000 | |
784 | #define RELAX_NOMACRO 0x40000 | |
785 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 786 | |
4a6a3df4 AO |
787 | /* Branch without likely bit. If label is out of range, we turn: |
788 | ||
789 | beq reg1, reg2, label | |
790 | delay slot | |
791 | ||
792 | into | |
793 | ||
794 | bne reg1, reg2, 0f | |
795 | nop | |
796 | j label | |
797 | 0: delay slot | |
798 | ||
799 | with the following opcode replacements: | |
800 | ||
801 | beq <-> bne | |
802 | blez <-> bgtz | |
803 | bltz <-> bgez | |
804 | bc1f <-> bc1t | |
805 | ||
806 | bltzal <-> bgezal (with jal label instead of j label) | |
807 | ||
808 | Even though keeping the delay slot instruction in the delay slot of | |
809 | the branch would be more efficient, it would be very tricky to do | |
810 | correctly, because we'd have to introduce a variable frag *after* | |
811 | the delay slot instruction, and expand that instead. Let's do it | |
812 | the easy way for now, even if the branch-not-taken case now costs | |
813 | one additional instruction. Out-of-range branches are not supposed | |
814 | to be common, anyway. | |
815 | ||
816 | Branch likely. If label is out of range, we turn: | |
817 | ||
818 | beql reg1, reg2, label | |
819 | delay slot (annulled if branch not taken) | |
820 | ||
821 | into | |
822 | ||
823 | beql reg1, reg2, 1f | |
824 | nop | |
825 | beql $0, $0, 2f | |
826 | nop | |
827 | 1: j[al] label | |
828 | delay slot (executed only if branch taken) | |
829 | 2: | |
830 | ||
831 | It would be possible to generate a shorter sequence by losing the | |
832 | likely bit, generating something like: | |
b34976b6 | 833 | |
4a6a3df4 AO |
834 | bne reg1, reg2, 0f |
835 | nop | |
836 | j[al] label | |
837 | delay slot (executed only if branch taken) | |
838 | 0: | |
839 | ||
840 | beql -> bne | |
841 | bnel -> beq | |
842 | blezl -> bgtz | |
843 | bgtzl -> blez | |
844 | bltzl -> bgez | |
845 | bgezl -> bltz | |
846 | bc1fl -> bc1t | |
847 | bc1tl -> bc1f | |
848 | ||
849 | bltzall -> bgezal (with jal label instead of j label) | |
850 | bgezall -> bltzal (ditto) | |
851 | ||
852 | ||
853 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 854 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
855 | ((relax_substateT) \ |
856 | (0xc0000000 \ | |
857 | | ((toofar) ? 1 : 0) \ | |
858 | | ((link) ? 2 : 0) \ | |
859 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 860 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 861 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
862 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
863 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
864 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 865 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 866 | |
252b5132 RH |
867 | /* For mips16 code, we use an entirely different form of relaxation. |
868 | mips16 supports two versions of most instructions which take | |
869 | immediate values: a small one which takes some small value, and a | |
870 | larger one which takes a 16 bit value. Since branches also follow | |
871 | this pattern, relaxing these values is required. | |
872 | ||
873 | We can assemble both mips16 and normal MIPS code in a single | |
874 | object. Therefore, we need to support this type of relaxation at | |
875 | the same time that we support the relaxation described above. We | |
876 | use the high bit of the subtype field to distinguish these cases. | |
877 | ||
878 | The information we store for this type of relaxation is the | |
879 | argument code found in the opcode file for this relocation, whether | |
880 | the user explicitly requested a small or extended form, and whether | |
881 | the relocation is in a jump or jal delay slot. That tells us the | |
882 | size of the value, and how it should be stored. We also store | |
883 | whether the fragment is considered to be extended or not. We also | |
884 | store whether this is known to be a branch to a different section, | |
885 | whether we have tried to relax this frag yet, and whether we have | |
886 | ever extended a PC relative fragment because of a shift count. */ | |
887 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
888 | (0x80000000 \ | |
889 | | ((type) & 0xff) \ | |
890 | | ((small) ? 0x100 : 0) \ | |
891 | | ((ext) ? 0x200 : 0) \ | |
892 | | ((dslot) ? 0x400 : 0) \ | |
893 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 894 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
895 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
896 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
897 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
898 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
899 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
900 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
901 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
902 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
903 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
904 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
905 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
906 | |
907 | /* Is the given value a sign-extended 32-bit value? */ | |
908 | #define IS_SEXT_32BIT_NUM(x) \ | |
909 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
910 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
911 | ||
912 | /* Is the given value a sign-extended 16-bit value? */ | |
913 | #define IS_SEXT_16BIT_NUM(x) \ | |
914 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
915 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
916 | ||
2051e8c4 MR |
917 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
918 | #define IS_ZEXT_32BIT_NUM(x) \ | |
919 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
920 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
921 | ||
bf12938e RS |
922 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
923 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
924 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
925 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
926 | | (((VALUE) & (MASK)) << (SHIFT))) | |
927 | ||
928 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
929 | SHIFT places. */ | |
930 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
931 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
932 | ||
933 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
934 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
935 | ||
936 | include/opcode/mips.h specifies operand fields using the macros | |
937 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
938 | with "MIPS16OP" instead of "OP". */ | |
939 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
940 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
941 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
942 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
943 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
944 | ||
945 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
946 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
947 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
948 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
949 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
950 | MIPS16OP_MASK_##FIELD, \ | |
951 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
952 | \f |
953 | /* Global variables used when generating relaxable macros. See the | |
954 | comment above RELAX_ENCODE for more details about how relaxation | |
955 | is used. */ | |
956 | static struct { | |
957 | /* 0 if we're not emitting a relaxable macro. | |
958 | 1 if we're emitting the first of the two relaxation alternatives. | |
959 | 2 if we're emitting the second alternative. */ | |
960 | int sequence; | |
961 | ||
962 | /* The first relaxable fixup in the current frag. (In other words, | |
963 | the first fixup that refers to relaxable code.) */ | |
964 | fixS *first_fixup; | |
965 | ||
966 | /* sizes[0] says how many bytes of the first alternative are stored in | |
967 | the current frag. Likewise sizes[1] for the second alternative. */ | |
968 | unsigned int sizes[2]; | |
969 | ||
970 | /* The symbol on which the choice of sequence depends. */ | |
971 | symbolS *symbol; | |
972 | } mips_relax; | |
252b5132 | 973 | \f |
584892a6 RS |
974 | /* Global variables used to decide whether a macro needs a warning. */ |
975 | static struct { | |
976 | /* True if the macro is in a branch delay slot. */ | |
977 | bfd_boolean delay_slot_p; | |
978 | ||
979 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
980 | in bytes and sizes[1] is the length of the second alternative. | |
981 | For non-relaxable macros, both elements give the length of the | |
982 | macro in bytes. */ | |
983 | unsigned int sizes[2]; | |
984 | ||
985 | /* The first variant frag for this macro. */ | |
986 | fragS *first_frag; | |
987 | } mips_macro_warning; | |
988 | \f | |
252b5132 RH |
989 | /* Prototypes for static functions. */ |
990 | ||
17a2f251 | 991 | #define internalError() \ |
252b5132 | 992 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
993 | |
994 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
995 | ||
b34976b6 | 996 | static void append_insn |
4d7206a2 | 997 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 998 | static void mips_no_prev_insn (void); |
b34976b6 | 999 | static void mips16_macro_build |
67c0d1eb RS |
1000 | (expressionS *, const char *, const char *, va_list); |
1001 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
1002 | static void macro_start (void); |
1003 | static void macro_end (void); | |
17a2f251 TS |
1004 | static void macro (struct mips_cl_insn * ip); |
1005 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1006 | #ifdef LOSING_COMPILER |
17a2f251 | 1007 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1008 | #endif |
17a2f251 TS |
1009 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1010 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1011 | static void mips16_immed |
17a2f251 TS |
1012 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1013 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1014 | static size_t my_getSmallExpression |
17a2f251 TS |
1015 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1016 | static void my_getExpression (expressionS *, char *); | |
1017 | static void s_align (int); | |
1018 | static void s_change_sec (int); | |
1019 | static void s_change_section (int); | |
1020 | static void s_cons (int); | |
1021 | static void s_float_cons (int); | |
1022 | static void s_mips_globl (int); | |
1023 | static void s_option (int); | |
1024 | static void s_mipsset (int); | |
1025 | static void s_abicalls (int); | |
1026 | static void s_cpload (int); | |
1027 | static void s_cpsetup (int); | |
1028 | static void s_cplocal (int); | |
1029 | static void s_cprestore (int); | |
1030 | static void s_cpreturn (int); | |
741d6ea8 JM |
1031 | static void s_dtprelword (int); |
1032 | static void s_dtpreldword (int); | |
17a2f251 TS |
1033 | static void s_gpvalue (int); |
1034 | static void s_gpword (int); | |
1035 | static void s_gpdword (int); | |
1036 | static void s_cpadd (int); | |
1037 | static void s_insn (int); | |
1038 | static void md_obj_begin (void); | |
1039 | static void md_obj_end (void); | |
1040 | static void s_mips_ent (int); | |
1041 | static void s_mips_end (int); | |
1042 | static void s_mips_frame (int); | |
1043 | static void s_mips_mask (int reg_type); | |
1044 | static void s_mips_stab (int); | |
1045 | static void s_mips_weakext (int); | |
1046 | static void s_mips_file (int); | |
1047 | static void s_mips_loc (int); | |
1048 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1049 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1050 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1051 | |
1052 | /* Table and functions used to map between CPU/ISA names, and | |
1053 | ISA levels, and CPU numbers. */ | |
1054 | ||
e972090a NC |
1055 | struct mips_cpu_info |
1056 | { | |
e7af610e | 1057 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1058 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1059 | int isa; /* ISA level. */ |
1060 | int cpu; /* CPU number (default CPU if ISA). */ | |
1061 | }; | |
1062 | ||
ad3fea08 TS |
1063 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1064 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1065 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1066 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1067 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1068 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1069 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1070 | |
17a2f251 TS |
1071 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1072 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1073 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1074 | \f |
1075 | /* Pseudo-op table. | |
1076 | ||
1077 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1078 | should be defined here, but are currently unsupported: .alias, | |
1079 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1080 | ||
1081 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1082 | specific to the type of debugging information being generated, and | |
1083 | should be defined by the object format: .aent, .begin, .bend, | |
1084 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1085 | .vreg. | |
1086 | ||
1087 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1088 | not MIPS CPU specific, but are also not specific to the object file | |
1089 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1090 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1091 | |
e972090a NC |
1092 | static const pseudo_typeS mips_pseudo_table[] = |
1093 | { | |
beae10d5 | 1094 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1095 | {"option", s_option, 0}, |
1096 | {"set", s_mipsset, 0}, | |
1097 | {"rdata", s_change_sec, 'r'}, | |
1098 | {"sdata", s_change_sec, 's'}, | |
1099 | {"livereg", s_ignore, 0}, | |
1100 | {"abicalls", s_abicalls, 0}, | |
1101 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1102 | {"cpsetup", s_cpsetup, 0}, |
1103 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1104 | {"cprestore", s_cprestore, 0}, |
6478892d | 1105 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1106 | {"dtprelword", s_dtprelword, 0}, |
1107 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1108 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1109 | {"gpword", s_gpword, 0}, |
10181a0d | 1110 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1111 | {"cpadd", s_cpadd, 0}, |
1112 | {"insn", s_insn, 0}, | |
1113 | ||
beae10d5 | 1114 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1115 | chips. */ |
38a57ae7 | 1116 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1117 | {"bss", s_change_sec, 'b'}, |
1118 | {"err", s_err, 0}, | |
1119 | {"half", s_cons, 1}, | |
1120 | {"dword", s_cons, 3}, | |
1121 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1122 | {"origin", s_org, 0}, |
1123 | {"repeat", s_rept, 0}, | |
252b5132 | 1124 | |
beae10d5 | 1125 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1126 | here for one reason or another. */ |
1127 | {"align", s_align, 0}, | |
1128 | {"byte", s_cons, 0}, | |
1129 | {"data", s_change_sec, 'd'}, | |
1130 | {"double", s_float_cons, 'd'}, | |
1131 | {"float", s_float_cons, 'f'}, | |
1132 | {"globl", s_mips_globl, 0}, | |
1133 | {"global", s_mips_globl, 0}, | |
1134 | {"hword", s_cons, 1}, | |
1135 | {"int", s_cons, 2}, | |
1136 | {"long", s_cons, 2}, | |
1137 | {"octa", s_cons, 4}, | |
1138 | {"quad", s_cons, 3}, | |
cca86cc8 | 1139 | {"section", s_change_section, 0}, |
252b5132 RH |
1140 | {"short", s_cons, 1}, |
1141 | {"single", s_float_cons, 'f'}, | |
1142 | {"stabn", s_mips_stab, 'n'}, | |
1143 | {"text", s_change_sec, 't'}, | |
1144 | {"word", s_cons, 2}, | |
add56521 | 1145 | |
add56521 | 1146 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1147 | |
43841e91 | 1148 | { NULL, NULL, 0 }, |
252b5132 RH |
1149 | }; |
1150 | ||
e972090a NC |
1151 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1152 | { | |
beae10d5 KH |
1153 | /* These pseudo-ops should be defined by the object file format. |
1154 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1155 | {"aent", s_mips_ent, 1}, |
1156 | {"bgnb", s_ignore, 0}, | |
1157 | {"end", s_mips_end, 0}, | |
1158 | {"endb", s_ignore, 0}, | |
1159 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1160 | {"file", s_mips_file, 0}, |
252b5132 RH |
1161 | {"fmask", s_mips_mask, 'F'}, |
1162 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1163 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1164 | {"mask", s_mips_mask, 'R'}, |
1165 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1166 | { NULL, NULL, 0 }, |
252b5132 RH |
1167 | }; |
1168 | ||
17a2f251 | 1169 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1170 | |
1171 | void | |
17a2f251 | 1172 | mips_pop_insert (void) |
252b5132 RH |
1173 | { |
1174 | pop_insert (mips_pseudo_table); | |
1175 | if (! ECOFF_DEBUGGING) | |
1176 | pop_insert (mips_nonecoff_pseudo_table); | |
1177 | } | |
1178 | \f | |
1179 | /* Symbols labelling the current insn. */ | |
1180 | ||
e972090a NC |
1181 | struct insn_label_list |
1182 | { | |
252b5132 RH |
1183 | struct insn_label_list *next; |
1184 | symbolS *label; | |
1185 | }; | |
1186 | ||
252b5132 | 1187 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1188 | #define label_list tc_segment_info_data.labels |
252b5132 | 1189 | |
17a2f251 | 1190 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1191 | |
1192 | static inline void | |
17a2f251 | 1193 | mips_clear_insn_labels (void) |
252b5132 RH |
1194 | { |
1195 | register struct insn_label_list **pl; | |
a8dbcb85 | 1196 | segment_info_type *si; |
252b5132 | 1197 | |
a8dbcb85 TS |
1198 | if (now_seg) |
1199 | { | |
1200 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1201 | ; | |
1202 | ||
1203 | si = seg_info (now_seg); | |
1204 | *pl = si->label_list; | |
1205 | si->label_list = NULL; | |
1206 | } | |
252b5132 | 1207 | } |
a8dbcb85 | 1208 | |
252b5132 RH |
1209 | \f |
1210 | static char *expr_end; | |
1211 | ||
1212 | /* Expressions which appear in instructions. These are set by | |
1213 | mips_ip. */ | |
1214 | ||
1215 | static expressionS imm_expr; | |
5f74bc13 | 1216 | static expressionS imm2_expr; |
252b5132 RH |
1217 | static expressionS offset_expr; |
1218 | ||
1219 | /* Relocs associated with imm_expr and offset_expr. */ | |
1220 | ||
f6688943 TS |
1221 | static bfd_reloc_code_real_type imm_reloc[3] |
1222 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1223 | static bfd_reloc_code_real_type offset_reloc[3] | |
1224 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1225 | |
252b5132 RH |
1226 | /* These are set by mips16_ip if an explicit extension is used. */ |
1227 | ||
b34976b6 | 1228 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1229 | |
7ed4a06a | 1230 | #ifdef OBJ_ELF |
ecb4347a DJ |
1231 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1232 | ECOFF debugging. */ | |
252b5132 RH |
1233 | |
1234 | static segT pdr_seg; | |
7ed4a06a | 1235 | #endif |
252b5132 | 1236 | |
e013f690 TS |
1237 | /* The default target format to use. */ |
1238 | ||
1239 | const char * | |
17a2f251 | 1240 | mips_target_format (void) |
e013f690 TS |
1241 | { |
1242 | switch (OUTPUT_FLAVOR) | |
1243 | { | |
e013f690 TS |
1244 | case bfd_target_ecoff_flavour: |
1245 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1246 | case bfd_target_coff_flavour: | |
1247 | return "pe-mips"; | |
1248 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1249 | #ifdef TE_VXWORKS |
1250 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1251 | return (target_big_endian | |
1252 | ? "elf32-bigmips-vxworks" | |
1253 | : "elf32-littlemips-vxworks"); | |
1254 | #endif | |
e013f690 | 1255 | #ifdef TE_TMIPS |
cfe86eaa | 1256 | /* This is traditional mips. */ |
e013f690 | 1257 | return (target_big_endian |
cfe86eaa TS |
1258 | ? (HAVE_64BIT_OBJECTS |
1259 | ? "elf64-tradbigmips" | |
1260 | : (HAVE_NEWABI | |
1261 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1262 | : (HAVE_64BIT_OBJECTS | |
1263 | ? "elf64-tradlittlemips" | |
1264 | : (HAVE_NEWABI | |
1265 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1266 | #else |
1267 | return (target_big_endian | |
cfe86eaa TS |
1268 | ? (HAVE_64BIT_OBJECTS |
1269 | ? "elf64-bigmips" | |
1270 | : (HAVE_NEWABI | |
1271 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1272 | : (HAVE_64BIT_OBJECTS | |
1273 | ? "elf64-littlemips" | |
1274 | : (HAVE_NEWABI | |
1275 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1276 | #endif |
1277 | default: | |
1278 | abort (); | |
1279 | return NULL; | |
1280 | } | |
1281 | } | |
1282 | ||
1e915849 RS |
1283 | /* Return the length of instruction INSN. */ |
1284 | ||
1285 | static inline unsigned int | |
1286 | insn_length (const struct mips_cl_insn *insn) | |
1287 | { | |
1288 | if (!mips_opts.mips16) | |
1289 | return 4; | |
1290 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1291 | } | |
1292 | ||
1293 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1294 | ||
1295 | static void | |
1296 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1297 | { | |
1298 | size_t i; | |
1299 | ||
1300 | insn->insn_mo = mo; | |
1301 | insn->use_extend = FALSE; | |
1302 | insn->extend = 0; | |
1303 | insn->insn_opcode = mo->match; | |
1304 | insn->frag = NULL; | |
1305 | insn->where = 0; | |
1306 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1307 | insn->fixp[i] = NULL; | |
1308 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1309 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1310 | insn->mips16_absolute_jump_p = 0; | |
1311 | } | |
1312 | ||
742a56fe RS |
1313 | /* Record the current MIPS16 mode in now_seg. */ |
1314 | ||
1315 | static void | |
1316 | mips_record_mips16_mode (void) | |
1317 | { | |
1318 | segment_info_type *si; | |
1319 | ||
1320 | si = seg_info (now_seg); | |
1321 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1322 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1323 | } | |
1324 | ||
1e915849 RS |
1325 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1326 | ||
1327 | static void | |
1328 | install_insn (const struct mips_cl_insn *insn) | |
1329 | { | |
1330 | char *f = insn->frag->fr_literal + insn->where; | |
1331 | if (!mips_opts.mips16) | |
1332 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1333 | else if (insn->mips16_absolute_jump_p) | |
1334 | { | |
1335 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1336 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1337 | } | |
1338 | else | |
1339 | { | |
1340 | if (insn->use_extend) | |
1341 | { | |
1342 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1343 | f += 2; | |
1344 | } | |
1345 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1346 | } | |
742a56fe | 1347 | mips_record_mips16_mode (); |
1e915849 RS |
1348 | } |
1349 | ||
1350 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1351 | and install the opcode in the new location. */ | |
1352 | ||
1353 | static void | |
1354 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1355 | { | |
1356 | size_t i; | |
1357 | ||
1358 | insn->frag = frag; | |
1359 | insn->where = where; | |
1360 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1361 | if (insn->fixp[i] != NULL) | |
1362 | { | |
1363 | insn->fixp[i]->fx_frag = frag; | |
1364 | insn->fixp[i]->fx_where = where; | |
1365 | } | |
1366 | install_insn (insn); | |
1367 | } | |
1368 | ||
1369 | /* Add INSN to the end of the output. */ | |
1370 | ||
1371 | static void | |
1372 | add_fixed_insn (struct mips_cl_insn *insn) | |
1373 | { | |
1374 | char *f = frag_more (insn_length (insn)); | |
1375 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1376 | } | |
1377 | ||
1378 | /* Start a variant frag and move INSN to the start of the variant part, | |
1379 | marking it as fixed. The other arguments are as for frag_var. */ | |
1380 | ||
1381 | static void | |
1382 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1383 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1384 | { | |
1385 | frag_grow (max_chars); | |
1386 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1387 | insn->fixed_p = 1; | |
1388 | frag_var (rs_machine_dependent, max_chars, var, | |
1389 | subtype, symbol, offset, NULL); | |
1390 | } | |
1391 | ||
1392 | /* Insert N copies of INSN into the history buffer, starting at | |
1393 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1394 | ||
1395 | static void | |
1396 | insert_into_history (unsigned int first, unsigned int n, | |
1397 | const struct mips_cl_insn *insn) | |
1398 | { | |
1399 | if (mips_relax.sequence != 2) | |
1400 | { | |
1401 | unsigned int i; | |
1402 | ||
1403 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1404 | if (i >= first + n) | |
1405 | history[i] = history[i - n]; | |
1406 | else | |
1407 | history[i] = *insn; | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1412 | ||
1413 | static void | |
1414 | emit_nop (void) | |
1415 | { | |
1416 | add_fixed_insn (NOP_INSN); | |
1417 | insert_into_history (0, 1, NOP_INSN); | |
1418 | } | |
1419 | ||
71400594 RS |
1420 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1421 | the idea is to make it obvious at a glance that each errata is | |
1422 | included. */ | |
1423 | ||
1424 | static void | |
1425 | init_vr4120_conflicts (void) | |
1426 | { | |
1427 | #define CONFLICT(FIRST, SECOND) \ | |
1428 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1429 | ||
1430 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1431 | CONFLICT (MACC, DIV); | |
1432 | CONFLICT (DMACC, DIV); | |
1433 | ||
1434 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1435 | CONFLICT (DMULT, DMULT); | |
1436 | CONFLICT (DMULT, DMACC); | |
1437 | CONFLICT (DMACC, DMULT); | |
1438 | CONFLICT (DMACC, DMACC); | |
1439 | ||
1440 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1441 | CONFLICT (MACC, MTHILO); | |
1442 | CONFLICT (DMACC, MTHILO); | |
1443 | ||
1444 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1445 | instruction is executed immediately after a MACC or DMACC | |
1446 | instruction, the result of [either instruction] is incorrect." */ | |
1447 | CONFLICT (MACC, MULT); | |
1448 | CONFLICT (MACC, DMULT); | |
1449 | CONFLICT (DMACC, MULT); | |
1450 | CONFLICT (DMACC, DMULT); | |
1451 | ||
1452 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1453 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1454 | DDIV or DDIVU instruction, the result of the MACC or | |
1455 | DMACC instruction is incorrect.". */ | |
1456 | CONFLICT (DMULT, MACC); | |
1457 | CONFLICT (DMULT, DMACC); | |
1458 | CONFLICT (DIV, MACC); | |
1459 | CONFLICT (DIV, DMACC); | |
1460 | ||
1461 | #undef CONFLICT | |
1462 | } | |
1463 | ||
707bfff6 TS |
1464 | struct regname { |
1465 | const char *name; | |
1466 | unsigned int num; | |
1467 | }; | |
1468 | ||
1469 | #define RTYPE_MASK 0x1ff00 | |
1470 | #define RTYPE_NUM 0x00100 | |
1471 | #define RTYPE_FPU 0x00200 | |
1472 | #define RTYPE_FCC 0x00400 | |
1473 | #define RTYPE_VEC 0x00800 | |
1474 | #define RTYPE_GP 0x01000 | |
1475 | #define RTYPE_CP0 0x02000 | |
1476 | #define RTYPE_PC 0x04000 | |
1477 | #define RTYPE_ACC 0x08000 | |
1478 | #define RTYPE_CCC 0x10000 | |
1479 | #define RNUM_MASK 0x000ff | |
1480 | #define RWARN 0x80000 | |
1481 | ||
1482 | #define GENERIC_REGISTER_NUMBERS \ | |
1483 | {"$0", RTYPE_NUM | 0}, \ | |
1484 | {"$1", RTYPE_NUM | 1}, \ | |
1485 | {"$2", RTYPE_NUM | 2}, \ | |
1486 | {"$3", RTYPE_NUM | 3}, \ | |
1487 | {"$4", RTYPE_NUM | 4}, \ | |
1488 | {"$5", RTYPE_NUM | 5}, \ | |
1489 | {"$6", RTYPE_NUM | 6}, \ | |
1490 | {"$7", RTYPE_NUM | 7}, \ | |
1491 | {"$8", RTYPE_NUM | 8}, \ | |
1492 | {"$9", RTYPE_NUM | 9}, \ | |
1493 | {"$10", RTYPE_NUM | 10}, \ | |
1494 | {"$11", RTYPE_NUM | 11}, \ | |
1495 | {"$12", RTYPE_NUM | 12}, \ | |
1496 | {"$13", RTYPE_NUM | 13}, \ | |
1497 | {"$14", RTYPE_NUM | 14}, \ | |
1498 | {"$15", RTYPE_NUM | 15}, \ | |
1499 | {"$16", RTYPE_NUM | 16}, \ | |
1500 | {"$17", RTYPE_NUM | 17}, \ | |
1501 | {"$18", RTYPE_NUM | 18}, \ | |
1502 | {"$19", RTYPE_NUM | 19}, \ | |
1503 | {"$20", RTYPE_NUM | 20}, \ | |
1504 | {"$21", RTYPE_NUM | 21}, \ | |
1505 | {"$22", RTYPE_NUM | 22}, \ | |
1506 | {"$23", RTYPE_NUM | 23}, \ | |
1507 | {"$24", RTYPE_NUM | 24}, \ | |
1508 | {"$25", RTYPE_NUM | 25}, \ | |
1509 | {"$26", RTYPE_NUM | 26}, \ | |
1510 | {"$27", RTYPE_NUM | 27}, \ | |
1511 | {"$28", RTYPE_NUM | 28}, \ | |
1512 | {"$29", RTYPE_NUM | 29}, \ | |
1513 | {"$30", RTYPE_NUM | 30}, \ | |
1514 | {"$31", RTYPE_NUM | 31} | |
1515 | ||
1516 | #define FPU_REGISTER_NAMES \ | |
1517 | {"$f0", RTYPE_FPU | 0}, \ | |
1518 | {"$f1", RTYPE_FPU | 1}, \ | |
1519 | {"$f2", RTYPE_FPU | 2}, \ | |
1520 | {"$f3", RTYPE_FPU | 3}, \ | |
1521 | {"$f4", RTYPE_FPU | 4}, \ | |
1522 | {"$f5", RTYPE_FPU | 5}, \ | |
1523 | {"$f6", RTYPE_FPU | 6}, \ | |
1524 | {"$f7", RTYPE_FPU | 7}, \ | |
1525 | {"$f8", RTYPE_FPU | 8}, \ | |
1526 | {"$f9", RTYPE_FPU | 9}, \ | |
1527 | {"$f10", RTYPE_FPU | 10}, \ | |
1528 | {"$f11", RTYPE_FPU | 11}, \ | |
1529 | {"$f12", RTYPE_FPU | 12}, \ | |
1530 | {"$f13", RTYPE_FPU | 13}, \ | |
1531 | {"$f14", RTYPE_FPU | 14}, \ | |
1532 | {"$f15", RTYPE_FPU | 15}, \ | |
1533 | {"$f16", RTYPE_FPU | 16}, \ | |
1534 | {"$f17", RTYPE_FPU | 17}, \ | |
1535 | {"$f18", RTYPE_FPU | 18}, \ | |
1536 | {"$f19", RTYPE_FPU | 19}, \ | |
1537 | {"$f20", RTYPE_FPU | 20}, \ | |
1538 | {"$f21", RTYPE_FPU | 21}, \ | |
1539 | {"$f22", RTYPE_FPU | 22}, \ | |
1540 | {"$f23", RTYPE_FPU | 23}, \ | |
1541 | {"$f24", RTYPE_FPU | 24}, \ | |
1542 | {"$f25", RTYPE_FPU | 25}, \ | |
1543 | {"$f26", RTYPE_FPU | 26}, \ | |
1544 | {"$f27", RTYPE_FPU | 27}, \ | |
1545 | {"$f28", RTYPE_FPU | 28}, \ | |
1546 | {"$f29", RTYPE_FPU | 29}, \ | |
1547 | {"$f30", RTYPE_FPU | 30}, \ | |
1548 | {"$f31", RTYPE_FPU | 31} | |
1549 | ||
1550 | #define FPU_CONDITION_CODE_NAMES \ | |
1551 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1552 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1553 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1554 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1555 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1556 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1557 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1558 | {"$fcc7", RTYPE_FCC | 7} | |
1559 | ||
1560 | #define COPROC_CONDITION_CODE_NAMES \ | |
1561 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1562 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1563 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1564 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1565 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1566 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1567 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1568 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1569 | ||
1570 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1571 | {"$a4", RTYPE_GP | 8}, \ | |
1572 | {"$a5", RTYPE_GP | 9}, \ | |
1573 | {"$a6", RTYPE_GP | 10}, \ | |
1574 | {"$a7", RTYPE_GP | 11}, \ | |
1575 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1576 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1577 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1578 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1579 | {"$t0", RTYPE_GP | 12}, \ | |
1580 | {"$t1", RTYPE_GP | 13}, \ | |
1581 | {"$t2", RTYPE_GP | 14}, \ | |
1582 | {"$t3", RTYPE_GP | 15} | |
1583 | ||
1584 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1585 | {"$t0", RTYPE_GP | 8}, \ | |
1586 | {"$t1", RTYPE_GP | 9}, \ | |
1587 | {"$t2", RTYPE_GP | 10}, \ | |
1588 | {"$t3", RTYPE_GP | 11}, \ | |
1589 | {"$t4", RTYPE_GP | 12}, \ | |
1590 | {"$t5", RTYPE_GP | 13}, \ | |
1591 | {"$t6", RTYPE_GP | 14}, \ | |
1592 | {"$t7", RTYPE_GP | 15}, \ | |
1593 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1594 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1595 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1596 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1597 | ||
1598 | /* Remaining symbolic register names */ | |
1599 | #define SYMBOLIC_REGISTER_NAMES \ | |
1600 | {"$zero", RTYPE_GP | 0}, \ | |
1601 | {"$at", RTYPE_GP | 1}, \ | |
1602 | {"$AT", RTYPE_GP | 1}, \ | |
1603 | {"$v0", RTYPE_GP | 2}, \ | |
1604 | {"$v1", RTYPE_GP | 3}, \ | |
1605 | {"$a0", RTYPE_GP | 4}, \ | |
1606 | {"$a1", RTYPE_GP | 5}, \ | |
1607 | {"$a2", RTYPE_GP | 6}, \ | |
1608 | {"$a3", RTYPE_GP | 7}, \ | |
1609 | {"$s0", RTYPE_GP | 16}, \ | |
1610 | {"$s1", RTYPE_GP | 17}, \ | |
1611 | {"$s2", RTYPE_GP | 18}, \ | |
1612 | {"$s3", RTYPE_GP | 19}, \ | |
1613 | {"$s4", RTYPE_GP | 20}, \ | |
1614 | {"$s5", RTYPE_GP | 21}, \ | |
1615 | {"$s6", RTYPE_GP | 22}, \ | |
1616 | {"$s7", RTYPE_GP | 23}, \ | |
1617 | {"$t8", RTYPE_GP | 24}, \ | |
1618 | {"$t9", RTYPE_GP | 25}, \ | |
1619 | {"$k0", RTYPE_GP | 26}, \ | |
1620 | {"$kt0", RTYPE_GP | 26}, \ | |
1621 | {"$k1", RTYPE_GP | 27}, \ | |
1622 | {"$kt1", RTYPE_GP | 27}, \ | |
1623 | {"$gp", RTYPE_GP | 28}, \ | |
1624 | {"$sp", RTYPE_GP | 29}, \ | |
1625 | {"$s8", RTYPE_GP | 30}, \ | |
1626 | {"$fp", RTYPE_GP | 30}, \ | |
1627 | {"$ra", RTYPE_GP | 31} | |
1628 | ||
1629 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1630 | {"$pc", RTYPE_PC | 0} | |
1631 | ||
1632 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1633 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1634 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1635 | {"$v2", RTYPE_VEC | 2}, \ | |
1636 | {"$v3", RTYPE_VEC | 3}, \ | |
1637 | {"$v4", RTYPE_VEC | 4}, \ | |
1638 | {"$v5", RTYPE_VEC | 5}, \ | |
1639 | {"$v6", RTYPE_VEC | 6}, \ | |
1640 | {"$v7", RTYPE_VEC | 7}, \ | |
1641 | {"$v8", RTYPE_VEC | 8}, \ | |
1642 | {"$v9", RTYPE_VEC | 9}, \ | |
1643 | {"$v10", RTYPE_VEC | 10}, \ | |
1644 | {"$v11", RTYPE_VEC | 11}, \ | |
1645 | {"$v12", RTYPE_VEC | 12}, \ | |
1646 | {"$v13", RTYPE_VEC | 13}, \ | |
1647 | {"$v14", RTYPE_VEC | 14}, \ | |
1648 | {"$v15", RTYPE_VEC | 15}, \ | |
1649 | {"$v16", RTYPE_VEC | 16}, \ | |
1650 | {"$v17", RTYPE_VEC | 17}, \ | |
1651 | {"$v18", RTYPE_VEC | 18}, \ | |
1652 | {"$v19", RTYPE_VEC | 19}, \ | |
1653 | {"$v20", RTYPE_VEC | 20}, \ | |
1654 | {"$v21", RTYPE_VEC | 21}, \ | |
1655 | {"$v22", RTYPE_VEC | 22}, \ | |
1656 | {"$v23", RTYPE_VEC | 23}, \ | |
1657 | {"$v24", RTYPE_VEC | 24}, \ | |
1658 | {"$v25", RTYPE_VEC | 25}, \ | |
1659 | {"$v26", RTYPE_VEC | 26}, \ | |
1660 | {"$v27", RTYPE_VEC | 27}, \ | |
1661 | {"$v28", RTYPE_VEC | 28}, \ | |
1662 | {"$v29", RTYPE_VEC | 29}, \ | |
1663 | {"$v30", RTYPE_VEC | 30}, \ | |
1664 | {"$v31", RTYPE_VEC | 31} | |
1665 | ||
1666 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1667 | {"$ac0", RTYPE_ACC | 0}, \ | |
1668 | {"$ac1", RTYPE_ACC | 1}, \ | |
1669 | {"$ac2", RTYPE_ACC | 2}, \ | |
1670 | {"$ac3", RTYPE_ACC | 3} | |
1671 | ||
1672 | static const struct regname reg_names[] = { | |
1673 | GENERIC_REGISTER_NUMBERS, | |
1674 | FPU_REGISTER_NAMES, | |
1675 | FPU_CONDITION_CODE_NAMES, | |
1676 | COPROC_CONDITION_CODE_NAMES, | |
1677 | ||
1678 | /* The $txx registers depends on the abi, | |
1679 | these will be added later into the symbol table from | |
1680 | one of the tables below once mips_abi is set after | |
1681 | parsing of arguments from the command line. */ | |
1682 | SYMBOLIC_REGISTER_NAMES, | |
1683 | ||
1684 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1685 | MDMX_VECTOR_REGISTER_NAMES, | |
1686 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1687 | {0, 0} | |
1688 | }; | |
1689 | ||
1690 | static const struct regname reg_names_o32[] = { | |
1691 | O32_SYMBOLIC_REGISTER_NAMES, | |
1692 | {0, 0} | |
1693 | }; | |
1694 | ||
1695 | static const struct regname reg_names_n32n64[] = { | |
1696 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1697 | {0, 0} | |
1698 | }; | |
1699 | ||
1700 | static int | |
1701 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1702 | { | |
1703 | symbolS *symbolP; | |
1704 | char *e; | |
1705 | char save_c; | |
1706 | int reg = -1; | |
1707 | ||
1708 | /* Find end of name. */ | |
1709 | e = *s; | |
1710 | if (is_name_beginner (*e)) | |
1711 | ++e; | |
1712 | while (is_part_of_name (*e)) | |
1713 | ++e; | |
1714 | ||
1715 | /* Terminate name. */ | |
1716 | save_c = *e; | |
1717 | *e = '\0'; | |
1718 | ||
1719 | /* Look for a register symbol. */ | |
1720 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1721 | { | |
1722 | int r = S_GET_VALUE (symbolP); | |
1723 | if (r & types) | |
1724 | reg = r & RNUM_MASK; | |
1725 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1726 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1727 | reg = (r & RNUM_MASK) - 2; | |
1728 | } | |
1729 | /* Else see if this is a register defined in an itbl entry. */ | |
1730 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1731 | { | |
1732 | char *n = *s; | |
1733 | unsigned long r; | |
1734 | ||
1735 | if (*n == '$') | |
1736 | ++n; | |
1737 | if (itbl_get_reg_val (n, &r)) | |
1738 | reg = r & RNUM_MASK; | |
1739 | } | |
1740 | ||
1741 | /* Advance to next token if a register was recognised. */ | |
1742 | if (reg >= 0) | |
1743 | *s = e; | |
1744 | else if (types & RWARN) | |
1745 | as_warn ("Unrecognized register name `%s'", *s); | |
1746 | ||
1747 | *e = save_c; | |
1748 | if (regnop) | |
1749 | *regnop = reg; | |
1750 | return reg >= 0; | |
1751 | } | |
1752 | ||
1753 | /* This function is called once, at assembler startup time. It should set up | |
1754 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1755 | |
252b5132 | 1756 | void |
17a2f251 | 1757 | md_begin (void) |
252b5132 | 1758 | { |
3994f87e | 1759 | const char *retval = NULL; |
156c2f8b | 1760 | int i = 0; |
252b5132 | 1761 | int broken = 0; |
1f25f5d3 | 1762 | |
0a44bf69 RS |
1763 | if (mips_pic != NO_PIC) |
1764 | { | |
1765 | if (g_switch_seen && g_switch_value != 0) | |
1766 | as_bad (_("-G may not be used in position-independent code")); | |
1767 | g_switch_value = 0; | |
1768 | } | |
1769 | ||
fef14a42 | 1770 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1771 | as_warn (_("Could not set architecture and machine")); |
1772 | ||
252b5132 RH |
1773 | op_hash = hash_new (); |
1774 | ||
1775 | for (i = 0; i < NUMOPCODES;) | |
1776 | { | |
1777 | const char *name = mips_opcodes[i].name; | |
1778 | ||
17a2f251 | 1779 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1780 | if (retval != NULL) |
1781 | { | |
1782 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1783 | mips_opcodes[i].name, retval); | |
1784 | /* Probably a memory allocation problem? Give up now. */ | |
1785 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1786 | } | |
1787 | do | |
1788 | { | |
1789 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1790 | { | |
1791 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1792 | broken = 1; | |
1e915849 RS |
1793 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1794 | { | |
1795 | create_insn (&nop_insn, mips_opcodes + i); | |
1796 | nop_insn.fixed_p = 1; | |
1797 | } | |
252b5132 RH |
1798 | } |
1799 | ++i; | |
1800 | } | |
1801 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1802 | } | |
1803 | ||
1804 | mips16_op_hash = hash_new (); | |
1805 | ||
1806 | i = 0; | |
1807 | while (i < bfd_mips16_num_opcodes) | |
1808 | { | |
1809 | const char *name = mips16_opcodes[i].name; | |
1810 | ||
17a2f251 | 1811 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1812 | if (retval != NULL) |
1813 | as_fatal (_("internal: can't hash `%s': %s"), | |
1814 | mips16_opcodes[i].name, retval); | |
1815 | do | |
1816 | { | |
1817 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1818 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1819 | != mips16_opcodes[i].match)) | |
1820 | { | |
1821 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1822 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1823 | broken = 1; | |
1824 | } | |
1e915849 RS |
1825 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1826 | { | |
1827 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1828 | mips16_nop_insn.fixed_p = 1; | |
1829 | } | |
252b5132 RH |
1830 | ++i; |
1831 | } | |
1832 | while (i < bfd_mips16_num_opcodes | |
1833 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1834 | } | |
1835 | ||
1836 | if (broken) | |
1837 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1838 | ||
1839 | /* We add all the general register names to the symbol table. This | |
1840 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1841 | for (i = 0; reg_names[i].name; i++) |
1842 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1843 | reg_names[i].num, // & RNUM_MASK, | |
1844 | &zero_address_frag)); | |
1845 | if (HAVE_NEWABI) | |
1846 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1847 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1848 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1849 | &zero_address_frag)); |
707bfff6 TS |
1850 | else |
1851 | for (i = 0; reg_names_o32[i].name; i++) | |
1852 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1853 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1854 | &zero_address_frag)); |
6047c971 | 1855 | |
7d10b47d | 1856 | mips_no_prev_insn (); |
252b5132 RH |
1857 | |
1858 | mips_gprmask = 0; | |
1859 | mips_cprmask[0] = 0; | |
1860 | mips_cprmask[1] = 0; | |
1861 | mips_cprmask[2] = 0; | |
1862 | mips_cprmask[3] = 0; | |
1863 | ||
1864 | /* set the default alignment for the text section (2**2) */ | |
1865 | record_alignment (text_section, 2); | |
1866 | ||
4d0d148d | 1867 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1868 | |
707bfff6 | 1869 | #ifdef OBJ_ELF |
f43abd2b | 1870 | if (IS_ELF) |
252b5132 | 1871 | { |
0a44bf69 RS |
1872 | /* On a native system other than VxWorks, sections must be aligned |
1873 | to 16 byte boundaries. When configured for an embedded ELF | |
1874 | target, we don't bother. */ | |
1875 | if (strcmp (TARGET_OS, "elf") != 0 | |
1876 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1877 | { |
1878 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1879 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1880 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1881 | } | |
1882 | ||
1883 | /* Create a .reginfo section for register masks and a .mdebug | |
1884 | section for debugging information. */ | |
1885 | { | |
1886 | segT seg; | |
1887 | subsegT subseg; | |
1888 | flagword flags; | |
1889 | segT sec; | |
1890 | ||
1891 | seg = now_seg; | |
1892 | subseg = now_subseg; | |
1893 | ||
1894 | /* The ABI says this section should be loaded so that the | |
1895 | running program can access it. However, we don't load it | |
1896 | if we are configured for an embedded target */ | |
1897 | flags = SEC_READONLY | SEC_DATA; | |
1898 | if (strcmp (TARGET_OS, "elf") != 0) | |
1899 | flags |= SEC_ALLOC | SEC_LOAD; | |
1900 | ||
316f5878 | 1901 | if (mips_abi != N64_ABI) |
252b5132 RH |
1902 | { |
1903 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1904 | ||
195325d2 TS |
1905 | bfd_set_section_flags (stdoutput, sec, flags); |
1906 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1907 | |
252b5132 | 1908 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1909 | } |
1910 | else | |
1911 | { | |
1912 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1913 | .reginfo section. */ | |
1914 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1915 | bfd_set_section_flags (stdoutput, sec, flags); |
1916 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1917 | |
252b5132 RH |
1918 | /* Set up the option header. */ |
1919 | { | |
1920 | Elf_Internal_Options opthdr; | |
1921 | char *f; | |
1922 | ||
1923 | opthdr.kind = ODK_REGINFO; | |
1924 | opthdr.size = (sizeof (Elf_External_Options) | |
1925 | + sizeof (Elf64_External_RegInfo)); | |
1926 | opthdr.section = 0; | |
1927 | opthdr.info = 0; | |
1928 | f = frag_more (sizeof (Elf_External_Options)); | |
1929 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1930 | (Elf_External_Options *) f); | |
1931 | ||
1932 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1933 | } | |
252b5132 RH |
1934 | } |
1935 | ||
1936 | if (ECOFF_DEBUGGING) | |
1937 | { | |
1938 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1939 | (void) bfd_set_section_flags (stdoutput, sec, | |
1940 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1941 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1942 | } | |
f43abd2b | 1943 | else if (mips_flag_pdr) |
ecb4347a DJ |
1944 | { |
1945 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1946 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1947 | SEC_READONLY | SEC_RELOC | |
1948 | | SEC_DEBUGGING); | |
1949 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1950 | } | |
252b5132 RH |
1951 | |
1952 | subseg_set (seg, subseg); | |
1953 | } | |
1954 | } | |
707bfff6 | 1955 | #endif /* OBJ_ELF */ |
252b5132 RH |
1956 | |
1957 | if (! ECOFF_DEBUGGING) | |
1958 | md_obj_begin (); | |
71400594 RS |
1959 | |
1960 | if (mips_fix_vr4120) | |
1961 | init_vr4120_conflicts (); | |
252b5132 RH |
1962 | } |
1963 | ||
1964 | void | |
17a2f251 | 1965 | md_mips_end (void) |
252b5132 RH |
1966 | { |
1967 | if (! ECOFF_DEBUGGING) | |
1968 | md_obj_end (); | |
1969 | } | |
1970 | ||
1971 | void | |
17a2f251 | 1972 | md_assemble (char *str) |
252b5132 RH |
1973 | { |
1974 | struct mips_cl_insn insn; | |
f6688943 TS |
1975 | bfd_reloc_code_real_type unused_reloc[3] |
1976 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1977 | |
1978 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1979 | imm2_expr.X_op = O_absent; |
252b5132 | 1980 | offset_expr.X_op = O_absent; |
f6688943 TS |
1981 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1982 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1983 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1984 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1985 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1986 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1987 | |
1988 | if (mips_opts.mips16) | |
1989 | mips16_ip (str, &insn); | |
1990 | else | |
1991 | { | |
1992 | mips_ip (str, &insn); | |
beae10d5 KH |
1993 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1994 | str, insn.insn_opcode)); | |
252b5132 RH |
1995 | } |
1996 | ||
1997 | if (insn_error) | |
1998 | { | |
1999 | as_bad ("%s `%s'", insn_error, str); | |
2000 | return; | |
2001 | } | |
2002 | ||
2003 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2004 | { | |
584892a6 | 2005 | macro_start (); |
252b5132 RH |
2006 | if (mips_opts.mips16) |
2007 | mips16_macro (&insn); | |
2008 | else | |
2009 | macro (&insn); | |
584892a6 | 2010 | macro_end (); |
252b5132 RH |
2011 | } |
2012 | else | |
2013 | { | |
2014 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2015 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2016 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2017 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2018 | else |
4d7206a2 | 2019 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2020 | } |
2021 | } | |
2022 | ||
5919d012 | 2023 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2024 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2025 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2026 | |
2027 | static inline bfd_boolean | |
17a2f251 | 2028 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2029 | { |
3b91255e RS |
2030 | return (HAVE_IN_PLACE_ADDENDS |
2031 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2032 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2033 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2034 | all GOT16 relocations evaluate to "G". */ | |
2035 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2036 | } |
2037 | ||
2038 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2039 | relocation. */ | |
2040 | ||
2041 | static inline bfd_boolean | |
17a2f251 | 2042 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2043 | { |
2044 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2045 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2046 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2047 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2048 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2049 | } | |
2050 | ||
252b5132 RH |
2051 | /* See whether instruction IP reads register REG. CLASS is the type |
2052 | of register. */ | |
2053 | ||
2054 | static int | |
71400594 | 2055 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2056 | enum mips_regclass class) |
252b5132 RH |
2057 | { |
2058 | if (class == MIPS16_REG) | |
2059 | { | |
2060 | assert (mips_opts.mips16); | |
2061 | reg = mips16_to_32_reg_map[reg]; | |
2062 | class = MIPS_GR_REG; | |
2063 | } | |
2064 | ||
85b51719 TS |
2065 | /* Don't report on general register ZERO, since it never changes. */ |
2066 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2067 | return 0; |
2068 | ||
2069 | if (class == MIPS_FP_REG) | |
2070 | { | |
2071 | assert (! mips_opts.mips16); | |
2072 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2073 | This is not optimal, because it will introduce an unnecessary | |
2074 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2075 | need to distinguish reading both $f0 and $f1 or just one of | |
2076 | them. Note that we don't have to check the other way, | |
2077 | because there is no instruction that sets both $f0 and $f1 | |
2078 | and requires a delay. */ | |
2079 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2080 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2081 | == (reg &~ (unsigned) 1))) |
2082 | return 1; | |
2083 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2084 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2085 | == (reg &~ (unsigned) 1))) |
2086 | return 1; | |
2087 | } | |
2088 | else if (! mips_opts.mips16) | |
2089 | { | |
2090 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2091 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2092 | return 1; |
2093 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2094 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2095 | return 1; |
2096 | } | |
2097 | else | |
2098 | { | |
2099 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2100 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2101 | return 1; |
2102 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2103 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2104 | return 1; |
2105 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2106 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2107 | == reg)) |
2108 | return 1; | |
2109 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2110 | return 1; | |
2111 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2112 | return 1; | |
2113 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2114 | return 1; | |
2115 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2116 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2117 | return 1; |
2118 | } | |
2119 | ||
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | /* This function returns true if modifying a register requires a | |
2124 | delay. */ | |
2125 | ||
2126 | static int | |
17a2f251 | 2127 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2128 | { |
2129 | unsigned long prev_pinfo; | |
2130 | ||
47e39b9d | 2131 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2132 | if (! mips_opts.noreorder |
81912461 ILT |
2133 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2134 | && ! gpr_interlocks) | |
2135 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2136 | && ! cop_interlocks))) | |
252b5132 | 2137 | { |
81912461 ILT |
2138 | /* A load from a coprocessor or from memory. All load delays |
2139 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2140 | /* Itbl support may require additional care here. */ |
252b5132 | 2141 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2142 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2143 | return 1; |
2144 | } | |
2145 | ||
2146 | return 0; | |
2147 | } | |
2148 | ||
404a8071 RS |
2149 | /* Move all labels in insn_labels to the current insertion point. */ |
2150 | ||
2151 | static void | |
2152 | mips_move_labels (void) | |
2153 | { | |
a8dbcb85 | 2154 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2155 | struct insn_label_list *l; |
2156 | valueT val; | |
2157 | ||
a8dbcb85 | 2158 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2159 | { |
2160 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2161 | symbol_set_frag (l->label, frag_now); | |
2162 | val = (valueT) frag_now_fix (); | |
2163 | /* mips16 text labels are stored as odd. */ | |
2164 | if (mips_opts.mips16) | |
2165 | ++val; | |
2166 | S_SET_VALUE (l->label, val); | |
2167 | } | |
2168 | } | |
2169 | ||
5f0fe04b TS |
2170 | static bfd_boolean |
2171 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2172 | { | |
2173 | bfd_boolean linkonce = FALSE; | |
2174 | segT symseg = S_GET_SEGMENT (sym); | |
2175 | ||
2176 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2177 | { | |
2178 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2179 | linkonce = TRUE; | |
2180 | #ifdef OBJ_ELF | |
2181 | /* The GNU toolchain uses an extension for ELF: a section | |
2182 | beginning with the magic string .gnu.linkonce is a | |
2183 | linkonce section. */ | |
2184 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2185 | sizeof ".gnu.linkonce" - 1) == 0) | |
2186 | linkonce = TRUE; | |
2187 | #endif | |
2188 | } | |
2189 | return linkonce; | |
2190 | } | |
2191 | ||
252b5132 RH |
2192 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2193 | handle them specially, such as generating jalx instructions when | |
2194 | needed. We also make them odd for the duration of the assembly, in | |
2195 | order to generate the right sort of code. We will make them even | |
2196 | in the adjust_symtab routine, while leaving them marked. This is | |
2197 | convenient for the debugger and the disassembler. The linker knows | |
2198 | to make them odd again. */ | |
2199 | ||
2200 | static void | |
17a2f251 | 2201 | mips16_mark_labels (void) |
252b5132 | 2202 | { |
a8dbcb85 TS |
2203 | segment_info_type *si = seg_info (now_seg); |
2204 | struct insn_label_list *l; | |
252b5132 | 2205 | |
a8dbcb85 TS |
2206 | if (!mips_opts.mips16) |
2207 | return; | |
2208 | ||
2209 | for (l = si->label_list; l != NULL; l = l->next) | |
2210 | { | |
2211 | symbolS *label = l->label; | |
2212 | ||
2213 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2214 | if (IS_ELF) |
a8dbcb85 | 2215 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2216 | #endif |
5f0fe04b TS |
2217 | if ((S_GET_VALUE (label) & 1) == 0 |
2218 | /* Don't adjust the address if the label is global or weak, or | |
2219 | in a link-once section, since we'll be emitting symbol reloc | |
2220 | references to it which will be patched up by the linker, and | |
2221 | the final value of the symbol may or may not be MIPS16. */ | |
2222 | && ! S_IS_WEAK (label) | |
2223 | && ! S_IS_EXTERNAL (label) | |
2224 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2225 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2226 | } |
2227 | } | |
2228 | ||
4d7206a2 RS |
2229 | /* End the current frag. Make it a variant frag and record the |
2230 | relaxation info. */ | |
2231 | ||
2232 | static void | |
2233 | relax_close_frag (void) | |
2234 | { | |
584892a6 | 2235 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2236 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2237 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2238 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2239 | ||
2240 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2241 | mips_relax.first_fixup = 0; | |
2242 | } | |
2243 | ||
2244 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2245 | See the comment above RELAX_ENCODE for more details. */ | |
2246 | ||
2247 | static void | |
2248 | relax_start (symbolS *symbol) | |
2249 | { | |
2250 | assert (mips_relax.sequence == 0); | |
2251 | mips_relax.sequence = 1; | |
2252 | mips_relax.symbol = symbol; | |
2253 | } | |
2254 | ||
2255 | /* Start generating the second version of a relaxable sequence. | |
2256 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2257 | |
2258 | static void | |
4d7206a2 RS |
2259 | relax_switch (void) |
2260 | { | |
2261 | assert (mips_relax.sequence == 1); | |
2262 | mips_relax.sequence = 2; | |
2263 | } | |
2264 | ||
2265 | /* End the current relaxable sequence. */ | |
2266 | ||
2267 | static void | |
2268 | relax_end (void) | |
2269 | { | |
2270 | assert (mips_relax.sequence == 2); | |
2271 | relax_close_frag (); | |
2272 | mips_relax.sequence = 0; | |
2273 | } | |
2274 | ||
71400594 RS |
2275 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2276 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2277 | by VR4120 errata. */ | |
4d7206a2 | 2278 | |
71400594 RS |
2279 | static unsigned int |
2280 | classify_vr4120_insn (const char *name) | |
252b5132 | 2281 | { |
71400594 RS |
2282 | if (strncmp (name, "macc", 4) == 0) |
2283 | return FIX_VR4120_MACC; | |
2284 | if (strncmp (name, "dmacc", 5) == 0) | |
2285 | return FIX_VR4120_DMACC; | |
2286 | if (strncmp (name, "mult", 4) == 0) | |
2287 | return FIX_VR4120_MULT; | |
2288 | if (strncmp (name, "dmult", 5) == 0) | |
2289 | return FIX_VR4120_DMULT; | |
2290 | if (strstr (name, "div")) | |
2291 | return FIX_VR4120_DIV; | |
2292 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2293 | return FIX_VR4120_MTHILO; | |
2294 | return NUM_FIX_VR4120_CLASSES; | |
2295 | } | |
252b5132 | 2296 | |
71400594 RS |
2297 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2298 | where INSN1 is the earlier instruction. Return the worst-case value | |
2299 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2300 | |
71400594 RS |
2301 | static unsigned int |
2302 | insns_between (const struct mips_cl_insn *insn1, | |
2303 | const struct mips_cl_insn *insn2) | |
2304 | { | |
2305 | unsigned long pinfo1, pinfo2; | |
2306 | ||
2307 | /* This function needs to know which pinfo flags are set for INSN2 | |
2308 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2309 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2310 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2311 | pinfo1 = insn1->insn_mo->pinfo; | |
2312 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2313 | |
71400594 RS |
2314 | #define INSN2_USES_REG(REG, CLASS) \ |
2315 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2316 | ||
2317 | /* For most targets, write-after-read dependencies on the HI and LO | |
2318 | registers must be separated by at least two instructions. */ | |
2319 | if (!hilo_interlocks) | |
252b5132 | 2320 | { |
71400594 RS |
2321 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2322 | return 2; | |
2323 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2324 | return 2; | |
2325 | } | |
2326 | ||
2327 | /* If we're working around r7000 errata, there must be two instructions | |
2328 | between an mfhi or mflo and any instruction that uses the result. */ | |
2329 | if (mips_7000_hilo_fix | |
2330 | && MF_HILO_INSN (pinfo1) | |
2331 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2332 | return 2; | |
2333 | ||
2334 | /* If working around VR4120 errata, check for combinations that need | |
2335 | a single intervening instruction. */ | |
2336 | if (mips_fix_vr4120) | |
2337 | { | |
2338 | unsigned int class1, class2; | |
252b5132 | 2339 | |
71400594 RS |
2340 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2341 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2342 | { |
71400594 RS |
2343 | if (insn2 == NULL) |
2344 | return 1; | |
2345 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2346 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2347 | return 1; | |
252b5132 | 2348 | } |
71400594 RS |
2349 | } |
2350 | ||
2351 | if (!mips_opts.mips16) | |
2352 | { | |
2353 | /* Check for GPR or coprocessor load delays. All such delays | |
2354 | are on the RT register. */ | |
2355 | /* Itbl support may require additional care here. */ | |
2356 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2357 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2358 | { |
71400594 RS |
2359 | know (pinfo1 & INSN_WRITE_GPR_T); |
2360 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2361 | return 1; | |
2362 | } | |
2363 | ||
2364 | /* Check for generic coprocessor hazards. | |
2365 | ||
2366 | This case is not handled very well. There is no special | |
2367 | knowledge of CP0 handling, and the coprocessors other than | |
2368 | the floating point unit are not distinguished at all. */ | |
2369 | /* Itbl support may require additional care here. FIXME! | |
2370 | Need to modify this to include knowledge about | |
2371 | user specified delays! */ | |
2372 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2373 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2374 | { | |
2375 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2376 | register. There must be a one instruction delay before INSN2 | |
2377 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2378 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2379 | { |
71400594 RS |
2380 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2381 | return 1; | |
252b5132 | 2382 | } |
71400594 | 2383 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2384 | { |
71400594 RS |
2385 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2386 | return 1; | |
252b5132 RH |
2387 | } |
2388 | else | |
2389 | { | |
71400594 RS |
2390 | /* Read-after-write dependencies on the control registers |
2391 | require a two-instruction gap. */ | |
2392 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2393 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2394 | return 2; | |
2395 | ||
2396 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2397 | also a coprocessor instruction, assume there must be | |
2398 | a one instruction gap. */ | |
2399 | if (pinfo2 & INSN_COP) | |
2400 | return 1; | |
252b5132 RH |
2401 | } |
2402 | } | |
6b76fefe | 2403 | |
71400594 RS |
2404 | /* Check for read-after-write dependencies on the coprocessor |
2405 | control registers in cases where INSN1 does not need a general | |
2406 | coprocessor delay. This means that INSN1 is a floating point | |
2407 | comparison instruction. */ | |
2408 | /* Itbl support may require additional care here. */ | |
2409 | else if (!cop_interlocks | |
2410 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2411 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2412 | return 1; | |
2413 | } | |
6b76fefe | 2414 | |
71400594 | 2415 | #undef INSN2_USES_REG |
6b76fefe | 2416 | |
71400594 RS |
2417 | return 0; |
2418 | } | |
6b76fefe | 2419 | |
7d8e00cf RS |
2420 | /* Return the number of nops that would be needed to work around the |
2421 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2422 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2423 | ||
2424 | static int | |
2425 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2426 | const struct mips_cl_insn *insn) | |
2427 | { | |
2428 | int i, j, reg; | |
2429 | ||
2430 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2431 | are not affected by the errata. */ | |
2432 | if (insn != 0 | |
2433 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2434 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2435 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2436 | return 0; | |
2437 | ||
2438 | /* Search for the first MFLO or MFHI. */ | |
2439 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2440 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2441 | { | |
2442 | /* Extract the destination register. */ | |
2443 | if (mips_opts.mips16) | |
2444 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2445 | else | |
2446 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2447 | ||
2448 | /* No nops are needed if INSN reads that register. */ | |
2449 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2450 | return 0; | |
2451 | ||
2452 | /* ...or if any of the intervening instructions do. */ | |
2453 | for (j = 0; j < i; j++) | |
2454 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2455 | return 0; | |
2456 | ||
2457 | return MAX_VR4130_NOPS - i; | |
2458 | } | |
2459 | return 0; | |
2460 | } | |
2461 | ||
71400594 RS |
2462 | /* Return the number of nops that would be needed if instruction INSN |
2463 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2464 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2465 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2466 | |
71400594 RS |
2467 | static int |
2468 | nops_for_insn (const struct mips_cl_insn *history, | |
2469 | const struct mips_cl_insn *insn) | |
2470 | { | |
2471 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2472 | |
71400594 | 2473 | nops = 0; |
7d8e00cf | 2474 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2475 | if (!history[i].noreorder_p) |
2476 | { | |
2477 | tmp_nops = insns_between (history + i, insn) - i; | |
2478 | if (tmp_nops > nops) | |
2479 | nops = tmp_nops; | |
2480 | } | |
7d8e00cf RS |
2481 | |
2482 | if (mips_fix_vr4130) | |
2483 | { | |
2484 | tmp_nops = nops_for_vr4130 (history, insn); | |
2485 | if (tmp_nops > nops) | |
2486 | nops = tmp_nops; | |
2487 | } | |
2488 | ||
71400594 RS |
2489 | return nops; |
2490 | } | |
252b5132 | 2491 | |
71400594 RS |
2492 | /* The variable arguments provide NUM_INSNS extra instructions that |
2493 | might be added to HISTORY. Return the largest number of nops that | |
2494 | would be needed after the extended sequence. */ | |
252b5132 | 2495 | |
71400594 RS |
2496 | static int |
2497 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2498 | { | |
2499 | va_list args; | |
2500 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2501 | struct mips_cl_insn *cursor; | |
2502 | int nops; | |
2503 | ||
2504 | va_start (args, history); | |
2505 | cursor = buffer + num_insns; | |
2506 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2507 | while (cursor > buffer) | |
2508 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2509 | ||
2510 | nops = nops_for_insn (buffer, NULL); | |
2511 | va_end (args); | |
2512 | return nops; | |
2513 | } | |
252b5132 | 2514 | |
71400594 RS |
2515 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2516 | worst-case delay for the branch target. */ | |
252b5132 | 2517 | |
71400594 RS |
2518 | static int |
2519 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2520 | const struct mips_cl_insn *insn) | |
2521 | { | |
2522 | int nops, tmp_nops; | |
60b63b72 | 2523 | |
71400594 RS |
2524 | nops = nops_for_insn (history, insn); |
2525 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2526 | | INSN_COND_BRANCH_DELAY | |
2527 | | INSN_COND_BRANCH_LIKELY)) | |
2528 | { | |
2529 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2530 | if (tmp_nops > nops) | |
2531 | nops = tmp_nops; | |
2532 | } | |
2533 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2534 | { | |
2535 | tmp_nops = nops_for_sequence (1, history, insn); | |
2536 | if (tmp_nops > nops) | |
2537 | nops = tmp_nops; | |
2538 | } | |
2539 | return nops; | |
2540 | } | |
2541 | ||
2542 | /* Output an instruction. IP is the instruction information. | |
2543 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2544 | RELOC_TYPE. */ | |
2545 | ||
2546 | static void | |
2547 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2548 | bfd_reloc_code_real_type *reloc_type) | |
2549 | { | |
3994f87e | 2550 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2551 | relax_stateT prev_insn_frag_type = 0; |
2552 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2553 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2554 | |
2555 | /* Mark instruction labels in mips16 mode. */ | |
2556 | mips16_mark_labels (); | |
2557 | ||
2558 | prev_pinfo = history[0].insn_mo->pinfo; | |
2559 | pinfo = ip->insn_mo->pinfo; | |
2560 | ||
2561 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2562 | { | |
2563 | /* There are a lot of optimizations we could do that we don't. | |
2564 | In particular, we do not, in general, reorder instructions. | |
2565 | If you use gcc with optimization, it will reorder | |
2566 | instructions and generally do much more optimization then we | |
2567 | do here; repeating all that work in the assembler would only | |
2568 | benefit hand written assembly code, and does not seem worth | |
2569 | it. */ | |
2570 | int nops = (mips_optimize == 0 | |
2571 | ? nops_for_insn (history, NULL) | |
2572 | : nops_for_insn_or_target (history, ip)); | |
2573 | if (nops > 0) | |
252b5132 RH |
2574 | { |
2575 | fragS *old_frag; | |
2576 | unsigned long old_frag_offset; | |
2577 | int i; | |
252b5132 RH |
2578 | |
2579 | old_frag = frag_now; | |
2580 | old_frag_offset = frag_now_fix (); | |
2581 | ||
2582 | for (i = 0; i < nops; i++) | |
2583 | emit_nop (); | |
2584 | ||
2585 | if (listing) | |
2586 | { | |
2587 | listing_prev_line (); | |
2588 | /* We may be at the start of a variant frag. In case we | |
2589 | are, make sure there is enough space for the frag | |
2590 | after the frags created by listing_prev_line. The | |
2591 | argument to frag_grow here must be at least as large | |
2592 | as the argument to all other calls to frag_grow in | |
2593 | this file. We don't have to worry about being in the | |
2594 | middle of a variant frag, because the variants insert | |
2595 | all needed nop instructions themselves. */ | |
2596 | frag_grow (40); | |
2597 | } | |
2598 | ||
404a8071 | 2599 | mips_move_labels (); |
252b5132 RH |
2600 | |
2601 | #ifndef NO_ECOFF_DEBUGGING | |
2602 | if (ECOFF_DEBUGGING) | |
2603 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2604 | #endif | |
2605 | } | |
71400594 RS |
2606 | } |
2607 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2608 | { | |
2609 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2610 | int nops = nops_for_insn_or_target (history, ip); | |
2611 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2612 | |
71400594 RS |
2613 | /* Enforce NOPS as a minimum. */ |
2614 | if (nops > prev_nop_frag_required) | |
2615 | prev_nop_frag_required = nops; | |
252b5132 | 2616 | |
71400594 RS |
2617 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2618 | { | |
2619 | /* Settle for the current number of nops. Update the history | |
2620 | accordingly (for the benefit of any future .set reorder code). */ | |
2621 | prev_nop_frag = NULL; | |
2622 | insert_into_history (prev_nop_frag_since, | |
2623 | prev_nop_frag_holds, NOP_INSN); | |
2624 | } | |
2625 | else | |
2626 | { | |
2627 | /* Allow this instruction to replace one of the nops that was | |
2628 | tentatively added to prev_nop_frag. */ | |
2629 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2630 | prev_nop_frag_holds--; | |
2631 | prev_nop_frag_since++; | |
252b5132 RH |
2632 | } |
2633 | } | |
2634 | ||
58e2ea4d MR |
2635 | #ifdef OBJ_ELF |
2636 | /* The value passed to dwarf2_emit_insn is the distance between | |
2637 | the beginning of the current instruction and the address that | |
2638 | should be recorded in the debug tables. For MIPS16 debug info | |
2639 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2640 | address higher by one than the current. */ | |
2641 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2642 | #endif | |
2643 | ||
895921c9 | 2644 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2645 | if (history[0].frag) |
2646 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2647 | |
4d7206a2 | 2648 | if (address_expr |
0b25d3e6 | 2649 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2650 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2651 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2652 | && mips_relax_branch | |
2653 | /* Don't try branch relaxation within .set nomacro, or within | |
2654 | .set noat if we use $at for PIC computations. If it turns | |
2655 | out that the branch was out-of-range, we'll get an error. */ | |
2656 | && !mips_opts.warn_about_macros | |
741fe287 | 2657 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2658 | && !mips_opts.mips16) |
2659 | { | |
895921c9 | 2660 | relaxed_branch = TRUE; |
1e915849 RS |
2661 | add_relaxed_insn (ip, (relaxed_branch_length |
2662 | (NULL, NULL, | |
2663 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2664 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2665 | : 0)), 4, | |
2666 | RELAX_BRANCH_ENCODE | |
2667 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2668 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2669 | pinfo & INSN_WRITE_GPR_31, | |
2670 | 0), | |
2671 | address_expr->X_add_symbol, | |
2672 | address_expr->X_add_number); | |
4a6a3df4 AO |
2673 | *reloc_type = BFD_RELOC_UNUSED; |
2674 | } | |
2675 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2676 | { |
2677 | /* We need to set up a variant frag. */ | |
2678 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2679 | add_relaxed_insn (ip, 4, 0, |
2680 | RELAX_MIPS16_ENCODE | |
2681 | (*reloc_type - BFD_RELOC_UNUSED, | |
2682 | mips16_small, mips16_ext, | |
2683 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2684 | history[0].mips16_absolute_jump_p), | |
2685 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2686 | } |
252b5132 RH |
2687 | else if (mips_opts.mips16 |
2688 | && ! ip->use_extend | |
f6688943 | 2689 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2690 | { |
b8ee1a6e DU |
2691 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2692 | /* Make sure there is enough room to swap this instruction with | |
2693 | a following jump instruction. */ | |
2694 | frag_grow (6); | |
1e915849 | 2695 | add_fixed_insn (ip); |
252b5132 RH |
2696 | } |
2697 | else | |
2698 | { | |
2699 | if (mips_opts.mips16 | |
2700 | && mips_opts.noreorder | |
2701 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2702 | as_warn (_("extended instruction in delay slot")); | |
2703 | ||
4d7206a2 RS |
2704 | if (mips_relax.sequence) |
2705 | { | |
2706 | /* If we've reached the end of this frag, turn it into a variant | |
2707 | frag and record the information for the instructions we've | |
2708 | written so far. */ | |
2709 | if (frag_room () < 4) | |
2710 | relax_close_frag (); | |
2711 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2712 | } | |
2713 | ||
584892a6 RS |
2714 | if (mips_relax.sequence != 2) |
2715 | mips_macro_warning.sizes[0] += 4; | |
2716 | if (mips_relax.sequence != 1) | |
2717 | mips_macro_warning.sizes[1] += 4; | |
2718 | ||
1e915849 RS |
2719 | if (mips_opts.mips16) |
2720 | { | |
2721 | ip->fixed_p = 1; | |
2722 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2723 | } | |
2724 | add_fixed_insn (ip); | |
252b5132 RH |
2725 | } |
2726 | ||
01a3f561 | 2727 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2728 | { |
2729 | if (address_expr->X_op == O_constant) | |
2730 | { | |
f17c130b | 2731 | unsigned int tmp; |
f6688943 TS |
2732 | |
2733 | switch (*reloc_type) | |
252b5132 RH |
2734 | { |
2735 | case BFD_RELOC_32: | |
2736 | ip->insn_opcode |= address_expr->X_add_number; | |
2737 | break; | |
2738 | ||
f6688943 | 2739 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2740 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2741 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2742 | break; |
2743 | ||
2744 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2745 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2746 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2747 | break; |
2748 | ||
2749 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2750 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2751 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2752 | break; |
2753 | ||
2754 | case BFD_RELOC_HI16: | |
2755 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2756 | break; | |
2757 | ||
01a3f561 | 2758 | case BFD_RELOC_UNUSED: |
252b5132 | 2759 | case BFD_RELOC_LO16: |
ed6fb7bd | 2760 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2761 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2762 | break; | |
2763 | ||
2764 | case BFD_RELOC_MIPS_JMP: | |
2765 | if ((address_expr->X_add_number & 3) != 0) | |
2766 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2767 | (unsigned long) address_expr->X_add_number); | |
2768 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2769 | break; | |
2770 | ||
2771 | case BFD_RELOC_MIPS16_JMP: | |
2772 | if ((address_expr->X_add_number & 3) != 0) | |
2773 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2774 | (unsigned long) address_expr->X_add_number); | |
2775 | ip->insn_opcode |= | |
2776 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2777 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2778 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2779 | break; | |
2780 | ||
252b5132 | 2781 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2782 | if ((address_expr->X_add_number & 3) != 0) |
2783 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2784 | (unsigned long) address_expr->X_add_number); | |
2785 | if (mips_relax_branch) | |
2786 | goto need_reloc; | |
2787 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2788 | as_bad (_("branch address range overflow (0x%lx)"), | |
2789 | (unsigned long) address_expr->X_add_number); | |
2790 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2791 | break; | |
252b5132 RH |
2792 | |
2793 | default: | |
2794 | internalError (); | |
2795 | } | |
2796 | } | |
01a3f561 | 2797 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2798 | need_reloc: |
4d7206a2 RS |
2799 | { |
2800 | reloc_howto_type *howto; | |
2801 | int i; | |
34ce925e | 2802 | |
4d7206a2 RS |
2803 | /* In a compound relocation, it is the final (outermost) |
2804 | operator that determines the relocated field. */ | |
2805 | for (i = 1; i < 3; i++) | |
2806 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2807 | break; | |
34ce925e | 2808 | |
4d7206a2 | 2809 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2810 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2811 | bfd_get_reloc_size (howto), | |
2812 | address_expr, | |
2813 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2814 | reloc_type[0]); | |
4d7206a2 | 2815 | |
b314ec0e RS |
2816 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
2817 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
2818 | && ip->fixp[0]->fx_addsy) | |
2819 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
2820 | ||
4d7206a2 RS |
2821 | /* These relocations can have an addend that won't fit in |
2822 | 4 octets for 64bit assembly. */ | |
2823 | if (HAVE_64BIT_GPRS | |
2824 | && ! howto->partial_inplace | |
2825 | && (reloc_type[0] == BFD_RELOC_16 | |
2826 | || reloc_type[0] == BFD_RELOC_32 | |
2827 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2828 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2829 | || reloc_type[0] == BFD_RELOC_LO16 | |
2830 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2831 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2832 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2833 | || reloc_type[0] == BFD_RELOC_64 | |
2834 | || reloc_type[0] == BFD_RELOC_CTOR | |
2835 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2836 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2837 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2838 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2839 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2840 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2841 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2842 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2843 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2844 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2845 | |
2846 | if (mips_relax.sequence) | |
2847 | { | |
2848 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2849 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2850 | } |
2851 | else if (reloc_needs_lo_p (*reloc_type)) | |
2852 | { | |
2853 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2854 | |
4d7206a2 RS |
2855 | /* Reuse the last entry if it already has a matching %lo. */ |
2856 | hi_fixup = mips_hi_fixup_list; | |
2857 | if (hi_fixup == 0 | |
2858 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2859 | { | |
2860 | hi_fixup = ((struct mips_hi_fixup *) | |
2861 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2862 | hi_fixup->next = mips_hi_fixup_list; | |
2863 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2864 | } |
1e915849 | 2865 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2866 | hi_fixup->seg = now_seg; |
2867 | } | |
f6688943 | 2868 | |
4d7206a2 RS |
2869 | /* Add fixups for the second and third relocations, if given. |
2870 | Note that the ABI allows the second relocation to be | |
2871 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2872 | moment we only use RSS_UNDEF, but we could add support | |
2873 | for the others if it ever becomes necessary. */ | |
2874 | for (i = 1; i < 3; i++) | |
2875 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2876 | { | |
1e915849 RS |
2877 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2878 | ip->fixp[0]->fx_size, NULL, 0, | |
2879 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2880 | |
2881 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2882 | ip->fixp[0]->fx_tcbit = 1; |
2883 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2884 | } |
252b5132 RH |
2885 | } |
2886 | } | |
1e915849 | 2887 | install_insn (ip); |
252b5132 RH |
2888 | |
2889 | /* Update the register mask information. */ | |
2890 | if (! mips_opts.mips16) | |
2891 | { | |
2892 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2893 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2894 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2895 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2896 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2897 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2898 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2899 | mips_gprmask |= 1 << RA; |
252b5132 | 2900 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2901 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2902 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2903 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2904 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2905 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2906 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2907 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2908 | if (pinfo & INSN_COP) |
2909 | { | |
bdaaa2e1 KH |
2910 | /* We don't keep enough information to sort these cases out. |
2911 | The itbl support does keep this information however, although | |
2912 | we currently don't support itbl fprmats as part of the cop | |
2913 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2914 | } |
2915 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2916 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2917 | } |
2918 | else | |
2919 | { | |
2920 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2921 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2922 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2923 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2924 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2925 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2926 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2927 | mips_gprmask |= 1 << TREG; | |
2928 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2929 | mips_gprmask |= 1 << SP; | |
2930 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2931 | mips_gprmask |= 1 << RA; | |
2932 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2933 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2934 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2935 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2936 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2937 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2938 | } |
2939 | ||
4d7206a2 | 2940 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2941 | { |
2942 | /* Filling the branch delay slot is more complex. We try to | |
2943 | switch the branch with the previous instruction, which we can | |
2944 | do if the previous instruction does not set up a condition | |
2945 | that the branch tests and if the branch is not itself the | |
2946 | target of any branch. */ | |
2947 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2948 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2949 | { | |
2950 | if (mips_optimize < 2 | |
2951 | /* If we have seen .set volatile or .set nomove, don't | |
2952 | optimize. */ | |
2953 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2954 | /* We can't swap if the previous instruction's position |
2955 | is fixed. */ | |
2956 | || history[0].fixed_p | |
252b5132 RH |
2957 | /* If the previous previous insn was in a .set |
2958 | noreorder, we can't swap. Actually, the MIPS | |
2959 | assembler will swap in this situation. However, gcc | |
2960 | configured -with-gnu-as will generate code like | |
2961 | .set noreorder | |
2962 | lw $4,XXX | |
2963 | .set reorder | |
2964 | INSN | |
2965 | bne $4,$0,foo | |
2966 | in which we can not swap the bne and INSN. If gcc is | |
2967 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2968 | .set pseudo-ops. */ |
47e39b9d | 2969 | || history[1].noreorder_p |
252b5132 RH |
2970 | /* If the branch is itself the target of a branch, we |
2971 | can not swap. We cheat on this; all we check for is | |
2972 | whether there is a label on this instruction. If | |
2973 | there are any branches to anything other than a | |
2974 | label, users must use .set noreorder. */ | |
a8dbcb85 | 2975 | || si->label_list != NULL |
895921c9 MR |
2976 | /* If the previous instruction is in a variant frag |
2977 | other than this branch's one, we cannot do the swap. | |
2978 | This does not apply to the mips16, which uses variant | |
2979 | frags for different purposes. */ | |
252b5132 | 2980 | || (! mips_opts.mips16 |
895921c9 | 2981 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2982 | /* Check for conflicts between the branch and the instructions |
2983 | before the candidate delay slot. */ | |
2984 | || nops_for_insn (history + 1, ip) > 0 | |
2985 | /* Check for conflicts between the swapped sequence and the | |
2986 | target of the branch. */ | |
2987 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2988 | /* We do not swap with a trap instruction, since it |
2989 | complicates trap handlers to have the trap | |
2990 | instruction be in a delay slot. */ | |
2991 | || (prev_pinfo & INSN_TRAP) | |
2992 | /* If the branch reads a register that the previous | |
2993 | instruction sets, we can not swap. */ | |
2994 | || (! mips_opts.mips16 | |
2995 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2996 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2997 | MIPS_GR_REG)) |
2998 | || (! mips_opts.mips16 | |
2999 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3000 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3001 | MIPS_GR_REG)) |
3002 | || (mips_opts.mips16 | |
3003 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3004 | && (insn_uses_reg |
3005 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3006 | MIPS16_REG))) | |
252b5132 | 3007 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3008 | && (insn_uses_reg |
3009 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3010 | MIPS16_REG))) | |
252b5132 | 3011 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3012 | && (insn_uses_reg |
3013 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3014 | MIPS16_REG))) | |
252b5132 RH |
3015 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3016 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3017 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3018 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3019 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3020 | && insn_uses_reg (ip, | |
47e39b9d RS |
3021 | MIPS16OP_EXTRACT_REG32R |
3022 | (history[0].insn_opcode), | |
252b5132 RH |
3023 | MIPS_GR_REG)))) |
3024 | /* If the branch writes a register that the previous | |
3025 | instruction sets, we can not swap (we know that | |
3026 | branches write only to RD or to $31). */ | |
3027 | || (! mips_opts.mips16 | |
3028 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3029 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3030 | && (EXTRACT_OPERAND (RT, history[0]) |
3031 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3032 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3033 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3034 | || (! mips_opts.mips16 |
3035 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3036 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3037 | && (EXTRACT_OPERAND (RD, history[0]) |
3038 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3039 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3040 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3041 | || (mips_opts.mips16 |
3042 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3043 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3044 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3045 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3046 | == RA)))) |
3047 | /* If the branch writes a register that the previous | |
3048 | instruction reads, we can not swap (we know that | |
3049 | branches only write to RD or to $31). */ | |
3050 | || (! mips_opts.mips16 | |
3051 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3052 | && insn_uses_reg (&history[0], |
bf12938e | 3053 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3054 | MIPS_GR_REG)) |
3055 | || (! mips_opts.mips16 | |
3056 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3057 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3058 | || (mips_opts.mips16 |
3059 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3060 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3061 | /* If one instruction sets a condition code and the |
3062 | other one uses a condition code, we can not swap. */ | |
3063 | || ((pinfo & INSN_READ_COND_CODE) | |
3064 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3065 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3066 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3067 | /* If the previous instruction uses the PC, we can not | |
3068 | swap. */ | |
3069 | || (mips_opts.mips16 | |
3070 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3071 | /* If the previous instruction had a fixup in mips16 |
3072 | mode, we can not swap. This normally means that the | |
3073 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3074 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3075 | /* If the previous instruction is a sync, sync.l, or |
3076 | sync.p, we can not swap. */ | |
f173e82e | 3077 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3078 | { |
29024861 DU |
3079 | if (mips_opts.mips16 |
3080 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3081 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3082 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3083 | { |
3084 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3085 | ip->insn_opcode |= 0x0080; | |
3086 | install_insn (ip); | |
3087 | insert_into_history (0, 1, ip); | |
3088 | } | |
3089 | else | |
3090 | { | |
3091 | /* We could do even better for unconditional branches to | |
3092 | portions of this object file; we could pick up the | |
3093 | instruction at the destination, put it in the delay | |
3094 | slot, and bump the destination address. */ | |
3095 | insert_into_history (0, 1, ip); | |
3096 | emit_nop (); | |
3097 | } | |
3098 | ||
dd22970f ILT |
3099 | if (mips_relax.sequence) |
3100 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3101 | } |
3102 | else | |
3103 | { | |
3104 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3105 | struct mips_cl_insn delay = history[0]; |
3106 | if (mips_opts.mips16) | |
252b5132 | 3107 | { |
b8ee1a6e DU |
3108 | know (delay.frag == ip->frag); |
3109 | move_insn (ip, delay.frag, delay.where); | |
3110 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3111 | } |
3112 | else if (relaxed_branch) | |
3113 | { | |
3114 | /* Add the delay slot instruction to the end of the | |
3115 | current frag and shrink the fixed part of the | |
3116 | original frag. If the branch occupies the tail of | |
3117 | the latter, move it backwards to cover the gap. */ | |
3118 | delay.frag->fr_fix -= 4; | |
3119 | if (delay.frag == ip->frag) | |
3120 | move_insn (ip, ip->frag, ip->where - 4); | |
3121 | add_fixed_insn (&delay); | |
252b5132 RH |
3122 | } |
3123 | else | |
3124 | { | |
1e915849 RS |
3125 | move_insn (&delay, ip->frag, ip->where); |
3126 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3127 | } |
1e915849 RS |
3128 | history[0] = *ip; |
3129 | delay.fixed_p = 1; | |
3130 | insert_into_history (0, 1, &delay); | |
252b5132 | 3131 | } |
252b5132 RH |
3132 | |
3133 | /* If that was an unconditional branch, forget the previous | |
3134 | insn information. */ | |
3135 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3136 | mips_no_prev_insn (); |
252b5132 RH |
3137 | } |
3138 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3139 | { | |
3140 | /* We don't yet optimize a branch likely. What we should do | |
3141 | is look at the target, copy the instruction found there | |
3142 | into the delay slot, and increment the branch to jump to | |
3143 | the next instruction. */ | |
1e915849 | 3144 | insert_into_history (0, 1, ip); |
252b5132 | 3145 | emit_nop (); |
252b5132 RH |
3146 | } |
3147 | else | |
1e915849 | 3148 | insert_into_history (0, 1, ip); |
252b5132 | 3149 | } |
1e915849 RS |
3150 | else |
3151 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3152 | |
3153 | /* We just output an insn, so the next one doesn't have a label. */ | |
3154 | mips_clear_insn_labels (); | |
252b5132 RH |
3155 | } |
3156 | ||
7d10b47d | 3157 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3158 | |
3159 | static void | |
7d10b47d | 3160 | mips_no_prev_insn (void) |
252b5132 | 3161 | { |
7d10b47d RS |
3162 | prev_nop_frag = NULL; |
3163 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3164 | mips_clear_insn_labels (); |
3165 | } | |
3166 | ||
7d10b47d RS |
3167 | /* This function must be called before we emit something other than |
3168 | instructions. It is like mips_no_prev_insn except that it inserts | |
3169 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3170 | |
7d10b47d RS |
3171 | void |
3172 | mips_emit_delays (void) | |
252b5132 RH |
3173 | { |
3174 | if (! mips_opts.noreorder) | |
3175 | { | |
71400594 | 3176 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3177 | if (nops > 0) |
3178 | { | |
7d10b47d RS |
3179 | while (nops-- > 0) |
3180 | add_fixed_insn (NOP_INSN); | |
3181 | mips_move_labels (); | |
3182 | } | |
3183 | } | |
3184 | mips_no_prev_insn (); | |
3185 | } | |
3186 | ||
3187 | /* Start a (possibly nested) noreorder block. */ | |
3188 | ||
3189 | static void | |
3190 | start_noreorder (void) | |
3191 | { | |
3192 | if (mips_opts.noreorder == 0) | |
3193 | { | |
3194 | unsigned int i; | |
3195 | int nops; | |
3196 | ||
3197 | /* None of the instructions before the .set noreorder can be moved. */ | |
3198 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3199 | history[i].fixed_p = 1; | |
3200 | ||
3201 | /* Insert any nops that might be needed between the .set noreorder | |
3202 | block and the previous instructions. We will later remove any | |
3203 | nops that turn out not to be needed. */ | |
3204 | nops = nops_for_insn (history, NULL); | |
3205 | if (nops > 0) | |
3206 | { | |
3207 | if (mips_optimize != 0) | |
252b5132 RH |
3208 | { |
3209 | /* Record the frag which holds the nop instructions, so | |
3210 | that we can remove them if we don't need them. */ | |
3211 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3212 | prev_nop_frag = frag_now; | |
3213 | prev_nop_frag_holds = nops; | |
3214 | prev_nop_frag_required = 0; | |
3215 | prev_nop_frag_since = 0; | |
3216 | } | |
3217 | ||
3218 | for (; nops > 0; --nops) | |
1e915849 | 3219 | add_fixed_insn (NOP_INSN); |
252b5132 | 3220 | |
7d10b47d RS |
3221 | /* Move on to a new frag, so that it is safe to simply |
3222 | decrease the size of prev_nop_frag. */ | |
3223 | frag_wane (frag_now); | |
3224 | frag_new (0); | |
404a8071 | 3225 | mips_move_labels (); |
252b5132 | 3226 | } |
7d10b47d RS |
3227 | mips16_mark_labels (); |
3228 | mips_clear_insn_labels (); | |
252b5132 | 3229 | } |
7d10b47d RS |
3230 | mips_opts.noreorder++; |
3231 | mips_any_noreorder = 1; | |
3232 | } | |
252b5132 | 3233 | |
7d10b47d | 3234 | /* End a nested noreorder block. */ |
252b5132 | 3235 | |
7d10b47d RS |
3236 | static void |
3237 | end_noreorder (void) | |
3238 | { | |
3239 | mips_opts.noreorder--; | |
3240 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3241 | { | |
3242 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3243 | handling nop insertion the .set reorder way. */ | |
3244 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3245 | * (mips_opts.mips16 ? 2 : 4)); | |
3246 | insert_into_history (prev_nop_frag_since, | |
3247 | prev_nop_frag_required, NOP_INSN); | |
3248 | prev_nop_frag = NULL; | |
3249 | } | |
252b5132 RH |
3250 | } |
3251 | ||
584892a6 RS |
3252 | /* Set up global variables for the start of a new macro. */ |
3253 | ||
3254 | static void | |
3255 | macro_start (void) | |
3256 | { | |
3257 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3258 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3259 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3260 | & (INSN_UNCOND_BRANCH_DELAY |
3261 | | INSN_COND_BRANCH_DELAY | |
3262 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3263 | } | |
3264 | ||
3265 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3266 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3267 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3268 | ||
3269 | static const char * | |
3270 | macro_warning (relax_substateT subtype) | |
3271 | { | |
3272 | if (subtype & RELAX_DELAY_SLOT) | |
3273 | return _("Macro instruction expanded into multiple instructions" | |
3274 | " in a branch delay slot"); | |
3275 | else if (subtype & RELAX_NOMACRO) | |
3276 | return _("Macro instruction expanded into multiple instructions"); | |
3277 | else | |
3278 | return 0; | |
3279 | } | |
3280 | ||
3281 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3282 | ||
3283 | static void | |
3284 | macro_end (void) | |
3285 | { | |
3286 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3287 | { | |
3288 | relax_substateT subtype; | |
3289 | ||
3290 | /* Set up the relaxation warning flags. */ | |
3291 | subtype = 0; | |
3292 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3293 | subtype |= RELAX_SECOND_LONGER; | |
3294 | if (mips_opts.warn_about_macros) | |
3295 | subtype |= RELAX_NOMACRO; | |
3296 | if (mips_macro_warning.delay_slot_p) | |
3297 | subtype |= RELAX_DELAY_SLOT; | |
3298 | ||
3299 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3300 | { | |
3301 | /* Either the macro has a single implementation or both | |
3302 | implementations are longer than 4 bytes. Emit the | |
3303 | warning now. */ | |
3304 | const char *msg = macro_warning (subtype); | |
3305 | if (msg != 0) | |
3306 | as_warn (msg); | |
3307 | } | |
3308 | else | |
3309 | { | |
3310 | /* One implementation might need a warning but the other | |
3311 | definitely doesn't. */ | |
3312 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3313 | } | |
3314 | } | |
3315 | } | |
3316 | ||
6e1304d8 RS |
3317 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3318 | The first argument in *ARGS will be either the code for a single | |
3319 | relocation or -1 followed by the three codes that make up a | |
3320 | composite relocation. */ | |
3321 | ||
3322 | static void | |
3323 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3324 | { | |
3325 | int i, next; | |
3326 | ||
3327 | next = va_arg (*args, int); | |
3328 | if (next >= 0) | |
3329 | r[0] = (bfd_reloc_code_real_type) next; | |
3330 | else | |
3331 | for (i = 0; i < 3; i++) | |
3332 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3333 | } | |
3334 | ||
252b5132 RH |
3335 | /* Build an instruction created by a macro expansion. This is passed |
3336 | a pointer to the count of instructions created so far, an | |
3337 | expression, the name of the instruction to build, an operand format | |
3338 | string, and corresponding arguments. */ | |
3339 | ||
252b5132 | 3340 | static void |
67c0d1eb | 3341 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3342 | { |
1e915849 | 3343 | const struct mips_opcode *mo; |
252b5132 | 3344 | struct mips_cl_insn insn; |
f6688943 | 3345 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3346 | va_list args; |
252b5132 | 3347 | |
252b5132 | 3348 | va_start (args, fmt); |
252b5132 | 3349 | |
252b5132 RH |
3350 | if (mips_opts.mips16) |
3351 | { | |
67c0d1eb | 3352 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3353 | va_end (args); |
3354 | return; | |
3355 | } | |
3356 | ||
f6688943 TS |
3357 | r[0] = BFD_RELOC_UNUSED; |
3358 | r[1] = BFD_RELOC_UNUSED; | |
3359 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3360 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3361 | assert (mo); | |
3362 | assert (strcmp (name, mo->name) == 0); | |
3363 | ||
8b082fb1 TS |
3364 | while (1) |
3365 | { | |
3366 | /* Search until we get a match for NAME. It is assumed here that | |
3367 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3368 | if (strcmp (fmt, mo->args) == 0 | |
3369 | && mo->pinfo != INSN_MACRO | |
3370 | && OPCODE_IS_MEMBER (mo, | |
1e915849 | 3371 | (mips_opts.isa |
9b3f89ee | 3372 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
8b082fb1 TS |
3373 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
3374 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
3375 | ? INSN_DSP64 : 0) | |
3376 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) | |
e16bfa71 | 3377 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3378 | mips_opts.arch) |
8b082fb1 TS |
3379 | && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0)) |
3380 | break; | |
3381 | ||
1e915849 RS |
3382 | ++mo; |
3383 | assert (mo->name); | |
3384 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3385 | } |
3386 | ||
1e915849 | 3387 | create_insn (&insn, mo); |
252b5132 RH |
3388 | for (;;) |
3389 | { | |
3390 | switch (*fmt++) | |
3391 | { | |
3392 | case '\0': | |
3393 | break; | |
3394 | ||
3395 | case ',': | |
3396 | case '(': | |
3397 | case ')': | |
3398 | continue; | |
3399 | ||
5f74bc13 CD |
3400 | case '+': |
3401 | switch (*fmt++) | |
3402 | { | |
3403 | case 'A': | |
3404 | case 'E': | |
bf12938e | 3405 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3406 | continue; |
3407 | ||
3408 | case 'B': | |
3409 | case 'F': | |
3410 | /* Note that in the macro case, these arguments are already | |
3411 | in MSB form. (When handling the instruction in the | |
3412 | non-macro case, these arguments are sizes from which | |
3413 | MSB values must be calculated.) */ | |
bf12938e | 3414 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3415 | continue; |
3416 | ||
3417 | case 'C': | |
3418 | case 'G': | |
3419 | case 'H': | |
3420 | /* Note that in the macro case, these arguments are already | |
3421 | in MSBD form. (When handling the instruction in the | |
3422 | non-macro case, these arguments are sizes from which | |
3423 | MSBD values must be calculated.) */ | |
bf12938e | 3424 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3425 | continue; |
3426 | ||
3427 | default: | |
3428 | internalError (); | |
3429 | } | |
3430 | continue; | |
3431 | ||
8b082fb1 TS |
3432 | case '2': |
3433 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3434 | continue; | |
3435 | ||
252b5132 RH |
3436 | case 't': |
3437 | case 'w': | |
3438 | case 'E': | |
bf12938e | 3439 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3440 | continue; |
3441 | ||
3442 | case 'c': | |
bf12938e | 3443 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3444 | continue; |
3445 | ||
252b5132 RH |
3446 | case 'T': |
3447 | case 'W': | |
bf12938e | 3448 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3449 | continue; |
3450 | ||
3451 | case 'd': | |
3452 | case 'G': | |
af7ee8bf | 3453 | case 'K': |
bf12938e | 3454 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3455 | continue; |
3456 | ||
4372b673 NC |
3457 | case 'U': |
3458 | { | |
3459 | int tmp = va_arg (args, int); | |
3460 | ||
bf12938e RS |
3461 | INSERT_OPERAND (RT, insn, tmp); |
3462 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3463 | continue; |
4372b673 NC |
3464 | } |
3465 | ||
252b5132 RH |
3466 | case 'V': |
3467 | case 'S': | |
bf12938e | 3468 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3469 | continue; |
3470 | ||
3471 | case 'z': | |
3472 | continue; | |
3473 | ||
3474 | case '<': | |
bf12938e | 3475 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3476 | continue; |
3477 | ||
3478 | case 'D': | |
bf12938e | 3479 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3480 | continue; |
3481 | ||
3482 | case 'B': | |
bf12938e | 3483 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3484 | continue; |
3485 | ||
4372b673 | 3486 | case 'J': |
bf12938e | 3487 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3488 | continue; |
3489 | ||
252b5132 | 3490 | case 'q': |
bf12938e | 3491 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3492 | continue; |
3493 | ||
3494 | case 'b': | |
3495 | case 's': | |
3496 | case 'r': | |
3497 | case 'v': | |
bf12938e | 3498 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3499 | continue; |
3500 | ||
3501 | case 'i': | |
3502 | case 'j': | |
3503 | case 'o': | |
6e1304d8 | 3504 | macro_read_relocs (&args, r); |
cdf6fd85 | 3505 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3506 | || *r == BFD_RELOC_MIPS_LITERAL |
3507 | || *r == BFD_RELOC_MIPS_HIGHER | |
3508 | || *r == BFD_RELOC_HI16_S | |
3509 | || *r == BFD_RELOC_LO16 | |
3510 | || *r == BFD_RELOC_MIPS_GOT16 | |
3511 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3512 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3513 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3514 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3515 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3516 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3517 | continue; |
3518 | ||
3519 | case 'u': | |
6e1304d8 | 3520 | macro_read_relocs (&args, r); |
252b5132 RH |
3521 | assert (ep != NULL |
3522 | && (ep->X_op == O_constant | |
3523 | || (ep->X_op == O_symbol | |
f6688943 TS |
3524 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3525 | || *r == BFD_RELOC_HI16_S | |
3526 | || *r == BFD_RELOC_HI16 | |
3527 | || *r == BFD_RELOC_GPREL16 | |
3528 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3529 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3530 | continue; |
3531 | ||
3532 | case 'p': | |
3533 | assert (ep != NULL); | |
bad36eac | 3534 | |
252b5132 RH |
3535 | /* |
3536 | * This allows macro() to pass an immediate expression for | |
3537 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3538 | * |
3539 | * We don't allow branch relaxation for these branches, as | |
3540 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3541 | */ |
3542 | if (ep->X_op == O_constant) | |
3543 | { | |
bad36eac DJ |
3544 | if ((ep->X_add_number & 3) != 0) |
3545 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3546 | (unsigned long) ep->X_add_number); | |
3547 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3548 | as_bad (_("branch address range overflow (0x%lx)"), | |
3549 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3550 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3551 | ep = NULL; | |
3552 | } | |
3553 | else | |
0b25d3e6 | 3554 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3555 | continue; |
3556 | ||
3557 | case 'a': | |
3558 | assert (ep != NULL); | |
f6688943 | 3559 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3560 | continue; |
3561 | ||
3562 | case 'C': | |
a9e24354 | 3563 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3564 | continue; |
3565 | ||
d43b4baf | 3566 | case 'k': |
a9e24354 | 3567 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3568 | continue; |
3569 | ||
252b5132 RH |
3570 | default: |
3571 | internalError (); | |
3572 | } | |
3573 | break; | |
3574 | } | |
3575 | va_end (args); | |
f6688943 | 3576 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3577 | |
4d7206a2 | 3578 | append_insn (&insn, ep, r); |
252b5132 RH |
3579 | } |
3580 | ||
3581 | static void | |
67c0d1eb | 3582 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3583 | va_list args) |
252b5132 | 3584 | { |
1e915849 | 3585 | struct mips_opcode *mo; |
252b5132 | 3586 | struct mips_cl_insn insn; |
f6688943 TS |
3587 | bfd_reloc_code_real_type r[3] |
3588 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3589 | |
1e915849 RS |
3590 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3591 | assert (mo); | |
3592 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3593 | |
1e915849 | 3594 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3595 | { |
1e915849 RS |
3596 | ++mo; |
3597 | assert (mo->name); | |
3598 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3599 | } |
3600 | ||
1e915849 | 3601 | create_insn (&insn, mo); |
252b5132 RH |
3602 | for (;;) |
3603 | { | |
3604 | int c; | |
3605 | ||
3606 | c = *fmt++; | |
3607 | switch (c) | |
3608 | { | |
3609 | case '\0': | |
3610 | break; | |
3611 | ||
3612 | case ',': | |
3613 | case '(': | |
3614 | case ')': | |
3615 | continue; | |
3616 | ||
3617 | case 'y': | |
3618 | case 'w': | |
bf12938e | 3619 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3620 | continue; |
3621 | ||
3622 | case 'x': | |
3623 | case 'v': | |
bf12938e | 3624 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3625 | continue; |
3626 | ||
3627 | case 'z': | |
bf12938e | 3628 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3629 | continue; |
3630 | ||
3631 | case 'Z': | |
bf12938e | 3632 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3633 | continue; |
3634 | ||
3635 | case '0': | |
3636 | case 'S': | |
3637 | case 'P': | |
3638 | case 'R': | |
3639 | continue; | |
3640 | ||
3641 | case 'X': | |
bf12938e | 3642 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3643 | continue; |
3644 | ||
3645 | case 'Y': | |
3646 | { | |
3647 | int regno; | |
3648 | ||
3649 | regno = va_arg (args, int); | |
3650 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3651 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3652 | } |
3653 | continue; | |
3654 | ||
3655 | case '<': | |
3656 | case '>': | |
3657 | case '4': | |
3658 | case '5': | |
3659 | case 'H': | |
3660 | case 'W': | |
3661 | case 'D': | |
3662 | case 'j': | |
3663 | case '8': | |
3664 | case 'V': | |
3665 | case 'C': | |
3666 | case 'U': | |
3667 | case 'k': | |
3668 | case 'K': | |
3669 | case 'p': | |
3670 | case 'q': | |
3671 | { | |
3672 | assert (ep != NULL); | |
3673 | ||
3674 | if (ep->X_op != O_constant) | |
874e8986 | 3675 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3676 | else |
3677 | { | |
b34976b6 AM |
3678 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3679 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3680 | &insn.extend); |
252b5132 | 3681 | ep = NULL; |
f6688943 | 3682 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3683 | } |
3684 | } | |
3685 | continue; | |
3686 | ||
3687 | case '6': | |
bf12938e | 3688 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3689 | continue; |
3690 | } | |
3691 | ||
3692 | break; | |
3693 | } | |
3694 | ||
f6688943 | 3695 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3696 | |
4d7206a2 | 3697 | append_insn (&insn, ep, r); |
252b5132 RH |
3698 | } |
3699 | ||
2051e8c4 MR |
3700 | /* |
3701 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3702 | * higher bits unset. | |
3703 | */ | |
9f872bbe | 3704 | static void |
2051e8c4 MR |
3705 | normalize_constant_expr (expressionS *ex) |
3706 | { | |
9ee2a2d4 | 3707 | if (ex->X_op == O_constant |
2051e8c4 MR |
3708 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3709 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3710 | - 0x80000000); | |
3711 | } | |
3712 | ||
3713 | /* | |
3714 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3715 | * all higher bits unset. | |
3716 | */ | |
3717 | static void | |
3718 | normalize_address_expr (expressionS *ex) | |
3719 | { | |
3720 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3721 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3722 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3723 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3724 | - 0x80000000); | |
3725 | } | |
3726 | ||
438c16b8 TS |
3727 | /* |
3728 | * Generate a "jalr" instruction with a relocation hint to the called | |
3729 | * function. This occurs in NewABI PIC code. | |
3730 | */ | |
3731 | static void | |
67c0d1eb | 3732 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3733 | { |
685736be | 3734 | char *f = NULL; |
b34976b6 | 3735 | |
438c16b8 | 3736 | if (HAVE_NEWABI) |
f21f8242 | 3737 | { |
cc3d92a5 | 3738 | frag_grow (8); |
f21f8242 AO |
3739 | f = frag_more (0); |
3740 | } | |
67c0d1eb | 3741 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3742 | if (HAVE_NEWABI) |
f21f8242 | 3743 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3744 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3745 | } |
3746 | ||
252b5132 RH |
3747 | /* |
3748 | * Generate a "lui" instruction. | |
3749 | */ | |
3750 | static void | |
67c0d1eb | 3751 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3752 | { |
3753 | expressionS high_expr; | |
1e915849 | 3754 | const struct mips_opcode *mo; |
252b5132 | 3755 | struct mips_cl_insn insn; |
f6688943 TS |
3756 | bfd_reloc_code_real_type r[3] |
3757 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3758 | const char *name = "lui"; |
3759 | const char *fmt = "t,u"; | |
252b5132 RH |
3760 | |
3761 | assert (! mips_opts.mips16); | |
3762 | ||
4d7206a2 | 3763 | high_expr = *ep; |
252b5132 RH |
3764 | |
3765 | if (high_expr.X_op == O_constant) | |
3766 | { | |
54f4ddb3 | 3767 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3768 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3769 | >> 16) & 0xffff; | |
f6688943 | 3770 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3771 | } |
78e1bb40 | 3772 | else |
252b5132 RH |
3773 | { |
3774 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3775 | /* _gp_disp is a special case, used from s_cpload. |
3776 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3777 | assert (mips_pic == NO_PIC |
78e1bb40 | 3778 | || (! HAVE_NEWABI |
aa6975fb ILT |
3779 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3780 | || (! mips_in_shared | |
bbe506e8 TS |
3781 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3782 | "__gnu_local_gp") == 0)); | |
f6688943 | 3783 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3784 | } |
3785 | ||
1e915849 RS |
3786 | mo = hash_find (op_hash, name); |
3787 | assert (strcmp (name, mo->name) == 0); | |
3788 | assert (strcmp (fmt, mo->args) == 0); | |
3789 | create_insn (&insn, mo); | |
252b5132 | 3790 | |
bf12938e RS |
3791 | insn.insn_opcode = insn.insn_mo->match; |
3792 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3793 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3794 | { |
3795 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3796 | append_insn (&insn, NULL, r); |
252b5132 RH |
3797 | } |
3798 | else | |
4d7206a2 | 3799 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3800 | } |
3801 | ||
885add95 CD |
3802 | /* Generate a sequence of instructions to do a load or store from a constant |
3803 | offset off of a base register (breg) into/from a target register (treg), | |
3804 | using AT if necessary. */ | |
3805 | static void | |
67c0d1eb RS |
3806 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3807 | int treg, int breg, int dbl) | |
885add95 CD |
3808 | { |
3809 | assert (ep->X_op == O_constant); | |
3810 | ||
256ab948 | 3811 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3812 | if (!dbl) |
3813 | normalize_constant_expr (ep); | |
256ab948 | 3814 | |
67c1ffbe | 3815 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3816 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3817 | as_warn (_("operand overflow")); |
3818 | ||
3819 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3820 | { | |
3821 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3822 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3823 | } |
3824 | else | |
3825 | { | |
3826 | /* 32-bit offset, need multiple instructions and AT, like: | |
3827 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3828 | addu $tempreg,$tempreg,$breg | |
3829 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3830 | to handle the complete offset. */ | |
67c0d1eb RS |
3831 | macro_build_lui (ep, AT); |
3832 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3833 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 3834 | |
741fe287 | 3835 | if (!mips_opts.at) |
8fc2e39e | 3836 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3837 | } |
3838 | } | |
3839 | ||
252b5132 RH |
3840 | /* set_at() |
3841 | * Generates code to set the $at register to true (one) | |
3842 | * if reg is less than the immediate expression. | |
3843 | */ | |
3844 | static void | |
67c0d1eb | 3845 | set_at (int reg, int unsignedp) |
252b5132 RH |
3846 | { |
3847 | if (imm_expr.X_op == O_constant | |
3848 | && imm_expr.X_add_number >= -0x8000 | |
3849 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3850 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3851 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3852 | else |
3853 | { | |
67c0d1eb RS |
3854 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3855 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3856 | } |
3857 | } | |
3858 | ||
3859 | /* Warn if an expression is not a constant. */ | |
3860 | ||
3861 | static void | |
17a2f251 | 3862 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3863 | { |
3864 | if (ex->X_op == O_big) | |
3865 | as_bad (_("unsupported large constant")); | |
3866 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3867 | as_bad (_("Instruction %s requires absolute expression"), |
3868 | ip->insn_mo->name); | |
13757d0c | 3869 | |
9ee2a2d4 MR |
3870 | if (HAVE_32BIT_GPRS) |
3871 | normalize_constant_expr (ex); | |
252b5132 RH |
3872 | } |
3873 | ||
3874 | /* Count the leading zeroes by performing a binary chop. This is a | |
3875 | bulky bit of source, but performance is a LOT better for the | |
3876 | majority of values than a simple loop to count the bits: | |
3877 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3878 | if ((v) & (1 << (31 - lcnt))) | |
3879 | break; | |
3880 | However it is not code size friendly, and the gain will drop a bit | |
3881 | on certain cached systems. | |
3882 | */ | |
3883 | #define COUNT_TOP_ZEROES(v) \ | |
3884 | (((v) & ~0xffff) == 0 \ | |
3885 | ? ((v) & ~0xff) == 0 \ | |
3886 | ? ((v) & ~0xf) == 0 \ | |
3887 | ? ((v) & ~0x3) == 0 \ | |
3888 | ? ((v) & ~0x1) == 0 \ | |
3889 | ? !(v) \ | |
3890 | ? 32 \ | |
3891 | : 31 \ | |
3892 | : 30 \ | |
3893 | : ((v) & ~0x7) == 0 \ | |
3894 | ? 29 \ | |
3895 | : 28 \ | |
3896 | : ((v) & ~0x3f) == 0 \ | |
3897 | ? ((v) & ~0x1f) == 0 \ | |
3898 | ? 27 \ | |
3899 | : 26 \ | |
3900 | : ((v) & ~0x7f) == 0 \ | |
3901 | ? 25 \ | |
3902 | : 24 \ | |
3903 | : ((v) & ~0xfff) == 0 \ | |
3904 | ? ((v) & ~0x3ff) == 0 \ | |
3905 | ? ((v) & ~0x1ff) == 0 \ | |
3906 | ? 23 \ | |
3907 | : 22 \ | |
3908 | : ((v) & ~0x7ff) == 0 \ | |
3909 | ? 21 \ | |
3910 | : 20 \ | |
3911 | : ((v) & ~0x3fff) == 0 \ | |
3912 | ? ((v) & ~0x1fff) == 0 \ | |
3913 | ? 19 \ | |
3914 | : 18 \ | |
3915 | : ((v) & ~0x7fff) == 0 \ | |
3916 | ? 17 \ | |
3917 | : 16 \ | |
3918 | : ((v) & ~0xffffff) == 0 \ | |
3919 | ? ((v) & ~0xfffff) == 0 \ | |
3920 | ? ((v) & ~0x3ffff) == 0 \ | |
3921 | ? ((v) & ~0x1ffff) == 0 \ | |
3922 | ? 15 \ | |
3923 | : 14 \ | |
3924 | : ((v) & ~0x7ffff) == 0 \ | |
3925 | ? 13 \ | |
3926 | : 12 \ | |
3927 | : ((v) & ~0x3fffff) == 0 \ | |
3928 | ? ((v) & ~0x1fffff) == 0 \ | |
3929 | ? 11 \ | |
3930 | : 10 \ | |
3931 | : ((v) & ~0x7fffff) == 0 \ | |
3932 | ? 9 \ | |
3933 | : 8 \ | |
3934 | : ((v) & ~0xfffffff) == 0 \ | |
3935 | ? ((v) & ~0x3ffffff) == 0 \ | |
3936 | ? ((v) & ~0x1ffffff) == 0 \ | |
3937 | ? 7 \ | |
3938 | : 6 \ | |
3939 | : ((v) & ~0x7ffffff) == 0 \ | |
3940 | ? 5 \ | |
3941 | : 4 \ | |
3942 | : ((v) & ~0x3fffffff) == 0 \ | |
3943 | ? ((v) & ~0x1fffffff) == 0 \ | |
3944 | ? 3 \ | |
3945 | : 2 \ | |
3946 | : ((v) & ~0x7fffffff) == 0 \ | |
3947 | ? 1 \ | |
3948 | : 0) | |
3949 | ||
3950 | /* load_register() | |
67c1ffbe | 3951 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3952 | * an absolute expression value into a register. |
3953 | */ | |
3954 | static void | |
67c0d1eb | 3955 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3956 | { |
3957 | int freg; | |
3958 | expressionS hi32, lo32; | |
3959 | ||
3960 | if (ep->X_op != O_big) | |
3961 | { | |
3962 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3963 | |
3964 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3965 | if (!dbl) |
3966 | normalize_constant_expr (ep); | |
256ab948 TS |
3967 | |
3968 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3969 | { |
3970 | /* We can handle 16 bit signed values with an addiu to | |
3971 | $zero. No need to ever use daddiu here, since $zero and | |
3972 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3973 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3974 | return; |
3975 | } | |
3976 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3977 | { | |
3978 | /* We can handle 16 bit unsigned values with an ori to | |
3979 | $zero. */ | |
67c0d1eb | 3980 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3981 | return; |
3982 | } | |
256ab948 | 3983 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3984 | { |
3985 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3986 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3987 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3988 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3989 | return; |
3990 | } | |
3991 | } | |
3992 | ||
3993 | /* The value is larger than 32 bits. */ | |
3994 | ||
2051e8c4 | 3995 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3996 | { |
55e08f71 NC |
3997 | char value[32]; |
3998 | ||
3999 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4000 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4001 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4002 | return; |
4003 | } | |
4004 | ||
4005 | if (ep->X_op != O_big) | |
4006 | { | |
4007 | hi32 = *ep; | |
4008 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4009 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4010 | hi32.X_add_number &= 0xffffffff; | |
4011 | lo32 = *ep; | |
4012 | lo32.X_add_number &= 0xffffffff; | |
4013 | } | |
4014 | else | |
4015 | { | |
4016 | assert (ep->X_add_number > 2); | |
4017 | if (ep->X_add_number == 3) | |
4018 | generic_bignum[3] = 0; | |
4019 | else if (ep->X_add_number > 4) | |
4020 | as_bad (_("Number larger than 64 bits")); | |
4021 | lo32.X_op = O_constant; | |
4022 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4023 | hi32.X_op = O_constant; | |
4024 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4025 | } | |
4026 | ||
4027 | if (hi32.X_add_number == 0) | |
4028 | freg = 0; | |
4029 | else | |
4030 | { | |
4031 | int shift, bit; | |
4032 | unsigned long hi, lo; | |
4033 | ||
956cd1d6 | 4034 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4035 | { |
4036 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4037 | { | |
67c0d1eb | 4038 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4039 | return; |
4040 | } | |
4041 | if (lo32.X_add_number & 0x80000000) | |
4042 | { | |
67c0d1eb | 4043 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4044 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4045 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4046 | return; |
4047 | } | |
4048 | } | |
252b5132 RH |
4049 | |
4050 | /* Check for 16bit shifted constant. We know that hi32 is | |
4051 | non-zero, so start the mask on the first bit of the hi32 | |
4052 | value. */ | |
4053 | shift = 17; | |
4054 | do | |
beae10d5 KH |
4055 | { |
4056 | unsigned long himask, lomask; | |
4057 | ||
4058 | if (shift < 32) | |
4059 | { | |
4060 | himask = 0xffff >> (32 - shift); | |
4061 | lomask = (0xffff << shift) & 0xffffffff; | |
4062 | } | |
4063 | else | |
4064 | { | |
4065 | himask = 0xffff << (shift - 32); | |
4066 | lomask = 0; | |
4067 | } | |
4068 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4069 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4070 | { | |
4071 | expressionS tmp; | |
4072 | ||
4073 | tmp.X_op = O_constant; | |
4074 | if (shift < 32) | |
4075 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4076 | | (lo32.X_add_number >> shift)); | |
4077 | else | |
4078 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4079 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4080 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4081 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4082 | return; |
4083 | } | |
f9419b05 | 4084 | ++shift; |
beae10d5 KH |
4085 | } |
4086 | while (shift <= (64 - 16)); | |
252b5132 RH |
4087 | |
4088 | /* Find the bit number of the lowest one bit, and store the | |
4089 | shifted value in hi/lo. */ | |
4090 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4091 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4092 | if (lo != 0) | |
4093 | { | |
4094 | bit = 0; | |
4095 | while ((lo & 1) == 0) | |
4096 | { | |
4097 | lo >>= 1; | |
4098 | ++bit; | |
4099 | } | |
4100 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4101 | hi >>= bit; | |
4102 | } | |
4103 | else | |
4104 | { | |
4105 | bit = 32; | |
4106 | while ((hi & 1) == 0) | |
4107 | { | |
4108 | hi >>= 1; | |
4109 | ++bit; | |
4110 | } | |
4111 | lo = hi; | |
4112 | hi = 0; | |
4113 | } | |
4114 | ||
4115 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4116 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4117 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4118 | { |
4119 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4120 | if (shift != 0) |
beae10d5 | 4121 | { |
252b5132 RH |
4122 | expressionS tmp; |
4123 | ||
4124 | /* This instruction will set the register to be all | |
4125 | ones. */ | |
beae10d5 KH |
4126 | tmp.X_op = O_constant; |
4127 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4128 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4129 | if (bit != 0) |
4130 | { | |
4131 | bit += shift; | |
67c0d1eb RS |
4132 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4133 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4134 | } |
67c0d1eb RS |
4135 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4136 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4137 | return; |
4138 | } | |
4139 | } | |
252b5132 RH |
4140 | |
4141 | /* Sign extend hi32 before calling load_register, because we can | |
4142 | generally get better code when we load a sign extended value. */ | |
4143 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4144 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4145 | load_register (reg, &hi32, 0); |
252b5132 RH |
4146 | freg = reg; |
4147 | } | |
4148 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4149 | { | |
4150 | if (freg != 0) | |
4151 | { | |
67c0d1eb | 4152 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4153 | freg = reg; |
4154 | } | |
4155 | } | |
4156 | else | |
4157 | { | |
4158 | expressionS mid16; | |
4159 | ||
956cd1d6 | 4160 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4161 | { |
67c0d1eb RS |
4162 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4163 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4164 | return; |
4165 | } | |
252b5132 RH |
4166 | |
4167 | if (freg != 0) | |
4168 | { | |
67c0d1eb | 4169 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4170 | freg = reg; |
4171 | } | |
4172 | mid16 = lo32; | |
4173 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4174 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4175 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4176 | freg = reg; |
4177 | } | |
4178 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4179 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4180 | } |
4181 | ||
269137b2 TS |
4182 | static inline void |
4183 | load_delay_nop (void) | |
4184 | { | |
4185 | if (!gpr_interlocks) | |
4186 | macro_build (NULL, "nop", ""); | |
4187 | } | |
4188 | ||
252b5132 RH |
4189 | /* Load an address into a register. */ |
4190 | ||
4191 | static void | |
67c0d1eb | 4192 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4193 | { |
252b5132 RH |
4194 | if (ep->X_op != O_constant |
4195 | && ep->X_op != O_symbol) | |
4196 | { | |
4197 | as_bad (_("expression too complex")); | |
4198 | ep->X_op = O_constant; | |
4199 | } | |
4200 | ||
4201 | if (ep->X_op == O_constant) | |
4202 | { | |
67c0d1eb | 4203 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4204 | return; |
4205 | } | |
4206 | ||
4207 | if (mips_pic == NO_PIC) | |
4208 | { | |
4209 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4210 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4211 | Otherwise we want |
4212 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4213 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4214 | If we have an addend, we always use the latter form. |
76b3015f | 4215 | |
d6bc6245 TS |
4216 | With 64bit address space and a usable $at we want |
4217 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4218 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4219 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4220 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4221 | dsll32 $reg,0 | |
3a482fd5 | 4222 | daddu $reg,$reg,$at |
76b3015f | 4223 | |
c03099e6 | 4224 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4225 | on superscalar processors. |
4226 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4227 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4228 | dsll $reg,16 | |
4229 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4230 | dsll $reg,16 | |
4231 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4232 | |
4233 | For GP relative symbols in 64bit address space we can use | |
4234 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4235 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4236 | { |
6caf9ef4 TS |
4237 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4238 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4239 | { | |
4240 | relax_start (ep->X_add_symbol); | |
4241 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4242 | mips_gp_register, BFD_RELOC_GPREL16); | |
4243 | relax_switch (); | |
4244 | } | |
d6bc6245 | 4245 | |
741fe287 | 4246 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4247 | { |
67c0d1eb RS |
4248 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4249 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4250 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4251 | BFD_RELOC_MIPS_HIGHER); | |
4252 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4253 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4254 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4255 | *used_at = 1; |
4256 | } | |
4257 | else | |
4258 | { | |
67c0d1eb RS |
4259 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4260 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4261 | BFD_RELOC_MIPS_HIGHER); | |
4262 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4263 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4264 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4265 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4266 | } |
6caf9ef4 TS |
4267 | |
4268 | if (mips_relax.sequence) | |
4269 | relax_end (); | |
d6bc6245 | 4270 | } |
252b5132 RH |
4271 | else |
4272 | { | |
d6bc6245 | 4273 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4274 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4275 | { |
4d7206a2 | 4276 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4277 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4278 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4279 | relax_switch (); |
d6bc6245 | 4280 | } |
67c0d1eb RS |
4281 | macro_build_lui (ep, reg); |
4282 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4283 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4284 | if (mips_relax.sequence) |
4285 | relax_end (); | |
d6bc6245 | 4286 | } |
252b5132 | 4287 | } |
0a44bf69 | 4288 | else if (!mips_big_got) |
252b5132 RH |
4289 | { |
4290 | expressionS ex; | |
4291 | ||
4292 | /* If this is a reference to an external symbol, we want | |
4293 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4294 | Otherwise we want | |
4295 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4296 | nop | |
4297 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4298 | If there is a constant, it must be added in after. |
4299 | ||
ed6fb7bd | 4300 | If we have NewABI, we want |
f5040a92 AO |
4301 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4302 | unless we're referencing a global symbol with a non-zero | |
4303 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4304 | if (HAVE_NEWABI) |
4305 | { | |
f5040a92 AO |
4306 | if (ep->X_add_number) |
4307 | { | |
4d7206a2 | 4308 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4309 | ep->X_add_number = 0; |
4d7206a2 | 4310 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4311 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4312 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4313 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4314 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4315 | ex.X_op = O_constant; | |
67c0d1eb | 4316 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4317 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4318 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4319 | relax_switch (); |
f5040a92 | 4320 | } |
67c0d1eb | 4321 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4322 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4323 | if (mips_relax.sequence) |
4324 | relax_end (); | |
ed6fb7bd SC |
4325 | } |
4326 | else | |
4327 | { | |
f5040a92 AO |
4328 | ex.X_add_number = ep->X_add_number; |
4329 | ep->X_add_number = 0; | |
67c0d1eb RS |
4330 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4331 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4332 | load_delay_nop (); |
4d7206a2 RS |
4333 | relax_start (ep->X_add_symbol); |
4334 | relax_switch (); | |
67c0d1eb | 4335 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4336 | BFD_RELOC_LO16); |
4d7206a2 | 4337 | relax_end (); |
ed6fb7bd | 4338 | |
f5040a92 AO |
4339 | if (ex.X_add_number != 0) |
4340 | { | |
4341 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4342 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4343 | ex.X_op = O_constant; | |
67c0d1eb | 4344 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4345 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4346 | } |
252b5132 RH |
4347 | } |
4348 | } | |
0a44bf69 | 4349 | else if (mips_big_got) |
252b5132 RH |
4350 | { |
4351 | expressionS ex; | |
252b5132 RH |
4352 | |
4353 | /* This is the large GOT case. If this is a reference to an | |
4354 | external symbol, we want | |
4355 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4356 | addu $reg,$reg,$gp | |
4357 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4358 | |
4359 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4360 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4361 | nop | |
4362 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4363 | If there is a constant, it must be added in after. |
f5040a92 AO |
4364 | |
4365 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4366 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4367 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4368 | */ |
438c16b8 TS |
4369 | if (HAVE_NEWABI) |
4370 | { | |
4d7206a2 | 4371 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4372 | ep->X_add_number = 0; |
4d7206a2 | 4373 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4374 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4375 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4376 | reg, reg, mips_gp_register); | |
4377 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4378 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4379 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4380 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4381 | else if (ex.X_add_number) | |
4382 | { | |
4383 | ex.X_op = O_constant; | |
67c0d1eb RS |
4384 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4385 | BFD_RELOC_LO16); | |
f5040a92 AO |
4386 | } |
4387 | ||
4388 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4389 | relax_switch (); |
67c0d1eb | 4390 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4391 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4392 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4393 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4394 | relax_end (); |
438c16b8 | 4395 | } |
252b5132 | 4396 | else |
438c16b8 | 4397 | { |
f5040a92 AO |
4398 | ex.X_add_number = ep->X_add_number; |
4399 | ep->X_add_number = 0; | |
4d7206a2 | 4400 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4401 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4402 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4403 | reg, reg, mips_gp_register); | |
4404 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4405 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4406 | relax_switch (); |
4407 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4408 | { |
4409 | /* We need a nop before loading from $gp. This special | |
4410 | check is required because the lui which starts the main | |
4411 | instruction stream does not refer to $gp, and so will not | |
4412 | insert the nop which may be required. */ | |
67c0d1eb | 4413 | macro_build (NULL, "nop", ""); |
438c16b8 | 4414 | } |
67c0d1eb | 4415 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4416 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4417 | load_delay_nop (); |
67c0d1eb | 4418 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4419 | BFD_RELOC_LO16); |
4d7206a2 | 4420 | relax_end (); |
438c16b8 | 4421 | |
f5040a92 AO |
4422 | if (ex.X_add_number != 0) |
4423 | { | |
4424 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4425 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4426 | ex.X_op = O_constant; | |
67c0d1eb RS |
4427 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4428 | BFD_RELOC_LO16); | |
f5040a92 | 4429 | } |
252b5132 RH |
4430 | } |
4431 | } | |
252b5132 RH |
4432 | else |
4433 | abort (); | |
8fc2e39e | 4434 | |
741fe287 | 4435 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4436 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4437 | } |
4438 | ||
ea1fb5dc RS |
4439 | /* Move the contents of register SOURCE into register DEST. */ |
4440 | ||
4441 | static void | |
67c0d1eb | 4442 | move_register (int dest, int source) |
ea1fb5dc | 4443 | { |
67c0d1eb RS |
4444 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4445 | dest, source, 0); | |
ea1fb5dc RS |
4446 | } |
4447 | ||
4d7206a2 | 4448 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4449 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4450 | The two alternatives are: | |
4d7206a2 RS |
4451 | |
4452 | Global symbol Local sybmol | |
4453 | ------------- ------------ | |
4454 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4455 | ... ... | |
4456 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4457 | ||
4458 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4459 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4460 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4461 | |
4462 | static void | |
67c0d1eb | 4463 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4464 | { |
4465 | expressionS global; | |
4466 | ||
4467 | global = *local; | |
4468 | global.X_add_number = 0; | |
4469 | ||
4470 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4471 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4472 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4473 | relax_switch (); |
67c0d1eb RS |
4474 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4475 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4476 | relax_end (); |
4477 | } | |
4478 | ||
4479 | static void | |
67c0d1eb | 4480 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4481 | { |
4482 | expressionS global; | |
4483 | ||
4484 | global.X_op = O_constant; | |
4485 | global.X_op_symbol = NULL; | |
4486 | global.X_add_symbol = NULL; | |
4487 | global.X_add_number = local->X_add_number; | |
4488 | ||
4489 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4490 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4491 | dest, dest, BFD_RELOC_LO16); |
4492 | relax_switch (); | |
67c0d1eb | 4493 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4494 | relax_end (); |
4495 | } | |
4496 | ||
f6a22291 MR |
4497 | static void |
4498 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4499 | { | |
4500 | expressionS global; | |
4501 | int hold_mips_optimize; | |
4502 | ||
4503 | global.X_op = O_constant; | |
4504 | global.X_op_symbol = NULL; | |
4505 | global.X_add_symbol = NULL; | |
4506 | global.X_add_number = local->X_add_number; | |
4507 | ||
4508 | relax_start (local->X_add_symbol); | |
4509 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4510 | relax_switch (); | |
4511 | /* Set mips_optimize around the lui instruction to avoid | |
4512 | inserting an unnecessary nop after the lw. */ | |
4513 | hold_mips_optimize = mips_optimize; | |
4514 | mips_optimize = 2; | |
4515 | macro_build_lui (&global, tmp); | |
4516 | mips_optimize = hold_mips_optimize; | |
4517 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4518 | relax_end (); | |
4519 | ||
4520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4521 | } | |
4522 | ||
252b5132 RH |
4523 | /* |
4524 | * Build macros | |
4525 | * This routine implements the seemingly endless macro or synthesized | |
4526 | * instructions and addressing modes in the mips assembly language. Many | |
4527 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4528 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4529 | * this verbose method. Others are not simple macros but are more like |
4530 | * optimizing code generation. | |
4531 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4532 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4533 | * The ensuing load upper instructions are ommited. This implies some kind |
4534 | * of global optimization. We currently only optimize within a single macro. | |
4535 | * For many of the load and store macros if the address is specified as a | |
4536 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4537 | * first load register 'at' with zero and use it as the base register. The | |
4538 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4539 | * we're missing. | |
4540 | */ | |
4541 | static void | |
17a2f251 | 4542 | macro (struct mips_cl_insn *ip) |
252b5132 | 4543 | { |
741fe287 MR |
4544 | unsigned int treg, sreg, dreg, breg; |
4545 | unsigned int tempreg; | |
252b5132 | 4546 | int mask; |
43841e91 | 4547 | int used_at = 0; |
252b5132 RH |
4548 | expressionS expr1; |
4549 | const char *s; | |
4550 | const char *s2; | |
4551 | const char *fmt; | |
4552 | int likely = 0; | |
4553 | int dbl = 0; | |
4554 | int coproc = 0; | |
4555 | int lr = 0; | |
4556 | int imm = 0; | |
1abe91b1 | 4557 | int call = 0; |
252b5132 | 4558 | int off; |
67c0d1eb | 4559 | offsetT maxnum; |
252b5132 | 4560 | bfd_reloc_code_real_type r; |
252b5132 RH |
4561 | int hold_mips_optimize; |
4562 | ||
4563 | assert (! mips_opts.mips16); | |
4564 | ||
4565 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4566 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4567 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4568 | mask = ip->insn_mo->mask; | |
4569 | ||
4570 | expr1.X_op = O_constant; | |
4571 | expr1.X_op_symbol = NULL; | |
4572 | expr1.X_add_symbol = NULL; | |
4573 | expr1.X_add_number = 1; | |
4574 | ||
4575 | switch (mask) | |
4576 | { | |
4577 | case M_DABS: | |
4578 | dbl = 1; | |
4579 | case M_ABS: | |
4580 | /* bgez $a0,.+12 | |
4581 | move v0,$a0 | |
4582 | sub v0,$zero,$a0 | |
4583 | */ | |
4584 | ||
7d10b47d | 4585 | start_noreorder (); |
252b5132 RH |
4586 | |
4587 | expr1.X_add_number = 8; | |
67c0d1eb | 4588 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4589 | if (dreg == sreg) |
67c0d1eb | 4590 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4591 | else |
67c0d1eb RS |
4592 | move_register (dreg, sreg); |
4593 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4594 | |
7d10b47d | 4595 | end_noreorder (); |
8fc2e39e | 4596 | break; |
252b5132 RH |
4597 | |
4598 | case M_ADD_I: | |
4599 | s = "addi"; | |
4600 | s2 = "add"; | |
4601 | goto do_addi; | |
4602 | case M_ADDU_I: | |
4603 | s = "addiu"; | |
4604 | s2 = "addu"; | |
4605 | goto do_addi; | |
4606 | case M_DADD_I: | |
4607 | dbl = 1; | |
4608 | s = "daddi"; | |
4609 | s2 = "dadd"; | |
4610 | goto do_addi; | |
4611 | case M_DADDU_I: | |
4612 | dbl = 1; | |
4613 | s = "daddiu"; | |
4614 | s2 = "daddu"; | |
4615 | do_addi: | |
4616 | if (imm_expr.X_op == O_constant | |
4617 | && imm_expr.X_add_number >= -0x8000 | |
4618 | && imm_expr.X_add_number < 0x8000) | |
4619 | { | |
67c0d1eb | 4620 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4621 | break; |
252b5132 | 4622 | } |
8fc2e39e | 4623 | used_at = 1; |
67c0d1eb RS |
4624 | load_register (AT, &imm_expr, dbl); |
4625 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4626 | break; |
4627 | ||
4628 | case M_AND_I: | |
4629 | s = "andi"; | |
4630 | s2 = "and"; | |
4631 | goto do_bit; | |
4632 | case M_OR_I: | |
4633 | s = "ori"; | |
4634 | s2 = "or"; | |
4635 | goto do_bit; | |
4636 | case M_NOR_I: | |
4637 | s = ""; | |
4638 | s2 = "nor"; | |
4639 | goto do_bit; | |
4640 | case M_XOR_I: | |
4641 | s = "xori"; | |
4642 | s2 = "xor"; | |
4643 | do_bit: | |
4644 | if (imm_expr.X_op == O_constant | |
4645 | && imm_expr.X_add_number >= 0 | |
4646 | && imm_expr.X_add_number < 0x10000) | |
4647 | { | |
4648 | if (mask != M_NOR_I) | |
67c0d1eb | 4649 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4650 | else |
4651 | { | |
67c0d1eb RS |
4652 | macro_build (&imm_expr, "ori", "t,r,i", |
4653 | treg, sreg, BFD_RELOC_LO16); | |
4654 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4655 | } |
8fc2e39e | 4656 | break; |
252b5132 RH |
4657 | } |
4658 | ||
8fc2e39e | 4659 | used_at = 1; |
67c0d1eb RS |
4660 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4661 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4662 | break; |
4663 | ||
8b082fb1 TS |
4664 | case M_BALIGN: |
4665 | switch (imm_expr.X_add_number) | |
4666 | { | |
4667 | case 0: | |
4668 | macro_build (NULL, "nop", ""); | |
4669 | break; | |
4670 | case 2: | |
4671 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4672 | break; | |
4673 | default: | |
4674 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4675 | (int)imm_expr.X_add_number); | |
4676 | break; | |
4677 | } | |
4678 | break; | |
4679 | ||
252b5132 RH |
4680 | case M_BEQ_I: |
4681 | s = "beq"; | |
4682 | goto beq_i; | |
4683 | case M_BEQL_I: | |
4684 | s = "beql"; | |
4685 | likely = 1; | |
4686 | goto beq_i; | |
4687 | case M_BNE_I: | |
4688 | s = "bne"; | |
4689 | goto beq_i; | |
4690 | case M_BNEL_I: | |
4691 | s = "bnel"; | |
4692 | likely = 1; | |
4693 | beq_i: | |
4694 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4695 | { | |
67c0d1eb | 4696 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4697 | break; |
252b5132 | 4698 | } |
8fc2e39e | 4699 | used_at = 1; |
67c0d1eb RS |
4700 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4701 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4702 | break; |
4703 | ||
4704 | case M_BGEL: | |
4705 | likely = 1; | |
4706 | case M_BGE: | |
4707 | if (treg == 0) | |
4708 | { | |
67c0d1eb | 4709 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4710 | break; |
252b5132 RH |
4711 | } |
4712 | if (sreg == 0) | |
4713 | { | |
67c0d1eb | 4714 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4715 | break; |
252b5132 | 4716 | } |
8fc2e39e | 4717 | used_at = 1; |
67c0d1eb RS |
4718 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4719 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4720 | break; |
4721 | ||
4722 | case M_BGTL_I: | |
4723 | likely = 1; | |
4724 | case M_BGT_I: | |
4725 | /* check for > max integer */ | |
4726 | maxnum = 0x7fffffff; | |
ca4e0257 | 4727 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4728 | { |
4729 | maxnum <<= 16; | |
4730 | maxnum |= 0xffff; | |
4731 | maxnum <<= 16; | |
4732 | maxnum |= 0xffff; | |
4733 | } | |
4734 | if (imm_expr.X_op == O_constant | |
4735 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4736 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4737 | { |
4738 | do_false: | |
4739 | /* result is always false */ | |
4740 | if (! likely) | |
67c0d1eb | 4741 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4742 | else |
67c0d1eb | 4743 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4744 | break; |
252b5132 RH |
4745 | } |
4746 | if (imm_expr.X_op != O_constant) | |
4747 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4748 | ++imm_expr.X_add_number; |
252b5132 RH |
4749 | /* FALLTHROUGH */ |
4750 | case M_BGE_I: | |
4751 | case M_BGEL_I: | |
4752 | if (mask == M_BGEL_I) | |
4753 | likely = 1; | |
4754 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4755 | { | |
67c0d1eb | 4756 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4757 | break; |
252b5132 RH |
4758 | } |
4759 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4760 | { | |
67c0d1eb | 4761 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4762 | break; |
252b5132 RH |
4763 | } |
4764 | maxnum = 0x7fffffff; | |
ca4e0257 | 4765 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4766 | { |
4767 | maxnum <<= 16; | |
4768 | maxnum |= 0xffff; | |
4769 | maxnum <<= 16; | |
4770 | maxnum |= 0xffff; | |
4771 | } | |
4772 | maxnum = - maxnum - 1; | |
4773 | if (imm_expr.X_op == O_constant | |
4774 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4775 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4776 | { |
4777 | do_true: | |
4778 | /* result is always true */ | |
4779 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4780 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4781 | break; |
252b5132 | 4782 | } |
8fc2e39e | 4783 | used_at = 1; |
67c0d1eb RS |
4784 | set_at (sreg, 0); |
4785 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4786 | break; |
4787 | ||
4788 | case M_BGEUL: | |
4789 | likely = 1; | |
4790 | case M_BGEU: | |
4791 | if (treg == 0) | |
4792 | goto do_true; | |
4793 | if (sreg == 0) | |
4794 | { | |
67c0d1eb | 4795 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4796 | "s,t,p", 0, treg); |
8fc2e39e | 4797 | break; |
252b5132 | 4798 | } |
8fc2e39e | 4799 | used_at = 1; |
67c0d1eb RS |
4800 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4801 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4802 | break; |
4803 | ||
4804 | case M_BGTUL_I: | |
4805 | likely = 1; | |
4806 | case M_BGTU_I: | |
4807 | if (sreg == 0 | |
ca4e0257 | 4808 | || (HAVE_32BIT_GPRS |
252b5132 | 4809 | && imm_expr.X_op == O_constant |
956cd1d6 | 4810 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4811 | goto do_false; |
4812 | if (imm_expr.X_op != O_constant) | |
4813 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4814 | ++imm_expr.X_add_number; |
252b5132 RH |
4815 | /* FALLTHROUGH */ |
4816 | case M_BGEU_I: | |
4817 | case M_BGEUL_I: | |
4818 | if (mask == M_BGEUL_I) | |
4819 | likely = 1; | |
4820 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4821 | goto do_true; | |
4822 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4823 | { | |
67c0d1eb | 4824 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4825 | "s,t,p", sreg, 0); |
8fc2e39e | 4826 | break; |
252b5132 | 4827 | } |
8fc2e39e | 4828 | used_at = 1; |
67c0d1eb RS |
4829 | set_at (sreg, 1); |
4830 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4831 | break; |
4832 | ||
4833 | case M_BGTL: | |
4834 | likely = 1; | |
4835 | case M_BGT: | |
4836 | if (treg == 0) | |
4837 | { | |
67c0d1eb | 4838 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4839 | break; |
252b5132 RH |
4840 | } |
4841 | if (sreg == 0) | |
4842 | { | |
67c0d1eb | 4843 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4844 | break; |
252b5132 | 4845 | } |
8fc2e39e | 4846 | used_at = 1; |
67c0d1eb RS |
4847 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4848 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4849 | break; |
4850 | ||
4851 | case M_BGTUL: | |
4852 | likely = 1; | |
4853 | case M_BGTU: | |
4854 | if (treg == 0) | |
4855 | { | |
67c0d1eb | 4856 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4857 | "s,t,p", sreg, 0); |
8fc2e39e | 4858 | break; |
252b5132 RH |
4859 | } |
4860 | if (sreg == 0) | |
4861 | goto do_false; | |
8fc2e39e | 4862 | used_at = 1; |
67c0d1eb RS |
4863 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4864 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4865 | break; |
4866 | ||
4867 | case M_BLEL: | |
4868 | likely = 1; | |
4869 | case M_BLE: | |
4870 | if (treg == 0) | |
4871 | { | |
67c0d1eb | 4872 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4873 | break; |
252b5132 RH |
4874 | } |
4875 | if (sreg == 0) | |
4876 | { | |
67c0d1eb | 4877 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4878 | break; |
252b5132 | 4879 | } |
8fc2e39e | 4880 | used_at = 1; |
67c0d1eb RS |
4881 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4882 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4883 | break; |
4884 | ||
4885 | case M_BLEL_I: | |
4886 | likely = 1; | |
4887 | case M_BLE_I: | |
4888 | maxnum = 0x7fffffff; | |
ca4e0257 | 4889 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4890 | { |
4891 | maxnum <<= 16; | |
4892 | maxnum |= 0xffff; | |
4893 | maxnum <<= 16; | |
4894 | maxnum |= 0xffff; | |
4895 | } | |
4896 | if (imm_expr.X_op == O_constant | |
4897 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4898 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4899 | goto do_true; |
4900 | if (imm_expr.X_op != O_constant) | |
4901 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4902 | ++imm_expr.X_add_number; |
252b5132 RH |
4903 | /* FALLTHROUGH */ |
4904 | case M_BLT_I: | |
4905 | case M_BLTL_I: | |
4906 | if (mask == M_BLTL_I) | |
4907 | likely = 1; | |
4908 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4909 | { | |
67c0d1eb | 4910 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4911 | break; |
252b5132 RH |
4912 | } |
4913 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4914 | { | |
67c0d1eb | 4915 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4916 | break; |
252b5132 | 4917 | } |
8fc2e39e | 4918 | used_at = 1; |
67c0d1eb RS |
4919 | set_at (sreg, 0); |
4920 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4921 | break; |
4922 | ||
4923 | case M_BLEUL: | |
4924 | likely = 1; | |
4925 | case M_BLEU: | |
4926 | if (treg == 0) | |
4927 | { | |
67c0d1eb | 4928 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4929 | "s,t,p", sreg, 0); |
8fc2e39e | 4930 | break; |
252b5132 RH |
4931 | } |
4932 | if (sreg == 0) | |
4933 | goto do_true; | |
8fc2e39e | 4934 | used_at = 1; |
67c0d1eb RS |
4935 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4936 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4937 | break; |
4938 | ||
4939 | case M_BLEUL_I: | |
4940 | likely = 1; | |
4941 | case M_BLEU_I: | |
4942 | if (sreg == 0 | |
ca4e0257 | 4943 | || (HAVE_32BIT_GPRS |
252b5132 | 4944 | && imm_expr.X_op == O_constant |
956cd1d6 | 4945 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4946 | goto do_true; |
4947 | if (imm_expr.X_op != O_constant) | |
4948 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4949 | ++imm_expr.X_add_number; |
252b5132 RH |
4950 | /* FALLTHROUGH */ |
4951 | case M_BLTU_I: | |
4952 | case M_BLTUL_I: | |
4953 | if (mask == M_BLTUL_I) | |
4954 | likely = 1; | |
4955 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4956 | goto do_false; | |
4957 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4958 | { | |
67c0d1eb | 4959 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4960 | "s,t,p", sreg, 0); |
8fc2e39e | 4961 | break; |
252b5132 | 4962 | } |
8fc2e39e | 4963 | used_at = 1; |
67c0d1eb RS |
4964 | set_at (sreg, 1); |
4965 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4966 | break; |
4967 | ||
4968 | case M_BLTL: | |
4969 | likely = 1; | |
4970 | case M_BLT: | |
4971 | if (treg == 0) | |
4972 | { | |
67c0d1eb | 4973 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4974 | break; |
252b5132 RH |
4975 | } |
4976 | if (sreg == 0) | |
4977 | { | |
67c0d1eb | 4978 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4979 | break; |
252b5132 | 4980 | } |
8fc2e39e | 4981 | used_at = 1; |
67c0d1eb RS |
4982 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4983 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4984 | break; |
4985 | ||
4986 | case M_BLTUL: | |
4987 | likely = 1; | |
4988 | case M_BLTU: | |
4989 | if (treg == 0) | |
4990 | goto do_false; | |
4991 | if (sreg == 0) | |
4992 | { | |
67c0d1eb | 4993 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4994 | "s,t,p", 0, treg); |
8fc2e39e | 4995 | break; |
252b5132 | 4996 | } |
8fc2e39e | 4997 | used_at = 1; |
67c0d1eb RS |
4998 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4999 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5000 | break; |
5001 | ||
5f74bc13 CD |
5002 | case M_DEXT: |
5003 | { | |
5004 | unsigned long pos; | |
5005 | unsigned long size; | |
5006 | ||
5007 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5008 | { | |
5009 | as_bad (_("Unsupported large constant")); | |
5010 | pos = size = 1; | |
5011 | } | |
5012 | else | |
5013 | { | |
5014 | pos = (unsigned long) imm_expr.X_add_number; | |
5015 | size = (unsigned long) imm2_expr.X_add_number; | |
5016 | } | |
5017 | ||
5018 | if (pos > 63) | |
5019 | { | |
5020 | as_bad (_("Improper position (%lu)"), pos); | |
5021 | pos = 1; | |
5022 | } | |
5023 | if (size == 0 || size > 64 | |
5024 | || (pos + size - 1) > 63) | |
5025 | { | |
5026 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5027 | size, pos); | |
5028 | size = 1; | |
5029 | } | |
5030 | ||
5031 | if (size <= 32 && pos < 32) | |
5032 | { | |
5033 | s = "dext"; | |
5034 | fmt = "t,r,+A,+C"; | |
5035 | } | |
5036 | else if (size <= 32) | |
5037 | { | |
5038 | s = "dextu"; | |
5039 | fmt = "t,r,+E,+H"; | |
5040 | } | |
5041 | else | |
5042 | { | |
5043 | s = "dextm"; | |
5044 | fmt = "t,r,+A,+G"; | |
5045 | } | |
67c0d1eb | 5046 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5047 | } |
8fc2e39e | 5048 | break; |
5f74bc13 CD |
5049 | |
5050 | case M_DINS: | |
5051 | { | |
5052 | unsigned long pos; | |
5053 | unsigned long size; | |
5054 | ||
5055 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5056 | { | |
5057 | as_bad (_("Unsupported large constant")); | |
5058 | pos = size = 1; | |
5059 | } | |
5060 | else | |
5061 | { | |
5062 | pos = (unsigned long) imm_expr.X_add_number; | |
5063 | size = (unsigned long) imm2_expr.X_add_number; | |
5064 | } | |
5065 | ||
5066 | if (pos > 63) | |
5067 | { | |
5068 | as_bad (_("Improper position (%lu)"), pos); | |
5069 | pos = 1; | |
5070 | } | |
5071 | if (size == 0 || size > 64 | |
5072 | || (pos + size - 1) > 63) | |
5073 | { | |
5074 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5075 | size, pos); | |
5076 | size = 1; | |
5077 | } | |
5078 | ||
5079 | if (pos < 32 && (pos + size - 1) < 32) | |
5080 | { | |
5081 | s = "dins"; | |
5082 | fmt = "t,r,+A,+B"; | |
5083 | } | |
5084 | else if (pos >= 32) | |
5085 | { | |
5086 | s = "dinsu"; | |
5087 | fmt = "t,r,+E,+F"; | |
5088 | } | |
5089 | else | |
5090 | { | |
5091 | s = "dinsm"; | |
5092 | fmt = "t,r,+A,+F"; | |
5093 | } | |
67c0d1eb RS |
5094 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5095 | pos + size - 1); | |
5f74bc13 | 5096 | } |
8fc2e39e | 5097 | break; |
5f74bc13 | 5098 | |
252b5132 RH |
5099 | case M_DDIV_3: |
5100 | dbl = 1; | |
5101 | case M_DIV_3: | |
5102 | s = "mflo"; | |
5103 | goto do_div3; | |
5104 | case M_DREM_3: | |
5105 | dbl = 1; | |
5106 | case M_REM_3: | |
5107 | s = "mfhi"; | |
5108 | do_div3: | |
5109 | if (treg == 0) | |
5110 | { | |
5111 | as_warn (_("Divide by zero.")); | |
5112 | if (mips_trap) | |
67c0d1eb | 5113 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5114 | else |
67c0d1eb | 5115 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5116 | break; |
252b5132 RH |
5117 | } |
5118 | ||
7d10b47d | 5119 | start_noreorder (); |
252b5132 RH |
5120 | if (mips_trap) |
5121 | { | |
67c0d1eb RS |
5122 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5123 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5124 | } |
5125 | else | |
5126 | { | |
5127 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5128 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5129 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5130 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5131 | } |
5132 | expr1.X_add_number = -1; | |
8fc2e39e | 5133 | used_at = 1; |
f6a22291 | 5134 | load_register (AT, &expr1, dbl); |
252b5132 | 5135 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5136 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5137 | if (dbl) |
5138 | { | |
5139 | expr1.X_add_number = 1; | |
f6a22291 | 5140 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5141 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5142 | } |
5143 | else | |
5144 | { | |
5145 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5146 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5147 | } |
5148 | if (mips_trap) | |
5149 | { | |
67c0d1eb | 5150 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5151 | /* We want to close the noreorder block as soon as possible, so |
5152 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5153 | end_noreorder (); |
252b5132 RH |
5154 | } |
5155 | else | |
5156 | { | |
5157 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5158 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5159 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5160 | |
5161 | /* We want to close the noreorder block as soon as possible, so | |
5162 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5163 | end_noreorder (); |
252b5132 | 5164 | |
67c0d1eb | 5165 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5166 | } |
67c0d1eb | 5167 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5168 | break; |
5169 | ||
5170 | case M_DIV_3I: | |
5171 | s = "div"; | |
5172 | s2 = "mflo"; | |
5173 | goto do_divi; | |
5174 | case M_DIVU_3I: | |
5175 | s = "divu"; | |
5176 | s2 = "mflo"; | |
5177 | goto do_divi; | |
5178 | case M_REM_3I: | |
5179 | s = "div"; | |
5180 | s2 = "mfhi"; | |
5181 | goto do_divi; | |
5182 | case M_REMU_3I: | |
5183 | s = "divu"; | |
5184 | s2 = "mfhi"; | |
5185 | goto do_divi; | |
5186 | case M_DDIV_3I: | |
5187 | dbl = 1; | |
5188 | s = "ddiv"; | |
5189 | s2 = "mflo"; | |
5190 | goto do_divi; | |
5191 | case M_DDIVU_3I: | |
5192 | dbl = 1; | |
5193 | s = "ddivu"; | |
5194 | s2 = "mflo"; | |
5195 | goto do_divi; | |
5196 | case M_DREM_3I: | |
5197 | dbl = 1; | |
5198 | s = "ddiv"; | |
5199 | s2 = "mfhi"; | |
5200 | goto do_divi; | |
5201 | case M_DREMU_3I: | |
5202 | dbl = 1; | |
5203 | s = "ddivu"; | |
5204 | s2 = "mfhi"; | |
5205 | do_divi: | |
5206 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5207 | { | |
5208 | as_warn (_("Divide by zero.")); | |
5209 | if (mips_trap) | |
67c0d1eb | 5210 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5211 | else |
67c0d1eb | 5212 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5213 | break; |
252b5132 RH |
5214 | } |
5215 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5216 | { | |
5217 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5218 | move_register (dreg, sreg); |
252b5132 | 5219 | else |
67c0d1eb | 5220 | move_register (dreg, 0); |
8fc2e39e | 5221 | break; |
252b5132 RH |
5222 | } |
5223 | if (imm_expr.X_op == O_constant | |
5224 | && imm_expr.X_add_number == -1 | |
5225 | && s[strlen (s) - 1] != 'u') | |
5226 | { | |
5227 | if (strcmp (s2, "mflo") == 0) | |
5228 | { | |
67c0d1eb | 5229 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5230 | } |
5231 | else | |
67c0d1eb | 5232 | move_register (dreg, 0); |
8fc2e39e | 5233 | break; |
252b5132 RH |
5234 | } |
5235 | ||
8fc2e39e | 5236 | used_at = 1; |
67c0d1eb RS |
5237 | load_register (AT, &imm_expr, dbl); |
5238 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5239 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5240 | break; |
5241 | ||
5242 | case M_DIVU_3: | |
5243 | s = "divu"; | |
5244 | s2 = "mflo"; | |
5245 | goto do_divu3; | |
5246 | case M_REMU_3: | |
5247 | s = "divu"; | |
5248 | s2 = "mfhi"; | |
5249 | goto do_divu3; | |
5250 | case M_DDIVU_3: | |
5251 | s = "ddivu"; | |
5252 | s2 = "mflo"; | |
5253 | goto do_divu3; | |
5254 | case M_DREMU_3: | |
5255 | s = "ddivu"; | |
5256 | s2 = "mfhi"; | |
5257 | do_divu3: | |
7d10b47d | 5258 | start_noreorder (); |
252b5132 RH |
5259 | if (mips_trap) |
5260 | { | |
67c0d1eb RS |
5261 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5262 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5263 | /* We want to close the noreorder block as soon as possible, so |
5264 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5265 | end_noreorder (); |
252b5132 RH |
5266 | } |
5267 | else | |
5268 | { | |
5269 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5270 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5271 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5272 | |
5273 | /* We want to close the noreorder block as soon as possible, so | |
5274 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5275 | end_noreorder (); |
67c0d1eb | 5276 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5277 | } |
67c0d1eb | 5278 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5279 | break; |
252b5132 | 5280 | |
1abe91b1 MR |
5281 | case M_DLCA_AB: |
5282 | dbl = 1; | |
5283 | case M_LCA_AB: | |
5284 | call = 1; | |
5285 | goto do_la; | |
252b5132 RH |
5286 | case M_DLA_AB: |
5287 | dbl = 1; | |
5288 | case M_LA_AB: | |
1abe91b1 | 5289 | do_la: |
252b5132 RH |
5290 | /* Load the address of a symbol into a register. If breg is not |
5291 | zero, we then add a base register to it. */ | |
5292 | ||
3bec30a8 TS |
5293 | if (dbl && HAVE_32BIT_GPRS) |
5294 | as_warn (_("dla used to load 32-bit register")); | |
5295 | ||
c90bbe5b | 5296 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5297 | as_warn (_("la used to load 64-bit address")); |
5298 | ||
0c11417f MR |
5299 | if (offset_expr.X_op == O_constant |
5300 | && offset_expr.X_add_number >= -0x8000 | |
5301 | && offset_expr.X_add_number < 0x8000) | |
5302 | { | |
aed1a261 | 5303 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5304 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5305 | break; |
0c11417f MR |
5306 | } |
5307 | ||
741fe287 | 5308 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5309 | { |
5310 | tempreg = AT; | |
5311 | used_at = 1; | |
5312 | } | |
5313 | else | |
5314 | { | |
5315 | tempreg = treg; | |
afdbd6d0 CD |
5316 | } |
5317 | ||
252b5132 RH |
5318 | if (offset_expr.X_op != O_symbol |
5319 | && offset_expr.X_op != O_constant) | |
5320 | { | |
5321 | as_bad (_("expression too complex")); | |
5322 | offset_expr.X_op = O_constant; | |
5323 | } | |
5324 | ||
252b5132 | 5325 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5326 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5327 | else if (mips_pic == NO_PIC) |
5328 | { | |
d6bc6245 | 5329 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5330 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5331 | Otherwise we want |
5332 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5333 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5334 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5335 | so we may as well always use the latter form. |
76b3015f | 5336 | |
6caf9ef4 TS |
5337 | With 64bit address space and a usable $at we want |
5338 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5339 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5340 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5341 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5342 | dsll32 $tempreg,0 | |
5343 | daddu $tempreg,$tempreg,$at | |
5344 | ||
5345 | If $at is already in use, we use a path which is suboptimal | |
5346 | on superscalar processors. | |
5347 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5348 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5349 | dsll $tempreg,16 | |
5350 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5351 | dsll $tempreg,16 | |
5352 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5353 | ||
5354 | For GP relative symbols in 64bit address space we can use | |
5355 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5356 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5357 | { |
6caf9ef4 TS |
5358 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5359 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5360 | { | |
5361 | relax_start (offset_expr.X_add_symbol); | |
5362 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5363 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5364 | relax_switch (); | |
5365 | } | |
d6bc6245 | 5366 | |
741fe287 | 5367 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5368 | { |
67c0d1eb | 5369 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5370 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5371 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5372 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5373 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5374 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5375 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5376 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5377 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5378 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5379 | used_at = 1; |
5380 | } | |
5381 | else | |
5382 | { | |
67c0d1eb | 5383 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5384 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5385 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5386 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5387 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5388 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5389 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5390 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5391 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5392 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5393 | } |
6caf9ef4 TS |
5394 | |
5395 | if (mips_relax.sequence) | |
5396 | relax_end (); | |
98d3f06f KH |
5397 | } |
5398 | else | |
5399 | { | |
5400 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5401 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5402 | { |
4d7206a2 | 5403 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5404 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5405 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5406 | relax_switch (); |
98d3f06f | 5407 | } |
6943caf0 ILT |
5408 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5409 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5410 | macro_build_lui (&offset_expr, tempreg); |
5411 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5412 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5413 | if (mips_relax.sequence) |
5414 | relax_end (); | |
98d3f06f | 5415 | } |
252b5132 | 5416 | } |
0a44bf69 | 5417 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5418 | { |
9117d219 NC |
5419 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5420 | ||
252b5132 RH |
5421 | /* If this is a reference to an external symbol, and there |
5422 | is no constant, we want | |
5423 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5424 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5425 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5426 | For a local symbol, we want |
5427 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5428 | nop | |
5429 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5430 | ||
5431 | If we have a small constant, and this is a reference to | |
5432 | an external symbol, we want | |
5433 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5434 | nop | |
5435 | addiu $tempreg,$tempreg,<constant> | |
5436 | For a local symbol, we want the same instruction | |
5437 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5438 | addiu instruction. | |
5439 | ||
5440 | If we have a large constant, and this is a reference to | |
5441 | an external symbol, we want | |
5442 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5443 | lui $at,<hiconstant> | |
5444 | addiu $at,$at,<loconstant> | |
5445 | addu $tempreg,$tempreg,$at | |
5446 | For a local symbol, we want the same instruction | |
5447 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5448 | addiu instruction. |
ed6fb7bd SC |
5449 | */ |
5450 | ||
4d7206a2 | 5451 | if (offset_expr.X_add_number == 0) |
252b5132 | 5452 | { |
0a44bf69 RS |
5453 | if (mips_pic == SVR4_PIC |
5454 | && breg == 0 | |
5455 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5456 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5457 | ||
5458 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5459 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5460 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5461 | if (breg != 0) |
252b5132 RH |
5462 | { |
5463 | /* We're going to put in an addu instruction using | |
5464 | tempreg, so we may as well insert the nop right | |
5465 | now. */ | |
269137b2 | 5466 | load_delay_nop (); |
252b5132 | 5467 | } |
4d7206a2 | 5468 | relax_switch (); |
67c0d1eb RS |
5469 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5470 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5471 | load_delay_nop (); |
67c0d1eb RS |
5472 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5473 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5474 | relax_end (); |
252b5132 RH |
5475 | /* FIXME: If breg == 0, and the next instruction uses |
5476 | $tempreg, then if this variant case is used an extra | |
5477 | nop will be generated. */ | |
5478 | } | |
4d7206a2 RS |
5479 | else if (offset_expr.X_add_number >= -0x8000 |
5480 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5481 | { |
67c0d1eb | 5482 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5483 | load_delay_nop (); |
67c0d1eb | 5484 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5485 | } |
5486 | else | |
5487 | { | |
4d7206a2 RS |
5488 | expr1.X_add_number = offset_expr.X_add_number; |
5489 | offset_expr.X_add_number = | |
5490 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5491 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5492 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5493 | /* If we are going to add in a base register, and the |
5494 | target register and the base register are the same, | |
5495 | then we are using AT as a temporary register. Since | |
5496 | we want to load the constant into AT, we add our | |
5497 | current AT (from the global offset table) and the | |
5498 | register into the register now, and pretend we were | |
5499 | not using a base register. */ | |
67c0d1eb | 5500 | if (breg == treg) |
252b5132 | 5501 | { |
269137b2 | 5502 | load_delay_nop (); |
67c0d1eb | 5503 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5504 | treg, AT, breg); |
252b5132 RH |
5505 | breg = 0; |
5506 | tempreg = treg; | |
252b5132 | 5507 | } |
f6a22291 | 5508 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5509 | used_at = 1; |
5510 | } | |
5511 | } | |
0a44bf69 | 5512 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5513 | { |
67c0d1eb | 5514 | int add_breg_early = 0; |
f5040a92 AO |
5515 | |
5516 | /* If this is a reference to an external, and there is no | |
5517 | constant, or local symbol (*), with or without a | |
5518 | constant, we want | |
5519 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5520 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5521 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5522 | ||
5523 | If we have a small constant, and this is a reference to | |
5524 | an external symbol, we want | |
5525 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5526 | addiu $tempreg,$tempreg,<constant> | |
5527 | ||
5528 | If we have a large constant, and this is a reference to | |
5529 | an external symbol, we want | |
5530 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5531 | lui $at,<hiconstant> | |
5532 | addiu $at,$at,<loconstant> | |
5533 | addu $tempreg,$tempreg,$at | |
5534 | ||
5535 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5536 | local symbols, even though it introduces an additional | |
5537 | instruction. */ | |
5538 | ||
f5040a92 AO |
5539 | if (offset_expr.X_add_number) |
5540 | { | |
4d7206a2 | 5541 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5542 | offset_expr.X_add_number = 0; |
5543 | ||
4d7206a2 | 5544 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5545 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5546 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5547 | |
5548 | if (expr1.X_add_number >= -0x8000 | |
5549 | && expr1.X_add_number < 0x8000) | |
5550 | { | |
67c0d1eb RS |
5551 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5552 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5553 | } |
ecd13cd3 | 5554 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5555 | { |
5556 | int dreg; | |
5557 | ||
5558 | /* If we are going to add in a base register, and the | |
5559 | target register and the base register are the same, | |
5560 | then we are using AT as a temporary register. Since | |
5561 | we want to load the constant into AT, we add our | |
5562 | current AT (from the global offset table) and the | |
5563 | register into the register now, and pretend we were | |
5564 | not using a base register. */ | |
5565 | if (breg != treg) | |
5566 | dreg = tempreg; | |
5567 | else | |
5568 | { | |
5569 | assert (tempreg == AT); | |
67c0d1eb RS |
5570 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5571 | treg, AT, breg); | |
f5040a92 | 5572 | dreg = treg; |
67c0d1eb | 5573 | add_breg_early = 1; |
f5040a92 AO |
5574 | } |
5575 | ||
f6a22291 | 5576 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5577 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5578 | dreg, dreg, AT); |
f5040a92 | 5579 | |
f5040a92 AO |
5580 | used_at = 1; |
5581 | } | |
5582 | else | |
5583 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5584 | ||
4d7206a2 | 5585 | relax_switch (); |
f5040a92 AO |
5586 | offset_expr.X_add_number = expr1.X_add_number; |
5587 | ||
67c0d1eb RS |
5588 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5589 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5590 | if (add_breg_early) | |
f5040a92 | 5591 | { |
67c0d1eb | 5592 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5593 | treg, tempreg, breg); |
f5040a92 AO |
5594 | breg = 0; |
5595 | tempreg = treg; | |
5596 | } | |
4d7206a2 | 5597 | relax_end (); |
f5040a92 | 5598 | } |
4d7206a2 | 5599 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5600 | { |
4d7206a2 | 5601 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5602 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5603 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5604 | relax_switch (); |
67c0d1eb RS |
5605 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5606 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5607 | relax_end (); |
f5040a92 | 5608 | } |
4d7206a2 | 5609 | else |
f5040a92 | 5610 | { |
67c0d1eb RS |
5611 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5612 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5613 | } |
5614 | } | |
0a44bf69 | 5615 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5616 | { |
67c0d1eb | 5617 | int gpdelay; |
9117d219 NC |
5618 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5619 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5620 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5621 | |
5622 | /* This is the large GOT case. If this is a reference to an | |
5623 | external symbol, and there is no constant, we want | |
5624 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5625 | addu $tempreg,$tempreg,$gp | |
5626 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5627 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5628 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5629 | addu $tempreg,$tempreg,$gp | |
5630 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5631 | For a local symbol, we want |
5632 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5633 | nop | |
5634 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5635 | ||
5636 | If we have a small constant, and this is a reference to | |
5637 | an external symbol, we want | |
5638 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5639 | addu $tempreg,$tempreg,$gp | |
5640 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5641 | nop | |
5642 | addiu $tempreg,$tempreg,<constant> | |
5643 | For a local symbol, we want | |
5644 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5645 | nop | |
5646 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5647 | ||
5648 | If we have a large constant, and this is a reference to | |
5649 | an external symbol, we want | |
5650 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5651 | addu $tempreg,$tempreg,$gp | |
5652 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5653 | lui $at,<hiconstant> | |
5654 | addiu $at,$at,<loconstant> | |
5655 | addu $tempreg,$tempreg,$at | |
5656 | For a local symbol, we want | |
5657 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5658 | lui $at,<hiconstant> | |
5659 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5660 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5661 | */ |
438c16b8 | 5662 | |
252b5132 RH |
5663 | expr1.X_add_number = offset_expr.X_add_number; |
5664 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5665 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5666 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5667 | if (expr1.X_add_number == 0 && breg == 0 |
5668 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5669 | { |
5670 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5671 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5672 | } | |
67c0d1eb RS |
5673 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5674 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5675 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5676 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5677 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5678 | if (expr1.X_add_number == 0) |
5679 | { | |
67c0d1eb | 5680 | if (breg != 0) |
252b5132 RH |
5681 | { |
5682 | /* We're going to put in an addu instruction using | |
5683 | tempreg, so we may as well insert the nop right | |
5684 | now. */ | |
269137b2 | 5685 | load_delay_nop (); |
252b5132 | 5686 | } |
252b5132 RH |
5687 | } |
5688 | else if (expr1.X_add_number >= -0x8000 | |
5689 | && expr1.X_add_number < 0x8000) | |
5690 | { | |
269137b2 | 5691 | load_delay_nop (); |
67c0d1eb | 5692 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5693 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5694 | } |
5695 | else | |
5696 | { | |
67c0d1eb | 5697 | int dreg; |
252b5132 RH |
5698 | |
5699 | /* If we are going to add in a base register, and the | |
5700 | target register and the base register are the same, | |
5701 | then we are using AT as a temporary register. Since | |
5702 | we want to load the constant into AT, we add our | |
5703 | current AT (from the global offset table) and the | |
5704 | register into the register now, and pretend we were | |
5705 | not using a base register. */ | |
5706 | if (breg != treg) | |
67c0d1eb | 5707 | dreg = tempreg; |
252b5132 RH |
5708 | else |
5709 | { | |
5710 | assert (tempreg == AT); | |
269137b2 | 5711 | load_delay_nop (); |
67c0d1eb | 5712 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5713 | treg, AT, breg); |
252b5132 | 5714 | dreg = treg; |
252b5132 RH |
5715 | } |
5716 | ||
f6a22291 | 5717 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5718 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5719 | |
252b5132 RH |
5720 | used_at = 1; |
5721 | } | |
4d7206a2 RS |
5722 | offset_expr.X_add_number = |
5723 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5724 | relax_switch (); | |
252b5132 | 5725 | |
67c0d1eb | 5726 | if (gpdelay) |
252b5132 RH |
5727 | { |
5728 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5729 | the first instruction on the main stream does not. */ |
67c0d1eb | 5730 | macro_build (NULL, "nop", ""); |
252b5132 | 5731 | } |
ed6fb7bd | 5732 | |
67c0d1eb RS |
5733 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5734 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5735 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5736 | && expr1.X_add_number < 0x8000) |
5737 | { | |
269137b2 | 5738 | load_delay_nop (); |
67c0d1eb RS |
5739 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5740 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5741 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5742 | register, the external symbol case ended with a load, |
5743 | so if the symbol turns out to not be external, and | |
5744 | the next instruction uses tempreg, an unnecessary nop | |
5745 | will be inserted. */ | |
252b5132 RH |
5746 | } |
5747 | else | |
5748 | { | |
5749 | if (breg == treg) | |
5750 | { | |
5751 | /* We must add in the base register now, as in the | |
f5040a92 | 5752 | external symbol case. */ |
252b5132 | 5753 | assert (tempreg == AT); |
269137b2 | 5754 | load_delay_nop (); |
67c0d1eb | 5755 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5756 | treg, AT, breg); |
252b5132 RH |
5757 | tempreg = treg; |
5758 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5759 | it in in both cases. */ |
252b5132 RH |
5760 | breg = 0; |
5761 | } | |
5762 | ||
67c0d1eb RS |
5763 | macro_build_lui (&expr1, AT); |
5764 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5765 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5766 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5767 | tempreg, tempreg, AT); |
8fc2e39e | 5768 | used_at = 1; |
252b5132 | 5769 | } |
4d7206a2 | 5770 | relax_end (); |
252b5132 | 5771 | } |
0a44bf69 | 5772 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5773 | { |
f5040a92 AO |
5774 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5775 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5776 | int add_breg_early = 0; |
f5040a92 AO |
5777 | |
5778 | /* This is the large GOT case. If this is a reference to an | |
5779 | external symbol, and there is no constant, we want | |
5780 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5781 | add $tempreg,$tempreg,$gp | |
5782 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5783 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5784 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5785 | add $tempreg,$tempreg,$gp | |
5786 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5787 | ||
5788 | If we have a small constant, and this is a reference to | |
5789 | an external symbol, we want | |
5790 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5791 | add $tempreg,$tempreg,$gp | |
5792 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5793 | addi $tempreg,$tempreg,<constant> | |
5794 | ||
5795 | If we have a large constant, and this is a reference to | |
5796 | an external symbol, we want | |
5797 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5798 | addu $tempreg,$tempreg,$gp | |
5799 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5800 | lui $at,<hiconstant> | |
5801 | addi $at,$at,<loconstant> | |
5802 | add $tempreg,$tempreg,$at | |
5803 | ||
5804 | If we have NewABI, and we know it's a local symbol, we want | |
5805 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5806 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5807 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5808 | ||
4d7206a2 | 5809 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5810 | |
4d7206a2 | 5811 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5812 | offset_expr.X_add_number = 0; |
5813 | ||
1abe91b1 MR |
5814 | if (expr1.X_add_number == 0 && breg == 0 |
5815 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5816 | { |
5817 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5818 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5819 | } | |
67c0d1eb RS |
5820 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5821 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5822 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5823 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5824 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5825 | |
5826 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5827 | ; |
f5040a92 AO |
5828 | else if (expr1.X_add_number >= -0x8000 |
5829 | && expr1.X_add_number < 0x8000) | |
5830 | { | |
67c0d1eb | 5831 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5832 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5833 | } |
ecd13cd3 | 5834 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5835 | { |
5836 | int dreg; | |
5837 | ||
5838 | /* If we are going to add in a base register, and the | |
5839 | target register and the base register are the same, | |
5840 | then we are using AT as a temporary register. Since | |
5841 | we want to load the constant into AT, we add our | |
5842 | current AT (from the global offset table) and the | |
5843 | register into the register now, and pretend we were | |
5844 | not using a base register. */ | |
5845 | if (breg != treg) | |
5846 | dreg = tempreg; | |
5847 | else | |
5848 | { | |
5849 | assert (tempreg == AT); | |
67c0d1eb | 5850 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5851 | treg, AT, breg); |
f5040a92 | 5852 | dreg = treg; |
67c0d1eb | 5853 | add_breg_early = 1; |
f5040a92 AO |
5854 | } |
5855 | ||
f6a22291 | 5856 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5857 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5858 | |
f5040a92 AO |
5859 | used_at = 1; |
5860 | } | |
5861 | else | |
5862 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5863 | ||
4d7206a2 | 5864 | relax_switch (); |
f5040a92 | 5865 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5866 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5867 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5868 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5869 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5870 | if (add_breg_early) | |
f5040a92 | 5871 | { |
67c0d1eb | 5872 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5873 | treg, tempreg, breg); |
f5040a92 AO |
5874 | breg = 0; |
5875 | tempreg = treg; | |
5876 | } | |
4d7206a2 | 5877 | relax_end (); |
f5040a92 | 5878 | } |
252b5132 RH |
5879 | else |
5880 | abort (); | |
5881 | ||
5882 | if (breg != 0) | |
aed1a261 | 5883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5884 | break; |
5885 | ||
5886 | case M_J_A: | |
5887 | /* The j instruction may not be used in PIC code, since it | |
5888 | requires an absolute address. We convert it to a b | |
5889 | instruction. */ | |
5890 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5891 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5892 | else |
67c0d1eb | 5893 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5894 | break; |
252b5132 RH |
5895 | |
5896 | /* The jal instructions must be handled as macros because when | |
5897 | generating PIC code they expand to multi-instruction | |
5898 | sequences. Normally they are simple instructions. */ | |
5899 | case M_JAL_1: | |
5900 | dreg = RA; | |
5901 | /* Fall through. */ | |
5902 | case M_JAL_2: | |
3e722fb5 | 5903 | if (mips_pic == NO_PIC) |
67c0d1eb | 5904 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5905 | else |
252b5132 RH |
5906 | { |
5907 | if (sreg != PIC_CALL_REG) | |
5908 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5909 | |
67c0d1eb | 5910 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5911 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5912 | { |
6478892d TS |
5913 | if (mips_cprestore_offset < 0) |
5914 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5915 | else | |
5916 | { | |
7a621144 DJ |
5917 | if (! mips_frame_reg_valid) |
5918 | { | |
5919 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5920 | /* Quiet this warning. */ | |
5921 | mips_frame_reg_valid = 1; | |
5922 | } | |
5923 | if (! mips_cprestore_valid) | |
5924 | { | |
5925 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5926 | /* Quiet this warning. */ | |
5927 | mips_cprestore_valid = 1; | |
5928 | } | |
6478892d | 5929 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5930 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5931 | mips_gp_register, |
256ab948 TS |
5932 | mips_frame_reg, |
5933 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5934 | } |
252b5132 RH |
5935 | } |
5936 | } | |
252b5132 | 5937 | |
8fc2e39e | 5938 | break; |
252b5132 RH |
5939 | |
5940 | case M_JAL_A: | |
5941 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5942 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5943 | else if (mips_pic == SVR4_PIC) |
5944 | { | |
5945 | /* If this is a reference to an external symbol, and we are | |
5946 | using a small GOT, we want | |
5947 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5948 | nop | |
f9419b05 | 5949 | jalr $ra,$25 |
252b5132 RH |
5950 | nop |
5951 | lw $gp,cprestore($sp) | |
5952 | The cprestore value is set using the .cprestore | |
5953 | pseudo-op. If we are using a big GOT, we want | |
5954 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5955 | addu $25,$25,$gp | |
5956 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5957 | nop | |
f9419b05 | 5958 | jalr $ra,$25 |
252b5132 RH |
5959 | nop |
5960 | lw $gp,cprestore($sp) | |
5961 | If the symbol is not external, we want | |
5962 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5963 | nop | |
5964 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5965 | jalr $ra,$25 |
252b5132 | 5966 | nop |
438c16b8 | 5967 | lw $gp,cprestore($sp) |
f5040a92 AO |
5968 | |
5969 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5970 | sequences above, minus nops, unless the symbol is local, | |
5971 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5972 | GOT_DISP. */ | |
438c16b8 | 5973 | if (HAVE_NEWABI) |
252b5132 | 5974 | { |
f5040a92 AO |
5975 | if (! mips_big_got) |
5976 | { | |
4d7206a2 | 5977 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5978 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5979 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5980 | mips_gp_register); |
4d7206a2 | 5981 | relax_switch (); |
67c0d1eb RS |
5982 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5983 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5984 | mips_gp_register); |
5985 | relax_end (); | |
f5040a92 AO |
5986 | } |
5987 | else | |
5988 | { | |
4d7206a2 | 5989 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5990 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5991 | BFD_RELOC_MIPS_CALL_HI16); | |
5992 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5993 | PIC_CALL_REG, mips_gp_register); | |
5994 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5995 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5996 | PIC_CALL_REG); | |
4d7206a2 | 5997 | relax_switch (); |
67c0d1eb RS |
5998 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5999 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6000 | mips_gp_register); | |
6001 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6002 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6003 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6004 | relax_end (); |
f5040a92 | 6005 | } |
684022ea | 6006 | |
67c0d1eb | 6007 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6008 | } |
6009 | else | |
6010 | { | |
4d7206a2 | 6011 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6012 | if (! mips_big_got) |
6013 | { | |
67c0d1eb RS |
6014 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6015 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6016 | mips_gp_register); |
269137b2 | 6017 | load_delay_nop (); |
4d7206a2 | 6018 | relax_switch (); |
438c16b8 | 6019 | } |
252b5132 | 6020 | else |
252b5132 | 6021 | { |
67c0d1eb RS |
6022 | int gpdelay; |
6023 | ||
6024 | gpdelay = reg_needs_delay (mips_gp_register); | |
6025 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6026 | BFD_RELOC_MIPS_CALL_HI16); | |
6027 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6028 | PIC_CALL_REG, mips_gp_register); | |
6029 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6030 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6031 | PIC_CALL_REG); | |
269137b2 | 6032 | load_delay_nop (); |
4d7206a2 | 6033 | relax_switch (); |
67c0d1eb RS |
6034 | if (gpdelay) |
6035 | macro_build (NULL, "nop", ""); | |
252b5132 | 6036 | } |
67c0d1eb RS |
6037 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6038 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6039 | mips_gp_register); |
269137b2 | 6040 | load_delay_nop (); |
67c0d1eb RS |
6041 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6042 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6043 | relax_end (); |
67c0d1eb | 6044 | macro_build_jalr (&offset_expr); |
438c16b8 | 6045 | |
6478892d TS |
6046 | if (mips_cprestore_offset < 0) |
6047 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6048 | else | |
6049 | { | |
7a621144 DJ |
6050 | if (! mips_frame_reg_valid) |
6051 | { | |
6052 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6053 | /* Quiet this warning. */ | |
6054 | mips_frame_reg_valid = 1; | |
6055 | } | |
6056 | if (! mips_cprestore_valid) | |
6057 | { | |
6058 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6059 | /* Quiet this warning. */ | |
6060 | mips_cprestore_valid = 1; | |
6061 | } | |
6478892d | 6062 | if (mips_opts.noreorder) |
67c0d1eb | 6063 | macro_build (NULL, "nop", ""); |
6478892d | 6064 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6065 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6066 | mips_gp_register, |
256ab948 TS |
6067 | mips_frame_reg, |
6068 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6069 | } |
252b5132 RH |
6070 | } |
6071 | } | |
0a44bf69 RS |
6072 | else if (mips_pic == VXWORKS_PIC) |
6073 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6074 | else |
6075 | abort (); | |
6076 | ||
8fc2e39e | 6077 | break; |
252b5132 RH |
6078 | |
6079 | case M_LB_AB: | |
6080 | s = "lb"; | |
6081 | goto ld; | |
6082 | case M_LBU_AB: | |
6083 | s = "lbu"; | |
6084 | goto ld; | |
6085 | case M_LH_AB: | |
6086 | s = "lh"; | |
6087 | goto ld; | |
6088 | case M_LHU_AB: | |
6089 | s = "lhu"; | |
6090 | goto ld; | |
6091 | case M_LW_AB: | |
6092 | s = "lw"; | |
6093 | goto ld; | |
6094 | case M_LWC0_AB: | |
6095 | s = "lwc0"; | |
bdaaa2e1 | 6096 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6097 | coproc = 1; |
6098 | goto ld; | |
6099 | case M_LWC1_AB: | |
6100 | s = "lwc1"; | |
bdaaa2e1 | 6101 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6102 | coproc = 1; |
6103 | goto ld; | |
6104 | case M_LWC2_AB: | |
6105 | s = "lwc2"; | |
bdaaa2e1 | 6106 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6107 | coproc = 1; |
6108 | goto ld; | |
6109 | case M_LWC3_AB: | |
6110 | s = "lwc3"; | |
bdaaa2e1 | 6111 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6112 | coproc = 1; |
6113 | goto ld; | |
6114 | case M_LWL_AB: | |
6115 | s = "lwl"; | |
6116 | lr = 1; | |
6117 | goto ld; | |
6118 | case M_LWR_AB: | |
6119 | s = "lwr"; | |
6120 | lr = 1; | |
6121 | goto ld; | |
6122 | case M_LDC1_AB: | |
fef14a42 | 6123 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6124 | { |
6125 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6126 | break; |
252b5132 RH |
6127 | } |
6128 | s = "ldc1"; | |
bdaaa2e1 | 6129 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6130 | coproc = 1; |
6131 | goto ld; | |
6132 | case M_LDC2_AB: | |
6133 | s = "ldc2"; | |
bdaaa2e1 | 6134 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6135 | coproc = 1; |
6136 | goto ld; | |
6137 | case M_LDC3_AB: | |
6138 | s = "ldc3"; | |
bdaaa2e1 | 6139 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6140 | coproc = 1; |
6141 | goto ld; | |
6142 | case M_LDL_AB: | |
6143 | s = "ldl"; | |
6144 | lr = 1; | |
6145 | goto ld; | |
6146 | case M_LDR_AB: | |
6147 | s = "ldr"; | |
6148 | lr = 1; | |
6149 | goto ld; | |
6150 | case M_LL_AB: | |
6151 | s = "ll"; | |
6152 | goto ld; | |
6153 | case M_LLD_AB: | |
6154 | s = "lld"; | |
6155 | goto ld; | |
6156 | case M_LWU_AB: | |
6157 | s = "lwu"; | |
6158 | ld: | |
8fc2e39e | 6159 | if (breg == treg || coproc || lr) |
252b5132 RH |
6160 | { |
6161 | tempreg = AT; | |
6162 | used_at = 1; | |
6163 | } | |
6164 | else | |
6165 | { | |
6166 | tempreg = treg; | |
252b5132 RH |
6167 | } |
6168 | goto ld_st; | |
6169 | case M_SB_AB: | |
6170 | s = "sb"; | |
6171 | goto st; | |
6172 | case M_SH_AB: | |
6173 | s = "sh"; | |
6174 | goto st; | |
6175 | case M_SW_AB: | |
6176 | s = "sw"; | |
6177 | goto st; | |
6178 | case M_SWC0_AB: | |
6179 | s = "swc0"; | |
bdaaa2e1 | 6180 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6181 | coproc = 1; |
6182 | goto st; | |
6183 | case M_SWC1_AB: | |
6184 | s = "swc1"; | |
bdaaa2e1 | 6185 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6186 | coproc = 1; |
6187 | goto st; | |
6188 | case M_SWC2_AB: | |
6189 | s = "swc2"; | |
bdaaa2e1 | 6190 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6191 | coproc = 1; |
6192 | goto st; | |
6193 | case M_SWC3_AB: | |
6194 | s = "swc3"; | |
bdaaa2e1 | 6195 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6196 | coproc = 1; |
6197 | goto st; | |
6198 | case M_SWL_AB: | |
6199 | s = "swl"; | |
6200 | goto st; | |
6201 | case M_SWR_AB: | |
6202 | s = "swr"; | |
6203 | goto st; | |
6204 | case M_SC_AB: | |
6205 | s = "sc"; | |
6206 | goto st; | |
6207 | case M_SCD_AB: | |
6208 | s = "scd"; | |
6209 | goto st; | |
d43b4baf TS |
6210 | case M_CACHE_AB: |
6211 | s = "cache"; | |
6212 | goto st; | |
252b5132 | 6213 | case M_SDC1_AB: |
fef14a42 | 6214 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6215 | { |
6216 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6217 | break; |
252b5132 RH |
6218 | } |
6219 | s = "sdc1"; | |
6220 | coproc = 1; | |
bdaaa2e1 | 6221 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6222 | goto st; |
6223 | case M_SDC2_AB: | |
6224 | s = "sdc2"; | |
bdaaa2e1 | 6225 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6226 | coproc = 1; |
6227 | goto st; | |
6228 | case M_SDC3_AB: | |
6229 | s = "sdc3"; | |
bdaaa2e1 | 6230 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6231 | coproc = 1; |
6232 | goto st; | |
6233 | case M_SDL_AB: | |
6234 | s = "sdl"; | |
6235 | goto st; | |
6236 | case M_SDR_AB: | |
6237 | s = "sdr"; | |
6238 | st: | |
8fc2e39e TS |
6239 | tempreg = AT; |
6240 | used_at = 1; | |
252b5132 | 6241 | ld_st: |
bdaaa2e1 | 6242 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6243 | if (mask == M_LWC1_AB |
6244 | || mask == M_SWC1_AB | |
6245 | || mask == M_LDC1_AB | |
6246 | || mask == M_SDC1_AB | |
6247 | || mask == M_L_DAB | |
6248 | || mask == M_S_DAB) | |
6249 | fmt = "T,o(b)"; | |
d43b4baf TS |
6250 | else if (mask == M_CACHE_AB) |
6251 | fmt = "k,o(b)"; | |
252b5132 RH |
6252 | else if (coproc) |
6253 | fmt = "E,o(b)"; | |
6254 | else | |
6255 | fmt = "t,o(b)"; | |
6256 | ||
6257 | if (offset_expr.X_op != O_constant | |
6258 | && offset_expr.X_op != O_symbol) | |
6259 | { | |
6260 | as_bad (_("expression too complex")); | |
6261 | offset_expr.X_op = O_constant; | |
6262 | } | |
6263 | ||
2051e8c4 MR |
6264 | if (HAVE_32BIT_ADDRESSES |
6265 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6266 | { |
6267 | char value [32]; | |
6268 | ||
6269 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6270 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6271 | } |
2051e8c4 | 6272 | |
252b5132 RH |
6273 | /* A constant expression in PIC code can be handled just as it |
6274 | is in non PIC code. */ | |
aed1a261 RS |
6275 | if (offset_expr.X_op == O_constant) |
6276 | { | |
aed1a261 RS |
6277 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6278 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6279 | normalize_address_expr (&expr1); |
aed1a261 RS |
6280 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6281 | if (breg != 0) | |
6282 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6283 | tempreg, tempreg, breg); | |
6284 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6285 | } | |
6286 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6287 | { |
6288 | /* If this is a reference to a GP relative symbol, and there | |
6289 | is no base register, we want | |
cdf6fd85 | 6290 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6291 | Otherwise, if there is no base register, we want |
6292 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6293 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6294 | If we have a constant, we need two instructions anyhow, | |
6295 | so we always use the latter form. | |
6296 | ||
6297 | If we have a base register, and this is a reference to a | |
6298 | GP relative symbol, we want | |
6299 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6300 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6301 | Otherwise we want |
6302 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6303 | addu $tempreg,$tempreg,$breg | |
6304 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6305 | With a constant we always use the latter case. |
76b3015f | 6306 | |
d6bc6245 TS |
6307 | With 64bit address space and no base register and $at usable, |
6308 | we want | |
6309 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6310 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6311 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6312 | dsll32 $tempreg,0 | |
6313 | daddu $tempreg,$at | |
6314 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6315 | If we have a base register, we want | |
6316 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6317 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6318 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6319 | daddu $at,$breg | |
6320 | dsll32 $tempreg,0 | |
6321 | daddu $tempreg,$at | |
6322 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6323 | ||
6324 | Without $at we can't generate the optimal path for superscalar | |
6325 | processors here since this would require two temporary registers. | |
6326 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6327 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6328 | dsll $tempreg,16 | |
6329 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6330 | dsll $tempreg,16 | |
6331 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6332 | If we have a base register, we want | |
6333 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6334 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6335 | dsll $tempreg,16 | |
6336 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6337 | dsll $tempreg,16 | |
6338 | daddu $tempreg,$tempreg,$breg | |
6339 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6340 | |
6caf9ef4 | 6341 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6342 | the same sequence as in 32bit address space. */ |
6343 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6344 | { |
aed1a261 | 6345 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6346 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6347 | { | |
6348 | relax_start (offset_expr.X_add_symbol); | |
6349 | if (breg == 0) | |
6350 | { | |
6351 | macro_build (&offset_expr, s, fmt, treg, | |
6352 | BFD_RELOC_GPREL16, mips_gp_register); | |
6353 | } | |
6354 | else | |
6355 | { | |
6356 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6357 | tempreg, breg, mips_gp_register); | |
6358 | macro_build (&offset_expr, s, fmt, treg, | |
6359 | BFD_RELOC_GPREL16, tempreg); | |
6360 | } | |
6361 | relax_switch (); | |
6362 | } | |
d6bc6245 | 6363 | |
741fe287 | 6364 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6365 | { |
67c0d1eb RS |
6366 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6367 | BFD_RELOC_MIPS_HIGHEST); | |
6368 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6369 | BFD_RELOC_HI16_S); | |
6370 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6371 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6372 | if (breg != 0) |
67c0d1eb RS |
6373 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6374 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6375 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6376 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6377 | tempreg); | |
d6bc6245 TS |
6378 | used_at = 1; |
6379 | } | |
6380 | else | |
6381 | { | |
67c0d1eb RS |
6382 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6383 | BFD_RELOC_MIPS_HIGHEST); | |
6384 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6385 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6386 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6387 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6388 | tempreg, BFD_RELOC_HI16_S); | |
6389 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6390 | if (breg != 0) |
67c0d1eb | 6391 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6392 | tempreg, tempreg, breg); |
67c0d1eb | 6393 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6394 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6395 | } |
6caf9ef4 TS |
6396 | |
6397 | if (mips_relax.sequence) | |
6398 | relax_end (); | |
8fc2e39e | 6399 | break; |
d6bc6245 | 6400 | } |
256ab948 | 6401 | |
252b5132 RH |
6402 | if (breg == 0) |
6403 | { | |
67c0d1eb | 6404 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6405 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6406 | { |
4d7206a2 | 6407 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6408 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6409 | mips_gp_register); | |
4d7206a2 | 6410 | relax_switch (); |
252b5132 | 6411 | } |
67c0d1eb RS |
6412 | macro_build_lui (&offset_expr, tempreg); |
6413 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6414 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6415 | if (mips_relax.sequence) |
6416 | relax_end (); | |
252b5132 RH |
6417 | } |
6418 | else | |
6419 | { | |
67c0d1eb | 6420 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6421 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6422 | { |
4d7206a2 | 6423 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6425 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6426 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6427 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6428 | relax_switch (); |
252b5132 | 6429 | } |
67c0d1eb RS |
6430 | macro_build_lui (&offset_expr, tempreg); |
6431 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6432 | tempreg, tempreg, breg); |
67c0d1eb | 6433 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6434 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6435 | if (mips_relax.sequence) |
6436 | relax_end (); | |
252b5132 RH |
6437 | } |
6438 | } | |
0a44bf69 | 6439 | else if (!mips_big_got) |
252b5132 | 6440 | { |
ed6fb7bd | 6441 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6442 | |
252b5132 RH |
6443 | /* If this is a reference to an external symbol, we want |
6444 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6445 | nop | |
6446 | <op> $treg,0($tempreg) | |
6447 | Otherwise we want | |
6448 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6449 | nop | |
6450 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6451 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6452 | |
6453 | For NewABI, we want | |
6454 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6455 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6456 | ||
252b5132 RH |
6457 | If there is a base register, we add it to $tempreg before |
6458 | the <op>. If there is a constant, we stick it in the | |
6459 | <op> instruction. We don't handle constants larger than | |
6460 | 16 bits, because we have no way to load the upper 16 bits | |
6461 | (actually, we could handle them for the subset of cases | |
6462 | in which we are not using $at). */ | |
6463 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6464 | if (HAVE_NEWABI) |
6465 | { | |
67c0d1eb RS |
6466 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6467 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6468 | if (breg != 0) |
67c0d1eb | 6469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6470 | tempreg, tempreg, breg); |
67c0d1eb | 6471 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6472 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6473 | break; |
6474 | } | |
252b5132 RH |
6475 | expr1.X_add_number = offset_expr.X_add_number; |
6476 | offset_expr.X_add_number = 0; | |
6477 | if (expr1.X_add_number < -0x8000 | |
6478 | || expr1.X_add_number >= 0x8000) | |
6479 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6480 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6481 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6482 | load_delay_nop (); |
4d7206a2 RS |
6483 | relax_start (offset_expr.X_add_symbol); |
6484 | relax_switch (); | |
67c0d1eb RS |
6485 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6486 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6487 | relax_end (); |
252b5132 | 6488 | if (breg != 0) |
67c0d1eb | 6489 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6490 | tempreg, tempreg, breg); |
67c0d1eb | 6491 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6492 | } |
0a44bf69 | 6493 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6494 | { |
67c0d1eb | 6495 | int gpdelay; |
252b5132 RH |
6496 | |
6497 | /* If this is a reference to an external symbol, we want | |
6498 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6499 | addu $tempreg,$tempreg,$gp | |
6500 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6501 | <op> $treg,0($tempreg) | |
6502 | Otherwise we want | |
6503 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6504 | nop | |
6505 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6506 | <op> $treg,0($tempreg) | |
6507 | If there is a base register, we add it to $tempreg before | |
6508 | the <op>. If there is a constant, we stick it in the | |
6509 | <op> instruction. We don't handle constants larger than | |
6510 | 16 bits, because we have no way to load the upper 16 bits | |
6511 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6512 | in which we are not using $at). */ |
252b5132 RH |
6513 | assert (offset_expr.X_op == O_symbol); |
6514 | expr1.X_add_number = offset_expr.X_add_number; | |
6515 | offset_expr.X_add_number = 0; | |
6516 | if (expr1.X_add_number < -0x8000 | |
6517 | || expr1.X_add_number >= 0x8000) | |
6518 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6519 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6520 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6521 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6522 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6523 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6524 | mips_gp_register); | |
6525 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6526 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6527 | relax_switch (); |
67c0d1eb RS |
6528 | if (gpdelay) |
6529 | macro_build (NULL, "nop", ""); | |
6530 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6531 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6532 | load_delay_nop (); |
67c0d1eb RS |
6533 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6534 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6535 | relax_end (); |
6536 | ||
252b5132 | 6537 | if (breg != 0) |
67c0d1eb | 6538 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6539 | tempreg, tempreg, breg); |
67c0d1eb | 6540 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6541 | } |
0a44bf69 | 6542 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6543 | { |
f5040a92 AO |
6544 | /* If this is a reference to an external symbol, we want |
6545 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6546 | add $tempreg,$tempreg,$gp | |
6547 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6548 | <op> $treg,<ofst>($tempreg) | |
6549 | Otherwise, for local symbols, we want: | |
6550 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6551 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6552 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6553 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6554 | offset_expr.X_add_number = 0; |
6555 | if (expr1.X_add_number < -0x8000 | |
6556 | || expr1.X_add_number >= 0x8000) | |
6557 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6558 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6559 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6560 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6561 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6562 | mips_gp_register); | |
6563 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6564 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6565 | if (breg != 0) |
67c0d1eb | 6566 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6567 | tempreg, tempreg, breg); |
67c0d1eb | 6568 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6569 | |
4d7206a2 | 6570 | relax_switch (); |
f5040a92 | 6571 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6572 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6573 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6574 | if (breg != 0) |
67c0d1eb | 6575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6576 | tempreg, tempreg, breg); |
67c0d1eb | 6577 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6578 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6579 | relax_end (); |
f5040a92 | 6580 | } |
252b5132 RH |
6581 | else |
6582 | abort (); | |
6583 | ||
252b5132 RH |
6584 | break; |
6585 | ||
6586 | case M_LI: | |
6587 | case M_LI_S: | |
67c0d1eb | 6588 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6589 | break; |
252b5132 RH |
6590 | |
6591 | case M_DLI: | |
67c0d1eb | 6592 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6593 | break; |
252b5132 RH |
6594 | |
6595 | case M_LI_SS: | |
6596 | if (imm_expr.X_op == O_constant) | |
6597 | { | |
8fc2e39e | 6598 | used_at = 1; |
67c0d1eb RS |
6599 | load_register (AT, &imm_expr, 0); |
6600 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6601 | break; |
6602 | } | |
6603 | else | |
6604 | { | |
6605 | assert (offset_expr.X_op == O_symbol | |
6606 | && strcmp (segment_name (S_GET_SEGMENT | |
6607 | (offset_expr.X_add_symbol)), | |
6608 | ".lit4") == 0 | |
6609 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6610 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6611 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6612 | break; |
252b5132 RH |
6613 | } |
6614 | ||
6615 | case M_LI_D: | |
ca4e0257 RS |
6616 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6617 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6618 | order 32 bits of the value and the low order 32 bits are either | |
6619 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6620 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6621 | { | |
ca4e0257 | 6622 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6623 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6624 | else |
6625 | { | |
6626 | int hreg, lreg; | |
6627 | ||
6628 | if (target_big_endian) | |
6629 | { | |
6630 | hreg = treg; | |
6631 | lreg = treg + 1; | |
6632 | } | |
6633 | else | |
6634 | { | |
6635 | hreg = treg + 1; | |
6636 | lreg = treg; | |
6637 | } | |
6638 | ||
6639 | if (hreg <= 31) | |
67c0d1eb | 6640 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6641 | if (lreg <= 31) |
6642 | { | |
6643 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6644 | move_register (lreg, 0); |
252b5132 RH |
6645 | else |
6646 | { | |
6647 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6648 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6649 | } |
6650 | } | |
6651 | } | |
8fc2e39e | 6652 | break; |
252b5132 RH |
6653 | } |
6654 | ||
6655 | /* We know that sym is in the .rdata section. First we get the | |
6656 | upper 16 bits of the address. */ | |
6657 | if (mips_pic == NO_PIC) | |
6658 | { | |
67c0d1eb | 6659 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6660 | used_at = 1; |
252b5132 | 6661 | } |
0a44bf69 | 6662 | else |
252b5132 | 6663 | { |
67c0d1eb RS |
6664 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6665 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6666 | used_at = 1; |
252b5132 | 6667 | } |
bdaaa2e1 | 6668 | |
252b5132 | 6669 | /* Now we load the register(s). */ |
ca4e0257 | 6670 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6671 | { |
6672 | used_at = 1; | |
6673 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6674 | } | |
252b5132 RH |
6675 | else |
6676 | { | |
8fc2e39e | 6677 | used_at = 1; |
67c0d1eb | 6678 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6679 | if (treg != RA) |
252b5132 RH |
6680 | { |
6681 | /* FIXME: How in the world do we deal with the possible | |
6682 | overflow here? */ | |
6683 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6684 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6685 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6686 | } |
6687 | } | |
252b5132 RH |
6688 | break; |
6689 | ||
6690 | case M_LI_DD: | |
ca4e0257 RS |
6691 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6692 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6693 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6694 | the value and the low order 32 bits are either zero or in | |
6695 | OFFSET_EXPR. */ | |
252b5132 RH |
6696 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6697 | { | |
8fc2e39e | 6698 | used_at = 1; |
67c0d1eb | 6699 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6700 | if (HAVE_64BIT_FPRS) |
6701 | { | |
6702 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6703 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6704 | } |
252b5132 RH |
6705 | else |
6706 | { | |
67c0d1eb | 6707 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6708 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6709 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6710 | else |
6711 | { | |
6712 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6713 | load_register (AT, &offset_expr, 0); |
6714 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6715 | } |
6716 | } | |
6717 | break; | |
6718 | } | |
6719 | ||
6720 | assert (offset_expr.X_op == O_symbol | |
6721 | && offset_expr.X_add_number == 0); | |
6722 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6723 | if (strcmp (s, ".lit8") == 0) | |
6724 | { | |
e7af610e | 6725 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6726 | { |
67c0d1eb | 6727 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6728 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6729 | break; |
252b5132 | 6730 | } |
c9914766 | 6731 | breg = mips_gp_register; |
252b5132 RH |
6732 | r = BFD_RELOC_MIPS_LITERAL; |
6733 | goto dob; | |
6734 | } | |
6735 | else | |
6736 | { | |
6737 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6738 | used_at = 1; |
0a44bf69 | 6739 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6740 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6741 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6742 | else |
6743 | { | |
6744 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6745 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6746 | } |
bdaaa2e1 | 6747 | |
e7af610e | 6748 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6749 | { |
67c0d1eb RS |
6750 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6751 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6752 | break; |
6753 | } | |
6754 | breg = AT; | |
6755 | r = BFD_RELOC_LO16; | |
6756 | goto dob; | |
6757 | } | |
6758 | ||
6759 | case M_L_DOB: | |
fef14a42 | 6760 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6761 | { |
6762 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6763 | break; |
252b5132 RH |
6764 | } |
6765 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6766 | to adjust when loading from memory. */ | |
6767 | r = BFD_RELOC_LO16; | |
6768 | dob: | |
e7af610e | 6769 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6770 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6771 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6772 | /* FIXME: A possible overflow which I don't know how to deal |
6773 | with. */ | |
6774 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6775 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6776 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6777 | break; |
6778 | ||
6779 | case M_L_DAB: | |
6780 | /* | |
6781 | * The MIPS assembler seems to check for X_add_number not | |
6782 | * being double aligned and generating: | |
6783 | * lui at,%hi(foo+1) | |
6784 | * addu at,at,v1 | |
6785 | * addiu at,at,%lo(foo+1) | |
6786 | * lwc1 f2,0(at) | |
6787 | * lwc1 f3,4(at) | |
6788 | * But, the resulting address is the same after relocation so why | |
6789 | * generate the extra instruction? | |
6790 | */ | |
fef14a42 | 6791 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6792 | { |
6793 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6794 | break; |
252b5132 | 6795 | } |
bdaaa2e1 | 6796 | /* Itbl support may require additional care here. */ |
252b5132 | 6797 | coproc = 1; |
e7af610e | 6798 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6799 | { |
6800 | s = "ldc1"; | |
6801 | goto ld; | |
6802 | } | |
6803 | ||
6804 | s = "lwc1"; | |
6805 | fmt = "T,o(b)"; | |
6806 | goto ldd_std; | |
6807 | ||
6808 | case M_S_DAB: | |
fef14a42 | 6809 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6810 | { |
6811 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6812 | break; |
252b5132 RH |
6813 | } |
6814 | ||
e7af610e | 6815 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6816 | { |
6817 | s = "sdc1"; | |
6818 | goto st; | |
6819 | } | |
6820 | ||
6821 | s = "swc1"; | |
6822 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6823 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6824 | coproc = 1; |
6825 | goto ldd_std; | |
6826 | ||
6827 | case M_LD_AB: | |
ca4e0257 | 6828 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6829 | { |
6830 | s = "ld"; | |
6831 | goto ld; | |
6832 | } | |
6833 | ||
6834 | s = "lw"; | |
6835 | fmt = "t,o(b)"; | |
6836 | goto ldd_std; | |
6837 | ||
6838 | case M_SD_AB: | |
ca4e0257 | 6839 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6840 | { |
6841 | s = "sd"; | |
6842 | goto st; | |
6843 | } | |
6844 | ||
6845 | s = "sw"; | |
6846 | fmt = "t,o(b)"; | |
6847 | ||
6848 | ldd_std: | |
6849 | if (offset_expr.X_op != O_symbol | |
6850 | && offset_expr.X_op != O_constant) | |
6851 | { | |
6852 | as_bad (_("expression too complex")); | |
6853 | offset_expr.X_op = O_constant; | |
6854 | } | |
6855 | ||
2051e8c4 MR |
6856 | if (HAVE_32BIT_ADDRESSES |
6857 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6858 | { |
6859 | char value [32]; | |
6860 | ||
6861 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6862 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6863 | } |
2051e8c4 | 6864 | |
252b5132 RH |
6865 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6866 | to adjust when loading from memory. We set coproc if we must | |
6867 | load $fn+1 first. */ | |
bdaaa2e1 | 6868 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6869 | if (! target_big_endian) |
6870 | coproc = 0; | |
6871 | ||
6872 | if (mips_pic == NO_PIC | |
6873 | || offset_expr.X_op == O_constant) | |
6874 | { | |
6875 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6876 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6877 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6878 | If we have a base register, we use this |
6879 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6880 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6881 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6882 | If this is not a GP relative symbol, we want |
6883 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6884 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6885 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6886 | If there is a base register, we add it to $at after the | |
6887 | lui instruction. If there is a constant, we always use | |
6888 | the last case. */ | |
39a59cf8 MR |
6889 | if (offset_expr.X_op == O_symbol |
6890 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6891 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6892 | { |
4d7206a2 | 6893 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6894 | if (breg == 0) |
6895 | { | |
c9914766 | 6896 | tempreg = mips_gp_register; |
252b5132 RH |
6897 | } |
6898 | else | |
6899 | { | |
67c0d1eb | 6900 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6901 | AT, breg, mips_gp_register); |
252b5132 | 6902 | tempreg = AT; |
252b5132 RH |
6903 | used_at = 1; |
6904 | } | |
6905 | ||
beae10d5 | 6906 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6907 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6908 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6909 | offset_expr.X_add_number += 4; |
6910 | ||
6911 | /* Set mips_optimize to 2 to avoid inserting an | |
6912 | undesired nop. */ | |
6913 | hold_mips_optimize = mips_optimize; | |
6914 | mips_optimize = 2; | |
beae10d5 | 6915 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6916 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6917 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6918 | mips_optimize = hold_mips_optimize; |
6919 | ||
4d7206a2 | 6920 | relax_switch (); |
252b5132 RH |
6921 | |
6922 | /* We just generated two relocs. When tc_gen_reloc | |
6923 | handles this case, it will skip the first reloc and | |
6924 | handle the second. The second reloc already has an | |
6925 | extra addend of 4, which we added above. We must | |
6926 | subtract it out, and then subtract another 4 to make | |
6927 | the first reloc come out right. The second reloc | |
6928 | will come out right because we are going to add 4 to | |
6929 | offset_expr when we build its instruction below. | |
6930 | ||
6931 | If we have a symbol, then we don't want to include | |
6932 | the offset, because it will wind up being included | |
6933 | when we generate the reloc. */ | |
6934 | ||
6935 | if (offset_expr.X_op == O_constant) | |
6936 | offset_expr.X_add_number -= 8; | |
6937 | else | |
6938 | { | |
6939 | offset_expr.X_add_number = -4; | |
6940 | offset_expr.X_op = O_constant; | |
6941 | } | |
6942 | } | |
8fc2e39e | 6943 | used_at = 1; |
67c0d1eb | 6944 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6945 | if (breg != 0) |
67c0d1eb | 6946 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6947 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6948 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6949 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6950 | /* FIXME: How do we handle overflow here? */ |
6951 | offset_expr.X_add_number += 4; | |
beae10d5 | 6952 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6953 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6954 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6955 | if (mips_relax.sequence) |
6956 | relax_end (); | |
bdaaa2e1 | 6957 | } |
0a44bf69 | 6958 | else if (!mips_big_got) |
252b5132 | 6959 | { |
252b5132 RH |
6960 | /* If this is a reference to an external symbol, we want |
6961 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6962 | nop | |
6963 | <op> $treg,0($at) | |
6964 | <op> $treg+1,4($at) | |
6965 | Otherwise we want | |
6966 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6967 | nop | |
6968 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6969 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6970 | If there is a base register we add it to $at before the | |
6971 | lwc1 instructions. If there is a constant we include it | |
6972 | in the lwc1 instructions. */ | |
6973 | used_at = 1; | |
6974 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6975 | if (expr1.X_add_number < -0x8000 |
6976 | || expr1.X_add_number >= 0x8000 - 4) | |
6977 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6978 | load_got_offset (AT, &offset_expr); |
269137b2 | 6979 | load_delay_nop (); |
252b5132 | 6980 | if (breg != 0) |
67c0d1eb | 6981 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6982 | |
6983 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6984 | nop. */ | |
6985 | hold_mips_optimize = mips_optimize; | |
6986 | mips_optimize = 2; | |
4d7206a2 | 6987 | |
beae10d5 | 6988 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6989 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6990 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6991 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6992 | expr1.X_add_number += 4; |
67c0d1eb RS |
6993 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6994 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6995 | relax_switch (); |
67c0d1eb RS |
6996 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6997 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6998 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6999 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7000 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7001 | relax_end (); |
252b5132 | 7002 | |
4d7206a2 | 7003 | mips_optimize = hold_mips_optimize; |
252b5132 | 7004 | } |
0a44bf69 | 7005 | else if (mips_big_got) |
252b5132 | 7006 | { |
67c0d1eb | 7007 | int gpdelay; |
252b5132 RH |
7008 | |
7009 | /* If this is a reference to an external symbol, we want | |
7010 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7011 | addu $at,$at,$gp | |
7012 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7013 | nop | |
7014 | <op> $treg,0($at) | |
7015 | <op> $treg+1,4($at) | |
7016 | Otherwise we want | |
7017 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7018 | nop | |
7019 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7020 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7021 | If there is a base register we add it to $at before the | |
7022 | lwc1 instructions. If there is a constant we include it | |
7023 | in the lwc1 instructions. */ | |
7024 | used_at = 1; | |
7025 | expr1.X_add_number = offset_expr.X_add_number; | |
7026 | offset_expr.X_add_number = 0; | |
7027 | if (expr1.X_add_number < -0x8000 | |
7028 | || expr1.X_add_number >= 0x8000 - 4) | |
7029 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7030 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7031 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7032 | macro_build (&offset_expr, "lui", "t,u", |
7033 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7034 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7035 | AT, AT, mips_gp_register); |
67c0d1eb | 7036 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7037 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7038 | load_delay_nop (); |
252b5132 | 7039 | if (breg != 0) |
67c0d1eb | 7040 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7041 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7042 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7043 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7044 | expr1.X_add_number += 4; |
7045 | ||
7046 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7047 | nop. */ | |
7048 | hold_mips_optimize = mips_optimize; | |
7049 | mips_optimize = 2; | |
beae10d5 | 7050 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7051 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7052 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7053 | mips_optimize = hold_mips_optimize; |
7054 | expr1.X_add_number -= 4; | |
7055 | ||
4d7206a2 RS |
7056 | relax_switch (); |
7057 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7058 | if (gpdelay) |
7059 | macro_build (NULL, "nop", ""); | |
7060 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7061 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7062 | load_delay_nop (); |
252b5132 | 7063 | if (breg != 0) |
67c0d1eb | 7064 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7065 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7066 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7067 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7068 | offset_expr.X_add_number += 4; |
252b5132 RH |
7069 | |
7070 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7071 | nop. */ | |
7072 | hold_mips_optimize = mips_optimize; | |
7073 | mips_optimize = 2; | |
beae10d5 | 7074 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7075 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7076 | BFD_RELOC_LO16, AT); | |
252b5132 | 7077 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7078 | relax_end (); |
252b5132 | 7079 | } |
252b5132 RH |
7080 | else |
7081 | abort (); | |
7082 | ||
252b5132 RH |
7083 | break; |
7084 | ||
7085 | case M_LD_OB: | |
7086 | s = "lw"; | |
7087 | goto sd_ob; | |
7088 | case M_SD_OB: | |
7089 | s = "sw"; | |
7090 | sd_ob: | |
ca4e0257 | 7091 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7092 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7093 | offset_expr.X_add_number += 4; |
67c0d1eb | 7094 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7095 | break; |
252b5132 RH |
7096 | |
7097 | /* New code added to support COPZ instructions. | |
7098 | This code builds table entries out of the macros in mip_opcodes. | |
7099 | R4000 uses interlocks to handle coproc delays. | |
7100 | Other chips (like the R3000) require nops to be inserted for delays. | |
7101 | ||
f72c8c98 | 7102 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7103 | In order to fill delay slots for non-interlocked chips, |
7104 | we must have a way to specify delays based on the coprocessor. | |
7105 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7106 | What are the side-effects of the cop instruction? | |
7107 | What cache support might we have and what are its effects? | |
7108 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7109 | What registers are read/set/modified? |
252b5132 RH |
7110 | |
7111 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7112 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7113 | |
7114 | case M_COP0: | |
7115 | s = "c0"; | |
7116 | goto copz; | |
7117 | case M_COP1: | |
7118 | s = "c1"; | |
7119 | goto copz; | |
7120 | case M_COP2: | |
7121 | s = "c2"; | |
7122 | goto copz; | |
7123 | case M_COP3: | |
7124 | s = "c3"; | |
7125 | copz: | |
7126 | /* For now we just do C (same as Cz). The parameter will be | |
7127 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7128 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7129 | break; |
252b5132 | 7130 | |
ea1fb5dc | 7131 | case M_MOVE: |
67c0d1eb | 7132 | move_register (dreg, sreg); |
8fc2e39e | 7133 | break; |
ea1fb5dc | 7134 | |
252b5132 RH |
7135 | #ifdef LOSING_COMPILER |
7136 | default: | |
7137 | /* Try and see if this is a new itbl instruction. | |
7138 | This code builds table entries out of the macros in mip_opcodes. | |
7139 | FIXME: For now we just assemble the expression and pass it's | |
7140 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7141 | We may want to have the assembler assemble this value, |
252b5132 RH |
7142 | so that we gain the assembler's knowledge of delay slots, |
7143 | symbols, etc. | |
7144 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7145 | if (itbl_have_entries |
252b5132 | 7146 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7147 | { |
252b5132 RH |
7148 | s = ip->insn_mo->name; |
7149 | s2 = "cop3"; | |
7150 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7151 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7152 | break; |
beae10d5 | 7153 | } |
252b5132 | 7154 | macro2 (ip); |
8fc2e39e | 7155 | break; |
252b5132 | 7156 | } |
741fe287 | 7157 | if (!mips_opts.at && used_at) |
8fc2e39e | 7158 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7159 | } |
bdaaa2e1 | 7160 | |
252b5132 | 7161 | static void |
17a2f251 | 7162 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7163 | { |
741fe287 MR |
7164 | unsigned int treg, sreg, dreg, breg; |
7165 | unsigned int tempreg; | |
252b5132 | 7166 | int mask; |
252b5132 RH |
7167 | int used_at; |
7168 | expressionS expr1; | |
7169 | const char *s; | |
7170 | const char *s2; | |
7171 | const char *fmt; | |
7172 | int likely = 0; | |
7173 | int dbl = 0; | |
7174 | int coproc = 0; | |
7175 | int lr = 0; | |
7176 | int imm = 0; | |
7177 | int off; | |
7178 | offsetT maxnum; | |
7179 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7180 | |
252b5132 RH |
7181 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7182 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7183 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7184 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7185 | |
252b5132 RH |
7186 | expr1.X_op = O_constant; |
7187 | expr1.X_op_symbol = NULL; | |
7188 | expr1.X_add_symbol = NULL; | |
7189 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7190 | |
252b5132 RH |
7191 | switch (mask) |
7192 | { | |
7193 | #endif /* LOSING_COMPILER */ | |
7194 | ||
7195 | case M_DMUL: | |
7196 | dbl = 1; | |
7197 | case M_MUL: | |
67c0d1eb RS |
7198 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7199 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7200 | break; |
252b5132 RH |
7201 | |
7202 | case M_DMUL_I: | |
7203 | dbl = 1; | |
7204 | case M_MUL_I: | |
7205 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7206 | not trying to be that fancy. GCC should do this for us | |
7207 | anyway. */ | |
8fc2e39e | 7208 | used_at = 1; |
67c0d1eb RS |
7209 | load_register (AT, &imm_expr, dbl); |
7210 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7211 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7212 | break; |
7213 | ||
7214 | case M_DMULO_I: | |
7215 | dbl = 1; | |
7216 | case M_MULO_I: | |
7217 | imm = 1; | |
7218 | goto do_mulo; | |
7219 | ||
7220 | case M_DMULO: | |
7221 | dbl = 1; | |
7222 | case M_MULO: | |
7223 | do_mulo: | |
7d10b47d | 7224 | start_noreorder (); |
8fc2e39e | 7225 | used_at = 1; |
252b5132 | 7226 | if (imm) |
67c0d1eb RS |
7227 | load_register (AT, &imm_expr, dbl); |
7228 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7229 | macro_build (NULL, "mflo", "d", dreg); | |
7230 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7231 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7232 | if (mips_trap) |
67c0d1eb | 7233 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7234 | else |
7235 | { | |
7236 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7237 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7238 | macro_build (NULL, "nop", "", 0); | |
7239 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7240 | } |
7d10b47d | 7241 | end_noreorder (); |
67c0d1eb | 7242 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7243 | break; |
7244 | ||
7245 | case M_DMULOU_I: | |
7246 | dbl = 1; | |
7247 | case M_MULOU_I: | |
7248 | imm = 1; | |
7249 | goto do_mulou; | |
7250 | ||
7251 | case M_DMULOU: | |
7252 | dbl = 1; | |
7253 | case M_MULOU: | |
7254 | do_mulou: | |
7d10b47d | 7255 | start_noreorder (); |
8fc2e39e | 7256 | used_at = 1; |
252b5132 | 7257 | if (imm) |
67c0d1eb RS |
7258 | load_register (AT, &imm_expr, dbl); |
7259 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7260 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7261 | macro_build (NULL, "mfhi", "d", AT); |
7262 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7263 | if (mips_trap) |
67c0d1eb | 7264 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7265 | else |
7266 | { | |
7267 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7268 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7269 | macro_build (NULL, "nop", "", 0); | |
7270 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7271 | } |
7d10b47d | 7272 | end_noreorder (); |
252b5132 RH |
7273 | break; |
7274 | ||
771c7ce4 | 7275 | case M_DROL: |
fef14a42 | 7276 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7277 | { |
7278 | if (dreg == sreg) | |
7279 | { | |
7280 | tempreg = AT; | |
7281 | used_at = 1; | |
7282 | } | |
7283 | else | |
7284 | { | |
7285 | tempreg = dreg; | |
82dd0097 | 7286 | } |
67c0d1eb RS |
7287 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7288 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7289 | break; |
82dd0097 | 7290 | } |
8fc2e39e | 7291 | used_at = 1; |
67c0d1eb RS |
7292 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7293 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7294 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7295 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7296 | break; |
7297 | ||
252b5132 | 7298 | case M_ROL: |
fef14a42 | 7299 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7300 | { |
7301 | if (dreg == sreg) | |
7302 | { | |
7303 | tempreg = AT; | |
7304 | used_at = 1; | |
7305 | } | |
7306 | else | |
7307 | { | |
7308 | tempreg = dreg; | |
82dd0097 | 7309 | } |
67c0d1eb RS |
7310 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7311 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7312 | break; |
82dd0097 | 7313 | } |
8fc2e39e | 7314 | used_at = 1; |
67c0d1eb RS |
7315 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7316 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7317 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7318 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7319 | break; |
7320 | ||
771c7ce4 TS |
7321 | case M_DROL_I: |
7322 | { | |
7323 | unsigned int rot; | |
82dd0097 | 7324 | char *l, *r; |
771c7ce4 TS |
7325 | |
7326 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7327 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7328 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7329 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7330 | { |
7331 | rot = (64 - rot) & 0x3f; | |
7332 | if (rot >= 32) | |
67c0d1eb | 7333 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7334 | else |
67c0d1eb | 7335 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7336 | break; |
60b63b72 | 7337 | } |
483fc7cd | 7338 | if (rot == 0) |
483fc7cd | 7339 | { |
67c0d1eb | 7340 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7341 | break; |
483fc7cd | 7342 | } |
82dd0097 CD |
7343 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7344 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7345 | rot &= 0x1f; | |
8fc2e39e | 7346 | used_at = 1; |
67c0d1eb RS |
7347 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7348 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7349 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7350 | } |
7351 | break; | |
7352 | ||
252b5132 | 7353 | case M_ROL_I: |
771c7ce4 TS |
7354 | { |
7355 | unsigned int rot; | |
7356 | ||
7357 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7358 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7359 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7360 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7361 | { |
67c0d1eb | 7362 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7363 | break; |
60b63b72 | 7364 | } |
483fc7cd | 7365 | if (rot == 0) |
483fc7cd | 7366 | { |
67c0d1eb | 7367 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7368 | break; |
483fc7cd | 7369 | } |
8fc2e39e | 7370 | used_at = 1; |
67c0d1eb RS |
7371 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7372 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7373 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7374 | } |
7375 | break; | |
7376 | ||
7377 | case M_DROR: | |
fef14a42 | 7378 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7379 | { |
67c0d1eb | 7380 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7381 | break; |
82dd0097 | 7382 | } |
8fc2e39e | 7383 | used_at = 1; |
67c0d1eb RS |
7384 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7385 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7386 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7387 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7388 | break; |
7389 | ||
7390 | case M_ROR: | |
fef14a42 | 7391 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7392 | { |
67c0d1eb | 7393 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7394 | break; |
82dd0097 | 7395 | } |
8fc2e39e | 7396 | used_at = 1; |
67c0d1eb RS |
7397 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7398 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7399 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7400 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7401 | break; |
7402 | ||
771c7ce4 TS |
7403 | case M_DROR_I: |
7404 | { | |
7405 | unsigned int rot; | |
82dd0097 | 7406 | char *l, *r; |
771c7ce4 TS |
7407 | |
7408 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7409 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7410 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7411 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7412 | { |
7413 | if (rot >= 32) | |
67c0d1eb | 7414 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7415 | else |
67c0d1eb | 7416 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7417 | break; |
82dd0097 | 7418 | } |
483fc7cd | 7419 | if (rot == 0) |
483fc7cd | 7420 | { |
67c0d1eb | 7421 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7422 | break; |
483fc7cd | 7423 | } |
82dd0097 CD |
7424 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7425 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7426 | rot &= 0x1f; | |
8fc2e39e | 7427 | used_at = 1; |
67c0d1eb RS |
7428 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7429 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7430 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7431 | } |
7432 | break; | |
7433 | ||
252b5132 | 7434 | case M_ROR_I: |
771c7ce4 TS |
7435 | { |
7436 | unsigned int rot; | |
7437 | ||
7438 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7439 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7440 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7441 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7442 | { |
67c0d1eb | 7443 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7444 | break; |
82dd0097 | 7445 | } |
483fc7cd | 7446 | if (rot == 0) |
483fc7cd | 7447 | { |
67c0d1eb | 7448 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7449 | break; |
483fc7cd | 7450 | } |
8fc2e39e | 7451 | used_at = 1; |
67c0d1eb RS |
7452 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7453 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7454 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7455 | } |
252b5132 RH |
7456 | break; |
7457 | ||
7458 | case M_S_DOB: | |
fef14a42 | 7459 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7460 | { |
7461 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7462 | break; |
252b5132 | 7463 | } |
e7af610e | 7464 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7465 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7466 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7467 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7468 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7469 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7470 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7471 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7472 | break; |
252b5132 RH |
7473 | |
7474 | case M_SEQ: | |
7475 | if (sreg == 0) | |
67c0d1eb | 7476 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7477 | else if (treg == 0) |
67c0d1eb | 7478 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7479 | else |
7480 | { | |
67c0d1eb RS |
7481 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7482 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7483 | } |
8fc2e39e | 7484 | break; |
252b5132 RH |
7485 | |
7486 | case M_SEQ_I: | |
7487 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7488 | { | |
67c0d1eb | 7489 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7490 | break; |
252b5132 RH |
7491 | } |
7492 | if (sreg == 0) | |
7493 | { | |
7494 | as_warn (_("Instruction %s: result is always false"), | |
7495 | ip->insn_mo->name); | |
67c0d1eb | 7496 | move_register (dreg, 0); |
8fc2e39e | 7497 | break; |
252b5132 RH |
7498 | } |
7499 | if (imm_expr.X_op == O_constant | |
7500 | && imm_expr.X_add_number >= 0 | |
7501 | && imm_expr.X_add_number < 0x10000) | |
7502 | { | |
67c0d1eb | 7503 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7504 | } |
7505 | else if (imm_expr.X_op == O_constant | |
7506 | && imm_expr.X_add_number > -0x8000 | |
7507 | && imm_expr.X_add_number < 0) | |
7508 | { | |
7509 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7510 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7511 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7512 | } |
7513 | else | |
7514 | { | |
67c0d1eb RS |
7515 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7516 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7517 | used_at = 1; |
7518 | } | |
67c0d1eb | 7519 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7520 | break; |
252b5132 RH |
7521 | |
7522 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7523 | s = "slt"; | |
7524 | goto sge; | |
7525 | case M_SGEU: | |
7526 | s = "sltu"; | |
7527 | sge: | |
67c0d1eb RS |
7528 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7529 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7530 | break; |
252b5132 RH |
7531 | |
7532 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7533 | case M_SGEU_I: | |
7534 | if (imm_expr.X_op == O_constant | |
7535 | && imm_expr.X_add_number >= -0x8000 | |
7536 | && imm_expr.X_add_number < 0x8000) | |
7537 | { | |
67c0d1eb RS |
7538 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7539 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7540 | } |
7541 | else | |
7542 | { | |
67c0d1eb RS |
7543 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7544 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7545 | dreg, sreg, AT); | |
252b5132 RH |
7546 | used_at = 1; |
7547 | } | |
67c0d1eb | 7548 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7549 | break; |
252b5132 RH |
7550 | |
7551 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7552 | s = "slt"; | |
7553 | goto sgt; | |
7554 | case M_SGTU: | |
7555 | s = "sltu"; | |
7556 | sgt: | |
67c0d1eb | 7557 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7558 | break; |
252b5132 RH |
7559 | |
7560 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7561 | s = "slt"; | |
7562 | goto sgti; | |
7563 | case M_SGTU_I: | |
7564 | s = "sltu"; | |
7565 | sgti: | |
8fc2e39e | 7566 | used_at = 1; |
67c0d1eb RS |
7567 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7568 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7569 | break; |
7570 | ||
2396cfb9 | 7571 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7572 | s = "slt"; |
7573 | goto sle; | |
7574 | case M_SLEU: | |
7575 | s = "sltu"; | |
7576 | sle: | |
67c0d1eb RS |
7577 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7578 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7579 | break; |
252b5132 | 7580 | |
2396cfb9 | 7581 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7582 | s = "slt"; |
7583 | goto slei; | |
7584 | case M_SLEU_I: | |
7585 | s = "sltu"; | |
7586 | slei: | |
8fc2e39e | 7587 | used_at = 1; |
67c0d1eb RS |
7588 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7589 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7590 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7591 | break; |
7592 | ||
7593 | case M_SLT_I: | |
7594 | if (imm_expr.X_op == O_constant | |
7595 | && imm_expr.X_add_number >= -0x8000 | |
7596 | && imm_expr.X_add_number < 0x8000) | |
7597 | { | |
67c0d1eb | 7598 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7599 | break; |
252b5132 | 7600 | } |
8fc2e39e | 7601 | used_at = 1; |
67c0d1eb RS |
7602 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7603 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7604 | break; |
7605 | ||
7606 | case M_SLTU_I: | |
7607 | if (imm_expr.X_op == O_constant | |
7608 | && imm_expr.X_add_number >= -0x8000 | |
7609 | && imm_expr.X_add_number < 0x8000) | |
7610 | { | |
67c0d1eb | 7611 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7612 | BFD_RELOC_LO16); |
8fc2e39e | 7613 | break; |
252b5132 | 7614 | } |
8fc2e39e | 7615 | used_at = 1; |
67c0d1eb RS |
7616 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7617 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7618 | break; |
7619 | ||
7620 | case M_SNE: | |
7621 | if (sreg == 0) | |
67c0d1eb | 7622 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7623 | else if (treg == 0) |
67c0d1eb | 7624 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7625 | else |
7626 | { | |
67c0d1eb RS |
7627 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7628 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7629 | } |
8fc2e39e | 7630 | break; |
252b5132 RH |
7631 | |
7632 | case M_SNE_I: | |
7633 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7634 | { | |
67c0d1eb | 7635 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7636 | break; |
252b5132 RH |
7637 | } |
7638 | if (sreg == 0) | |
7639 | { | |
7640 | as_warn (_("Instruction %s: result is always true"), | |
7641 | ip->insn_mo->name); | |
67c0d1eb RS |
7642 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7643 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7644 | break; |
252b5132 RH |
7645 | } |
7646 | if (imm_expr.X_op == O_constant | |
7647 | && imm_expr.X_add_number >= 0 | |
7648 | && imm_expr.X_add_number < 0x10000) | |
7649 | { | |
67c0d1eb | 7650 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7651 | } |
7652 | else if (imm_expr.X_op == O_constant | |
7653 | && imm_expr.X_add_number > -0x8000 | |
7654 | && imm_expr.X_add_number < 0) | |
7655 | { | |
7656 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7657 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7658 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7659 | } |
7660 | else | |
7661 | { | |
67c0d1eb RS |
7662 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7663 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7664 | used_at = 1; |
7665 | } | |
67c0d1eb | 7666 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7667 | break; |
252b5132 RH |
7668 | |
7669 | case M_DSUB_I: | |
7670 | dbl = 1; | |
7671 | case M_SUB_I: | |
7672 | if (imm_expr.X_op == O_constant | |
7673 | && imm_expr.X_add_number > -0x8000 | |
7674 | && imm_expr.X_add_number <= 0x8000) | |
7675 | { | |
7676 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7677 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7678 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7679 | break; |
252b5132 | 7680 | } |
8fc2e39e | 7681 | used_at = 1; |
67c0d1eb RS |
7682 | load_register (AT, &imm_expr, dbl); |
7683 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7684 | break; |
7685 | ||
7686 | case M_DSUBU_I: | |
7687 | dbl = 1; | |
7688 | case M_SUBU_I: | |
7689 | if (imm_expr.X_op == O_constant | |
7690 | && imm_expr.X_add_number > -0x8000 | |
7691 | && imm_expr.X_add_number <= 0x8000) | |
7692 | { | |
7693 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7694 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7695 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7696 | break; |
252b5132 | 7697 | } |
8fc2e39e | 7698 | used_at = 1; |
67c0d1eb RS |
7699 | load_register (AT, &imm_expr, dbl); |
7700 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7701 | break; |
7702 | ||
7703 | case M_TEQ_I: | |
7704 | s = "teq"; | |
7705 | goto trap; | |
7706 | case M_TGE_I: | |
7707 | s = "tge"; | |
7708 | goto trap; | |
7709 | case M_TGEU_I: | |
7710 | s = "tgeu"; | |
7711 | goto trap; | |
7712 | case M_TLT_I: | |
7713 | s = "tlt"; | |
7714 | goto trap; | |
7715 | case M_TLTU_I: | |
7716 | s = "tltu"; | |
7717 | goto trap; | |
7718 | case M_TNE_I: | |
7719 | s = "tne"; | |
7720 | trap: | |
8fc2e39e | 7721 | used_at = 1; |
67c0d1eb RS |
7722 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7723 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7724 | break; |
7725 | ||
252b5132 | 7726 | case M_TRUNCWS: |
43841e91 | 7727 | case M_TRUNCWD: |
e7af610e | 7728 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7729 | used_at = 1; |
252b5132 RH |
7730 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7731 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7732 | ||
7733 | /* | |
7734 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7735 | * or is there a reason for it? | |
7736 | */ | |
7d10b47d | 7737 | start_noreorder (); |
67c0d1eb RS |
7738 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7739 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7740 | macro_build (NULL, "nop", ""); | |
252b5132 | 7741 | expr1.X_add_number = 3; |
67c0d1eb | 7742 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7743 | expr1.X_add_number = 2; |
67c0d1eb RS |
7744 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7745 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7746 | macro_build (NULL, "nop", ""); | |
7747 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7748 | dreg, sreg); | |
7749 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7750 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7751 | end_noreorder (); |
252b5132 RH |
7752 | break; |
7753 | ||
7754 | case M_ULH: | |
7755 | s = "lb"; | |
7756 | goto ulh; | |
7757 | case M_ULHU: | |
7758 | s = "lbu"; | |
7759 | ulh: | |
8fc2e39e | 7760 | used_at = 1; |
252b5132 RH |
7761 | if (offset_expr.X_add_number >= 0x7fff) |
7762 | as_bad (_("operand overflow")); | |
252b5132 | 7763 | if (! target_big_endian) |
f9419b05 | 7764 | ++offset_expr.X_add_number; |
67c0d1eb | 7765 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7766 | if (! target_big_endian) |
f9419b05 | 7767 | --offset_expr.X_add_number; |
252b5132 | 7768 | else |
f9419b05 | 7769 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7770 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7771 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7772 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7773 | break; |
7774 | ||
7775 | case M_ULD: | |
7776 | s = "ldl"; | |
7777 | s2 = "ldr"; | |
7778 | off = 7; | |
7779 | goto ulw; | |
7780 | case M_ULW: | |
7781 | s = "lwl"; | |
7782 | s2 = "lwr"; | |
7783 | off = 3; | |
7784 | ulw: | |
7785 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7786 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7787 | if (treg != breg) |
7788 | tempreg = treg; | |
7789 | else | |
8fc2e39e TS |
7790 | { |
7791 | used_at = 1; | |
7792 | tempreg = AT; | |
7793 | } | |
252b5132 RH |
7794 | if (! target_big_endian) |
7795 | offset_expr.X_add_number += off; | |
67c0d1eb | 7796 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7797 | if (! target_big_endian) |
7798 | offset_expr.X_add_number -= off; | |
7799 | else | |
7800 | offset_expr.X_add_number += off; | |
67c0d1eb | 7801 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7802 | |
7803 | /* If necessary, move the result in tempreg the final destination. */ | |
7804 | if (treg == tempreg) | |
8fc2e39e | 7805 | break; |
af22f5b2 | 7806 | /* Protect second load's delay slot. */ |
017315e4 | 7807 | load_delay_nop (); |
67c0d1eb | 7808 | move_register (treg, tempreg); |
af22f5b2 | 7809 | break; |
252b5132 RH |
7810 | |
7811 | case M_ULD_A: | |
7812 | s = "ldl"; | |
7813 | s2 = "ldr"; | |
7814 | off = 7; | |
7815 | goto ulwa; | |
7816 | case M_ULW_A: | |
7817 | s = "lwl"; | |
7818 | s2 = "lwr"; | |
7819 | off = 3; | |
7820 | ulwa: | |
d6bc6245 | 7821 | used_at = 1; |
67c0d1eb | 7822 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7823 | if (breg != 0) |
67c0d1eb | 7824 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7825 | if (! target_big_endian) |
7826 | expr1.X_add_number = off; | |
7827 | else | |
7828 | expr1.X_add_number = 0; | |
67c0d1eb | 7829 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7830 | if (! target_big_endian) |
7831 | expr1.X_add_number = 0; | |
7832 | else | |
7833 | expr1.X_add_number = off; | |
67c0d1eb | 7834 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7835 | break; |
7836 | ||
7837 | case M_ULH_A: | |
7838 | case M_ULHU_A: | |
d6bc6245 | 7839 | used_at = 1; |
67c0d1eb | 7840 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7841 | if (breg != 0) |
67c0d1eb | 7842 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7843 | if (target_big_endian) |
7844 | expr1.X_add_number = 0; | |
67c0d1eb | 7845 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7846 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7847 | if (target_big_endian) |
7848 | expr1.X_add_number = 1; | |
7849 | else | |
7850 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7851 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7852 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7853 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7854 | break; |
7855 | ||
7856 | case M_USH: | |
8fc2e39e | 7857 | used_at = 1; |
252b5132 RH |
7858 | if (offset_expr.X_add_number >= 0x7fff) |
7859 | as_bad (_("operand overflow")); | |
7860 | if (target_big_endian) | |
f9419b05 | 7861 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7862 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7863 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7864 | if (target_big_endian) |
f9419b05 | 7865 | --offset_expr.X_add_number; |
252b5132 | 7866 | else |
f9419b05 | 7867 | ++offset_expr.X_add_number; |
67c0d1eb | 7868 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7869 | break; |
7870 | ||
7871 | case M_USD: | |
7872 | s = "sdl"; | |
7873 | s2 = "sdr"; | |
7874 | off = 7; | |
7875 | goto usw; | |
7876 | case M_USW: | |
7877 | s = "swl"; | |
7878 | s2 = "swr"; | |
7879 | off = 3; | |
7880 | usw: | |
7881 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7882 | as_bad (_("operand overflow")); | |
7883 | if (! target_big_endian) | |
7884 | offset_expr.X_add_number += off; | |
67c0d1eb | 7885 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7886 | if (! target_big_endian) |
7887 | offset_expr.X_add_number -= off; | |
7888 | else | |
7889 | offset_expr.X_add_number += off; | |
67c0d1eb | 7890 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7891 | break; |
252b5132 RH |
7892 | |
7893 | case M_USD_A: | |
7894 | s = "sdl"; | |
7895 | s2 = "sdr"; | |
7896 | off = 7; | |
7897 | goto uswa; | |
7898 | case M_USW_A: | |
7899 | s = "swl"; | |
7900 | s2 = "swr"; | |
7901 | off = 3; | |
7902 | uswa: | |
d6bc6245 | 7903 | used_at = 1; |
67c0d1eb | 7904 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7905 | if (breg != 0) |
67c0d1eb | 7906 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7907 | if (! target_big_endian) |
7908 | expr1.X_add_number = off; | |
7909 | else | |
7910 | expr1.X_add_number = 0; | |
67c0d1eb | 7911 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7912 | if (! target_big_endian) |
7913 | expr1.X_add_number = 0; | |
7914 | else | |
7915 | expr1.X_add_number = off; | |
67c0d1eb | 7916 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7917 | break; |
7918 | ||
7919 | case M_USH_A: | |
d6bc6245 | 7920 | used_at = 1; |
67c0d1eb | 7921 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7922 | if (breg != 0) |
67c0d1eb | 7923 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7924 | if (! target_big_endian) |
7925 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7926 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7927 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7928 | if (! target_big_endian) |
7929 | expr1.X_add_number = 1; | |
7930 | else | |
7931 | expr1.X_add_number = 0; | |
67c0d1eb | 7932 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7933 | if (! target_big_endian) |
7934 | expr1.X_add_number = 0; | |
7935 | else | |
7936 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7937 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7938 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7939 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7940 | break; |
7941 | ||
7942 | default: | |
7943 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7944 | are added dynamically. */ |
252b5132 RH |
7945 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7946 | break; | |
7947 | } | |
741fe287 | 7948 | if (!mips_opts.at && used_at) |
8fc2e39e | 7949 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
7950 | } |
7951 | ||
7952 | /* Implement macros in mips16 mode. */ | |
7953 | ||
7954 | static void | |
17a2f251 | 7955 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7956 | { |
7957 | int mask; | |
7958 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7959 | expressionS expr1; |
7960 | int dbl; | |
7961 | const char *s, *s2, *s3; | |
7962 | ||
7963 | mask = ip->insn_mo->mask; | |
7964 | ||
bf12938e RS |
7965 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7966 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7967 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7968 | |
252b5132 RH |
7969 | expr1.X_op = O_constant; |
7970 | expr1.X_op_symbol = NULL; | |
7971 | expr1.X_add_symbol = NULL; | |
7972 | expr1.X_add_number = 1; | |
7973 | ||
7974 | dbl = 0; | |
7975 | ||
7976 | switch (mask) | |
7977 | { | |
7978 | default: | |
7979 | internalError (); | |
7980 | ||
7981 | case M_DDIV_3: | |
7982 | dbl = 1; | |
7983 | case M_DIV_3: | |
7984 | s = "mflo"; | |
7985 | goto do_div3; | |
7986 | case M_DREM_3: | |
7987 | dbl = 1; | |
7988 | case M_REM_3: | |
7989 | s = "mfhi"; | |
7990 | do_div3: | |
7d10b47d | 7991 | start_noreorder (); |
67c0d1eb | 7992 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7993 | expr1.X_add_number = 2; |
67c0d1eb RS |
7994 | macro_build (&expr1, "bnez", "x,p", yreg); |
7995 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7996 | |
252b5132 RH |
7997 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7998 | since that causes an overflow. We should do that as well, | |
7999 | but I don't see how to do the comparisons without a temporary | |
8000 | register. */ | |
7d10b47d | 8001 | end_noreorder (); |
67c0d1eb | 8002 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8003 | break; |
8004 | ||
8005 | case M_DIVU_3: | |
8006 | s = "divu"; | |
8007 | s2 = "mflo"; | |
8008 | goto do_divu3; | |
8009 | case M_REMU_3: | |
8010 | s = "divu"; | |
8011 | s2 = "mfhi"; | |
8012 | goto do_divu3; | |
8013 | case M_DDIVU_3: | |
8014 | s = "ddivu"; | |
8015 | s2 = "mflo"; | |
8016 | goto do_divu3; | |
8017 | case M_DREMU_3: | |
8018 | s = "ddivu"; | |
8019 | s2 = "mfhi"; | |
8020 | do_divu3: | |
7d10b47d | 8021 | start_noreorder (); |
67c0d1eb | 8022 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8023 | expr1.X_add_number = 2; |
67c0d1eb RS |
8024 | macro_build (&expr1, "bnez", "x,p", yreg); |
8025 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8026 | end_noreorder (); |
67c0d1eb | 8027 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8028 | break; |
8029 | ||
8030 | case M_DMUL: | |
8031 | dbl = 1; | |
8032 | case M_MUL: | |
67c0d1eb RS |
8033 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8034 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8035 | break; |
252b5132 RH |
8036 | |
8037 | case M_DSUBU_I: | |
8038 | dbl = 1; | |
8039 | goto do_subu; | |
8040 | case M_SUBU_I: | |
8041 | do_subu: | |
8042 | if (imm_expr.X_op != O_constant) | |
8043 | as_bad (_("Unsupported large constant")); | |
8044 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8045 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8046 | break; |
8047 | ||
8048 | case M_SUBU_I_2: | |
8049 | if (imm_expr.X_op != O_constant) | |
8050 | as_bad (_("Unsupported large constant")); | |
8051 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8052 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8053 | break; |
8054 | ||
8055 | case M_DSUBU_I_2: | |
8056 | if (imm_expr.X_op != O_constant) | |
8057 | as_bad (_("Unsupported large constant")); | |
8058 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8059 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8060 | break; |
8061 | ||
8062 | case M_BEQ: | |
8063 | s = "cmp"; | |
8064 | s2 = "bteqz"; | |
8065 | goto do_branch; | |
8066 | case M_BNE: | |
8067 | s = "cmp"; | |
8068 | s2 = "btnez"; | |
8069 | goto do_branch; | |
8070 | case M_BLT: | |
8071 | s = "slt"; | |
8072 | s2 = "btnez"; | |
8073 | goto do_branch; | |
8074 | case M_BLTU: | |
8075 | s = "sltu"; | |
8076 | s2 = "btnez"; | |
8077 | goto do_branch; | |
8078 | case M_BLE: | |
8079 | s = "slt"; | |
8080 | s2 = "bteqz"; | |
8081 | goto do_reverse_branch; | |
8082 | case M_BLEU: | |
8083 | s = "sltu"; | |
8084 | s2 = "bteqz"; | |
8085 | goto do_reverse_branch; | |
8086 | case M_BGE: | |
8087 | s = "slt"; | |
8088 | s2 = "bteqz"; | |
8089 | goto do_branch; | |
8090 | case M_BGEU: | |
8091 | s = "sltu"; | |
8092 | s2 = "bteqz"; | |
8093 | goto do_branch; | |
8094 | case M_BGT: | |
8095 | s = "slt"; | |
8096 | s2 = "btnez"; | |
8097 | goto do_reverse_branch; | |
8098 | case M_BGTU: | |
8099 | s = "sltu"; | |
8100 | s2 = "btnez"; | |
8101 | ||
8102 | do_reverse_branch: | |
8103 | tmp = xreg; | |
8104 | xreg = yreg; | |
8105 | yreg = tmp; | |
8106 | ||
8107 | do_branch: | |
67c0d1eb RS |
8108 | macro_build (NULL, s, "x,y", xreg, yreg); |
8109 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8110 | break; |
8111 | ||
8112 | case M_BEQ_I: | |
8113 | s = "cmpi"; | |
8114 | s2 = "bteqz"; | |
8115 | s3 = "x,U"; | |
8116 | goto do_branch_i; | |
8117 | case M_BNE_I: | |
8118 | s = "cmpi"; | |
8119 | s2 = "btnez"; | |
8120 | s3 = "x,U"; | |
8121 | goto do_branch_i; | |
8122 | case M_BLT_I: | |
8123 | s = "slti"; | |
8124 | s2 = "btnez"; | |
8125 | s3 = "x,8"; | |
8126 | goto do_branch_i; | |
8127 | case M_BLTU_I: | |
8128 | s = "sltiu"; | |
8129 | s2 = "btnez"; | |
8130 | s3 = "x,8"; | |
8131 | goto do_branch_i; | |
8132 | case M_BLE_I: | |
8133 | s = "slti"; | |
8134 | s2 = "btnez"; | |
8135 | s3 = "x,8"; | |
8136 | goto do_addone_branch_i; | |
8137 | case M_BLEU_I: | |
8138 | s = "sltiu"; | |
8139 | s2 = "btnez"; | |
8140 | s3 = "x,8"; | |
8141 | goto do_addone_branch_i; | |
8142 | case M_BGE_I: | |
8143 | s = "slti"; | |
8144 | s2 = "bteqz"; | |
8145 | s3 = "x,8"; | |
8146 | goto do_branch_i; | |
8147 | case M_BGEU_I: | |
8148 | s = "sltiu"; | |
8149 | s2 = "bteqz"; | |
8150 | s3 = "x,8"; | |
8151 | goto do_branch_i; | |
8152 | case M_BGT_I: | |
8153 | s = "slti"; | |
8154 | s2 = "bteqz"; | |
8155 | s3 = "x,8"; | |
8156 | goto do_addone_branch_i; | |
8157 | case M_BGTU_I: | |
8158 | s = "sltiu"; | |
8159 | s2 = "bteqz"; | |
8160 | s3 = "x,8"; | |
8161 | ||
8162 | do_addone_branch_i: | |
8163 | if (imm_expr.X_op != O_constant) | |
8164 | as_bad (_("Unsupported large constant")); | |
8165 | ++imm_expr.X_add_number; | |
8166 | ||
8167 | do_branch_i: | |
67c0d1eb RS |
8168 | macro_build (&imm_expr, s, s3, xreg); |
8169 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8170 | break; |
8171 | ||
8172 | case M_ABS: | |
8173 | expr1.X_add_number = 0; | |
67c0d1eb | 8174 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8175 | if (xreg != yreg) |
67c0d1eb | 8176 | move_register (xreg, yreg); |
252b5132 | 8177 | expr1.X_add_number = 2; |
67c0d1eb RS |
8178 | macro_build (&expr1, "bteqz", "p"); |
8179 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8180 | } |
8181 | } | |
8182 | ||
8183 | /* For consistency checking, verify that all bits are specified either | |
8184 | by the match/mask part of the instruction definition, or by the | |
8185 | operand list. */ | |
8186 | static int | |
17a2f251 | 8187 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8188 | { |
8189 | const char *p = opc->args; | |
8190 | char c; | |
8191 | unsigned long used_bits = opc->mask; | |
8192 | ||
8193 | if ((used_bits & opc->match) != opc->match) | |
8194 | { | |
8195 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8196 | opc->name, opc->args); | |
8197 | return 0; | |
8198 | } | |
8199 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8200 | while (*p) | |
8201 | switch (c = *p++) | |
8202 | { | |
8203 | case ',': break; | |
8204 | case '(': break; | |
8205 | case ')': break; | |
af7ee8bf CD |
8206 | case '+': |
8207 | switch (c = *p++) | |
8208 | { | |
9bcd4f99 TS |
8209 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8210 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8211 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8212 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8213 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8214 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8215 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8216 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8217 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8218 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8219 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8220 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8221 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8222 | case 'I': break; | |
ef2e4d86 CF |
8223 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8224 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8225 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8226 | default: |
8227 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8228 | c, opc->name, opc->args); | |
8229 | return 0; | |
8230 | } | |
8231 | break; | |
252b5132 RH |
8232 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8233 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8234 | case 'A': break; | |
4372b673 | 8235 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8236 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8237 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8238 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8239 | case 'F': break; | |
8240 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8241 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8242 | case 'I': break; |
e972090a | 8243 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8244 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8245 | case 'L': break; |
8246 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8247 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8248 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8249 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8250 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8251 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8252 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8253 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8254 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8255 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8256 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8257 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8258 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8259 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8260 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8261 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8262 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8263 | case 'f': break; | |
8264 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8265 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8266 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8267 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8268 | case 'l': break; | |
8269 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8270 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8271 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8272 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8273 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8274 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8275 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8276 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8277 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8278 | case 'x': break; | |
8279 | case 'z': break; | |
8280 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8281 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8282 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8283 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8284 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8285 | case '[': break; | |
8286 | case ']': break; | |
8b082fb1 | 8287 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8288 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8289 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8290 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8291 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8292 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8293 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8294 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8295 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8296 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8297 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8298 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8299 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8300 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8301 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8302 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8303 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8304 | default: |
8305 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8306 | c, opc->name, opc->args); | |
8307 | return 0; | |
8308 | } | |
8309 | #undef USE_BITS | |
8310 | if (used_bits != 0xffffffff) | |
8311 | { | |
8312 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8313 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8314 | return 0; | |
8315 | } | |
8316 | return 1; | |
8317 | } | |
8318 | ||
9bcd4f99 TS |
8319 | /* UDI immediates. */ |
8320 | struct mips_immed { | |
8321 | char type; | |
8322 | unsigned int shift; | |
8323 | unsigned long mask; | |
8324 | const char * desc; | |
8325 | }; | |
8326 | ||
8327 | static const struct mips_immed mips_immed[] = { | |
8328 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8329 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8330 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8331 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8332 | { 0,0,0,0 } | |
8333 | }; | |
8334 | ||
7455baf8 TS |
8335 | /* Check whether an odd floating-point register is allowed. */ |
8336 | static int | |
8337 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8338 | { | |
8339 | const char *s = insn->name; | |
8340 | ||
8341 | if (insn->pinfo == INSN_MACRO) | |
8342 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8343 | return 1; | |
8344 | ||
8345 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8346 | { | |
8347 | /* Allow odd registers for single-precision ops. */ | |
8348 | switch (insn->pinfo & (FP_S | FP_D)) | |
8349 | { | |
8350 | case FP_S: | |
8351 | case 0: | |
8352 | return 1; /* both single precision - ok */ | |
8353 | case FP_D: | |
8354 | return 0; /* both double precision - fail */ | |
8355 | default: | |
8356 | break; | |
8357 | } | |
8358 | ||
8359 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8360 | s = strchr (insn->name, '.'); | |
8361 | if (argnum == 2) | |
8362 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8363 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8364 | } | |
8365 | ||
8366 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8367 | if ((insn->pinfo & FP_S) | |
8368 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8369 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8370 | return 1; | |
8371 | ||
8372 | return 0; | |
8373 | } | |
8374 | ||
252b5132 RH |
8375 | /* This routine assembles an instruction into its binary format. As a |
8376 | side effect, it sets one of the global variables imm_reloc or | |
8377 | offset_reloc to the type of relocation to do if one of the operands | |
8378 | is an address expression. */ | |
8379 | ||
8380 | static void | |
17a2f251 | 8381 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8382 | { |
8383 | char *s; | |
8384 | const char *args; | |
43841e91 | 8385 | char c = 0; |
252b5132 RH |
8386 | struct mips_opcode *insn; |
8387 | char *argsStart; | |
8388 | unsigned int regno; | |
8389 | unsigned int lastregno = 0; | |
af7ee8bf | 8390 | unsigned int lastpos = 0; |
071742cf | 8391 | unsigned int limlo, limhi; |
252b5132 RH |
8392 | char *s_reset; |
8393 | char save_c = 0; | |
74cd071d | 8394 | offsetT min_range, max_range; |
707bfff6 TS |
8395 | int argnum; |
8396 | unsigned int rtype; | |
252b5132 RH |
8397 | |
8398 | insn_error = NULL; | |
8399 | ||
8400 | /* If the instruction contains a '.', we first try to match an instruction | |
8401 | including the '.'. Then we try again without the '.'. */ | |
8402 | insn = NULL; | |
3882b010 | 8403 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8404 | continue; |
8405 | ||
8406 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8407 | the call to hash_find. Save the character we replaced just in case we | |
8408 | have to re-parse the instruction. */ | |
3882b010 | 8409 | if (ISSPACE (*s)) |
252b5132 RH |
8410 | { |
8411 | save_c = *s; | |
8412 | *s++ = '\0'; | |
8413 | } | |
bdaaa2e1 | 8414 | |
252b5132 RH |
8415 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8416 | ||
8417 | /* If we didn't find the instruction in the opcode table, try again, but | |
8418 | this time with just the instruction up to, but not including the | |
8419 | first '.'. */ | |
8420 | if (insn == NULL) | |
8421 | { | |
bdaaa2e1 | 8422 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8423 | if (save_c) |
8424 | *(--s) = save_c; | |
8425 | ||
8426 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8427 | for (s = str; |
8428 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8429 | ++s) | |
252b5132 RH |
8430 | continue; |
8431 | ||
8432 | /* If we did not find a '.', then we can quit now. */ | |
8433 | if (*s != '.') | |
8434 | { | |
8435 | insn_error = "unrecognized opcode"; | |
8436 | return; | |
8437 | } | |
8438 | ||
8439 | /* Lookup the instruction in the hash table. */ | |
8440 | *s++ = '\0'; | |
8441 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8442 | { | |
8443 | insn_error = "unrecognized opcode"; | |
8444 | return; | |
8445 | } | |
252b5132 RH |
8446 | } |
8447 | ||
8448 | argsStart = s; | |
8449 | for (;;) | |
8450 | { | |
b34976b6 | 8451 | bfd_boolean ok; |
252b5132 RH |
8452 | |
8453 | assert (strcmp (insn->name, str) == 0); | |
8454 | ||
1f25f5d3 CD |
8455 | if (OPCODE_IS_MEMBER (insn, |
8456 | (mips_opts.isa | |
9b3f89ee TS |
8457 | /* We don't check for mips_opts.mips16 here since |
8458 | we want to allow jalx if -mips16 was specified | |
8459 | on the command line. */ | |
3396de36 | 8460 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8461 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8462 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8463 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8464 | ? INSN_DSP64 : 0) | |
8b082fb1 | 8465 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) |
ef2e4d86 | 8466 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8467 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8468 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8469 | mips_opts.arch)) |
b34976b6 | 8470 | ok = TRUE; |
bdaaa2e1 | 8471 | else |
b34976b6 | 8472 | ok = FALSE; |
bdaaa2e1 | 8473 | |
252b5132 RH |
8474 | if (insn->pinfo != INSN_MACRO) |
8475 | { | |
fef14a42 | 8476 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8477 | ok = FALSE; |
252b5132 RH |
8478 | } |
8479 | ||
8480 | if (! ok) | |
8481 | { | |
8482 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8483 | && strcmp (insn->name, insn[1].name) == 0) | |
8484 | { | |
8485 | ++insn; | |
8486 | continue; | |
8487 | } | |
252b5132 | 8488 | else |
beae10d5 | 8489 | { |
268f6bed L |
8490 | if (!insn_error) |
8491 | { | |
8492 | static char buf[100]; | |
fef14a42 TS |
8493 | sprintf (buf, |
8494 | _("opcode not supported on this processor: %s (%s)"), | |
8495 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8496 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8497 | insn_error = buf; |
8498 | } | |
8499 | if (save_c) | |
8500 | *(--s) = save_c; | |
2bd7f1f3 | 8501 | return; |
252b5132 | 8502 | } |
252b5132 RH |
8503 | } |
8504 | ||
1e915849 | 8505 | create_insn (ip, insn); |
268f6bed | 8506 | insn_error = NULL; |
707bfff6 | 8507 | argnum = 1; |
252b5132 RH |
8508 | for (args = insn->args;; ++args) |
8509 | { | |
deec1734 CD |
8510 | int is_mdmx; |
8511 | ||
ad8d3bb3 | 8512 | s += strspn (s, " \t"); |
deec1734 | 8513 | is_mdmx = 0; |
252b5132 RH |
8514 | switch (*args) |
8515 | { | |
8516 | case '\0': /* end of args */ | |
8517 | if (*s == '\0') | |
8518 | return; | |
8519 | break; | |
8520 | ||
8b082fb1 TS |
8521 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8522 | my_getExpression (&imm_expr, s); | |
8523 | check_absolute_expr (ip, &imm_expr); | |
8524 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8525 | && (unsigned long) imm_expr.X_add_number != 3) | |
8526 | { | |
8527 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8528 | (unsigned long) imm_expr.X_add_number); | |
8529 | } | |
8530 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8531 | imm_expr.X_op = O_absent; | |
8532 | s = expr_end; | |
8533 | continue; | |
8534 | ||
74cd071d CF |
8535 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8536 | my_getExpression (&imm_expr, s); | |
8537 | check_absolute_expr (ip, &imm_expr); | |
8538 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8539 | { | |
a9e24354 TS |
8540 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8541 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8542 | } |
a9e24354 | 8543 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8544 | imm_expr.X_op = O_absent; |
8545 | s = expr_end; | |
8546 | continue; | |
8547 | ||
8548 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8549 | my_getExpression (&imm_expr, s); | |
8550 | check_absolute_expr (ip, &imm_expr); | |
8551 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8552 | { | |
a9e24354 TS |
8553 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8554 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8555 | } |
a9e24354 | 8556 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8557 | imm_expr.X_op = O_absent; |
8558 | s = expr_end; | |
8559 | continue; | |
8560 | ||
8561 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8562 | my_getExpression (&imm_expr, s); | |
8563 | check_absolute_expr (ip, &imm_expr); | |
8564 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8565 | { | |
a9e24354 TS |
8566 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8567 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8568 | } |
a9e24354 | 8569 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8570 | imm_expr.X_op = O_absent; |
8571 | s = expr_end; | |
8572 | continue; | |
8573 | ||
8574 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8575 | my_getExpression (&imm_expr, s); | |
8576 | check_absolute_expr (ip, &imm_expr); | |
8577 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8578 | { | |
a9e24354 TS |
8579 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8580 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8581 | } |
a9e24354 | 8582 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8583 | imm_expr.X_op = O_absent; |
8584 | s = expr_end; | |
8585 | continue; | |
8586 | ||
8587 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8588 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8589 | s[3] >= '0' && s[3] <= '3') | |
8590 | { | |
8591 | regno = s[3] - '0'; | |
8592 | s += 4; | |
a9e24354 | 8593 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8594 | continue; |
8595 | } | |
8596 | else | |
8597 | as_bad (_("Invalid dsp acc register")); | |
8598 | break; | |
8599 | ||
8600 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8601 | my_getExpression (&imm_expr, s); | |
8602 | check_absolute_expr (ip, &imm_expr); | |
8603 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8604 | { | |
a9e24354 TS |
8605 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8606 | OP_MASK_WRDSP, | |
8607 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8608 | } |
a9e24354 | 8609 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8610 | imm_expr.X_op = O_absent; |
8611 | s = expr_end; | |
8612 | continue; | |
8613 | ||
8614 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8615 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8616 | s[3] >= '0' && s[3] <= '3') | |
8617 | { | |
8618 | regno = s[3] - '0'; | |
8619 | s += 4; | |
a9e24354 | 8620 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8621 | continue; |
8622 | } | |
8623 | else | |
8624 | as_bad (_("Invalid dsp acc register")); | |
8625 | break; | |
8626 | ||
8627 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8628 | my_getExpression (&imm_expr, s); | |
8629 | check_absolute_expr (ip, &imm_expr); | |
8630 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8631 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8632 | if (imm_expr.X_add_number < min_range || | |
8633 | imm_expr.X_add_number > max_range) | |
8634 | { | |
a9e24354 TS |
8635 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8636 | (long) min_range, (long) max_range, | |
8637 | (long) imm_expr.X_add_number); | |
74cd071d | 8638 | } |
a9e24354 | 8639 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8640 | imm_expr.X_op = O_absent; |
8641 | s = expr_end; | |
8642 | continue; | |
8643 | ||
8644 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8645 | my_getExpression (&imm_expr, s); | |
8646 | check_absolute_expr (ip, &imm_expr); | |
8647 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8648 | { | |
a9e24354 TS |
8649 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8650 | OP_MASK_RDDSP, | |
8651 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8652 | } |
a9e24354 | 8653 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8654 | imm_expr.X_op = O_absent; |
8655 | s = expr_end; | |
8656 | continue; | |
8657 | ||
8658 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8659 | my_getExpression (&imm_expr, s); | |
8660 | check_absolute_expr (ip, &imm_expr); | |
8661 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8662 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8663 | if (imm_expr.X_add_number < min_range || | |
8664 | imm_expr.X_add_number > max_range) | |
8665 | { | |
a9e24354 TS |
8666 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8667 | (long) min_range, (long) max_range, | |
8668 | (long) imm_expr.X_add_number); | |
74cd071d | 8669 | } |
a9e24354 | 8670 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8671 | imm_expr.X_op = O_absent; |
8672 | s = expr_end; | |
8673 | continue; | |
8674 | ||
8675 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8676 | my_getExpression (&imm_expr, s); | |
8677 | check_absolute_expr (ip, &imm_expr); | |
8678 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8679 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8680 | if (imm_expr.X_add_number < min_range || | |
8681 | imm_expr.X_add_number > max_range) | |
8682 | { | |
a9e24354 TS |
8683 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8684 | (long) min_range, (long) max_range, | |
8685 | (long) imm_expr.X_add_number); | |
74cd071d | 8686 | } |
a9e24354 | 8687 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8688 | imm_expr.X_op = O_absent; |
8689 | s = expr_end; | |
8690 | continue; | |
8691 | ||
a9e24354 | 8692 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8693 | my_getExpression (&imm_expr, s); |
8694 | check_absolute_expr (ip, &imm_expr); | |
8695 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8696 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8697 | (unsigned long) imm_expr.X_add_number); | |
8698 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8699 | imm_expr.X_op = O_absent; |
8700 | s = expr_end; | |
8701 | continue; | |
8702 | ||
a9e24354 | 8703 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8704 | my_getExpression (&imm_expr, s); |
8705 | check_absolute_expr (ip, &imm_expr); | |
8706 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8707 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8708 | (unsigned long) imm_expr.X_add_number); | |
8709 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8710 | imm_expr.X_op = O_absent; |
8711 | s = expr_end; | |
8712 | continue; | |
8713 | ||
8714 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8715 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8716 | s[3] >= '0' && s[3] <= '3') | |
8717 | { | |
8718 | regno = s[3] - '0'; | |
8719 | s += 4; | |
a9e24354 | 8720 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8721 | continue; |
8722 | } | |
8723 | else | |
8724 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8725 | break; | |
8726 | ||
8727 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8728 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8729 | s[3] >= '0' && s[3] <= '3') | |
8730 | { | |
8731 | regno = s[3] - '0'; | |
8732 | s += 4; | |
a9e24354 | 8733 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8734 | continue; |
8735 | } | |
8736 | else | |
8737 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8738 | break; | |
8739 | ||
252b5132 | 8740 | case ',': |
a339155f | 8741 | ++argnum; |
252b5132 RH |
8742 | if (*s++ == *args) |
8743 | continue; | |
8744 | s--; | |
8745 | switch (*++args) | |
8746 | { | |
8747 | case 'r': | |
8748 | case 'v': | |
bf12938e | 8749 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8750 | continue; |
8751 | ||
8752 | case 'w': | |
bf12938e | 8753 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8754 | continue; |
8755 | ||
252b5132 | 8756 | case 'W': |
bf12938e | 8757 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8758 | continue; |
8759 | ||
8760 | case 'V': | |
bf12938e | 8761 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8762 | continue; |
8763 | } | |
8764 | break; | |
8765 | ||
8766 | case '(': | |
8767 | /* Handle optional base register. | |
8768 | Either the base register is omitted or | |
bdaaa2e1 | 8769 | we must have a left paren. */ |
252b5132 RH |
8770 | /* This is dependent on the next operand specifier |
8771 | is a base register specification. */ | |
8772 | assert (args[1] == 'b' || args[1] == '5' | |
8773 | || args[1] == '-' || args[1] == '4'); | |
8774 | if (*s == '\0') | |
8775 | return; | |
8776 | ||
8777 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8778 | case '[': |
8779 | case ']': | |
252b5132 RH |
8780 | if (*s++ == *args) |
8781 | continue; | |
8782 | break; | |
8783 | ||
af7ee8bf CD |
8784 | case '+': /* Opcode extension character. */ |
8785 | switch (*++args) | |
8786 | { | |
9bcd4f99 TS |
8787 | case '1': /* UDI immediates. */ |
8788 | case '2': | |
8789 | case '3': | |
8790 | case '4': | |
8791 | { | |
8792 | const struct mips_immed *imm = mips_immed; | |
8793 | ||
8794 | while (imm->type && imm->type != *args) | |
8795 | ++imm; | |
8796 | if (! imm->type) | |
8797 | internalError (); | |
8798 | my_getExpression (&imm_expr, s); | |
8799 | check_absolute_expr (ip, &imm_expr); | |
8800 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8801 | { | |
8802 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8803 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8804 | (unsigned long) imm_expr.X_add_number, | |
8805 | (unsigned long) imm_expr.X_add_number); | |
8806 | imm_expr.X_add_number &= imm->mask; | |
8807 | } | |
8808 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8809 | << imm->shift); | |
8810 | imm_expr.X_op = O_absent; | |
8811 | s = expr_end; | |
8812 | } | |
8813 | continue; | |
8814 | ||
071742cf CD |
8815 | case 'A': /* ins/ext position, becomes LSB. */ |
8816 | limlo = 0; | |
8817 | limhi = 31; | |
5f74bc13 CD |
8818 | goto do_lsb; |
8819 | case 'E': | |
8820 | limlo = 32; | |
8821 | limhi = 63; | |
8822 | goto do_lsb; | |
8823 | do_lsb: | |
071742cf CD |
8824 | my_getExpression (&imm_expr, s); |
8825 | check_absolute_expr (ip, &imm_expr); | |
8826 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8827 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8828 | { | |
8829 | as_bad (_("Improper position (%lu)"), | |
8830 | (unsigned long) imm_expr.X_add_number); | |
8831 | imm_expr.X_add_number = limlo; | |
8832 | } | |
8833 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8834 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8835 | imm_expr.X_op = O_absent; |
8836 | s = expr_end; | |
8837 | continue; | |
8838 | ||
8839 | case 'B': /* ins size, becomes MSB. */ | |
8840 | limlo = 1; | |
8841 | limhi = 32; | |
5f74bc13 CD |
8842 | goto do_msb; |
8843 | case 'F': | |
8844 | limlo = 33; | |
8845 | limhi = 64; | |
8846 | goto do_msb; | |
8847 | do_msb: | |
071742cf CD |
8848 | my_getExpression (&imm_expr, s); |
8849 | check_absolute_expr (ip, &imm_expr); | |
8850 | /* Check for negative input so that small negative numbers | |
8851 | will not succeed incorrectly. The checks against | |
8852 | (pos+size) transitively check "size" itself, | |
8853 | assuming that "pos" is reasonable. */ | |
8854 | if ((long) imm_expr.X_add_number < 0 | |
8855 | || ((unsigned long) imm_expr.X_add_number | |
8856 | + lastpos) < limlo | |
8857 | || ((unsigned long) imm_expr.X_add_number | |
8858 | + lastpos) > limhi) | |
8859 | { | |
8860 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8861 | (unsigned long) imm_expr.X_add_number, | |
8862 | (unsigned long) lastpos); | |
8863 | imm_expr.X_add_number = limlo - lastpos; | |
8864 | } | |
bf12938e RS |
8865 | INSERT_OPERAND (INSMSB, *ip, |
8866 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8867 | imm_expr.X_op = O_absent; |
8868 | s = expr_end; | |
8869 | continue; | |
8870 | ||
8871 | case 'C': /* ext size, becomes MSBD. */ | |
8872 | limlo = 1; | |
8873 | limhi = 32; | |
5f74bc13 CD |
8874 | goto do_msbd; |
8875 | case 'G': | |
8876 | limlo = 33; | |
8877 | limhi = 64; | |
8878 | goto do_msbd; | |
8879 | case 'H': | |
8880 | limlo = 33; | |
8881 | limhi = 64; | |
8882 | goto do_msbd; | |
8883 | do_msbd: | |
071742cf CD |
8884 | my_getExpression (&imm_expr, s); |
8885 | check_absolute_expr (ip, &imm_expr); | |
8886 | /* Check for negative input so that small negative numbers | |
8887 | will not succeed incorrectly. The checks against | |
8888 | (pos+size) transitively check "size" itself, | |
8889 | assuming that "pos" is reasonable. */ | |
8890 | if ((long) imm_expr.X_add_number < 0 | |
8891 | || ((unsigned long) imm_expr.X_add_number | |
8892 | + lastpos) < limlo | |
8893 | || ((unsigned long) imm_expr.X_add_number | |
8894 | + lastpos) > limhi) | |
8895 | { | |
8896 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8897 | (unsigned long) imm_expr.X_add_number, | |
8898 | (unsigned long) lastpos); | |
8899 | imm_expr.X_add_number = limlo - lastpos; | |
8900 | } | |
bf12938e | 8901 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8902 | imm_expr.X_op = O_absent; |
8903 | s = expr_end; | |
8904 | continue; | |
af7ee8bf | 8905 | |
bbcc0807 CD |
8906 | case 'D': |
8907 | /* +D is for disassembly only; never match. */ | |
8908 | break; | |
8909 | ||
5f74bc13 CD |
8910 | case 'I': |
8911 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8912 | my_getExpression (&imm2_expr, s); | |
8913 | if (imm2_expr.X_op != O_big | |
8914 | && imm2_expr.X_op != O_constant) | |
8915 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8916 | if (HAVE_32BIT_GPRS) |
8917 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8918 | s = expr_end; |
8919 | continue; | |
8920 | ||
707bfff6 | 8921 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8922 | /* +T is for disassembly only; never match. */ |
8923 | break; | |
8924 | ||
707bfff6 | 8925 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8926 | if (s[0] == '$' && ISDIGIT (s[1])) |
8927 | { | |
8928 | ++s; | |
8929 | regno = 0; | |
8930 | do | |
8931 | { | |
8932 | regno *= 10; | |
8933 | regno += *s - '0'; | |
8934 | ++s; | |
8935 | } | |
8936 | while (ISDIGIT (*s)); | |
8937 | if (regno > 31) | |
8938 | as_bad (_("Invalid register number (%d)"), regno); | |
8939 | else | |
8940 | { | |
a9e24354 | 8941 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8942 | continue; |
8943 | } | |
8944 | } | |
8945 | else | |
8946 | as_bad (_("Invalid coprocessor 0 register number")); | |
8947 | break; | |
8948 | ||
af7ee8bf CD |
8949 | default: |
8950 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8951 | *args, insn->name, insn->args); | |
8952 | /* Further processing is fruitless. */ | |
8953 | return; | |
8954 | } | |
8955 | break; | |
8956 | ||
252b5132 RH |
8957 | case '<': /* must be at least one digit */ |
8958 | /* | |
8959 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8960 | * than 31 or less than 0, then the shift amount should be |
8961 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8962 | * We issue a warning and mask out all but the low 5 bits. |
8963 | */ | |
8964 | my_getExpression (&imm_expr, s); | |
8965 | check_absolute_expr (ip, &imm_expr); | |
8966 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8967 | as_warn (_("Improper shift amount (%lu)"), |
8968 | (unsigned long) imm_expr.X_add_number); | |
8969 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8970 | imm_expr.X_op = O_absent; |
8971 | s = expr_end; | |
8972 | continue; | |
8973 | ||
8974 | case '>': /* shift amount minus 32 */ | |
8975 | my_getExpression (&imm_expr, s); | |
8976 | check_absolute_expr (ip, &imm_expr); | |
8977 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8978 | || (unsigned long) imm_expr.X_add_number > 63) | |
8979 | break; | |
bf12938e | 8980 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8981 | imm_expr.X_op = O_absent; |
8982 | s = expr_end; | |
8983 | continue; | |
8984 | ||
252b5132 RH |
8985 | case 'k': /* cache code */ |
8986 | case 'h': /* prefx code */ | |
8987 | my_getExpression (&imm_expr, s); | |
8988 | check_absolute_expr (ip, &imm_expr); | |
8989 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8990 | as_warn (_("Invalid value for `%s' (%lu)"), |
8991 | ip->insn_mo->name, | |
8992 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8993 | if (*args == 'k') |
bf12938e | 8994 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8995 | else |
bf12938e | 8996 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8997 | imm_expr.X_op = O_absent; |
8998 | s = expr_end; | |
8999 | continue; | |
9000 | ||
9001 | case 'c': /* break code */ | |
9002 | my_getExpression (&imm_expr, s); | |
9003 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9004 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9005 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9006 | ip->insn_mo->name, | |
bf12938e RS |
9007 | (unsigned long) imm_expr.X_add_number); |
9008 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9009 | imm_expr.X_op = O_absent; |
9010 | s = expr_end; | |
9011 | continue; | |
9012 | ||
9013 | case 'q': /* lower break code */ | |
9014 | my_getExpression (&imm_expr, s); | |
9015 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9016 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9017 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9018 | ip->insn_mo->name, | |
bf12938e RS |
9019 | (unsigned long) imm_expr.X_add_number); |
9020 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9021 | imm_expr.X_op = O_absent; |
9022 | s = expr_end; | |
9023 | continue; | |
9024 | ||
4372b673 | 9025 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9026 | my_getExpression (&imm_expr, s); |
156c2f8b | 9027 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9028 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9029 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9030 | ip->insn_mo->name, | |
793b27f4 | 9031 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9032 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9033 | imm_expr.X_op = O_absent; |
9034 | s = expr_end; | |
9035 | continue; | |
9036 | ||
98d3f06f | 9037 | case 'C': /* Coprocessor code */ |
beae10d5 | 9038 | my_getExpression (&imm_expr, s); |
252b5132 | 9039 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9040 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9041 | { |
793b27f4 TS |
9042 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9043 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9044 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9045 | } |
a9e24354 | 9046 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9047 | imm_expr.X_op = O_absent; |
9048 | s = expr_end; | |
9049 | continue; | |
252b5132 | 9050 | |
4372b673 NC |
9051 | case 'J': /* 19-bit wait code. */ |
9052 | my_getExpression (&imm_expr, s); | |
9053 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9054 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9055 | { |
9056 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9057 | (unsigned long) imm_expr.X_add_number); | |
9058 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9059 | } | |
bf12938e | 9060 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9061 | imm_expr.X_op = O_absent; |
9062 | s = expr_end; | |
9063 | continue; | |
9064 | ||
707bfff6 | 9065 | case 'P': /* Performance register. */ |
beae10d5 | 9066 | my_getExpression (&imm_expr, s); |
252b5132 | 9067 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9068 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9069 | as_warn (_("Invalid performance register (%lu)"), |
9070 | (unsigned long) imm_expr.X_add_number); | |
9071 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9072 | imm_expr.X_op = O_absent; |
9073 | s = expr_end; | |
9074 | continue; | |
252b5132 | 9075 | |
707bfff6 TS |
9076 | case 'G': /* Coprocessor destination register. */ |
9077 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9078 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9079 | else | |
9080 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9081 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9082 | if (ok) |
9083 | { | |
9084 | lastregno = regno; | |
9085 | continue; | |
9086 | } | |
9087 | else | |
9088 | break; | |
9089 | ||
252b5132 RH |
9090 | case 'b': /* base register */ |
9091 | case 'd': /* destination register */ | |
9092 | case 's': /* source register */ | |
9093 | case 't': /* target register */ | |
9094 | case 'r': /* both target and source */ | |
9095 | case 'v': /* both dest and source */ | |
9096 | case 'w': /* both dest and target */ | |
9097 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9098 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9099 | case 'x': /* ignore register name */ |
9100 | case 'z': /* must be zero register */ | |
4372b673 | 9101 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9102 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9103 | s_reset = s; |
9104 | if (*args == 'E' || *args == 'K') | |
9105 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9106 | else | |
9107 | { | |
9108 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9109 | if (regno == AT && mips_opts.at) |
9110 | { | |
9111 | if (mips_opts.at == ATREG) | |
9112 | as_warn (_("used $at without \".set noat\"")); | |
9113 | else | |
9114 | as_warn (_("used $%u with \".set at=$%u\""), | |
9115 | regno, mips_opts.at); | |
9116 | } | |
707bfff6 TS |
9117 | } |
9118 | if (ok) | |
252b5132 | 9119 | { |
252b5132 RH |
9120 | c = *args; |
9121 | if (*s == ' ') | |
f9419b05 | 9122 | ++s; |
252b5132 RH |
9123 | if (args[1] != *s) |
9124 | { | |
9125 | if (c == 'r' || c == 'v' || c == 'w') | |
9126 | { | |
9127 | regno = lastregno; | |
9128 | s = s_reset; | |
f9419b05 | 9129 | ++args; |
252b5132 RH |
9130 | } |
9131 | } | |
9132 | /* 'z' only matches $0. */ | |
9133 | if (c == 'z' && regno != 0) | |
9134 | break; | |
9135 | ||
bdaaa2e1 KH |
9136 | /* Now that we have assembled one operand, we use the args string |
9137 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9138 | switch (c) |
9139 | { | |
9140 | case 'r': | |
9141 | case 's': | |
9142 | case 'v': | |
9143 | case 'b': | |
bf12938e | 9144 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9145 | break; |
9146 | case 'd': | |
9147 | case 'G': | |
af7ee8bf | 9148 | case 'K': |
ef2e4d86 | 9149 | case 'g': |
bf12938e | 9150 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9151 | break; |
4372b673 | 9152 | case 'U': |
bf12938e RS |
9153 | INSERT_OPERAND (RD, *ip, regno); |
9154 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9155 | break; |
252b5132 RH |
9156 | case 'w': |
9157 | case 't': | |
9158 | case 'E': | |
bf12938e | 9159 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9160 | break; |
9161 | case 'x': | |
9162 | /* This case exists because on the r3000 trunc | |
9163 | expands into a macro which requires a gp | |
9164 | register. On the r6000 or r4000 it is | |
9165 | assembled into a single instruction which | |
9166 | ignores the register. Thus the insn version | |
9167 | is MIPS_ISA2 and uses 'x', and the macro | |
9168 | version is MIPS_ISA1 and uses 't'. */ | |
9169 | break; | |
9170 | case 'z': | |
9171 | /* This case is for the div instruction, which | |
9172 | acts differently if the destination argument | |
9173 | is $0. This only matches $0, and is checked | |
9174 | outside the switch. */ | |
9175 | break; | |
9176 | case 'D': | |
9177 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9178 | break; | |
9179 | /* What about all other operands like 'i', which | |
9180 | can be specified in the opcode table? */ | |
9181 | } | |
9182 | lastregno = regno; | |
9183 | continue; | |
9184 | } | |
252b5132 RH |
9185 | switch (*args++) |
9186 | { | |
9187 | case 'r': | |
9188 | case 'v': | |
bf12938e | 9189 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9190 | continue; |
9191 | case 'w': | |
bf12938e | 9192 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9193 | continue; |
9194 | } | |
9195 | break; | |
9196 | ||
deec1734 CD |
9197 | case 'O': /* MDMX alignment immediate constant. */ |
9198 | my_getExpression (&imm_expr, s); | |
9199 | check_absolute_expr (ip, &imm_expr); | |
9200 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9201 | as_warn ("Improper align amount (%ld), using low bits", |
9202 | (long) imm_expr.X_add_number); | |
9203 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9204 | imm_expr.X_op = O_absent; |
9205 | s = expr_end; | |
9206 | continue; | |
9207 | ||
9208 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9209 | if (s[0] != '$') | |
9210 | { | |
9211 | /* MDMX Immediate. */ | |
9212 | my_getExpression (&imm_expr, s); | |
9213 | check_absolute_expr (ip, &imm_expr); | |
9214 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9215 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9216 | (long) imm_expr.X_add_number); | |
9217 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9218 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9219 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9220 | else | |
9221 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9222 | imm_expr.X_op = O_absent; |
9223 | s = expr_end; | |
9224 | continue; | |
9225 | } | |
9226 | /* Not MDMX Immediate. Fall through. */ | |
9227 | case 'X': /* MDMX destination register. */ | |
9228 | case 'Y': /* MDMX source register. */ | |
9229 | case 'Z': /* MDMX target register. */ | |
9230 | is_mdmx = 1; | |
252b5132 RH |
9231 | case 'D': /* floating point destination register */ |
9232 | case 'S': /* floating point source register */ | |
9233 | case 'T': /* floating point target register */ | |
9234 | case 'R': /* floating point source register */ | |
9235 | case 'V': | |
9236 | case 'W': | |
707bfff6 TS |
9237 | rtype = RTYPE_FPU; |
9238 | if (is_mdmx | |
9239 | || (mips_opts.ase_mdmx | |
9240 | && (ip->insn_mo->pinfo & FP_D) | |
9241 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9242 | | INSN_COPROC_MEMORY_DELAY | |
9243 | | INSN_LOAD_COPROC_DELAY | |
9244 | | INSN_LOAD_MEMORY_DELAY | |
9245 | | INSN_STORE_MEMORY)))) | |
9246 | rtype |= RTYPE_VEC; | |
252b5132 | 9247 | s_reset = s; |
707bfff6 | 9248 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9249 | { |
252b5132 | 9250 | if ((regno & 1) != 0 |
ca4e0257 | 9251 | && HAVE_32BIT_FPRS |
7455baf8 | 9252 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9253 | as_warn (_("Float register should be even, was %d"), |
9254 | regno); | |
9255 | ||
9256 | c = *args; | |
9257 | if (*s == ' ') | |
f9419b05 | 9258 | ++s; |
252b5132 RH |
9259 | if (args[1] != *s) |
9260 | { | |
9261 | if (c == 'V' || c == 'W') | |
9262 | { | |
9263 | regno = lastregno; | |
9264 | s = s_reset; | |
f9419b05 | 9265 | ++args; |
252b5132 RH |
9266 | } |
9267 | } | |
9268 | switch (c) | |
9269 | { | |
9270 | case 'D': | |
deec1734 | 9271 | case 'X': |
bf12938e | 9272 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9273 | break; |
9274 | case 'V': | |
9275 | case 'S': | |
deec1734 | 9276 | case 'Y': |
bf12938e | 9277 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9278 | break; |
deec1734 CD |
9279 | case 'Q': |
9280 | /* This is like 'Z', but also needs to fix the MDMX | |
9281 | vector/scalar select bits. Note that the | |
9282 | scalar immediate case is handled above. */ | |
9283 | if (*s == '[') | |
9284 | { | |
9285 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9286 | int max_el = (is_qh ? 3 : 7); | |
9287 | s++; | |
9288 | my_getExpression(&imm_expr, s); | |
9289 | check_absolute_expr (ip, &imm_expr); | |
9290 | s = expr_end; | |
9291 | if (imm_expr.X_add_number > max_el) | |
9292 | as_bad(_("Bad element selector %ld"), | |
9293 | (long) imm_expr.X_add_number); | |
9294 | imm_expr.X_add_number &= max_el; | |
9295 | ip->insn_opcode |= (imm_expr.X_add_number | |
9296 | << (OP_SH_VSEL + | |
9297 | (is_qh ? 2 : 1))); | |
01a3f561 | 9298 | imm_expr.X_op = O_absent; |
deec1734 CD |
9299 | if (*s != ']') |
9300 | as_warn(_("Expecting ']' found '%s'"), s); | |
9301 | else | |
9302 | s++; | |
9303 | } | |
9304 | else | |
9305 | { | |
9306 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9307 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9308 | << OP_SH_VSEL); | |
9309 | else | |
9310 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9311 | OP_SH_VSEL); | |
9312 | } | |
9313 | /* Fall through */ | |
252b5132 RH |
9314 | case 'W': |
9315 | case 'T': | |
deec1734 | 9316 | case 'Z': |
bf12938e | 9317 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9318 | break; |
9319 | case 'R': | |
bf12938e | 9320 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9321 | break; |
9322 | } | |
9323 | lastregno = regno; | |
9324 | continue; | |
9325 | } | |
9326 | ||
252b5132 RH |
9327 | switch (*args++) |
9328 | { | |
9329 | case 'V': | |
bf12938e | 9330 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9331 | continue; |
9332 | case 'W': | |
bf12938e | 9333 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9334 | continue; |
9335 | } | |
9336 | break; | |
9337 | ||
9338 | case 'I': | |
9339 | my_getExpression (&imm_expr, s); | |
9340 | if (imm_expr.X_op != O_big | |
9341 | && imm_expr.X_op != O_constant) | |
9342 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9343 | if (HAVE_32BIT_GPRS) |
9344 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9345 | s = expr_end; |
9346 | continue; | |
9347 | ||
9348 | case 'A': | |
9349 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9350 | normalize_address_expr (&offset_expr); |
f6688943 | 9351 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9352 | s = expr_end; |
9353 | continue; | |
9354 | ||
9355 | case 'F': | |
9356 | case 'L': | |
9357 | case 'f': | |
9358 | case 'l': | |
9359 | { | |
9360 | int f64; | |
ca4e0257 | 9361 | int using_gprs; |
252b5132 RH |
9362 | char *save_in; |
9363 | char *err; | |
9364 | unsigned char temp[8]; | |
9365 | int len; | |
9366 | unsigned int length; | |
9367 | segT seg; | |
9368 | subsegT subseg; | |
9369 | char *p; | |
9370 | ||
9371 | /* These only appear as the last operand in an | |
9372 | instruction, and every instruction that accepts | |
9373 | them in any variant accepts them in all variants. | |
9374 | This means we don't have to worry about backing out | |
9375 | any changes if the instruction does not match. | |
9376 | ||
9377 | The difference between them is the size of the | |
9378 | floating point constant and where it goes. For 'F' | |
9379 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9380 | is 32 bits. Where the constant is placed is based | |
9381 | on how the MIPS assembler does things: | |
9382 | F -- .rdata | |
9383 | L -- .lit8 | |
9384 | f -- immediate value | |
9385 | l -- .lit4 | |
9386 | ||
9387 | The .lit4 and .lit8 sections are only used if | |
9388 | permitted by the -G argument. | |
9389 | ||
ca4e0257 RS |
9390 | The code below needs to know whether the target register |
9391 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9392 | 'F' are used with GPR-based instructions and 'l' and | |
9393 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9394 | |
9395 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9396 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9397 | |
9398 | save_in = input_line_pointer; | |
9399 | input_line_pointer = s; | |
9400 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9401 | length = len; | |
9402 | s = input_line_pointer; | |
9403 | input_line_pointer = save_in; | |
9404 | if (err != NULL && *err != '\0') | |
9405 | { | |
9406 | as_bad (_("Bad floating point constant: %s"), err); | |
9407 | memset (temp, '\0', sizeof temp); | |
9408 | length = f64 ? 8 : 4; | |
9409 | } | |
9410 | ||
156c2f8b | 9411 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9412 | |
9413 | if (*args == 'f' | |
9414 | || (*args == 'l' | |
3e722fb5 | 9415 | && (g_switch_value < 4 |
252b5132 RH |
9416 | || (temp[0] == 0 && temp[1] == 0) |
9417 | || (temp[2] == 0 && temp[3] == 0)))) | |
9418 | { | |
9419 | imm_expr.X_op = O_constant; | |
9420 | if (! target_big_endian) | |
9421 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9422 | else | |
9423 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9424 | } | |
9425 | else if (length > 4 | |
119d663a | 9426 | && ! mips_disable_float_construction |
ca4e0257 RS |
9427 | /* Constants can only be constructed in GPRs and |
9428 | copied to FPRs if the GPRs are at least as wide | |
9429 | as the FPRs. Force the constant into memory if | |
9430 | we are using 64-bit FPRs but the GPRs are only | |
9431 | 32 bits wide. */ | |
9432 | && (using_gprs | |
9433 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9434 | && ((temp[0] == 0 && temp[1] == 0) |
9435 | || (temp[2] == 0 && temp[3] == 0)) | |
9436 | && ((temp[4] == 0 && temp[5] == 0) | |
9437 | || (temp[6] == 0 && temp[7] == 0))) | |
9438 | { | |
ca4e0257 RS |
9439 | /* The value is simple enough to load with a couple of |
9440 | instructions. If using 32-bit registers, set | |
9441 | imm_expr to the high order 32 bits and offset_expr to | |
9442 | the low order 32 bits. Otherwise, set imm_expr to | |
9443 | the entire 64 bit constant. */ | |
9444 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9445 | { |
9446 | imm_expr.X_op = O_constant; | |
9447 | offset_expr.X_op = O_constant; | |
9448 | if (! target_big_endian) | |
9449 | { | |
9450 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9451 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9452 | } | |
9453 | else | |
9454 | { | |
9455 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9456 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9457 | } | |
9458 | if (offset_expr.X_add_number == 0) | |
9459 | offset_expr.X_op = O_absent; | |
9460 | } | |
9461 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9462 | { | |
9463 | imm_expr.X_op = O_constant; | |
9464 | if (! target_big_endian) | |
9465 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9466 | else | |
9467 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9468 | } | |
9469 | else | |
9470 | { | |
9471 | imm_expr.X_op = O_big; | |
9472 | imm_expr.X_add_number = 4; | |
9473 | if (! target_big_endian) | |
9474 | { | |
9475 | generic_bignum[0] = bfd_getl16 (temp); | |
9476 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9477 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9478 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9479 | } | |
9480 | else | |
9481 | { | |
9482 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9483 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9484 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9485 | generic_bignum[3] = bfd_getb16 (temp); | |
9486 | } | |
9487 | } | |
9488 | } | |
9489 | else | |
9490 | { | |
9491 | const char *newname; | |
9492 | segT new_seg; | |
9493 | ||
9494 | /* Switch to the right section. */ | |
9495 | seg = now_seg; | |
9496 | subseg = now_subseg; | |
9497 | switch (*args) | |
9498 | { | |
9499 | default: /* unused default case avoids warnings. */ | |
9500 | case 'L': | |
9501 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9502 | if (g_switch_value >= 8) |
252b5132 RH |
9503 | newname = ".lit8"; |
9504 | break; | |
9505 | case 'F': | |
3e722fb5 | 9506 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9507 | break; |
9508 | case 'l': | |
4d0d148d | 9509 | assert (g_switch_value >= 4); |
252b5132 RH |
9510 | newname = ".lit4"; |
9511 | break; | |
9512 | } | |
9513 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9514 | if (IS_ELF) |
252b5132 RH |
9515 | bfd_set_section_flags (stdoutput, new_seg, |
9516 | (SEC_ALLOC | |
9517 | | SEC_LOAD | |
9518 | | SEC_READONLY | |
9519 | | SEC_DATA)); | |
9520 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
f43abd2b | 9521 | if (IS_ELF && strcmp (TARGET_OS, "elf") != 0) |
252b5132 RH |
9522 | record_alignment (new_seg, 4); |
9523 | else | |
9524 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9525 | if (seg == now_seg) | |
9526 | as_bad (_("Can't use floating point insn in this section")); | |
9527 | ||
9528 | /* Set the argument to the current address in the | |
9529 | section. */ | |
9530 | offset_expr.X_op = O_symbol; | |
9531 | offset_expr.X_add_symbol = | |
9532 | symbol_new ("L0\001", now_seg, | |
9533 | (valueT) frag_now_fix (), frag_now); | |
9534 | offset_expr.X_add_number = 0; | |
9535 | ||
9536 | /* Put the floating point number into the section. */ | |
9537 | p = frag_more ((int) length); | |
9538 | memcpy (p, temp, length); | |
9539 | ||
9540 | /* Switch back to the original section. */ | |
9541 | subseg_set (seg, subseg); | |
9542 | } | |
9543 | } | |
9544 | continue; | |
9545 | ||
9546 | case 'i': /* 16 bit unsigned immediate */ | |
9547 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9548 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9549 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9550 | { |
9551 | int more; | |
5e0116d5 RS |
9552 | offsetT minval, maxval; |
9553 | ||
9554 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9555 | && strcmp (insn->name, insn[1].name) == 0); | |
9556 | ||
9557 | /* If the expression was written as an unsigned number, | |
9558 | only treat it as signed if there are no more | |
9559 | alternatives. */ | |
9560 | if (more | |
9561 | && *args == 'j' | |
9562 | && sizeof (imm_expr.X_add_number) <= 4 | |
9563 | && imm_expr.X_op == O_constant | |
9564 | && imm_expr.X_add_number < 0 | |
9565 | && imm_expr.X_unsigned | |
9566 | && HAVE_64BIT_GPRS) | |
9567 | break; | |
9568 | ||
9569 | /* For compatibility with older assemblers, we accept | |
9570 | 0x8000-0xffff as signed 16-bit numbers when only | |
9571 | signed numbers are allowed. */ | |
9572 | if (*args == 'i') | |
9573 | minval = 0, maxval = 0xffff; | |
9574 | else if (more) | |
9575 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9576 | else |
5e0116d5 RS |
9577 | minval = -0x8000, maxval = 0xffff; |
9578 | ||
9579 | if (imm_expr.X_op != O_constant | |
9580 | || imm_expr.X_add_number < minval | |
9581 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9582 | { |
9583 | if (more) | |
9584 | break; | |
2ae7e77b AH |
9585 | if (imm_expr.X_op == O_constant |
9586 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9587 | as_bad (_("expression out of range")); |
252b5132 RH |
9588 | } |
9589 | } | |
9590 | s = expr_end; | |
9591 | continue; | |
9592 | ||
9593 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9594 | /* Check whether there is only a single bracketed expression |
9595 | left. If so, it must be the base register and the | |
9596 | constant must be zero. */ | |
9597 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9598 | { | |
9599 | offset_expr.X_op = O_constant; | |
9600 | offset_expr.X_add_number = 0; | |
9601 | continue; | |
9602 | } | |
252b5132 RH |
9603 | |
9604 | /* If this value won't fit into a 16 bit offset, then go | |
9605 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9606 | code pattern. */ |
5e0116d5 | 9607 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9608 | && (offset_expr.X_op != O_constant |
9609 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9610 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9611 | break; |
9612 | ||
252b5132 RH |
9613 | s = expr_end; |
9614 | continue; | |
9615 | ||
9616 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9617 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9618 | my_getExpression (&offset_expr, s); |
9619 | s = expr_end; | |
9620 | continue; | |
9621 | ||
9622 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9623 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9624 | && imm_expr.X_op == O_constant | |
9625 | && (imm_expr.X_add_number < 0 | |
9626 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9627 | as_bad (_("lui expression not in range 0..65535")); |
9628 | s = expr_end; | |
9629 | continue; | |
9630 | ||
9631 | case 'a': /* 26 bit address */ | |
9632 | my_getExpression (&offset_expr, s); | |
9633 | s = expr_end; | |
f6688943 | 9634 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9635 | continue; |
9636 | ||
9637 | case 'N': /* 3 bit branch condition code */ | |
9638 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9639 | rtype = RTYPE_CCC; |
9640 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9641 | rtype |= RTYPE_FCC; | |
9642 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9643 | break; |
30c378fd CD |
9644 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9645 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9646 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9647 | && (regno & 1) != 0) | |
9648 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9649 | str, regno); | |
9650 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9651 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9652 | && (regno & 3) != 0) | |
9653 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9654 | str, regno); | |
252b5132 | 9655 | if (*args == 'N') |
bf12938e | 9656 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9657 | else |
bf12938e | 9658 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9659 | continue; |
252b5132 | 9660 | |
156c2f8b NC |
9661 | case 'H': |
9662 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9663 | s += 2; | |
3882b010 | 9664 | if (ISDIGIT (*s)) |
156c2f8b NC |
9665 | { |
9666 | c = 0; | |
9667 | do | |
9668 | { | |
9669 | c *= 10; | |
9670 | c += *s - '0'; | |
9671 | ++s; | |
9672 | } | |
3882b010 | 9673 | while (ISDIGIT (*s)); |
156c2f8b NC |
9674 | } |
9675 | else | |
9676 | c = 8; /* Invalid sel value. */ | |
9677 | ||
9678 | if (c > 7) | |
9679 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9680 | ip->insn_opcode |= c; | |
9681 | continue; | |
9682 | ||
60b63b72 RS |
9683 | case 'e': |
9684 | /* Must be at least one digit. */ | |
9685 | my_getExpression (&imm_expr, s); | |
9686 | check_absolute_expr (ip, &imm_expr); | |
9687 | ||
9688 | if ((unsigned long) imm_expr.X_add_number | |
9689 | > (unsigned long) OP_MASK_VECBYTE) | |
9690 | { | |
9691 | as_bad (_("bad byte vector index (%ld)"), | |
9692 | (long) imm_expr.X_add_number); | |
9693 | imm_expr.X_add_number = 0; | |
9694 | } | |
9695 | ||
bf12938e | 9696 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9697 | imm_expr.X_op = O_absent; |
9698 | s = expr_end; | |
9699 | continue; | |
9700 | ||
9701 | case '%': | |
9702 | my_getExpression (&imm_expr, s); | |
9703 | check_absolute_expr (ip, &imm_expr); | |
9704 | ||
9705 | if ((unsigned long) imm_expr.X_add_number | |
9706 | > (unsigned long) OP_MASK_VECALIGN) | |
9707 | { | |
9708 | as_bad (_("bad byte vector index (%ld)"), | |
9709 | (long) imm_expr.X_add_number); | |
9710 | imm_expr.X_add_number = 0; | |
9711 | } | |
9712 | ||
bf12938e | 9713 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9714 | imm_expr.X_op = O_absent; |
9715 | s = expr_end; | |
9716 | continue; | |
9717 | ||
252b5132 RH |
9718 | default: |
9719 | as_bad (_("bad char = '%c'\n"), *args); | |
9720 | internalError (); | |
9721 | } | |
9722 | break; | |
9723 | } | |
9724 | /* Args don't match. */ | |
9725 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9726 | !strcmp (insn->name, insn[1].name)) | |
9727 | { | |
9728 | ++insn; | |
9729 | s = argsStart; | |
268f6bed | 9730 | insn_error = _("illegal operands"); |
252b5132 RH |
9731 | continue; |
9732 | } | |
268f6bed L |
9733 | if (save_c) |
9734 | *(--s) = save_c; | |
252b5132 RH |
9735 | insn_error = _("illegal operands"); |
9736 | return; | |
9737 | } | |
9738 | } | |
9739 | ||
0499d65b TS |
9740 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9741 | ||
252b5132 RH |
9742 | /* This routine assembles an instruction into its binary format when |
9743 | assembling for the mips16. As a side effect, it sets one of the | |
9744 | global variables imm_reloc or offset_reloc to the type of | |
9745 | relocation to do if one of the operands is an address expression. | |
9746 | It also sets mips16_small and mips16_ext if the user explicitly | |
9747 | requested a small or extended instruction. */ | |
9748 | ||
9749 | static void | |
17a2f251 | 9750 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9751 | { |
9752 | char *s; | |
9753 | const char *args; | |
9754 | struct mips_opcode *insn; | |
9755 | char *argsstart; | |
9756 | unsigned int regno; | |
9757 | unsigned int lastregno = 0; | |
9758 | char *s_reset; | |
d6f16593 | 9759 | size_t i; |
252b5132 RH |
9760 | |
9761 | insn_error = NULL; | |
9762 | ||
b34976b6 AM |
9763 | mips16_small = FALSE; |
9764 | mips16_ext = FALSE; | |
252b5132 | 9765 | |
3882b010 | 9766 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9767 | ; |
9768 | switch (*s) | |
9769 | { | |
9770 | case '\0': | |
9771 | break; | |
9772 | ||
9773 | case ' ': | |
9774 | *s++ = '\0'; | |
9775 | break; | |
9776 | ||
9777 | case '.': | |
9778 | if (s[1] == 't' && s[2] == ' ') | |
9779 | { | |
9780 | *s = '\0'; | |
b34976b6 | 9781 | mips16_small = TRUE; |
252b5132 RH |
9782 | s += 3; |
9783 | break; | |
9784 | } | |
9785 | else if (s[1] == 'e' && s[2] == ' ') | |
9786 | { | |
9787 | *s = '\0'; | |
b34976b6 | 9788 | mips16_ext = TRUE; |
252b5132 RH |
9789 | s += 3; |
9790 | break; | |
9791 | } | |
9792 | /* Fall through. */ | |
9793 | default: | |
9794 | insn_error = _("unknown opcode"); | |
9795 | return; | |
9796 | } | |
9797 | ||
9798 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9799 | mips16_small = TRUE; |
252b5132 RH |
9800 | |
9801 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9802 | { | |
9803 | insn_error = _("unrecognized opcode"); | |
9804 | return; | |
9805 | } | |
9806 | ||
9807 | argsstart = s; | |
9808 | for (;;) | |
9809 | { | |
9b3f89ee TS |
9810 | bfd_boolean ok; |
9811 | ||
252b5132 RH |
9812 | assert (strcmp (insn->name, str) == 0); |
9813 | ||
9b3f89ee TS |
9814 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9815 | ok = TRUE; | |
9816 | else | |
9817 | ok = FALSE; | |
9818 | ||
9819 | if (! ok) | |
9820 | { | |
9821 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9822 | && strcmp (insn->name, insn[1].name) == 0) | |
9823 | { | |
9824 | ++insn; | |
9825 | continue; | |
9826 | } | |
9827 | else | |
9828 | { | |
9829 | if (!insn_error) | |
9830 | { | |
9831 | static char buf[100]; | |
9832 | sprintf (buf, | |
9833 | _("opcode not supported on this processor: %s (%s)"), | |
9834 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9835 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9836 | insn_error = buf; | |
9837 | } | |
9838 | return; | |
9839 | } | |
9840 | } | |
9841 | ||
1e915849 | 9842 | create_insn (ip, insn); |
252b5132 | 9843 | imm_expr.X_op = O_absent; |
f6688943 TS |
9844 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9845 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9846 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9847 | imm2_expr.X_op = O_absent; |
252b5132 | 9848 | offset_expr.X_op = O_absent; |
f6688943 TS |
9849 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9850 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9851 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9852 | for (args = insn->args; 1; ++args) |
9853 | { | |
9854 | int c; | |
9855 | ||
9856 | if (*s == ' ') | |
9857 | ++s; | |
9858 | ||
9859 | /* In this switch statement we call break if we did not find | |
9860 | a match, continue if we did find a match, or return if we | |
9861 | are done. */ | |
9862 | ||
9863 | c = *args; | |
9864 | switch (c) | |
9865 | { | |
9866 | case '\0': | |
9867 | if (*s == '\0') | |
9868 | { | |
9869 | /* Stuff the immediate value in now, if we can. */ | |
9870 | if (imm_expr.X_op == O_constant | |
f6688943 | 9871 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9872 | && insn->pinfo != INSN_MACRO) |
9873 | { | |
d6f16593 MR |
9874 | valueT tmp; |
9875 | ||
9876 | switch (*offset_reloc) | |
9877 | { | |
9878 | case BFD_RELOC_MIPS16_HI16_S: | |
9879 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9880 | break; | |
9881 | ||
9882 | case BFD_RELOC_MIPS16_HI16: | |
9883 | tmp = imm_expr.X_add_number >> 16; | |
9884 | break; | |
9885 | ||
9886 | case BFD_RELOC_MIPS16_LO16: | |
9887 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9888 | - 0x8000; | |
9889 | break; | |
9890 | ||
9891 | case BFD_RELOC_UNUSED: | |
9892 | tmp = imm_expr.X_add_number; | |
9893 | break; | |
9894 | ||
9895 | default: | |
9896 | internalError (); | |
9897 | } | |
9898 | *offset_reloc = BFD_RELOC_UNUSED; | |
9899 | ||
c4e7957c | 9900 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9901 | tmp, TRUE, mips16_small, |
252b5132 RH |
9902 | mips16_ext, &ip->insn_opcode, |
9903 | &ip->use_extend, &ip->extend); | |
9904 | imm_expr.X_op = O_absent; | |
f6688943 | 9905 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9906 | } |
9907 | ||
9908 | return; | |
9909 | } | |
9910 | break; | |
9911 | ||
9912 | case ',': | |
9913 | if (*s++ == c) | |
9914 | continue; | |
9915 | s--; | |
9916 | switch (*++args) | |
9917 | { | |
9918 | case 'v': | |
bf12938e | 9919 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9920 | continue; |
9921 | case 'w': | |
bf12938e | 9922 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9923 | continue; |
9924 | } | |
9925 | break; | |
9926 | ||
9927 | case '(': | |
9928 | case ')': | |
9929 | if (*s++ == c) | |
9930 | continue; | |
9931 | break; | |
9932 | ||
9933 | case 'v': | |
9934 | case 'w': | |
9935 | if (s[0] != '$') | |
9936 | { | |
9937 | if (c == 'v') | |
bf12938e | 9938 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9939 | else |
bf12938e | 9940 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9941 | ++args; |
9942 | continue; | |
9943 | } | |
9944 | /* Fall through. */ | |
9945 | case 'x': | |
9946 | case 'y': | |
9947 | case 'z': | |
9948 | case 'Z': | |
9949 | case '0': | |
9950 | case 'S': | |
9951 | case 'R': | |
9952 | case 'X': | |
9953 | case 'Y': | |
707bfff6 TS |
9954 | s_reset = s; |
9955 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9956 | { |
707bfff6 | 9957 | if (c == 'v' || c == 'w') |
85b51719 | 9958 | { |
707bfff6 | 9959 | if (c == 'v') |
a9e24354 | 9960 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9961 | else |
a9e24354 | 9962 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9963 | ++args; |
9964 | continue; | |
85b51719 | 9965 | } |
707bfff6 | 9966 | break; |
252b5132 RH |
9967 | } |
9968 | ||
9969 | if (*s == ' ') | |
9970 | ++s; | |
9971 | if (args[1] != *s) | |
9972 | { | |
9973 | if (c == 'v' || c == 'w') | |
9974 | { | |
9975 | regno = mips16_to_32_reg_map[lastregno]; | |
9976 | s = s_reset; | |
f9419b05 | 9977 | ++args; |
252b5132 RH |
9978 | } |
9979 | } | |
9980 | ||
9981 | switch (c) | |
9982 | { | |
9983 | case 'x': | |
9984 | case 'y': | |
9985 | case 'z': | |
9986 | case 'v': | |
9987 | case 'w': | |
9988 | case 'Z': | |
9989 | regno = mips32_to_16_reg_map[regno]; | |
9990 | break; | |
9991 | ||
9992 | case '0': | |
9993 | if (regno != 0) | |
9994 | regno = ILLEGAL_REG; | |
9995 | break; | |
9996 | ||
9997 | case 'S': | |
9998 | if (regno != SP) | |
9999 | regno = ILLEGAL_REG; | |
10000 | break; | |
10001 | ||
10002 | case 'R': | |
10003 | if (regno != RA) | |
10004 | regno = ILLEGAL_REG; | |
10005 | break; | |
10006 | ||
10007 | case 'X': | |
10008 | case 'Y': | |
741fe287 MR |
10009 | if (regno == AT && mips_opts.at) |
10010 | { | |
10011 | if (mips_opts.at == ATREG) | |
10012 | as_warn (_("used $at without \".set noat\"")); | |
10013 | else | |
10014 | as_warn (_("used $%u with \".set at=$%u\""), | |
10015 | regno, mips_opts.at); | |
10016 | } | |
252b5132 RH |
10017 | break; |
10018 | ||
10019 | default: | |
10020 | internalError (); | |
10021 | } | |
10022 | ||
10023 | if (regno == ILLEGAL_REG) | |
10024 | break; | |
10025 | ||
10026 | switch (c) | |
10027 | { | |
10028 | case 'x': | |
10029 | case 'v': | |
bf12938e | 10030 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10031 | break; |
10032 | case 'y': | |
10033 | case 'w': | |
bf12938e | 10034 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10035 | break; |
10036 | case 'z': | |
bf12938e | 10037 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10038 | break; |
10039 | case 'Z': | |
bf12938e | 10040 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10041 | case '0': |
10042 | case 'S': | |
10043 | case 'R': | |
10044 | break; | |
10045 | case 'X': | |
bf12938e | 10046 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10047 | break; |
10048 | case 'Y': | |
10049 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10050 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10051 | break; |
10052 | default: | |
10053 | internalError (); | |
10054 | } | |
10055 | ||
10056 | lastregno = regno; | |
10057 | continue; | |
10058 | ||
10059 | case 'P': | |
10060 | if (strncmp (s, "$pc", 3) == 0) | |
10061 | { | |
10062 | s += 3; | |
10063 | continue; | |
10064 | } | |
10065 | break; | |
10066 | ||
252b5132 RH |
10067 | case '5': |
10068 | case 'H': | |
10069 | case 'W': | |
10070 | case 'D': | |
10071 | case 'j': | |
252b5132 RH |
10072 | case 'V': |
10073 | case 'C': | |
10074 | case 'U': | |
10075 | case 'k': | |
10076 | case 'K': | |
d6f16593 MR |
10077 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10078 | if (i > 0) | |
252b5132 | 10079 | { |
d6f16593 | 10080 | if (imm_expr.X_op != O_constant) |
252b5132 | 10081 | { |
b34976b6 | 10082 | mips16_ext = TRUE; |
b34976b6 | 10083 | ip->use_extend = TRUE; |
252b5132 | 10084 | ip->extend = 0; |
252b5132 | 10085 | } |
d6f16593 MR |
10086 | else |
10087 | { | |
10088 | /* We need to relax this instruction. */ | |
10089 | *offset_reloc = *imm_reloc; | |
10090 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10091 | } | |
10092 | s = expr_end; | |
10093 | continue; | |
252b5132 | 10094 | } |
d6f16593 MR |
10095 | *imm_reloc = BFD_RELOC_UNUSED; |
10096 | /* Fall through. */ | |
10097 | case '<': | |
10098 | case '>': | |
10099 | case '[': | |
10100 | case ']': | |
10101 | case '4': | |
10102 | case '8': | |
10103 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10104 | if (imm_expr.X_op == O_register) |
10105 | { | |
10106 | /* What we thought was an expression turned out to | |
10107 | be a register. */ | |
10108 | ||
10109 | if (s[0] == '(' && args[1] == '(') | |
10110 | { | |
10111 | /* It looks like the expression was omitted | |
10112 | before a register indirection, which means | |
10113 | that the expression is implicitly zero. We | |
10114 | still set up imm_expr, so that we handle | |
10115 | explicit extensions correctly. */ | |
10116 | imm_expr.X_op = O_constant; | |
10117 | imm_expr.X_add_number = 0; | |
f6688943 | 10118 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10119 | continue; |
10120 | } | |
10121 | ||
10122 | break; | |
10123 | } | |
10124 | ||
10125 | /* We need to relax this instruction. */ | |
f6688943 | 10126 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10127 | s = expr_end; |
10128 | continue; | |
10129 | ||
10130 | case 'p': | |
10131 | case 'q': | |
10132 | case 'A': | |
10133 | case 'B': | |
10134 | case 'E': | |
10135 | /* We use offset_reloc rather than imm_reloc for the PC | |
10136 | relative operands. This lets macros with both | |
10137 | immediate and address operands work correctly. */ | |
10138 | my_getExpression (&offset_expr, s); | |
10139 | ||
10140 | if (offset_expr.X_op == O_register) | |
10141 | break; | |
10142 | ||
10143 | /* We need to relax this instruction. */ | |
f6688943 | 10144 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10145 | s = expr_end; |
10146 | continue; | |
10147 | ||
10148 | case '6': /* break code */ | |
10149 | my_getExpression (&imm_expr, s); | |
10150 | check_absolute_expr (ip, &imm_expr); | |
10151 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10152 | as_warn (_("Invalid value for `%s' (%lu)"), |
10153 | ip->insn_mo->name, | |
10154 | (unsigned long) imm_expr.X_add_number); | |
10155 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10156 | imm_expr.X_op = O_absent; |
10157 | s = expr_end; | |
10158 | continue; | |
10159 | ||
10160 | case 'a': /* 26 bit address */ | |
10161 | my_getExpression (&offset_expr, s); | |
10162 | s = expr_end; | |
f6688943 | 10163 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10164 | ip->insn_opcode <<= 16; |
10165 | continue; | |
10166 | ||
10167 | case 'l': /* register list for entry macro */ | |
10168 | case 'L': /* register list for exit macro */ | |
10169 | { | |
10170 | int mask; | |
10171 | ||
10172 | if (c == 'l') | |
10173 | mask = 0; | |
10174 | else | |
10175 | mask = 7 << 3; | |
10176 | while (*s != '\0') | |
10177 | { | |
707bfff6 | 10178 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10179 | |
10180 | while (*s == ' ' || *s == ',') | |
10181 | ++s; | |
707bfff6 | 10182 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10183 | freg = 0; |
707bfff6 TS |
10184 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10185 | freg = 1; | |
252b5132 RH |
10186 | else |
10187 | { | |
707bfff6 TS |
10188 | as_bad (_("can't parse register list")); |
10189 | break; | |
252b5132 RH |
10190 | } |
10191 | if (*s == ' ') | |
10192 | ++s; | |
10193 | if (*s != '-') | |
10194 | reg2 = reg1; | |
10195 | else | |
10196 | { | |
10197 | ++s; | |
707bfff6 TS |
10198 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10199 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10200 | { |
707bfff6 TS |
10201 | as_bad (_("invalid register list")); |
10202 | break; | |
252b5132 RH |
10203 | } |
10204 | } | |
10205 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10206 | { | |
10207 | mask &= ~ (7 << 3); | |
10208 | mask |= 5 << 3; | |
10209 | } | |
10210 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10211 | { | |
10212 | mask &= ~ (7 << 3); | |
10213 | mask |= 6 << 3; | |
10214 | } | |
10215 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10216 | mask |= (reg2 - 3) << 3; | |
10217 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10218 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10219 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10220 | mask |= 1; |
10221 | else | |
10222 | { | |
10223 | as_bad (_("invalid register list")); | |
10224 | break; | |
10225 | } | |
10226 | } | |
10227 | /* The mask is filled in in the opcode table for the | |
10228 | benefit of the disassembler. We remove it before | |
10229 | applying the actual mask. */ | |
10230 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10231 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10232 | } | |
10233 | continue; | |
10234 | ||
0499d65b TS |
10235 | case 'm': /* Register list for save insn. */ |
10236 | case 'M': /* Register list for restore insn. */ | |
10237 | { | |
10238 | int opcode = 0; | |
10239 | int framesz = 0, seen_framesz = 0; | |
10240 | int args = 0, statics = 0, sregs = 0; | |
10241 | ||
10242 | while (*s != '\0') | |
10243 | { | |
10244 | unsigned int reg1, reg2; | |
10245 | ||
10246 | SKIP_SPACE_TABS (s); | |
10247 | while (*s == ',') | |
10248 | ++s; | |
10249 | SKIP_SPACE_TABS (s); | |
10250 | ||
10251 | my_getExpression (&imm_expr, s); | |
10252 | if (imm_expr.X_op == O_constant) | |
10253 | { | |
10254 | /* Handle the frame size. */ | |
10255 | if (seen_framesz) | |
10256 | { | |
10257 | as_bad (_("more than one frame size in list")); | |
10258 | break; | |
10259 | } | |
10260 | seen_framesz = 1; | |
10261 | framesz = imm_expr.X_add_number; | |
10262 | imm_expr.X_op = O_absent; | |
10263 | s = expr_end; | |
10264 | continue; | |
10265 | } | |
10266 | ||
707bfff6 | 10267 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10268 | { |
10269 | as_bad (_("can't parse register list")); | |
10270 | break; | |
10271 | } | |
0499d65b | 10272 | |
707bfff6 TS |
10273 | while (*s == ' ') |
10274 | ++s; | |
10275 | ||
0499d65b TS |
10276 | if (*s != '-') |
10277 | reg2 = reg1; | |
10278 | else | |
10279 | { | |
10280 | ++s; | |
707bfff6 TS |
10281 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10282 | || reg2 < reg1) | |
0499d65b TS |
10283 | { |
10284 | as_bad (_("can't parse register list")); | |
10285 | break; | |
10286 | } | |
0499d65b TS |
10287 | } |
10288 | ||
10289 | while (reg1 <= reg2) | |
10290 | { | |
10291 | if (reg1 >= 4 && reg1 <= 7) | |
10292 | { | |
3a93f742 | 10293 | if (!seen_framesz) |
0499d65b TS |
10294 | /* args $a0-$a3 */ |
10295 | args |= 1 << (reg1 - 4); | |
10296 | else | |
10297 | /* statics $a0-$a3 */ | |
10298 | statics |= 1 << (reg1 - 4); | |
10299 | } | |
10300 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10301 | { | |
10302 | /* $s0-$s8 */ | |
10303 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10304 | } | |
10305 | else if (reg1 == 31) | |
10306 | { | |
10307 | /* Add $ra to insn. */ | |
10308 | opcode |= 0x40; | |
10309 | } | |
10310 | else | |
10311 | { | |
10312 | as_bad (_("unexpected register in list")); | |
10313 | break; | |
10314 | } | |
10315 | if (++reg1 == 24) | |
10316 | reg1 = 30; | |
10317 | } | |
10318 | } | |
10319 | ||
10320 | /* Encode args/statics combination. */ | |
10321 | if (args & statics) | |
10322 | as_bad (_("arg/static registers overlap")); | |
10323 | else if (args == 0xf) | |
10324 | /* All $a0-$a3 are args. */ | |
10325 | opcode |= MIPS16_ALL_ARGS << 16; | |
10326 | else if (statics == 0xf) | |
10327 | /* All $a0-$a3 are statics. */ | |
10328 | opcode |= MIPS16_ALL_STATICS << 16; | |
10329 | else | |
10330 | { | |
10331 | int narg = 0, nstat = 0; | |
10332 | ||
10333 | /* Count arg registers. */ | |
10334 | while (args & 0x1) | |
10335 | { | |
10336 | args >>= 1; | |
10337 | narg++; | |
10338 | } | |
10339 | if (args != 0) | |
10340 | as_bad (_("invalid arg register list")); | |
10341 | ||
10342 | /* Count static registers. */ | |
10343 | while (statics & 0x8) | |
10344 | { | |
10345 | statics = (statics << 1) & 0xf; | |
10346 | nstat++; | |
10347 | } | |
10348 | if (statics != 0) | |
10349 | as_bad (_("invalid static register list")); | |
10350 | ||
10351 | /* Encode args/statics. */ | |
10352 | opcode |= ((narg << 2) | nstat) << 16; | |
10353 | } | |
10354 | ||
10355 | /* Encode $s0/$s1. */ | |
10356 | if (sregs & (1 << 0)) /* $s0 */ | |
10357 | opcode |= 0x20; | |
10358 | if (sregs & (1 << 1)) /* $s1 */ | |
10359 | opcode |= 0x10; | |
10360 | sregs >>= 2; | |
10361 | ||
10362 | if (sregs != 0) | |
10363 | { | |
10364 | /* Count regs $s2-$s8. */ | |
10365 | int nsreg = 0; | |
10366 | while (sregs & 1) | |
10367 | { | |
10368 | sregs >>= 1; | |
10369 | nsreg++; | |
10370 | } | |
10371 | if (sregs != 0) | |
10372 | as_bad (_("invalid static register list")); | |
10373 | /* Encode $s2-$s8. */ | |
10374 | opcode |= nsreg << 24; | |
10375 | } | |
10376 | ||
10377 | /* Encode frame size. */ | |
10378 | if (!seen_framesz) | |
10379 | as_bad (_("missing frame size")); | |
10380 | else if ((framesz & 7) != 0 || framesz < 0 | |
10381 | || framesz > 0xff * 8) | |
10382 | as_bad (_("invalid frame size")); | |
10383 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10384 | { | |
10385 | framesz /= 8; | |
10386 | opcode |= (((framesz & 0xf0) << 16) | |
10387 | | (framesz & 0x0f)); | |
10388 | } | |
10389 | ||
10390 | /* Finally build the instruction. */ | |
10391 | if ((opcode >> 16) != 0 || framesz == 0) | |
10392 | { | |
10393 | ip->use_extend = TRUE; | |
10394 | ip->extend = opcode >> 16; | |
10395 | } | |
10396 | ip->insn_opcode |= opcode & 0x7f; | |
10397 | } | |
10398 | continue; | |
10399 | ||
252b5132 RH |
10400 | case 'e': /* extend code */ |
10401 | my_getExpression (&imm_expr, s); | |
10402 | check_absolute_expr (ip, &imm_expr); | |
10403 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10404 | { | |
10405 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10406 | ip->insn_mo->name, | |
10407 | (unsigned long) imm_expr.X_add_number); | |
10408 | imm_expr.X_add_number &= 0x7ff; | |
10409 | } | |
10410 | ip->insn_opcode |= imm_expr.X_add_number; | |
10411 | imm_expr.X_op = O_absent; | |
10412 | s = expr_end; | |
10413 | continue; | |
10414 | ||
10415 | default: | |
10416 | internalError (); | |
10417 | } | |
10418 | break; | |
10419 | } | |
10420 | ||
10421 | /* Args don't match. */ | |
10422 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10423 | strcmp (insn->name, insn[1].name) == 0) | |
10424 | { | |
10425 | ++insn; | |
10426 | s = argsstart; | |
10427 | continue; | |
10428 | } | |
10429 | ||
10430 | insn_error = _("illegal operands"); | |
10431 | ||
10432 | return; | |
10433 | } | |
10434 | } | |
10435 | ||
10436 | /* This structure holds information we know about a mips16 immediate | |
10437 | argument type. */ | |
10438 | ||
e972090a NC |
10439 | struct mips16_immed_operand |
10440 | { | |
252b5132 RH |
10441 | /* The type code used in the argument string in the opcode table. */ |
10442 | int type; | |
10443 | /* The number of bits in the short form of the opcode. */ | |
10444 | int nbits; | |
10445 | /* The number of bits in the extended form of the opcode. */ | |
10446 | int extbits; | |
10447 | /* The amount by which the short form is shifted when it is used; | |
10448 | for example, the sw instruction has a shift count of 2. */ | |
10449 | int shift; | |
10450 | /* The amount by which the short form is shifted when it is stored | |
10451 | into the instruction code. */ | |
10452 | int op_shift; | |
10453 | /* Non-zero if the short form is unsigned. */ | |
10454 | int unsp; | |
10455 | /* Non-zero if the extended form is unsigned. */ | |
10456 | int extu; | |
10457 | /* Non-zero if the value is PC relative. */ | |
10458 | int pcrel; | |
10459 | }; | |
10460 | ||
10461 | /* The mips16 immediate operand types. */ | |
10462 | ||
10463 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10464 | { | |
10465 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10466 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10467 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10468 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10469 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10470 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10471 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10472 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10473 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10474 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10475 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10476 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10477 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10478 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10479 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10480 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10481 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10482 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10483 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10484 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10485 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10486 | }; | |
10487 | ||
10488 | #define MIPS16_NUM_IMMED \ | |
10489 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10490 | ||
10491 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10492 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10493 | whether an extended value is needed; if one is needed, it sets | |
10494 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10495 | If SMALL is true, an unextended opcode was explicitly requested. | |
10496 | If EXT is true, an extended opcode was explicitly requested. If | |
10497 | WARN is true, warn if EXT does not match reality. */ | |
10498 | ||
10499 | static void | |
17a2f251 TS |
10500 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10501 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10502 | unsigned long *insn, bfd_boolean *use_extend, | |
10503 | unsigned short *extend) | |
252b5132 | 10504 | { |
3994f87e | 10505 | const struct mips16_immed_operand *op; |
252b5132 | 10506 | int mintiny, maxtiny; |
b34976b6 | 10507 | bfd_boolean needext; |
252b5132 RH |
10508 | |
10509 | op = mips16_immed_operands; | |
10510 | while (op->type != type) | |
10511 | { | |
10512 | ++op; | |
10513 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10514 | } | |
10515 | ||
10516 | if (op->unsp) | |
10517 | { | |
10518 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10519 | { | |
10520 | mintiny = 1; | |
10521 | maxtiny = 1 << op->nbits; | |
10522 | } | |
10523 | else | |
10524 | { | |
10525 | mintiny = 0; | |
10526 | maxtiny = (1 << op->nbits) - 1; | |
10527 | } | |
10528 | } | |
10529 | else | |
10530 | { | |
10531 | mintiny = - (1 << (op->nbits - 1)); | |
10532 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10533 | } | |
10534 | ||
10535 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10536 | if (type == 'p' || type == 'q') | |
10537 | val /= 2; | |
10538 | ||
10539 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10540 | || val < (mintiny << op->shift) | |
10541 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10542 | needext = TRUE; |
252b5132 | 10543 | else |
b34976b6 | 10544 | needext = FALSE; |
252b5132 RH |
10545 | |
10546 | if (warn && ext && ! needext) | |
beae10d5 KH |
10547 | as_warn_where (file, line, |
10548 | _("extended operand requested but not required")); | |
252b5132 RH |
10549 | if (small && needext) |
10550 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10551 | ||
10552 | if (small || (! ext && ! needext)) | |
10553 | { | |
10554 | int insnval; | |
10555 | ||
b34976b6 | 10556 | *use_extend = FALSE; |
252b5132 RH |
10557 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10558 | insnval <<= op->op_shift; | |
10559 | *insn |= insnval; | |
10560 | } | |
10561 | else | |
10562 | { | |
10563 | long minext, maxext; | |
10564 | int extval; | |
10565 | ||
10566 | if (op->extu) | |
10567 | { | |
10568 | minext = 0; | |
10569 | maxext = (1 << op->extbits) - 1; | |
10570 | } | |
10571 | else | |
10572 | { | |
10573 | minext = - (1 << (op->extbits - 1)); | |
10574 | maxext = (1 << (op->extbits - 1)) - 1; | |
10575 | } | |
10576 | if (val < minext || val > maxext) | |
10577 | as_bad_where (file, line, | |
10578 | _("operand value out of range for instruction")); | |
10579 | ||
b34976b6 | 10580 | *use_extend = TRUE; |
252b5132 RH |
10581 | if (op->extbits == 16) |
10582 | { | |
10583 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10584 | val &= 0x1f; | |
10585 | } | |
10586 | else if (op->extbits == 15) | |
10587 | { | |
10588 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10589 | val &= 0xf; | |
10590 | } | |
10591 | else | |
10592 | { | |
10593 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10594 | val = 0; | |
10595 | } | |
10596 | ||
10597 | *extend = (unsigned short) extval; | |
10598 | *insn |= val; | |
10599 | } | |
10600 | } | |
10601 | \f | |
d6f16593 | 10602 | struct percent_op_match |
ad8d3bb3 | 10603 | { |
5e0116d5 RS |
10604 | const char *str; |
10605 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10606 | }; |
10607 | ||
10608 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10609 | { |
5e0116d5 | 10610 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10611 | #ifdef OBJ_ELF |
5e0116d5 RS |
10612 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10613 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10614 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10615 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10616 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10617 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10618 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10619 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10620 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10621 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10622 | {"%half", BFD_RELOC_16}, | |
10623 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10624 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10625 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10626 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10627 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10628 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10629 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10630 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10631 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10632 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10633 | #endif |
5e0116d5 | 10634 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10635 | }; |
10636 | ||
d6f16593 MR |
10637 | static const struct percent_op_match mips16_percent_op[] = |
10638 | { | |
10639 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10640 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10641 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10642 | }; | |
10643 | ||
252b5132 | 10644 | |
5e0116d5 RS |
10645 | /* Return true if *STR points to a relocation operator. When returning true, |
10646 | move *STR over the operator and store its relocation code in *RELOC. | |
10647 | Leave both *STR and *RELOC alone when returning false. */ | |
10648 | ||
10649 | static bfd_boolean | |
17a2f251 | 10650 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10651 | { |
d6f16593 MR |
10652 | const struct percent_op_match *percent_op; |
10653 | size_t limit, i; | |
10654 | ||
10655 | if (mips_opts.mips16) | |
10656 | { | |
10657 | percent_op = mips16_percent_op; | |
10658 | limit = ARRAY_SIZE (mips16_percent_op); | |
10659 | } | |
10660 | else | |
10661 | { | |
10662 | percent_op = mips_percent_op; | |
10663 | limit = ARRAY_SIZE (mips_percent_op); | |
10664 | } | |
76b3015f | 10665 | |
d6f16593 | 10666 | for (i = 0; i < limit; i++) |
5e0116d5 | 10667 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10668 | { |
3f98094e DJ |
10669 | int len = strlen (percent_op[i].str); |
10670 | ||
10671 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10672 | continue; | |
10673 | ||
5e0116d5 RS |
10674 | *str += strlen (percent_op[i].str); |
10675 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10676 | |
5e0116d5 RS |
10677 | /* Check whether the output BFD supports this relocation. |
10678 | If not, issue an error and fall back on something safe. */ | |
10679 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10680 | { |
5e0116d5 RS |
10681 | as_bad ("relocation %s isn't supported by the current ABI", |
10682 | percent_op[i].str); | |
01a3f561 | 10683 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10684 | } |
5e0116d5 | 10685 | return TRUE; |
394f9b3a | 10686 | } |
5e0116d5 | 10687 | return FALSE; |
394f9b3a | 10688 | } |
ad8d3bb3 | 10689 | |
ad8d3bb3 | 10690 | |
5e0116d5 RS |
10691 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10692 | expression in *EP and the relocations in the array starting | |
10693 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10694 | |
01a3f561 | 10695 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10696 | |
5e0116d5 | 10697 | static size_t |
17a2f251 TS |
10698 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10699 | char *str) | |
ad8d3bb3 | 10700 | { |
5e0116d5 RS |
10701 | bfd_reloc_code_real_type reversed_reloc[3]; |
10702 | size_t reloc_index, i; | |
09b8f35a RS |
10703 | int crux_depth, str_depth; |
10704 | char *crux; | |
5e0116d5 RS |
10705 | |
10706 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10707 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10708 | of the main expression and with CRUX_DEPTH containing the number | |
10709 | of open brackets at that point. */ | |
10710 | reloc_index = -1; | |
10711 | str_depth = 0; | |
10712 | do | |
fb1b3232 | 10713 | { |
09b8f35a RS |
10714 | reloc_index++; |
10715 | crux = str; | |
10716 | crux_depth = str_depth; | |
10717 | ||
10718 | /* Skip over whitespace and brackets, keeping count of the number | |
10719 | of brackets. */ | |
10720 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10721 | if (*str++ == '(') | |
10722 | str_depth++; | |
5e0116d5 | 10723 | } |
09b8f35a RS |
10724 | while (*str == '%' |
10725 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10726 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10727 | |
09b8f35a | 10728 | my_getExpression (ep, crux); |
5e0116d5 | 10729 | str = expr_end; |
394f9b3a | 10730 | |
5e0116d5 | 10731 | /* Match every open bracket. */ |
09b8f35a | 10732 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10733 | if (*str++ == ')') |
09b8f35a | 10734 | crux_depth--; |
394f9b3a | 10735 | |
09b8f35a | 10736 | if (crux_depth > 0) |
5e0116d5 | 10737 | as_bad ("unclosed '('"); |
394f9b3a | 10738 | |
5e0116d5 | 10739 | expr_end = str; |
252b5132 | 10740 | |
01a3f561 | 10741 | if (reloc_index != 0) |
64bdfcaf RS |
10742 | { |
10743 | prev_reloc_op_frag = frag_now; | |
10744 | for (i = 0; i < reloc_index; i++) | |
10745 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10746 | } | |
fb1b3232 | 10747 | |
5e0116d5 | 10748 | return reloc_index; |
252b5132 RH |
10749 | } |
10750 | ||
10751 | static void | |
17a2f251 | 10752 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10753 | { |
10754 | char *save_in; | |
98aa84af | 10755 | valueT val; |
252b5132 RH |
10756 | |
10757 | save_in = input_line_pointer; | |
10758 | input_line_pointer = str; | |
10759 | expression (ep); | |
10760 | expr_end = input_line_pointer; | |
10761 | input_line_pointer = save_in; | |
10762 | ||
10763 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10764 | then we bump the value of the symbol by 1 since that is how other | |
10765 | text symbols are handled. We don't bother to handle complex | |
10766 | expressions, just `.' plus or minus a constant. */ | |
10767 | if (mips_opts.mips16 | |
10768 | && ep->X_op == O_symbol | |
10769 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10770 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10771 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10772 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10773 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10774 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10775 | } |
10776 | ||
252b5132 | 10777 | char * |
17a2f251 | 10778 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10779 | { |
499ac353 | 10780 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
10781 | } |
10782 | ||
10783 | void | |
17a2f251 | 10784 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10785 | { |
10786 | if (target_big_endian) | |
10787 | number_to_chars_bigendian (buf, val, n); | |
10788 | else | |
10789 | number_to_chars_littleendian (buf, val, n); | |
10790 | } | |
10791 | \f | |
ae948b86 | 10792 | #ifdef OBJ_ELF |
e013f690 TS |
10793 | static int support_64bit_objects(void) |
10794 | { | |
10795 | const char **list, **l; | |
aa3d8fdf | 10796 | int yes; |
e013f690 TS |
10797 | |
10798 | list = bfd_target_list (); | |
10799 | for (l = list; *l != NULL; l++) | |
10800 | #ifdef TE_TMIPS | |
10801 | /* This is traditional mips */ | |
10802 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10803 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10804 | #else | |
10805 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10806 | || strcmp (*l, "elf64-littlemips") == 0) | |
10807 | #endif | |
10808 | break; | |
aa3d8fdf | 10809 | yes = (*l != NULL); |
e013f690 | 10810 | free (list); |
aa3d8fdf | 10811 | return yes; |
e013f690 | 10812 | } |
ae948b86 | 10813 | #endif /* OBJ_ELF */ |
e013f690 | 10814 | |
78849248 | 10815 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10816 | |
e972090a NC |
10817 | struct option md_longopts[] = |
10818 | { | |
f9b4148d CD |
10819 | /* Options which specify architecture. */ |
10820 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10821 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10822 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10823 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10824 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10825 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10826 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10827 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10828 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10829 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10830 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10831 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10832 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10833 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10834 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10835 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10836 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10837 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10838 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10839 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10840 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10841 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10842 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10843 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10844 | |
10845 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10846 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10847 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10848 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10849 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10850 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10851 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10852 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10853 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10854 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10855 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10856 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10857 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10858 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10859 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10860 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10861 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10862 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10863 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10864 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10865 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10866 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10867 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10868 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10869 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10870 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
8b082fb1 TS |
10871 | #define OPTION_DSPR2 (OPTION_ASE_BASE + 12) |
10872 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
10873 | #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) | |
10874 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
f9b4148d CD |
10875 | |
10876 | /* Old-style architecture options. Don't add more of these. */ | |
8b082fb1 | 10877 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) |
f9b4148d CD |
10878 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10879 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10880 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10881 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10882 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10883 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10884 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10885 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10886 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10887 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10888 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10889 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10890 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10891 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10892 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10893 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10894 | ||
10895 | /* Options which enable bug fixes. */ | |
10896 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10897 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10898 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10899 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10900 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10901 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10902 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10903 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10904 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10905 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10906 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10907 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10908 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10909 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10910 | |
10911 | /* Miscellaneous options. */ | |
7d8e00cf | 10912 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10913 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10914 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10915 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10916 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10917 | {"break", no_argument, NULL, OPTION_BREAK}, |
10918 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10919 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10920 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10921 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10922 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10923 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10924 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10925 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10926 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10927 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10928 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10929 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10930 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10931 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10932 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10933 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10934 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10935 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10936 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10937 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10938 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10939 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10940 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10941 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10942 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10943 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10944 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10945 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10946 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10947 | |
10948 | /* ELF-specific options. */ | |
156c2f8b | 10949 | #ifdef OBJ_ELF |
aed1a261 | 10950 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10951 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10952 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10953 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10954 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10955 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10956 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10957 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10958 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10959 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10960 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10961 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10962 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10963 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10964 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10965 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10966 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10967 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10968 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10969 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10970 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10971 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10972 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10973 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10974 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10975 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10976 | #endif /* OBJ_ELF */ |
f9b4148d | 10977 | |
252b5132 RH |
10978 | {NULL, no_argument, NULL, 0} |
10979 | }; | |
156c2f8b | 10980 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10981 | |
316f5878 RS |
10982 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10983 | NEW_VALUE. Warn if another value was already specified. Note: | |
10984 | we have to defer parsing the -march and -mtune arguments in order | |
10985 | to handle 'from-abi' correctly, since the ABI might be specified | |
10986 | in a later argument. */ | |
10987 | ||
10988 | static void | |
17a2f251 | 10989 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10990 | { |
10991 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10992 | as_warn (_("A different %s was already specified, is now %s"), | |
10993 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10994 | new_value); | |
10995 | ||
10996 | *string_ptr = new_value; | |
10997 | } | |
10998 | ||
252b5132 | 10999 | int |
17a2f251 | 11000 | md_parse_option (int c, char *arg) |
252b5132 RH |
11001 | { |
11002 | switch (c) | |
11003 | { | |
119d663a NC |
11004 | case OPTION_CONSTRUCT_FLOATS: |
11005 | mips_disable_float_construction = 0; | |
11006 | break; | |
bdaaa2e1 | 11007 | |
119d663a NC |
11008 | case OPTION_NO_CONSTRUCT_FLOATS: |
11009 | mips_disable_float_construction = 1; | |
11010 | break; | |
bdaaa2e1 | 11011 | |
252b5132 RH |
11012 | case OPTION_TRAP: |
11013 | mips_trap = 1; | |
11014 | break; | |
11015 | ||
11016 | case OPTION_BREAK: | |
11017 | mips_trap = 0; | |
11018 | break; | |
11019 | ||
11020 | case OPTION_EB: | |
11021 | target_big_endian = 1; | |
11022 | break; | |
11023 | ||
11024 | case OPTION_EL: | |
11025 | target_big_endian = 0; | |
11026 | break; | |
11027 | ||
11028 | case 'O': | |
4ffff32f TS |
11029 | if (arg == NULL) |
11030 | mips_optimize = 1; | |
11031 | else if (arg[0] == '0') | |
11032 | mips_optimize = 0; | |
11033 | else if (arg[0] == '1') | |
252b5132 RH |
11034 | mips_optimize = 1; |
11035 | else | |
11036 | mips_optimize = 2; | |
11037 | break; | |
11038 | ||
11039 | case 'g': | |
11040 | if (arg == NULL) | |
11041 | mips_debug = 2; | |
11042 | else | |
11043 | mips_debug = atoi (arg); | |
252b5132 RH |
11044 | break; |
11045 | ||
11046 | case OPTION_MIPS1: | |
316f5878 | 11047 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11048 | break; |
11049 | ||
11050 | case OPTION_MIPS2: | |
316f5878 | 11051 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11052 | break; |
11053 | ||
11054 | case OPTION_MIPS3: | |
316f5878 | 11055 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11056 | break; |
11057 | ||
11058 | case OPTION_MIPS4: | |
316f5878 | 11059 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11060 | break; |
11061 | ||
84ea6cf2 | 11062 | case OPTION_MIPS5: |
316f5878 | 11063 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11064 | break; |
11065 | ||
e7af610e | 11066 | case OPTION_MIPS32: |
316f5878 | 11067 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11068 | break; |
11069 | ||
af7ee8bf CD |
11070 | case OPTION_MIPS32R2: |
11071 | file_mips_isa = ISA_MIPS32R2; | |
11072 | break; | |
11073 | ||
5f74bc13 CD |
11074 | case OPTION_MIPS64R2: |
11075 | file_mips_isa = ISA_MIPS64R2; | |
11076 | break; | |
11077 | ||
84ea6cf2 | 11078 | case OPTION_MIPS64: |
316f5878 | 11079 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11080 | break; |
11081 | ||
ec68c924 | 11082 | case OPTION_MTUNE: |
316f5878 RS |
11083 | mips_set_option_string (&mips_tune_string, arg); |
11084 | break; | |
ec68c924 | 11085 | |
316f5878 RS |
11086 | case OPTION_MARCH: |
11087 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11088 | break; |
11089 | ||
11090 | case OPTION_M4650: | |
316f5878 RS |
11091 | mips_set_option_string (&mips_arch_string, "4650"); |
11092 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11093 | break; |
11094 | ||
11095 | case OPTION_NO_M4650: | |
11096 | break; | |
11097 | ||
11098 | case OPTION_M4010: | |
316f5878 RS |
11099 | mips_set_option_string (&mips_arch_string, "4010"); |
11100 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11101 | break; |
11102 | ||
11103 | case OPTION_NO_M4010: | |
11104 | break; | |
11105 | ||
11106 | case OPTION_M4100: | |
316f5878 RS |
11107 | mips_set_option_string (&mips_arch_string, "4100"); |
11108 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11109 | break; |
11110 | ||
11111 | case OPTION_NO_M4100: | |
11112 | break; | |
11113 | ||
252b5132 | 11114 | case OPTION_M3900: |
316f5878 RS |
11115 | mips_set_option_string (&mips_arch_string, "3900"); |
11116 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11117 | break; |
bdaaa2e1 | 11118 | |
252b5132 RH |
11119 | case OPTION_NO_M3900: |
11120 | break; | |
11121 | ||
deec1734 CD |
11122 | case OPTION_MDMX: |
11123 | mips_opts.ase_mdmx = 1; | |
11124 | break; | |
11125 | ||
11126 | case OPTION_NO_MDMX: | |
11127 | mips_opts.ase_mdmx = 0; | |
11128 | break; | |
11129 | ||
74cd071d CF |
11130 | case OPTION_DSP: |
11131 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11132 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11133 | break; |
11134 | ||
11135 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11136 | mips_opts.ase_dsp = 0; |
11137 | mips_opts.ase_dspr2 = 0; | |
11138 | break; | |
11139 | ||
11140 | case OPTION_DSPR2: | |
11141 | mips_opts.ase_dspr2 = 1; | |
11142 | mips_opts.ase_dsp = 1; | |
11143 | break; | |
11144 | ||
11145 | case OPTION_NO_DSPR2: | |
11146 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11147 | mips_opts.ase_dsp = 0; |
11148 | break; | |
11149 | ||
ef2e4d86 CF |
11150 | case OPTION_MT: |
11151 | mips_opts.ase_mt = 1; | |
11152 | break; | |
11153 | ||
11154 | case OPTION_NO_MT: | |
11155 | mips_opts.ase_mt = 0; | |
11156 | break; | |
11157 | ||
252b5132 RH |
11158 | case OPTION_MIPS16: |
11159 | mips_opts.mips16 = 1; | |
7d10b47d | 11160 | mips_no_prev_insn (); |
252b5132 RH |
11161 | break; |
11162 | ||
11163 | case OPTION_NO_MIPS16: | |
11164 | mips_opts.mips16 = 0; | |
7d10b47d | 11165 | mips_no_prev_insn (); |
252b5132 RH |
11166 | break; |
11167 | ||
1f25f5d3 CD |
11168 | case OPTION_MIPS3D: |
11169 | mips_opts.ase_mips3d = 1; | |
11170 | break; | |
11171 | ||
11172 | case OPTION_NO_MIPS3D: | |
11173 | mips_opts.ase_mips3d = 0; | |
11174 | break; | |
11175 | ||
e16bfa71 TS |
11176 | case OPTION_SMARTMIPS: |
11177 | mips_opts.ase_smartmips = 1; | |
11178 | break; | |
11179 | ||
11180 | case OPTION_NO_SMARTMIPS: | |
11181 | mips_opts.ase_smartmips = 0; | |
11182 | break; | |
11183 | ||
d766e8ec RS |
11184 | case OPTION_FIX_VR4120: |
11185 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11186 | break; |
11187 | ||
d766e8ec RS |
11188 | case OPTION_NO_FIX_VR4120: |
11189 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11190 | break; |
11191 | ||
7d8e00cf RS |
11192 | case OPTION_FIX_VR4130: |
11193 | mips_fix_vr4130 = 1; | |
11194 | break; | |
11195 | ||
11196 | case OPTION_NO_FIX_VR4130: | |
11197 | mips_fix_vr4130 = 0; | |
11198 | break; | |
11199 | ||
4a6a3df4 AO |
11200 | case OPTION_RELAX_BRANCH: |
11201 | mips_relax_branch = 1; | |
11202 | break; | |
11203 | ||
11204 | case OPTION_NO_RELAX_BRANCH: | |
11205 | mips_relax_branch = 0; | |
11206 | break; | |
11207 | ||
aa6975fb ILT |
11208 | case OPTION_MSHARED: |
11209 | mips_in_shared = TRUE; | |
11210 | break; | |
11211 | ||
11212 | case OPTION_MNO_SHARED: | |
11213 | mips_in_shared = FALSE; | |
11214 | break; | |
11215 | ||
aed1a261 RS |
11216 | case OPTION_MSYM32: |
11217 | mips_opts.sym32 = TRUE; | |
11218 | break; | |
11219 | ||
11220 | case OPTION_MNO_SYM32: | |
11221 | mips_opts.sym32 = FALSE; | |
11222 | break; | |
11223 | ||
0f074f60 | 11224 | #ifdef OBJ_ELF |
252b5132 RH |
11225 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11226 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11227 | intended to be compatible with Irix 5. */ | |
11228 | case OPTION_CALL_SHARED: | |
f43abd2b | 11229 | if (!IS_ELF) |
252b5132 RH |
11230 | { |
11231 | as_bad (_("-call_shared is supported only for ELF format")); | |
11232 | return 0; | |
11233 | } | |
11234 | mips_pic = SVR4_PIC; | |
143d77c5 | 11235 | mips_abicalls = TRUE; |
252b5132 RH |
11236 | break; |
11237 | ||
11238 | case OPTION_NON_SHARED: | |
f43abd2b | 11239 | if (!IS_ELF) |
252b5132 RH |
11240 | { |
11241 | as_bad (_("-non_shared is supported only for ELF format")); | |
11242 | return 0; | |
11243 | } | |
11244 | mips_pic = NO_PIC; | |
143d77c5 | 11245 | mips_abicalls = FALSE; |
252b5132 RH |
11246 | break; |
11247 | ||
44075ae2 TS |
11248 | /* The -xgot option tells the assembler to use 32 bit offsets |
11249 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11250 | compatibility. */ |
11251 | case OPTION_XGOT: | |
11252 | mips_big_got = 1; | |
11253 | break; | |
0f074f60 | 11254 | #endif /* OBJ_ELF */ |
252b5132 RH |
11255 | |
11256 | case 'G': | |
6caf9ef4 TS |
11257 | g_switch_value = atoi (arg); |
11258 | g_switch_seen = 1; | |
252b5132 RH |
11259 | break; |
11260 | ||
0f074f60 | 11261 | #ifdef OBJ_ELF |
34ba82a8 TS |
11262 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11263 | and -mabi=64. */ | |
252b5132 | 11264 | case OPTION_32: |
f43abd2b | 11265 | if (!IS_ELF) |
34ba82a8 TS |
11266 | { |
11267 | as_bad (_("-32 is supported for ELF format only")); | |
11268 | return 0; | |
11269 | } | |
316f5878 | 11270 | mips_abi = O32_ABI; |
252b5132 RH |
11271 | break; |
11272 | ||
e013f690 | 11273 | case OPTION_N32: |
f43abd2b | 11274 | if (!IS_ELF) |
34ba82a8 TS |
11275 | { |
11276 | as_bad (_("-n32 is supported for ELF format only")); | |
11277 | return 0; | |
11278 | } | |
316f5878 | 11279 | mips_abi = N32_ABI; |
e013f690 | 11280 | break; |
252b5132 | 11281 | |
e013f690 | 11282 | case OPTION_64: |
f43abd2b | 11283 | if (!IS_ELF) |
34ba82a8 TS |
11284 | { |
11285 | as_bad (_("-64 is supported for ELF format only")); | |
11286 | return 0; | |
11287 | } | |
316f5878 | 11288 | mips_abi = N64_ABI; |
f43abd2b | 11289 | if (!support_64bit_objects()) |
e013f690 | 11290 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11291 | break; |
ae948b86 | 11292 | #endif /* OBJ_ELF */ |
252b5132 | 11293 | |
c97ef257 | 11294 | case OPTION_GP32: |
a325df1d | 11295 | file_mips_gp32 = 1; |
c97ef257 AH |
11296 | break; |
11297 | ||
11298 | case OPTION_GP64: | |
a325df1d | 11299 | file_mips_gp32 = 0; |
c97ef257 | 11300 | break; |
252b5132 | 11301 | |
ca4e0257 | 11302 | case OPTION_FP32: |
a325df1d | 11303 | file_mips_fp32 = 1; |
316f5878 RS |
11304 | break; |
11305 | ||
11306 | case OPTION_FP64: | |
11307 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11308 | break; |
11309 | ||
ae948b86 | 11310 | #ifdef OBJ_ELF |
252b5132 | 11311 | case OPTION_MABI: |
f43abd2b | 11312 | if (!IS_ELF) |
34ba82a8 TS |
11313 | { |
11314 | as_bad (_("-mabi is supported for ELF format only")); | |
11315 | return 0; | |
11316 | } | |
e013f690 | 11317 | if (strcmp (arg, "32") == 0) |
316f5878 | 11318 | mips_abi = O32_ABI; |
e013f690 | 11319 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11320 | mips_abi = O64_ABI; |
e013f690 | 11321 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11322 | mips_abi = N32_ABI; |
e013f690 TS |
11323 | else if (strcmp (arg, "64") == 0) |
11324 | { | |
316f5878 | 11325 | mips_abi = N64_ABI; |
e013f690 TS |
11326 | if (! support_64bit_objects()) |
11327 | as_fatal (_("No compiled in support for 64 bit object file " | |
11328 | "format")); | |
11329 | } | |
11330 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11331 | mips_abi = EABI_ABI; |
e013f690 | 11332 | else |
da0e507f TS |
11333 | { |
11334 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11335 | return 0; | |
11336 | } | |
252b5132 | 11337 | break; |
e013f690 | 11338 | #endif /* OBJ_ELF */ |
252b5132 | 11339 | |
6b76fefe | 11340 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11341 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11342 | break; |
11343 | ||
9ee72ff1 | 11344 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11345 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11346 | break; |
11347 | ||
ecb4347a DJ |
11348 | #ifdef OBJ_ELF |
11349 | case OPTION_MDEBUG: | |
b34976b6 | 11350 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11351 | break; |
11352 | ||
11353 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11354 | mips_flag_mdebug = FALSE; |
ecb4347a | 11355 | break; |
dcd410fe RO |
11356 | |
11357 | case OPTION_PDR: | |
11358 | mips_flag_pdr = TRUE; | |
11359 | break; | |
11360 | ||
11361 | case OPTION_NO_PDR: | |
11362 | mips_flag_pdr = FALSE; | |
11363 | break; | |
0a44bf69 RS |
11364 | |
11365 | case OPTION_MVXWORKS_PIC: | |
11366 | mips_pic = VXWORKS_PIC; | |
11367 | break; | |
ecb4347a DJ |
11368 | #endif /* OBJ_ELF */ |
11369 | ||
252b5132 RH |
11370 | default: |
11371 | return 0; | |
11372 | } | |
11373 | ||
11374 | return 1; | |
11375 | } | |
316f5878 RS |
11376 | \f |
11377 | /* Set up globals to generate code for the ISA or processor | |
11378 | described by INFO. */ | |
252b5132 | 11379 | |
252b5132 | 11380 | static void |
17a2f251 | 11381 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11382 | { |
316f5878 | 11383 | if (info != 0) |
252b5132 | 11384 | { |
fef14a42 TS |
11385 | file_mips_arch = info->cpu; |
11386 | mips_opts.arch = info->cpu; | |
316f5878 | 11387 | mips_opts.isa = info->isa; |
252b5132 | 11388 | } |
252b5132 RH |
11389 | } |
11390 | ||
252b5132 | 11391 | |
316f5878 | 11392 | /* Likewise for tuning. */ |
252b5132 | 11393 | |
316f5878 | 11394 | static void |
17a2f251 | 11395 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11396 | { |
11397 | if (info != 0) | |
fef14a42 | 11398 | mips_tune = info->cpu; |
316f5878 | 11399 | } |
80cc45a5 | 11400 | |
34ba82a8 | 11401 | |
252b5132 | 11402 | void |
17a2f251 | 11403 | mips_after_parse_args (void) |
e9670677 | 11404 | { |
fef14a42 TS |
11405 | const struct mips_cpu_info *arch_info = 0; |
11406 | const struct mips_cpu_info *tune_info = 0; | |
11407 | ||
e9670677 | 11408 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11409 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11410 | { |
6caf9ef4 | 11411 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11412 | as_bad (_("-G not supported in this configuration.")); |
11413 | g_switch_value = 0; | |
11414 | } | |
11415 | ||
cac012d6 AO |
11416 | if (mips_abi == NO_ABI) |
11417 | mips_abi = MIPS_DEFAULT_ABI; | |
11418 | ||
22923709 RS |
11419 | /* The following code determines the architecture and register size. |
11420 | Similar code was added to GCC 3.3 (see override_options() in | |
11421 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11422 | as much as possible. */ | |
e9670677 | 11423 | |
316f5878 | 11424 | if (mips_arch_string != 0) |
fef14a42 | 11425 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11426 | |
316f5878 | 11427 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11428 | { |
316f5878 | 11429 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11430 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11431 | the -march selection (if any). */ |
fef14a42 | 11432 | if (arch_info != 0) |
e9670677 | 11433 | { |
316f5878 RS |
11434 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11435 | There's no harm in specifying both as long as the ISA levels | |
11436 | are the same. */ | |
fef14a42 | 11437 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11438 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11439 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11440 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11441 | } |
316f5878 | 11442 | else |
fef14a42 | 11443 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11444 | } |
11445 | ||
fef14a42 TS |
11446 | if (arch_info == 0) |
11447 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11448 | |
fef14a42 | 11449 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11450 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11451 | arch_info->name); |
11452 | ||
11453 | mips_set_architecture (arch_info); | |
11454 | ||
11455 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11456 | if (mips_tune_string != 0) | |
11457 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11458 | |
fef14a42 TS |
11459 | if (tune_info == 0) |
11460 | mips_set_tune (arch_info); | |
11461 | else | |
11462 | mips_set_tune (tune_info); | |
e9670677 | 11463 | |
316f5878 | 11464 | if (file_mips_gp32 >= 0) |
e9670677 | 11465 | { |
316f5878 RS |
11466 | /* The user specified the size of the integer registers. Make sure |
11467 | it agrees with the ABI and ISA. */ | |
11468 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11469 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11470 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11471 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11472 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11473 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11474 | } |
11475 | else | |
11476 | { | |
316f5878 RS |
11477 | /* Infer the integer register size from the ABI and processor. |
11478 | Restrict ourselves to 32-bit registers if that's all the | |
11479 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11480 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11481 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11482 | } |
11483 | ||
ad3fea08 TS |
11484 | switch (file_mips_fp32) |
11485 | { | |
11486 | default: | |
11487 | case -1: | |
11488 | /* No user specified float register size. | |
11489 | ??? GAS treats single-float processors as though they had 64-bit | |
11490 | float registers (although it complains when double-precision | |
11491 | instructions are used). As things stand, saying they have 32-bit | |
11492 | registers would lead to spurious "register must be even" messages. | |
11493 | So here we assume float registers are never smaller than the | |
11494 | integer ones. */ | |
11495 | if (file_mips_gp32 == 0) | |
11496 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11497 | file_mips_fp32 = 0; | |
11498 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11499 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11500 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11501 | file_mips_fp32 = 0; | |
11502 | else | |
11503 | /* 32-bit float registers. */ | |
11504 | file_mips_fp32 = 1; | |
11505 | break; | |
11506 | ||
11507 | /* The user specified the size of the float registers. Check if it | |
11508 | agrees with the ABI and ISA. */ | |
11509 | case 0: | |
11510 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11511 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11512 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11513 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11514 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11515 | break; | |
11516 | case 1: | |
11517 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11518 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11519 | break; | |
11520 | } | |
e9670677 | 11521 | |
316f5878 | 11522 | /* End of GCC-shared inference code. */ |
e9670677 | 11523 | |
17a2f251 TS |
11524 | /* This flag is set when we have a 64-bit capable CPU but use only |
11525 | 32-bit wide registers. Note that EABI does not use it. */ | |
11526 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11527 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11528 | || mips_abi == O32_ABI)) | |
316f5878 | 11529 | mips_32bitmode = 1; |
e9670677 MR |
11530 | |
11531 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11532 | as_bad (_("trap exception not supported at ISA 1")); | |
11533 | ||
e9670677 MR |
11534 | /* If the selected architecture includes support for ASEs, enable |
11535 | generation of code for them. */ | |
a4672219 | 11536 | if (mips_opts.mips16 == -1) |
fef14a42 | 11537 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11538 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11539 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11540 | && file_mips_fp32 == 0) ? 1 : 0; |
11541 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11542 | as_bad (_("-mfp32 used with -mips3d")); | |
11543 | ||
ffdefa66 | 11544 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11545 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11546 | && file_mips_fp32 == 0) ? 1 : 0; |
11547 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11548 | as_bad (_("-mfp32 used with -mdmx")); | |
11549 | ||
11550 | if (mips_opts.ase_smartmips == -1) | |
11551 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11552 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11553 | as_warn ("%s ISA does not support SmartMIPS", | |
11554 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11555 | ||
74cd071d | 11556 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11557 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11558 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11559 | as_warn ("%s ISA does not support DSP ASE", | |
11560 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11561 | ||
8b082fb1 TS |
11562 | if (mips_opts.ase_dspr2 == -1) |
11563 | { | |
11564 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11565 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11566 | } | |
11567 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
11568 | as_warn ("%s ISA does not support DSP R2 ASE", | |
11569 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11570 | ||
ef2e4d86 | 11571 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11572 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11573 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
8b082fb1 | 11574 | as_warn ("%s ISA does not support MT ASE", |
ad3fea08 | 11575 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
e9670677 | 11576 | |
e9670677 | 11577 | file_mips_isa = mips_opts.isa; |
a4672219 | 11578 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11579 | file_ase_mips3d = mips_opts.ase_mips3d; |
11580 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11581 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11582 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11583 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11584 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11585 | mips_opts.gp32 = file_mips_gp32; |
11586 | mips_opts.fp32 = file_mips_fp32; | |
11587 | ||
ecb4347a DJ |
11588 | if (mips_flag_mdebug < 0) |
11589 | { | |
11590 | #ifdef OBJ_MAYBE_ECOFF | |
11591 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11592 | mips_flag_mdebug = 1; | |
11593 | else | |
11594 | #endif /* OBJ_MAYBE_ECOFF */ | |
11595 | mips_flag_mdebug = 0; | |
11596 | } | |
e9670677 MR |
11597 | } |
11598 | \f | |
11599 | void | |
17a2f251 | 11600 | mips_init_after_args (void) |
252b5132 RH |
11601 | { |
11602 | /* initialize opcodes */ | |
11603 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11604 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11605 | } |
11606 | ||
11607 | long | |
17a2f251 | 11608 | md_pcrel_from (fixS *fixP) |
252b5132 | 11609 | { |
a7ebbfdf TS |
11610 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11611 | switch (fixP->fx_r_type) | |
11612 | { | |
11613 | case BFD_RELOC_16_PCREL_S2: | |
11614 | case BFD_RELOC_MIPS_JMP: | |
11615 | /* Return the address of the delay slot. */ | |
11616 | return addr + 4; | |
11617 | default: | |
58ea3d6a | 11618 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11619 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11620 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11621 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11622 | return addr; |
11623 | } | |
252b5132 RH |
11624 | } |
11625 | ||
252b5132 RH |
11626 | /* This is called before the symbol table is processed. In order to |
11627 | work with gcc when using mips-tfile, we must keep all local labels. | |
11628 | However, in other cases, we want to discard them. If we were | |
11629 | called with -g, but we didn't see any debugging information, it may | |
11630 | mean that gcc is smuggling debugging information through to | |
11631 | mips-tfile, in which case we must generate all local labels. */ | |
11632 | ||
11633 | void | |
17a2f251 | 11634 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11635 | { |
11636 | #ifndef NO_ECOFF_DEBUGGING | |
11637 | if (ECOFF_DEBUGGING | |
11638 | && mips_debug != 0 | |
11639 | && ! ecoff_debugging_seen) | |
11640 | flag_keep_locals = 1; | |
11641 | #endif | |
11642 | } | |
11643 | ||
3b91255e | 11644 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11645 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11646 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11647 | relocation operators. | |
11648 | ||
11649 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11650 | expression if: | |
11651 | ||
11652 | (a) it refers to the same symbol; and | |
11653 | (b) the offset applied in the %lo() expression is no lower than | |
11654 | the offset applied in the %got() or %hi(). | |
11655 | ||
11656 | (b) allows us to cope with code like: | |
11657 | ||
11658 | lui $4,%hi(foo) | |
11659 | lh $4,%lo(foo+2)($4) | |
11660 | ||
11661 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11662 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11663 | the high 16 bits. | |
11664 | ||
11665 | When several %lo()s match a particular %got() or %hi(), we use the | |
11666 | following rules to distinguish them: | |
11667 | ||
11668 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11669 | higher offsets. | |
11670 | ||
11671 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11672 | that already have a matching %got() or %hi(). | |
11673 | ||
11674 | (3) later %lo()s are better than earlier %lo()s. | |
11675 | ||
11676 | These rules are applied in order. | |
11677 | ||
11678 | (1) means, among other things, that %lo()s with identical offsets are | |
11679 | chosen if they exist. | |
11680 | ||
11681 | (2) means that we won't associate several high-part relocations with | |
11682 | the same low-part relocation unless there's no alternative. Having | |
11683 | several high parts for the same low part is a GNU extension; this rule | |
11684 | allows careful users to avoid it. | |
11685 | ||
11686 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11687 | with the last high-part relocation being at the front of the list. | |
11688 | It therefore makes sense to choose the last matching low-part | |
11689 | relocation, all other things being equal. It's also easier | |
11690 | to code that way. */ | |
252b5132 RH |
11691 | |
11692 | void | |
17a2f251 | 11693 | mips_frob_file (void) |
252b5132 RH |
11694 | { |
11695 | struct mips_hi_fixup *l; | |
11696 | ||
11697 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11698 | { | |
11699 | segment_info_type *seginfo; | |
3b91255e RS |
11700 | bfd_boolean matched_lo_p; |
11701 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11702 | |
5919d012 | 11703 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11704 | |
5919d012 RS |
11705 | /* If a GOT16 relocation turns out to be against a global symbol, |
11706 | there isn't supposed to be a matching LO. */ | |
11707 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11708 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11709 | continue; | |
11710 | ||
11711 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11712 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11713 | continue; |
11714 | ||
252b5132 | 11715 | seginfo = seg_info (l->seg); |
252b5132 | 11716 | |
3b91255e RS |
11717 | /* Set HI_POS to the position of this relocation in the chain. |
11718 | Set LO_POS to the position of the chosen low-part relocation. | |
11719 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11720 | relocation that matches an immediately-preceding high-part | |
11721 | relocation. */ | |
11722 | hi_pos = NULL; | |
11723 | lo_pos = NULL; | |
11724 | matched_lo_p = FALSE; | |
11725 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11726 | { | |
11727 | if (*pos == l->fixp) | |
11728 | hi_pos = pos; | |
11729 | ||
704803a9 MR |
11730 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11731 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11732 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11733 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11734 | && (lo_pos == NULL | |
11735 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11736 | || (!matched_lo_p | |
11737 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11738 | lo_pos = pos; | |
11739 | ||
11740 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11741 | && fixup_has_matching_lo_p (*pos)); | |
11742 | } | |
11743 | ||
11744 | /* If we found a match, remove the high-part relocation from its | |
11745 | current position and insert it before the low-part relocation. | |
11746 | Make the offsets match so that fixup_has_matching_lo_p() | |
11747 | will return true. | |
11748 | ||
11749 | We don't warn about unmatched high-part relocations since some | |
11750 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11751 | instructions. */ | |
11752 | if (lo_pos != NULL) | |
11753 | { | |
11754 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11755 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11756 | { |
3b91255e RS |
11757 | *hi_pos = l->fixp->fx_next; |
11758 | l->fixp->fx_next = *lo_pos; | |
11759 | *lo_pos = l->fixp; | |
252b5132 | 11760 | } |
252b5132 RH |
11761 | } |
11762 | } | |
11763 | } | |
11764 | ||
3e722fb5 | 11765 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11766 | We have to prevent gas from dropping them. */ |
252b5132 | 11767 | |
252b5132 | 11768 | int |
17a2f251 | 11769 | mips_force_relocation (fixS *fixp) |
252b5132 | 11770 | { |
ae6063d4 | 11771 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11772 | return 1; |
11773 | ||
f6688943 TS |
11774 | if (HAVE_NEWABI |
11775 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11776 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11777 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11778 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11779 | return 1; | |
11780 | ||
3e722fb5 | 11781 | return 0; |
252b5132 RH |
11782 | } |
11783 | ||
11784 | /* Apply a fixup to the object file. */ | |
11785 | ||
94f592af | 11786 | void |
55cf6793 | 11787 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11788 | { |
874e8986 | 11789 | bfd_byte *buf; |
98aa84af | 11790 | long insn; |
a7ebbfdf | 11791 | reloc_howto_type *howto; |
252b5132 | 11792 | |
a7ebbfdf TS |
11793 | /* We ignore generic BFD relocations we don't know about. */ |
11794 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11795 | if (! howto) | |
11796 | return; | |
65551fa4 | 11797 | |
252b5132 RH |
11798 | assert (fixP->fx_size == 4 |
11799 | || fixP->fx_r_type == BFD_RELOC_16 | |
11800 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11801 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11802 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11803 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
11804 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11805 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 11806 | |
a7ebbfdf | 11807 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11808 | |
3994f87e | 11809 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11810 | |
11811 | /* Don't treat parts of a composite relocation as done. There are two | |
11812 | reasons for this: | |
11813 | ||
11814 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11815 | should nevertheless be emitted if the first part is. | |
11816 | ||
11817 | (2) In normal usage, composite relocations are never assembly-time | |
11818 | constants. The easiest way of dealing with the pathological | |
11819 | exceptions is to generate a relocation against STN_UNDEF and | |
11820 | leave everything up to the linker. */ | |
3994f87e | 11821 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11822 | fixP->fx_done = 1; |
11823 | ||
11824 | switch (fixP->fx_r_type) | |
11825 | { | |
3f98094e DJ |
11826 | case BFD_RELOC_MIPS_TLS_GD: |
11827 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
11828 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
11829 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
11830 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
11831 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11832 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11833 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11834 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11835 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11836 | /* fall through */ | |
11837 | ||
252b5132 | 11838 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11839 | case BFD_RELOC_MIPS_SHIFT5: |
11840 | case BFD_RELOC_MIPS_SHIFT6: | |
11841 | case BFD_RELOC_MIPS_GOT_DISP: | |
11842 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11843 | case BFD_RELOC_MIPS_GOT_OFST: | |
11844 | case BFD_RELOC_MIPS_SUB: | |
11845 | case BFD_RELOC_MIPS_INSERT_A: | |
11846 | case BFD_RELOC_MIPS_INSERT_B: | |
11847 | case BFD_RELOC_MIPS_DELETE: | |
11848 | case BFD_RELOC_MIPS_HIGHEST: | |
11849 | case BFD_RELOC_MIPS_HIGHER: | |
11850 | case BFD_RELOC_MIPS_SCN_DISP: | |
11851 | case BFD_RELOC_MIPS_REL16: | |
11852 | case BFD_RELOC_MIPS_RELGOT: | |
11853 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11854 | case BFD_RELOC_HI16: |
11855 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11856 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11857 | case BFD_RELOC_MIPS_LITERAL: |
11858 | case BFD_RELOC_MIPS_CALL16: | |
11859 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11860 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11861 | case BFD_RELOC_MIPS_GOT_HI16: |
11862 | case BFD_RELOC_MIPS_GOT_LO16: | |
11863 | case BFD_RELOC_MIPS_CALL_HI16: | |
11864 | case BFD_RELOC_MIPS_CALL_LO16: | |
11865 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11866 | case BFD_RELOC_MIPS16_HI16: |
11867 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 11868 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 11869 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
11870 | break; |
11871 | ||
252b5132 RH |
11872 | case BFD_RELOC_64: |
11873 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11874 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11875 | if (fixP->fx_done) |
252b5132 RH |
11876 | { |
11877 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11878 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11879 | else |
11880 | { | |
a7ebbfdf | 11881 | valueT hiv; |
252b5132 | 11882 | |
a7ebbfdf | 11883 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11884 | hiv = 0xffffffff; |
11885 | else | |
11886 | hiv = 0; | |
b215186b | 11887 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11888 | *valP, 4); |
b215186b | 11889 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11890 | hiv, 4); |
252b5132 RH |
11891 | } |
11892 | } | |
11893 | break; | |
11894 | ||
056350c6 | 11895 | case BFD_RELOC_RVA: |
252b5132 | 11896 | case BFD_RELOC_32: |
252b5132 RH |
11897 | case BFD_RELOC_16: |
11898 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
11899 | value now. This can happen if we have a .word which is not |
11900 | resolved when it appears but is later defined. */ | |
252b5132 | 11901 | if (fixP->fx_done) |
54f4ddb3 | 11902 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
11903 | break; |
11904 | ||
11905 | case BFD_RELOC_LO16: | |
d6f16593 | 11906 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11907 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11908 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11909 | /* When handling an embedded PIC switch statement, we can wind |
11910 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11911 | if (fixP->fx_done) | |
11912 | { | |
a7ebbfdf | 11913 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11914 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11915 | _("relocation overflow")); | |
252b5132 RH |
11916 | if (target_big_endian) |
11917 | buf += 2; | |
2132e3a3 | 11918 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11919 | } |
11920 | break; | |
11921 | ||
11922 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11923 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11924 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11925 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11926 | |
54f4ddb3 TS |
11927 | /* We need to save the bits in the instruction since fixup_segment() |
11928 | might be deleting the relocation entry (i.e., a branch within | |
11929 | the current segment). */ | |
a7ebbfdf | 11930 | if (! fixP->fx_done) |
bb2d6cd7 | 11931 | break; |
252b5132 | 11932 | |
54f4ddb3 | 11933 | /* Update old instruction data. */ |
252b5132 RH |
11934 | if (target_big_endian) |
11935 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11936 | else | |
11937 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11938 | ||
a7ebbfdf TS |
11939 | if (*valP + 0x20000 <= 0x3ffff) |
11940 | { | |
11941 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11942 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11943 | } |
11944 | else if (mips_pic == NO_PIC | |
11945 | && fixP->fx_done | |
11946 | && fixP->fx_frag->fr_address >= text_section->vma | |
11947 | && (fixP->fx_frag->fr_address | |
587aac4e | 11948 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11949 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11950 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11951 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11952 | { |
11953 | /* The branch offset is too large. If this is an | |
11954 | unconditional branch, and we are not generating PIC code, | |
11955 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11956 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11957 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11958 | else |
a7ebbfdf TS |
11959 | insn = 0x08000000; /* j */ |
11960 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11961 | fixP->fx_done = 0; | |
11962 | fixP->fx_addsy = section_symbol (text_section); | |
11963 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11964 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11965 | } |
11966 | else | |
11967 | { | |
11968 | /* If we got here, we have branch-relaxation disabled, | |
11969 | and there's nothing we can do to fix this instruction | |
11970 | without turning it into a longer sequence. */ | |
11971 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11972 | _("Branch out of range")); | |
252b5132 | 11973 | } |
252b5132 RH |
11974 | break; |
11975 | ||
11976 | case BFD_RELOC_VTABLE_INHERIT: | |
11977 | fixP->fx_done = 0; | |
11978 | if (fixP->fx_addsy | |
11979 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11980 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11981 | S_SET_WEAK (fixP->fx_addsy); | |
11982 | break; | |
11983 | ||
11984 | case BFD_RELOC_VTABLE_ENTRY: | |
11985 | fixP->fx_done = 0; | |
11986 | break; | |
11987 | ||
11988 | default: | |
11989 | internalError (); | |
11990 | } | |
a7ebbfdf TS |
11991 | |
11992 | /* Remember value for tc_gen_reloc. */ | |
11993 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11994 | } |
11995 | ||
252b5132 | 11996 | static symbolS * |
17a2f251 | 11997 | get_symbol (void) |
252b5132 RH |
11998 | { |
11999 | int c; | |
12000 | char *name; | |
12001 | symbolS *p; | |
12002 | ||
12003 | name = input_line_pointer; | |
12004 | c = get_symbol_end (); | |
12005 | p = (symbolS *) symbol_find_or_make (name); | |
12006 | *input_line_pointer = c; | |
12007 | return p; | |
12008 | } | |
12009 | ||
742a56fe RS |
12010 | /* Align the current frag to a given power of two. If a particular |
12011 | fill byte should be used, FILL points to an integer that contains | |
12012 | that byte, otherwise FILL is null. | |
12013 | ||
12014 | The MIPS assembler also automatically adjusts any preceding | |
12015 | label. */ | |
252b5132 RH |
12016 | |
12017 | static void | |
742a56fe | 12018 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12019 | { |
7d10b47d | 12020 | mips_emit_delays (); |
742a56fe RS |
12021 | mips_record_mips16_mode (); |
12022 | if (fill == NULL && subseg_text_p (now_seg)) | |
12023 | frag_align_code (to, 0); | |
12024 | else | |
12025 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12026 | record_alignment (now_seg, to); |
12027 | if (label != NULL) | |
12028 | { | |
12029 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 12030 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12031 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12032 | } | |
12033 | } | |
12034 | ||
12035 | /* Align to a given power of two. .align 0 turns off the automatic | |
12036 | alignment used by the data creating pseudo-ops. */ | |
12037 | ||
12038 | static void | |
17a2f251 | 12039 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12040 | { |
742a56fe | 12041 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12042 | long max_alignment = 28; |
252b5132 | 12043 | |
54f4ddb3 | 12044 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12045 | to the aligned address. |
54f4ddb3 | 12046 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12047 | a .align pseudo instruction. |
54f4ddb3 | 12048 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12049 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12050 | We don't. */ |
252b5132 RH |
12051 | |
12052 | temp = get_absolute_expression (); | |
12053 | if (temp > max_alignment) | |
12054 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12055 | else if (temp < 0) | |
12056 | { | |
12057 | as_warn (_("Alignment negative: 0 assumed.")); | |
12058 | temp = 0; | |
12059 | } | |
12060 | if (*input_line_pointer == ',') | |
12061 | { | |
f9419b05 | 12062 | ++input_line_pointer; |
742a56fe RS |
12063 | fill_value = get_absolute_expression (); |
12064 | fill_ptr = &fill_value; | |
252b5132 RH |
12065 | } |
12066 | else | |
742a56fe | 12067 | fill_ptr = 0; |
252b5132 RH |
12068 | if (temp) |
12069 | { | |
a8dbcb85 TS |
12070 | segment_info_type *si = seg_info (now_seg); |
12071 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12072 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12073 | auto_align = 1; |
742a56fe | 12074 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12075 | } |
12076 | else | |
12077 | { | |
12078 | auto_align = 0; | |
12079 | } | |
12080 | ||
12081 | demand_empty_rest_of_line (); | |
12082 | } | |
12083 | ||
252b5132 | 12084 | static void |
17a2f251 | 12085 | s_change_sec (int sec) |
252b5132 RH |
12086 | { |
12087 | segT seg; | |
12088 | ||
252b5132 RH |
12089 | #ifdef OBJ_ELF |
12090 | /* The ELF backend needs to know that we are changing sections, so | |
12091 | that .previous works correctly. We could do something like check | |
b6ff326e | 12092 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12093 | as it would not be appropriate to use it in the section changing |
12094 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12095 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12096 | if (IS_ELF) |
12097 | obj_elf_section_change_hook (); | |
252b5132 RH |
12098 | #endif |
12099 | ||
7d10b47d | 12100 | mips_emit_delays (); |
252b5132 RH |
12101 | switch (sec) |
12102 | { | |
12103 | case 't': | |
12104 | s_text (0); | |
12105 | break; | |
12106 | case 'd': | |
12107 | s_data (0); | |
12108 | break; | |
12109 | case 'b': | |
12110 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12111 | demand_empty_rest_of_line (); | |
12112 | break; | |
12113 | ||
12114 | case 'r': | |
4d0d148d TS |
12115 | seg = subseg_new (RDATA_SECTION_NAME, |
12116 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12117 | if (IS_ELF) |
252b5132 | 12118 | { |
4d0d148d TS |
12119 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12120 | | SEC_READONLY | SEC_RELOC | |
12121 | | SEC_DATA)); | |
12122 | if (strcmp (TARGET_OS, "elf") != 0) | |
12123 | record_alignment (seg, 4); | |
252b5132 | 12124 | } |
4d0d148d | 12125 | demand_empty_rest_of_line (); |
252b5132 RH |
12126 | break; |
12127 | ||
12128 | case 's': | |
4d0d148d | 12129 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12130 | if (IS_ELF) |
252b5132 | 12131 | { |
4d0d148d TS |
12132 | bfd_set_section_flags (stdoutput, seg, |
12133 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12134 | if (strcmp (TARGET_OS, "elf") != 0) | |
12135 | record_alignment (seg, 4); | |
252b5132 | 12136 | } |
4d0d148d TS |
12137 | demand_empty_rest_of_line (); |
12138 | break; | |
252b5132 RH |
12139 | } |
12140 | ||
12141 | auto_align = 1; | |
12142 | } | |
b34976b6 | 12143 | |
cca86cc8 | 12144 | void |
17a2f251 | 12145 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12146 | { |
7ed4a06a | 12147 | #ifdef OBJ_ELF |
cca86cc8 SC |
12148 | char *section_name; |
12149 | char c; | |
684022ea | 12150 | char next_c = 0; |
cca86cc8 SC |
12151 | int section_type; |
12152 | int section_flag; | |
12153 | int section_entry_size; | |
12154 | int section_alignment; | |
b34976b6 | 12155 | |
f43abd2b | 12156 | if (!IS_ELF) |
7ed4a06a TS |
12157 | return; |
12158 | ||
cca86cc8 SC |
12159 | section_name = input_line_pointer; |
12160 | c = get_symbol_end (); | |
a816d1ed AO |
12161 | if (c) |
12162 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12163 | |
4cf0dd0d TS |
12164 | /* Do we have .section Name<,"flags">? */ |
12165 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12166 | { |
4cf0dd0d TS |
12167 | /* just after name is now '\0'. */ |
12168 | *input_line_pointer = c; | |
cca86cc8 SC |
12169 | input_line_pointer = section_name; |
12170 | obj_elf_section (ignore); | |
12171 | return; | |
12172 | } | |
12173 | input_line_pointer++; | |
12174 | ||
12175 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12176 | if (c == ',') | |
12177 | section_type = get_absolute_expression (); | |
12178 | else | |
12179 | section_type = 0; | |
12180 | if (*input_line_pointer++ == ',') | |
12181 | section_flag = get_absolute_expression (); | |
12182 | else | |
12183 | section_flag = 0; | |
12184 | if (*input_line_pointer++ == ',') | |
12185 | section_entry_size = get_absolute_expression (); | |
12186 | else | |
12187 | section_entry_size = 0; | |
12188 | if (*input_line_pointer++ == ',') | |
12189 | section_alignment = get_absolute_expression (); | |
12190 | else | |
12191 | section_alignment = 0; | |
12192 | ||
a816d1ed AO |
12193 | section_name = xstrdup (section_name); |
12194 | ||
8ab8a5c8 RS |
12195 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12196 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12197 | traditionally had to fall back on the more common @progbits instead. | |
12198 | ||
12199 | There's nothing really harmful in this, since bfd will correct | |
12200 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12201 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12202 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12203 | ||
12204 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12205 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12206 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12207 | generic type-checking code. */ | |
12208 | if (section_type == SHT_MIPS_DWARF) | |
12209 | section_type = SHT_PROGBITS; | |
12210 | ||
cca86cc8 SC |
12211 | obj_elf_change_section (section_name, section_type, section_flag, |
12212 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12213 | |
12214 | if (now_seg->name != section_name) | |
12215 | free (section_name); | |
7ed4a06a | 12216 | #endif /* OBJ_ELF */ |
cca86cc8 | 12217 | } |
252b5132 RH |
12218 | |
12219 | void | |
17a2f251 | 12220 | mips_enable_auto_align (void) |
252b5132 RH |
12221 | { |
12222 | auto_align = 1; | |
12223 | } | |
12224 | ||
12225 | static void | |
17a2f251 | 12226 | s_cons (int log_size) |
252b5132 | 12227 | { |
a8dbcb85 TS |
12228 | segment_info_type *si = seg_info (now_seg); |
12229 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12230 | symbolS *label; |
12231 | ||
a8dbcb85 | 12232 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12233 | mips_emit_delays (); |
252b5132 RH |
12234 | if (log_size > 0 && auto_align) |
12235 | mips_align (log_size, 0, label); | |
12236 | mips_clear_insn_labels (); | |
12237 | cons (1 << log_size); | |
12238 | } | |
12239 | ||
12240 | static void | |
17a2f251 | 12241 | s_float_cons (int type) |
252b5132 | 12242 | { |
a8dbcb85 TS |
12243 | segment_info_type *si = seg_info (now_seg); |
12244 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12245 | symbolS *label; |
12246 | ||
a8dbcb85 | 12247 | label = l != NULL ? l->label : NULL; |
252b5132 | 12248 | |
7d10b47d | 12249 | mips_emit_delays (); |
252b5132 RH |
12250 | |
12251 | if (auto_align) | |
49309057 ILT |
12252 | { |
12253 | if (type == 'd') | |
12254 | mips_align (3, 0, label); | |
12255 | else | |
12256 | mips_align (2, 0, label); | |
12257 | } | |
252b5132 RH |
12258 | |
12259 | mips_clear_insn_labels (); | |
12260 | ||
12261 | float_cons (type); | |
12262 | } | |
12263 | ||
12264 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12265 | permitted to say | |
12266 | .globl foo .text | |
12267 | where foo is an undefined symbol, to mean that foo should be | |
12268 | considered to be the address of a function. */ | |
12269 | ||
12270 | static void | |
17a2f251 | 12271 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12272 | { |
12273 | char *name; | |
12274 | int c; | |
12275 | symbolS *symbolP; | |
12276 | flagword flag; | |
12277 | ||
8a06b769 | 12278 | do |
252b5132 | 12279 | { |
8a06b769 | 12280 | name = input_line_pointer; |
252b5132 | 12281 | c = get_symbol_end (); |
8a06b769 TS |
12282 | symbolP = symbol_find_or_make (name); |
12283 | S_SET_EXTERNAL (symbolP); | |
12284 | ||
252b5132 | 12285 | *input_line_pointer = c; |
8a06b769 | 12286 | SKIP_WHITESPACE (); |
252b5132 | 12287 | |
8a06b769 TS |
12288 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12289 | being a function is apparently labelled as being an object. */ | |
12290 | flag = BSF_OBJECT; | |
252b5132 | 12291 | |
8a06b769 TS |
12292 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12293 | && (*input_line_pointer != ',')) | |
12294 | { | |
12295 | char *secname; | |
12296 | asection *sec; | |
12297 | ||
12298 | secname = input_line_pointer; | |
12299 | c = get_symbol_end (); | |
12300 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12301 | if (sec == NULL) | |
12302 | as_bad (_("%s: no such section"), secname); | |
12303 | *input_line_pointer = c; | |
12304 | ||
12305 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12306 | flag = BSF_FUNCTION; | |
12307 | } | |
12308 | ||
12309 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12310 | ||
12311 | c = *input_line_pointer; | |
12312 | if (c == ',') | |
12313 | { | |
12314 | input_line_pointer++; | |
12315 | SKIP_WHITESPACE (); | |
12316 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12317 | c = '\n'; | |
12318 | } | |
12319 | } | |
12320 | while (c == ','); | |
252b5132 | 12321 | |
252b5132 RH |
12322 | demand_empty_rest_of_line (); |
12323 | } | |
12324 | ||
12325 | static void | |
17a2f251 | 12326 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12327 | { |
12328 | char *opt; | |
12329 | char c; | |
12330 | ||
12331 | opt = input_line_pointer; | |
12332 | c = get_symbol_end (); | |
12333 | ||
12334 | if (*opt == 'O') | |
12335 | { | |
12336 | /* FIXME: What does this mean? */ | |
12337 | } | |
12338 | else if (strncmp (opt, "pic", 3) == 0) | |
12339 | { | |
12340 | int i; | |
12341 | ||
12342 | i = atoi (opt + 3); | |
12343 | if (i == 0) | |
12344 | mips_pic = NO_PIC; | |
12345 | else if (i == 2) | |
143d77c5 | 12346 | { |
252b5132 | 12347 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12348 | mips_abicalls = TRUE; |
12349 | } | |
252b5132 RH |
12350 | else |
12351 | as_bad (_(".option pic%d not supported"), i); | |
12352 | ||
4d0d148d | 12353 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12354 | { |
12355 | if (g_switch_seen && g_switch_value != 0) | |
12356 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12357 | g_switch_value = 0; | |
12358 | bfd_set_gp_size (stdoutput, 0); | |
12359 | } | |
12360 | } | |
12361 | else | |
12362 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12363 | ||
12364 | *input_line_pointer = c; | |
12365 | demand_empty_rest_of_line (); | |
12366 | } | |
12367 | ||
12368 | /* This structure is used to hold a stack of .set values. */ | |
12369 | ||
e972090a NC |
12370 | struct mips_option_stack |
12371 | { | |
252b5132 RH |
12372 | struct mips_option_stack *next; |
12373 | struct mips_set_options options; | |
12374 | }; | |
12375 | ||
12376 | static struct mips_option_stack *mips_opts_stack; | |
12377 | ||
12378 | /* Handle the .set pseudo-op. */ | |
12379 | ||
12380 | static void | |
17a2f251 | 12381 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12382 | { |
12383 | char *name = input_line_pointer, ch; | |
12384 | ||
12385 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12386 | ++input_line_pointer; |
252b5132 RH |
12387 | ch = *input_line_pointer; |
12388 | *input_line_pointer = '\0'; | |
12389 | ||
12390 | if (strcmp (name, "reorder") == 0) | |
12391 | { | |
7d10b47d RS |
12392 | if (mips_opts.noreorder) |
12393 | end_noreorder (); | |
252b5132 RH |
12394 | } |
12395 | else if (strcmp (name, "noreorder") == 0) | |
12396 | { | |
7d10b47d RS |
12397 | if (!mips_opts.noreorder) |
12398 | start_noreorder (); | |
252b5132 | 12399 | } |
741fe287 MR |
12400 | else if (strncmp (name, "at=", 3) == 0) |
12401 | { | |
12402 | char *s = name + 3; | |
12403 | ||
12404 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12405 | as_bad (_("Unrecognized register name `%s'"), s); | |
12406 | } | |
252b5132 RH |
12407 | else if (strcmp (name, "at") == 0) |
12408 | { | |
741fe287 | 12409 | mips_opts.at = ATREG; |
252b5132 RH |
12410 | } |
12411 | else if (strcmp (name, "noat") == 0) | |
12412 | { | |
741fe287 | 12413 | mips_opts.at = ZERO; |
252b5132 RH |
12414 | } |
12415 | else if (strcmp (name, "macro") == 0) | |
12416 | { | |
12417 | mips_opts.warn_about_macros = 0; | |
12418 | } | |
12419 | else if (strcmp (name, "nomacro") == 0) | |
12420 | { | |
12421 | if (mips_opts.noreorder == 0) | |
12422 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12423 | mips_opts.warn_about_macros = 1; | |
12424 | } | |
12425 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12426 | { | |
12427 | mips_opts.nomove = 0; | |
12428 | } | |
12429 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12430 | { | |
12431 | mips_opts.nomove = 1; | |
12432 | } | |
12433 | else if (strcmp (name, "bopt") == 0) | |
12434 | { | |
12435 | mips_opts.nobopt = 0; | |
12436 | } | |
12437 | else if (strcmp (name, "nobopt") == 0) | |
12438 | { | |
12439 | mips_opts.nobopt = 1; | |
12440 | } | |
ad3fea08 TS |
12441 | else if (strcmp (name, "gp=default") == 0) |
12442 | mips_opts.gp32 = file_mips_gp32; | |
12443 | else if (strcmp (name, "gp=32") == 0) | |
12444 | mips_opts.gp32 = 1; | |
12445 | else if (strcmp (name, "gp=64") == 0) | |
12446 | { | |
12447 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12448 | as_warn ("%s isa does not support 64-bit registers", | |
12449 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12450 | mips_opts.gp32 = 0; | |
12451 | } | |
12452 | else if (strcmp (name, "fp=default") == 0) | |
12453 | mips_opts.fp32 = file_mips_fp32; | |
12454 | else if (strcmp (name, "fp=32") == 0) | |
12455 | mips_opts.fp32 = 1; | |
12456 | else if (strcmp (name, "fp=64") == 0) | |
12457 | { | |
12458 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12459 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12460 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12461 | mips_opts.fp32 = 0; | |
12462 | } | |
252b5132 RH |
12463 | else if (strcmp (name, "mips16") == 0 |
12464 | || strcmp (name, "MIPS-16") == 0) | |
12465 | mips_opts.mips16 = 1; | |
12466 | else if (strcmp (name, "nomips16") == 0 | |
12467 | || strcmp (name, "noMIPS-16") == 0) | |
12468 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12469 | else if (strcmp (name, "smartmips") == 0) |
12470 | { | |
ad3fea08 | 12471 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12472 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12473 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12474 | mips_opts.ase_smartmips = 1; | |
12475 | } | |
12476 | else if (strcmp (name, "nosmartmips") == 0) | |
12477 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12478 | else if (strcmp (name, "mips3d") == 0) |
12479 | mips_opts.ase_mips3d = 1; | |
12480 | else if (strcmp (name, "nomips3d") == 0) | |
12481 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12482 | else if (strcmp (name, "mdmx") == 0) |
12483 | mips_opts.ase_mdmx = 1; | |
12484 | else if (strcmp (name, "nomdmx") == 0) | |
12485 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12486 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12487 | { |
12488 | if (!ISA_SUPPORTS_DSP_ASE) | |
12489 | as_warn ("%s ISA does not support DSP ASE", | |
12490 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12491 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12492 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12493 | } |
74cd071d | 12494 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12495 | { |
12496 | mips_opts.ase_dsp = 0; | |
12497 | mips_opts.ase_dspr2 = 0; | |
12498 | } | |
12499 | else if (strcmp (name, "dspr2") == 0) | |
12500 | { | |
12501 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
12502 | as_warn ("%s ISA does not support DSP R2 ASE", | |
12503 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12504 | mips_opts.ase_dspr2 = 1; | |
12505 | mips_opts.ase_dsp = 1; | |
12506 | } | |
12507 | else if (strcmp (name, "nodspr2") == 0) | |
12508 | { | |
12509 | mips_opts.ase_dspr2 = 0; | |
12510 | mips_opts.ase_dsp = 0; | |
12511 | } | |
ef2e4d86 | 12512 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12513 | { |
12514 | if (!ISA_SUPPORTS_MT_ASE) | |
12515 | as_warn ("%s ISA does not support MT ASE", | |
12516 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12517 | mips_opts.ase_mt = 1; | |
12518 | } | |
ef2e4d86 CF |
12519 | else if (strcmp (name, "nomt") == 0) |
12520 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12521 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12522 | { |
af7ee8bf | 12523 | int reset = 0; |
252b5132 | 12524 | |
1a2c1fad CD |
12525 | /* Permit the user to change the ISA and architecture on the fly. |
12526 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12527 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12528 | { |
12529 | reset = 1; | |
12530 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12531 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12532 | } |
12533 | else if (strncmp (name, "arch=", 5) == 0) | |
12534 | { | |
12535 | const struct mips_cpu_info *p; | |
12536 | ||
12537 | p = mips_parse_cpu("internal use", name + 5); | |
12538 | if (!p) | |
12539 | as_bad (_("unknown architecture %s"), name + 5); | |
12540 | else | |
12541 | { | |
12542 | mips_opts.arch = p->cpu; | |
12543 | mips_opts.isa = p->isa; | |
12544 | } | |
12545 | } | |
81a21e38 TS |
12546 | else if (strncmp (name, "mips", 4) == 0) |
12547 | { | |
12548 | const struct mips_cpu_info *p; | |
12549 | ||
12550 | p = mips_parse_cpu("internal use", name); | |
12551 | if (!p) | |
12552 | as_bad (_("unknown ISA level %s"), name + 4); | |
12553 | else | |
12554 | { | |
12555 | mips_opts.arch = p->cpu; | |
12556 | mips_opts.isa = p->isa; | |
12557 | } | |
12558 | } | |
af7ee8bf | 12559 | else |
81a21e38 | 12560 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12561 | |
12562 | switch (mips_opts.isa) | |
98d3f06f KH |
12563 | { |
12564 | case 0: | |
98d3f06f | 12565 | break; |
af7ee8bf CD |
12566 | case ISA_MIPS1: |
12567 | case ISA_MIPS2: | |
12568 | case ISA_MIPS32: | |
12569 | case ISA_MIPS32R2: | |
98d3f06f KH |
12570 | mips_opts.gp32 = 1; |
12571 | mips_opts.fp32 = 1; | |
12572 | break; | |
af7ee8bf CD |
12573 | case ISA_MIPS3: |
12574 | case ISA_MIPS4: | |
12575 | case ISA_MIPS5: | |
12576 | case ISA_MIPS64: | |
5f74bc13 | 12577 | case ISA_MIPS64R2: |
98d3f06f KH |
12578 | mips_opts.gp32 = 0; |
12579 | mips_opts.fp32 = 0; | |
12580 | break; | |
12581 | default: | |
12582 | as_bad (_("unknown ISA level %s"), name + 4); | |
12583 | break; | |
12584 | } | |
af7ee8bf | 12585 | if (reset) |
98d3f06f | 12586 | { |
af7ee8bf CD |
12587 | mips_opts.gp32 = file_mips_gp32; |
12588 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12589 | } |
252b5132 RH |
12590 | } |
12591 | else if (strcmp (name, "autoextend") == 0) | |
12592 | mips_opts.noautoextend = 0; | |
12593 | else if (strcmp (name, "noautoextend") == 0) | |
12594 | mips_opts.noautoextend = 1; | |
12595 | else if (strcmp (name, "push") == 0) | |
12596 | { | |
12597 | struct mips_option_stack *s; | |
12598 | ||
12599 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12600 | s->next = mips_opts_stack; | |
12601 | s->options = mips_opts; | |
12602 | mips_opts_stack = s; | |
12603 | } | |
12604 | else if (strcmp (name, "pop") == 0) | |
12605 | { | |
12606 | struct mips_option_stack *s; | |
12607 | ||
12608 | s = mips_opts_stack; | |
12609 | if (s == NULL) | |
12610 | as_bad (_(".set pop with no .set push")); | |
12611 | else | |
12612 | { | |
12613 | /* If we're changing the reorder mode we need to handle | |
12614 | delay slots correctly. */ | |
12615 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12616 | start_noreorder (); |
252b5132 | 12617 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12618 | end_noreorder (); |
252b5132 RH |
12619 | |
12620 | mips_opts = s->options; | |
12621 | mips_opts_stack = s->next; | |
12622 | free (s); | |
12623 | } | |
12624 | } | |
aed1a261 RS |
12625 | else if (strcmp (name, "sym32") == 0) |
12626 | mips_opts.sym32 = TRUE; | |
12627 | else if (strcmp (name, "nosym32") == 0) | |
12628 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
12629 | else if (strchr (name, ',')) |
12630 | { | |
12631 | /* Generic ".set" directive; use the generic handler. */ | |
12632 | *input_line_pointer = ch; | |
12633 | input_line_pointer = name; | |
12634 | s_set (0); | |
12635 | return; | |
12636 | } | |
252b5132 RH |
12637 | else |
12638 | { | |
12639 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12640 | } | |
12641 | *input_line_pointer = ch; | |
12642 | demand_empty_rest_of_line (); | |
12643 | } | |
12644 | ||
12645 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12646 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12647 | ||
12648 | static void | |
17a2f251 | 12649 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12650 | { |
12651 | mips_pic = SVR4_PIC; | |
143d77c5 | 12652 | mips_abicalls = TRUE; |
4d0d148d TS |
12653 | |
12654 | if (g_switch_seen && g_switch_value != 0) | |
12655 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12656 | g_switch_value = 0; | |
12657 | ||
252b5132 RH |
12658 | bfd_set_gp_size (stdoutput, 0); |
12659 | demand_empty_rest_of_line (); | |
12660 | } | |
12661 | ||
12662 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12663 | PIC code. It sets the $gp register for the function based on the | |
12664 | function address, which is in the register named in the argument. | |
12665 | This uses a relocation against _gp_disp, which is handled specially | |
12666 | by the linker. The result is: | |
12667 | lui $gp,%hi(_gp_disp) | |
12668 | addiu $gp,$gp,%lo(_gp_disp) | |
12669 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12670 | The .cpload argument is normally $25 == $t9. |
12671 | ||
12672 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12673 | lui $gp,%hi(__gnu_local_gp) |
12674 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12675 | and the argument is ignored. This saves an instruction, but the |
12676 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12677 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12678 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12679 | |
12680 | static void | |
17a2f251 | 12681 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12682 | { |
12683 | expressionS ex; | |
aa6975fb ILT |
12684 | int reg; |
12685 | int in_shared; | |
252b5132 | 12686 | |
6478892d TS |
12687 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12688 | .cpload is ignored. */ | |
12689 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12690 | { |
12691 | s_ignore (0); | |
12692 | return; | |
12693 | } | |
12694 | ||
d3ecfc59 | 12695 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12696 | if (mips_opts.noreorder == 0) |
12697 | as_warn (_(".cpload not in noreorder section")); | |
12698 | ||
aa6975fb ILT |
12699 | reg = tc_get_register (0); |
12700 | ||
12701 | /* If we need to produce a 64-bit address, we are better off using | |
12702 | the default instruction sequence. */ | |
aed1a261 | 12703 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12704 | |
252b5132 | 12705 | ex.X_op = O_symbol; |
bbe506e8 TS |
12706 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12707 | "__gnu_local_gp"); | |
252b5132 RH |
12708 | ex.X_op_symbol = NULL; |
12709 | ex.X_add_number = 0; | |
12710 | ||
12711 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12712 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12713 | |
584892a6 | 12714 | macro_start (); |
67c0d1eb RS |
12715 | macro_build_lui (&ex, mips_gp_register); |
12716 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12717 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12718 | if (in_shared) |
12719 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12720 | mips_gp_register, reg); | |
584892a6 | 12721 | macro_end (); |
252b5132 RH |
12722 | |
12723 | demand_empty_rest_of_line (); | |
12724 | } | |
12725 | ||
6478892d TS |
12726 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12727 | .cpsetup $reg1, offset|$reg2, label | |
12728 | ||
12729 | If offset is given, this results in: | |
12730 | sd $gp, offset($sp) | |
956cd1d6 | 12731 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12732 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12733 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12734 | |
12735 | If $reg2 is given, this results in: | |
12736 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12737 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12738 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12739 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12740 | $reg1 is normally $25 == $t9. |
12741 | ||
12742 | The -mno-shared option replaces the last three instructions with | |
12743 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12744 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12745 | |
6478892d | 12746 | static void |
17a2f251 | 12747 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12748 | { |
12749 | expressionS ex_off; | |
12750 | expressionS ex_sym; | |
12751 | int reg1; | |
6478892d | 12752 | |
8586fc66 | 12753 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12754 | We also need NewABI support. */ |
12755 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12756 | { | |
12757 | s_ignore (0); | |
12758 | return; | |
12759 | } | |
12760 | ||
12761 | reg1 = tc_get_register (0); | |
12762 | SKIP_WHITESPACE (); | |
12763 | if (*input_line_pointer != ',') | |
12764 | { | |
12765 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12766 | return; | |
12767 | } | |
12768 | else | |
80245285 | 12769 | ++input_line_pointer; |
6478892d TS |
12770 | SKIP_WHITESPACE (); |
12771 | if (*input_line_pointer == '$') | |
80245285 TS |
12772 | { |
12773 | mips_cpreturn_register = tc_get_register (0); | |
12774 | mips_cpreturn_offset = -1; | |
12775 | } | |
6478892d | 12776 | else |
80245285 TS |
12777 | { |
12778 | mips_cpreturn_offset = get_absolute_expression (); | |
12779 | mips_cpreturn_register = -1; | |
12780 | } | |
6478892d TS |
12781 | SKIP_WHITESPACE (); |
12782 | if (*input_line_pointer != ',') | |
12783 | { | |
12784 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12785 | return; | |
12786 | } | |
12787 | else | |
f9419b05 | 12788 | ++input_line_pointer; |
6478892d | 12789 | SKIP_WHITESPACE (); |
f21f8242 | 12790 | expression (&ex_sym); |
6478892d | 12791 | |
584892a6 | 12792 | macro_start (); |
6478892d TS |
12793 | if (mips_cpreturn_register == -1) |
12794 | { | |
12795 | ex_off.X_op = O_constant; | |
12796 | ex_off.X_add_symbol = NULL; | |
12797 | ex_off.X_op_symbol = NULL; | |
12798 | ex_off.X_add_number = mips_cpreturn_offset; | |
12799 | ||
67c0d1eb | 12800 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12801 | BFD_RELOC_LO16, SP); |
6478892d TS |
12802 | } |
12803 | else | |
67c0d1eb | 12804 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12805 | mips_gp_register, 0); |
6478892d | 12806 | |
aed1a261 | 12807 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12808 | { |
12809 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12810 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12811 | BFD_RELOC_HI16_S); | |
12812 | ||
12813 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12814 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12815 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12816 | ||
12817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12818 | mips_gp_register, reg1); | |
12819 | } | |
12820 | else | |
12821 | { | |
12822 | expressionS ex; | |
12823 | ||
12824 | ex.X_op = O_symbol; | |
4184909a | 12825 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12826 | ex.X_op_symbol = NULL; |
12827 | ex.X_add_number = 0; | |
6e1304d8 | 12828 | |
aa6975fb ILT |
12829 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12830 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12831 | ||
12832 | macro_build_lui (&ex, mips_gp_register); | |
12833 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12834 | mips_gp_register, BFD_RELOC_LO16); | |
12835 | } | |
f21f8242 | 12836 | |
584892a6 | 12837 | macro_end (); |
6478892d TS |
12838 | |
12839 | demand_empty_rest_of_line (); | |
12840 | } | |
12841 | ||
12842 | static void | |
17a2f251 | 12843 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12844 | { |
12845 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 12846 | .cplocal is ignored. */ |
6478892d TS |
12847 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
12848 | { | |
12849 | s_ignore (0); | |
12850 | return; | |
12851 | } | |
12852 | ||
12853 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12854 | demand_empty_rest_of_line (); |
6478892d TS |
12855 | } |
12856 | ||
252b5132 RH |
12857 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12858 | offset from $sp. The offset is remembered, and after making a PIC | |
12859 | call $gp is restored from that location. */ | |
12860 | ||
12861 | static void | |
17a2f251 | 12862 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12863 | { |
12864 | expressionS ex; | |
252b5132 | 12865 | |
6478892d | 12866 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12867 | .cprestore is ignored. */ |
6478892d | 12868 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12869 | { |
12870 | s_ignore (0); | |
12871 | return; | |
12872 | } | |
12873 | ||
12874 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12875 | mips_cprestore_valid = 1; |
252b5132 RH |
12876 | |
12877 | ex.X_op = O_constant; | |
12878 | ex.X_add_symbol = NULL; | |
12879 | ex.X_op_symbol = NULL; | |
12880 | ex.X_add_number = mips_cprestore_offset; | |
12881 | ||
584892a6 | 12882 | macro_start (); |
67c0d1eb RS |
12883 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12884 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12885 | macro_end (); |
252b5132 RH |
12886 | |
12887 | demand_empty_rest_of_line (); | |
12888 | } | |
12889 | ||
6478892d | 12890 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12891 | was given in the preceding .cpsetup, it results in: |
6478892d | 12892 | ld $gp, offset($sp) |
76b3015f | 12893 | |
6478892d | 12894 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
12895 | daddu $gp, $reg2, $0 */ |
12896 | ||
6478892d | 12897 | static void |
17a2f251 | 12898 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12899 | { |
12900 | expressionS ex; | |
6478892d TS |
12901 | |
12902 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12903 | We also need NewABI support. */ | |
12904 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12905 | { | |
12906 | s_ignore (0); | |
12907 | return; | |
12908 | } | |
12909 | ||
584892a6 | 12910 | macro_start (); |
6478892d TS |
12911 | if (mips_cpreturn_register == -1) |
12912 | { | |
12913 | ex.X_op = O_constant; | |
12914 | ex.X_add_symbol = NULL; | |
12915 | ex.X_op_symbol = NULL; | |
12916 | ex.X_add_number = mips_cpreturn_offset; | |
12917 | ||
67c0d1eb | 12918 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12919 | } |
12920 | else | |
67c0d1eb | 12921 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12922 | mips_cpreturn_register, 0); |
584892a6 | 12923 | macro_end (); |
6478892d TS |
12924 | |
12925 | demand_empty_rest_of_line (); | |
12926 | } | |
12927 | ||
741d6ea8 JM |
12928 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
12929 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
12930 | use in DWARF debug information. */ | |
12931 | ||
12932 | static void | |
12933 | s_dtprel_internal (size_t bytes) | |
12934 | { | |
12935 | expressionS ex; | |
12936 | char *p; | |
12937 | ||
12938 | expression (&ex); | |
12939 | ||
12940 | if (ex.X_op != O_symbol) | |
12941 | { | |
12942 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
12943 | ? ".dtpreldword" | |
12944 | : ".dtprelword")); | |
12945 | ignore_rest_of_line (); | |
12946 | } | |
12947 | ||
12948 | p = frag_more (bytes); | |
12949 | md_number_to_chars (p, 0, bytes); | |
12950 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
12951 | (bytes == 8 | |
12952 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
12953 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
12954 | ||
12955 | demand_empty_rest_of_line (); | |
12956 | } | |
12957 | ||
12958 | /* Handle .dtprelword. */ | |
12959 | ||
12960 | static void | |
12961 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
12962 | { | |
12963 | s_dtprel_internal (4); | |
12964 | } | |
12965 | ||
12966 | /* Handle .dtpreldword. */ | |
12967 | ||
12968 | static void | |
12969 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
12970 | { | |
12971 | s_dtprel_internal (8); | |
12972 | } | |
12973 | ||
6478892d TS |
12974 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
12975 | code. It sets the offset to use in gp_rel relocations. */ | |
12976 | ||
12977 | static void | |
17a2f251 | 12978 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12979 | { |
12980 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12981 | We also need NewABI support. */ | |
12982 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12983 | { | |
12984 | s_ignore (0); | |
12985 | return; | |
12986 | } | |
12987 | ||
def2e0dd | 12988 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12989 | |
12990 | demand_empty_rest_of_line (); | |
12991 | } | |
12992 | ||
252b5132 RH |
12993 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12994 | code. It generates a 32 bit GP relative reloc. */ | |
12995 | ||
12996 | static void | |
17a2f251 | 12997 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12998 | { |
a8dbcb85 TS |
12999 | segment_info_type *si; |
13000 | struct insn_label_list *l; | |
252b5132 RH |
13001 | symbolS *label; |
13002 | expressionS ex; | |
13003 | char *p; | |
13004 | ||
13005 | /* When not generating PIC code, this is treated as .word. */ | |
13006 | if (mips_pic != SVR4_PIC) | |
13007 | { | |
13008 | s_cons (2); | |
13009 | return; | |
13010 | } | |
13011 | ||
a8dbcb85 TS |
13012 | si = seg_info (now_seg); |
13013 | l = si->label_list; | |
13014 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13015 | mips_emit_delays (); |
252b5132 RH |
13016 | if (auto_align) |
13017 | mips_align (2, 0, label); | |
13018 | mips_clear_insn_labels (); | |
13019 | ||
13020 | expression (&ex); | |
13021 | ||
13022 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13023 | { | |
13024 | as_bad (_("Unsupported use of .gpword")); | |
13025 | ignore_rest_of_line (); | |
13026 | } | |
13027 | ||
13028 | p = frag_more (4); | |
17a2f251 | 13029 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13030 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13031 | BFD_RELOC_GPREL32); |
252b5132 RH |
13032 | |
13033 | demand_empty_rest_of_line (); | |
13034 | } | |
13035 | ||
10181a0d | 13036 | static void |
17a2f251 | 13037 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13038 | { |
a8dbcb85 TS |
13039 | segment_info_type *si; |
13040 | struct insn_label_list *l; | |
10181a0d AO |
13041 | symbolS *label; |
13042 | expressionS ex; | |
13043 | char *p; | |
13044 | ||
13045 | /* When not generating PIC code, this is treated as .dword. */ | |
13046 | if (mips_pic != SVR4_PIC) | |
13047 | { | |
13048 | s_cons (3); | |
13049 | return; | |
13050 | } | |
13051 | ||
a8dbcb85 TS |
13052 | si = seg_info (now_seg); |
13053 | l = si->label_list; | |
13054 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13055 | mips_emit_delays (); |
10181a0d AO |
13056 | if (auto_align) |
13057 | mips_align (3, 0, label); | |
13058 | mips_clear_insn_labels (); | |
13059 | ||
13060 | expression (&ex); | |
13061 | ||
13062 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13063 | { | |
13064 | as_bad (_("Unsupported use of .gpdword")); | |
13065 | ignore_rest_of_line (); | |
13066 | } | |
13067 | ||
13068 | p = frag_more (8); | |
17a2f251 | 13069 | md_number_to_chars (p, 0, 8); |
a105a300 | 13070 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13071 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13072 | |
13073 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13074 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13075 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13076 | |
13077 | demand_empty_rest_of_line (); | |
13078 | } | |
13079 | ||
252b5132 RH |
13080 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13081 | tables in SVR4 PIC code. */ | |
13082 | ||
13083 | static void | |
17a2f251 | 13084 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13085 | { |
252b5132 RH |
13086 | int reg; |
13087 | ||
10181a0d AO |
13088 | /* This is ignored when not generating SVR4 PIC code. */ |
13089 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13090 | { |
13091 | s_ignore (0); | |
13092 | return; | |
13093 | } | |
13094 | ||
13095 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13096 | macro_start (); |
252b5132 | 13097 | reg = tc_get_register (0); |
67c0d1eb | 13098 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13099 | macro_end (); |
252b5132 | 13100 | |
bdaaa2e1 | 13101 | demand_empty_rest_of_line (); |
252b5132 RH |
13102 | } |
13103 | ||
13104 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13105 | mips16 mode. This permits the linker to handle them specially, | |
13106 | such as generating jalx instructions when needed. We also make | |
13107 | them odd for the duration of the assembly, in order to generate the | |
13108 | right sort of code. We will make them even in the adjust_symtab | |
13109 | routine, while leaving them marked. This is convenient for the | |
13110 | debugger and the disassembler. The linker knows to make them odd | |
13111 | again. */ | |
13112 | ||
13113 | static void | |
17a2f251 | 13114 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13115 | { |
f9419b05 | 13116 | mips16_mark_labels (); |
252b5132 RH |
13117 | |
13118 | demand_empty_rest_of_line (); | |
13119 | } | |
13120 | ||
13121 | /* Handle a .stabn directive. We need these in order to mark a label | |
13122 | as being a mips16 text label correctly. Sometimes the compiler | |
13123 | will emit a label, followed by a .stabn, and then switch sections. | |
13124 | If the label and .stabn are in mips16 mode, then the label is | |
13125 | really a mips16 text label. */ | |
13126 | ||
13127 | static void | |
17a2f251 | 13128 | s_mips_stab (int type) |
252b5132 | 13129 | { |
f9419b05 | 13130 | if (type == 'n') |
252b5132 RH |
13131 | mips16_mark_labels (); |
13132 | ||
13133 | s_stab (type); | |
13134 | } | |
13135 | ||
54f4ddb3 | 13136 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13137 | |
13138 | static void | |
17a2f251 | 13139 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13140 | { |
13141 | char *name; | |
13142 | int c; | |
13143 | symbolS *symbolP; | |
13144 | expressionS exp; | |
13145 | ||
13146 | name = input_line_pointer; | |
13147 | c = get_symbol_end (); | |
13148 | symbolP = symbol_find_or_make (name); | |
13149 | S_SET_WEAK (symbolP); | |
13150 | *input_line_pointer = c; | |
13151 | ||
13152 | SKIP_WHITESPACE (); | |
13153 | ||
13154 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13155 | { | |
13156 | if (S_IS_DEFINED (symbolP)) | |
13157 | { | |
956cd1d6 | 13158 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
13159 | S_GET_NAME (symbolP)); |
13160 | ignore_rest_of_line (); | |
13161 | return; | |
13162 | } | |
bdaaa2e1 | 13163 | |
252b5132 RH |
13164 | if (*input_line_pointer == ',') |
13165 | { | |
13166 | ++input_line_pointer; | |
13167 | SKIP_WHITESPACE (); | |
13168 | } | |
bdaaa2e1 | 13169 | |
252b5132 RH |
13170 | expression (&exp); |
13171 | if (exp.X_op != O_symbol) | |
13172 | { | |
13173 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13174 | ignore_rest_of_line (); |
252b5132 RH |
13175 | return; |
13176 | } | |
49309057 | 13177 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13178 | } |
13179 | ||
13180 | demand_empty_rest_of_line (); | |
13181 | } | |
13182 | ||
13183 | /* Parse a register string into a number. Called from the ECOFF code | |
13184 | to parse .frame. The argument is non-zero if this is the frame | |
13185 | register, so that we can record it in mips_frame_reg. */ | |
13186 | ||
13187 | int | |
17a2f251 | 13188 | tc_get_register (int frame) |
252b5132 | 13189 | { |
707bfff6 | 13190 | unsigned int reg; |
252b5132 RH |
13191 | |
13192 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13193 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13194 | reg = 0; | |
252b5132 | 13195 | if (frame) |
7a621144 DJ |
13196 | { |
13197 | mips_frame_reg = reg != 0 ? reg : SP; | |
13198 | mips_frame_reg_valid = 1; | |
13199 | mips_cprestore_valid = 0; | |
13200 | } | |
252b5132 RH |
13201 | return reg; |
13202 | } | |
13203 | ||
13204 | valueT | |
17a2f251 | 13205 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13206 | { |
13207 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13208 | ||
b4c71f56 TS |
13209 | if (IS_ELF) |
13210 | { | |
13211 | /* We don't need to align ELF sections to the full alignment. | |
13212 | However, Irix 5 may prefer that we align them at least to a 16 | |
13213 | byte boundary. We don't bother to align the sections if we | |
13214 | are targeted for an embedded system. */ | |
13215 | if (strcmp (TARGET_OS, "elf") == 0) | |
13216 | return addr; | |
13217 | if (align > 4) | |
13218 | align = 4; | |
13219 | } | |
252b5132 RH |
13220 | |
13221 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13222 | } | |
13223 | ||
13224 | /* Utility routine, called from above as well. If called while the | |
13225 | input file is still being read, it's only an approximation. (For | |
13226 | example, a symbol may later become defined which appeared to be | |
13227 | undefined earlier.) */ | |
13228 | ||
13229 | static int | |
17a2f251 | 13230 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13231 | { |
13232 | if (sym == 0) | |
13233 | return 0; | |
13234 | ||
4d0d148d | 13235 | if (g_switch_value > 0) |
252b5132 RH |
13236 | { |
13237 | const char *symname; | |
13238 | int change; | |
13239 | ||
c9914766 | 13240 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13241 | register. It can be if it is smaller than the -G size or if |
13242 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13243 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13244 | they can. */ |
13245 | symname = S_GET_NAME (sym); | |
13246 | if (symname != (const char *) NULL | |
13247 | && (strcmp (symname, "eprol") == 0 | |
13248 | || strcmp (symname, "etext") == 0 | |
13249 | || strcmp (symname, "_gp") == 0 | |
13250 | || strcmp (symname, "edata") == 0 | |
13251 | || strcmp (symname, "_fbss") == 0 | |
13252 | || strcmp (symname, "_fdata") == 0 | |
13253 | || strcmp (symname, "_ftext") == 0 | |
13254 | || strcmp (symname, "end") == 0 | |
13255 | || strcmp (symname, "_gp_disp") == 0)) | |
13256 | change = 1; | |
13257 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13258 | && (0 | |
13259 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13260 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13261 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13262 | <= g_switch_value)) | |
252b5132 RH |
13263 | #endif |
13264 | /* We must defer this decision until after the whole | |
13265 | file has been read, since there might be a .extern | |
13266 | after the first use of this symbol. */ | |
13267 | || (before_relaxing | |
13268 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13269 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13270 | #endif |
13271 | && S_GET_VALUE (sym) == 0) | |
13272 | || (S_GET_VALUE (sym) != 0 | |
13273 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13274 | change = 0; | |
13275 | else | |
13276 | { | |
13277 | const char *segname; | |
13278 | ||
13279 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13280 | assert (strcmp (segname, ".lit8") != 0 | |
13281 | && strcmp (segname, ".lit4") != 0); | |
13282 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13283 | && strcmp (segname, ".sbss") != 0 |
13284 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13285 | && strncmp (segname, ".sbss.", 6) != 0 |
13286 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13287 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13288 | } |
13289 | return change; | |
13290 | } | |
13291 | else | |
c9914766 | 13292 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13293 | return 1; |
13294 | } | |
13295 | ||
5919d012 RS |
13296 | |
13297 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13298 | ||
13299 | static bfd_boolean | |
17a2f251 | 13300 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13301 | { |
13302 | asection *symsec; | |
5919d012 RS |
13303 | |
13304 | /* Handle the case of a symbol equated to another symbol. */ | |
13305 | while (symbol_equated_reloc_p (sym)) | |
13306 | { | |
13307 | symbolS *n; | |
13308 | ||
5f0fe04b | 13309 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13310 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13311 | if (n == sym) | |
13312 | break; | |
13313 | sym = n; | |
13314 | } | |
13315 | ||
df1f3cda DD |
13316 | if (symbol_section_p (sym)) |
13317 | return TRUE; | |
13318 | ||
5919d012 RS |
13319 | symsec = S_GET_SEGMENT (sym); |
13320 | ||
5919d012 RS |
13321 | /* This must duplicate the test in adjust_reloc_syms. */ |
13322 | return (symsec != &bfd_und_section | |
13323 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13324 | && !bfd_is_com_section (symsec) |
13325 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13326 | #ifdef OBJ_ELF |
13327 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13328 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13329 | #endif |
13330 | ); | |
13331 | } | |
13332 | ||
13333 | ||
252b5132 RH |
13334 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13335 | extended opcode. SEC is the section the frag is in. */ | |
13336 | ||
13337 | static int | |
17a2f251 | 13338 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13339 | { |
13340 | int type; | |
3994f87e | 13341 | const struct mips16_immed_operand *op; |
252b5132 RH |
13342 | offsetT val; |
13343 | int mintiny, maxtiny; | |
13344 | segT symsec; | |
98aa84af | 13345 | fragS *sym_frag; |
252b5132 RH |
13346 | |
13347 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13348 | return 0; | |
13349 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13350 | return 1; | |
13351 | ||
13352 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13353 | op = mips16_immed_operands; | |
13354 | while (op->type != type) | |
13355 | { | |
13356 | ++op; | |
13357 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13358 | } | |
13359 | ||
13360 | if (op->unsp) | |
13361 | { | |
13362 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13363 | { | |
13364 | mintiny = 1; | |
13365 | maxtiny = 1 << op->nbits; | |
13366 | } | |
13367 | else | |
13368 | { | |
13369 | mintiny = 0; | |
13370 | maxtiny = (1 << op->nbits) - 1; | |
13371 | } | |
13372 | } | |
13373 | else | |
13374 | { | |
13375 | mintiny = - (1 << (op->nbits - 1)); | |
13376 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13377 | } | |
13378 | ||
98aa84af | 13379 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13380 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13381 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13382 | |
13383 | if (op->pcrel) | |
13384 | { | |
13385 | addressT addr; | |
13386 | ||
13387 | /* We won't have the section when we are called from | |
13388 | mips_relax_frag. However, we will always have been called | |
13389 | from md_estimate_size_before_relax first. If this is a | |
13390 | branch to a different section, we mark it as such. If SEC is | |
13391 | NULL, and the frag is not marked, then it must be a branch to | |
13392 | the same section. */ | |
13393 | if (sec == NULL) | |
13394 | { | |
13395 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13396 | return 1; | |
13397 | } | |
13398 | else | |
13399 | { | |
98aa84af | 13400 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13401 | if (symsec != sec) |
13402 | { | |
13403 | fragp->fr_subtype = | |
13404 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13405 | ||
13406 | /* FIXME: We should support this, and let the linker | |
13407 | catch branches and loads that are out of range. */ | |
13408 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13409 | _("unsupported PC relative reference to different section")); | |
13410 | ||
13411 | return 1; | |
13412 | } | |
98aa84af AM |
13413 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13414 | /* Assume non-extended on the first relaxation pass. | |
13415 | The address we have calculated will be bogus if this is | |
13416 | a forward branch to another frag, as the forward frag | |
13417 | will have fr_address == 0. */ | |
13418 | return 0; | |
252b5132 RH |
13419 | } |
13420 | ||
13421 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13422 | the same section. If the relax_marker of the symbol fragment |
13423 | differs from the relax_marker of this fragment, we have not | |
13424 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13425 | in STRETCH in order to get a better estimate of the address. |
13426 | This particularly matters because of the shift bits. */ | |
13427 | if (stretch != 0 | |
98aa84af | 13428 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13429 | { |
13430 | fragS *f; | |
13431 | ||
13432 | /* Adjust stretch for any alignment frag. Note that if have | |
13433 | been expanding the earlier code, the symbol may be | |
13434 | defined in what appears to be an earlier frag. FIXME: | |
13435 | This doesn't handle the fr_subtype field, which specifies | |
13436 | a maximum number of bytes to skip when doing an | |
13437 | alignment. */ | |
98aa84af | 13438 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13439 | { |
13440 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13441 | { | |
13442 | if (stretch < 0) | |
13443 | stretch = - ((- stretch) | |
13444 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13445 | else | |
13446 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13447 | if (stretch == 0) | |
13448 | break; | |
13449 | } | |
13450 | } | |
13451 | if (f != NULL) | |
13452 | val += stretch; | |
13453 | } | |
13454 | ||
13455 | addr = fragp->fr_address + fragp->fr_fix; | |
13456 | ||
13457 | /* The base address rules are complicated. The base address of | |
13458 | a branch is the following instruction. The base address of a | |
13459 | PC relative load or add is the instruction itself, but if it | |
13460 | is in a delay slot (in which case it can not be extended) use | |
13461 | the address of the instruction whose delay slot it is in. */ | |
13462 | if (type == 'p' || type == 'q') | |
13463 | { | |
13464 | addr += 2; | |
13465 | ||
13466 | /* If we are currently assuming that this frag should be | |
13467 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13468 | higher. */ |
252b5132 RH |
13469 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13470 | addr += 2; | |
13471 | ||
13472 | /* Ignore the low bit in the target, since it will be set | |
13473 | for a text label. */ | |
13474 | if ((val & 1) != 0) | |
13475 | --val; | |
13476 | } | |
13477 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13478 | addr -= 4; | |
13479 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13480 | addr -= 2; | |
13481 | ||
13482 | val -= addr & ~ ((1 << op->shift) - 1); | |
13483 | ||
13484 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13485 | if (type == 'p' || type == 'q') | |
13486 | val /= 2; | |
13487 | ||
13488 | /* If any of the shifted bits are set, we must use an extended | |
13489 | opcode. If the address depends on the size of this | |
13490 | instruction, this can lead to a loop, so we arrange to always | |
13491 | use an extended opcode. We only check this when we are in | |
13492 | the main relaxation loop, when SEC is NULL. */ | |
13493 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13494 | { | |
13495 | fragp->fr_subtype = | |
13496 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13497 | return 1; | |
13498 | } | |
13499 | ||
13500 | /* If we are about to mark a frag as extended because the value | |
13501 | is precisely maxtiny + 1, then there is a chance of an | |
13502 | infinite loop as in the following code: | |
13503 | la $4,foo | |
13504 | .skip 1020 | |
13505 | .align 2 | |
13506 | foo: | |
13507 | In this case when the la is extended, foo is 0x3fc bytes | |
13508 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13509 | the la must be extended. To avoid this loop, we mark the | |
13510 | frag as extended if it was small, and is about to become | |
13511 | extended with a value of maxtiny + 1. */ | |
13512 | if (val == ((maxtiny + 1) << op->shift) | |
13513 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13514 | && sec == NULL) | |
13515 | { | |
13516 | fragp->fr_subtype = | |
13517 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13518 | return 1; | |
13519 | } | |
13520 | } | |
13521 | else if (symsec != absolute_section && sec != NULL) | |
13522 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13523 | ||
13524 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13525 | || val < (mintiny << op->shift) | |
13526 | || val > (maxtiny << op->shift)) | |
13527 | return 1; | |
13528 | else | |
13529 | return 0; | |
13530 | } | |
13531 | ||
4a6a3df4 AO |
13532 | /* Compute the length of a branch sequence, and adjust the |
13533 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13534 | worst-case length is computed, with UPDATE being used to indicate | |
13535 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13536 | branch is to be computed. */ | |
13537 | static int | |
17a2f251 | 13538 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13539 | { |
b34976b6 | 13540 | bfd_boolean toofar; |
4a6a3df4 AO |
13541 | int length; |
13542 | ||
13543 | if (fragp | |
13544 | && S_IS_DEFINED (fragp->fr_symbol) | |
13545 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13546 | { | |
13547 | addressT addr; | |
13548 | offsetT val; | |
13549 | ||
13550 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13551 | ||
13552 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13553 | ||
13554 | val -= addr; | |
13555 | ||
13556 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13557 | } | |
13558 | else if (fragp) | |
13559 | /* If the symbol is not defined or it's in a different segment, | |
13560 | assume the user knows what's going on and emit a short | |
13561 | branch. */ | |
b34976b6 | 13562 | toofar = FALSE; |
4a6a3df4 | 13563 | else |
b34976b6 | 13564 | toofar = TRUE; |
4a6a3df4 AO |
13565 | |
13566 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13567 | fragp->fr_subtype | |
af6ae2ad | 13568 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13569 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13570 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13571 | toofar); | |
13572 | ||
13573 | length = 4; | |
13574 | if (toofar) | |
13575 | { | |
13576 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13577 | length += 8; | |
13578 | ||
13579 | if (mips_pic != NO_PIC) | |
13580 | { | |
13581 | /* Additional space for PIC loading of target address. */ | |
13582 | length += 8; | |
13583 | if (mips_opts.isa == ISA_MIPS1) | |
13584 | /* Additional space for $at-stabilizing nop. */ | |
13585 | length += 4; | |
13586 | } | |
13587 | ||
13588 | /* If branch is conditional. */ | |
13589 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13590 | length += 8; | |
13591 | } | |
b34976b6 | 13592 | |
4a6a3df4 AO |
13593 | return length; |
13594 | } | |
13595 | ||
252b5132 RH |
13596 | /* Estimate the size of a frag before relaxing. Unless this is the |
13597 | mips16, we are not really relaxing here, and the final size is | |
13598 | encoded in the subtype information. For the mips16, we have to | |
13599 | decide whether we are using an extended opcode or not. */ | |
13600 | ||
252b5132 | 13601 | int |
17a2f251 | 13602 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13603 | { |
5919d012 | 13604 | int change; |
252b5132 | 13605 | |
4a6a3df4 AO |
13606 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13607 | { | |
13608 | ||
b34976b6 AM |
13609 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13610 | ||
4a6a3df4 AO |
13611 | return fragp->fr_var; |
13612 | } | |
13613 | ||
252b5132 | 13614 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13615 | /* We don't want to modify the EXTENDED bit here; it might get us |
13616 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13617 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13618 | |
13619 | if (mips_pic == NO_PIC) | |
5919d012 | 13620 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13621 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13622 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13623 | else if (mips_pic == VXWORKS_PIC) |
13624 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13625 | change = 0; | |
252b5132 RH |
13626 | else |
13627 | abort (); | |
13628 | ||
13629 | if (change) | |
13630 | { | |
4d7206a2 | 13631 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13632 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13633 | } |
4d7206a2 RS |
13634 | else |
13635 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13636 | } |
13637 | ||
13638 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13639 | should be converted into a reloc against a section. */ |
252b5132 RH |
13640 | |
13641 | int | |
17a2f251 | 13642 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13643 | { |
252b5132 RH |
13644 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13645 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13646 | return 0; | |
a161fe53 | 13647 | |
252b5132 RH |
13648 | if (fixp->fx_addsy == NULL) |
13649 | return 1; | |
a161fe53 | 13650 | |
de7e6852 RS |
13651 | /* If symbol SYM is in a mergeable section, relocations of the form |
13652 | SYM + 0 can usually be made section-relative. The mergeable data | |
13653 | is then identified by the section offset rather than by the symbol. | |
13654 | ||
13655 | However, if we're generating REL LO16 relocations, the offset is split | |
13656 | between the LO16 and parterning high part relocation. The linker will | |
13657 | need to recalculate the complete offset in order to correctly identify | |
13658 | the merge data. | |
13659 | ||
13660 | The linker has traditionally not looked for the parterning high part | |
13661 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13662 | placed anywhere. Rather than break backwards compatibility by changing | |
13663 | this, it seems better not to force the issue, and instead keep the | |
13664 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13665 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13666 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13667 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13668 | && HAVE_IN_PLACE_ADDENDS |
13669 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13670 | return 0; | |
13671 | ||
252b5132 | 13672 | #ifdef OBJ_ELF |
b314ec0e RS |
13673 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
13674 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
13675 | relocations against MIPS16 functions; in this case, the stub becomes | |
13676 | the function's canonical address. | |
13677 | ||
13678 | Floating-point stubs are stored in unique .mips16.call.* or | |
13679 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
13680 | the first relocation in section S must be against F; this is how the | |
13681 | linker determines the target function. All relocations that might | |
13682 | resolve to T must also be against F. We therefore have the following | |
13683 | restrictions, which are given in an intentionally-redundant way: | |
13684 | ||
13685 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
13686 | symbols. | |
13687 | ||
13688 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
13689 | if that stub might be used. | |
13690 | ||
13691 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
13692 | symbols. | |
13693 | ||
13694 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
13695 | that stub might be used. | |
13696 | ||
13697 | There is a further restriction: | |
13698 | ||
13699 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
13700 | on targets with in-place addends; the relocation field cannot | |
13701 | encode the low bit. | |
13702 | ||
13703 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
13704 | against a MIPS16 symbol. | |
13705 | ||
13706 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
13707 | relocation against some symbol R, no relocation against R may be | |
13708 | reduced. (Note that this deals with (2) as well as (1) because | |
13709 | relocations against global symbols will never be reduced on ELF | |
13710 | targets.) This approach is a little simpler than trying to detect | |
13711 | stub sections, and gives the "all or nothing" per-symbol consistency | |
13712 | that we have for MIPS16 symbols. */ | |
f43abd2b | 13713 | if (IS_ELF |
b314ec0e RS |
13714 | && fixp->fx_subsy == NULL |
13715 | && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13716 | || *symbol_get_tc (fixp->fx_addsy))) | |
252b5132 RH |
13717 | return 0; |
13718 | #endif | |
a161fe53 | 13719 | |
252b5132 RH |
13720 | return 1; |
13721 | } | |
13722 | ||
13723 | /* Translate internal representation of relocation info to BFD target | |
13724 | format. */ | |
13725 | ||
13726 | arelent ** | |
17a2f251 | 13727 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13728 | { |
13729 | static arelent *retval[4]; | |
13730 | arelent *reloc; | |
13731 | bfd_reloc_code_real_type code; | |
13732 | ||
4b0cff4e TS |
13733 | memset (retval, 0, sizeof(retval)); |
13734 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13735 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13736 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13737 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13738 | ||
bad36eac DJ |
13739 | if (fixp->fx_pcrel) |
13740 | { | |
13741 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13742 | ||
13743 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13744 | Relocations want only the symbol offset. */ | |
13745 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13746 | if (!IS_ELF) |
bad36eac DJ |
13747 | { |
13748 | /* A gruesome hack which is a result of the gruesome gas | |
13749 | reloc handling. What's worse, for COFF (as opposed to | |
13750 | ECOFF), we might need yet another copy of reloc->address. | |
13751 | See bfd_install_relocation. */ | |
13752 | reloc->addend += reloc->address; | |
13753 | } | |
13754 | } | |
13755 | else | |
13756 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13757 | |
438c16b8 TS |
13758 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13759 | entry to be used in the relocation's section offset. */ | |
13760 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13761 | { |
13762 | reloc->address = reloc->addend; | |
13763 | reloc->addend = 0; | |
13764 | } | |
13765 | ||
252b5132 | 13766 | code = fixp->fx_r_type; |
252b5132 | 13767 | |
bad36eac | 13768 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13769 | if (reloc->howto == NULL) |
13770 | { | |
13771 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13772 | _("Can not represent %s relocation in this object file format"), | |
13773 | bfd_get_reloc_code_name (code)); | |
13774 | retval[0] = NULL; | |
13775 | } | |
13776 | ||
13777 | return retval; | |
13778 | } | |
13779 | ||
13780 | /* Relax a machine dependent frag. This returns the amount by which | |
13781 | the current size of the frag should change. */ | |
13782 | ||
13783 | int | |
17a2f251 | 13784 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13785 | { |
4a6a3df4 AO |
13786 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13787 | { | |
13788 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13789 | |
13790 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13791 | |
13792 | return fragp->fr_var - old_var; | |
13793 | } | |
13794 | ||
252b5132 RH |
13795 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13796 | return 0; | |
13797 | ||
c4e7957c | 13798 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13799 | { |
13800 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13801 | return 0; | |
13802 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13803 | return 2; | |
13804 | } | |
13805 | else | |
13806 | { | |
13807 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13808 | return 0; | |
13809 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13810 | return -2; | |
13811 | } | |
13812 | ||
13813 | return 0; | |
13814 | } | |
13815 | ||
13816 | /* Convert a machine dependent frag. */ | |
13817 | ||
13818 | void | |
17a2f251 | 13819 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13820 | { |
4a6a3df4 AO |
13821 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13822 | { | |
13823 | bfd_byte *buf; | |
13824 | unsigned long insn; | |
13825 | expressionS exp; | |
13826 | fixS *fixp; | |
b34976b6 | 13827 | |
4a6a3df4 AO |
13828 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13829 | ||
13830 | if (target_big_endian) | |
13831 | insn = bfd_getb32 (buf); | |
13832 | else | |
13833 | insn = bfd_getl32 (buf); | |
b34976b6 | 13834 | |
4a6a3df4 AO |
13835 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13836 | { | |
13837 | /* We generate a fixup instead of applying it right now | |
13838 | because, if there are linker relaxations, we're going to | |
13839 | need the relocations. */ | |
13840 | exp.X_op = O_symbol; | |
13841 | exp.X_add_symbol = fragp->fr_symbol; | |
13842 | exp.X_add_number = fragp->fr_offset; | |
13843 | ||
13844 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13845 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13846 | fixp->fx_file = fragp->fr_file; |
13847 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13848 | |
2132e3a3 | 13849 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13850 | buf += 4; |
13851 | } | |
13852 | else | |
13853 | { | |
13854 | int i; | |
13855 | ||
13856 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13857 | _("relaxed out-of-range branch into a jump")); | |
13858 | ||
13859 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13860 | goto uncond; | |
13861 | ||
13862 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13863 | { | |
13864 | /* Reverse the branch. */ | |
13865 | switch ((insn >> 28) & 0xf) | |
13866 | { | |
13867 | case 4: | |
13868 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13869 | have the condition reversed by tweaking a single | |
13870 | bit, and their opcodes all have 0x4???????. */ | |
13871 | assert ((insn & 0xf1000000) == 0x41000000); | |
13872 | insn ^= 0x00010000; | |
13873 | break; | |
13874 | ||
13875 | case 0: | |
13876 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 13877 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
13878 | assert ((insn & 0xfc0e0000) == 0x04000000); |
13879 | insn ^= 0x00010000; | |
13880 | break; | |
b34976b6 | 13881 | |
4a6a3df4 AO |
13882 | case 1: |
13883 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 13884 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
13885 | insn ^= 0x04000000; |
13886 | break; | |
13887 | ||
13888 | default: | |
13889 | abort (); | |
13890 | } | |
13891 | } | |
13892 | ||
13893 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13894 | { | |
13895 | /* Clear the and-link bit. */ | |
13896 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13897 | ||
54f4ddb3 TS |
13898 | /* bltzal 0x04100000 bgezal 0x04110000 |
13899 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
13900 | insn &= ~0x00100000; |
13901 | } | |
13902 | ||
13903 | /* Branch over the branch (if the branch was likely) or the | |
13904 | full jump (not likely case). Compute the offset from the | |
13905 | current instruction to branch to. */ | |
13906 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13907 | i = 16; | |
13908 | else | |
13909 | { | |
13910 | /* How many bytes in instructions we've already emitted? */ | |
13911 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13912 | /* How many bytes in instructions from here to the end? */ | |
13913 | i = fragp->fr_var - i; | |
13914 | } | |
13915 | /* Convert to instruction count. */ | |
13916 | i >>= 2; | |
13917 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13918 | i--; |
4a6a3df4 AO |
13919 | insn |= i; |
13920 | /* Branch over the jump. */ | |
2132e3a3 | 13921 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13922 | buf += 4; |
13923 | ||
54f4ddb3 | 13924 | /* nop */ |
2132e3a3 | 13925 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13926 | buf += 4; |
13927 | ||
13928 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13929 | { | |
13930 | /* beql $0, $0, 2f */ | |
13931 | insn = 0x50000000; | |
13932 | /* Compute the PC offset from the current instruction to | |
13933 | the end of the variable frag. */ | |
13934 | /* How many bytes in instructions we've already emitted? */ | |
13935 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13936 | /* How many bytes in instructions from here to the end? */ | |
13937 | i = fragp->fr_var - i; | |
13938 | /* Convert to instruction count. */ | |
13939 | i >>= 2; | |
13940 | /* Don't decrement i, because we want to branch over the | |
13941 | delay slot. */ | |
13942 | ||
13943 | insn |= i; | |
2132e3a3 | 13944 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13945 | buf += 4; |
13946 | ||
2132e3a3 | 13947 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13948 | buf += 4; |
13949 | } | |
13950 | ||
13951 | uncond: | |
13952 | if (mips_pic == NO_PIC) | |
13953 | { | |
13954 | /* j or jal. */ | |
13955 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13956 | ? 0x0c000000 : 0x08000000); | |
13957 | exp.X_op = O_symbol; | |
13958 | exp.X_add_symbol = fragp->fr_symbol; | |
13959 | exp.X_add_number = fragp->fr_offset; | |
13960 | ||
13961 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13962 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
13963 | fixp->fx_file = fragp->fr_file; |
13964 | fixp->fx_line = fragp->fr_line; | |
13965 | ||
2132e3a3 | 13966 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13967 | buf += 4; |
13968 | } | |
13969 | else | |
13970 | { | |
13971 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13972 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13973 | exp.X_op = O_symbol; | |
13974 | exp.X_add_symbol = fragp->fr_symbol; | |
13975 | exp.X_add_number = fragp->fr_offset; | |
13976 | ||
13977 | if (fragp->fr_offset) | |
13978 | { | |
13979 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13980 | exp.X_add_number = 0; | |
13981 | } | |
13982 | ||
13983 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13984 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
13985 | fixp->fx_file = fragp->fr_file; |
13986 | fixp->fx_line = fragp->fr_line; | |
13987 | ||
2132e3a3 | 13988 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13989 | buf += 4; |
b34976b6 | 13990 | |
4a6a3df4 AO |
13991 | if (mips_opts.isa == ISA_MIPS1) |
13992 | { | |
13993 | /* nop */ | |
2132e3a3 | 13994 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13995 | buf += 4; |
13996 | } | |
13997 | ||
13998 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13999 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14000 | ||
14001 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14002 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14003 | fixp->fx_file = fragp->fr_file; |
14004 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14005 | |
2132e3a3 | 14006 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14007 | buf += 4; |
14008 | ||
14009 | /* j(al)r $at. */ | |
14010 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14011 | insn = 0x0020f809; | |
14012 | else | |
14013 | insn = 0x00200008; | |
14014 | ||
2132e3a3 | 14015 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14016 | buf += 4; |
14017 | } | |
14018 | } | |
14019 | ||
14020 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14021 | + fragp->fr_fix + fragp->fr_var); | |
14022 | ||
14023 | fragp->fr_fix += fragp->fr_var; | |
14024 | ||
14025 | return; | |
14026 | } | |
14027 | ||
252b5132 RH |
14028 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14029 | { | |
14030 | int type; | |
3994f87e | 14031 | const struct mips16_immed_operand *op; |
b34976b6 | 14032 | bfd_boolean small, ext; |
252b5132 RH |
14033 | offsetT val; |
14034 | bfd_byte *buf; | |
14035 | unsigned long insn; | |
b34976b6 | 14036 | bfd_boolean use_extend; |
252b5132 RH |
14037 | unsigned short extend; |
14038 | ||
14039 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14040 | op = mips16_immed_operands; | |
14041 | while (op->type != type) | |
14042 | ++op; | |
14043 | ||
14044 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14045 | { | |
b34976b6 AM |
14046 | small = FALSE; |
14047 | ext = TRUE; | |
252b5132 RH |
14048 | } |
14049 | else | |
14050 | { | |
b34976b6 AM |
14051 | small = TRUE; |
14052 | ext = FALSE; | |
252b5132 RH |
14053 | } |
14054 | ||
6386f3a7 | 14055 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14056 | val = S_GET_VALUE (fragp->fr_symbol); |
14057 | if (op->pcrel) | |
14058 | { | |
14059 | addressT addr; | |
14060 | ||
14061 | addr = fragp->fr_address + fragp->fr_fix; | |
14062 | ||
14063 | /* The rules for the base address of a PC relative reloc are | |
14064 | complicated; see mips16_extended_frag. */ | |
14065 | if (type == 'p' || type == 'q') | |
14066 | { | |
14067 | addr += 2; | |
14068 | if (ext) | |
14069 | addr += 2; | |
14070 | /* Ignore the low bit in the target, since it will be | |
14071 | set for a text label. */ | |
14072 | if ((val & 1) != 0) | |
14073 | --val; | |
14074 | } | |
14075 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14076 | addr -= 4; | |
14077 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14078 | addr -= 2; | |
14079 | ||
14080 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14081 | val -= addr; | |
14082 | ||
14083 | /* Make sure the section winds up with the alignment we have | |
14084 | assumed. */ | |
14085 | if (op->shift > 0) | |
14086 | record_alignment (asec, op->shift); | |
14087 | } | |
14088 | ||
14089 | if (ext | |
14090 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14091 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14092 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14093 | _("extended instruction in delay slot")); | |
14094 | ||
14095 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14096 | ||
14097 | if (target_big_endian) | |
14098 | insn = bfd_getb16 (buf); | |
14099 | else | |
14100 | insn = bfd_getl16 (buf); | |
14101 | ||
14102 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14103 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14104 | small, ext, &insn, &use_extend, &extend); | |
14105 | ||
14106 | if (use_extend) | |
14107 | { | |
2132e3a3 | 14108 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14109 | fragp->fr_fix += 2; |
14110 | buf += 2; | |
14111 | } | |
14112 | ||
2132e3a3 | 14113 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14114 | fragp->fr_fix += 2; |
14115 | buf += 2; | |
14116 | } | |
14117 | else | |
14118 | { | |
4d7206a2 RS |
14119 | int first, second; |
14120 | fixS *fixp; | |
252b5132 | 14121 | |
4d7206a2 RS |
14122 | first = RELAX_FIRST (fragp->fr_subtype); |
14123 | second = RELAX_SECOND (fragp->fr_subtype); | |
14124 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14125 | |
584892a6 RS |
14126 | /* Possibly emit a warning if we've chosen the longer option. */ |
14127 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14128 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14129 | { | |
14130 | const char *msg = macro_warning (fragp->fr_subtype); | |
14131 | if (msg != 0) | |
14132 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
14133 | } | |
14134 | ||
4d7206a2 RS |
14135 | /* Go through all the fixups for the first sequence. Disable them |
14136 | (by marking them as done) if we're going to use the second | |
14137 | sequence instead. */ | |
14138 | while (fixp | |
14139 | && fixp->fx_frag == fragp | |
14140 | && fixp->fx_where < fragp->fr_fix - second) | |
14141 | { | |
14142 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14143 | fixp->fx_done = 1; | |
14144 | fixp = fixp->fx_next; | |
14145 | } | |
252b5132 | 14146 | |
4d7206a2 RS |
14147 | /* Go through the fixups for the second sequence. Disable them if |
14148 | we're going to use the first sequence, otherwise adjust their | |
14149 | addresses to account for the relaxation. */ | |
14150 | while (fixp && fixp->fx_frag == fragp) | |
14151 | { | |
14152 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14153 | fixp->fx_where -= first; | |
14154 | else | |
14155 | fixp->fx_done = 1; | |
14156 | fixp = fixp->fx_next; | |
14157 | } | |
14158 | ||
14159 | /* Now modify the frag contents. */ | |
14160 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14161 | { | |
14162 | char *start; | |
14163 | ||
14164 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14165 | memmove (start, start + first, second); | |
14166 | fragp->fr_fix -= first; | |
14167 | } | |
14168 | else | |
14169 | fragp->fr_fix -= second; | |
252b5132 RH |
14170 | } |
14171 | } | |
14172 | ||
14173 | #ifdef OBJ_ELF | |
14174 | ||
14175 | /* This function is called after the relocs have been generated. | |
14176 | We've been storing mips16 text labels as odd. Here we convert them | |
14177 | back to even for the convenience of the debugger. */ | |
14178 | ||
14179 | void | |
17a2f251 | 14180 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14181 | { |
14182 | asymbol **syms; | |
14183 | unsigned int count, i; | |
14184 | ||
f43abd2b | 14185 | if (!IS_ELF) |
252b5132 RH |
14186 | return; |
14187 | ||
14188 | syms = bfd_get_outsymbols (stdoutput); | |
14189 | count = bfd_get_symcount (stdoutput); | |
14190 | for (i = 0; i < count; i++, syms++) | |
14191 | { | |
14192 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14193 | && ((*syms)->value & 1) != 0) | |
14194 | { | |
14195 | (*syms)->value &= ~1; | |
14196 | /* If the symbol has an odd size, it was probably computed | |
14197 | incorrectly, so adjust that as well. */ | |
14198 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14199 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14200 | } | |
14201 | } | |
14202 | } | |
14203 | ||
14204 | #endif | |
14205 | ||
14206 | /* This function is called whenever a label is defined. It is used | |
14207 | when handling branch delays; if a branch has a label, we assume we | |
14208 | can not move it. */ | |
14209 | ||
14210 | void | |
17a2f251 | 14211 | mips_define_label (symbolS *sym) |
252b5132 | 14212 | { |
a8dbcb85 | 14213 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14214 | struct insn_label_list *l; |
14215 | ||
14216 | if (free_insn_labels == NULL) | |
14217 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14218 | else | |
14219 | { | |
14220 | l = free_insn_labels; | |
14221 | free_insn_labels = l->next; | |
14222 | } | |
14223 | ||
14224 | l->label = sym; | |
a8dbcb85 TS |
14225 | l->next = si->label_list; |
14226 | si->label_list = l; | |
07a53e5c RH |
14227 | |
14228 | #ifdef OBJ_ELF | |
14229 | dwarf2_emit_label (sym); | |
14230 | #endif | |
252b5132 RH |
14231 | } |
14232 | \f | |
14233 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14234 | ||
14235 | /* Some special processing for a MIPS ELF file. */ | |
14236 | ||
14237 | void | |
17a2f251 | 14238 | mips_elf_final_processing (void) |
252b5132 RH |
14239 | { |
14240 | /* Write out the register information. */ | |
316f5878 | 14241 | if (mips_abi != N64_ABI) |
252b5132 RH |
14242 | { |
14243 | Elf32_RegInfo s; | |
14244 | ||
14245 | s.ri_gprmask = mips_gprmask; | |
14246 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14247 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14248 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14249 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14250 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14251 | ||
14252 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14253 | ((Elf32_External_RegInfo *) | |
14254 | mips_regmask_frag)); | |
14255 | } | |
14256 | else | |
14257 | { | |
14258 | Elf64_Internal_RegInfo s; | |
14259 | ||
14260 | s.ri_gprmask = mips_gprmask; | |
14261 | s.ri_pad = 0; | |
14262 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14263 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14264 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14265 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14266 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14267 | ||
14268 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14269 | ((Elf64_External_RegInfo *) | |
14270 | mips_regmask_frag)); | |
14271 | } | |
14272 | ||
14273 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14274 | sort of BFD interface for this. */ | |
14275 | if (mips_any_noreorder) | |
14276 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14277 | if (mips_pic != NO_PIC) | |
143d77c5 | 14278 | { |
252b5132 | 14279 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14280 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14281 | } | |
14282 | if (mips_abicalls) | |
14283 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14284 | |
98d3f06f | 14285 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14286 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14287 | file_ase_dsp is true. */ | |
8b082fb1 | 14288 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14289 | /* We may need to define a new flag for MT ASE, and set this flag when |
14290 | file_ase_mt is true. */ | |
a4672219 TS |
14291 | if (file_ase_mips16) |
14292 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14293 | #if 0 /* XXX FIXME */ |
14294 | if (file_ase_mips3d) | |
14295 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14296 | #endif | |
deec1734 CD |
14297 | if (file_ase_mdmx) |
14298 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14299 | |
bdaaa2e1 | 14300 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14301 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14302 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14303 | else if (mips_abi == O64_ABI) |
252b5132 | 14304 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14305 | else if (mips_abi == EABI_ABI) |
252b5132 | 14306 | { |
316f5878 | 14307 | if (!file_mips_gp32) |
252b5132 RH |
14308 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14309 | else | |
14310 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14311 | } | |
316f5878 | 14312 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14313 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14314 | ||
c9914766 | 14315 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14316 | |
14317 | if (mips_32bitmode) | |
14318 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14319 | |
14320 | #if 0 /* XXX FIXME */ | |
14321 | /* 32 bit code with 64 bit FP registers. */ | |
14322 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14323 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14324 | #endif | |
252b5132 RH |
14325 | } |
14326 | ||
14327 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14328 | \f | |
beae10d5 | 14329 | typedef struct proc { |
9b2f1d35 EC |
14330 | symbolS *func_sym; |
14331 | symbolS *func_end_sym; | |
beae10d5 KH |
14332 | unsigned long reg_mask; |
14333 | unsigned long reg_offset; | |
14334 | unsigned long fpreg_mask; | |
14335 | unsigned long fpreg_offset; | |
14336 | unsigned long frame_offset; | |
14337 | unsigned long frame_reg; | |
14338 | unsigned long pc_reg; | |
14339 | } procS; | |
252b5132 RH |
14340 | |
14341 | static procS cur_proc; | |
14342 | static procS *cur_proc_ptr; | |
14343 | static int numprocs; | |
14344 | ||
742a56fe RS |
14345 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14346 | nop as "0". */ | |
14347 | ||
14348 | char | |
14349 | mips_nop_opcode (void) | |
14350 | { | |
14351 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14352 | } | |
14353 | ||
14354 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14355 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14356 | |
0a9ef439 | 14357 | void |
17a2f251 | 14358 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14359 | { |
742a56fe RS |
14360 | char *p; |
14361 | ||
0a9ef439 RH |
14362 | if (fragp->fr_type != rs_align_code) |
14363 | return; | |
14364 | ||
742a56fe RS |
14365 | p = fragp->fr_literal + fragp->fr_fix; |
14366 | if (*p) | |
a19d8eb0 | 14367 | { |
0a9ef439 | 14368 | int bytes; |
a19d8eb0 | 14369 | |
0a9ef439 | 14370 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
0a9ef439 RH |
14371 | if (bytes & 1) |
14372 | { | |
14373 | *p++ = 0; | |
f9419b05 | 14374 | fragp->fr_fix++; |
0a9ef439 | 14375 | } |
742a56fe | 14376 | md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2); |
0a9ef439 | 14377 | fragp->fr_var = 2; |
a19d8eb0 | 14378 | } |
a19d8eb0 CP |
14379 | } |
14380 | ||
252b5132 | 14381 | static void |
17a2f251 | 14382 | md_obj_begin (void) |
252b5132 RH |
14383 | { |
14384 | } | |
14385 | ||
14386 | static void | |
17a2f251 | 14387 | md_obj_end (void) |
252b5132 | 14388 | { |
54f4ddb3 | 14389 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14390 | if (cur_proc_ptr) |
9a41af64 | 14391 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14392 | } |
14393 | ||
14394 | static long | |
17a2f251 | 14395 | get_number (void) |
252b5132 RH |
14396 | { |
14397 | int negative = 0; | |
14398 | long val = 0; | |
14399 | ||
14400 | if (*input_line_pointer == '-') | |
14401 | { | |
14402 | ++input_line_pointer; | |
14403 | negative = 1; | |
14404 | } | |
3882b010 | 14405 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14406 | as_bad (_("expected simple number")); |
252b5132 RH |
14407 | if (input_line_pointer[0] == '0') |
14408 | { | |
14409 | if (input_line_pointer[1] == 'x') | |
14410 | { | |
14411 | input_line_pointer += 2; | |
3882b010 | 14412 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14413 | { |
14414 | val <<= 4; | |
14415 | val |= hex_value (*input_line_pointer++); | |
14416 | } | |
14417 | return negative ? -val : val; | |
14418 | } | |
14419 | else | |
14420 | { | |
14421 | ++input_line_pointer; | |
3882b010 | 14422 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14423 | { |
14424 | val <<= 3; | |
14425 | val |= *input_line_pointer++ - '0'; | |
14426 | } | |
14427 | return negative ? -val : val; | |
14428 | } | |
14429 | } | |
3882b010 | 14430 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14431 | { |
14432 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14433 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14434 | as_warn (_("invalid number")); |
252b5132 RH |
14435 | return -1; |
14436 | } | |
3882b010 | 14437 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14438 | { |
14439 | val *= 10; | |
14440 | val += *input_line_pointer++ - '0'; | |
14441 | } | |
14442 | return negative ? -val : val; | |
14443 | } | |
14444 | ||
14445 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14446 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14447 | case .file implies DWARF-2. */ | |
14448 | ||
14449 | static void | |
17a2f251 | 14450 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14451 | { |
ecb4347a DJ |
14452 | static int first_file_directive = 0; |
14453 | ||
c5dd6aab DJ |
14454 | if (ECOFF_DEBUGGING) |
14455 | { | |
14456 | get_number (); | |
14457 | s_app_file (0); | |
14458 | } | |
14459 | else | |
ecb4347a DJ |
14460 | { |
14461 | char *filename; | |
14462 | ||
14463 | filename = dwarf2_directive_file (0); | |
14464 | ||
14465 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14466 | directive even for stabs output. Make sure that this | |
14467 | ".file" is handled. Note that you need a version of GCC | |
14468 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14469 | if (filename != NULL && ! first_file_directive) | |
14470 | { | |
14471 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14472 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14473 | } |
14474 | first_file_directive = 1; | |
14475 | } | |
c5dd6aab DJ |
14476 | } |
14477 | ||
14478 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14479 | |
14480 | static void | |
17a2f251 | 14481 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14482 | { |
c5dd6aab DJ |
14483 | if (!ECOFF_DEBUGGING) |
14484 | dwarf2_directive_loc (0); | |
252b5132 RH |
14485 | } |
14486 | ||
252b5132 RH |
14487 | /* The .end directive. */ |
14488 | ||
14489 | static void | |
17a2f251 | 14490 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14491 | { |
14492 | symbolS *p; | |
252b5132 | 14493 | |
7a621144 DJ |
14494 | /* Following functions need their own .frame and .cprestore directives. */ |
14495 | mips_frame_reg_valid = 0; | |
14496 | mips_cprestore_valid = 0; | |
14497 | ||
252b5132 RH |
14498 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14499 | { | |
14500 | p = get_symbol (); | |
14501 | demand_empty_rest_of_line (); | |
14502 | } | |
14503 | else | |
14504 | p = NULL; | |
14505 | ||
14949570 | 14506 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14507 | as_warn (_(".end not in text section")); |
14508 | ||
14509 | if (!cur_proc_ptr) | |
14510 | { | |
14511 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14512 | demand_empty_rest_of_line (); | |
14513 | return; | |
14514 | } | |
14515 | ||
14516 | if (p != NULL) | |
14517 | { | |
14518 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14519 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14520 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14521 | |
14522 | if (debug_type == DEBUG_STABS) | |
14523 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14524 | S_GET_NAME (p)); | |
252b5132 RH |
14525 | } |
14526 | else | |
14527 | as_warn (_(".end directive missing or unknown symbol")); | |
14528 | ||
2132e3a3 | 14529 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14530 | /* Create an expression to calculate the size of the function. */ |
14531 | if (p && cur_proc_ptr) | |
14532 | { | |
14533 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14534 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14535 | ||
14536 | obj->size = exp; | |
14537 | exp->X_op = O_subtract; | |
14538 | exp->X_add_symbol = symbol_temp_new_now (); | |
14539 | exp->X_op_symbol = p; | |
14540 | exp->X_add_number = 0; | |
14541 | ||
14542 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14543 | } | |
14544 | ||
ecb4347a | 14545 | /* Generate a .pdr section. */ |
f43abd2b | 14546 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14547 | { |
14548 | segT saved_seg = now_seg; | |
14549 | subsegT saved_subseg = now_subseg; | |
14550 | valueT dot; | |
14551 | expressionS exp; | |
14552 | char *fragp; | |
252b5132 | 14553 | |
ecb4347a | 14554 | dot = frag_now_fix (); |
252b5132 RH |
14555 | |
14556 | #ifdef md_flush_pending_output | |
ecb4347a | 14557 | md_flush_pending_output (); |
252b5132 RH |
14558 | #endif |
14559 | ||
ecb4347a DJ |
14560 | assert (pdr_seg); |
14561 | subseg_set (pdr_seg, 0); | |
252b5132 | 14562 | |
ecb4347a DJ |
14563 | /* Write the symbol. */ |
14564 | exp.X_op = O_symbol; | |
14565 | exp.X_add_symbol = p; | |
14566 | exp.X_add_number = 0; | |
14567 | emit_expr (&exp, 4); | |
252b5132 | 14568 | |
ecb4347a | 14569 | fragp = frag_more (7 * 4); |
252b5132 | 14570 | |
17a2f251 TS |
14571 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14572 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14573 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14574 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14575 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14576 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14577 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14578 | |
ecb4347a DJ |
14579 | subseg_set (saved_seg, saved_subseg); |
14580 | } | |
14581 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14582 | |
14583 | cur_proc_ptr = NULL; | |
14584 | } | |
14585 | ||
14586 | /* The .aent and .ent directives. */ | |
14587 | ||
14588 | static void | |
17a2f251 | 14589 | s_mips_ent (int aent) |
252b5132 | 14590 | { |
252b5132 | 14591 | symbolS *symbolP; |
252b5132 RH |
14592 | |
14593 | symbolP = get_symbol (); | |
14594 | if (*input_line_pointer == ',') | |
f9419b05 | 14595 | ++input_line_pointer; |
252b5132 | 14596 | SKIP_WHITESPACE (); |
3882b010 | 14597 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14598 | || *input_line_pointer == '-') |
874e8986 | 14599 | get_number (); |
252b5132 | 14600 | |
14949570 | 14601 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14602 | as_warn (_(".ent or .aent not in text section.")); |
14603 | ||
14604 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14605 | as_warn (_("missing .end")); |
252b5132 RH |
14606 | |
14607 | if (!aent) | |
14608 | { | |
7a621144 DJ |
14609 | /* This function needs its own .frame and .cprestore directives. */ |
14610 | mips_frame_reg_valid = 0; | |
14611 | mips_cprestore_valid = 0; | |
14612 | ||
252b5132 RH |
14613 | cur_proc_ptr = &cur_proc; |
14614 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14615 | ||
9b2f1d35 | 14616 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14617 | |
49309057 | 14618 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14619 | |
f9419b05 | 14620 | ++numprocs; |
ecb4347a DJ |
14621 | |
14622 | if (debug_type == DEBUG_STABS) | |
14623 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14624 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14625 | } |
14626 | ||
14627 | demand_empty_rest_of_line (); | |
14628 | } | |
14629 | ||
14630 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14631 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14632 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14633 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14634 | symbol table (in the mdebug section). */ |
14635 | ||
14636 | static void | |
17a2f251 | 14637 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14638 | { |
ecb4347a | 14639 | #ifdef OBJ_ELF |
f43abd2b | 14640 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14641 | { |
14642 | long val; | |
252b5132 | 14643 | |
ecb4347a DJ |
14644 | if (cur_proc_ptr == (procS *) NULL) |
14645 | { | |
14646 | as_warn (_(".frame outside of .ent")); | |
14647 | demand_empty_rest_of_line (); | |
14648 | return; | |
14649 | } | |
252b5132 | 14650 | |
ecb4347a DJ |
14651 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14652 | ||
14653 | SKIP_WHITESPACE (); | |
14654 | if (*input_line_pointer++ != ',' | |
14655 | || get_absolute_expression_and_terminator (&val) != ',') | |
14656 | { | |
14657 | as_warn (_("Bad .frame directive")); | |
14658 | --input_line_pointer; | |
14659 | demand_empty_rest_of_line (); | |
14660 | return; | |
14661 | } | |
252b5132 | 14662 | |
ecb4347a DJ |
14663 | cur_proc_ptr->frame_offset = val; |
14664 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14665 | |
252b5132 | 14666 | demand_empty_rest_of_line (); |
252b5132 | 14667 | } |
ecb4347a DJ |
14668 | else |
14669 | #endif /* OBJ_ELF */ | |
14670 | s_ignore (ignore); | |
252b5132 RH |
14671 | } |
14672 | ||
bdaaa2e1 KH |
14673 | /* The .fmask and .mask directives. If the mdebug section is present |
14674 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14675 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14676 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14677 | make reference to the ecoff symbol table (in the mdebug section). */ |
14678 | ||
14679 | static void | |
17a2f251 | 14680 | s_mips_mask (int reg_type) |
252b5132 | 14681 | { |
ecb4347a | 14682 | #ifdef OBJ_ELF |
f43abd2b | 14683 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14684 | { |
ecb4347a | 14685 | long mask, off; |
252b5132 | 14686 | |
ecb4347a DJ |
14687 | if (cur_proc_ptr == (procS *) NULL) |
14688 | { | |
14689 | as_warn (_(".mask/.fmask outside of .ent")); | |
14690 | demand_empty_rest_of_line (); | |
14691 | return; | |
14692 | } | |
252b5132 | 14693 | |
ecb4347a DJ |
14694 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14695 | { | |
14696 | as_warn (_("Bad .mask/.fmask directive")); | |
14697 | --input_line_pointer; | |
14698 | demand_empty_rest_of_line (); | |
14699 | return; | |
14700 | } | |
252b5132 | 14701 | |
ecb4347a DJ |
14702 | off = get_absolute_expression (); |
14703 | ||
14704 | if (reg_type == 'F') | |
14705 | { | |
14706 | cur_proc_ptr->fpreg_mask = mask; | |
14707 | cur_proc_ptr->fpreg_offset = off; | |
14708 | } | |
14709 | else | |
14710 | { | |
14711 | cur_proc_ptr->reg_mask = mask; | |
14712 | cur_proc_ptr->reg_offset = off; | |
14713 | } | |
14714 | ||
14715 | demand_empty_rest_of_line (); | |
252b5132 RH |
14716 | } |
14717 | else | |
ecb4347a DJ |
14718 | #endif /* OBJ_ELF */ |
14719 | s_ignore (reg_type); | |
252b5132 RH |
14720 | } |
14721 | ||
316f5878 RS |
14722 | /* A table describing all the processors gas knows about. Names are |
14723 | matched in the order listed. | |
e7af610e | 14724 | |
316f5878 RS |
14725 | To ease comparison, please keep this table in the same order as |
14726 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14727 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14728 | { | |
316f5878 | 14729 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14730 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14731 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14732 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14733 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14734 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14735 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14736 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14737 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14738 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14739 | |
14740 | /* MIPS I */ | |
ad3fea08 TS |
14741 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14742 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14743 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14744 | |
14745 | /* MIPS II */ | |
ad3fea08 | 14746 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14747 | |
14748 | /* MIPS III */ | |
ad3fea08 TS |
14749 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14750 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14751 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14752 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14753 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14754 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14755 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14756 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14757 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14758 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14759 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14760 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14761 | |
14762 | /* MIPS IV */ | |
ad3fea08 TS |
14763 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14764 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14765 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14766 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14767 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14768 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14769 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14770 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14771 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14772 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14773 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14774 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14775 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14776 | |
14777 | /* MIPS 32 */ | |
ad3fea08 TS |
14778 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14779 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14780 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14781 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14782 | ||
14783 | /* MIPS 32 Release 2 */ | |
14784 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14785 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14786 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14787 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14788 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14789 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14790 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14791 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14792 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14793 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14794 | /* Deprecated forms of the above. */ | |
14795 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14796 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14797 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 14798 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14799 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14800 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14801 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14802 | /* Deprecated forms of the above. */ | |
14803 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14804 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14805 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
14806 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14807 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14808 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14809 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14810 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14811 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14812 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14813 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14814 | /* Deprecated forms of the above. */ | |
14815 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14816 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14817 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14818 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14819 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
14820 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14821 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14822 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14823 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14824 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14825 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14826 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14827 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14828 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14829 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14830 | /* Deprecated forms of the above. */ | |
14831 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14832 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14833 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14834 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 14835 | |
316f5878 | 14836 | /* MIPS 64 */ |
ad3fea08 TS |
14837 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14838 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14839 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 14840 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
14841 | |
14842 | /* MIPS 64 Release 2 */ | |
e7af610e | 14843 | |
c7a23324 | 14844 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14845 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14846 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
14847 | /* Broadcom SB-1A CPU core */ |
14848 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
14849 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14850 | |
350cc38d MS |
14851 | /* ST Microelectronics Loongson 2E and 2F cores */ |
14852 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
14853 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
14854 | ||
316f5878 RS |
14855 | /* End marker */ |
14856 | { NULL, 0, 0, 0 } | |
14857 | }; | |
e7af610e | 14858 | |
84ea6cf2 | 14859 | |
316f5878 RS |
14860 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14861 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14862 | |
316f5878 | 14863 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14864 | |
b34976b6 | 14865 | static bfd_boolean |
17a2f251 | 14866 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14867 | { |
14868 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14869 | given++, canonical++; | |
14870 | ||
14871 | return ((*given == 0 && *canonical == 0) | |
14872 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14873 | } | |
14874 | ||
14875 | ||
14876 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14877 | CPU name. We've traditionally allowed a lot of variation here. | |
14878 | ||
14879 | Note: this function is shared between GCC and GAS. */ | |
14880 | ||
b34976b6 | 14881 | static bfd_boolean |
17a2f251 | 14882 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14883 | { |
14884 | /* First see if the name matches exactly, or with a final "000" | |
14885 | turned into "k". */ | |
14886 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14887 | return TRUE; |
316f5878 RS |
14888 | |
14889 | /* If not, try comparing based on numerical designation alone. | |
14890 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14891 | if (TOLOWER (*given) == 'r') | |
14892 | given++; | |
14893 | if (!ISDIGIT (*given)) | |
b34976b6 | 14894 | return FALSE; |
316f5878 RS |
14895 | |
14896 | /* Skip over some well-known prefixes in the canonical name, | |
14897 | hoping to find a number there too. */ | |
14898 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14899 | canonical += 2; | |
14900 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14901 | canonical += 2; | |
14902 | else if (TOLOWER (canonical[0]) == 'r') | |
14903 | canonical += 1; | |
14904 | ||
14905 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14906 | } | |
14907 | ||
14908 | ||
14909 | /* Parse an option that takes the name of a processor as its argument. | |
14910 | OPTION is the name of the option and CPU_STRING is the argument. | |
14911 | Return the corresponding processor enumeration if the CPU_STRING is | |
14912 | recognized, otherwise report an error and return null. | |
14913 | ||
14914 | A similar function exists in GCC. */ | |
e7af610e NC |
14915 | |
14916 | static const struct mips_cpu_info * | |
17a2f251 | 14917 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14918 | { |
316f5878 | 14919 | const struct mips_cpu_info *p; |
e7af610e | 14920 | |
316f5878 RS |
14921 | /* 'from-abi' selects the most compatible architecture for the given |
14922 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14923 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14924 | version. Look first at the -mgp options, if given, otherwise base | |
14925 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14926 | |
316f5878 RS |
14927 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14928 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14929 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14930 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14931 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14932 | { | |
14933 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14934 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14935 | ||
14936 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14937 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14938 | ||
14939 | if (file_mips_gp32 >= 0) | |
14940 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14941 | ||
14942 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14943 | ? ISA_MIPS3 | |
14944 | : ISA_MIPS1); | |
14945 | } | |
14946 | ||
14947 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14948 | if (strcasecmp (cpu_string, "default") == 0) | |
14949 | return 0; | |
14950 | ||
14951 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14952 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14953 | return p; | |
14954 | ||
14955 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14956 | return 0; | |
e7af610e NC |
14957 | } |
14958 | ||
316f5878 RS |
14959 | /* Return the canonical processor information for ISA (a member of the |
14960 | ISA_MIPS* enumeration). */ | |
14961 | ||
e7af610e | 14962 | static const struct mips_cpu_info * |
17a2f251 | 14963 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14964 | { |
14965 | int i; | |
14966 | ||
14967 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14968 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14969 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14970 | return (&mips_cpu_info_table[i]); |
14971 | ||
e972090a | 14972 | return NULL; |
e7af610e | 14973 | } |
fef14a42 TS |
14974 | |
14975 | static const struct mips_cpu_info * | |
17a2f251 | 14976 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14977 | { |
14978 | int i; | |
14979 | ||
14980 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14981 | if (arch == mips_cpu_info_table[i].cpu) | |
14982 | return (&mips_cpu_info_table[i]); | |
14983 | ||
14984 | return NULL; | |
14985 | } | |
316f5878 RS |
14986 | \f |
14987 | static void | |
17a2f251 | 14988 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14989 | { |
14990 | if (*first_p) | |
14991 | { | |
14992 | fprintf (stream, "%24s", ""); | |
14993 | *col_p = 24; | |
14994 | } | |
14995 | else | |
14996 | { | |
14997 | fprintf (stream, ", "); | |
14998 | *col_p += 2; | |
14999 | } | |
e7af610e | 15000 | |
316f5878 RS |
15001 | if (*col_p + strlen (string) > 72) |
15002 | { | |
15003 | fprintf (stream, "\n%24s", ""); | |
15004 | *col_p = 24; | |
15005 | } | |
15006 | ||
15007 | fprintf (stream, "%s", string); | |
15008 | *col_p += strlen (string); | |
15009 | ||
15010 | *first_p = 0; | |
15011 | } | |
15012 | ||
15013 | void | |
17a2f251 | 15014 | md_show_usage (FILE *stream) |
e7af610e | 15015 | { |
316f5878 RS |
15016 | int column, first; |
15017 | size_t i; | |
15018 | ||
15019 | fprintf (stream, _("\ | |
15020 | MIPS options:\n\ | |
316f5878 RS |
15021 | -EB generate big endian output\n\ |
15022 | -EL generate little endian output\n\ | |
15023 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15024 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15025 | implicitly with the gp register [default 8]\n")); | |
15026 | fprintf (stream, _("\ | |
15027 | -mips1 generate MIPS ISA I instructions\n\ | |
15028 | -mips2 generate MIPS ISA II instructions\n\ | |
15029 | -mips3 generate MIPS ISA III instructions\n\ | |
15030 | -mips4 generate MIPS ISA IV instructions\n\ | |
15031 | -mips5 generate MIPS ISA V instructions\n\ | |
15032 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15033 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15034 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15035 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15036 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15037 | ||
15038 | first = 1; | |
e7af610e NC |
15039 | |
15040 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15041 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15042 | show (stream, "from-abi", &column, &first); | |
15043 | fputc ('\n', stream); | |
e7af610e | 15044 | |
316f5878 RS |
15045 | fprintf (stream, _("\ |
15046 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15047 | -no-mCPU don't generate code specific to CPU.\n\ | |
15048 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15049 | ||
15050 | first = 1; | |
15051 | ||
15052 | show (stream, "3900", &column, &first); | |
15053 | show (stream, "4010", &column, &first); | |
15054 | show (stream, "4100", &column, &first); | |
15055 | show (stream, "4650", &column, &first); | |
15056 | fputc ('\n', stream); | |
15057 | ||
15058 | fprintf (stream, _("\ | |
15059 | -mips16 generate mips16 instructions\n\ | |
15060 | -no-mips16 do not generate mips16 instructions\n")); | |
15061 | fprintf (stream, _("\ | |
e16bfa71 TS |
15062 | -msmartmips generate smartmips instructions\n\ |
15063 | -mno-smartmips do not generate smartmips instructions\n")); | |
15064 | fprintf (stream, _("\ | |
74cd071d CF |
15065 | -mdsp generate DSP instructions\n\ |
15066 | -mno-dsp do not generate DSP instructions\n")); | |
15067 | fprintf (stream, _("\ | |
8b082fb1 TS |
15068 | -mdspr2 generate DSP R2 instructions\n\ |
15069 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15070 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15071 | -mmt generate MT instructions\n\ |
15072 | -mno-mt do not generate MT instructions\n")); | |
15073 | fprintf (stream, _("\ | |
d766e8ec | 15074 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15075 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
15076 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15077 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15078 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15079 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15080 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15081 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
15082 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
15083 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
15084 | #ifdef OBJ_ELF | |
15085 | fprintf (stream, _("\ | |
15086 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
0c000745 | 15087 | -mvxworks-pic generate VxWorks position independent code\n\ |
316f5878 RS |
15088 | -non_shared do not generate position independent code\n\ |
15089 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 15090 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15091 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15092 | position dependent (non shared) code\n\ |
316f5878 RS |
15093 | -mabi=ABI create ABI conformant object file for:\n")); |
15094 | ||
15095 | first = 1; | |
15096 | ||
15097 | show (stream, "32", &column, &first); | |
15098 | show (stream, "o64", &column, &first); | |
15099 | show (stream, "n32", &column, &first); | |
15100 | show (stream, "64", &column, &first); | |
15101 | show (stream, "eabi", &column, &first); | |
15102 | ||
15103 | fputc ('\n', stream); | |
15104 | ||
15105 | fprintf (stream, _("\ | |
15106 | -32 create o32 ABI object file (default)\n\ | |
15107 | -n32 create n32 ABI object file\n\ | |
15108 | -64 create 64 ABI object file\n")); | |
15109 | #endif | |
e7af610e | 15110 | } |
14e777e0 KB |
15111 | |
15112 | enum dwarf2_format | |
17a2f251 | 15113 | mips_dwarf2_format (void) |
14e777e0 | 15114 | { |
369943fe | 15115 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15116 | { |
15117 | #ifdef TE_IRIX | |
15118 | return dwarf2_format_64bit_irix; | |
15119 | #else | |
15120 | return dwarf2_format_64bit; | |
15121 | #endif | |
15122 | } | |
14e777e0 KB |
15123 | else |
15124 | return dwarf2_format_32bit; | |
15125 | } | |
73369e65 EC |
15126 | |
15127 | int | |
15128 | mips_dwarf2_addr_size (void) | |
15129 | { | |
369943fe | 15130 | if (HAVE_64BIT_SYMBOLS) |
73369e65 | 15131 | return 8; |
73369e65 EC |
15132 | else |
15133 | return 4; | |
15134 | } | |
5862107c EC |
15135 | |
15136 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15137 | void | |
15138 | mips_cfi_frame_initial_instructions (void) | |
15139 | { | |
15140 | cfi_add_CFA_def_cfa_register (SP); | |
15141 | } | |
15142 | ||
707bfff6 TS |
15143 | int |
15144 | tc_mips_regname_to_dw2regnum (char *regname) | |
15145 | { | |
15146 | unsigned int regnum = -1; | |
15147 | unsigned int reg; | |
15148 | ||
15149 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15150 | regnum = reg; | |
15151 | ||
15152 | return regnum; | |
15153 | } |