Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 RH |
113 | /* The name of the readonly data section. */ |
114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
115 | ? ".data" \ | |
116 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
117 | ? ".rdata" \ | |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a325df1d TS |
124 | /* The ABI to use. */ |
125 | enum mips_abi_level | |
126 | { | |
127 | NO_ABI = 0, | |
128 | O32_ABI, | |
129 | O64_ABI, | |
130 | N32_ABI, | |
131 | N64_ABI, | |
132 | EABI_ABI | |
133 | }; | |
134 | ||
135 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 136 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 137 | |
143d77c5 EC |
138 | /* Whether or not we have code that can call pic code. */ |
139 | int mips_abicalls = FALSE; | |
140 | ||
252b5132 RH |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
e972090a NC |
145 | struct mips_set_options |
146 | { | |
252b5132 RH |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
1f25f5d3 CD |
151 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
152 | if they have not been initialized. Changed by `.set <asename>', by | |
153 | command line options, and based on the default architecture. */ | |
154 | int ase_mips3d; | |
deec1734 | 155 | int ase_mdmx; |
252b5132 RH |
156 | /* Whether we are assembling for the mips16 processor. 0 if we are |
157 | not, 1 if we are, and -1 if the value has not been initialized. | |
158 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
159 | -nomips16 command line options, and the default CPU. */ | |
160 | int mips16; | |
161 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
162 | reorder' and `.set noreorder'. */ | |
163 | int noreorder; | |
164 | /* Non-zero if we should not permit the $at ($1) register to be used | |
165 | in instructions. Changed by `.set at' and `.set noat'. */ | |
166 | int noat; | |
167 | /* Non-zero if we should warn when a macro instruction expands into | |
168 | more than one machine instruction. Changed by `.set nomacro' and | |
169 | `.set macro'. */ | |
170 | int warn_about_macros; | |
171 | /* Non-zero if we should not move instructions. Changed by `.set | |
172 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
173 | int nomove; | |
174 | /* Non-zero if we should not optimize branches by moving the target | |
175 | of the branch into the delay slot. Actually, we don't perform | |
176 | this optimization anyhow. Changed by `.set bopt' and `.set | |
177 | nobopt'. */ | |
178 | int nobopt; | |
179 | /* Non-zero if we should not autoextend mips16 instructions. | |
180 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
181 | int noautoextend; | |
a325df1d TS |
182 | /* Restrict general purpose registers and floating point registers |
183 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
184 | is passed but can changed if the assembler code uses .set mipsN. */ | |
185 | int gp32; | |
186 | int fp32; | |
fef14a42 TS |
187 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
188 | command line option, and the default CPU. */ | |
189 | int arch; | |
252b5132 RH |
190 | }; |
191 | ||
a325df1d | 192 | /* True if -mgp32 was passed. */ |
a8e8e863 | 193 | static int file_mips_gp32 = -1; |
a325df1d TS |
194 | |
195 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 196 | static int file_mips_fp32 = -1; |
a325df1d | 197 | |
252b5132 | 198 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 199 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 200 | -1 to indicate that they have not been initialized. */ |
252b5132 | 201 | |
e972090a NC |
202 | static struct mips_set_options mips_opts = |
203 | { | |
fef14a42 | 204 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 205 | }; |
252b5132 RH |
206 | |
207 | /* These variables are filled in with the masks of registers used. | |
208 | The object format code reads them and puts them in the appropriate | |
209 | place. */ | |
210 | unsigned long mips_gprmask; | |
211 | unsigned long mips_cprmask[4]; | |
212 | ||
213 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 214 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 215 | |
a4672219 TS |
216 | /* True if -mips16 was passed or implied by arguments passed on the |
217 | command line (e.g., by -march). */ | |
218 | static int file_ase_mips16; | |
219 | ||
1f25f5d3 CD |
220 | /* True if -mips3d was passed or implied by arguments passed on the |
221 | command line (e.g., by -march). */ | |
222 | static int file_ase_mips3d; | |
223 | ||
deec1734 CD |
224 | /* True if -mdmx was passed or implied by arguments passed on the |
225 | command line (e.g., by -march). */ | |
226 | static int file_ase_mdmx; | |
227 | ||
ec68c924 | 228 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 229 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 230 | static const char *mips_arch_string; |
ec68c924 EC |
231 | |
232 | /* The argument of the -mtune= flag. The architecture for which we | |
233 | are optimizing. */ | |
234 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 235 | static const char *mips_tune_string; |
ec68c924 | 236 | |
316f5878 | 237 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
238 | static int mips_32bitmode = 0; |
239 | ||
316f5878 RS |
240 | /* True if the given ABI requires 32-bit registers. */ |
241 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
242 | ||
243 | /* Likewise 64-bit registers. */ | |
244 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
245 | ((ABI) == N32_ABI \ | |
246 | || (ABI) == N64_ABI \ | |
247 | || (ABI) == O64_ABI) | |
248 | ||
bdaaa2e1 | 249 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 250 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
251 | (ISA) == ISA_MIPS3 \ |
252 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 253 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 254 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 255 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
256 | ) |
257 | ||
af7ee8bf CD |
258 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
259 | instructions. */ | |
260 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 261 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
262 | ) |
263 | ||
264 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
265 | instructions. */ | |
266 | #define ISA_HAS_ROR(ISA) ( \ | |
267 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 268 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
269 | ) |
270 | ||
e013f690 | 271 | #define HAVE_32BIT_GPRS \ |
316f5878 | 272 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 273 | |
e013f690 | 274 | #define HAVE_32BIT_FPRS \ |
316f5878 | 275 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
276 | |
277 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
278 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
279 | ||
316f5878 | 280 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 281 | |
316f5878 | 282 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
283 | |
284 | /* We can only have 64bit addresses if the object file format | |
285 | supports it. */ | |
afdbd6d0 CD |
286 | #define HAVE_32BIT_ADDRESSES \ |
287 | (HAVE_32BIT_GPRS \ | |
288 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
289 | || ! HAVE_64BIT_OBJECTS) \ | |
290 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
291 | |
292 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 293 | |
b7c7d6c1 TS |
294 | /* Addresses are loaded in different ways, depending on the address size |
295 | in use. The n32 ABI Documentation also mandates the use of additions | |
296 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 297 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 298 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
299 | |
300 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_LOAD_INSN \ | |
304 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
305 | ||
306 | #define ADDRESS_STORE_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
308 | ||
a4672219 | 309 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
310 | #define CPU_HAS_MIPS16(cpu) \ |
311 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
312 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 313 | |
1f25f5d3 CD |
314 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
315 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
316 | ) | |
317 | ||
deec1734 | 318 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 319 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
320 | ) |
321 | ||
60b63b72 RS |
322 | /* True if CPU has a dror instruction. */ |
323 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
324 | ||
325 | /* True if CPU has a ror instruction. */ | |
326 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
327 | ||
bdaaa2e1 | 328 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 329 | reads from the HI and LO registers, and thus does not |
ec68c924 | 330 | require nops to be inserted. */ |
252b5132 | 331 | |
fef14a42 TS |
332 | #define hilo_interlocks (mips_opts.arch == CPU_R4010 \ |
333 | || mips_opts.arch == CPU_VR5500 \ | |
5a7ea749 | 334 | || mips_opts.arch == CPU_RM7000 \ |
fef14a42 | 335 | || mips_opts.arch == CPU_SB1 \ |
252b5132 RH |
336 | ) |
337 | ||
338 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
339 | from the GPRs after they are loaded from memory, and thus does not |
340 | require nops to be inserted. This applies to instructions marked | |
341 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
342 | level I. */ | |
252b5132 | 343 | #define gpr_interlocks \ |
e7af610e | 344 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 TS |
345 | || mips_opts.arch == CPU_VR5400 \ |
346 | || mips_opts.arch == CPU_VR5500 \ | |
347 | || mips_opts.arch == CPU_R3900) | |
252b5132 | 348 | |
81912461 ILT |
349 | /* Whether the processor uses hardware interlocks to avoid delays |
350 | required by coprocessor instructions, and thus does not require | |
351 | nops to be inserted. This applies to instructions marked | |
352 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
353 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
354 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
355 | levels I, II, and III. */ | |
bdaaa2e1 | 356 | /* Itbl support may require additional care here. */ |
81912461 ILT |
357 | #define cop_interlocks \ |
358 | ((mips_opts.isa != ISA_MIPS1 \ | |
359 | && mips_opts.isa != ISA_MIPS2 \ | |
360 | && mips_opts.isa != ISA_MIPS3) \ | |
361 | || mips_opts.arch == CPU_R4300 \ | |
362 | || mips_opts.arch == CPU_VR5400 \ | |
363 | || mips_opts.arch == CPU_VR5500 \ | |
364 | || mips_opts.arch == CPU_SB1 \ | |
365 | ) | |
366 | ||
367 | /* Whether the processor uses hardware interlocks to protect reads | |
368 | from coprocessor registers after they are loaded from memory, and | |
369 | thus does not require nops to be inserted. This applies to | |
370 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
371 | requires at MIPS ISA level I. */ | |
372 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 373 | |
6b76fefe CM |
374 | /* Is this a mfhi or mflo instruction? */ |
375 | #define MF_HILO_INSN(PINFO) \ | |
376 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
377 | ||
252b5132 RH |
378 | /* MIPS PIC level. */ |
379 | ||
a161fe53 | 380 | enum mips_pic_level mips_pic; |
252b5132 | 381 | |
c9914766 | 382 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 383 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 384 | static int mips_big_got = 0; |
252b5132 RH |
385 | |
386 | /* 1 if trap instructions should used for overflow rather than break | |
387 | instructions. */ | |
c9914766 | 388 | static int mips_trap = 0; |
252b5132 | 389 | |
119d663a | 390 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 391 | by assembling two single width halves into two single width floating |
119d663a NC |
392 | point registers which just happen to alias the double width destination |
393 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 394 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
395 | automatically at assemble time. */ |
396 | static int mips_disable_float_construction; | |
397 | ||
252b5132 RH |
398 | /* Non-zero if any .set noreorder directives were used. */ |
399 | ||
400 | static int mips_any_noreorder; | |
401 | ||
6b76fefe CM |
402 | /* Non-zero if nops should be inserted when the register referenced in |
403 | an mfhi/mflo instruction is read in the next two instructions. */ | |
404 | static int mips_7000_hilo_fix; | |
405 | ||
252b5132 | 406 | /* The size of the small data section. */ |
156c2f8b | 407 | static unsigned int g_switch_value = 8; |
252b5132 RH |
408 | /* Whether the -G option was used. */ |
409 | static int g_switch_seen = 0; | |
410 | ||
411 | #define N_RMASK 0xc4 | |
412 | #define N_VFP 0xd4 | |
413 | ||
414 | /* If we can determine in advance that GP optimization won't be | |
415 | possible, we can skip the relaxation stuff that tries to produce | |
416 | GP-relative references. This makes delay slot optimization work | |
417 | better. | |
418 | ||
419 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
420 | gcc output. It needs to guess right for gcc, otherwise gcc |
421 | will put what it thinks is a GP-relative instruction in a branch | |
422 | delay slot. | |
252b5132 RH |
423 | |
424 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
425 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 426 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
427 | |
428 | /* handle of the OPCODE hash table */ | |
429 | static struct hash_control *op_hash = NULL; | |
430 | ||
431 | /* The opcode hash table we use for the mips16. */ | |
432 | static struct hash_control *mips16_op_hash = NULL; | |
433 | ||
434 | /* This array holds the chars that always start a comment. If the | |
435 | pre-processor is disabled, these aren't very useful */ | |
436 | const char comment_chars[] = "#"; | |
437 | ||
438 | /* This array holds the chars that only start a comment at the beginning of | |
439 | a line. If the line seems to have the form '# 123 filename' | |
440 | .line and .file directives will appear in the pre-processed output */ | |
441 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
442 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 443 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
444 | /* Also note that C style comments are always supported. */ |
445 | const char line_comment_chars[] = "#"; | |
446 | ||
bdaaa2e1 | 447 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 448 | const char line_separator_chars[] = ";"; |
252b5132 RH |
449 | |
450 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
451 | const char EXP_CHARS[] = "eE"; | |
452 | ||
453 | /* Chars that mean this number is a floating point constant */ | |
454 | /* As in 0f12.456 */ | |
455 | /* or 0d1.2345e12 */ | |
456 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
457 | ||
458 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
459 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
460 | but nothing is ideal around here. | |
461 | */ | |
462 | ||
463 | static char *insn_error; | |
464 | ||
465 | static int auto_align = 1; | |
466 | ||
467 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
468 | offset in the stack frame from which to restore the $gp register. | |
469 | This is set by the .cprestore pseudo-op, and saved in this | |
470 | variable. */ | |
471 | static offsetT mips_cprestore_offset = -1; | |
472 | ||
67c1ffbe | 473 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 474 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 475 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
476 | static offsetT mips_cpreturn_offset = -1; |
477 | static int mips_cpreturn_register = -1; | |
478 | static int mips_gp_register = GP; | |
def2e0dd | 479 | static int mips_gprel_offset = 0; |
6478892d | 480 | |
7a621144 DJ |
481 | /* Whether mips_cprestore_offset has been set in the current function |
482 | (or whether it has already been warned about, if not). */ | |
483 | static int mips_cprestore_valid = 0; | |
484 | ||
252b5132 RH |
485 | /* This is the register which holds the stack frame, as set by the |
486 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
487 | static int mips_frame_reg = SP; | |
488 | ||
7a621144 DJ |
489 | /* Whether mips_frame_reg has been set in the current function |
490 | (or whether it has already been warned about, if not). */ | |
491 | static int mips_frame_reg_valid = 0; | |
492 | ||
252b5132 RH |
493 | /* To output NOP instructions correctly, we need to keep information |
494 | about the previous two instructions. */ | |
495 | ||
496 | /* Whether we are optimizing. The default value of 2 means to remove | |
497 | unneeded NOPs and swap branch instructions when possible. A value | |
498 | of 1 means to not swap branches. A value of 0 means to always | |
499 | insert NOPs. */ | |
500 | static int mips_optimize = 2; | |
501 | ||
502 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
503 | equivalent to seeing no -g option at all. */ | |
504 | static int mips_debug = 0; | |
505 | ||
506 | /* The previous instruction. */ | |
507 | static struct mips_cl_insn prev_insn; | |
508 | ||
509 | /* The instruction before prev_insn. */ | |
510 | static struct mips_cl_insn prev_prev_insn; | |
511 | ||
512 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
513 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 514 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
515 | |
516 | /* Non-zero if prev_insn is valid. */ | |
517 | static int prev_insn_valid; | |
518 | ||
519 | /* The frag for the previous instruction. */ | |
520 | static struct frag *prev_insn_frag; | |
521 | ||
522 | /* The offset into prev_insn_frag for the previous instruction. */ | |
523 | static long prev_insn_where; | |
524 | ||
525 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 526 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
527 | |
528 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 529 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
530 | |
531 | /* Non-zero if the previous instruction was in a delay slot. */ | |
532 | static int prev_insn_is_delay_slot; | |
533 | ||
534 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
535 | static int prev_insn_unreordered; | |
536 | ||
537 | /* Non-zero if the previous instruction uses an extend opcode (if | |
538 | mips16). */ | |
539 | static int prev_insn_extended; | |
540 | ||
541 | /* Non-zero if the previous previous instruction was in a .set | |
542 | noreorder. */ | |
543 | static int prev_prev_insn_unreordered; | |
544 | ||
545 | /* If this is set, it points to a frag holding nop instructions which | |
546 | were inserted before the start of a noreorder section. If those | |
547 | nops turn out to be unnecessary, the size of the frag can be | |
548 | decreased. */ | |
549 | static fragS *prev_nop_frag; | |
550 | ||
551 | /* The number of nop instructions we created in prev_nop_frag. */ | |
552 | static int prev_nop_frag_holds; | |
553 | ||
554 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 555 | prev_nop_frag. */ |
252b5132 RH |
556 | static int prev_nop_frag_required; |
557 | ||
558 | /* The number of instructions we've seen since prev_nop_frag. */ | |
559 | static int prev_nop_frag_since; | |
560 | ||
561 | /* For ECOFF and ELF, relocations against symbols are done in two | |
562 | parts, with a HI relocation and a LO relocation. Each relocation | |
563 | has only 16 bits of space to store an addend. This means that in | |
564 | order for the linker to handle carries correctly, it must be able | |
565 | to locate both the HI and the LO relocation. This means that the | |
566 | relocations must appear in order in the relocation table. | |
567 | ||
568 | In order to implement this, we keep track of each unmatched HI | |
569 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 570 | corresponding LO relocation. */ |
252b5132 | 571 | |
e972090a NC |
572 | struct mips_hi_fixup |
573 | { | |
252b5132 RH |
574 | /* Next HI fixup. */ |
575 | struct mips_hi_fixup *next; | |
576 | /* This fixup. */ | |
577 | fixS *fixp; | |
578 | /* The section this fixup is in. */ | |
579 | segT seg; | |
580 | }; | |
581 | ||
582 | /* The list of unmatched HI relocs. */ | |
583 | ||
584 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
585 | ||
64bdfcaf RS |
586 | /* The frag containing the last explicit relocation operator. |
587 | Null if explicit relocations have not been used. */ | |
588 | ||
589 | static fragS *prev_reloc_op_frag; | |
590 | ||
252b5132 RH |
591 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
592 | ||
593 | #define X ILLEGAL_REG | |
e972090a NC |
594 | static const int mips32_to_16_reg_map[] = |
595 | { | |
252b5132 RH |
596 | X, X, 2, 3, 4, 5, 6, 7, |
597 | X, X, X, X, X, X, X, X, | |
598 | 0, 1, X, X, X, X, X, X, | |
599 | X, X, X, X, X, X, X, X | |
600 | }; | |
601 | #undef X | |
602 | ||
603 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
604 | ||
e972090a NC |
605 | static const unsigned int mips16_to_32_reg_map[] = |
606 | { | |
252b5132 RH |
607 | 16, 17, 2, 3, 4, 5, 6, 7 |
608 | }; | |
60b63b72 RS |
609 | |
610 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
611 | |
612 | /* We don't relax branches by default, since this causes us to expand | |
613 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
614 | fail to compute the offset before expanding the macro to the most | |
615 | efficient expansion. */ | |
616 | ||
617 | static int mips_relax_branch; | |
252b5132 RH |
618 | \f |
619 | /* Since the MIPS does not have multiple forms of PC relative | |
620 | instructions, we do not have to do relaxing as is done on other | |
621 | platforms. However, we do have to handle GP relative addressing | |
622 | correctly, which turns out to be a similar problem. | |
623 | ||
624 | Every macro that refers to a symbol can occur in (at least) two | |
625 | forms, one with GP relative addressing and one without. For | |
626 | example, loading a global variable into a register generally uses | |
627 | a macro instruction like this: | |
628 | lw $4,i | |
629 | If i can be addressed off the GP register (this is true if it is in | |
630 | the .sbss or .sdata section, or if it is known to be smaller than | |
631 | the -G argument) this will generate the following instruction: | |
632 | lw $4,i($gp) | |
633 | This instruction will use a GPREL reloc. If i can not be addressed | |
634 | off the GP register, the following instruction sequence will be used: | |
635 | lui $at,i | |
636 | lw $4,i($at) | |
637 | In this case the first instruction will have a HI16 reloc, and the | |
638 | second reloc will have a LO16 reloc. Both relocs will be against | |
639 | the symbol i. | |
640 | ||
641 | The issue here is that we may not know whether i is GP addressable | |
642 | until after we see the instruction that uses it. Therefore, we | |
643 | want to be able to choose the final instruction sequence only at | |
644 | the end of the assembly. This is similar to the way other | |
645 | platforms choose the size of a PC relative instruction only at the | |
646 | end of assembly. | |
647 | ||
648 | When generating position independent code we do not use GP | |
649 | addressing in quite the same way, but the issue still arises as | |
650 | external symbols and local symbols must be handled differently. | |
651 | ||
652 | We handle these issues by actually generating both possible | |
653 | instruction sequences. The longer one is put in a frag_var with | |
654 | type rs_machine_dependent. We encode what to do with the frag in | |
655 | the subtype field. We encode (1) the number of existing bytes to | |
656 | replace, (2) the number of new bytes to use, (3) the offset from | |
657 | the start of the existing bytes to the first reloc we must generate | |
658 | (that is, the offset is applied from the start of the existing | |
659 | bytes after they are replaced by the new bytes, if any), (4) the | |
660 | offset from the start of the existing bytes to the second reloc, | |
661 | (5) whether a third reloc is needed (the third reloc is always four | |
662 | bytes after the second reloc), and (6) whether to warn if this | |
663 | variant is used (this is sometimes needed if .set nomacro or .set | |
664 | noat is in effect). All these numbers are reasonably small. | |
665 | ||
666 | Generating two instruction sequences must be handled carefully to | |
667 | ensure that delay slots are handled correctly. Fortunately, there | |
668 | are a limited number of cases. When the second instruction | |
669 | sequence is generated, append_insn is directed to maintain the | |
670 | existing delay slot information, so it continues to apply to any | |
671 | code after the second instruction sequence. This means that the | |
672 | second instruction sequence must not impose any requirements not | |
673 | required by the first instruction sequence. | |
674 | ||
675 | These variant frags are then handled in functions called by the | |
676 | machine independent code. md_estimate_size_before_relax returns | |
677 | the final size of the frag. md_convert_frag sets up the final form | |
678 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
679 | one if needed. */ | |
680 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
681 | ((relax_substateT) \ | |
682 | (((old) << 23) \ | |
683 | | ((new) << 16) \ | |
684 | | (((reloc1) + 64) << 9) \ | |
685 | | (((reloc2) + 64) << 2) \ | |
686 | | ((reloc3) ? (1 << 1) : 0) \ | |
687 | | ((warn) ? 1 : 0))) | |
688 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
689 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
690 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
691 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
692 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
693 | #define RELAX_WARN(i) ((i) & 1) | |
694 | ||
4a6a3df4 AO |
695 | /* Branch without likely bit. If label is out of range, we turn: |
696 | ||
697 | beq reg1, reg2, label | |
698 | delay slot | |
699 | ||
700 | into | |
701 | ||
702 | bne reg1, reg2, 0f | |
703 | nop | |
704 | j label | |
705 | 0: delay slot | |
706 | ||
707 | with the following opcode replacements: | |
708 | ||
709 | beq <-> bne | |
710 | blez <-> bgtz | |
711 | bltz <-> bgez | |
712 | bc1f <-> bc1t | |
713 | ||
714 | bltzal <-> bgezal (with jal label instead of j label) | |
715 | ||
716 | Even though keeping the delay slot instruction in the delay slot of | |
717 | the branch would be more efficient, it would be very tricky to do | |
718 | correctly, because we'd have to introduce a variable frag *after* | |
719 | the delay slot instruction, and expand that instead. Let's do it | |
720 | the easy way for now, even if the branch-not-taken case now costs | |
721 | one additional instruction. Out-of-range branches are not supposed | |
722 | to be common, anyway. | |
723 | ||
724 | Branch likely. If label is out of range, we turn: | |
725 | ||
726 | beql reg1, reg2, label | |
727 | delay slot (annulled if branch not taken) | |
728 | ||
729 | into | |
730 | ||
731 | beql reg1, reg2, 1f | |
732 | nop | |
733 | beql $0, $0, 2f | |
734 | nop | |
735 | 1: j[al] label | |
736 | delay slot (executed only if branch taken) | |
737 | 2: | |
738 | ||
739 | It would be possible to generate a shorter sequence by losing the | |
740 | likely bit, generating something like: | |
b34976b6 | 741 | |
4a6a3df4 AO |
742 | bne reg1, reg2, 0f |
743 | nop | |
744 | j[al] label | |
745 | delay slot (executed only if branch taken) | |
746 | 0: | |
747 | ||
748 | beql -> bne | |
749 | bnel -> beq | |
750 | blezl -> bgtz | |
751 | bgtzl -> blez | |
752 | bltzl -> bgez | |
753 | bgezl -> bltz | |
754 | bc1fl -> bc1t | |
755 | bc1tl -> bc1f | |
756 | ||
757 | bltzall -> bgezal (with jal label instead of j label) | |
758 | bgezall -> bltzal (ditto) | |
759 | ||
760 | ||
761 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 762 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
763 | ((relax_substateT) \ |
764 | (0xc0000000 \ | |
765 | | ((toofar) ? 1 : 0) \ | |
766 | | ((link) ? 2 : 0) \ | |
767 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 768 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 769 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
770 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
771 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
772 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 773 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 774 | |
252b5132 RH |
775 | /* For mips16 code, we use an entirely different form of relaxation. |
776 | mips16 supports two versions of most instructions which take | |
777 | immediate values: a small one which takes some small value, and a | |
778 | larger one which takes a 16 bit value. Since branches also follow | |
779 | this pattern, relaxing these values is required. | |
780 | ||
781 | We can assemble both mips16 and normal MIPS code in a single | |
782 | object. Therefore, we need to support this type of relaxation at | |
783 | the same time that we support the relaxation described above. We | |
784 | use the high bit of the subtype field to distinguish these cases. | |
785 | ||
786 | The information we store for this type of relaxation is the | |
787 | argument code found in the opcode file for this relocation, whether | |
788 | the user explicitly requested a small or extended form, and whether | |
789 | the relocation is in a jump or jal delay slot. That tells us the | |
790 | size of the value, and how it should be stored. We also store | |
791 | whether the fragment is considered to be extended or not. We also | |
792 | store whether this is known to be a branch to a different section, | |
793 | whether we have tried to relax this frag yet, and whether we have | |
794 | ever extended a PC relative fragment because of a shift count. */ | |
795 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
796 | (0x80000000 \ | |
797 | | ((type) & 0xff) \ | |
798 | | ((small) ? 0x100 : 0) \ | |
799 | | ((ext) ? 0x200 : 0) \ | |
800 | | ((dslot) ? 0x400 : 0) \ | |
801 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 802 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
803 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
804 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
805 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
806 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
807 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
808 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
809 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
810 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
811 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
812 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
813 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
814 | |
815 | /* Is the given value a sign-extended 32-bit value? */ | |
816 | #define IS_SEXT_32BIT_NUM(x) \ | |
817 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
818 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
819 | ||
820 | /* Is the given value a sign-extended 16-bit value? */ | |
821 | #define IS_SEXT_16BIT_NUM(x) \ | |
822 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
823 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
824 | ||
252b5132 RH |
825 | \f |
826 | /* Prototypes for static functions. */ | |
827 | ||
17a2f251 | 828 | #define internalError() \ |
252b5132 | 829 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
830 | |
831 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
832 | ||
b34976b6 | 833 | static void append_insn |
17a2f251 TS |
834 | (char *place, struct mips_cl_insn *ip, expressionS *p, |
835 | bfd_reloc_code_real_type *r); | |
836 | static void mips_no_prev_insn (int); | |
b34976b6 | 837 | static void mips16_macro_build |
17a2f251 TS |
838 | (char *, int *, expressionS *, const char *, const char *, va_list); |
839 | static void load_register (int *, int, expressionS *, int); | |
840 | static void macro (struct mips_cl_insn * ip); | |
841 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 842 | #ifdef LOSING_COMPILER |
17a2f251 | 843 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 844 | #endif |
17a2f251 TS |
845 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
846 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 847 | static void mips16_immed |
17a2f251 TS |
848 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
849 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 850 | static size_t my_getSmallExpression |
17a2f251 TS |
851 | (expressionS *, bfd_reloc_code_real_type *, char *); |
852 | static void my_getExpression (expressionS *, char *); | |
853 | static void s_align (int); | |
854 | static void s_change_sec (int); | |
855 | static void s_change_section (int); | |
856 | static void s_cons (int); | |
857 | static void s_float_cons (int); | |
858 | static void s_mips_globl (int); | |
859 | static void s_option (int); | |
860 | static void s_mipsset (int); | |
861 | static void s_abicalls (int); | |
862 | static void s_cpload (int); | |
863 | static void s_cpsetup (int); | |
864 | static void s_cplocal (int); | |
865 | static void s_cprestore (int); | |
866 | static void s_cpreturn (int); | |
867 | static void s_gpvalue (int); | |
868 | static void s_gpword (int); | |
869 | static void s_gpdword (int); | |
870 | static void s_cpadd (int); | |
871 | static void s_insn (int); | |
872 | static void md_obj_begin (void); | |
873 | static void md_obj_end (void); | |
874 | static void s_mips_ent (int); | |
875 | static void s_mips_end (int); | |
876 | static void s_mips_frame (int); | |
877 | static void s_mips_mask (int reg_type); | |
878 | static void s_mips_stab (int); | |
879 | static void s_mips_weakext (int); | |
880 | static void s_mips_file (int); | |
881 | static void s_mips_loc (int); | |
882 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 883 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 884 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
885 | |
886 | /* Table and functions used to map between CPU/ISA names, and | |
887 | ISA levels, and CPU numbers. */ | |
888 | ||
e972090a NC |
889 | struct mips_cpu_info |
890 | { | |
e7af610e NC |
891 | const char *name; /* CPU or ISA name. */ |
892 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
893 | int isa; /* ISA level. */ | |
894 | int cpu; /* CPU number (default CPU if ISA). */ | |
895 | }; | |
896 | ||
17a2f251 TS |
897 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
898 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
899 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
900 | \f |
901 | /* Pseudo-op table. | |
902 | ||
903 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
904 | should be defined here, but are currently unsupported: .alias, | |
905 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
906 | ||
907 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
908 | specific to the type of debugging information being generated, and | |
909 | should be defined by the object format: .aent, .begin, .bend, | |
910 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
911 | .vreg. | |
912 | ||
913 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
914 | not MIPS CPU specific, but are also not specific to the object file | |
915 | format. This file is probably the best place to define them, but | |
916 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
917 | .struct. */ | |
918 | ||
e972090a NC |
919 | static const pseudo_typeS mips_pseudo_table[] = |
920 | { | |
beae10d5 | 921 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
922 | {"option", s_option, 0}, |
923 | {"set", s_mipsset, 0}, | |
924 | {"rdata", s_change_sec, 'r'}, | |
925 | {"sdata", s_change_sec, 's'}, | |
926 | {"livereg", s_ignore, 0}, | |
927 | {"abicalls", s_abicalls, 0}, | |
928 | {"cpload", s_cpload, 0}, | |
6478892d TS |
929 | {"cpsetup", s_cpsetup, 0}, |
930 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 931 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
932 | {"cpreturn", s_cpreturn, 0}, |
933 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 934 | {"gpword", s_gpword, 0}, |
10181a0d | 935 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
936 | {"cpadd", s_cpadd, 0}, |
937 | {"insn", s_insn, 0}, | |
938 | ||
beae10d5 | 939 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
940 | chips. */ |
941 | {"asciiz", stringer, 1}, | |
942 | {"bss", s_change_sec, 'b'}, | |
943 | {"err", s_err, 0}, | |
944 | {"half", s_cons, 1}, | |
945 | {"dword", s_cons, 3}, | |
946 | {"weakext", s_mips_weakext, 0}, | |
947 | ||
beae10d5 | 948 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
949 | here for one reason or another. */ |
950 | {"align", s_align, 0}, | |
951 | {"byte", s_cons, 0}, | |
952 | {"data", s_change_sec, 'd'}, | |
953 | {"double", s_float_cons, 'd'}, | |
954 | {"float", s_float_cons, 'f'}, | |
955 | {"globl", s_mips_globl, 0}, | |
956 | {"global", s_mips_globl, 0}, | |
957 | {"hword", s_cons, 1}, | |
958 | {"int", s_cons, 2}, | |
959 | {"long", s_cons, 2}, | |
960 | {"octa", s_cons, 4}, | |
961 | {"quad", s_cons, 3}, | |
cca86cc8 | 962 | {"section", s_change_section, 0}, |
252b5132 RH |
963 | {"short", s_cons, 1}, |
964 | {"single", s_float_cons, 'f'}, | |
965 | {"stabn", s_mips_stab, 'n'}, | |
966 | {"text", s_change_sec, 't'}, | |
967 | {"word", s_cons, 2}, | |
add56521 | 968 | |
add56521 | 969 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 970 | |
43841e91 | 971 | { NULL, NULL, 0 }, |
252b5132 RH |
972 | }; |
973 | ||
e972090a NC |
974 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
975 | { | |
beae10d5 KH |
976 | /* These pseudo-ops should be defined by the object file format. |
977 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
978 | {"aent", s_mips_ent, 1}, |
979 | {"bgnb", s_ignore, 0}, | |
980 | {"end", s_mips_end, 0}, | |
981 | {"endb", s_ignore, 0}, | |
982 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 983 | {"file", s_mips_file, 0}, |
252b5132 RH |
984 | {"fmask", s_mips_mask, 'F'}, |
985 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 986 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
987 | {"mask", s_mips_mask, 'R'}, |
988 | {"verstamp", s_ignore, 0}, | |
43841e91 | 989 | { NULL, NULL, 0 }, |
252b5132 RH |
990 | }; |
991 | ||
17a2f251 | 992 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
993 | |
994 | void | |
17a2f251 | 995 | mips_pop_insert (void) |
252b5132 RH |
996 | { |
997 | pop_insert (mips_pseudo_table); | |
998 | if (! ECOFF_DEBUGGING) | |
999 | pop_insert (mips_nonecoff_pseudo_table); | |
1000 | } | |
1001 | \f | |
1002 | /* Symbols labelling the current insn. */ | |
1003 | ||
e972090a NC |
1004 | struct insn_label_list |
1005 | { | |
252b5132 RH |
1006 | struct insn_label_list *next; |
1007 | symbolS *label; | |
1008 | }; | |
1009 | ||
1010 | static struct insn_label_list *insn_labels; | |
1011 | static struct insn_label_list *free_insn_labels; | |
1012 | ||
17a2f251 | 1013 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1014 | |
1015 | static inline void | |
17a2f251 | 1016 | mips_clear_insn_labels (void) |
252b5132 RH |
1017 | { |
1018 | register struct insn_label_list **pl; | |
1019 | ||
1020 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1021 | ; | |
1022 | *pl = insn_labels; | |
1023 | insn_labels = NULL; | |
1024 | } | |
1025 | \f | |
1026 | static char *expr_end; | |
1027 | ||
1028 | /* Expressions which appear in instructions. These are set by | |
1029 | mips_ip. */ | |
1030 | ||
1031 | static expressionS imm_expr; | |
5f74bc13 | 1032 | static expressionS imm2_expr; |
252b5132 RH |
1033 | static expressionS offset_expr; |
1034 | ||
1035 | /* Relocs associated with imm_expr and offset_expr. */ | |
1036 | ||
f6688943 TS |
1037 | static bfd_reloc_code_real_type imm_reloc[3] |
1038 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1039 | static bfd_reloc_code_real_type offset_reloc[3] | |
1040 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1041 | |
252b5132 RH |
1042 | /* These are set by mips16_ip if an explicit extension is used. */ |
1043 | ||
b34976b6 | 1044 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1045 | |
7ed4a06a | 1046 | #ifdef OBJ_ELF |
ecb4347a DJ |
1047 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1048 | ECOFF debugging. */ | |
252b5132 RH |
1049 | |
1050 | static segT pdr_seg; | |
7ed4a06a | 1051 | #endif |
252b5132 | 1052 | |
e013f690 TS |
1053 | /* The default target format to use. */ |
1054 | ||
1055 | const char * | |
17a2f251 | 1056 | mips_target_format (void) |
e013f690 TS |
1057 | { |
1058 | switch (OUTPUT_FLAVOR) | |
1059 | { | |
1060 | case bfd_target_aout_flavour: | |
1061 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1062 | case bfd_target_ecoff_flavour: | |
1063 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1064 | case bfd_target_coff_flavour: | |
1065 | return "pe-mips"; | |
1066 | case bfd_target_elf_flavour: | |
1067 | #ifdef TE_TMIPS | |
cfe86eaa | 1068 | /* This is traditional mips. */ |
e013f690 | 1069 | return (target_big_endian |
cfe86eaa TS |
1070 | ? (HAVE_64BIT_OBJECTS |
1071 | ? "elf64-tradbigmips" | |
1072 | : (HAVE_NEWABI | |
1073 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1074 | : (HAVE_64BIT_OBJECTS | |
1075 | ? "elf64-tradlittlemips" | |
1076 | : (HAVE_NEWABI | |
1077 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1078 | #else |
1079 | return (target_big_endian | |
cfe86eaa TS |
1080 | ? (HAVE_64BIT_OBJECTS |
1081 | ? "elf64-bigmips" | |
1082 | : (HAVE_NEWABI | |
1083 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1084 | : (HAVE_64BIT_OBJECTS | |
1085 | ? "elf64-littlemips" | |
1086 | : (HAVE_NEWABI | |
1087 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1088 | #endif |
1089 | default: | |
1090 | abort (); | |
1091 | return NULL; | |
1092 | } | |
1093 | } | |
1094 | ||
156c2f8b NC |
1095 | /* This function is called once, at assembler startup time. It should |
1096 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1097 | ||
252b5132 | 1098 | void |
17a2f251 | 1099 | md_begin (void) |
252b5132 | 1100 | { |
252b5132 | 1101 | register const char *retval = NULL; |
156c2f8b | 1102 | int i = 0; |
252b5132 | 1103 | int broken = 0; |
1f25f5d3 | 1104 | |
fef14a42 | 1105 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1106 | as_warn (_("Could not set architecture and machine")); |
1107 | ||
252b5132 RH |
1108 | op_hash = hash_new (); |
1109 | ||
1110 | for (i = 0; i < NUMOPCODES;) | |
1111 | { | |
1112 | const char *name = mips_opcodes[i].name; | |
1113 | ||
17a2f251 | 1114 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1115 | if (retval != NULL) |
1116 | { | |
1117 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1118 | mips_opcodes[i].name, retval); | |
1119 | /* Probably a memory allocation problem? Give up now. */ | |
1120 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1121 | } | |
1122 | do | |
1123 | { | |
1124 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1125 | { | |
1126 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1127 | broken = 1; | |
1128 | } | |
1129 | ++i; | |
1130 | } | |
1131 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1132 | } | |
1133 | ||
1134 | mips16_op_hash = hash_new (); | |
1135 | ||
1136 | i = 0; | |
1137 | while (i < bfd_mips16_num_opcodes) | |
1138 | { | |
1139 | const char *name = mips16_opcodes[i].name; | |
1140 | ||
17a2f251 | 1141 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1142 | if (retval != NULL) |
1143 | as_fatal (_("internal: can't hash `%s': %s"), | |
1144 | mips16_opcodes[i].name, retval); | |
1145 | do | |
1146 | { | |
1147 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1148 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1149 | != mips16_opcodes[i].match)) | |
1150 | { | |
1151 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1152 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1153 | broken = 1; | |
1154 | } | |
1155 | ++i; | |
1156 | } | |
1157 | while (i < bfd_mips16_num_opcodes | |
1158 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1159 | } | |
1160 | ||
1161 | if (broken) | |
1162 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1163 | ||
1164 | /* We add all the general register names to the symbol table. This | |
1165 | helps us detect invalid uses of them. */ | |
1166 | for (i = 0; i < 32; i++) | |
1167 | { | |
1168 | char buf[5]; | |
1169 | ||
1170 | sprintf (buf, "$%d", i); | |
1171 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1172 | &zero_address_frag)); | |
1173 | } | |
76db943d TS |
1174 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1175 | &zero_address_frag)); | |
252b5132 RH |
1176 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1177 | &zero_address_frag)); | |
1178 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1179 | &zero_address_frag)); | |
1180 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1181 | &zero_address_frag)); | |
1182 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1183 | &zero_address_frag)); | |
1184 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1185 | &zero_address_frag)); | |
1186 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1187 | &zero_address_frag)); | |
85b51719 TS |
1188 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1189 | &zero_address_frag)); | |
252b5132 RH |
1190 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1191 | &zero_address_frag)); | |
1192 | ||
6047c971 AO |
1193 | /* If we don't add these register names to the symbol table, they |
1194 | may end up being added as regular symbols by operand(), and then | |
1195 | make it to the object file as undefined in case they're not | |
1196 | regarded as local symbols. They're local in o32, since `$' is a | |
1197 | local symbol prefix, but not in n32 or n64. */ | |
1198 | for (i = 0; i < 8; i++) | |
1199 | { | |
1200 | char buf[6]; | |
1201 | ||
1202 | sprintf (buf, "$fcc%i", i); | |
1203 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1204 | &zero_address_frag)); | |
1205 | } | |
1206 | ||
b34976b6 | 1207 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1208 | |
1209 | mips_gprmask = 0; | |
1210 | mips_cprmask[0] = 0; | |
1211 | mips_cprmask[1] = 0; | |
1212 | mips_cprmask[2] = 0; | |
1213 | mips_cprmask[3] = 0; | |
1214 | ||
1215 | /* set the default alignment for the text section (2**2) */ | |
1216 | record_alignment (text_section, 2); | |
1217 | ||
1218 | if (USE_GLOBAL_POINTER_OPT) | |
1219 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1220 | ||
1221 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1222 | { | |
1223 | /* On a native system, sections must be aligned to 16 byte | |
1224 | boundaries. When configured for an embedded ELF target, we | |
1225 | don't bother. */ | |
1226 | if (strcmp (TARGET_OS, "elf") != 0) | |
1227 | { | |
1228 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1229 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1230 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1231 | } | |
1232 | ||
1233 | /* Create a .reginfo section for register masks and a .mdebug | |
1234 | section for debugging information. */ | |
1235 | { | |
1236 | segT seg; | |
1237 | subsegT subseg; | |
1238 | flagword flags; | |
1239 | segT sec; | |
1240 | ||
1241 | seg = now_seg; | |
1242 | subseg = now_subseg; | |
1243 | ||
1244 | /* The ABI says this section should be loaded so that the | |
1245 | running program can access it. However, we don't load it | |
1246 | if we are configured for an embedded target */ | |
1247 | flags = SEC_READONLY | SEC_DATA; | |
1248 | if (strcmp (TARGET_OS, "elf") != 0) | |
1249 | flags |= SEC_ALLOC | SEC_LOAD; | |
1250 | ||
316f5878 | 1251 | if (mips_abi != N64_ABI) |
252b5132 RH |
1252 | { |
1253 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1254 | ||
195325d2 TS |
1255 | bfd_set_section_flags (stdoutput, sec, flags); |
1256 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1257 | |
252b5132 RH |
1258 | #ifdef OBJ_ELF |
1259 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1260 | #endif | |
1261 | } | |
1262 | else | |
1263 | { | |
1264 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1265 | .reginfo section. */ | |
1266 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1267 | bfd_set_section_flags (stdoutput, sec, flags); |
1268 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1269 | |
1270 | #ifdef OBJ_ELF | |
1271 | /* Set up the option header. */ | |
1272 | { | |
1273 | Elf_Internal_Options opthdr; | |
1274 | char *f; | |
1275 | ||
1276 | opthdr.kind = ODK_REGINFO; | |
1277 | opthdr.size = (sizeof (Elf_External_Options) | |
1278 | + sizeof (Elf64_External_RegInfo)); | |
1279 | opthdr.section = 0; | |
1280 | opthdr.info = 0; | |
1281 | f = frag_more (sizeof (Elf_External_Options)); | |
1282 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1283 | (Elf_External_Options *) f); | |
1284 | ||
1285 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1286 | } | |
1287 | #endif | |
1288 | } | |
1289 | ||
1290 | if (ECOFF_DEBUGGING) | |
1291 | { | |
1292 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1293 | (void) bfd_set_section_flags (stdoutput, sec, | |
1294 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1295 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1296 | } | |
ecb4347a | 1297 | #ifdef OBJ_ELF |
dcd410fe | 1298 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1299 | { |
1300 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1301 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1302 | SEC_READONLY | SEC_RELOC | |
1303 | | SEC_DEBUGGING); | |
1304 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1305 | } | |
252b5132 RH |
1306 | #endif |
1307 | ||
1308 | subseg_set (seg, subseg); | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | if (! ECOFF_DEBUGGING) | |
1313 | md_obj_begin (); | |
1314 | } | |
1315 | ||
1316 | void | |
17a2f251 | 1317 | md_mips_end (void) |
252b5132 RH |
1318 | { |
1319 | if (! ECOFF_DEBUGGING) | |
1320 | md_obj_end (); | |
1321 | } | |
1322 | ||
1323 | void | |
17a2f251 | 1324 | md_assemble (char *str) |
252b5132 RH |
1325 | { |
1326 | struct mips_cl_insn insn; | |
f6688943 TS |
1327 | bfd_reloc_code_real_type unused_reloc[3] |
1328 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1329 | |
1330 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1331 | imm2_expr.X_op = O_absent; |
252b5132 | 1332 | offset_expr.X_op = O_absent; |
f6688943 TS |
1333 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1334 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1335 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1336 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1337 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1338 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1339 | |
1340 | if (mips_opts.mips16) | |
1341 | mips16_ip (str, &insn); | |
1342 | else | |
1343 | { | |
1344 | mips_ip (str, &insn); | |
beae10d5 KH |
1345 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1346 | str, insn.insn_opcode)); | |
252b5132 RH |
1347 | } |
1348 | ||
1349 | if (insn_error) | |
1350 | { | |
1351 | as_bad ("%s `%s'", insn_error, str); | |
1352 | return; | |
1353 | } | |
1354 | ||
1355 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1356 | { | |
1357 | if (mips_opts.mips16) | |
1358 | mips16_macro (&insn); | |
1359 | else | |
1360 | macro (&insn); | |
1361 | } | |
1362 | else | |
1363 | { | |
1364 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1365 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1366 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1367 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1368 | else |
5e0116d5 | 1369 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1370 | } |
1371 | } | |
1372 | ||
5919d012 RS |
1373 | /* Return true if the given relocation might need a matching %lo(). |
1374 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1375 | applied to local symbols. */ | |
1376 | ||
1377 | static inline bfd_boolean | |
17a2f251 | 1378 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1379 | { |
1380 | return (reloc == BFD_RELOC_HI16_S | |
1381 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1382 | } | |
1383 | ||
1384 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1385 | relocation. */ | |
1386 | ||
1387 | static inline bfd_boolean | |
17a2f251 | 1388 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1389 | { |
1390 | return (fixp->fx_next != NULL | |
1391 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1392 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1393 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1394 | } | |
1395 | ||
252b5132 RH |
1396 | /* See whether instruction IP reads register REG. CLASS is the type |
1397 | of register. */ | |
1398 | ||
1399 | static int | |
17a2f251 TS |
1400 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1401 | enum mips_regclass class) | |
252b5132 RH |
1402 | { |
1403 | if (class == MIPS16_REG) | |
1404 | { | |
1405 | assert (mips_opts.mips16); | |
1406 | reg = mips16_to_32_reg_map[reg]; | |
1407 | class = MIPS_GR_REG; | |
1408 | } | |
1409 | ||
85b51719 TS |
1410 | /* Don't report on general register ZERO, since it never changes. */ |
1411 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1412 | return 0; |
1413 | ||
1414 | if (class == MIPS_FP_REG) | |
1415 | { | |
1416 | assert (! mips_opts.mips16); | |
1417 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1418 | This is not optimal, because it will introduce an unnecessary | |
1419 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1420 | need to distinguish reading both $f0 and $f1 or just one of | |
1421 | them. Note that we don't have to check the other way, | |
1422 | because there is no instruction that sets both $f0 and $f1 | |
1423 | and requires a delay. */ | |
1424 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1425 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1426 | == (reg &~ (unsigned) 1))) | |
1427 | return 1; | |
1428 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1429 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1430 | == (reg &~ (unsigned) 1))) | |
1431 | return 1; | |
1432 | } | |
1433 | else if (! mips_opts.mips16) | |
1434 | { | |
1435 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1436 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1437 | return 1; | |
1438 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1439 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1440 | return 1; | |
1441 | } | |
1442 | else | |
1443 | { | |
1444 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1445 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1446 | & MIPS16OP_MASK_RX)] | |
1447 | == reg)) | |
1448 | return 1; | |
1449 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1450 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1451 | & MIPS16OP_MASK_RY)] | |
1452 | == reg)) | |
1453 | return 1; | |
1454 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1455 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1456 | & MIPS16OP_MASK_MOVE32Z)] | |
1457 | == reg)) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1460 | return 1; | |
1461 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1462 | return 1; | |
1463 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1464 | return 1; | |
1465 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1466 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1467 | & MIPS16OP_MASK_REGR32) == reg) | |
1468 | return 1; | |
1469 | } | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /* This function returns true if modifying a register requires a | |
1475 | delay. */ | |
1476 | ||
1477 | static int | |
17a2f251 | 1478 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1479 | { |
1480 | unsigned long prev_pinfo; | |
1481 | ||
1482 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1483 | if (! mips_opts.noreorder | |
81912461 ILT |
1484 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1485 | && ! gpr_interlocks) | |
1486 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1487 | && ! cop_interlocks))) | |
252b5132 | 1488 | { |
81912461 ILT |
1489 | /* A load from a coprocessor or from memory. All load delays |
1490 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1491 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1492 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1493 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1494 | return 1; | |
1495 | } | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
1500 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1501 | handle them specially, such as generating jalx instructions when | |
1502 | needed. We also make them odd for the duration of the assembly, in | |
1503 | order to generate the right sort of code. We will make them even | |
1504 | in the adjust_symtab routine, while leaving them marked. This is | |
1505 | convenient for the debugger and the disassembler. The linker knows | |
1506 | to make them odd again. */ | |
1507 | ||
1508 | static void | |
17a2f251 | 1509 | mips16_mark_labels (void) |
252b5132 RH |
1510 | { |
1511 | if (mips_opts.mips16) | |
1512 | { | |
1513 | struct insn_label_list *l; | |
98aa84af | 1514 | valueT val; |
252b5132 RH |
1515 | |
1516 | for (l = insn_labels; l != NULL; l = l->next) | |
1517 | { | |
1518 | #ifdef OBJ_ELF | |
1519 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1520 | S_SET_OTHER (l->label, STO_MIPS16); | |
1521 | #endif | |
98aa84af AM |
1522 | val = S_GET_VALUE (l->label); |
1523 | if ((val & 1) == 0) | |
1524 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1525 | } |
1526 | } | |
1527 | } | |
1528 | ||
1529 | /* Output an instruction. PLACE is where to put the instruction; if | |
1530 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1531 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1532 | used with RELOC_TYPE. */ | |
1533 | ||
1534 | static void | |
17a2f251 TS |
1535 | append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr, |
1536 | bfd_reloc_code_real_type *reloc_type) | |
252b5132 RH |
1537 | { |
1538 | register unsigned long prev_pinfo, pinfo; | |
1539 | char *f; | |
f6688943 | 1540 | fixS *fixp[3]; |
252b5132 | 1541 | int nops = 0; |
f5040a92 | 1542 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1543 | |
1544 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1545 | mips16_mark_labels (); |
252b5132 RH |
1546 | |
1547 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1548 | pinfo = ip->insn_mo->pinfo; | |
1549 | ||
1550 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1551 | { | |
1552 | int prev_prev_nop; | |
1553 | ||
1554 | /* If the previous insn required any delay slots, see if we need | |
1555 | to insert a NOP or two. There are eight kinds of possible | |
1556 | hazards, of which an instruction can have at most one type. | |
1557 | (1) a load from memory delay | |
1558 | (2) a load from a coprocessor delay | |
1559 | (3) an unconditional branch delay | |
1560 | (4) a conditional branch delay | |
1561 | (5) a move to coprocessor register delay | |
1562 | (6) a load coprocessor register from memory delay | |
1563 | (7) a coprocessor condition code delay | |
1564 | (8) a HI/LO special register delay | |
1565 | ||
1566 | There are a lot of optimizations we could do that we don't. | |
1567 | In particular, we do not, in general, reorder instructions. | |
1568 | If you use gcc with optimization, it will reorder | |
1569 | instructions and generally do much more optimization then we | |
1570 | do here; repeating all that work in the assembler would only | |
1571 | benefit hand written assembly code, and does not seem worth | |
1572 | it. */ | |
1573 | ||
1574 | /* This is how a NOP is emitted. */ | |
1575 | #define emit_nop() \ | |
1576 | (mips_opts.mips16 \ | |
1577 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1578 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1579 | ||
1580 | /* The previous insn might require a delay slot, depending upon | |
1581 | the contents of the current insn. */ | |
1582 | if (! mips_opts.mips16 | |
81912461 ILT |
1583 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1584 | && ! gpr_interlocks) | |
1585 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1586 | && ! cop_interlocks))) | |
252b5132 RH |
1587 | { |
1588 | /* A load from a coprocessor or from memory. All load | |
1589 | delays delay the use of general register rt for one | |
81912461 | 1590 | instruction. */ |
beae10d5 | 1591 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1592 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1593 | if (mips_optimize == 0 | |
1594 | || insn_uses_reg (ip, | |
1595 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1596 | & OP_MASK_RT), | |
1597 | MIPS_GR_REG)) | |
1598 | ++nops; | |
1599 | } | |
1600 | else if (! mips_opts.mips16 | |
252b5132 | 1601 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1602 | && ! cop_interlocks) |
81912461 ILT |
1603 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1604 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1605 | { |
1606 | /* A generic coprocessor delay. The previous instruction | |
1607 | modified a coprocessor general or control register. If | |
1608 | it modified a control register, we need to avoid any | |
1609 | coprocessor instruction (this is probably not always | |
1610 | required, but it sometimes is). If it modified a general | |
1611 | register, we avoid using that register. | |
1612 | ||
252b5132 RH |
1613 | This case is not handled very well. There is no special |
1614 | knowledge of CP0 handling, and the coprocessors other | |
1615 | than the floating point unit are not distinguished at | |
1616 | all. */ | |
1617 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1618 | Need to modify this to include knowledge about |
252b5132 RH |
1619 | user specified delays! */ |
1620 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1621 | { | |
1622 | if (mips_optimize == 0 | |
1623 | || insn_uses_reg (ip, | |
1624 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1625 | & OP_MASK_FT), | |
1626 | MIPS_FP_REG)) | |
1627 | ++nops; | |
1628 | } | |
1629 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1630 | { | |
1631 | if (mips_optimize == 0 | |
1632 | || insn_uses_reg (ip, | |
1633 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1634 | & OP_MASK_FS), | |
1635 | MIPS_FP_REG)) | |
1636 | ++nops; | |
1637 | } | |
1638 | else | |
1639 | { | |
1640 | /* We don't know exactly what the previous instruction | |
1641 | does. If the current instruction uses a coprocessor | |
1642 | register, we must insert a NOP. If previous | |
1643 | instruction may set the condition codes, and the | |
1644 | current instruction uses them, we must insert two | |
1645 | NOPS. */ | |
bdaaa2e1 | 1646 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1647 | if (mips_optimize == 0 |
1648 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1649 | && (pinfo & INSN_READ_COND_CODE))) | |
1650 | nops += 2; | |
1651 | else if (pinfo & INSN_COP) | |
1652 | ++nops; | |
1653 | } | |
1654 | } | |
1655 | else if (! mips_opts.mips16 | |
252b5132 RH |
1656 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1657 | && ! cop_interlocks) | |
1658 | { | |
1659 | /* The previous instruction sets the coprocessor condition | |
1660 | codes, but does not require a general coprocessor delay | |
1661 | (this means it is a floating point comparison | |
1662 | instruction). If this instruction uses the condition | |
1663 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1664 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1665 | if (mips_optimize == 0 |
1666 | || (pinfo & INSN_READ_COND_CODE)) | |
1667 | ++nops; | |
1668 | } | |
6b76fefe CM |
1669 | |
1670 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1671 | previous insn was an mfhi/mflo and the current insn | |
1672 | reads the register that the mfhi/mflo wrote to, then | |
1673 | insert two nops. */ | |
1674 | ||
1675 | else if (mips_7000_hilo_fix | |
1676 | && MF_HILO_INSN (prev_pinfo) | |
1677 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1678 | & OP_MASK_RD), |
1679 | MIPS_GR_REG)) | |
6b76fefe CM |
1680 | { |
1681 | nops += 2; | |
1682 | } | |
1683 | ||
1684 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1685 | 2nd previous insn was an mfhi/mflo and the current insn | |
1686 | reads the register that the mfhi/mflo wrote to, then | |
1687 | insert one nop. */ | |
1688 | ||
1689 | else if (mips_7000_hilo_fix | |
1690 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1691 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1692 | & OP_MASK_RD), | |
1693 | MIPS_GR_REG)) | |
bdaaa2e1 | 1694 | |
6b76fefe | 1695 | { |
f9419b05 | 1696 | ++nops; |
6b76fefe | 1697 | } |
bdaaa2e1 | 1698 | |
252b5132 RH |
1699 | else if (prev_pinfo & INSN_READ_LO) |
1700 | { | |
1701 | /* The previous instruction reads the LO register; if the | |
1702 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1703 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1704 | Also the tx39's multiply instructions can be executed |
1705 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1706 | though the tx39's divide insns still do require the |
1707 | delay. */ | |
252b5132 | 1708 | if (! (hilo_interlocks |
ec68c924 | 1709 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1710 | && (mips_optimize == 0 |
1711 | || (pinfo & INSN_WRITE_LO))) | |
1712 | nops += 2; | |
1713 | /* Most mips16 branch insns don't have a delay slot. | |
1714 | If a read from LO is immediately followed by a branch | |
1715 | to a write to LO we have a read followed by a write | |
1716 | less than 2 insns away. We assume the target of | |
1717 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1718 | between a read and an immediately following branch. */ |
252b5132 RH |
1719 | else if (mips_opts.mips16 |
1720 | && (mips_optimize == 0 | |
1721 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1722 | ++nops; |
252b5132 RH |
1723 | } |
1724 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1725 | { | |
1726 | /* The previous instruction reads the HI register; if the | |
1727 | current instruction writes to the HI register, we must | |
1728 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1729 | Also the note tx39's multiply above. */ |
252b5132 | 1730 | if (! (hilo_interlocks |
ec68c924 | 1731 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1732 | && (mips_optimize == 0 |
1733 | || (pinfo & INSN_WRITE_HI))) | |
1734 | nops += 2; | |
1735 | /* Most mips16 branch insns don't have a delay slot. | |
1736 | If a read from HI is immediately followed by a branch | |
1737 | to a write to HI we have a read followed by a write | |
1738 | less than 2 insns away. We assume the target of | |
1739 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1740 | between a read and an immediately following branch. */ |
252b5132 RH |
1741 | else if (mips_opts.mips16 |
1742 | && (mips_optimize == 0 | |
1743 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1744 | ++nops; |
252b5132 RH |
1745 | } |
1746 | ||
1747 | /* If the previous instruction was in a noreorder section, then | |
1748 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1749 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1750 | if (prev_insn_unreordered) |
1751 | nops = 0; | |
1752 | ||
1753 | /* There are two cases which require two intervening | |
1754 | instructions: 1) setting the condition codes using a move to | |
1755 | coprocessor instruction which requires a general coprocessor | |
1756 | delay and then reading the condition codes 2) reading the HI | |
1757 | or LO register and then writing to it (except on processors | |
1758 | which have interlocks). If we are not already emitting a NOP | |
1759 | instruction, we must check for these cases compared to the | |
1760 | instruction previous to the previous instruction. */ | |
1761 | if ((! mips_opts.mips16 | |
252b5132 RH |
1762 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1763 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1764 | && (pinfo & INSN_READ_COND_CODE) | |
1765 | && ! cop_interlocks) | |
1766 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1767 | && (pinfo & INSN_WRITE_LO) | |
1768 | && ! (hilo_interlocks | |
ec68c924 | 1769 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1770 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1771 | && (pinfo & INSN_WRITE_HI) | |
1772 | && ! (hilo_interlocks | |
ec68c924 | 1773 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1774 | prev_prev_nop = 1; |
1775 | else | |
1776 | prev_prev_nop = 0; | |
1777 | ||
1778 | if (prev_prev_insn_unreordered) | |
1779 | prev_prev_nop = 0; | |
1780 | ||
1781 | if (prev_prev_nop && nops == 0) | |
1782 | ++nops; | |
1783 | ||
60b63b72 RS |
1784 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1785 | { | |
1786 | /* We're out of bits in pinfo, so we must resort to string | |
1787 | ops here. Shortcuts are selected based on opcodes being | |
1788 | limited to the VR4122 instruction set. */ | |
1789 | int min_nops = 0; | |
1790 | const char *pn = prev_insn.insn_mo->name; | |
1791 | const char *tn = ip->insn_mo->name; | |
1792 | if (strncmp(pn, "macc", 4) == 0 | |
1793 | || strncmp(pn, "dmacc", 5) == 0) | |
1794 | { | |
1795 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1796 | if (strstr (tn, "div")) | |
1797 | { | |
1798 | min_nops = 1; | |
1799 | } | |
1800 | ||
1801 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1802 | if (pn[0] == 'd' /* dmacc */ | |
1803 | && (strncmp(tn, "dmult", 5) == 0 | |
1804 | || strncmp(tn, "dmacc", 5) == 0)) | |
1805 | { | |
1806 | min_nops = 1; | |
1807 | } | |
1808 | ||
1809 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1810 | if (strcmp (tn, "mtlo") == 0 | |
1811 | || strcmp (tn, "mthi") == 0) | |
1812 | { | |
1813 | min_nops = 1; | |
1814 | } | |
1815 | ||
1816 | } | |
1817 | else if (strncmp(pn, "dmult", 5) == 0 | |
1818 | && (strncmp(tn, "dmult", 5) == 0 | |
1819 | || strncmp(tn, "dmacc", 5) == 0)) | |
1820 | { | |
1821 | /* Here is the rest of errata 23. */ | |
1822 | min_nops = 1; | |
1823 | } | |
1824 | if (nops < min_nops) | |
1825 | nops = min_nops; | |
1826 | } | |
1827 | ||
252b5132 RH |
1828 | /* If we are being given a nop instruction, don't bother with |
1829 | one of the nops we would otherwise output. This will only | |
1830 | happen when a nop instruction is used with mips_optimize set | |
1831 | to 0. */ | |
1832 | if (nops > 0 | |
1833 | && ! mips_opts.noreorder | |
156c2f8b | 1834 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1835 | --nops; |
1836 | ||
1837 | /* Now emit the right number of NOP instructions. */ | |
1838 | if (nops > 0 && ! mips_opts.noreorder) | |
1839 | { | |
1840 | fragS *old_frag; | |
1841 | unsigned long old_frag_offset; | |
1842 | int i; | |
1843 | struct insn_label_list *l; | |
1844 | ||
1845 | old_frag = frag_now; | |
1846 | old_frag_offset = frag_now_fix (); | |
1847 | ||
1848 | for (i = 0; i < nops; i++) | |
1849 | emit_nop (); | |
1850 | ||
1851 | if (listing) | |
1852 | { | |
1853 | listing_prev_line (); | |
1854 | /* We may be at the start of a variant frag. In case we | |
1855 | are, make sure there is enough space for the frag | |
1856 | after the frags created by listing_prev_line. The | |
1857 | argument to frag_grow here must be at least as large | |
1858 | as the argument to all other calls to frag_grow in | |
1859 | this file. We don't have to worry about being in the | |
1860 | middle of a variant frag, because the variants insert | |
1861 | all needed nop instructions themselves. */ | |
1862 | frag_grow (40); | |
1863 | } | |
1864 | ||
1865 | for (l = insn_labels; l != NULL; l = l->next) | |
1866 | { | |
98aa84af AM |
1867 | valueT val; |
1868 | ||
252b5132 | 1869 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1870 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1871 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1872 | /* mips16 text labels are stored as odd. */ |
1873 | if (mips_opts.mips16) | |
f9419b05 | 1874 | ++val; |
98aa84af | 1875 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1876 | } |
1877 | ||
1878 | #ifndef NO_ECOFF_DEBUGGING | |
1879 | if (ECOFF_DEBUGGING) | |
1880 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1881 | #endif | |
1882 | } | |
1883 | else if (prev_nop_frag != NULL) | |
1884 | { | |
1885 | /* We have a frag holding nops we may be able to remove. If | |
1886 | we don't need any nops, we can decrease the size of | |
1887 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1888 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1889 | if (prev_nop_frag_since == 0) |
1890 | { | |
1891 | if (nops == 0) | |
1892 | { | |
1893 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1894 | --prev_nop_frag_holds; | |
1895 | } | |
1896 | else | |
1897 | prev_nop_frag_required += nops; | |
1898 | } | |
1899 | else | |
1900 | { | |
1901 | if (prev_prev_nop == 0) | |
1902 | { | |
1903 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1904 | --prev_nop_frag_holds; | |
1905 | } | |
1906 | else | |
1907 | ++prev_nop_frag_required; | |
1908 | } | |
1909 | ||
1910 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1911 | prev_nop_frag = NULL; | |
1912 | ||
1913 | ++prev_nop_frag_since; | |
1914 | ||
1915 | /* Sanity check: by the time we reach the second instruction | |
1916 | after prev_nop_frag, we should have used up all the nops | |
1917 | one way or another. */ | |
1918 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1919 | } | |
1920 | } | |
1921 | ||
4a6a3df4 AO |
1922 | if (place == NULL |
1923 | && address_expr | |
0b25d3e6 | 1924 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
1925 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
1926 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
1927 | && mips_relax_branch | |
1928 | /* Don't try branch relaxation within .set nomacro, or within | |
1929 | .set noat if we use $at for PIC computations. If it turns | |
1930 | out that the branch was out-of-range, we'll get an error. */ | |
1931 | && !mips_opts.warn_about_macros | |
1932 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
1933 | && !mips_opts.mips16) | |
1934 | { | |
1935 | f = frag_var (rs_machine_dependent, | |
1936 | relaxed_branch_length | |
1937 | (NULL, NULL, | |
1938 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
1939 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
1940 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 1941 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
1942 | pinfo & INSN_COND_BRANCH_LIKELY, |
1943 | pinfo & INSN_WRITE_GPR_31, | |
1944 | 0), | |
1945 | address_expr->X_add_symbol, | |
1946 | address_expr->X_add_number, | |
1947 | 0); | |
1948 | *reloc_type = BFD_RELOC_UNUSED; | |
1949 | } | |
1950 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
1951 | { |
1952 | /* We need to set up a variant frag. */ | |
1953 | assert (mips_opts.mips16 && address_expr != NULL); | |
1954 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1955 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1956 | mips16_small, mips16_ext, |
1957 | (prev_pinfo | |
1958 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1959 | (*prev_insn_reloc_type |
252b5132 | 1960 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 1961 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
1962 | } |
1963 | else if (place != NULL) | |
1964 | f = place; | |
1965 | else if (mips_opts.mips16 | |
1966 | && ! ip->use_extend | |
f6688943 | 1967 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1968 | { |
1969 | /* Make sure there is enough room to swap this instruction with | |
1970 | a following jump instruction. */ | |
1971 | frag_grow (6); | |
1972 | f = frag_more (2); | |
1973 | } | |
1974 | else | |
1975 | { | |
1976 | if (mips_opts.mips16 | |
1977 | && mips_opts.noreorder | |
1978 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1979 | as_warn (_("extended instruction in delay slot")); | |
1980 | ||
1981 | f = frag_more (4); | |
1982 | } | |
1983 | ||
f6688943 TS |
1984 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1985 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1986 | { |
1987 | if (address_expr->X_op == O_constant) | |
1988 | { | |
4db1a35d | 1989 | valueT tmp; |
f6688943 TS |
1990 | |
1991 | switch (*reloc_type) | |
252b5132 RH |
1992 | { |
1993 | case BFD_RELOC_32: | |
1994 | ip->insn_opcode |= address_expr->X_add_number; | |
1995 | break; | |
1996 | ||
f6688943 | 1997 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
1998 | tmp = (address_expr->X_add_number |
1999 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2000 | tmp >>= 16; |
2001 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2002 | break; | |
2003 | ||
2004 | case BFD_RELOC_MIPS_HIGHER: | |
2005 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2006 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2007 | break; | |
2008 | ||
2009 | case BFD_RELOC_HI16_S: | |
2010 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2011 | >> 16) & 0xffff; | |
2012 | break; | |
2013 | ||
2014 | case BFD_RELOC_HI16: | |
2015 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2016 | break; | |
2017 | ||
252b5132 | 2018 | case BFD_RELOC_LO16: |
ed6fb7bd | 2019 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2020 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2021 | break; | |
2022 | ||
2023 | case BFD_RELOC_MIPS_JMP: | |
2024 | if ((address_expr->X_add_number & 3) != 0) | |
2025 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2026 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2027 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2028 | as_bad (_("jump address range overflow (0x%lx)"), |
2029 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2030 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2031 | break; | |
2032 | ||
2033 | case BFD_RELOC_MIPS16_JMP: | |
2034 | if ((address_expr->X_add_number & 3) != 0) | |
2035 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2036 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2037 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2038 | as_bad (_("jump address range overflow (0x%lx)"), |
2039 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2040 | ip->insn_opcode |= |
2041 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2042 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2043 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2044 | break; | |
2045 | ||
252b5132 RH |
2046 | case BFD_RELOC_16_PCREL_S2: |
2047 | goto need_reloc; | |
2048 | ||
2049 | default: | |
2050 | internalError (); | |
2051 | } | |
2052 | } | |
2053 | else | |
2054 | { | |
2055 | need_reloc: | |
f6688943 | 2056 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2057 | if (place == NULL) |
2058 | { | |
34ce925e RS |
2059 | reloc_howto_type *howto; |
2060 | int i; | |
2061 | ||
2062 | /* In a compound relocation, it is the final (outermost) | |
2063 | operator that determines the relocated field. */ | |
2064 | for (i = 1; i < 3; i++) | |
2065 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2066 | break; | |
2067 | ||
2068 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); | |
a105a300 TS |
2069 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
2070 | bfd_get_reloc_size(howto), | |
f6688943 | 2071 | address_expr, |
a105a300 | 2072 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2073 | reloc_type[0]); |
2074 | ||
b6ff326e | 2075 | /* These relocations can have an addend that won't fit in |
f6688943 | 2076 | 4 octets for 64bit assembly. */ |
a105a300 TS |
2077 | if (HAVE_64BIT_GPRS |
2078 | && ! howto->partial_inplace | |
2079 | && (reloc_type[0] == BFD_RELOC_16 | |
2080 | || reloc_type[0] == BFD_RELOC_32 | |
2081 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2082 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2083 | || reloc_type[0] == BFD_RELOC_LO16 | |
2084 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2085 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2086 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2087 | || reloc_type[0] == BFD_RELOC_64 | |
2088 | || reloc_type[0] == BFD_RELOC_CTOR | |
2089 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2090 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2091 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2092 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2093 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2094 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2095 | fixp[0]->fx_no_overflow = 1; |
2096 | ||
5919d012 | 2097 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2098 | { |
2099 | struct mips_hi_fixup *hi_fixup; | |
2100 | ||
5919d012 RS |
2101 | /* Reuse the last entry if it already has a matching %lo. */ |
2102 | hi_fixup = mips_hi_fixup_list; | |
2103 | if (hi_fixup == 0 | |
2104 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2105 | { | |
2106 | hi_fixup = ((struct mips_hi_fixup *) | |
2107 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2108 | hi_fixup->next = mips_hi_fixup_list; | |
2109 | mips_hi_fixup_list = hi_fixup; | |
2110 | } | |
f6688943 | 2111 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2112 | hi_fixup->seg = now_seg; |
252b5132 | 2113 | } |
f6688943 | 2114 | |
34ce925e RS |
2115 | /* Add fixups for the second and third relocations, if given. |
2116 | Note that the ABI allows the second relocation to be | |
2117 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2118 | moment we only use RSS_UNDEF, but we could add support | |
2119 | for the others if it ever becomes necessary. */ | |
2120 | for (i = 1; i < 3; i++) | |
2121 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2122 | { | |
2123 | address_expr->X_op = O_absent; | |
2124 | address_expr->X_add_symbol = 0; | |
2125 | address_expr->X_add_number = 0; | |
2126 | ||
2127 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, | |
2128 | fixp[0]->fx_size, address_expr, | |
2129 | FALSE, reloc_type[i]); | |
2130 | } | |
252b5132 RH |
2131 | } |
2132 | } | |
2133 | } | |
2134 | ||
2135 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2136 | { |
2137 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2138 | #ifdef OBJ_ELF | |
2139 | dwarf2_emit_insn (4); | |
2140 | #endif | |
2141 | } | |
f6688943 | 2142 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2143 | { |
2144 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2145 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2146 | #ifdef OBJ_ELF |
2147 | dwarf2_emit_insn (4); | |
2148 | #endif | |
252b5132 RH |
2149 | } |
2150 | else | |
2151 | { | |
2152 | if (ip->use_extend) | |
2153 | { | |
2154 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2155 | f += 2; | |
2156 | } | |
2157 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2158 | #ifdef OBJ_ELF |
2159 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2160 | #endif | |
252b5132 RH |
2161 | } |
2162 | ||
2163 | /* Update the register mask information. */ | |
2164 | if (! mips_opts.mips16) | |
2165 | { | |
2166 | if (pinfo & INSN_WRITE_GPR_D) | |
2167 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2168 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2169 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2170 | if (pinfo & INSN_READ_GPR_S) | |
2171 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2172 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2173 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2174 | if (pinfo & INSN_WRITE_FPR_D) |
2175 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2176 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2177 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2178 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2179 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2180 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2181 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2182 | if (pinfo & INSN_COP) | |
2183 | { | |
bdaaa2e1 KH |
2184 | /* We don't keep enough information to sort these cases out. |
2185 | The itbl support does keep this information however, although | |
2186 | we currently don't support itbl fprmats as part of the cop | |
2187 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2188 | } |
2189 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2190 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2191 | } |
2192 | else | |
2193 | { | |
2194 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2195 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2196 | & MIPS16OP_MASK_RX); | |
2197 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2198 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2199 | & MIPS16OP_MASK_RY); | |
2200 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2201 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2202 | & MIPS16OP_MASK_RZ); | |
2203 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2204 | mips_gprmask |= 1 << TREG; | |
2205 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2206 | mips_gprmask |= 1 << SP; | |
2207 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2208 | mips_gprmask |= 1 << RA; | |
2209 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2210 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2211 | if (pinfo & MIPS16_INSN_READ_Z) | |
2212 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2213 | & MIPS16OP_MASK_MOVE32Z); | |
2214 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2215 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2216 | & MIPS16OP_MASK_REGR32); | |
2217 | } | |
2218 | ||
2219 | if (place == NULL && ! mips_opts.noreorder) | |
2220 | { | |
2221 | /* Filling the branch delay slot is more complex. We try to | |
2222 | switch the branch with the previous instruction, which we can | |
2223 | do if the previous instruction does not set up a condition | |
2224 | that the branch tests and if the branch is not itself the | |
2225 | target of any branch. */ | |
2226 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2227 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2228 | { | |
2229 | if (mips_optimize < 2 | |
2230 | /* If we have seen .set volatile or .set nomove, don't | |
2231 | optimize. */ | |
2232 | || mips_opts.nomove != 0 | |
2233 | /* If we had to emit any NOP instructions, then we | |
2234 | already know we can not swap. */ | |
2235 | || nops != 0 | |
2236 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2237 | swap. */ |
252b5132 RH |
2238 | || ! prev_insn_valid |
2239 | /* If the previous insn is already in a branch delay | |
2240 | slot, then we can not swap. */ | |
2241 | || prev_insn_is_delay_slot | |
2242 | /* If the previous previous insn was in a .set | |
2243 | noreorder, we can't swap. Actually, the MIPS | |
2244 | assembler will swap in this situation. However, gcc | |
2245 | configured -with-gnu-as will generate code like | |
2246 | .set noreorder | |
2247 | lw $4,XXX | |
2248 | .set reorder | |
2249 | INSN | |
2250 | bne $4,$0,foo | |
2251 | in which we can not swap the bne and INSN. If gcc is | |
2252 | not configured -with-gnu-as, it does not output the | |
2253 | .set pseudo-ops. We don't have to check | |
2254 | prev_insn_unreordered, because prev_insn_valid will | |
2255 | be 0 in that case. We don't want to use | |
2256 | prev_prev_insn_valid, because we do want to be able | |
2257 | to swap at the start of a function. */ | |
2258 | || prev_prev_insn_unreordered | |
2259 | /* If the branch is itself the target of a branch, we | |
2260 | can not swap. We cheat on this; all we check for is | |
2261 | whether there is a label on this instruction. If | |
2262 | there are any branches to anything other than a | |
2263 | label, users must use .set noreorder. */ | |
2264 | || insn_labels != NULL | |
2265 | /* If the previous instruction is in a variant frag, we | |
2266 | can not do the swap. This does not apply to the | |
2267 | mips16, which uses variant frags for different | |
2268 | purposes. */ | |
2269 | || (! mips_opts.mips16 | |
2270 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2271 | /* If the branch reads the condition codes, we don't | |
2272 | even try to swap, because in the sequence | |
2273 | ctc1 $X,$31 | |
2274 | INSN | |
2275 | INSN | |
2276 | bc1t LABEL | |
2277 | we can not swap, and I don't feel like handling that | |
2278 | case. */ | |
2279 | || (! mips_opts.mips16 | |
81912461 ILT |
2280 | && (pinfo & INSN_READ_COND_CODE) |
2281 | && ! cop_interlocks) | |
252b5132 | 2282 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2283 | delay slot, because the target of the branch might |
252b5132 RH |
2284 | interfere with that instruction. */ |
2285 | || (! mips_opts.mips16 | |
252b5132 | 2286 | && (prev_pinfo |
bdaaa2e1 | 2287 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2288 | & (INSN_LOAD_COPROC_DELAY |
2289 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2290 | | INSN_WRITE_COND_CODE)) |
2291 | && ! cop_interlocks) | |
252b5132 | 2292 | || (! (hilo_interlocks |
ec68c924 | 2293 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2294 | && (prev_pinfo |
2295 | & (INSN_READ_LO | |
2296 | | INSN_READ_HI))) | |
2297 | || (! mips_opts.mips16 | |
81912461 ILT |
2298 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2299 | && ! gpr_interlocks) | |
252b5132 | 2300 | || (! mips_opts.mips16 |
bdaaa2e1 | 2301 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2302 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2303 | && ! cop_mem_interlocks) | |
252b5132 RH |
2304 | /* We can not swap with a branch instruction. */ |
2305 | || (prev_pinfo | |
2306 | & (INSN_UNCOND_BRANCH_DELAY | |
2307 | | INSN_COND_BRANCH_DELAY | |
2308 | | INSN_COND_BRANCH_LIKELY)) | |
2309 | /* We do not swap with a trap instruction, since it | |
2310 | complicates trap handlers to have the trap | |
2311 | instruction be in a delay slot. */ | |
2312 | || (prev_pinfo & INSN_TRAP) | |
2313 | /* If the branch reads a register that the previous | |
2314 | instruction sets, we can not swap. */ | |
2315 | || (! mips_opts.mips16 | |
2316 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2317 | && insn_uses_reg (ip, | |
2318 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2319 | & OP_MASK_RT), | |
2320 | MIPS_GR_REG)) | |
2321 | || (! mips_opts.mips16 | |
2322 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2323 | && insn_uses_reg (ip, | |
2324 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2325 | & OP_MASK_RD), | |
2326 | MIPS_GR_REG)) | |
2327 | || (mips_opts.mips16 | |
2328 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2329 | && insn_uses_reg (ip, | |
2330 | ((prev_insn.insn_opcode | |
2331 | >> MIPS16OP_SH_RX) | |
2332 | & MIPS16OP_MASK_RX), | |
2333 | MIPS16_REG)) | |
2334 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2335 | && insn_uses_reg (ip, | |
2336 | ((prev_insn.insn_opcode | |
2337 | >> MIPS16OP_SH_RY) | |
2338 | & MIPS16OP_MASK_RY), | |
2339 | MIPS16_REG)) | |
2340 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2341 | && insn_uses_reg (ip, | |
2342 | ((prev_insn.insn_opcode | |
2343 | >> MIPS16OP_SH_RZ) | |
2344 | & MIPS16OP_MASK_RZ), | |
2345 | MIPS16_REG)) | |
2346 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2347 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2348 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2349 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2350 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2351 | && insn_uses_reg (ip, | |
2352 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2353 | insn_opcode), | |
2354 | MIPS_GR_REG)))) | |
2355 | /* If the branch writes a register that the previous | |
2356 | instruction sets, we can not swap (we know that | |
2357 | branches write only to RD or to $31). */ | |
2358 | || (! mips_opts.mips16 | |
2359 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2360 | && (((pinfo & INSN_WRITE_GPR_D) | |
2361 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2362 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2363 | || ((pinfo & INSN_WRITE_GPR_31) | |
2364 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2365 | & OP_MASK_RT) | |
f9419b05 | 2366 | == RA)))) |
252b5132 RH |
2367 | || (! mips_opts.mips16 |
2368 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2369 | && (((pinfo & INSN_WRITE_GPR_D) | |
2370 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2371 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2372 | || ((pinfo & INSN_WRITE_GPR_31) | |
2373 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2374 | & OP_MASK_RD) | |
f9419b05 | 2375 | == RA)))) |
252b5132 RH |
2376 | || (mips_opts.mips16 |
2377 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2378 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2379 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2380 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2381 | == RA)))) | |
2382 | /* If the branch writes a register that the previous | |
2383 | instruction reads, we can not swap (we know that | |
2384 | branches only write to RD or to $31). */ | |
2385 | || (! mips_opts.mips16 | |
2386 | && (pinfo & INSN_WRITE_GPR_D) | |
2387 | && insn_uses_reg (&prev_insn, | |
2388 | ((ip->insn_opcode >> OP_SH_RD) | |
2389 | & OP_MASK_RD), | |
2390 | MIPS_GR_REG)) | |
2391 | || (! mips_opts.mips16 | |
2392 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2393 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2394 | || (mips_opts.mips16 |
2395 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2396 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2397 | /* If we are generating embedded PIC code, the branch | |
2398 | might be expanded into a sequence which uses $at, so | |
2399 | we can't swap with an instruction which reads it. */ | |
2400 | || (mips_pic == EMBEDDED_PIC | |
2401 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2402 | /* If the previous previous instruction has a load | |
2403 | delay, and sets a register that the branch reads, we | |
2404 | can not swap. */ | |
2405 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2406 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2407 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2408 | && ! cop_interlocks) | |
2409 | || ((prev_prev_insn.insn_mo->pinfo | |
2410 | & INSN_LOAD_MEMORY_DELAY) | |
2411 | && ! gpr_interlocks)) | |
252b5132 RH |
2412 | && insn_uses_reg (ip, |
2413 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2414 | & OP_MASK_RT), | |
2415 | MIPS_GR_REG)) | |
2416 | /* If one instruction sets a condition code and the | |
2417 | other one uses a condition code, we can not swap. */ | |
2418 | || ((pinfo & INSN_READ_COND_CODE) | |
2419 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2420 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2421 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2422 | /* If the previous instruction uses the PC, we can not | |
2423 | swap. */ | |
2424 | || (mips_opts.mips16 | |
2425 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2426 | /* If the previous instruction was extended, we can not | |
2427 | swap. */ | |
2428 | || (mips_opts.mips16 && prev_insn_extended) | |
2429 | /* If the previous instruction had a fixup in mips16 | |
2430 | mode, we can not swap. This normally means that the | |
2431 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2432 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2433 | /* If the previous instruction is a sync, sync.l, or |
2434 | sync.p, we can not swap. */ | |
f173e82e | 2435 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2436 | { |
2437 | /* We could do even better for unconditional branches to | |
2438 | portions of this object file; we could pick up the | |
2439 | instruction at the destination, put it in the delay | |
2440 | slot, and bump the destination address. */ | |
2441 | emit_nop (); | |
2442 | /* Update the previous insn information. */ | |
2443 | prev_prev_insn = *ip; | |
2444 | prev_insn.insn_mo = &dummy_opcode; | |
2445 | } | |
2446 | else | |
2447 | { | |
2448 | /* It looks like we can actually do the swap. */ | |
2449 | if (! mips_opts.mips16) | |
2450 | { | |
2451 | char *prev_f; | |
2452 | char temp[4]; | |
2453 | ||
2454 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2455 | memcpy (temp, prev_f, 4); | |
2456 | memcpy (prev_f, f, 4); | |
2457 | memcpy (f, temp, 4); | |
f6688943 TS |
2458 | if (prev_insn_fixp[0]) |
2459 | { | |
2460 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2461 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2462 | } | |
2463 | if (prev_insn_fixp[1]) | |
2464 | { | |
2465 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2466 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2467 | } | |
2468 | if (prev_insn_fixp[2]) | |
252b5132 | 2469 | { |
f6688943 TS |
2470 | prev_insn_fixp[2]->fx_frag = frag_now; |
2471 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2472 | } |
f5040a92 AO |
2473 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2474 | && prev_insn_frag != frag_now | |
2475 | && (prev_insn_fixp[0]->fx_r_type | |
2476 | == BFD_RELOC_MIPS_GOT_DISP | |
2477 | || (prev_insn_fixp[0]->fx_r_type | |
2478 | == BFD_RELOC_MIPS_CALL16))) | |
2479 | { | |
2480 | /* To avoid confusion in tc_gen_reloc, we must | |
2481 | ensure that this does not become a variant | |
2482 | frag. */ | |
2483 | force_new_frag = TRUE; | |
2484 | } | |
f6688943 | 2485 | if (fixp[0]) |
252b5132 | 2486 | { |
f6688943 TS |
2487 | fixp[0]->fx_frag = prev_insn_frag; |
2488 | fixp[0]->fx_where = prev_insn_where; | |
2489 | } | |
2490 | if (fixp[1]) | |
2491 | { | |
2492 | fixp[1]->fx_frag = prev_insn_frag; | |
2493 | fixp[1]->fx_where = prev_insn_where; | |
2494 | } | |
2495 | if (fixp[2]) | |
2496 | { | |
2497 | fixp[2]->fx_frag = prev_insn_frag; | |
2498 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2499 | } |
2500 | } | |
2501 | else | |
2502 | { | |
2503 | char *prev_f; | |
2504 | char temp[2]; | |
2505 | ||
f6688943 TS |
2506 | assert (prev_insn_fixp[0] == NULL); |
2507 | assert (prev_insn_fixp[1] == NULL); | |
2508 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2509 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2510 | memcpy (temp, prev_f, 2); | |
2511 | memcpy (prev_f, f, 2); | |
f6688943 | 2512 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2513 | { |
f6688943 | 2514 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2515 | memcpy (f, temp, 2); |
2516 | } | |
2517 | else | |
2518 | { | |
2519 | memcpy (f, f + 2, 2); | |
2520 | memcpy (f + 2, temp, 2); | |
2521 | } | |
f6688943 TS |
2522 | if (fixp[0]) |
2523 | { | |
2524 | fixp[0]->fx_frag = prev_insn_frag; | |
2525 | fixp[0]->fx_where = prev_insn_where; | |
2526 | } | |
2527 | if (fixp[1]) | |
2528 | { | |
2529 | fixp[1]->fx_frag = prev_insn_frag; | |
2530 | fixp[1]->fx_where = prev_insn_where; | |
2531 | } | |
2532 | if (fixp[2]) | |
252b5132 | 2533 | { |
f6688943 TS |
2534 | fixp[2]->fx_frag = prev_insn_frag; |
2535 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2536 | } |
2537 | } | |
2538 | ||
2539 | /* Update the previous insn information; leave prev_insn | |
2540 | unchanged. */ | |
2541 | prev_prev_insn = *ip; | |
2542 | } | |
2543 | prev_insn_is_delay_slot = 1; | |
2544 | ||
2545 | /* If that was an unconditional branch, forget the previous | |
2546 | insn information. */ | |
2547 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2548 | { | |
2549 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2550 | prev_insn.insn_mo = &dummy_opcode; | |
2551 | } | |
2552 | ||
f6688943 TS |
2553 | prev_insn_fixp[0] = NULL; |
2554 | prev_insn_fixp[1] = NULL; | |
2555 | prev_insn_fixp[2] = NULL; | |
2556 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2557 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2558 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2559 | prev_insn_extended = 0; |
2560 | } | |
2561 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2562 | { | |
2563 | /* We don't yet optimize a branch likely. What we should do | |
2564 | is look at the target, copy the instruction found there | |
2565 | into the delay slot, and increment the branch to jump to | |
2566 | the next instruction. */ | |
2567 | emit_nop (); | |
2568 | /* Update the previous insn information. */ | |
2569 | prev_prev_insn = *ip; | |
2570 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2571 | prev_insn_fixp[0] = NULL; |
2572 | prev_insn_fixp[1] = NULL; | |
2573 | prev_insn_fixp[2] = NULL; | |
2574 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2575 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2576 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2577 | prev_insn_extended = 0; |
2578 | } | |
2579 | else | |
2580 | { | |
2581 | /* Update the previous insn information. */ | |
2582 | if (nops > 0) | |
2583 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2584 | else | |
2585 | prev_prev_insn = prev_insn; | |
2586 | prev_insn = *ip; | |
2587 | ||
2588 | /* Any time we see a branch, we always fill the delay slot | |
2589 | immediately; since this insn is not a branch, we know it | |
2590 | is not in a delay slot. */ | |
2591 | prev_insn_is_delay_slot = 0; | |
2592 | ||
f6688943 TS |
2593 | prev_insn_fixp[0] = fixp[0]; |
2594 | prev_insn_fixp[1] = fixp[1]; | |
2595 | prev_insn_fixp[2] = fixp[2]; | |
2596 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2597 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2598 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2599 | if (mips_opts.mips16) |
2600 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2601 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2602 | } |
2603 | ||
2604 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2605 | prev_insn_unreordered = 0; | |
2606 | prev_insn_frag = frag_now; | |
2607 | prev_insn_where = f - frag_now->fr_literal; | |
2608 | prev_insn_valid = 1; | |
2609 | } | |
2610 | else if (place == NULL) | |
2611 | { | |
2612 | /* We need to record a bit of information even when we are not | |
2613 | reordering, in order to determine the base address for mips16 | |
2614 | PC relative relocs. */ | |
2615 | prev_prev_insn = prev_insn; | |
2616 | prev_insn = *ip; | |
f6688943 TS |
2617 | prev_insn_reloc_type[0] = reloc_type[0]; |
2618 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2619 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2620 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2621 | prev_insn_unreordered = 1; | |
2622 | } | |
2623 | ||
2624 | /* We just output an insn, so the next one doesn't have a label. */ | |
2625 | mips_clear_insn_labels (); | |
f5040a92 AO |
2626 | |
2627 | /* We must ensure that the frag to which an instruction that was | |
2628 | moved from a non-variant frag doesn't become a variant frag, | |
2629 | otherwise tc_gen_reloc may get confused. */ | |
2630 | if (force_new_frag) | |
2631 | { | |
2632 | frag_wane (frag_now); | |
2633 | frag_new (0); | |
2634 | } | |
252b5132 RH |
2635 | } |
2636 | ||
2637 | /* This function forgets that there was any previous instruction or | |
2638 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2639 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2640 | |
2641 | static void | |
17a2f251 | 2642 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2643 | { |
2644 | if (! preserve) | |
2645 | { | |
2646 | prev_insn.insn_mo = &dummy_opcode; | |
2647 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2648 | prev_nop_frag = NULL; | |
2649 | prev_nop_frag_holds = 0; | |
2650 | prev_nop_frag_required = 0; | |
2651 | prev_nop_frag_since = 0; | |
2652 | } | |
2653 | prev_insn_valid = 0; | |
2654 | prev_insn_is_delay_slot = 0; | |
2655 | prev_insn_unreordered = 0; | |
2656 | prev_insn_extended = 0; | |
f6688943 TS |
2657 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2658 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2659 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2660 | prev_prev_insn_unreordered = 0; |
2661 | mips_clear_insn_labels (); | |
2662 | } | |
2663 | ||
2664 | /* This function must be called whenever we turn on noreorder or emit | |
2665 | something other than instructions. It inserts any NOPS which might | |
2666 | be needed by the previous instruction, and clears the information | |
2667 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2668 | instructions are to follow. */ |
252b5132 RH |
2669 | |
2670 | static void | |
17a2f251 | 2671 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2672 | { |
2673 | if (! mips_opts.noreorder) | |
2674 | { | |
2675 | int nops; | |
2676 | ||
2677 | nops = 0; | |
2678 | if ((! mips_opts.mips16 | |
81912461 ILT |
2679 | && ((prev_insn.insn_mo->pinfo |
2680 | & (INSN_LOAD_COPROC_DELAY | |
2681 | | INSN_COPROC_MOVE_DELAY | |
2682 | | INSN_WRITE_COND_CODE)) | |
2683 | && ! cop_interlocks)) | |
252b5132 RH |
2684 | || (! hilo_interlocks |
2685 | && (prev_insn.insn_mo->pinfo | |
2686 | & (INSN_READ_LO | |
2687 | | INSN_READ_HI))) | |
2688 | || (! mips_opts.mips16 | |
81912461 ILT |
2689 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2690 | && ! gpr_interlocks) | |
252b5132 | 2691 | || (! mips_opts.mips16 |
81912461 ILT |
2692 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2693 | && ! cop_mem_interlocks)) | |
252b5132 | 2694 | { |
beae10d5 | 2695 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2696 | ++nops; |
2697 | if ((! mips_opts.mips16 | |
81912461 ILT |
2698 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2699 | && ! cop_interlocks)) | |
252b5132 RH |
2700 | || (! hilo_interlocks |
2701 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2702 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2703 | ++nops; | |
2704 | ||
2705 | if (prev_insn_unreordered) | |
2706 | nops = 0; | |
2707 | } | |
2708 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2709 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2710 | && ! cop_interlocks)) | |
252b5132 RH |
2711 | || (! hilo_interlocks |
2712 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2713 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2714 | { | |
beae10d5 | 2715 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2716 | if (! prev_prev_insn_unreordered) |
2717 | ++nops; | |
2718 | } | |
2719 | ||
60b63b72 RS |
2720 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2721 | { | |
2722 | int min_nops = 0; | |
2723 | const char *pn = prev_insn.insn_mo->name; | |
2724 | if (strncmp(pn, "macc", 4) == 0 | |
2725 | || strncmp(pn, "dmacc", 5) == 0 | |
2726 | || strncmp(pn, "dmult", 5) == 0) | |
2727 | { | |
2728 | min_nops = 1; | |
2729 | } | |
2730 | if (nops < min_nops) | |
2731 | nops = min_nops; | |
2732 | } | |
2733 | ||
252b5132 RH |
2734 | if (nops > 0) |
2735 | { | |
2736 | struct insn_label_list *l; | |
2737 | ||
2738 | if (insns) | |
2739 | { | |
2740 | /* Record the frag which holds the nop instructions, so | |
2741 | that we can remove them if we don't need them. */ | |
2742 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2743 | prev_nop_frag = frag_now; | |
2744 | prev_nop_frag_holds = nops; | |
2745 | prev_nop_frag_required = 0; | |
2746 | prev_nop_frag_since = 0; | |
2747 | } | |
2748 | ||
2749 | for (; nops > 0; --nops) | |
2750 | emit_nop (); | |
2751 | ||
2752 | if (insns) | |
2753 | { | |
2754 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2755 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2756 | frag_wane (frag_now); |
2757 | frag_new (0); | |
2758 | } | |
2759 | ||
2760 | for (l = insn_labels; l != NULL; l = l->next) | |
2761 | { | |
98aa84af AM |
2762 | valueT val; |
2763 | ||
252b5132 | 2764 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2765 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2766 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2767 | /* mips16 text labels are stored as odd. */ |
2768 | if (mips_opts.mips16) | |
f9419b05 | 2769 | ++val; |
98aa84af | 2770 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2771 | } |
2772 | } | |
2773 | } | |
2774 | ||
2775 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2776 | if (insns) |
252b5132 RH |
2777 | mips16_mark_labels (); |
2778 | ||
2779 | mips_no_prev_insn (insns); | |
2780 | } | |
2781 | ||
2782 | /* Build an instruction created by a macro expansion. This is passed | |
2783 | a pointer to the count of instructions created so far, an | |
2784 | expression, the name of the instruction to build, an operand format | |
2785 | string, and corresponding arguments. */ | |
2786 | ||
252b5132 | 2787 | static void |
17a2f251 TS |
2788 | macro_build (char *place, int *counter, expressionS *ep, const char *name, |
2789 | const char *fmt, ...) | |
252b5132 RH |
2790 | { |
2791 | struct mips_cl_insn insn; | |
f6688943 | 2792 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2793 | va_list args; |
252b5132 | 2794 | |
252b5132 | 2795 | va_start (args, fmt); |
252b5132 RH |
2796 | |
2797 | /* | |
2798 | * If the macro is about to expand into a second instruction, | |
2799 | * print a warning if needed. We need to pass ip as a parameter | |
2800 | * to generate a better warning message here... | |
2801 | */ | |
2802 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2803 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2804 | ||
80cc45a5 EC |
2805 | /* |
2806 | * If the macro is about to expand into a second instruction, | |
2807 | * and it is in a delay slot, print a warning. | |
2808 | */ | |
2809 | if (place == NULL | |
2810 | && *counter == 1 | |
2811 | && mips_opts.noreorder | |
2812 | && (prev_prev_insn.insn_mo->pinfo | |
2813 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2814 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2815 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2816 | ||
252b5132 | 2817 | if (place == NULL) |
f9419b05 | 2818 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2819 | |
2820 | if (mips_opts.mips16) | |
2821 | { | |
2822 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2823 | va_end (args); | |
2824 | return; | |
2825 | } | |
2826 | ||
f6688943 TS |
2827 | r[0] = BFD_RELOC_UNUSED; |
2828 | r[1] = BFD_RELOC_UNUSED; | |
2829 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2830 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2831 | assert (insn.insn_mo); | |
2832 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2833 | ||
2834 | /* Search until we get a match for NAME. */ | |
2835 | while (1) | |
2836 | { | |
b34976b6 | 2837 | /* It is assumed here that macros will never generate |
deec1734 | 2838 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2839 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2840 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2841 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2842 | (mips_opts.isa | |
3396de36 | 2843 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
2844 | mips_opts.arch) |
2845 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
2846 | break; |
2847 | ||
2848 | ++insn.insn_mo; | |
2849 | assert (insn.insn_mo->name); | |
2850 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2851 | } | |
2852 | ||
2853 | insn.insn_opcode = insn.insn_mo->match; | |
2854 | for (;;) | |
2855 | { | |
2856 | switch (*fmt++) | |
2857 | { | |
2858 | case '\0': | |
2859 | break; | |
2860 | ||
2861 | case ',': | |
2862 | case '(': | |
2863 | case ')': | |
2864 | continue; | |
2865 | ||
5f74bc13 CD |
2866 | case '+': |
2867 | switch (*fmt++) | |
2868 | { | |
2869 | case 'A': | |
2870 | case 'E': | |
2871 | insn.insn_opcode |= (va_arg (args, int) | |
2872 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
2873 | continue; | |
2874 | ||
2875 | case 'B': | |
2876 | case 'F': | |
2877 | /* Note that in the macro case, these arguments are already | |
2878 | in MSB form. (When handling the instruction in the | |
2879 | non-macro case, these arguments are sizes from which | |
2880 | MSB values must be calculated.) */ | |
2881 | insn.insn_opcode |= (va_arg (args, int) | |
2882 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
2883 | continue; | |
2884 | ||
2885 | case 'C': | |
2886 | case 'G': | |
2887 | case 'H': | |
2888 | /* Note that in the macro case, these arguments are already | |
2889 | in MSBD form. (When handling the instruction in the | |
2890 | non-macro case, these arguments are sizes from which | |
2891 | MSBD values must be calculated.) */ | |
2892 | insn.insn_opcode |= (va_arg (args, int) | |
2893 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
2894 | continue; | |
2895 | ||
2896 | default: | |
2897 | internalError (); | |
2898 | } | |
2899 | continue; | |
2900 | ||
252b5132 RH |
2901 | case 't': |
2902 | case 'w': | |
2903 | case 'E': | |
38487616 | 2904 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2905 | continue; |
2906 | ||
2907 | case 'c': | |
38487616 TS |
2908 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2909 | continue; | |
2910 | ||
252b5132 RH |
2911 | case 'T': |
2912 | case 'W': | |
38487616 | 2913 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2914 | continue; |
2915 | ||
2916 | case 'd': | |
2917 | case 'G': | |
af7ee8bf | 2918 | case 'K': |
38487616 | 2919 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2920 | continue; |
2921 | ||
4372b673 NC |
2922 | case 'U': |
2923 | { | |
2924 | int tmp = va_arg (args, int); | |
2925 | ||
38487616 TS |
2926 | insn.insn_opcode |= tmp << OP_SH_RT; |
2927 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2928 | continue; |
4372b673 NC |
2929 | } |
2930 | ||
252b5132 RH |
2931 | case 'V': |
2932 | case 'S': | |
38487616 | 2933 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2934 | continue; |
2935 | ||
2936 | case 'z': | |
2937 | continue; | |
2938 | ||
2939 | case '<': | |
38487616 | 2940 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2941 | continue; |
2942 | ||
2943 | case 'D': | |
38487616 | 2944 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2945 | continue; |
2946 | ||
2947 | case 'B': | |
38487616 | 2948 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2949 | continue; |
2950 | ||
4372b673 | 2951 | case 'J': |
38487616 | 2952 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2953 | continue; |
2954 | ||
252b5132 | 2955 | case 'q': |
38487616 | 2956 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2957 | continue; |
2958 | ||
2959 | case 'b': | |
2960 | case 's': | |
2961 | case 'r': | |
2962 | case 'v': | |
38487616 | 2963 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2964 | continue; |
2965 | ||
2966 | case 'i': | |
2967 | case 'j': | |
2968 | case 'o': | |
f6688943 | 2969 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 2970 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
2971 | || *r == BFD_RELOC_MIPS_LITERAL |
2972 | || *r == BFD_RELOC_MIPS_HIGHER | |
2973 | || *r == BFD_RELOC_HI16_S | |
2974 | || *r == BFD_RELOC_LO16 | |
2975 | || *r == BFD_RELOC_MIPS_GOT16 | |
2976 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
2977 | || *r == BFD_RELOC_MIPS_GOT_DISP |
2978 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
2979 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
2980 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
2981 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2982 | || (ep->X_op == O_subtract |
f6688943 | 2983 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2984 | continue; |
2985 | ||
2986 | case 'u': | |
f6688943 | 2987 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2988 | assert (ep != NULL |
2989 | && (ep->X_op == O_constant | |
2990 | || (ep->X_op == O_symbol | |
f6688943 TS |
2991 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2992 | || *r == BFD_RELOC_HI16_S | |
2993 | || *r == BFD_RELOC_HI16 | |
2994 | || *r == BFD_RELOC_GPREL16 | |
2995 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2996 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2997 | || (ep->X_op == O_subtract |
f6688943 | 2998 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2999 | continue; |
3000 | ||
3001 | case 'p': | |
3002 | assert (ep != NULL); | |
3003 | /* | |
3004 | * This allows macro() to pass an immediate expression for | |
3005 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3006 | * Note that the expression still might come from the assembly |
3007 | * input, in which case the value is not checked for range nor | |
3008 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3009 | */ |
3010 | if (ep->X_op == O_constant) | |
3011 | { | |
3012 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3013 | ep = NULL; | |
3014 | } | |
3015 | else | |
0b25d3e6 | 3016 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3017 | continue; |
3018 | ||
3019 | case 'a': | |
3020 | assert (ep != NULL); | |
f6688943 | 3021 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3022 | continue; |
3023 | ||
3024 | case 'C': | |
3025 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3026 | continue; | |
3027 | ||
3028 | default: | |
3029 | internalError (); | |
3030 | } | |
3031 | break; | |
3032 | } | |
3033 | va_end (args); | |
f6688943 | 3034 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3035 | |
5e0116d5 | 3036 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3037 | } |
3038 | ||
3039 | static void | |
17a2f251 TS |
3040 | mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED, |
3041 | expressionS *ep, const char *name, const char *fmt, | |
3042 | va_list args) | |
252b5132 RH |
3043 | { |
3044 | struct mips_cl_insn insn; | |
f6688943 TS |
3045 | bfd_reloc_code_real_type r[3] |
3046 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3047 | |
252b5132 RH |
3048 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3049 | assert (insn.insn_mo); | |
3050 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3051 | ||
3052 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3053 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3054 | { | |
3055 | ++insn.insn_mo; | |
3056 | assert (insn.insn_mo->name); | |
3057 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3058 | } | |
3059 | ||
3060 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3061 | insn.use_extend = FALSE; |
252b5132 RH |
3062 | |
3063 | for (;;) | |
3064 | { | |
3065 | int c; | |
3066 | ||
3067 | c = *fmt++; | |
3068 | switch (c) | |
3069 | { | |
3070 | case '\0': | |
3071 | break; | |
3072 | ||
3073 | case ',': | |
3074 | case '(': | |
3075 | case ')': | |
3076 | continue; | |
3077 | ||
3078 | case 'y': | |
3079 | case 'w': | |
3080 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3081 | continue; | |
3082 | ||
3083 | case 'x': | |
3084 | case 'v': | |
3085 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3086 | continue; | |
3087 | ||
3088 | case 'z': | |
3089 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3090 | continue; | |
3091 | ||
3092 | case 'Z': | |
3093 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3094 | continue; | |
3095 | ||
3096 | case '0': | |
3097 | case 'S': | |
3098 | case 'P': | |
3099 | case 'R': | |
3100 | continue; | |
3101 | ||
3102 | case 'X': | |
3103 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3104 | continue; | |
3105 | ||
3106 | case 'Y': | |
3107 | { | |
3108 | int regno; | |
3109 | ||
3110 | regno = va_arg (args, int); | |
3111 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3112 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3113 | } | |
3114 | continue; | |
3115 | ||
3116 | case '<': | |
3117 | case '>': | |
3118 | case '4': | |
3119 | case '5': | |
3120 | case 'H': | |
3121 | case 'W': | |
3122 | case 'D': | |
3123 | case 'j': | |
3124 | case '8': | |
3125 | case 'V': | |
3126 | case 'C': | |
3127 | case 'U': | |
3128 | case 'k': | |
3129 | case 'K': | |
3130 | case 'p': | |
3131 | case 'q': | |
3132 | { | |
3133 | assert (ep != NULL); | |
3134 | ||
3135 | if (ep->X_op != O_constant) | |
874e8986 | 3136 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3137 | else |
3138 | { | |
b34976b6 AM |
3139 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3140 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3141 | &insn.extend); |
252b5132 | 3142 | ep = NULL; |
f6688943 | 3143 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3144 | } |
3145 | } | |
3146 | continue; | |
3147 | ||
3148 | case '6': | |
3149 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3150 | continue; | |
3151 | } | |
3152 | ||
3153 | break; | |
3154 | } | |
3155 | ||
f6688943 | 3156 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3157 | |
5e0116d5 | 3158 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3159 | } |
3160 | ||
438c16b8 TS |
3161 | /* |
3162 | * Generate a "jalr" instruction with a relocation hint to the called | |
3163 | * function. This occurs in NewABI PIC code. | |
3164 | */ | |
3165 | static void | |
17a2f251 | 3166 | macro_build_jalr (int icnt, expressionS *ep) |
438c16b8 | 3167 | { |
685736be | 3168 | char *f = NULL; |
b34976b6 | 3169 | |
438c16b8 | 3170 | if (HAVE_NEWABI) |
f21f8242 | 3171 | { |
cc3d92a5 | 3172 | frag_grow (8); |
f21f8242 AO |
3173 | f = frag_more (0); |
3174 | } | |
17a2f251 | 3175 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3176 | if (HAVE_NEWABI) |
f21f8242 | 3177 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3178 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3179 | } |
3180 | ||
252b5132 RH |
3181 | /* |
3182 | * Generate a "lui" instruction. | |
3183 | */ | |
3184 | static void | |
17a2f251 | 3185 | macro_build_lui (char *place, int *counter, expressionS *ep, int regnum) |
252b5132 RH |
3186 | { |
3187 | expressionS high_expr; | |
3188 | struct mips_cl_insn insn; | |
f6688943 TS |
3189 | bfd_reloc_code_real_type r[3] |
3190 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3191 | const char *name = "lui"; |
3192 | const char *fmt = "t,u"; | |
252b5132 RH |
3193 | |
3194 | assert (! mips_opts.mips16); | |
3195 | ||
3196 | if (place == NULL) | |
3197 | high_expr = *ep; | |
3198 | else | |
3199 | { | |
3200 | high_expr.X_op = O_constant; | |
3201 | high_expr.X_add_number = ep->X_add_number; | |
3202 | } | |
3203 | ||
3204 | if (high_expr.X_op == O_constant) | |
3205 | { | |
3206 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3207 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3208 | >> 16) & 0xffff; | |
f6688943 | 3209 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3210 | } |
78e1bb40 | 3211 | else |
252b5132 RH |
3212 | { |
3213 | assert (ep->X_op == O_symbol); | |
3214 | /* _gp_disp is a special case, used from s_cpload. */ | |
3215 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3216 | || (! HAVE_NEWABI |
3217 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3218 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3219 | } |
3220 | ||
3221 | /* | |
3222 | * If the macro is about to expand into a second instruction, | |
3223 | * print a warning if needed. We need to pass ip as a parameter | |
3224 | * to generate a better warning message here... | |
3225 | */ | |
3226 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3227 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3228 | ||
3229 | if (place == NULL) | |
f9419b05 | 3230 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3231 | |
3232 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3233 | assert (insn.insn_mo); | |
3234 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3235 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3236 | ||
3237 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3238 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3239 | { |
3240 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3241 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3242 | } |
3243 | else | |
5e0116d5 | 3244 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3245 | } |
3246 | ||
885add95 CD |
3247 | /* Generate a sequence of instructions to do a load or store from a constant |
3248 | offset off of a base register (breg) into/from a target register (treg), | |
3249 | using AT if necessary. */ | |
3250 | static void | |
17a2f251 | 3251 | macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep, |
256ab948 | 3252 | const char *op, int treg, int breg, int dbl) |
885add95 CD |
3253 | { |
3254 | assert (ep->X_op == O_constant); | |
3255 | ||
256ab948 | 3256 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3257 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3258 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3259 | { |
d17e7bce | 3260 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3261 | as_bad (_("constant too large")); |
ae826530 | 3262 | |
1b8e29e5 TS |
3263 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3264 | - 0x80000000); | |
ae826530 | 3265 | } |
256ab948 | 3266 | |
67c1ffbe | 3267 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3268 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3269 | as_warn (_("operand overflow")); |
3270 | ||
3271 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3272 | { | |
3273 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
17a2f251 TS |
3274 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3275 | breg); | |
885add95 CD |
3276 | } |
3277 | else | |
3278 | { | |
3279 | /* 32-bit offset, need multiple instructions and AT, like: | |
3280 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3281 | addu $tempreg,$tempreg,$breg | |
3282 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3283 | to handle the complete offset. */ | |
3284 | macro_build_lui (place, counter, ep, AT); | |
3285 | if (place != NULL) | |
3286 | place += 4; | |
17a2f251 TS |
3287 | macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, |
3288 | breg); | |
885add95 CD |
3289 | if (place != NULL) |
3290 | place += 4; | |
17a2f251 TS |
3291 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3292 | AT); | |
885add95 CD |
3293 | |
3294 | if (mips_opts.noat) | |
3295 | as_warn (_("Macro used $at after \".set noat\"")); | |
3296 | } | |
3297 | } | |
3298 | ||
252b5132 RH |
3299 | /* set_at() |
3300 | * Generates code to set the $at register to true (one) | |
3301 | * if reg is less than the immediate expression. | |
3302 | */ | |
3303 | static void | |
17a2f251 | 3304 | set_at (int *counter, int reg, int unsignedp) |
252b5132 RH |
3305 | { |
3306 | if (imm_expr.X_op == O_constant | |
3307 | && imm_expr.X_add_number >= -0x8000 | |
3308 | && imm_expr.X_add_number < 0x8000) | |
17a2f251 TS |
3309 | macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti", |
3310 | "t,r,j", AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3311 | else |
3312 | { | |
4d34fb5f | 3313 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 3314 | macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt", |
252b5132 RH |
3315 | "d,v,t", AT, reg, AT); |
3316 | } | |
3317 | } | |
3318 | ||
13757d0c TS |
3319 | static void |
3320 | normalize_constant_expr (expressionS *ex) | |
3321 | { | |
3322 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3323 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3324 | - 0x80000000); | |
3325 | } | |
3326 | ||
252b5132 RH |
3327 | /* Warn if an expression is not a constant. */ |
3328 | ||
3329 | static void | |
17a2f251 | 3330 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3331 | { |
3332 | if (ex->X_op == O_big) | |
3333 | as_bad (_("unsupported large constant")); | |
3334 | else if (ex->X_op != O_constant) | |
3335 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3336 | |
3337 | normalize_constant_expr (ex); | |
252b5132 RH |
3338 | } |
3339 | ||
3340 | /* Count the leading zeroes by performing a binary chop. This is a | |
3341 | bulky bit of source, but performance is a LOT better for the | |
3342 | majority of values than a simple loop to count the bits: | |
3343 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3344 | if ((v) & (1 << (31 - lcnt))) | |
3345 | break; | |
3346 | However it is not code size friendly, and the gain will drop a bit | |
3347 | on certain cached systems. | |
3348 | */ | |
3349 | #define COUNT_TOP_ZEROES(v) \ | |
3350 | (((v) & ~0xffff) == 0 \ | |
3351 | ? ((v) & ~0xff) == 0 \ | |
3352 | ? ((v) & ~0xf) == 0 \ | |
3353 | ? ((v) & ~0x3) == 0 \ | |
3354 | ? ((v) & ~0x1) == 0 \ | |
3355 | ? !(v) \ | |
3356 | ? 32 \ | |
3357 | : 31 \ | |
3358 | : 30 \ | |
3359 | : ((v) & ~0x7) == 0 \ | |
3360 | ? 29 \ | |
3361 | : 28 \ | |
3362 | : ((v) & ~0x3f) == 0 \ | |
3363 | ? ((v) & ~0x1f) == 0 \ | |
3364 | ? 27 \ | |
3365 | : 26 \ | |
3366 | : ((v) & ~0x7f) == 0 \ | |
3367 | ? 25 \ | |
3368 | : 24 \ | |
3369 | : ((v) & ~0xfff) == 0 \ | |
3370 | ? ((v) & ~0x3ff) == 0 \ | |
3371 | ? ((v) & ~0x1ff) == 0 \ | |
3372 | ? 23 \ | |
3373 | : 22 \ | |
3374 | : ((v) & ~0x7ff) == 0 \ | |
3375 | ? 21 \ | |
3376 | : 20 \ | |
3377 | : ((v) & ~0x3fff) == 0 \ | |
3378 | ? ((v) & ~0x1fff) == 0 \ | |
3379 | ? 19 \ | |
3380 | : 18 \ | |
3381 | : ((v) & ~0x7fff) == 0 \ | |
3382 | ? 17 \ | |
3383 | : 16 \ | |
3384 | : ((v) & ~0xffffff) == 0 \ | |
3385 | ? ((v) & ~0xfffff) == 0 \ | |
3386 | ? ((v) & ~0x3ffff) == 0 \ | |
3387 | ? ((v) & ~0x1ffff) == 0 \ | |
3388 | ? 15 \ | |
3389 | : 14 \ | |
3390 | : ((v) & ~0x7ffff) == 0 \ | |
3391 | ? 13 \ | |
3392 | : 12 \ | |
3393 | : ((v) & ~0x3fffff) == 0 \ | |
3394 | ? ((v) & ~0x1fffff) == 0 \ | |
3395 | ? 11 \ | |
3396 | : 10 \ | |
3397 | : ((v) & ~0x7fffff) == 0 \ | |
3398 | ? 9 \ | |
3399 | : 8 \ | |
3400 | : ((v) & ~0xfffffff) == 0 \ | |
3401 | ? ((v) & ~0x3ffffff) == 0 \ | |
3402 | ? ((v) & ~0x1ffffff) == 0 \ | |
3403 | ? 7 \ | |
3404 | : 6 \ | |
3405 | : ((v) & ~0x7ffffff) == 0 \ | |
3406 | ? 5 \ | |
3407 | : 4 \ | |
3408 | : ((v) & ~0x3fffffff) == 0 \ | |
3409 | ? ((v) & ~0x1fffffff) == 0 \ | |
3410 | ? 3 \ | |
3411 | : 2 \ | |
3412 | : ((v) & ~0x7fffffff) == 0 \ | |
3413 | ? 1 \ | |
3414 | : 0) | |
3415 | ||
3416 | /* load_register() | |
67c1ffbe | 3417 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3418 | * an absolute expression value into a register. |
3419 | */ | |
3420 | static void | |
17a2f251 | 3421 | load_register (int *counter, int reg, expressionS *ep, int dbl) |
252b5132 RH |
3422 | { |
3423 | int freg; | |
3424 | expressionS hi32, lo32; | |
3425 | ||
3426 | if (ep->X_op != O_big) | |
3427 | { | |
3428 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3429 | |
3430 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3431 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3432 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3433 | { |
d17e7bce | 3434 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3435 | as_bad (_("constant too large")); |
ae826530 | 3436 | |
1b8e29e5 TS |
3437 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3438 | - 0x80000000); | |
ae826530 | 3439 | } |
256ab948 TS |
3440 | |
3441 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3442 | { |
3443 | /* We can handle 16 bit signed values with an addiu to | |
3444 | $zero. No need to ever use daddiu here, since $zero and | |
3445 | the result are always correct in 32 bit mode. */ | |
17a2f251 TS |
3446 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3447 | BFD_RELOC_LO16); | |
252b5132 RH |
3448 | return; |
3449 | } | |
3450 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3451 | { | |
3452 | /* We can handle 16 bit unsigned values with an ori to | |
3453 | $zero. */ | |
17a2f251 TS |
3454 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0, |
3455 | BFD_RELOC_LO16); | |
252b5132 RH |
3456 | return; |
3457 | } | |
256ab948 | 3458 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3459 | { |
3460 | /* 32 bit values require an lui. */ | |
17a2f251 | 3461 | macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3462 | if ((ep->X_add_number & 0xffff) != 0) |
17a2f251 TS |
3463 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg, |
3464 | BFD_RELOC_LO16); | |
252b5132 RH |
3465 | return; |
3466 | } | |
3467 | } | |
3468 | ||
3469 | /* The value is larger than 32 bits. */ | |
3470 | ||
ca4e0257 | 3471 | if (HAVE_32BIT_GPRS) |
252b5132 | 3472 | { |
956cd1d6 TS |
3473 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3474 | (unsigned long) ep->X_add_number); | |
17a2f251 TS |
3475 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3476 | BFD_RELOC_LO16); | |
252b5132 RH |
3477 | return; |
3478 | } | |
3479 | ||
3480 | if (ep->X_op != O_big) | |
3481 | { | |
3482 | hi32 = *ep; | |
3483 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3484 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3485 | hi32.X_add_number &= 0xffffffff; | |
3486 | lo32 = *ep; | |
3487 | lo32.X_add_number &= 0xffffffff; | |
3488 | } | |
3489 | else | |
3490 | { | |
3491 | assert (ep->X_add_number > 2); | |
3492 | if (ep->X_add_number == 3) | |
3493 | generic_bignum[3] = 0; | |
3494 | else if (ep->X_add_number > 4) | |
3495 | as_bad (_("Number larger than 64 bits")); | |
3496 | lo32.X_op = O_constant; | |
3497 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3498 | hi32.X_op = O_constant; | |
3499 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3500 | } | |
3501 | ||
3502 | if (hi32.X_add_number == 0) | |
3503 | freg = 0; | |
3504 | else | |
3505 | { | |
3506 | int shift, bit; | |
3507 | unsigned long hi, lo; | |
3508 | ||
956cd1d6 | 3509 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3510 | { |
3511 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3512 | { | |
17a2f251 TS |
3513 | macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, |
3514 | BFD_RELOC_LO16); | |
beae10d5 KH |
3515 | return; |
3516 | } | |
3517 | if (lo32.X_add_number & 0x80000000) | |
3518 | { | |
17a2f251 TS |
3519 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3520 | BFD_RELOC_HI16); | |
252b5132 | 3521 | if (lo32.X_add_number & 0xffff) |
17a2f251 TS |
3522 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
3523 | BFD_RELOC_LO16); | |
beae10d5 KH |
3524 | return; |
3525 | } | |
3526 | } | |
252b5132 RH |
3527 | |
3528 | /* Check for 16bit shifted constant. We know that hi32 is | |
3529 | non-zero, so start the mask on the first bit of the hi32 | |
3530 | value. */ | |
3531 | shift = 17; | |
3532 | do | |
beae10d5 KH |
3533 | { |
3534 | unsigned long himask, lomask; | |
3535 | ||
3536 | if (shift < 32) | |
3537 | { | |
3538 | himask = 0xffff >> (32 - shift); | |
3539 | lomask = (0xffff << shift) & 0xffffffff; | |
3540 | } | |
3541 | else | |
3542 | { | |
3543 | himask = 0xffff << (shift - 32); | |
3544 | lomask = 0; | |
3545 | } | |
3546 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3547 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3548 | { | |
3549 | expressionS tmp; | |
3550 | ||
3551 | tmp.X_op = O_constant; | |
3552 | if (shift < 32) | |
3553 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3554 | | (lo32.X_add_number >> shift)); | |
3555 | else | |
3556 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
17a2f251 TS |
3557 | macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0, |
3558 | BFD_RELOC_LO16); | |
3559 | macro_build (NULL, counter, NULL, | |
beae10d5 KH |
3560 | (shift >= 32) ? "dsll32" : "dsll", |
3561 | "d,w,<", reg, reg, | |
3562 | (shift >= 32) ? shift - 32 : shift); | |
3563 | return; | |
3564 | } | |
f9419b05 | 3565 | ++shift; |
beae10d5 KH |
3566 | } |
3567 | while (shift <= (64 - 16)); | |
252b5132 RH |
3568 | |
3569 | /* Find the bit number of the lowest one bit, and store the | |
3570 | shifted value in hi/lo. */ | |
3571 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3572 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3573 | if (lo != 0) | |
3574 | { | |
3575 | bit = 0; | |
3576 | while ((lo & 1) == 0) | |
3577 | { | |
3578 | lo >>= 1; | |
3579 | ++bit; | |
3580 | } | |
3581 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3582 | hi >>= bit; | |
3583 | } | |
3584 | else | |
3585 | { | |
3586 | bit = 32; | |
3587 | while ((hi & 1) == 0) | |
3588 | { | |
3589 | hi >>= 1; | |
3590 | ++bit; | |
3591 | } | |
3592 | lo = hi; | |
3593 | hi = 0; | |
3594 | } | |
3595 | ||
3596 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3597 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3598 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3599 | { |
3600 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3601 | if (shift != 0) |
beae10d5 | 3602 | { |
252b5132 RH |
3603 | expressionS tmp; |
3604 | ||
3605 | /* This instruction will set the register to be all | |
3606 | ones. */ | |
beae10d5 KH |
3607 | tmp.X_op = O_constant; |
3608 | tmp.X_add_number = (offsetT) -1; | |
17a2f251 TS |
3609 | macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, |
3610 | BFD_RELOC_LO16); | |
beae10d5 KH |
3611 | if (bit != 0) |
3612 | { | |
3613 | bit += shift; | |
17a2f251 | 3614 | macro_build (NULL, counter, NULL, |
beae10d5 KH |
3615 | (bit >= 32) ? "dsll32" : "dsll", |
3616 | "d,w,<", reg, reg, | |
3617 | (bit >= 32) ? bit - 32 : bit); | |
3618 | } | |
17a2f251 | 3619 | macro_build (NULL, counter, NULL, |
252b5132 | 3620 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3621 | "d,w,<", reg, reg, |
252b5132 | 3622 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3623 | return; |
3624 | } | |
3625 | } | |
252b5132 RH |
3626 | |
3627 | /* Sign extend hi32 before calling load_register, because we can | |
3628 | generally get better code when we load a sign extended value. */ | |
3629 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3630 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3631 | load_register (counter, reg, &hi32, 0); |
3632 | freg = reg; | |
3633 | } | |
3634 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3635 | { | |
3636 | if (freg != 0) | |
3637 | { | |
17a2f251 | 3638 | macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3639 | freg = reg; |
3640 | } | |
3641 | } | |
3642 | else | |
3643 | { | |
3644 | expressionS mid16; | |
3645 | ||
956cd1d6 | 3646 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3647 | { |
17a2f251 TS |
3648 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3649 | BFD_RELOC_HI16); | |
3650 | macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3651 | return; |
3652 | } | |
252b5132 RH |
3653 | |
3654 | if (freg != 0) | |
3655 | { | |
17a2f251 | 3656 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3657 | freg = reg; |
3658 | } | |
3659 | mid16 = lo32; | |
3660 | mid16.X_add_number >>= 16; | |
17a2f251 TS |
3661 | macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg, |
3662 | BFD_RELOC_LO16); | |
3663 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3664 | freg = reg; |
3665 | } | |
3666 | if ((lo32.X_add_number & 0xffff) != 0) | |
17a2f251 TS |
3667 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
3668 | BFD_RELOC_LO16); | |
252b5132 RH |
3669 | } |
3670 | ||
3671 | /* Load an address into a register. */ | |
3672 | ||
3673 | static void | |
17a2f251 | 3674 | load_address (int *counter, int reg, expressionS *ep, int *used_at) |
252b5132 | 3675 | { |
f9419b05 | 3676 | char *p = NULL; |
252b5132 RH |
3677 | |
3678 | if (ep->X_op != O_constant | |
3679 | && ep->X_op != O_symbol) | |
3680 | { | |
3681 | as_bad (_("expression too complex")); | |
3682 | ep->X_op = O_constant; | |
3683 | } | |
3684 | ||
3685 | if (ep->X_op == O_constant) | |
3686 | { | |
c9914766 | 3687 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3688 | return; |
3689 | } | |
3690 | ||
3691 | if (mips_pic == NO_PIC) | |
3692 | { | |
3693 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3694 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3695 | Otherwise we want |
3696 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3697 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3698 | If we have an addend, we always use the latter form. |
76b3015f | 3699 | |
d6bc6245 TS |
3700 | With 64bit address space and a usable $at we want |
3701 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3702 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3703 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3704 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3705 | dsll32 $reg,0 | |
3a482fd5 | 3706 | daddu $reg,$reg,$at |
76b3015f | 3707 | |
c03099e6 | 3708 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3709 | on superscalar processors. |
3710 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3711 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3712 | dsll $reg,16 | |
3713 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3714 | dsll $reg,16 | |
3715 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3716 | */ | |
c9914766 | 3717 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3718 | { |
d6bc6245 TS |
3719 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3720 | hold the data for such large chunks. */ | |
3721 | ||
460597ba | 3722 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3723 | { |
3724 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3725 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3726 | macro_build (p, counter, ep, "lui", "t,u", |
17a2f251 | 3727 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 3728 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3729 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 3730 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3731 | AT, AT, BFD_RELOC_LO16); |
3732 | macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3733 | macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3734 | *used_at = 1; |
3735 | } | |
3736 | else | |
3737 | { | |
3738 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3739 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3740 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3741 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
3742 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3743 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3744 | reg, reg, BFD_RELOC_HI16_S); |
3745 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3746 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3747 | reg, reg, BFD_RELOC_LO16); |
d6bc6245 TS |
3748 | } |
3749 | } | |
252b5132 RH |
3750 | else |
3751 | { | |
d6bc6245 TS |
3752 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3753 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3754 | { | |
3755 | frag_grow (20); | |
17a2f251 TS |
3756 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3757 | mips_gp_register, BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3758 | p = frag_var (rs_machine_dependent, 8, 0, |
3759 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3760 | mips_opts.warn_about_macros), | |
956cd1d6 | 3761 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3762 | } |
3763 | macro_build_lui (p, counter, ep, reg); | |
3764 | if (p != NULL) | |
3765 | p += 4; | |
17a2f251 TS |
3766 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3767 | BFD_RELOC_LO16); | |
d6bc6245 | 3768 | } |
252b5132 RH |
3769 | } |
3770 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3771 | { | |
3772 | expressionS ex; | |
3773 | ||
3774 | /* If this is a reference to an external symbol, we want | |
3775 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3776 | Otherwise we want | |
3777 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3778 | nop | |
3779 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3780 | If there is a constant, it must be added in after. |
3781 | ||
ed6fb7bd | 3782 | If we have NewABI, we want |
f5040a92 AO |
3783 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3784 | unless we're referencing a global symbol with a non-zero | |
3785 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3786 | if (HAVE_NEWABI) |
3787 | { | |
f5040a92 | 3788 | frag_grow (12); |
684022ea | 3789 | |
f5040a92 AO |
3790 | if (ep->X_add_number) |
3791 | { | |
3792 | frag_now->tc_frag_data.tc_fr_offset = | |
3793 | ex.X_add_number = ep->X_add_number; | |
3794 | ep->X_add_number = 0; | |
17a2f251 TS |
3795 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", |
3796 | reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3797 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3798 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3799 | ex.X_op = O_constant; | |
17a2f251 TS |
3800 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3801 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3802 | p = frag_var (rs_machine_dependent, 8, 0, |
3803 | RELAX_ENCODE (8, 4, 0, 0, 0, | |
3804 | mips_opts.warn_about_macros), | |
17a2f251 | 3805 | ep->X_add_symbol, 0, NULL); |
f5040a92 AO |
3806 | ep->X_add_number = ex.X_add_number; |
3807 | } | |
3808 | ||
f899b4b8 | 3809 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3810 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
f5040a92 AO |
3811 | |
3812 | if (! p) | |
3813 | { | |
3814 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3815 | that this does not become a variant frag. */ | |
3816 | frag_wane (frag_now); | |
3817 | frag_new (0); | |
3818 | } | |
ed6fb7bd SC |
3819 | } |
3820 | else | |
3821 | { | |
f5040a92 AO |
3822 | ex.X_add_number = ep->X_add_number; |
3823 | ep->X_add_number = 0; | |
3824 | frag_grow (20); | |
17a2f251 TS |
3825 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3826 | BFD_RELOC_MIPS_GOT16, | |
f899b4b8 | 3827 | mips_gp_register); |
17a2f251 | 3828 | macro_build (NULL, counter, NULL, "nop", ""); |
ed6fb7bd SC |
3829 | p = frag_var (rs_machine_dependent, 4, 0, |
3830 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
17a2f251 TS |
3831 | ep->X_add_symbol, 0, NULL); |
3832 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, | |
3833 | BFD_RELOC_LO16); | |
ed6fb7bd | 3834 | |
f5040a92 AO |
3835 | if (ex.X_add_number != 0) |
3836 | { | |
3837 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3838 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3839 | ex.X_op = O_constant; | |
17a2f251 TS |
3840 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3841 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3842 | } |
252b5132 RH |
3843 | } |
3844 | } | |
3845 | else if (mips_pic == SVR4_PIC) | |
3846 | { | |
3847 | expressionS ex; | |
3848 | int off; | |
3849 | ||
3850 | /* This is the large GOT case. If this is a reference to an | |
3851 | external symbol, we want | |
3852 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3853 | addu $reg,$reg,$gp | |
3854 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3855 | |
3856 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3857 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3858 | nop | |
3859 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3860 | If there is a constant, it must be added in after. |
f5040a92 AO |
3861 | |
3862 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3863 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3864 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3865 | */ |
438c16b8 TS |
3866 | if (HAVE_NEWABI) |
3867 | { | |
f5040a92 AO |
3868 | frag_grow (24); |
3869 | ||
3870 | frag_now->tc_frag_data.tc_fr_offset = | |
3871 | ex.X_add_number = ep->X_add_number; | |
3872 | ep->X_add_number = 0; | |
17a2f251 TS |
3873 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3874 | BFD_RELOC_MIPS_GOT_HI16); | |
3875 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3876 | reg, mips_gp_register); | |
3877 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3878 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3879 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3880 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3881 | else if (ex.X_add_number) | |
3882 | { | |
3883 | ex.X_op = O_constant; | |
17a2f251 TS |
3884 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3885 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3886 | } |
3887 | ||
3888 | ep->X_add_number = ex.X_add_number; | |
3889 | p = frag_var (rs_machine_dependent, 8, 0, | |
3890 | RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0, | |
3891 | mips_opts.warn_about_macros), | |
17a2f251 | 3892 | ep->X_add_symbol, 0, NULL); |
f899b4b8 | 3893 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 TS |
3894 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
3895 | macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3896 | reg, BFD_RELOC_MIPS_GOT_OFST); | |
438c16b8 | 3897 | } |
252b5132 | 3898 | else |
438c16b8 | 3899 | { |
f5040a92 AO |
3900 | ex.X_add_number = ep->X_add_number; |
3901 | ep->X_add_number = 0; | |
438c16b8 TS |
3902 | if (reg_needs_delay (mips_gp_register)) |
3903 | off = 4; | |
3904 | else | |
3905 | off = 0; | |
3906 | frag_grow (32); | |
17a2f251 TS |
3907 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3908 | BFD_RELOC_MIPS_GOT_HI16); | |
3909 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3910 | reg, mips_gp_register); | |
3911 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3912 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
438c16b8 TS |
3913 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3914 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3915 | mips_opts.warn_about_macros), | |
3916 | ep->X_add_symbol, 0, NULL); | |
3917 | if (off > 0) | |
3918 | { | |
3919 | /* We need a nop before loading from $gp. This special | |
3920 | check is required because the lui which starts the main | |
3921 | instruction stream does not refer to $gp, and so will not | |
3922 | insert the nop which may be required. */ | |
17a2f251 | 3923 | macro_build (p, counter, NULL, "nop", ""); |
438c16b8 TS |
3924 | p += 4; |
3925 | } | |
f899b4b8 | 3926 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3927 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
438c16b8 | 3928 | p += 4; |
17a2f251 | 3929 | macro_build (p, counter, NULL, "nop", ""); |
252b5132 | 3930 | p += 4; |
17a2f251 TS |
3931 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3932 | BFD_RELOC_LO16); | |
438c16b8 | 3933 | |
f5040a92 AO |
3934 | if (ex.X_add_number != 0) |
3935 | { | |
3936 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3937 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3938 | ex.X_op = O_constant; | |
17a2f251 TS |
3939 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3940 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3941 | } |
252b5132 RH |
3942 | } |
3943 | } | |
3944 | else if (mips_pic == EMBEDDED_PIC) | |
3945 | { | |
3946 | /* We always do | |
cdf6fd85 | 3947 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 3948 | */ |
17a2f251 TS |
3949 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3950 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
3951 | } |
3952 | else | |
3953 | abort (); | |
3954 | } | |
3955 | ||
ea1fb5dc RS |
3956 | /* Move the contents of register SOURCE into register DEST. */ |
3957 | ||
3958 | static void | |
17a2f251 | 3959 | move_register (int *counter, int dest, int source) |
ea1fb5dc | 3960 | { |
17a2f251 | 3961 | macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", |
ea1fb5dc RS |
3962 | "d,v,t", dest, source, 0); |
3963 | } | |
3964 | ||
252b5132 RH |
3965 | /* |
3966 | * Build macros | |
3967 | * This routine implements the seemingly endless macro or synthesized | |
3968 | * instructions and addressing modes in the mips assembly language. Many | |
3969 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 3970 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
3971 | * this verbose method. Others are not simple macros but are more like |
3972 | * optimizing code generation. | |
3973 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 3974 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
3975 | * The ensuing load upper instructions are ommited. This implies some kind |
3976 | * of global optimization. We currently only optimize within a single macro. | |
3977 | * For many of the load and store macros if the address is specified as a | |
3978 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3979 | * first load register 'at' with zero and use it as the base register. The | |
3980 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3981 | * we're missing. | |
3982 | */ | |
3983 | static void | |
17a2f251 | 3984 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
3985 | { |
3986 | register int treg, sreg, dreg, breg; | |
3987 | int tempreg; | |
3988 | int mask; | |
3989 | int icnt = 0; | |
43841e91 | 3990 | int used_at = 0; |
252b5132 RH |
3991 | expressionS expr1; |
3992 | const char *s; | |
3993 | const char *s2; | |
3994 | const char *fmt; | |
3995 | int likely = 0; | |
3996 | int dbl = 0; | |
3997 | int coproc = 0; | |
3998 | int lr = 0; | |
3999 | int imm = 0; | |
1abe91b1 | 4000 | int call = 0; |
252b5132 RH |
4001 | offsetT maxnum; |
4002 | int off; | |
4003 | bfd_reloc_code_real_type r; | |
252b5132 RH |
4004 | int hold_mips_optimize; |
4005 | ||
4006 | assert (! mips_opts.mips16); | |
4007 | ||
4008 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4009 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4010 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4011 | mask = ip->insn_mo->mask; | |
4012 | ||
4013 | expr1.X_op = O_constant; | |
4014 | expr1.X_op_symbol = NULL; | |
4015 | expr1.X_add_symbol = NULL; | |
4016 | expr1.X_add_number = 1; | |
4017 | ||
67c1ffbe | 4018 | /* Unmatched fixups should not be put in the same frag as a relaxable |
5919d012 RS |
4019 | macro. For example, suppose we have: |
4020 | ||
4021 | lui $4,%hi(l1) # 1 | |
4022 | la $5,l2 # 2 | |
4023 | addiu $4,$4,%lo(l1) # 3 | |
4024 | ||
4025 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
4026 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
4027 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
4028 | for #2 to be the last for that frag. | |
4029 | ||
64bdfcaf RS |
4030 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
4031 | it assumes that they belong to a relaxable macro. We mustn't put | |
4032 | other uses of such relocations into a variant frag. | |
4033 | ||
4034 | To avoid both problems, finish the current frag it contains a | |
4035 | %reloc() operator. The macro then goes into a new frag. */ | |
4036 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
4037 | { |
4038 | frag_wane (frag_now); | |
4039 | frag_new (0); | |
4040 | } | |
4041 | ||
252b5132 RH |
4042 | switch (mask) |
4043 | { | |
4044 | case M_DABS: | |
4045 | dbl = 1; | |
4046 | case M_ABS: | |
4047 | /* bgez $a0,.+12 | |
4048 | move v0,$a0 | |
4049 | sub v0,$zero,$a0 | |
4050 | */ | |
4051 | ||
b34976b6 | 4052 | mips_emit_delays (TRUE); |
252b5132 RH |
4053 | ++mips_opts.noreorder; |
4054 | mips_any_noreorder = 1; | |
4055 | ||
4056 | expr1.X_add_number = 8; | |
17a2f251 | 4057 | macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
252b5132 | 4058 | if (dreg == sreg) |
17a2f251 | 4059 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 | 4060 | else |
ea1fb5dc | 4061 | move_register (&icnt, dreg, sreg); |
17a2f251 TS |
4062 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, |
4063 | sreg); | |
252b5132 RH |
4064 | |
4065 | --mips_opts.noreorder; | |
4066 | return; | |
4067 | ||
4068 | case M_ADD_I: | |
4069 | s = "addi"; | |
4070 | s2 = "add"; | |
4071 | goto do_addi; | |
4072 | case M_ADDU_I: | |
4073 | s = "addiu"; | |
4074 | s2 = "addu"; | |
4075 | goto do_addi; | |
4076 | case M_DADD_I: | |
4077 | dbl = 1; | |
4078 | s = "daddi"; | |
4079 | s2 = "dadd"; | |
4080 | goto do_addi; | |
4081 | case M_DADDU_I: | |
4082 | dbl = 1; | |
4083 | s = "daddiu"; | |
4084 | s2 = "daddu"; | |
4085 | do_addi: | |
4086 | if (imm_expr.X_op == O_constant | |
4087 | && imm_expr.X_add_number >= -0x8000 | |
4088 | && imm_expr.X_add_number < 0x8000) | |
4089 | { | |
17a2f251 TS |
4090 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
4091 | BFD_RELOC_LO16); | |
252b5132 RH |
4092 | return; |
4093 | } | |
4094 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 | 4095 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4096 | break; |
4097 | ||
4098 | case M_AND_I: | |
4099 | s = "andi"; | |
4100 | s2 = "and"; | |
4101 | goto do_bit; | |
4102 | case M_OR_I: | |
4103 | s = "ori"; | |
4104 | s2 = "or"; | |
4105 | goto do_bit; | |
4106 | case M_NOR_I: | |
4107 | s = ""; | |
4108 | s2 = "nor"; | |
4109 | goto do_bit; | |
4110 | case M_XOR_I: | |
4111 | s = "xori"; | |
4112 | s2 = "xor"; | |
4113 | do_bit: | |
4114 | if (imm_expr.X_op == O_constant | |
4115 | && imm_expr.X_add_number >= 0 | |
4116 | && imm_expr.X_add_number < 0x10000) | |
4117 | { | |
4118 | if (mask != M_NOR_I) | |
17a2f251 TS |
4119 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg, |
4120 | BFD_RELOC_LO16); | |
252b5132 RH |
4121 | else |
4122 | { | |
17a2f251 TS |
4123 | macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg, |
4124 | BFD_RELOC_LO16); | |
4125 | macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4126 | } |
4127 | return; | |
4128 | } | |
4129 | ||
d6bc6245 | 4130 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4131 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4132 | break; |
4133 | ||
4134 | case M_BEQ_I: | |
4135 | s = "beq"; | |
4136 | goto beq_i; | |
4137 | case M_BEQL_I: | |
4138 | s = "beql"; | |
4139 | likely = 1; | |
4140 | goto beq_i; | |
4141 | case M_BNE_I: | |
4142 | s = "bne"; | |
4143 | goto beq_i; | |
4144 | case M_BNEL_I: | |
4145 | s = "bnel"; | |
4146 | likely = 1; | |
4147 | beq_i: | |
4148 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4149 | { | |
17a2f251 | 4150 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4151 | return; |
4152 | } | |
4d34fb5f | 4153 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4154 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
252b5132 RH |
4155 | break; |
4156 | ||
4157 | case M_BGEL: | |
4158 | likely = 1; | |
4159 | case M_BGE: | |
4160 | if (treg == 0) | |
4161 | { | |
17a2f251 TS |
4162 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4163 | "s,p", sreg); | |
252b5132 RH |
4164 | return; |
4165 | } | |
4166 | if (sreg == 0) | |
4167 | { | |
17a2f251 TS |
4168 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4169 | "s,p", treg); | |
252b5132 RH |
4170 | return; |
4171 | } | |
17a2f251 TS |
4172 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4173 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4174 | "s,t,p", AT, 0); | |
252b5132 RH |
4175 | break; |
4176 | ||
4177 | case M_BGTL_I: | |
4178 | likely = 1; | |
4179 | case M_BGT_I: | |
4180 | /* check for > max integer */ | |
4181 | maxnum = 0x7fffffff; | |
ca4e0257 | 4182 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4183 | { |
4184 | maxnum <<= 16; | |
4185 | maxnum |= 0xffff; | |
4186 | maxnum <<= 16; | |
4187 | maxnum |= 0xffff; | |
4188 | } | |
4189 | if (imm_expr.X_op == O_constant | |
4190 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4191 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4192 | { |
4193 | do_false: | |
4194 | /* result is always false */ | |
4195 | if (! likely) | |
78849248 | 4196 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 | 4197 | else |
78849248 | 4198 | macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4199 | return; |
4200 | } | |
4201 | if (imm_expr.X_op != O_constant) | |
4202 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4203 | ++imm_expr.X_add_number; |
252b5132 RH |
4204 | /* FALLTHROUGH */ |
4205 | case M_BGE_I: | |
4206 | case M_BGEL_I: | |
4207 | if (mask == M_BGEL_I) | |
4208 | likely = 1; | |
4209 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4210 | { | |
17a2f251 TS |
4211 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4212 | "s,p", sreg); | |
252b5132 RH |
4213 | return; |
4214 | } | |
4215 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4216 | { | |
17a2f251 TS |
4217 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4218 | "s,p", sreg); | |
252b5132 RH |
4219 | return; |
4220 | } | |
4221 | maxnum = 0x7fffffff; | |
ca4e0257 | 4222 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4223 | { |
4224 | maxnum <<= 16; | |
4225 | maxnum |= 0xffff; | |
4226 | maxnum <<= 16; | |
4227 | maxnum |= 0xffff; | |
4228 | } | |
4229 | maxnum = - maxnum - 1; | |
4230 | if (imm_expr.X_op == O_constant | |
4231 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4232 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4233 | { |
4234 | do_true: | |
4235 | /* result is always true */ | |
4236 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
17a2f251 | 4237 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
4238 | return; |
4239 | } | |
4240 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4241 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4242 | "s,t,p", AT, 0); | |
252b5132 RH |
4243 | break; |
4244 | ||
4245 | case M_BGEUL: | |
4246 | likely = 1; | |
4247 | case M_BGEU: | |
4248 | if (treg == 0) | |
4249 | goto do_true; | |
4250 | if (sreg == 0) | |
4251 | { | |
17a2f251 TS |
4252 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4253 | "s,t,p", 0, treg); | |
252b5132 RH |
4254 | return; |
4255 | } | |
17a2f251 TS |
4256 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4257 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4258 | "s,t,p", AT, 0); | |
252b5132 RH |
4259 | break; |
4260 | ||
4261 | case M_BGTUL_I: | |
4262 | likely = 1; | |
4263 | case M_BGTU_I: | |
4264 | if (sreg == 0 | |
ca4e0257 | 4265 | || (HAVE_32BIT_GPRS |
252b5132 | 4266 | && imm_expr.X_op == O_constant |
956cd1d6 | 4267 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4268 | goto do_false; |
4269 | if (imm_expr.X_op != O_constant) | |
4270 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4271 | ++imm_expr.X_add_number; |
252b5132 RH |
4272 | /* FALLTHROUGH */ |
4273 | case M_BGEU_I: | |
4274 | case M_BGEUL_I: | |
4275 | if (mask == M_BGEUL_I) | |
4276 | likely = 1; | |
4277 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4278 | goto do_true; | |
4279 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4280 | { | |
17a2f251 TS |
4281 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4282 | "s,t,p", sreg, 0); | |
252b5132 RH |
4283 | return; |
4284 | } | |
4285 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4286 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4287 | "s,t,p", AT, 0); | |
252b5132 RH |
4288 | break; |
4289 | ||
4290 | case M_BGTL: | |
4291 | likely = 1; | |
4292 | case M_BGT: | |
4293 | if (treg == 0) | |
4294 | { | |
17a2f251 TS |
4295 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4296 | "s,p", sreg); | |
252b5132 RH |
4297 | return; |
4298 | } | |
4299 | if (sreg == 0) | |
4300 | { | |
17a2f251 TS |
4301 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4302 | "s,p", treg); | |
252b5132 RH |
4303 | return; |
4304 | } | |
17a2f251 TS |
4305 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4306 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4307 | "s,t,p", AT, 0); | |
252b5132 RH |
4308 | break; |
4309 | ||
4310 | case M_BGTUL: | |
4311 | likely = 1; | |
4312 | case M_BGTU: | |
4313 | if (treg == 0) | |
4314 | { | |
17a2f251 TS |
4315 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4316 | "s,t,p", sreg, 0); | |
252b5132 RH |
4317 | return; |
4318 | } | |
4319 | if (sreg == 0) | |
4320 | goto do_false; | |
17a2f251 TS |
4321 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4322 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4323 | "s,t,p", AT, 0); | |
252b5132 RH |
4324 | break; |
4325 | ||
4326 | case M_BLEL: | |
4327 | likely = 1; | |
4328 | case M_BLE: | |
4329 | if (treg == 0) | |
4330 | { | |
17a2f251 TS |
4331 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4332 | "s,p", sreg); | |
252b5132 RH |
4333 | return; |
4334 | } | |
4335 | if (sreg == 0) | |
4336 | { | |
17a2f251 TS |
4337 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4338 | "s,p", treg); | |
252b5132 RH |
4339 | return; |
4340 | } | |
17a2f251 TS |
4341 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4342 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4343 | "s,t,p", AT, 0); | |
252b5132 RH |
4344 | break; |
4345 | ||
4346 | case M_BLEL_I: | |
4347 | likely = 1; | |
4348 | case M_BLE_I: | |
4349 | maxnum = 0x7fffffff; | |
ca4e0257 | 4350 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4351 | { |
4352 | maxnum <<= 16; | |
4353 | maxnum |= 0xffff; | |
4354 | maxnum <<= 16; | |
4355 | maxnum |= 0xffff; | |
4356 | } | |
4357 | if (imm_expr.X_op == O_constant | |
4358 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4359 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4360 | goto do_true; |
4361 | if (imm_expr.X_op != O_constant) | |
4362 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4363 | ++imm_expr.X_add_number; |
252b5132 RH |
4364 | /* FALLTHROUGH */ |
4365 | case M_BLT_I: | |
4366 | case M_BLTL_I: | |
4367 | if (mask == M_BLTL_I) | |
4368 | likely = 1; | |
4369 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4370 | { | |
17a2f251 TS |
4371 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4372 | "s,p", sreg); | |
252b5132 RH |
4373 | return; |
4374 | } | |
4375 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4376 | { | |
17a2f251 TS |
4377 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4378 | "s,p", sreg); | |
252b5132 RH |
4379 | return; |
4380 | } | |
4381 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4382 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4383 | "s,t,p", AT, 0); | |
252b5132 RH |
4384 | break; |
4385 | ||
4386 | case M_BLEUL: | |
4387 | likely = 1; | |
4388 | case M_BLEU: | |
4389 | if (treg == 0) | |
4390 | { | |
17a2f251 TS |
4391 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4392 | "s,t,p", sreg, 0); | |
252b5132 RH |
4393 | return; |
4394 | } | |
4395 | if (sreg == 0) | |
4396 | goto do_true; | |
17a2f251 TS |
4397 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4398 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4399 | "s,t,p", AT, 0); | |
252b5132 RH |
4400 | break; |
4401 | ||
4402 | case M_BLEUL_I: | |
4403 | likely = 1; | |
4404 | case M_BLEU_I: | |
4405 | if (sreg == 0 | |
ca4e0257 | 4406 | || (HAVE_32BIT_GPRS |
252b5132 | 4407 | && imm_expr.X_op == O_constant |
956cd1d6 | 4408 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4409 | goto do_true; |
4410 | if (imm_expr.X_op != O_constant) | |
4411 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4412 | ++imm_expr.X_add_number; |
252b5132 RH |
4413 | /* FALLTHROUGH */ |
4414 | case M_BLTU_I: | |
4415 | case M_BLTUL_I: | |
4416 | if (mask == M_BLTUL_I) | |
4417 | likely = 1; | |
4418 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4419 | goto do_false; | |
4420 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4421 | { | |
17a2f251 | 4422 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4423 | "s,t,p", sreg, 0); |
4424 | return; | |
4425 | } | |
4426 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4427 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4428 | "s,t,p", AT, 0); | |
252b5132 RH |
4429 | break; |
4430 | ||
4431 | case M_BLTL: | |
4432 | likely = 1; | |
4433 | case M_BLT: | |
4434 | if (treg == 0) | |
4435 | { | |
17a2f251 TS |
4436 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4437 | "s,p", sreg); | |
252b5132 RH |
4438 | return; |
4439 | } | |
4440 | if (sreg == 0) | |
4441 | { | |
17a2f251 TS |
4442 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4443 | "s,p", treg); | |
252b5132 RH |
4444 | return; |
4445 | } | |
17a2f251 TS |
4446 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4447 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4448 | "s,t,p", AT, 0); | |
252b5132 RH |
4449 | break; |
4450 | ||
4451 | case M_BLTUL: | |
4452 | likely = 1; | |
4453 | case M_BLTU: | |
4454 | if (treg == 0) | |
4455 | goto do_false; | |
4456 | if (sreg == 0) | |
4457 | { | |
17a2f251 TS |
4458 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4459 | "s,t,p", 0, treg); | |
252b5132 RH |
4460 | return; |
4461 | } | |
17a2f251 TS |
4462 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4463 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4464 | "s,t,p", AT, 0); | |
252b5132 RH |
4465 | break; |
4466 | ||
5f74bc13 CD |
4467 | case M_DEXT: |
4468 | { | |
4469 | unsigned long pos; | |
4470 | unsigned long size; | |
4471 | ||
4472 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4473 | { | |
4474 | as_bad (_("Unsupported large constant")); | |
4475 | pos = size = 1; | |
4476 | } | |
4477 | else | |
4478 | { | |
4479 | pos = (unsigned long) imm_expr.X_add_number; | |
4480 | size = (unsigned long) imm2_expr.X_add_number; | |
4481 | } | |
4482 | ||
4483 | if (pos > 63) | |
4484 | { | |
4485 | as_bad (_("Improper position (%lu)"), pos); | |
4486 | pos = 1; | |
4487 | } | |
4488 | if (size == 0 || size > 64 | |
4489 | || (pos + size - 1) > 63) | |
4490 | { | |
4491 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4492 | size, pos); | |
4493 | size = 1; | |
4494 | } | |
4495 | ||
4496 | if (size <= 32 && pos < 32) | |
4497 | { | |
4498 | s = "dext"; | |
4499 | fmt = "t,r,+A,+C"; | |
4500 | } | |
4501 | else if (size <= 32) | |
4502 | { | |
4503 | s = "dextu"; | |
4504 | fmt = "t,r,+E,+H"; | |
4505 | } | |
4506 | else | |
4507 | { | |
4508 | s = "dextm"; | |
4509 | fmt = "t,r,+A,+G"; | |
4510 | } | |
4511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
4512 | fmt, treg, sreg, pos, size - 1); | |
4513 | } | |
4514 | return; | |
4515 | ||
4516 | case M_DINS: | |
4517 | { | |
4518 | unsigned long pos; | |
4519 | unsigned long size; | |
4520 | ||
4521 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4522 | { | |
4523 | as_bad (_("Unsupported large constant")); | |
4524 | pos = size = 1; | |
4525 | } | |
4526 | else | |
4527 | { | |
4528 | pos = (unsigned long) imm_expr.X_add_number; | |
4529 | size = (unsigned long) imm2_expr.X_add_number; | |
4530 | } | |
4531 | ||
4532 | if (pos > 63) | |
4533 | { | |
4534 | as_bad (_("Improper position (%lu)"), pos); | |
4535 | pos = 1; | |
4536 | } | |
4537 | if (size == 0 || size > 64 | |
4538 | || (pos + size - 1) > 63) | |
4539 | { | |
4540 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4541 | size, pos); | |
4542 | size = 1; | |
4543 | } | |
4544 | ||
4545 | if (pos < 32 && (pos + size - 1) < 32) | |
4546 | { | |
4547 | s = "dins"; | |
4548 | fmt = "t,r,+A,+B"; | |
4549 | } | |
4550 | else if (pos >= 32) | |
4551 | { | |
4552 | s = "dinsu"; | |
4553 | fmt = "t,r,+E,+F"; | |
4554 | } | |
4555 | else | |
4556 | { | |
4557 | s = "dinsm"; | |
4558 | fmt = "t,r,+A,+F"; | |
4559 | } | |
4560 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
4561 | fmt, treg, sreg, pos, pos + size - 1); | |
4562 | } | |
4563 | return; | |
4564 | ||
252b5132 RH |
4565 | case M_DDIV_3: |
4566 | dbl = 1; | |
4567 | case M_DIV_3: | |
4568 | s = "mflo"; | |
4569 | goto do_div3; | |
4570 | case M_DREM_3: | |
4571 | dbl = 1; | |
4572 | case M_REM_3: | |
4573 | s = "mfhi"; | |
4574 | do_div3: | |
4575 | if (treg == 0) | |
4576 | { | |
4577 | as_warn (_("Divide by zero.")); | |
4578 | if (mips_trap) | |
17a2f251 | 4579 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4580 | else |
17a2f251 | 4581 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4582 | return; |
4583 | } | |
4584 | ||
b34976b6 | 4585 | mips_emit_delays (TRUE); |
252b5132 RH |
4586 | ++mips_opts.noreorder; |
4587 | mips_any_noreorder = 1; | |
4588 | if (mips_trap) | |
4589 | { | |
17a2f251 TS |
4590 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4591 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4592 | sreg, treg); | |
252b5132 RH |
4593 | } |
4594 | else | |
4595 | { | |
4596 | expr1.X_add_number = 8; | |
17a2f251 TS |
4597 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4598 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4599 | sreg, treg); | |
bf151ce7 | 4600 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4601 | } |
4602 | expr1.X_add_number = -1; | |
17a2f251 TS |
4603 | macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j", |
4604 | AT, 0, BFD_RELOC_LO16); | |
252b5132 | 4605 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
17a2f251 | 4606 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4607 | if (dbl) |
4608 | { | |
4609 | expr1.X_add_number = 1; | |
17a2f251 TS |
4610 | macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
4611 | BFD_RELOC_LO16); | |
4612 | macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31); | |
252b5132 RH |
4613 | } |
4614 | else | |
4615 | { | |
4616 | expr1.X_add_number = 0x80000000; | |
17a2f251 TS |
4617 | macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT, |
4618 | BFD_RELOC_HI16); | |
252b5132 RH |
4619 | } |
4620 | if (mips_trap) | |
4621 | { | |
17a2f251 | 4622 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4623 | /* We want to close the noreorder block as soon as possible, so |
4624 | that later insns are available for delay slot filling. */ | |
4625 | --mips_opts.noreorder; | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | expr1.X_add_number = 8; | |
17a2f251 TS |
4630 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); |
4631 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
252b5132 RH |
4632 | |
4633 | /* We want to close the noreorder block as soon as possible, so | |
4634 | that later insns are available for delay slot filling. */ | |
4635 | --mips_opts.noreorder; | |
4636 | ||
17a2f251 | 4637 | macro_build (NULL, &icnt, NULL, "break", "c", 6); |
252b5132 | 4638 | } |
17a2f251 | 4639 | macro_build (NULL, &icnt, NULL, s, "d", dreg); |
252b5132 RH |
4640 | break; |
4641 | ||
4642 | case M_DIV_3I: | |
4643 | s = "div"; | |
4644 | s2 = "mflo"; | |
4645 | goto do_divi; | |
4646 | case M_DIVU_3I: | |
4647 | s = "divu"; | |
4648 | s2 = "mflo"; | |
4649 | goto do_divi; | |
4650 | case M_REM_3I: | |
4651 | s = "div"; | |
4652 | s2 = "mfhi"; | |
4653 | goto do_divi; | |
4654 | case M_REMU_3I: | |
4655 | s = "divu"; | |
4656 | s2 = "mfhi"; | |
4657 | goto do_divi; | |
4658 | case M_DDIV_3I: | |
4659 | dbl = 1; | |
4660 | s = "ddiv"; | |
4661 | s2 = "mflo"; | |
4662 | goto do_divi; | |
4663 | case M_DDIVU_3I: | |
4664 | dbl = 1; | |
4665 | s = "ddivu"; | |
4666 | s2 = "mflo"; | |
4667 | goto do_divi; | |
4668 | case M_DREM_3I: | |
4669 | dbl = 1; | |
4670 | s = "ddiv"; | |
4671 | s2 = "mfhi"; | |
4672 | goto do_divi; | |
4673 | case M_DREMU_3I: | |
4674 | dbl = 1; | |
4675 | s = "ddivu"; | |
4676 | s2 = "mfhi"; | |
4677 | do_divi: | |
4678 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4679 | { | |
4680 | as_warn (_("Divide by zero.")); | |
4681 | if (mips_trap) | |
17a2f251 | 4682 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4683 | else |
17a2f251 | 4684 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4685 | return; |
4686 | } | |
4687 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4688 | { | |
4689 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4690 | move_register (&icnt, dreg, sreg); |
252b5132 | 4691 | else |
ea1fb5dc | 4692 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4693 | return; |
4694 | } | |
4695 | if (imm_expr.X_op == O_constant | |
4696 | && imm_expr.X_add_number == -1 | |
4697 | && s[strlen (s) - 1] != 'u') | |
4698 | { | |
4699 | if (strcmp (s2, "mflo") == 0) | |
4700 | { | |
17a2f251 TS |
4701 | macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w", |
4702 | dreg, sreg); | |
252b5132 RH |
4703 | } |
4704 | else | |
ea1fb5dc | 4705 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4706 | return; |
4707 | } | |
4708 | ||
4709 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
4710 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4711 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); | |
252b5132 RH |
4712 | break; |
4713 | ||
4714 | case M_DIVU_3: | |
4715 | s = "divu"; | |
4716 | s2 = "mflo"; | |
4717 | goto do_divu3; | |
4718 | case M_REMU_3: | |
4719 | s = "divu"; | |
4720 | s2 = "mfhi"; | |
4721 | goto do_divu3; | |
4722 | case M_DDIVU_3: | |
4723 | s = "ddivu"; | |
4724 | s2 = "mflo"; | |
4725 | goto do_divu3; | |
4726 | case M_DREMU_3: | |
4727 | s = "ddivu"; | |
4728 | s2 = "mfhi"; | |
4729 | do_divu3: | |
b34976b6 | 4730 | mips_emit_delays (TRUE); |
252b5132 RH |
4731 | ++mips_opts.noreorder; |
4732 | mips_any_noreorder = 1; | |
4733 | if (mips_trap) | |
4734 | { | |
17a2f251 TS |
4735 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4736 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4737 | /* We want to close the noreorder block as soon as possible, so |
4738 | that later insns are available for delay slot filling. */ | |
4739 | --mips_opts.noreorder; | |
4740 | } | |
4741 | else | |
4742 | { | |
4743 | expr1.X_add_number = 8; | |
17a2f251 TS |
4744 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4745 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4746 | |
4747 | /* We want to close the noreorder block as soon as possible, so | |
4748 | that later insns are available for delay slot filling. */ | |
4749 | --mips_opts.noreorder; | |
17a2f251 | 4750 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 | 4751 | } |
17a2f251 | 4752 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); |
252b5132 RH |
4753 | return; |
4754 | ||
1abe91b1 MR |
4755 | case M_DLCA_AB: |
4756 | dbl = 1; | |
4757 | case M_LCA_AB: | |
4758 | call = 1; | |
4759 | goto do_la; | |
252b5132 RH |
4760 | case M_DLA_AB: |
4761 | dbl = 1; | |
4762 | case M_LA_AB: | |
1abe91b1 | 4763 | do_la: |
252b5132 RH |
4764 | /* Load the address of a symbol into a register. If breg is not |
4765 | zero, we then add a base register to it. */ | |
4766 | ||
3bec30a8 TS |
4767 | if (dbl && HAVE_32BIT_GPRS) |
4768 | as_warn (_("dla used to load 32-bit register")); | |
4769 | ||
c90bbe5b | 4770 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4771 | as_warn (_("la used to load 64-bit address")); |
4772 | ||
0c11417f MR |
4773 | if (offset_expr.X_op == O_constant |
4774 | && offset_expr.X_add_number >= -0x8000 | |
4775 | && offset_expr.X_add_number < 0x8000) | |
4776 | { | |
17a2f251 | 4777 | macro_build (NULL, &icnt, &offset_expr, |
b7c7d6c1 | 4778 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4779 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4780 | return; |
4781 | } | |
4782 | ||
afdbd6d0 CD |
4783 | if (treg == breg) |
4784 | { | |
4785 | tempreg = AT; | |
4786 | used_at = 1; | |
4787 | } | |
4788 | else | |
4789 | { | |
4790 | tempreg = treg; | |
4791 | used_at = 0; | |
4792 | } | |
4793 | ||
252b5132 RH |
4794 | /* When generating embedded PIC code, we permit expressions of |
4795 | the form | |
afdbd6d0 CD |
4796 | la $treg,foo-bar |
4797 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4798 | where bar is an address in the current section. These are used |
252b5132 RH |
4799 | when getting the addresses of functions. We don't permit |
4800 | X_add_number to be non-zero, because if the symbol is | |
4801 | external the relaxing code needs to know that any addend is | |
4802 | purely the offset to X_op_symbol. */ | |
4803 | if (mips_pic == EMBEDDED_PIC | |
4804 | && offset_expr.X_op == O_subtract | |
49309057 | 4805 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4806 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4807 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4808 | && (S_GET_SEGMENT | |
4809 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4810 | ->X_add_symbol) | |
bb2d6cd7 | 4811 | == now_seg))) |
bb2d6cd7 GK |
4812 | && (offset_expr.X_add_number == 0 |
4813 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4814 | { |
afdbd6d0 CD |
4815 | if (breg == 0) |
4816 | { | |
4817 | tempreg = treg; | |
4818 | used_at = 0; | |
17a2f251 TS |
4819 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4820 | BFD_RELOC_PCREL_HI16_S); | |
afdbd6d0 CD |
4821 | } |
4822 | else | |
4823 | { | |
17a2f251 TS |
4824 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4825 | BFD_RELOC_PCREL_HI16_S); | |
4826 | macro_build (NULL, &icnt, NULL, | |
4d34fb5f | 4827 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4828 | "d,v,t", tempreg, tempreg, breg); |
4829 | } | |
17a2f251 | 4830 | macro_build (NULL, &icnt, &offset_expr, |
4d34fb5f | 4831 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4832 | "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); |
afdbd6d0 CD |
4833 | if (! used_at) |
4834 | return; | |
4835 | break; | |
252b5132 RH |
4836 | } |
4837 | ||
4838 | if (offset_expr.X_op != O_symbol | |
4839 | && offset_expr.X_op != O_constant) | |
4840 | { | |
4841 | as_bad (_("expression too complex")); | |
4842 | offset_expr.X_op = O_constant; | |
4843 | } | |
4844 | ||
252b5132 | 4845 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4846 | load_register (&icnt, tempreg, &offset_expr, |
4847 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4848 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4849 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4850 | else if (mips_pic == NO_PIC) |
4851 | { | |
d6bc6245 | 4852 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4853 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4854 | Otherwise we want |
4855 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4856 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4857 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4858 | so we may as well always use the latter form. |
76b3015f | 4859 | |
d6bc6245 TS |
4860 | With 64bit address space and a usable $at we want |
4861 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4862 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4863 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4864 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4865 | dsll32 $tempreg,0 | |
3a482fd5 | 4866 | daddu $tempreg,$tempreg,$at |
76b3015f | 4867 | |
c03099e6 | 4868 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4869 | on superscalar processors. |
4870 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4871 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4872 | dsll $tempreg,16 | |
4873 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4874 | dsll $tempreg,16 | |
4875 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4876 | */ | |
f9419b05 | 4877 | char *p = NULL; |
d6bc6245 | 4878 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4879 | { |
d6bc6245 TS |
4880 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4881 | hold the data for such large chunks. */ | |
4882 | ||
460597ba | 4883 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4884 | { |
4885 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4886 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4887 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 4888 | AT, BFD_RELOC_HI16_S); |
98d3f06f | 4889 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4890 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
98d3f06f | 4891 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4892 | AT, AT, BFD_RELOC_LO16); |
4893 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
4894 | tempreg, tempreg, 0); | |
4895 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
4896 | tempreg, tempreg, AT); | |
98d3f06f KH |
4897 | used_at = 1; |
4898 | } | |
4899 | else | |
4900 | { | |
4901 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4902 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4903 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4904 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
4905 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4906 | tempreg, tempreg, 16); |
4907 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 TS |
4908 | tempreg, tempreg, BFD_RELOC_HI16_S); |
4909 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4910 | tempreg, tempreg, 16); |
4911 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4912 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4913 | } |
4914 | } | |
4915 | else | |
4916 | { | |
4917 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4918 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4919 | { | |
4920 | frag_grow (20); | |
17a2f251 TS |
4921 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
4922 | "t,r,j", tempreg, mips_gp_register, | |
4923 | BFD_RELOC_GPREL16); | |
98d3f06f KH |
4924 | p = frag_var (rs_machine_dependent, 8, 0, |
4925 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4926 | mips_opts.warn_about_macros), | |
4927 | offset_expr.X_add_symbol, 0, NULL); | |
4928 | } | |
4929 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4930 | if (p != NULL) | |
4931 | p += 4; | |
f899b4b8 | 4932 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4933 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4934 | } |
252b5132 | 4935 | } |
f5040a92 | 4936 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4937 | { |
9117d219 NC |
4938 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4939 | ||
252b5132 RH |
4940 | /* If this is a reference to an external symbol, and there |
4941 | is no constant, we want | |
4942 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4943 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4944 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4945 | For a local symbol, we want |
4946 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4947 | nop | |
4948 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4949 | ||
4950 | If we have a small constant, and this is a reference to | |
4951 | an external symbol, we want | |
4952 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4953 | nop | |
4954 | addiu $tempreg,$tempreg,<constant> | |
4955 | For a local symbol, we want the same instruction | |
4956 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4957 | addiu instruction. | |
4958 | ||
4959 | If we have a large constant, and this is a reference to | |
4960 | an external symbol, we want | |
4961 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4962 | lui $at,<hiconstant> | |
4963 | addiu $at,$at,<loconstant> | |
4964 | addu $tempreg,$tempreg,$at | |
4965 | For a local symbol, we want the same instruction | |
4966 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4967 | addiu instruction. |
ed6fb7bd SC |
4968 | */ |
4969 | ||
252b5132 RH |
4970 | expr1.X_add_number = offset_expr.X_add_number; |
4971 | offset_expr.X_add_number = 0; | |
4972 | frag_grow (32); | |
1abe91b1 MR |
4973 | if (expr1.X_add_number == 0 && breg == 0 |
4974 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 | 4975 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
17a2f251 TS |
4976 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
4977 | tempreg, lw_reloc_type, mips_gp_register); | |
252b5132 RH |
4978 | if (expr1.X_add_number == 0) |
4979 | { | |
4980 | int off; | |
f9419b05 | 4981 | char *p; |
252b5132 RH |
4982 | |
4983 | if (breg == 0) | |
4984 | off = 0; | |
4985 | else | |
4986 | { | |
4987 | /* We're going to put in an addu instruction using | |
4988 | tempreg, so we may as well insert the nop right | |
4989 | now. */ | |
17a2f251 | 4990 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
4991 | off = 4; |
4992 | } | |
4993 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4994 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4995 | (breg == 0 | |
4996 | ? mips_opts.warn_about_macros | |
4997 | : 0)), | |
c4e7957c | 4998 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4999 | if (breg == 0) |
5000 | { | |
17a2f251 | 5001 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5002 | p += 4; |
5003 | } | |
f899b4b8 | 5004 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 5005 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5006 | /* FIXME: If breg == 0, and the next instruction uses |
5007 | $tempreg, then if this variant case is used an extra | |
5008 | nop will be generated. */ | |
5009 | } | |
5010 | else if (expr1.X_add_number >= -0x8000 | |
5011 | && expr1.X_add_number < 0x8000) | |
5012 | { | |
17a2f251 TS |
5013 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5014 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5015 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
c4e7957c TS |
5016 | frag_var (rs_machine_dependent, 0, 0, |
5017 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
5018 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5019 | } |
5020 | else | |
5021 | { | |
5022 | int off1; | |
5023 | ||
5024 | /* If we are going to add in a base register, and the | |
5025 | target register and the base register are the same, | |
5026 | then we are using AT as a temporary register. Since | |
5027 | we want to load the constant into AT, we add our | |
5028 | current AT (from the global offset table) and the | |
5029 | register into the register now, and pretend we were | |
5030 | not using a base register. */ | |
5031 | if (breg != treg) | |
5032 | off1 = 0; | |
5033 | else | |
5034 | { | |
17a2f251 TS |
5035 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5036 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5037 | treg, AT, breg); | |
252b5132 RH |
5038 | breg = 0; |
5039 | tempreg = treg; | |
5040 | off1 = -8; | |
5041 | } | |
5042 | ||
5043 | /* Set mips_optimize around the lui instruction to avoid | |
5044 | inserting an unnecessary nop after the lw. */ | |
5045 | hold_mips_optimize = mips_optimize; | |
5046 | mips_optimize = 2; | |
c4e7957c | 5047 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5048 | mips_optimize = hold_mips_optimize; |
5049 | ||
17a2f251 TS |
5050 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5051 | AT, AT, BFD_RELOC_LO16); | |
5052 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5053 | tempreg, tempreg, AT); | |
c4e7957c TS |
5054 | frag_var (rs_machine_dependent, 0, 0, |
5055 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
5056 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5057 | used_at = 1; |
5058 | } | |
5059 | } | |
f5040a92 AO |
5060 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5061 | { | |
5062 | char *p = NULL; | |
5063 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
5064 | int adj = 0; | |
5065 | ||
5066 | /* If this is a reference to an external, and there is no | |
5067 | constant, or local symbol (*), with or without a | |
5068 | constant, we want | |
5069 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5070 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5071 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5072 | ||
5073 | If we have a small constant, and this is a reference to | |
5074 | an external symbol, we want | |
5075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5076 | addiu $tempreg,$tempreg,<constant> | |
5077 | ||
5078 | If we have a large constant, and this is a reference to | |
5079 | an external symbol, we want | |
5080 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5081 | lui $at,<hiconstant> | |
5082 | addiu $at,$at,<loconstant> | |
5083 | addu $tempreg,$tempreg,$at | |
5084 | ||
5085 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5086 | local symbols, even though it introduces an additional | |
5087 | instruction. */ | |
5088 | ||
5089 | frag_grow (28); | |
1abe91b1 MR |
5090 | if (offset_expr.X_add_number == 0 && breg == 0 |
5091 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5092 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5093 | if (offset_expr.X_add_number) | |
5094 | { | |
5095 | frag_now->tc_frag_data.tc_fr_offset = | |
5096 | expr1.X_add_number = offset_expr.X_add_number; | |
5097 | offset_expr.X_add_number = 0; | |
5098 | ||
17a2f251 TS |
5099 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5100 | "t,o(b)", tempreg, lw_reloc_type, | |
5101 | mips_gp_register); | |
f5040a92 AO |
5102 | |
5103 | if (expr1.X_add_number >= -0x8000 | |
5104 | && expr1.X_add_number < 0x8000) | |
5105 | { | |
17a2f251 TS |
5106 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
5107 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
5108 | p = frag_var (rs_machine_dependent, 4, 0, |
5109 | RELAX_ENCODE (8, 4, 0, 0, 0, 0), | |
5110 | offset_expr.X_add_symbol, 0, NULL); | |
5111 | } | |
ecd13cd3 | 5112 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5113 | { |
5114 | int dreg; | |
5115 | ||
5116 | /* If we are going to add in a base register, and the | |
5117 | target register and the base register are the same, | |
5118 | then we are using AT as a temporary register. Since | |
5119 | we want to load the constant into AT, we add our | |
5120 | current AT (from the global offset table) and the | |
5121 | register into the register now, and pretend we were | |
5122 | not using a base register. */ | |
5123 | if (breg != treg) | |
5124 | dreg = tempreg; | |
5125 | else | |
5126 | { | |
5127 | assert (tempreg == AT); | |
bf151ce7 | 5128 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, |
17a2f251 | 5129 | "d,v,t", treg, AT, breg); |
f5040a92 AO |
5130 | dreg = treg; |
5131 | adj = 4; | |
5132 | } | |
5133 | ||
17a2f251 TS |
5134 | macro_build_lui (NULL, &icnt, &expr1, AT); |
5135 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5136 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
5137 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5138 | dreg, dreg, AT); | |
f5040a92 AO |
5139 | |
5140 | p = frag_var (rs_machine_dependent, 4 + adj, 0, | |
5141 | RELAX_ENCODE (16 + adj, 4 + adj, | |
5142 | 0, 0, 0, 0), | |
5143 | offset_expr.X_add_symbol, 0, NULL); | |
5144 | ||
5145 | used_at = 1; | |
5146 | } | |
5147 | else | |
5148 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5149 | ||
5150 | offset_expr.X_add_number = expr1.X_add_number; | |
5151 | ||
f899b4b8 | 5152 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 | 5153 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP, |
f5040a92 AO |
5154 | mips_gp_register); |
5155 | if (adj) | |
5156 | { | |
17a2f251 | 5157 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5158 | treg, tempreg, breg); |
f5040a92 AO |
5159 | breg = 0; |
5160 | tempreg = treg; | |
5161 | } | |
5162 | } | |
5163 | else | |
5164 | { | |
17a2f251 TS |
5165 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5166 | "t,o(b)", tempreg, lw_reloc_type, | |
5167 | mips_gp_register); | |
f5040a92 AO |
5168 | if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP) |
5169 | p = frag_var (rs_machine_dependent, 0, 0, | |
5170 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5171 | offset_expr.X_add_symbol, 0, NULL); | |
5172 | } | |
5173 | ||
5174 | if (! p) | |
5175 | { | |
5176 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5177 | that this does not become a variant frag. */ | |
5178 | frag_wane (frag_now); | |
5179 | frag_new (0); | |
5180 | } | |
5181 | } | |
5182 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 RH |
5183 | { |
5184 | int gpdel; | |
f9419b05 | 5185 | char *p; |
9117d219 NC |
5186 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5187 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5188 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5189 | |
5190 | /* This is the large GOT case. If this is a reference to an | |
5191 | external symbol, and there is no constant, we want | |
5192 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5193 | addu $tempreg,$tempreg,$gp | |
5194 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5195 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5196 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5197 | addu $tempreg,$tempreg,$gp | |
5198 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5199 | For a local symbol, we want |
5200 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5201 | nop | |
5202 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5203 | ||
5204 | If we have a small constant, and this is a reference to | |
5205 | an external symbol, we want | |
5206 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5207 | addu $tempreg,$tempreg,$gp | |
5208 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5209 | nop | |
5210 | addiu $tempreg,$tempreg,<constant> | |
5211 | For a local symbol, we want | |
5212 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5213 | nop | |
5214 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5215 | ||
5216 | If we have a large constant, and this is a reference to | |
5217 | an external symbol, we want | |
5218 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5219 | addu $tempreg,$tempreg,$gp | |
5220 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5221 | lui $at,<hiconstant> | |
5222 | addiu $at,$at,<loconstant> | |
5223 | addu $tempreg,$tempreg,$at | |
5224 | For a local symbol, we want | |
5225 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5226 | lui $at,<hiconstant> | |
5227 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5228 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5229 | */ |
438c16b8 | 5230 | |
252b5132 RH |
5231 | expr1.X_add_number = offset_expr.X_add_number; |
5232 | offset_expr.X_add_number = 0; | |
5233 | frag_grow (52); | |
f7ea7ef2 | 5234 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5235 | gpdel = 4; |
5236 | else | |
5237 | gpdel = 0; | |
1abe91b1 MR |
5238 | if (expr1.X_add_number == 0 && breg == 0 |
5239 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5240 | { |
5241 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5242 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5243 | } | |
17a2f251 | 5244 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5245 | tempreg, lui_reloc_type); |
17a2f251 TS |
5246 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5247 | tempreg, tempreg, mips_gp_register); | |
5248 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5249 | tempreg, lw_reloc_type, tempreg); | |
252b5132 RH |
5250 | if (expr1.X_add_number == 0) |
5251 | { | |
5252 | int off; | |
5253 | ||
5254 | if (breg == 0) | |
5255 | off = 0; | |
5256 | else | |
5257 | { | |
5258 | /* We're going to put in an addu instruction using | |
5259 | tempreg, so we may as well insert the nop right | |
5260 | now. */ | |
17a2f251 | 5261 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
5262 | off = 4; |
5263 | } | |
5264 | ||
5265 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5266 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5267 | 8 + gpdel, 0, | |
5268 | (breg == 0 | |
5269 | ? mips_opts.warn_about_macros | |
5270 | : 0)), | |
c4e7957c | 5271 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5272 | } |
5273 | else if (expr1.X_add_number >= -0x8000 | |
5274 | && expr1.X_add_number < 0x8000) | |
5275 | { | |
17a2f251 TS |
5276 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5277 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
5278 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 RH |
5279 | |
5280 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5281 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5282 | (breg == 0 | |
5283 | ? mips_opts.warn_about_macros | |
5284 | : 0)), | |
c4e7957c | 5285 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5286 | } |
5287 | else | |
5288 | { | |
5289 | int adj, dreg; | |
5290 | ||
5291 | /* If we are going to add in a base register, and the | |
5292 | target register and the base register are the same, | |
5293 | then we are using AT as a temporary register. Since | |
5294 | we want to load the constant into AT, we add our | |
5295 | current AT (from the global offset table) and the | |
5296 | register into the register now, and pretend we were | |
5297 | not using a base register. */ | |
5298 | if (breg != treg) | |
5299 | { | |
5300 | adj = 0; | |
5301 | dreg = tempreg; | |
5302 | } | |
5303 | else | |
5304 | { | |
5305 | assert (tempreg == AT); | |
17a2f251 TS |
5306 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5307 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5308 | treg, AT, breg); | |
252b5132 RH |
5309 | dreg = treg; |
5310 | adj = 8; | |
5311 | } | |
5312 | ||
5313 | /* Set mips_optimize around the lui instruction to avoid | |
5314 | inserting an unnecessary nop after the lw. */ | |
5315 | hold_mips_optimize = mips_optimize; | |
5316 | mips_optimize = 2; | |
c4e7957c | 5317 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5318 | mips_optimize = hold_mips_optimize; |
5319 | ||
17a2f251 TS |
5320 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5321 | AT, AT, BFD_RELOC_LO16); | |
5322 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5323 | dreg, dreg, AT); | |
252b5132 RH |
5324 | |
5325 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5326 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5327 | 8 + gpdel, 0, | |
5328 | (breg == 0 | |
5329 | ? mips_opts.warn_about_macros | |
5330 | : 0)), | |
c4e7957c | 5331 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5332 | |
5333 | used_at = 1; | |
5334 | } | |
5335 | ||
5336 | if (gpdel > 0) | |
5337 | { | |
5338 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5339 | the first instruction on the main stream does not. */ |
17a2f251 | 5340 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5341 | p += 4; |
5342 | } | |
ed6fb7bd | 5343 | |
f899b4b8 TS |
5344 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5345 | tempreg, local_reloc_type, mips_gp_register); | |
252b5132 | 5346 | p += 4; |
f5040a92 | 5347 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5348 | && expr1.X_add_number < 0x8000) |
5349 | { | |
17a2f251 | 5350 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5351 | p += 4; |
f899b4b8 | 5352 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 5353 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 5354 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5355 | register, the external symbol case ended with a load, |
5356 | so if the symbol turns out to not be external, and | |
5357 | the next instruction uses tempreg, an unnecessary nop | |
5358 | will be inserted. */ | |
252b5132 RH |
5359 | } |
5360 | else | |
5361 | { | |
5362 | if (breg == treg) | |
5363 | { | |
5364 | /* We must add in the base register now, as in the | |
f5040a92 | 5365 | external symbol case. */ |
252b5132 | 5366 | assert (tempreg == AT); |
17a2f251 | 5367 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5368 | p += 4; |
17a2f251 TS |
5369 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5370 | treg, AT, breg); | |
252b5132 RH |
5371 | p += 4; |
5372 | tempreg = treg; | |
5373 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5374 | it in in both cases. */ |
252b5132 RH |
5375 | breg = 0; |
5376 | } | |
5377 | ||
5378 | macro_build_lui (p, &icnt, &expr1, AT); | |
5379 | p += 4; | |
17a2f251 TS |
5380 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5381 | AT, AT, BFD_RELOC_LO16); | |
252b5132 | 5382 | p += 4; |
17a2f251 TS |
5383 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5384 | tempreg, tempreg, AT); | |
252b5132 RH |
5385 | p += 4; |
5386 | } | |
5387 | } | |
f5040a92 AO |
5388 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5389 | { | |
5390 | char *p = NULL; | |
5391 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; | |
5392 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
5393 | int adj = 0; | |
5394 | ||
5395 | /* This is the large GOT case. If this is a reference to an | |
5396 | external symbol, and there is no constant, we want | |
5397 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5398 | add $tempreg,$tempreg,$gp | |
5399 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5400 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5401 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5402 | add $tempreg,$tempreg,$gp | |
5403 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5404 | ||
5405 | If we have a small constant, and this is a reference to | |
5406 | an external symbol, we want | |
5407 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5408 | add $tempreg,$tempreg,$gp | |
5409 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5410 | addi $tempreg,$tempreg,<constant> | |
5411 | ||
5412 | If we have a large constant, and this is a reference to | |
5413 | an external symbol, we want | |
5414 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5415 | addu $tempreg,$tempreg,$gp | |
5416 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5417 | lui $at,<hiconstant> | |
5418 | addi $at,$at,<loconstant> | |
5419 | add $tempreg,$tempreg,$at | |
5420 | ||
5421 | If we have NewABI, and we know it's a local symbol, we want | |
5422 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5423 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5424 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5425 | ||
5426 | frag_grow (40); | |
5427 | ||
5428 | frag_now->tc_frag_data.tc_fr_offset = | |
5429 | expr1.X_add_number = offset_expr.X_add_number; | |
5430 | offset_expr.X_add_number = 0; | |
5431 | ||
1abe91b1 MR |
5432 | if (expr1.X_add_number == 0 && breg == 0 |
5433 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5434 | { |
5435 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5436 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5437 | } | |
17a2f251 | 5438 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
f5040a92 | 5439 | tempreg, lui_reloc_type); |
17a2f251 TS |
5440 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5441 | tempreg, tempreg, mips_gp_register); | |
5442 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
5443 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
5444 | ||
5445 | if (expr1.X_add_number == 0) | |
5446 | { | |
5447 | p = frag_var (rs_machine_dependent, 8, 0, | |
5448 | RELAX_ENCODE (12, 8, 0, 4, 0, | |
5449 | mips_opts.warn_about_macros), | |
5450 | offset_expr.X_add_symbol, 0, NULL); | |
684022ea | 5451 | } |
f5040a92 AO |
5452 | else if (expr1.X_add_number >= -0x8000 |
5453 | && expr1.X_add_number < 0x8000) | |
5454 | { | |
17a2f251 TS |
5455 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5456 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
5457 | p = frag_var (rs_machine_dependent, 8, 0, |
5458 | RELAX_ENCODE (16, 8, 0, 4, 0, | |
5459 | mips_opts.warn_about_macros), | |
5460 | offset_expr.X_add_symbol, 0, NULL); | |
5461 | } | |
ecd13cd3 | 5462 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5463 | { |
5464 | int dreg; | |
5465 | ||
5466 | /* If we are going to add in a base register, and the | |
5467 | target register and the base register are the same, | |
5468 | then we are using AT as a temporary register. Since | |
5469 | we want to load the constant into AT, we add our | |
5470 | current AT (from the global offset table) and the | |
5471 | register into the register now, and pretend we were | |
5472 | not using a base register. */ | |
5473 | if (breg != treg) | |
5474 | dreg = tempreg; | |
5475 | else | |
5476 | { | |
5477 | assert (tempreg == AT); | |
17a2f251 TS |
5478 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5479 | treg, AT, breg); | |
f5040a92 AO |
5480 | dreg = treg; |
5481 | adj = 4; | |
5482 | } | |
5483 | ||
5484 | /* Set mips_optimize around the lui instruction to avoid | |
5485 | inserting an unnecessary nop after the lw. */ | |
17a2f251 TS |
5486 | macro_build_lui (NULL, &icnt, &expr1, AT); |
5487 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5488 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
5489 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5490 | dreg, dreg, AT); | |
f5040a92 AO |
5491 | |
5492 | p = frag_var (rs_machine_dependent, 8 + adj, 0, | |
5493 | RELAX_ENCODE (24 + adj, 8 + adj, | |
5494 | 0, 4, 0, | |
5495 | (breg == 0 | |
5496 | ? mips_opts.warn_about_macros | |
5497 | : 0)), | |
5498 | offset_expr.X_add_symbol, 0, NULL); | |
5499 | ||
5500 | used_at = 1; | |
5501 | } | |
5502 | else | |
5503 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5504 | ||
5505 | offset_expr.X_add_number = expr1.X_add_number; | |
f899b4b8 | 5506 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5507 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5508 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5509 | tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 AO |
5510 | if (adj) |
5511 | { | |
17a2f251 TS |
5512 | macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5513 | treg, tempreg, breg); | |
f5040a92 AO |
5514 | breg = 0; |
5515 | tempreg = treg; | |
5516 | } | |
5517 | } | |
252b5132 RH |
5518 | else if (mips_pic == EMBEDDED_PIC) |
5519 | { | |
5520 | /* We use | |
cdf6fd85 | 5521 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5522 | */ |
17a2f251 TS |
5523 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5524 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
5525 | } |
5526 | else | |
5527 | abort (); | |
5528 | ||
5529 | if (breg != 0) | |
4d34fb5f TS |
5530 | { |
5531 | char *s; | |
5532 | ||
5533 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5534 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5535 | else |
f899b4b8 | 5536 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5537 | |
17a2f251 | 5538 | macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5539 | } |
252b5132 RH |
5540 | |
5541 | if (! used_at) | |
5542 | return; | |
5543 | ||
5544 | break; | |
5545 | ||
5546 | case M_J_A: | |
5547 | /* The j instruction may not be used in PIC code, since it | |
5548 | requires an absolute address. We convert it to a b | |
5549 | instruction. */ | |
5550 | if (mips_pic == NO_PIC) | |
17a2f251 | 5551 | macro_build (NULL, &icnt, &offset_expr, "j", "a"); |
252b5132 | 5552 | else |
17a2f251 | 5553 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
5554 | return; |
5555 | ||
5556 | /* The jal instructions must be handled as macros because when | |
5557 | generating PIC code they expand to multi-instruction | |
5558 | sequences. Normally they are simple instructions. */ | |
5559 | case M_JAL_1: | |
5560 | dreg = RA; | |
5561 | /* Fall through. */ | |
5562 | case M_JAL_2: | |
5563 | if (mips_pic == NO_PIC | |
5564 | || mips_pic == EMBEDDED_PIC) | |
17a2f251 | 5565 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5566 | else if (mips_pic == SVR4_PIC) |
5567 | { | |
5568 | if (sreg != PIC_CALL_REG) | |
5569 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5570 | |
17a2f251 | 5571 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5572 | if (! HAVE_NEWABI) |
252b5132 | 5573 | { |
6478892d TS |
5574 | if (mips_cprestore_offset < 0) |
5575 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5576 | else | |
5577 | { | |
7a621144 DJ |
5578 | if (! mips_frame_reg_valid) |
5579 | { | |
5580 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5581 | /* Quiet this warning. */ | |
5582 | mips_frame_reg_valid = 1; | |
5583 | } | |
5584 | if (! mips_cprestore_valid) | |
5585 | { | |
5586 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5587 | /* Quiet this warning. */ | |
5588 | mips_cprestore_valid = 1; | |
5589 | } | |
6478892d | 5590 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5591 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5592 | ADDRESS_LOAD_INSN, |
5593 | mips_gp_register, | |
256ab948 TS |
5594 | mips_frame_reg, |
5595 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5596 | } |
252b5132 RH |
5597 | } |
5598 | } | |
5599 | else | |
5600 | abort (); | |
5601 | ||
5602 | return; | |
5603 | ||
5604 | case M_JAL_A: | |
5605 | if (mips_pic == NO_PIC) | |
17a2f251 | 5606 | macro_build (NULL, &icnt, &offset_expr, "jal", "a"); |
252b5132 RH |
5607 | else if (mips_pic == SVR4_PIC) |
5608 | { | |
f9419b05 TS |
5609 | char *p; |
5610 | ||
252b5132 RH |
5611 | /* If this is a reference to an external symbol, and we are |
5612 | using a small GOT, we want | |
5613 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5614 | nop | |
f9419b05 | 5615 | jalr $ra,$25 |
252b5132 RH |
5616 | nop |
5617 | lw $gp,cprestore($sp) | |
5618 | The cprestore value is set using the .cprestore | |
5619 | pseudo-op. If we are using a big GOT, we want | |
5620 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5621 | addu $25,$25,$gp | |
5622 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5623 | nop | |
f9419b05 | 5624 | jalr $ra,$25 |
252b5132 RH |
5625 | nop |
5626 | lw $gp,cprestore($sp) | |
5627 | If the symbol is not external, we want | |
5628 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5629 | nop | |
5630 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5631 | jalr $ra,$25 |
252b5132 | 5632 | nop |
438c16b8 | 5633 | lw $gp,cprestore($sp) |
f5040a92 AO |
5634 | |
5635 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5636 | sequences above, minus nops, unless the symbol is local, | |
5637 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5638 | GOT_DISP. */ | |
438c16b8 | 5639 | if (HAVE_NEWABI) |
252b5132 | 5640 | { |
f5040a92 AO |
5641 | if (! mips_big_got) |
5642 | { | |
5643 | frag_grow (4); | |
17a2f251 TS |
5644 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5645 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 AO |
5646 | mips_gp_register); |
5647 | frag_var (rs_machine_dependent, 0, 0, | |
5648 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5649 | offset_expr.X_add_symbol, 0, NULL); | |
5650 | } | |
5651 | else | |
5652 | { | |
5653 | frag_grow (20); | |
17a2f251 TS |
5654 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5655 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5656 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5657 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5658 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5659 | "t,o(b)", PIC_CALL_REG, | |
5660 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
f5040a92 AO |
5661 | p = frag_var (rs_machine_dependent, 8, 0, |
5662 | RELAX_ENCODE (12, 8, 0, 4, 0, 0), | |
5663 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
5664 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5665 | "t,o(b)", PIC_CALL_REG, | |
17a2f251 | 5666 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5667 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
dc9461f6 | 5668 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5669 | BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 | 5670 | } |
684022ea | 5671 | |
438c16b8 | 5672 | macro_build_jalr (icnt, &offset_expr); |
252b5132 RH |
5673 | } |
5674 | else | |
5675 | { | |
438c16b8 TS |
5676 | frag_grow (40); |
5677 | if (! mips_big_got) | |
5678 | { | |
17a2f251 TS |
5679 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5680 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
5681 | mips_gp_register); | |
5682 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5683 | p = frag_var (rs_machine_dependent, 4, 0, |
5684 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5685 | offset_expr.X_add_symbol, 0, NULL); | |
5686 | } | |
252b5132 | 5687 | else |
252b5132 | 5688 | { |
438c16b8 TS |
5689 | int gpdel; |
5690 | ||
5691 | if (reg_needs_delay (mips_gp_register)) | |
5692 | gpdel = 4; | |
5693 | else | |
5694 | gpdel = 0; | |
17a2f251 TS |
5695 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5696 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5697 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5698 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5699 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5700 | "t,o(b)", PIC_CALL_REG, | |
5701 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5702 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5703 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5704 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5705 | 8 + gpdel, 0, 0), | |
5706 | offset_expr.X_add_symbol, 0, NULL); | |
5707 | if (gpdel > 0) | |
5708 | { | |
17a2f251 | 5709 | macro_build (p, &icnt, NULL, "nop", ""); |
438c16b8 TS |
5710 | p += 4; |
5711 | } | |
f899b4b8 | 5712 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 TS |
5713 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, |
5714 | mips_gp_register); | |
438c16b8 | 5715 | p += 4; |
17a2f251 | 5716 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5717 | p += 4; |
5718 | } | |
f899b4b8 | 5719 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
438c16b8 | 5720 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5721 | BFD_RELOC_LO16); |
438c16b8 TS |
5722 | macro_build_jalr (icnt, &offset_expr); |
5723 | ||
6478892d TS |
5724 | if (mips_cprestore_offset < 0) |
5725 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5726 | else | |
5727 | { | |
7a621144 DJ |
5728 | if (! mips_frame_reg_valid) |
5729 | { | |
5730 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5731 | /* Quiet this warning. */ | |
5732 | mips_frame_reg_valid = 1; | |
5733 | } | |
5734 | if (! mips_cprestore_valid) | |
5735 | { | |
5736 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5737 | /* Quiet this warning. */ | |
5738 | mips_cprestore_valid = 1; | |
5739 | } | |
6478892d | 5740 | if (mips_opts.noreorder) |
17a2f251 | 5741 | macro_build (NULL, &icnt, NULL, "nop", ""); |
6478892d | 5742 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5743 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5744 | ADDRESS_LOAD_INSN, |
5745 | mips_gp_register, | |
256ab948 TS |
5746 | mips_frame_reg, |
5747 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5748 | } |
252b5132 RH |
5749 | } |
5750 | } | |
5751 | else if (mips_pic == EMBEDDED_PIC) | |
5752 | { | |
17a2f251 | 5753 | macro_build (NULL, &icnt, &offset_expr, "bal", "p"); |
252b5132 RH |
5754 | /* The linker may expand the call to a longer sequence which |
5755 | uses $at, so we must break rather than return. */ | |
5756 | break; | |
5757 | } | |
5758 | else | |
5759 | abort (); | |
5760 | ||
5761 | return; | |
5762 | ||
5763 | case M_LB_AB: | |
5764 | s = "lb"; | |
5765 | goto ld; | |
5766 | case M_LBU_AB: | |
5767 | s = "lbu"; | |
5768 | goto ld; | |
5769 | case M_LH_AB: | |
5770 | s = "lh"; | |
5771 | goto ld; | |
5772 | case M_LHU_AB: | |
5773 | s = "lhu"; | |
5774 | goto ld; | |
5775 | case M_LW_AB: | |
5776 | s = "lw"; | |
5777 | goto ld; | |
5778 | case M_LWC0_AB: | |
5779 | s = "lwc0"; | |
bdaaa2e1 | 5780 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5781 | coproc = 1; |
5782 | goto ld; | |
5783 | case M_LWC1_AB: | |
5784 | s = "lwc1"; | |
bdaaa2e1 | 5785 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5786 | coproc = 1; |
5787 | goto ld; | |
5788 | case M_LWC2_AB: | |
5789 | s = "lwc2"; | |
bdaaa2e1 | 5790 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5791 | coproc = 1; |
5792 | goto ld; | |
5793 | case M_LWC3_AB: | |
5794 | s = "lwc3"; | |
bdaaa2e1 | 5795 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5796 | coproc = 1; |
5797 | goto ld; | |
5798 | case M_LWL_AB: | |
5799 | s = "lwl"; | |
5800 | lr = 1; | |
5801 | goto ld; | |
5802 | case M_LWR_AB: | |
5803 | s = "lwr"; | |
5804 | lr = 1; | |
5805 | goto ld; | |
5806 | case M_LDC1_AB: | |
fef14a42 | 5807 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5808 | { |
5809 | as_bad (_("opcode not supported on this processor")); | |
5810 | return; | |
5811 | } | |
5812 | s = "ldc1"; | |
bdaaa2e1 | 5813 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5814 | coproc = 1; |
5815 | goto ld; | |
5816 | case M_LDC2_AB: | |
5817 | s = "ldc2"; | |
bdaaa2e1 | 5818 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5819 | coproc = 1; |
5820 | goto ld; | |
5821 | case M_LDC3_AB: | |
5822 | s = "ldc3"; | |
bdaaa2e1 | 5823 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5824 | coproc = 1; |
5825 | goto ld; | |
5826 | case M_LDL_AB: | |
5827 | s = "ldl"; | |
5828 | lr = 1; | |
5829 | goto ld; | |
5830 | case M_LDR_AB: | |
5831 | s = "ldr"; | |
5832 | lr = 1; | |
5833 | goto ld; | |
5834 | case M_LL_AB: | |
5835 | s = "ll"; | |
5836 | goto ld; | |
5837 | case M_LLD_AB: | |
5838 | s = "lld"; | |
5839 | goto ld; | |
5840 | case M_LWU_AB: | |
5841 | s = "lwu"; | |
5842 | ld: | |
5843 | if (breg == treg || coproc || lr) | |
5844 | { | |
5845 | tempreg = AT; | |
5846 | used_at = 1; | |
5847 | } | |
5848 | else | |
5849 | { | |
5850 | tempreg = treg; | |
5851 | used_at = 0; | |
5852 | } | |
5853 | goto ld_st; | |
5854 | case M_SB_AB: | |
5855 | s = "sb"; | |
5856 | goto st; | |
5857 | case M_SH_AB: | |
5858 | s = "sh"; | |
5859 | goto st; | |
5860 | case M_SW_AB: | |
5861 | s = "sw"; | |
5862 | goto st; | |
5863 | case M_SWC0_AB: | |
5864 | s = "swc0"; | |
bdaaa2e1 | 5865 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5866 | coproc = 1; |
5867 | goto st; | |
5868 | case M_SWC1_AB: | |
5869 | s = "swc1"; | |
bdaaa2e1 | 5870 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5871 | coproc = 1; |
5872 | goto st; | |
5873 | case M_SWC2_AB: | |
5874 | s = "swc2"; | |
bdaaa2e1 | 5875 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5876 | coproc = 1; |
5877 | goto st; | |
5878 | case M_SWC3_AB: | |
5879 | s = "swc3"; | |
bdaaa2e1 | 5880 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5881 | coproc = 1; |
5882 | goto st; | |
5883 | case M_SWL_AB: | |
5884 | s = "swl"; | |
5885 | goto st; | |
5886 | case M_SWR_AB: | |
5887 | s = "swr"; | |
5888 | goto st; | |
5889 | case M_SC_AB: | |
5890 | s = "sc"; | |
5891 | goto st; | |
5892 | case M_SCD_AB: | |
5893 | s = "scd"; | |
5894 | goto st; | |
5895 | case M_SDC1_AB: | |
fef14a42 | 5896 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5897 | { |
5898 | as_bad (_("opcode not supported on this processor")); | |
5899 | return; | |
5900 | } | |
5901 | s = "sdc1"; | |
5902 | coproc = 1; | |
bdaaa2e1 | 5903 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5904 | goto st; |
5905 | case M_SDC2_AB: | |
5906 | s = "sdc2"; | |
bdaaa2e1 | 5907 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5908 | coproc = 1; |
5909 | goto st; | |
5910 | case M_SDC3_AB: | |
5911 | s = "sdc3"; | |
bdaaa2e1 | 5912 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5913 | coproc = 1; |
5914 | goto st; | |
5915 | case M_SDL_AB: | |
5916 | s = "sdl"; | |
5917 | goto st; | |
5918 | case M_SDR_AB: | |
5919 | s = "sdr"; | |
5920 | st: | |
5921 | tempreg = AT; | |
5922 | used_at = 1; | |
5923 | ld_st: | |
bdaaa2e1 | 5924 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5925 | if (mask == M_LWC1_AB |
5926 | || mask == M_SWC1_AB | |
5927 | || mask == M_LDC1_AB | |
5928 | || mask == M_SDC1_AB | |
5929 | || mask == M_L_DAB | |
5930 | || mask == M_S_DAB) | |
5931 | fmt = "T,o(b)"; | |
5932 | else if (coproc) | |
5933 | fmt = "E,o(b)"; | |
5934 | else | |
5935 | fmt = "t,o(b)"; | |
5936 | ||
256ab948 TS |
5937 | /* Sign-extending 32-bit constants makes their handling easier. |
5938 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5939 | described below. */ | |
5940 | if ((! HAVE_64BIT_ADDRESSES | |
5941 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5942 | && (offset_expr.X_op == O_constant) |
5943 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5944 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5945 | { |
d17e7bce | 5946 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5947 | as_bad (_("constant too large")); |
ae826530 | 5948 | |
1b8e29e5 TS |
5949 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5950 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5951 | } |
256ab948 | 5952 | |
afdbd6d0 CD |
5953 | /* For embedded PIC, we allow loads where the offset is calculated |
5954 | by subtracting a symbol in the current segment from an unknown | |
5955 | symbol, relative to a base register, e.g.: | |
5956 | <op> $treg, <sym>-<localsym>($breg) | |
5957 | This is used by the compiler for switch statements. */ | |
76b3015f | 5958 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5959 | && offset_expr.X_op == O_subtract |
5960 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5961 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5962 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5963 | && (S_GET_SEGMENT | |
5964 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5965 | ->X_add_symbol) | |
5966 | == now_seg))) | |
5967 | && breg != 0 | |
5968 | && (offset_expr.X_add_number == 0 | |
5969 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5970 | { | |
5971 | /* For this case, we output the instructions: | |
5972 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5973 | addiu $tempreg,$tempreg,$breg | |
5974 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5975 | If the relocation would fit entirely in 16 bits, it would be | |
5976 | nice to emit: | |
5977 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5978 | instead, but that seems quite difficult. */ | |
17a2f251 TS |
5979 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
5980 | BFD_RELOC_PCREL_HI16_S); | |
5981 | macro_build (NULL, &icnt, NULL, | |
afdbd6d0 CD |
5982 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5983 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
b7c7d6c1 | 5984 | ? "addu" : "daddu"), |
afdbd6d0 | 5985 | "d,v,t", tempreg, tempreg, breg); |
17a2f251 TS |
5986 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
5987 | BFD_RELOC_PCREL_LO16, tempreg); | |
afdbd6d0 CD |
5988 | if (! used_at) |
5989 | return; | |
5990 | break; | |
5991 | } | |
5992 | ||
252b5132 RH |
5993 | if (offset_expr.X_op != O_constant |
5994 | && offset_expr.X_op != O_symbol) | |
5995 | { | |
5996 | as_bad (_("expression too complex")); | |
5997 | offset_expr.X_op = O_constant; | |
5998 | } | |
5999 | ||
6000 | /* A constant expression in PIC code can be handled just as it | |
6001 | is in non PIC code. */ | |
6002 | if (mips_pic == NO_PIC | |
6003 | || offset_expr.X_op == O_constant) | |
6004 | { | |
f9419b05 TS |
6005 | char *p; |
6006 | ||
252b5132 RH |
6007 | /* If this is a reference to a GP relative symbol, and there |
6008 | is no base register, we want | |
cdf6fd85 | 6009 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6010 | Otherwise, if there is no base register, we want |
6011 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6012 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6013 | If we have a constant, we need two instructions anyhow, | |
6014 | so we always use the latter form. | |
6015 | ||
6016 | If we have a base register, and this is a reference to a | |
6017 | GP relative symbol, we want | |
6018 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6019 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6020 | Otherwise we want |
6021 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6022 | addu $tempreg,$tempreg,$breg | |
6023 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6024 | With a constant we always use the latter case. |
76b3015f | 6025 | |
d6bc6245 TS |
6026 | With 64bit address space and no base register and $at usable, |
6027 | we want | |
6028 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6029 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6030 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6031 | dsll32 $tempreg,0 | |
6032 | daddu $tempreg,$at | |
6033 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6034 | If we have a base register, we want | |
6035 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6036 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6037 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6038 | daddu $at,$breg | |
6039 | dsll32 $tempreg,0 | |
6040 | daddu $tempreg,$at | |
6041 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6042 | ||
6043 | Without $at we can't generate the optimal path for superscalar | |
6044 | processors here since this would require two temporary registers. | |
6045 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6046 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6047 | dsll $tempreg,16 | |
6048 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6049 | dsll $tempreg,16 | |
6050 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6051 | If we have a base register, we want | |
6052 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6053 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6054 | dsll $tempreg,16 | |
6055 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6056 | dsll $tempreg,16 | |
6057 | daddu $tempreg,$tempreg,$breg | |
6058 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
6059 | |
6060 | If we have 64-bit addresses, as an optimization, for | |
6061 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
6062 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
6063 | mechanism since it is more efficient. Note that due to |
6064 | the signed offset used by memory operations, the 32-bit | |
6065 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
6066 | probably attempt to generate 64-bit constants more |
6067 | efficiently in general. | |
9214dd3b AO |
6068 | |
6069 | As an extension for architectures with 64-bit registers, | |
6070 | we don't truncate 64-bit addresses given as literal | |
6071 | constants down to 32 bits, to support existing practice | |
6072 | in the mips64 Linux (the kernel), that compiles source | |
6073 | files with -mabi=64, assembling them as o32 or n32 (with | |
6074 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
6075 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 6076 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
6077 | wasteful to compute the upper 32 bits of every |
6078 | non-literal address, that takes more space and time. | |
6079 | Some day this should probably be implemented as an | |
6080 | assembler option, such that the kernel doesn't have to | |
6081 | use such ugly hacks, even though it will still have to | |
6082 | end up converting the binary to ELF32 for a number of | |
6083 | platforms whose boot loaders don't support ELF64 | |
6084 | binaries. */ | |
256ab948 TS |
6085 | if ((HAVE_64BIT_ADDRESSES |
6086 | && ! (offset_expr.X_op == O_constant | |
6087 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
6088 | || (HAVE_64BIT_GPRS | |
6089 | && offset_expr.X_op == O_constant | |
6090 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 TS |
6091 | { |
6092 | p = NULL; | |
6093 | ||
6094 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
6095 | hold the data for such large chunks. */ | |
6096 | ||
460597ba | 6097 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
6098 | { |
6099 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 6100 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 6101 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 6102 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 6103 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 6104 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 6105 | if (breg != 0) |
17a2f251 TS |
6106 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
6107 | AT, AT, breg); | |
6108 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
6109 | tempreg, tempreg, 0); | |
6110 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
6111 | tempreg, tempreg, AT); | |
6112 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6113 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
6114 | used_at = 1; |
6115 | } | |
6116 | else | |
6117 | { | |
6118 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 6119 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 6120 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
6121 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
6122 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
6123 | tempreg, tempreg, 16); | |
d6bc6245 | 6124 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
6125 | tempreg, tempreg, BFD_RELOC_HI16_S); |
6126 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
6127 | tempreg, tempreg, 16); | |
d6bc6245 | 6128 | if (breg != 0) |
17a2f251 TS |
6129 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
6130 | tempreg, tempreg, breg); | |
6131 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6132 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
6133 | } |
6134 | ||
6135 | return; | |
6136 | } | |
256ab948 TS |
6137 | |
6138 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6139 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6140 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6141 | |
252b5132 RH |
6142 | if (breg == 0) |
6143 | { | |
e7d556df | 6144 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6145 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6146 | p = NULL; | |
6147 | else | |
6148 | { | |
6149 | frag_grow (20); | |
17a2f251 TS |
6150 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
6151 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
6152 | p = frag_var (rs_machine_dependent, 8, 0, |
6153 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
6154 | (mips_opts.warn_about_macros | |
6155 | || (used_at | |
6156 | && mips_opts.noat))), | |
956cd1d6 | 6157 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6158 | used_at = 0; |
6159 | } | |
6160 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6161 | if (p != NULL) | |
6162 | p += 4; | |
6163 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6164 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6165 | } |
6166 | else | |
6167 | { | |
e7d556df | 6168 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6169 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6170 | p = NULL; | |
6171 | else | |
6172 | { | |
6173 | frag_grow (28); | |
17a2f251 TS |
6174 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6175 | tempreg, breg, mips_gp_register); | |
6176 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6177 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6178 | p = frag_var (rs_machine_dependent, 12, 0, |
6179 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 6180 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6181 | } |
6182 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6183 | if (p != NULL) | |
6184 | p += 4; | |
17a2f251 TS |
6185 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6186 | tempreg, tempreg, breg); | |
252b5132 RH |
6187 | if (p != NULL) |
6188 | p += 4; | |
6189 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6190 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6191 | } |
6192 | } | |
6193 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6194 | { | |
f9419b05 | 6195 | char *p; |
ed6fb7bd | 6196 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6197 | |
252b5132 RH |
6198 | /* If this is a reference to an external symbol, we want |
6199 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6200 | nop | |
6201 | <op> $treg,0($tempreg) | |
6202 | Otherwise we want | |
6203 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6204 | nop | |
6205 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6206 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6207 | |
6208 | For NewABI, we want | |
6209 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6210 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6211 | ||
252b5132 RH |
6212 | If there is a base register, we add it to $tempreg before |
6213 | the <op>. If there is a constant, we stick it in the | |
6214 | <op> instruction. We don't handle constants larger than | |
6215 | 16 bits, because we have no way to load the upper 16 bits | |
6216 | (actually, we could handle them for the subset of cases | |
6217 | in which we are not using $at). */ | |
6218 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6219 | if (HAVE_NEWABI) |
6220 | { | |
17a2f251 TS |
6221 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6222 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
6223 | mips_gp_register); | |
f5040a92 | 6224 | if (breg != 0) |
17a2f251 TS |
6225 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6226 | tempreg, tempreg, breg); | |
6227 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6228 | BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
f5040a92 AO |
6229 | |
6230 | if (! used_at) | |
6231 | return; | |
6232 | ||
6233 | break; | |
6234 | } | |
252b5132 RH |
6235 | expr1.X_add_number = offset_expr.X_add_number; |
6236 | offset_expr.X_add_number = 0; | |
6237 | if (expr1.X_add_number < -0x8000 | |
6238 | || expr1.X_add_number >= 0x8000) | |
6239 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6240 | frag_grow (20); | |
17a2f251 TS |
6241 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6242 | tempreg, lw_reloc_type, mips_gp_register); | |
6243 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
bdaaa2e1 | 6244 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 6245 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 6246 | offset_expr.X_add_symbol, 0, NULL); |
f899b4b8 | 6247 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 6248 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 6249 | if (breg != 0) |
17a2f251 TS |
6250 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6251 | tempreg, tempreg, breg); | |
6252 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6253 | tempreg); | |
252b5132 | 6254 | } |
f5040a92 | 6255 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 RH |
6256 | { |
6257 | int gpdel; | |
f9419b05 | 6258 | char *p; |
252b5132 RH |
6259 | |
6260 | /* If this is a reference to an external symbol, we want | |
6261 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6262 | addu $tempreg,$tempreg,$gp | |
6263 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6264 | <op> $treg,0($tempreg) | |
6265 | Otherwise we want | |
6266 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6267 | nop | |
6268 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6269 | <op> $treg,0($tempreg) | |
6270 | If there is a base register, we add it to $tempreg before | |
6271 | the <op>. If there is a constant, we stick it in the | |
6272 | <op> instruction. We don't handle constants larger than | |
6273 | 16 bits, because we have no way to load the upper 16 bits | |
6274 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6275 | in which we are not using $at). */ |
252b5132 RH |
6276 | assert (offset_expr.X_op == O_symbol); |
6277 | expr1.X_add_number = offset_expr.X_add_number; | |
6278 | offset_expr.X_add_number = 0; | |
6279 | if (expr1.X_add_number < -0x8000 | |
6280 | || expr1.X_add_number >= 0x8000) | |
6281 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
f7ea7ef2 | 6282 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6283 | gpdel = 4; |
6284 | else | |
6285 | gpdel = 0; | |
6286 | frag_grow (36); | |
17a2f251 TS |
6287 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6288 | BFD_RELOC_MIPS_GOT_HI16); | |
6289 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6290 | tempreg, tempreg, mips_gp_register); | |
6291 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6292 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
252b5132 RH |
6293 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
6294 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6295 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6296 | if (gpdel > 0) |
6297 | { | |
17a2f251 | 6298 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6299 | p += 4; |
6300 | } | |
17a2f251 TS |
6301 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6302 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6303 | p += 4; |
17a2f251 | 6304 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 6305 | p += 4; |
17a2f251 TS |
6306 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6307 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6308 | if (breg != 0) |
17a2f251 TS |
6309 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6310 | tempreg, tempreg, breg); | |
6311 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6312 | tempreg); | |
252b5132 | 6313 | } |
f5040a92 AO |
6314 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6315 | { | |
6316 | char *p; | |
6317 | int bregsz = breg != 0 ? 4 : 0; | |
6318 | ||
6319 | /* If this is a reference to an external symbol, we want | |
6320 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6321 | add $tempreg,$tempreg,$gp | |
6322 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6323 | <op> $treg,<ofst>($tempreg) | |
6324 | Otherwise, for local symbols, we want: | |
6325 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6326 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6327 | assert (offset_expr.X_op == O_symbol); | |
0a6ace1e | 6328 | frag_grow (36); |
f5040a92 AO |
6329 | frag_now->tc_frag_data.tc_fr_offset = |
6330 | expr1.X_add_number = offset_expr.X_add_number; | |
6331 | offset_expr.X_add_number = 0; | |
6332 | if (expr1.X_add_number < -0x8000 | |
6333 | || expr1.X_add_number >= 0x8000) | |
6334 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
17a2f251 TS |
6335 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6336 | BFD_RELOC_MIPS_GOT_HI16); | |
6337 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6338 | tempreg, tempreg, mips_gp_register); | |
6339 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6340 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6341 | if (breg != 0) |
17a2f251 TS |
6342 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6343 | tempreg, tempreg, breg); | |
6344 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6345 | tempreg); | |
684022ea | 6346 | |
f5040a92 AO |
6347 | offset_expr.X_add_number = expr1.X_add_number; |
6348 | p = frag_var (rs_machine_dependent, 12 + bregsz, 0, | |
6349 | RELAX_ENCODE (16 + bregsz, 8 + bregsz, | |
6350 | 0, 4 + bregsz, 0, 0), | |
6351 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 | 6352 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6353 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f5040a92 | 6354 | if (breg != 0) |
17a2f251 TS |
6355 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6356 | tempreg, tempreg, breg); | |
f5040a92 | 6357 | macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg, |
17a2f251 | 6358 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 | 6359 | } |
252b5132 RH |
6360 | else if (mips_pic == EMBEDDED_PIC) |
6361 | { | |
6362 | /* If there is no base register, we want | |
cdf6fd85 | 6363 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6364 | If there is a base register, we want |
6365 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6366 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6367 | */ |
6368 | assert (offset_expr.X_op == O_symbol); | |
6369 | if (breg == 0) | |
6370 | { | |
17a2f251 TS |
6371 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
6372 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
6373 | used_at = 0; |
6374 | } | |
6375 | else | |
6376 | { | |
17a2f251 TS |
6377 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6378 | tempreg, breg, mips_gp_register); | |
6379 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6380 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6381 | } |
6382 | } | |
6383 | else | |
6384 | abort (); | |
6385 | ||
6386 | if (! used_at) | |
6387 | return; | |
6388 | ||
6389 | break; | |
6390 | ||
6391 | case M_LI: | |
6392 | case M_LI_S: | |
6393 | load_register (&icnt, treg, &imm_expr, 0); | |
6394 | return; | |
6395 | ||
6396 | case M_DLI: | |
6397 | load_register (&icnt, treg, &imm_expr, 1); | |
6398 | return; | |
6399 | ||
6400 | case M_LI_SS: | |
6401 | if (imm_expr.X_op == O_constant) | |
6402 | { | |
6403 | load_register (&icnt, AT, &imm_expr, 0); | |
17a2f251 | 6404 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6405 | break; |
6406 | } | |
6407 | else | |
6408 | { | |
6409 | assert (offset_expr.X_op == O_symbol | |
6410 | && strcmp (segment_name (S_GET_SEGMENT | |
6411 | (offset_expr.X_add_symbol)), | |
6412 | ".lit4") == 0 | |
6413 | && offset_expr.X_add_number == 0); | |
17a2f251 TS |
6414 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg, |
6415 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6416 | return; |
6417 | } | |
6418 | ||
6419 | case M_LI_D: | |
ca4e0257 RS |
6420 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6421 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6422 | order 32 bits of the value and the low order 32 bits are either | |
6423 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6424 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6425 | { | |
ca4e0257 | 6426 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6427 | load_register (&icnt, treg, &imm_expr, 1); |
6428 | else | |
6429 | { | |
6430 | int hreg, lreg; | |
6431 | ||
6432 | if (target_big_endian) | |
6433 | { | |
6434 | hreg = treg; | |
6435 | lreg = treg + 1; | |
6436 | } | |
6437 | else | |
6438 | { | |
6439 | hreg = treg + 1; | |
6440 | lreg = treg; | |
6441 | } | |
6442 | ||
6443 | if (hreg <= 31) | |
6444 | load_register (&icnt, hreg, &imm_expr, 0); | |
6445 | if (lreg <= 31) | |
6446 | { | |
6447 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6448 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6449 | else |
6450 | { | |
6451 | assert (offset_expr.X_op == O_constant); | |
6452 | load_register (&icnt, lreg, &offset_expr, 0); | |
6453 | } | |
6454 | } | |
6455 | } | |
6456 | return; | |
6457 | } | |
6458 | ||
6459 | /* We know that sym is in the .rdata section. First we get the | |
6460 | upper 16 bits of the address. */ | |
6461 | if (mips_pic == NO_PIC) | |
6462 | { | |
956cd1d6 | 6463 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6464 | } |
6465 | else if (mips_pic == SVR4_PIC) | |
6466 | { | |
17a2f251 TS |
6467 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6468 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6469 | } |
6470 | else if (mips_pic == EMBEDDED_PIC) | |
6471 | { | |
6472 | /* For embedded PIC we pick up the entire address off $gp in | |
6473 | a single instruction. */ | |
17a2f251 TS |
6474 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6475 | AT, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
6476 | offset_expr.X_op = O_constant; |
6477 | offset_expr.X_add_number = 0; | |
6478 | } | |
6479 | else | |
6480 | abort (); | |
bdaaa2e1 | 6481 | |
252b5132 | 6482 | /* Now we load the register(s). */ |
ca4e0257 | 6483 | if (HAVE_64BIT_GPRS) |
17a2f251 TS |
6484 | macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg, |
6485 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6486 | else |
6487 | { | |
17a2f251 TS |
6488 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg, |
6489 | BFD_RELOC_LO16, AT); | |
f9419b05 | 6490 | if (treg != RA) |
252b5132 RH |
6491 | { |
6492 | /* FIXME: How in the world do we deal with the possible | |
6493 | overflow here? */ | |
6494 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6495 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
6496 | treg + 1, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6497 | } |
6498 | } | |
6499 | ||
6500 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6501 | does not become a variant frag. */ | |
6502 | frag_wane (frag_now); | |
6503 | frag_new (0); | |
6504 | ||
6505 | break; | |
6506 | ||
6507 | case M_LI_DD: | |
ca4e0257 RS |
6508 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6509 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6510 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6511 | the value and the low order 32 bits are either zero or in | |
6512 | OFFSET_EXPR. */ | |
252b5132 RH |
6513 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6514 | { | |
ca4e0257 RS |
6515 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6516 | if (HAVE_64BIT_FPRS) | |
6517 | { | |
6518 | assert (HAVE_64BIT_GPRS); | |
17a2f251 | 6519 | macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6520 | } |
252b5132 RH |
6521 | else |
6522 | { | |
17a2f251 | 6523 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6524 | if (offset_expr.X_op == O_absent) |
17a2f251 | 6525 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6526 | else |
6527 | { | |
6528 | assert (offset_expr.X_op == O_constant); | |
6529 | load_register (&icnt, AT, &offset_expr, 0); | |
17a2f251 | 6530 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6531 | } |
6532 | } | |
6533 | break; | |
6534 | } | |
6535 | ||
6536 | assert (offset_expr.X_op == O_symbol | |
6537 | && offset_expr.X_add_number == 0); | |
6538 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6539 | if (strcmp (s, ".lit8") == 0) | |
6540 | { | |
e7af610e | 6541 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6542 | { |
17a2f251 TS |
6543 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6544 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6545 | return; |
6546 | } | |
c9914766 | 6547 | breg = mips_gp_register; |
252b5132 RH |
6548 | r = BFD_RELOC_MIPS_LITERAL; |
6549 | goto dob; | |
6550 | } | |
6551 | else | |
6552 | { | |
6553 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6554 | if (mips_pic == SVR4_PIC) | |
17a2f251 TS |
6555 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6556 | "t,o(b)", AT, BFD_RELOC_MIPS_GOT16, | |
6557 | mips_gp_register); | |
252b5132 RH |
6558 | else |
6559 | { | |
6560 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6561 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6562 | } |
bdaaa2e1 | 6563 | |
e7af610e | 6564 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6565 | { |
17a2f251 TS |
6566 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6567 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6568 | |
6569 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6570 | that this does not become a variant frag. */ | |
6571 | frag_wane (frag_now); | |
6572 | frag_new (0); | |
6573 | ||
6574 | break; | |
6575 | } | |
6576 | breg = AT; | |
6577 | r = BFD_RELOC_LO16; | |
6578 | goto dob; | |
6579 | } | |
6580 | ||
6581 | case M_L_DOB: | |
fef14a42 | 6582 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6583 | { |
6584 | as_bad (_("opcode not supported on this processor")); | |
6585 | return; | |
6586 | } | |
6587 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6588 | to adjust when loading from memory. */ | |
6589 | r = BFD_RELOC_LO16; | |
6590 | dob: | |
e7af610e | 6591 | assert (mips_opts.isa == ISA_MIPS1); |
17a2f251 TS |
6592 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6593 | target_big_endian ? treg + 1 : treg, r, breg); | |
252b5132 RH |
6594 | /* FIXME: A possible overflow which I don't know how to deal |
6595 | with. */ | |
6596 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6597 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6598 | target_big_endian ? treg : treg + 1, r, breg); | |
252b5132 RH |
6599 | |
6600 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6601 | does not become a variant frag. */ | |
6602 | frag_wane (frag_now); | |
6603 | frag_new (0); | |
6604 | ||
6605 | if (breg != AT) | |
6606 | return; | |
6607 | break; | |
6608 | ||
6609 | case M_L_DAB: | |
6610 | /* | |
6611 | * The MIPS assembler seems to check for X_add_number not | |
6612 | * being double aligned and generating: | |
6613 | * lui at,%hi(foo+1) | |
6614 | * addu at,at,v1 | |
6615 | * addiu at,at,%lo(foo+1) | |
6616 | * lwc1 f2,0(at) | |
6617 | * lwc1 f3,4(at) | |
6618 | * But, the resulting address is the same after relocation so why | |
6619 | * generate the extra instruction? | |
6620 | */ | |
fef14a42 | 6621 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6622 | { |
6623 | as_bad (_("opcode not supported on this processor")); | |
6624 | return; | |
6625 | } | |
bdaaa2e1 | 6626 | /* Itbl support may require additional care here. */ |
252b5132 | 6627 | coproc = 1; |
e7af610e | 6628 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6629 | { |
6630 | s = "ldc1"; | |
6631 | goto ld; | |
6632 | } | |
6633 | ||
6634 | s = "lwc1"; | |
6635 | fmt = "T,o(b)"; | |
6636 | goto ldd_std; | |
6637 | ||
6638 | case M_S_DAB: | |
fef14a42 | 6639 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6640 | { |
6641 | as_bad (_("opcode not supported on this processor")); | |
6642 | return; | |
6643 | } | |
6644 | ||
e7af610e | 6645 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6646 | { |
6647 | s = "sdc1"; | |
6648 | goto st; | |
6649 | } | |
6650 | ||
6651 | s = "swc1"; | |
6652 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6653 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6654 | coproc = 1; |
6655 | goto ldd_std; | |
6656 | ||
6657 | case M_LD_AB: | |
ca4e0257 | 6658 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6659 | { |
6660 | s = "ld"; | |
6661 | goto ld; | |
6662 | } | |
6663 | ||
6664 | s = "lw"; | |
6665 | fmt = "t,o(b)"; | |
6666 | goto ldd_std; | |
6667 | ||
6668 | case M_SD_AB: | |
ca4e0257 | 6669 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6670 | { |
6671 | s = "sd"; | |
6672 | goto st; | |
6673 | } | |
6674 | ||
6675 | s = "sw"; | |
6676 | fmt = "t,o(b)"; | |
6677 | ||
6678 | ldd_std: | |
afdbd6d0 CD |
6679 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6680 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6681 | This is not currently done by the compiler, and assembly coders | |
6682 | writing embedded-pic code can cope. */ | |
6683 | ||
252b5132 RH |
6684 | if (offset_expr.X_op != O_symbol |
6685 | && offset_expr.X_op != O_constant) | |
6686 | { | |
6687 | as_bad (_("expression too complex")); | |
6688 | offset_expr.X_op = O_constant; | |
6689 | } | |
6690 | ||
6691 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6692 | to adjust when loading from memory. We set coproc if we must | |
6693 | load $fn+1 first. */ | |
bdaaa2e1 | 6694 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6695 | if (! target_big_endian) |
6696 | coproc = 0; | |
6697 | ||
6698 | if (mips_pic == NO_PIC | |
6699 | || offset_expr.X_op == O_constant) | |
6700 | { | |
f9419b05 TS |
6701 | char *p; |
6702 | ||
252b5132 | 6703 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6704 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6705 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6706 | If we have a base register, we use this |
6707 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6708 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6709 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6710 | If this is not a GP relative symbol, we want |
6711 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6712 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6713 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6714 | If there is a base register, we add it to $at after the | |
6715 | lui instruction. If there is a constant, we always use | |
6716 | the last case. */ | |
e7d556df | 6717 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6718 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6719 | { | |
6720 | p = NULL; | |
6721 | used_at = 1; | |
6722 | } | |
6723 | else | |
6724 | { | |
6725 | int off; | |
6726 | ||
6727 | if (breg == 0) | |
6728 | { | |
6729 | frag_grow (28); | |
c9914766 | 6730 | tempreg = mips_gp_register; |
252b5132 RH |
6731 | off = 0; |
6732 | used_at = 0; | |
6733 | } | |
6734 | else | |
6735 | { | |
6736 | frag_grow (36); | |
17a2f251 TS |
6737 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6738 | AT, breg, mips_gp_register); | |
252b5132 RH |
6739 | tempreg = AT; |
6740 | off = 4; | |
6741 | used_at = 1; | |
6742 | } | |
6743 | ||
beae10d5 | 6744 | /* Itbl support may require additional care here. */ |
17a2f251 | 6745 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6746 | coproc ? treg + 1 : treg, |
17a2f251 | 6747 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6748 | offset_expr.X_add_number += 4; |
6749 | ||
6750 | /* Set mips_optimize to 2 to avoid inserting an | |
6751 | undesired nop. */ | |
6752 | hold_mips_optimize = mips_optimize; | |
6753 | mips_optimize = 2; | |
beae10d5 | 6754 | /* Itbl support may require additional care here. */ |
17a2f251 | 6755 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6756 | coproc ? treg : treg + 1, |
17a2f251 | 6757 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6758 | mips_optimize = hold_mips_optimize; |
6759 | ||
6760 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6761 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6762 | used_at && mips_opts.noat), | |
956cd1d6 | 6763 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6764 | |
6765 | /* We just generated two relocs. When tc_gen_reloc | |
6766 | handles this case, it will skip the first reloc and | |
6767 | handle the second. The second reloc already has an | |
6768 | extra addend of 4, which we added above. We must | |
6769 | subtract it out, and then subtract another 4 to make | |
6770 | the first reloc come out right. The second reloc | |
6771 | will come out right because we are going to add 4 to | |
6772 | offset_expr when we build its instruction below. | |
6773 | ||
6774 | If we have a symbol, then we don't want to include | |
6775 | the offset, because it will wind up being included | |
6776 | when we generate the reloc. */ | |
6777 | ||
6778 | if (offset_expr.X_op == O_constant) | |
6779 | offset_expr.X_add_number -= 8; | |
6780 | else | |
6781 | { | |
6782 | offset_expr.X_add_number = -4; | |
6783 | offset_expr.X_op = O_constant; | |
6784 | } | |
6785 | } | |
6786 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6787 | if (p != NULL) | |
6788 | p += 4; | |
6789 | if (breg != 0) | |
6790 | { | |
17a2f251 TS |
6791 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6792 | AT, breg, AT); | |
252b5132 RH |
6793 | if (p != NULL) |
6794 | p += 4; | |
6795 | } | |
beae10d5 | 6796 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6797 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6798 | coproc ? treg + 1 : treg, | |
17a2f251 | 6799 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6800 | if (p != NULL) |
6801 | p += 4; | |
6802 | /* FIXME: How do we handle overflow here? */ | |
6803 | offset_expr.X_add_number += 4; | |
beae10d5 | 6804 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6805 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6806 | coproc ? treg : treg + 1, | |
17a2f251 | 6807 | BFD_RELOC_LO16, AT); |
bdaaa2e1 | 6808 | } |
252b5132 RH |
6809 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6810 | { | |
6811 | int off; | |
6812 | ||
6813 | /* If this is a reference to an external symbol, we want | |
6814 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6815 | nop | |
6816 | <op> $treg,0($at) | |
6817 | <op> $treg+1,4($at) | |
6818 | Otherwise we want | |
6819 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6820 | nop | |
6821 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6822 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6823 | If there is a base register we add it to $at before the | |
6824 | lwc1 instructions. If there is a constant we include it | |
6825 | in the lwc1 instructions. */ | |
6826 | used_at = 1; | |
6827 | expr1.X_add_number = offset_expr.X_add_number; | |
6828 | offset_expr.X_add_number = 0; | |
6829 | if (expr1.X_add_number < -0x8000 | |
6830 | || expr1.X_add_number >= 0x8000 - 4) | |
6831 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6832 | if (breg == 0) | |
6833 | off = 0; | |
6834 | else | |
6835 | off = 4; | |
6836 | frag_grow (24 + off); | |
17a2f251 TS |
6837 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6838 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
6839 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6840 | if (breg != 0) |
17a2f251 TS |
6841 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6842 | AT, breg, AT); | |
beae10d5 | 6843 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6844 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6845 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6846 | expr1.X_add_number += 4; |
6847 | ||
6848 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6849 | nop. */ | |
6850 | hold_mips_optimize = mips_optimize; | |
6851 | mips_optimize = 2; | |
beae10d5 | 6852 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6853 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6854 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6855 | mips_optimize = hold_mips_optimize; |
6856 | ||
6857 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6858 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6859 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6860 | } |
6861 | else if (mips_pic == SVR4_PIC) | |
6862 | { | |
6863 | int gpdel, off; | |
f9419b05 | 6864 | char *p; |
252b5132 RH |
6865 | |
6866 | /* If this is a reference to an external symbol, we want | |
6867 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6868 | addu $at,$at,$gp | |
6869 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6870 | nop | |
6871 | <op> $treg,0($at) | |
6872 | <op> $treg+1,4($at) | |
6873 | Otherwise we want | |
6874 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6875 | nop | |
6876 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6877 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6878 | If there is a base register we add it to $at before the | |
6879 | lwc1 instructions. If there is a constant we include it | |
6880 | in the lwc1 instructions. */ | |
6881 | used_at = 1; | |
6882 | expr1.X_add_number = offset_expr.X_add_number; | |
6883 | offset_expr.X_add_number = 0; | |
6884 | if (expr1.X_add_number < -0x8000 | |
6885 | || expr1.X_add_number >= 0x8000 - 4) | |
6886 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6887 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6888 | gpdel = 4; |
6889 | else | |
6890 | gpdel = 0; | |
6891 | if (breg == 0) | |
6892 | off = 0; | |
6893 | else | |
6894 | off = 4; | |
6895 | frag_grow (56); | |
17a2f251 TS |
6896 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT, |
6897 | BFD_RELOC_MIPS_GOT_HI16); | |
6898 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6899 | AT, AT, mips_gp_register); | |
6900 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6901 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); | |
6902 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6903 | if (breg != 0) |
17a2f251 TS |
6904 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6905 | AT, breg, AT); | |
beae10d5 | 6906 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6907 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6908 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6909 | expr1.X_add_number += 4; |
6910 | ||
6911 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6912 | nop. */ | |
6913 | hold_mips_optimize = mips_optimize; | |
6914 | mips_optimize = 2; | |
beae10d5 | 6915 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6916 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6917 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6918 | mips_optimize = hold_mips_optimize; |
6919 | expr1.X_add_number -= 4; | |
6920 | ||
6921 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6922 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6923 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6924 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6925 | if (gpdel > 0) |
6926 | { | |
17a2f251 | 6927 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6928 | p += 4; |
6929 | } | |
17a2f251 TS |
6930 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6931 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6932 | p += 4; |
17a2f251 | 6933 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6934 | p += 4; |
6935 | if (breg != 0) | |
6936 | { | |
17a2f251 TS |
6937 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6938 | AT, breg, AT); | |
252b5132 RH |
6939 | p += 4; |
6940 | } | |
beae10d5 | 6941 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6942 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6943 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6944 | p += 4; |
6945 | expr1.X_add_number += 4; | |
6946 | ||
6947 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6948 | nop. */ | |
6949 | hold_mips_optimize = mips_optimize; | |
6950 | mips_optimize = 2; | |
beae10d5 | 6951 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6952 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6953 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6954 | mips_optimize = hold_mips_optimize; |
6955 | } | |
6956 | else if (mips_pic == EMBEDDED_PIC) | |
6957 | { | |
6958 | /* If there is no base register, we use | |
cdf6fd85 TS |
6959 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6960 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6961 | If we have a base register, we use |
6962 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6963 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6964 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6965 | */ |
6966 | if (breg == 0) | |
6967 | { | |
c9914766 | 6968 | tempreg = mips_gp_register; |
252b5132 RH |
6969 | used_at = 0; |
6970 | } | |
6971 | else | |
6972 | { | |
17a2f251 TS |
6973 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6974 | AT, breg, mips_gp_register); | |
252b5132 RH |
6975 | tempreg = AT; |
6976 | used_at = 1; | |
6977 | } | |
6978 | ||
beae10d5 | 6979 | /* Itbl support may require additional care here. */ |
17a2f251 | 6980 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6981 | coproc ? treg + 1 : treg, |
17a2f251 | 6982 | BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6983 | offset_expr.X_add_number += 4; |
beae10d5 | 6984 | /* Itbl support may require additional care here. */ |
17a2f251 | 6985 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6986 | coproc ? treg : treg + 1, |
17a2f251 | 6987 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6988 | } |
6989 | else | |
6990 | abort (); | |
6991 | ||
6992 | if (! used_at) | |
6993 | return; | |
6994 | ||
6995 | break; | |
6996 | ||
6997 | case M_LD_OB: | |
6998 | s = "lw"; | |
6999 | goto sd_ob; | |
7000 | case M_SD_OB: | |
7001 | s = "sw"; | |
7002 | sd_ob: | |
ca4e0257 | 7003 | assert (HAVE_32BIT_ADDRESSES); |
17a2f251 TS |
7004 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7005 | BFD_RELOC_LO16, breg); | |
252b5132 | 7006 | offset_expr.X_add_number += 4; |
17a2f251 TS |
7007 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, |
7008 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7009 | return; |
7010 | ||
7011 | /* New code added to support COPZ instructions. | |
7012 | This code builds table entries out of the macros in mip_opcodes. | |
7013 | R4000 uses interlocks to handle coproc delays. | |
7014 | Other chips (like the R3000) require nops to be inserted for delays. | |
7015 | ||
f72c8c98 | 7016 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7017 | In order to fill delay slots for non-interlocked chips, |
7018 | we must have a way to specify delays based on the coprocessor. | |
7019 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7020 | What are the side-effects of the cop instruction? | |
7021 | What cache support might we have and what are its effects? | |
7022 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7023 | What registers are read/set/modified? |
252b5132 RH |
7024 | |
7025 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7026 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7027 | |
7028 | case M_COP0: | |
7029 | s = "c0"; | |
7030 | goto copz; | |
7031 | case M_COP1: | |
7032 | s = "c1"; | |
7033 | goto copz; | |
7034 | case M_COP2: | |
7035 | s = "c2"; | |
7036 | goto copz; | |
7037 | case M_COP3: | |
7038 | s = "c3"; | |
7039 | copz: | |
7040 | /* For now we just do C (same as Cz). The parameter will be | |
7041 | stored in insn_opcode by mips_ip. */ | |
17a2f251 | 7042 | macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
7043 | return; |
7044 | ||
ea1fb5dc RS |
7045 | case M_MOVE: |
7046 | move_register (&icnt, dreg, sreg); | |
7047 | return; | |
7048 | ||
252b5132 RH |
7049 | #ifdef LOSING_COMPILER |
7050 | default: | |
7051 | /* Try and see if this is a new itbl instruction. | |
7052 | This code builds table entries out of the macros in mip_opcodes. | |
7053 | FIXME: For now we just assemble the expression and pass it's | |
7054 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7055 | We may want to have the assembler assemble this value, |
252b5132 RH |
7056 | so that we gain the assembler's knowledge of delay slots, |
7057 | symbols, etc. | |
7058 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7059 | if (itbl_have_entries |
252b5132 | 7060 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7061 | { |
252b5132 RH |
7062 | s = ip->insn_mo->name; |
7063 | s2 = "cop3"; | |
7064 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
17a2f251 | 7065 | macro_build (NULL, &icnt, &immed_expr, s, "C"); |
252b5132 | 7066 | return; |
beae10d5 | 7067 | } |
252b5132 RH |
7068 | macro2 (ip); |
7069 | return; | |
7070 | } | |
7071 | if (mips_opts.noat) | |
7072 | as_warn (_("Macro used $at after \".set noat\"")); | |
7073 | } | |
bdaaa2e1 | 7074 | |
252b5132 | 7075 | static void |
17a2f251 | 7076 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
7077 | { |
7078 | register int treg, sreg, dreg, breg; | |
7079 | int tempreg; | |
7080 | int mask; | |
7081 | int icnt = 0; | |
7082 | int used_at; | |
7083 | expressionS expr1; | |
7084 | const char *s; | |
7085 | const char *s2; | |
7086 | const char *fmt; | |
7087 | int likely = 0; | |
7088 | int dbl = 0; | |
7089 | int coproc = 0; | |
7090 | int lr = 0; | |
7091 | int imm = 0; | |
7092 | int off; | |
7093 | offsetT maxnum; | |
7094 | bfd_reloc_code_real_type r; | |
7095 | char *p; | |
bdaaa2e1 | 7096 | |
252b5132 RH |
7097 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7098 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7099 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7100 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7101 | |
252b5132 RH |
7102 | expr1.X_op = O_constant; |
7103 | expr1.X_op_symbol = NULL; | |
7104 | expr1.X_add_symbol = NULL; | |
7105 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7106 | |
252b5132 RH |
7107 | switch (mask) |
7108 | { | |
7109 | #endif /* LOSING_COMPILER */ | |
7110 | ||
7111 | case M_DMUL: | |
7112 | dbl = 1; | |
7113 | case M_MUL: | |
17a2f251 TS |
7114 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
7115 | sreg, treg); | |
7116 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
7117 | return; |
7118 | ||
7119 | case M_DMUL_I: | |
7120 | dbl = 1; | |
7121 | case M_MUL_I: | |
7122 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7123 | not trying to be that fancy. GCC should do this for us | |
7124 | anyway. */ | |
7125 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7126 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
7127 | sreg, AT); | |
7128 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
7129 | break; |
7130 | ||
7131 | case M_DMULO_I: | |
7132 | dbl = 1; | |
7133 | case M_MULO_I: | |
7134 | imm = 1; | |
7135 | goto do_mulo; | |
7136 | ||
7137 | case M_DMULO: | |
7138 | dbl = 1; | |
7139 | case M_MULO: | |
7140 | do_mulo: | |
b34976b6 | 7141 | mips_emit_delays (TRUE); |
252b5132 RH |
7142 | ++mips_opts.noreorder; |
7143 | mips_any_noreorder = 1; | |
7144 | if (imm) | |
7145 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7146 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
7147 | sreg, imm ? AT : treg); | |
7148 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
7149 | macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<", | |
7150 | dreg, dreg, RA); | |
7151 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
252b5132 | 7152 | if (mips_trap) |
17a2f251 | 7153 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7154 | else |
7155 | { | |
7156 | expr1.X_add_number = 8; | |
17a2f251 TS |
7157 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); |
7158 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
7159 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
7160 | } |
7161 | --mips_opts.noreorder; | |
17a2f251 | 7162 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); |
252b5132 RH |
7163 | break; |
7164 | ||
7165 | case M_DMULOU_I: | |
7166 | dbl = 1; | |
7167 | case M_MULOU_I: | |
7168 | imm = 1; | |
7169 | goto do_mulou; | |
7170 | ||
7171 | case M_DMULOU: | |
7172 | dbl = 1; | |
7173 | case M_MULOU: | |
7174 | do_mulou: | |
b34976b6 | 7175 | mips_emit_delays (TRUE); |
252b5132 RH |
7176 | ++mips_opts.noreorder; |
7177 | mips_any_noreorder = 1; | |
7178 | if (imm) | |
7179 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7180 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
7181 | sreg, imm ? AT : treg); | |
7182 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
7183 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 | 7184 | if (mips_trap) |
17a2f251 | 7185 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7186 | else |
7187 | { | |
7188 | expr1.X_add_number = 8; | |
17a2f251 TS |
7189 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); |
7190 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
7191 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
7192 | } |
7193 | --mips_opts.noreorder; | |
7194 | break; | |
7195 | ||
771c7ce4 | 7196 | case M_DROL: |
fef14a42 | 7197 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7198 | { |
7199 | if (dreg == sreg) | |
7200 | { | |
7201 | tempreg = AT; | |
7202 | used_at = 1; | |
7203 | } | |
7204 | else | |
7205 | { | |
7206 | tempreg = dreg; | |
7207 | used_at = 0; | |
7208 | } | |
17a2f251 TS |
7209 | macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg); |
7210 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, | |
7211 | tempreg); | |
82dd0097 CD |
7212 | if (used_at) |
7213 | break; | |
7214 | return; | |
7215 | } | |
17a2f251 TS |
7216 | macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg); |
7217 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7218 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7219 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7220 | break; |
7221 | ||
252b5132 | 7222 | case M_ROL: |
fef14a42 | 7223 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7224 | { |
7225 | if (dreg == sreg) | |
7226 | { | |
7227 | tempreg = AT; | |
7228 | used_at = 1; | |
7229 | } | |
7230 | else | |
7231 | { | |
7232 | tempreg = dreg; | |
7233 | used_at = 0; | |
7234 | } | |
17a2f251 TS |
7235 | macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg); |
7236 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, | |
7237 | tempreg); | |
82dd0097 CD |
7238 | if (used_at) |
7239 | break; | |
7240 | return; | |
7241 | } | |
17a2f251 TS |
7242 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7243 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7244 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7245 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7246 | break; |
7247 | ||
771c7ce4 TS |
7248 | case M_DROL_I: |
7249 | { | |
7250 | unsigned int rot; | |
82dd0097 | 7251 | char *l, *r; |
771c7ce4 TS |
7252 | |
7253 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7254 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7255 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7256 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7257 | { |
7258 | rot = (64 - rot) & 0x3f; | |
7259 | if (rot >= 32) | |
17a2f251 TS |
7260 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7261 | dreg, sreg, rot - 32); | |
60b63b72 | 7262 | else |
17a2f251 TS |
7263 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7264 | dreg, sreg, rot); | |
82dd0097 | 7265 | return; |
60b63b72 | 7266 | } |
483fc7cd | 7267 | if (rot == 0) |
483fc7cd | 7268 | { |
17a2f251 | 7269 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7270 | return; |
483fc7cd | 7271 | } |
82dd0097 CD |
7272 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7273 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7274 | rot &= 0x1f; | |
17a2f251 TS |
7275 | macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot); |
7276 | macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg, | |
7277 | (0x20 - rot) & 0x1f); | |
7278 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7279 | } |
7280 | break; | |
7281 | ||
252b5132 | 7282 | case M_ROL_I: |
771c7ce4 TS |
7283 | { |
7284 | unsigned int rot; | |
7285 | ||
7286 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7287 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7288 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7289 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7290 | { |
17a2f251 TS |
7291 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, |
7292 | (32 - rot) & 0x1f); | |
82dd0097 | 7293 | return; |
60b63b72 | 7294 | } |
483fc7cd | 7295 | if (rot == 0) |
483fc7cd | 7296 | { |
17a2f251 | 7297 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7298 | return; |
483fc7cd | 7299 | } |
17a2f251 TS |
7300 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot); |
7301 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
7302 | (0x20 - rot) & 0x1f); | |
7303 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7304 | } |
7305 | break; | |
7306 | ||
7307 | case M_DROR: | |
fef14a42 | 7308 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7309 | { |
17a2f251 | 7310 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7311 | return; |
7312 | } | |
bf151ce7 | 7313 | macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg); |
17a2f251 TS |
7314 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7315 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7316 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7317 | break; |
7318 | ||
7319 | case M_ROR: | |
fef14a42 | 7320 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7321 | { |
17a2f251 | 7322 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7323 | return; |
7324 | } | |
17a2f251 TS |
7325 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7326 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7327 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7328 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7329 | break; |
7330 | ||
771c7ce4 TS |
7331 | case M_DROR_I: |
7332 | { | |
7333 | unsigned int rot; | |
82dd0097 | 7334 | char *l, *r; |
771c7ce4 TS |
7335 | |
7336 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7337 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7338 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7339 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7340 | { |
7341 | if (rot >= 32) | |
17a2f251 TS |
7342 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7343 | dreg, sreg, rot - 32); | |
82dd0097 | 7344 | else |
17a2f251 TS |
7345 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7346 | dreg, sreg, rot); | |
82dd0097 CD |
7347 | return; |
7348 | } | |
483fc7cd | 7349 | if (rot == 0) |
483fc7cd | 7350 | { |
17a2f251 | 7351 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7352 | return; |
483fc7cd | 7353 | } |
82dd0097 CD |
7354 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7355 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7356 | rot &= 0x1f; | |
bf151ce7 | 7357 | macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot); |
17a2f251 TS |
7358 | macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg, |
7359 | (0x20 - rot) & 0x1f); | |
7360 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7361 | } |
7362 | break; | |
7363 | ||
252b5132 | 7364 | case M_ROR_I: |
771c7ce4 TS |
7365 | { |
7366 | unsigned int rot; | |
7367 | ||
7368 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7369 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7370 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7371 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7372 | { |
17a2f251 | 7373 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7374 | return; |
7375 | } | |
483fc7cd | 7376 | if (rot == 0) |
483fc7cd | 7377 | { |
17a2f251 | 7378 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7379 | return; |
483fc7cd | 7380 | } |
17a2f251 TS |
7381 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot); |
7382 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
7383 | (0x20 - rot) & 0x1f); | |
7384 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7385 | } |
252b5132 RH |
7386 | break; |
7387 | ||
7388 | case M_S_DOB: | |
fef14a42 | 7389 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7390 | { |
7391 | as_bad (_("opcode not supported on this processor")); | |
7392 | return; | |
7393 | } | |
e7af610e | 7394 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7395 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7396 | to adjust when storing to memory. */ | |
17a2f251 | 7397 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7398 | target_big_endian ? treg + 1 : treg, |
17a2f251 | 7399 | BFD_RELOC_LO16, breg); |
252b5132 | 7400 | offset_expr.X_add_number += 4; |
17a2f251 | 7401 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7402 | target_big_endian ? treg : treg + 1, |
17a2f251 | 7403 | BFD_RELOC_LO16, breg); |
252b5132 RH |
7404 | return; |
7405 | ||
7406 | case M_SEQ: | |
7407 | if (sreg == 0) | |
17a2f251 TS |
7408 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg, |
7409 | BFD_RELOC_LO16); | |
252b5132 | 7410 | else if (treg == 0) |
17a2f251 TS |
7411 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7412 | BFD_RELOC_LO16); | |
252b5132 RH |
7413 | else |
7414 | { | |
17a2f251 TS |
7415 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7416 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7417 | BFD_RELOC_LO16); | |
252b5132 RH |
7418 | } |
7419 | return; | |
7420 | ||
7421 | case M_SEQ_I: | |
7422 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7423 | { | |
17a2f251 TS |
7424 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7425 | BFD_RELOC_LO16); | |
252b5132 RH |
7426 | return; |
7427 | } | |
7428 | if (sreg == 0) | |
7429 | { | |
7430 | as_warn (_("Instruction %s: result is always false"), | |
7431 | ip->insn_mo->name); | |
ea1fb5dc | 7432 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7433 | return; |
7434 | } | |
7435 | if (imm_expr.X_op == O_constant | |
7436 | && imm_expr.X_add_number >= 0 | |
7437 | && imm_expr.X_add_number < 0x10000) | |
7438 | { | |
17a2f251 TS |
7439 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7440 | BFD_RELOC_LO16); | |
252b5132 RH |
7441 | used_at = 0; |
7442 | } | |
7443 | else if (imm_expr.X_op == O_constant | |
7444 | && imm_expr.X_add_number > -0x8000 | |
7445 | && imm_expr.X_add_number < 0) | |
7446 | { | |
7447 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7448 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7449 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7450 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7451 | used_at = 0; |
7452 | } | |
7453 | else | |
7454 | { | |
4d34fb5f | 7455 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7456 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7457 | used_at = 1; |
7458 | } | |
17a2f251 TS |
7459 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
7460 | BFD_RELOC_LO16); | |
252b5132 RH |
7461 | if (used_at) |
7462 | break; | |
7463 | return; | |
7464 | ||
7465 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7466 | s = "slt"; | |
7467 | goto sge; | |
7468 | case M_SGEU: | |
7469 | s = "sltu"; | |
7470 | sge: | |
17a2f251 TS |
7471 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
7472 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7473 | BFD_RELOC_LO16); | |
252b5132 RH |
7474 | return; |
7475 | ||
7476 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7477 | case M_SGEU_I: | |
7478 | if (imm_expr.X_op == O_constant | |
7479 | && imm_expr.X_add_number >= -0x8000 | |
7480 | && imm_expr.X_add_number < 0x8000) | |
7481 | { | |
17a2f251 | 7482 | macro_build (NULL, &icnt, &imm_expr, |
252b5132 | 7483 | mask == M_SGE_I ? "slti" : "sltiu", |
17a2f251 | 7484 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7485 | used_at = 0; |
7486 | } | |
7487 | else | |
7488 | { | |
4d34fb5f | 7489 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7490 | macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu", |
7491 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7492 | used_at = 1; |
7493 | } | |
17a2f251 TS |
7494 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7495 | BFD_RELOC_LO16); | |
252b5132 RH |
7496 | if (used_at) |
7497 | break; | |
7498 | return; | |
7499 | ||
7500 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7501 | s = "slt"; | |
7502 | goto sgt; | |
7503 | case M_SGTU: | |
7504 | s = "sltu"; | |
7505 | sgt: | |
17a2f251 | 7506 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7507 | return; |
7508 | ||
7509 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7510 | s = "slt"; | |
7511 | goto sgti; | |
7512 | case M_SGTU_I: | |
7513 | s = "sltu"; | |
7514 | sgti: | |
4d34fb5f | 7515 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7516 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
252b5132 RH |
7517 | break; |
7518 | ||
2396cfb9 | 7519 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7520 | s = "slt"; |
7521 | goto sle; | |
7522 | case M_SLEU: | |
7523 | s = "sltu"; | |
7524 | sle: | |
17a2f251 TS |
7525 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
7526 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7527 | BFD_RELOC_LO16); | |
252b5132 RH |
7528 | return; |
7529 | ||
2396cfb9 | 7530 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7531 | s = "slt"; |
7532 | goto slei; | |
7533 | case M_SLEU_I: | |
7534 | s = "sltu"; | |
7535 | slei: | |
4d34fb5f | 7536 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7537 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
7538 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7539 | BFD_RELOC_LO16); | |
252b5132 RH |
7540 | break; |
7541 | ||
7542 | case M_SLT_I: | |
7543 | if (imm_expr.X_op == O_constant | |
7544 | && imm_expr.X_add_number >= -0x8000 | |
7545 | && imm_expr.X_add_number < 0x8000) | |
7546 | { | |
17a2f251 TS |
7547 | macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg, |
7548 | BFD_RELOC_LO16); | |
252b5132 RH |
7549 | return; |
7550 | } | |
4d34fb5f | 7551 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7552 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7553 | break; |
7554 | ||
7555 | case M_SLTU_I: | |
7556 | if (imm_expr.X_op == O_constant | |
7557 | && imm_expr.X_add_number >= -0x8000 | |
7558 | && imm_expr.X_add_number < 0x8000) | |
7559 | { | |
17a2f251 TS |
7560 | macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg, |
7561 | BFD_RELOC_LO16); | |
252b5132 RH |
7562 | return; |
7563 | } | |
4d34fb5f | 7564 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7565 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7566 | break; |
7567 | ||
7568 | case M_SNE: | |
7569 | if (sreg == 0) | |
bf151ce7 | 7570 | macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg); |
252b5132 | 7571 | else if (treg == 0) |
17a2f251 | 7572 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7573 | else |
7574 | { | |
17a2f251 TS |
7575 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7576 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7577 | } |
7578 | return; | |
7579 | ||
7580 | case M_SNE_I: | |
7581 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7582 | { | |
17a2f251 | 7583 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7584 | return; |
7585 | } | |
7586 | if (sreg == 0) | |
7587 | { | |
7588 | as_warn (_("Instruction %s: result is always true"), | |
7589 | ip->insn_mo->name); | |
17a2f251 | 7590 | macro_build (NULL, &icnt, &expr1, |
ca4e0257 | 7591 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7592 | "t,r,j", dreg, 0, BFD_RELOC_LO16); |
252b5132 RH |
7593 | return; |
7594 | } | |
7595 | if (imm_expr.X_op == O_constant | |
7596 | && imm_expr.X_add_number >= 0 | |
7597 | && imm_expr.X_add_number < 0x10000) | |
7598 | { | |
17a2f251 TS |
7599 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7600 | BFD_RELOC_LO16); | |
252b5132 RH |
7601 | used_at = 0; |
7602 | } | |
7603 | else if (imm_expr.X_op == O_constant | |
7604 | && imm_expr.X_add_number > -0x8000 | |
7605 | && imm_expr.X_add_number < 0) | |
7606 | { | |
7607 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7608 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7609 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7610 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7611 | used_at = 0; |
7612 | } | |
7613 | else | |
7614 | { | |
4d34fb5f | 7615 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7616 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7617 | used_at = 1; |
7618 | } | |
17a2f251 | 7619 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7620 | if (used_at) |
7621 | break; | |
7622 | return; | |
7623 | ||
7624 | case M_DSUB_I: | |
7625 | dbl = 1; | |
7626 | case M_SUB_I: | |
7627 | if (imm_expr.X_op == O_constant | |
7628 | && imm_expr.X_add_number > -0x8000 | |
7629 | && imm_expr.X_add_number <= 0x8000) | |
7630 | { | |
7631 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7632 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi", |
7633 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7634 | return; |
7635 | } | |
7636 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7637 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", |
7638 | dreg, sreg, AT); | |
252b5132 RH |
7639 | break; |
7640 | ||
7641 | case M_DSUBU_I: | |
7642 | dbl = 1; | |
7643 | case M_SUBU_I: | |
7644 | if (imm_expr.X_op == O_constant | |
7645 | && imm_expr.X_add_number > -0x8000 | |
7646 | && imm_expr.X_add_number <= 0x8000) | |
7647 | { | |
7648 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7649 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", |
7650 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7651 | return; |
7652 | } | |
7653 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7654 | macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t", |
7655 | dreg, sreg, AT); | |
252b5132 RH |
7656 | break; |
7657 | ||
7658 | case M_TEQ_I: | |
7659 | s = "teq"; | |
7660 | goto trap; | |
7661 | case M_TGE_I: | |
7662 | s = "tge"; | |
7663 | goto trap; | |
7664 | case M_TGEU_I: | |
7665 | s = "tgeu"; | |
7666 | goto trap; | |
7667 | case M_TLT_I: | |
7668 | s = "tlt"; | |
7669 | goto trap; | |
7670 | case M_TLTU_I: | |
7671 | s = "tltu"; | |
7672 | goto trap; | |
7673 | case M_TNE_I: | |
7674 | s = "tne"; | |
7675 | trap: | |
4d34fb5f | 7676 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7677 | macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT); |
252b5132 RH |
7678 | break; |
7679 | ||
252b5132 | 7680 | case M_TRUNCWS: |
43841e91 | 7681 | case M_TRUNCWD: |
e7af610e | 7682 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7683 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7684 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7685 | ||
7686 | /* | |
7687 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7688 | * or is there a reason for it? | |
7689 | */ | |
b34976b6 | 7690 | mips_emit_delays (TRUE); |
252b5132 RH |
7691 | ++mips_opts.noreorder; |
7692 | mips_any_noreorder = 1; | |
17a2f251 TS |
7693 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); |
7694 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); | |
7695 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 7696 | expr1.X_add_number = 3; |
17a2f251 TS |
7697 | macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
7698 | BFD_RELOC_LO16); | |
252b5132 | 7699 | expr1.X_add_number = 2; |
17a2f251 TS |
7700 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
7701 | BFD_RELOC_LO16); | |
7702 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA); | |
7703 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
7704 | macro_build (NULL, &icnt, NULL, | |
7705 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", | |
7706 | "D,S", dreg, sreg); | |
7707 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA); | |
7708 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 RH |
7709 | --mips_opts.noreorder; |
7710 | break; | |
7711 | ||
7712 | case M_ULH: | |
7713 | s = "lb"; | |
7714 | goto ulh; | |
7715 | case M_ULHU: | |
7716 | s = "lbu"; | |
7717 | ulh: | |
7718 | if (offset_expr.X_add_number >= 0x7fff) | |
7719 | as_bad (_("operand overflow")); | |
252b5132 | 7720 | if (! target_big_endian) |
f9419b05 | 7721 | ++offset_expr.X_add_number; |
17a2f251 TS |
7722 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT, |
7723 | BFD_RELOC_LO16, breg); | |
252b5132 | 7724 | if (! target_big_endian) |
f9419b05 | 7725 | --offset_expr.X_add_number; |
252b5132 | 7726 | else |
f9419b05 | 7727 | ++offset_expr.X_add_number; |
17a2f251 TS |
7728 | macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg, |
7729 | BFD_RELOC_LO16, breg); | |
7730 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8); | |
7731 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7732 | break; |
7733 | ||
7734 | case M_ULD: | |
7735 | s = "ldl"; | |
7736 | s2 = "ldr"; | |
7737 | off = 7; | |
7738 | goto ulw; | |
7739 | case M_ULW: | |
7740 | s = "lwl"; | |
7741 | s2 = "lwr"; | |
7742 | off = 3; | |
7743 | ulw: | |
7744 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7745 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7746 | if (treg != breg) |
7747 | tempreg = treg; | |
7748 | else | |
7749 | tempreg = AT; | |
252b5132 RH |
7750 | if (! target_big_endian) |
7751 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7752 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg, |
7753 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7754 | if (! target_big_endian) |
7755 | offset_expr.X_add_number -= off; | |
7756 | else | |
7757 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7758 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg, |
7759 | BFD_RELOC_LO16, breg); | |
af22f5b2 CD |
7760 | |
7761 | /* If necessary, move the result in tempreg the final destination. */ | |
7762 | if (treg == tempreg) | |
7763 | return; | |
7764 | /* Protect second load's delay slot. */ | |
7765 | if (!gpr_interlocks) | |
17a2f251 | 7766 | macro_build (NULL, &icnt, NULL, "nop", ""); |
af22f5b2 CD |
7767 | move_register (&icnt, treg, tempreg); |
7768 | break; | |
252b5132 RH |
7769 | |
7770 | case M_ULD_A: | |
7771 | s = "ldl"; | |
7772 | s2 = "ldr"; | |
7773 | off = 7; | |
7774 | goto ulwa; | |
7775 | case M_ULW_A: | |
7776 | s = "lwl"; | |
7777 | s2 = "lwr"; | |
7778 | off = 3; | |
7779 | ulwa: | |
d6bc6245 | 7780 | used_at = 1; |
c9914766 | 7781 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7782 | if (breg != 0) |
17a2f251 TS |
7783 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7784 | AT, AT, breg); | |
252b5132 RH |
7785 | if (! target_big_endian) |
7786 | expr1.X_add_number = off; | |
7787 | else | |
7788 | expr1.X_add_number = 0; | |
17a2f251 TS |
7789 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7790 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7791 | if (! target_big_endian) |
7792 | expr1.X_add_number = 0; | |
7793 | else | |
7794 | expr1.X_add_number = off; | |
17a2f251 TS |
7795 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7796 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7797 | break; |
7798 | ||
7799 | case M_ULH_A: | |
7800 | case M_ULHU_A: | |
d6bc6245 | 7801 | used_at = 1; |
c9914766 | 7802 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7803 | if (breg != 0) |
17a2f251 TS |
7804 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7805 | AT, AT, breg); | |
252b5132 RH |
7806 | if (target_big_endian) |
7807 | expr1.X_add_number = 0; | |
17a2f251 TS |
7808 | macro_build (NULL, &icnt, &expr1, |
7809 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", | |
7810 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7811 | if (target_big_endian) |
7812 | expr1.X_add_number = 1; | |
7813 | else | |
7814 | expr1.X_add_number = 0; | |
17a2f251 TS |
7815 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", |
7816 | AT, BFD_RELOC_LO16, AT); | |
7817 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7818 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7819 | break; |
7820 | ||
7821 | case M_USH: | |
7822 | if (offset_expr.X_add_number >= 0x7fff) | |
7823 | as_bad (_("operand overflow")); | |
7824 | if (target_big_endian) | |
f9419b05 | 7825 | ++offset_expr.X_add_number; |
17a2f251 TS |
7826 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7827 | BFD_RELOC_LO16, breg); | |
7828 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7829 | if (target_big_endian) |
f9419b05 | 7830 | --offset_expr.X_add_number; |
252b5132 | 7831 | else |
f9419b05 | 7832 | ++offset_expr.X_add_number; |
17a2f251 TS |
7833 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7834 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7835 | break; |
7836 | ||
7837 | case M_USD: | |
7838 | s = "sdl"; | |
7839 | s2 = "sdr"; | |
7840 | off = 7; | |
7841 | goto usw; | |
7842 | case M_USW: | |
7843 | s = "swl"; | |
7844 | s2 = "swr"; | |
7845 | off = 3; | |
7846 | usw: | |
7847 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7848 | as_bad (_("operand overflow")); | |
7849 | if (! target_big_endian) | |
7850 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7851 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7852 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7853 | if (! target_big_endian) |
7854 | offset_expr.X_add_number -= off; | |
7855 | else | |
7856 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7857 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
7858 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7859 | return; |
7860 | ||
7861 | case M_USD_A: | |
7862 | s = "sdl"; | |
7863 | s2 = "sdr"; | |
7864 | off = 7; | |
7865 | goto uswa; | |
7866 | case M_USW_A: | |
7867 | s = "swl"; | |
7868 | s2 = "swr"; | |
7869 | off = 3; | |
7870 | uswa: | |
d6bc6245 | 7871 | used_at = 1; |
c9914766 | 7872 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7873 | if (breg != 0) |
17a2f251 TS |
7874 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7875 | AT, AT, breg); | |
252b5132 RH |
7876 | if (! target_big_endian) |
7877 | expr1.X_add_number = off; | |
7878 | else | |
7879 | expr1.X_add_number = 0; | |
17a2f251 TS |
7880 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7881 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7882 | if (! target_big_endian) |
7883 | expr1.X_add_number = 0; | |
7884 | else | |
7885 | expr1.X_add_number = off; | |
17a2f251 TS |
7886 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7887 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7888 | break; |
7889 | ||
7890 | case M_USH_A: | |
d6bc6245 | 7891 | used_at = 1; |
c9914766 | 7892 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7893 | if (breg != 0) |
17a2f251 TS |
7894 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7895 | AT, AT, breg); | |
252b5132 RH |
7896 | if (! target_big_endian) |
7897 | expr1.X_add_number = 0; | |
17a2f251 TS |
7898 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7899 | BFD_RELOC_LO16, AT); | |
7900 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7901 | if (! target_big_endian) |
7902 | expr1.X_add_number = 1; | |
7903 | else | |
7904 | expr1.X_add_number = 0; | |
17a2f251 TS |
7905 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7906 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7907 | if (! target_big_endian) |
7908 | expr1.X_add_number = 0; | |
7909 | else | |
7910 | expr1.X_add_number = 1; | |
17a2f251 TS |
7911 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
7912 | BFD_RELOC_LO16, AT); | |
7913 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7914 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7915 | break; |
7916 | ||
7917 | default: | |
7918 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7919 | are added dynamically. */ |
252b5132 RH |
7920 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7921 | break; | |
7922 | } | |
7923 | if (mips_opts.noat) | |
7924 | as_warn (_("Macro used $at after \".set noat\"")); | |
7925 | } | |
7926 | ||
7927 | /* Implement macros in mips16 mode. */ | |
7928 | ||
7929 | static void | |
17a2f251 | 7930 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7931 | { |
7932 | int mask; | |
7933 | int xreg, yreg, zreg, tmp; | |
7934 | int icnt; | |
7935 | expressionS expr1; | |
7936 | int dbl; | |
7937 | const char *s, *s2, *s3; | |
7938 | ||
7939 | mask = ip->insn_mo->mask; | |
7940 | ||
7941 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7942 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7943 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7944 | ||
7945 | icnt = 0; | |
7946 | ||
7947 | expr1.X_op = O_constant; | |
7948 | expr1.X_op_symbol = NULL; | |
7949 | expr1.X_add_symbol = NULL; | |
7950 | expr1.X_add_number = 1; | |
7951 | ||
7952 | dbl = 0; | |
7953 | ||
7954 | switch (mask) | |
7955 | { | |
7956 | default: | |
7957 | internalError (); | |
7958 | ||
7959 | case M_DDIV_3: | |
7960 | dbl = 1; | |
7961 | case M_DIV_3: | |
7962 | s = "mflo"; | |
7963 | goto do_div3; | |
7964 | case M_DREM_3: | |
7965 | dbl = 1; | |
7966 | case M_REM_3: | |
7967 | s = "mfhi"; | |
7968 | do_div3: | |
b34976b6 | 7969 | mips_emit_delays (TRUE); |
252b5132 RH |
7970 | ++mips_opts.noreorder; |
7971 | mips_any_noreorder = 1; | |
17a2f251 TS |
7972 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y", |
7973 | xreg, yreg); | |
252b5132 | 7974 | expr1.X_add_number = 2; |
17a2f251 TS |
7975 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
7976 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
bdaaa2e1 | 7977 | |
252b5132 RH |
7978 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7979 | since that causes an overflow. We should do that as well, | |
7980 | but I don't see how to do the comparisons without a temporary | |
7981 | register. */ | |
7982 | --mips_opts.noreorder; | |
17a2f251 | 7983 | macro_build (NULL, &icnt, NULL, s, "x", zreg); |
252b5132 RH |
7984 | break; |
7985 | ||
7986 | case M_DIVU_3: | |
7987 | s = "divu"; | |
7988 | s2 = "mflo"; | |
7989 | goto do_divu3; | |
7990 | case M_REMU_3: | |
7991 | s = "divu"; | |
7992 | s2 = "mfhi"; | |
7993 | goto do_divu3; | |
7994 | case M_DDIVU_3: | |
7995 | s = "ddivu"; | |
7996 | s2 = "mflo"; | |
7997 | goto do_divu3; | |
7998 | case M_DREMU_3: | |
7999 | s = "ddivu"; | |
8000 | s2 = "mfhi"; | |
8001 | do_divu3: | |
b34976b6 | 8002 | mips_emit_delays (TRUE); |
252b5132 RH |
8003 | ++mips_opts.noreorder; |
8004 | mips_any_noreorder = 1; | |
17a2f251 | 8005 | macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8006 | expr1.X_add_number = 2; |
17a2f251 TS |
8007 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
8008 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
252b5132 | 8009 | --mips_opts.noreorder; |
17a2f251 | 8010 | macro_build (NULL, &icnt, NULL, s2, "x", zreg); |
252b5132 RH |
8011 | break; |
8012 | ||
8013 | case M_DMUL: | |
8014 | dbl = 1; | |
8015 | case M_MUL: | |
17a2f251 TS |
8016 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y", |
8017 | xreg, yreg); | |
8018 | macro_build (NULL, &icnt, NULL, "mflo", "x", zreg); | |
252b5132 RH |
8019 | return; |
8020 | ||
8021 | case M_DSUBU_I: | |
8022 | dbl = 1; | |
8023 | goto do_subu; | |
8024 | case M_SUBU_I: | |
8025 | do_subu: | |
8026 | if (imm_expr.X_op != O_constant) | |
8027 | as_bad (_("Unsupported large constant")); | |
8028 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
8029 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", |
8030 | yreg, xreg); | |
252b5132 RH |
8031 | break; |
8032 | ||
8033 | case M_SUBU_I_2: | |
8034 | if (imm_expr.X_op != O_constant) | |
8035 | as_bad (_("Unsupported large constant")); | |
8036 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 8037 | macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8038 | break; |
8039 | ||
8040 | case M_DSUBU_I_2: | |
8041 | if (imm_expr.X_op != O_constant) | |
8042 | as_bad (_("Unsupported large constant")); | |
8043 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 8044 | macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8045 | break; |
8046 | ||
8047 | case M_BEQ: | |
8048 | s = "cmp"; | |
8049 | s2 = "bteqz"; | |
8050 | goto do_branch; | |
8051 | case M_BNE: | |
8052 | s = "cmp"; | |
8053 | s2 = "btnez"; | |
8054 | goto do_branch; | |
8055 | case M_BLT: | |
8056 | s = "slt"; | |
8057 | s2 = "btnez"; | |
8058 | goto do_branch; | |
8059 | case M_BLTU: | |
8060 | s = "sltu"; | |
8061 | s2 = "btnez"; | |
8062 | goto do_branch; | |
8063 | case M_BLE: | |
8064 | s = "slt"; | |
8065 | s2 = "bteqz"; | |
8066 | goto do_reverse_branch; | |
8067 | case M_BLEU: | |
8068 | s = "sltu"; | |
8069 | s2 = "bteqz"; | |
8070 | goto do_reverse_branch; | |
8071 | case M_BGE: | |
8072 | s = "slt"; | |
8073 | s2 = "bteqz"; | |
8074 | goto do_branch; | |
8075 | case M_BGEU: | |
8076 | s = "sltu"; | |
8077 | s2 = "bteqz"; | |
8078 | goto do_branch; | |
8079 | case M_BGT: | |
8080 | s = "slt"; | |
8081 | s2 = "btnez"; | |
8082 | goto do_reverse_branch; | |
8083 | case M_BGTU: | |
8084 | s = "sltu"; | |
8085 | s2 = "btnez"; | |
8086 | ||
8087 | do_reverse_branch: | |
8088 | tmp = xreg; | |
8089 | xreg = yreg; | |
8090 | yreg = tmp; | |
8091 | ||
8092 | do_branch: | |
17a2f251 TS |
8093 | macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg); |
8094 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
8095 | break; |
8096 | ||
8097 | case M_BEQ_I: | |
8098 | s = "cmpi"; | |
8099 | s2 = "bteqz"; | |
8100 | s3 = "x,U"; | |
8101 | goto do_branch_i; | |
8102 | case M_BNE_I: | |
8103 | s = "cmpi"; | |
8104 | s2 = "btnez"; | |
8105 | s3 = "x,U"; | |
8106 | goto do_branch_i; | |
8107 | case M_BLT_I: | |
8108 | s = "slti"; | |
8109 | s2 = "btnez"; | |
8110 | s3 = "x,8"; | |
8111 | goto do_branch_i; | |
8112 | case M_BLTU_I: | |
8113 | s = "sltiu"; | |
8114 | s2 = "btnez"; | |
8115 | s3 = "x,8"; | |
8116 | goto do_branch_i; | |
8117 | case M_BLE_I: | |
8118 | s = "slti"; | |
8119 | s2 = "btnez"; | |
8120 | s3 = "x,8"; | |
8121 | goto do_addone_branch_i; | |
8122 | case M_BLEU_I: | |
8123 | s = "sltiu"; | |
8124 | s2 = "btnez"; | |
8125 | s3 = "x,8"; | |
8126 | goto do_addone_branch_i; | |
8127 | case M_BGE_I: | |
8128 | s = "slti"; | |
8129 | s2 = "bteqz"; | |
8130 | s3 = "x,8"; | |
8131 | goto do_branch_i; | |
8132 | case M_BGEU_I: | |
8133 | s = "sltiu"; | |
8134 | s2 = "bteqz"; | |
8135 | s3 = "x,8"; | |
8136 | goto do_branch_i; | |
8137 | case M_BGT_I: | |
8138 | s = "slti"; | |
8139 | s2 = "bteqz"; | |
8140 | s3 = "x,8"; | |
8141 | goto do_addone_branch_i; | |
8142 | case M_BGTU_I: | |
8143 | s = "sltiu"; | |
8144 | s2 = "bteqz"; | |
8145 | s3 = "x,8"; | |
8146 | ||
8147 | do_addone_branch_i: | |
8148 | if (imm_expr.X_op != O_constant) | |
8149 | as_bad (_("Unsupported large constant")); | |
8150 | ++imm_expr.X_add_number; | |
8151 | ||
8152 | do_branch_i: | |
17a2f251 TS |
8153 | macro_build (NULL, &icnt, &imm_expr, s, s3, xreg); |
8154 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
8155 | break; |
8156 | ||
8157 | case M_ABS: | |
8158 | expr1.X_add_number = 0; | |
17a2f251 | 8159 | macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 8160 | if (xreg != yreg) |
ea1fb5dc | 8161 | move_register (&icnt, xreg, yreg); |
252b5132 | 8162 | expr1.X_add_number = 2; |
17a2f251 TS |
8163 | macro_build (NULL, &icnt, &expr1, "bteqz", "p"); |
8164 | macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8165 | } |
8166 | } | |
8167 | ||
8168 | /* For consistency checking, verify that all bits are specified either | |
8169 | by the match/mask part of the instruction definition, or by the | |
8170 | operand list. */ | |
8171 | static int | |
17a2f251 | 8172 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8173 | { |
8174 | const char *p = opc->args; | |
8175 | char c; | |
8176 | unsigned long used_bits = opc->mask; | |
8177 | ||
8178 | if ((used_bits & opc->match) != opc->match) | |
8179 | { | |
8180 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8181 | opc->name, opc->args); | |
8182 | return 0; | |
8183 | } | |
8184 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8185 | while (*p) | |
8186 | switch (c = *p++) | |
8187 | { | |
8188 | case ',': break; | |
8189 | case '(': break; | |
8190 | case ')': break; | |
af7ee8bf CD |
8191 | case '+': |
8192 | switch (c = *p++) | |
8193 | { | |
8194 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8195 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8196 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8197 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8198 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8199 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8200 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8201 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8202 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8203 | case 'I': break; | |
af7ee8bf CD |
8204 | default: |
8205 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8206 | c, opc->name, opc->args); | |
8207 | return 0; | |
8208 | } | |
8209 | break; | |
252b5132 RH |
8210 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8211 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8212 | case 'A': break; | |
4372b673 | 8213 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8214 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8215 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8216 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8217 | case 'F': break; | |
8218 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8219 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8220 | case 'I': break; |
e972090a | 8221 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8222 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8223 | case 'L': break; |
8224 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8225 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8226 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8227 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8228 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8229 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8230 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8231 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8232 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8233 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8234 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8235 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8236 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8237 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8238 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8239 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8240 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8241 | case 'f': break; | |
8242 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8243 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8244 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8245 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8246 | case 'l': break; | |
8247 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8248 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8249 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8250 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8251 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8252 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8253 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8254 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8255 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8256 | case 'x': break; | |
8257 | case 'z': break; | |
8258 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8259 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8260 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8261 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8262 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8263 | case '[': break; | |
8264 | case ']': break; | |
252b5132 RH |
8265 | default: |
8266 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8267 | c, opc->name, opc->args); | |
8268 | return 0; | |
8269 | } | |
8270 | #undef USE_BITS | |
8271 | if (used_bits != 0xffffffff) | |
8272 | { | |
8273 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8274 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8275 | return 0; | |
8276 | } | |
8277 | return 1; | |
8278 | } | |
8279 | ||
8280 | /* This routine assembles an instruction into its binary format. As a | |
8281 | side effect, it sets one of the global variables imm_reloc or | |
8282 | offset_reloc to the type of relocation to do if one of the operands | |
8283 | is an address expression. */ | |
8284 | ||
8285 | static void | |
17a2f251 | 8286 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8287 | { |
8288 | char *s; | |
8289 | const char *args; | |
43841e91 | 8290 | char c = 0; |
252b5132 RH |
8291 | struct mips_opcode *insn; |
8292 | char *argsStart; | |
8293 | unsigned int regno; | |
8294 | unsigned int lastregno = 0; | |
af7ee8bf | 8295 | unsigned int lastpos = 0; |
071742cf | 8296 | unsigned int limlo, limhi; |
252b5132 RH |
8297 | char *s_reset; |
8298 | char save_c = 0; | |
252b5132 RH |
8299 | |
8300 | insn_error = NULL; | |
8301 | ||
8302 | /* If the instruction contains a '.', we first try to match an instruction | |
8303 | including the '.'. Then we try again without the '.'. */ | |
8304 | insn = NULL; | |
3882b010 | 8305 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8306 | continue; |
8307 | ||
8308 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8309 | the call to hash_find. Save the character we replaced just in case we | |
8310 | have to re-parse the instruction. */ | |
3882b010 | 8311 | if (ISSPACE (*s)) |
252b5132 RH |
8312 | { |
8313 | save_c = *s; | |
8314 | *s++ = '\0'; | |
8315 | } | |
bdaaa2e1 | 8316 | |
252b5132 RH |
8317 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8318 | ||
8319 | /* If we didn't find the instruction in the opcode table, try again, but | |
8320 | this time with just the instruction up to, but not including the | |
8321 | first '.'. */ | |
8322 | if (insn == NULL) | |
8323 | { | |
bdaaa2e1 | 8324 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8325 | if (save_c) |
8326 | *(--s) = save_c; | |
8327 | ||
8328 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8329 | for (s = str; |
8330 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8331 | ++s) | |
252b5132 RH |
8332 | continue; |
8333 | ||
8334 | /* If we did not find a '.', then we can quit now. */ | |
8335 | if (*s != '.') | |
8336 | { | |
8337 | insn_error = "unrecognized opcode"; | |
8338 | return; | |
8339 | } | |
8340 | ||
8341 | /* Lookup the instruction in the hash table. */ | |
8342 | *s++ = '\0'; | |
8343 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8344 | { | |
8345 | insn_error = "unrecognized opcode"; | |
8346 | return; | |
8347 | } | |
252b5132 RH |
8348 | } |
8349 | ||
8350 | argsStart = s; | |
8351 | for (;;) | |
8352 | { | |
b34976b6 | 8353 | bfd_boolean ok; |
252b5132 RH |
8354 | |
8355 | assert (strcmp (insn->name, str) == 0); | |
8356 | ||
1f25f5d3 CD |
8357 | if (OPCODE_IS_MEMBER (insn, |
8358 | (mips_opts.isa | |
3396de36 | 8359 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8360 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8361 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8362 | mips_opts.arch)) |
b34976b6 | 8363 | ok = TRUE; |
bdaaa2e1 | 8364 | else |
b34976b6 | 8365 | ok = FALSE; |
bdaaa2e1 | 8366 | |
252b5132 RH |
8367 | if (insn->pinfo != INSN_MACRO) |
8368 | { | |
fef14a42 | 8369 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8370 | ok = FALSE; |
252b5132 RH |
8371 | } |
8372 | ||
8373 | if (! ok) | |
8374 | { | |
8375 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8376 | && strcmp (insn->name, insn[1].name) == 0) | |
8377 | { | |
8378 | ++insn; | |
8379 | continue; | |
8380 | } | |
252b5132 | 8381 | else |
beae10d5 | 8382 | { |
268f6bed L |
8383 | if (!insn_error) |
8384 | { | |
8385 | static char buf[100]; | |
fef14a42 TS |
8386 | sprintf (buf, |
8387 | _("opcode not supported on this processor: %s (%s)"), | |
8388 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8389 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8390 | insn_error = buf; |
8391 | } | |
8392 | if (save_c) | |
8393 | *(--s) = save_c; | |
2bd7f1f3 | 8394 | return; |
252b5132 | 8395 | } |
252b5132 RH |
8396 | } |
8397 | ||
8398 | ip->insn_mo = insn; | |
8399 | ip->insn_opcode = insn->match; | |
268f6bed | 8400 | insn_error = NULL; |
252b5132 RH |
8401 | for (args = insn->args;; ++args) |
8402 | { | |
deec1734 CD |
8403 | int is_mdmx; |
8404 | ||
ad8d3bb3 | 8405 | s += strspn (s, " \t"); |
deec1734 | 8406 | is_mdmx = 0; |
252b5132 RH |
8407 | switch (*args) |
8408 | { | |
8409 | case '\0': /* end of args */ | |
8410 | if (*s == '\0') | |
8411 | return; | |
8412 | break; | |
8413 | ||
8414 | case ',': | |
8415 | if (*s++ == *args) | |
8416 | continue; | |
8417 | s--; | |
8418 | switch (*++args) | |
8419 | { | |
8420 | case 'r': | |
8421 | case 'v': | |
38487616 | 8422 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8423 | continue; |
8424 | ||
8425 | case 'w': | |
38487616 TS |
8426 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8427 | continue; | |
8428 | ||
252b5132 | 8429 | case 'W': |
38487616 | 8430 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8431 | continue; |
8432 | ||
8433 | case 'V': | |
38487616 | 8434 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8435 | continue; |
8436 | } | |
8437 | break; | |
8438 | ||
8439 | case '(': | |
8440 | /* Handle optional base register. | |
8441 | Either the base register is omitted or | |
bdaaa2e1 | 8442 | we must have a left paren. */ |
252b5132 RH |
8443 | /* This is dependent on the next operand specifier |
8444 | is a base register specification. */ | |
8445 | assert (args[1] == 'b' || args[1] == '5' | |
8446 | || args[1] == '-' || args[1] == '4'); | |
8447 | if (*s == '\0') | |
8448 | return; | |
8449 | ||
8450 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8451 | case '[': |
8452 | case ']': | |
252b5132 RH |
8453 | if (*s++ == *args) |
8454 | continue; | |
8455 | break; | |
8456 | ||
af7ee8bf CD |
8457 | case '+': /* Opcode extension character. */ |
8458 | switch (*++args) | |
8459 | { | |
071742cf CD |
8460 | case 'A': /* ins/ext position, becomes LSB. */ |
8461 | limlo = 0; | |
8462 | limhi = 31; | |
5f74bc13 CD |
8463 | goto do_lsb; |
8464 | case 'E': | |
8465 | limlo = 32; | |
8466 | limhi = 63; | |
8467 | goto do_lsb; | |
8468 | do_lsb: | |
071742cf CD |
8469 | my_getExpression (&imm_expr, s); |
8470 | check_absolute_expr (ip, &imm_expr); | |
8471 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8472 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8473 | { | |
8474 | as_bad (_("Improper position (%lu)"), | |
8475 | (unsigned long) imm_expr.X_add_number); | |
8476 | imm_expr.X_add_number = limlo; | |
8477 | } | |
8478 | lastpos = imm_expr.X_add_number; | |
8479 | ip->insn_opcode |= (imm_expr.X_add_number | |
8480 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8481 | imm_expr.X_op = O_absent; | |
8482 | s = expr_end; | |
8483 | continue; | |
8484 | ||
8485 | case 'B': /* ins size, becomes MSB. */ | |
8486 | limlo = 1; | |
8487 | limhi = 32; | |
5f74bc13 CD |
8488 | goto do_msb; |
8489 | case 'F': | |
8490 | limlo = 33; | |
8491 | limhi = 64; | |
8492 | goto do_msb; | |
8493 | do_msb: | |
071742cf CD |
8494 | my_getExpression (&imm_expr, s); |
8495 | check_absolute_expr (ip, &imm_expr); | |
8496 | /* Check for negative input so that small negative numbers | |
8497 | will not succeed incorrectly. The checks against | |
8498 | (pos+size) transitively check "size" itself, | |
8499 | assuming that "pos" is reasonable. */ | |
8500 | if ((long) imm_expr.X_add_number < 0 | |
8501 | || ((unsigned long) imm_expr.X_add_number | |
8502 | + lastpos) < limlo | |
8503 | || ((unsigned long) imm_expr.X_add_number | |
8504 | + lastpos) > limhi) | |
8505 | { | |
8506 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8507 | (unsigned long) imm_expr.X_add_number, | |
8508 | (unsigned long) lastpos); | |
8509 | imm_expr.X_add_number = limlo - lastpos; | |
8510 | } | |
8511 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8512 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8513 | imm_expr.X_op = O_absent; | |
8514 | s = expr_end; | |
8515 | continue; | |
8516 | ||
8517 | case 'C': /* ext size, becomes MSBD. */ | |
8518 | limlo = 1; | |
8519 | limhi = 32; | |
5f74bc13 CD |
8520 | goto do_msbd; |
8521 | case 'G': | |
8522 | limlo = 33; | |
8523 | limhi = 64; | |
8524 | goto do_msbd; | |
8525 | case 'H': | |
8526 | limlo = 33; | |
8527 | limhi = 64; | |
8528 | goto do_msbd; | |
8529 | do_msbd: | |
071742cf CD |
8530 | my_getExpression (&imm_expr, s); |
8531 | check_absolute_expr (ip, &imm_expr); | |
8532 | /* Check for negative input so that small negative numbers | |
8533 | will not succeed incorrectly. The checks against | |
8534 | (pos+size) transitively check "size" itself, | |
8535 | assuming that "pos" is reasonable. */ | |
8536 | if ((long) imm_expr.X_add_number < 0 | |
8537 | || ((unsigned long) imm_expr.X_add_number | |
8538 | + lastpos) < limlo | |
8539 | || ((unsigned long) imm_expr.X_add_number | |
8540 | + lastpos) > limhi) | |
8541 | { | |
8542 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8543 | (unsigned long) imm_expr.X_add_number, | |
8544 | (unsigned long) lastpos); | |
8545 | imm_expr.X_add_number = limlo - lastpos; | |
8546 | } | |
8547 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8548 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8549 | imm_expr.X_op = O_absent; | |
8550 | s = expr_end; | |
8551 | continue; | |
af7ee8bf | 8552 | |
bbcc0807 CD |
8553 | case 'D': |
8554 | /* +D is for disassembly only; never match. */ | |
8555 | break; | |
8556 | ||
5f74bc13 CD |
8557 | case 'I': |
8558 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8559 | my_getExpression (&imm2_expr, s); | |
8560 | if (imm2_expr.X_op != O_big | |
8561 | && imm2_expr.X_op != O_constant) | |
8562 | insn_error = _("absolute expression required"); | |
13757d0c | 8563 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8564 | s = expr_end; |
8565 | continue; | |
8566 | ||
af7ee8bf CD |
8567 | default: |
8568 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8569 | *args, insn->name, insn->args); | |
8570 | /* Further processing is fruitless. */ | |
8571 | return; | |
8572 | } | |
8573 | break; | |
8574 | ||
252b5132 RH |
8575 | case '<': /* must be at least one digit */ |
8576 | /* | |
8577 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8578 | * than 31 or less than 0, then the shift amount should be |
8579 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8580 | * We issue a warning and mask out all but the low 5 bits. |
8581 | */ | |
8582 | my_getExpression (&imm_expr, s); | |
8583 | check_absolute_expr (ip, &imm_expr); | |
8584 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8585 | { | |
793b27f4 TS |
8586 | as_warn (_("Improper shift amount (%lu)"), |
8587 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8588 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8589 | } |
38487616 | 8590 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8591 | imm_expr.X_op = O_absent; |
8592 | s = expr_end; | |
8593 | continue; | |
8594 | ||
8595 | case '>': /* shift amount minus 32 */ | |
8596 | my_getExpression (&imm_expr, s); | |
8597 | check_absolute_expr (ip, &imm_expr); | |
8598 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8599 | || (unsigned long) imm_expr.X_add_number > 63) | |
8600 | break; | |
38487616 | 8601 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8602 | imm_expr.X_op = O_absent; |
8603 | s = expr_end; | |
8604 | continue; | |
8605 | ||
252b5132 RH |
8606 | case 'k': /* cache code */ |
8607 | case 'h': /* prefx code */ | |
8608 | my_getExpression (&imm_expr, s); | |
8609 | check_absolute_expr (ip, &imm_expr); | |
8610 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8611 | { | |
8612 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8613 | ip->insn_mo->name, | |
8614 | (unsigned long) imm_expr.X_add_number); | |
8615 | imm_expr.X_add_number &= 0x1f; | |
8616 | } | |
8617 | if (*args == 'k') | |
8618 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8619 | else | |
8620 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8621 | imm_expr.X_op = O_absent; | |
8622 | s = expr_end; | |
8623 | continue; | |
8624 | ||
8625 | case 'c': /* break code */ | |
8626 | my_getExpression (&imm_expr, s); | |
8627 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8628 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8629 | { |
793b27f4 TS |
8630 | as_warn (_("Illegal break code (%lu)"), |
8631 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8632 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8633 | } |
38487616 | 8634 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8635 | imm_expr.X_op = O_absent; |
8636 | s = expr_end; | |
8637 | continue; | |
8638 | ||
8639 | case 'q': /* lower break code */ | |
8640 | my_getExpression (&imm_expr, s); | |
8641 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8642 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8643 | { |
793b27f4 TS |
8644 | as_warn (_("Illegal lower break code (%lu)"), |
8645 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8646 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8647 | } |
38487616 | 8648 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8649 | imm_expr.X_op = O_absent; |
8650 | s = expr_end; | |
8651 | continue; | |
8652 | ||
4372b673 | 8653 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8654 | my_getExpression (&imm_expr, s); |
156c2f8b | 8655 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8656 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8657 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8658 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8659 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8660 | imm_expr.X_op = O_absent; |
8661 | s = expr_end; | |
8662 | continue; | |
8663 | ||
98d3f06f | 8664 | case 'C': /* Coprocessor code */ |
beae10d5 | 8665 | my_getExpression (&imm_expr, s); |
252b5132 | 8666 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8667 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8668 | { |
793b27f4 TS |
8669 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8670 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8671 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8672 | } |
beae10d5 KH |
8673 | ip->insn_opcode |= imm_expr.X_add_number; |
8674 | imm_expr.X_op = O_absent; | |
8675 | s = expr_end; | |
8676 | continue; | |
252b5132 | 8677 | |
4372b673 NC |
8678 | case 'J': /* 19-bit wait code. */ |
8679 | my_getExpression (&imm_expr, s); | |
8680 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8681 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8682 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8683 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8684 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8685 | imm_expr.X_op = O_absent; |
8686 | s = expr_end; | |
8687 | continue; | |
8688 | ||
252b5132 | 8689 | case 'P': /* Performance register */ |
beae10d5 | 8690 | my_getExpression (&imm_expr, s); |
252b5132 | 8691 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8692 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8693 | { |
793b27f4 TS |
8694 | as_warn (_("Invalid performance register (%lu)"), |
8695 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8696 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8697 | } |
38487616 | 8698 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8699 | imm_expr.X_op = O_absent; |
8700 | s = expr_end; | |
8701 | continue; | |
252b5132 RH |
8702 | |
8703 | case 'b': /* base register */ | |
8704 | case 'd': /* destination register */ | |
8705 | case 's': /* source register */ | |
8706 | case 't': /* target register */ | |
8707 | case 'r': /* both target and source */ | |
8708 | case 'v': /* both dest and source */ | |
8709 | case 'w': /* both dest and target */ | |
8710 | case 'E': /* coprocessor target register */ | |
8711 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8712 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8713 | case 'x': /* ignore register name */ |
8714 | case 'z': /* must be zero register */ | |
4372b673 | 8715 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8716 | s_reset = s; |
8717 | if (s[0] == '$') | |
8718 | { | |
8719 | ||
3882b010 | 8720 | if (ISDIGIT (s[1])) |
252b5132 RH |
8721 | { |
8722 | ++s; | |
8723 | regno = 0; | |
8724 | do | |
8725 | { | |
8726 | regno *= 10; | |
8727 | regno += *s - '0'; | |
8728 | ++s; | |
8729 | } | |
3882b010 | 8730 | while (ISDIGIT (*s)); |
252b5132 RH |
8731 | if (regno > 31) |
8732 | as_bad (_("Invalid register number (%d)"), regno); | |
8733 | } | |
af7ee8bf | 8734 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8735 | goto notreg; |
8736 | else | |
8737 | { | |
76db943d TS |
8738 | if (s[1] == 'r' && s[2] == 'a') |
8739 | { | |
8740 | s += 3; | |
8741 | regno = RA; | |
8742 | } | |
8743 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8744 | { |
8745 | s += 3; | |
8746 | regno = FP; | |
8747 | } | |
8748 | else if (s[1] == 's' && s[2] == 'p') | |
8749 | { | |
8750 | s += 3; | |
8751 | regno = SP; | |
8752 | } | |
8753 | else if (s[1] == 'g' && s[2] == 'p') | |
8754 | { | |
8755 | s += 3; | |
8756 | regno = GP; | |
8757 | } | |
8758 | else if (s[1] == 'a' && s[2] == 't') | |
8759 | { | |
8760 | s += 3; | |
8761 | regno = AT; | |
8762 | } | |
8763 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8764 | { | |
8765 | s += 4; | |
8766 | regno = KT0; | |
8767 | } | |
8768 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8769 | { | |
8770 | s += 4; | |
8771 | regno = KT1; | |
8772 | } | |
85b51719 TS |
8773 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8774 | { | |
8775 | s += 5; | |
8776 | regno = ZERO; | |
8777 | } | |
252b5132 RH |
8778 | else if (itbl_have_entries) |
8779 | { | |
8780 | char *p, *n; | |
d7ba4a77 | 8781 | unsigned long r; |
252b5132 | 8782 | |
d7ba4a77 | 8783 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8784 | n = itbl_get_field (&p); /* n is name */ |
8785 | ||
d7ba4a77 ILT |
8786 | /* See if this is a register defined in an |
8787 | itbl entry. */ | |
8788 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8789 | { |
8790 | /* Get_field advances to the start of | |
8791 | the next field, so we need to back | |
d7ba4a77 | 8792 | rack to the end of the last field. */ |
bdaaa2e1 | 8793 | if (p) |
252b5132 | 8794 | s = p - 1; |
bdaaa2e1 | 8795 | else |
d7ba4a77 | 8796 | s = strchr (s, '\0'); |
252b5132 RH |
8797 | regno = r; |
8798 | } | |
8799 | else | |
8800 | goto notreg; | |
beae10d5 | 8801 | } |
252b5132 RH |
8802 | else |
8803 | goto notreg; | |
8804 | } | |
8805 | if (regno == AT | |
8806 | && ! mips_opts.noat | |
8807 | && *args != 'E' | |
af7ee8bf CD |
8808 | && *args != 'G' |
8809 | && *args != 'K') | |
252b5132 RH |
8810 | as_warn (_("Used $at without \".set noat\"")); |
8811 | c = *args; | |
8812 | if (*s == ' ') | |
f9419b05 | 8813 | ++s; |
252b5132 RH |
8814 | if (args[1] != *s) |
8815 | { | |
8816 | if (c == 'r' || c == 'v' || c == 'w') | |
8817 | { | |
8818 | regno = lastregno; | |
8819 | s = s_reset; | |
f9419b05 | 8820 | ++args; |
252b5132 RH |
8821 | } |
8822 | } | |
8823 | /* 'z' only matches $0. */ | |
8824 | if (c == 'z' && regno != 0) | |
8825 | break; | |
8826 | ||
bdaaa2e1 KH |
8827 | /* Now that we have assembled one operand, we use the args string |
8828 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8829 | switch (c) |
8830 | { | |
8831 | case 'r': | |
8832 | case 's': | |
8833 | case 'v': | |
8834 | case 'b': | |
38487616 | 8835 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8836 | break; |
8837 | case 'd': | |
8838 | case 'G': | |
af7ee8bf | 8839 | case 'K': |
38487616 | 8840 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8841 | break; |
4372b673 | 8842 | case 'U': |
38487616 TS |
8843 | ip->insn_opcode |= regno << OP_SH_RD; |
8844 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8845 | break; |
252b5132 RH |
8846 | case 'w': |
8847 | case 't': | |
8848 | case 'E': | |
38487616 | 8849 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8850 | break; |
8851 | case 'x': | |
8852 | /* This case exists because on the r3000 trunc | |
8853 | expands into a macro which requires a gp | |
8854 | register. On the r6000 or r4000 it is | |
8855 | assembled into a single instruction which | |
8856 | ignores the register. Thus the insn version | |
8857 | is MIPS_ISA2 and uses 'x', and the macro | |
8858 | version is MIPS_ISA1 and uses 't'. */ | |
8859 | break; | |
8860 | case 'z': | |
8861 | /* This case is for the div instruction, which | |
8862 | acts differently if the destination argument | |
8863 | is $0. This only matches $0, and is checked | |
8864 | outside the switch. */ | |
8865 | break; | |
8866 | case 'D': | |
8867 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8868 | break; | |
8869 | /* What about all other operands like 'i', which | |
8870 | can be specified in the opcode table? */ | |
8871 | } | |
8872 | lastregno = regno; | |
8873 | continue; | |
8874 | } | |
8875 | notreg: | |
8876 | switch (*args++) | |
8877 | { | |
8878 | case 'r': | |
8879 | case 'v': | |
38487616 | 8880 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8881 | continue; |
8882 | case 'w': | |
38487616 | 8883 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8884 | continue; |
8885 | } | |
8886 | break; | |
8887 | ||
deec1734 CD |
8888 | case 'O': /* MDMX alignment immediate constant. */ |
8889 | my_getExpression (&imm_expr, s); | |
8890 | check_absolute_expr (ip, &imm_expr); | |
8891 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8892 | { | |
8893 | as_warn ("Improper align amount (%ld), using low bits", | |
8894 | (long) imm_expr.X_add_number); | |
8895 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8896 | } | |
8897 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8898 | imm_expr.X_op = O_absent; | |
8899 | s = expr_end; | |
8900 | continue; | |
8901 | ||
8902 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8903 | if (s[0] != '$') | |
8904 | { | |
8905 | /* MDMX Immediate. */ | |
8906 | my_getExpression (&imm_expr, s); | |
8907 | check_absolute_expr (ip, &imm_expr); | |
8908 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8909 | { | |
8910 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8911 | (long) imm_expr.X_add_number); | |
8912 | imm_expr.X_add_number &= OP_MASK_FT; | |
8913 | } | |
8914 | imm_expr.X_add_number &= OP_MASK_FT; | |
8915 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8916 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8917 | else | |
8918 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8919 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8920 | imm_expr.X_op = O_absent; | |
8921 | s = expr_end; | |
8922 | continue; | |
8923 | } | |
8924 | /* Not MDMX Immediate. Fall through. */ | |
8925 | case 'X': /* MDMX destination register. */ | |
8926 | case 'Y': /* MDMX source register. */ | |
8927 | case 'Z': /* MDMX target register. */ | |
8928 | is_mdmx = 1; | |
252b5132 RH |
8929 | case 'D': /* floating point destination register */ |
8930 | case 'S': /* floating point source register */ | |
8931 | case 'T': /* floating point target register */ | |
8932 | case 'R': /* floating point source register */ | |
8933 | case 'V': | |
8934 | case 'W': | |
8935 | s_reset = s; | |
deec1734 CD |
8936 | /* Accept $fN for FP and MDMX register numbers, and in |
8937 | addition accept $vN for MDMX register numbers. */ | |
8938 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8939 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8940 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8941 | { |
8942 | s += 2; | |
8943 | regno = 0; | |
8944 | do | |
8945 | { | |
8946 | regno *= 10; | |
8947 | regno += *s - '0'; | |
8948 | ++s; | |
8949 | } | |
3882b010 | 8950 | while (ISDIGIT (*s)); |
252b5132 RH |
8951 | |
8952 | if (regno > 31) | |
8953 | as_bad (_("Invalid float register number (%d)"), regno); | |
8954 | ||
8955 | if ((regno & 1) != 0 | |
ca4e0257 | 8956 | && HAVE_32BIT_FPRS |
252b5132 RH |
8957 | && ! (strcmp (str, "mtc1") == 0 |
8958 | || strcmp (str, "mfc1") == 0 | |
8959 | || strcmp (str, "lwc1") == 0 | |
8960 | || strcmp (str, "swc1") == 0 | |
8961 | || strcmp (str, "l.s") == 0 | |
8962 | || strcmp (str, "s.s") == 0)) | |
8963 | as_warn (_("Float register should be even, was %d"), | |
8964 | regno); | |
8965 | ||
8966 | c = *args; | |
8967 | if (*s == ' ') | |
f9419b05 | 8968 | ++s; |
252b5132 RH |
8969 | if (args[1] != *s) |
8970 | { | |
8971 | if (c == 'V' || c == 'W') | |
8972 | { | |
8973 | regno = lastregno; | |
8974 | s = s_reset; | |
f9419b05 | 8975 | ++args; |
252b5132 RH |
8976 | } |
8977 | } | |
8978 | switch (c) | |
8979 | { | |
8980 | case 'D': | |
deec1734 | 8981 | case 'X': |
38487616 | 8982 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8983 | break; |
8984 | case 'V': | |
8985 | case 'S': | |
deec1734 | 8986 | case 'Y': |
38487616 | 8987 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8988 | break; |
deec1734 CD |
8989 | case 'Q': |
8990 | /* This is like 'Z', but also needs to fix the MDMX | |
8991 | vector/scalar select bits. Note that the | |
8992 | scalar immediate case is handled above. */ | |
8993 | if (*s == '[') | |
8994 | { | |
8995 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8996 | int max_el = (is_qh ? 3 : 7); | |
8997 | s++; | |
8998 | my_getExpression(&imm_expr, s); | |
8999 | check_absolute_expr (ip, &imm_expr); | |
9000 | s = expr_end; | |
9001 | if (imm_expr.X_add_number > max_el) | |
9002 | as_bad(_("Bad element selector %ld"), | |
9003 | (long) imm_expr.X_add_number); | |
9004 | imm_expr.X_add_number &= max_el; | |
9005 | ip->insn_opcode |= (imm_expr.X_add_number | |
9006 | << (OP_SH_VSEL + | |
9007 | (is_qh ? 2 : 1))); | |
9008 | if (*s != ']') | |
9009 | as_warn(_("Expecting ']' found '%s'"), s); | |
9010 | else | |
9011 | s++; | |
9012 | } | |
9013 | else | |
9014 | { | |
9015 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9016 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9017 | << OP_SH_VSEL); | |
9018 | else | |
9019 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9020 | OP_SH_VSEL); | |
9021 | } | |
9022 | /* Fall through */ | |
252b5132 RH |
9023 | case 'W': |
9024 | case 'T': | |
deec1734 | 9025 | case 'Z': |
38487616 | 9026 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
9027 | break; |
9028 | case 'R': | |
38487616 | 9029 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
9030 | break; |
9031 | } | |
9032 | lastregno = regno; | |
9033 | continue; | |
9034 | } | |
9035 | ||
252b5132 RH |
9036 | switch (*args++) |
9037 | { | |
9038 | case 'V': | |
38487616 | 9039 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
9040 | continue; |
9041 | case 'W': | |
38487616 | 9042 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
9043 | continue; |
9044 | } | |
9045 | break; | |
9046 | ||
9047 | case 'I': | |
9048 | my_getExpression (&imm_expr, s); | |
9049 | if (imm_expr.X_op != O_big | |
9050 | && imm_expr.X_op != O_constant) | |
9051 | insn_error = _("absolute expression required"); | |
13757d0c | 9052 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
9053 | s = expr_end; |
9054 | continue; | |
9055 | ||
9056 | case 'A': | |
9057 | my_getExpression (&offset_expr, s); | |
f6688943 | 9058 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9059 | s = expr_end; |
9060 | continue; | |
9061 | ||
9062 | case 'F': | |
9063 | case 'L': | |
9064 | case 'f': | |
9065 | case 'l': | |
9066 | { | |
9067 | int f64; | |
ca4e0257 | 9068 | int using_gprs; |
252b5132 RH |
9069 | char *save_in; |
9070 | char *err; | |
9071 | unsigned char temp[8]; | |
9072 | int len; | |
9073 | unsigned int length; | |
9074 | segT seg; | |
9075 | subsegT subseg; | |
9076 | char *p; | |
9077 | ||
9078 | /* These only appear as the last operand in an | |
9079 | instruction, and every instruction that accepts | |
9080 | them in any variant accepts them in all variants. | |
9081 | This means we don't have to worry about backing out | |
9082 | any changes if the instruction does not match. | |
9083 | ||
9084 | The difference between them is the size of the | |
9085 | floating point constant and where it goes. For 'F' | |
9086 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9087 | is 32 bits. Where the constant is placed is based | |
9088 | on how the MIPS assembler does things: | |
9089 | F -- .rdata | |
9090 | L -- .lit8 | |
9091 | f -- immediate value | |
9092 | l -- .lit4 | |
9093 | ||
9094 | The .lit4 and .lit8 sections are only used if | |
9095 | permitted by the -G argument. | |
9096 | ||
9097 | When generating embedded PIC code, we use the | |
9098 | .lit8 section but not the .lit4 section (we can do | |
9099 | .lit4 inline easily; we need to put .lit8 | |
9100 | somewhere in the data segment, and using .lit8 | |
9101 | permits the linker to eventually combine identical | |
ca4e0257 RS |
9102 | .lit8 entries). |
9103 | ||
9104 | The code below needs to know whether the target register | |
9105 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9106 | 'F' are used with GPR-based instructions and 'l' and | |
9107 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9108 | |
9109 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9110 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9111 | |
9112 | save_in = input_line_pointer; | |
9113 | input_line_pointer = s; | |
9114 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9115 | length = len; | |
9116 | s = input_line_pointer; | |
9117 | input_line_pointer = save_in; | |
9118 | if (err != NULL && *err != '\0') | |
9119 | { | |
9120 | as_bad (_("Bad floating point constant: %s"), err); | |
9121 | memset (temp, '\0', sizeof temp); | |
9122 | length = f64 ? 8 : 4; | |
9123 | } | |
9124 | ||
156c2f8b | 9125 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9126 | |
9127 | if (*args == 'f' | |
9128 | || (*args == 'l' | |
9129 | && (! USE_GLOBAL_POINTER_OPT | |
9130 | || mips_pic == EMBEDDED_PIC | |
9131 | || g_switch_value < 4 | |
9132 | || (temp[0] == 0 && temp[1] == 0) | |
9133 | || (temp[2] == 0 && temp[3] == 0)))) | |
9134 | { | |
9135 | imm_expr.X_op = O_constant; | |
9136 | if (! target_big_endian) | |
9137 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9138 | else | |
9139 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9140 | } | |
9141 | else if (length > 4 | |
119d663a | 9142 | && ! mips_disable_float_construction |
ca4e0257 RS |
9143 | /* Constants can only be constructed in GPRs and |
9144 | copied to FPRs if the GPRs are at least as wide | |
9145 | as the FPRs. Force the constant into memory if | |
9146 | we are using 64-bit FPRs but the GPRs are only | |
9147 | 32 bits wide. */ | |
9148 | && (using_gprs | |
9149 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9150 | && ((temp[0] == 0 && temp[1] == 0) |
9151 | || (temp[2] == 0 && temp[3] == 0)) | |
9152 | && ((temp[4] == 0 && temp[5] == 0) | |
9153 | || (temp[6] == 0 && temp[7] == 0))) | |
9154 | { | |
ca4e0257 RS |
9155 | /* The value is simple enough to load with a couple of |
9156 | instructions. If using 32-bit registers, set | |
9157 | imm_expr to the high order 32 bits and offset_expr to | |
9158 | the low order 32 bits. Otherwise, set imm_expr to | |
9159 | the entire 64 bit constant. */ | |
9160 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9161 | { |
9162 | imm_expr.X_op = O_constant; | |
9163 | offset_expr.X_op = O_constant; | |
9164 | if (! target_big_endian) | |
9165 | { | |
9166 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9167 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9168 | } | |
9169 | else | |
9170 | { | |
9171 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9172 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9173 | } | |
9174 | if (offset_expr.X_add_number == 0) | |
9175 | offset_expr.X_op = O_absent; | |
9176 | } | |
9177 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9178 | { | |
9179 | imm_expr.X_op = O_constant; | |
9180 | if (! target_big_endian) | |
9181 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9182 | else | |
9183 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9184 | } | |
9185 | else | |
9186 | { | |
9187 | imm_expr.X_op = O_big; | |
9188 | imm_expr.X_add_number = 4; | |
9189 | if (! target_big_endian) | |
9190 | { | |
9191 | generic_bignum[0] = bfd_getl16 (temp); | |
9192 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9193 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9194 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9195 | } | |
9196 | else | |
9197 | { | |
9198 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9199 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9200 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9201 | generic_bignum[3] = bfd_getb16 (temp); | |
9202 | } | |
9203 | } | |
9204 | } | |
9205 | else | |
9206 | { | |
9207 | const char *newname; | |
9208 | segT new_seg; | |
9209 | ||
9210 | /* Switch to the right section. */ | |
9211 | seg = now_seg; | |
9212 | subseg = now_subseg; | |
9213 | switch (*args) | |
9214 | { | |
9215 | default: /* unused default case avoids warnings. */ | |
9216 | case 'L': | |
9217 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9218 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9219 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9220 | newname = ".lit8"; |
9221 | break; | |
9222 | case 'F': | |
bb2d6cd7 GK |
9223 | if (mips_pic == EMBEDDED_PIC) |
9224 | newname = ".lit8"; | |
9225 | else | |
9226 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9227 | break; |
9228 | case 'l': | |
9229 | assert (!USE_GLOBAL_POINTER_OPT | |
9230 | || g_switch_value >= 4); | |
9231 | newname = ".lit4"; | |
9232 | break; | |
9233 | } | |
9234 | new_seg = subseg_new (newname, (subsegT) 0); | |
9235 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9236 | bfd_set_section_flags (stdoutput, new_seg, | |
9237 | (SEC_ALLOC | |
9238 | | SEC_LOAD | |
9239 | | SEC_READONLY | |
9240 | | SEC_DATA)); | |
9241 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9242 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9243 | && strcmp (TARGET_OS, "elf") != 0) | |
9244 | record_alignment (new_seg, 4); | |
9245 | else | |
9246 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9247 | if (seg == now_seg) | |
9248 | as_bad (_("Can't use floating point insn in this section")); | |
9249 | ||
9250 | /* Set the argument to the current address in the | |
9251 | section. */ | |
9252 | offset_expr.X_op = O_symbol; | |
9253 | offset_expr.X_add_symbol = | |
9254 | symbol_new ("L0\001", now_seg, | |
9255 | (valueT) frag_now_fix (), frag_now); | |
9256 | offset_expr.X_add_number = 0; | |
9257 | ||
9258 | /* Put the floating point number into the section. */ | |
9259 | p = frag_more ((int) length); | |
9260 | memcpy (p, temp, length); | |
9261 | ||
9262 | /* Switch back to the original section. */ | |
9263 | subseg_set (seg, subseg); | |
9264 | } | |
9265 | } | |
9266 | continue; | |
9267 | ||
9268 | case 'i': /* 16 bit unsigned immediate */ | |
9269 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9270 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9271 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9272 | { |
9273 | int more; | |
5e0116d5 RS |
9274 | offsetT minval, maxval; |
9275 | ||
9276 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9277 | && strcmp (insn->name, insn[1].name) == 0); | |
9278 | ||
9279 | /* If the expression was written as an unsigned number, | |
9280 | only treat it as signed if there are no more | |
9281 | alternatives. */ | |
9282 | if (more | |
9283 | && *args == 'j' | |
9284 | && sizeof (imm_expr.X_add_number) <= 4 | |
9285 | && imm_expr.X_op == O_constant | |
9286 | && imm_expr.X_add_number < 0 | |
9287 | && imm_expr.X_unsigned | |
9288 | && HAVE_64BIT_GPRS) | |
9289 | break; | |
9290 | ||
9291 | /* For compatibility with older assemblers, we accept | |
9292 | 0x8000-0xffff as signed 16-bit numbers when only | |
9293 | signed numbers are allowed. */ | |
9294 | if (*args == 'i') | |
9295 | minval = 0, maxval = 0xffff; | |
9296 | else if (more) | |
9297 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9298 | else |
5e0116d5 RS |
9299 | minval = -0x8000, maxval = 0xffff; |
9300 | ||
9301 | if (imm_expr.X_op != O_constant | |
9302 | || imm_expr.X_add_number < minval | |
9303 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9304 | { |
9305 | if (more) | |
9306 | break; | |
2ae7e77b AH |
9307 | if (imm_expr.X_op == O_constant |
9308 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9309 | as_bad (_("expression out of range")); |
252b5132 RH |
9310 | } |
9311 | } | |
9312 | s = expr_end; | |
9313 | continue; | |
9314 | ||
9315 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9316 | /* Check whether there is only a single bracketed expression |
9317 | left. If so, it must be the base register and the | |
9318 | constant must be zero. */ | |
9319 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9320 | { | |
9321 | offset_expr.X_op = O_constant; | |
9322 | offset_expr.X_add_number = 0; | |
9323 | continue; | |
9324 | } | |
252b5132 RH |
9325 | |
9326 | /* If this value won't fit into a 16 bit offset, then go | |
9327 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9328 | code pattern. */ |
5e0116d5 | 9329 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9330 | && (offset_expr.X_op != O_constant |
9331 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9332 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9333 | break; |
9334 | ||
252b5132 RH |
9335 | s = expr_end; |
9336 | continue; | |
9337 | ||
9338 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9339 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9340 | my_getExpression (&offset_expr, s); |
9341 | s = expr_end; | |
9342 | continue; | |
9343 | ||
9344 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9345 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9346 | && imm_expr.X_op == O_constant | |
9347 | && (imm_expr.X_add_number < 0 | |
9348 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9349 | as_bad (_("lui expression not in range 0..65535")); |
9350 | s = expr_end; | |
9351 | continue; | |
9352 | ||
9353 | case 'a': /* 26 bit address */ | |
9354 | my_getExpression (&offset_expr, s); | |
9355 | s = expr_end; | |
f6688943 | 9356 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9357 | continue; |
9358 | ||
9359 | case 'N': /* 3 bit branch condition code */ | |
9360 | case 'M': /* 3 bit compare condition code */ | |
9361 | if (strncmp (s, "$fcc", 4) != 0) | |
9362 | break; | |
9363 | s += 4; | |
9364 | regno = 0; | |
9365 | do | |
9366 | { | |
9367 | regno *= 10; | |
9368 | regno += *s - '0'; | |
9369 | ++s; | |
9370 | } | |
3882b010 | 9371 | while (ISDIGIT (*s)); |
252b5132 | 9372 | if (regno > 7) |
30c378fd CD |
9373 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9374 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9375 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9376 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9377 | && (regno & 1) != 0) | |
9378 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9379 | str, regno); | |
9380 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9381 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9382 | && (regno & 3) != 0) | |
9383 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9384 | str, regno); | |
252b5132 RH |
9385 | if (*args == 'N') |
9386 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9387 | else | |
9388 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9389 | continue; |
252b5132 | 9390 | |
156c2f8b NC |
9391 | case 'H': |
9392 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9393 | s += 2; | |
3882b010 | 9394 | if (ISDIGIT (*s)) |
156c2f8b NC |
9395 | { |
9396 | c = 0; | |
9397 | do | |
9398 | { | |
9399 | c *= 10; | |
9400 | c += *s - '0'; | |
9401 | ++s; | |
9402 | } | |
3882b010 | 9403 | while (ISDIGIT (*s)); |
156c2f8b NC |
9404 | } |
9405 | else | |
9406 | c = 8; /* Invalid sel value. */ | |
9407 | ||
9408 | if (c > 7) | |
9409 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9410 | ip->insn_opcode |= c; | |
9411 | continue; | |
9412 | ||
60b63b72 RS |
9413 | case 'e': |
9414 | /* Must be at least one digit. */ | |
9415 | my_getExpression (&imm_expr, s); | |
9416 | check_absolute_expr (ip, &imm_expr); | |
9417 | ||
9418 | if ((unsigned long) imm_expr.X_add_number | |
9419 | > (unsigned long) OP_MASK_VECBYTE) | |
9420 | { | |
9421 | as_bad (_("bad byte vector index (%ld)"), | |
9422 | (long) imm_expr.X_add_number); | |
9423 | imm_expr.X_add_number = 0; | |
9424 | } | |
9425 | ||
9426 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9427 | imm_expr.X_op = O_absent; | |
9428 | s = expr_end; | |
9429 | continue; | |
9430 | ||
9431 | case '%': | |
9432 | my_getExpression (&imm_expr, s); | |
9433 | check_absolute_expr (ip, &imm_expr); | |
9434 | ||
9435 | if ((unsigned long) imm_expr.X_add_number | |
9436 | > (unsigned long) OP_MASK_VECALIGN) | |
9437 | { | |
9438 | as_bad (_("bad byte vector index (%ld)"), | |
9439 | (long) imm_expr.X_add_number); | |
9440 | imm_expr.X_add_number = 0; | |
9441 | } | |
9442 | ||
9443 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9444 | imm_expr.X_op = O_absent; | |
9445 | s = expr_end; | |
9446 | continue; | |
9447 | ||
252b5132 RH |
9448 | default: |
9449 | as_bad (_("bad char = '%c'\n"), *args); | |
9450 | internalError (); | |
9451 | } | |
9452 | break; | |
9453 | } | |
9454 | /* Args don't match. */ | |
9455 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9456 | !strcmp (insn->name, insn[1].name)) | |
9457 | { | |
9458 | ++insn; | |
9459 | s = argsStart; | |
268f6bed | 9460 | insn_error = _("illegal operands"); |
252b5132 RH |
9461 | continue; |
9462 | } | |
268f6bed L |
9463 | if (save_c) |
9464 | *(--s) = save_c; | |
252b5132 RH |
9465 | insn_error = _("illegal operands"); |
9466 | return; | |
9467 | } | |
9468 | } | |
9469 | ||
9470 | /* This routine assembles an instruction into its binary format when | |
9471 | assembling for the mips16. As a side effect, it sets one of the | |
9472 | global variables imm_reloc or offset_reloc to the type of | |
9473 | relocation to do if one of the operands is an address expression. | |
9474 | It also sets mips16_small and mips16_ext if the user explicitly | |
9475 | requested a small or extended instruction. */ | |
9476 | ||
9477 | static void | |
17a2f251 | 9478 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9479 | { |
9480 | char *s; | |
9481 | const char *args; | |
9482 | struct mips_opcode *insn; | |
9483 | char *argsstart; | |
9484 | unsigned int regno; | |
9485 | unsigned int lastregno = 0; | |
9486 | char *s_reset; | |
9487 | ||
9488 | insn_error = NULL; | |
9489 | ||
b34976b6 AM |
9490 | mips16_small = FALSE; |
9491 | mips16_ext = FALSE; | |
252b5132 | 9492 | |
3882b010 | 9493 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9494 | ; |
9495 | switch (*s) | |
9496 | { | |
9497 | case '\0': | |
9498 | break; | |
9499 | ||
9500 | case ' ': | |
9501 | *s++ = '\0'; | |
9502 | break; | |
9503 | ||
9504 | case '.': | |
9505 | if (s[1] == 't' && s[2] == ' ') | |
9506 | { | |
9507 | *s = '\0'; | |
b34976b6 | 9508 | mips16_small = TRUE; |
252b5132 RH |
9509 | s += 3; |
9510 | break; | |
9511 | } | |
9512 | else if (s[1] == 'e' && s[2] == ' ') | |
9513 | { | |
9514 | *s = '\0'; | |
b34976b6 | 9515 | mips16_ext = TRUE; |
252b5132 RH |
9516 | s += 3; |
9517 | break; | |
9518 | } | |
9519 | /* Fall through. */ | |
9520 | default: | |
9521 | insn_error = _("unknown opcode"); | |
9522 | return; | |
9523 | } | |
9524 | ||
9525 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9526 | mips16_small = TRUE; |
252b5132 RH |
9527 | |
9528 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9529 | { | |
9530 | insn_error = _("unrecognized opcode"); | |
9531 | return; | |
9532 | } | |
9533 | ||
9534 | argsstart = s; | |
9535 | for (;;) | |
9536 | { | |
9537 | assert (strcmp (insn->name, str) == 0); | |
9538 | ||
9539 | ip->insn_mo = insn; | |
9540 | ip->insn_opcode = insn->match; | |
b34976b6 | 9541 | ip->use_extend = FALSE; |
252b5132 | 9542 | imm_expr.X_op = O_absent; |
f6688943 TS |
9543 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9544 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9545 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9546 | imm2_expr.X_op = O_absent; |
252b5132 | 9547 | offset_expr.X_op = O_absent; |
f6688943 TS |
9548 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9549 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9550 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9551 | for (args = insn->args; 1; ++args) |
9552 | { | |
9553 | int c; | |
9554 | ||
9555 | if (*s == ' ') | |
9556 | ++s; | |
9557 | ||
9558 | /* In this switch statement we call break if we did not find | |
9559 | a match, continue if we did find a match, or return if we | |
9560 | are done. */ | |
9561 | ||
9562 | c = *args; | |
9563 | switch (c) | |
9564 | { | |
9565 | case '\0': | |
9566 | if (*s == '\0') | |
9567 | { | |
9568 | /* Stuff the immediate value in now, if we can. */ | |
9569 | if (imm_expr.X_op == O_constant | |
f6688943 | 9570 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9571 | && insn->pinfo != INSN_MACRO) |
9572 | { | |
c4e7957c | 9573 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9574 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9575 | mips16_ext, &ip->insn_opcode, |
9576 | &ip->use_extend, &ip->extend); | |
9577 | imm_expr.X_op = O_absent; | |
f6688943 | 9578 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9579 | } |
9580 | ||
9581 | return; | |
9582 | } | |
9583 | break; | |
9584 | ||
9585 | case ',': | |
9586 | if (*s++ == c) | |
9587 | continue; | |
9588 | s--; | |
9589 | switch (*++args) | |
9590 | { | |
9591 | case 'v': | |
9592 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9593 | continue; | |
9594 | case 'w': | |
9595 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9596 | continue; | |
9597 | } | |
9598 | break; | |
9599 | ||
9600 | case '(': | |
9601 | case ')': | |
9602 | if (*s++ == c) | |
9603 | continue; | |
9604 | break; | |
9605 | ||
9606 | case 'v': | |
9607 | case 'w': | |
9608 | if (s[0] != '$') | |
9609 | { | |
9610 | if (c == 'v') | |
9611 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9612 | else | |
9613 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9614 | ++args; | |
9615 | continue; | |
9616 | } | |
9617 | /* Fall through. */ | |
9618 | case 'x': | |
9619 | case 'y': | |
9620 | case 'z': | |
9621 | case 'Z': | |
9622 | case '0': | |
9623 | case 'S': | |
9624 | case 'R': | |
9625 | case 'X': | |
9626 | case 'Y': | |
9627 | if (s[0] != '$') | |
9628 | break; | |
9629 | s_reset = s; | |
3882b010 | 9630 | if (ISDIGIT (s[1])) |
252b5132 RH |
9631 | { |
9632 | ++s; | |
9633 | regno = 0; | |
9634 | do | |
9635 | { | |
9636 | regno *= 10; | |
9637 | regno += *s - '0'; | |
9638 | ++s; | |
9639 | } | |
3882b010 | 9640 | while (ISDIGIT (*s)); |
252b5132 RH |
9641 | if (regno > 31) |
9642 | { | |
9643 | as_bad (_("invalid register number (%d)"), regno); | |
9644 | regno = 2; | |
9645 | } | |
9646 | } | |
9647 | else | |
9648 | { | |
76db943d TS |
9649 | if (s[1] == 'r' && s[2] == 'a') |
9650 | { | |
9651 | s += 3; | |
9652 | regno = RA; | |
9653 | } | |
9654 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9655 | { |
9656 | s += 3; | |
9657 | regno = FP; | |
9658 | } | |
9659 | else if (s[1] == 's' && s[2] == 'p') | |
9660 | { | |
9661 | s += 3; | |
9662 | regno = SP; | |
9663 | } | |
9664 | else if (s[1] == 'g' && s[2] == 'p') | |
9665 | { | |
9666 | s += 3; | |
9667 | regno = GP; | |
9668 | } | |
9669 | else if (s[1] == 'a' && s[2] == 't') | |
9670 | { | |
9671 | s += 3; | |
9672 | regno = AT; | |
9673 | } | |
9674 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9675 | { | |
9676 | s += 4; | |
9677 | regno = KT0; | |
9678 | } | |
9679 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9680 | { | |
9681 | s += 4; | |
9682 | regno = KT1; | |
9683 | } | |
85b51719 TS |
9684 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9685 | { | |
9686 | s += 5; | |
9687 | regno = ZERO; | |
9688 | } | |
252b5132 RH |
9689 | else |
9690 | break; | |
9691 | } | |
9692 | ||
9693 | if (*s == ' ') | |
9694 | ++s; | |
9695 | if (args[1] != *s) | |
9696 | { | |
9697 | if (c == 'v' || c == 'w') | |
9698 | { | |
9699 | regno = mips16_to_32_reg_map[lastregno]; | |
9700 | s = s_reset; | |
f9419b05 | 9701 | ++args; |
252b5132 RH |
9702 | } |
9703 | } | |
9704 | ||
9705 | switch (c) | |
9706 | { | |
9707 | case 'x': | |
9708 | case 'y': | |
9709 | case 'z': | |
9710 | case 'v': | |
9711 | case 'w': | |
9712 | case 'Z': | |
9713 | regno = mips32_to_16_reg_map[regno]; | |
9714 | break; | |
9715 | ||
9716 | case '0': | |
9717 | if (regno != 0) | |
9718 | regno = ILLEGAL_REG; | |
9719 | break; | |
9720 | ||
9721 | case 'S': | |
9722 | if (regno != SP) | |
9723 | regno = ILLEGAL_REG; | |
9724 | break; | |
9725 | ||
9726 | case 'R': | |
9727 | if (regno != RA) | |
9728 | regno = ILLEGAL_REG; | |
9729 | break; | |
9730 | ||
9731 | case 'X': | |
9732 | case 'Y': | |
9733 | if (regno == AT && ! mips_opts.noat) | |
9734 | as_warn (_("used $at without \".set noat\"")); | |
9735 | break; | |
9736 | ||
9737 | default: | |
9738 | internalError (); | |
9739 | } | |
9740 | ||
9741 | if (regno == ILLEGAL_REG) | |
9742 | break; | |
9743 | ||
9744 | switch (c) | |
9745 | { | |
9746 | case 'x': | |
9747 | case 'v': | |
9748 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9749 | break; | |
9750 | case 'y': | |
9751 | case 'w': | |
9752 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9753 | break; | |
9754 | case 'z': | |
9755 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9756 | break; | |
9757 | case 'Z': | |
9758 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9759 | case '0': | |
9760 | case 'S': | |
9761 | case 'R': | |
9762 | break; | |
9763 | case 'X': | |
9764 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9765 | break; | |
9766 | case 'Y': | |
9767 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9768 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9769 | break; | |
9770 | default: | |
9771 | internalError (); | |
9772 | } | |
9773 | ||
9774 | lastregno = regno; | |
9775 | continue; | |
9776 | ||
9777 | case 'P': | |
9778 | if (strncmp (s, "$pc", 3) == 0) | |
9779 | { | |
9780 | s += 3; | |
9781 | continue; | |
9782 | } | |
9783 | break; | |
9784 | ||
9785 | case '<': | |
9786 | case '>': | |
9787 | case '[': | |
9788 | case ']': | |
9789 | case '4': | |
9790 | case '5': | |
9791 | case 'H': | |
9792 | case 'W': | |
9793 | case 'D': | |
9794 | case 'j': | |
9795 | case '8': | |
9796 | case 'V': | |
9797 | case 'C': | |
9798 | case 'U': | |
9799 | case 'k': | |
9800 | case 'K': | |
9801 | if (s[0] == '%' | |
9802 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9803 | { | |
9804 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9805 | and generate the appropriate reloc. If the text | |
9806 | inside %gprel is not a symbol name with an | |
9807 | optional offset, then we generate a normal reloc | |
9808 | and will probably fail later. */ | |
9809 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9810 | if (imm_expr.X_op == O_symbol) | |
9811 | { | |
b34976b6 | 9812 | mips16_ext = TRUE; |
f6688943 | 9813 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9814 | s = expr_end; |
b34976b6 | 9815 | ip->use_extend = TRUE; |
252b5132 RH |
9816 | ip->extend = 0; |
9817 | continue; | |
9818 | } | |
9819 | } | |
9820 | else | |
9821 | { | |
9822 | /* Just pick up a normal expression. */ | |
9823 | my_getExpression (&imm_expr, s); | |
9824 | } | |
9825 | ||
9826 | if (imm_expr.X_op == O_register) | |
9827 | { | |
9828 | /* What we thought was an expression turned out to | |
9829 | be a register. */ | |
9830 | ||
9831 | if (s[0] == '(' && args[1] == '(') | |
9832 | { | |
9833 | /* It looks like the expression was omitted | |
9834 | before a register indirection, which means | |
9835 | that the expression is implicitly zero. We | |
9836 | still set up imm_expr, so that we handle | |
9837 | explicit extensions correctly. */ | |
9838 | imm_expr.X_op = O_constant; | |
9839 | imm_expr.X_add_number = 0; | |
f6688943 | 9840 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9841 | continue; |
9842 | } | |
9843 | ||
9844 | break; | |
9845 | } | |
9846 | ||
9847 | /* We need to relax this instruction. */ | |
f6688943 | 9848 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9849 | s = expr_end; |
9850 | continue; | |
9851 | ||
9852 | case 'p': | |
9853 | case 'q': | |
9854 | case 'A': | |
9855 | case 'B': | |
9856 | case 'E': | |
9857 | /* We use offset_reloc rather than imm_reloc for the PC | |
9858 | relative operands. This lets macros with both | |
9859 | immediate and address operands work correctly. */ | |
9860 | my_getExpression (&offset_expr, s); | |
9861 | ||
9862 | if (offset_expr.X_op == O_register) | |
9863 | break; | |
9864 | ||
9865 | /* We need to relax this instruction. */ | |
f6688943 | 9866 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9867 | s = expr_end; |
9868 | continue; | |
9869 | ||
9870 | case '6': /* break code */ | |
9871 | my_getExpression (&imm_expr, s); | |
9872 | check_absolute_expr (ip, &imm_expr); | |
9873 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9874 | { | |
9875 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9876 | ip->insn_mo->name, | |
9877 | (unsigned long) imm_expr.X_add_number); | |
9878 | imm_expr.X_add_number &= 0x3f; | |
9879 | } | |
9880 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9881 | imm_expr.X_op = O_absent; | |
9882 | s = expr_end; | |
9883 | continue; | |
9884 | ||
9885 | case 'a': /* 26 bit address */ | |
9886 | my_getExpression (&offset_expr, s); | |
9887 | s = expr_end; | |
f6688943 | 9888 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9889 | ip->insn_opcode <<= 16; |
9890 | continue; | |
9891 | ||
9892 | case 'l': /* register list for entry macro */ | |
9893 | case 'L': /* register list for exit macro */ | |
9894 | { | |
9895 | int mask; | |
9896 | ||
9897 | if (c == 'l') | |
9898 | mask = 0; | |
9899 | else | |
9900 | mask = 7 << 3; | |
9901 | while (*s != '\0') | |
9902 | { | |
9903 | int freg, reg1, reg2; | |
9904 | ||
9905 | while (*s == ' ' || *s == ',') | |
9906 | ++s; | |
9907 | if (*s != '$') | |
9908 | { | |
9909 | as_bad (_("can't parse register list")); | |
9910 | break; | |
9911 | } | |
9912 | ++s; | |
9913 | if (*s != 'f') | |
9914 | freg = 0; | |
9915 | else | |
9916 | { | |
9917 | freg = 1; | |
9918 | ++s; | |
9919 | } | |
9920 | reg1 = 0; | |
3882b010 | 9921 | while (ISDIGIT (*s)) |
252b5132 RH |
9922 | { |
9923 | reg1 *= 10; | |
9924 | reg1 += *s - '0'; | |
9925 | ++s; | |
9926 | } | |
9927 | if (*s == ' ') | |
9928 | ++s; | |
9929 | if (*s != '-') | |
9930 | reg2 = reg1; | |
9931 | else | |
9932 | { | |
9933 | ++s; | |
9934 | if (*s != '$') | |
9935 | break; | |
9936 | ++s; | |
9937 | if (freg) | |
9938 | { | |
9939 | if (*s == 'f') | |
9940 | ++s; | |
9941 | else | |
9942 | { | |
9943 | as_bad (_("invalid register list")); | |
9944 | break; | |
9945 | } | |
9946 | } | |
9947 | reg2 = 0; | |
3882b010 | 9948 | while (ISDIGIT (*s)) |
252b5132 RH |
9949 | { |
9950 | reg2 *= 10; | |
9951 | reg2 += *s - '0'; | |
9952 | ++s; | |
9953 | } | |
9954 | } | |
9955 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9956 | { | |
9957 | mask &= ~ (7 << 3); | |
9958 | mask |= 5 << 3; | |
9959 | } | |
9960 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9961 | { | |
9962 | mask &= ~ (7 << 3); | |
9963 | mask |= 6 << 3; | |
9964 | } | |
9965 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9966 | mask |= (reg2 - 3) << 3; | |
9967 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9968 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9969 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9970 | mask |= 1; |
9971 | else | |
9972 | { | |
9973 | as_bad (_("invalid register list")); | |
9974 | break; | |
9975 | } | |
9976 | } | |
9977 | /* The mask is filled in in the opcode table for the | |
9978 | benefit of the disassembler. We remove it before | |
9979 | applying the actual mask. */ | |
9980 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9981 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9982 | } | |
9983 | continue; | |
9984 | ||
9985 | case 'e': /* extend code */ | |
9986 | my_getExpression (&imm_expr, s); | |
9987 | check_absolute_expr (ip, &imm_expr); | |
9988 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9989 | { | |
9990 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9991 | ip->insn_mo->name, | |
9992 | (unsigned long) imm_expr.X_add_number); | |
9993 | imm_expr.X_add_number &= 0x7ff; | |
9994 | } | |
9995 | ip->insn_opcode |= imm_expr.X_add_number; | |
9996 | imm_expr.X_op = O_absent; | |
9997 | s = expr_end; | |
9998 | continue; | |
9999 | ||
10000 | default: | |
10001 | internalError (); | |
10002 | } | |
10003 | break; | |
10004 | } | |
10005 | ||
10006 | /* Args don't match. */ | |
10007 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10008 | strcmp (insn->name, insn[1].name) == 0) | |
10009 | { | |
10010 | ++insn; | |
10011 | s = argsstart; | |
10012 | continue; | |
10013 | } | |
10014 | ||
10015 | insn_error = _("illegal operands"); | |
10016 | ||
10017 | return; | |
10018 | } | |
10019 | } | |
10020 | ||
10021 | /* This structure holds information we know about a mips16 immediate | |
10022 | argument type. */ | |
10023 | ||
e972090a NC |
10024 | struct mips16_immed_operand |
10025 | { | |
252b5132 RH |
10026 | /* The type code used in the argument string in the opcode table. */ |
10027 | int type; | |
10028 | /* The number of bits in the short form of the opcode. */ | |
10029 | int nbits; | |
10030 | /* The number of bits in the extended form of the opcode. */ | |
10031 | int extbits; | |
10032 | /* The amount by which the short form is shifted when it is used; | |
10033 | for example, the sw instruction has a shift count of 2. */ | |
10034 | int shift; | |
10035 | /* The amount by which the short form is shifted when it is stored | |
10036 | into the instruction code. */ | |
10037 | int op_shift; | |
10038 | /* Non-zero if the short form is unsigned. */ | |
10039 | int unsp; | |
10040 | /* Non-zero if the extended form is unsigned. */ | |
10041 | int extu; | |
10042 | /* Non-zero if the value is PC relative. */ | |
10043 | int pcrel; | |
10044 | }; | |
10045 | ||
10046 | /* The mips16 immediate operand types. */ | |
10047 | ||
10048 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10049 | { | |
10050 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10051 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10052 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10053 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10054 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10055 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10056 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10057 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10058 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10059 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10060 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10061 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10062 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10063 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10064 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10065 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10066 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10067 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10068 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10069 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10070 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10071 | }; | |
10072 | ||
10073 | #define MIPS16_NUM_IMMED \ | |
10074 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10075 | ||
10076 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10077 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10078 | whether an extended value is needed; if one is needed, it sets | |
10079 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10080 | If SMALL is true, an unextended opcode was explicitly requested. | |
10081 | If EXT is true, an extended opcode was explicitly requested. If | |
10082 | WARN is true, warn if EXT does not match reality. */ | |
10083 | ||
10084 | static void | |
17a2f251 TS |
10085 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10086 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10087 | unsigned long *insn, bfd_boolean *use_extend, | |
10088 | unsigned short *extend) | |
252b5132 RH |
10089 | { |
10090 | register const struct mips16_immed_operand *op; | |
10091 | int mintiny, maxtiny; | |
b34976b6 | 10092 | bfd_boolean needext; |
252b5132 RH |
10093 | |
10094 | op = mips16_immed_operands; | |
10095 | while (op->type != type) | |
10096 | { | |
10097 | ++op; | |
10098 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10099 | } | |
10100 | ||
10101 | if (op->unsp) | |
10102 | { | |
10103 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10104 | { | |
10105 | mintiny = 1; | |
10106 | maxtiny = 1 << op->nbits; | |
10107 | } | |
10108 | else | |
10109 | { | |
10110 | mintiny = 0; | |
10111 | maxtiny = (1 << op->nbits) - 1; | |
10112 | } | |
10113 | } | |
10114 | else | |
10115 | { | |
10116 | mintiny = - (1 << (op->nbits - 1)); | |
10117 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10118 | } | |
10119 | ||
10120 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10121 | if (type == 'p' || type == 'q') | |
10122 | val /= 2; | |
10123 | ||
10124 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10125 | || val < (mintiny << op->shift) | |
10126 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10127 | needext = TRUE; |
252b5132 | 10128 | else |
b34976b6 | 10129 | needext = FALSE; |
252b5132 RH |
10130 | |
10131 | if (warn && ext && ! needext) | |
beae10d5 KH |
10132 | as_warn_where (file, line, |
10133 | _("extended operand requested but not required")); | |
252b5132 RH |
10134 | if (small && needext) |
10135 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10136 | ||
10137 | if (small || (! ext && ! needext)) | |
10138 | { | |
10139 | int insnval; | |
10140 | ||
b34976b6 | 10141 | *use_extend = FALSE; |
252b5132 RH |
10142 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10143 | insnval <<= op->op_shift; | |
10144 | *insn |= insnval; | |
10145 | } | |
10146 | else | |
10147 | { | |
10148 | long minext, maxext; | |
10149 | int extval; | |
10150 | ||
10151 | if (op->extu) | |
10152 | { | |
10153 | minext = 0; | |
10154 | maxext = (1 << op->extbits) - 1; | |
10155 | } | |
10156 | else | |
10157 | { | |
10158 | minext = - (1 << (op->extbits - 1)); | |
10159 | maxext = (1 << (op->extbits - 1)) - 1; | |
10160 | } | |
10161 | if (val < minext || val > maxext) | |
10162 | as_bad_where (file, line, | |
10163 | _("operand value out of range for instruction")); | |
10164 | ||
b34976b6 | 10165 | *use_extend = TRUE; |
252b5132 RH |
10166 | if (op->extbits == 16) |
10167 | { | |
10168 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10169 | val &= 0x1f; | |
10170 | } | |
10171 | else if (op->extbits == 15) | |
10172 | { | |
10173 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10174 | val &= 0xf; | |
10175 | } | |
10176 | else | |
10177 | { | |
10178 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10179 | val = 0; | |
10180 | } | |
10181 | ||
10182 | *extend = (unsigned short) extval; | |
10183 | *insn |= val; | |
10184 | } | |
10185 | } | |
10186 | \f | |
5e0116d5 | 10187 | static const struct percent_op_match |
ad8d3bb3 | 10188 | { |
5e0116d5 RS |
10189 | const char *str; |
10190 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
10191 | } percent_op[] = |
10192 | { | |
5e0116d5 | 10193 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10194 | #ifdef OBJ_ELF |
5e0116d5 RS |
10195 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10196 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10197 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10198 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10199 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10200 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10201 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10202 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10203 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10204 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10205 | {"%half", BFD_RELOC_16}, | |
10206 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10207 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10208 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 10209 | #endif |
5e0116d5 | 10210 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10211 | }; |
10212 | ||
252b5132 | 10213 | |
5e0116d5 RS |
10214 | /* Return true if *STR points to a relocation operator. When returning true, |
10215 | move *STR over the operator and store its relocation code in *RELOC. | |
10216 | Leave both *STR and *RELOC alone when returning false. */ | |
10217 | ||
10218 | static bfd_boolean | |
17a2f251 | 10219 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10220 | { |
5e0116d5 | 10221 | size_t i; |
76b3015f | 10222 | |
5e0116d5 RS |
10223 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10224 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10225 | { |
5e0116d5 RS |
10226 | *str += strlen (percent_op[i].str); |
10227 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10228 | |
5e0116d5 RS |
10229 | /* Check whether the output BFD supports this relocation. |
10230 | If not, issue an error and fall back on something safe. */ | |
10231 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10232 | { |
5e0116d5 RS |
10233 | as_bad ("relocation %s isn't supported by the current ABI", |
10234 | percent_op[i].str); | |
10235 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10236 | } |
5e0116d5 | 10237 | return TRUE; |
394f9b3a | 10238 | } |
5e0116d5 | 10239 | return FALSE; |
394f9b3a | 10240 | } |
ad8d3bb3 | 10241 | |
ad8d3bb3 | 10242 | |
5e0116d5 RS |
10243 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10244 | expression in *EP and the relocations in the array starting | |
10245 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10246 | |
5e0116d5 RS |
10247 | On exit, EXPR_END points to the first character after the expression. |
10248 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10249 | |
5e0116d5 | 10250 | static size_t |
17a2f251 TS |
10251 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10252 | char *str) | |
ad8d3bb3 | 10253 | { |
5e0116d5 RS |
10254 | bfd_reloc_code_real_type reversed_reloc[3]; |
10255 | size_t reloc_index, i; | |
09b8f35a RS |
10256 | int crux_depth, str_depth; |
10257 | char *crux; | |
5e0116d5 RS |
10258 | |
10259 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10260 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10261 | of the main expression and with CRUX_DEPTH containing the number | |
10262 | of open brackets at that point. */ | |
10263 | reloc_index = -1; | |
10264 | str_depth = 0; | |
10265 | do | |
fb1b3232 | 10266 | { |
09b8f35a RS |
10267 | reloc_index++; |
10268 | crux = str; | |
10269 | crux_depth = str_depth; | |
10270 | ||
10271 | /* Skip over whitespace and brackets, keeping count of the number | |
10272 | of brackets. */ | |
10273 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10274 | if (*str++ == '(') | |
10275 | str_depth++; | |
5e0116d5 | 10276 | } |
09b8f35a RS |
10277 | while (*str == '%' |
10278 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10279 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10280 | |
09b8f35a | 10281 | my_getExpression (ep, crux); |
5e0116d5 | 10282 | str = expr_end; |
394f9b3a | 10283 | |
5e0116d5 | 10284 | /* Match every open bracket. */ |
09b8f35a | 10285 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10286 | if (*str++ == ')') |
09b8f35a | 10287 | crux_depth--; |
394f9b3a | 10288 | |
09b8f35a | 10289 | if (crux_depth > 0) |
5e0116d5 | 10290 | as_bad ("unclosed '('"); |
394f9b3a | 10291 | |
5e0116d5 | 10292 | expr_end = str; |
252b5132 | 10293 | |
64bdfcaf RS |
10294 | if (reloc_index == 0) |
10295 | reloc[0] = BFD_RELOC_LO16; | |
10296 | else | |
10297 | { | |
10298 | prev_reloc_op_frag = frag_now; | |
10299 | for (i = 0; i < reloc_index; i++) | |
10300 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10301 | } | |
fb1b3232 | 10302 | |
5e0116d5 | 10303 | return reloc_index; |
252b5132 RH |
10304 | } |
10305 | ||
10306 | static void | |
17a2f251 | 10307 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10308 | { |
10309 | char *save_in; | |
98aa84af | 10310 | valueT val; |
252b5132 RH |
10311 | |
10312 | save_in = input_line_pointer; | |
10313 | input_line_pointer = str; | |
10314 | expression (ep); | |
10315 | expr_end = input_line_pointer; | |
10316 | input_line_pointer = save_in; | |
10317 | ||
10318 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10319 | then we bump the value of the symbol by 1 since that is how other | |
10320 | text symbols are handled. We don't bother to handle complex | |
10321 | expressions, just `.' plus or minus a constant. */ | |
10322 | if (mips_opts.mips16 | |
10323 | && ep->X_op == O_symbol | |
10324 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10325 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10326 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10327 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10328 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10329 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10330 | } |
10331 | ||
10332 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10333 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10334 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10335 | returned, or NULL on OK. */ |
10336 | ||
10337 | char * | |
17a2f251 | 10338 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10339 | { |
10340 | int prec; | |
10341 | LITTLENUM_TYPE words[4]; | |
10342 | char *t; | |
10343 | int i; | |
10344 | ||
10345 | switch (type) | |
10346 | { | |
10347 | case 'f': | |
10348 | prec = 2; | |
10349 | break; | |
10350 | ||
10351 | case 'd': | |
10352 | prec = 4; | |
10353 | break; | |
10354 | ||
10355 | default: | |
10356 | *sizeP = 0; | |
10357 | return _("bad call to md_atof"); | |
10358 | } | |
10359 | ||
10360 | t = atof_ieee (input_line_pointer, type, words); | |
10361 | if (t) | |
10362 | input_line_pointer = t; | |
10363 | ||
10364 | *sizeP = prec * 2; | |
10365 | ||
10366 | if (! target_big_endian) | |
10367 | { | |
10368 | for (i = prec - 1; i >= 0; i--) | |
10369 | { | |
17a2f251 | 10370 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10371 | litP += 2; |
10372 | } | |
10373 | } | |
10374 | else | |
10375 | { | |
10376 | for (i = 0; i < prec; i++) | |
10377 | { | |
17a2f251 | 10378 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10379 | litP += 2; |
10380 | } | |
10381 | } | |
bdaaa2e1 | 10382 | |
252b5132 RH |
10383 | return NULL; |
10384 | } | |
10385 | ||
10386 | void | |
17a2f251 | 10387 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10388 | { |
10389 | if (target_big_endian) | |
10390 | number_to_chars_bigendian (buf, val, n); | |
10391 | else | |
10392 | number_to_chars_littleendian (buf, val, n); | |
10393 | } | |
10394 | \f | |
ae948b86 | 10395 | #ifdef OBJ_ELF |
e013f690 TS |
10396 | static int support_64bit_objects(void) |
10397 | { | |
10398 | const char **list, **l; | |
aa3d8fdf | 10399 | int yes; |
e013f690 TS |
10400 | |
10401 | list = bfd_target_list (); | |
10402 | for (l = list; *l != NULL; l++) | |
10403 | #ifdef TE_TMIPS | |
10404 | /* This is traditional mips */ | |
10405 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10406 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10407 | #else | |
10408 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10409 | || strcmp (*l, "elf64-littlemips") == 0) | |
10410 | #endif | |
10411 | break; | |
aa3d8fdf | 10412 | yes = (*l != NULL); |
e013f690 | 10413 | free (list); |
aa3d8fdf | 10414 | return yes; |
e013f690 | 10415 | } |
ae948b86 | 10416 | #endif /* OBJ_ELF */ |
e013f690 | 10417 | |
78849248 | 10418 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10419 | |
e972090a NC |
10420 | struct option md_longopts[] = |
10421 | { | |
f9b4148d CD |
10422 | /* Options which specify architecture. */ |
10423 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10424 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10425 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10426 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10427 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10428 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10429 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10430 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10431 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10432 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10433 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10434 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10435 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10436 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10437 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10438 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10439 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10440 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10441 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10442 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10443 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10444 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10445 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10446 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10447 | |
10448 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10449 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10450 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10451 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10452 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10453 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10454 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10455 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10456 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10457 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10458 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10459 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10460 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10461 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10462 | ||
10463 | /* Old-style architecture options. Don't add more of these. */ | |
10464 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10465 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10466 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10467 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10468 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10469 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10470 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10471 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10472 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10473 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10474 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10475 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10476 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10477 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10478 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10479 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10480 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10481 | ||
10482 | /* Options which enable bug fixes. */ | |
10483 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10484 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10485 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10486 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10487 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10488 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10489 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10490 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10491 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10492 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10493 | ||
10494 | /* Miscellaneous options. */ | |
10495 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10496 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10497 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10498 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10499 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10500 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10501 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10502 | {"break", no_argument, NULL, OPTION_BREAK}, |
10503 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10504 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10505 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10506 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10507 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10508 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10509 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10510 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10511 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10512 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10513 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10514 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10515 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10516 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10517 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10518 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10519 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10520 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10521 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10522 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10523 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10524 | |
10525 | /* ELF-specific options. */ | |
156c2f8b | 10526 | #ifdef OBJ_ELF |
f9b4148d | 10527 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10528 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10529 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10530 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10531 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10532 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10533 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10534 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10535 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10536 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10537 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10538 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10539 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10540 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10541 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10542 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10543 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10544 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10545 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10546 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10547 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10548 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10549 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10550 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10551 | #endif /* OBJ_ELF */ |
f9b4148d | 10552 | |
252b5132 RH |
10553 | {NULL, no_argument, NULL, 0} |
10554 | }; | |
156c2f8b | 10555 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10556 | |
316f5878 RS |
10557 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10558 | NEW_VALUE. Warn if another value was already specified. Note: | |
10559 | we have to defer parsing the -march and -mtune arguments in order | |
10560 | to handle 'from-abi' correctly, since the ABI might be specified | |
10561 | in a later argument. */ | |
10562 | ||
10563 | static void | |
17a2f251 | 10564 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10565 | { |
10566 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10567 | as_warn (_("A different %s was already specified, is now %s"), | |
10568 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10569 | new_value); | |
10570 | ||
10571 | *string_ptr = new_value; | |
10572 | } | |
10573 | ||
252b5132 | 10574 | int |
17a2f251 | 10575 | md_parse_option (int c, char *arg) |
252b5132 RH |
10576 | { |
10577 | switch (c) | |
10578 | { | |
119d663a NC |
10579 | case OPTION_CONSTRUCT_FLOATS: |
10580 | mips_disable_float_construction = 0; | |
10581 | break; | |
bdaaa2e1 | 10582 | |
119d663a NC |
10583 | case OPTION_NO_CONSTRUCT_FLOATS: |
10584 | mips_disable_float_construction = 1; | |
10585 | break; | |
bdaaa2e1 | 10586 | |
252b5132 RH |
10587 | case OPTION_TRAP: |
10588 | mips_trap = 1; | |
10589 | break; | |
10590 | ||
10591 | case OPTION_BREAK: | |
10592 | mips_trap = 0; | |
10593 | break; | |
10594 | ||
10595 | case OPTION_EB: | |
10596 | target_big_endian = 1; | |
10597 | break; | |
10598 | ||
10599 | case OPTION_EL: | |
10600 | target_big_endian = 0; | |
10601 | break; | |
10602 | ||
10603 | case 'O': | |
10604 | if (arg && arg[1] == '0') | |
10605 | mips_optimize = 1; | |
10606 | else | |
10607 | mips_optimize = 2; | |
10608 | break; | |
10609 | ||
10610 | case 'g': | |
10611 | if (arg == NULL) | |
10612 | mips_debug = 2; | |
10613 | else | |
10614 | mips_debug = atoi (arg); | |
10615 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10616 | optimizations which limit full symbolic debugging. We take | |
10617 | that to be equivalent to -O0. */ | |
10618 | if (mips_debug == 2) | |
10619 | mips_optimize = 1; | |
10620 | break; | |
10621 | ||
10622 | case OPTION_MIPS1: | |
316f5878 | 10623 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10624 | break; |
10625 | ||
10626 | case OPTION_MIPS2: | |
316f5878 | 10627 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10628 | break; |
10629 | ||
10630 | case OPTION_MIPS3: | |
316f5878 | 10631 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10632 | break; |
10633 | ||
10634 | case OPTION_MIPS4: | |
316f5878 | 10635 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10636 | break; |
10637 | ||
84ea6cf2 | 10638 | case OPTION_MIPS5: |
316f5878 | 10639 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10640 | break; |
10641 | ||
e7af610e | 10642 | case OPTION_MIPS32: |
316f5878 | 10643 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10644 | break; |
10645 | ||
af7ee8bf CD |
10646 | case OPTION_MIPS32R2: |
10647 | file_mips_isa = ISA_MIPS32R2; | |
10648 | break; | |
10649 | ||
5f74bc13 CD |
10650 | case OPTION_MIPS64R2: |
10651 | file_mips_isa = ISA_MIPS64R2; | |
10652 | break; | |
10653 | ||
84ea6cf2 | 10654 | case OPTION_MIPS64: |
316f5878 | 10655 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10656 | break; |
10657 | ||
ec68c924 | 10658 | case OPTION_MTUNE: |
316f5878 RS |
10659 | mips_set_option_string (&mips_tune_string, arg); |
10660 | break; | |
ec68c924 | 10661 | |
316f5878 RS |
10662 | case OPTION_MARCH: |
10663 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10664 | break; |
10665 | ||
10666 | case OPTION_M4650: | |
316f5878 RS |
10667 | mips_set_option_string (&mips_arch_string, "4650"); |
10668 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10669 | break; |
10670 | ||
10671 | case OPTION_NO_M4650: | |
10672 | break; | |
10673 | ||
10674 | case OPTION_M4010: | |
316f5878 RS |
10675 | mips_set_option_string (&mips_arch_string, "4010"); |
10676 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10677 | break; |
10678 | ||
10679 | case OPTION_NO_M4010: | |
10680 | break; | |
10681 | ||
10682 | case OPTION_M4100: | |
316f5878 RS |
10683 | mips_set_option_string (&mips_arch_string, "4100"); |
10684 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10685 | break; |
10686 | ||
10687 | case OPTION_NO_M4100: | |
10688 | break; | |
10689 | ||
252b5132 | 10690 | case OPTION_M3900: |
316f5878 RS |
10691 | mips_set_option_string (&mips_arch_string, "3900"); |
10692 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10693 | break; |
bdaaa2e1 | 10694 | |
252b5132 RH |
10695 | case OPTION_NO_M3900: |
10696 | break; | |
10697 | ||
deec1734 CD |
10698 | case OPTION_MDMX: |
10699 | mips_opts.ase_mdmx = 1; | |
10700 | break; | |
10701 | ||
10702 | case OPTION_NO_MDMX: | |
10703 | mips_opts.ase_mdmx = 0; | |
10704 | break; | |
10705 | ||
252b5132 RH |
10706 | case OPTION_MIPS16: |
10707 | mips_opts.mips16 = 1; | |
b34976b6 | 10708 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10709 | break; |
10710 | ||
10711 | case OPTION_NO_MIPS16: | |
10712 | mips_opts.mips16 = 0; | |
b34976b6 | 10713 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10714 | break; |
10715 | ||
1f25f5d3 CD |
10716 | case OPTION_MIPS3D: |
10717 | mips_opts.ase_mips3d = 1; | |
10718 | break; | |
10719 | ||
10720 | case OPTION_NO_MIPS3D: | |
10721 | mips_opts.ase_mips3d = 0; | |
10722 | break; | |
10723 | ||
252b5132 RH |
10724 | case OPTION_MEMBEDDED_PIC: |
10725 | mips_pic = EMBEDDED_PIC; | |
10726 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10727 | { | |
10728 | as_bad (_("-G may not be used with embedded PIC code")); | |
10729 | return 0; | |
10730 | } | |
10731 | g_switch_value = 0x7fffffff; | |
10732 | break; | |
10733 | ||
60b63b72 RS |
10734 | case OPTION_FIX_VR4122: |
10735 | mips_fix_4122_bugs = 1; | |
10736 | break; | |
10737 | ||
10738 | case OPTION_NO_FIX_VR4122: | |
10739 | mips_fix_4122_bugs = 0; | |
10740 | break; | |
10741 | ||
4a6a3df4 AO |
10742 | case OPTION_RELAX_BRANCH: |
10743 | mips_relax_branch = 1; | |
10744 | break; | |
10745 | ||
10746 | case OPTION_NO_RELAX_BRANCH: | |
10747 | mips_relax_branch = 0; | |
10748 | break; | |
10749 | ||
0f074f60 | 10750 | #ifdef OBJ_ELF |
252b5132 RH |
10751 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10752 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10753 | intended to be compatible with Irix 5. */ | |
10754 | case OPTION_CALL_SHARED: | |
10755 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10756 | { | |
10757 | as_bad (_("-call_shared is supported only for ELF format")); | |
10758 | return 0; | |
10759 | } | |
10760 | mips_pic = SVR4_PIC; | |
143d77c5 | 10761 | mips_abicalls = TRUE; |
252b5132 RH |
10762 | if (g_switch_seen && g_switch_value != 0) |
10763 | { | |
10764 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10765 | return 0; | |
10766 | } | |
10767 | g_switch_value = 0; | |
10768 | break; | |
10769 | ||
10770 | case OPTION_NON_SHARED: | |
10771 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10772 | { | |
10773 | as_bad (_("-non_shared is supported only for ELF format")); | |
10774 | return 0; | |
10775 | } | |
10776 | mips_pic = NO_PIC; | |
143d77c5 | 10777 | mips_abicalls = FALSE; |
252b5132 RH |
10778 | break; |
10779 | ||
10780 | /* The -xgot option tells the assembler to use 32 offsets when | |
10781 | accessing the got in SVR4_PIC mode. It is for Irix | |
10782 | compatibility. */ | |
10783 | case OPTION_XGOT: | |
10784 | mips_big_got = 1; | |
10785 | break; | |
0f074f60 | 10786 | #endif /* OBJ_ELF */ |
252b5132 RH |
10787 | |
10788 | case 'G': | |
10789 | if (! USE_GLOBAL_POINTER_OPT) | |
10790 | { | |
10791 | as_bad (_("-G is not supported for this configuration")); | |
10792 | return 0; | |
10793 | } | |
10794 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10795 | { | |
10796 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10797 | return 0; | |
10798 | } | |
10799 | else | |
10800 | g_switch_value = atoi (arg); | |
10801 | g_switch_seen = 1; | |
10802 | break; | |
10803 | ||
0f074f60 | 10804 | #ifdef OBJ_ELF |
34ba82a8 TS |
10805 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10806 | and -mabi=64. */ | |
252b5132 | 10807 | case OPTION_32: |
34ba82a8 TS |
10808 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10809 | { | |
10810 | as_bad (_("-32 is supported for ELF format only")); | |
10811 | return 0; | |
10812 | } | |
316f5878 | 10813 | mips_abi = O32_ABI; |
252b5132 RH |
10814 | break; |
10815 | ||
e013f690 | 10816 | case OPTION_N32: |
34ba82a8 TS |
10817 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10818 | { | |
10819 | as_bad (_("-n32 is supported for ELF format only")); | |
10820 | return 0; | |
10821 | } | |
316f5878 | 10822 | mips_abi = N32_ABI; |
e013f690 | 10823 | break; |
252b5132 | 10824 | |
e013f690 | 10825 | case OPTION_64: |
34ba82a8 TS |
10826 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10827 | { | |
10828 | as_bad (_("-64 is supported for ELF format only")); | |
10829 | return 0; | |
10830 | } | |
316f5878 | 10831 | mips_abi = N64_ABI; |
e013f690 TS |
10832 | if (! support_64bit_objects()) |
10833 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10834 | break; |
ae948b86 | 10835 | #endif /* OBJ_ELF */ |
252b5132 | 10836 | |
c97ef257 | 10837 | case OPTION_GP32: |
a325df1d | 10838 | file_mips_gp32 = 1; |
c97ef257 AH |
10839 | break; |
10840 | ||
10841 | case OPTION_GP64: | |
a325df1d | 10842 | file_mips_gp32 = 0; |
c97ef257 | 10843 | break; |
252b5132 | 10844 | |
ca4e0257 | 10845 | case OPTION_FP32: |
a325df1d | 10846 | file_mips_fp32 = 1; |
316f5878 RS |
10847 | break; |
10848 | ||
10849 | case OPTION_FP64: | |
10850 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10851 | break; |
10852 | ||
ae948b86 | 10853 | #ifdef OBJ_ELF |
252b5132 | 10854 | case OPTION_MABI: |
34ba82a8 TS |
10855 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10856 | { | |
10857 | as_bad (_("-mabi is supported for ELF format only")); | |
10858 | return 0; | |
10859 | } | |
e013f690 | 10860 | if (strcmp (arg, "32") == 0) |
316f5878 | 10861 | mips_abi = O32_ABI; |
e013f690 | 10862 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10863 | mips_abi = O64_ABI; |
e013f690 | 10864 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10865 | mips_abi = N32_ABI; |
e013f690 TS |
10866 | else if (strcmp (arg, "64") == 0) |
10867 | { | |
316f5878 | 10868 | mips_abi = N64_ABI; |
e013f690 TS |
10869 | if (! support_64bit_objects()) |
10870 | as_fatal (_("No compiled in support for 64 bit object file " | |
10871 | "format")); | |
10872 | } | |
10873 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10874 | mips_abi = EABI_ABI; |
e013f690 | 10875 | else |
da0e507f TS |
10876 | { |
10877 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10878 | return 0; | |
10879 | } | |
252b5132 | 10880 | break; |
e013f690 | 10881 | #endif /* OBJ_ELF */ |
252b5132 | 10882 | |
6b76fefe | 10883 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10884 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10885 | break; |
10886 | ||
9ee72ff1 | 10887 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10888 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10889 | break; |
10890 | ||
ecb4347a DJ |
10891 | #ifdef OBJ_ELF |
10892 | case OPTION_MDEBUG: | |
b34976b6 | 10893 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10894 | break; |
10895 | ||
10896 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10897 | mips_flag_mdebug = FALSE; |
ecb4347a | 10898 | break; |
dcd410fe RO |
10899 | |
10900 | case OPTION_PDR: | |
10901 | mips_flag_pdr = TRUE; | |
10902 | break; | |
10903 | ||
10904 | case OPTION_NO_PDR: | |
10905 | mips_flag_pdr = FALSE; | |
10906 | break; | |
ecb4347a DJ |
10907 | #endif /* OBJ_ELF */ |
10908 | ||
252b5132 RH |
10909 | default: |
10910 | return 0; | |
10911 | } | |
10912 | ||
10913 | return 1; | |
10914 | } | |
316f5878 RS |
10915 | \f |
10916 | /* Set up globals to generate code for the ISA or processor | |
10917 | described by INFO. */ | |
252b5132 | 10918 | |
252b5132 | 10919 | static void |
17a2f251 | 10920 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10921 | { |
316f5878 | 10922 | if (info != 0) |
252b5132 | 10923 | { |
fef14a42 TS |
10924 | file_mips_arch = info->cpu; |
10925 | mips_opts.arch = info->cpu; | |
316f5878 | 10926 | mips_opts.isa = info->isa; |
252b5132 | 10927 | } |
252b5132 RH |
10928 | } |
10929 | ||
252b5132 | 10930 | |
316f5878 | 10931 | /* Likewise for tuning. */ |
252b5132 | 10932 | |
316f5878 | 10933 | static void |
17a2f251 | 10934 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10935 | { |
10936 | if (info != 0) | |
fef14a42 | 10937 | mips_tune = info->cpu; |
316f5878 | 10938 | } |
80cc45a5 | 10939 | |
34ba82a8 | 10940 | |
252b5132 | 10941 | void |
17a2f251 | 10942 | mips_after_parse_args (void) |
e9670677 | 10943 | { |
fef14a42 TS |
10944 | const struct mips_cpu_info *arch_info = 0; |
10945 | const struct mips_cpu_info *tune_info = 0; | |
10946 | ||
e9670677 MR |
10947 | /* GP relative stuff not working for PE */ |
10948 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10949 | && g_switch_value != 0) | |
10950 | { | |
10951 | if (g_switch_seen) | |
10952 | as_bad (_("-G not supported in this configuration.")); | |
10953 | g_switch_value = 0; | |
10954 | } | |
10955 | ||
cac012d6 AO |
10956 | if (mips_abi == NO_ABI) |
10957 | mips_abi = MIPS_DEFAULT_ABI; | |
10958 | ||
22923709 RS |
10959 | /* The following code determines the architecture and register size. |
10960 | Similar code was added to GCC 3.3 (see override_options() in | |
10961 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10962 | as much as possible. */ | |
e9670677 | 10963 | |
316f5878 | 10964 | if (mips_arch_string != 0) |
fef14a42 | 10965 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10966 | |
316f5878 | 10967 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10968 | { |
316f5878 | 10969 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10970 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10971 | the -march selection (if any). */ |
fef14a42 | 10972 | if (arch_info != 0) |
e9670677 | 10973 | { |
316f5878 RS |
10974 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10975 | There's no harm in specifying both as long as the ISA levels | |
10976 | are the same. */ | |
fef14a42 | 10977 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10978 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10979 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10980 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10981 | } |
316f5878 | 10982 | else |
fef14a42 | 10983 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10984 | } |
10985 | ||
fef14a42 TS |
10986 | if (arch_info == 0) |
10987 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10988 | |
fef14a42 | 10989 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10990 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10991 | arch_info->name); |
10992 | ||
10993 | mips_set_architecture (arch_info); | |
10994 | ||
10995 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10996 | if (mips_tune_string != 0) | |
10997 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10998 | |
fef14a42 TS |
10999 | if (tune_info == 0) |
11000 | mips_set_tune (arch_info); | |
11001 | else | |
11002 | mips_set_tune (tune_info); | |
e9670677 | 11003 | |
316f5878 | 11004 | if (file_mips_gp32 >= 0) |
e9670677 | 11005 | { |
316f5878 RS |
11006 | /* The user specified the size of the integer registers. Make sure |
11007 | it agrees with the ABI and ISA. */ | |
11008 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11009 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11010 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11011 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11012 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11013 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11014 | } |
11015 | else | |
11016 | { | |
316f5878 RS |
11017 | /* Infer the integer register size from the ABI and processor. |
11018 | Restrict ourselves to 32-bit registers if that's all the | |
11019 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11020 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11021 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11022 | } |
11023 | ||
316f5878 RS |
11024 | /* ??? GAS treats single-float processors as though they had 64-bit |
11025 | float registers (although it complains when double-precision | |
11026 | instructions are used). As things stand, saying they have 32-bit | |
11027 | registers would lead to spurious "register must be even" messages. | |
11028 | So here we assume float registers are always the same size as | |
11029 | integer ones, unless the user says otherwise. */ | |
11030 | if (file_mips_fp32 < 0) | |
11031 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 11032 | |
316f5878 | 11033 | /* End of GCC-shared inference code. */ |
e9670677 | 11034 | |
17a2f251 TS |
11035 | /* This flag is set when we have a 64-bit capable CPU but use only |
11036 | 32-bit wide registers. Note that EABI does not use it. */ | |
11037 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11038 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11039 | || mips_abi == O32_ABI)) | |
316f5878 | 11040 | mips_32bitmode = 1; |
e9670677 MR |
11041 | |
11042 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11043 | as_bad (_("trap exception not supported at ISA 1")); | |
11044 | ||
e9670677 MR |
11045 | /* If the selected architecture includes support for ASEs, enable |
11046 | generation of code for them. */ | |
a4672219 | 11047 | if (mips_opts.mips16 == -1) |
fef14a42 | 11048 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11049 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 11050 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11051 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 11052 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 11053 | |
e9670677 | 11054 | file_mips_isa = mips_opts.isa; |
a4672219 | 11055 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11056 | file_ase_mips3d = mips_opts.ase_mips3d; |
11057 | file_ase_mdmx = mips_opts.ase_mdmx; | |
11058 | mips_opts.gp32 = file_mips_gp32; | |
11059 | mips_opts.fp32 = file_mips_fp32; | |
11060 | ||
ecb4347a DJ |
11061 | if (mips_flag_mdebug < 0) |
11062 | { | |
11063 | #ifdef OBJ_MAYBE_ECOFF | |
11064 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11065 | mips_flag_mdebug = 1; | |
11066 | else | |
11067 | #endif /* OBJ_MAYBE_ECOFF */ | |
11068 | mips_flag_mdebug = 0; | |
11069 | } | |
e9670677 MR |
11070 | } |
11071 | \f | |
11072 | void | |
17a2f251 | 11073 | mips_init_after_args (void) |
252b5132 RH |
11074 | { |
11075 | /* initialize opcodes */ | |
11076 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11077 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11078 | } |
11079 | ||
11080 | long | |
17a2f251 | 11081 | md_pcrel_from (fixS *fixP) |
252b5132 | 11082 | { |
a7ebbfdf TS |
11083 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11084 | switch (fixP->fx_r_type) | |
11085 | { | |
11086 | case BFD_RELOC_16_PCREL_S2: | |
11087 | case BFD_RELOC_MIPS_JMP: | |
11088 | /* Return the address of the delay slot. */ | |
11089 | return addr + 4; | |
11090 | default: | |
11091 | return addr; | |
11092 | } | |
252b5132 RH |
11093 | } |
11094 | ||
252b5132 RH |
11095 | /* This is called before the symbol table is processed. In order to |
11096 | work with gcc when using mips-tfile, we must keep all local labels. | |
11097 | However, in other cases, we want to discard them. If we were | |
11098 | called with -g, but we didn't see any debugging information, it may | |
11099 | mean that gcc is smuggling debugging information through to | |
11100 | mips-tfile, in which case we must generate all local labels. */ | |
11101 | ||
11102 | void | |
17a2f251 | 11103 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11104 | { |
11105 | #ifndef NO_ECOFF_DEBUGGING | |
11106 | if (ECOFF_DEBUGGING | |
11107 | && mips_debug != 0 | |
11108 | && ! ecoff_debugging_seen) | |
11109 | flag_keep_locals = 1; | |
11110 | #endif | |
11111 | } | |
11112 | ||
11113 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 11114 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
11115 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
11116 | explicit use of the %hi modifier. */ | |
11117 | ||
11118 | void | |
17a2f251 | 11119 | mips_frob_file (void) |
252b5132 RH |
11120 | { |
11121 | struct mips_hi_fixup *l; | |
11122 | ||
11123 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11124 | { | |
11125 | segment_info_type *seginfo; | |
11126 | int pass; | |
11127 | ||
5919d012 | 11128 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11129 | |
5919d012 RS |
11130 | /* If a GOT16 relocation turns out to be against a global symbol, |
11131 | there isn't supposed to be a matching LO. */ | |
11132 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11133 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11134 | continue; | |
11135 | ||
11136 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11137 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11138 | continue; |
11139 | ||
11140 | /* Look through the fixups for this segment for a matching %lo. | |
11141 | When we find one, move the %hi just in front of it. We do | |
11142 | this in two passes. In the first pass, we try to find a | |
11143 | unique %lo. In the second pass, we permit multiple %hi | |
11144 | relocs for a single %lo (this is a GNU extension). */ | |
11145 | seginfo = seg_info (l->seg); | |
11146 | for (pass = 0; pass < 2; pass++) | |
11147 | { | |
11148 | fixS *f, *prev; | |
11149 | ||
11150 | prev = NULL; | |
11151 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
11152 | { | |
11153 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
11154 | if (f->fx_r_type == BFD_RELOC_LO16 | |
11155 | && f->fx_addsy == l->fixp->fx_addsy | |
11156 | && f->fx_offset == l->fixp->fx_offset | |
11157 | && (pass == 1 | |
11158 | || prev == NULL | |
5919d012 RS |
11159 | || !reloc_needs_lo_p (prev->fx_r_type) |
11160 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
11161 | { |
11162 | fixS **pf; | |
11163 | ||
11164 | /* Move l->fixp before f. */ | |
11165 | for (pf = &seginfo->fix_root; | |
11166 | *pf != l->fixp; | |
11167 | pf = &(*pf)->fx_next) | |
11168 | assert (*pf != NULL); | |
11169 | ||
11170 | *pf = l->fixp->fx_next; | |
11171 | ||
11172 | l->fixp->fx_next = f; | |
11173 | if (prev == NULL) | |
11174 | seginfo->fix_root = l->fixp; | |
11175 | else | |
11176 | prev->fx_next = l->fixp; | |
11177 | ||
11178 | break; | |
11179 | } | |
11180 | ||
11181 | prev = f; | |
11182 | } | |
11183 | ||
11184 | if (f != NULL) | |
11185 | break; | |
11186 | ||
11187 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
11188 | can leave a %hi without a %lo. */ | |
11189 | if (pass == 1) | |
11190 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
11191 | _("Unmatched %%hi reloc")); | |
11192 | #endif | |
11193 | } | |
11194 | } | |
11195 | } | |
11196 | ||
11197 | /* When generating embedded PIC code we need to use a special | |
11198 | relocation to represent the difference of two symbols in the .text | |
11199 | section (switch tables use a difference of this sort). See | |
11200 | include/coff/mips.h for details. This macro checks whether this | |
11201 | fixup requires the special reloc. */ | |
11202 | #define SWITCH_TABLE(fixp) \ | |
11203 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 11204 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
11205 | && (fixp)->fx_addsy != NULL \ |
11206 | && (fixp)->fx_subsy != NULL \ | |
11207 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
11208 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11209 | ||
11210 | /* When generating embedded PIC code we must keep all PC relative | |
11211 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11212 | to keep relocations for switch table entries. |
11213 | ||
11214 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11215 | We have to prevent gas from dropping them. */ | |
252b5132 | 11216 | |
252b5132 | 11217 | int |
17a2f251 | 11218 | mips_force_relocation (fixS *fixp) |
252b5132 | 11219 | { |
ae6063d4 | 11220 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11221 | return 1; |
11222 | ||
f6688943 TS |
11223 | if (HAVE_NEWABI |
11224 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11225 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11226 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11227 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11228 | return 1; | |
11229 | ||
252b5132 RH |
11230 | return (mips_pic == EMBEDDED_PIC |
11231 | && (fixp->fx_pcrel | |
11232 | || SWITCH_TABLE (fixp) | |
11233 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11234 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11235 | } | |
11236 | ||
45f8dfe8 AO |
11237 | /* This hook is called before a fix is simplified. We don't really |
11238 | decide whether to skip a fix here. Rather, we turn global symbols | |
11239 | used as branch targets into local symbols, such that they undergo | |
11240 | simplification. We can only do this if the symbol is defined and | |
11241 | it is in the same section as the branch. If this doesn't hold, we | |
11242 | emit a better error message than just saying the relocation is not | |
11243 | valid for the selected object format. | |
11244 | ||
11245 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11246 | segment in which the fix up occurs. The return value should be | |
11247 | non-zero to indicate the fix-up is valid for further | |
11248 | simplifications. */ | |
11249 | ||
11250 | int | |
17a2f251 | 11251 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11252 | { |
11253 | /* There's a lot of discussion on whether it should be possible to | |
11254 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11255 | seems to be that it can, but gas/bfd are very broken in creating | |
11256 | RELA relocations for this, so for now we only accept branches to | |
11257 | symbols in the same section. Anything else is of dubious value, | |
11258 | since there's no guarantee that at link time the symbol would be | |
11259 | in range. Even for branches to local symbols this is arguably | |
11260 | wrong, since it we assume the symbol is not going to be | |
11261 | overridden, which should be possible per ELF library semantics, | |
11262 | but then, there isn't a dynamic relocation that could be used to | |
11263 | this effect, and the target would likely be out of range as well. | |
11264 | ||
11265 | Unfortunately, it seems that there is too much code out there | |
11266 | that relies on branches to symbols that are global to be resolved | |
11267 | as if they were local, like the IRIX tools do, so we do it as | |
11268 | well, but with a warning so that people are reminded to fix their | |
11269 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11270 | targets, this entire block should go away (and probably the | |
11271 | whole function). */ | |
11272 | ||
11273 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11274 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11275 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11276 | && mips_pic != EMBEDDED_PIC) | |
11277 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11278 | && fixP->fx_addsy) | |
11279 | { | |
11280 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11281 | { | |
11282 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11283 | _("Cannot branch to undefined symbol.")); | |
11284 | /* Avoid any further errors about this fixup. */ | |
11285 | fixP->fx_done = 1; | |
11286 | } | |
11287 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11288 | { | |
11289 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11290 | _("Cannot branch to symbol in another section.")); | |
11291 | fixP->fx_done = 1; | |
11292 | } | |
11293 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11294 | { | |
11295 | symbolS *sym = fixP->fx_addsy; | |
11296 | ||
115695a8 CD |
11297 | if (mips_pic == SVR4_PIC) |
11298 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11299 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11300 | |
11301 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11302 | S_GET_SEGMENT (sym), | |
11303 | S_GET_VALUE (sym), | |
11304 | symbol_get_frag (sym)); | |
11305 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11306 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11307 | assert (symbol_resolved_p (sym)); | |
11308 | symbol_mark_resolved (fixP->fx_addsy); | |
11309 | } | |
11310 | } | |
11311 | ||
11312 | return 1; | |
11313 | } | |
11314 | ||
252b5132 RH |
11315 | /* Apply a fixup to the object file. */ |
11316 | ||
94f592af | 11317 | void |
17a2f251 | 11318 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11319 | { |
874e8986 | 11320 | bfd_byte *buf; |
98aa84af | 11321 | long insn; |
ed6fb7bd | 11322 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11323 | reloc_howto_type *howto; |
252b5132 | 11324 | |
a7ebbfdf TS |
11325 | /* We ignore generic BFD relocations we don't know about. */ |
11326 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11327 | if (! howto) | |
11328 | return; | |
65551fa4 | 11329 | |
252b5132 RH |
11330 | assert (fixP->fx_size == 4 |
11331 | || fixP->fx_r_type == BFD_RELOC_16 | |
11332 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11333 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11334 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11335 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11336 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11337 | |
a7ebbfdf | 11338 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11339 | |
ed6fb7bd SC |
11340 | /* We are not done if this is a composite relocation to set up gp. */ |
11341 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11342 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11343 | || (fixP->fx_r_type == BFD_RELOC_64 |
11344 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11345 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11346 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11347 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11348 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11349 | fixP->fx_done = 1; |
ed6fb7bd | 11350 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11351 | |
11352 | switch (fixP->fx_r_type) | |
11353 | { | |
11354 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11355 | case BFD_RELOC_MIPS_SHIFT5: |
11356 | case BFD_RELOC_MIPS_SHIFT6: | |
11357 | case BFD_RELOC_MIPS_GOT_DISP: | |
11358 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11359 | case BFD_RELOC_MIPS_GOT_OFST: | |
11360 | case BFD_RELOC_MIPS_SUB: | |
11361 | case BFD_RELOC_MIPS_INSERT_A: | |
11362 | case BFD_RELOC_MIPS_INSERT_B: | |
11363 | case BFD_RELOC_MIPS_DELETE: | |
11364 | case BFD_RELOC_MIPS_HIGHEST: | |
11365 | case BFD_RELOC_MIPS_HIGHER: | |
11366 | case BFD_RELOC_MIPS_SCN_DISP: | |
11367 | case BFD_RELOC_MIPS_REL16: | |
11368 | case BFD_RELOC_MIPS_RELGOT: | |
11369 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11370 | case BFD_RELOC_HI16: |
11371 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11372 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11373 | case BFD_RELOC_MIPS_LITERAL: |
11374 | case BFD_RELOC_MIPS_CALL16: | |
11375 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11376 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11377 | case BFD_RELOC_MIPS_GOT_HI16: |
11378 | case BFD_RELOC_MIPS_GOT_LO16: | |
11379 | case BFD_RELOC_MIPS_CALL_HI16: | |
11380 | case BFD_RELOC_MIPS_CALL_LO16: | |
11381 | case BFD_RELOC_MIPS16_GPREL: | |
11382 | if (fixP->fx_pcrel) | |
11383 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11384 | _("Invalid PC relative reloc")); | |
11385 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11386 | break; | |
11387 | ||
11388 | case BFD_RELOC_MIPS16_JMP: | |
11389 | /* We currently always generate a reloc against a symbol, which | |
11390 | means that we don't want an addend even if the symbol is | |
11391 | defined. */ | |
a7ebbfdf | 11392 | *valP = 0; |
252b5132 RH |
11393 | break; |
11394 | ||
11395 | case BFD_RELOC_PCREL_HI16_S: | |
11396 | /* The addend for this is tricky if it is internal, so we just | |
11397 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11398 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11399 | break; |
11400 | if (fixP->fx_addsy | |
11401 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11402 | { |
11403 | /* For an external symbol adjust by the address to make it | |
11404 | pcrel_offset. We use the address of the RELLO reloc | |
11405 | which follows this one. */ | |
a7ebbfdf | 11406 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11407 | + fixP->fx_next->fx_where); |
11408 | } | |
a7ebbfdf | 11409 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11410 | if (target_big_endian) |
11411 | buf += 2; | |
17a2f251 | 11412 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11413 | break; |
11414 | ||
11415 | case BFD_RELOC_PCREL_LO16: | |
11416 | /* The addend for this is tricky if it is internal, so we just | |
11417 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11418 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11419 | break; |
11420 | if (fixP->fx_addsy | |
11421 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11422 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11423 | if (target_big_endian) |
11424 | buf += 2; | |
17a2f251 | 11425 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11426 | break; |
11427 | ||
11428 | case BFD_RELOC_64: | |
11429 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11430 | extended value if we are only 32 bits. */ | |
11431 | if (fixP->fx_done | |
11432 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11433 | { | |
11434 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11435 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11436 | else |
11437 | { | |
a7ebbfdf | 11438 | valueT hiv; |
252b5132 | 11439 | |
a7ebbfdf | 11440 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11441 | hiv = 0xffffffff; |
11442 | else | |
11443 | hiv = 0; | |
a7ebbfdf TS |
11444 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11445 | *valP, 4); | |
11446 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11447 | hiv, 4); | |
252b5132 RH |
11448 | } |
11449 | } | |
11450 | break; | |
11451 | ||
056350c6 | 11452 | case BFD_RELOC_RVA: |
252b5132 RH |
11453 | case BFD_RELOC_32: |
11454 | /* If we are deleting this reloc entry, we must fill in the | |
11455 | value now. This can happen if we have a .word which is not | |
11456 | resolved when it appears but is later defined. We also need | |
11457 | to fill in the value if this is an embedded PIC switch table | |
11458 | entry. */ | |
11459 | if (fixP->fx_done | |
11460 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11461 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11462 | break; |
11463 | ||
11464 | case BFD_RELOC_16: | |
11465 | /* If we are deleting this reloc entry, we must fill in the | |
11466 | value now. */ | |
11467 | assert (fixP->fx_size == 2); | |
11468 | if (fixP->fx_done) | |
a7ebbfdf | 11469 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11470 | break; |
11471 | ||
11472 | case BFD_RELOC_LO16: | |
11473 | /* When handling an embedded PIC switch statement, we can wind | |
11474 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11475 | if (fixP->fx_done) | |
11476 | { | |
a7ebbfdf | 11477 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11478 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11479 | _("relocation overflow")); | |
252b5132 RH |
11480 | if (target_big_endian) |
11481 | buf += 2; | |
17a2f251 | 11482 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11483 | } |
11484 | break; | |
11485 | ||
11486 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11487 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11488 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11489 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11490 | |
252b5132 RH |
11491 | /* |
11492 | * We need to save the bits in the instruction since fixup_segment() | |
11493 | * might be deleting the relocation entry (i.e., a branch within | |
11494 | * the current segment). | |
11495 | */ | |
a7ebbfdf | 11496 | if (! fixP->fx_done) |
bb2d6cd7 | 11497 | break; |
252b5132 RH |
11498 | |
11499 | /* update old instruction data */ | |
252b5132 RH |
11500 | if (target_big_endian) |
11501 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11502 | else | |
11503 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11504 | ||
a7ebbfdf TS |
11505 | if (*valP + 0x20000 <= 0x3ffff) |
11506 | { | |
11507 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11508 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11509 | } |
11510 | else if (mips_pic == NO_PIC | |
11511 | && fixP->fx_done | |
11512 | && fixP->fx_frag->fr_address >= text_section->vma | |
11513 | && (fixP->fx_frag->fr_address | |
11514 | < text_section->vma + text_section->_raw_size) | |
11515 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11516 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11517 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11518 | { |
11519 | /* The branch offset is too large. If this is an | |
11520 | unconditional branch, and we are not generating PIC code, | |
11521 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11522 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11523 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11524 | else |
a7ebbfdf TS |
11525 | insn = 0x08000000; /* j */ |
11526 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11527 | fixP->fx_done = 0; | |
11528 | fixP->fx_addsy = section_symbol (text_section); | |
11529 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11530 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11531 | } |
11532 | else | |
11533 | { | |
11534 | /* If we got here, we have branch-relaxation disabled, | |
11535 | and there's nothing we can do to fix this instruction | |
11536 | without turning it into a longer sequence. */ | |
11537 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11538 | _("Branch out of range")); | |
252b5132 | 11539 | } |
252b5132 RH |
11540 | break; |
11541 | ||
11542 | case BFD_RELOC_VTABLE_INHERIT: | |
11543 | fixP->fx_done = 0; | |
11544 | if (fixP->fx_addsy | |
11545 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11546 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11547 | S_SET_WEAK (fixP->fx_addsy); | |
11548 | break; | |
11549 | ||
11550 | case BFD_RELOC_VTABLE_ENTRY: | |
11551 | fixP->fx_done = 0; | |
11552 | break; | |
11553 | ||
11554 | default: | |
11555 | internalError (); | |
11556 | } | |
a7ebbfdf TS |
11557 | |
11558 | /* Remember value for tc_gen_reloc. */ | |
11559 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11560 | } |
11561 | ||
11562 | #if 0 | |
11563 | void | |
17a2f251 | 11564 | printInsn (unsigned long oc) |
252b5132 RH |
11565 | { |
11566 | const struct mips_opcode *p; | |
11567 | int treg, sreg, dreg, shamt; | |
11568 | short imm; | |
11569 | const char *args; | |
11570 | int i; | |
11571 | ||
11572 | for (i = 0; i < NUMOPCODES; ++i) | |
11573 | { | |
11574 | p = &mips_opcodes[i]; | |
11575 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11576 | { | |
11577 | printf ("%08lx %s\t", oc, p->name); | |
11578 | treg = (oc >> 16) & 0x1f; | |
11579 | sreg = (oc >> 21) & 0x1f; | |
11580 | dreg = (oc >> 11) & 0x1f; | |
11581 | shamt = (oc >> 6) & 0x1f; | |
11582 | imm = oc; | |
11583 | for (args = p->args;; ++args) | |
11584 | { | |
11585 | switch (*args) | |
11586 | { | |
11587 | case '\0': | |
11588 | printf ("\n"); | |
11589 | break; | |
11590 | ||
11591 | case ',': | |
11592 | case '(': | |
11593 | case ')': | |
11594 | printf ("%c", *args); | |
11595 | continue; | |
11596 | ||
11597 | case 'r': | |
11598 | assert (treg == sreg); | |
11599 | printf ("$%d,$%d", treg, sreg); | |
11600 | continue; | |
11601 | ||
11602 | case 'd': | |
11603 | case 'G': | |
11604 | printf ("$%d", dreg); | |
11605 | continue; | |
11606 | ||
11607 | case 't': | |
11608 | case 'E': | |
11609 | printf ("$%d", treg); | |
11610 | continue; | |
11611 | ||
11612 | case 'k': | |
11613 | printf ("0x%x", treg); | |
11614 | continue; | |
11615 | ||
11616 | case 'b': | |
11617 | case 's': | |
11618 | printf ("$%d", sreg); | |
11619 | continue; | |
11620 | ||
11621 | case 'a': | |
11622 | printf ("0x%08lx", oc & 0x1ffffff); | |
11623 | continue; | |
11624 | ||
11625 | case 'i': | |
11626 | case 'j': | |
11627 | case 'o': | |
11628 | case 'u': | |
11629 | printf ("%d", imm); | |
11630 | continue; | |
11631 | ||
11632 | case '<': | |
11633 | case '>': | |
11634 | printf ("$%d", shamt); | |
11635 | continue; | |
11636 | ||
11637 | default: | |
11638 | internalError (); | |
11639 | } | |
11640 | break; | |
11641 | } | |
11642 | return; | |
11643 | } | |
11644 | } | |
11645 | printf (_("%08lx UNDEFINED\n"), oc); | |
11646 | } | |
11647 | #endif | |
11648 | ||
11649 | static symbolS * | |
17a2f251 | 11650 | get_symbol (void) |
252b5132 RH |
11651 | { |
11652 | int c; | |
11653 | char *name; | |
11654 | symbolS *p; | |
11655 | ||
11656 | name = input_line_pointer; | |
11657 | c = get_symbol_end (); | |
11658 | p = (symbolS *) symbol_find_or_make (name); | |
11659 | *input_line_pointer = c; | |
11660 | return p; | |
11661 | } | |
11662 | ||
11663 | /* Align the current frag to a given power of two. The MIPS assembler | |
11664 | also automatically adjusts any preceding label. */ | |
11665 | ||
11666 | static void | |
17a2f251 | 11667 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11668 | { |
b34976b6 | 11669 | mips_emit_delays (FALSE); |
252b5132 RH |
11670 | frag_align (to, fill, 0); |
11671 | record_alignment (now_seg, to); | |
11672 | if (label != NULL) | |
11673 | { | |
11674 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11675 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11676 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11677 | } | |
11678 | } | |
11679 | ||
11680 | /* Align to a given power of two. .align 0 turns off the automatic | |
11681 | alignment used by the data creating pseudo-ops. */ | |
11682 | ||
11683 | static void | |
17a2f251 | 11684 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11685 | { |
11686 | register int temp; | |
11687 | register long temp_fill; | |
11688 | long max_alignment = 15; | |
11689 | ||
11690 | /* | |
11691 | ||
67c1ffbe | 11692 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11693 | to the aligned address. |
11694 | o It's not documented but auto alignment is reinstated by | |
11695 | a .align pseudo instruction. | |
11696 | o Note also that after auto alignment is turned off the mips assembler | |
11697 | issues an error on attempt to assemble an improperly aligned data item. | |
11698 | We don't. | |
11699 | ||
11700 | */ | |
11701 | ||
11702 | temp = get_absolute_expression (); | |
11703 | if (temp > max_alignment) | |
11704 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11705 | else if (temp < 0) | |
11706 | { | |
11707 | as_warn (_("Alignment negative: 0 assumed.")); | |
11708 | temp = 0; | |
11709 | } | |
11710 | if (*input_line_pointer == ',') | |
11711 | { | |
f9419b05 | 11712 | ++input_line_pointer; |
252b5132 RH |
11713 | temp_fill = get_absolute_expression (); |
11714 | } | |
11715 | else | |
11716 | temp_fill = 0; | |
11717 | if (temp) | |
11718 | { | |
11719 | auto_align = 1; | |
11720 | mips_align (temp, (int) temp_fill, | |
11721 | insn_labels != NULL ? insn_labels->label : NULL); | |
11722 | } | |
11723 | else | |
11724 | { | |
11725 | auto_align = 0; | |
11726 | } | |
11727 | ||
11728 | demand_empty_rest_of_line (); | |
11729 | } | |
11730 | ||
11731 | void | |
17a2f251 | 11732 | mips_flush_pending_output (void) |
252b5132 | 11733 | { |
b34976b6 | 11734 | mips_emit_delays (FALSE); |
252b5132 RH |
11735 | mips_clear_insn_labels (); |
11736 | } | |
11737 | ||
11738 | static void | |
17a2f251 | 11739 | s_change_sec (int sec) |
252b5132 RH |
11740 | { |
11741 | segT seg; | |
11742 | ||
11743 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11744 | .sdata and .sbss sections. We change the .data and .rdata | |
11745 | pseudo-ops to use .sdata. */ | |
11746 | if (mips_pic == EMBEDDED_PIC | |
11747 | && (sec == 'd' || sec == 'r')) | |
11748 | sec = 's'; | |
11749 | ||
11750 | #ifdef OBJ_ELF | |
11751 | /* The ELF backend needs to know that we are changing sections, so | |
11752 | that .previous works correctly. We could do something like check | |
b6ff326e | 11753 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11754 | as it would not be appropriate to use it in the section changing |
11755 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11756 | This should be cleaner, somehow. */ | |
11757 | obj_elf_section_change_hook (); | |
11758 | #endif | |
11759 | ||
b34976b6 | 11760 | mips_emit_delays (FALSE); |
252b5132 RH |
11761 | switch (sec) |
11762 | { | |
11763 | case 't': | |
11764 | s_text (0); | |
11765 | break; | |
11766 | case 'd': | |
11767 | s_data (0); | |
11768 | break; | |
11769 | case 'b': | |
11770 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11771 | demand_empty_rest_of_line (); | |
11772 | break; | |
11773 | ||
11774 | case 'r': | |
11775 | if (USE_GLOBAL_POINTER_OPT) | |
11776 | { | |
11777 | seg = subseg_new (RDATA_SECTION_NAME, | |
11778 | (subsegT) get_absolute_expression ()); | |
11779 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11780 | { | |
11781 | bfd_set_section_flags (stdoutput, seg, | |
11782 | (SEC_ALLOC | |
11783 | | SEC_LOAD | |
11784 | | SEC_READONLY | |
11785 | | SEC_RELOC | |
11786 | | SEC_DATA)); | |
11787 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11788 | record_alignment (seg, 4); |
252b5132 RH |
11789 | } |
11790 | demand_empty_rest_of_line (); | |
11791 | } | |
11792 | else | |
11793 | { | |
11794 | as_bad (_("No read only data section in this object file format")); | |
11795 | demand_empty_rest_of_line (); | |
11796 | return; | |
11797 | } | |
11798 | break; | |
11799 | ||
11800 | case 's': | |
11801 | if (USE_GLOBAL_POINTER_OPT) | |
11802 | { | |
11803 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11804 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11805 | { | |
11806 | bfd_set_section_flags (stdoutput, seg, | |
11807 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11808 | | SEC_DATA); | |
11809 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11810 | record_alignment (seg, 4); |
252b5132 RH |
11811 | } |
11812 | demand_empty_rest_of_line (); | |
11813 | break; | |
11814 | } | |
11815 | else | |
11816 | { | |
11817 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11818 | demand_empty_rest_of_line (); | |
11819 | return; | |
11820 | } | |
11821 | } | |
11822 | ||
11823 | auto_align = 1; | |
11824 | } | |
b34976b6 | 11825 | |
cca86cc8 | 11826 | void |
17a2f251 | 11827 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11828 | { |
7ed4a06a | 11829 | #ifdef OBJ_ELF |
cca86cc8 SC |
11830 | char *section_name; |
11831 | char c; | |
684022ea | 11832 | char next_c = 0; |
cca86cc8 SC |
11833 | int section_type; |
11834 | int section_flag; | |
11835 | int section_entry_size; | |
11836 | int section_alignment; | |
b34976b6 | 11837 | |
7ed4a06a TS |
11838 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11839 | return; | |
11840 | ||
cca86cc8 SC |
11841 | section_name = input_line_pointer; |
11842 | c = get_symbol_end (); | |
a816d1ed AO |
11843 | if (c) |
11844 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11845 | |
4cf0dd0d TS |
11846 | /* Do we have .section Name<,"flags">? */ |
11847 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11848 | { |
4cf0dd0d TS |
11849 | /* just after name is now '\0'. */ |
11850 | *input_line_pointer = c; | |
cca86cc8 SC |
11851 | input_line_pointer = section_name; |
11852 | obj_elf_section (ignore); | |
11853 | return; | |
11854 | } | |
11855 | input_line_pointer++; | |
11856 | ||
11857 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11858 | if (c == ',') | |
11859 | section_type = get_absolute_expression (); | |
11860 | else | |
11861 | section_type = 0; | |
11862 | if (*input_line_pointer++ == ',') | |
11863 | section_flag = get_absolute_expression (); | |
11864 | else | |
11865 | section_flag = 0; | |
11866 | if (*input_line_pointer++ == ',') | |
11867 | section_entry_size = get_absolute_expression (); | |
11868 | else | |
11869 | section_entry_size = 0; | |
11870 | if (*input_line_pointer++ == ',') | |
11871 | section_alignment = get_absolute_expression (); | |
11872 | else | |
11873 | section_alignment = 0; | |
11874 | ||
a816d1ed AO |
11875 | section_name = xstrdup (section_name); |
11876 | ||
8ab8a5c8 RS |
11877 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11878 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11879 | traditionally had to fall back on the more common @progbits instead. | |
11880 | ||
11881 | There's nothing really harmful in this, since bfd will correct | |
11882 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11883 | means that, for backwards compatibiltiy, the special_section entries | |
11884 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11885 | ||
11886 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11887 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11888 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11889 | generic type-checking code. */ | |
11890 | if (section_type == SHT_MIPS_DWARF) | |
11891 | section_type = SHT_PROGBITS; | |
11892 | ||
cca86cc8 SC |
11893 | obj_elf_change_section (section_name, section_type, section_flag, |
11894 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11895 | |
11896 | if (now_seg->name != section_name) | |
11897 | free (section_name); | |
7ed4a06a | 11898 | #endif /* OBJ_ELF */ |
cca86cc8 | 11899 | } |
252b5132 RH |
11900 | |
11901 | void | |
17a2f251 | 11902 | mips_enable_auto_align (void) |
252b5132 RH |
11903 | { |
11904 | auto_align = 1; | |
11905 | } | |
11906 | ||
11907 | static void | |
17a2f251 | 11908 | s_cons (int log_size) |
252b5132 RH |
11909 | { |
11910 | symbolS *label; | |
11911 | ||
11912 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11913 | mips_emit_delays (FALSE); |
252b5132 RH |
11914 | if (log_size > 0 && auto_align) |
11915 | mips_align (log_size, 0, label); | |
11916 | mips_clear_insn_labels (); | |
11917 | cons (1 << log_size); | |
11918 | } | |
11919 | ||
11920 | static void | |
17a2f251 | 11921 | s_float_cons (int type) |
252b5132 RH |
11922 | { |
11923 | symbolS *label; | |
11924 | ||
11925 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11926 | ||
b34976b6 | 11927 | mips_emit_delays (FALSE); |
252b5132 RH |
11928 | |
11929 | if (auto_align) | |
49309057 ILT |
11930 | { |
11931 | if (type == 'd') | |
11932 | mips_align (3, 0, label); | |
11933 | else | |
11934 | mips_align (2, 0, label); | |
11935 | } | |
252b5132 RH |
11936 | |
11937 | mips_clear_insn_labels (); | |
11938 | ||
11939 | float_cons (type); | |
11940 | } | |
11941 | ||
11942 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11943 | permitted to say | |
11944 | .globl foo .text | |
11945 | where foo is an undefined symbol, to mean that foo should be | |
11946 | considered to be the address of a function. */ | |
11947 | ||
11948 | static void | |
17a2f251 | 11949 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11950 | { |
11951 | char *name; | |
11952 | int c; | |
11953 | symbolS *symbolP; | |
11954 | flagword flag; | |
11955 | ||
11956 | name = input_line_pointer; | |
11957 | c = get_symbol_end (); | |
11958 | symbolP = symbol_find_or_make (name); | |
11959 | *input_line_pointer = c; | |
11960 | SKIP_WHITESPACE (); | |
11961 | ||
11962 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11963 | being a function is apparently labelled as being an object. */ | |
11964 | flag = BSF_OBJECT; | |
11965 | ||
11966 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11967 | { | |
11968 | char *secname; | |
11969 | asection *sec; | |
11970 | ||
11971 | secname = input_line_pointer; | |
11972 | c = get_symbol_end (); | |
11973 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11974 | if (sec == NULL) | |
11975 | as_bad (_("%s: no such section"), secname); | |
11976 | *input_line_pointer = c; | |
11977 | ||
11978 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11979 | flag = BSF_FUNCTION; | |
11980 | } | |
11981 | ||
49309057 | 11982 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11983 | |
11984 | S_SET_EXTERNAL (symbolP); | |
11985 | demand_empty_rest_of_line (); | |
11986 | } | |
11987 | ||
11988 | static void | |
17a2f251 | 11989 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11990 | { |
11991 | char *opt; | |
11992 | char c; | |
11993 | ||
11994 | opt = input_line_pointer; | |
11995 | c = get_symbol_end (); | |
11996 | ||
11997 | if (*opt == 'O') | |
11998 | { | |
11999 | /* FIXME: What does this mean? */ | |
12000 | } | |
12001 | else if (strncmp (opt, "pic", 3) == 0) | |
12002 | { | |
12003 | int i; | |
12004 | ||
12005 | i = atoi (opt + 3); | |
12006 | if (i == 0) | |
12007 | mips_pic = NO_PIC; | |
12008 | else if (i == 2) | |
143d77c5 | 12009 | { |
252b5132 | 12010 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12011 | mips_abicalls = TRUE; |
12012 | } | |
252b5132 RH |
12013 | else |
12014 | as_bad (_(".option pic%d not supported"), i); | |
12015 | ||
12016 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
12017 | { | |
12018 | if (g_switch_seen && g_switch_value != 0) | |
12019 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12020 | g_switch_value = 0; | |
12021 | bfd_set_gp_size (stdoutput, 0); | |
12022 | } | |
12023 | } | |
12024 | else | |
12025 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12026 | ||
12027 | *input_line_pointer = c; | |
12028 | demand_empty_rest_of_line (); | |
12029 | } | |
12030 | ||
12031 | /* This structure is used to hold a stack of .set values. */ | |
12032 | ||
e972090a NC |
12033 | struct mips_option_stack |
12034 | { | |
252b5132 RH |
12035 | struct mips_option_stack *next; |
12036 | struct mips_set_options options; | |
12037 | }; | |
12038 | ||
12039 | static struct mips_option_stack *mips_opts_stack; | |
12040 | ||
12041 | /* Handle the .set pseudo-op. */ | |
12042 | ||
12043 | static void | |
17a2f251 | 12044 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12045 | { |
12046 | char *name = input_line_pointer, ch; | |
12047 | ||
12048 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12049 | ++input_line_pointer; |
252b5132 RH |
12050 | ch = *input_line_pointer; |
12051 | *input_line_pointer = '\0'; | |
12052 | ||
12053 | if (strcmp (name, "reorder") == 0) | |
12054 | { | |
12055 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
12056 | { | |
12057 | /* If we still have pending nops, we can discard them. The | |
12058 | usual nop handling will insert any that are still | |
bdaaa2e1 | 12059 | needed. */ |
252b5132 RH |
12060 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
12061 | * (mips_opts.mips16 ? 2 : 4)); | |
12062 | prev_nop_frag = NULL; | |
12063 | } | |
12064 | mips_opts.noreorder = 0; | |
12065 | } | |
12066 | else if (strcmp (name, "noreorder") == 0) | |
12067 | { | |
b34976b6 | 12068 | mips_emit_delays (TRUE); |
252b5132 RH |
12069 | mips_opts.noreorder = 1; |
12070 | mips_any_noreorder = 1; | |
12071 | } | |
12072 | else if (strcmp (name, "at") == 0) | |
12073 | { | |
12074 | mips_opts.noat = 0; | |
12075 | } | |
12076 | else if (strcmp (name, "noat") == 0) | |
12077 | { | |
12078 | mips_opts.noat = 1; | |
12079 | } | |
12080 | else if (strcmp (name, "macro") == 0) | |
12081 | { | |
12082 | mips_opts.warn_about_macros = 0; | |
12083 | } | |
12084 | else if (strcmp (name, "nomacro") == 0) | |
12085 | { | |
12086 | if (mips_opts.noreorder == 0) | |
12087 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12088 | mips_opts.warn_about_macros = 1; | |
12089 | } | |
12090 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12091 | { | |
12092 | mips_opts.nomove = 0; | |
12093 | } | |
12094 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12095 | { | |
12096 | mips_opts.nomove = 1; | |
12097 | } | |
12098 | else if (strcmp (name, "bopt") == 0) | |
12099 | { | |
12100 | mips_opts.nobopt = 0; | |
12101 | } | |
12102 | else if (strcmp (name, "nobopt") == 0) | |
12103 | { | |
12104 | mips_opts.nobopt = 1; | |
12105 | } | |
12106 | else if (strcmp (name, "mips16") == 0 | |
12107 | || strcmp (name, "MIPS-16") == 0) | |
12108 | mips_opts.mips16 = 1; | |
12109 | else if (strcmp (name, "nomips16") == 0 | |
12110 | || strcmp (name, "noMIPS-16") == 0) | |
12111 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
12112 | else if (strcmp (name, "mips3d") == 0) |
12113 | mips_opts.ase_mips3d = 1; | |
12114 | else if (strcmp (name, "nomips3d") == 0) | |
12115 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12116 | else if (strcmp (name, "mdmx") == 0) |
12117 | mips_opts.ase_mdmx = 1; | |
12118 | else if (strcmp (name, "nomdmx") == 0) | |
12119 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 12120 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12121 | { |
af7ee8bf | 12122 | int reset = 0; |
252b5132 | 12123 | |
1a2c1fad CD |
12124 | /* Permit the user to change the ISA and architecture on the fly. |
12125 | Needless to say, misuse can cause serious problems. */ | |
af7ee8bf CD |
12126 | if (strcmp (name, "mips0") == 0) |
12127 | { | |
12128 | reset = 1; | |
12129 | mips_opts.isa = file_mips_isa; | |
12130 | } | |
12131 | else if (strcmp (name, "mips1") == 0) | |
12132 | mips_opts.isa = ISA_MIPS1; | |
12133 | else if (strcmp (name, "mips2") == 0) | |
12134 | mips_opts.isa = ISA_MIPS2; | |
12135 | else if (strcmp (name, "mips3") == 0) | |
12136 | mips_opts.isa = ISA_MIPS3; | |
12137 | else if (strcmp (name, "mips4") == 0) | |
12138 | mips_opts.isa = ISA_MIPS4; | |
12139 | else if (strcmp (name, "mips5") == 0) | |
12140 | mips_opts.isa = ISA_MIPS5; | |
12141 | else if (strcmp (name, "mips32") == 0) | |
12142 | mips_opts.isa = ISA_MIPS32; | |
12143 | else if (strcmp (name, "mips32r2") == 0) | |
12144 | mips_opts.isa = ISA_MIPS32R2; | |
12145 | else if (strcmp (name, "mips64") == 0) | |
12146 | mips_opts.isa = ISA_MIPS64; | |
5f74bc13 CD |
12147 | else if (strcmp (name, "mips64r2") == 0) |
12148 | mips_opts.isa = ISA_MIPS64R2; | |
1a2c1fad CD |
12149 | else if (strcmp (name, "arch=default") == 0) |
12150 | { | |
12151 | reset = 1; | |
12152 | mips_opts.arch = file_mips_arch; | |
12153 | mips_opts.isa = file_mips_isa; | |
12154 | } | |
12155 | else if (strncmp (name, "arch=", 5) == 0) | |
12156 | { | |
12157 | const struct mips_cpu_info *p; | |
12158 | ||
12159 | p = mips_parse_cpu("internal use", name + 5); | |
12160 | if (!p) | |
12161 | as_bad (_("unknown architecture %s"), name + 5); | |
12162 | else | |
12163 | { | |
12164 | mips_opts.arch = p->cpu; | |
12165 | mips_opts.isa = p->isa; | |
12166 | } | |
12167 | } | |
af7ee8bf CD |
12168 | else |
12169 | as_bad (_("unknown ISA level %s"), name + 4); | |
12170 | ||
12171 | switch (mips_opts.isa) | |
98d3f06f KH |
12172 | { |
12173 | case 0: | |
98d3f06f | 12174 | break; |
af7ee8bf CD |
12175 | case ISA_MIPS1: |
12176 | case ISA_MIPS2: | |
12177 | case ISA_MIPS32: | |
12178 | case ISA_MIPS32R2: | |
98d3f06f KH |
12179 | mips_opts.gp32 = 1; |
12180 | mips_opts.fp32 = 1; | |
12181 | break; | |
af7ee8bf CD |
12182 | case ISA_MIPS3: |
12183 | case ISA_MIPS4: | |
12184 | case ISA_MIPS5: | |
12185 | case ISA_MIPS64: | |
5f74bc13 | 12186 | case ISA_MIPS64R2: |
98d3f06f KH |
12187 | mips_opts.gp32 = 0; |
12188 | mips_opts.fp32 = 0; | |
12189 | break; | |
12190 | default: | |
12191 | as_bad (_("unknown ISA level %s"), name + 4); | |
12192 | break; | |
12193 | } | |
af7ee8bf | 12194 | if (reset) |
98d3f06f | 12195 | { |
af7ee8bf CD |
12196 | mips_opts.gp32 = file_mips_gp32; |
12197 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12198 | } |
252b5132 RH |
12199 | } |
12200 | else if (strcmp (name, "autoextend") == 0) | |
12201 | mips_opts.noautoextend = 0; | |
12202 | else if (strcmp (name, "noautoextend") == 0) | |
12203 | mips_opts.noautoextend = 1; | |
12204 | else if (strcmp (name, "push") == 0) | |
12205 | { | |
12206 | struct mips_option_stack *s; | |
12207 | ||
12208 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12209 | s->next = mips_opts_stack; | |
12210 | s->options = mips_opts; | |
12211 | mips_opts_stack = s; | |
12212 | } | |
12213 | else if (strcmp (name, "pop") == 0) | |
12214 | { | |
12215 | struct mips_option_stack *s; | |
12216 | ||
12217 | s = mips_opts_stack; | |
12218 | if (s == NULL) | |
12219 | as_bad (_(".set pop with no .set push")); | |
12220 | else | |
12221 | { | |
12222 | /* If we're changing the reorder mode we need to handle | |
12223 | delay slots correctly. */ | |
12224 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12225 | mips_emit_delays (TRUE); |
252b5132 RH |
12226 | else if (! s->options.noreorder && mips_opts.noreorder) |
12227 | { | |
12228 | if (prev_nop_frag != NULL) | |
12229 | { | |
12230 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12231 | * (mips_opts.mips16 ? 2 : 4)); | |
12232 | prev_nop_frag = NULL; | |
12233 | } | |
12234 | } | |
12235 | ||
12236 | mips_opts = s->options; | |
12237 | mips_opts_stack = s->next; | |
12238 | free (s); | |
12239 | } | |
12240 | } | |
12241 | else | |
12242 | { | |
12243 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12244 | } | |
12245 | *input_line_pointer = ch; | |
12246 | demand_empty_rest_of_line (); | |
12247 | } | |
12248 | ||
12249 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12250 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12251 | ||
12252 | static void | |
17a2f251 | 12253 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12254 | { |
12255 | mips_pic = SVR4_PIC; | |
143d77c5 | 12256 | mips_abicalls = TRUE; |
252b5132 RH |
12257 | if (USE_GLOBAL_POINTER_OPT) |
12258 | { | |
12259 | if (g_switch_seen && g_switch_value != 0) | |
12260 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12261 | g_switch_value = 0; | |
12262 | } | |
12263 | bfd_set_gp_size (stdoutput, 0); | |
12264 | demand_empty_rest_of_line (); | |
12265 | } | |
12266 | ||
12267 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12268 | PIC code. It sets the $gp register for the function based on the | |
12269 | function address, which is in the register named in the argument. | |
12270 | This uses a relocation against _gp_disp, which is handled specially | |
12271 | by the linker. The result is: | |
12272 | lui $gp,%hi(_gp_disp) | |
12273 | addiu $gp,$gp,%lo(_gp_disp) | |
12274 | addu $gp,$gp,.cpload argument | |
12275 | The .cpload argument is normally $25 == $t9. */ | |
12276 | ||
12277 | static void | |
17a2f251 | 12278 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12279 | { |
12280 | expressionS ex; | |
12281 | int icnt = 0; | |
12282 | ||
6478892d TS |
12283 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12284 | .cpload is ignored. */ | |
12285 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12286 | { |
12287 | s_ignore (0); | |
12288 | return; | |
12289 | } | |
12290 | ||
d3ecfc59 | 12291 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12292 | if (mips_opts.noreorder == 0) |
12293 | as_warn (_(".cpload not in noreorder section")); | |
12294 | ||
12295 | ex.X_op = O_symbol; | |
12296 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12297 | ex.X_op_symbol = NULL; | |
12298 | ex.X_add_number = 0; | |
12299 | ||
12300 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12301 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12302 | |
c9914766 | 12303 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
17a2f251 TS |
12304 | macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register, |
12305 | mips_gp_register, BFD_RELOC_LO16); | |
252b5132 | 12306 | |
17a2f251 TS |
12307 | macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register, |
12308 | mips_gp_register, tc_get_register (0)); | |
252b5132 RH |
12309 | |
12310 | demand_empty_rest_of_line (); | |
12311 | } | |
12312 | ||
6478892d TS |
12313 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12314 | .cpsetup $reg1, offset|$reg2, label | |
12315 | ||
12316 | If offset is given, this results in: | |
12317 | sd $gp, offset($sp) | |
956cd1d6 | 12318 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12319 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12320 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12321 | |
12322 | If $reg2 is given, this results in: | |
12323 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12324 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12325 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12326 | daddu $gp, $gp, $reg1 | |
12327 | $reg1 is normally $25 == $t9. */ | |
6478892d | 12328 | static void |
17a2f251 | 12329 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12330 | { |
12331 | expressionS ex_off; | |
12332 | expressionS ex_sym; | |
12333 | int reg1; | |
12334 | int icnt = 0; | |
f21f8242 | 12335 | char *f; |
6478892d | 12336 | |
8586fc66 | 12337 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12338 | We also need NewABI support. */ |
12339 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12340 | { | |
12341 | s_ignore (0); | |
12342 | return; | |
12343 | } | |
12344 | ||
12345 | reg1 = tc_get_register (0); | |
12346 | SKIP_WHITESPACE (); | |
12347 | if (*input_line_pointer != ',') | |
12348 | { | |
12349 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12350 | return; | |
12351 | } | |
12352 | else | |
80245285 | 12353 | ++input_line_pointer; |
6478892d TS |
12354 | SKIP_WHITESPACE (); |
12355 | if (*input_line_pointer == '$') | |
80245285 TS |
12356 | { |
12357 | mips_cpreturn_register = tc_get_register (0); | |
12358 | mips_cpreturn_offset = -1; | |
12359 | } | |
6478892d | 12360 | else |
80245285 TS |
12361 | { |
12362 | mips_cpreturn_offset = get_absolute_expression (); | |
12363 | mips_cpreturn_register = -1; | |
12364 | } | |
6478892d TS |
12365 | SKIP_WHITESPACE (); |
12366 | if (*input_line_pointer != ',') | |
12367 | { | |
12368 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12369 | return; | |
12370 | } | |
12371 | else | |
f9419b05 | 12372 | ++input_line_pointer; |
6478892d | 12373 | SKIP_WHITESPACE (); |
f21f8242 | 12374 | expression (&ex_sym); |
6478892d TS |
12375 | |
12376 | if (mips_cpreturn_register == -1) | |
12377 | { | |
12378 | ex_off.X_op = O_constant; | |
12379 | ex_off.X_add_symbol = NULL; | |
12380 | ex_off.X_op_symbol = NULL; | |
12381 | ex_off.X_add_number = mips_cpreturn_offset; | |
12382 | ||
17a2f251 TS |
12383 | macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register, |
12384 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12385 | } |
12386 | else | |
17a2f251 TS |
12387 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register, |
12388 | mips_gp_register, 0); | |
6478892d | 12389 | |
f21f8242 AO |
12390 | /* Ensure there's room for the next two instructions, so that `f' |
12391 | doesn't end up with an address in the wrong frag. */ | |
12392 | frag_grow (8); | |
12393 | f = frag_more (0); | |
17a2f251 TS |
12394 | macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12395 | BFD_RELOC_GPREL16); | |
f21f8242 | 12396 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12397 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12398 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12399 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12400 | |
12401 | f = frag_more (0); | |
17a2f251 TS |
12402 | macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register, |
12403 | mips_gp_register, BFD_RELOC_GPREL16); | |
f21f8242 | 12404 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12405 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12406 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12407 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12408 | |
17a2f251 TS |
12409 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
12410 | mips_gp_register, reg1); | |
6478892d TS |
12411 | |
12412 | demand_empty_rest_of_line (); | |
12413 | } | |
12414 | ||
12415 | static void | |
17a2f251 | 12416 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12417 | { |
12418 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12419 | .cplocal is ignored. */ | |
12420 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12421 | { | |
12422 | s_ignore (0); | |
12423 | return; | |
12424 | } | |
12425 | ||
12426 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12427 | demand_empty_rest_of_line (); |
6478892d TS |
12428 | } |
12429 | ||
252b5132 RH |
12430 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12431 | offset from $sp. The offset is remembered, and after making a PIC | |
12432 | call $gp is restored from that location. */ | |
12433 | ||
12434 | static void | |
17a2f251 | 12435 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12436 | { |
12437 | expressionS ex; | |
12438 | int icnt = 0; | |
12439 | ||
6478892d | 12440 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12441 | .cprestore is ignored. */ |
6478892d | 12442 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12443 | { |
12444 | s_ignore (0); | |
12445 | return; | |
12446 | } | |
12447 | ||
12448 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12449 | mips_cprestore_valid = 1; |
252b5132 RH |
12450 | |
12451 | ex.X_op = O_constant; | |
12452 | ex.X_add_symbol = NULL; | |
12453 | ex.X_op_symbol = NULL; | |
12454 | ex.X_add_number = mips_cprestore_offset; | |
12455 | ||
17a2f251 | 12456 | macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN, |
256ab948 | 12457 | mips_gp_register, SP, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
12458 | |
12459 | demand_empty_rest_of_line (); | |
12460 | } | |
12461 | ||
6478892d | 12462 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12463 | was given in the preceding .cpsetup, it results in: |
6478892d | 12464 | ld $gp, offset($sp) |
76b3015f | 12465 | |
6478892d | 12466 | If a register $reg2 was given there, it results in: |
609f23f4 | 12467 | daddu $gp, $reg2, $0 |
6478892d TS |
12468 | */ |
12469 | static void | |
17a2f251 | 12470 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12471 | { |
12472 | expressionS ex; | |
12473 | int icnt = 0; | |
12474 | ||
12475 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12476 | We also need NewABI support. */ | |
12477 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12478 | { | |
12479 | s_ignore (0); | |
12480 | return; | |
12481 | } | |
12482 | ||
12483 | if (mips_cpreturn_register == -1) | |
12484 | { | |
12485 | ex.X_op = O_constant; | |
12486 | ex.X_add_symbol = NULL; | |
12487 | ex.X_op_symbol = NULL; | |
12488 | ex.X_add_number = mips_cpreturn_offset; | |
12489 | ||
17a2f251 TS |
12490 | macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register, |
12491 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12492 | } |
12493 | else | |
17a2f251 TS |
12494 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register, |
12495 | mips_cpreturn_register, 0); | |
6478892d TS |
12496 | |
12497 | demand_empty_rest_of_line (); | |
12498 | } | |
12499 | ||
12500 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12501 | code. It sets the offset to use in gp_rel relocations. */ | |
12502 | ||
12503 | static void | |
17a2f251 | 12504 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12505 | { |
12506 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12507 | We also need NewABI support. */ | |
12508 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12509 | { | |
12510 | s_ignore (0); | |
12511 | return; | |
12512 | } | |
12513 | ||
def2e0dd | 12514 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12515 | |
12516 | demand_empty_rest_of_line (); | |
12517 | } | |
12518 | ||
252b5132 RH |
12519 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12520 | code. It generates a 32 bit GP relative reloc. */ | |
12521 | ||
12522 | static void | |
17a2f251 | 12523 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12524 | { |
12525 | symbolS *label; | |
12526 | expressionS ex; | |
12527 | char *p; | |
12528 | ||
12529 | /* When not generating PIC code, this is treated as .word. */ | |
12530 | if (mips_pic != SVR4_PIC) | |
12531 | { | |
12532 | s_cons (2); | |
12533 | return; | |
12534 | } | |
12535 | ||
12536 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12537 | mips_emit_delays (TRUE); |
252b5132 RH |
12538 | if (auto_align) |
12539 | mips_align (2, 0, label); | |
12540 | mips_clear_insn_labels (); | |
12541 | ||
12542 | expression (&ex); | |
12543 | ||
12544 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12545 | { | |
12546 | as_bad (_("Unsupported use of .gpword")); | |
12547 | ignore_rest_of_line (); | |
12548 | } | |
12549 | ||
12550 | p = frag_more (4); | |
17a2f251 | 12551 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12552 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12553 | BFD_RELOC_GPREL32); |
252b5132 RH |
12554 | |
12555 | demand_empty_rest_of_line (); | |
12556 | } | |
12557 | ||
10181a0d | 12558 | static void |
17a2f251 | 12559 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12560 | { |
12561 | symbolS *label; | |
12562 | expressionS ex; | |
12563 | char *p; | |
12564 | ||
12565 | /* When not generating PIC code, this is treated as .dword. */ | |
12566 | if (mips_pic != SVR4_PIC) | |
12567 | { | |
12568 | s_cons (3); | |
12569 | return; | |
12570 | } | |
12571 | ||
12572 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12573 | mips_emit_delays (TRUE); |
10181a0d AO |
12574 | if (auto_align) |
12575 | mips_align (3, 0, label); | |
12576 | mips_clear_insn_labels (); | |
12577 | ||
12578 | expression (&ex); | |
12579 | ||
12580 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12581 | { | |
12582 | as_bad (_("Unsupported use of .gpdword")); | |
12583 | ignore_rest_of_line (); | |
12584 | } | |
12585 | ||
12586 | p = frag_more (8); | |
17a2f251 | 12587 | md_number_to_chars (p, 0, 8); |
a105a300 | 12588 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12589 | BFD_RELOC_GPREL32); |
12590 | ||
12591 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12592 | ex.X_op = O_absent; | |
12593 | ex.X_add_symbol = 0; | |
12594 | ex.X_add_number = 0; | |
b34976b6 | 12595 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12596 | BFD_RELOC_64); |
12597 | ||
12598 | demand_empty_rest_of_line (); | |
12599 | } | |
12600 | ||
252b5132 RH |
12601 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12602 | tables in SVR4 PIC code. */ | |
12603 | ||
12604 | static void | |
17a2f251 | 12605 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12606 | { |
12607 | int icnt = 0; | |
12608 | int reg; | |
12609 | ||
10181a0d AO |
12610 | /* This is ignored when not generating SVR4 PIC code. */ |
12611 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12612 | { |
12613 | s_ignore (0); | |
12614 | return; | |
12615 | } | |
12616 | ||
12617 | /* Add $gp to the register named as an argument. */ | |
12618 | reg = tc_get_register (0); | |
17a2f251 TS |
12619 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
12620 | reg, reg, mips_gp_register); | |
252b5132 | 12621 | |
bdaaa2e1 | 12622 | demand_empty_rest_of_line (); |
252b5132 RH |
12623 | } |
12624 | ||
12625 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12626 | mips16 mode. This permits the linker to handle them specially, | |
12627 | such as generating jalx instructions when needed. We also make | |
12628 | them odd for the duration of the assembly, in order to generate the | |
12629 | right sort of code. We will make them even in the adjust_symtab | |
12630 | routine, while leaving them marked. This is convenient for the | |
12631 | debugger and the disassembler. The linker knows to make them odd | |
12632 | again. */ | |
12633 | ||
12634 | static void | |
17a2f251 | 12635 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12636 | { |
f9419b05 | 12637 | mips16_mark_labels (); |
252b5132 RH |
12638 | |
12639 | demand_empty_rest_of_line (); | |
12640 | } | |
12641 | ||
12642 | /* Handle a .stabn directive. We need these in order to mark a label | |
12643 | as being a mips16 text label correctly. Sometimes the compiler | |
12644 | will emit a label, followed by a .stabn, and then switch sections. | |
12645 | If the label and .stabn are in mips16 mode, then the label is | |
12646 | really a mips16 text label. */ | |
12647 | ||
12648 | static void | |
17a2f251 | 12649 | s_mips_stab (int type) |
252b5132 | 12650 | { |
f9419b05 | 12651 | if (type == 'n') |
252b5132 RH |
12652 | mips16_mark_labels (); |
12653 | ||
12654 | s_stab (type); | |
12655 | } | |
12656 | ||
12657 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12658 | */ | |
12659 | ||
12660 | static void | |
17a2f251 | 12661 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12662 | { |
12663 | char *name; | |
12664 | int c; | |
12665 | symbolS *symbolP; | |
12666 | expressionS exp; | |
12667 | ||
12668 | name = input_line_pointer; | |
12669 | c = get_symbol_end (); | |
12670 | symbolP = symbol_find_or_make (name); | |
12671 | S_SET_WEAK (symbolP); | |
12672 | *input_line_pointer = c; | |
12673 | ||
12674 | SKIP_WHITESPACE (); | |
12675 | ||
12676 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12677 | { | |
12678 | if (S_IS_DEFINED (symbolP)) | |
12679 | { | |
956cd1d6 | 12680 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12681 | S_GET_NAME (symbolP)); |
12682 | ignore_rest_of_line (); | |
12683 | return; | |
12684 | } | |
bdaaa2e1 | 12685 | |
252b5132 RH |
12686 | if (*input_line_pointer == ',') |
12687 | { | |
12688 | ++input_line_pointer; | |
12689 | SKIP_WHITESPACE (); | |
12690 | } | |
bdaaa2e1 | 12691 | |
252b5132 RH |
12692 | expression (&exp); |
12693 | if (exp.X_op != O_symbol) | |
12694 | { | |
12695 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12696 | ignore_rest_of_line (); |
252b5132 RH |
12697 | return; |
12698 | } | |
49309057 | 12699 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12700 | } |
12701 | ||
12702 | demand_empty_rest_of_line (); | |
12703 | } | |
12704 | ||
12705 | /* Parse a register string into a number. Called from the ECOFF code | |
12706 | to parse .frame. The argument is non-zero if this is the frame | |
12707 | register, so that we can record it in mips_frame_reg. */ | |
12708 | ||
12709 | int | |
17a2f251 | 12710 | tc_get_register (int frame) |
252b5132 RH |
12711 | { |
12712 | int reg; | |
12713 | ||
12714 | SKIP_WHITESPACE (); | |
12715 | if (*input_line_pointer++ != '$') | |
12716 | { | |
12717 | as_warn (_("expected `$'")); | |
85b51719 | 12718 | reg = ZERO; |
252b5132 | 12719 | } |
3882b010 | 12720 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12721 | { |
12722 | reg = get_absolute_expression (); | |
12723 | if (reg < 0 || reg >= 32) | |
12724 | { | |
12725 | as_warn (_("Bad register number")); | |
85b51719 | 12726 | reg = ZERO; |
252b5132 RH |
12727 | } |
12728 | } | |
12729 | else | |
12730 | { | |
76db943d | 12731 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12732 | { |
12733 | reg = RA; | |
12734 | input_line_pointer += 2; | |
12735 | } | |
76db943d | 12736 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12737 | { |
12738 | reg = FP; | |
12739 | input_line_pointer += 2; | |
12740 | } | |
252b5132 | 12741 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12742 | { |
12743 | reg = SP; | |
12744 | input_line_pointer += 2; | |
12745 | } | |
252b5132 | 12746 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12747 | { |
12748 | reg = GP; | |
12749 | input_line_pointer += 2; | |
12750 | } | |
252b5132 | 12751 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12752 | { |
12753 | reg = AT; | |
12754 | input_line_pointer += 2; | |
12755 | } | |
12756 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12757 | { | |
12758 | reg = KT0; | |
12759 | input_line_pointer += 3; | |
12760 | } | |
12761 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12762 | { | |
12763 | reg = KT1; | |
12764 | input_line_pointer += 3; | |
12765 | } | |
12766 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12767 | { | |
12768 | reg = ZERO; | |
12769 | input_line_pointer += 4; | |
12770 | } | |
252b5132 RH |
12771 | else |
12772 | { | |
12773 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12774 | reg = ZERO; |
12775 | while (ISALNUM(*input_line_pointer)) | |
12776 | input_line_pointer++; | |
252b5132 | 12777 | } |
252b5132 RH |
12778 | } |
12779 | if (frame) | |
7a621144 DJ |
12780 | { |
12781 | mips_frame_reg = reg != 0 ? reg : SP; | |
12782 | mips_frame_reg_valid = 1; | |
12783 | mips_cprestore_valid = 0; | |
12784 | } | |
252b5132 RH |
12785 | return reg; |
12786 | } | |
12787 | ||
12788 | valueT | |
17a2f251 | 12789 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12790 | { |
12791 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12792 | ||
12793 | #ifdef OBJ_ELF | |
12794 | /* We don't need to align ELF sections to the full alignment. | |
12795 | However, Irix 5 may prefer that we align them at least to a 16 | |
12796 | byte boundary. We don't bother to align the sections if we are | |
12797 | targeted for an embedded system. */ | |
12798 | if (strcmp (TARGET_OS, "elf") == 0) | |
12799 | return addr; | |
12800 | if (align > 4) | |
12801 | align = 4; | |
12802 | #endif | |
12803 | ||
12804 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12805 | } | |
12806 | ||
12807 | /* Utility routine, called from above as well. If called while the | |
12808 | input file is still being read, it's only an approximation. (For | |
12809 | example, a symbol may later become defined which appeared to be | |
12810 | undefined earlier.) */ | |
12811 | ||
12812 | static int | |
17a2f251 | 12813 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12814 | { |
12815 | if (sym == 0) | |
12816 | return 0; | |
12817 | ||
6478892d | 12818 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12819 | { |
12820 | const char *symname; | |
12821 | int change; | |
12822 | ||
c9914766 | 12823 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12824 | register. It can be if it is smaller than the -G size or if |
12825 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12826 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12827 | they can. */ |
12828 | symname = S_GET_NAME (sym); | |
12829 | if (symname != (const char *) NULL | |
12830 | && (strcmp (symname, "eprol") == 0 | |
12831 | || strcmp (symname, "etext") == 0 | |
12832 | || strcmp (symname, "_gp") == 0 | |
12833 | || strcmp (symname, "edata") == 0 | |
12834 | || strcmp (symname, "_fbss") == 0 | |
12835 | || strcmp (symname, "_fdata") == 0 | |
12836 | || strcmp (symname, "_ftext") == 0 | |
12837 | || strcmp (symname, "end") == 0 | |
12838 | || strcmp (symname, "_gp_disp") == 0)) | |
12839 | change = 1; | |
12840 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12841 | && (0 | |
12842 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12843 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12844 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12845 | <= g_switch_value)) | |
252b5132 RH |
12846 | #endif |
12847 | /* We must defer this decision until after the whole | |
12848 | file has been read, since there might be a .extern | |
12849 | after the first use of this symbol. */ | |
12850 | || (before_relaxing | |
12851 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12852 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12853 | #endif |
12854 | && S_GET_VALUE (sym) == 0) | |
12855 | || (S_GET_VALUE (sym) != 0 | |
12856 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12857 | change = 0; | |
12858 | else | |
12859 | { | |
12860 | const char *segname; | |
12861 | ||
12862 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12863 | assert (strcmp (segname, ".lit8") != 0 | |
12864 | && strcmp (segname, ".lit4") != 0); | |
12865 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12866 | && strcmp (segname, ".sbss") != 0 |
12867 | && strncmp (segname, ".sdata.", 7) != 0 | |
12868 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12869 | } |
12870 | return change; | |
12871 | } | |
12872 | else | |
c9914766 | 12873 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12874 | return 1; |
12875 | } | |
12876 | ||
5919d012 RS |
12877 | |
12878 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12879 | ||
12880 | static bfd_boolean | |
17a2f251 | 12881 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12882 | { |
12883 | asection *symsec; | |
12884 | bfd_boolean linkonce; | |
12885 | ||
12886 | /* Handle the case of a symbol equated to another symbol. */ | |
12887 | while (symbol_equated_reloc_p (sym)) | |
12888 | { | |
12889 | symbolS *n; | |
12890 | ||
12891 | /* It's possible to get a loop here in a badly written | |
12892 | program. */ | |
12893 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12894 | if (n == sym) | |
12895 | break; | |
12896 | sym = n; | |
12897 | } | |
12898 | ||
12899 | symsec = S_GET_SEGMENT (sym); | |
12900 | ||
12901 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12902 | linkonce = FALSE; | |
12903 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12904 | { | |
12905 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12906 | != 0) | |
12907 | linkonce = TRUE; | |
12908 | ||
12909 | /* The GNU toolchain uses an extension for ELF: a section | |
12910 | beginning with the magic string .gnu.linkonce is a linkonce | |
12911 | section. */ | |
12912 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12913 | sizeof ".gnu.linkonce" - 1) == 0) | |
12914 | linkonce = TRUE; | |
12915 | } | |
12916 | ||
12917 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12918 | return (symsec != &bfd_und_section | |
12919 | && symsec != &bfd_abs_section | |
12920 | && ! bfd_is_com_section (symsec) | |
12921 | && !linkonce | |
12922 | #ifdef OBJ_ELF | |
12923 | /* A global or weak symbol is treated as external. */ | |
12924 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12925 | || (! S_IS_WEAK (sym) | |
12926 | && (! S_IS_EXTERNAL (sym) | |
12927 | || mips_pic == EMBEDDED_PIC))) | |
12928 | #endif | |
12929 | ); | |
12930 | } | |
12931 | ||
12932 | ||
252b5132 RH |
12933 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12934 | extended opcode. SEC is the section the frag is in. */ | |
12935 | ||
12936 | static int | |
17a2f251 | 12937 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12938 | { |
12939 | int type; | |
12940 | register const struct mips16_immed_operand *op; | |
12941 | offsetT val; | |
12942 | int mintiny, maxtiny; | |
12943 | segT symsec; | |
98aa84af | 12944 | fragS *sym_frag; |
252b5132 RH |
12945 | |
12946 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12947 | return 0; | |
12948 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12949 | return 1; | |
12950 | ||
12951 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12952 | op = mips16_immed_operands; | |
12953 | while (op->type != type) | |
12954 | { | |
12955 | ++op; | |
12956 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12957 | } | |
12958 | ||
12959 | if (op->unsp) | |
12960 | { | |
12961 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12962 | { | |
12963 | mintiny = 1; | |
12964 | maxtiny = 1 << op->nbits; | |
12965 | } | |
12966 | else | |
12967 | { | |
12968 | mintiny = 0; | |
12969 | maxtiny = (1 << op->nbits) - 1; | |
12970 | } | |
12971 | } | |
12972 | else | |
12973 | { | |
12974 | mintiny = - (1 << (op->nbits - 1)); | |
12975 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12976 | } | |
12977 | ||
98aa84af | 12978 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12979 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12980 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12981 | |
12982 | if (op->pcrel) | |
12983 | { | |
12984 | addressT addr; | |
12985 | ||
12986 | /* We won't have the section when we are called from | |
12987 | mips_relax_frag. However, we will always have been called | |
12988 | from md_estimate_size_before_relax first. If this is a | |
12989 | branch to a different section, we mark it as such. If SEC is | |
12990 | NULL, and the frag is not marked, then it must be a branch to | |
12991 | the same section. */ | |
12992 | if (sec == NULL) | |
12993 | { | |
12994 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12995 | return 1; | |
12996 | } | |
12997 | else | |
12998 | { | |
98aa84af | 12999 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13000 | if (symsec != sec) |
13001 | { | |
13002 | fragp->fr_subtype = | |
13003 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13004 | ||
13005 | /* FIXME: We should support this, and let the linker | |
13006 | catch branches and loads that are out of range. */ | |
13007 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13008 | _("unsupported PC relative reference to different section")); | |
13009 | ||
13010 | return 1; | |
13011 | } | |
98aa84af AM |
13012 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13013 | /* Assume non-extended on the first relaxation pass. | |
13014 | The address we have calculated will be bogus if this is | |
13015 | a forward branch to another frag, as the forward frag | |
13016 | will have fr_address == 0. */ | |
13017 | return 0; | |
252b5132 RH |
13018 | } |
13019 | ||
13020 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13021 | the same section. If the relax_marker of the symbol fragment |
13022 | differs from the relax_marker of this fragment, we have not | |
13023 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13024 | in STRETCH in order to get a better estimate of the address. |
13025 | This particularly matters because of the shift bits. */ | |
13026 | if (stretch != 0 | |
98aa84af | 13027 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13028 | { |
13029 | fragS *f; | |
13030 | ||
13031 | /* Adjust stretch for any alignment frag. Note that if have | |
13032 | been expanding the earlier code, the symbol may be | |
13033 | defined in what appears to be an earlier frag. FIXME: | |
13034 | This doesn't handle the fr_subtype field, which specifies | |
13035 | a maximum number of bytes to skip when doing an | |
13036 | alignment. */ | |
98aa84af | 13037 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13038 | { |
13039 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13040 | { | |
13041 | if (stretch < 0) | |
13042 | stretch = - ((- stretch) | |
13043 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13044 | else | |
13045 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13046 | if (stretch == 0) | |
13047 | break; | |
13048 | } | |
13049 | } | |
13050 | if (f != NULL) | |
13051 | val += stretch; | |
13052 | } | |
13053 | ||
13054 | addr = fragp->fr_address + fragp->fr_fix; | |
13055 | ||
13056 | /* The base address rules are complicated. The base address of | |
13057 | a branch is the following instruction. The base address of a | |
13058 | PC relative load or add is the instruction itself, but if it | |
13059 | is in a delay slot (in which case it can not be extended) use | |
13060 | the address of the instruction whose delay slot it is in. */ | |
13061 | if (type == 'p' || type == 'q') | |
13062 | { | |
13063 | addr += 2; | |
13064 | ||
13065 | /* If we are currently assuming that this frag should be | |
13066 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13067 | higher. */ |
252b5132 RH |
13068 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13069 | addr += 2; | |
13070 | ||
13071 | /* Ignore the low bit in the target, since it will be set | |
13072 | for a text label. */ | |
13073 | if ((val & 1) != 0) | |
13074 | --val; | |
13075 | } | |
13076 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13077 | addr -= 4; | |
13078 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13079 | addr -= 2; | |
13080 | ||
13081 | val -= addr & ~ ((1 << op->shift) - 1); | |
13082 | ||
13083 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13084 | if (type == 'p' || type == 'q') | |
13085 | val /= 2; | |
13086 | ||
13087 | /* If any of the shifted bits are set, we must use an extended | |
13088 | opcode. If the address depends on the size of this | |
13089 | instruction, this can lead to a loop, so we arrange to always | |
13090 | use an extended opcode. We only check this when we are in | |
13091 | the main relaxation loop, when SEC is NULL. */ | |
13092 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13093 | { | |
13094 | fragp->fr_subtype = | |
13095 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13096 | return 1; | |
13097 | } | |
13098 | ||
13099 | /* If we are about to mark a frag as extended because the value | |
13100 | is precisely maxtiny + 1, then there is a chance of an | |
13101 | infinite loop as in the following code: | |
13102 | la $4,foo | |
13103 | .skip 1020 | |
13104 | .align 2 | |
13105 | foo: | |
13106 | In this case when the la is extended, foo is 0x3fc bytes | |
13107 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13108 | the la must be extended. To avoid this loop, we mark the | |
13109 | frag as extended if it was small, and is about to become | |
13110 | extended with a value of maxtiny + 1. */ | |
13111 | if (val == ((maxtiny + 1) << op->shift) | |
13112 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13113 | && sec == NULL) | |
13114 | { | |
13115 | fragp->fr_subtype = | |
13116 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13117 | return 1; | |
13118 | } | |
13119 | } | |
13120 | else if (symsec != absolute_section && sec != NULL) | |
13121 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13122 | ||
13123 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13124 | || val < (mintiny << op->shift) | |
13125 | || val > (maxtiny << op->shift)) | |
13126 | return 1; | |
13127 | else | |
13128 | return 0; | |
13129 | } | |
13130 | ||
4a6a3df4 AO |
13131 | /* Compute the length of a branch sequence, and adjust the |
13132 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13133 | worst-case length is computed, with UPDATE being used to indicate | |
13134 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13135 | branch is to be computed. */ | |
13136 | static int | |
17a2f251 | 13137 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13138 | { |
b34976b6 | 13139 | bfd_boolean toofar; |
4a6a3df4 AO |
13140 | int length; |
13141 | ||
13142 | if (fragp | |
13143 | && S_IS_DEFINED (fragp->fr_symbol) | |
13144 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13145 | { | |
13146 | addressT addr; | |
13147 | offsetT val; | |
13148 | ||
13149 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13150 | ||
13151 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13152 | ||
13153 | val -= addr; | |
13154 | ||
13155 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13156 | } | |
13157 | else if (fragp) | |
13158 | /* If the symbol is not defined or it's in a different segment, | |
13159 | assume the user knows what's going on and emit a short | |
13160 | branch. */ | |
b34976b6 | 13161 | toofar = FALSE; |
4a6a3df4 | 13162 | else |
b34976b6 | 13163 | toofar = TRUE; |
4a6a3df4 AO |
13164 | |
13165 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13166 | fragp->fr_subtype | |
af6ae2ad | 13167 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13168 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13169 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13170 | toofar); | |
13171 | ||
13172 | length = 4; | |
13173 | if (toofar) | |
13174 | { | |
13175 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13176 | length += 8; | |
13177 | ||
13178 | if (mips_pic != NO_PIC) | |
13179 | { | |
13180 | /* Additional space for PIC loading of target address. */ | |
13181 | length += 8; | |
13182 | if (mips_opts.isa == ISA_MIPS1) | |
13183 | /* Additional space for $at-stabilizing nop. */ | |
13184 | length += 4; | |
13185 | } | |
13186 | ||
13187 | /* If branch is conditional. */ | |
13188 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13189 | length += 8; | |
13190 | } | |
b34976b6 | 13191 | |
4a6a3df4 AO |
13192 | return length; |
13193 | } | |
13194 | ||
252b5132 RH |
13195 | /* Estimate the size of a frag before relaxing. Unless this is the |
13196 | mips16, we are not really relaxing here, and the final size is | |
13197 | encoded in the subtype information. For the mips16, we have to | |
13198 | decide whether we are using an extended opcode or not. */ | |
13199 | ||
252b5132 | 13200 | int |
17a2f251 | 13201 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13202 | { |
5919d012 | 13203 | int change; |
252b5132 | 13204 | |
4a6a3df4 AO |
13205 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13206 | { | |
13207 | ||
b34976b6 AM |
13208 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13209 | ||
4a6a3df4 AO |
13210 | return fragp->fr_var; |
13211 | } | |
13212 | ||
252b5132 | 13213 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13214 | /* We don't want to modify the EXTENDED bit here; it might get us |
13215 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13216 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13217 | |
13218 | if (mips_pic == NO_PIC) | |
5919d012 | 13219 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13220 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13221 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13222 | else |
13223 | abort (); | |
13224 | ||
13225 | if (change) | |
13226 | { | |
13227 | /* Record the offset to the first reloc in the fr_opcode field. | |
13228 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13229 | must be expanded. */ | |
13230 | fragp->fr_opcode = (fragp->fr_literal | |
13231 | + fragp->fr_fix | |
13232 | - RELAX_OLD (fragp->fr_subtype) | |
13233 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13234 | /* FIXME: This really needs as_warn_where. */ | |
13235 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13236 | as_warn (_("AT used after \".set noat\" or macro used after " |
13237 | "\".set nomacro\"")); | |
13238 | ||
13239 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13240 | } |
13241 | ||
9a41af64 | 13242 | return 0; |
252b5132 RH |
13243 | } |
13244 | ||
13245 | /* This is called to see whether a reloc against a defined symbol | |
13246 | should be converted into a reloc against a section. Don't adjust | |
13247 | MIPS16 jump relocations, so we don't have to worry about the format | |
13248 | of the offset in the .o file. Don't adjust relocations against | |
13249 | mips16 symbols, so that the linker can find them if it needs to set | |
13250 | up a stub. */ | |
13251 | ||
13252 | int | |
17a2f251 | 13253 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
13254 | { |
13255 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13256 | return 0; | |
a161fe53 | 13257 | |
252b5132 RH |
13258 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13259 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13260 | return 0; | |
a161fe53 | 13261 | |
252b5132 RH |
13262 | if (fixp->fx_addsy == NULL) |
13263 | return 1; | |
a161fe53 | 13264 | |
252b5132 RH |
13265 | #ifdef OBJ_ELF |
13266 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13267 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13268 | && fixp->fx_subsy == NULL) | |
13269 | return 0; | |
13270 | #endif | |
a161fe53 | 13271 | |
252b5132 RH |
13272 | return 1; |
13273 | } | |
13274 | ||
13275 | /* Translate internal representation of relocation info to BFD target | |
13276 | format. */ | |
13277 | ||
13278 | arelent ** | |
17a2f251 | 13279 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13280 | { |
13281 | static arelent *retval[4]; | |
13282 | arelent *reloc; | |
13283 | bfd_reloc_code_real_type code; | |
13284 | ||
4b0cff4e TS |
13285 | memset (retval, 0, sizeof(retval)); |
13286 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13287 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13288 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13289 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13290 | ||
13291 | if (mips_pic == EMBEDDED_PIC | |
13292 | && SWITCH_TABLE (fixp)) | |
13293 | { | |
13294 | /* For a switch table entry we use a special reloc. The addend | |
13295 | is actually the difference between the reloc address and the | |
13296 | subtrahend. */ | |
13297 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13298 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13299 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13300 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13301 | } | |
30ac9238 | 13302 | else if (fixp->fx_pcrel) |
252b5132 | 13303 | { |
30ac9238 RS |
13304 | bfd_vma pcrel_address; |
13305 | ||
13306 | /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high | |
13307 | high-part relocs is the address of the low-part reloc. */ | |
13308 | if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13309 | { | |
13310 | assert (fixp->fx_next != NULL | |
13311 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
13312 | pcrel_address = (fixp->fx_next->fx_where | |
13313 | + fixp->fx_next->fx_frag->fr_address); | |
13314 | } | |
252b5132 | 13315 | else |
30ac9238 RS |
13316 | pcrel_address = reloc->address; |
13317 | ||
13318 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13319 | { | |
13320 | /* At this point, fx_addnumber is "symbol offset - pcrel_address". | |
13321 | Relocations want only the symbol offset. */ | |
13322 | reloc->addend = fixp->fx_addnumber + pcrel_address; | |
13323 | } | |
13324 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 | |
13325 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
4514d474 | 13326 | { |
30ac9238 | 13327 | /* We use a special addend for an internal RELLO or RELHI reloc. */ |
4514d474 | 13328 | if (symbol_section_p (fixp->fx_addsy)) |
30ac9238 | 13329 | reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); |
4514d474 | 13330 | else |
30ac9238 | 13331 | reloc->addend = fixp->fx_addnumber + pcrel_address; |
4514d474 | 13332 | } |
252b5132 | 13333 | else |
4514d474 | 13334 | { |
30ac9238 RS |
13335 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
13336 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13337 | handling. */ | |
13338 | reloc->addend = pcrel_address; | |
4514d474 | 13339 | else |
30ac9238 | 13340 | reloc->addend = -pcrel_address; |
4514d474 | 13341 | } |
252b5132 | 13342 | } |
252b5132 | 13343 | else |
30ac9238 | 13344 | reloc->addend = fixp->fx_addnumber; |
252b5132 RH |
13345 | |
13346 | /* If this is a variant frag, we may need to adjust the existing | |
13347 | reloc and generate a new one. */ | |
13348 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13349 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13350 | && ! HAVE_NEWABI) | |
f5040a92 AO |
13351 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP |
13352 | && HAVE_NEWABI) | |
252b5132 RH |
13353 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13354 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13355 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13356 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13357 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13358 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13359 | ) |
252b5132 RH |
13360 | { |
13361 | arelent *reloc2; | |
13362 | ||
13363 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13364 | ||
13365 | /* If this is not the last reloc in this frag, then we have two | |
13366 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13367 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13368 | the second one handle all of them. */ | |
13369 | if (fixp->fx_next != NULL | |
13370 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13371 | { | |
cdf6fd85 TS |
13372 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13373 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13374 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13375 | && (fixp->fx_next->fx_r_type | |
13376 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13377 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13378 | && (fixp->fx_next->fx_r_type | |
13379 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13380 | retval[0] = NULL; | |
13381 | return retval; | |
13382 | } | |
13383 | ||
13384 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13385 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
f5040a92 | 13386 | reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 | 13387 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
49309057 ILT |
13388 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13389 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13390 | reloc2->address = (reloc->address |
13391 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13392 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
30ac9238 | 13393 | reloc2->addend = reloc->addend; |
252b5132 RH |
13394 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
13395 | assert (reloc2->howto != NULL); | |
13396 | ||
13397 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13398 | { | |
13399 | arelent *reloc3; | |
13400 | ||
13401 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
252b5132 RH |
13402 | *reloc3 = *reloc2; |
13403 | reloc3->address += 4; | |
13404 | } | |
13405 | ||
13406 | if (mips_pic == NO_PIC) | |
13407 | { | |
cdf6fd85 | 13408 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13409 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13410 | } | |
13411 | else if (mips_pic == SVR4_PIC) | |
13412 | { | |
13413 | switch (fixp->fx_r_type) | |
13414 | { | |
13415 | default: | |
13416 | abort (); | |
13417 | case BFD_RELOC_MIPS_GOT16: | |
13418 | break; | |
252b5132 RH |
13419 | case BFD_RELOC_MIPS_GOT_LO16: |
13420 | case BFD_RELOC_MIPS_CALL_LO16: | |
ed6fb7bd SC |
13421 | if (HAVE_NEWABI) |
13422 | { | |
ed6fb7bd SC |
13423 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; |
13424 | reloc2->howto = bfd_reloc_type_lookup | |
13425 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13426 | } | |
13427 | else | |
13428 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13429 | break; | |
f5040a92 AO |
13430 | case BFD_RELOC_MIPS_CALL16: |
13431 | case BFD_RELOC_MIPS_GOT_OFST: | |
13432 | case BFD_RELOC_MIPS_GOT_DISP: | |
13433 | if (HAVE_NEWABI) | |
13434 | { | |
13435 | /* It may seem nonsensical to relax GOT_DISP to | |
13436 | GOT_DISP, but we're actually turning a GOT_DISP | |
13437 | without offset into a GOT_DISP with an offset, | |
13438 | getting rid of the separate addition, which we can | |
13439 | do when the symbol is found to be local. */ | |
13440 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13441 | retval[1] = NULL; | |
13442 | } | |
13443 | else | |
13444 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13445 | break; | |
252b5132 RH |
13446 | } |
13447 | } | |
13448 | else | |
13449 | abort (); | |
13450 | } | |
13451 | ||
438c16b8 TS |
13452 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13453 | entry to be used in the relocation's section offset. */ | |
13454 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13455 | { |
13456 | reloc->address = reloc->addend; | |
13457 | reloc->addend = 0; | |
13458 | } | |
13459 | ||
13460 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13461 | fixup_segment converted a non-PC relative reloc into a PC | |
13462 | relative reloc. In such a case, we need to convert the reloc | |
13463 | code. */ | |
13464 | code = fixp->fx_r_type; | |
13465 | if (fixp->fx_pcrel) | |
13466 | { | |
13467 | switch (code) | |
13468 | { | |
13469 | case BFD_RELOC_8: | |
13470 | code = BFD_RELOC_8_PCREL; | |
13471 | break; | |
13472 | case BFD_RELOC_16: | |
13473 | code = BFD_RELOC_16_PCREL; | |
13474 | break; | |
13475 | case BFD_RELOC_32: | |
13476 | code = BFD_RELOC_32_PCREL; | |
13477 | break; | |
13478 | case BFD_RELOC_64: | |
13479 | code = BFD_RELOC_64_PCREL; | |
13480 | break; | |
13481 | case BFD_RELOC_8_PCREL: | |
13482 | case BFD_RELOC_16_PCREL: | |
13483 | case BFD_RELOC_32_PCREL: | |
13484 | case BFD_RELOC_64_PCREL: | |
13485 | case BFD_RELOC_16_PCREL_S2: | |
13486 | case BFD_RELOC_PCREL_HI16_S: | |
13487 | case BFD_RELOC_PCREL_LO16: | |
13488 | break; | |
13489 | default: | |
13490 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13491 | _("Cannot make %s relocation PC relative"), | |
13492 | bfd_get_reloc_code_name (code)); | |
13493 | } | |
13494 | } | |
13495 | ||
0b25d3e6 AO |
13496 | /* To support a PC relative reloc when generating embedded PIC code |
13497 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13498 | make sure that we don't let such a reloc escape normally. */ | |
13499 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13500 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13501 | && code == BFD_RELOC_16_PCREL_S2 | |
13502 | && mips_pic != EMBEDDED_PIC) | |
13503 | reloc->howto = NULL; | |
13504 | else | |
13505 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13506 | ||
252b5132 RH |
13507 | if (reloc->howto == NULL) |
13508 | { | |
13509 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13510 | _("Can not represent %s relocation in this object file format"), | |
13511 | bfd_get_reloc_code_name (code)); | |
13512 | retval[0] = NULL; | |
13513 | } | |
13514 | ||
13515 | return retval; | |
13516 | } | |
13517 | ||
13518 | /* Relax a machine dependent frag. This returns the amount by which | |
13519 | the current size of the frag should change. */ | |
13520 | ||
13521 | int | |
17a2f251 | 13522 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13523 | { |
4a6a3df4 AO |
13524 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13525 | { | |
13526 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13527 | |
13528 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13529 | |
13530 | return fragp->fr_var - old_var; | |
13531 | } | |
13532 | ||
252b5132 RH |
13533 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13534 | return 0; | |
13535 | ||
c4e7957c | 13536 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13537 | { |
13538 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13539 | return 0; | |
13540 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13541 | return 2; | |
13542 | } | |
13543 | else | |
13544 | { | |
13545 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13546 | return 0; | |
13547 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13548 | return -2; | |
13549 | } | |
13550 | ||
13551 | return 0; | |
13552 | } | |
13553 | ||
13554 | /* Convert a machine dependent frag. */ | |
13555 | ||
13556 | void | |
17a2f251 | 13557 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 RH |
13558 | { |
13559 | int old, new; | |
13560 | char *fixptr; | |
13561 | ||
4a6a3df4 AO |
13562 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13563 | { | |
13564 | bfd_byte *buf; | |
13565 | unsigned long insn; | |
13566 | expressionS exp; | |
13567 | fixS *fixp; | |
b34976b6 | 13568 | |
4a6a3df4 AO |
13569 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13570 | ||
13571 | if (target_big_endian) | |
13572 | insn = bfd_getb32 (buf); | |
13573 | else | |
13574 | insn = bfd_getl32 (buf); | |
b34976b6 | 13575 | |
4a6a3df4 AO |
13576 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13577 | { | |
13578 | /* We generate a fixup instead of applying it right now | |
13579 | because, if there are linker relaxations, we're going to | |
13580 | need the relocations. */ | |
13581 | exp.X_op = O_symbol; | |
13582 | exp.X_add_symbol = fragp->fr_symbol; | |
13583 | exp.X_add_number = fragp->fr_offset; | |
13584 | ||
13585 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13586 | 4, &exp, 1, |
13587 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13588 | fixp->fx_file = fragp->fr_file; |
13589 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13590 | |
17a2f251 | 13591 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13592 | buf += 4; |
13593 | } | |
13594 | else | |
13595 | { | |
13596 | int i; | |
13597 | ||
13598 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13599 | _("relaxed out-of-range branch into a jump")); | |
13600 | ||
13601 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13602 | goto uncond; | |
13603 | ||
13604 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13605 | { | |
13606 | /* Reverse the branch. */ | |
13607 | switch ((insn >> 28) & 0xf) | |
13608 | { | |
13609 | case 4: | |
13610 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13611 | have the condition reversed by tweaking a single | |
13612 | bit, and their opcodes all have 0x4???????. */ | |
13613 | assert ((insn & 0xf1000000) == 0x41000000); | |
13614 | insn ^= 0x00010000; | |
13615 | break; | |
13616 | ||
13617 | case 0: | |
13618 | /* bltz 0x04000000 bgez 0x04010000 | |
13619 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13620 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13621 | insn ^= 0x00010000; | |
13622 | break; | |
b34976b6 | 13623 | |
4a6a3df4 AO |
13624 | case 1: |
13625 | /* beq 0x10000000 bne 0x14000000 | |
13626 | blez 0x18000000 bgtz 0x1c000000 */ | |
13627 | insn ^= 0x04000000; | |
13628 | break; | |
13629 | ||
13630 | default: | |
13631 | abort (); | |
13632 | } | |
13633 | } | |
13634 | ||
13635 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13636 | { | |
13637 | /* Clear the and-link bit. */ | |
13638 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13639 | ||
13640 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13641 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13642 | insn &= ~0x00100000; | |
13643 | } | |
13644 | ||
13645 | /* Branch over the branch (if the branch was likely) or the | |
13646 | full jump (not likely case). Compute the offset from the | |
13647 | current instruction to branch to. */ | |
13648 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13649 | i = 16; | |
13650 | else | |
13651 | { | |
13652 | /* How many bytes in instructions we've already emitted? */ | |
13653 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13654 | /* How many bytes in instructions from here to the end? */ | |
13655 | i = fragp->fr_var - i; | |
13656 | } | |
13657 | /* Convert to instruction count. */ | |
13658 | i >>= 2; | |
13659 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13660 | i--; |
4a6a3df4 AO |
13661 | insn |= i; |
13662 | /* Branch over the jump. */ | |
17a2f251 | 13663 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13664 | buf += 4; |
13665 | ||
13666 | /* Nop */ | |
17a2f251 | 13667 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13668 | buf += 4; |
13669 | ||
13670 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13671 | { | |
13672 | /* beql $0, $0, 2f */ | |
13673 | insn = 0x50000000; | |
13674 | /* Compute the PC offset from the current instruction to | |
13675 | the end of the variable frag. */ | |
13676 | /* How many bytes in instructions we've already emitted? */ | |
13677 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13678 | /* How many bytes in instructions from here to the end? */ | |
13679 | i = fragp->fr_var - i; | |
13680 | /* Convert to instruction count. */ | |
13681 | i >>= 2; | |
13682 | /* Don't decrement i, because we want to branch over the | |
13683 | delay slot. */ | |
13684 | ||
13685 | insn |= i; | |
17a2f251 | 13686 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13687 | buf += 4; |
13688 | ||
17a2f251 | 13689 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13690 | buf += 4; |
13691 | } | |
13692 | ||
13693 | uncond: | |
13694 | if (mips_pic == NO_PIC) | |
13695 | { | |
13696 | /* j or jal. */ | |
13697 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13698 | ? 0x0c000000 : 0x08000000); | |
13699 | exp.X_op = O_symbol; | |
13700 | exp.X_add_symbol = fragp->fr_symbol; | |
13701 | exp.X_add_number = fragp->fr_offset; | |
13702 | ||
13703 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13704 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13705 | fixp->fx_file = fragp->fr_file; | |
13706 | fixp->fx_line = fragp->fr_line; | |
13707 | ||
17a2f251 | 13708 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13709 | buf += 4; |
13710 | } | |
13711 | else | |
13712 | { | |
13713 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13714 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13715 | exp.X_op = O_symbol; | |
13716 | exp.X_add_symbol = fragp->fr_symbol; | |
13717 | exp.X_add_number = fragp->fr_offset; | |
13718 | ||
13719 | if (fragp->fr_offset) | |
13720 | { | |
13721 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13722 | exp.X_add_number = 0; | |
13723 | } | |
13724 | ||
13725 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13726 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13727 | fixp->fx_file = fragp->fr_file; | |
13728 | fixp->fx_line = fragp->fr_line; | |
13729 | ||
17a2f251 | 13730 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13731 | buf += 4; |
b34976b6 | 13732 | |
4a6a3df4 AO |
13733 | if (mips_opts.isa == ISA_MIPS1) |
13734 | { | |
13735 | /* nop */ | |
17a2f251 | 13736 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13737 | buf += 4; |
13738 | } | |
13739 | ||
13740 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13741 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13742 | ||
13743 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13744 | 4, &exp, 0, BFD_RELOC_LO16); | |
13745 | fixp->fx_file = fragp->fr_file; | |
13746 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13747 | |
17a2f251 | 13748 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13749 | buf += 4; |
13750 | ||
13751 | /* j(al)r $at. */ | |
13752 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13753 | insn = 0x0020f809; | |
13754 | else | |
13755 | insn = 0x00200008; | |
13756 | ||
17a2f251 | 13757 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13758 | buf += 4; |
13759 | } | |
13760 | } | |
13761 | ||
13762 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13763 | + fragp->fr_fix + fragp->fr_var); | |
13764 | ||
13765 | fragp->fr_fix += fragp->fr_var; | |
13766 | ||
13767 | return; | |
13768 | } | |
13769 | ||
252b5132 RH |
13770 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13771 | { | |
13772 | int type; | |
13773 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13774 | bfd_boolean small, ext; |
252b5132 RH |
13775 | offsetT val; |
13776 | bfd_byte *buf; | |
13777 | unsigned long insn; | |
b34976b6 | 13778 | bfd_boolean use_extend; |
252b5132 RH |
13779 | unsigned short extend; |
13780 | ||
13781 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13782 | op = mips16_immed_operands; | |
13783 | while (op->type != type) | |
13784 | ++op; | |
13785 | ||
13786 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13787 | { | |
b34976b6 AM |
13788 | small = FALSE; |
13789 | ext = TRUE; | |
252b5132 RH |
13790 | } |
13791 | else | |
13792 | { | |
b34976b6 AM |
13793 | small = TRUE; |
13794 | ext = FALSE; | |
252b5132 RH |
13795 | } |
13796 | ||
6386f3a7 | 13797 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13798 | val = S_GET_VALUE (fragp->fr_symbol); |
13799 | if (op->pcrel) | |
13800 | { | |
13801 | addressT addr; | |
13802 | ||
13803 | addr = fragp->fr_address + fragp->fr_fix; | |
13804 | ||
13805 | /* The rules for the base address of a PC relative reloc are | |
13806 | complicated; see mips16_extended_frag. */ | |
13807 | if (type == 'p' || type == 'q') | |
13808 | { | |
13809 | addr += 2; | |
13810 | if (ext) | |
13811 | addr += 2; | |
13812 | /* Ignore the low bit in the target, since it will be | |
13813 | set for a text label. */ | |
13814 | if ((val & 1) != 0) | |
13815 | --val; | |
13816 | } | |
13817 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13818 | addr -= 4; | |
13819 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13820 | addr -= 2; | |
13821 | ||
13822 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13823 | val -= addr; | |
13824 | ||
13825 | /* Make sure the section winds up with the alignment we have | |
13826 | assumed. */ | |
13827 | if (op->shift > 0) | |
13828 | record_alignment (asec, op->shift); | |
13829 | } | |
13830 | ||
13831 | if (ext | |
13832 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13833 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13834 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13835 | _("extended instruction in delay slot")); | |
13836 | ||
13837 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13838 | ||
13839 | if (target_big_endian) | |
13840 | insn = bfd_getb16 (buf); | |
13841 | else | |
13842 | insn = bfd_getl16 (buf); | |
13843 | ||
13844 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13845 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13846 | small, ext, &insn, &use_extend, &extend); | |
13847 | ||
13848 | if (use_extend) | |
13849 | { | |
17a2f251 | 13850 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13851 | fragp->fr_fix += 2; |
13852 | buf += 2; | |
13853 | } | |
13854 | ||
17a2f251 | 13855 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13856 | fragp->fr_fix += 2; |
13857 | buf += 2; | |
13858 | } | |
13859 | else | |
13860 | { | |
13861 | if (fragp->fr_opcode == NULL) | |
13862 | return; | |
13863 | ||
13864 | old = RELAX_OLD (fragp->fr_subtype); | |
13865 | new = RELAX_NEW (fragp->fr_subtype); | |
13866 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13867 | ||
13868 | if (new > 0) | |
f5040a92 | 13869 | memmove (fixptr - old, fixptr, new); |
252b5132 RH |
13870 | |
13871 | fragp->fr_fix += new - old; | |
13872 | } | |
13873 | } | |
13874 | ||
13875 | #ifdef OBJ_ELF | |
13876 | ||
13877 | /* This function is called after the relocs have been generated. | |
13878 | We've been storing mips16 text labels as odd. Here we convert them | |
13879 | back to even for the convenience of the debugger. */ | |
13880 | ||
13881 | void | |
17a2f251 | 13882 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13883 | { |
13884 | asymbol **syms; | |
13885 | unsigned int count, i; | |
13886 | ||
13887 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13888 | return; | |
13889 | ||
13890 | syms = bfd_get_outsymbols (stdoutput); | |
13891 | count = bfd_get_symcount (stdoutput); | |
13892 | for (i = 0; i < count; i++, syms++) | |
13893 | { | |
13894 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13895 | && ((*syms)->value & 1) != 0) | |
13896 | { | |
13897 | (*syms)->value &= ~1; | |
13898 | /* If the symbol has an odd size, it was probably computed | |
13899 | incorrectly, so adjust that as well. */ | |
13900 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13901 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13902 | } | |
13903 | } | |
13904 | } | |
13905 | ||
13906 | #endif | |
13907 | ||
13908 | /* This function is called whenever a label is defined. It is used | |
13909 | when handling branch delays; if a branch has a label, we assume we | |
13910 | can not move it. */ | |
13911 | ||
13912 | void | |
17a2f251 | 13913 | mips_define_label (symbolS *sym) |
252b5132 RH |
13914 | { |
13915 | struct insn_label_list *l; | |
13916 | ||
13917 | if (free_insn_labels == NULL) | |
13918 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13919 | else | |
13920 | { | |
13921 | l = free_insn_labels; | |
13922 | free_insn_labels = l->next; | |
13923 | } | |
13924 | ||
13925 | l->label = sym; | |
13926 | l->next = insn_labels; | |
13927 | insn_labels = l; | |
13928 | } | |
13929 | \f | |
13930 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13931 | ||
13932 | /* Some special processing for a MIPS ELF file. */ | |
13933 | ||
13934 | void | |
17a2f251 | 13935 | mips_elf_final_processing (void) |
252b5132 RH |
13936 | { |
13937 | /* Write out the register information. */ | |
316f5878 | 13938 | if (mips_abi != N64_ABI) |
252b5132 RH |
13939 | { |
13940 | Elf32_RegInfo s; | |
13941 | ||
13942 | s.ri_gprmask = mips_gprmask; | |
13943 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13944 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13945 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13946 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13947 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13948 | ||
13949 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13950 | ((Elf32_External_RegInfo *) | |
13951 | mips_regmask_frag)); | |
13952 | } | |
13953 | else | |
13954 | { | |
13955 | Elf64_Internal_RegInfo s; | |
13956 | ||
13957 | s.ri_gprmask = mips_gprmask; | |
13958 | s.ri_pad = 0; | |
13959 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13960 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13961 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13962 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13963 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13964 | ||
13965 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13966 | ((Elf64_External_RegInfo *) | |
13967 | mips_regmask_frag)); | |
13968 | } | |
13969 | ||
13970 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13971 | sort of BFD interface for this. */ | |
13972 | if (mips_any_noreorder) | |
13973 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13974 | if (mips_pic != NO_PIC) | |
143d77c5 | 13975 | { |
252b5132 | 13976 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13977 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13978 | } | |
13979 | if (mips_abicalls) | |
13980 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13981 | |
98d3f06f | 13982 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13983 | if (file_ase_mips16) |
13984 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13985 | #if 0 /* XXX FIXME */ |
13986 | if (file_ase_mips3d) | |
13987 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13988 | #endif | |
deec1734 CD |
13989 | if (file_ase_mdmx) |
13990 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13991 | |
bdaaa2e1 | 13992 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13993 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13994 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13995 | else if (mips_abi == O64_ABI) |
252b5132 | 13996 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13997 | else if (mips_abi == EABI_ABI) |
252b5132 | 13998 | { |
316f5878 | 13999 | if (!file_mips_gp32) |
252b5132 RH |
14000 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14001 | else | |
14002 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14003 | } | |
316f5878 | 14004 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14005 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14006 | ||
c9914766 | 14007 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14008 | |
14009 | if (mips_32bitmode) | |
14010 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
14011 | } | |
14012 | ||
14013 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14014 | \f | |
beae10d5 KH |
14015 | typedef struct proc { |
14016 | symbolS *isym; | |
14017 | unsigned long reg_mask; | |
14018 | unsigned long reg_offset; | |
14019 | unsigned long fpreg_mask; | |
14020 | unsigned long fpreg_offset; | |
14021 | unsigned long frame_offset; | |
14022 | unsigned long frame_reg; | |
14023 | unsigned long pc_reg; | |
14024 | } procS; | |
252b5132 RH |
14025 | |
14026 | static procS cur_proc; | |
14027 | static procS *cur_proc_ptr; | |
14028 | static int numprocs; | |
14029 | ||
0a9ef439 | 14030 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14031 | |
0a9ef439 | 14032 | void |
17a2f251 | 14033 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14034 | { |
0a9ef439 RH |
14035 | if (fragp->fr_type != rs_align_code) |
14036 | return; | |
14037 | ||
14038 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14039 | { |
14040 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14041 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14042 | ||
0a9ef439 RH |
14043 | int bytes; |
14044 | char *p; | |
a19d8eb0 | 14045 | |
0a9ef439 RH |
14046 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14047 | p = fragp->fr_literal + fragp->fr_fix; | |
14048 | ||
14049 | if (bytes & 1) | |
14050 | { | |
14051 | *p++ = 0; | |
f9419b05 | 14052 | fragp->fr_fix++; |
0a9ef439 RH |
14053 | } |
14054 | ||
14055 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14056 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14057 | } |
14058 | ||
0a9ef439 | 14059 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14060 | } |
14061 | ||
252b5132 | 14062 | static void |
17a2f251 | 14063 | md_obj_begin (void) |
252b5132 RH |
14064 | { |
14065 | } | |
14066 | ||
14067 | static void | |
17a2f251 | 14068 | md_obj_end (void) |
252b5132 RH |
14069 | { |
14070 | /* check for premature end, nesting errors, etc */ | |
14071 | if (cur_proc_ptr) | |
9a41af64 | 14072 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14073 | } |
14074 | ||
14075 | static long | |
17a2f251 | 14076 | get_number (void) |
252b5132 RH |
14077 | { |
14078 | int negative = 0; | |
14079 | long val = 0; | |
14080 | ||
14081 | if (*input_line_pointer == '-') | |
14082 | { | |
14083 | ++input_line_pointer; | |
14084 | negative = 1; | |
14085 | } | |
3882b010 | 14086 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14087 | as_bad (_("expected simple number")); |
252b5132 RH |
14088 | if (input_line_pointer[0] == '0') |
14089 | { | |
14090 | if (input_line_pointer[1] == 'x') | |
14091 | { | |
14092 | input_line_pointer += 2; | |
3882b010 | 14093 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14094 | { |
14095 | val <<= 4; | |
14096 | val |= hex_value (*input_line_pointer++); | |
14097 | } | |
14098 | return negative ? -val : val; | |
14099 | } | |
14100 | else | |
14101 | { | |
14102 | ++input_line_pointer; | |
3882b010 | 14103 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14104 | { |
14105 | val <<= 3; | |
14106 | val |= *input_line_pointer++ - '0'; | |
14107 | } | |
14108 | return negative ? -val : val; | |
14109 | } | |
14110 | } | |
3882b010 | 14111 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14112 | { |
14113 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14114 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14115 | as_warn (_("invalid number")); |
252b5132 RH |
14116 | return -1; |
14117 | } | |
3882b010 | 14118 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14119 | { |
14120 | val *= 10; | |
14121 | val += *input_line_pointer++ - '0'; | |
14122 | } | |
14123 | return negative ? -val : val; | |
14124 | } | |
14125 | ||
14126 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14127 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14128 | case .file implies DWARF-2. */ | |
14129 | ||
14130 | static void | |
17a2f251 | 14131 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14132 | { |
ecb4347a DJ |
14133 | static int first_file_directive = 0; |
14134 | ||
c5dd6aab DJ |
14135 | if (ECOFF_DEBUGGING) |
14136 | { | |
14137 | get_number (); | |
14138 | s_app_file (0); | |
14139 | } | |
14140 | else | |
ecb4347a DJ |
14141 | { |
14142 | char *filename; | |
14143 | ||
14144 | filename = dwarf2_directive_file (0); | |
14145 | ||
14146 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14147 | directive even for stabs output. Make sure that this | |
14148 | ".file" is handled. Note that you need a version of GCC | |
14149 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14150 | if (filename != NULL && ! first_file_directive) | |
14151 | { | |
14152 | (void) new_logical_line (filename, -1); | |
14153 | s_app_file_string (filename); | |
14154 | } | |
14155 | first_file_directive = 1; | |
14156 | } | |
c5dd6aab DJ |
14157 | } |
14158 | ||
14159 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14160 | |
14161 | static void | |
17a2f251 | 14162 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14163 | { |
c5dd6aab DJ |
14164 | if (!ECOFF_DEBUGGING) |
14165 | dwarf2_directive_loc (0); | |
252b5132 RH |
14166 | } |
14167 | ||
252b5132 RH |
14168 | /* The .end directive. */ |
14169 | ||
14170 | static void | |
17a2f251 | 14171 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14172 | { |
14173 | symbolS *p; | |
252b5132 | 14174 | |
7a621144 DJ |
14175 | /* Following functions need their own .frame and .cprestore directives. */ |
14176 | mips_frame_reg_valid = 0; | |
14177 | mips_cprestore_valid = 0; | |
14178 | ||
252b5132 RH |
14179 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14180 | { | |
14181 | p = get_symbol (); | |
14182 | demand_empty_rest_of_line (); | |
14183 | } | |
14184 | else | |
14185 | p = NULL; | |
14186 | ||
14949570 | 14187 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14188 | as_warn (_(".end not in text section")); |
14189 | ||
14190 | if (!cur_proc_ptr) | |
14191 | { | |
14192 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14193 | demand_empty_rest_of_line (); | |
14194 | return; | |
14195 | } | |
14196 | ||
14197 | if (p != NULL) | |
14198 | { | |
14199 | assert (S_GET_NAME (p)); | |
14200 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14201 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14202 | |
14203 | if (debug_type == DEBUG_STABS) | |
14204 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14205 | S_GET_NAME (p)); | |
252b5132 RH |
14206 | } |
14207 | else | |
14208 | as_warn (_(".end directive missing or unknown symbol")); | |
14209 | ||
ecb4347a DJ |
14210 | #ifdef OBJ_ELF |
14211 | /* Generate a .pdr section. */ | |
dcd410fe RO |
14212 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14213 | && mips_flag_pdr) | |
ecb4347a DJ |
14214 | { |
14215 | segT saved_seg = now_seg; | |
14216 | subsegT saved_subseg = now_subseg; | |
14217 | valueT dot; | |
14218 | expressionS exp; | |
14219 | char *fragp; | |
252b5132 | 14220 | |
ecb4347a | 14221 | dot = frag_now_fix (); |
252b5132 RH |
14222 | |
14223 | #ifdef md_flush_pending_output | |
ecb4347a | 14224 | md_flush_pending_output (); |
252b5132 RH |
14225 | #endif |
14226 | ||
ecb4347a DJ |
14227 | assert (pdr_seg); |
14228 | subseg_set (pdr_seg, 0); | |
252b5132 | 14229 | |
ecb4347a DJ |
14230 | /* Write the symbol. */ |
14231 | exp.X_op = O_symbol; | |
14232 | exp.X_add_symbol = p; | |
14233 | exp.X_add_number = 0; | |
14234 | emit_expr (&exp, 4); | |
252b5132 | 14235 | |
ecb4347a | 14236 | fragp = frag_more (7 * 4); |
252b5132 | 14237 | |
17a2f251 TS |
14238 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14239 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14240 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14241 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14242 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14243 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14244 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14245 | |
ecb4347a DJ |
14246 | subseg_set (saved_seg, saved_subseg); |
14247 | } | |
14248 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14249 | |
14250 | cur_proc_ptr = NULL; | |
14251 | } | |
14252 | ||
14253 | /* The .aent and .ent directives. */ | |
14254 | ||
14255 | static void | |
17a2f251 | 14256 | s_mips_ent (int aent) |
252b5132 | 14257 | { |
252b5132 | 14258 | symbolS *symbolP; |
252b5132 RH |
14259 | |
14260 | symbolP = get_symbol (); | |
14261 | if (*input_line_pointer == ',') | |
f9419b05 | 14262 | ++input_line_pointer; |
252b5132 | 14263 | SKIP_WHITESPACE (); |
3882b010 | 14264 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14265 | || *input_line_pointer == '-') |
874e8986 | 14266 | get_number (); |
252b5132 | 14267 | |
14949570 | 14268 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14269 | as_warn (_(".ent or .aent not in text section.")); |
14270 | ||
14271 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14272 | as_warn (_("missing .end")); |
252b5132 RH |
14273 | |
14274 | if (!aent) | |
14275 | { | |
7a621144 DJ |
14276 | /* This function needs its own .frame and .cprestore directives. */ |
14277 | mips_frame_reg_valid = 0; | |
14278 | mips_cprestore_valid = 0; | |
14279 | ||
252b5132 RH |
14280 | cur_proc_ptr = &cur_proc; |
14281 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14282 | ||
14283 | cur_proc_ptr->isym = symbolP; | |
14284 | ||
49309057 | 14285 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14286 | |
f9419b05 | 14287 | ++numprocs; |
ecb4347a DJ |
14288 | |
14289 | if (debug_type == DEBUG_STABS) | |
14290 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14291 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14292 | } |
14293 | ||
14294 | demand_empty_rest_of_line (); | |
14295 | } | |
14296 | ||
14297 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14298 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14299 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14300 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14301 | symbol table (in the mdebug section). */ |
14302 | ||
14303 | static void | |
17a2f251 | 14304 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14305 | { |
ecb4347a DJ |
14306 | #ifdef OBJ_ELF |
14307 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14308 | { | |
14309 | long val; | |
252b5132 | 14310 | |
ecb4347a DJ |
14311 | if (cur_proc_ptr == (procS *) NULL) |
14312 | { | |
14313 | as_warn (_(".frame outside of .ent")); | |
14314 | demand_empty_rest_of_line (); | |
14315 | return; | |
14316 | } | |
252b5132 | 14317 | |
ecb4347a DJ |
14318 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14319 | ||
14320 | SKIP_WHITESPACE (); | |
14321 | if (*input_line_pointer++ != ',' | |
14322 | || get_absolute_expression_and_terminator (&val) != ',') | |
14323 | { | |
14324 | as_warn (_("Bad .frame directive")); | |
14325 | --input_line_pointer; | |
14326 | demand_empty_rest_of_line (); | |
14327 | return; | |
14328 | } | |
252b5132 | 14329 | |
ecb4347a DJ |
14330 | cur_proc_ptr->frame_offset = val; |
14331 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14332 | |
252b5132 | 14333 | demand_empty_rest_of_line (); |
252b5132 | 14334 | } |
ecb4347a DJ |
14335 | else |
14336 | #endif /* OBJ_ELF */ | |
14337 | s_ignore (ignore); | |
252b5132 RH |
14338 | } |
14339 | ||
bdaaa2e1 KH |
14340 | /* The .fmask and .mask directives. If the mdebug section is present |
14341 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14342 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14343 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14344 | make reference to the ecoff symbol table (in the mdebug section). */ |
14345 | ||
14346 | static void | |
17a2f251 | 14347 | s_mips_mask (int reg_type) |
252b5132 | 14348 | { |
ecb4347a DJ |
14349 | #ifdef OBJ_ELF |
14350 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14351 | { |
ecb4347a | 14352 | long mask, off; |
252b5132 | 14353 | |
ecb4347a DJ |
14354 | if (cur_proc_ptr == (procS *) NULL) |
14355 | { | |
14356 | as_warn (_(".mask/.fmask outside of .ent")); | |
14357 | demand_empty_rest_of_line (); | |
14358 | return; | |
14359 | } | |
252b5132 | 14360 | |
ecb4347a DJ |
14361 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14362 | { | |
14363 | as_warn (_("Bad .mask/.fmask directive")); | |
14364 | --input_line_pointer; | |
14365 | demand_empty_rest_of_line (); | |
14366 | return; | |
14367 | } | |
252b5132 | 14368 | |
ecb4347a DJ |
14369 | off = get_absolute_expression (); |
14370 | ||
14371 | if (reg_type == 'F') | |
14372 | { | |
14373 | cur_proc_ptr->fpreg_mask = mask; | |
14374 | cur_proc_ptr->fpreg_offset = off; | |
14375 | } | |
14376 | else | |
14377 | { | |
14378 | cur_proc_ptr->reg_mask = mask; | |
14379 | cur_proc_ptr->reg_offset = off; | |
14380 | } | |
14381 | ||
14382 | demand_empty_rest_of_line (); | |
252b5132 RH |
14383 | } |
14384 | else | |
ecb4347a DJ |
14385 | #endif /* OBJ_ELF */ |
14386 | s_ignore (reg_type); | |
252b5132 RH |
14387 | } |
14388 | ||
14389 | /* The .loc directive. */ | |
14390 | ||
14391 | #if 0 | |
14392 | static void | |
17a2f251 | 14393 | s_loc (int x) |
252b5132 RH |
14394 | { |
14395 | symbolS *symbolP; | |
14396 | int lineno; | |
14397 | int addroff; | |
14398 | ||
14399 | assert (now_seg == text_section); | |
14400 | ||
14401 | lineno = get_number (); | |
14402 | addroff = frag_now_fix (); | |
14403 | ||
14404 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14405 | S_SET_TYPE (symbolP, N_SLINE); | |
14406 | S_SET_OTHER (symbolP, 0); | |
14407 | S_SET_DESC (symbolP, lineno); | |
14408 | symbolP->sy_segment = now_seg; | |
14409 | } | |
14410 | #endif | |
e7af610e | 14411 | |
316f5878 RS |
14412 | /* A table describing all the processors gas knows about. Names are |
14413 | matched in the order listed. | |
e7af610e | 14414 | |
316f5878 RS |
14415 | To ease comparison, please keep this table in the same order as |
14416 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14417 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14418 | { | |
316f5878 RS |
14419 | /* Entries for generic ISAs */ |
14420 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14421 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14422 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14423 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14424 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14425 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14426 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14427 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14428 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14429 | |
14430 | /* MIPS I */ | |
14431 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14432 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14433 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14434 | ||
14435 | /* MIPS II */ | |
14436 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14437 | ||
14438 | /* MIPS III */ | |
14439 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14440 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14441 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14442 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14443 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14444 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14445 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14446 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14447 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14448 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14449 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14450 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14451 | ||
14452 | /* MIPS IV */ | |
14453 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14454 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14455 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14456 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14457 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14458 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14459 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14460 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14461 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14462 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14463 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
14464 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
14465 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
14466 | |
14467 | /* MIPS 32 */ | |
fef14a42 | 14468 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14469 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14470 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14471 | |
316f5878 RS |
14472 | /* MIPS 64 */ |
14473 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14474 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14475 | |
c7a23324 | 14476 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14477 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14478 | |
316f5878 RS |
14479 | /* End marker */ |
14480 | { NULL, 0, 0, 0 } | |
14481 | }; | |
e7af610e | 14482 | |
84ea6cf2 | 14483 | |
316f5878 RS |
14484 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14485 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14486 | |
316f5878 | 14487 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14488 | |
b34976b6 | 14489 | static bfd_boolean |
17a2f251 | 14490 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14491 | { |
14492 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14493 | given++, canonical++; | |
14494 | ||
14495 | return ((*given == 0 && *canonical == 0) | |
14496 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14497 | } | |
14498 | ||
14499 | ||
14500 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14501 | CPU name. We've traditionally allowed a lot of variation here. | |
14502 | ||
14503 | Note: this function is shared between GCC and GAS. */ | |
14504 | ||
b34976b6 | 14505 | static bfd_boolean |
17a2f251 | 14506 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14507 | { |
14508 | /* First see if the name matches exactly, or with a final "000" | |
14509 | turned into "k". */ | |
14510 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14511 | return TRUE; |
316f5878 RS |
14512 | |
14513 | /* If not, try comparing based on numerical designation alone. | |
14514 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14515 | if (TOLOWER (*given) == 'r') | |
14516 | given++; | |
14517 | if (!ISDIGIT (*given)) | |
b34976b6 | 14518 | return FALSE; |
316f5878 RS |
14519 | |
14520 | /* Skip over some well-known prefixes in the canonical name, | |
14521 | hoping to find a number there too. */ | |
14522 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14523 | canonical += 2; | |
14524 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14525 | canonical += 2; | |
14526 | else if (TOLOWER (canonical[0]) == 'r') | |
14527 | canonical += 1; | |
14528 | ||
14529 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14530 | } | |
14531 | ||
14532 | ||
14533 | /* Parse an option that takes the name of a processor as its argument. | |
14534 | OPTION is the name of the option and CPU_STRING is the argument. | |
14535 | Return the corresponding processor enumeration if the CPU_STRING is | |
14536 | recognized, otherwise report an error and return null. | |
14537 | ||
14538 | A similar function exists in GCC. */ | |
e7af610e NC |
14539 | |
14540 | static const struct mips_cpu_info * | |
17a2f251 | 14541 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14542 | { |
316f5878 | 14543 | const struct mips_cpu_info *p; |
e7af610e | 14544 | |
316f5878 RS |
14545 | /* 'from-abi' selects the most compatible architecture for the given |
14546 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14547 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14548 | version. Look first at the -mgp options, if given, otherwise base | |
14549 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14550 | |
316f5878 RS |
14551 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14552 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14553 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14554 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14555 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14556 | { | |
14557 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14558 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14559 | ||
14560 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14561 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14562 | ||
14563 | if (file_mips_gp32 >= 0) | |
14564 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14565 | ||
14566 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14567 | ? ISA_MIPS3 | |
14568 | : ISA_MIPS1); | |
14569 | } | |
14570 | ||
14571 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14572 | if (strcasecmp (cpu_string, "default") == 0) | |
14573 | return 0; | |
14574 | ||
14575 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14576 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14577 | return p; | |
14578 | ||
14579 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14580 | return 0; | |
e7af610e NC |
14581 | } |
14582 | ||
316f5878 RS |
14583 | /* Return the canonical processor information for ISA (a member of the |
14584 | ISA_MIPS* enumeration). */ | |
14585 | ||
e7af610e | 14586 | static const struct mips_cpu_info * |
17a2f251 | 14587 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14588 | { |
14589 | int i; | |
14590 | ||
14591 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14592 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14593 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14594 | return (&mips_cpu_info_table[i]); |
14595 | ||
e972090a | 14596 | return NULL; |
e7af610e | 14597 | } |
fef14a42 TS |
14598 | |
14599 | static const struct mips_cpu_info * | |
17a2f251 | 14600 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14601 | { |
14602 | int i; | |
14603 | ||
14604 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14605 | if (arch == mips_cpu_info_table[i].cpu) | |
14606 | return (&mips_cpu_info_table[i]); | |
14607 | ||
14608 | return NULL; | |
14609 | } | |
316f5878 RS |
14610 | \f |
14611 | static void | |
17a2f251 | 14612 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14613 | { |
14614 | if (*first_p) | |
14615 | { | |
14616 | fprintf (stream, "%24s", ""); | |
14617 | *col_p = 24; | |
14618 | } | |
14619 | else | |
14620 | { | |
14621 | fprintf (stream, ", "); | |
14622 | *col_p += 2; | |
14623 | } | |
e7af610e | 14624 | |
316f5878 RS |
14625 | if (*col_p + strlen (string) > 72) |
14626 | { | |
14627 | fprintf (stream, "\n%24s", ""); | |
14628 | *col_p = 24; | |
14629 | } | |
14630 | ||
14631 | fprintf (stream, "%s", string); | |
14632 | *col_p += strlen (string); | |
14633 | ||
14634 | *first_p = 0; | |
14635 | } | |
14636 | ||
14637 | void | |
17a2f251 | 14638 | md_show_usage (FILE *stream) |
e7af610e | 14639 | { |
316f5878 RS |
14640 | int column, first; |
14641 | size_t i; | |
14642 | ||
14643 | fprintf (stream, _("\ | |
14644 | MIPS options:\n\ | |
14645 | -membedded-pic generate embedded position independent code\n\ | |
14646 | -EB generate big endian output\n\ | |
14647 | -EL generate little endian output\n\ | |
14648 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14649 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14650 | implicitly with the gp register [default 8]\n")); | |
14651 | fprintf (stream, _("\ | |
14652 | -mips1 generate MIPS ISA I instructions\n\ | |
14653 | -mips2 generate MIPS ISA II instructions\n\ | |
14654 | -mips3 generate MIPS ISA III instructions\n\ | |
14655 | -mips4 generate MIPS ISA IV instructions\n\ | |
14656 | -mips5 generate MIPS ISA V instructions\n\ | |
14657 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14658 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14659 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14660 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14661 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14662 | ||
14663 | first = 1; | |
e7af610e NC |
14664 | |
14665 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14666 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14667 | show (stream, "from-abi", &column, &first); | |
14668 | fputc ('\n', stream); | |
e7af610e | 14669 | |
316f5878 RS |
14670 | fprintf (stream, _("\ |
14671 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14672 | -no-mCPU don't generate code specific to CPU.\n\ | |
14673 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14674 | ||
14675 | first = 1; | |
14676 | ||
14677 | show (stream, "3900", &column, &first); | |
14678 | show (stream, "4010", &column, &first); | |
14679 | show (stream, "4100", &column, &first); | |
14680 | show (stream, "4650", &column, &first); | |
14681 | fputc ('\n', stream); | |
14682 | ||
14683 | fprintf (stream, _("\ | |
14684 | -mips16 generate mips16 instructions\n\ | |
14685 | -no-mips16 do not generate mips16 instructions\n")); | |
14686 | fprintf (stream, _("\ | |
14687 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14688 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14689 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14690 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14691 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14692 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14693 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14694 | #ifdef OBJ_ELF | |
14695 | fprintf (stream, _("\ | |
14696 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14697 | -non_shared do not generate position independent code\n\ | |
14698 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14699 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14700 | -mabi=ABI create ABI conformant object file for:\n")); |
14701 | ||
14702 | first = 1; | |
14703 | ||
14704 | show (stream, "32", &column, &first); | |
14705 | show (stream, "o64", &column, &first); | |
14706 | show (stream, "n32", &column, &first); | |
14707 | show (stream, "64", &column, &first); | |
14708 | show (stream, "eabi", &column, &first); | |
14709 | ||
14710 | fputc ('\n', stream); | |
14711 | ||
14712 | fprintf (stream, _("\ | |
14713 | -32 create o32 ABI object file (default)\n\ | |
14714 | -n32 create n32 ABI object file\n\ | |
14715 | -64 create 64 ABI object file\n")); | |
14716 | #endif | |
e7af610e | 14717 | } |
14e777e0 KB |
14718 | |
14719 | enum dwarf2_format | |
17a2f251 | 14720 | mips_dwarf2_format (void) |
14e777e0 KB |
14721 | { |
14722 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14723 | { |
14724 | #ifdef TE_IRIX | |
14725 | return dwarf2_format_64bit_irix; | |
14726 | #else | |
14727 | return dwarf2_format_64bit; | |
14728 | #endif | |
14729 | } | |
14e777e0 KB |
14730 | else |
14731 | return dwarf2_format_32bit; | |
14732 | } |