Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
622b1860 ILT |
143 | reliable. |
144 | ||
145 | FIXME: The CPU specific variables (mips_4010, et. al.) should | |
146 | probably be in here as well, and there should probably be some way | |
147 | to set them. */ | |
3c83da8a JW |
148 | |
149 | struct mips_set_options | |
150 | { | |
151 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
152 | if it has not been initialized. Changed by `.set mipsN', and the | |
153 | -mipsN command line option, and the default CPU. */ | |
154 | int isa; | |
155 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
156 | not, 1 if we are, and -1 if the value has not been initialized. | |
157 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
158 | -nomips16 command line options, and the default CPU. */ | |
159 | int mips16; | |
160 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
161 | reorder' and `.set noreorder'. */ | |
162 | int noreorder; | |
163 | /* Non-zero if we should not permit the $at ($1) register to be used | |
164 | in instructions. Changed by `.set at' and `.set noat'. */ | |
165 | int noat; | |
166 | /* Non-zero if we should warn when a macro instruction expands into | |
167 | more than one machine instruction. Changed by `.set nomacro' and | |
168 | `.set macro'. */ | |
169 | int warn_about_macros; | |
170 | /* Non-zero if we should not move instructions. Changed by `.set | |
171 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
172 | int nomove; | |
173 | /* Non-zero if we should not optimize branches by moving the target | |
174 | of the branch into the delay slot. Actually, we don't perform | |
175 | this optimization anyhow. Changed by `.set bopt' and `.set | |
176 | nobopt'. */ | |
177 | int nobopt; | |
178 | /* Non-zero if we should not autoextend mips16 instructions. | |
179 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
180 | int noautoextend; | |
181 | }; | |
182 | ||
183 | /* This is the struct we use to hold the current set of options. Note | |
184 | that we must set the isa and mips16 fields to -1 to indicate that | |
185 | they have not been initialized. */ | |
186 | ||
187 | static struct mips_set_options mips_opts = { -1, -1 }; | |
188 | ||
1aa6938e ILT |
189 | /* These variables are filled in with the masks of registers used. |
190 | The object format code reads them and puts them in the appropriate | |
191 | place. */ | |
192 | unsigned long mips_gprmask; | |
193 | unsigned long mips_cprmask[4]; | |
194 | ||
1051c97f ILT |
195 | /* MIPS ISA we are using for this output file. */ |
196 | static int file_mips_isa; | |
197 | ||
8c63448a | 198 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 199 | static int mips_cpu = -1; |
8c63448a | 200 | |
b2b8c24e ILT |
201 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
202 | static int mips_4650 = -1; | |
203 | ||
e532b44c ILT |
204 | /* Whether the 4010 instructions are permitted. */ |
205 | static int mips_4010 = -1; | |
206 | ||
c625fc23 JSC |
207 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
208 | static int mips_4100 = -1; | |
209 | ||
2d035a50 GRK |
210 | /* start-sanitize-vr4320 */ |
211 | /* Whether NEC vr4320 instructions are permitted. */ | |
212 | static int mips_4320 = -1; | |
213 | ||
214 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 215 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
216 | /* Whether NEC vr5400 instructions are permitted. */ |
217 | static int mips_5400 = -1; | |
218 | ||
6b34ac5a | 219 | /* end-sanitize-cygnus */ |
276c2d7d GRK |
220 | /* start-sanitize-r5900 */ |
221 | /* Whether Toshiba r5900 instructions are permitted. */ | |
222 | static int mips_5900 = -1; | |
276c2d7d | 223 | |
aa2e0460 | 224 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
225 | /* Whether Toshiba r3900 instructions are permitted. */ |
226 | static int mips_3900 = -1; | |
227 | ||
42444087 GRK |
228 | /* start-sanitize-tx49 */ |
229 | /* Whether Toshiba r4900 instructions are permitted. */ | |
230 | static int mips_4900 = -1; | |
231 | ||
232 | /* end-sanitize-tx49 */ | |
4e96260f JL |
233 | /* start-sanitize-tx19 */ |
234 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
235 | The tx19 related options and configuration bits are handled by | |
236 | the tx39 flags. */ | |
237 | /* end-sanitize-tx19 */ | |
238 | ||
5c6f5923 GRK |
239 | /* Whether the processor uses hardware interlocks to protect |
240 | reads from the HI and LO registers, and thus does not | |
622b1860 ILT |
241 | require nops to be inserted. |
242 | ||
243 | FIXME: We really should not be checking mips_cpu here. The -mcpu= | |
244 | option is documented to not do anything special. In gcc, the | |
245 | -mcpu= option only affects scheduling, and does not affect code | |
246 | generation. Each test of -mcpu= here should actually be testing a | |
247 | specific variable, such as mips_4010, and each such variable should | |
248 | have a command line option to set it. The -mcpu= option may be | |
249 | used to set the default value of these options, as is the case for | |
250 | mips_4010. */ | |
251 | ||
2cf51495 | 252 | #define hilo_interlocks (mips_4010 || mips_3900 \ |
4ebda395 | 253 | /* start-sanitize-tx49 */ \ |
42444087 | 254 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 255 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
256 | /* start-sanitize-vr4320 */ \ |
257 | || mips_cpu == 4320 \ | |
258 | /* end-sanitize-vr4320 */ \ | |
be294de6 | 259 | /* start-sanitize-r5900 */ \ |
ec85f6bc | 260 | || mips_5900 \ |
be294de6 | 261 | /* end-sanitize-r5900 */ \ |
4ebda395 | 262 | ) |
5c6f5923 | 263 | |
a3e8c5b7 ILT |
264 | /* Whether the processor uses hardware interlocks to protect reads |
265 | from the GPRs, and thus does not require nops to be inserted. */ | |
266 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
6b34ac5a | 267 | /* start-sanitize-cygnus */ |
1c6f3441 ILT |
268 | #undef gpr_interlocks |
269 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
6b34ac5a | 270 | /* end-sanitize-cygnus */ |
1c6f3441 | 271 | |
e532b44c | 272 | |
5c6f5923 | 273 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 274 | (co-processor) interlocks. */ |
efec4a28 | 275 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
276 | #define cop_interlocks (mips_cpu == 4300 \ |
277 | /* start-sanitize-vr4320 */ \ | |
278 | || mips_cpu == 4320 \ | |
279 | /* end-sanitize-vr4320 */ \ | |
6b34ac5a | 280 | /* start-sanitize-cygnus */ \ |
2d035a50 | 281 | || mips_cpu == 5400 \ |
6b34ac5a | 282 | /* end-sanitize-cygnus */ \ |
2d035a50 | 283 | ) |
344a8d61 | 284 | |
d9aba805 ILT |
285 | /* MIPS PIC level. */ |
286 | ||
287 | enum mips_pic_level | |
288 | { | |
289 | /* Do not generate PIC code. */ | |
290 | NO_PIC, | |
291 | ||
292 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
293 | not sure what it is supposed to do. */ | |
294 | IRIX4_PIC, | |
295 | ||
296 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
297 | SVR4_PIC, | |
298 | ||
299 | /* Generate PIC code without using a global offset table: the data | |
300 | segment has a maximum size of 64K, all data references are off | |
301 | the $gp register, and all text references are PC relative. This | |
302 | is used on some embedded systems. */ | |
303 | EMBEDDED_PIC | |
304 | }; | |
305 | ||
306 | static enum mips_pic_level mips_pic; | |
9226253a | 307 | |
fb251650 ILT |
308 | /* 1 if we should generate 32 bit offsets from the GP register in |
309 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
310 | static int mips_big_got; | |
311 | ||
8ea7f4e8 ILT |
312 | /* 1 if trap instructions should used for overflow rather than break |
313 | instructions. */ | |
314 | static int mips_trap; | |
315 | ||
3c83da8a | 316 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 317 | |
0dd2d296 | 318 | static int mips_any_noreorder; |
3d3c5039 | 319 | |
670a50eb ILT |
320 | /* The size of the small data section. */ |
321 | static int g_switch_value = 8; | |
42562568 ILT |
322 | /* Whether the -G option was used. */ |
323 | static int g_switch_seen = 0; | |
670a50eb | 324 | |
3d3c5039 ILT |
325 | #define N_RMASK 0xc4 |
326 | #define N_VFP 0xd4 | |
327 | ||
d8a1c247 KR |
328 | /* If we can determine in advance that GP optimization won't be |
329 | possible, we can skip the relaxation stuff that tries to produce | |
330 | GP-relative references. This makes delay slot optimization work | |
331 | better. | |
332 | ||
333 | This function can only provide a guess, but it seems to work for | |
334 | gcc output. If it guesses wrong, the only loss should be in | |
335 | efficiency; it shouldn't introduce any bugs. | |
336 | ||
337 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
338 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 339 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 340 | |
3d3c5039 ILT |
341 | /* handle of the OPCODE hash table */ |
342 | static struct hash_control *op_hash = NULL; | |
343 | ||
cc5703cd ILT |
344 | /* The opcode hash table we use for the mips16. */ |
345 | static struct hash_control *mips16_op_hash = NULL; | |
346 | ||
3d3c5039 ILT |
347 | /* This array holds the chars that always start a comment. If the |
348 | pre-processor is disabled, these aren't very useful */ | |
349 | const char comment_chars[] = "#"; | |
350 | ||
351 | /* This array holds the chars that only start a comment at the beginning of | |
352 | a line. If the line seems to have the form '# 123 filename' | |
353 | .line and .file directives will appear in the pre-processed output */ | |
354 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
355 | first line of the input file. This is because the compiler outputs | |
356 | #NO_APP at the beginning of its output. */ | |
357 | /* Also note that C style comments are always supported. */ | |
358 | const char line_comment_chars[] = "#"; | |
359 | ||
360 | /* This array holds machine specific line separator characters. */ | |
361 | const char line_separator_chars[] = ""; | |
362 | ||
363 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
364 | const char EXP_CHARS[] = "eE"; | |
365 | ||
366 | /* Chars that mean this number is a floating point constant */ | |
367 | /* As in 0f12.456 */ | |
368 | /* or 0d1.2345e12 */ | |
369 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
370 | ||
371 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
372 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
373 | but nothing is ideal around here. | |
374 | */ | |
375 | ||
670a50eb | 376 | static char *insn_error; |
3d3c5039 | 377 | |
3d3c5039 | 378 | static int auto_align = 1; |
becfe05e | 379 | |
9226253a ILT |
380 | /* When outputting SVR4 PIC code, the assembler needs to know the |
381 | offset in the stack frame from which to restore the $gp register. | |
382 | This is set by the .cprestore pseudo-op, and saved in this | |
383 | variable. */ | |
0dd2d296 ILT |
384 | static offsetT mips_cprestore_offset = -1; |
385 | ||
386 | /* This is the register which holds the stack frame, as set by the | |
387 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
388 | static int mips_frame_reg = SP; | |
9226253a | 389 | |
becfe05e ILT |
390 | /* To output NOP instructions correctly, we need to keep information |
391 | about the previous two instructions. */ | |
392 | ||
0aa07269 ILT |
393 | /* Whether we are optimizing. The default value of 2 means to remove |
394 | unneeded NOPs and swap branch instructions when possible. A value | |
395 | of 1 means to not swap branches. A value of 0 means to always | |
396 | insert NOPs. */ | |
397 | static int mips_optimize = 2; | |
4e95866e | 398 | |
22ba90ce ILT |
399 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
400 | equivalent to seeing no -g option at all. */ | |
401 | static int mips_debug = 0; | |
402 | ||
becfe05e ILT |
403 | /* The previous instruction. */ |
404 | static struct mips_cl_insn prev_insn; | |
405 | ||
406 | /* The instruction before prev_insn. */ | |
407 | static struct mips_cl_insn prev_prev_insn; | |
408 | ||
409 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
410 | point the insn_mo field at this dummy integer. */ | |
411 | static const struct mips_opcode dummy_opcode = { 0 }; | |
412 | ||
413 | /* Non-zero if prev_insn is valid. */ | |
414 | static int prev_insn_valid; | |
415 | ||
416 | /* The frag for the previous instruction. */ | |
417 | static struct frag *prev_insn_frag; | |
418 | ||
419 | /* The offset into prev_insn_frag for the previous instruction. */ | |
420 | static long prev_insn_where; | |
421 | ||
a677feeb ILT |
422 | /* The reloc type for the previous instruction, if any. */ |
423 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
424 | ||
becfe05e ILT |
425 | /* The reloc for the previous instruction, if any. */ |
426 | static fixS *prev_insn_fixp; | |
427 | ||
428 | /* Non-zero if the previous instruction was in a delay slot. */ | |
429 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
430 | |
431 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
432 | static int prev_insn_unreordered; | |
433 | ||
cc5703cd ILT |
434 | /* Non-zero if the previous instruction uses an extend opcode (if |
435 | mips16). */ | |
436 | static int prev_insn_extended; | |
437 | ||
4e95866e ILT |
438 | /* Non-zero if the previous previous instruction was in a .set |
439 | noreorder. */ | |
440 | static int prev_prev_insn_unreordered; | |
867a58b3 | 441 | |
7e656649 RH |
442 | /* start-sanitize-branchbug4011 */ |
443 | /* Non-zero if the previous insn had one or more labels */ | |
444 | static int prev_insn_labels; | |
445 | ||
446 | /* end-sanitize-branchbug4011 */ | |
4a1cb507 ILT |
447 | /* If this is set, it points to a frag holding nop instructions which |
448 | were inserted before the start of a noreorder section. If those | |
449 | nops turn out to be unnecessary, the size of the frag can be | |
450 | decreased. */ | |
451 | static fragS *prev_nop_frag; | |
452 | ||
453 | /* The number of nop instructions we created in prev_nop_frag. */ | |
454 | static int prev_nop_frag_holds; | |
455 | ||
456 | /* The number of nop instructions that we know we need in | |
457 | prev_nop_frag. */ | |
458 | static int prev_nop_frag_required; | |
459 | ||
460 | /* The number of instructions we've seen since prev_nop_frag. */ | |
461 | static int prev_nop_frag_since; | |
462 | ||
867a58b3 ILT |
463 | /* For ECOFF and ELF, relocations against symbols are done in two |
464 | parts, with a HI relocation and a LO relocation. Each relocation | |
465 | has only 16 bits of space to store an addend. This means that in | |
466 | order for the linker to handle carries correctly, it must be able | |
467 | to locate both the HI and the LO relocation. This means that the | |
468 | relocations must appear in order in the relocation table. | |
469 | ||
470 | In order to implement this, we keep track of each unmatched HI | |
471 | relocation. We then sort them so that they immediately precede the | |
472 | corresponding LO relocation. */ | |
473 | ||
474 | struct mips_hi_fixup | |
475 | { | |
476 | /* Next HI fixup. */ | |
477 | struct mips_hi_fixup *next; | |
478 | /* This fixup. */ | |
479 | fixS *fixp; | |
480 | /* The section this fixup is in. */ | |
481 | segT seg; | |
482 | }; | |
483 | ||
484 | /* The list of unmatched HI relocs. */ | |
485 | ||
486 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
487 | |
488 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
489 | ||
490 | #define X ILLEGAL_REG | |
491 | static const int mips32_to_16_reg_map[] = | |
492 | { | |
493 | X, X, 2, 3, 4, 5, 6, 7, | |
494 | X, X, X, X, X, X, X, X, | |
495 | 0, 1, X, X, X, X, X, X, | |
496 | X, X, X, X, X, X, X, X | |
497 | }; | |
498 | #undef X | |
499 | ||
500 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
501 | ||
502 | static const int mips16_to_32_reg_map[] = | |
503 | { | |
504 | 16, 17, 2, 3, 4, 5, 6, 7 | |
505 | }; | |
3d3c5039 | 506 | \f |
0dd2d296 ILT |
507 | /* Since the MIPS does not have multiple forms of PC relative |
508 | instructions, we do not have to do relaxing as is done on other | |
509 | platforms. However, we do have to handle GP relative addressing | |
510 | correctly, which turns out to be a similar problem. | |
511 | ||
512 | Every macro that refers to a symbol can occur in (at least) two | |
513 | forms, one with GP relative addressing and one without. For | |
514 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 515 | a macro instruction like this: |
0dd2d296 ILT |
516 | lw $4,i |
517 | If i can be addressed off the GP register (this is true if it is in | |
518 | the .sbss or .sdata section, or if it is known to be smaller than | |
519 | the -G argument) this will generate the following instruction: | |
520 | lw $4,i($gp) | |
521 | This instruction will use a GPREL reloc. If i can not be addressed | |
522 | off the GP register, the following instruction sequence will be used: | |
523 | lui $at,i | |
524 | lw $4,i($at) | |
525 | In this case the first instruction will have a HI16 reloc, and the | |
526 | second reloc will have a LO16 reloc. Both relocs will be against | |
527 | the symbol i. | |
528 | ||
529 | The issue here is that we may not know whether i is GP addressable | |
530 | until after we see the instruction that uses it. Therefore, we | |
531 | want to be able to choose the final instruction sequence only at | |
532 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 533 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
534 | end of assembly. |
535 | ||
536 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
537 | addressing in quite the same way, but the issue still arises as |
538 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
539 | |
540 | We handle these issues by actually generating both possible | |
541 | instruction sequences. The longer one is put in a frag_var with | |
542 | type rs_machine_dependent. We encode what to do with the frag in | |
543 | the subtype field. We encode (1) the number of existing bytes to | |
544 | replace, (2) the number of new bytes to use, (3) the offset from | |
545 | the start of the existing bytes to the first reloc we must generate | |
546 | (that is, the offset is applied from the start of the existing | |
547 | bytes after they are replaced by the new bytes, if any), (4) the | |
548 | offset from the start of the existing bytes to the second reloc, | |
549 | (5) whether a third reloc is needed (the third reloc is always four | |
550 | bytes after the second reloc), and (6) whether to warn if this | |
551 | variant is used (this is sometimes needed if .set nomacro or .set | |
552 | noat is in effect). All these numbers are reasonably small. | |
553 | ||
554 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
555 | ensure that delay slots are handled correctly. Fortunately, there |
556 | are a limited number of cases. When the second instruction | |
557 | sequence is generated, append_insn is directed to maintain the | |
558 | existing delay slot information, so it continues to apply to any | |
559 | code after the second instruction sequence. This means that the | |
560 | second instruction sequence must not impose any requirements not | |
561 | required by the first instruction sequence. | |
0dd2d296 ILT |
562 | |
563 | These variant frags are then handled in functions called by the | |
564 | machine independent code. md_estimate_size_before_relax returns | |
565 | the final size of the frag. md_convert_frag sets up the final form | |
566 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
567 | one if needed. */ | |
568 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
569 | ((relax_substateT) \ | |
cc5703cd | 570 | (((old) << 23) \ |
0dd2d296 ILT |
571 | | ((new) << 16) \ |
572 | | (((reloc1) + 64) << 9) \ | |
573 | | (((reloc2) + 64) << 2) \ | |
574 | | ((reloc3) ? (1 << 1) : 0) \ | |
575 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
576 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
577 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
578 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
579 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
580 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
581 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
582 | |
583 | /* For mips16 code, we use an entirely different form of relaxation. | |
584 | mips16 supports two versions of most instructions which take | |
585 | immediate values: a small one which takes some small value, and a | |
586 | larger one which takes a 16 bit value. Since branches also follow | |
587 | this pattern, relaxing these values is required. | |
588 | ||
589 | We can assemble both mips16 and normal MIPS code in a single | |
590 | object. Therefore, we need to support this type of relaxation at | |
591 | the same time that we support the relaxation described above. We | |
592 | use the high bit of the subtype field to distinguish these cases. | |
593 | ||
a677feeb ILT |
594 | The information we store for this type of relaxation is the |
595 | argument code found in the opcode file for this relocation, whether | |
596 | the user explicitly requested a small or extended form, and whether | |
597 | the relocation is in a jump or jal delay slot. That tells us the | |
598 | size of the value, and how it should be stored. We also store | |
599 | whether the fragment is considered to be extended or not. We also | |
600 | store whether this is known to be a branch to a different section, | |
601 | whether we have tried to relax this frag yet, and whether we have | |
602 | ever extended a PC relative fragment because of a shift count. */ | |
603 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
604 | (0x80000000 \ | |
605 | | ((type) & 0xff) \ | |
606 | | ((small) ? 0x100 : 0) \ | |
607 | | ((ext) ? 0x200 : 0) \ | |
608 | | ((dslot) ? 0x400 : 0) \ | |
609 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
610 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
611 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
612 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
613 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
614 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
615 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
616 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
617 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
618 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
619 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
620 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
621 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
7e656649 RH |
622 | /* start-sanitize-branchbug4011 */ |
623 | /* The 4011 core has a bug in it's branch processing that | |
624 | an be avoided if branches never branches (where branches | |
625 | are defined as those starting with 'b'). We do this here | |
626 | by insuring that labels are not directly on branch instructions, | |
627 | and if they are inserting a no-op between the label and the | |
628 | branch. */ | |
629 | static int mips_fix_4011_branch_bug = 0; | |
630 | /* end-sanitize-branchbug4011 */ | |
0dd2d296 | 631 | \f |
3d3c5039 ILT |
632 | /* Prototypes for static functions. */ |
633 | ||
634 | #ifdef __STDC__ | |
635 | #define internalError() \ | |
48401fcf | 636 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
3d3c5039 | 637 | #else |
48401fcf | 638 | #define internalError() as_fatal (_("MIPS internal Error")); |
3d3c5039 ILT |
639 | #endif |
640 | ||
cc5703cd ILT |
641 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
642 | ||
becfe05e | 643 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 644 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 645 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 646 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
647 | static void append_insn PARAMS ((char *place, |
648 | struct mips_cl_insn * ip, | |
670a50eb | 649 | expressionS * p, |
867a58b3 ILT |
650 | bfd_reloc_code_real_type r, |
651 | boolean)); | |
4a1cb507 | 652 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 653 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 654 | #ifdef USE_STDARG |
0dd2d296 | 655 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
656 | const char *name, const char *fmt, |
657 | ...)); | |
c625fc23 JSC |
658 | #else |
659 | static void macro_build (); | |
660 | #endif | |
cc5703cd ILT |
661 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
662 | const char *, const char *, | |
663 | va_list)); | |
0dd2d296 ILT |
664 | static void macro_build_lui PARAMS ((char *place, int *counter, |
665 | expressionS * ep, int regnum)); | |
6e8dda9c | 666 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 667 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 668 | expressionS *)); |
d8a1c247 | 669 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 670 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 671 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 672 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
673 | #ifdef LOSING_COMPILER |
674 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
675 | #endif | |
670a50eb | 676 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 677 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
678 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
679 | boolean, boolean, unsigned long *, | |
680 | boolean *, unsigned short *)); | |
670a50eb ILT |
681 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
682 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 683 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 684 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
685 | static void s_align PARAMS ((int)); |
686 | static void s_change_sec PARAMS ((int)); | |
687 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 688 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 689 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
690 | static void s_option PARAMS ((int)); |
691 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
692 | static void s_abicalls PARAMS ((int)); |
693 | static void s_cpload PARAMS ((int)); | |
694 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
695 | static void s_gpword PARAMS ((int)); |
696 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 697 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
698 | static void md_obj_begin PARAMS ((void)); |
699 | static void md_obj_end PARAMS ((void)); | |
700 | static long get_number PARAMS ((void)); | |
701 | static void s_ent PARAMS ((int)); | |
702 | static void s_mipsend PARAMS ((int)); | |
703 | static void s_file PARAMS ((int)); | |
3c83da8a | 704 | static void s_mips_stab PARAMS ((int)); |
3c69baf9 | 705 | static void s_mips_weakext PARAMS ((int)); |
cc5703cd | 706 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 | 707 | |
3c69baf9 | 708 | |
aa2e0460 | 709 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
3d3c5039 ILT |
710 | \f |
711 | /* Pseudo-op table. | |
712 | ||
713 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
714 | should be defined here, but are currently unsupported: .alias, | |
715 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
716 | ||
717 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
718 | specific to the type of debugging information being generated, and | |
719 | should be defined by the object format: .aent, .begin, .bend, | |
720 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
721 | .vreg. | |
722 | ||
723 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
724 | not MIPS CPU specific, but are also not specific to the object file | |
725 | format. This file is probably the best place to define them, but | |
726 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
3c69baf9 | 727 | .struct. */ |
3d3c5039 | 728 | |
739708fa | 729 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 730 | { |
670a50eb ILT |
731 | /* MIPS specific pseudo-ops. */ |
732 | {"option", s_option, 0}, | |
733 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
734 | {"rdata", s_change_sec, 'r'}, |
735 | {"sdata", s_change_sec, 's'}, | |
736 | {"livereg", s_ignore, 0}, | |
739708fa KR |
737 | {"abicalls", s_abicalls, 0}, |
738 | {"cpload", s_cpload, 0}, | |
739 | {"cprestore", s_cprestore, 0}, | |
740 | {"gpword", s_gpword, 0}, | |
741 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 742 | {"insn", s_insn, 0}, |
3d3c5039 | 743 | |
670a50eb | 744 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 745 | chips. */ |
739708fa | 746 | {"asciiz", stringer, 1}, |
670a50eb ILT |
747 | {"bss", s_change_sec, 'b'}, |
748 | {"err", s_err, 0}, | |
749 | {"half", s_cons, 1}, | |
52aa70b5 | 750 | {"dword", s_cons, 3}, |
3c69baf9 | 751 | {"weakext", s_mips_weakext, 0}, |
3d3c5039 | 752 | |
670a50eb | 753 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 754 | here for one reason or another. */ |
670a50eb ILT |
755 | {"align", s_align, 0}, |
756 | {"byte", s_cons, 0}, | |
757 | {"data", s_change_sec, 'd'}, | |
becfe05e | 758 | {"double", s_float_cons, 'd'}, |
becfe05e | 759 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
760 | {"globl", s_mips_globl, 0}, |
761 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
762 | {"hword", s_cons, 1}, |
763 | {"int", s_cons, 2}, | |
764 | {"long", s_cons, 2}, | |
765 | {"octa", s_cons, 4}, | |
766 | {"quad", s_cons, 3}, | |
767 | {"short", s_cons, 1}, | |
768 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 769 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
770 | {"text", s_change_sec, 't'}, |
771 | {"word", s_cons, 2}, | |
739708fa KR |
772 | { 0 }, |
773 | }; | |
3d3c5039 | 774 | |
739708fa | 775 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 776 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 777 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 778 | {"aent", s_ent, 1}, |
9226253a | 779 | {"bgnb", s_ignore, 0}, |
670a50eb | 780 | {"end", s_mipsend, 0}, |
9226253a | 781 | {"endb", s_ignore, 0}, |
670a50eb ILT |
782 | {"ent", s_ent, 0}, |
783 | {"file", s_file, 0}, | |
784 | {"fmask", s_ignore, 'F'}, | |
785 | {"frame", s_ignore, 0}, | |
786 | {"loc", s_ignore, 0}, | |
787 | {"mask", s_ignore, 'R'}, | |
788 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
789 | { 0 }, |
790 | }; | |
61420a20 | 791 | |
739708fa KR |
792 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
793 | ||
794 | void | |
795 | mips_pop_insert () | |
796 | { | |
797 | pop_insert (mips_pseudo_table); | |
798 | if (! ECOFF_DEBUGGING) | |
799 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 800 | } |
3d3c5039 | 801 | \f |
fbcfacb7 ILT |
802 | /* Symbols labelling the current insn. */ |
803 | ||
804 | struct insn_label_list | |
805 | { | |
806 | struct insn_label_list *next; | |
807 | symbolS *label; | |
808 | }; | |
809 | ||
810 | static struct insn_label_list *insn_labels; | |
811 | static struct insn_label_list *free_insn_labels; | |
812 | ||
813 | static void mips_clear_insn_labels PARAMS ((void)); | |
814 | ||
815 | static inline void | |
816 | mips_clear_insn_labels () | |
817 | { | |
818 | register struct insn_label_list **pl; | |
819 | ||
820 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
821 | ; | |
822 | *pl = insn_labels; | |
823 | insn_labels = NULL; | |
824 | } | |
825 | \f | |
3d3c5039 ILT |
826 | static char *expr_end; |
827 | ||
867a58b3 ILT |
828 | /* Expressions which appear in instructions. These are set by |
829 | mips_ip. */ | |
830 | ||
3d3c5039 ILT |
831 | static expressionS imm_expr; |
832 | static expressionS offset_expr; | |
867a58b3 ILT |
833 | |
834 | /* Relocs associated with imm_expr and offset_expr. */ | |
835 | ||
3d3c5039 ILT |
836 | static bfd_reloc_code_real_type imm_reloc; |
837 | static bfd_reloc_code_real_type offset_reloc; | |
838 | ||
867a58b3 ILT |
839 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
840 | ||
841 | static boolean imm_unmatched_hi; | |
842 | ||
8728fa92 ILT |
843 | /* These are set by mips16_ip if an explicit extension is used. */ |
844 | ||
845 | static boolean mips16_small, mips16_ext; | |
846 | ||
3d3c5039 ILT |
847 | /* |
848 | * This function is called once, at assembler startup time. It should | |
849 | * set up all the tables, etc. that the MD part of the assembler will need. | |
850 | */ | |
851 | void | |
670a50eb | 852 | md_begin () |
3d3c5039 | 853 | { |
0dd2d296 | 854 | boolean ok = false; |
604633ae | 855 | register const char *retval = NULL; |
670a50eb | 856 | register unsigned int i = 0; |
1724c79e GRK |
857 | const char *cpu; |
858 | char *a = NULL; | |
aa2e0460 | 859 | int broken = 0; |
3d3c5039 | 860 | |
1724c79e GRK |
861 | cpu = TARGET_CPU; |
862 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 863 | { |
1724c79e GRK |
864 | a = xmalloc (sizeof TARGET_CPU); |
865 | strcpy (a, TARGET_CPU); | |
866 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
867 | cpu = a; | |
868 | } | |
8c63448a | 869 | |
1724c79e GRK |
870 | if (mips_cpu < 0) |
871 | { | |
872 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
873 | just the generic 'mips', in which case set mips_cpu based | |
874 | on the given ISA, if any. */ | |
8c63448a ILT |
875 | |
876 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
877 | { |
878 | if (mips_opts.isa < 0) | |
879 | mips_cpu = 3000; | |
880 | ||
881 | else if (mips_opts.isa == 2) | |
882 | mips_cpu = 6000; | |
883 | ||
884 | else if (mips_opts.isa == 3) | |
885 | mips_cpu = 4000; | |
886 | ||
887 | else if (mips_opts.isa == 4) | |
888 | mips_cpu = 8000; | |
889 | ||
890 | else | |
891 | mips_cpu = 3000; | |
892 | } | |
893 | ||
5c6f5923 | 894 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 895 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
896 | /* start-sanitize-tx19 */ |
897 | || strcmp (cpu, "r1900") == 0 | |
898 | || strcmp (cpu, "mipstx19") == 0 | |
899 | /* end-sanitize-tx19 */ | |
900 | ) | |
1724c79e GRK |
901 | mips_cpu = 3900; |
902 | ||
8c63448a ILT |
903 | else if (strcmp (cpu, "r6000") == 0 |
904 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
905 | mips_cpu = 6000; |
906 | ||
8c63448a ILT |
907 | else if (strcmp (cpu, "mips64") == 0 |
908 | || strcmp (cpu, "r4000") == 0 | |
909 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
910 | mips_cpu = 4000; |
911 | ||
8c63448a | 912 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
913 | mips_cpu = 4400; |
914 | ||
8c63448a ILT |
915 | else if (strcmp (cpu, "mips64orion") == 0 |
916 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
917 | mips_cpu = 4600; |
918 | ||
b2b8c24e | 919 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
920 | mips_cpu = 4650; |
921 | ||
c625fc23 | 922 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
923 | mips_cpu = 4300; |
924 | ||
2d035a50 GRK |
925 | /* start-sanitize-vr4320 */ |
926 | else if (strcmp (cpu, "r4320") == 0 | |
927 | || strcmp (cpu, "mips64vr4320") == 0) | |
928 | mips_cpu = 4320; | |
929 | ||
930 | /* end-sanitize-vr4320 */ | |
e599ab16 | 931 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
932 | mips_cpu = 4100; |
933 | ||
e532b44c | 934 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
935 | mips_cpu = 4010; |
936 | ||
4ebda395 GRK |
937 | /* start-sanitize-tx49 */ |
938 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 939 | mips_cpu = 4900; |
4ebda395 | 940 | /* end-sanitize-tx49 */ |
1724c79e | 941 | |
517078c1 ILT |
942 | else if (strcmp (cpu, "r5000") == 0 |
943 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
944 | mips_cpu = 5000; |
945 | ||
6b34ac5a | 946 | /* start-sanitize-cygnus */ |
aa2e0460 | 947 | else if (strcmp (cpu, "r5400") == 0 |
b3ed1af3 KR |
948 | || strcmp (cpu, "mips64vr5400") == 0) |
949 | mips_cpu = 5400; | |
6b34ac5a | 950 | /* end-sanitize-cygnus */ |
1724c79e | 951 | |
276c2d7d GRK |
952 | /* start-sanitize-r5900 */ |
953 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
954 | || strcmp (cpu, "mips64r5900") == 0) |
955 | mips_cpu = 5900; | |
276c2d7d | 956 | /* end-sanitize-r5900 */ |
1724c79e | 957 | |
d8a1c247 KR |
958 | else if (strcmp (cpu, "r8000") == 0 |
959 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
960 | mips_cpu = 8000; |
961 | ||
d8a1c247 | 962 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
963 | mips_cpu = 10000; |
964 | ||
cc5703cd | 965 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
966 | mips_cpu = 0; /* FIXME */ |
967 | ||
8358c818 | 968 | else |
1724c79e GRK |
969 | mips_cpu = 3000; |
970 | } | |
8c63448a | 971 | |
1724c79e GRK |
972 | if (mips_opts.isa == -1) |
973 | { | |
974 | if (mips_cpu == 3000 | |
975 | || mips_cpu == 3900) | |
976 | mips_opts.isa = 1; | |
977 | ||
978 | else if (mips_cpu == 6000 | |
979 | || mips_cpu == 4010) | |
980 | mips_opts.isa = 2; | |
981 | ||
982 | else if (mips_cpu == 4000 | |
983 | || mips_cpu == 4100 | |
984 | || mips_cpu == 4400 | |
985 | || mips_cpu == 4300 | |
2d035a50 GRK |
986 | /* start-sanitize-vr4320 */ |
987 | || mips_cpu == 4320 | |
059a6388 | 988 | /* end-sanitize-vr4320 */ |
1724c79e GRK |
989 | || mips_cpu == 4600 |
990 | /* start-sanitize-tx49 */ | |
991 | || mips_cpu == 4900 | |
992 | /* end-sanitize-tx49 */ | |
993 | /* start-sanitize-r5900 */ | |
994 | || mips_cpu == 5900 | |
995 | /* end-sanitize-r5900 */ | |
996 | || mips_cpu == 4650) | |
997 | mips_opts.isa = 3; | |
998 | ||
999 | else if (mips_cpu == 5000 | |
6b34ac5a | 1000 | /* start-sanitize-cygnus */ |
1724c79e | 1001 | || mips_cpu == 5400 |
6b34ac5a | 1002 | /* end-sanitize-cygnus */ |
1724c79e GRK |
1003 | || mips_cpu == 8000 |
1004 | || mips_cpu == 10000) | |
1005 | mips_opts.isa = 4; | |
1006 | ||
1007 | else | |
1008 | mips_opts.isa = 1; | |
8358c818 ILT |
1009 | } |
1010 | ||
3c83da8a | 1011 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
1012 | { |
1013 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 1014 | mips_opts.mips16 = 1; |
cc5703cd | 1015 | else |
3c83da8a | 1016 | mips_opts.mips16 = 0; |
cc5703cd ILT |
1017 | } |
1018 | ||
b2b8c24e | 1019 | if (mips_4650 < 0) |
1724c79e | 1020 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 1021 | |
e532b44c | 1022 | if (mips_4010 < 0) |
1724c79e | 1023 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 1024 | |
c625fc23 | 1025 | if (mips_4100 < 0) |
1724c79e | 1026 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 1027 | |
2d035a50 GRK |
1028 | /* start-sanitize-vr4320 */ |
1029 | if (mips_4320 < 0) | |
1030 | mips_4320 = (mips_cpu == 4320); | |
1031 | ||
1032 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 1033 | /* start-sanitize-cygnus */ |
aa2e0460 | 1034 | if (mips_5400 < 0) |
1724c79e | 1035 | mips_5400 = (mips_cpu == 5400); |
6b34ac5a | 1036 | /* end-sanitize-cygnus */ |
1724c79e | 1037 | |
276c2d7d GRK |
1038 | /* start-sanitize-r5900 */ |
1039 | if (mips_5900 < 0) | |
1724c79e | 1040 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 1041 | /* end-sanitize-r5900 */ |
1724c79e | 1042 | |
5c6f5923 | 1043 | if (mips_3900 < 0) |
1724c79e GRK |
1044 | mips_3900 = (mips_cpu == 3900); |
1045 | ||
42444087 GRK |
1046 | /* start-sanitize-tx49 */ |
1047 | if (mips_4900 < 0) | |
1048 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 1049 | |
42444087 | 1050 | /* end-sanitize-tx49 */ |
1724c79e GRK |
1051 | |
1052 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1053 | if necessary. */ | |
1054 | cpu = NULL; | |
1055 | if (a != NULL) | |
1056 | { | |
1057 | free (a); | |
1058 | a = NULL; | |
1059 | } | |
1060 | ||
3c83da8a | 1061 | if (mips_opts.isa < 2 && mips_trap) |
48401fcf | 1062 | as_bad (_("trap exception not supported at ISA 1")); |
8ea7f4e8 | 1063 | |
9a1f3160 | 1064 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1065 | { |
9a1f3160 JL |
1066 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1067 | } | |
1068 | else | |
1069 | { | |
1070 | switch (mips_opts.isa) | |
1071 | { | |
1072 | case 1: | |
1073 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1074 | break; | |
1075 | case 2: | |
1076 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1077 | break; | |
1078 | case 3: | |
1079 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1080 | break; | |
1081 | case 4: | |
1082 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1083 | break; | |
1084 | } | |
97f99d11 | 1085 | } |
9a1f3160 | 1086 | |
97f99d11 | 1087 | if (! ok) |
48401fcf | 1088 | as_warn (_("Could not set architecture and machine")); |
97f99d11 | 1089 | |
3c83da8a | 1090 | file_mips_isa = mips_opts.isa; |
1051c97f | 1091 | |
13fe1379 ILT |
1092 | op_hash = hash_new (); |
1093 | ||
670a50eb ILT |
1094 | for (i = 0; i < NUMOPCODES;) |
1095 | { | |
1096 | const char *name = mips_opcodes[i].name; | |
1097 | ||
604633ae | 1098 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1099 | if (retval != NULL) |
670a50eb | 1100 | { |
48401fcf | 1101 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
670a50eb | 1102 | mips_opcodes[i].name, retval); |
aa2e0460 | 1103 | /* Probably a memory allocation problem? Give up now. */ |
48401fcf | 1104 | as_fatal (_("Broken assembler. No assembly attempted.")); |
670a50eb ILT |
1105 | } |
1106 | do | |
1107 | { | |
aa2e0460 | 1108 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1109 | { |
aa2e0460 KR |
1110 | if (!validate_mips_insn (&mips_opcodes[i])) |
1111 | broken = 1; | |
3d3c5039 | 1112 | } |
670a50eb ILT |
1113 | ++i; |
1114 | } | |
1115 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1116 | } |
1117 | ||
cc5703cd ILT |
1118 | mips16_op_hash = hash_new (); |
1119 | ||
1120 | i = 0; | |
1121 | while (i < bfd_mips16_num_opcodes) | |
1122 | { | |
1123 | const char *name = mips16_opcodes[i].name; | |
1124 | ||
1125 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1126 | if (retval != NULL) | |
48401fcf | 1127 | as_fatal (_("internal: can't hash `%s': %s"), |
cc5703cd ILT |
1128 | mips16_opcodes[i].name, retval); |
1129 | do | |
1130 | { | |
1131 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1132 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1133 | != mips16_opcodes[i].match)) | |
aa2e0460 | 1134 | { |
48401fcf | 1135 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
aa2e0460 KR |
1136 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
1137 | broken = 1; | |
1138 | } | |
cc5703cd ILT |
1139 | ++i; |
1140 | } | |
1141 | while (i < bfd_mips16_num_opcodes | |
1142 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1143 | } | |
1144 | ||
aa2e0460 | 1145 | if (broken) |
48401fcf | 1146 | as_fatal (_("Broken assembler. No assembly attempted.")); |
aa2e0460 | 1147 | |
ebf28372 ILT |
1148 | /* We add all the general register names to the symbol table. This |
1149 | helps us detect invalid uses of them. */ | |
1150 | for (i = 0; i < 32; i++) | |
1151 | { | |
1152 | char buf[5]; | |
1153 | ||
1154 | sprintf (buf, "$%d", i); | |
1155 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1156 | &zero_address_frag)); | |
1157 | } | |
1158 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1159 | &zero_address_frag)); | |
1160 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1161 | &zero_address_frag)); | |
1162 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1163 | &zero_address_frag)); | |
1164 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1165 | &zero_address_frag)); | |
1166 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1167 | &zero_address_frag)); | |
1168 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1169 | &zero_address_frag)); | |
1170 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1171 | &zero_address_frag)); | |
1172 | ||
4a1cb507 | 1173 | mips_no_prev_insn (false); |
becfe05e | 1174 | |
1aa6938e ILT |
1175 | mips_gprmask = 0; |
1176 | mips_cprmask[0] = 0; | |
1177 | mips_cprmask[1] = 0; | |
1178 | mips_cprmask[2] = 0; | |
1179 | mips_cprmask[3] = 0; | |
1180 | ||
8358c818 | 1181 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1182 | record_alignment (text_section, 2); |
8358c818 | 1183 | |
1dc1e798 KR |
1184 | if (USE_GLOBAL_POINTER_OPT) |
1185 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1186 | |
1dc1e798 KR |
1187 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1188 | { | |
08e17202 ILT |
1189 | /* On a native system, sections must be aligned to 16 byte |
1190 | boundaries. When configured for an embedded ELF target, we | |
1191 | don't bother. */ | |
1192 | if (strcmp (TARGET_OS, "elf") != 0) | |
1193 | { | |
1194 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1195 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1196 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1197 | } | |
1dc1e798 KR |
1198 | |
1199 | /* Create a .reginfo section for register masks and a .mdebug | |
1200 | section for debugging information. */ | |
1201 | { | |
1202 | segT seg; | |
1203 | subsegT subseg; | |
b3a64736 | 1204 | flagword flags; |
1dc1e798 KR |
1205 | segT sec; |
1206 | ||
1207 | seg = now_seg; | |
1208 | subseg = now_subseg; | |
1dc1e798 | 1209 | |
b3a64736 ILT |
1210 | /* The ABI says this section should be loaded so that the |
1211 | running program can access it. However, we don't load it | |
1212 | if we are configured for an embedded target */ | |
1213 | flags = SEC_READONLY | SEC_DATA; | |
1214 | if (strcmp (TARGET_OS, "elf") != 0) | |
1215 | flags |= SEC_ALLOC | SEC_LOAD; | |
1216 | ||
87178180 ILT |
1217 | if (! mips_64) |
1218 | { | |
1219 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1220 | |
b3a64736 ILT |
1221 | |
1222 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1223 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1224 | ||
f2a663d3 | 1225 | #ifdef OBJ_ELF |
87178180 | 1226 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1227 | #endif |
87178180 ILT |
1228 | } |
1229 | else | |
1230 | { | |
1231 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1232 | .reginfo section. */ | |
1233 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1234 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1235 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1236 | ||
1237 | #ifdef OBJ_ELF | |
1238 | /* Set up the option header. */ | |
1239 | { | |
1240 | Elf_Internal_Options opthdr; | |
1241 | char *f; | |
1242 | ||
1243 | opthdr.kind = ODK_REGINFO; | |
1244 | opthdr.size = (sizeof (Elf_External_Options) | |
1245 | + sizeof (Elf64_External_RegInfo)); | |
1246 | opthdr.section = 0; | |
1247 | opthdr.info = 0; | |
1248 | f = frag_more (sizeof (Elf_External_Options)); | |
1249 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1250 | (Elf_External_Options *) f); | |
1251 | ||
1252 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1253 | } | |
1254 | #endif | |
1255 | } | |
f2a663d3 | 1256 | |
739708fa KR |
1257 | if (ECOFF_DEBUGGING) |
1258 | { | |
1259 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1260 | (void) bfd_set_section_flags (stdoutput, sec, | |
1261 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1262 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1263 | } | |
0dd2d296 | 1264 | |
1dc1e798 KR |
1265 | subseg_set (seg, subseg); |
1266 | } | |
1267 | } | |
f2a663d3 | 1268 | |
739708fa KR |
1269 | if (! ECOFF_DEBUGGING) |
1270 | md_obj_begin (); | |
3d3c5039 ILT |
1271 | } |
1272 | ||
1273 | void | |
13fe1379 | 1274 | md_mips_end () |
3d3c5039 | 1275 | { |
739708fa KR |
1276 | if (! ECOFF_DEBUGGING) |
1277 | md_obj_end (); | |
3d3c5039 ILT |
1278 | } |
1279 | ||
1280 | void | |
670a50eb ILT |
1281 | md_assemble (str) |
1282 | char *str; | |
3d3c5039 | 1283 | { |
670a50eb | 1284 | struct mips_cl_insn insn; |
3d3c5039 | 1285 | |
5ac34ac3 | 1286 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1287 | imm_reloc = BFD_RELOC_UNUSED; |
1288 | imm_unmatched_hi = false; | |
5ac34ac3 | 1289 | offset_expr.X_op = O_absent; |
867a58b3 | 1290 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1291 | |
3c83da8a | 1292 | if (mips_opts.mips16) |
cc5703cd ILT |
1293 | mips16_ip (str, &insn); |
1294 | else | |
efec4a28 | 1295 | { |
9218cee0 | 1296 | mips_ip (str, &insn); |
48401fcf | 1297 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
efec4a28 DP |
1298 | str, insn.insn_opcode)); |
1299 | } | |
cc5703cd | 1300 | |
670a50eb ILT |
1301 | if (insn_error) |
1302 | { | |
1303 | as_bad ("%s `%s'", insn_error, str); | |
1304 | return; | |
1305 | } | |
cc5703cd | 1306 | |
670a50eb ILT |
1307 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1308 | { | |
3c83da8a | 1309 | if (mips_opts.mips16) |
cc5703cd ILT |
1310 | mips16_macro (&insn); |
1311 | else | |
1312 | macro (&insn); | |
3d3c5039 | 1313 | } |
670a50eb ILT |
1314 | else |
1315 | { | |
5ac34ac3 | 1316 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1317 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1318 | imm_unmatched_hi); | |
5ac34ac3 | 1319 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1320 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1321 | else |
867a58b3 | 1322 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1323 | } |
1324 | } | |
1325 | ||
cc5703cd ILT |
1326 | /* See whether instruction IP reads register REG. CLASS is the type |
1327 | of register. */ | |
becfe05e ILT |
1328 | |
1329 | static int | |
cc5703cd | 1330 | insn_uses_reg (ip, reg, class) |
becfe05e | 1331 | struct mips_cl_insn *ip; |
604633ae | 1332 | unsigned int reg; |
cc5703cd | 1333 | enum mips_regclass class; |
becfe05e | 1334 | { |
cc5703cd ILT |
1335 | if (class == MIPS16_REG) |
1336 | { | |
3c83da8a | 1337 | assert (mips_opts.mips16); |
cc5703cd ILT |
1338 | reg = mips16_to_32_reg_map[reg]; |
1339 | class = MIPS_GR_REG; | |
1340 | } | |
1341 | ||
becfe05e | 1342 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1343 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1344 | return 0; |
1345 | ||
cc5703cd | 1346 | if (class == MIPS_FP_REG) |
becfe05e | 1347 | { |
3c83da8a | 1348 | assert (! mips_opts.mips16); |
becfe05e ILT |
1349 | /* If we are called with either $f0 or $f1, we must check $f0. |
1350 | This is not optimal, because it will introduce an unnecessary | |
1351 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1352 | need to distinguish reading both $f0 and $f1 or just one of | |
1353 | them. Note that we don't have to check the other way, | |
1354 | because there is no instruction that sets both $f0 and $f1 | |
1355 | and requires a delay. */ | |
1356 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1357 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1358 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1359 | return 1; |
1360 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1361 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1362 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1363 | return 1; |
1364 | } | |
3c83da8a | 1365 | else if (! mips_opts.mips16) |
becfe05e ILT |
1366 | { |
1367 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1368 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1369 | return 1; | |
1370 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1371 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1372 | return 1; | |
1373 | } | |
cc5703cd ILT |
1374 | else |
1375 | { | |
1376 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1377 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1378 | & MIPS16OP_MASK_RX)] | |
1379 | == reg)) | |
cc5703cd ILT |
1380 | return 1; |
1381 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1382 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1383 | & MIPS16OP_MASK_RY)] | |
1384 | == reg)) | |
cc5703cd ILT |
1385 | return 1; |
1386 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1387 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1388 | & MIPS16OP_MASK_MOVE32Z)] | |
1389 | == reg)) | |
cc5703cd ILT |
1390 | return 1; |
1391 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1392 | return 1; | |
1393 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1394 | return 1; | |
1395 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1396 | return 1; | |
1397 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1398 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1399 | & MIPS16OP_MASK_REGR32) == reg) | |
1400 | return 1; | |
1401 | } | |
becfe05e ILT |
1402 | |
1403 | return 0; | |
1404 | } | |
1405 | ||
fb251650 ILT |
1406 | /* This function returns true if modifying a register requires a |
1407 | delay. */ | |
1408 | ||
1409 | static int | |
1410 | reg_needs_delay (reg) | |
1411 | int reg; | |
1412 | { | |
1413 | unsigned long prev_pinfo; | |
1414 | ||
1415 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1416 | if (! mips_opts.noreorder |
1417 | && mips_opts.isa < 4 | |
fb251650 | 1418 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1419 | || (! gpr_interlocks |
fb251650 ILT |
1420 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1421 | { | |
1422 | /* A load from a coprocessor or from memory. All load | |
1423 | delays delay the use of general register rt for one | |
1424 | instruction on the r3000. The r6000 and r4000 use | |
1425 | interlocks. */ | |
efec4a28 | 1426 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1427 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1428 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1429 | return 1; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | ||
3c83da8a JW |
1435 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1436 | handle them specially, such as generating jalx instructions when | |
1437 | needed. We also make them odd for the duration of the assembly, in | |
1438 | order to generate the right sort of code. We will make them even | |
1439 | in the adjust_symtab routine, while leaving them marked. This is | |
1440 | convenient for the debugger and the disassembler. The linker knows | |
1441 | to make them odd again. */ | |
1442 | ||
1443 | static void | |
1444 | mips16_mark_labels () | |
1445 | { | |
1446 | if (mips_opts.mips16) | |
1447 | { | |
1448 | struct insn_label_list *l; | |
1449 | ||
1450 | for (l = insn_labels; l != NULL; l = l->next) | |
1451 | { | |
68952421 | 1452 | #ifdef OBJ_ELF |
3c83da8a JW |
1453 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1454 | S_SET_OTHER (l->label, STO_MIPS16); | |
1455 | #endif | |
1456 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1457 | ++l->label->sy_value.X_add_number; | |
1458 | } | |
1459 | } | |
1460 | } | |
1461 | ||
0dd2d296 ILT |
1462 | /* Output an instruction. PLACE is where to put the instruction; if |
1463 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1464 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1465 | used with RELOC_TYPE. */ | |
3d3c5039 | 1466 | |
3d3c5039 | 1467 | static void |
867a58b3 | 1468 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1469 | char *place; |
670a50eb ILT |
1470 | struct mips_cl_insn *ip; |
1471 | expressionS *address_expr; | |
1472 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1473 | boolean unmatched_hi; |
3d3c5039 | 1474 | { |
1aa6938e | 1475 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1476 | char *f; |
becfe05e ILT |
1477 | fixS *fixp; |
1478 | int nops = 0; | |
7e656649 RH |
1479 | /* start-sanitize-branchbug4011 */ |
1480 | int label_nop = 0; /* True if a no-op needs to appear between | |
1481 | the current insn and the current labels */ | |
1482 | /* end-sanitize-branchbug4011 */ | |
3d3c5039 | 1483 | |
3c83da8a JW |
1484 | /* Mark instruction labels in mips16 mode. */ |
1485 | if (mips_opts.mips16) | |
1486 | mips16_mark_labels (); | |
fbcfacb7 | 1487 | |
1aa6938e ILT |
1488 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1489 | pinfo = ip->insn_mo->pinfo; | |
1490 | ||
3c83da8a | 1491 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1492 | { |
4a1cb507 ILT |
1493 | int prev_prev_nop; |
1494 | ||
becfe05e | 1495 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1496 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1497 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1498 | (1) a load from memory delay |
1499 | (2) a load from a coprocessor delay | |
1500 | (3) an unconditional branch delay | |
1501 | (4) a conditional branch delay | |
1502 | (5) a move to coprocessor register delay | |
1503 | (6) a load coprocessor register from memory delay | |
1504 | (7) a coprocessor condition code delay | |
1505 | (8) a HI/LO special register delay | |
becfe05e ILT |
1506 | |
1507 | There are a lot of optimizations we could do that we don't. | |
1508 | In particular, we do not, in general, reorder instructions. | |
1509 | If you use gcc with optimization, it will reorder | |
1510 | instructions and generally do much more optimization then we | |
1511 | do here; repeating all that work in the assembler would only | |
1512 | benefit hand written assembly code, and does not seem worth | |
1513 | it. */ | |
1514 | ||
1515 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1516 | #define emit_nop() \ |
3c83da8a | 1517 | (mips_opts.mips16 \ |
cc5703cd ILT |
1518 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1519 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1520 | |
1521 | /* The previous insn might require a delay slot, depending upon | |
1522 | the contents of the current insn. */ | |
3c83da8a JW |
1523 | if (! mips_opts.mips16 |
1524 | && mips_opts.isa < 4 | |
5af96dce ILT |
1525 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1526 | && ! cop_interlocks) | |
5c6f5923 | 1527 | || (! gpr_interlocks |
d8a1c247 | 1528 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1529 | { |
1530 | /* A load from a coprocessor or from memory. All load | |
1531 | delays delay the use of general register rt for one | |
1532 | instruction on the r3000. The r6000 and r4000 use | |
1533 | interlocks. */ | |
efec4a28 | 1534 | /* Itbl support may require additional care here. */ |
1aa6938e | 1535 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1536 | if (mips_optimize == 0 |
1537 | || insn_uses_reg (ip, | |
1538 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1539 | & OP_MASK_RT), | |
cc5703cd | 1540 | MIPS_GR_REG)) |
becfe05e ILT |
1541 | ++nops; |
1542 | } | |
3c83da8a JW |
1543 | else if (! mips_opts.mips16 |
1544 | && mips_opts.isa < 4 | |
5af96dce ILT |
1545 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1546 | && ! cop_interlocks) | |
3c83da8a | 1547 | || (mips_opts.isa < 2 |
d8a1c247 | 1548 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1549 | { |
1550 | /* A generic coprocessor delay. The previous instruction | |
1551 | modified a coprocessor general or control register. If | |
1552 | it modified a control register, we need to avoid any | |
1553 | coprocessor instruction (this is probably not always | |
1554 | required, but it sometimes is). If it modified a general | |
1555 | register, we avoid using that register. | |
1556 | ||
8358c818 ILT |
1557 | On the r6000 and r4000 loading a coprocessor register |
1558 | from memory is interlocked, and does not require a delay. | |
1559 | ||
becfe05e ILT |
1560 | This case is not handled very well. There is no special |
1561 | knowledge of CP0 handling, and the coprocessors other | |
1562 | than the floating point unit are not distinguished at | |
1563 | all. */ | |
efec4a28 DP |
1564 | /* Itbl support may require additional care here. FIXME! |
1565 | Need to modify this to include knowledge about | |
1566 | user specified delays! */ | |
1aa6938e | 1567 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1568 | { |
0aa07269 ILT |
1569 | if (mips_optimize == 0 |
1570 | || insn_uses_reg (ip, | |
8358c818 ILT |
1571 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1572 | & OP_MASK_FT), | |
cc5703cd | 1573 | MIPS_FP_REG)) |
becfe05e ILT |
1574 | ++nops; |
1575 | } | |
1aa6938e | 1576 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1577 | { |
0aa07269 ILT |
1578 | if (mips_optimize == 0 |
1579 | || insn_uses_reg (ip, | |
8358c818 ILT |
1580 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1581 | & OP_MASK_FS), | |
cc5703cd | 1582 | MIPS_FP_REG)) |
becfe05e ILT |
1583 | ++nops; |
1584 | } | |
1585 | else | |
1586 | { | |
1587 | /* We don't know exactly what the previous instruction | |
1588 | does. If the current instruction uses a coprocessor | |
1589 | register, we must insert a NOP. If previous | |
1590 | instruction may set the condition codes, and the | |
1591 | current instruction uses them, we must insert two | |
1592 | NOPS. */ | |
efec4a28 | 1593 | /* Itbl support may require additional care here. */ |
0aa07269 | 1594 | if (mips_optimize == 0 |
1aa6938e ILT |
1595 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1596 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1597 | nops += 2; |
1aa6938e | 1598 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1599 | ++nops; |
1600 | } | |
1601 | } | |
3c83da8a JW |
1602 | else if (! mips_opts.mips16 |
1603 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1604 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1605 | && ! cop_interlocks) | |
becfe05e ILT |
1606 | { |
1607 | /* The previous instruction sets the coprocessor condition | |
1608 | codes, but does not require a general coprocessor delay | |
1609 | (this means it is a floating point comparison | |
1610 | instruction). If this instruction uses the condition | |
1611 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1612 | /* Itbl support may require additional care here. */ |
0aa07269 | 1613 | if (mips_optimize == 0 |
1aa6938e | 1614 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1615 | ++nops; |
1616 | } | |
1aa6938e | 1617 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1618 | { |
1619 | /* The previous instruction reads the LO register; if the | |
1620 | current instruction writes to the LO register, we must | |
517078c1 | 1621 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1622 | if (! hilo_interlocks |
b2b8c24e ILT |
1623 | && (mips_optimize == 0 |
1624 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1625 | nops += 2; |
1626 | } | |
1627 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1628 | { | |
1629 | /* The previous instruction reads the HI register; if the | |
1630 | current instruction writes to the HI register, we must | |
517078c1 | 1631 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1632 | if (! hilo_interlocks |
b2b8c24e ILT |
1633 | && (mips_optimize == 0 |
1634 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1635 | nops += 2; |
1636 | } | |
1637 | ||
4a1cb507 ILT |
1638 | /* If the previous instruction was in a noreorder section, then |
1639 | we don't want to insert the nop after all. */ | |
efec4a28 | 1640 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1641 | if (prev_insn_unreordered) |
1642 | nops = 0; | |
1643 | ||
becfe05e ILT |
1644 | /* There are two cases which require two intervening |
1645 | instructions: 1) setting the condition codes using a move to | |
1646 | coprocessor instruction which requires a general coprocessor | |
1647 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1648 | or LO register and then writing to it (except on processors |
1649 | which have interlocks). If we are not already emitting a NOP | |
1650 | instruction, we must check for these cases compared to the | |
1651 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1652 | if ((! mips_opts.mips16 |
1653 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1654 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1655 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1656 | && (pinfo & INSN_READ_COND_CODE) | |
1657 | && ! cop_interlocks) | |
1658 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1659 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1660 | && ! hilo_interlocks) |
4a1cb507 ILT |
1661 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1662 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1663 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1664 | prev_prev_nop = 1; |
1665 | else | |
1666 | prev_prev_nop = 0; | |
1667 | ||
1668 | if (prev_prev_insn_unreordered) | |
1669 | prev_prev_nop = 0; | |
1670 | ||
1671 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1672 | ++nops; |
1673 | ||
0dd2d296 ILT |
1674 | /* If we are being given a nop instruction, don't bother with |
1675 | one of the nops we would otherwise output. This will only | |
1676 | happen when a nop instruction is used with mips_optimize set | |
1677 | to 0. */ | |
4a1cb507 | 1678 | if (nops > 0 |
3c83da8a JW |
1679 | && ! mips_opts.noreorder |
1680 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1681 | --nops; |
1682 | ||
7e656649 RH |
1683 | /* start-sanitize-branchbug4011 */ |
1684 | /* If we have a label on a branch insn, we need at least one no-op | |
1685 | between the label and the branch. The pinfo flags in this test | |
1686 | must cover all the kinds of branches. */ | |
1687 | if (mips_fix_4011_branch_bug | |
1688 | && insn_labels != NULL | |
1689 | && (ip->insn_mo->pinfo | |
1690 | & (INSN_UNCOND_BRANCH_DELAY | |
1691 | |INSN_COND_BRANCH_DELAY | |
1692 | |INSN_COND_BRANCH_LIKELY))) | |
1693 | { | |
1694 | label_nop = 1; | |
1695 | ||
1696 | /* Make sure we've got at least one nop. */ | |
1697 | if (nops == 0) | |
1698 | nops = 1; | |
1699 | } | |
1700 | ||
1701 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1702 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1703 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1704 | { |
5af96dce ILT |
1705 | fragS *old_frag; |
1706 | unsigned long old_frag_offset; | |
8c63448a | 1707 | int i; |
fbcfacb7 | 1708 | struct insn_label_list *l; |
8c63448a | 1709 | |
5af96dce ILT |
1710 | old_frag = frag_now; |
1711 | old_frag_offset = frag_now_fix (); | |
1712 | ||
7e656649 RH |
1713 | /* start-sanitize-branchbug4011 */ |
1714 | /* Emit the nops that should be before the label. */ | |
1715 | if (label_nop) | |
1716 | nops -= 1; | |
1717 | ||
1718 | /* end-sanitize-branchbug4011 */ | |
8c63448a | 1719 | for (i = 0; i < nops; i++) |
becfe05e | 1720 | emit_nop (); |
5af96dce | 1721 | |
af255ca0 | 1722 | if (listing) |
546f5536 ILT |
1723 | { |
1724 | listing_prev_line (); | |
1725 | /* We may be at the start of a variant frag. In case we | |
1726 | are, make sure there is enough space for the frag | |
1727 | after the frags created by listing_prev_line. The | |
1728 | argument to frag_grow here must be at least as large | |
1729 | as the argument to all other calls to frag_grow in | |
1730 | this file. We don't have to worry about being in the | |
1731 | middle of a variant frag, because the variants insert | |
1732 | all needed nop instructions themselves. */ | |
1733 | frag_grow (40); | |
1734 | } | |
5af96dce | 1735 | |
fbcfacb7 | 1736 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1737 | { |
fbcfacb7 ILT |
1738 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1739 | l->label->sy_frag = frag_now; | |
1740 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1741 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1742 | if (mips_opts.mips16) |
fbcfacb7 | 1743 | ++l->label->sy_value.X_add_number; |
becfe05e | 1744 | } |
5af96dce ILT |
1745 | |
1746 | #ifndef NO_ECOFF_DEBUGGING | |
1747 | if (ECOFF_DEBUGGING) | |
1748 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1749 | #endif | |
7e656649 RH |
1750 | /* start-sanitize-branchbug4011 */ |
1751 | if (label_nop) | |
1752 | { | |
1753 | /* Emit the nop after the label, and return the | |
1754 | nop count to it's proper value. */ | |
1755 | emit_nop (); | |
1756 | nops += 1; | |
1757 | } | |
1758 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1759 | } |
4a1cb507 ILT |
1760 | else if (prev_nop_frag != NULL) |
1761 | { | |
1762 | /* We have a frag holding nops we may be able to remove. If | |
1763 | we don't need any nops, we can decrease the size of | |
1764 | prev_nop_frag by the size of one instruction. If we do | |
1765 | need some nops, we count them in prev_nops_required. */ | |
1766 | if (prev_nop_frag_since == 0) | |
1767 | { | |
1768 | if (nops == 0) | |
1769 | { | |
3c83da8a | 1770 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1771 | --prev_nop_frag_holds; |
1772 | } | |
1773 | else | |
1774 | prev_nop_frag_required += nops; | |
1775 | } | |
1776 | else | |
1777 | { | |
1778 | if (prev_prev_nop == 0) | |
1779 | { | |
3c83da8a | 1780 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1781 | --prev_nop_frag_holds; |
1782 | } | |
1783 | else | |
1784 | ++prev_nop_frag_required; | |
1785 | } | |
1786 | ||
1787 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1788 | prev_nop_frag = NULL; | |
1789 | ||
1790 | ++prev_nop_frag_since; | |
1791 | ||
1792 | /* Sanity check: by the time we reach the second instruction | |
1793 | after prev_nop_frag, we should have used up all the nops | |
1794 | one way or another. */ | |
1795 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1796 | } | |
becfe05e | 1797 | } |
4a1cb507 | 1798 | |
cc5703cd ILT |
1799 | if (reloc_type > BFD_RELOC_UNUSED) |
1800 | { | |
1801 | /* We need to set up a variant frag. */ | |
3c83da8a | 1802 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1803 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1804 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1805 | mips16_small, mips16_ext, |
1806 | (prev_pinfo | |
1807 | & INSN_UNCOND_BRANCH_DELAY), | |
1808 | (prev_insn_reloc_type | |
1809 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1810 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1811 | (char *) NULL); |
1812 | } | |
1813 | else if (place != NULL) | |
0dd2d296 | 1814 | f = place; |
3c83da8a JW |
1815 | else if (mips_opts.mips16 |
1816 | && ! ip->use_extend | |
1817 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1818 | { |
1819 | /* Make sure there is enough room to swap this instruction with | |
1820 | a following jump instruction. */ | |
1821 | frag_grow (6); | |
1822 | f = frag_more (2); | |
1823 | } | |
cc5703cd | 1824 | else |
035936da | 1825 | { |
3c83da8a JW |
1826 | if (mips_opts.mips16 |
1827 | && mips_opts.noreorder | |
035936da | 1828 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
48401fcf | 1829 | as_warn (_("extended instruction in delay slot")); |
035936da ILT |
1830 | |
1831 | f = frag_more (4); | |
1832 | } | |
1833 | ||
becfe05e | 1834 | fixp = NULL; |
cc5703cd | 1835 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1836 | { |
5ac34ac3 | 1837 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1838 | { |
1839 | switch (reloc_type) | |
1840 | { | |
3d3c5039 | 1841 | case BFD_RELOC_32: |
670a50eb ILT |
1842 | ip->insn_opcode |= address_expr->X_add_number; |
1843 | break; | |
3d3c5039 ILT |
1844 | |
1845 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1846 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1847 | break; | |
3d3c5039 ILT |
1848 | |
1849 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 | 1850 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1851 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1852 | (unsigned long) address_expr->X_add_number); |
5e1e8f23 ILT |
1853 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1854 | break; | |
1855 | ||
cc5703cd | 1856 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 | 1857 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1858 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1859 | (unsigned long) address_expr->X_add_number); |
cc5703cd ILT |
1860 | ip->insn_opcode |= |
1861 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1862 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1863 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1864 | break; | |
1865 | ||
3c69baf9 | 1866 | /* start-sanitize-r5900 */ |
0bc0e337 JL |
1867 | case BFD_RELOC_MIPS15_S3: |
1868 | ip->insn_opcode |= ((imm_expr.X_add_number & 0x7fff) >> 3) << 6; | |
1869 | break; | |
3c69baf9 | 1870 | /* end-sanitize-r5900 */ |
0bc0e337 | 1871 | |
3d3c5039 | 1872 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1873 | goto need_reloc; |
3d3c5039 ILT |
1874 | |
1875 | default: | |
670a50eb | 1876 | internalError (); |
3d3c5039 | 1877 | } |
670a50eb ILT |
1878 | } |
1879 | else | |
1880 | { | |
3d3c5039 | 1881 | need_reloc: |
0dd2d296 ILT |
1882 | /* Don't generate a reloc if we are writing into a variant |
1883 | frag. */ | |
1884 | if (place == NULL) | |
867a58b3 ILT |
1885 | { |
1886 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1887 | address_expr, | |
1888 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1889 | reloc_type); | |
1890 | if (unmatched_hi) | |
1891 | { | |
1892 | struct mips_hi_fixup *hi_fixup; | |
1893 | ||
1894 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1895 | hi_fixup = ((struct mips_hi_fixup *) | |
1896 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1897 | hi_fixup->fixp = fixp; | |
1898 | hi_fixup->seg = now_seg; | |
1899 | hi_fixup->next = mips_hi_fixup_list; | |
1900 | mips_hi_fixup_list = hi_fixup; | |
1901 | } | |
1902 | } | |
3d3c5039 ILT |
1903 | } |
1904 | } | |
becfe05e | 1905 | |
3c83da8a | 1906 | if (! mips_opts.mips16) |
cc5703cd | 1907 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1908 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1909 | { | |
1910 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1911 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1912 | } | |
cc5703cd ILT |
1913 | else |
1914 | { | |
1915 | if (ip->use_extend) | |
1916 | { | |
1917 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1918 | f += 2; | |
1919 | } | |
1920 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1921 | } | |
670a50eb | 1922 | |
1aa6938e | 1923 | /* Update the register mask information. */ |
3c83da8a | 1924 | if (! mips_opts.mips16) |
cc5703cd ILT |
1925 | { |
1926 | if (pinfo & INSN_WRITE_GPR_D) | |
1927 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1928 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1929 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1930 | if (pinfo & INSN_READ_GPR_S) | |
1931 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1932 | if (pinfo & INSN_WRITE_GPR_31) | |
1933 | mips_gprmask |= 1 << 31; | |
1934 | if (pinfo & INSN_WRITE_FPR_D) | |
1935 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1936 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1937 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1938 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1939 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1940 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1941 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1942 | if (pinfo & INSN_COP) | |
1943 | { | |
efec4a28 DP |
1944 | /* We don't keep enough information to sort these cases out. |
1945 | The itbl support does keep this information however, although | |
1946 | we currently don't support itbl fprmats as part of the cop | |
1947 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1948 | } |
1949 | /* Never set the bit for $0, which is always zero. */ | |
1950 | mips_gprmask &=~ 1 << 0; | |
1951 | } | |
1952 | else | |
1aa6938e | 1953 | { |
cc5703cd ILT |
1954 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1955 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1956 | & MIPS16OP_MASK_RX); | |
1957 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1958 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1959 | & MIPS16OP_MASK_RY); | |
1960 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1961 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1962 | & MIPS16OP_MASK_RZ); | |
1963 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1964 | mips_gprmask |= 1 << TREG; | |
1965 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1966 | mips_gprmask |= 1 << SP; | |
1967 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1968 | mips_gprmask |= 1 << RA; | |
1969 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1970 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1971 | if (pinfo & MIPS16_INSN_READ_Z) | |
1972 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1973 | & MIPS16OP_MASK_MOVE32Z); | |
1974 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1975 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1976 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1977 | } |
1aa6938e | 1978 | |
3c83da8a | 1979 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1980 | { |
becfe05e ILT |
1981 | /* Filling the branch delay slot is more complex. We try to |
1982 | switch the branch with the previous instruction, which we can | |
1983 | do if the previous instruction does not set up a condition | |
1984 | that the branch tests and if the branch is not itself the | |
1985 | target of any branch. */ | |
1aa6938e ILT |
1986 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1987 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1988 | { |
0aa07269 | 1989 | if (mips_optimize < 2 |
19ed8960 ILT |
1990 | /* If we have seen .set volatile or .set nomove, don't |
1991 | optimize. */ | |
3c83da8a | 1992 | || mips_opts.nomove != 0 |
4e95866e ILT |
1993 | /* If we had to emit any NOP instructions, then we |
1994 | already know we can not swap. */ | |
1995 | || nops != 0 | |
becfe05e ILT |
1996 | /* If we don't even know the previous insn, we can not |
1997 | swap. */ | |
1998 | || ! prev_insn_valid | |
1999 | /* If the previous insn is already in a branch delay | |
2000 | slot, then we can not swap. */ | |
2001 | || prev_insn_is_delay_slot | |
7e656649 RH |
2002 | /* start-sanitize-branchbug4011 */ |
2003 | /* We can't swap the branch back to a previous label */ | |
2004 | || (mips_fix_4011_branch_bug && prev_insn_labels) | |
2005 | /* end-sanitize-branchbug4011 */ | |
4e95866e ILT |
2006 | /* If the previous previous insn was in a .set |
2007 | noreorder, we can't swap. Actually, the MIPS | |
2008 | assembler will swap in this situation. However, gcc | |
2009 | configured -with-gnu-as will generate code like | |
2010 | .set noreorder | |
2011 | lw $4,XXX | |
2012 | .set reorder | |
2013 | INSN | |
2014 | bne $4,$0,foo | |
2015 | in which we can not swap the bne and INSN. If gcc is | |
2016 | not configured -with-gnu-as, it does not output the | |
2017 | .set pseudo-ops. We don't have to check | |
2018 | prev_insn_unreordered, because prev_insn_valid will | |
2019 | be 0 in that case. We don't want to use | |
2020 | prev_prev_insn_valid, because we do want to be able | |
2021 | to swap at the start of a function. */ | |
2022 | || prev_prev_insn_unreordered | |
becfe05e ILT |
2023 | /* If the branch is itself the target of a branch, we |
2024 | can not swap. We cheat on this; all we check for is | |
2025 | whether there is a label on this instruction. If | |
2026 | there are any branches to anything other than a | |
2027 | label, users must use .set noreorder. */ | |
fbcfacb7 | 2028 | || insn_labels != NULL |
777ad64d | 2029 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
2030 | can not do the swap. This does not apply to the |
2031 | mips16, which uses variant frags for different | |
2032 | purposes. */ | |
3c83da8a | 2033 | || (! mips_opts.mips16 |
cc5703cd | 2034 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
2035 | /* If the branch reads the condition codes, we don't |
2036 | even try to swap, because in the sequence | |
2037 | ctc1 $X,$31 | |
2038 | INSN | |
2039 | INSN | |
2040 | bc1t LABEL | |
2041 | we can not swap, and I don't feel like handling that | |
2042 | case. */ | |
3c83da8a JW |
2043 | || (! mips_opts.mips16 |
2044 | && mips_opts.isa < 4 | |
d8a1c247 | 2045 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
2046 | /* We can not swap with an instruction that requires a |
2047 | delay slot, becase the target of the branch might | |
2048 | interfere with that instruction. */ | |
3c83da8a JW |
2049 | || (! mips_opts.mips16 |
2050 | && mips_opts.isa < 4 | |
d8a1c247 | 2051 | && (prev_pinfo |
efec4a28 | 2052 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
2053 | & (INSN_LOAD_COPROC_DELAY |
2054 | | INSN_COPROC_MOVE_DELAY | |
2055 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 2056 | || (! hilo_interlocks |
b2b8c24e ILT |
2057 | && (prev_pinfo |
2058 | & (INSN_READ_LO | |
2059 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2060 | || (! mips_opts.mips16 |
2061 | && ! gpr_interlocks | |
2062 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2063 | || (! mips_opts.mips16 |
2064 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
2065 | /* Itbl support may require additional care here. */ |
2066 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 2067 | /* We can not swap with a branch instruction. */ |
1aa6938e | 2068 | || (prev_pinfo |
6e8dda9c ILT |
2069 | & (INSN_UNCOND_BRANCH_DELAY |
2070 | | INSN_COND_BRANCH_DELAY | |
2071 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
2072 | /* We do not swap with a trap instruction, since it |
2073 | complicates trap handlers to have the trap | |
2074 | instruction be in a delay slot. */ | |
1aa6938e | 2075 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
2076 | /* If the branch reads a register that the previous |
2077 | instruction sets, we can not swap. */ | |
3c83da8a | 2078 | || (! mips_opts.mips16 |
cc5703cd | 2079 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2080 | && insn_uses_reg (ip, |
2081 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2082 | & OP_MASK_RT), | |
cc5703cd | 2083 | MIPS_GR_REG)) |
3c83da8a | 2084 | || (! mips_opts.mips16 |
cc5703cd | 2085 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2086 | && insn_uses_reg (ip, |
2087 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2088 | & OP_MASK_RD), | |
cc5703cd | 2089 | MIPS_GR_REG)) |
3c83da8a | 2090 | || (mips_opts.mips16 |
cc5703cd ILT |
2091 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2092 | && insn_uses_reg (ip, | |
2093 | ((prev_insn.insn_opcode | |
2094 | >> MIPS16OP_SH_RX) | |
2095 | & MIPS16OP_MASK_RX), | |
2096 | MIPS16_REG)) | |
2097 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2098 | && insn_uses_reg (ip, | |
2099 | ((prev_insn.insn_opcode | |
2100 | >> MIPS16OP_SH_RY) | |
2101 | & MIPS16OP_MASK_RY), | |
2102 | MIPS16_REG)) | |
2103 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2104 | && insn_uses_reg (ip, | |
2105 | ((prev_insn.insn_opcode | |
2106 | >> MIPS16OP_SH_RZ) | |
2107 | & MIPS16OP_MASK_RZ), | |
2108 | MIPS16_REG)) | |
2109 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2110 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2111 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2112 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2113 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2114 | && insn_uses_reg (ip, | |
2115 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2116 | insn_opcode), | |
2117 | MIPS_GR_REG)))) | |
1849d646 ILT |
2118 | /* If the branch writes a register that the previous |
2119 | instruction sets, we can not swap (we know that | |
2120 | branches write only to RD or to $31). */ | |
3c83da8a | 2121 | || (! mips_opts.mips16 |
cc5703cd | 2122 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2123 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2124 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2125 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2126 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2127 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2128 | & OP_MASK_RT) | |
2129 | == 31)))) | |
3c83da8a | 2130 | || (! mips_opts.mips16 |
cc5703cd | 2131 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2132 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2133 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2134 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2135 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2136 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2137 | & OP_MASK_RD) | |
2138 | == 31)))) | |
3c83da8a | 2139 | || (mips_opts.mips16 |
cc5703cd ILT |
2140 | && (pinfo & MIPS16_INSN_WRITE_31) |
2141 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2142 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2143 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2144 | == RA)))) | |
becfe05e ILT |
2145 | /* If the branch writes a register that the previous |
2146 | instruction reads, we can not swap (we know that | |
2147 | branches only write to RD or to $31). */ | |
3c83da8a | 2148 | || (! mips_opts.mips16 |
cc5703cd | 2149 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2150 | && insn_uses_reg (&prev_insn, |
2151 | ((ip->insn_opcode >> OP_SH_RD) | |
2152 | & OP_MASK_RD), | |
cc5703cd | 2153 | MIPS_GR_REG)) |
3c83da8a | 2154 | || (! mips_opts.mips16 |
cc5703cd ILT |
2155 | && (pinfo & INSN_WRITE_GPR_31) |
2156 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2157 | || (mips_opts.mips16 |
cc5703cd ILT |
2158 | && (pinfo & MIPS16_INSN_WRITE_31) |
2159 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2160 | /* If we are generating embedded PIC code, the branch |
2161 | might be expanded into a sequence which uses $at, so | |
2162 | we can't swap with an instruction which reads it. */ | |
2163 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2164 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2165 | /* If the previous previous instruction has a load |
2166 | delay, and sets a register that the branch reads, we | |
2167 | can not swap. */ | |
3c83da8a JW |
2168 | || (! mips_opts.mips16 |
2169 | && mips_opts.isa < 4 | |
efec4a28 | 2170 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2171 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2172 | || (! gpr_interlocks |
d8a1c247 KR |
2173 | && (prev_prev_insn.insn_mo->pinfo |
2174 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2175 | && insn_uses_reg (ip, |
2176 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2177 | & OP_MASK_RT), | |
cc5703cd | 2178 | MIPS_GR_REG)) |
d31a3f5e ILT |
2179 | /* If one instruction sets a condition code and the |
2180 | other one uses a condition code, we can not swap. */ | |
2181 | || ((pinfo & INSN_READ_COND_CODE) | |
2182 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2183 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2184 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2185 | /* If the previous instruction uses the PC, we can not | |
2186 | swap. */ | |
3c83da8a | 2187 | || (mips_opts.mips16 |
cc5703cd ILT |
2188 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2189 | /* If the previous instruction was extended, we can not | |
2190 | swap. */ | |
3c83da8a | 2191 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2192 | /* If the previous instruction had a fixup in mips16 |
2193 | mode, we can not swap. This normally means that the | |
2194 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2195 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2196 | { |
2197 | /* We could do even better for unconditional branches to | |
2198 | portions of this object file; we could pick up the | |
2199 | instruction at the destination, put it in the delay | |
2200 | slot, and bump the destination address. */ | |
2201 | emit_nop (); | |
2202 | /* Update the previous insn information. */ | |
2203 | prev_prev_insn = *ip; | |
2204 | prev_insn.insn_mo = &dummy_opcode; | |
2205 | } | |
2206 | else | |
2207 | { | |
becfe05e | 2208 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2209 | if (! mips_opts.mips16) |
cc5703cd ILT |
2210 | { |
2211 | char *prev_f; | |
2212 | char temp[4]; | |
2213 | ||
2214 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2215 | memcpy (temp, prev_f, 4); | |
2216 | memcpy (prev_f, f, 4); | |
2217 | memcpy (f, temp, 4); | |
2218 | if (prev_insn_fixp) | |
2219 | { | |
2220 | prev_insn_fixp->fx_frag = frag_now; | |
2221 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2222 | } | |
2223 | if (fixp) | |
2224 | { | |
2225 | fixp->fx_frag = prev_insn_frag; | |
2226 | fixp->fx_where = prev_insn_where; | |
2227 | } | |
2228 | } | |
cc5703cd | 2229 | else |
becfe05e | 2230 | { |
cc5703cd ILT |
2231 | char *prev_f; |
2232 | char temp[2]; | |
2233 | ||
2234 | assert (prev_insn_fixp == NULL); | |
2235 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2236 | memcpy (temp, prev_f, 2); | |
2237 | memcpy (prev_f, f, 2); | |
2238 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2239 | { |
2240 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2241 | memcpy (f, temp, 2); | |
2242 | } | |
cc5703cd ILT |
2243 | else |
2244 | { | |
2245 | memcpy (f, f + 2, 2); | |
2246 | memcpy (f + 2, temp, 2); | |
2247 | } | |
2248 | if (fixp) | |
2249 | { | |
2250 | fixp->fx_frag = prev_insn_frag; | |
2251 | fixp->fx_where = prev_insn_where; | |
2252 | } | |
becfe05e | 2253 | } |
cc5703cd | 2254 | |
becfe05e ILT |
2255 | /* Update the previous insn information; leave prev_insn |
2256 | unchanged. */ | |
2257 | prev_prev_insn = *ip; | |
2258 | } | |
2259 | prev_insn_is_delay_slot = 1; | |
2260 | ||
2261 | /* If that was an unconditional branch, forget the previous | |
2262 | insn information. */ | |
1aa6938e | 2263 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2264 | { |
2265 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2266 | prev_insn.insn_mo = &dummy_opcode; | |
2267 | } | |
a677feeb ILT |
2268 | |
2269 | prev_insn_fixp = NULL; | |
2270 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2271 | prev_insn_extended = 0; | |
becfe05e | 2272 | } |
1aa6938e | 2273 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2274 | { |
2275 | /* We don't yet optimize a branch likely. What we should do | |
2276 | is look at the target, copy the instruction found there | |
2277 | into the delay slot, and increment the branch to jump to | |
2278 | the next instruction. */ | |
2279 | emit_nop (); | |
2280 | /* Update the previous insn information. */ | |
2281 | prev_prev_insn = *ip; | |
2282 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2283 | prev_insn_fixp = NULL; |
2284 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2285 | prev_insn_extended = 0; | |
8358c818 | 2286 | } |
becfe05e | 2287 | else |
670a50eb | 2288 | { |
becfe05e ILT |
2289 | /* Update the previous insn information. */ |
2290 | if (nops > 0) | |
2291 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2292 | else | |
2293 | prev_prev_insn = prev_insn; | |
2294 | prev_insn = *ip; | |
2295 | ||
2296 | /* Any time we see a branch, we always fill the delay slot | |
2297 | immediately; since this insn is not a branch, we know it | |
2298 | is not in a delay slot. */ | |
2299 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2300 | |
2301 | prev_insn_fixp = fixp; | |
2302 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2303 | if (mips_opts.mips16) |
a677feeb ILT |
2304 | prev_insn_extended = (ip->use_extend |
2305 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2306 | } |
2307 | ||
4e95866e ILT |
2308 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2309 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2310 | prev_insn_frag = frag_now; |
2311 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e | 2312 | prev_insn_valid = 1; |
7e656649 RH |
2313 | /* start-sanitize-branchbug4011 */ |
2314 | prev_insn_labels = !! insn_labels; | |
2315 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 2316 | } |
fbcfacb7 | 2317 | else if (place == NULL) |
a677feeb | 2318 | { |
fbcfacb7 | 2319 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2320 | reordering, in order to determine the base address for mips16 |
2321 | PC relative relocs. */ | |
4a1cb507 | 2322 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2323 | prev_insn = *ip; |
2324 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2325 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2326 | prev_insn_unreordered = 1; | |
7e656649 RH |
2327 | /* start-sanitize-branchbug4011 */ |
2328 | prev_insn_labels = !! insn_labels; | |
2329 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2330 | } |
3d3c5039 | 2331 | |
becfe05e | 2332 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2333 | mips_clear_insn_labels (); |
b073d428 ILT |
2334 | |
2335 | /* We must ensure that a fixup associated with an unmatched %hi | |
2336 | reloc does not become a variant frag. Otherwise, the | |
2337 | rearrangement of %hi relocs in frob_file may confuse | |
2338 | tc_gen_reloc. */ | |
2339 | if (unmatched_hi) | |
2340 | { | |
2341 | frag_wane (frag_now); | |
2342 | frag_new (0); | |
2343 | } | |
becfe05e ILT |
2344 | } |
2345 | ||
2346 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2347 | label. If PRESERVE is non-zero, it remembers enough information to |
2348 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2349 | |
2350 | static void | |
4a1cb507 ILT |
2351 | mips_no_prev_insn (preserve) |
2352 | int preserve; | |
becfe05e | 2353 | { |
4a1cb507 ILT |
2354 | if (! preserve) |
2355 | { | |
2356 | prev_insn.insn_mo = &dummy_opcode; | |
2357 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2358 | prev_nop_frag = NULL; | |
2359 | prev_nop_frag_holds = 0; | |
2360 | prev_nop_frag_required = 0; | |
2361 | prev_nop_frag_since = 0; | |
2362 | } | |
becfe05e ILT |
2363 | prev_insn_valid = 0; |
2364 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2365 | prev_insn_unreordered = 0; |
cc5703cd | 2366 | prev_insn_extended = 0; |
7e656649 RH |
2367 | /* start-sanitize-branchbug4011 */ |
2368 | prev_insn_labels = 0; | |
2369 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2370 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2371 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2372 | mips_clear_insn_labels (); |
becfe05e ILT |
2373 | } |
2374 | ||
2375 | /* This function must be called whenever we turn on noreorder or emit | |
2376 | something other than instructions. It inserts any NOPS which might | |
2377 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2378 | kept for the previous instructions. The INSNS parameter is true if |
2379 | instructions are to follow. */ | |
becfe05e ILT |
2380 | |
2381 | static void | |
fbcfacb7 ILT |
2382 | mips_emit_delays (insns) |
2383 | boolean insns; | |
becfe05e | 2384 | { |
3c83da8a | 2385 | if (! mips_opts.noreorder) |
becfe05e | 2386 | { |
4a1cb507 | 2387 | int nops; |
becfe05e | 2388 | |
4a1cb507 | 2389 | nops = 0; |
3c83da8a JW |
2390 | if ((! mips_opts.mips16 |
2391 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2392 | && (! cop_interlocks |
2393 | && (prev_insn.insn_mo->pinfo | |
2394 | & (INSN_LOAD_COPROC_DELAY | |
2395 | | INSN_COPROC_MOVE_DELAY | |
2396 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2397 | || (! hilo_interlocks |
b2b8c24e ILT |
2398 | && (prev_insn.insn_mo->pinfo |
2399 | & (INSN_READ_LO | |
2400 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2401 | || (! mips_opts.mips16 |
2402 | && ! gpr_interlocks | |
2403 | && (prev_insn.insn_mo->pinfo | |
2404 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2405 | || (! mips_opts.mips16 |
2406 | && mips_opts.isa < 2 | |
8358c818 | 2407 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2408 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2409 | { |
efec4a28 | 2410 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2411 | ++nops; |
3c83da8a JW |
2412 | if ((! mips_opts.mips16 |
2413 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2414 | && (! cop_interlocks |
2415 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2416 | || (! hilo_interlocks |
b2b8c24e ILT |
2417 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2418 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2419 | ++nops; |
2420 | ||
2421 | if (prev_insn_unreordered) | |
2422 | nops = 0; | |
becfe05e | 2423 | } |
3c83da8a JW |
2424 | else if ((! mips_opts.mips16 |
2425 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2426 | && (! cop_interlocks |
2427 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2428 | || (! hilo_interlocks |
b2b8c24e ILT |
2429 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2430 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2431 | { |
efec4a28 | 2432 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2433 | if (! prev_prev_insn_unreordered) |
2434 | ++nops; | |
2435 | } | |
2436 | ||
2437 | if (nops > 0) | |
670a50eb | 2438 | { |
fbcfacb7 ILT |
2439 | struct insn_label_list *l; |
2440 | ||
4a1cb507 ILT |
2441 | if (insns) |
2442 | { | |
2443 | /* Record the frag which holds the nop instructions, so | |
2444 | that we can remove them if we don't need them. */ | |
3c83da8a | 2445 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2446 | prev_nop_frag = frag_now; |
2447 | prev_nop_frag_holds = nops; | |
2448 | prev_nop_frag_required = 0; | |
2449 | prev_nop_frag_since = 0; | |
2450 | } | |
2451 | ||
2452 | for (; nops > 0; --nops) | |
2453 | emit_nop (); | |
2454 | ||
2455 | if (insns) | |
2456 | { | |
2457 | /* Move on to a new frag, so that it is safe to simply | |
2458 | decrease the size of prev_nop_frag. */ | |
2459 | frag_wane (frag_now); | |
2460 | frag_new (0); | |
2461 | } | |
2462 | ||
fbcfacb7 | 2463 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2464 | { |
fbcfacb7 ILT |
2465 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2466 | l->label->sy_frag = frag_now; | |
2467 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2468 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2469 | if (mips_opts.mips16) |
fbcfacb7 | 2470 | ++l->label->sy_value.X_add_number; |
becfe05e | 2471 | } |
3d3c5039 ILT |
2472 | } |
2473 | } | |
0221ddf7 | 2474 | |
3c83da8a JW |
2475 | /* Mark instruction labels in mips16 mode. */ |
2476 | if (mips_opts.mips16 && insns) | |
2477 | mips16_mark_labels (); | |
fbcfacb7 | 2478 | |
4a1cb507 | 2479 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2480 | } |
2481 | ||
670a50eb ILT |
2482 | /* Build an instruction created by a macro expansion. This is passed |
2483 | a pointer to the count of instructions created so far, an | |
2484 | expression, the name of the instruction to build, an operand format | |
2485 | string, and corresponding arguments. */ | |
2486 | ||
1dc1e798 | 2487 | #ifdef USE_STDARG |
3d3c5039 | 2488 | static void |
0dd2d296 ILT |
2489 | macro_build (char *place, |
2490 | int *counter, | |
670a50eb | 2491 | expressionS * ep, |
3d3c5039 ILT |
2492 | const char *name, |
2493 | const char *fmt, | |
2494 | ...) | |
1dc1e798 | 2495 | #else |
3d3c5039 | 2496 | static void |
0dd2d296 ILT |
2497 | macro_build (place, counter, ep, name, fmt, va_alist) |
2498 | char *place; | |
3d3c5039 ILT |
2499 | int *counter; |
2500 | expressionS *ep; | |
2501 | const char *name; | |
2502 | const char *fmt; | |
2503 | va_dcl | |
1dc1e798 | 2504 | #endif |
3d3c5039 | 2505 | { |
670a50eb ILT |
2506 | struct mips_cl_insn insn; |
2507 | bfd_reloc_code_real_type r; | |
2508 | va_list args; | |
931a1858 | 2509 | int insn_isa; |
3d3c5039 | 2510 | |
1dc1e798 | 2511 | #ifdef USE_STDARG |
670a50eb | 2512 | va_start (args, fmt); |
3d3c5039 | 2513 | #else |
670a50eb | 2514 | va_start (args); |
3d3c5039 ILT |
2515 | #endif |
2516 | ||
670a50eb ILT |
2517 | /* |
2518 | * If the macro is about to expand into a second instruction, | |
2519 | * print a warning if needed. We need to pass ip as a parameter | |
2520 | * to generate a better warning message here... | |
2521 | */ | |
3c83da8a | 2522 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2523 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2524 | |
0dd2d296 ILT |
2525 | if (place == NULL) |
2526 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2527 | |
3c83da8a | 2528 | if (mips_opts.mips16) |
cc5703cd ILT |
2529 | { |
2530 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2531 | va_end (args); | |
2532 | return; | |
2533 | } | |
2534 | ||
670a50eb ILT |
2535 | r = BFD_RELOC_UNUSED; |
2536 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2537 | assert (insn.insn_mo); | |
2538 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2539 | ||
931a1858 JL |
2540 | /* Search until we get a match for NAME. */ |
2541 | while (1) | |
670a50eb | 2542 | { |
1c6f3441 | 2543 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2544 | insn_isa = 1; |
2545 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2546 | insn_isa = 2; | |
2547 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2548 | insn_isa = 3; | |
2549 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2550 | insn_isa = 4; | |
2551 | else | |
2552 | insn_isa = 15; | |
2553 | ||
a652f74c ILT |
2554 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2555 | && insn.insn_mo->pinfo != INSN_MACRO | |
2556 | && (insn_isa <= mips_opts.isa | |
2557 | || (mips_4650 | |
2558 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2559 | || (mips_4010 | |
2560 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2561 | || (mips_4100 | |
2562 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
2d035a50 GRK |
2563 | /* start-sanitize-vr4320 */ |
2564 | || (mips_4320 | |
2565 | && (insn.insn_mo->membership & INSN_4320) != 0) | |
2566 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
2567 | /* start-sanitize-tx49 */ |
2568 | || (mips_4900 | |
2569 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2570 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2571 | /* start-sanitize-r5900 */ |
2572 | || (mips_5900 | |
2573 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2574 | /* end-sanitize-r5900 */ | |
6b34ac5a | 2575 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
2576 | || (mips_5400 |
2577 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
6b34ac5a | 2578 | /* end-sanitize-cygnus */ |
a652f74c ILT |
2579 | || (mips_3900 |
2580 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2581 | /* start-sanitize-r5900 */ | |
2582 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2583 | /* end-sanitize-r5900 */ | |
2584 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2585 | break; | |
931a1858 | 2586 | |
a652f74c ILT |
2587 | ++insn.insn_mo; |
2588 | assert (insn.insn_mo->name); | |
2589 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2590 | } |
931a1858 | 2591 | |
670a50eb ILT |
2592 | insn.insn_opcode = insn.insn_mo->match; |
2593 | for (;;) | |
2594 | { | |
2595 | switch (*fmt++) | |
2596 | { | |
3d3c5039 | 2597 | case '\0': |
670a50eb | 2598 | break; |
3d3c5039 ILT |
2599 | |
2600 | case ',': | |
2601 | case '(': | |
2602 | case ')': | |
670a50eb | 2603 | continue; |
3d3c5039 ILT |
2604 | |
2605 | case 't': | |
2606 | case 'w': | |
918692a5 | 2607 | case 'E': |
670a50eb ILT |
2608 | insn.insn_opcode |= va_arg (args, int) << 16; |
2609 | continue; | |
3d3c5039 ILT |
2610 | |
2611 | case 'c': | |
2612 | case 'T': | |
2613 | case 'W': | |
670a50eb ILT |
2614 | insn.insn_opcode |= va_arg (args, int) << 16; |
2615 | continue; | |
3d3c5039 ILT |
2616 | |
2617 | case 'd': | |
918692a5 | 2618 | case 'G': |
670a50eb ILT |
2619 | insn.insn_opcode |= va_arg (args, int) << 11; |
2620 | continue; | |
3d3c5039 ILT |
2621 | |
2622 | case 'V': | |
2623 | case 'S': | |
670a50eb ILT |
2624 | insn.insn_opcode |= va_arg (args, int) << 11; |
2625 | continue; | |
3d3c5039 | 2626 | |
ff3a5c18 ILT |
2627 | case 'z': |
2628 | continue; | |
2629 | ||
3d3c5039 | 2630 | case '<': |
670a50eb ILT |
2631 | insn.insn_opcode |= va_arg (args, int) << 6; |
2632 | continue; | |
3d3c5039 ILT |
2633 | |
2634 | case 'D': | |
670a50eb ILT |
2635 | insn.insn_opcode |= va_arg (args, int) << 6; |
2636 | continue; | |
3d3c5039 | 2637 | |
918692a5 ILT |
2638 | case 'B': |
2639 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2640 | continue; | |
2641 | ||
40f0c904 FCE |
2642 | case 'q': |
2643 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2644 | continue; | |
2645 | ||
3d3c5039 ILT |
2646 | case 'b': |
2647 | case 's': | |
2648 | case 'r': | |
2649 | case 'v': | |
670a50eb ILT |
2650 | insn.insn_opcode |= va_arg (args, int) << 21; |
2651 | continue; | |
3d3c5039 ILT |
2652 | |
2653 | case 'i': | |
2654 | case 'j': | |
2655 | case 'o': | |
9226253a | 2656 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2657 | assert (r == BFD_RELOC_MIPS_GPREL |
2658 | || r == BFD_RELOC_MIPS_LITERAL | |
2659 | || r == BFD_RELOC_LO16 | |
2660 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2661 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2662 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2663 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2664 | || (ep->X_op == O_subtract |
2665 | && now_seg == text_section | |
ecd4ca1c | 2666 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2667 | continue; |
3d3c5039 | 2668 | |
6e8dda9c | 2669 | case 'u': |
ecd4ca1c ILT |
2670 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2671 | assert (ep != NULL | |
2672 | && (ep->X_op == O_constant | |
2673 | || (ep->X_op == O_symbol | |
2674 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2675 | || r == BFD_RELOC_HI16 |
2676 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2677 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2678 | || (ep->X_op == O_subtract |
2679 | && now_seg == text_section | |
ecd4ca1c ILT |
2680 | && r == BFD_RELOC_PCREL_HI16_S))); |
2681 | if (ep->X_op == O_constant) | |
2682 | { | |
2683 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2684 | ep = NULL; | |
2685 | r = BFD_RELOC_UNUSED; | |
2686 | } | |
6e8dda9c ILT |
2687 | continue; |
2688 | ||
3d3c5039 | 2689 | case 'p': |
670a50eb ILT |
2690 | assert (ep != NULL); |
2691 | /* | |
2692 | * This allows macro() to pass an immediate expression for | |
2693 | * creating short branches without creating a symbol. | |
2694 | * Note that the expression still might come from the assembly | |
2695 | * input, in which case the value is not checked for range nor | |
2696 | * is a relocation entry generated (yuck). | |
2697 | */ | |
5ac34ac3 | 2698 | if (ep->X_op == O_constant) |
670a50eb ILT |
2699 | { |
2700 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2701 | ep = NULL; | |
2702 | } | |
2703 | else | |
2704 | r = BFD_RELOC_16_PCREL_S2; | |
2705 | continue; | |
3d3c5039 | 2706 | |
9226253a ILT |
2707 | case 'a': |
2708 | assert (ep != NULL); | |
2709 | r = BFD_RELOC_MIPS_JMP; | |
2710 | continue; | |
2711 | ||
65d2c7d3 JL |
2712 | case 'C': |
2713 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2714 | continue; | |
2715 | ||
3d3c5039 | 2716 | default: |
670a50eb | 2717 | internalError (); |
3d3c5039 | 2718 | } |
670a50eb | 2719 | break; |
3d3c5039 | 2720 | } |
670a50eb ILT |
2721 | va_end (args); |
2722 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2723 | ||
867a58b3 | 2724 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2725 | } |
2726 | ||
cc5703cd ILT |
2727 | static void |
2728 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2729 | char *place; | |
2730 | int *counter; | |
2731 | expressionS *ep; | |
2732 | const char *name; | |
2733 | const char *fmt; | |
2734 | va_list args; | |
2735 | { | |
2736 | struct mips_cl_insn insn; | |
2737 | bfd_reloc_code_real_type r; | |
2738 | ||
2739 | r = BFD_RELOC_UNUSED; | |
2740 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2741 | assert (insn.insn_mo); | |
2742 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2743 | ||
2744 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2745 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2746 | { | |
2747 | ++insn.insn_mo; | |
2748 | assert (insn.insn_mo->name); | |
2749 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2750 | } | |
2751 | ||
2752 | insn.insn_opcode = insn.insn_mo->match; | |
2753 | insn.use_extend = false; | |
2754 | ||
2755 | for (;;) | |
2756 | { | |
2757 | int c; | |
2758 | ||
2759 | c = *fmt++; | |
2760 | switch (c) | |
2761 | { | |
2762 | case '\0': | |
2763 | break; | |
2764 | ||
2765 | case ',': | |
2766 | case '(': | |
2767 | case ')': | |
2768 | continue; | |
2769 | ||
2770 | case 'y': | |
2771 | case 'w': | |
2772 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2773 | continue; | |
2774 | ||
2775 | case 'x': | |
2776 | case 'v': | |
2777 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2778 | continue; | |
2779 | ||
2780 | case 'z': | |
2781 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2782 | continue; | |
2783 | ||
2784 | case 'Z': | |
2785 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2786 | continue; | |
2787 | ||
2788 | case '0': | |
2789 | case 'S': | |
2790 | case 'P': | |
2791 | case 'R': | |
2792 | continue; | |
2793 | ||
2794 | case 'X': | |
2795 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2796 | continue; | |
2797 | ||
2798 | case 'Y': | |
2799 | { | |
2800 | int regno; | |
2801 | ||
2802 | regno = va_arg (args, int); | |
2803 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2804 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2805 | } | |
2806 | continue; | |
2807 | ||
2808 | case '<': | |
2809 | case '>': | |
2810 | case '4': | |
2811 | case '5': | |
2812 | case 'H': | |
2813 | case 'W': | |
2814 | case 'D': | |
2815 | case 'j': | |
2816 | case '8': | |
2817 | case 'V': | |
2818 | case 'C': | |
2819 | case 'U': | |
2820 | case 'k': | |
2821 | case 'K': | |
2822 | case 'p': | |
2823 | case 'q': | |
2824 | { | |
2825 | assert (ep != NULL); | |
2826 | ||
2827 | if (ep->X_op != O_constant) | |
2828 | r = BFD_RELOC_UNUSED + c; | |
2829 | else | |
2830 | { | |
15e69f98 ILT |
2831 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2832 | false, false, &insn.insn_opcode, | |
2833 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2834 | ep = NULL; |
2835 | r = BFD_RELOC_UNUSED; | |
2836 | } | |
2837 | } | |
2838 | continue; | |
2839 | ||
2840 | case '6': | |
2841 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2842 | continue; | |
2843 | } | |
2844 | ||
2845 | break; | |
2846 | } | |
2847 | ||
2848 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2849 | ||
2850 | append_insn (place, &insn, ep, r, false); | |
2851 | } | |
2852 | ||
3d3c5039 ILT |
2853 | /* |
2854 | * Generate a "lui" instruction. | |
2855 | */ | |
2856 | static void | |
0dd2d296 ILT |
2857 | macro_build_lui (place, counter, ep, regnum) |
2858 | char *place; | |
3d3c5039 ILT |
2859 | int *counter; |
2860 | expressionS *ep; | |
2861 | int regnum; | |
2862 | { | |
670a50eb ILT |
2863 | expressionS high_expr; |
2864 | struct mips_cl_insn insn; | |
2865 | bfd_reloc_code_real_type r; | |
2866 | CONST char *name = "lui"; | |
2867 | CONST char *fmt = "t,u"; | |
2868 | ||
3c83da8a | 2869 | assert (! mips_opts.mips16); |
cc5703cd | 2870 | |
0dd2d296 ILT |
2871 | if (place == NULL) |
2872 | high_expr = *ep; | |
2873 | else | |
2874 | { | |
2875 | high_expr.X_op = O_constant; | |
fb251650 | 2876 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2877 | } |
670a50eb | 2878 | |
5ac34ac3 | 2879 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2880 | { |
2881 | /* we can compute the instruction now without a relocation entry */ | |
2882 | if (high_expr.X_add_number & 0x8000) | |
2883 | high_expr.X_add_number += 0x10000; | |
2884 | high_expr.X_add_number = | |
2885 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2886 | r = BFD_RELOC_UNUSED; | |
2887 | } | |
2888 | else | |
0dd2d296 ILT |
2889 | { |
2890 | assert (ep->X_op == O_symbol); | |
2891 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2892 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2893 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2894 | r = BFD_RELOC_HI16_S; | |
2895 | } | |
670a50eb ILT |
2896 | |
2897 | /* | |
2898 | * If the macro is about to expand into a second instruction, | |
2899 | * print a warning if needed. We need to pass ip as a parameter | |
2900 | * to generate a better warning message here... | |
2901 | */ | |
3c83da8a | 2902 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2903 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2904 | |
0dd2d296 ILT |
2905 | if (place == NULL) |
2906 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2907 | |
2908 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2909 | assert (insn.insn_mo); | |
2910 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2911 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2912 | ||
0dd2d296 | 2913 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2914 | if (r == BFD_RELOC_UNUSED) |
2915 | { | |
2916 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2917 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2918 | } |
2919 | else | |
867a58b3 | 2920 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2921 | } |
2922 | ||
2923 | /* set_at() | |
2924 | * Generates code to set the $at register to true (one) | |
2925 | * if reg is less than the immediate expression. | |
2926 | */ | |
2927 | static void | |
6e8dda9c | 2928 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2929 | int *counter; |
2930 | int reg; | |
6e8dda9c | 2931 | int unsignedp; |
3d3c5039 | 2932 | { |
5c6f5923 GRK |
2933 | if (imm_expr.X_op == O_constant |
2934 | && imm_expr.X_add_number >= -0x8000 | |
2935 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2936 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2937 | unsignedp ? "sltiu" : "slti", |
9226253a | 2938 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2939 | else |
670a50eb | 2940 | { |
d8a1c247 | 2941 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2942 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2943 | unsignedp ? "sltu" : "slt", |
2944 | "d,v,t", AT, reg, AT); | |
670a50eb | 2945 | } |
3d3c5039 ILT |
2946 | } |
2947 | ||
6e8dda9c | 2948 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2949 | |
2950 | static void | |
19ed8960 | 2951 | check_absolute_expr (ip, ex) |
3d3c5039 | 2952 | struct mips_cl_insn *ip; |
19ed8960 | 2953 | expressionS *ex; |
3d3c5039 | 2954 | { |
5c6f5923 | 2955 | if (ex->X_op == O_big) |
48401fcf | 2956 | as_bad (_("unsupported large constant")); |
5c6f5923 | 2957 | else if (ex->X_op != O_constant) |
48401fcf | 2958 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
3d3c5039 ILT |
2959 | } |
2960 | ||
ff8716f5 JSC |
2961 | /* Count the leading zeroes by performing a binary chop. This is a |
2962 | bulky bit of source, but performance is a LOT better for the | |
2963 | majority of values than a simple loop to count the bits: | |
2964 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2965 | if ((v) & (1 << (31 - lcnt))) | |
2966 | break; | |
2967 | However it is not code size friendly, and the gain will drop a bit | |
2968 | on certain cached systems. | |
2969 | */ | |
2970 | #define COUNT_TOP_ZEROES(v) \ | |
2971 | (((v) & ~0xffff) == 0 \ | |
2972 | ? ((v) & ~0xff) == 0 \ | |
2973 | ? ((v) & ~0xf) == 0 \ | |
2974 | ? ((v) & ~0x3) == 0 \ | |
2975 | ? ((v) & ~0x1) == 0 \ | |
2976 | ? !(v) \ | |
2977 | ? 32 \ | |
2978 | : 31 \ | |
2979 | : 30 \ | |
2980 | : ((v) & ~0x7) == 0 \ | |
2981 | ? 29 \ | |
2982 | : 28 \ | |
2983 | : ((v) & ~0x3f) == 0 \ | |
2984 | ? ((v) & ~0x1f) == 0 \ | |
2985 | ? 27 \ | |
2986 | : 26 \ | |
2987 | : ((v) & ~0x7f) == 0 \ | |
2988 | ? 25 \ | |
2989 | : 24 \ | |
2990 | : ((v) & ~0xfff) == 0 \ | |
2991 | ? ((v) & ~0x3ff) == 0 \ | |
2992 | ? ((v) & ~0x1ff) == 0 \ | |
2993 | ? 23 \ | |
2994 | : 22 \ | |
2995 | : ((v) & ~0x7ff) == 0 \ | |
2996 | ? 21 \ | |
2997 | : 20 \ | |
2998 | : ((v) & ~0x3fff) == 0 \ | |
2999 | ? ((v) & ~0x1fff) == 0 \ | |
3000 | ? 19 \ | |
3001 | : 18 \ | |
3002 | : ((v) & ~0x7fff) == 0 \ | |
3003 | ? 17 \ | |
3004 | : 16 \ | |
3005 | : ((v) & ~0xffffff) == 0 \ | |
3006 | ? ((v) & ~0xfffff) == 0 \ | |
3007 | ? ((v) & ~0x3ffff) == 0 \ | |
3008 | ? ((v) & ~0x1ffff) == 0 \ | |
3009 | ? 15 \ | |
3010 | : 14 \ | |
3011 | : ((v) & ~0x7ffff) == 0 \ | |
3012 | ? 13 \ | |
3013 | : 12 \ | |
3014 | : ((v) & ~0x3fffff) == 0 \ | |
3015 | ? ((v) & ~0x1fffff) == 0 \ | |
3016 | ? 11 \ | |
3017 | : 10 \ | |
3018 | : ((v) & ~0x7fffff) == 0 \ | |
3019 | ? 9 \ | |
3020 | : 8 \ | |
3021 | : ((v) & ~0xfffffff) == 0 \ | |
3022 | ? ((v) & ~0x3ffffff) == 0 \ | |
3023 | ? ((v) & ~0x1ffffff) == 0 \ | |
3024 | ? 7 \ | |
3025 | : 6 \ | |
3026 | : ((v) & ~0x7ffffff) == 0 \ | |
3027 | ? 5 \ | |
3028 | : 4 \ | |
3029 | : ((v) & ~0x3fffffff) == 0 \ | |
3030 | ? ((v) & ~0x1fffffff) == 0 \ | |
3031 | ? 3 \ | |
3032 | : 2 \ | |
3033 | : ((v) & ~0x7fffffff) == 0 \ | |
3034 | ? 1 \ | |
3035 | : 0) | |
3036 | ||
3d3c5039 ILT |
3037 | /* load_register() |
3038 | * This routine generates the least number of instructions neccessary to load | |
3039 | * an absolute expression value into a register. | |
3040 | */ | |
3041 | static void | |
d8a1c247 | 3042 | load_register (counter, reg, ep, dbl) |
670a50eb | 3043 | int *counter; |
670a50eb ILT |
3044 | int reg; |
3045 | expressionS *ep; | |
d8a1c247 | 3046 | int dbl; |
3d3c5039 | 3047 | { |
c36a90ef ILT |
3048 | int freg; |
3049 | expressionS hi32, lo32; | |
847a01cd ILT |
3050 | |
3051 | if (ep->X_op != O_big) | |
6e8dda9c | 3052 | { |
847a01cd | 3053 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
3054 | if (ep->X_add_number < 0x8000 |
3055 | && (ep->X_add_number >= 0 | |
3056 | || (ep->X_add_number >= -0x8000 | |
3057 | && (! dbl | |
3058 | || ! ep->X_unsigned | |
3059 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
3060 | { |
3061 | /* We can handle 16 bit signed values with an addiu to | |
3062 | $zero. No need to ever use daddiu here, since $zero and | |
3063 | the result are always correct in 32 bit mode. */ | |
3064 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3065 | (int) BFD_RELOC_LO16); | |
3066 | return; | |
3067 | } | |
3068 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3069 | { | |
3070 | /* We can handle 16 bit unsigned values with an ori to | |
3071 | $zero. */ | |
3072 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3073 | (int) BFD_RELOC_LO16); | |
3074 | return; | |
3075 | } | |
98bfd087 ILT |
3076 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
3077 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3078 | == ~ (offsetT) 0x7fffffff)) | |
3079 | && (! dbl | |
3080 | || ! ep->X_unsigned | |
3081 | || sizeof (ep->X_add_number) > 4 | |
3082 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 3083 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 3084 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 3085 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
3086 | && ! dbl |
3087 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3088 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
3089 | { |
3090 | /* 32 bit values require an lui. */ | |
3091 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3092 | (int) BFD_RELOC_HI16); | |
3093 | if ((ep->X_add_number & 0xffff) != 0) | |
3094 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3095 | (int) BFD_RELOC_LO16); | |
3096 | return; | |
3097 | } | |
6e8dda9c | 3098 | } |
847a01cd ILT |
3099 | |
3100 | /* The value is larger than 32 bits. */ | |
3101 | ||
3c83da8a | 3102 | if (mips_opts.isa < 3) |
670a50eb | 3103 | { |
48401fcf | 3104 | as_bad (_("Number larger than 32 bits")); |
0dd2d296 | 3105 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3106 | (int) BFD_RELOC_LO16); |
847a01cd | 3107 | return; |
6e8dda9c | 3108 | } |
6e8dda9c | 3109 | |
847a01cd ILT |
3110 | if (ep->X_op != O_big) |
3111 | { | |
6e8dda9c | 3112 | hi32 = *ep; |
c36a90ef ILT |
3113 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3114 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3115 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3116 | lo32 = *ep; |
3117 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3118 | } |
847a01cd ILT |
3119 | else |
3120 | { | |
3121 | assert (ep->X_add_number > 2); | |
3122 | if (ep->X_add_number == 3) | |
3123 | generic_bignum[3] = 0; | |
3124 | else if (ep->X_add_number > 4) | |
48401fcf | 3125 | as_bad (_("Number larger than 64 bits")); |
847a01cd ILT |
3126 | lo32.X_op = O_constant; |
3127 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3128 | hi32.X_op = O_constant; | |
3129 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3130 | } | |
3131 | ||
d8a1c247 KR |
3132 | if (hi32.X_add_number == 0) |
3133 | freg = 0; | |
3134 | else | |
3135 | { | |
c36a90ef ILT |
3136 | int shift, bit; |
3137 | unsigned long hi, lo; | |
3138 | ||
fb251650 ILT |
3139 | if (hi32.X_add_number == 0xffffffff) |
3140 | { | |
3141 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3142 | { | |
c36a90ef ILT |
3143 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3144 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3145 | return; |
3146 | } | |
3147 | if (lo32.X_add_number & 0x80000000) | |
3148 | { | |
3149 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3150 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3151 | if (lo32.X_add_number & 0xffff) |
3152 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3153 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3154 | return; |
3155 | } | |
3156 | } | |
ff8716f5 | 3157 | |
c36a90ef ILT |
3158 | /* Check for 16bit shifted constant. We know that hi32 is |
3159 | non-zero, so start the mask on the first bit of the hi32 | |
3160 | value. */ | |
ff8716f5 JSC |
3161 | shift = 17; |
3162 | do | |
3163 | { | |
c36a90ef ILT |
3164 | unsigned long himask, lomask; |
3165 | ||
3166 | if (shift < 32) | |
3167 | { | |
3168 | himask = 0xffff >> (32 - shift); | |
3169 | lomask = (0xffff << shift) & 0xffffffff; | |
3170 | } | |
3171 | else | |
3172 | { | |
3173 | himask = 0xffff << (shift - 32); | |
3174 | lomask = 0; | |
3175 | } | |
3176 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3177 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3178 | { | |
3179 | expressionS tmp; | |
3180 | ||
3181 | tmp.X_op = O_constant; | |
3182 | if (shift < 32) | |
3183 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3184 | | (lo32.X_add_number >> shift)); | |
3185 | else | |
3186 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3187 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3188 | (int) BFD_RELOC_LO16); | |
3189 | macro_build ((char *) NULL, counter, NULL, | |
3190 | (shift >= 32) ? "dsll32" : "dsll", | |
3191 | "d,w,<", reg, reg, | |
3192 | (shift >= 32) ? shift - 32 : shift); | |
3193 | return; | |
3194 | } | |
ff8716f5 JSC |
3195 | shift++; |
3196 | } while (shift <= (64 - 16)); | |
3197 | ||
c36a90ef ILT |
3198 | /* Find the bit number of the lowest one bit, and store the |
3199 | shifted value in hi/lo. */ | |
3200 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3201 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3202 | if (lo != 0) | |
3203 | { | |
3204 | bit = 0; | |
3205 | while ((lo & 1) == 0) | |
3206 | { | |
3207 | lo >>= 1; | |
3208 | ++bit; | |
3209 | } | |
3210 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3211 | hi >>= bit; | |
3212 | } | |
3213 | else | |
3214 | { | |
3215 | bit = 32; | |
3216 | while ((hi & 1) == 0) | |
3217 | { | |
3218 | hi >>= 1; | |
3219 | ++bit; | |
3220 | } | |
3221 | lo = hi; | |
3222 | hi = 0; | |
3223 | } | |
3224 | ||
3225 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3226 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3227 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3228 | { |
c36a90ef | 3229 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3230 | if (shift != 0) |
3231 | { | |
c36a90ef ILT |
3232 | expressionS tmp; |
3233 | ||
3234 | /* This instruction will set the register to be all | |
3235 | ones. */ | |
ff8716f5 | 3236 | tmp.X_op = O_constant; |
c36a90ef ILT |
3237 | tmp.X_add_number = (offsetT) -1; |
3238 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3239 | reg, 0, (int) BFD_RELOC_LO16); | |
3240 | if (bit != 0) | |
ff8716f5 | 3241 | { |
c36a90ef | 3242 | bit += shift; |
ff8716f5 | 3243 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3244 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3245 | "d,w,<", reg, reg, |
c36a90ef | 3246 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3247 | } |
c36a90ef ILT |
3248 | macro_build ((char *) NULL, counter, NULL, |
3249 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3250 | "d,w,<", reg, reg, | |
3251 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3252 | return; |
3253 | } | |
3254 | } | |
c36a90ef ILT |
3255 | |
3256 | /* Sign extend hi32 before calling load_register, because we can | |
3257 | generally get better code when we load a sign extended value. */ | |
3258 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3259 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3260 | load_register (counter, reg, &hi32, 0); |
3261 | freg = reg; | |
3262 | } | |
847a01cd | 3263 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3264 | { |
3265 | if (freg != 0) | |
3266 | { | |
3267 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3268 | freg, 0); | |
3269 | freg = reg; | |
3270 | } | |
3271 | } | |
847a01cd ILT |
3272 | else |
3273 | { | |
3274 | expressionS mid16; | |
3275 | ||
fb251650 ILT |
3276 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3277 | { | |
3278 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3279 | (int) BFD_RELOC_HI16); | |
3280 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3281 | reg, 0); |
fb251650 ILT |
3282 | return; |
3283 | } | |
3284 | ||
d8a1c247 KR |
3285 | if (freg != 0) |
3286 | { | |
3287 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3288 | freg, 16); | |
3289 | freg = reg; | |
3290 | } | |
847a01cd ILT |
3291 | mid16 = lo32; |
3292 | mid16.X_add_number >>= 16; | |
3293 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3294 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3295 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3296 | reg, 16); | |
d8a1c247 | 3297 | freg = reg; |
847a01cd ILT |
3298 | } |
3299 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3300 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3301 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3302 | } |
3303 | ||
0dd2d296 ILT |
3304 | /* Load an address into a register. */ |
3305 | ||
3306 | static void | |
3307 | load_address (counter, reg, ep) | |
3308 | int *counter; | |
3309 | int reg; | |
3310 | expressionS *ep; | |
3311 | { | |
3312 | char *p; | |
3313 | ||
3314 | if (ep->X_op != O_constant | |
3315 | && ep->X_op != O_symbol) | |
3316 | { | |
48401fcf | 3317 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
3318 | ep->X_op = O_constant; |
3319 | } | |
3320 | ||
3321 | if (ep->X_op == O_constant) | |
d9aba805 | 3322 | { |
d8a1c247 | 3323 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3324 | return; |
3325 | } | |
3326 | ||
3327 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3328 | { |
3329 | /* If this is a reference to a GP relative symbol, we want | |
3330 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3331 | Otherwise we want | |
04cb3372 | 3332 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3333 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3334 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3335 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3336 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3337 | p = NULL; |
3338 | else | |
3339 | { | |
8ea7f4e8 | 3340 | frag_grow (20); |
0dd2d296 | 3341 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3342 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3343 | || mips_opts.isa < 3) | |
3344 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3345 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3346 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3347 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3348 | mips_opts.warn_about_macros), | |
f59fb6ca | 3349 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3350 | } |
3351 | macro_build_lui (p, counter, ep, reg); | |
3352 | if (p != NULL) | |
3353 | p += 4; | |
3354 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3355 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3356 | || mips_opts.isa < 3) | |
3357 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3358 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3359 | } | |
fb251650 | 3360 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3361 | { |
3362 | expressionS ex; | |
3363 | ||
3364 | /* If this is a reference to an external symbol, we want | |
3365 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3366 | Otherwise we want | |
3367 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3368 | nop | |
3369 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3370 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3371 | ex.X_add_number = ep->X_add_number; |
3372 | ep->X_add_number = 0; | |
8ea7f4e8 | 3373 | frag_grow (20); |
0dd2d296 | 3374 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3375 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3376 | || mips_opts.isa < 3) | |
3377 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3378 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3379 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3380 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3381 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3382 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3383 | macro_build (p, counter, ep, |
9a1f3160 JL |
3384 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3385 | || mips_opts.isa < 3) | |
3386 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3387 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3388 | if (ex.X_add_number != 0) | |
3389 | { | |
3390 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3391 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 | 3392 | ex.X_op = O_constant; |
fb251650 | 3393 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3394 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3395 | || mips_opts.isa < 3) | |
3396 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3397 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3398 | } | |
3399 | } | |
3400 | else if (mips_pic == SVR4_PIC) | |
3401 | { | |
3402 | expressionS ex; | |
3403 | int off; | |
3404 | ||
3405 | /* This is the large GOT case. If this is a reference to an | |
3406 | external symbol, we want | |
3407 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3408 | addu $reg,$reg,$gp | |
3409 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3410 | Otherwise, for a reference to a local symbol, we want | |
3411 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3412 | nop | |
3413 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3414 | If there is a constant, it must be added in after. */ | |
3415 | ex.X_add_number = ep->X_add_number; | |
3416 | ep->X_add_number = 0; | |
3417 | if (reg_needs_delay (GP)) | |
3418 | off = 4; | |
3419 | else | |
3420 | off = 0; | |
3421 | frag_grow (32); | |
3422 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3423 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3424 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3425 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3426 | || mips_opts.isa < 3) | |
3427 | ? "addu" : "daddu"), | |
fb251650 ILT |
3428 | "d,v,t", reg, reg, GP); |
3429 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3430 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3431 | || mips_opts.isa < 3) | |
3432 | ? "lw" : "ld"), | |
fb251650 ILT |
3433 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3434 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3435 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3436 | mips_opts.warn_about_macros), |
f59fb6ca | 3437 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3438 | if (off > 0) |
3439 | { | |
3440 | /* We need a nop before loading from $gp. This special | |
3441 | check is required because the lui which starts the main | |
3442 | instruction stream does not refer to $gp, and so will not | |
3443 | insert the nop which may be required. */ | |
3444 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3445 | p += 4; | |
3446 | } | |
3447 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3448 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3449 | || mips_opts.isa < 3) | |
3450 | ? "lw" : "ld"), | |
fb251650 ILT |
3451 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3452 | p += 4; | |
3453 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3454 | p += 4; | |
3455 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3456 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3457 | || mips_opts.isa < 3) | |
3458 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3459 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3460 | if (ex.X_add_number != 0) | |
3461 | { | |
3462 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3463 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
3464 | ex.X_op = O_constant; |
3465 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3466 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3467 | || mips_opts.isa < 3) | |
3468 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3469 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3470 | } | |
d9aba805 ILT |
3471 | } |
3472 | else if (mips_pic == EMBEDDED_PIC) | |
3473 | { | |
3474 | /* We always do | |
3475 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3476 | */ | |
3477 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3478 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3479 | || mips_opts.isa < 3) | |
3480 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3481 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3482 | } | |
3483 | else | |
3484 | abort (); | |
0dd2d296 ILT |
3485 | } |
3486 | ||
3d3c5039 ILT |
3487 | /* |
3488 | * Build macros | |
3489 | * This routine implements the seemingly endless macro or synthesized | |
3490 | * instructions and addressing modes in the mips assembly language. Many | |
3491 | * of these macros are simple and are similar to each other. These could | |
3492 | * probably be handled by some kind of table or grammer aproach instead of | |
3493 | * this verbose method. Others are not simple macros but are more like | |
3494 | * optimizing code generation. | |
3495 | * One interesting optimization is when several store macros appear | |
3496 | * consecutivly that would load AT with the upper half of the same address. | |
3497 | * The ensuing load upper instructions are ommited. This implies some kind | |
3498 | * of global optimization. We currently only optimize within a single macro. | |
3499 | * For many of the load and store macros if the address is specified as a | |
3500 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3501 | * first load register 'at' with zero and use it as the base register. The | |
3502 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3503 | * we're missing. | |
3504 | */ | |
3505 | static void | |
3506 | macro (ip) | |
3507 | struct mips_cl_insn *ip; | |
3508 | { | |
670a50eb ILT |
3509 | register int treg, sreg, dreg, breg; |
3510 | int tempreg; | |
3511 | int mask; | |
3512 | int icnt = 0; | |
3513 | int used_at; | |
670a50eb ILT |
3514 | expressionS expr1; |
3515 | const char *s; | |
8358c818 | 3516 | const char *s2; |
670a50eb | 3517 | const char *fmt; |
8358c818 ILT |
3518 | int likely = 0; |
3519 | int dbl = 0; | |
3520 | int coproc = 0; | |
b2b8c24e | 3521 | int lr = 0; |
40f0c904 | 3522 | int imm = 0; |
6e8dda9c | 3523 | offsetT maxnum; |
adcf2b9d | 3524 | int off; |
9226253a | 3525 | bfd_reloc_code_real_type r; |
0dd2d296 | 3526 | char *p; |
55933a58 | 3527 | int hold_mips_optimize; |
670a50eb | 3528 | |
3c83da8a | 3529 | assert (! mips_opts.mips16); |
cc5703cd | 3530 | |
670a50eb ILT |
3531 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3532 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3533 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3534 | mask = ip->insn_mo->mask; | |
3535 | ||
5ac34ac3 ILT |
3536 | expr1.X_op = O_constant; |
3537 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3538 | expr1.X_add_symbol = NULL; |
3539 | expr1.X_add_number = 1; | |
3540 | ||
3541 | switch (mask) | |
3542 | { | |
6e8dda9c ILT |
3543 | case M_DABS: |
3544 | dbl = 1; | |
3d3c5039 | 3545 | case M_ABS: |
6e8dda9c ILT |
3546 | /* bgez $a0,.+12 |
3547 | move v0,$a0 | |
3548 | sub v0,$zero,$a0 | |
3549 | */ | |
3d3c5039 | 3550 | |
fbcfacb7 | 3551 | mips_emit_delays (true); |
3c83da8a | 3552 | ++mips_opts.noreorder; |
0dd2d296 | 3553 | mips_any_noreorder = 1; |
3d3c5039 | 3554 | |
670a50eb | 3555 | expr1.X_add_number = 8; |
0dd2d296 | 3556 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3557 | if (dreg == sreg) |
0dd2d296 | 3558 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3559 | else |
0dd2d296 ILT |
3560 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3561 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3562 | dbl ? "dsub" : "sub", |
3563 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3564 | |
3c83da8a | 3565 | --mips_opts.noreorder; |
670a50eb | 3566 | return; |
3d3c5039 ILT |
3567 | |
3568 | case M_ADD_I: | |
8358c818 ILT |
3569 | s = "addi"; |
3570 | s2 = "add"; | |
3571 | goto do_addi; | |
3d3c5039 | 3572 | case M_ADDU_I: |
8358c818 ILT |
3573 | s = "addiu"; |
3574 | s2 = "addu"; | |
3575 | goto do_addi; | |
3576 | case M_DADD_I: | |
6e8dda9c | 3577 | dbl = 1; |
8358c818 ILT |
3578 | s = "daddi"; |
3579 | s2 = "dadd"; | |
3580 | goto do_addi; | |
3581 | case M_DADDU_I: | |
6e8dda9c | 3582 | dbl = 1; |
8358c818 ILT |
3583 | s = "daddiu"; |
3584 | s2 = "daddu"; | |
3585 | do_addi: | |
5c6f5923 GRK |
3586 | if (imm_expr.X_op == O_constant |
3587 | && imm_expr.X_add_number >= -0x8000 | |
3588 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3589 | { |
0dd2d296 | 3590 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3591 | (int) BFD_RELOC_LO16); |
670a50eb | 3592 | return; |
3d3c5039 | 3593 | } |
d8a1c247 | 3594 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3595 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3596 | break; |
3d3c5039 ILT |
3597 | |
3598 | case M_AND_I: | |
6e8dda9c ILT |
3599 | s = "andi"; |
3600 | s2 = "and"; | |
3601 | goto do_bit; | |
3d3c5039 | 3602 | case M_OR_I: |
6e8dda9c ILT |
3603 | s = "ori"; |
3604 | s2 = "or"; | |
3605 | goto do_bit; | |
3d3c5039 | 3606 | case M_NOR_I: |
6e8dda9c ILT |
3607 | s = ""; |
3608 | s2 = "nor"; | |
3609 | goto do_bit; | |
3d3c5039 | 3610 | case M_XOR_I: |
6e8dda9c ILT |
3611 | s = "xori"; |
3612 | s2 = "xor"; | |
3613 | do_bit: | |
5c6f5923 GRK |
3614 | if (imm_expr.X_op == O_constant |
3615 | && imm_expr.X_add_number >= 0 | |
3616 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3617 | { |
6e8dda9c | 3618 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3619 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3620 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3621 | else |
670a50eb | 3622 | { |
0dd2d296 ILT |
3623 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3624 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3625 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3626 | treg, treg, 0); |
3d3c5039 | 3627 | } |
6e8dda9c | 3628 | return; |
3d3c5039 | 3629 | } |
6e8dda9c | 3630 | |
d8a1c247 | 3631 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3632 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3633 | break; |
3d3c5039 ILT |
3634 | |
3635 | case M_BEQ_I: | |
8358c818 ILT |
3636 | s = "beq"; |
3637 | goto beq_i; | |
3638 | case M_BEQL_I: | |
3639 | s = "beql"; | |
3640 | likely = 1; | |
3641 | goto beq_i; | |
3d3c5039 | 3642 | case M_BNE_I: |
8358c818 ILT |
3643 | s = "bne"; |
3644 | goto beq_i; | |
3645 | case M_BNEL_I: | |
3646 | s = "bnel"; | |
3647 | likely = 1; | |
3648 | beq_i: | |
5c6f5923 | 3649 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3650 | { |
0dd2d296 ILT |
3651 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3652 | 0); | |
670a50eb ILT |
3653 | return; |
3654 | } | |
d8a1c247 | 3655 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3656 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3657 | break; |
3d3c5039 | 3658 | |
8358c818 ILT |
3659 | case M_BGEL: |
3660 | likely = 1; | |
3d3c5039 | 3661 | case M_BGE: |
670a50eb ILT |
3662 | if (treg == 0) |
3663 | { | |
0dd2d296 | 3664 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3665 | likely ? "bgezl" : "bgez", |
3666 | "s,p", sreg); | |
670a50eb | 3667 | return; |
3d3c5039 | 3668 | } |
9a7d824a ILT |
3669 | if (sreg == 0) |
3670 | { | |
0dd2d296 | 3671 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3672 | likely ? "blezl" : "blez", |
3673 | "s,p", treg); | |
9a7d824a ILT |
3674 | return; |
3675 | } | |
0dd2d296 ILT |
3676 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3677 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3678 | likely ? "beql" : "beq", |
3679 | "s,t,p", AT, 0); | |
670a50eb | 3680 | break; |
3d3c5039 | 3681 | |
8358c818 ILT |
3682 | case M_BGTL_I: |
3683 | likely = 1; | |
3d3c5039 | 3684 | case M_BGT_I: |
9a7d824a | 3685 | /* check for > max integer */ |
6e8dda9c | 3686 | maxnum = 0x7fffffff; |
5c6f5923 | 3687 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3688 | { |
3689 | maxnum <<= 16; | |
3690 | maxnum |= 0xffff; | |
3691 | maxnum <<= 16; | |
3692 | maxnum |= 0xffff; | |
3693 | } | |
5c6f5923 GRK |
3694 | if (imm_expr.X_op == O_constant |
3695 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3696 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3697 | { |
3698 | do_false: | |
3699 | /* result is always false */ | |
8358c818 ILT |
3700 | if (! likely) |
3701 | { | |
48401fcf | 3702 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); |
0dd2d296 | 3703 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3704 | } |
3705 | else | |
3706 | { | |
48401fcf | 3707 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); |
0dd2d296 ILT |
3708 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3709 | "s,t,p", 0, 0); | |
8358c818 | 3710 | } |
9a7d824a ILT |
3711 | return; |
3712 | } | |
5c6f5923 | 3713 | if (imm_expr.X_op != O_constant) |
48401fcf | 3714 | as_bad (_("Unsupported large constant")); |
670a50eb ILT |
3715 | imm_expr.X_add_number++; |
3716 | /* FALLTHROUGH */ | |
3d3c5039 | 3717 | case M_BGE_I: |
8358c818 ILT |
3718 | case M_BGEL_I: |
3719 | if (mask == M_BGEL_I) | |
3720 | likely = 1; | |
5c6f5923 | 3721 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3722 | { |
0dd2d296 | 3723 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3724 | likely ? "bgezl" : "bgez", |
3725 | "s,p", sreg); | |
670a50eb | 3726 | return; |
3d3c5039 | 3727 | } |
5c6f5923 | 3728 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3729 | { |
0dd2d296 | 3730 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3731 | likely ? "bgtzl" : "bgtz", |
3732 | "s,p", sreg); | |
670a50eb | 3733 | return; |
3d3c5039 | 3734 | } |
6e8dda9c | 3735 | maxnum = 0x7fffffff; |
5c6f5923 | 3736 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3737 | { |
3738 | maxnum <<= 16; | |
3739 | maxnum |= 0xffff; | |
3740 | maxnum <<= 16; | |
3741 | maxnum |= 0xffff; | |
3742 | } | |
3743 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3744 | if (imm_expr.X_op == O_constant |
3745 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3746 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3747 | { |
3748 | do_true: | |
3749 | /* result is always true */ | |
48401fcf | 3750 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
0dd2d296 | 3751 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3752 | return; |
3753 | } | |
6e8dda9c | 3754 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3755 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3756 | likely ? "beql" : "beq", |
3757 | "s,t,p", AT, 0); | |
670a50eb | 3758 | break; |
3d3c5039 | 3759 | |
8358c818 ILT |
3760 | case M_BGEUL: |
3761 | likely = 1; | |
3d3c5039 | 3762 | case M_BGEU: |
670a50eb | 3763 | if (treg == 0) |
9a7d824a ILT |
3764 | goto do_true; |
3765 | if (sreg == 0) | |
670a50eb | 3766 | { |
0dd2d296 | 3767 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3768 | likely ? "beql" : "beq", |
3769 | "s,t,p", 0, treg); | |
670a50eb | 3770 | return; |
3d3c5039 | 3771 | } |
0dd2d296 ILT |
3772 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3773 | treg); | |
3774 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3775 | likely ? "beql" : "beq", |
3776 | "s,t,p", AT, 0); | |
670a50eb | 3777 | break; |
3d3c5039 | 3778 | |
8358c818 ILT |
3779 | case M_BGTUL_I: |
3780 | likely = 1; | |
9a7d824a | 3781 | case M_BGTU_I: |
5c6f5923 GRK |
3782 | if (sreg == 0 |
3783 | || (mips_opts.isa < 3 | |
3784 | && imm_expr.X_op == O_constant | |
3785 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3786 | goto do_false; |
5c6f5923 | 3787 | if (imm_expr.X_op != O_constant) |
48401fcf | 3788 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3789 | imm_expr.X_add_number++; |
3790 | /* FALLTHROUGH */ | |
3d3c5039 | 3791 | case M_BGEU_I: |
8358c818 ILT |
3792 | case M_BGEUL_I: |
3793 | if (mask == M_BGEUL_I) | |
3794 | likely = 1; | |
5c6f5923 | 3795 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3796 | goto do_true; |
5c6f5923 | 3797 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3798 | { |
0dd2d296 | 3799 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3800 | likely ? "bnel" : "bne", |
3801 | "s,t,p", sreg, 0); | |
670a50eb | 3802 | return; |
3d3c5039 | 3803 | } |
6e8dda9c | 3804 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3805 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3806 | likely ? "beql" : "beq", |
3807 | "s,t,p", AT, 0); | |
670a50eb | 3808 | break; |
3d3c5039 | 3809 | |
8358c818 ILT |
3810 | case M_BGTL: |
3811 | likely = 1; | |
3d3c5039 | 3812 | case M_BGT: |
670a50eb ILT |
3813 | if (treg == 0) |
3814 | { | |
0dd2d296 | 3815 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3816 | likely ? "bgtzl" : "bgtz", |
3817 | "s,p", sreg); | |
670a50eb | 3818 | return; |
3d3c5039 | 3819 | } |
9a7d824a ILT |
3820 | if (sreg == 0) |
3821 | { | |
0dd2d296 | 3822 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3823 | likely ? "bltzl" : "bltz", |
3824 | "s,p", treg); | |
9a7d824a ILT |
3825 | return; |
3826 | } | |
0dd2d296 ILT |
3827 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3828 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3829 | likely ? "bnel" : "bne", |
3830 | "s,t,p", AT, 0); | |
670a50eb | 3831 | break; |
3d3c5039 | 3832 | |
8358c818 ILT |
3833 | case M_BGTUL: |
3834 | likely = 1; | |
3d3c5039 | 3835 | case M_BGTU: |
670a50eb ILT |
3836 | if (treg == 0) |
3837 | { | |
0dd2d296 | 3838 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3839 | likely ? "bnel" : "bne", |
3840 | "s,t,p", sreg, 0); | |
670a50eb | 3841 | return; |
3d3c5039 | 3842 | } |
9a7d824a ILT |
3843 | if (sreg == 0) |
3844 | goto do_false; | |
0dd2d296 ILT |
3845 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3846 | sreg); | |
3847 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3848 | likely ? "bnel" : "bne", |
3849 | "s,t,p", AT, 0); | |
670a50eb | 3850 | break; |
3d3c5039 | 3851 | |
8358c818 ILT |
3852 | case M_BLEL: |
3853 | likely = 1; | |
3d3c5039 | 3854 | case M_BLE: |
670a50eb ILT |
3855 | if (treg == 0) |
3856 | { | |
0dd2d296 | 3857 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3858 | likely ? "blezl" : "blez", |
3859 | "s,p", sreg); | |
670a50eb ILT |
3860 | return; |
3861 | } | |
9a7d824a ILT |
3862 | if (sreg == 0) |
3863 | { | |
0dd2d296 | 3864 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3865 | likely ? "bgezl" : "bgez", |
3866 | "s,p", treg); | |
9a7d824a ILT |
3867 | return; |
3868 | } | |
0dd2d296 ILT |
3869 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3870 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3871 | likely ? "beql" : "beq", |
3872 | "s,t,p", AT, 0); | |
670a50eb | 3873 | break; |
3d3c5039 | 3874 | |
8358c818 ILT |
3875 | case M_BLEL_I: |
3876 | likely = 1; | |
3d3c5039 | 3877 | case M_BLE_I: |
6e8dda9c | 3878 | maxnum = 0x7fffffff; |
5c6f5923 | 3879 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3880 | { |
3881 | maxnum <<= 16; | |
3882 | maxnum |= 0xffff; | |
3883 | maxnum <<= 16; | |
3884 | maxnum |= 0xffff; | |
3885 | } | |
5c6f5923 GRK |
3886 | if (imm_expr.X_op == O_constant |
3887 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3888 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3889 | goto do_true; |
5c6f5923 | 3890 | if (imm_expr.X_op != O_constant) |
48401fcf | 3891 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3892 | imm_expr.X_add_number++; |
3893 | /* FALLTHROUGH */ | |
9a7d824a | 3894 | case M_BLT_I: |
8358c818 ILT |
3895 | case M_BLTL_I: |
3896 | if (mask == M_BLTL_I) | |
3897 | likely = 1; | |
5c6f5923 | 3898 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3899 | { |
0dd2d296 | 3900 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3901 | likely ? "bltzl" : "bltz", |
3902 | "s,p", sreg); | |
670a50eb ILT |
3903 | return; |
3904 | } | |
5c6f5923 | 3905 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3906 | { |
0dd2d296 | 3907 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3908 | likely ? "blezl" : "blez", |
3909 | "s,p", sreg); | |
670a50eb ILT |
3910 | return; |
3911 | } | |
6e8dda9c | 3912 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3913 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3914 | likely ? "bnel" : "bne", |
3915 | "s,t,p", AT, 0); | |
670a50eb | 3916 | break; |
3d3c5039 | 3917 | |
8358c818 ILT |
3918 | case M_BLEUL: |
3919 | likely = 1; | |
3d3c5039 | 3920 | case M_BLEU: |
670a50eb ILT |
3921 | if (treg == 0) |
3922 | { | |
0dd2d296 | 3923 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3924 | likely ? "beql" : "beq", |
3925 | "s,t,p", sreg, 0); | |
670a50eb | 3926 | return; |
3d3c5039 | 3927 | } |
9a7d824a ILT |
3928 | if (sreg == 0) |
3929 | goto do_true; | |
0dd2d296 ILT |
3930 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3931 | sreg); | |
3932 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3933 | likely ? "beql" : "beq", |
3934 | "s,t,p", AT, 0); | |
670a50eb | 3935 | break; |
3d3c5039 | 3936 | |
8358c818 ILT |
3937 | case M_BLEUL_I: |
3938 | likely = 1; | |
3d3c5039 | 3939 | case M_BLEU_I: |
5c6f5923 GRK |
3940 | if (sreg == 0 |
3941 | || (mips_opts.isa < 3 | |
3942 | && imm_expr.X_op == O_constant | |
3943 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3944 | goto do_true; |
5c6f5923 | 3945 | if (imm_expr.X_op != O_constant) |
48401fcf | 3946 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3947 | imm_expr.X_add_number++; |
3948 | /* FALLTHROUGH */ | |
9a7d824a | 3949 | case M_BLTU_I: |
8358c818 ILT |
3950 | case M_BLTUL_I: |
3951 | if (mask == M_BLTUL_I) | |
3952 | likely = 1; | |
5c6f5923 | 3953 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3954 | goto do_false; |
5c6f5923 | 3955 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3956 | { |
0dd2d296 | 3957 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3958 | likely ? "beql" : "beq", |
3959 | "s,t,p", sreg, 0); | |
670a50eb | 3960 | return; |
3d3c5039 | 3961 | } |
6e8dda9c | 3962 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3963 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3964 | likely ? "bnel" : "bne", |
3965 | "s,t,p", AT, 0); | |
670a50eb | 3966 | break; |
3d3c5039 | 3967 | |
8358c818 ILT |
3968 | case M_BLTL: |
3969 | likely = 1; | |
3d3c5039 | 3970 | case M_BLT: |
670a50eb ILT |
3971 | if (treg == 0) |
3972 | { | |
0dd2d296 | 3973 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3974 | likely ? "bltzl" : "bltz", |
3975 | "s,p", sreg); | |
670a50eb | 3976 | return; |
3d3c5039 | 3977 | } |
9a7d824a | 3978 | if (sreg == 0) |
670a50eb | 3979 | { |
0dd2d296 | 3980 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3981 | likely ? "bgtzl" : "bgtz", |
3982 | "s,p", treg); | |
670a50eb | 3983 | return; |
3d3c5039 | 3984 | } |
0dd2d296 ILT |
3985 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3986 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3987 | likely ? "bnel" : "bne", |
3988 | "s,t,p", AT, 0); | |
670a50eb | 3989 | break; |
3d3c5039 | 3990 | |
8358c818 ILT |
3991 | case M_BLTUL: |
3992 | likely = 1; | |
3d3c5039 | 3993 | case M_BLTU: |
670a50eb | 3994 | if (treg == 0) |
9a7d824a ILT |
3995 | goto do_false; |
3996 | if (sreg == 0) | |
670a50eb | 3997 | { |
0dd2d296 | 3998 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3999 | likely ? "bnel" : "bne", |
4000 | "s,t,p", 0, treg); | |
670a50eb ILT |
4001 | return; |
4002 | } | |
0dd2d296 ILT |
4003 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
4004 | treg); | |
4005 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
4006 | likely ? "bnel" : "bne", |
4007 | "s,t,p", AT, 0); | |
670a50eb | 4008 | break; |
3d3c5039 | 4009 | |
8358c818 ILT |
4010 | case M_DDIV_3: |
4011 | dbl = 1; | |
3d3c5039 | 4012 | case M_DIV_3: |
8358c818 ILT |
4013 | s = "mflo"; |
4014 | goto do_div3; | |
4015 | case M_DREM_3: | |
4016 | dbl = 1; | |
3d3c5039 | 4017 | case M_REM_3: |
8358c818 ILT |
4018 | s = "mfhi"; |
4019 | do_div3: | |
670a50eb ILT |
4020 | if (treg == 0) |
4021 | { | |
48401fcf | 4022 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4023 | if (mips_trap) |
4024 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4025 | else | |
d9c2c0c5 FCE |
4026 | /* start-sanitize-r5900 */ |
4027 | if (mips_5900) | |
4028 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4029 | else | |
4030 | /* end-sanitize-r5900 */ | |
4031 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4032 | return; |
4033 | } | |
4034 | ||
fbcfacb7 | 4035 | mips_emit_delays (true); |
3c83da8a | 4036 | ++mips_opts.noreorder; |
0dd2d296 | 4037 | mips_any_noreorder = 1; |
8ea7f4e8 | 4038 | if (mips_trap) |
6c4b811d JL |
4039 | { |
4040 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4041 | macro_build ((char *) NULL, &icnt, NULL, | |
4042 | dbl ? "ddiv" : "div", | |
4043 | "z,s,t", sreg, treg); | |
4044 | } | |
8ea7f4e8 ILT |
4045 | else |
4046 | { | |
4047 | expr1.X_add_number = 8; | |
4048 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
4049 | macro_build ((char *) NULL, &icnt, NULL, |
4050 | dbl ? "ddiv" : "div", | |
4051 | "z,s,t", sreg, treg); | |
d9c2c0c5 FCE |
4052 | /* start-sanitize-r5900 */ |
4053 | if (mips_5900) | |
4054 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4055 | else | |
4056 | /* end-sanitize-r5900 */ | |
4057 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4058 | } |
670a50eb | 4059 | expr1.X_add_number = -1; |
0dd2d296 | 4060 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 4061 | dbl ? "daddiu" : "addiu", |
9226253a | 4062 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 4063 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 4064 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
4065 | if (dbl) |
4066 | { | |
4067 | expr1.X_add_number = 1; | |
0dd2d296 | 4068 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 4069 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
4070 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
4071 | 31); | |
8358c818 ILT |
4072 | } |
4073 | else | |
4074 | { | |
4075 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
4076 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
4077 | (int) BFD_RELOC_HI16); | |
8358c818 | 4078 | } |
8ea7f4e8 | 4079 | if (mips_trap) |
edc8f76e JL |
4080 | { |
4081 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4082 | /* We want to close the noreorder block as soon as possible, so | |
4083 | that later insns are available for delay slot filling. */ | |
4084 | --mips_opts.noreorder; | |
4085 | } | |
8ea7f4e8 ILT |
4086 | else |
4087 | { | |
4088 | expr1.X_add_number = 8; | |
4089 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4090 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 | 4091 | |
edc8f76e JL |
4092 | /* We want to close the noreorder block as soon as possible, so |
4093 | that later insns are available for delay slot filling. */ | |
4094 | --mips_opts.noreorder; | |
4095 | ||
d9c2c0c5 FCE |
4096 | /* start-sanitize-r5900 */ |
4097 | if (mips_5900) | |
4098 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
4099 | else | |
4100 | /* end-sanitize-r5900 */ | |
4101 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 4102 | } |
0dd2d296 | 4103 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 4104 | break; |
3d3c5039 ILT |
4105 | |
4106 | case M_DIV_3I: | |
8358c818 ILT |
4107 | s = "div"; |
4108 | s2 = "mflo"; | |
4109 | goto do_divi; | |
3d3c5039 | 4110 | case M_DIVU_3I: |
8358c818 ILT |
4111 | s = "divu"; |
4112 | s2 = "mflo"; | |
4113 | goto do_divi; | |
3d3c5039 | 4114 | case M_REM_3I: |
8358c818 ILT |
4115 | s = "div"; |
4116 | s2 = "mfhi"; | |
4117 | goto do_divi; | |
3d3c5039 | 4118 | case M_REMU_3I: |
8358c818 ILT |
4119 | s = "divu"; |
4120 | s2 = "mfhi"; | |
4121 | goto do_divi; | |
4122 | case M_DDIV_3I: | |
4123 | dbl = 1; | |
4124 | s = "ddiv"; | |
4125 | s2 = "mflo"; | |
4126 | goto do_divi; | |
4127 | case M_DDIVU_3I: | |
4128 | dbl = 1; | |
4129 | s = "ddivu"; | |
4130 | s2 = "mflo"; | |
4131 | goto do_divi; | |
4132 | case M_DREM_3I: | |
4133 | dbl = 1; | |
4134 | s = "ddiv"; | |
4135 | s2 = "mfhi"; | |
4136 | goto do_divi; | |
4137 | case M_DREMU_3I: | |
4138 | dbl = 1; | |
4139 | s = "ddivu"; | |
4140 | s2 = "mfhi"; | |
4141 | do_divi: | |
5c6f5923 | 4142 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 4143 | { |
48401fcf | 4144 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4145 | if (mips_trap) |
4146 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4147 | else | |
d9c2c0c5 FCE |
4148 | /* start-sanitize-r5900 */ |
4149 | if (mips_5900) | |
4150 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4151 | else | |
4152 | /* end-sanitize-r5900 */ | |
4153 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4154 | return; |
4155 | } | |
5c6f5923 | 4156 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4157 | { |
8358c818 | 4158 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4159 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4160 | sreg); | |
3d3c5039 | 4161 | else |
0dd2d296 | 4162 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4163 | return; |
4164 | } | |
5c6f5923 GRK |
4165 | if (imm_expr.X_op == O_constant |
4166 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4167 | && s[strlen (s) - 1] != 'u') |
4168 | { | |
4169 | if (strcmp (s2, "mflo") == 0) | |
4170 | { | |
4171 | if (dbl) | |
0dd2d296 ILT |
4172 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4173 | sreg); | |
8358c818 | 4174 | else |
0dd2d296 ILT |
4175 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4176 | sreg); | |
8358c818 ILT |
4177 | } |
4178 | else | |
0dd2d296 | 4179 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4180 | return; |
4181 | } | |
3d3c5039 | 4182 | |
d8a1c247 | 4183 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4184 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4185 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4186 | break; |
4187 | ||
4188 | case M_DIVU_3: | |
8358c818 ILT |
4189 | s = "divu"; |
4190 | s2 = "mflo"; | |
4191 | goto do_divu3; | |
670a50eb | 4192 | case M_REMU_3: |
8358c818 ILT |
4193 | s = "divu"; |
4194 | s2 = "mfhi"; | |
4195 | goto do_divu3; | |
4196 | case M_DDIVU_3: | |
4197 | s = "ddivu"; | |
4198 | s2 = "mflo"; | |
4199 | goto do_divu3; | |
4200 | case M_DREMU_3: | |
4201 | s = "ddivu"; | |
4202 | s2 = "mfhi"; | |
4203 | do_divu3: | |
fbcfacb7 | 4204 | mips_emit_delays (true); |
3c83da8a | 4205 | ++mips_opts.noreorder; |
0dd2d296 | 4206 | mips_any_noreorder = 1; |
8ea7f4e8 | 4207 | if (mips_trap) |
6c4b811d JL |
4208 | { |
4209 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4210 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
edc8f76e JL |
4211 | /* We want to close the noreorder block as soon as possible, so |
4212 | that later insns are available for delay slot filling. */ | |
4213 | --mips_opts.noreorder; | |
6c4b811d | 4214 | } |
8ea7f4e8 ILT |
4215 | else |
4216 | { | |
4217 | expr1.X_add_number = 8; | |
4218 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4219 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
edc8f76e JL |
4220 | |
4221 | /* We want to close the noreorder block as soon as possible, so | |
4222 | that later insns are available for delay slot filling. */ | |
4223 | --mips_opts.noreorder; | |
d9c2c0c5 FCE |
4224 | /* start-sanitize-r5900 */ |
4225 | if (mips_5900) | |
4226 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4227 | else | |
4228 | /* end-sanitize-r5900 */ | |
4229 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4230 | } |
0dd2d296 | 4231 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4232 | return; |
3d3c5039 | 4233 | |
d8a1c247 KR |
4234 | case M_DLA_AB: |
4235 | dbl = 1; | |
0dd2d296 | 4236 | case M_LA_AB: |
d9aba805 ILT |
4237 | /* Load the address of a symbol into a register. If breg is not |
4238 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4239 | |
4240 | /* When generating embedded PIC code, we permit expressions of | |
4241 | the form | |
4242 | la $4,foo-bar | |
4243 | where bar is an address in the .text section. These are used | |
4244 | when getting the addresses of functions. We don't permit | |
4245 | X_add_number to be non-zero, because if the symbol is | |
4246 | external the relaxing code needs to know that any addend is | |
4247 | purely the offset to X_op_symbol. */ | |
4248 | if (mips_pic == EMBEDDED_PIC | |
4249 | && offset_expr.X_op == O_subtract | |
4250 | && now_seg == text_section | |
847a01cd ILT |
4251 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4252 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4253 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4254 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4255 | ->sy_value.X_add_symbol) | |
4256 | == text_section))) | |
ecd4ca1c ILT |
4257 | && breg == 0 |
4258 | && offset_expr.X_add_number == 0) | |
4259 | { | |
4260 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4261 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4262 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4263 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4264 | || mips_opts.isa < 3) | |
4265 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4266 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4267 | return; | |
4268 | } | |
4269 | ||
0dd2d296 ILT |
4270 | if (offset_expr.X_op != O_symbol |
4271 | && offset_expr.X_op != O_constant) | |
670a50eb | 4272 | { |
48401fcf | 4273 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
4274 | offset_expr.X_op = O_constant; |
4275 | } | |
4276 | ||
4277 | if (treg == breg) | |
4278 | { | |
4279 | tempreg = AT; | |
4280 | used_at = 1; | |
3d3c5039 | 4281 | } |
670a50eb ILT |
4282 | else |
4283 | { | |
0dd2d296 ILT |
4284 | tempreg = treg; |
4285 | used_at = 0; | |
670a50eb | 4286 | } |
3d3c5039 | 4287 | |
5ac34ac3 | 4288 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4289 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4290 | else if (mips_pic == NO_PIC) |
670a50eb | 4291 | { |
0dd2d296 ILT |
4292 | /* If this is a reference to an GP relative symbol, we want |
4293 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4294 | Otherwise we want | |
4295 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4296 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4297 | If we have a constant, we need two instructions anyhow, | |
4298 | so we may as well always use the latter form. */ | |
7a15a226 | 4299 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4300 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4301 | p = NULL; |
4302 | else | |
4303 | { | |
8ea7f4e8 | 4304 | frag_grow (20); |
0dd2d296 | 4305 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4306 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4307 | || mips_opts.isa < 3) | |
4308 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4309 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4310 | p = frag_var (rs_machine_dependent, 8, 0, | |
4311 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4312 | mips_opts.warn_about_macros), |
f59fb6ca | 4313 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4314 | (char *) NULL); |
4315 | } | |
4316 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4317 | if (p != NULL) | |
4318 | p += 4; | |
4319 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4320 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4321 | || mips_opts.isa < 3) | |
4322 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4323 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4324 | } | |
fb251650 | 4325 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4326 | { |
4327 | /* If this is a reference to an external symbol, and there | |
4328 | is no constant, we want | |
4329 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4330 | For a local symbol, we want | |
4331 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4332 | nop | |
4333 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4334 | ||
4335 | If we have a small constant, and this is a reference to | |
4336 | an external symbol, we want | |
4337 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4338 | nop | |
4339 | addiu $tempreg,$tempreg,<constant> | |
4340 | For a local symbol, we want the same instruction | |
4341 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4342 | addiu instruction. | |
4343 | ||
4344 | If we have a large constant, and this is a reference to | |
4345 | an external symbol, we want | |
4346 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4347 | lui $at,<hiconstant> | |
4348 | addiu $at,$at,<loconstant> | |
4349 | addu $tempreg,$tempreg,$at | |
4350 | For a local symbol, we want the same instruction | |
4351 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4352 | addiu instruction. */ | |
4353 | expr1.X_add_number = offset_expr.X_add_number; | |
4354 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4355 | frag_grow (32); |
0dd2d296 | 4356 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4357 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4358 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4359 | if (expr1.X_add_number == 0) | |
4360 | { | |
4361 | int off; | |
4362 | ||
4363 | if (breg == 0) | |
4364 | off = 0; | |
4365 | else | |
4366 | { | |
4367 | /* We're going to put in an addu instruction using | |
4368 | tempreg, so we may as well insert the nop right | |
4369 | now. */ | |
4370 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4371 | "nop", ""); | |
4372 | off = 4; | |
4373 | } | |
4374 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4375 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4376 | (breg == 0 | |
3c83da8a | 4377 | ? mips_opts.warn_about_macros |
0dd2d296 | 4378 | : 0)), |
f59fb6ca | 4379 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4380 | (char *) NULL); |
4381 | if (breg == 0) | |
4382 | { | |
4383 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4384 | p += 4; | |
4385 | } | |
4386 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4387 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4388 | || mips_opts.isa < 3) | |
4389 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4390 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4391 | /* FIXME: If breg == 0, and the next instruction uses | |
4392 | $tempreg, then if this variant case is used an extra | |
4393 | nop will be generated. */ | |
4394 | } | |
4395 | else if (expr1.X_add_number >= -0x8000 | |
4396 | && expr1.X_add_number < 0x8000) | |
4397 | { | |
4398 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4399 | "nop", ""); | |
4400 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4401 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4402 | || mips_opts.isa < 3) | |
4403 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4404 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4405 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4406 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4407 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4408 | (char *) NULL); |
4409 | } | |
4410 | else | |
4411 | { | |
4412 | int off1; | |
4413 | ||
4414 | /* If we are going to add in a base register, and the | |
4415 | target register and the base register are the same, | |
4416 | then we are using AT as a temporary register. Since | |
4417 | we want to load the constant into AT, we add our | |
4418 | current AT (from the global offset table) and the | |
4419 | register into the register now, and pretend we were | |
4420 | not using a base register. */ | |
4421 | if (breg != treg) | |
4422 | off1 = 0; | |
4423 | else | |
4424 | { | |
4425 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4426 | "nop", ""); | |
4427 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4428 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4429 | || mips_opts.isa < 3) | |
4430 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4431 | "d,v,t", treg, AT, breg); |
4432 | breg = 0; | |
4433 | tempreg = treg; | |
4434 | off1 = -8; | |
4435 | } | |
4436 | ||
55933a58 ILT |
4437 | /* Set mips_optimize around the lui instruction to avoid |
4438 | inserting an unnecessary nop after the lw. */ | |
4439 | hold_mips_optimize = mips_optimize; | |
4440 | mips_optimize = 2; | |
0dd2d296 | 4441 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4442 | mips_optimize = hold_mips_optimize; |
4443 | ||
0dd2d296 | 4444 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4445 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4446 | || mips_opts.isa < 3) | |
4447 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4448 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4450 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4451 | || mips_opts.isa < 3) | |
4452 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4453 | "d,v,t", tempreg, tempreg, AT); |
4454 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4455 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4456 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4457 | (char *) NULL); |
4458 | used_at = 1; | |
4459 | } | |
670a50eb | 4460 | } |
fb251650 ILT |
4461 | else if (mips_pic == SVR4_PIC) |
4462 | { | |
4463 | int gpdel; | |
4464 | ||
4465 | /* This is the large GOT case. If this is a reference to an | |
4466 | external symbol, and there is no constant, we want | |
4467 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4468 | addu $tempreg,$tempreg,$gp | |
4469 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4470 | For a local symbol, we want | |
4471 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4472 | nop | |
4473 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4474 | ||
4475 | If we have a small constant, and this is a reference to | |
4476 | an external symbol, we want | |
4477 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4478 | addu $tempreg,$tempreg,$gp | |
4479 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4480 | nop | |
4481 | addiu $tempreg,$tempreg,<constant> | |
4482 | For a local symbol, we want | |
4483 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4484 | nop | |
4485 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4486 | ||
4487 | If we have a large constant, and this is a reference to | |
4488 | an external symbol, we want | |
4489 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4490 | addu $tempreg,$tempreg,$gp | |
4491 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4492 | lui $at,<hiconstant> | |
4493 | addiu $at,$at,<loconstant> | |
4494 | addu $tempreg,$tempreg,$at | |
4495 | For a local symbol, we want | |
4496 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4497 | lui $at,<hiconstant> | |
4498 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4499 | addu $tempreg,$tempreg,$at | |
4500 | */ | |
4501 | expr1.X_add_number = offset_expr.X_add_number; | |
4502 | offset_expr.X_add_number = 0; | |
4503 | frag_grow (52); | |
4504 | if (reg_needs_delay (GP)) | |
4505 | gpdel = 4; | |
4506 | else | |
4507 | gpdel = 0; | |
4508 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4509 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4511 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4512 | || mips_opts.isa < 3) | |
4513 | ? "addu" : "daddu"), | |
fb251650 ILT |
4514 | "d,v,t", tempreg, tempreg, GP); |
4515 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4516 | dbl ? "ld" : "lw", | |
4517 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4518 | tempreg); | |
4519 | if (expr1.X_add_number == 0) | |
4520 | { | |
4521 | int off; | |
4522 | ||
4523 | if (breg == 0) | |
4524 | off = 0; | |
4525 | else | |
4526 | { | |
4527 | /* We're going to put in an addu instruction using | |
4528 | tempreg, so we may as well insert the nop right | |
4529 | now. */ | |
4530 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4531 | "nop", ""); | |
4532 | off = 4; | |
4533 | } | |
4534 | ||
4535 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4536 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4537 | 8 + gpdel, 0, | |
4538 | (breg == 0 | |
3c83da8a | 4539 | ? mips_opts.warn_about_macros |
fb251650 | 4540 | : 0)), |
f59fb6ca | 4541 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4542 | (char *) NULL); |
4543 | } | |
4544 | else if (expr1.X_add_number >= -0x8000 | |
4545 | && expr1.X_add_number < 0x8000) | |
4546 | { | |
4547 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4548 | "nop", ""); | |
4549 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4550 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4551 | || mips_opts.isa < 3) | |
4552 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4553 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4554 | ||
4555 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4556 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4557 | (breg == 0 | |
3c83da8a | 4558 | ? mips_opts.warn_about_macros |
fb251650 | 4559 | : 0)), |
f59fb6ca | 4560 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4561 | (char *) NULL); |
4562 | } | |
4563 | else | |
4564 | { | |
4565 | int adj, dreg; | |
4566 | ||
4567 | /* If we are going to add in a base register, and the | |
4568 | target register and the base register are the same, | |
4569 | then we are using AT as a temporary register. Since | |
4570 | we want to load the constant into AT, we add our | |
4571 | current AT (from the global offset table) and the | |
4572 | register into the register now, and pretend we were | |
4573 | not using a base register. */ | |
4574 | if (breg != treg) | |
4575 | { | |
4576 | adj = 0; | |
4577 | dreg = tempreg; | |
4578 | } | |
4579 | else | |
4580 | { | |
4581 | assert (tempreg == AT); | |
4582 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4583 | "nop", ""); | |
4584 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4585 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4586 | || mips_opts.isa < 3) | |
4587 | ? "addu" : "daddu"), | |
fb251650 ILT |
4588 | "d,v,t", treg, AT, breg); |
4589 | dreg = treg; | |
4590 | adj = 8; | |
4591 | } | |
4592 | ||
4593 | /* Set mips_optimize around the lui instruction to avoid | |
4594 | inserting an unnecessary nop after the lw. */ | |
4595 | hold_mips_optimize = mips_optimize; | |
4596 | mips_optimize = 2; | |
4597 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4598 | mips_optimize = hold_mips_optimize; | |
4599 | ||
4600 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4601 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4602 | || mips_opts.isa < 3) | |
4603 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4604 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4606 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4607 | || mips_opts.isa < 3) | |
4608 | ? "addu" : "daddu"), | |
fb251650 ILT |
4609 | "d,v,t", dreg, dreg, AT); |
4610 | ||
4611 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4612 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4613 | 8 + gpdel, 0, | |
4614 | (breg == 0 | |
3c83da8a | 4615 | ? mips_opts.warn_about_macros |
fb251650 | 4616 | : 0)), |
f59fb6ca | 4617 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4618 | (char *) NULL); |
4619 | ||
4620 | used_at = 1; | |
4621 | } | |
4622 | ||
4623 | if (gpdel > 0) | |
4624 | { | |
4625 | /* This is needed because this instruction uses $gp, but | |
4626 | the first instruction on the main stream does not. */ | |
4627 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4628 | p += 4; | |
4629 | } | |
4630 | macro_build (p, &icnt, &offset_expr, | |
4631 | dbl ? "ld" : "lw", | |
4632 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4633 | p += 4; | |
4634 | if (expr1.X_add_number >= -0x8000 | |
4635 | && expr1.X_add_number < 0x8000) | |
4636 | { | |
4637 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4638 | p += 4; | |
4639 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4640 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4641 | || mips_opts.isa < 3) | |
4642 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4643 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4644 | /* FIXME: If add_number is 0, and there was no base | |
4645 | register, the external symbol case ended with a load, | |
4646 | so if the symbol turns out to not be external, and | |
4647 | the next instruction uses tempreg, an unnecessary nop | |
4648 | will be inserted. */ | |
4649 | } | |
4650 | else | |
4651 | { | |
4652 | if (breg == treg) | |
4653 | { | |
4654 | /* We must add in the base register now, as in the | |
4655 | external symbol case. */ | |
4656 | assert (tempreg == AT); | |
4657 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4658 | p += 4; | |
4659 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4660 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4661 | || mips_opts.isa < 3) | |
4662 | ? "addu" : "daddu"), | |
fb251650 ILT |
4663 | "d,v,t", treg, AT, breg); |
4664 | p += 4; | |
4665 | tempreg = treg; | |
4666 | /* We set breg to 0 because we have arranged to add | |
4667 | it in in both cases. */ | |
4668 | breg = 0; | |
4669 | } | |
4670 | ||
4671 | macro_build_lui (p, &icnt, &expr1, AT); | |
4672 | p += 4; | |
4673 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4674 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4675 | || mips_opts.isa < 3) | |
4676 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4677 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4678 | p += 4; | |
4679 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4680 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4681 | || mips_opts.isa < 3) | |
4682 | ? "addu" : "daddu"), | |
fb251650 ILT |
4683 | "d,v,t", tempreg, tempreg, AT); |
4684 | p += 4; | |
4685 | } | |
4686 | } | |
d9aba805 ILT |
4687 | else if (mips_pic == EMBEDDED_PIC) |
4688 | { | |
4689 | /* We use | |
4690 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4691 | */ | |
4692 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4693 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4694 | || mips_opts.isa < 3) | |
4695 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4696 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4697 | } | |
4698 | else | |
4699 | abort (); | |
0dd2d296 | 4700 | |
670a50eb | 4701 | if (breg != 0) |
0dd2d296 | 4702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4703 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4704 | || mips_opts.isa < 3) | |
4705 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4706 | "d,v,t", treg, tempreg, breg); |
4707 | ||
4708 | if (! used_at) | |
4709 | return; | |
4710 | ||
4711 | break; | |
4712 | ||
4713 | case M_J_A: | |
4714 | /* The j instruction may not be used in PIC code, since it | |
4715 | requires an absolute address. We convert it to a b | |
4716 | instruction. */ | |
d9aba805 | 4717 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4718 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4719 | else | |
4720 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4721 | return; |
3d3c5039 | 4722 | |
9226253a ILT |
4723 | /* The jal instructions must be handled as macros because when |
4724 | generating PIC code they expand to multi-instruction | |
4725 | sequences. Normally they are simple instructions. */ | |
4726 | case M_JAL_1: | |
4727 | dreg = RA; | |
4728 | /* Fall through. */ | |
4729 | case M_JAL_2: | |
d9aba805 ILT |
4730 | if (mips_pic == NO_PIC |
4731 | || mips_pic == EMBEDDED_PIC) | |
4732 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4733 | "d,s", dreg, sreg); | |
4734 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4735 | { |
d9aba805 | 4736 | if (sreg != PIC_CALL_REG) |
48401fcf | 4737 | as_warn (_("MIPS PIC call to register other than $25")); |
d9aba805 | 4738 | |
0dd2d296 ILT |
4739 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4740 | "d,s", dreg, sreg); | |
d9aba805 | 4741 | if (mips_cprestore_offset < 0) |
48401fcf | 4742 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4743 | else |
4744 | { | |
4745 | expr1.X_add_number = mips_cprestore_offset; | |
4746 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4747 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4748 | || mips_opts.isa < 3) | |
4749 | ? "lw" : "ld"), | |
d9aba805 ILT |
4750 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4751 | } | |
9226253a | 4752 | } |
0dd2d296 | 4753 | else |
d9aba805 ILT |
4754 | abort (); |
4755 | ||
9226253a ILT |
4756 | return; |
4757 | ||
4758 | case M_JAL_A: | |
d9aba805 ILT |
4759 | if (mips_pic == NO_PIC) |
4760 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4761 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4762 | { |
fb251650 ILT |
4763 | /* If this is a reference to an external symbol, and we are |
4764 | using a small GOT, we want | |
d9aba805 ILT |
4765 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4766 | nop | |
4767 | jalr $25 | |
4768 | nop | |
4769 | lw $gp,cprestore($sp) | |
4770 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4771 | pseudo-op. If we are using a big GOT, we want |
4772 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4773 | addu $25,$25,$gp | |
4774 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4775 | nop | |
4776 | jalr $25 | |
4777 | nop | |
4778 | lw $gp,cprestore($sp) | |
4779 | If the symbol is not external, we want | |
d9aba805 ILT |
4780 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4781 | nop | |
4782 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4783 | jalr $25 | |
4784 | nop | |
fb251650 ILT |
4785 | lw $gp,cprestore($sp) */ |
4786 | frag_grow (40); | |
4787 | if (! mips_big_got) | |
4788 | { | |
4789 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4790 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4791 | || mips_opts.isa < 3) | |
4792 | ? "lw" : "ld"), | |
fb251650 ILT |
4793 | "t,o(b)", PIC_CALL_REG, |
4794 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4795 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4796 | "nop", ""); | |
4797 | p = frag_var (rs_machine_dependent, 4, 0, | |
4798 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4799 | offset_expr.X_add_symbol, (offsetT) 0, |
4800 | (char *) NULL); | |
fb251650 ILT |
4801 | } |
4802 | else | |
4803 | { | |
4804 | int gpdel; | |
4805 | ||
4806 | if (reg_needs_delay (GP)) | |
4807 | gpdel = 4; | |
4808 | else | |
4809 | gpdel = 0; | |
4810 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4811 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4813 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4814 | || mips_opts.isa < 3) | |
4815 | ? "addu" : "daddu"), | |
fb251650 ILT |
4816 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4817 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4818 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4819 | || mips_opts.isa < 3) | |
4820 | ? "lw" : "ld"), | |
fb251650 ILT |
4821 | "t,o(b)", PIC_CALL_REG, |
4822 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4823 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4824 | "nop", ""); | |
4825 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4826 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4827 | 0, 0), | |
f59fb6ca ILT |
4828 | offset_expr.X_add_symbol, (offsetT) 0, |
4829 | (char *) NULL); | |
fb251650 ILT |
4830 | if (gpdel > 0) |
4831 | { | |
4832 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4833 | p += 4; | |
4834 | } | |
4835 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4836 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4837 | || mips_opts.isa < 3) | |
4838 | ? "lw" : "ld"), | |
fb251650 ILT |
4839 | "t,o(b)", PIC_CALL_REG, |
4840 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4841 | p += 4; | |
4842 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4843 | p += 4; | |
4844 | } | |
d9aba805 | 4845 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4846 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4847 | || mips_opts.isa < 3) | |
4848 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4849 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4850 | (int) BFD_RELOC_LO16); | |
4851 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4852 | "jalr", "s", PIC_CALL_REG); | |
4853 | if (mips_cprestore_offset < 0) | |
48401fcf | 4854 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4855 | else |
4856 | { | |
3c83da8a | 4857 | if (mips_opts.noreorder) |
d9aba805 ILT |
4858 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4859 | "nop", ""); | |
4860 | expr1.X_add_number = mips_cprestore_offset; | |
4861 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4862 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4863 | || mips_opts.isa < 3) | |
4864 | ? "lw" : "ld"), | |
d9aba805 ILT |
4865 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4866 | mips_frame_reg); | |
4867 | } | |
0dd2d296 | 4868 | } |
d9aba805 | 4869 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4870 | { |
4871 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4872 | /* The linker may expand the call to a longer sequence which | |
4873 | uses $at, so we must break rather than return. */ | |
4874 | break; | |
4875 | } | |
d9aba805 ILT |
4876 | else |
4877 | abort (); | |
4878 | ||
9226253a ILT |
4879 | return; |
4880 | ||
3d3c5039 | 4881 | case M_LB_AB: |
670a50eb ILT |
4882 | s = "lb"; |
4883 | goto ld; | |
3d3c5039 | 4884 | case M_LBU_AB: |
670a50eb ILT |
4885 | s = "lbu"; |
4886 | goto ld; | |
3d3c5039 | 4887 | case M_LH_AB: |
670a50eb ILT |
4888 | s = "lh"; |
4889 | goto ld; | |
3d3c5039 | 4890 | case M_LHU_AB: |
670a50eb ILT |
4891 | s = "lhu"; |
4892 | goto ld; | |
3d3c5039 | 4893 | case M_LW_AB: |
670a50eb ILT |
4894 | s = "lw"; |
4895 | goto ld; | |
3d3c5039 | 4896 | case M_LWC0_AB: |
670a50eb | 4897 | s = "lwc0"; |
efec4a28 | 4898 | /* Itbl support may require additional care here. */ |
8358c818 | 4899 | coproc = 1; |
670a50eb | 4900 | goto ld; |
3d3c5039 | 4901 | case M_LWC1_AB: |
670a50eb | 4902 | s = "lwc1"; |
efec4a28 | 4903 | /* Itbl support may require additional care here. */ |
8358c818 | 4904 | coproc = 1; |
670a50eb | 4905 | goto ld; |
3d3c5039 | 4906 | case M_LWC2_AB: |
670a50eb | 4907 | s = "lwc2"; |
efec4a28 | 4908 | /* Itbl support may require additional care here. */ |
8358c818 | 4909 | coproc = 1; |
670a50eb | 4910 | goto ld; |
3d3c5039 | 4911 | case M_LWC3_AB: |
670a50eb | 4912 | s = "lwc3"; |
efec4a28 | 4913 | /* Itbl support may require additional care here. */ |
8358c818 | 4914 | coproc = 1; |
670a50eb | 4915 | goto ld; |
3d3c5039 | 4916 | case M_LWL_AB: |
670a50eb | 4917 | s = "lwl"; |
b2b8c24e | 4918 | lr = 1; |
670a50eb | 4919 | goto ld; |
3d3c5039 | 4920 | case M_LWR_AB: |
670a50eb | 4921 | s = "lwr"; |
b2b8c24e | 4922 | lr = 1; |
8358c818 ILT |
4923 | goto ld; |
4924 | case M_LDC1_AB: | |
1c6f3441 ILT |
4925 | if (mips_4650) |
4926 | { | |
48401fcf | 4927 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
4928 | return; |
4929 | } | |
8358c818 | 4930 | s = "ldc1"; |
efec4a28 | 4931 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4932 | coproc = 1; |
4933 | goto ld; | |
4934 | case M_LDC2_AB: | |
4935 | s = "ldc2"; | |
efec4a28 | 4936 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4937 | coproc = 1; |
4938 | goto ld; | |
4939 | case M_LDC3_AB: | |
4940 | s = "ldc3"; | |
efec4a28 | 4941 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4942 | coproc = 1; |
4943 | goto ld; | |
4944 | case M_LDL_AB: | |
4945 | s = "ldl"; | |
b2b8c24e | 4946 | lr = 1; |
8358c818 ILT |
4947 | goto ld; |
4948 | case M_LDR_AB: | |
4949 | s = "ldr"; | |
b2b8c24e | 4950 | lr = 1; |
8358c818 ILT |
4951 | goto ld; |
4952 | case M_LL_AB: | |
4953 | s = "ll"; | |
4954 | goto ld; | |
4955 | case M_LLD_AB: | |
4956 | s = "lld"; | |
4957 | goto ld; | |
4958 | case M_LWU_AB: | |
4959 | s = "lwu"; | |
3d3c5039 | 4960 | ld: |
b2b8c24e | 4961 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4962 | { |
4963 | tempreg = AT; | |
4964 | used_at = 1; | |
4965 | } | |
4966 | else | |
4967 | { | |
4968 | tempreg = treg; | |
4969 | used_at = 0; | |
4970 | } | |
4971 | goto ld_st; | |
3d3c5039 | 4972 | case M_SB_AB: |
670a50eb ILT |
4973 | s = "sb"; |
4974 | goto st; | |
3d3c5039 | 4975 | case M_SH_AB: |
670a50eb ILT |
4976 | s = "sh"; |
4977 | goto st; | |
3d3c5039 | 4978 | case M_SW_AB: |
670a50eb ILT |
4979 | s = "sw"; |
4980 | goto st; | |
3d3c5039 | 4981 | case M_SWC0_AB: |
670a50eb | 4982 | s = "swc0"; |
efec4a28 | 4983 | /* Itbl support may require additional care here. */ |
8358c818 | 4984 | coproc = 1; |
670a50eb | 4985 | goto st; |
3d3c5039 | 4986 | case M_SWC1_AB: |
670a50eb | 4987 | s = "swc1"; |
efec4a28 | 4988 | /* Itbl support may require additional care here. */ |
8358c818 | 4989 | coproc = 1; |
670a50eb | 4990 | goto st; |
3d3c5039 | 4991 | case M_SWC2_AB: |
670a50eb | 4992 | s = "swc2"; |
efec4a28 | 4993 | /* Itbl support may require additional care here. */ |
8358c818 | 4994 | coproc = 1; |
670a50eb | 4995 | goto st; |
3d3c5039 | 4996 | case M_SWC3_AB: |
670a50eb | 4997 | s = "swc3"; |
efec4a28 | 4998 | /* Itbl support may require additional care here. */ |
8358c818 | 4999 | coproc = 1; |
670a50eb | 5000 | goto st; |
3d3c5039 | 5001 | case M_SWL_AB: |
670a50eb ILT |
5002 | s = "swl"; |
5003 | goto st; | |
3d3c5039 | 5004 | case M_SWR_AB: |
670a50eb | 5005 | s = "swr"; |
8358c818 ILT |
5006 | goto st; |
5007 | case M_SC_AB: | |
5008 | s = "sc"; | |
5009 | goto st; | |
5010 | case M_SCD_AB: | |
5011 | s = "scd"; | |
5012 | goto st; | |
5013 | case M_SDC1_AB: | |
1c6f3441 ILT |
5014 | if (mips_4650) |
5015 | { | |
48401fcf | 5016 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5017 | return; |
5018 | } | |
8358c818 ILT |
5019 | s = "sdc1"; |
5020 | coproc = 1; | |
efec4a28 | 5021 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5022 | goto st; |
5023 | case M_SDC2_AB: | |
5024 | s = "sdc2"; | |
efec4a28 | 5025 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5026 | coproc = 1; |
5027 | goto st; | |
5028 | case M_SDC3_AB: | |
5029 | s = "sdc3"; | |
efec4a28 | 5030 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5031 | coproc = 1; |
5032 | goto st; | |
5033 | case M_SDL_AB: | |
5034 | s = "sdl"; | |
5035 | goto st; | |
5036 | case M_SDR_AB: | |
5037 | s = "sdr"; | |
3d3c5039 | 5038 | st: |
670a50eb ILT |
5039 | tempreg = AT; |
5040 | used_at = 1; | |
3d3c5039 | 5041 | ld_st: |
efec4a28 | 5042 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5043 | if (mask == M_LWC1_AB |
5044 | || mask == M_SWC1_AB | |
8358c818 | 5045 | || mask == M_LDC1_AB |
0dd2d296 ILT |
5046 | || mask == M_SDC1_AB |
5047 | || mask == M_L_DAB | |
5048 | || mask == M_S_DAB) | |
670a50eb | 5049 | fmt = "T,o(b)"; |
8358c818 | 5050 | else if (coproc) |
19ed8960 | 5051 | fmt = "E,o(b)"; |
670a50eb ILT |
5052 | else |
5053 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
5054 | |
5055 | if (offset_expr.X_op != O_constant | |
5056 | && offset_expr.X_op != O_symbol) | |
5057 | { | |
48401fcf | 5058 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5059 | offset_expr.X_op = O_constant; |
5060 | } | |
5061 | ||
5062 | /* A constant expression in PIC code can be handled just as it | |
5063 | is in non PIC code. */ | |
d9aba805 | 5064 | if (mips_pic == NO_PIC |
0dd2d296 | 5065 | || offset_expr.X_op == O_constant) |
670a50eb | 5066 | { |
0dd2d296 ILT |
5067 | /* If this is a reference to a GP relative symbol, and there |
5068 | is no base register, we want | |
5069 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 5070 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
5071 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
5072 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5073 | If we have a constant, we need two instructions anyhow, | |
5074 | so we always use the latter form. | |
5075 | ||
5076 | If we have a base register, and this is a reference to a | |
5077 | GP relative symbol, we want | |
5078 | addu $tempreg,$breg,$gp | |
5079 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5080 | Otherwise we want | |
5081 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5082 | addu $tempreg,$tempreg,$breg | |
5083 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5084 | With a constant we always use the latter case. */ | |
670a50eb ILT |
5085 | if (breg == 0) |
5086 | { | |
7a15a226 | 5087 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5088 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5089 | p = NULL; |
5090 | else | |
5091 | { | |
8ea7f4e8 | 5092 | frag_grow (20); |
0dd2d296 ILT |
5093 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5094 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5095 | p = frag_var (rs_machine_dependent, 8, 0, | |
5096 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
5097 | (mips_opts.warn_about_macros |
5098 | || (used_at | |
5099 | && mips_opts.noat))), | |
f59fb6ca | 5100 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5101 | (char *) NULL); |
8197b589 | 5102 | used_at = 0; |
0dd2d296 ILT |
5103 | } |
5104 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5105 | if (p != NULL) | |
5106 | p += 4; | |
5107 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5108 | (int) BFD_RELOC_LO16, tempreg); | |
5109 | } | |
5110 | else | |
5111 | { | |
7a15a226 | 5112 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5113 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5114 | p = NULL; |
5115 | else | |
5116 | { | |
8ea7f4e8 | 5117 | frag_grow (28); |
0dd2d296 | 5118 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5119 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5120 | || mips_opts.isa < 3) | |
5121 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5122 | "d,v,t", tempreg, breg, GP); |
5123 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5124 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5125 | p = frag_var (rs_machine_dependent, 12, 0, | |
5126 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 5127 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5128 | (char *) NULL); |
5129 | } | |
5130 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5131 | if (p != NULL) | |
5132 | p += 4; | |
5133 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5134 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5135 | || mips_opts.isa < 3) | |
5136 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5137 | "d,v,t", tempreg, tempreg, breg); |
5138 | if (p != NULL) | |
5139 | p += 4; | |
5140 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5141 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5142 | } |
670a50eb | 5143 | } |
fb251650 | 5144 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5145 | { |
0dd2d296 ILT |
5146 | /* If this is a reference to an external symbol, we want |
5147 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5148 | nop | |
5149 | <op> $treg,0($tempreg) | |
5150 | Otherwise we want | |
5151 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5152 | nop | |
5153 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5154 | <op> $treg,0($tempreg) | |
5155 | If there is a base register, we add it to $tempreg before | |
5156 | the <op>. If there is a constant, we stick it in the | |
5157 | <op> instruction. We don't handle constants larger than | |
5158 | 16 bits, because we have no way to load the upper 16 bits | |
5159 | (actually, we could handle them for the subset of cases | |
5160 | in which we are not using $at). */ | |
5161 | assert (offset_expr.X_op == O_symbol); | |
5162 | expr1.X_add_number = offset_expr.X_add_number; | |
5163 | offset_expr.X_add_number = 0; | |
5164 | if (expr1.X_add_number < -0x8000 | |
5165 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5166 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
8ea7f4e8 | 5167 | frag_grow (20); |
0dd2d296 | 5168 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5169 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5170 | || mips_opts.isa < 3) | |
5171 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5172 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5173 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5174 | p = frag_var (rs_machine_dependent, 4, 0, | |
5175 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5176 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5177 | (char *) NULL); |
5178 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5179 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5180 | || mips_opts.isa < 3) | |
5181 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5182 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5183 | if (breg != 0) |
0dd2d296 | 5184 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5185 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5186 | || mips_opts.isa < 3) | |
5187 | ? "addu" : "daddu"), | |
6e8dda9c | 5188 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5189 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5190 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5191 | } |
fb251650 ILT |
5192 | else if (mips_pic == SVR4_PIC) |
5193 | { | |
5194 | int gpdel; | |
5195 | ||
5196 | /* If this is a reference to an external symbol, we want | |
5197 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5198 | addu $tempreg,$tempreg,$gp | |
5199 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5200 | <op> $treg,0($tempreg) | |
5201 | Otherwise we want | |
5202 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5203 | nop | |
5204 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5205 | <op> $treg,0($tempreg) | |
5206 | If there is a base register, we add it to $tempreg before | |
5207 | the <op>. If there is a constant, we stick it in the | |
5208 | <op> instruction. We don't handle constants larger than | |
5209 | 16 bits, because we have no way to load the upper 16 bits | |
5210 | (actually, we could handle them for the subset of cases | |
5211 | in which we are not using $at). */ | |
5212 | assert (offset_expr.X_op == O_symbol); | |
5213 | expr1.X_add_number = offset_expr.X_add_number; | |
5214 | offset_expr.X_add_number = 0; | |
5215 | if (expr1.X_add_number < -0x8000 | |
5216 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5217 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5218 | if (reg_needs_delay (GP)) |
5219 | gpdel = 4; | |
5220 | else | |
5221 | gpdel = 0; | |
5222 | frag_grow (36); | |
5223 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5224 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5225 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5226 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5227 | || mips_opts.isa < 3) | |
5228 | ? "addu" : "daddu"), | |
fb251650 ILT |
5229 | "d,v,t", tempreg, tempreg, GP); |
5230 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5231 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5232 | || mips_opts.isa < 3) | |
5233 | ? "lw" : "ld"), | |
867a58b3 ILT |
5234 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5235 | tempreg); | |
fb251650 ILT |
5236 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5237 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5238 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5239 | if (gpdel > 0) |
5240 | { | |
5241 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5242 | p += 4; | |
5243 | } | |
5244 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5245 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5246 | || mips_opts.isa < 3) | |
5247 | ? "lw" : "ld"), | |
867a58b3 | 5248 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5249 | p += 4; |
5250 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5251 | p += 4; | |
5252 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5253 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5254 | || mips_opts.isa < 3) | |
5255 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5256 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5257 | if (breg != 0) | |
5258 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5259 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5260 | || mips_opts.isa < 3) | |
5261 | ? "addu" : "daddu"), | |
fb251650 ILT |
5262 | "d,v,t", tempreg, tempreg, breg); |
5263 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5264 | (int) BFD_RELOC_LO16, tempreg); | |
5265 | } | |
d9aba805 ILT |
5266 | else if (mips_pic == EMBEDDED_PIC) |
5267 | { | |
5268 | /* If there is no base register, we want | |
5269 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5270 | If there is a base register, we want | |
5271 | addu $tempreg,$breg,$gp | |
5272 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5273 | */ | |
5274 | assert (offset_expr.X_op == O_symbol); | |
5275 | if (breg == 0) | |
5276 | { | |
5277 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5278 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5279 | used_at = 0; | |
5280 | } | |
5281 | else | |
5282 | { | |
5283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5284 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5285 | || mips_opts.isa < 3) | |
5286 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5287 | "d,v,t", tempreg, breg, GP); |
5288 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5289 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5290 | } | |
5291 | } | |
5292 | else | |
5293 | abort (); | |
0dd2d296 ILT |
5294 | |
5295 | if (! used_at) | |
5296 | return; | |
5297 | ||
5298 | break; | |
3d3c5039 ILT |
5299 | |
5300 | case M_LI: | |
19ed8960 | 5301 | case M_LI_S: |
d8a1c247 KR |
5302 | load_register (&icnt, treg, &imm_expr, 0); |
5303 | return; | |
5304 | ||
5305 | case M_DLI: | |
5306 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5307 | return; |
3d3c5039 | 5308 | |
0dd2d296 | 5309 | case M_LI_SS: |
55933a58 | 5310 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5311 | { |
d8a1c247 | 5312 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5313 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5314 | "mtc1", "t,G", AT, treg); | |
5315 | break; | |
0dd2d296 | 5316 | } |
d9aba805 | 5317 | else |
d2c71068 | 5318 | { |
55933a58 ILT |
5319 | assert (offset_expr.X_op == O_symbol |
5320 | && strcmp (segment_name (S_GET_SEGMENT | |
5321 | (offset_expr.X_add_symbol)), | |
5322 | ".lit4") == 0 | |
5323 | && offset_expr.X_add_number == 0); | |
5324 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5325 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5326 | return; |
5327 | } | |
0dd2d296 | 5328 | |
3d3c5039 | 5329 | case M_LI_D: |
a5586bdc ILT |
5330 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5331 | the entire value, and in mips1 mode it is the high order 32 | |
5332 | bits of the value and the low order 32 bits are either zero | |
5333 | or in offset_expr. */ | |
5334 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5335 | { | |
517640d9 ILT |
5336 | if (mips_opts.isa >= 3) |
5337 | load_register (&icnt, treg, &imm_expr, 1); | |
5338 | else | |
a5586bdc | 5339 | { |
517640d9 ILT |
5340 | int hreg, lreg; |
5341 | ||
5342 | if (target_big_endian) | |
5343 | { | |
5344 | hreg = treg; | |
5345 | lreg = treg + 1; | |
5346 | } | |
a5586bdc ILT |
5347 | else |
5348 | { | |
517640d9 ILT |
5349 | hreg = treg + 1; |
5350 | lreg = treg; | |
5351 | } | |
5352 | ||
5353 | if (hreg <= 31) | |
5354 | load_register (&icnt, hreg, &imm_expr, 0); | |
5355 | if (lreg <= 31) | |
5356 | { | |
5357 | if (offset_expr.X_op == O_absent) | |
5358 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5359 | lreg, 0); | |
5360 | else | |
5361 | { | |
5362 | assert (offset_expr.X_op == O_constant); | |
5363 | load_register (&icnt, lreg, &offset_expr, 0); | |
5364 | } | |
a5586bdc ILT |
5365 | } |
5366 | } | |
5367 | return; | |
5368 | } | |
5369 | ||
d9aba805 ILT |
5370 | /* We know that sym is in the .rdata section. First we get the |
5371 | upper 16 bits of the address. */ | |
5372 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5373 | { |
5374 | /* FIXME: This won't work for a 64 bit address. */ | |
5375 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5376 | } | |
d9aba805 | 5377 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5378 | { |
5379 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5380 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5381 | || mips_opts.isa < 3) | |
5382 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5383 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5384 | } | |
d9aba805 ILT |
5385 | else if (mips_pic == EMBEDDED_PIC) |
5386 | { | |
5387 | /* For embedded PIC we pick up the entire address off $gp in | |
5388 | a single instruction. */ | |
5389 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5390 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5391 | || mips_opts.isa < 3) | |
5392 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5393 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5394 | offset_expr.X_op = O_constant; | |
5395 | offset_expr.X_add_number = 0; | |
5396 | } | |
5397 | else | |
5398 | abort (); | |
5399 | ||
0dd2d296 | 5400 | /* Now we load the register(s). */ |
3c83da8a | 5401 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5402 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5403 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5404 | else |
5405 | { | |
0dd2d296 ILT |
5406 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5407 | treg, (int) BFD_RELOC_LO16, AT); | |
5408 | if (treg != 31) | |
5409 | { | |
5410 | /* FIXME: How in the world do we deal with the possible | |
5411 | overflow here? */ | |
5412 | offset_expr.X_add_number += 4; | |
5413 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5414 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5415 | } | |
8358c818 | 5416 | } |
d2c71068 ILT |
5417 | |
5418 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5419 | does not become a variant frag. */ | |
5420 | frag_wane (frag_now); | |
5421 | frag_new (0); | |
5422 | ||
670a50eb | 5423 | break; |
3d3c5039 ILT |
5424 | |
5425 | case M_LI_DD: | |
a5586bdc ILT |
5426 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5427 | the entire value, and in mips1 mode it is the high order 32 | |
5428 | bits of the value and the low order 32 bits are either zero | |
5429 | or in offset_expr. */ | |
5430 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5431 | { | |
5432 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5433 | if (mips_opts.isa >= 3) | |
5434 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5435 | "dmtc1", "t,S", AT, treg); | |
5436 | else | |
5437 | { | |
5438 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5439 | "mtc1", "t,G", AT, treg + 1); | |
5440 | if (offset_expr.X_op == O_absent) | |
5441 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5442 | "mtc1", "t,G", 0, treg); | |
5443 | else | |
5444 | { | |
5445 | assert (offset_expr.X_op == O_constant); | |
5446 | load_register (&icnt, AT, &offset_expr, 0); | |
5447 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5448 | "mtc1", "t,G", AT, treg); | |
5449 | } | |
5450 | } | |
5451 | break; | |
5452 | } | |
5453 | ||
55933a58 ILT |
5454 | assert (offset_expr.X_op == O_symbol |
5455 | && offset_expr.X_add_number == 0); | |
5456 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5457 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5458 | { |
3c83da8a | 5459 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5460 | { |
5461 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5462 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5463 | return; | |
5464 | } | |
5465 | breg = GP; | |
5466 | r = BFD_RELOC_MIPS_LITERAL; | |
5467 | goto dob; | |
5468 | } | |
55933a58 | 5469 | else |
0dd2d296 | 5470 | { |
55933a58 ILT |
5471 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5472 | if (mips_pic == SVR4_PIC) | |
5473 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5474 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5475 | || mips_opts.isa < 3) | |
5476 | ? "lw" : "ld"), | |
55933a58 ILT |
5477 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5478 | else | |
5479 | { | |
5480 | /* FIXME: This won't work for a 64 bit address. */ | |
5481 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5482 | } | |
5483 | ||
3c83da8a | 5484 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5485 | { |
5486 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5487 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5488 | |
5489 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5490 | that this does not become a variant frag. */ | |
5491 | frag_wane (frag_now); | |
5492 | frag_new (0); | |
5493 | ||
0dd2d296 ILT |
5494 | break; |
5495 | } | |
5496 | breg = AT; | |
5497 | r = BFD_RELOC_LO16; | |
5498 | goto dob; | |
8358c818 | 5499 | } |
9226253a | 5500 | |
3d3c5039 | 5501 | case M_L_DOB: |
1c6f3441 ILT |
5502 | if (mips_4650) |
5503 | { | |
48401fcf | 5504 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5505 | return; |
5506 | } | |
9a7d824a ILT |
5507 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5508 | to adjust when loading from memory. */ | |
9226253a ILT |
5509 | r = BFD_RELOC_LO16; |
5510 | dob: | |
3c83da8a | 5511 | assert (mips_opts.isa < 2); |
0dd2d296 | 5512 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5513 | target_big_endian ? treg + 1 : treg, |
9226253a | 5514 | (int) r, breg); |
0dd2d296 ILT |
5515 | /* FIXME: A possible overflow which I don't know how to deal |
5516 | with. */ | |
670a50eb | 5517 | offset_expr.X_add_number += 4; |
0dd2d296 | 5518 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5519 | target_big_endian ? treg : treg + 1, |
9226253a | 5520 | (int) r, breg); |
d2c71068 ILT |
5521 | |
5522 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5523 | does not become a variant frag. */ | |
5524 | frag_wane (frag_now); | |
5525 | frag_new (0); | |
5526 | ||
0dd2d296 ILT |
5527 | if (breg != AT) |
5528 | return; | |
5529 | break; | |
3d3c5039 ILT |
5530 | |
5531 | case M_L_DAB: | |
670a50eb ILT |
5532 | /* |
5533 | * The MIPS assembler seems to check for X_add_number not | |
5534 | * being double aligned and generating: | |
5535 | * lui at,%hi(foo+1) | |
5536 | * addu at,at,v1 | |
5537 | * addiu at,at,%lo(foo+1) | |
5538 | * lwc1 f2,0(at) | |
5539 | * lwc1 f3,4(at) | |
5540 | * But, the resulting address is the same after relocation so why | |
5541 | * generate the extra instruction? | |
5542 | */ | |
1c6f3441 ILT |
5543 | if (mips_4650) |
5544 | { | |
48401fcf | 5545 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5546 | return; |
5547 | } | |
efec4a28 | 5548 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5549 | coproc = 1; |
3c83da8a | 5550 | if (mips_opts.isa >= 2) |
670a50eb | 5551 | { |
0dd2d296 ILT |
5552 | s = "ldc1"; |
5553 | goto ld; | |
670a50eb | 5554 | } |
0dd2d296 ILT |
5555 | |
5556 | s = "lwc1"; | |
5557 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5558 | goto ldd_std; |
5559 | ||
5560 | case M_S_DAB: | |
1c6f3441 ILT |
5561 | if (mips_4650) |
5562 | { | |
48401fcf | 5563 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5564 | return; |
5565 | } | |
5566 | ||
3c83da8a | 5567 | if (mips_opts.isa >= 2) |
8358c818 | 5568 | { |
0dd2d296 ILT |
5569 | s = "sdc1"; |
5570 | goto st; | |
8358c818 | 5571 | } |
3d3c5039 | 5572 | |
0dd2d296 ILT |
5573 | s = "swc1"; |
5574 | fmt = "T,o(b)"; | |
efec4a28 | 5575 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5576 | coproc = 1; |
5577 | goto ldd_std; | |
3d3c5039 ILT |
5578 | |
5579 | case M_LD_AB: | |
3c83da8a | 5580 | if (mips_opts.isa >= 3) |
670a50eb | 5581 | { |
0dd2d296 ILT |
5582 | s = "ld"; |
5583 | goto ld; | |
670a50eb | 5584 | } |
0dd2d296 ILT |
5585 | |
5586 | s = "lw"; | |
5587 | fmt = "t,o(b)"; | |
5588 | goto ldd_std; | |
5589 | ||
5590 | case M_SD_AB: | |
3c83da8a | 5591 | if (mips_opts.isa >= 3) |
670a50eb | 5592 | { |
0dd2d296 ILT |
5593 | s = "sd"; |
5594 | goto st; | |
670a50eb | 5595 | } |
0dd2d296 | 5596 | |
670a50eb | 5597 | s = "sw"; |
0dd2d296 ILT |
5598 | fmt = "t,o(b)"; |
5599 | ||
5600 | ldd_std: | |
5601 | if (offset_expr.X_op != O_symbol | |
5602 | && offset_expr.X_op != O_constant) | |
670a50eb | 5603 | { |
48401fcf | 5604 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5605 | offset_expr.X_op = O_constant; |
5606 | } | |
5607 | ||
5608 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5609 | to adjust when loading from memory. We set coproc if we must | |
5610 | load $fn+1 first. */ | |
efec4a28 | 5611 | /* Itbl support may require additional care here. */ |
b9129c6f | 5612 | if (! target_big_endian) |
0dd2d296 ILT |
5613 | coproc = 0; |
5614 | ||
d9aba805 | 5615 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5616 | || offset_expr.X_op == O_constant) |
5617 | { | |
5618 | /* If this is a reference to a GP relative symbol, we want | |
5619 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5620 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5621 | If we have a base register, we use this | |
5622 | addu $at,$breg,$gp | |
5623 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5624 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5625 | If this is not a GP relative symbol, we want | |
5626 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5627 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5628 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5629 | If there is a base register, we add it to $at after the | |
5630 | lui instruction. If there is a constant, we always use | |
5631 | the last case. */ | |
7a15a226 | 5632 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5633 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5634 | { |
0dd2d296 ILT |
5635 | p = NULL; |
5636 | used_at = 1; | |
670a50eb ILT |
5637 | } |
5638 | else | |
0dd2d296 ILT |
5639 | { |
5640 | int off; | |
5641 | ||
5642 | if (breg == 0) | |
5643 | { | |
8ea7f4e8 | 5644 | frag_grow (28); |
0dd2d296 ILT |
5645 | tempreg = GP; |
5646 | off = 0; | |
5647 | used_at = 0; | |
5648 | } | |
5649 | else | |
5650 | { | |
8ea7f4e8 | 5651 | frag_grow (36); |
0dd2d296 | 5652 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5653 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5654 | || mips_opts.isa < 3) | |
5655 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5656 | "d,v,t", AT, breg, GP); |
5657 | tempreg = AT; | |
5658 | off = 4; | |
5659 | used_at = 1; | |
5660 | } | |
5661 | ||
efec4a28 | 5662 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5663 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5664 | coproc ? treg + 1 : treg, | |
5665 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5666 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5667 | |
5668 | /* Set mips_optimize to 2 to avoid inserting an | |
5669 | undesired nop. */ | |
5670 | hold_mips_optimize = mips_optimize; | |
5671 | mips_optimize = 2; | |
efec4a28 | 5672 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5673 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5674 | coproc ? treg : treg + 1, | |
5675 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5676 | mips_optimize = hold_mips_optimize; |
5677 | ||
0dd2d296 ILT |
5678 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5679 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5680 | used_at && mips_opts.noat), |
f59fb6ca | 5681 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5682 | (char *) NULL); |
777ad64d ILT |
5683 | |
5684 | /* We just generated two relocs. When tc_gen_reloc | |
5685 | handles this case, it will skip the first reloc and | |
5686 | handle the second. The second reloc already has an | |
5687 | extra addend of 4, which we added above. We must | |
5688 | subtract it out, and then subtract another 4 to make | |
5689 | the first reloc come out right. The second reloc | |
5690 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5691 | offset_expr when we build its instruction below. |
5692 | ||
5693 | If we have a symbol, then we don't want to include | |
5694 | the offset, because it will wind up being included | |
5695 | when we generate the reloc. */ | |
5696 | ||
5697 | if (offset_expr.X_op == O_constant) | |
5698 | offset_expr.X_add_number -= 8; | |
5699 | else | |
5700 | { | |
5701 | offset_expr.X_add_number = -4; | |
5702 | offset_expr.X_op = O_constant; | |
5703 | } | |
0dd2d296 ILT |
5704 | } |
5705 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5706 | if (p != NULL) | |
5707 | p += 4; | |
5708 | if (breg != 0) | |
5709 | { | |
5710 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5711 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5712 | || mips_opts.isa < 3) | |
5713 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5714 | "d,v,t", AT, breg, AT); |
5715 | if (p != NULL) | |
5716 | p += 4; | |
5717 | } | |
efec4a28 | 5718 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5719 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5720 | coproc ? treg + 1 : treg, | |
5721 | (int) BFD_RELOC_LO16, AT); | |
5722 | if (p != NULL) | |
5723 | p += 4; | |
5724 | /* FIXME: How do we handle overflow here? */ | |
5725 | offset_expr.X_add_number += 4; | |
efec4a28 | 5726 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5727 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5728 | coproc ? treg : treg + 1, | |
5729 | (int) BFD_RELOC_LO16, AT); | |
5730 | } | |
fb251650 | 5731 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5732 | { |
0dd2d296 ILT |
5733 | int off; |
5734 | ||
5735 | /* If this is a reference to an external symbol, we want | |
5736 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5737 | nop | |
5738 | <op> $treg,0($at) | |
5739 | <op> $treg+1,4($at) | |
5740 | Otherwise we want | |
5741 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5742 | nop | |
5743 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5744 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5745 | If there is a base register we add it to $at before the | |
5746 | lwc1 instructions. If there is a constant we include it | |
5747 | in the lwc1 instructions. */ | |
5748 | used_at = 1; | |
5749 | expr1.X_add_number = offset_expr.X_add_number; | |
5750 | offset_expr.X_add_number = 0; | |
5751 | if (expr1.X_add_number < -0x8000 | |
5752 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5753 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 ILT |
5754 | if (breg == 0) |
5755 | off = 0; | |
5756 | else | |
5757 | off = 4; | |
8ea7f4e8 | 5758 | frag_grow (24 + off); |
0dd2d296 | 5759 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5760 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5761 | || mips_opts.isa < 3) | |
5762 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5763 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5765 | if (breg != 0) |
0dd2d296 | 5766 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5767 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5768 | || mips_opts.isa < 3) | |
5769 | ? "addu" : "daddu"), | |
0dd2d296 | 5770 | "d,v,t", AT, breg, AT); |
efec4a28 | 5771 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5772 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5773 | coproc ? treg + 1 : treg, | |
5774 | (int) BFD_RELOC_LO16, AT); | |
5775 | expr1.X_add_number += 4; | |
55933a58 ILT |
5776 | |
5777 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5778 | nop. */ | |
5779 | hold_mips_optimize = mips_optimize; | |
5780 | mips_optimize = 2; | |
efec4a28 | 5781 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5782 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5783 | coproc ? treg : treg + 1, | |
5784 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5785 | mips_optimize = hold_mips_optimize; |
5786 | ||
0dd2d296 ILT |
5787 | (void) frag_var (rs_machine_dependent, 0, 0, |
5788 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5789 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5790 | (char *) NULL); |
8358c818 | 5791 | } |
fb251650 ILT |
5792 | else if (mips_pic == SVR4_PIC) |
5793 | { | |
5794 | int gpdel, off; | |
5795 | ||
5796 | /* If this is a reference to an external symbol, we want | |
5797 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5798 | addu $at,$at,$gp | |
5799 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5800 | nop | |
5801 | <op> $treg,0($at) | |
5802 | <op> $treg+1,4($at) | |
5803 | Otherwise we want | |
5804 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5805 | nop | |
5806 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5807 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5808 | If there is a base register we add it to $at before the | |
5809 | lwc1 instructions. If there is a constant we include it | |
5810 | in the lwc1 instructions. */ | |
5811 | used_at = 1; | |
5812 | expr1.X_add_number = offset_expr.X_add_number; | |
5813 | offset_expr.X_add_number = 0; | |
5814 | if (expr1.X_add_number < -0x8000 | |
5815 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5816 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5817 | if (reg_needs_delay (GP)) |
5818 | gpdel = 4; | |
5819 | else | |
5820 | gpdel = 0; | |
5821 | if (breg == 0) | |
5822 | off = 0; | |
5823 | else | |
5824 | off = 4; | |
5825 | frag_grow (56); | |
5826 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5827 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5828 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5829 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5830 | || mips_opts.isa < 3) | |
5831 | ? "addu" : "daddu"), | |
fb251650 ILT |
5832 | "d,v,t", AT, AT, GP); |
5833 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5834 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5835 | || mips_opts.isa < 3) | |
5836 | ? "lw" : "ld"), | |
fb251650 ILT |
5837 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5838 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5839 | if (breg != 0) | |
5840 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5841 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5842 | || mips_opts.isa < 3) | |
5843 | ? "addu" : "daddu"), | |
fb251650 | 5844 | "d,v,t", AT, breg, AT); |
efec4a28 | 5845 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5846 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5847 | coproc ? treg + 1 : treg, | |
5848 | (int) BFD_RELOC_LO16, AT); | |
5849 | expr1.X_add_number += 4; | |
5850 | ||
5851 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5852 | nop. */ | |
5853 | hold_mips_optimize = mips_optimize; | |
5854 | mips_optimize = 2; | |
efec4a28 | 5855 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5856 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5857 | coproc ? treg : treg + 1, | |
5858 | (int) BFD_RELOC_LO16, AT); | |
5859 | mips_optimize = hold_mips_optimize; | |
5860 | expr1.X_add_number -= 4; | |
5861 | ||
5862 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5863 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5864 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5865 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5866 | (char *) NULL); |
5867 | if (gpdel > 0) | |
5868 | { | |
5869 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5870 | p += 4; | |
5871 | } | |
5872 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5873 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5874 | || mips_opts.isa < 3) | |
5875 | ? "lw" : "ld"), | |
fb251650 ILT |
5876 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5877 | p += 4; | |
5878 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5879 | p += 4; | |
5880 | if (breg != 0) | |
5881 | { | |
5882 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5883 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5884 | || mips_opts.isa < 3) | |
5885 | ? "addu" : "daddu"), | |
fb251650 ILT |
5886 | "d,v,t", AT, breg, AT); |
5887 | p += 4; | |
5888 | } | |
efec4a28 | 5889 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5890 | macro_build (p, &icnt, &expr1, s, fmt, |
5891 | coproc ? treg + 1 : treg, | |
5892 | (int) BFD_RELOC_LO16, AT); | |
5893 | p += 4; | |
5894 | expr1.X_add_number += 4; | |
5895 | ||
5896 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5897 | nop. */ | |
5898 | hold_mips_optimize = mips_optimize; | |
5899 | mips_optimize = 2; | |
efec4a28 | 5900 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5901 | macro_build (p, &icnt, &expr1, s, fmt, |
5902 | coproc ? treg : treg + 1, | |
5903 | (int) BFD_RELOC_LO16, AT); | |
5904 | mips_optimize = hold_mips_optimize; | |
5905 | } | |
d9aba805 ILT |
5906 | else if (mips_pic == EMBEDDED_PIC) |
5907 | { | |
5908 | /* If there is no base register, we use | |
5909 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5910 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5911 | If we have a base register, we use | |
5912 | addu $at,$breg,$gp | |
5913 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5914 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5915 | */ | |
5916 | if (breg == 0) | |
5917 | { | |
5918 | tempreg = GP; | |
5919 | used_at = 0; | |
5920 | } | |
5921 | else | |
5922 | { | |
5923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5924 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5925 | || mips_opts.isa < 3) | |
5926 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5927 | "d,v,t", AT, breg, GP); |
5928 | tempreg = AT; | |
5929 | used_at = 1; | |
5930 | } | |
5931 | ||
efec4a28 | 5932 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5933 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5934 | coproc ? treg + 1 : treg, | |
5935 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5936 | offset_expr.X_add_number += 4; | |
efec4a28 | 5937 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5938 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5939 | coproc ? treg : treg + 1, | |
5940 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5941 | } | |
5942 | else | |
5943 | abort (); | |
0dd2d296 ILT |
5944 | |
5945 | if (! used_at) | |
5946 | return; | |
5947 | ||
5948 | break; | |
5949 | ||
5950 | case M_LD_OB: | |
5951 | s = "lw"; | |
5952 | goto sd_ob; | |
5953 | case M_SD_OB: | |
5954 | s = "sw"; | |
5955 | sd_ob: | |
9a1f3160 | 5956 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5957 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5958 | (int) BFD_RELOC_LO16, breg); | |
5959 | offset_expr.X_add_number += 4; | |
5960 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5961 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5962 | return; |
efec4a28 DP |
5963 | |
5964 | /* New code added to support COPZ instructions. | |
5965 | This code builds table entries out of the macros in mip_opcodes. | |
5966 | R4000 uses interlocks to handle coproc delays. | |
5967 | Other chips (like the R3000) require nops to be inserted for delays. | |
5968 | ||
5969 | FIXME: Currently, we require that the user handle delays. | |
5970 | In order to fill delay slots for non-interlocked chips, | |
5971 | we must have a way to specify delays based on the coprocessor. | |
5972 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5973 | What are the side-effects of the cop instruction? | |
5974 | What cache support might we have and what are its effects? | |
5975 | Both coprocessor & memory require delays. how long??? | |
5976 | What registers are read/set/modified? | |
5977 | ||
5978 | If an itbl is provided to interpret cop instructions, | |
5979 | this knowledge can be encoded in the itbl spec. */ | |
5980 | ||
5981 | case M_COP0: | |
65d2c7d3 | 5982 | s = "c0"; |
efec4a28 DP |
5983 | goto copz; |
5984 | case M_COP1: | |
65d2c7d3 | 5985 | s = "c1"; |
efec4a28 DP |
5986 | goto copz; |
5987 | case M_COP2: | |
65d2c7d3 | 5988 | s = "c2"; |
efec4a28 DP |
5989 | goto copz; |
5990 | case M_COP3: | |
65d2c7d3 | 5991 | s = "c3"; |
efec4a28 | 5992 | copz: |
65d2c7d3 JL |
5993 | /* For now we just do C (same as Cz). The parameter will be |
5994 | stored in insn_opcode by mips_ip. */ | |
5995 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5996 | ip->insn_opcode); | |
efec4a28 DP |
5997 | return; |
5998 | ||
917fae09 SS |
5999 | #ifdef LOSING_COMPILER |
6000 | default: | |
efec4a28 DP |
6001 | /* Try and see if this is a new itbl instruction. |
6002 | This code builds table entries out of the macros in mip_opcodes. | |
6003 | FIXME: For now we just assemble the expression and pass it's | |
6004 | value along as a 32-bit immediate. | |
6005 | We may want to have the assembler assemble this value, | |
6006 | so that we gain the assembler's knowledge of delay slots, | |
6007 | symbols, etc. | |
6008 | Would it be more efficient to use mask (id) here? */ | |
6009 | if (itbl_have_entries | |
9218cee0 | 6010 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
6011 | { |
6012 | s = ip->insn_mo->name; | |
6013 | s2 = "cop3"; | |
9218cee0 | 6014 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
6015 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
6016 | return; | |
6017 | } | |
917fae09 SS |
6018 | macro2 (ip); |
6019 | return; | |
6020 | } | |
3c83da8a | 6021 | if (mips_opts.noat) |
48401fcf | 6022 | as_warn (_("Macro used $at after \".set noat\"")); |
917fae09 SS |
6023 | } |
6024 | ||
6025 | static void | |
6026 | macro2 (ip) | |
6027 | struct mips_cl_insn *ip; | |
6028 | { | |
6029 | register int treg, sreg, dreg, breg; | |
6030 | int tempreg; | |
6031 | int mask; | |
6032 | int icnt = 0; | |
6033 | int used_at; | |
6034 | expressionS expr1; | |
6035 | const char *s; | |
6036 | const char *s2; | |
6037 | const char *fmt; | |
6038 | int likely = 0; | |
6039 | int dbl = 0; | |
6040 | int coproc = 0; | |
adcf2b9d | 6041 | int lr = 0; |
40f0c904 | 6042 | int imm = 0; |
adcf2b9d | 6043 | int off; |
917fae09 SS |
6044 | offsetT maxnum; |
6045 | bfd_reloc_code_real_type r; | |
6046 | char *p; | |
6047 | ||
6048 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
6049 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6050 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6051 | mask = ip->insn_mo->mask; | |
6052 | ||
6053 | expr1.X_op = O_constant; | |
6054 | expr1.X_op_symbol = NULL; | |
6055 | expr1.X_add_symbol = NULL; | |
6056 | expr1.X_add_number = 1; | |
6057 | ||
6058 | switch (mask) | |
6059 | { | |
6060 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 6061 | |
8358c818 ILT |
6062 | case M_DMUL: |
6063 | dbl = 1; | |
3d3c5039 | 6064 | case M_MUL: |
0dd2d296 | 6065 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6066 | dbl ? "dmultu" : "multu", |
6067 | "s,t", sreg, treg); | |
0dd2d296 | 6068 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6069 | return; |
3d3c5039 | 6070 | |
8358c818 ILT |
6071 | case M_DMUL_I: |
6072 | dbl = 1; | |
3d3c5039 | 6073 | case M_MUL_I: |
8358c818 ILT |
6074 | /* The MIPS assembler some times generates shifts and adds. I'm |
6075 | not trying to be that fancy. GCC should do this for us | |
6076 | anyway. */ | |
d8a1c247 | 6077 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6078 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6079 | dbl ? "dmult" : "mult", |
6080 | "s,t", sreg, AT); | |
0dd2d296 | 6081 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6082 | break; |
3d3c5039 | 6083 | |
40f0c904 FCE |
6084 | case M_DMULO_I: |
6085 | dbl = 1; | |
6086 | case M_MULO_I: | |
6087 | imm = 1; | |
6088 | goto do_mulo; | |
6089 | ||
8358c818 ILT |
6090 | case M_DMULO: |
6091 | dbl = 1; | |
6092 | case M_MULO: | |
40f0c904 | 6093 | do_mulo: |
fbcfacb7 | 6094 | mips_emit_delays (true); |
3c83da8a | 6095 | ++mips_opts.noreorder; |
0dd2d296 | 6096 | mips_any_noreorder = 1; |
40f0c904 FCE |
6097 | if (imm) |
6098 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6099 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6100 | dbl ? "dmult" : "mult", |
40f0c904 | 6101 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6102 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6103 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
6104 | dbl ? "dsra32" : "sra", |
6105 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 6106 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
6107 | if (mips_trap) |
6108 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6109 | else | |
6110 | { | |
6111 | expr1.X_add_number = 8; | |
6112 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6113 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6114 | /* start-sanitize-r5900 */ |
6115 | if (mips_5900) | |
6116 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6117 | else | |
6118 | /* end-sanitize-r5900 */ | |
6119 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6120 | } |
3c83da8a | 6121 | --mips_opts.noreorder; |
0dd2d296 | 6122 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
6123 | break; |
6124 | ||
40f0c904 FCE |
6125 | case M_DMULOU_I: |
6126 | dbl = 1; | |
6127 | case M_MULOU_I: | |
6128 | imm = 1; | |
6129 | goto do_mulou; | |
6130 | ||
8358c818 ILT |
6131 | case M_DMULOU: |
6132 | dbl = 1; | |
6133 | case M_MULOU: | |
40f0c904 | 6134 | do_mulou: |
fbcfacb7 | 6135 | mips_emit_delays (true); |
3c83da8a | 6136 | ++mips_opts.noreorder; |
0dd2d296 | 6137 | mips_any_noreorder = 1; |
40f0c904 FCE |
6138 | if (imm) |
6139 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6140 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6141 | dbl ? "dmultu" : "multu", |
40f0c904 | 6142 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6143 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
6144 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
6145 | if (mips_trap) |
6146 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6147 | else | |
6148 | { | |
6149 | expr1.X_add_number = 8; | |
6150 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6151 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6152 | /* start-sanitize-r5900 */ |
6153 | if (mips_5900) | |
6154 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6155 | else | |
6156 | /* end-sanitize-r5900 */ | |
6157 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6158 | } |
3c83da8a | 6159 | --mips_opts.noreorder; |
8358c818 ILT |
6160 | break; |
6161 | ||
3d3c5039 | 6162 | case M_ROL: |
0dd2d296 ILT |
6163 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6164 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6165 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6166 | treg); | |
6167 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6168 | break; |
3d3c5039 ILT |
6169 | |
6170 | case M_ROL_I: | |
5c6f5923 | 6171 | if (imm_expr.X_op != O_constant) |
48401fcf | 6172 | as_bad (_("rotate count too large")); |
0dd2d296 | 6173 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6174 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6175 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6176 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6177 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6178 | break; |
3d3c5039 ILT |
6179 | |
6180 | case M_ROR: | |
0dd2d296 ILT |
6181 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6182 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6183 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6184 | treg); | |
6185 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6186 | break; |
3d3c5039 ILT |
6187 | |
6188 | case M_ROR_I: | |
5c6f5923 | 6189 | if (imm_expr.X_op != O_constant) |
48401fcf | 6190 | as_bad (_("rotate count too large")); |
0dd2d296 | 6191 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6192 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6193 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6194 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6195 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6196 | break; |
3d3c5039 ILT |
6197 | |
6198 | case M_S_DOB: | |
1c6f3441 ILT |
6199 | if (mips_4650) |
6200 | { | |
48401fcf | 6201 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
6202 | return; |
6203 | } | |
3c83da8a | 6204 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6205 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6206 | to adjust when storing to memory. */ | |
0dd2d296 | 6207 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6208 | target_big_endian ? treg + 1 : treg, |
9226253a | 6209 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6210 | offset_expr.X_add_number += 4; |
0dd2d296 | 6211 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6212 | target_big_endian ? treg : treg + 1, |
9226253a | 6213 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6214 | return; |
3d3c5039 | 6215 | |
3d3c5039 | 6216 | case M_SEQ: |
670a50eb | 6217 | if (sreg == 0) |
0dd2d296 ILT |
6218 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6219 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6220 | else if (treg == 0) |
0dd2d296 ILT |
6221 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6222 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6223 | else |
6224 | { | |
0dd2d296 ILT |
6225 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6226 | sreg, treg); | |
6227 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6228 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6229 | } |
670a50eb | 6230 | return; |
3d3c5039 ILT |
6231 | |
6232 | case M_SEQ_I: | |
5c6f5923 | 6233 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6234 | { |
0dd2d296 ILT |
6235 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6236 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6237 | return; |
3d3c5039 | 6238 | } |
670a50eb ILT |
6239 | if (sreg == 0) |
6240 | { | |
48401fcf | 6241 | as_warn (_("Instruction %s: result is always false"), |
6e8dda9c | 6242 | ip->insn_mo->name); |
0dd2d296 | 6243 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6244 | return; |
3d3c5039 | 6245 | } |
5c6f5923 GRK |
6246 | if (imm_expr.X_op == O_constant |
6247 | && imm_expr.X_add_number >= 0 | |
6248 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6249 | { |
0dd2d296 ILT |
6250 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6251 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6252 | used_at = 0; |
6e8dda9c | 6253 | } |
5c6f5923 GRK |
6254 | else if (imm_expr.X_op == O_constant |
6255 | && imm_expr.X_add_number > -0x8000 | |
6256 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6257 | { |
6258 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6259 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6260 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6261 | || mips_opts.isa < 3) | |
6262 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6263 | "t,r,j", dreg, sreg, |
6264 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6265 | used_at = 0; |
6266 | } | |
6267 | else | |
6268 | { | |
d8a1c247 | 6269 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6270 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6271 | sreg, AT); | |
670a50eb ILT |
6272 | used_at = 1; |
6273 | } | |
0dd2d296 | 6274 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6275 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6276 | if (used_at) |
6277 | break; | |
6278 | return; | |
3d3c5039 ILT |
6279 | |
6280 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6281 | s = "slt"; |
6282 | goto sge; | |
3d3c5039 | 6283 | case M_SGEU: |
670a50eb | 6284 | s = "sltu"; |
3d3c5039 | 6285 | sge: |
0dd2d296 ILT |
6286 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6287 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6288 | (int) BFD_RELOC_LO16); |
670a50eb | 6289 | return; |
3d3c5039 | 6290 | |
670a50eb | 6291 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6292 | case M_SGEU_I: |
5c6f5923 GRK |
6293 | if (imm_expr.X_op == O_constant |
6294 | && imm_expr.X_add_number >= -0x8000 | |
6295 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6296 | { |
6b34ac5a | 6297 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 6298 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6299 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6300 | used_at = 0; |
6301 | } | |
6302 | else | |
6303 | { | |
d8a1c247 | 6304 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6305 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6306 | mask == M_SGE_I ? "slt" : "sltu", |
6307 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6308 | used_at = 1; |
6309 | } | |
0dd2d296 | 6310 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6311 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6312 | if (used_at) |
6313 | break; | |
6314 | return; | |
3d3c5039 ILT |
6315 | |
6316 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6317 | s = "slt"; |
6318 | goto sgt; | |
3d3c5039 | 6319 | case M_SGTU: |
670a50eb | 6320 | s = "sltu"; |
3d3c5039 | 6321 | sgt: |
0dd2d296 | 6322 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6323 | return; |
3d3c5039 | 6324 | |
670a50eb ILT |
6325 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6326 | s = "slt"; | |
6327 | goto sgti; | |
3d3c5039 | 6328 | case M_SGTU_I: |
670a50eb | 6329 | s = "sltu"; |
3d3c5039 | 6330 | sgti: |
d8a1c247 | 6331 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6332 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6333 | break; |
3d3c5039 | 6334 | |
670a50eb ILT |
6335 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6336 | s = "slt"; | |
6337 | goto sle; | |
3d3c5039 | 6338 | case M_SLEU: |
670a50eb | 6339 | s = "sltu"; |
3d3c5039 | 6340 | sle: |
0dd2d296 ILT |
6341 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6342 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6343 | (int) BFD_RELOC_LO16); |
670a50eb | 6344 | return; |
3d3c5039 | 6345 | |
670a50eb ILT |
6346 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6347 | s = "slt"; | |
6348 | goto slei; | |
3d3c5039 | 6349 | case M_SLEU_I: |
670a50eb | 6350 | s = "sltu"; |
3d3c5039 | 6351 | slei: |
d8a1c247 | 6352 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6353 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6354 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6355 | (int) BFD_RELOC_LO16); |
670a50eb | 6356 | break; |
3d3c5039 ILT |
6357 | |
6358 | case M_SLT_I: | |
5c6f5923 GRK |
6359 | if (imm_expr.X_op == O_constant |
6360 | && imm_expr.X_add_number >= -0x8000 | |
6361 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6362 | { |
0dd2d296 ILT |
6363 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6364 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6365 | return; |
3d3c5039 | 6366 | } |
d8a1c247 | 6367 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6368 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6369 | break; |
3d3c5039 ILT |
6370 | |
6371 | case M_SLTU_I: | |
5c6f5923 GRK |
6372 | if (imm_expr.X_op == O_constant |
6373 | && imm_expr.X_add_number >= -0x8000 | |
6374 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6375 | { |
0dd2d296 ILT |
6376 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6377 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6378 | return; |
3d3c5039 | 6379 | } |
d8a1c247 | 6380 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6381 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6382 | AT); | |
670a50eb | 6383 | break; |
3d3c5039 ILT |
6384 | |
6385 | case M_SNE: | |
670a50eb | 6386 | if (sreg == 0) |
0dd2d296 ILT |
6387 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6388 | treg); | |
670a50eb | 6389 | else if (treg == 0) |
0dd2d296 ILT |
6390 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6391 | sreg); | |
670a50eb ILT |
6392 | else |
6393 | { | |
0dd2d296 ILT |
6394 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6395 | sreg, treg); | |
6396 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6397 | dreg); | |
3d3c5039 | 6398 | } |
670a50eb | 6399 | return; |
3d3c5039 ILT |
6400 | |
6401 | case M_SNE_I: | |
5c6f5923 | 6402 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6403 | { |
0dd2d296 ILT |
6404 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6405 | sreg); | |
670a50eb | 6406 | return; |
3d3c5039 | 6407 | } |
670a50eb ILT |
6408 | if (sreg == 0) |
6409 | { | |
48401fcf | 6410 | as_warn (_("Instruction %s: result is always true"), |
6e8dda9c | 6411 | ip->insn_mo->name); |
0dd2d296 | 6412 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6413 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6414 | || mips_opts.isa < 3) | |
6415 | ? "addiu" : "daddiu"), | |
9226253a | 6416 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6417 | return; |
3d3c5039 | 6418 | } |
5c6f5923 GRK |
6419 | if (imm_expr.X_op == O_constant |
6420 | && imm_expr.X_add_number >= 0 | |
6421 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6422 | { |
0dd2d296 ILT |
6423 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6424 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6425 | used_at = 0; |
6e8dda9c | 6426 | } |
5c6f5923 GRK |
6427 | else if (imm_expr.X_op == O_constant |
6428 | && imm_expr.X_add_number > -0x8000 | |
6429 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6430 | { |
6431 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6432 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6433 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6434 | || mips_opts.isa < 3) | |
6435 | ? "addiu" : "daddiu"), | |
9226253a | 6436 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6437 | used_at = 0; |
6438 | } | |
6439 | else | |
6440 | { | |
d8a1c247 | 6441 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6442 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6443 | sreg, AT); | |
670a50eb ILT |
6444 | used_at = 1; |
6445 | } | |
0dd2d296 | 6446 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6447 | if (used_at) |
6448 | break; | |
6449 | return; | |
3d3c5039 | 6450 | |
8358c818 ILT |
6451 | case M_DSUB_I: |
6452 | dbl = 1; | |
3d3c5039 | 6453 | case M_SUB_I: |
5c6f5923 GRK |
6454 | if (imm_expr.X_op == O_constant |
6455 | && imm_expr.X_add_number > -0x8000 | |
6456 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6457 | { |
6458 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6459 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6460 | dbl ? "daddi" : "addi", |
9226253a | 6461 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6462 | return; |
3d3c5039 | 6463 | } |
d8a1c247 | 6464 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6465 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6466 | dbl ? "dsub" : "sub", |
6467 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6468 | break; |
3d3c5039 | 6469 | |
8358c818 ILT |
6470 | case M_DSUBU_I: |
6471 | dbl = 1; | |
3d3c5039 | 6472 | case M_SUBU_I: |
5c6f5923 GRK |
6473 | if (imm_expr.X_op == O_constant |
6474 | && imm_expr.X_add_number > -0x8000 | |
6475 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6476 | { |
6477 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6478 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6479 | dbl ? "daddiu" : "addiu", |
9226253a | 6480 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6481 | return; |
3d3c5039 | 6482 | } |
d8a1c247 | 6483 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6484 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6485 | dbl ? "dsubu" : "subu", |
6486 | "d,v,t", dreg, sreg, AT); | |
6487 | break; | |
6488 | ||
6489 | case M_TEQ_I: | |
6490 | s = "teq"; | |
6491 | goto trap; | |
6492 | case M_TGE_I: | |
6493 | s = "tge"; | |
6494 | goto trap; | |
6495 | case M_TGEU_I: | |
6496 | s = "tgeu"; | |
6497 | goto trap; | |
6498 | case M_TLT_I: | |
6499 | s = "tlt"; | |
6500 | goto trap; | |
6501 | case M_TLTU_I: | |
6502 | s = "tltu"; | |
6503 | goto trap; | |
6504 | case M_TNE_I: | |
6505 | s = "tne"; | |
6506 | trap: | |
d8a1c247 | 6507 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6508 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6509 | break; |
3d3c5039 ILT |
6510 | |
6511 | case M_TRUNCWD: | |
6512 | case M_TRUNCWS: | |
3c83da8a | 6513 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6514 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6515 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6516 | ||
6517 | /* | |
6518 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6519 | * or is there a reason for it? | |
6520 | */ | |
fbcfacb7 | 6521 | mips_emit_delays (true); |
3c83da8a | 6522 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6523 | mips_any_noreorder = 1; |
6524 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6525 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6526 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6527 | expr1.X_add_number = 3; |
0dd2d296 | 6528 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6529 | (int) BFD_RELOC_LO16); |
670a50eb | 6530 | expr1.X_add_number = 2; |
0dd2d296 | 6531 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6532 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6533 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6534 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6535 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6536 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6537 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6538 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6539 | --mips_opts.noreorder; |
670a50eb | 6540 | break; |
3d3c5039 ILT |
6541 | |
6542 | case M_ULH: | |
670a50eb ILT |
6543 | s = "lb"; |
6544 | goto ulh; | |
3d3c5039 | 6545 | case M_ULHU: |
670a50eb | 6546 | s = "lbu"; |
3d3c5039 | 6547 | ulh: |
8ea7f4e8 | 6548 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6549 | as_bad (_("operand overflow")); |
670a50eb | 6550 | /* avoid load delay */ |
b9129c6f | 6551 | if (! target_big_endian) |
8ea7f4e8 | 6552 | offset_expr.X_add_number += 1; |
0dd2d296 | 6553 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6554 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6555 | if (! target_big_endian) |
8ea7f4e8 ILT |
6556 | offset_expr.X_add_number -= 1; |
6557 | else | |
6558 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6559 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6560 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6561 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6562 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6563 | break; |
3d3c5039 | 6564 | |
adcf2b9d ILT |
6565 | case M_ULD: |
6566 | s = "ldl"; | |
6567 | s2 = "ldr"; | |
6568 | off = 7; | |
6569 | goto ulw; | |
3d3c5039 | 6570 | case M_ULW: |
adcf2b9d ILT |
6571 | s = "lwl"; |
6572 | s2 = "lwr"; | |
6573 | off = 3; | |
6574 | ulw: | |
6575 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6576 | as_bad (_("operand overflow")); |
b9129c6f | 6577 | if (! target_big_endian) |
adcf2b9d ILT |
6578 | offset_expr.X_add_number += off; |
6579 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6580 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6581 | if (! target_big_endian) |
adcf2b9d | 6582 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6583 | else |
adcf2b9d ILT |
6584 | offset_expr.X_add_number += off; |
6585 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6586 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6587 | return; |
3d3c5039 | 6588 | |
adcf2b9d ILT |
6589 | case M_ULD_A: |
6590 | s = "ldl"; | |
6591 | s2 = "ldr"; | |
6592 | off = 7; | |
6593 | goto ulwa; | |
6594 | case M_ULW_A: | |
6595 | s = "lwl"; | |
6596 | s2 = "lwr"; | |
6597 | off = 3; | |
6598 | ulwa: | |
6599 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6600 | if (breg != 0) |
6601 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6602 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6603 | || mips_opts.isa < 3) | |
6604 | ? "addu" : "daddu"), | |
c625fc23 | 6605 | "d,v,t", AT, AT, breg); |
b9129c6f | 6606 | if (! target_big_endian) |
adcf2b9d ILT |
6607 | expr1.X_add_number = off; |
6608 | else | |
6609 | expr1.X_add_number = 0; | |
6610 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6611 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6612 | if (! target_big_endian) |
adcf2b9d ILT |
6613 | expr1.X_add_number = 0; |
6614 | else | |
6615 | expr1.X_add_number = off; | |
6616 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6617 | (int) BFD_RELOC_LO16, AT); | |
6618 | break; | |
6619 | ||
3d3c5039 ILT |
6620 | case M_ULH_A: |
6621 | case M_ULHU_A: | |
0dd2d296 | 6622 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6623 | if (breg != 0) |
6624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6625 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6626 | || mips_opts.isa < 3) | |
6627 | ? "addu" : "daddu"), | |
c625fc23 | 6628 | "d,v,t", AT, AT, breg); |
b9129c6f | 6629 | if (target_big_endian) |
adcf2b9d ILT |
6630 | expr1.X_add_number = 0; |
6631 | macro_build ((char *) NULL, &icnt, &expr1, | |
6632 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6633 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6634 | if (target_big_endian) |
adcf2b9d | 6635 | expr1.X_add_number = 1; |
670a50eb | 6636 | else |
adcf2b9d ILT |
6637 | expr1.X_add_number = 0; |
6638 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6639 | (int) BFD_RELOC_LO16, AT); | |
6640 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6641 | treg, 8); | |
6642 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6643 | treg, AT); | |
670a50eb | 6644 | break; |
3d3c5039 ILT |
6645 | |
6646 | case M_USH: | |
8ea7f4e8 | 6647 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6648 | as_bad (_("operand overflow")); |
b9129c6f | 6649 | if (target_big_endian) |
8ea7f4e8 | 6650 | offset_expr.X_add_number += 1; |
0dd2d296 | 6651 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6652 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6653 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6654 | if (target_big_endian) |
8ea7f4e8 ILT |
6655 | offset_expr.X_add_number -= 1; |
6656 | else | |
6657 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6658 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6659 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6660 | break; |
3d3c5039 | 6661 | |
adcf2b9d ILT |
6662 | case M_USD: |
6663 | s = "sdl"; | |
6664 | s2 = "sdr"; | |
6665 | off = 7; | |
6666 | goto usw; | |
3d3c5039 | 6667 | case M_USW: |
adcf2b9d ILT |
6668 | s = "swl"; |
6669 | s2 = "swr"; | |
6670 | off = 3; | |
6671 | usw: | |
6672 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6673 | as_bad (_("operand overflow")); |
b9129c6f | 6674 | if (! target_big_endian) |
adcf2b9d ILT |
6675 | offset_expr.X_add_number += off; |
6676 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6677 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6678 | if (! target_big_endian) |
adcf2b9d | 6679 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6680 | else |
adcf2b9d ILT |
6681 | offset_expr.X_add_number += off; |
6682 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6683 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6684 | return; |
3d3c5039 | 6685 | |
adcf2b9d ILT |
6686 | case M_USD_A: |
6687 | s = "sdl"; | |
6688 | s2 = "sdr"; | |
6689 | off = 7; | |
6690 | goto uswa; | |
3d3c5039 | 6691 | case M_USW_A: |
adcf2b9d ILT |
6692 | s = "swl"; |
6693 | s2 = "swr"; | |
6694 | off = 3; | |
6695 | uswa: | |
0dd2d296 | 6696 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6697 | if (breg != 0) |
6698 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6699 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6700 | || mips_opts.isa < 3) | |
6701 | ? "addu" : "daddu"), | |
c625fc23 | 6702 | "d,v,t", AT, AT, breg); |
b9129c6f | 6703 | if (! target_big_endian) |
adcf2b9d | 6704 | expr1.X_add_number = off; |
670a50eb | 6705 | else |
adcf2b9d ILT |
6706 | expr1.X_add_number = 0; |
6707 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6708 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6709 | if (! target_big_endian) |
adcf2b9d ILT |
6710 | expr1.X_add_number = 0; |
6711 | else | |
6712 | expr1.X_add_number = off; | |
6713 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6714 | (int) BFD_RELOC_LO16, AT); | |
6715 | break; | |
6716 | ||
6717 | case M_USH_A: | |
6718 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6719 | if (breg != 0) |
6720 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6721 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6722 | || mips_opts.isa < 3) | |
6723 | ? "addu" : "daddu"), | |
c625fc23 | 6724 | "d,v,t", AT, AT, breg); |
b9129c6f | 6725 | if (! target_big_endian) |
adcf2b9d ILT |
6726 | expr1.X_add_number = 0; |
6727 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6728 | (int) BFD_RELOC_LO16, AT); | |
6729 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6730 | treg, 8); | |
b9129c6f | 6731 | if (! target_big_endian) |
adcf2b9d ILT |
6732 | expr1.X_add_number = 1; |
6733 | else | |
6734 | expr1.X_add_number = 0; | |
6735 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6736 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6737 | if (! target_big_endian) |
adcf2b9d ILT |
6738 | expr1.X_add_number = 0; |
6739 | else | |
6740 | expr1.X_add_number = 1; | |
6741 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6742 | (int) BFD_RELOC_LO16, AT); | |
6743 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6744 | treg, 8); | |
6745 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6746 | treg, AT); | |
670a50eb | 6747 | break; |
3d3c5039 ILT |
6748 | |
6749 | default: | |
9218cee0 ILT |
6750 | /* FIXME: Check if this is one of the itbl macros, since they |
6751 | are added dynamically. */ | |
48401fcf | 6752 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8358c818 | 6753 | break; |
3d3c5039 | 6754 | } |
3c83da8a | 6755 | if (mips_opts.noat) |
48401fcf | 6756 | as_warn (_("Macro used $at after \".set noat\"")); |
3d3c5039 ILT |
6757 | } |
6758 | ||
cc5703cd | 6759 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6760 | |
3d3c5039 | 6761 | static void |
cc5703cd | 6762 | mips16_macro (ip) |
3d3c5039 ILT |
6763 | struct mips_cl_insn *ip; |
6764 | { | |
cc5703cd ILT |
6765 | int mask; |
6766 | int xreg, yreg, zreg, tmp; | |
6767 | int icnt; | |
6768 | expressionS expr1; | |
6769 | int dbl; | |
6770 | const char *s, *s2, *s3; | |
3d3c5039 | 6771 | |
cc5703cd | 6772 | mask = ip->insn_mo->mask; |
3d3c5039 | 6773 | |
cc5703cd ILT |
6774 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6775 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6776 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6777 | |
cc5703cd | 6778 | icnt = 0; |
8358c818 | 6779 | |
cc5703cd ILT |
6780 | expr1.X_op = O_constant; |
6781 | expr1.X_op_symbol = NULL; | |
6782 | expr1.X_add_symbol = NULL; | |
6783 | expr1.X_add_number = 1; | |
8358c818 | 6784 | |
cc5703cd | 6785 | dbl = 0; |
517078c1 | 6786 | |
cc5703cd ILT |
6787 | switch (mask) |
6788 | { | |
6789 | default: | |
6790 | internalError (); | |
6791 | ||
6792 | case M_DDIV_3: | |
6793 | dbl = 1; | |
6794 | case M_DIV_3: | |
6795 | s = "mflo"; | |
6796 | goto do_div3; | |
6797 | case M_DREM_3: | |
6798 | dbl = 1; | |
6799 | case M_REM_3: | |
6800 | s = "mfhi"; | |
6801 | do_div3: | |
fbcfacb7 | 6802 | mips_emit_delays (true); |
3c83da8a | 6803 | ++mips_opts.noreorder; |
cc5703cd ILT |
6804 | mips_any_noreorder = 1; |
6805 | macro_build ((char *) NULL, &icnt, NULL, | |
6806 | dbl ? "ddiv" : "div", | |
6807 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6808 | expr1.X_add_number = 2; |
cc5703cd | 6809 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6810 | /* start-sanitize-r5900 */ |
6811 | if (mips_5900) | |
6812 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6813 | else | |
6814 | /* end-sanitize-r5900 */ | |
6815 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6816 | ||
cc5703cd ILT |
6817 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6818 | since that causes an overflow. We should do that as well, | |
6819 | but I don't see how to do the comparisons without a temporary | |
6820 | register. */ | |
3c83da8a | 6821 | --mips_opts.noreorder; |
cc5703cd ILT |
6822 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6823 | break; | |
6824 | ||
6825 | case M_DIVU_3: | |
6826 | s = "divu"; | |
6827 | s2 = "mflo"; | |
6828 | goto do_divu3; | |
6829 | case M_REMU_3: | |
6830 | s = "divu"; | |
6831 | s2 = "mfhi"; | |
6832 | goto do_divu3; | |
6833 | case M_DDIVU_3: | |
6834 | s = "ddivu"; | |
6835 | s2 = "mflo"; | |
6836 | goto do_divu3; | |
6837 | case M_DREMU_3: | |
6838 | s = "ddivu"; | |
6839 | s2 = "mfhi"; | |
6840 | do_divu3: | |
fbcfacb7 | 6841 | mips_emit_delays (true); |
3c83da8a | 6842 | ++mips_opts.noreorder; |
cc5703cd ILT |
6843 | mips_any_noreorder = 1; |
6844 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6845 | expr1.X_add_number = 2; |
cc5703cd | 6846 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6847 | /* start-sanitize-r5900 */ |
6848 | if (mips_5900) | |
6849 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6850 | else | |
6851 | /* end-sanitize-r5900 */ | |
6852 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
3c83da8a | 6853 | --mips_opts.noreorder; |
cc5703cd ILT |
6854 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6855 | break; | |
6856 | ||
08438bef ILT |
6857 | case M_DMUL: |
6858 | dbl = 1; | |
6859 | case M_MUL: | |
6860 | macro_build ((char *) NULL, &icnt, NULL, | |
6861 | dbl ? "dmultu" : "multu", | |
6862 | "x,y", xreg, yreg); | |
6863 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6864 | return; | |
6865 | ||
cc5703cd ILT |
6866 | case M_DSUBU_I: |
6867 | dbl = 1; | |
6868 | goto do_subu; | |
6869 | case M_SUBU_I: | |
6870 | do_subu: | |
5c6f5923 | 6871 | if (imm_expr.X_op != O_constant) |
48401fcf | 6872 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6873 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6874 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6875 | dbl ? "daddiu" : "addiu", | |
6876 | "y,x,4", yreg, xreg); | |
6877 | break; | |
6878 | ||
6879 | case M_SUBU_I_2: | |
5c6f5923 | 6880 | if (imm_expr.X_op != O_constant) |
48401fcf | 6881 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6882 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6883 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6884 | "x,k", xreg); | |
6885 | break; | |
6886 | ||
6887 | case M_DSUBU_I_2: | |
5c6f5923 | 6888 | if (imm_expr.X_op != O_constant) |
48401fcf | 6889 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6890 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6891 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6892 | "y,j", yreg); | |
6893 | break; | |
6894 | ||
6895 | case M_BEQ: | |
6896 | s = "cmp"; | |
6897 | s2 = "bteqz"; | |
6898 | goto do_branch; | |
6899 | case M_BNE: | |
6900 | s = "cmp"; | |
6901 | s2 = "btnez"; | |
6902 | goto do_branch; | |
6903 | case M_BLT: | |
6904 | s = "slt"; | |
6905 | s2 = "btnez"; | |
6906 | goto do_branch; | |
6907 | case M_BLTU: | |
6908 | s = "sltu"; | |
6909 | s2 = "btnez"; | |
6910 | goto do_branch; | |
6911 | case M_BLE: | |
6912 | s = "slt"; | |
6913 | s2 = "bteqz"; | |
6914 | goto do_reverse_branch; | |
6915 | case M_BLEU: | |
6916 | s = "sltu"; | |
6917 | s2 = "bteqz"; | |
6918 | goto do_reverse_branch; | |
6919 | case M_BGE: | |
6920 | s = "slt"; | |
6921 | s2 = "bteqz"; | |
6922 | goto do_branch; | |
6923 | case M_BGEU: | |
6924 | s = "sltu"; | |
6925 | s2 = "bteqz"; | |
6926 | goto do_branch; | |
6927 | case M_BGT: | |
6928 | s = "slt"; | |
6929 | s2 = "btnez"; | |
6930 | goto do_reverse_branch; | |
6931 | case M_BGTU: | |
6932 | s = "sltu"; | |
6933 | s2 = "btnez"; | |
6934 | ||
6935 | do_reverse_branch: | |
6936 | tmp = xreg; | |
6937 | xreg = yreg; | |
6938 | yreg = tmp; | |
6939 | ||
6940 | do_branch: | |
6941 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6942 | xreg, yreg); | |
6943 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6944 | break; | |
6945 | ||
6946 | case M_BEQ_I: | |
6947 | s = "cmpi"; | |
6948 | s2 = "bteqz"; | |
6949 | s3 = "x,U"; | |
6950 | goto do_branch_i; | |
6951 | case M_BNE_I: | |
6952 | s = "cmpi"; | |
6953 | s2 = "btnez"; | |
6954 | s3 = "x,U"; | |
6955 | goto do_branch_i; | |
6956 | case M_BLT_I: | |
6957 | s = "slti"; | |
6958 | s2 = "btnez"; | |
6959 | s3 = "x,8"; | |
6960 | goto do_branch_i; | |
6961 | case M_BLTU_I: | |
6962 | s = "sltiu"; | |
6963 | s2 = "btnez"; | |
6964 | s3 = "x,8"; | |
6965 | goto do_branch_i; | |
6966 | case M_BLE_I: | |
6967 | s = "slti"; | |
6968 | s2 = "btnez"; | |
6969 | s3 = "x,8"; | |
6970 | goto do_addone_branch_i; | |
6971 | case M_BLEU_I: | |
6972 | s = "sltiu"; | |
6973 | s2 = "btnez"; | |
6974 | s3 = "x,8"; | |
6975 | goto do_addone_branch_i; | |
6976 | case M_BGE_I: | |
6977 | s = "slti"; | |
6978 | s2 = "bteqz"; | |
6979 | s3 = "x,8"; | |
6980 | goto do_branch_i; | |
6981 | case M_BGEU_I: | |
6982 | s = "sltiu"; | |
6983 | s2 = "bteqz"; | |
6984 | s3 = "x,8"; | |
6985 | goto do_branch_i; | |
6986 | case M_BGT_I: | |
6987 | s = "slti"; | |
6988 | s2 = "bteqz"; | |
6989 | s3 = "x,8"; | |
6990 | goto do_addone_branch_i; | |
6991 | case M_BGTU_I: | |
6992 | s = "sltiu"; | |
6993 | s2 = "bteqz"; | |
6994 | s3 = "x,8"; | |
6995 | ||
6996 | do_addone_branch_i: | |
5c6f5923 | 6997 | if (imm_expr.X_op != O_constant) |
48401fcf | 6998 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6999 | ++imm_expr.X_add_number; |
7000 | ||
7001 | do_branch_i: | |
7002 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7003 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7004 | break; | |
18e0764d ILT |
7005 | |
7006 | case M_ABS: | |
7007 | expr1.X_add_number = 0; | |
7008 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
7009 | if (xreg != yreg) | |
7010 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7011 | "move", "y,X", xreg, yreg); | |
7012 | expr1.X_add_number = 2; | |
7013 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7015 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
7016 | } |
7017 | } | |
7018 | ||
aa2e0460 KR |
7019 | /* For consistency checking, verify that all bits are specified either |
7020 | by the match/mask part of the instruction definition, or by the | |
7021 | operand list. */ | |
7022 | static int | |
7023 | validate_mips_insn (opc) | |
7024 | const struct mips_opcode *opc; | |
7025 | { | |
7026 | const char *p = opc->args; | |
7027 | char c; | |
7028 | unsigned long used_bits = opc->mask; | |
7029 | ||
7030 | if ((used_bits & opc->match) != opc->match) | |
7031 | { | |
48401fcf | 7032 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
aa2e0460 KR |
7033 | opc->name, opc->args); |
7034 | return 0; | |
7035 | } | |
7036 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7037 | while (*p) | |
7038 | switch (c = *p++) | |
7039 | { | |
7040 | case ',': break; | |
7041 | case '(': break; | |
7042 | case ')': break; | |
7043 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7044 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7045 | case 'A': break; | |
7046 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
7047 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
7048 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7049 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7050 | case 'F': break; | |
7051 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7052 | case 'I': break; | |
7053 | case 'L': break; | |
7054 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7055 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7056 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7057 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7058 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7059 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7060 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7061 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7062 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7063 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7064 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7065 | case 'f': break; | |
7066 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7067 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7068 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7069 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7070 | case 'l': break; | |
7071 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7072 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
40f0c904 | 7073 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
aa2e0460 KR |
7074 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
7075 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7076 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7077 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7078 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7079 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7080 | case 'x': break; | |
7081 | case 'z': break; | |
aa2e0460 | 7082 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
3c69baf9 GRK |
7083 | /* start-sanitize-r5900 */ |
7084 | case '0': USE_BITS (OP_MASK_VADDI, OP_SH_VADDI); break; | |
7085 | case '1': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7086 | case '2': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7087 | case '3': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7088 | case '4': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7089 | case '5': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7090 | case '6': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7091 | case '7': | |
7092 | USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); | |
7093 | USE_BITS (OP_MASK_VUFTF, OP_SH_VUFTF); | |
7094 | break; | |
7095 | case '8': | |
7096 | USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); | |
7097 | USE_BITS (OP_MASK_VUFSF, OP_SH_VUFSF); | |
7098 | break; | |
7099 | case '9': break; | |
7100 | case 'K': break; | |
7101 | case 'X': break; | |
7102 | case 'U': break; | |
7103 | case 'Q': break; | |
7104 | case 'J': break; | |
7105 | case 'O': USE_BITS (OP_MASK_VUCALLMS, OP_SH_VUCALLMS);break; | |
7106 | case '&': USE_BITS (OP_MASK_VUDEST, OP_SH_VUDEST); break; | |
be294de6 | 7107 | case ';': break; |
3c69baf9 GRK |
7108 | case '#': |
7109 | p++; | |
7110 | break; | |
7111 | case '-': break; | |
7112 | case '+': break; | |
7113 | /* end-sanitize-r5900 */ | |
6b34ac5a | 7114 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7115 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7116 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7117 | case '[': break; | |
7118 | case ']': break; | |
6b34ac5a | 7119 | /* end-sanitize-cygnus */ |
aa2e0460 | 7120 | default: |
48401fcf | 7121 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
aa2e0460 KR |
7122 | c, opc->name, opc->args); |
7123 | return 0; | |
7124 | } | |
7125 | #undef USE_BITS | |
aa2e0460 KR |
7126 | if (used_bits != 0xffffffff) |
7127 | { | |
48401fcf | 7128 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
aa2e0460 KR |
7129 | ~used_bits & 0xffffffff, opc->name, opc->args); |
7130 | return 0; | |
7131 | } | |
7132 | return 1; | |
7133 | } | |
7134 | ||
cc5703cd ILT |
7135 | /* This routine assembles an instruction into its binary format. As a |
7136 | side effect, it sets one of the global variables imm_reloc or | |
7137 | offset_reloc to the type of relocation to do if one of the operands | |
7138 | is an address expression. */ | |
7139 | ||
7140 | static void | |
7141 | mips_ip (str, ip) | |
7142 | char *str; | |
7143 | struct mips_cl_insn *ip; | |
7144 | { | |
7145 | char *s; | |
7146 | const char *args; | |
7147 | char c; | |
7148 | struct mips_opcode *insn; | |
7149 | char *argsStart; | |
7150 | unsigned int regno; | |
7151 | unsigned int lastregno = 0; | |
7152 | char *s_reset; | |
059a6388 | 7153 | char save_c = 0; |
48401fcf | 7154 | int full_opcode_match = 1; |
cc5703cd ILT |
7155 | |
7156 | insn_error = NULL; | |
7157 | ||
059a6388 JL |
7158 | /* If the instruction contains a '.', we first try to match an instruction |
7159 | including the '.'. Then we try again without the '.'. */ | |
7160 | insn = NULL; | |
e2e5acfa | 7161 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 7162 | continue; |
059a6388 JL |
7163 | |
7164 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7165 | the call to hash_find. Save the character we replaced just in case we | |
7166 | have to re-parse the instruction. */ | |
1857d1e6 | 7167 | if (isspace (*s)) |
059a6388 JL |
7168 | { |
7169 | save_c = *s; | |
7170 | *s++ = '\0'; | |
7171 | } | |
7172 | ||
7173 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
1857d1e6 | 7174 | |
059a6388 JL |
7175 | /* If we didn't find the instruction in the opcode table, try again, but |
7176 | this time with just the instruction up to, but not including the | |
7177 | first '.'. */ | |
7178 | if (insn == NULL) | |
cc5703cd | 7179 | { |
059a6388 JL |
7180 | /* Restore the character we overwrite above (if any). */ |
7181 | if (save_c) | |
7182 | *(--s) = save_c; | |
7183 | ||
7184 | /* Scan up to the first '.' or whitespace. */ | |
7185 | for (s = str; *s != '\0' && *s != '.' && !isspace (*s); ++s) | |
7186 | continue; | |
7187 | ||
7188 | /* If we did not find a '.', then we can quit now. */ | |
7189 | if (*s != '.') | |
7190 | { | |
7191 | insn_error = "unrecognized opcode"; | |
7192 | return; | |
7193 | } | |
7194 | ||
7195 | /* Lookup the instruction in the hash table. */ | |
7196 | *s++ = '\0'; | |
7197 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7198 | { | |
7199 | insn_error = "unrecognized opcode"; | |
7200 | return; | |
7201 | } | |
48401fcf TT |
7202 | |
7203 | full_opcode_match = 0; | |
cc5703cd | 7204 | } |
059a6388 | 7205 | |
cc5703cd ILT |
7206 | argsStart = s; |
7207 | for (;;) | |
7208 | { | |
7209 | int insn_isa; | |
a652f74c | 7210 | boolean ok; |
cc5703cd ILT |
7211 | |
7212 | assert (strcmp (insn->name, str) == 0); | |
7213 | ||
1c6f3441 | 7214 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 7215 | insn_isa = 1; |
5c6f5923 | 7216 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 7217 | insn_isa = 2; |
5c6f5923 | 7218 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 7219 | insn_isa = 3; |
5c6f5923 | 7220 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
7221 | insn_isa = 4; |
7222 | else | |
931a1858 | 7223 | insn_isa = 15; |
cc5703cd | 7224 | |
a652f74c ILT |
7225 | if (insn_isa <= mips_opts.isa) |
7226 | ok = true; | |
7227 | else if (insn->pinfo == INSN_MACRO) | |
7228 | ok = false; | |
7229 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
7230 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
7231 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
2d035a50 GRK |
7232 | /* start-sanitize-vr4320 */ |
7233 | || (mips_4320 && (insn->membership & INSN_4320) != 0) | |
7234 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
7235 | /* start-sanitize-tx49 */ |
7236 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
7237 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
7238 | /* start-sanitize-r5900 */ |
7239 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
7240 | /* end-sanitize-r5900 */ | |
6b34ac5a | 7241 | /* start-sanitize-cygnus */ |
aa2e0460 | 7242 | || (mips_5400 && (insn->membership & INSN_5400) != 0) |
6b34ac5a | 7243 | /* end-sanitize-cygnus */ |
a652f74c | 7244 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7245 | ok = true; |
a652f74c ILT |
7246 | else |
7247 | ok = false; | |
7248 | ||
b2cf4548 DE |
7249 | if (insn->pinfo != INSN_MACRO) |
7250 | { | |
7251 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
7252 | ok = false; | |
7253 | /* start-sanitize-r5900 */ | |
7254 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
7255 | ok = false; | |
7256 | /* end-sanitize-r5900 */ | |
7257 | } | |
1c6f3441 | 7258 | |
a652f74c | 7259 | if (! ok) |
cc5703cd ILT |
7260 | { |
7261 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7262 | && strcmp (insn->name, insn[1].name) == 0) | |
7263 | { | |
7264 | ++insn; | |
7265 | continue; | |
7266 | } | |
6fd819cf GRK |
7267 | if (insn_isa == 15 |
7268 | || insn_isa <= mips_opts.isa) | |
48401fcf | 7269 | insn_error = _("opcode not supported on this processor"); |
cc5703cd ILT |
7270 | else |
7271 | { | |
7272 | static char buf[100]; | |
7273 | ||
48401fcf | 7274 | sprintf (buf, _("opcode requires -mips%d or greater"), insn_isa); |
cc5703cd ILT |
7275 | insn_error = buf; |
7276 | } | |
7277 | return; | |
7278 | } | |
8358c818 | 7279 | |
670a50eb ILT |
7280 | ip->insn_mo = insn; |
7281 | ip->insn_opcode = insn->match; | |
7282 | for (args = insn->args;; ++args) | |
7283 | { | |
7284 | if (*s == ' ') | |
7285 | ++s; | |
7286 | switch (*args) | |
7287 | { | |
7288 | case '\0': /* end of args */ | |
7289 | if (*s == '\0') | |
7290 | return; | |
7291 | break; | |
3d3c5039 ILT |
7292 | |
7293 | case ',': | |
670a50eb ILT |
7294 | if (*s++ == *args) |
7295 | continue; | |
7296 | s--; | |
7297 | switch (*++args) | |
7298 | { | |
3d3c5039 ILT |
7299 | case 'r': |
7300 | case 'v': | |
670a50eb ILT |
7301 | ip->insn_opcode |= lastregno << 21; |
7302 | continue; | |
3d3c5039 ILT |
7303 | |
7304 | case 'w': | |
7305 | case 'W': | |
670a50eb ILT |
7306 | ip->insn_opcode |= lastregno << 16; |
7307 | continue; | |
3d3c5039 ILT |
7308 | |
7309 | case 'V': | |
670a50eb ILT |
7310 | ip->insn_opcode |= lastregno << 11; |
7311 | continue; | |
3d3c5039 | 7312 | } |
670a50eb | 7313 | break; |
3d3c5039 ILT |
7314 | |
7315 | case '(': | |
059a6388 | 7316 | /* Handle optional base register. |
670a50eb ILT |
7317 | Either the base register is omitted or |
7318 | we must have a left paren. */ | |
059a6388 JL |
7319 | /* This is dependent on the next operand specifier |
7320 | is a base register specification. */ | |
7321 | assert (args[1] == 'b' || args[1] == '5' | |
7322 | || args[1] == '-' || args[1] == '4'); | |
670a50eb ILT |
7323 | if (*s == '\0') |
7324 | return; | |
3d3c5039 | 7325 | |
670a50eb | 7326 | case ')': /* these must match exactly */ |
6b34ac5a | 7327 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7328 | case '[': |
7329 | case ']': | |
6b34ac5a | 7330 | /* end-sanitize-cygnus */ |
059a6388 JL |
7331 | /* start-sanitize-r5900 */ |
7332 | case '-': | |
7333 | case '+': | |
7334 | /* end-sanitize-r5900 */ | |
670a50eb | 7335 | if (*s++ == *args) |
3d3c5039 | 7336 | continue; |
670a50eb ILT |
7337 | break; |
7338 | ||
7339 | case '<': /* must be at least one digit */ | |
7340 | /* | |
7341 | * According to the manual, if the shift amount is greater | |
7342 | * than 31 or less than 0 the the shift amount should be | |
7343 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7344 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7345 | */ |
7346 | my_getExpression (&imm_expr, s); | |
7347 | check_absolute_expr (ip, &imm_expr); | |
7348 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7349 | { | |
48401fcf | 7350 | as_warn (_("Improper shift amount (%ld)"), |
58d4951d | 7351 | (long) imm_expr.X_add_number); |
9226253a | 7352 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7353 | } |
7354 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7355 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7356 | s = expr_end; |
7357 | continue; | |
7358 | ||
56c96faa ILT |
7359 | case '>': /* shift amount minus 32 */ |
7360 | my_getExpression (&imm_expr, s); | |
7361 | check_absolute_expr (ip, &imm_expr); | |
7362 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7363 | || (unsigned long) imm_expr.X_add_number > 63) | |
7364 | break; | |
7365 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7366 | imm_expr.X_op = O_absent; | |
7367 | s = expr_end; | |
7368 | continue; | |
7369 | ||
059a6388 JL |
7370 | /* start-sanitize-r5900 */ |
7371 | case '0': /* 5 bit signed immediate at 6 */ | |
7372 | my_getExpression (&imm_expr, s); | |
7373 | check_absolute_expr (ip, &imm_expr); | |
7374 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7375 | || ((imm_expr.X_add_number < -16 | |
7376 | || imm_expr.X_add_number >= 16) | |
7377 | && imm_expr.X_op == O_constant)) | |
7378 | { | |
7379 | if (imm_expr.X_op != O_constant | |
7380 | && imm_expr.X_op != O_big) | |
7381 | insn_error = "absolute expression required"; | |
7382 | else | |
48401fcf | 7383 | as_bad (_("5 bit expression not in range -16..15")); |
059a6388 JL |
7384 | } |
7385 | ip->insn_opcode |= (imm_expr.X_add_number) << 6; | |
7386 | imm_expr.X_op = O_absent; | |
7387 | s = expr_end; | |
7388 | continue; | |
7389 | ||
65a17223 | 7390 | case '9': /* vi27 for vcallmsr */ |
7e656649 RH |
7391 | if (strncmp (s, "$vi27", 5) == 0) |
7392 | s += 5; | |
7393 | else if (strncmp (s, "vi27", 4) == 0) | |
059a6388 JL |
7394 | s += 4; |
7395 | else | |
48401fcf | 7396 | as_bad (_("expected vi27")); |
059a6388 JL |
7397 | continue; |
7398 | ||
981ce186 JL |
7399 | case '#': /* escape character */ |
7400 | /* '#' specifies that we've got an optional suffix to this | |
059a6388 JL |
7401 | operand that must match exactly (if it exists). */ |
7402 | if (*s != '\0' && *s != ',' | |
7403 | && *s != ' ' && *s != '\t' && *s != '\n') | |
7404 | { | |
7405 | if (*s == *(args + 1)) | |
7406 | { | |
7407 | s++; | |
7408 | args++; | |
7409 | continue; | |
7410 | } | |
7411 | break; | |
7412 | } | |
7413 | args++; | |
7414 | continue; | |
7415 | ||
7416 | case 'K': /* DEST operand completer (optional), must | |
7417 | match previous dest if specified. */ | |
7418 | case '&': /* DEST instruction completer */ | |
be294de6 | 7419 | case ';': /* DEST instruction completer, must be xyz */ |
059a6388 JL |
7420 | { |
7421 | int w,x,y,z; | |
7422 | static int last_h; | |
7423 | ||
7424 | w = x = y = z = 0; | |
7425 | ||
7426 | /* Parse the completer. */ | |
7427 | s_reset = s; | |
48401fcf TT |
7428 | while ((!full_opcode_match || *args == 'K') |
7429 | && *s != '\0' && *s != ' ' && *s != ',') | |
059a6388 JL |
7430 | { |
7431 | if (*s == 'w') | |
7432 | w++; | |
7433 | else if (*s == 'x') | |
7434 | x++; | |
7435 | else if (*s == 'y') | |
7436 | y++; | |
7437 | else if (*s == 'z') | |
7438 | z++; | |
7439 | else | |
7440 | { | |
7441 | insn_error = "Invalid dest specification"; | |
48401fcf | 7442 | break; |
059a6388 JL |
7443 | } |
7444 | s++; | |
7445 | } | |
7446 | ||
48401fcf TT |
7447 | if (insn_error) |
7448 | continue; | |
7449 | ||
059a6388 JL |
7450 | /* Each completer can only appear once. */ |
7451 | if (w > 1 || x > 1 || y > 1 || z > 1) | |
7452 | { | |
7453 | insn_error = "Invalid dest specification"; | |
7454 | continue; | |
7455 | } | |
7456 | ||
7457 | /* If this is the opcode completer, then we must insert | |
7458 | the appropriate value into the insn. */ | |
7459 | if (*args == '&') | |
7460 | { | |
48401fcf TT |
7461 | /* Not strictly in the specs, but requested by users. */ |
7462 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7463 | w = x = y = z = 1; | |
7464 | ||
059a6388 JL |
7465 | ip->insn_opcode |= ((w << 21) | (x << 24) |
7466 | | (y << 23) | (z << 22)); | |
7467 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7468 | } | |
be294de6 JL |
7469 | else if (*args == ';') |
7470 | { | |
7471 | /* This implicitly has the .xyz completer. */ | |
7472 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7473 | x = y = z = 1; | |
7474 | ||
7475 | if (w != 0 || x != 1 || y != 1 || z != 1) | |
7476 | { | |
7477 | insn_error = "Invalid dest specification"; | |
7478 | continue; | |
7479 | } | |
7480 | ||
7481 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7482 | } | |
059a6388 JL |
7483 | else |
7484 | { | |
7485 | int temp; | |
7486 | ||
7487 | /* This is the operand completer, make sure it matches | |
7488 | the previous opcode completer. */ | |
7489 | temp = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7490 | if (temp && temp != last_h) | |
7491 | { | |
7492 | insn_error = "DEST field in operand does not match DEST field in instruction"; | |
7493 | continue; | |
7494 | } | |
7495 | ||
7496 | } | |
7497 | ||
7498 | continue; | |
7499 | } | |
7500 | ||
7501 | case 'J': /* vu0 I register */ | |
7502 | if (s[0] == 'I') | |
7503 | s += 1; | |
7504 | else | |
7505 | insn_error = "operand `I' expected"; | |
7506 | continue; | |
7507 | ||
7508 | case 'Q': /* vu0 Q register */ | |
7509 | if (s[0] == 'Q') | |
7510 | s += 1; | |
7511 | else | |
7512 | insn_error = "operand `Q' expected"; | |
7513 | continue; | |
7514 | ||
7515 | case 'X': /* vu0 R register */ | |
7516 | if (s[0] == 'R') | |
7517 | s += 1; | |
7518 | else | |
7519 | insn_error = "operand `R' expected"; | |
7520 | continue; | |
7521 | ||
7522 | case 'U': /* vu0 ACC register */ | |
7523 | if (s[0] == 'A' && s[1] == 'C' && s[2] == 'C') | |
7524 | s += 3; | |
7525 | else | |
7526 | insn_error = "operand `ACC' expected"; | |
7527 | continue; | |
0bc0e337 JL |
7528 | |
7529 | case 'O': | |
7530 | my_getSmallExpression (&imm_expr, s); | |
7531 | imm_reloc = BFD_RELOC_MIPS15_S3; | |
7532 | s = expr_end; | |
7533 | continue; | |
059a6388 JL |
7534 | /* end-sanitize-r5900 */ |
7535 | ||
9226253a | 7536 | case 'k': /* cache code */ |
d8a1c247 | 7537 | case 'h': /* prefx code */ |
9226253a ILT |
7538 | my_getExpression (&imm_expr, s); |
7539 | check_absolute_expr (ip, &imm_expr); | |
7540 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7541 | { | |
48401fcf | 7542 | as_warn (_("Invalid value for `%s' (%lu)"), |
d8a1c247 | 7543 | ip->insn_mo->name, |
9226253a ILT |
7544 | (unsigned long) imm_expr.X_add_number); |
7545 | imm_expr.X_add_number &= 0x1f; | |
7546 | } | |
d8a1c247 KR |
7547 | if (*args == 'k') |
7548 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7549 | else | |
7550 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7551 | imm_expr.X_op = O_absent; |
7552 | s = expr_end; | |
7553 | continue; | |
7554 | ||
670a50eb ILT |
7555 | case 'c': /* break code */ |
7556 | my_getExpression (&imm_expr, s); | |
7557 | check_absolute_expr (ip, &imm_expr); | |
7558 | if ((unsigned) imm_expr.X_add_number > 1023) | |
40f0c904 FCE |
7559 | { |
7560 | as_warn (_("Illegal break code (%ld)"), | |
7561 | (long) imm_expr.X_add_number); | |
7562 | imm_expr.X_add_number &= 0x3ff; | |
7563 | } | |
670a50eb | 7564 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7565 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7566 | s = expr_end; |
7567 | continue; | |
7568 | ||
40f0c904 FCE |
7569 | case 'q': /* lower break code */ |
7570 | my_getExpression (&imm_expr, s); | |
7571 | check_absolute_expr (ip, &imm_expr); | |
7572 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7573 | { | |
7574 | as_warn (_("Illegal lower break code (%ld)"), | |
7575 | (long) imm_expr.X_add_number); | |
7576 | imm_expr.X_add_number &= 0x3ff; | |
7577 | } | |
7578 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7579 | imm_expr.X_op = O_absent; | |
7580 | s = expr_end; | |
7581 | continue; | |
7582 | ||
918692a5 ILT |
7583 | case 'B': /* syscall code */ |
7584 | my_getExpression (&imm_expr, s); | |
7585 | check_absolute_expr (ip, &imm_expr); | |
7586 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
48401fcf | 7587 | as_warn (_("Illegal syscall code (%ld)"), |
58d4951d | 7588 | (long) imm_expr.X_add_number); |
918692a5 | 7589 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7590 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7591 | s = expr_end; |
7592 | continue; | |
7593 | ||
0aa07269 ILT |
7594 | case 'C': /* Coprocessor code */ |
7595 | my_getExpression (&imm_expr, s); | |
7596 | check_absolute_expr (ip, &imm_expr); | |
7597 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7598 | { | |
48401fcf | 7599 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
58d4951d | 7600 | (long) imm_expr.X_add_number); |
0aa07269 ILT |
7601 | imm_expr.X_add_number &= ((1<<25) - 1); |
7602 | } | |
7603 | ip->insn_opcode |= imm_expr.X_add_number; | |
7604 | imm_expr.X_op = O_absent; | |
7605 | s = expr_end; | |
7606 | continue; | |
7607 | ||
65d2c7d3 JL |
7608 | case 'P': /* Performance register */ |
7609 | my_getExpression (&imm_expr, s); | |
7610 | check_absolute_expr (ip, &imm_expr); | |
7611 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7612 | { | |
48401fcf | 7613 | as_warn (_("Invalidate performance regster (%ld)"), |
65d2c7d3 JL |
7614 | (long) imm_expr.X_add_number); |
7615 | imm_expr.X_add_number &= 1; | |
7616 | } | |
7617 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7618 | imm_expr.X_op = O_absent; | |
7619 | s = expr_end; | |
7620 | continue; | |
7621 | ||
670a50eb ILT |
7622 | case 'b': /* base register */ |
7623 | case 'd': /* destination register */ | |
7624 | case 's': /* source register */ | |
7625 | case 't': /* target register */ | |
7626 | case 'r': /* both target and source */ | |
7627 | case 'v': /* both dest and source */ | |
7628 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7629 | case 'E': /* coprocessor target register */ |
7630 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7631 | case 'x': /* ignore register name */ |
ff3a5c18 | 7632 | case 'z': /* must be zero register */ |
670a50eb ILT |
7633 | s_reset = s; |
7634 | if (s[0] == '$') | |
7635 | { | |
7e656649 RH |
7636 | /* start-sanitize-r5900 */ |
7637 | /* Allow "$viNN" as coprocessor register name */ | |
7638 | if (mips_5900 | |
7639 | && *args == 'G' | |
7640 | && s[1] == 'v' | |
7641 | && s[2] == 'i') | |
7642 | { | |
7643 | s += 2; | |
7644 | } | |
7645 | /* end-sanitize-r5900 */ | |
7646 | ||
670a50eb ILT |
7647 | if (isdigit (s[1])) |
7648 | { | |
7649 | ++s; | |
7650 | regno = 0; | |
7651 | do | |
7652 | { | |
7653 | regno *= 10; | |
7654 | regno += *s - '0'; | |
7655 | ++s; | |
7656 | } | |
7657 | while (isdigit (*s)); | |
0aa07269 | 7658 | if (regno > 31) |
48401fcf | 7659 | as_bad (_("Invalid register number (%d)"), regno); |
670a50eb | 7660 | } |
0dd2d296 ILT |
7661 | else if (*args == 'E' || *args == 'G') |
7662 | goto notreg; | |
7663 | else | |
670a50eb | 7664 | { |
0aa07269 ILT |
7665 | if (s[1] == 'f' && s[2] == 'p') |
7666 | { | |
7667 | s += 3; | |
9226253a | 7668 | regno = FP; |
0aa07269 ILT |
7669 | } |
7670 | else if (s[1] == 's' && s[2] == 'p') | |
7671 | { | |
7672 | s += 3; | |
9226253a | 7673 | regno = SP; |
0aa07269 ILT |
7674 | } |
7675 | else if (s[1] == 'g' && s[2] == 'p') | |
7676 | { | |
7677 | s += 3; | |
9226253a | 7678 | regno = GP; |
0aa07269 ILT |
7679 | } |
7680 | else if (s[1] == 'a' && s[2] == 't') | |
7681 | { | |
7682 | s += 3; | |
9226253a | 7683 | regno = AT; |
0aa07269 | 7684 | } |
b2b8c24e ILT |
7685 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7686 | { | |
7687 | s += 4; | |
7688 | regno = KT0; | |
7689 | } | |
7690 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7691 | { | |
7692 | s += 4; | |
7693 | regno = KT1; | |
7694 | } | |
efec4a28 DP |
7695 | else if (itbl_have_entries) |
7696 | { | |
7697 | char *p, *n; | |
7698 | int r; | |
7699 | ||
7700 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7701 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7702 | |
7703 | /* See if this is a register defined in an | |
7704 | itbl entry */ | |
9218cee0 ILT |
7705 | r = itbl_get_reg_val (n); |
7706 | if (r) | |
efec4a28 | 7707 | { |
9218cee0 ILT |
7708 | /* Get_field advances to the start of |
7709 | the next field, so we need to back | |
7710 | rack to the end of the last field. */ | |
efec4a28 | 7711 | if (p) |
9218cee0 | 7712 | s = p - 1; |
efec4a28 | 7713 | else |
9218cee0 | 7714 | s = strchr (s,'\0'); |
efec4a28 DP |
7715 | regno = r; |
7716 | } | |
7717 | else | |
7718 | goto notreg; | |
7719 | } | |
0aa07269 ILT |
7720 | else |
7721 | goto notreg; | |
670a50eb | 7722 | } |
9753202d | 7723 | if (regno == AT |
3c83da8a | 7724 | && ! mips_opts.noat |
9753202d ILT |
7725 | && *args != 'E' |
7726 | && *args != 'G') | |
48401fcf | 7727 | as_warn (_("Used $at without \".set noat\"")); |
670a50eb ILT |
7728 | c = *args; |
7729 | if (*s == ' ') | |
7730 | s++; | |
7731 | if (args[1] != *s) | |
7732 | { | |
7733 | if (c == 'r' || c == 'v' || c == 'w') | |
7734 | { | |
7735 | regno = lastregno; | |
7736 | s = s_reset; | |
7737 | args++; | |
7738 | } | |
7739 | } | |
ff3a5c18 ILT |
7740 | /* 'z' only matches $0. */ |
7741 | if (c == 'z' && regno != 0) | |
7742 | break; | |
efec4a28 DP |
7743 | |
7744 | /* Now that we have assembled one operand, we use the args string | |
7745 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7746 | switch (c) |
7747 | { | |
3d3c5039 ILT |
7748 | case 'r': |
7749 | case 's': | |
7750 | case 'v': | |
7751 | case 'b': | |
670a50eb ILT |
7752 | ip->insn_opcode |= regno << 21; |
7753 | break; | |
3d3c5039 | 7754 | case 'd': |
918692a5 | 7755 | case 'G': |
670a50eb ILT |
7756 | ip->insn_opcode |= regno << 11; |
7757 | break; | |
3d3c5039 ILT |
7758 | case 'w': |
7759 | case 't': | |
918692a5 | 7760 | case 'E': |
670a50eb | 7761 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7762 | break; |
7763 | case 'x': | |
7764 | /* This case exists because on the r3000 trunc | |
7765 | expands into a macro which requires a gp | |
7766 | register. On the r6000 or r4000 it is | |
7767 | assembled into a single instruction which | |
7768 | ignores the register. Thus the insn version | |
7769 | is MIPS_ISA2 and uses 'x', and the macro | |
7770 | version is MIPS_ISA1 and uses 't'. */ | |
7771 | break; | |
ff3a5c18 ILT |
7772 | case 'z': |
7773 | /* This case is for the div instruction, which | |
7774 | acts differently if the destination argument | |
7775 | is $0. This only matches $0, and is checked | |
7776 | outside the switch. */ | |
7777 | break; | |
efec4a28 DP |
7778 | case 'D': |
7779 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7780 | break; | |
9218cee0 ILT |
7781 | /* What about all other operands like 'i', which |
7782 | can be specified in the opcode table? */ | |
3d3c5039 | 7783 | } |
670a50eb ILT |
7784 | lastregno = regno; |
7785 | continue; | |
3d3c5039 ILT |
7786 | } |
7787 | notreg: | |
670a50eb ILT |
7788 | switch (*args++) |
7789 | { | |
3d3c5039 ILT |
7790 | case 'r': |
7791 | case 'v': | |
670a50eb ILT |
7792 | ip->insn_opcode |= lastregno << 21; |
7793 | continue; | |
3d3c5039 | 7794 | case 'w': |
670a50eb ILT |
7795 | ip->insn_opcode |= lastregno << 16; |
7796 | continue; | |
3d3c5039 | 7797 | } |
670a50eb | 7798 | break; |
3d3c5039 | 7799 | |
670a50eb ILT |
7800 | case 'D': /* floating point destination register */ |
7801 | case 'S': /* floating point source register */ | |
7802 | case 'T': /* floating point target register */ | |
d8a1c247 | 7803 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7804 | case 'V': |
7805 | case 'W': | |
059a6388 JL |
7806 | /* start-sanitize-r5900 */ |
7807 | case '1': /* vu0 fp reg position 1 */ | |
7808 | case '2': /* vu0 fp reg position 2 */ | |
7809 | case '3': /* vu0 fp reg position 3 */ | |
7810 | case '4': /* vu0 int reg position 1 */ | |
7811 | case '5': /* vu0 int reg position 2 */ | |
7812 | case '6': /* vu0 int reg position 3 */ | |
7813 | case '7': /* vu0 fp reg with ftf modifier */ | |
7814 | case '8': /* vu0 fp reg with fsf modifier */ | |
7815 | /* end-sanitize-r5900 */ | |
670a50eb ILT |
7816 | s_reset = s; |
7817 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7818 | { | |
7819 | s += 2; | |
7820 | regno = 0; | |
7821 | do | |
7822 | { | |
7823 | regno *= 10; | |
7824 | regno += *s - '0'; | |
7825 | ++s; | |
7826 | } | |
7827 | while (isdigit (*s)); | |
7828 | ||
7829 | if (regno > 31) | |
48401fcf | 7830 | as_bad (_("Invalid float register number (%d)"), regno); |
670a50eb | 7831 | |
9226253a | 7832 | if ((regno & 1) != 0 |
3c83da8a | 7833 | && mips_opts.isa < 3 |
538034cf ILT |
7834 | && ! (strcmp (str, "mtc1") == 0 |
7835 | || strcmp (str, "mfc1") == 0 | |
7836 | || strcmp (str, "lwc1") == 0 | |
7837 | || strcmp (str, "swc1") == 0 | |
7838 | || strcmp (str, "l.s") == 0 | |
7839 | || strcmp (str, "s.s") == 0)) | |
48401fcf | 7840 | as_warn (_("Float register should be even, was %d"), |
670a50eb ILT |
7841 | regno); |
7842 | ||
7843 | c = *args; | |
7844 | if (*s == ' ') | |
7845 | s++; | |
7846 | if (args[1] != *s) | |
7847 | { | |
7848 | if (c == 'V' || c == 'W') | |
7849 | { | |
7850 | regno = lastregno; | |
7851 | s = s_reset; | |
7852 | args++; | |
3d3c5039 ILT |
7853 | } |
7854 | } | |
670a50eb ILT |
7855 | switch (c) |
7856 | { | |
3d3c5039 | 7857 | case 'D': |
670a50eb ILT |
7858 | ip->insn_opcode |= regno << 6; |
7859 | break; | |
3d3c5039 ILT |
7860 | case 'V': |
7861 | case 'S': | |
670a50eb ILT |
7862 | ip->insn_opcode |= regno << 11; |
7863 | break; | |
3d3c5039 ILT |
7864 | case 'W': |
7865 | case 'T': | |
670a50eb | 7866 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7867 | break; |
7868 | case 'R': | |
7869 | ip->insn_opcode |= regno << 21; | |
7870 | break; | |
3d3c5039 | 7871 | } |
670a50eb ILT |
7872 | lastregno = regno; |
7873 | continue; | |
3d3c5039 | 7874 | } |
059a6388 JL |
7875 | |
7876 | /* start-sanitize-r5900 */ | |
7e656649 RH |
7877 | /* Handle vf and vi regsiters for vu0. Handle optional |
7878 | `$' prefix. */ | |
7879 | ||
7880 | if ((s[0] == 'v' | |
7881 | && (s[1] == 'f' || s[1] == 'i') | |
7882 | && isdigit (s[2])) | |
7883 | || | |
7884 | (s[0] == '$' | |
7885 | && s[1] == 'v' | |
7886 | && (s[2] == 'f' || s[2] == 'i') | |
7887 | && isdigit (s[3]))) | |
7888 | { | |
7889 | if(s[0] == '$') | |
7890 | ++s; | |
059a6388 JL |
7891 | s += 2; |
7892 | regno = 0; | |
7893 | do | |
7894 | { | |
7895 | regno *= 10; | |
7896 | regno += *s - '0'; | |
7897 | ++s; | |
7898 | } | |
7899 | while (isdigit (*s)); | |
7900 | ||
7901 | if (regno > 31) | |
48401fcf | 7902 | as_bad (_("Invalid vu0 register number (%d)"), regno); |
059a6388 JL |
7903 | |
7904 | c = *args; | |
7905 | ||
7906 | if (c == '7' || c == '8') | |
7907 | { | |
7908 | int value; | |
7909 | ||
7910 | switch (*s) | |
7911 | { | |
7912 | case 'w': | |
7913 | value = 3; | |
7914 | s++; | |
7915 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7916 | break; | |
7917 | case 'x': | |
7918 | value = 0; | |
7919 | s++; | |
7920 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7921 | break; | |
7922 | case 'y': | |
7923 | value = 1; | |
7924 | s++; | |
7925 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7926 | break; | |
7927 | case 'z': | |
7928 | value = 2; | |
7929 | s++; | |
7930 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7931 | break; | |
7932 | default: | |
48401fcf | 7933 | as_bad (_("Invalid FSF/FTF specification")); |
059a6388 JL |
7934 | } |
7935 | } | |
7936 | ||
7937 | if (*s == ' ') | |
7938 | s++; | |
7939 | if (args[1] != *s) | |
7940 | { | |
7941 | if (c == 'V' || c == 'W') | |
7942 | { | |
7943 | regno = lastregno; | |
7944 | s = s_reset; | |
7945 | args++; | |
7946 | } | |
7947 | } | |
7948 | switch (c) | |
7949 | { | |
7950 | case '1': | |
7951 | case '4': | |
7952 | case '7': | |
7953 | ip->insn_opcode |= regno << 16; | |
7954 | break; | |
7955 | case '2': | |
7956 | case '5': | |
7957 | case '8': | |
7958 | ip->insn_opcode |= regno << 11; | |
7959 | break; | |
7960 | case '3': | |
7961 | case '6': | |
7962 | ip->insn_opcode |= regno << 6; | |
7963 | break; | |
7964 | } | |
7965 | lastregno = regno; | |
7966 | continue; | |
7967 | } | |
7968 | /* end-sanitize-r5900 */ | |
7969 | ||
670a50eb ILT |
7970 | switch (*args++) |
7971 | { | |
3d3c5039 | 7972 | case 'V': |
670a50eb ILT |
7973 | ip->insn_opcode |= lastregno << 11; |
7974 | continue; | |
3d3c5039 | 7975 | case 'W': |
670a50eb ILT |
7976 | ip->insn_opcode |= lastregno << 16; |
7977 | continue; | |
3d3c5039 | 7978 | } |
670a50eb | 7979 | break; |
3d3c5039 ILT |
7980 | |
7981 | case 'I': | |
670a50eb | 7982 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7983 | if (imm_expr.X_op != O_big |
7984 | && imm_expr.X_op != O_constant) | |
48401fcf | 7985 | insn_error = _("absolute expression required"); |
670a50eb ILT |
7986 | s = expr_end; |
7987 | continue; | |
3d3c5039 ILT |
7988 | |
7989 | case 'A': | |
670a50eb ILT |
7990 | my_getExpression (&offset_expr, s); |
7991 | imm_reloc = BFD_RELOC_32; | |
7992 | s = expr_end; | |
7993 | continue; | |
3d3c5039 ILT |
7994 | |
7995 | case 'F': | |
19ed8960 ILT |
7996 | case 'L': |
7997 | case 'f': | |
7998 | case 'l': | |
7999 | { | |
8000 | int f64; | |
8001 | char *save_in; | |
8002 | char *err; | |
8003 | unsigned char temp[8]; | |
604633ae ILT |
8004 | int len; |
8005 | unsigned int length; | |
19ed8960 ILT |
8006 | segT seg; |
8007 | subsegT subseg; | |
8008 | char *p; | |
8009 | ||
8010 | /* These only appear as the last operand in an | |
8011 | instruction, and every instruction that accepts | |
8012 | them in any variant accepts them in all variants. | |
8013 | This means we don't have to worry about backing out | |
8014 | any changes if the instruction does not match. | |
8015 | ||
8016 | The difference between them is the size of the | |
8017 | floating point constant and where it goes. For 'F' | |
8018 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8019 | is 32 bits. Where the constant is placed is based | |
8020 | on how the MIPS assembler does things: | |
8021 | F -- .rdata | |
8022 | L -- .lit8 | |
8023 | f -- immediate value | |
8024 | l -- .lit4 | |
0dd2d296 | 8025 | |
55933a58 ILT |
8026 | The .lit4 and .lit8 sections are only used if |
8027 | permitted by the -G argument. | |
8028 | ||
8029 | When generating embedded PIC code, we use the | |
8030 | .lit8 section but not the .lit4 section (we can do | |
8031 | .lit4 inline easily; we need to put .lit8 | |
8032 | somewhere in the data segment, and using .lit8 | |
8033 | permits the linker to eventually combine identical | |
8034 | .lit8 entries). */ | |
19ed8960 ILT |
8035 | |
8036 | f64 = *args == 'F' || *args == 'L'; | |
8037 | ||
8038 | save_in = input_line_pointer; | |
8039 | input_line_pointer = s; | |
604633ae ILT |
8040 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
8041 | length = len; | |
19ed8960 ILT |
8042 | s = input_line_pointer; |
8043 | input_line_pointer = save_in; | |
8044 | if (err != NULL && *err != '\0') | |
8045 | { | |
48401fcf | 8046 | as_bad (_("Bad floating point constant: %s"), err); |
19ed8960 ILT |
8047 | memset (temp, '\0', sizeof temp); |
8048 | length = f64 ? 8 : 4; | |
8049 | } | |
8050 | ||
8051 | assert (length == (f64 ? 8 : 4)); | |
8052 | ||
0dd2d296 | 8053 | if (*args == 'f' |
55933a58 | 8054 | || (*args == 'l' |
1dc1e798 KR |
8055 | && (! USE_GLOBAL_POINTER_OPT |
8056 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
8057 | || g_switch_value < 4 |
8058 | || (temp[0] == 0 && temp[1] == 0) | |
8059 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
8060 | { |
8061 | imm_expr.X_op = O_constant; | |
b9129c6f | 8062 | if (! target_big_endian) |
a5586bdc | 8063 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 8064 | else |
a5586bdc ILT |
8065 | imm_expr.X_add_number = bfd_getb32 (temp); |
8066 | } | |
8067 | else if (length > 4 | |
8068 | && ((temp[0] == 0 && temp[1] == 0) | |
8069 | || (temp[2] == 0 && temp[3] == 0)) | |
8070 | && ((temp[4] == 0 && temp[5] == 0) | |
8071 | || (temp[6] == 0 && temp[7] == 0))) | |
8072 | { | |
8073 | /* The value is simple enough to load with a | |
8074 | couple of instructions. In mips1 mode, set | |
8075 | imm_expr to the high order 32 bits and | |
8076 | offset_expr to the low order 32 bits. | |
8077 | Otherwise, set imm_expr to the entire 64 bit | |
8078 | constant. */ | |
8079 | if (mips_opts.isa < 3) | |
8080 | { | |
8081 | imm_expr.X_op = O_constant; | |
8082 | offset_expr.X_op = O_constant; | |
8083 | if (! target_big_endian) | |
8084 | { | |
8085 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8086 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8087 | } | |
8088 | else | |
8089 | { | |
8090 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8091 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8092 | } | |
8093 | if (offset_expr.X_add_number == 0) | |
8094 | offset_expr.X_op = O_absent; | |
8095 | } | |
8096 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8097 | { | |
8098 | imm_expr.X_op = O_constant; | |
8099 | if (! target_big_endian) | |
8100 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8101 | else | |
8102 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8103 | } | |
8104 | else | |
8105 | { | |
8106 | imm_expr.X_op = O_big; | |
8107 | imm_expr.X_add_number = 4; | |
8108 | if (! target_big_endian) | |
8109 | { | |
8110 | generic_bignum[0] = bfd_getl16 (temp); | |
8111 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8112 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8113 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8114 | } | |
8115 | else | |
8116 | { | |
8117 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8118 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8119 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8120 | generic_bignum[3] = bfd_getb16 (temp); | |
8121 | } | |
8122 | } | |
19ed8960 ILT |
8123 | } |
8124 | else | |
8125 | { | |
0dd2d296 ILT |
8126 | const char *newname; |
8127 | segT new_seg; | |
8128 | ||
19ed8960 ILT |
8129 | /* Switch to the right section. */ |
8130 | seg = now_seg; | |
8131 | subseg = now_subseg; | |
8132 | switch (*args) | |
8133 | { | |
0dd2d296 | 8134 | default: /* unused default case avoids warnings. */ |
19ed8960 | 8135 | case 'L': |
1113140a | 8136 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 8137 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 8138 | newname = ".lit8"; |
0dd2d296 ILT |
8139 | break; |
8140 | case 'F': | |
d2c71068 | 8141 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
8142 | break; |
8143 | case 'l': | |
1dc1e798 KR |
8144 | assert (!USE_GLOBAL_POINTER_OPT |
8145 | || g_switch_value >= 4); | |
0dd2d296 | 8146 | newname = ".lit4"; |
19ed8960 ILT |
8147 | break; |
8148 | } | |
0dd2d296 | 8149 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
8150 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
8151 | bfd_set_section_flags (stdoutput, new_seg, | |
8152 | (SEC_ALLOC | |
8153 | | SEC_LOAD | |
8154 | | SEC_READONLY | |
8155 | | SEC_DATA)); | |
e2e5acfa JW |
8156 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
8157 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8158 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
8159 | record_alignment (new_seg, 4); |
8160 | else | |
8161 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 | 8162 | if (seg == now_seg) |
48401fcf | 8163 | as_bad (_("Can't use floating point insn in this section")); |
19ed8960 ILT |
8164 | |
8165 | /* Set the argument to the current address in the | |
6e8dda9c | 8166 | section. */ |
19ed8960 ILT |
8167 | offset_expr.X_op = O_symbol; |
8168 | offset_expr.X_add_symbol = | |
8169 | symbol_new ("L0\001", now_seg, | |
8170 | (valueT) frag_now_fix (), frag_now); | |
8171 | offset_expr.X_add_number = 0; | |
8172 | ||
8173 | /* Put the floating point number into the section. */ | |
604633ae | 8174 | p = frag_more ((int) length); |
19ed8960 ILT |
8175 | memcpy (p, temp, length); |
8176 | ||
8177 | /* Switch back to the original section. */ | |
8178 | subseg_set (seg, subseg); | |
8179 | } | |
8180 | } | |
670a50eb ILT |
8181 | continue; |
8182 | ||
8183 | case 'i': /* 16 bit unsigned immediate */ | |
8184 | case 'j': /* 16 bit signed immediate */ | |
8185 | imm_reloc = BFD_RELOC_LO16; | |
8186 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 8187 | if (c != '\0') |
670a50eb ILT |
8188 | { |
8189 | if (c != 'l') | |
8190 | { | |
5ac34ac3 | 8191 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
8192 | imm_expr.X_add_number = |
8193 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8194 | else if (c == 'h') | |
867a58b3 ILT |
8195 | { |
8196 | imm_reloc = BFD_RELOC_HI16_S; | |
8197 | imm_unmatched_hi = true; | |
8198 | } | |
670a50eb ILT |
8199 | else |
8200 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 8201 | } |
6b34ac5a ILT |
8202 | else if (imm_expr.X_op == O_constant) |
8203 | imm_expr.X_add_number &= 0xffff; | |
670a50eb | 8204 | } |
670a50eb ILT |
8205 | if (*args == 'i') |
8206 | { | |
344a8d61 | 8207 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8208 | || ((imm_expr.X_add_number < 0 |
8209 | || imm_expr.X_add_number >= 0x10000) | |
8210 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
8211 | { |
8212 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8213 | !strcmp (insn->name, insn[1].name)) | |
8214 | break; | |
9753202d ILT |
8215 | if (imm_expr.X_op != O_constant |
8216 | && imm_expr.X_op != O_big) | |
48401fcf | 8217 | insn_error = _("absolute expression required"); |
9753202d | 8218 | else |
48401fcf | 8219 | as_bad (_("16 bit expression not in range 0..65535")); |
99c24539 | 8220 | } |
670a50eb ILT |
8221 | } |
8222 | else | |
8223 | { | |
d9aba805 ILT |
8224 | int more; |
8225 | offsetT max; | |
8226 | ||
be22008b ILT |
8227 | /* The upper bound should be 0x8000, but |
8228 | unfortunately the MIPS assembler accepts numbers | |
8229 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
8230 | we want to be compatible. We only permit this |
8231 | extended range for an instruction which does not | |
8232 | provide any further alternates, since those | |
8233 | alternates may handle other cases. People should | |
8234 | use the numbers they mean, rather than relying on | |
8235 | a mysterious sign extension. */ | |
8236 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8237 | strcmp (insn->name, insn[1].name) == 0); | |
8238 | if (more) | |
8239 | max = 0x8000; | |
8240 | else | |
8241 | max = 0x10000; | |
344a8d61 | 8242 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8243 | || ((imm_expr.X_add_number < -0x8000 |
8244 | || imm_expr.X_add_number >= max) | |
8245 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
8246 | || (more |
8247 | && imm_expr.X_add_number < 0 | |
3c83da8a | 8248 | && mips_opts.isa >= 3 |
d8a1c247 KR |
8249 | && imm_expr.X_unsigned |
8250 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 8251 | { |
d9aba805 | 8252 | if (more) |
99c24539 | 8253 | break; |
9753202d ILT |
8254 | if (imm_expr.X_op != O_constant |
8255 | && imm_expr.X_op != O_big) | |
48401fcf | 8256 | insn_error = _("absolute expression required"); |
9753202d | 8257 | else |
48401fcf | 8258 | as_bad (_("16 bit expression not in range -32768..32767")); |
99c24539 | 8259 | } |
3d3c5039 | 8260 | } |
670a50eb ILT |
8261 | s = expr_end; |
8262 | continue; | |
8263 | ||
8264 | case 'o': /* 16 bit offset */ | |
8265 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
8266 | |
8267 | /* If this value won't fit into a 16 bit offset, then go | |
8268 | find a macro that will generate the 32 bit offset | |
8269 | code pattern. As a special hack, we accept the | |
8270 | difference of two local symbols as a constant. This | |
8271 | is required to suppose embedded PIC switches, which | |
8272 | use an instruction which looks like | |
8273 | lw $4,$L12-$LS12($4) | |
8274 | The problem with handling this in a more general | |
8275 | fashion is that the macro function doesn't expect to | |
8276 | see anything which can be handled in a single | |
8277 | constant instruction. */ | |
6f0b87c3 SS |
8278 | if (c == 0 |
8279 | && (offset_expr.X_op != O_constant | |
8280 | || offset_expr.X_add_number >= 0x8000 | |
8281 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
8282 | && (mips_pic != EMBEDDED_PIC |
8283 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
8284 | || now_seg != text_section |
8285 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
8286 | != text_section))) | |
670a50eb | 8287 | break; |
3d3c5039 | 8288 | |
670a50eb ILT |
8289 | offset_reloc = BFD_RELOC_LO16; |
8290 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
8291 | { |
8292 | assert (offset_expr.X_op == O_constant); | |
8293 | offset_expr.X_add_number = | |
8294 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8295 | } | |
cc5703cd ILT |
8296 | s = expr_end; |
8297 | continue; | |
8298 | ||
8299 | case 'p': /* pc relative offset */ | |
8300 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8301 | my_getExpression (&offset_expr, s); | |
8302 | s = expr_end; | |
8303 | continue; | |
8304 | ||
8305 | case 'u': /* upper 16 bits */ | |
8306 | c = my_getSmallExpression (&imm_expr, s); | |
cc5703cd ILT |
8307 | imm_reloc = BFD_RELOC_LO16; |
8308 | if (c) | |
8309 | { | |
8310 | if (c != 'l') | |
8311 | { | |
8312 | if (imm_expr.X_op == O_constant) | |
8313 | imm_expr.X_add_number = | |
8314 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8315 | else if (c == 'h') | |
8316 | { | |
8317 | imm_reloc = BFD_RELOC_HI16_S; | |
8318 | imm_unmatched_hi = true; | |
8319 | } | |
8320 | else | |
8321 | imm_reloc = BFD_RELOC_HI16; | |
8322 | } | |
6b34ac5a ILT |
8323 | else if (imm_expr.X_op == O_constant) |
8324 | imm_expr.X_add_number &= 0xffff; | |
cc5703cd | 8325 | } |
6b34ac5a ILT |
8326 | if (imm_expr.X_op == O_constant |
8327 | && (imm_expr.X_add_number < 0 | |
8328 | || imm_expr.X_add_number >= 0x10000)) | |
8329 | as_bad (_("lui expression not in range 0..65535")); | |
cc5703cd ILT |
8330 | s = expr_end; |
8331 | continue; | |
8332 | ||
8333 | case 'a': /* 26 bit address */ | |
8334 | my_getExpression (&offset_expr, s); | |
8335 | s = expr_end; | |
8336 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
8337 | continue; | |
8338 | ||
8339 | case 'N': /* 3 bit branch condition code */ | |
8340 | case 'M': /* 3 bit compare condition code */ | |
8341 | if (strncmp (s, "$fcc", 4) != 0) | |
8342 | break; | |
8343 | s += 4; | |
8344 | regno = 0; | |
8345 | do | |
8346 | { | |
8347 | regno *= 10; | |
8348 | regno += *s - '0'; | |
8349 | ++s; | |
8350 | } | |
8351 | while (isdigit (*s)); | |
8352 | if (regno > 7) | |
48401fcf | 8353 | as_bad (_("invalid condition code register $fcc%d"), regno); |
cc5703cd ILT |
8354 | if (*args == 'N') |
8355 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8356 | else | |
8357 | ip->insn_opcode |= regno << OP_SH_CCC; | |
8358 | continue; | |
8359 | ||
6b34ac5a | 8360 | /* start-sanitize-cygnus */ |
b3ed1af3 KR |
8361 | case 'e': /* must be at least one digit */ |
8362 | my_getExpression (&imm_expr, s); | |
8363 | check_absolute_expr (ip, &imm_expr); | |
8364 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
8365 | { | |
48401fcf | 8366 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8367 | (long) imm_expr.X_add_number); |
8368 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8369 | } | |
8370 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
8371 | imm_expr.X_op = O_absent; | |
8372 | s = expr_end; | |
8373 | continue; | |
8374 | ||
8375 | case '%': | |
8376 | my_getExpression (&imm_expr, s); | |
8377 | check_absolute_expr (ip, &imm_expr); | |
8378 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
8379 | { | |
48401fcf | 8380 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8381 | (long) imm_expr.X_add_number); |
8382 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8383 | } | |
8384 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
8385 | imm_expr.X_op = O_absent; | |
8386 | s = expr_end; | |
8387 | continue; | |
8388 | ||
6b34ac5a | 8389 | /* end-sanitize-cygnus */ |
cc5703cd | 8390 | default: |
48401fcf | 8391 | as_bad (_("bad char = '%c'\n"), *args); |
cc5703cd ILT |
8392 | internalError (); |
8393 | } | |
8394 | break; | |
8395 | } | |
8396 | /* Args don't match. */ | |
8397 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8398 | !strcmp (insn->name, insn[1].name)) | |
8399 | { | |
8400 | ++insn; | |
8401 | s = argsStart; | |
8402 | continue; | |
8403 | } | |
48401fcf | 8404 | insn_error = _("illegal operands"); |
cc5703cd ILT |
8405 | return; |
8406 | } | |
8407 | } | |
8408 | ||
8409 | /* This routine assembles an instruction into its binary format when | |
8410 | assembling for the mips16. As a side effect, it sets one of the | |
8411 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
8412 | relocation to do if one of the operands is an address expression. |
8413 | It also sets mips16_small and mips16_ext if the user explicitly | |
8414 | requested a small or extended instruction. */ | |
cc5703cd ILT |
8415 | |
8416 | static void | |
8417 | mips16_ip (str, ip) | |
8418 | char *str; | |
8419 | struct mips_cl_insn *ip; | |
8420 | { | |
8421 | char *s; | |
cc5703cd ILT |
8422 | const char *args; |
8423 | struct mips_opcode *insn; | |
8424 | char *argsstart; | |
8425 | unsigned int regno; | |
8426 | unsigned int lastregno = 0; | |
8427 | char *s_reset; | |
8428 | ||
8429 | insn_error = NULL; | |
8430 | ||
8728fa92 ILT |
8431 | mips16_small = false; |
8432 | mips16_ext = false; | |
cc5703cd ILT |
8433 | |
8434 | for (s = str; islower (*s); ++s) | |
8435 | ; | |
8436 | switch (*s) | |
8437 | { | |
8438 | case '\0': | |
8439 | break; | |
8440 | ||
8441 | case ' ': | |
8442 | *s++ = '\0'; | |
8443 | break; | |
8444 | ||
8445 | case '.': | |
8446 | if (s[1] == 't' && s[2] == ' ') | |
8447 | { | |
8448 | *s = '\0'; | |
8728fa92 | 8449 | mips16_small = true; |
cc5703cd ILT |
8450 | s += 3; |
8451 | break; | |
8452 | } | |
8453 | else if (s[1] == 'e' && s[2] == ' ') | |
8454 | { | |
8455 | *s = '\0'; | |
8728fa92 | 8456 | mips16_ext = true; |
cc5703cd ILT |
8457 | s += 3; |
8458 | break; | |
8459 | } | |
8460 | /* Fall through. */ | |
8461 | default: | |
48401fcf | 8462 | insn_error = _("unknown opcode"); |
cc5703cd ILT |
8463 | return; |
8464 | } | |
8465 | ||
3c83da8a | 8466 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
8467 | mips16_small = true; |
8468 | ||
cc5703cd ILT |
8469 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
8470 | { | |
48401fcf | 8471 | insn_error = _("unrecognized opcode"); |
cc5703cd ILT |
8472 | return; |
8473 | } | |
8474 | ||
8475 | argsstart = s; | |
8476 | for (;;) | |
8477 | { | |
8478 | assert (strcmp (insn->name, str) == 0); | |
8479 | ||
8480 | ip->insn_mo = insn; | |
8481 | ip->insn_opcode = insn->match; | |
8482 | ip->use_extend = false; | |
8483 | imm_expr.X_op = O_absent; | |
8484 | imm_reloc = BFD_RELOC_UNUSED; | |
8485 | offset_expr.X_op = O_absent; | |
8486 | offset_reloc = BFD_RELOC_UNUSED; | |
8487 | for (args = insn->args; 1; ++args) | |
8488 | { | |
8489 | int c; | |
8490 | ||
8491 | if (*s == ' ') | |
8492 | ++s; | |
8493 | ||
8494 | /* In this switch statement we call break if we did not find | |
8495 | a match, continue if we did find a match, or return if we | |
8496 | are done. */ | |
8497 | ||
8498 | c = *args; | |
8499 | switch (c) | |
8500 | { | |
8501 | case '\0': | |
8502 | if (*s == '\0') | |
8503 | { | |
8504 | /* Stuff the immediate value in now, if we can. */ | |
8505 | if (imm_expr.X_op == O_constant | |
8506 | && imm_reloc > BFD_RELOC_UNUSED | |
8507 | && insn->pinfo != INSN_MACRO) | |
8508 | { | |
15e69f98 ILT |
8509 | mips16_immed ((char *) NULL, 0, |
8510 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
8511 | imm_expr.X_add_number, true, mips16_small, |
8512 | mips16_ext, &ip->insn_opcode, | |
8513 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
8514 | imm_expr.X_op = O_absent; |
8515 | imm_reloc = BFD_RELOC_UNUSED; | |
8516 | } | |
8517 | ||
8518 | return; | |
8519 | } | |
8520 | break; | |
8521 | ||
8522 | case ',': | |
8523 | if (*s++ == c) | |
8524 | continue; | |
8525 | s--; | |
8526 | switch (*++args) | |
8527 | { | |
8528 | case 'v': | |
8529 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8530 | continue; | |
8531 | case 'w': | |
8532 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8533 | continue; | |
8534 | } | |
8535 | break; | |
8536 | ||
8537 | case '(': | |
8538 | case ')': | |
8539 | if (*s++ == c) | |
8540 | continue; | |
8541 | break; | |
8542 | ||
8543 | case 'v': | |
8544 | case 'w': | |
8545 | if (s[0] != '$') | |
8546 | { | |
8547 | if (c == 'v') | |
8548 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8549 | else | |
8550 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8551 | ++args; | |
8552 | continue; | |
8553 | } | |
8554 | /* Fall through. */ | |
8555 | case 'x': | |
8556 | case 'y': | |
8557 | case 'z': | |
8558 | case 'Z': | |
8559 | case '0': | |
8560 | case 'S': | |
8561 | case 'R': | |
8562 | case 'X': | |
8563 | case 'Y': | |
8564 | if (s[0] != '$') | |
8565 | break; | |
8566 | s_reset = s; | |
8567 | if (isdigit (s[1])) | |
8568 | { | |
8569 | ++s; | |
8570 | regno = 0; | |
8571 | do | |
8572 | { | |
8573 | regno *= 10; | |
8574 | regno += *s - '0'; | |
8575 | ++s; | |
8576 | } | |
8577 | while (isdigit (*s)); | |
8578 | if (regno > 31) | |
8579 | { | |
48401fcf | 8580 | as_bad (_("invalid register number (%d)"), regno); |
cc5703cd ILT |
8581 | regno = 2; |
8582 | } | |
8583 | } | |
8584 | else | |
8585 | { | |
8586 | if (s[1] == 'f' && s[2] == 'p') | |
8587 | { | |
8588 | s += 3; | |
8589 | regno = FP; | |
8590 | } | |
8591 | else if (s[1] == 's' && s[2] == 'p') | |
8592 | { | |
8593 | s += 3; | |
8594 | regno = SP; | |
8595 | } | |
8596 | else if (s[1] == 'g' && s[2] == 'p') | |
8597 | { | |
8598 | s += 3; | |
8599 | regno = GP; | |
8600 | } | |
8601 | else if (s[1] == 'a' && s[2] == 't') | |
8602 | { | |
8603 | s += 3; | |
8604 | regno = AT; | |
8605 | } | |
8606 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8607 | { | |
8608 | s += 4; | |
8609 | regno = KT0; | |
8610 | } | |
8611 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8612 | { | |
8613 | s += 4; | |
8614 | regno = KT1; | |
8615 | } | |
8616 | else | |
8617 | break; | |
8618 | } | |
8619 | ||
8620 | if (*s == ' ') | |
8621 | ++s; | |
8622 | if (args[1] != *s) | |
8623 | { | |
8624 | if (c == 'v' || c == 'w') | |
8625 | { | |
8626 | regno = mips16_to_32_reg_map[lastregno]; | |
8627 | s = s_reset; | |
8628 | args++; | |
8629 | } | |
8630 | } | |
8631 | ||
8632 | switch (c) | |
8633 | { | |
8634 | case 'x': | |
8635 | case 'y': | |
8636 | case 'z': | |
8637 | case 'v': | |
8638 | case 'w': | |
8639 | case 'Z': | |
8640 | regno = mips32_to_16_reg_map[regno]; | |
8641 | break; | |
8642 | ||
8643 | case '0': | |
8644 | if (regno != 0) | |
8645 | regno = ILLEGAL_REG; | |
8646 | break; | |
8647 | ||
8648 | case 'S': | |
8649 | if (regno != SP) | |
8650 | regno = ILLEGAL_REG; | |
8651 | break; | |
8652 | ||
8653 | case 'R': | |
8654 | if (regno != RA) | |
8655 | regno = ILLEGAL_REG; | |
8656 | break; | |
8657 | ||
8658 | case 'X': | |
8659 | case 'Y': | |
3c83da8a | 8660 | if (regno == AT && ! mips_opts.noat) |
48401fcf | 8661 | as_warn (_("used $at without \".set noat\"")); |
cc5703cd ILT |
8662 | break; |
8663 | ||
8664 | default: | |
8665 | internalError (); | |
8666 | } | |
8667 | ||
8668 | if (regno == ILLEGAL_REG) | |
8669 | break; | |
8670 | ||
8671 | switch (c) | |
8672 | { | |
8673 | case 'x': | |
8674 | case 'v': | |
8675 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8676 | break; | |
8677 | case 'y': | |
8678 | case 'w': | |
8679 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8680 | break; | |
8681 | case 'z': | |
8682 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8683 | break; | |
8684 | case 'Z': | |
8685 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8686 | case '0': | |
8687 | case 'S': | |
8688 | case 'R': | |
8689 | break; | |
8690 | case 'X': | |
8691 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8692 | break; | |
8693 | case 'Y': | |
8694 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8695 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8696 | break; | |
8697 | default: | |
8698 | internalError (); | |
8699 | } | |
8700 | ||
8701 | lastregno = regno; | |
8702 | continue; | |
8703 | ||
8704 | case 'P': | |
8705 | if (strncmp (s, "$pc", 3) == 0) | |
8706 | { | |
8707 | s += 3; | |
8708 | continue; | |
8709 | } | |
8710 | break; | |
8711 | ||
8712 | case '<': | |
8713 | case '>': | |
8714 | case '[': | |
8715 | case ']': | |
8716 | case '4': | |
8717 | case '5': | |
8718 | case 'H': | |
8719 | case 'W': | |
8720 | case 'D': | |
8721 | case 'j': | |
8722 | case '8': | |
8723 | case 'V': | |
8724 | case 'C': | |
8725 | case 'U': | |
8726 | case 'k': | |
8727 | case 'K': | |
16262668 ILT |
8728 | if (s[0] == '%' |
8729 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8730 | { | |
8731 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8732 | and generate the appropriate reloc. If the text | |
8733 | inside %gprel is not a symbol name with an | |
8734 | optional offset, then we generate a normal reloc | |
8735 | and will probably fail later. */ | |
8736 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8737 | if (imm_expr.X_op == O_symbol) | |
8738 | { | |
8739 | mips16_ext = true; | |
8740 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8741 | s = expr_end; | |
8742 | ip->use_extend = true; | |
8743 | ip->extend = 0; | |
8744 | continue; | |
8745 | } | |
8746 | } | |
8747 | else | |
8748 | { | |
8749 | /* Just pick up a normal expression. */ | |
8750 | my_getExpression (&imm_expr, s); | |
8751 | } | |
8752 | ||
ebf28372 ILT |
8753 | if (imm_expr.X_op == O_register) |
8754 | { | |
8755 | /* What we thought was an expression turned out to | |
8756 | be a register. */ | |
8757 | ||
8758 | if (s[0] == '(' && args[1] == '(') | |
8759 | { | |
8760 | /* It looks like the expression was omitted | |
8761 | before a register indirection, which means | |
8762 | that the expression is implicitly zero. We | |
8763 | still set up imm_expr, so that we handle | |
8764 | explicit extensions correctly. */ | |
8765 | imm_expr.X_op = O_constant; | |
8766 | imm_expr.X_add_number = 0; | |
8767 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8768 | continue; | |
8769 | } | |
8770 | ||
8771 | break; | |
8772 | } | |
8773 | ||
cc5703cd ILT |
8774 | /* We need to relax this instruction. */ |
8775 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8776 | s = expr_end; | |
8777 | continue; | |
8778 | ||
8779 | case 'p': | |
8780 | case 'q': | |
8781 | case 'A': | |
8782 | case 'B': | |
8783 | case 'E': | |
8784 | /* We use offset_reloc rather than imm_reloc for the PC | |
8785 | relative operands. This lets macros with both | |
8786 | immediate and address operands work correctly. */ | |
670a50eb | 8787 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8788 | |
8789 | if (offset_expr.X_op == O_register) | |
8790 | break; | |
8791 | ||
cc5703cd ILT |
8792 | /* We need to relax this instruction. */ |
8793 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8794 | s = expr_end; |
8795 | continue; | |
8796 | ||
cc5703cd ILT |
8797 | case '6': /* break code */ |
8798 | my_getExpression (&imm_expr, s); | |
8799 | check_absolute_expr (ip, &imm_expr); | |
8800 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8801 | { |
48401fcf | 8802 | as_warn (_("Invalid value for `%s' (%lu)"), |
cc5703cd ILT |
8803 | ip->insn_mo->name, |
8804 | (unsigned long) imm_expr.X_add_number); | |
8805 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8806 | } |
cc5703cd ILT |
8807 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8808 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8809 | s = expr_end; |
8810 | continue; | |
3d3c5039 | 8811 | |
670a50eb ILT |
8812 | case 'a': /* 26 bit address */ |
8813 | my_getExpression (&offset_expr, s); | |
8814 | s = expr_end; | |
cc5703cd ILT |
8815 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8816 | ip->insn_opcode <<= 16; | |
670a50eb | 8817 | continue; |
3d3c5039 | 8818 | |
cc5703cd ILT |
8819 | case 'l': /* register list for entry macro */ |
8820 | case 'L': /* register list for exit macro */ | |
8821 | { | |
8822 | int mask; | |
8823 | ||
8824 | if (c == 'l') | |
8825 | mask = 0; | |
8826 | else | |
8827 | mask = 7 << 3; | |
8828 | while (*s != '\0') | |
8829 | { | |
c9167640 | 8830 | int freg, reg1, reg2; |
cc5703cd ILT |
8831 | |
8832 | while (*s == ' ' || *s == ',') | |
8833 | ++s; | |
8834 | if (*s != '$') | |
8835 | { | |
48401fcf | 8836 | as_bad (_("can't parse register list")); |
cc5703cd ILT |
8837 | break; |
8838 | } | |
8839 | ++s; | |
c9167640 ILT |
8840 | if (*s != 'f') |
8841 | freg = 0; | |
8842 | else | |
8843 | { | |
8844 | freg = 1; | |
8845 | ++s; | |
8846 | } | |
cc5703cd ILT |
8847 | reg1 = 0; |
8848 | while (isdigit (*s)) | |
8849 | { | |
8850 | reg1 *= 10; | |
8851 | reg1 += *s - '0'; | |
8852 | ++s; | |
8853 | } | |
8854 | if (*s == ' ') | |
8855 | ++s; | |
8856 | if (*s != '-') | |
8857 | reg2 = reg1; | |
8858 | else | |
8859 | { | |
8860 | ++s; | |
8861 | if (*s != '$') | |
8862 | break; | |
8863 | ++s; | |
c9167640 ILT |
8864 | if (freg) |
8865 | { | |
8866 | if (*s == 'f') | |
8867 | ++s; | |
8868 | else | |
8869 | { | |
48401fcf | 8870 | as_bad (_("invalid register list")); |
c9167640 ILT |
8871 | break; |
8872 | } | |
8873 | } | |
cc5703cd ILT |
8874 | reg2 = 0; |
8875 | while (isdigit (*s)) | |
8876 | { | |
8877 | reg2 *= 10; | |
8878 | reg2 += *s - '0'; | |
8879 | ++s; | |
8880 | } | |
8881 | } | |
c9167640 ILT |
8882 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8883 | { | |
8884 | mask &= ~ (7 << 3); | |
8885 | mask |= 5 << 3; | |
8886 | } | |
8887 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8888 | { | |
8889 | mask &= ~ (7 << 3); | |
8890 | mask |= 6 << 3; | |
8891 | } | |
8892 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8893 | mask |= (reg2 - 3) << 3; |
8894 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8895 | mask |= (reg2 - 15) << 1; | |
8896 | else if (reg1 == 31 && reg2 == 31) | |
8897 | mask |= 1; | |
8898 | else | |
c9167640 | 8899 | { |
48401fcf | 8900 | as_bad (_("invalid register list")); |
c9167640 ILT |
8901 | break; |
8902 | } | |
cc5703cd | 8903 | } |
c9167640 ILT |
8904 | /* The mask is filled in in the opcode table for the |
8905 | benefit of the disassembler. We remove it before | |
8906 | applying the actual mask. */ | |
8907 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8908 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8909 | } | |
8910 | continue; | |
d8a1c247 | 8911 | |
56bb6eee ILT |
8912 | case 'e': /* extend code */ |
8913 | my_getExpression (&imm_expr, s); | |
8914 | check_absolute_expr (ip, &imm_expr); | |
8915 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8916 | { | |
48401fcf | 8917 | as_warn (_("Invalid value for `%s' (%lu)"), |
56bb6eee ILT |
8918 | ip->insn_mo->name, |
8919 | (unsigned long) imm_expr.X_add_number); | |
8920 | imm_expr.X_add_number &= 0x7ff; | |
8921 | } | |
8922 | ip->insn_opcode |= imm_expr.X_add_number; | |
8923 | imm_expr.X_op = O_absent; | |
8924 | s = expr_end; | |
8925 | continue; | |
8926 | ||
3d3c5039 | 8927 | default: |
670a50eb | 8928 | internalError (); |
3d3c5039 | 8929 | } |
670a50eb | 8930 | break; |
3d3c5039 | 8931 | } |
cc5703cd | 8932 | |
670a50eb | 8933 | /* Args don't match. */ |
cc5703cd ILT |
8934 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8935 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8936 | { |
8937 | ++insn; | |
cc5703cd | 8938 | s = argsstart; |
670a50eb | 8939 | continue; |
3d3c5039 | 8940 | } |
cc5703cd | 8941 | |
48401fcf | 8942 | insn_error = _("illegal operands"); |
cc5703cd | 8943 | |
670a50eb | 8944 | return; |
3d3c5039 ILT |
8945 | } |
8946 | } | |
8947 | ||
cc5703cd ILT |
8948 | /* This structure holds information we know about a mips16 immediate |
8949 | argument type. */ | |
8950 | ||
8951 | struct mips16_immed_operand | |
8952 | { | |
8953 | /* The type code used in the argument string in the opcode table. */ | |
8954 | int type; | |
8955 | /* The number of bits in the short form of the opcode. */ | |
8956 | int nbits; | |
8957 | /* The number of bits in the extended form of the opcode. */ | |
8958 | int extbits; | |
8959 | /* The amount by which the short form is shifted when it is used; | |
8960 | for example, the sw instruction has a shift count of 2. */ | |
8961 | int shift; | |
8962 | /* The amount by which the short form is shifted when it is stored | |
8963 | into the instruction code. */ | |
8964 | int op_shift; | |
8965 | /* Non-zero if the short form is unsigned. */ | |
8966 | int unsp; | |
8967 | /* Non-zero if the extended form is unsigned. */ | |
8968 | int extu; | |
8969 | /* Non-zero if the value is PC relative. */ | |
8970 | int pcrel; | |
8971 | }; | |
8972 | ||
8973 | /* The mips16 immediate operand types. */ | |
8974 | ||
8975 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8976 | { | |
8977 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8978 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8979 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8980 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8981 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8982 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8983 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8984 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8985 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8986 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8987 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8988 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8989 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8990 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8991 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8992 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8993 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8994 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8995 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8996 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8997 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8998 | }; | |
8999 | ||
9000 | #define MIPS16_NUM_IMMED \ | |
9001 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9002 | ||
9003 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9004 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9005 | whether an extended value is needed; if one is needed, it sets | |
9006 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9007 | If SMALL is true, an unextended opcode was explicitly requested. | |
9008 | If EXT is true, an extended opcode was explicitly requested. If | |
9009 | WARN is true, warn if EXT does not match reality. */ | |
9010 | ||
9011 | static void | |
15e69f98 ILT |
9012 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
9013 | extend) | |
9014 | char *file; | |
9015 | unsigned int line; | |
cc5703cd ILT |
9016 | int type; |
9017 | offsetT val; | |
9018 | boolean warn; | |
9019 | boolean small; | |
9020 | boolean ext; | |
9021 | unsigned long *insn; | |
9022 | boolean *use_extend; | |
9023 | unsigned short *extend; | |
9024 | { | |
9025 | register const struct mips16_immed_operand *op; | |
9026 | int mintiny, maxtiny; | |
9027 | boolean needext; | |
9028 | ||
9029 | op = mips16_immed_operands; | |
9030 | while (op->type != type) | |
9031 | { | |
9032 | ++op; | |
9033 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9034 | } | |
9035 | ||
9036 | if (op->unsp) | |
9037 | { | |
9038 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9039 | { | |
9040 | mintiny = 1; | |
9041 | maxtiny = 1 << op->nbits; | |
9042 | } | |
9043 | else | |
9044 | { | |
9045 | mintiny = 0; | |
9046 | maxtiny = (1 << op->nbits) - 1; | |
9047 | } | |
9048 | } | |
9049 | else | |
9050 | { | |
9051 | mintiny = - (1 << (op->nbits - 1)); | |
9052 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9053 | } | |
9054 | ||
9055 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9056 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 9057 | val /= 2; |
cc5703cd ILT |
9058 | |
9059 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9060 | || val < (mintiny << op->shift) | |
9061 | || val > (maxtiny << op->shift)) | |
9062 | needext = true; | |
9063 | else | |
9064 | needext = false; | |
9065 | ||
9066 | if (warn && ext && ! needext) | |
48401fcf | 9067 | as_warn_where (file, line, _("extended operand requested but not required")); |
8728fa92 | 9068 | if (small && needext) |
48401fcf | 9069 | as_bad_where (file, line, _("invalid unextended operand value")); |
cc5703cd ILT |
9070 | |
9071 | if (small || (! ext && ! needext)) | |
9072 | { | |
9073 | int insnval; | |
9074 | ||
9075 | *use_extend = false; | |
9076 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9077 | insnval <<= op->op_shift; | |
9078 | *insn |= insnval; | |
9079 | } | |
9080 | else | |
9081 | { | |
9082 | long minext, maxext; | |
9083 | int extval; | |
9084 | ||
9085 | if (op->extu) | |
9086 | { | |
9087 | minext = 0; | |
9088 | maxext = (1 << op->extbits) - 1; | |
9089 | } | |
9090 | else | |
9091 | { | |
9092 | minext = - (1 << (op->extbits - 1)); | |
9093 | maxext = (1 << (op->extbits - 1)) - 1; | |
9094 | } | |
9095 | if (val < minext || val > maxext) | |
15e69f98 | 9096 | as_bad_where (file, line, |
48401fcf | 9097 | _("operand value out of range for instruction")); |
cc5703cd ILT |
9098 | |
9099 | *use_extend = true; | |
9100 | if (op->extbits == 16) | |
9101 | { | |
9102 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9103 | val &= 0x1f; | |
9104 | } | |
9105 | else if (op->extbits == 15) | |
9106 | { | |
9107 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9108 | val &= 0xf; | |
9109 | } | |
9110 | else | |
9111 | { | |
9112 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9113 | val = 0; | |
9114 | } | |
9115 | ||
9116 | *extend = (unsigned short) extval; | |
9117 | *insn |= val; | |
9118 | } | |
9119 | } | |
9120 | \f | |
3d3c5039 ILT |
9121 | #define LP '(' |
9122 | #define RP ')' | |
9123 | ||
9124 | static int | |
9125 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
9126 | expressionS *ep; |
9127 | char *str; | |
3d3c5039 | 9128 | { |
670a50eb ILT |
9129 | char *sp; |
9130 | int c = 0; | |
9131 | ||
9132 | if (*str == ' ') | |
9133 | str++; | |
9134 | if (*str == LP | |
9135 | || (*str == '%' && | |
9136 | ((str[1] == 'h' && str[2] == 'i') | |
9137 | || (str[1] == 'H' && str[2] == 'I') | |
9138 | || (str[1] == 'l' && str[2] == 'o')) | |
9139 | && str[3] == LP)) | |
9140 | { | |
9141 | if (*str == LP) | |
9142 | c = 0; | |
9143 | else | |
9144 | { | |
9145 | c = str[1]; | |
9146 | str += 3; | |
9147 | } | |
9148 | ||
9149 | /* | |
9150 | * A small expression may be followed by a base register. | |
9151 | * Scan to the end of this operand, and then back over a possible | |
9152 | * base register. Then scan the small expression up to that | |
9153 | * point. (Based on code in sparc.c...) | |
9154 | */ | |
9155 | for (sp = str; *sp && *sp != ','; sp++) | |
9156 | ; | |
9157 | if (sp - 4 >= str && sp[-1] == RP) | |
9158 | { | |
9159 | if (isdigit (sp[-2])) | |
9160 | { | |
9161 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
9162 | ; | |
9163 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
9164 | { | |
9165 | sp--; | |
9166 | goto do_it; | |
3d3c5039 | 9167 | } |
670a50eb ILT |
9168 | } |
9169 | else if (sp - 5 >= str | |
9170 | && sp[-5] == LP | |
9171 | && sp[-4] == '$' | |
9172 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
9173 | || (sp[-3] == 's' && sp[-2] == 'p') | |
9174 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
9175 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
9176 | { | |
9177 | sp -= 5; | |
3d3c5039 | 9178 | do_it: |
670a50eb ILT |
9179 | if (sp == str) |
9180 | { | |
9181 | /* no expression means zero offset */ | |
9182 | if (c) | |
9183 | { | |
9184 | /* %xx(reg) is an error */ | |
5ac34ac3 | 9185 | ep->X_op = O_absent; |
670a50eb | 9186 | expr_end = str - 3; |
3d3c5039 | 9187 | } |
670a50eb ILT |
9188 | else |
9189 | { | |
52aa70b5 | 9190 | ep->X_op = O_constant; |
670a50eb ILT |
9191 | expr_end = sp; |
9192 | } | |
9193 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 9194 | ep->X_op_symbol = NULL; |
670a50eb ILT |
9195 | ep->X_add_number = 0; |
9196 | } | |
9197 | else | |
9198 | { | |
9199 | *sp = '\0'; | |
9200 | my_getExpression (ep, str); | |
9201 | *sp = LP; | |
3d3c5039 | 9202 | } |
670a50eb | 9203 | return c; |
3d3c5039 ILT |
9204 | } |
9205 | } | |
9206 | } | |
670a50eb ILT |
9207 | my_getExpression (ep, str); |
9208 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
9209 | } |
9210 | ||
9211 | static void | |
9212 | my_getExpression (ep, str) | |
670a50eb ILT |
9213 | expressionS *ep; |
9214 | char *str; | |
3d3c5039 | 9215 | { |
670a50eb | 9216 | char *save_in; |
670a50eb ILT |
9217 | |
9218 | save_in = input_line_pointer; | |
9219 | input_line_pointer = str; | |
5ac34ac3 | 9220 | expression (ep); |
670a50eb ILT |
9221 | expr_end = input_line_pointer; |
9222 | input_line_pointer = save_in; | |
eb17f56c ILT |
9223 | |
9224 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9225 | then we bump the value of the symbol by 1 since that is how other | |
9226 | text symbols are handled. We don't bother to handle complex | |
9227 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 9228 | if (mips_opts.mips16 |
eb17f56c ILT |
9229 | && ep->X_op == O_symbol |
9230 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9231 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
9232 | && ep->X_add_symbol->sy_frag == frag_now | |
9233 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
9234 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
9235 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
9236 | } |
9237 | ||
becfe05e ILT |
9238 | /* Turn a string in input_line_pointer into a floating point constant |
9239 | of type type, and store the appropriate bytes in *litP. The number | |
9240 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
9241 | returned, or NULL on OK. */ | |
9242 | ||
3d3c5039 | 9243 | char * |
670a50eb | 9244 | md_atof (type, litP, sizeP) |
becfe05e | 9245 | int type; |
3d3c5039 ILT |
9246 | char *litP; |
9247 | int *sizeP; | |
9248 | { | |
becfe05e ILT |
9249 | int prec; |
9250 | LITTLENUM_TYPE words[4]; | |
9251 | char *t; | |
9252 | int i; | |
9253 | ||
9254 | switch (type) | |
9255 | { | |
9256 | case 'f': | |
9257 | prec = 2; | |
9258 | break; | |
9259 | ||
9260 | case 'd': | |
9261 | prec = 4; | |
9262 | break; | |
9263 | ||
9264 | default: | |
9265 | *sizeP = 0; | |
48401fcf | 9266 | return _("bad call to md_atof"); |
becfe05e ILT |
9267 | } |
9268 | ||
9269 | t = atof_ieee (input_line_pointer, type, words); | |
9270 | if (t) | |
9271 | input_line_pointer = t; | |
9272 | ||
9273 | *sizeP = prec * 2; | |
9274 | ||
b9129c6f | 9275 | if (! target_big_endian) |
becfe05e ILT |
9276 | { |
9277 | for (i = prec - 1; i >= 0; i--) | |
9278 | { | |
9279 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9280 | litP += 2; | |
9281 | } | |
9282 | } | |
9283 | else | |
9284 | { | |
9285 | for (i = 0; i < prec; i++) | |
9286 | { | |
9287 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9288 | litP += 2; | |
9289 | } | |
9290 | } | |
9291 | ||
670a50eb | 9292 | return NULL; |
3d3c5039 ILT |
9293 | } |
9294 | ||
9295 | void | |
9296 | md_number_to_chars (buf, val, n) | |
9297 | char *buf; | |
918692a5 | 9298 | valueT val; |
3d3c5039 ILT |
9299 | int n; |
9300 | { | |
b9129c6f ILT |
9301 | if (target_big_endian) |
9302 | number_to_chars_bigendian (buf, val, n); | |
9303 | else | |
9304 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 9305 | } |
f3d817d8 | 9306 | \f |
e8d4d475 | 9307 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 9308 | |
f3d817d8 DM |
9309 | struct option md_longopts[] = { |
9310 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
9311 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9312 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9313 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9314 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9315 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9316 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
9317 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
9318 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
9319 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 9320 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 9321 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 9322 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 9323 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
9324 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9325 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 9326 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
9327 | {"break", no_argument, NULL, OPTION_BREAK}, |
9328 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 9329 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 9330 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 9331 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 9332 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 9333 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 9334 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 9335 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 9336 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
9337 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
9338 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9339 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
9340 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
9341 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
9342 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9343 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
9344 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 9345 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 9346 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 9347 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 9348 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 9349 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
9350 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
9351 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
9352 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
9353 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 9354 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
9355 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
9356 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9357 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
9358 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
9359 | |
9360 | /* start-sanitize-tx19 */ | |
9361 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
9362 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
9363 | /* end-sanitize-tx19 */ | |
f3d817d8 | 9364 | |
6b34ac5a | 9365 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9366 | #define OPTION_M5400 (OPTION_MD_BASE + 28) |
9367 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
9368 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
9369 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
9370 | ||
6b34ac5a | 9371 | /* end-sanitize-cygnus */ |
42444087 GRK |
9372 | /* start-sanitize-tx49 */ |
9373 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
9374 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
9375 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
9376 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
9377 | ||
9378 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
9379 | /* start-sanitize-vr4320 */ |
9380 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
9381 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
9382 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
9383 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
9384 | ||
9385 | /* end-sanitize-vr4320 */ | |
7e656649 RH |
9386 | /* start-sanitize-branchbug4011 */ |
9387 | #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34) | |
9388 | {"fix-4011-branch-bug", no_argument, NULL, OPTION_FIX_4011_BRANCH_BUG}, | |
9389 | #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35) | |
9390 | {"no-fix-4011-branch-bug", no_argument, NULL, OPTION_NO_FIX_4011_BRANCH_BUG}, | |
9391 | /* end-sanitize-branchbug4011 */ | |
d8a1c247 | 9392 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 9393 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 9394 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
9395 | #define OPTION_32 (OPTION_MD_BASE + 20) |
9396 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 9397 | #ifdef OBJ_ELF |
f3d817d8 | 9398 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 9399 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 9400 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 9401 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
9402 | {"32", no_argument, NULL, OPTION_32}, |
9403 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
9404 | #endif |
9405 | ||
9406 | {NULL, no_argument, NULL, 0} | |
9407 | }; | |
9408 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
9409 | |
9410 | int | |
f3d817d8 DM |
9411 | md_parse_option (c, arg) |
9412 | int c; | |
9413 | char *arg; | |
3d3c5039 | 9414 | { |
f3d817d8 | 9415 | switch (c) |
670a50eb | 9416 | { |
f3d817d8 DM |
9417 | case OPTION_TRAP: |
9418 | mips_trap = 1; | |
9419 | break; | |
670a50eb | 9420 | |
f3d817d8 DM |
9421 | case OPTION_BREAK: |
9422 | mips_trap = 0; | |
9423 | break; | |
9424 | ||
e8d4d475 | 9425 | case OPTION_EB: |
1dc1e798 | 9426 | target_big_endian = 1; |
e8d4d475 | 9427 | break; |
04cb3372 | 9428 | |
e8d4d475 | 9429 | case OPTION_EL: |
1dc1e798 | 9430 | target_big_endian = 0; |
f3d817d8 | 9431 | break; |
670a50eb | 9432 | |
f3d817d8 DM |
9433 | case 'O': |
9434 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
9435 | mips_optimize = 1; |
9436 | else | |
9437 | mips_optimize = 2; | |
f3d817d8 | 9438 | break; |
0aa07269 | 9439 | |
f3d817d8 | 9440 | case 'g': |
22ba90ce ILT |
9441 | if (arg == NULL) |
9442 | mips_debug = 2; | |
9443 | else | |
9444 | mips_debug = atoi (arg); | |
9445 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9446 | optimizations which limit full symbolic debugging. We take | |
9447 | that to be equivalent to -O0. */ | |
9448 | if (mips_debug == 2) | |
05874c2e | 9449 | mips_optimize = 1; |
f3d817d8 | 9450 | break; |
4e95866e | 9451 | |
f3d817d8 | 9452 | case OPTION_MIPS1: |
3c83da8a | 9453 | mips_opts.isa = 1; |
f3d817d8 | 9454 | break; |
8358c818 | 9455 | |
f3d817d8 | 9456 | case OPTION_MIPS2: |
3c83da8a | 9457 | mips_opts.isa = 2; |
f3d817d8 | 9458 | break; |
8358c818 | 9459 | |
f3d817d8 | 9460 | case OPTION_MIPS3: |
3c83da8a | 9461 | mips_opts.isa = 3; |
f3d817d8 | 9462 | break; |
8358c818 | 9463 | |
d8a1c247 | 9464 | case OPTION_MIPS4: |
3c83da8a | 9465 | mips_opts.isa = 4; |
d8a1c247 KR |
9466 | break; |
9467 | ||
f3d817d8 DM |
9468 | case OPTION_MCPU: |
9469 | { | |
9470 | char *p; | |
9471 | ||
9472 | /* Identify the processor type */ | |
9473 | p = arg; | |
9474 | if (strcmp (p, "default") == 0 | |
9475 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 9476 | mips_cpu = -1; |
f3d817d8 DM |
9477 | else |
9478 | { | |
c625fc23 JSC |
9479 | int sv = 0; |
9480 | ||
9481 | /* We need to cope with the various "vr" prefixes for the 4300 | |
9482 | processor. */ | |
9483 | if (*p == 'v' || *p == 'V') | |
9484 | { | |
9485 | sv = 1; | |
9486 | p++; | |
9487 | } | |
9488 | ||
f3d817d8 DM |
9489 | if (*p == 'r' || *p == 'R') |
9490 | p++; | |
8358c818 | 9491 | |
4bb0cc41 | 9492 | mips_cpu = -1; |
f3d817d8 DM |
9493 | switch (*p) |
9494 | { | |
d8a1c247 KR |
9495 | case '1': |
9496 | if (strcmp (p, "10000") == 0 | |
9497 | || strcmp (p, "10k") == 0 | |
9498 | || strcmp (p, "10K") == 0) | |
9499 | mips_cpu = 10000; | |
4e96260f JL |
9500 | /* start-sanitize-tx19 */ |
9501 | else if (strcmp (p, "1900") == 0) | |
9502 | mips_cpu = 3900; | |
9503 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
9504 | break; |
9505 | ||
f3d817d8 DM |
9506 | case '2': |
9507 | if (strcmp (p, "2000") == 0 | |
9508 | || strcmp (p, "2k") == 0 | |
9509 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 9510 | mips_cpu = 2000; |
f3d817d8 | 9511 | break; |
8358c818 | 9512 | |
f3d817d8 DM |
9513 | case '3': |
9514 | if (strcmp (p, "3000") == 0 | |
9515 | || strcmp (p, "3k") == 0 | |
9516 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 9517 | mips_cpu = 3000; |
5c6f5923 GRK |
9518 | else if (strcmp (p, "3900") == 0) |
9519 | mips_cpu = 3900; | |
f3d817d8 | 9520 | break; |
8358c818 | 9521 | |
f3d817d8 DM |
9522 | case '4': |
9523 | if (strcmp (p, "4000") == 0 | |
9524 | || strcmp (p, "4k") == 0 | |
8c63448a | 9525 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 9526 | mips_cpu = 4000; |
c625fc23 | 9527 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 9528 | mips_cpu = 4100; |
c625fc23 JSC |
9529 | else if (strcmp (p, "4300") == 0) |
9530 | mips_cpu = 4300; | |
2d035a50 GRK |
9531 | /* start-sanitize-vr4320 */ |
9532 | else if (strcmp (p, "4320") == 0) | |
9533 | mips_cpu = 4320; | |
9534 | /* end-sanitize-vr4320 */ | |
8c63448a | 9535 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 9536 | mips_cpu = 4400; |
8c63448a | 9537 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 9538 | mips_cpu = 4600; |
b2b8c24e | 9539 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 9540 | mips_cpu = 4650; |
4ebda395 GRK |
9541 | /* start-sanitize-tx49 */ |
9542 | else if (strcmp (p, "4900") == 0) | |
9543 | mips_cpu = 4900; | |
9544 | /* end-sanitize-tx49 */ | |
e532b44c | 9545 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9546 | mips_cpu = 4010; |
f3d817d8 | 9547 | break; |
8358c818 | 9548 | |
517078c1 ILT |
9549 | case '5': |
9550 | if (strcmp (p, "5000") == 0 | |
9551 | || strcmp (p, "5k") == 0 | |
9552 | || strcmp (p, "5K") == 0) | |
9553 | mips_cpu = 5000; | |
6b34ac5a | 9554 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9555 | else if (strcmp (p, "5400") == 0) |
9556 | mips_cpu = 5400; | |
6b34ac5a | 9557 | /* end-sanitize-cygnus */ |
276c2d7d GRK |
9558 | /* start-sanitize-r5900 */ |
9559 | else if (strcmp (p, "5900") == 0) | |
9560 | mips_cpu = 5900; | |
9561 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9562 | break; |
9563 | ||
f3d817d8 DM |
9564 | case '6': |
9565 | if (strcmp (p, "6000") == 0 | |
9566 | || strcmp (p, "6k") == 0 | |
9567 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9568 | mips_cpu = 6000; |
f3d817d8 | 9569 | break; |
55933a58 | 9570 | |
d8a1c247 KR |
9571 | case '8': |
9572 | if (strcmp (p, "8000") == 0 | |
9573 | || strcmp (p, "8k") == 0 | |
9574 | || strcmp (p, "8K") == 0) | |
9575 | mips_cpu = 8000; | |
9576 | break; | |
9577 | ||
55933a58 ILT |
9578 | case 'o': |
9579 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9580 | mips_cpu = 4600; |
55933a58 | 9581 | break; |
f3d817d8 | 9582 | } |
8358c818 | 9583 | |
b3ed1af3 KR |
9584 | if (sv |
9585 | && (mips_cpu != 4300 | |
9586 | && mips_cpu != 4100 | |
2d035a50 GRK |
9587 | /* start-sanitize-vr4320 */ |
9588 | && mips_cpu != 4320 | |
9589 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9590 | /* start-sanitize-cygnus */ |
b3ed1af3 | 9591 | && mips_cpu != 5400 |
6b34ac5a | 9592 | /* end-sanitize-cygnus */ |
b3ed1af3 | 9593 | && mips_cpu != 5000)) |
c625fc23 | 9594 | { |
48401fcf | 9595 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); |
c625fc23 JSC |
9596 | return 0; |
9597 | } | |
9598 | ||
4bb0cc41 | 9599 | if (mips_cpu == -1) |
f3d817d8 | 9600 | { |
48401fcf | 9601 | as_bad (_("invalid architecture -mcpu=%s"), arg); |
f3d817d8 DM |
9602 | return 0; |
9603 | } | |
9604 | } | |
9605 | } | |
9606 | break; | |
8358c818 | 9607 | |
b2b8c24e ILT |
9608 | case OPTION_M4650: |
9609 | mips_4650 = 1; | |
9610 | break; | |
9611 | ||
9612 | case OPTION_NO_M4650: | |
9613 | mips_4650 = 0; | |
9614 | break; | |
9615 | ||
e532b44c ILT |
9616 | case OPTION_M4010: |
9617 | mips_4010 = 1; | |
9618 | break; | |
9619 | ||
9620 | case OPTION_NO_M4010: | |
9621 | mips_4010 = 0; | |
9622 | break; | |
9623 | ||
c625fc23 JSC |
9624 | case OPTION_M4100: |
9625 | mips_4100 = 1; | |
9626 | break; | |
9627 | ||
9628 | case OPTION_NO_M4100: | |
9629 | mips_4100 = 0; | |
9630 | break; | |
9631 | ||
276c2d7d GRK |
9632 | /* start-sanitize-r5900 */ |
9633 | case OPTION_M5900: | |
9634 | mips_5900 = 1; | |
9635 | break; | |
9636 | ||
9637 | case OPTION_NO_M5900: | |
9638 | mips_5900 = 0; | |
9639 | break; | |
9640 | /* end-sanitize-r5900 */ | |
9641 | ||
2d035a50 GRK |
9642 | /* start-sanitize-vr4320 */ |
9643 | case OPTION_M4320: | |
9644 | mips_4320 = 1; | |
9645 | break; | |
9646 | ||
9647 | case OPTION_NO_M4320: | |
9648 | mips_4320 = 0; | |
9649 | break; | |
9650 | ||
9651 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9652 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9653 | case OPTION_M5400: |
9654 | mips_5400 = 1; | |
9655 | break; | |
9656 | ||
9657 | case OPTION_NO_M5400: | |
9658 | mips_5400 = 0; | |
9659 | break; | |
9660 | ||
6b34ac5a | 9661 | /* end-sanitize-cygnus */ |
5c6f5923 GRK |
9662 | case OPTION_M3900: |
9663 | mips_3900 = 1; | |
9664 | break; | |
9665 | ||
9666 | case OPTION_NO_M3900: | |
9667 | mips_3900 = 0; | |
9668 | break; | |
9669 | ||
42444087 GRK |
9670 | /* start-sanitize-tx49 */ |
9671 | case OPTION_M4900: | |
9672 | mips_4900 = 1; | |
9673 | break; | |
9674 | ||
9675 | case OPTION_NO_M4900: | |
9676 | mips_4900 = 0; | |
9677 | break; | |
9678 | ||
9679 | /* end-sanitize-tx49 */ | |
cc5703cd | 9680 | case OPTION_MIPS16: |
3c83da8a | 9681 | mips_opts.mips16 = 1; |
4a1cb507 | 9682 | mips_no_prev_insn (false); |
cc5703cd ILT |
9683 | break; |
9684 | ||
9685 | case OPTION_NO_MIPS16: | |
3c83da8a | 9686 | mips_opts.mips16 = 0; |
4a1cb507 | 9687 | mips_no_prev_insn (false); |
cc5703cd ILT |
9688 | break; |
9689 | ||
f3d817d8 | 9690 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9691 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9692 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 | 9693 | { |
48401fcf | 9694 | as_bad (_("-G may not be used with embedded PIC code")); |
f3d817d8 DM |
9695 | return 0; |
9696 | } | |
5b63f465 | 9697 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9698 | break; |
d9aba805 | 9699 | |
fb251650 ILT |
9700 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9701 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9702 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9703 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9704 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9705 | { | |
48401fcf | 9706 | as_bad (_("-call_shared is supported only for ELF format")); |
1dc1e798 KR |
9707 | return 0; |
9708 | } | |
d9aba805 ILT |
9709 | mips_pic = SVR4_PIC; |
9710 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 | 9711 | { |
48401fcf | 9712 | as_bad (_("-G may not be used with SVR4 PIC code")); |
f3d817d8 DM |
9713 | return 0; |
9714 | } | |
d9aba805 | 9715 | g_switch_value = 0; |
f3d817d8 DM |
9716 | break; |
9717 | ||
9718 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9719 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9720 | { | |
48401fcf | 9721 | as_bad (_("-non_shared is supported only for ELF format")); |
1dc1e798 KR |
9722 | return 0; |
9723 | } | |
d9aba805 | 9724 | mips_pic = NO_PIC; |
f3d817d8 | 9725 | break; |
8358c818 | 9726 | |
fb251650 ILT |
9727 | /* The -xgot option tells the assembler to use 32 offsets when |
9728 | accessing the got in SVR4_PIC mode. It is for Irix | |
9729 | compatibility. */ | |
9730 | case OPTION_XGOT: | |
9731 | mips_big_got = 1; | |
9732 | break; | |
9733 | ||
f3d817d8 | 9734 | case 'G': |
1dc1e798 KR |
9735 | if (! USE_GLOBAL_POINTER_OPT) |
9736 | { | |
48401fcf | 9737 | as_bad (_("-G is not supported for this configuration")); |
1dc1e798 KR |
9738 | return 0; |
9739 | } | |
9740 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9741 | { |
48401fcf | 9742 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
f3d817d8 | 9743 | return 0; |
670a50eb ILT |
9744 | } |
9745 | else | |
f3d817d8 | 9746 | g_switch_value = atoi (arg); |
42562568 | 9747 | g_switch_seen = 1; |
f3d817d8 | 9748 | break; |
4e95866e | 9749 | |
7f9880e5 ILT |
9750 | /* The -32 and -64 options tell the assembler to output the 32 |
9751 | bit or the 64 bit MIPS ELF format. */ | |
9752 | case OPTION_32: | |
9753 | mips_64 = 0; | |
9754 | break; | |
9755 | ||
9756 | case OPTION_64: | |
9c44af60 ILT |
9757 | { |
9758 | const char **list, **l; | |
9759 | ||
9760 | list = bfd_target_list (); | |
9761 | for (l = list; *l != NULL; l++) | |
9762 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9763 | || strcmp (*l, "elf64-littlemips") == 0) | |
9764 | break; | |
9765 | if (*l == NULL) | |
48401fcf | 9766 | as_fatal (_("No compiled in support for 64 bit object file format")); |
9c44af60 ILT |
9767 | free (list); |
9768 | mips_64 = 1; | |
9769 | } | |
7f9880e5 ILT |
9770 | break; |
9771 | ||
7e656649 RH |
9772 | /* start-sanitize-branchbug4011 */ |
9773 | case OPTION_FIX_4011_BRANCH_BUG: | |
9774 | mips_fix_4011_branch_bug = 1; | |
9775 | break; | |
9776 | ||
9777 | case OPTION_NO_FIX_4011_BRANCH_BUG: | |
9778 | mips_fix_4011_branch_bug = 0; | |
9779 | break; | |
9780 | ||
9781 | /* end-sanitize-branchbug4011 */ | |
f3d817d8 DM |
9782 | default: |
9783 | return 0; | |
8ea7f4e8 ILT |
9784 | } |
9785 | ||
f3d817d8 | 9786 | return 1; |
8ea7f4e8 ILT |
9787 | } |
9788 | ||
f3d817d8 DM |
9789 | void |
9790 | md_show_usage (stream) | |
9791 | FILE *stream; | |
9792 | { | |
48401fcf | 9793 | fprintf(stream, _("\ |
f3d817d8 DM |
9794 | MIPS options:\n\ |
9795 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9796 | -EB generate big endian output\n\ |
9797 | -EL generate little endian output\n\ | |
9798 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9799 | -G NUM allow referencing objects up to NUM bytes\n\ | |
48401fcf TT |
9800 | implicitly with the gp register [default 8]\n")); |
9801 | fprintf(stream, _("\ | |
31493cdf ILT |
9802 | -mips1 generate MIPS ISA I instructions\n\ |
9803 | -mips2 generate MIPS ISA II instructions\n\ | |
9804 | -mips3 generate MIPS ISA III instructions\n\ | |
9805 | -mips4 generate MIPS ISA IV instructions\n\ | |
c625fc23 | 9806 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9807 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9808 | -m4650 permit R4650 instructions\n\ |
9809 | -no-m4650 do not permit R4650 instructions\n\ | |
9810 | -m4010 permit R4010 instructions\n\ | |
9811 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 | 9812 | -m4100 permit VR4100 instructions\n\ |
48401fcf TT |
9813 | -no-m4100 do not permit VR4100 instructions\n")); |
9814 | fprintf(stream, _("\ | |
cc5703cd | 9815 | -mips16 generate mips16 instructions\n\ |
48401fcf TT |
9816 | -no-mips16 do not generate mips16 instructions\n")); |
9817 | fprintf(stream, _("\ | |
f3d817d8 DM |
9818 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9819 | -O remove unneeded NOPs and swap branches\n\ | |
9820 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
48401fcf | 9821 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
f3d817d8 | 9822 | #ifdef OBJ_ELF |
48401fcf | 9823 | fprintf(stream, _("\ |
f3d817d8 | 9824 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
fb251650 | 9825 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9826 | -xgot assume a 32 bit GOT\n\ |
9827 | -32 create 32 bit object file (default)\n\ | |
48401fcf | 9828 | -64 create 64 bit object file\n")); |
f3d817d8 DM |
9829 | #endif |
9830 | } | |
9831 | \f | |
efec4a28 DP |
9832 | void |
9833 | mips_init_after_args () | |
9834 | { | |
af942793 SS |
9835 | /* initialize opcodes */ |
9836 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9837 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9838 | } |
9839 | ||
3d3c5039 ILT |
9840 | long |
9841 | md_pcrel_from (fixP) | |
9842 | fixS *fixP; | |
9843 | { | |
1dc1e798 KR |
9844 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9845 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9846 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9847 | { | |
9848 | /* This makes a branch to an undefined symbol be a branch to the | |
9849 | current location. */ | |
9850 | return 4; | |
9851 | } | |
5b63f465 | 9852 | |
670a50eb ILT |
9853 | /* return the address of the delay slot */ |
9854 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9855 | } |
9856 | ||
abdad6bc ILT |
9857 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9858 | reloc for a cons. We could use the definition there, except that | |
9859 | we want to handle 64 bit relocs specially. */ | |
9860 | ||
9861 | void | |
9862 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9863 | fragS *frag; | |
9864 | int where; | |
9865 | unsigned int nbytes; | |
9866 | expressionS *exp; | |
9867 | { | |
bf39474f | 9868 | #ifndef OBJ_ELF |
abdad6bc | 9869 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9870 | 4 byte reloc. */ |
9871 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9872 | { |
b9129c6f | 9873 | if (target_big_endian) |
abdad6bc ILT |
9874 | where += 4; |
9875 | nbytes = 4; | |
9876 | } | |
bf39474f | 9877 | #endif |
abdad6bc | 9878 | |
7f9880e5 | 9879 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
48401fcf | 9880 | as_bad (_("Unsupported reloc size %d"), nbytes); |
abdad6bc ILT |
9881 | |
9882 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9883 | (nbytes == 2 |
9884 | ? BFD_RELOC_16 | |
9885 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9886 | } |
9887 | ||
23604921 ILT |
9888 | /* This is called before the symbol table is processed. In order to |
9889 | work with gcc when using mips-tfile, we must keep all local labels. | |
9890 | However, in other cases, we want to discard them. If we were | |
9891 | called with -g, but we didn't see any debugging information, it may | |
9892 | mean that gcc is smuggling debugging information through to | |
9893 | mips-tfile, in which case we must generate all local labels. */ | |
9894 | ||
9895 | void | |
9896 | mips_frob_file_before_adjust () | |
9897 | { | |
9898 | #ifndef NO_ECOFF_DEBUGGING | |
9899 | if (ECOFF_DEBUGGING | |
9900 | && mips_debug != 0 | |
9901 | && ! ecoff_debugging_seen) | |
9902 | flag_keep_locals = 1; | |
9903 | #endif | |
9904 | } | |
9905 | ||
867a58b3 ILT |
9906 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9907 | the corresponding LO reloc. This is called before md_apply_fix and | |
9908 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9909 | explicit use of the %hi modifier. */ | |
9910 | ||
9911 | void | |
9912 | mips_frob_file () | |
9913 | { | |
9914 | struct mips_hi_fixup *l; | |
9915 | ||
9916 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9917 | { | |
9918 | segment_info_type *seginfo; | |
9b61d62b | 9919 | int pass; |
867a58b3 ILT |
9920 | |
9921 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9922 | ||
9923 | /* Check quickly whether the next fixup happens to be a matching | |
9924 | %lo. */ | |
9925 | if (l->fixp->fx_next != NULL | |
9926 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9927 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9928 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9929 | continue; | |
9930 | ||
9931 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9932 | When we find one, move the %hi just in front of it. We do |
9933 | this in two passes. In the first pass, we try to find a | |
9934 | unique %lo. In the second pass, we permit multiple %hi | |
9935 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9936 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9937 | for (pass = 0; pass < 2; pass++) |
9938 | { | |
9939 | fixS *f, *prev; | |
9940 | ||
9941 | prev = NULL; | |
9942 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9943 | { |
9b61d62b ILT |
9944 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9945 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9946 | && f->fx_addsy == l->fixp->fx_addsy | |
9947 | && f->fx_offset == l->fixp->fx_offset | |
9948 | && (pass == 1 | |
9949 | || prev == NULL | |
9950 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9951 | || prev->fx_addsy != f->fx_addsy | |
9952 | || prev->fx_offset != f->fx_offset)) | |
9953 | { | |
9954 | fixS **pf; | |
867a58b3 | 9955 | |
9b61d62b ILT |
9956 | /* Move l->fixp before f. */ |
9957 | for (pf = &seginfo->fix_root; | |
9958 | *pf != l->fixp; | |
9959 | pf = &(*pf)->fx_next) | |
9960 | assert (*pf != NULL); | |
867a58b3 | 9961 | |
9b61d62b | 9962 | *pf = l->fixp->fx_next; |
867a58b3 | 9963 | |
9b61d62b ILT |
9964 | l->fixp->fx_next = f; |
9965 | if (prev == NULL) | |
9966 | seginfo->fix_root = l->fixp; | |
9967 | else | |
9968 | prev->fx_next = l->fixp; | |
867a58b3 | 9969 | |
9b61d62b ILT |
9970 | break; |
9971 | } | |
9972 | ||
9973 | prev = f; | |
867a58b3 ILT |
9974 | } |
9975 | ||
9b61d62b ILT |
9976 | if (f != NULL) |
9977 | break; | |
867a58b3 | 9978 | |
9b61d62b ILT |
9979 | if (pass == 1) |
9980 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
48401fcf | 9981 | _("Unmatched %%hi reloc")); |
9b61d62b | 9982 | } |
867a58b3 ILT |
9983 | } |
9984 | } | |
9985 | ||
1c803e52 ILT |
9986 | /* When generating embedded PIC code we need to use a special |
9987 | relocation to represent the difference of two symbols in the .text | |
9988 | section (switch tables use a difference of this sort). See | |
9989 | include/coff/mips.h for details. This macro checks whether this | |
9990 | fixup requires the special reloc. */ | |
9991 | #define SWITCH_TABLE(fixp) \ | |
9992 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9993 | && (fixp)->fx_addsy != NULL \ | |
9994 | && (fixp)->fx_subsy != NULL \ | |
9995 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9996 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9997 | ||
5b63f465 | 9998 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
9999 | relocations, in case the linker has to relax a call. We also need |
10000 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
10001 | |
10002 | /*ARGSUSED*/ | |
10003 | int | |
10004 | mips_force_relocation (fixp) | |
10005 | fixS *fixp; | |
10006 | { | |
7e656649 RH |
10007 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10008 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10009 | return 1; | |
10010 | ||
1c803e52 | 10011 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
10012 | && (fixp->fx_pcrel |
10013 | || SWITCH_TABLE (fixp) | |
10014 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10015 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
10016 | } |
10017 | ||
10018 | /* Apply a fixup to the object file. */ | |
10019 | ||
3d3c5039 ILT |
10020 | int |
10021 | md_apply_fix (fixP, valueP) | |
10022 | fixS *fixP; | |
918692a5 | 10023 | valueT *valueP; |
3d3c5039 | 10024 | { |
670a50eb ILT |
10025 | unsigned char *buf; |
10026 | long insn, value; | |
3d3c5039 | 10027 | |
bf39474f ILT |
10028 | assert (fixP->fx_size == 4 |
10029 | || fixP->fx_r_type == BFD_RELOC_16 | |
7e656649 RH |
10030 | || fixP->fx_r_type == BFD_RELOC_64 |
10031 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10032 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
3d3c5039 | 10033 | |
670a50eb | 10034 | value = *valueP; |
1748b9d8 ILT |
10035 | |
10036 | /* If we aren't adjusting this fixup to be against the section | |
10037 | symbol, we need to adjust the value. */ | |
68952421 | 10038 | #ifdef OBJ_ELF |
1748b9d8 | 10039 | if (fixP->fx_addsy != NULL |
1748b9d8 | 10040 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
622b1860 ILT |
10041 | && (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
10042 | || S_IS_WEAK (fixP->fx_addsy))) | |
1748b9d8 ILT |
10043 | { |
10044 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10045 | if (value != 0 && ! fixP->fx_pcrel) | |
10046 | { | |
10047 | /* In this case, the bfd_install_relocation routine will | |
10048 | incorrectly add the symbol value back in. We just want | |
10049 | the addend to appear in the object file. */ | |
10050 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10051 | } | |
10052 | } | |
10053 | #endif | |
10054 | ||
670a50eb | 10055 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 10056 | |
5b63f465 ILT |
10057 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
10058 | fixP->fx_done = 1; | |
10059 | ||
670a50eb ILT |
10060 | switch (fixP->fx_r_type) |
10061 | { | |
3d3c5039 ILT |
10062 | case BFD_RELOC_MIPS_JMP: |
10063 | case BFD_RELOC_HI16: | |
10064 | case BFD_RELOC_HI16_S: | |
670a50eb | 10065 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
10066 | case BFD_RELOC_MIPS_LITERAL: |
10067 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
10068 | case BFD_RELOC_MIPS_GOT16: |
10069 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
10070 | case BFD_RELOC_MIPS_GOT_HI16: |
10071 | case BFD_RELOC_MIPS_GOT_LO16: | |
10072 | case BFD_RELOC_MIPS_CALL_HI16: | |
10073 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 10074 | case BFD_RELOC_MIPS16_GPREL: |
0bc0e337 JL |
10075 | /* start-sanitize-r5900 */ |
10076 | case BFD_RELOC_MIPS15_S3: | |
10077 | /* end-sanitize-r5900 */ | |
ecd4ca1c | 10078 | if (fixP->fx_pcrel) |
7b777690 | 10079 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10080 | _("Invalid PC relative reloc")); |
670a50eb | 10081 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 10082 | break; |
3d3c5039 | 10083 | |
cc5703cd ILT |
10084 | case BFD_RELOC_MIPS16_JMP: |
10085 | /* We currently always generate a reloc against a symbol, which | |
10086 | means that we don't want an addend even if the symbol is | |
10087 | defined. */ | |
10088 | fixP->fx_addnumber = 0; | |
10089 | break; | |
10090 | ||
ecd4ca1c ILT |
10091 | case BFD_RELOC_PCREL_HI16_S: |
10092 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10093 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10094 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10095 | { | |
10096 | /* For an external symbol adjust by the address to make it | |
10097 | pcrel_offset. We use the address of the RELLO reloc | |
10098 | which follows this one. */ | |
10099 | value += (fixP->fx_next->fx_frag->fr_address | |
10100 | + fixP->fx_next->fx_where); | |
10101 | } | |
10102 | if (value & 0x8000) | |
10103 | value += 0x10000; | |
10104 | value >>= 16; | |
0221ddf7 | 10105 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10106 | if (target_big_endian) |
ecd4ca1c ILT |
10107 | buf += 2; |
10108 | md_number_to_chars (buf, value, 2); | |
10109 | break; | |
10110 | ||
10111 | case BFD_RELOC_PCREL_LO16: | |
10112 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10113 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10114 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10115 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 10116 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10117 | if (target_big_endian) |
ecd4ca1c ILT |
10118 | buf += 2; |
10119 | md_number_to_chars (buf, value, 2); | |
10120 | break; | |
10121 | ||
bf39474f ILT |
10122 | case BFD_RELOC_64: |
10123 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10124 | extended value if we are only 32 bits. */ | |
10125 | if (fixP->fx_done | |
10126 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10127 | { | |
10128 | if (8 <= sizeof (valueT)) | |
10129 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10130 | value, 8); | |
10131 | else | |
10132 | { | |
10133 | long w1, w2; | |
10134 | long hiv; | |
10135 | ||
10136 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 10137 | if (target_big_endian) |
bf39474f ILT |
10138 | w1 += 4; |
10139 | else | |
10140 | w2 += 4; | |
10141 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10142 | if ((value & 0x80000000) != 0) | |
10143 | hiv = 0xffffffff; | |
10144 | else | |
10145 | hiv = 0; | |
10146 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10147 | } | |
10148 | } | |
10149 | break; | |
10150 | ||
f3645945 ILT |
10151 | case BFD_RELOC_32: |
10152 | /* If we are deleting this reloc entry, we must fill in the | |
10153 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
10154 | resolved when it appears but is later defined. We also need |
10155 | to fill in the value if this is an embedded PIC switch table | |
10156 | entry. */ | |
10157 | if (fixP->fx_done | |
10158 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
10159 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
10160 | value, 4); | |
10161 | break; | |
10162 | ||
49ad0c4c ILT |
10163 | case BFD_RELOC_16: |
10164 | /* If we are deleting this reloc entry, we must fill in the | |
10165 | value now. */ | |
10166 | assert (fixP->fx_size == 2); | |
10167 | if (fixP->fx_done) | |
10168 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10169 | value, 2); | |
10170 | break; | |
10171 | ||
f3645945 ILT |
10172 | case BFD_RELOC_LO16: |
10173 | /* When handling an embedded PIC switch statement, we can wind | |
10174 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10175 | if (fixP->fx_done) | |
10176 | { | |
10177 | if (value < -0x8000 || value > 0x7fff) | |
10178 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10179 | _("relocation overflow")); |
0221ddf7 | 10180 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10181 | if (target_big_endian) |
f3645945 ILT |
10182 | buf += 2; |
10183 | md_number_to_chars (buf, value, 2); | |
10184 | } | |
10185 | break; | |
10186 | ||
3d3c5039 | 10187 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
10188 | /* |
10189 | * We need to save the bits in the instruction since fixup_segment() | |
10190 | * might be deleting the relocation entry (i.e., a branch within | |
10191 | * the current segment). | |
10192 | */ | |
fbcfacb7 | 10193 | if ((value & 0x3) != 0) |
3b320c48 | 10194 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10195 | _("Branch to odd address (%lx)"), value); |
670a50eb | 10196 | value >>= 2; |
670a50eb ILT |
10197 | |
10198 | /* update old instruction data */ | |
10199 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
10200 | if (target_big_endian) |
10201 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10202 | else | |
10203 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
10204 | |
10205 | if (value >= -0x8000 && value < 0x8000) | |
10206 | insn |= value & 0xffff; | |
10207 | else | |
10208 | { | |
10209 | /* The branch offset is too large. If this is an | |
10210 | unconditional branch, and we are not generating PIC code, | |
10211 | we can convert it to an absolute jump instruction. */ | |
10212 | if (mips_pic == NO_PIC | |
10213 | && fixP->fx_done | |
10214 | && fixP->fx_frag->fr_address >= text_section->vma | |
10215 | && (fixP->fx_frag->fr_address | |
10216 | < text_section->vma + text_section->_raw_size) | |
10217 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10218 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10219 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10220 | { | |
10221 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10222 | insn = 0x0c000000; /* jal */ | |
10223 | else | |
10224 | insn = 0x08000000; /* j */ | |
10225 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10226 | fixP->fx_done = 0; | |
10227 | fixP->fx_addsy = section_symbol (text_section); | |
10228 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10229 | } | |
10230 | else | |
10231 | { | |
10232 | /* FIXME. It would be possible in principle to handle | |
10233 | conditional branches which overflow. They could be | |
10234 | transformed into a branch around a jump. This would | |
10235 | require setting up variant frags for each different | |
10236 | branch type. The native MIPS assembler attempts to | |
10237 | handle these cases, but it appears to do it | |
10238 | incorrectly. */ | |
10239 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10240 | _("Branch out of range")); |
9da4c5d1 ILT |
10241 | } |
10242 | } | |
10243 | ||
604633ae | 10244 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 10245 | break; |
3d3c5039 | 10246 | |
7e656649 RH |
10247 | case BFD_RELOC_VTABLE_INHERIT: |
10248 | fixP->fx_done = 0; | |
10249 | if (fixP->fx_addsy | |
10250 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10251 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10252 | S_SET_WEAK (fixP->fx_addsy); | |
10253 | break; | |
10254 | ||
10255 | case BFD_RELOC_VTABLE_ENTRY: | |
10256 | fixP->fx_done = 0; | |
10257 | break; | |
10258 | ||
3d3c5039 | 10259 | default: |
670a50eb | 10260 | internalError (); |
3d3c5039 | 10261 | } |
5b63f465 | 10262 | |
670a50eb | 10263 | return 1; |
3d3c5039 ILT |
10264 | } |
10265 | ||
10266 | #if 0 | |
10267 | void | |
670a50eb ILT |
10268 | printInsn (oc) |
10269 | unsigned long oc; | |
3d3c5039 | 10270 | { |
670a50eb ILT |
10271 | const struct mips_opcode *p; |
10272 | int treg, sreg, dreg, shamt; | |
10273 | short imm; | |
10274 | const char *args; | |
10275 | int i; | |
3d3c5039 | 10276 | |
670a50eb ILT |
10277 | for (i = 0; i < NUMOPCODES; ++i) |
10278 | { | |
10279 | p = &mips_opcodes[i]; | |
10280 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10281 | { | |
10282 | printf ("%08lx %s\t", oc, p->name); | |
10283 | treg = (oc >> 16) & 0x1f; | |
10284 | sreg = (oc >> 21) & 0x1f; | |
10285 | dreg = (oc >> 11) & 0x1f; | |
10286 | shamt = (oc >> 6) & 0x1f; | |
10287 | imm = oc; | |
10288 | for (args = p->args;; ++args) | |
10289 | { | |
10290 | switch (*args) | |
10291 | { | |
3d3c5039 | 10292 | case '\0': |
670a50eb ILT |
10293 | printf ("\n"); |
10294 | break; | |
3d3c5039 ILT |
10295 | |
10296 | case ',': | |
10297 | case '(': | |
10298 | case ')': | |
670a50eb ILT |
10299 | printf ("%c", *args); |
10300 | continue; | |
3d3c5039 ILT |
10301 | |
10302 | case 'r': | |
670a50eb ILT |
10303 | assert (treg == sreg); |
10304 | printf ("$%d,$%d", treg, sreg); | |
10305 | continue; | |
3d3c5039 ILT |
10306 | |
10307 | case 'd': | |
918692a5 | 10308 | case 'G': |
670a50eb ILT |
10309 | printf ("$%d", dreg); |
10310 | continue; | |
3d3c5039 ILT |
10311 | |
10312 | case 't': | |
918692a5 | 10313 | case 'E': |
670a50eb ILT |
10314 | printf ("$%d", treg); |
10315 | continue; | |
3d3c5039 | 10316 | |
9226253a ILT |
10317 | case 'k': |
10318 | printf ("0x%x", treg); | |
10319 | continue; | |
10320 | ||
3d3c5039 ILT |
10321 | case 'b': |
10322 | case 's': | |
670a50eb ILT |
10323 | printf ("$%d", sreg); |
10324 | continue; | |
3d3c5039 ILT |
10325 | |
10326 | case 'a': | |
670a50eb ILT |
10327 | printf ("0x%08lx", oc & 0x1ffffff); |
10328 | continue; | |
3d3c5039 ILT |
10329 | |
10330 | case 'i': | |
10331 | case 'j': | |
10332 | case 'o': | |
10333 | case 'u': | |
670a50eb ILT |
10334 | printf ("%d", imm); |
10335 | continue; | |
3d3c5039 ILT |
10336 | |
10337 | case '<': | |
56c96faa | 10338 | case '>': |
670a50eb ILT |
10339 | printf ("$%d", shamt); |
10340 | continue; | |
3d3c5039 ILT |
10341 | |
10342 | default: | |
670a50eb | 10343 | internalError (); |
3d3c5039 | 10344 | } |
670a50eb | 10345 | break; |
3d3c5039 | 10346 | } |
670a50eb | 10347 | return; |
3d3c5039 ILT |
10348 | } |
10349 | } | |
48401fcf | 10350 | printf (_("%08lx UNDEFINED\n"), oc); |
3d3c5039 ILT |
10351 | } |
10352 | #endif | |
10353 | ||
10354 | static symbolS * | |
10355 | get_symbol () | |
10356 | { | |
670a50eb ILT |
10357 | int c; |
10358 | char *name; | |
10359 | symbolS *p; | |
10360 | ||
10361 | name = input_line_pointer; | |
10362 | c = get_symbol_end (); | |
10363 | p = (symbolS *) symbol_find_or_make (name); | |
10364 | *input_line_pointer = c; | |
10365 | return p; | |
3d3c5039 ILT |
10366 | } |
10367 | ||
becfe05e ILT |
10368 | /* Align the current frag to a given power of two. The MIPS assembler |
10369 | also automatically adjusts any preceding label. */ | |
10370 | ||
10371 | static void | |
23dc1ae3 | 10372 | mips_align (to, fill, label) |
becfe05e ILT |
10373 | int to; |
10374 | int fill; | |
23dc1ae3 | 10375 | symbolS *label; |
becfe05e | 10376 | { |
fbcfacb7 | 10377 | mips_emit_delays (false); |
e2e5acfa | 10378 | frag_align (to, fill, 0); |
becfe05e | 10379 | record_alignment (now_seg, to); |
23dc1ae3 | 10380 | if (label != NULL) |
becfe05e | 10381 | { |
23dc1ae3 ILT |
10382 | assert (S_GET_SEGMENT (label) == now_seg); |
10383 | label->sy_frag = frag_now; | |
10384 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
10385 | } |
10386 | } | |
10387 | ||
10388 | /* Align to a given power of two. .align 0 turns off the automatic | |
10389 | alignment used by the data creating pseudo-ops. */ | |
10390 | ||
3d3c5039 ILT |
10391 | static void |
10392 | s_align (x) | |
10393 | int x; | |
10394 | { | |
670a50eb ILT |
10395 | register int temp; |
10396 | register long temp_fill; | |
10397 | long max_alignment = 15; | |
3d3c5039 | 10398 | |
670a50eb | 10399 | /* |
3d3c5039 ILT |
10400 | |
10401 | o Note that the assembler pulls down any immediately preceeding label | |
10402 | to the aligned address. | |
10403 | o It's not documented but auto alignment is reinstated by | |
10404 | a .align pseudo instruction. | |
10405 | o Note also that after auto alignment is turned off the mips assembler | |
10406 | issues an error on attempt to assemble an improperly aligned data item. | |
10407 | We don't. | |
10408 | ||
10409 | */ | |
10410 | ||
670a50eb ILT |
10411 | temp = get_absolute_expression (); |
10412 | if (temp > max_alignment) | |
48401fcf | 10413 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
670a50eb ILT |
10414 | else if (temp < 0) |
10415 | { | |
48401fcf | 10416 | as_warn (_("Alignment negative: 0 assumed.")); |
670a50eb ILT |
10417 | temp = 0; |
10418 | } | |
10419 | if (*input_line_pointer == ',') | |
10420 | { | |
10421 | input_line_pointer++; | |
10422 | temp_fill = get_absolute_expression (); | |
10423 | } | |
10424 | else | |
10425 | temp_fill = 0; | |
10426 | if (temp) | |
10427 | { | |
10428 | auto_align = 1; | |
fbcfacb7 ILT |
10429 | mips_align (temp, (int) temp_fill, |
10430 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 10431 | } |
670a50eb ILT |
10432 | else |
10433 | { | |
10434 | auto_align = 0; | |
3d3c5039 ILT |
10435 | } |
10436 | ||
670a50eb | 10437 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10438 | } |
10439 | ||
739708fa KR |
10440 | void |
10441 | mips_flush_pending_output () | |
becfe05e | 10442 | { |
fbcfacb7 ILT |
10443 | mips_emit_delays (false); |
10444 | mips_clear_insn_labels (); | |
becfe05e ILT |
10445 | } |
10446 | ||
3d3c5039 ILT |
10447 | static void |
10448 | s_change_sec (sec) | |
10449 | int sec; | |
10450 | { | |
88225433 | 10451 | segT seg; |
becfe05e | 10452 | |
5b63f465 ILT |
10453 | /* When generating embedded PIC code, we only use the .text, .lit8, |
10454 | .sdata and .sbss sections. We change the .data and .rdata | |
10455 | pseudo-ops to use .sdata. */ | |
10456 | if (mips_pic == EMBEDDED_PIC | |
10457 | && (sec == 'd' || sec == 'r')) | |
10458 | sec = 's'; | |
10459 | ||
acdc7ce3 ILT |
10460 | #ifdef OBJ_ELF |
10461 | /* The ELF backend needs to know that we are changing sections, so | |
10462 | that .previous works correctly. We could do something like check | |
10463 | for a obj_section_change_hook macro, but that might be confusing | |
10464 | as it would not be appropriate to use it in the section changing | |
10465 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10466 | This should be cleaner, somehow. */ | |
10467 | obj_elf_section_change_hook (); | |
10468 | #endif | |
10469 | ||
fbcfacb7 | 10470 | mips_emit_delays (false); |
670a50eb ILT |
10471 | switch (sec) |
10472 | { | |
3d3c5039 | 10473 | case 't': |
604633ae | 10474 | s_text (0); |
670a50eb | 10475 | break; |
3d3c5039 | 10476 | case 'd': |
604633ae | 10477 | s_data (0); |
670a50eb | 10478 | break; |
3d3c5039 | 10479 | case 'b': |
670a50eb | 10480 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
10481 | demand_empty_rest_of_line (); |
10482 | break; | |
88225433 ILT |
10483 | |
10484 | case 'r': | |
1dc1e798 KR |
10485 | if (USE_GLOBAL_POINTER_OPT) |
10486 | { | |
10487 | seg = subseg_new (RDATA_SECTION_NAME, | |
10488 | (subsegT) get_absolute_expression ()); | |
10489 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10490 | { | |
10491 | bfd_set_section_flags (stdoutput, seg, | |
10492 | (SEC_ALLOC | |
10493 | | SEC_LOAD | |
10494 | | SEC_READONLY | |
10495 | | SEC_RELOC | |
10496 | | SEC_DATA)); | |
08e17202 ILT |
10497 | if (strcmp (TARGET_OS, "elf") != 0) |
10498 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10499 | } |
10500 | demand_empty_rest_of_line (); | |
10501 | } | |
10502 | else | |
10503 | { | |
48401fcf | 10504 | as_bad (_("No read only data section in this object file format")); |
1dc1e798 KR |
10505 | demand_empty_rest_of_line (); |
10506 | return; | |
10507 | } | |
88225433 | 10508 | break; |
88225433 ILT |
10509 | |
10510 | case 's': | |
1dc1e798 KR |
10511 | if (USE_GLOBAL_POINTER_OPT) |
10512 | { | |
10513 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10514 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10515 | { | |
10516 | bfd_set_section_flags (stdoutput, seg, | |
10517 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10518 | | SEC_DATA); | |
08e17202 ILT |
10519 | if (strcmp (TARGET_OS, "elf") != 0) |
10520 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10521 | } |
10522 | demand_empty_rest_of_line (); | |
10523 | break; | |
10524 | } | |
10525 | else | |
10526 | { | |
48401fcf | 10527 | as_bad (_("Global pointers not supported; recompile -G 0")); |
1dc1e798 KR |
10528 | demand_empty_rest_of_line (); |
10529 | return; | |
10530 | } | |
3d3c5039 | 10531 | } |
88225433 | 10532 | |
670a50eb | 10533 | auto_align = 1; |
3d3c5039 ILT |
10534 | } |
10535 | ||
739708fa KR |
10536 | void |
10537 | mips_enable_auto_align () | |
9da4c5d1 | 10538 | { |
9da4c5d1 ILT |
10539 | auto_align = 1; |
10540 | } | |
10541 | ||
3d3c5039 ILT |
10542 | static void |
10543 | s_cons (log_size) | |
10544 | int log_size; | |
10545 | { | |
23dc1ae3 ILT |
10546 | symbolS *label; |
10547 | ||
fbcfacb7 ILT |
10548 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10549 | mips_emit_delays (false); | |
670a50eb | 10550 | if (log_size > 0 && auto_align) |
23dc1ae3 | 10551 | mips_align (log_size, 0, label); |
fbcfacb7 | 10552 | mips_clear_insn_labels (); |
670a50eb | 10553 | cons (1 << log_size); |
3d3c5039 ILT |
10554 | } |
10555 | ||
3d3c5039 | 10556 | static void |
becfe05e ILT |
10557 | s_float_cons (type) |
10558 | int type; | |
3d3c5039 | 10559 | { |
23dc1ae3 ILT |
10560 | symbolS *label; |
10561 | ||
fbcfacb7 | 10562 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 10563 | |
fbcfacb7 | 10564 | mips_emit_delays (false); |
670a50eb ILT |
10565 | |
10566 | if (auto_align) | |
becfe05e | 10567 | if (type == 'd') |
23dc1ae3 | 10568 | mips_align (3, 0, label); |
670a50eb | 10569 | else |
23dc1ae3 | 10570 | mips_align (2, 0, label); |
670a50eb | 10571 | |
fbcfacb7 | 10572 | mips_clear_insn_labels (); |
1849d646 | 10573 | |
becfe05e | 10574 | float_cons (type); |
3d3c5039 ILT |
10575 | } |
10576 | ||
c1444ec4 ILT |
10577 | /* Handle .globl. We need to override it because on Irix 5 you are |
10578 | permitted to say | |
10579 | .globl foo .text | |
10580 | where foo is an undefined symbol, to mean that foo should be | |
10581 | considered to be the address of a function. */ | |
10582 | ||
10583 | static void | |
10584 | s_mips_globl (x) | |
10585 | int x; | |
10586 | { | |
10587 | char *name; | |
10588 | int c; | |
10589 | symbolS *symbolP; | |
fb251650 | 10590 | flagword flag; |
c1444ec4 ILT |
10591 | |
10592 | name = input_line_pointer; | |
10593 | c = get_symbol_end (); | |
10594 | symbolP = symbol_find_or_make (name); | |
10595 | *input_line_pointer = c; | |
10596 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10597 | |
10598 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10599 | being a function is apparently labelled as being an object. */ | |
10600 | flag = BSF_OBJECT; | |
10601 | ||
c1444ec4 ILT |
10602 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10603 | { | |
10604 | char *secname; | |
10605 | asection *sec; | |
10606 | ||
10607 | secname = input_line_pointer; | |
10608 | c = get_symbol_end (); | |
10609 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10610 | if (sec == NULL) | |
48401fcf | 10611 | as_bad (_("%s: no such section"), secname); |
c1444ec4 ILT |
10612 | *input_line_pointer = c; |
10613 | ||
10614 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10615 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10616 | } |
10617 | ||
fb251650 ILT |
10618 | symbolP->bsym->flags |= flag; |
10619 | ||
c1444ec4 ILT |
10620 | S_SET_EXTERNAL (symbolP); |
10621 | demand_empty_rest_of_line (); | |
10622 | } | |
10623 | ||
3d3c5039 ILT |
10624 | static void |
10625 | s_option (x) | |
10626 | int x; | |
10627 | { | |
dd3f1f76 ILT |
10628 | char *opt; |
10629 | char c; | |
10630 | ||
10631 | opt = input_line_pointer; | |
10632 | c = get_symbol_end (); | |
10633 | ||
dd3f1f76 | 10634 | if (*opt == 'O') |
9226253a ILT |
10635 | { |
10636 | /* FIXME: What does this mean? */ | |
10637 | } | |
dd3f1f76 | 10638 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10639 | { |
d9aba805 | 10640 | int i; |
42562568 | 10641 | |
d9aba805 ILT |
10642 | i = atoi (opt + 3); |
10643 | if (i == 0) | |
10644 | mips_pic = NO_PIC; | |
10645 | else if (i == 2) | |
10646 | mips_pic = SVR4_PIC; | |
10647 | else | |
48401fcf | 10648 | as_bad (_(".option pic%d not supported"), i); |
d9aba805 | 10649 | |
1dc1e798 | 10650 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10651 | { |
10652 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10653 | as_warn (_("-G may not be used with SVR4 PIC code")); |
42562568 ILT |
10654 | g_switch_value = 0; |
10655 | bfd_set_gp_size (stdoutput, 0); | |
10656 | } | |
9226253a | 10657 | } |
dd3f1f76 | 10658 | else |
48401fcf | 10659 | as_warn (_("Unrecognized option \"%s\""), opt); |
dd3f1f76 ILT |
10660 | |
10661 | *input_line_pointer = c; | |
670a50eb | 10662 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10663 | } |
10664 | ||
3c83da8a JW |
10665 | /* This structure is used to hold a stack of .set values. */ |
10666 | ||
10667 | struct mips_option_stack | |
10668 | { | |
10669 | struct mips_option_stack *next; | |
10670 | struct mips_set_options options; | |
10671 | }; | |
10672 | ||
10673 | static struct mips_option_stack *mips_opts_stack; | |
10674 | ||
10675 | /* Handle the .set pseudo-op. */ | |
10676 | ||
3d3c5039 ILT |
10677 | static void |
10678 | s_mipsset (x) | |
10679 | int x; | |
10680 | { | |
670a50eb ILT |
10681 | char *name = input_line_pointer, ch; |
10682 | ||
10683 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10684 | input_line_pointer++; | |
10685 | ch = *input_line_pointer; | |
10686 | *input_line_pointer = '\0'; | |
10687 | ||
10688 | if (strcmp (name, "reorder") == 0) | |
10689 | { | |
3c83da8a | 10690 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10691 | { |
4a1cb507 ILT |
10692 | /* If we still have pending nops, we can discard them. The |
10693 | usual nop handling will insert any that are still | |
10694 | needed. */ | |
3c83da8a JW |
10695 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10696 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10697 | prev_nop_frag = NULL; |
4e95866e | 10698 | } |
3c83da8a | 10699 | mips_opts.noreorder = 0; |
670a50eb ILT |
10700 | } |
10701 | else if (strcmp (name, "noreorder") == 0) | |
10702 | { | |
fbcfacb7 | 10703 | mips_emit_delays (true); |
3c83da8a | 10704 | mips_opts.noreorder = 1; |
0dd2d296 | 10705 | mips_any_noreorder = 1; |
670a50eb ILT |
10706 | } |
10707 | else if (strcmp (name, "at") == 0) | |
10708 | { | |
3c83da8a | 10709 | mips_opts.noat = 0; |
670a50eb ILT |
10710 | } |
10711 | else if (strcmp (name, "noat") == 0) | |
10712 | { | |
3c83da8a | 10713 | mips_opts.noat = 1; |
3d3c5039 | 10714 | } |
670a50eb ILT |
10715 | else if (strcmp (name, "macro") == 0) |
10716 | { | |
3c83da8a | 10717 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10718 | } |
10719 | else if (strcmp (name, "nomacro") == 0) | |
10720 | { | |
3c83da8a | 10721 | if (mips_opts.noreorder == 0) |
48401fcf | 10722 | as_bad (_("`noreorder' must be set before `nomacro'")); |
3c83da8a | 10723 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10724 | } |
10725 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10726 | { | |
3c83da8a | 10727 | mips_opts.nomove = 0; |
670a50eb ILT |
10728 | } |
10729 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10730 | { | |
3c83da8a | 10731 | mips_opts.nomove = 1; |
670a50eb ILT |
10732 | } |
10733 | else if (strcmp (name, "bopt") == 0) | |
10734 | { | |
3c83da8a | 10735 | mips_opts.nobopt = 0; |
670a50eb ILT |
10736 | } |
10737 | else if (strcmp (name, "nobopt") == 0) | |
10738 | { | |
3c83da8a | 10739 | mips_opts.nobopt = 1; |
670a50eb | 10740 | } |
943321c0 ILT |
10741 | else if (strcmp (name, "mips16") == 0 |
10742 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10743 | mips_opts.mips16 = 1; |
943321c0 ILT |
10744 | else if (strcmp (name, "nomips16") == 0 |
10745 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10746 | mips_opts.mips16 = 0; |
1051c97f ILT |
10747 | else if (strncmp (name, "mips", 4) == 0) |
10748 | { | |
10749 | int isa; | |
10750 | ||
10751 | /* Permit the user to change the ISA on the fly. Needless to | |
10752 | say, misuse can cause serious problems. */ | |
10753 | isa = atoi (name + 4); | |
10754 | if (isa == 0) | |
3c83da8a | 10755 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10756 | else if (isa < 1 || isa > 4) |
48401fcf | 10757 | as_bad (_("unknown ISA level")); |
1051c97f | 10758 | else |
3c83da8a | 10759 | mips_opts.isa = isa; |
1051c97f | 10760 | } |
cc5703cd | 10761 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10762 | mips_opts.noautoextend = 0; |
cc5703cd | 10763 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10764 | mips_opts.noautoextend = 1; |
10765 | else if (strcmp (name, "push") == 0) | |
10766 | { | |
10767 | struct mips_option_stack *s; | |
10768 | ||
10769 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10770 | s->next = mips_opts_stack; | |
10771 | s->options = mips_opts; | |
10772 | mips_opts_stack = s; | |
10773 | } | |
10774 | else if (strcmp (name, "pop") == 0) | |
10775 | { | |
10776 | struct mips_option_stack *s; | |
10777 | ||
10778 | s = mips_opts_stack; | |
10779 | if (s == NULL) | |
48401fcf | 10780 | as_bad (_(".set pop with no .set push")); |
3c83da8a JW |
10781 | else |
10782 | { | |
10783 | /* If we're changing the reorder mode we need to handle | |
10784 | delay slots correctly. */ | |
10785 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10786 | mips_emit_delays (true); | |
10787 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10788 | { | |
10789 | if (prev_nop_frag != NULL) | |
10790 | { | |
10791 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10792 | * (mips_opts.mips16 ? 2 : 4)); | |
10793 | prev_nop_frag = NULL; | |
10794 | } | |
10795 | } | |
10796 | ||
10797 | mips_opts = s->options; | |
10798 | mips_opts_stack = s->next; | |
10799 | free (s); | |
10800 | } | |
10801 | } | |
670a50eb ILT |
10802 | else |
10803 | { | |
48401fcf | 10804 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
670a50eb ILT |
10805 | } |
10806 | *input_line_pointer = ch; | |
10807 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10808 | } |
10809 | ||
9226253a ILT |
10810 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10811 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10812 | ||
10813 | static void | |
10814 | s_abicalls (ignore) | |
10815 | int ignore; | |
10816 | { | |
d9aba805 | 10817 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10818 | if (USE_GLOBAL_POINTER_OPT) |
10819 | { | |
10820 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10821 | as_warn (_("-G may not be used with SVR4 PIC code")); |
1dc1e798 KR |
10822 | g_switch_value = 0; |
10823 | } | |
d9aba805 | 10824 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10825 | demand_empty_rest_of_line (); |
10826 | } | |
10827 | ||
10828 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10829 | PIC code. It sets the $gp register for the function based on the | |
10830 | function address, which is in the register named in the argument. | |
10831 | This uses a relocation against _gp_disp, which is handled specially | |
10832 | by the linker. The result is: | |
10833 | lui $gp,%hi(_gp_disp) | |
10834 | addiu $gp,$gp,%lo(_gp_disp) | |
10835 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10836 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10837 | |
10838 | static void | |
10839 | s_cpload (ignore) | |
10840 | int ignore; | |
10841 | { | |
10842 | expressionS ex; | |
10843 | int icnt = 0; | |
10844 | ||
d9aba805 ILT |
10845 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10846 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10847 | { |
10848 | s_ignore (0); | |
10849 | return; | |
10850 | } | |
10851 | ||
10852 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10853 | if (mips_opts.noreorder == 0) |
48401fcf | 10854 | as_warn (_(".cpload not in noreorder section")); |
0dd2d296 | 10855 | |
9226253a ILT |
10856 | ex.X_op = O_symbol; |
10857 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10858 | ex.X_op_symbol = NULL; | |
10859 | ex.X_add_number = 0; | |
10860 | ||
fb251650 ILT |
10861 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10862 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10863 | ||
0dd2d296 ILT |
10864 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10865 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10866 | (int) BFD_RELOC_LO16); |
10867 | ||
0dd2d296 ILT |
10868 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10869 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10870 | |
10871 | demand_empty_rest_of_line (); | |
10872 | } | |
10873 | ||
10874 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10875 | offset from $sp. The offset is remembered, and after making a PIC | |
10876 | call $gp is restored from that location. */ | |
10877 | ||
10878 | static void | |
10879 | s_cprestore (ignore) | |
10880 | int ignore; | |
10881 | { | |
10882 | expressionS ex; | |
10883 | int icnt = 0; | |
10884 | ||
d9aba805 ILT |
10885 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10886 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10887 | { |
10888 | s_ignore (0); | |
10889 | return; | |
10890 | } | |
10891 | ||
9226253a ILT |
10892 | mips_cprestore_offset = get_absolute_expression (); |
10893 | ||
10894 | ex.X_op = O_constant; | |
10895 | ex.X_add_symbol = NULL; | |
10896 | ex.X_op_symbol = NULL; | |
10897 | ex.X_add_number = mips_cprestore_offset; | |
10898 | ||
0dd2d296 | 10899 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
10900 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10901 | || mips_opts.isa < 3) | |
10902 | ? "sw" : "sd"), | |
9226253a ILT |
10903 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10904 | ||
10905 | demand_empty_rest_of_line (); | |
10906 | } | |
10907 | ||
0dd2d296 ILT |
10908 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10909 | code. It generates a 32 bit GP relative reloc. */ | |
10910 | ||
10911 | static void | |
10912 | s_gpword (ignore) | |
10913 | int ignore; | |
10914 | { | |
23dc1ae3 | 10915 | symbolS *label; |
0dd2d296 ILT |
10916 | expressionS ex; |
10917 | char *p; | |
10918 | ||
10919 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10920 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10921 | { |
10922 | s_cons (2); | |
10923 | return; | |
10924 | } | |
10925 | ||
fbcfacb7 ILT |
10926 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10927 | mips_emit_delays (true); | |
0dd2d296 | 10928 | if (auto_align) |
23dc1ae3 | 10929 | mips_align (2, 0, label); |
fbcfacb7 | 10930 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10931 | |
10932 | expression (&ex); | |
10933 | ||
10934 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10935 | { | |
48401fcf | 10936 | as_bad (_("Unsupported use of .gpword")); |
0dd2d296 ILT |
10937 | ignore_rest_of_line (); |
10938 | } | |
10939 | ||
10940 | p = frag_more (4); | |
10941 | md_number_to_chars (p, (valueT) 0, 4); | |
10942 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10943 | BFD_RELOC_MIPS_GPREL32); | |
10944 | ||
10945 | demand_empty_rest_of_line (); | |
10946 | } | |
10947 | ||
10948 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10949 | tables in SVR4 PIC code. */ | |
10950 | ||
10951 | static void | |
10952 | s_cpadd (ignore) | |
10953 | int ignore; | |
10954 | { | |
10955 | int icnt = 0; | |
10956 | int reg; | |
10957 | ||
10958 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10959 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10960 | { |
10961 | s_ignore (0); | |
10962 | return; | |
10963 | } | |
10964 | ||
10965 | /* Add $gp to the register named as an argument. */ | |
10966 | reg = tc_get_register (0); | |
10967 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
10968 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10969 | || mips_opts.isa < 3) | |
10970 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
10971 | "d,v,t", reg, reg, GP); |
10972 | ||
10973 | demand_empty_rest_of_line (); | |
10974 | } | |
10975 | ||
ed3eb786 ILT |
10976 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10977 | mips16 mode. This permits the linker to handle them specially, | |
10978 | such as generating jalx instructions when needed. We also make | |
10979 | them odd for the duration of the assembly, in order to generate the | |
10980 | right sort of code. We will make them even in the adjust_symtab | |
10981 | routine, while leaving them marked. This is convenient for the | |
10982 | debugger and the disassembler. The linker knows to make them odd | |
10983 | again. */ | |
10984 | ||
10985 | static void | |
10986 | s_insn (ignore) | |
10987 | int ignore; | |
10988 | { | |
3c83da8a JW |
10989 | if (mips_opts.mips16) |
10990 | mips16_mark_labels (); | |
ed3eb786 | 10991 | |
3c83da8a JW |
10992 | demand_empty_rest_of_line (); |
10993 | } | |
ed3eb786 | 10994 | |
3c83da8a JW |
10995 | /* Handle a .stabn directive. We need these in order to mark a label |
10996 | as being a mips16 text label correctly. Sometimes the compiler | |
10997 | will emit a label, followed by a .stabn, and then switch sections. | |
10998 | If the label and .stabn are in mips16 mode, then the label is | |
10999 | really a mips16 text label. */ | |
ed3eb786 | 11000 | |
3c83da8a JW |
11001 | static void |
11002 | s_mips_stab (type) | |
11003 | int type; | |
11004 | { | |
11005 | if (type == 'n' && mips_opts.mips16) | |
11006 | mips16_mark_labels (); | |
11007 | ||
11008 | s_stab (type); | |
ed3eb786 ILT |
11009 | } |
11010 | ||
3c69baf9 GRK |
11011 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
11012 | */ | |
11013 | ||
11014 | static void | |
11015 | s_mips_weakext (ignore) | |
11016 | int ignore; | |
11017 | { | |
11018 | char *name; | |
11019 | int c; | |
11020 | symbolS *symbolP; | |
11021 | expressionS exp; | |
11022 | ||
11023 | name = input_line_pointer; | |
11024 | c = get_symbol_end (); | |
11025 | symbolP = symbol_find_or_make (name); | |
11026 | S_SET_WEAK (symbolP); | |
11027 | *input_line_pointer = c; | |
11028 | ||
11029 | SKIP_WHITESPACE (); | |
11030 | ||
11031 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11032 | { | |
11033 | if (S_IS_DEFINED (symbolP)) | |
11034 | { | |
11035 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
11036 | S_GET_NAME (symbolP)); | |
11037 | ignore_rest_of_line (); | |
11038 | return; | |
11039 | } | |
11040 | ||
11041 | if (*input_line_pointer == ',') | |
11042 | { | |
11043 | ++input_line_pointer; | |
11044 | SKIP_WHITESPACE (); | |
11045 | } | |
11046 | ||
11047 | expression (&exp); | |
11048 | if (exp.X_op != O_symbol) | |
11049 | { | |
11050 | as_bad ("bad .weakext directive"); | |
11051 | ignore_rest_of_line(); | |
11052 | return; | |
11053 | } | |
11054 | symbolP->sy_value = exp; | |
11055 | } | |
11056 | ||
11057 | demand_empty_rest_of_line (); | |
11058 | } | |
11059 | ||
9226253a | 11060 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
11061 | to parse .frame. The argument is non-zero if this is the frame |
11062 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 11063 | |
3d3c5039 | 11064 | int |
0dd2d296 ILT |
11065 | tc_get_register (frame) |
11066 | int frame; | |
3d3c5039 ILT |
11067 | { |
11068 | int reg; | |
11069 | ||
11070 | SKIP_WHITESPACE (); | |
11071 | if (*input_line_pointer++ != '$') | |
11072 | { | |
48401fcf | 11073 | as_warn (_("expected `$'")); |
0dd2d296 | 11074 | reg = 0; |
3d3c5039 | 11075 | } |
0dd2d296 | 11076 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
11077 | { |
11078 | reg = get_absolute_expression (); | |
11079 | if (reg < 0 || reg >= 32) | |
11080 | { | |
48401fcf | 11081 | as_warn (_("Bad register number")); |
3d3c5039 ILT |
11082 | reg = 0; |
11083 | } | |
11084 | } | |
11085 | else | |
11086 | { | |
11087 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 11088 | reg = FP; |
3d3c5039 | 11089 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 11090 | reg = SP; |
3d3c5039 | 11091 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 11092 | reg = GP; |
3d3c5039 | 11093 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 11094 | reg = AT; |
3d3c5039 ILT |
11095 | else |
11096 | { | |
48401fcf | 11097 | as_warn (_("Unrecognized register name")); |
0dd2d296 | 11098 | reg = 0; |
3d3c5039 ILT |
11099 | } |
11100 | input_line_pointer += 2; | |
11101 | } | |
0dd2d296 ILT |
11102 | if (frame) |
11103 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
11104 | return reg; |
11105 | } | |
11106 | ||
0dd2d296 ILT |
11107 | valueT |
11108 | md_section_align (seg, addr) | |
11109 | asection *seg; | |
11110 | valueT addr; | |
11111 | { | |
11112 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11113 | ||
cf32394d ILT |
11114 | #ifdef OBJ_ELF |
11115 | /* We don't need to align ELF sections to the full alignment. | |
11116 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
11117 | byte boundary. We don't bother to align the sections if we are |
11118 | targeted for an embedded system. */ | |
11119 | if (strcmp (TARGET_OS, "elf") == 0) | |
11120 | return addr; | |
943321c0 ILT |
11121 | if (align > 4) |
11122 | align = 4; | |
10a14e36 | 11123 | #endif |
cf32394d ILT |
11124 | |
11125 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
11126 | } |
11127 | ||
d8a1c247 KR |
11128 | /* Utility routine, called from above as well. If called while the |
11129 | input file is still being read, it's only an approximation. (For | |
11130 | example, a symbol may later become defined which appeared to be | |
11131 | undefined earlier.) */ | |
22ba90ce ILT |
11132 | |
11133 | static int | |
85ce5635 | 11134 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 11135 | symbolS *sym; |
85ce5635 | 11136 | int before_relaxing; |
d8a1c247 KR |
11137 | { |
11138 | if (sym == 0) | |
11139 | return 0; | |
11140 | ||
1dc1e798 KR |
11141 | if (USE_GLOBAL_POINTER_OPT) |
11142 | { | |
11143 | const char *symname; | |
11144 | int change; | |
11145 | ||
11146 | /* Find out whether this symbol can be referenced off the GP | |
11147 | register. It can be if it is smaller than the -G size or if | |
11148 | it is in the .sdata or .sbss section. Certain symbols can | |
11149 | not be referenced off the GP, although it appears as though | |
11150 | they can. */ | |
11151 | symname = S_GET_NAME (sym); | |
11152 | if (symname != (const char *) NULL | |
11153 | && (strcmp (symname, "eprol") == 0 | |
11154 | || strcmp (symname, "etext") == 0 | |
11155 | || strcmp (symname, "_gp") == 0 | |
11156 | || strcmp (symname, "edata") == 0 | |
11157 | || strcmp (symname, "_fbss") == 0 | |
11158 | || strcmp (symname, "_fdata") == 0 | |
11159 | || strcmp (symname, "_ftext") == 0 | |
11160 | || strcmp (symname, "end") == 0 | |
11161 | || strcmp (symname, "_gp_disp") == 0)) | |
11162 | change = 1; | |
23ac3ca1 | 11163 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
11164 | && (0 |
11165 | #ifndef NO_ECOFF_DEBUGGING | |
11166 | || (sym->ecoff_extern_size != 0 | |
11167 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 11168 | #endif |
85ce5635 ILT |
11169 | /* We must defer this decision until after the whole |
11170 | file has been read, since there might be a .extern | |
11171 | after the first use of this symbol. */ | |
a5586bdc ILT |
11172 | || (before_relaxing |
11173 | #ifndef NO_ECOFF_DEBUGGING | |
11174 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 11175 | #endif |
a5586bdc | 11176 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
11177 | || (S_GET_VALUE (sym) != 0 |
11178 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11179 | change = 0; | |
11180 | else | |
11181 | { | |
11182 | const char *segname; | |
d8a1c247 | 11183 | |
1dc1e798 KR |
11184 | segname = segment_name (S_GET_SEGMENT (sym)); |
11185 | assert (strcmp (segname, ".lit8") != 0 | |
11186 | && strcmp (segname, ".lit4") != 0); | |
11187 | change = (strcmp (segname, ".sdata") != 0 | |
11188 | && strcmp (segname, ".sbss") != 0); | |
11189 | } | |
11190 | return change; | |
11191 | } | |
11192 | else | |
11193 | /* We are not optimizing for the GP register. */ | |
11194 | return 1; | |
d8a1c247 KR |
11195 | } |
11196 | ||
cc5703cd ILT |
11197 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
11198 | extended opcode. SEC is the section the frag is in. */ | |
11199 | ||
11200 | static int | |
11201 | mips16_extended_frag (fragp, sec, stretch) | |
11202 | fragS *fragp; | |
11203 | asection *sec; | |
11204 | long stretch; | |
11205 | { | |
11206 | int type; | |
11207 | register const struct mips16_immed_operand *op; | |
11208 | offsetT val; | |
11209 | int mintiny, maxtiny; | |
f74ba7a3 | 11210 | segT symsec; |
cc5703cd | 11211 | |
8728fa92 ILT |
11212 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
11213 | return 0; | |
11214 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11215 | return 1; | |
11216 | ||
cc5703cd ILT |
11217 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
11218 | op = mips16_immed_operands; | |
11219 | while (op->type != type) | |
11220 | { | |
11221 | ++op; | |
11222 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11223 | } | |
11224 | ||
11225 | if (op->unsp) | |
11226 | { | |
11227 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11228 | { | |
11229 | mintiny = 1; | |
11230 | maxtiny = 1 << op->nbits; | |
11231 | } | |
11232 | else | |
11233 | { | |
11234 | mintiny = 0; | |
11235 | maxtiny = (1 << op->nbits) - 1; | |
11236 | } | |
11237 | } | |
11238 | else | |
11239 | { | |
11240 | mintiny = - (1 << (op->nbits - 1)); | |
11241 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11242 | } | |
11243 | ||
f74ba7a3 ILT |
11244 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
11245 | a particular frag address. */ | |
11246 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
11247 | { | |
11248 | val = (fragp->fr_symbol->sy_value.X_add_number | |
11249 | + fragp->fr_symbol->sy_frag->fr_address); | |
11250 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
11251 | } | |
11252 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
11253 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
11254 | == O_constant)) | |
11255 | { | |
11256 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
11257 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
11258 | + fragp->fr_symbol->sy_value.X_add_number | |
11259 | + fragp->fr_symbol->sy_frag->fr_address); | |
11260 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
11261 | } | |
11262 | else | |
11263 | return 1; | |
cc5703cd ILT |
11264 | |
11265 | if (op->pcrel) | |
11266 | { | |
11267 | addressT addr; | |
11268 | ||
11269 | /* We won't have the section when we are called from | |
11270 | mips_relax_frag. However, we will always have been called | |
11271 | from md_estimate_size_before_relax first. If this is a | |
11272 | branch to a different section, we mark it as such. If SEC is | |
11273 | NULL, and the frag is not marked, then it must be a branch to | |
11274 | the same section. */ | |
11275 | if (sec == NULL) | |
11276 | { | |
11277 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11278 | return 1; | |
11279 | } | |
11280 | else | |
11281 | { | |
f74ba7a3 | 11282 | if (symsec != sec) |
cc5703cd ILT |
11283 | { |
11284 | fragp->fr_subtype = | |
11285 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11286 | ||
11287 | /* FIXME: We should support this, and let the linker | |
11288 | catch branches and loads that are out of range. */ | |
11289 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11290 | _("unsupported PC relative reference to different section")); |
cc5703cd ILT |
11291 | |
11292 | return 1; | |
11293 | } | |
11294 | } | |
11295 | ||
11296 | /* In this case, we know for sure that the symbol fragment is in | |
11297 | the same section. If the fr_address of the symbol fragment | |
11298 | is greater then the address of this fragment we want to add | |
11299 | in STRETCH in order to get a better estimate of the address. | |
11300 | This particularly matters because of the shift bits. */ | |
11301 | if (stretch != 0 | |
11302 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
11303 | { | |
11304 | fragS *f; | |
11305 | ||
a941619c ILT |
11306 | /* Adjust stretch for any alignment frag. Note that if have |
11307 | been expanding the earlier code, the symbol may be | |
11308 | defined in what appears to be an earlier frag. FIXME: | |
11309 | This doesn't handle the fr_subtype field, which specifies | |
11310 | a maximum number of bytes to skip when doing an | |
11311 | alignment. */ | |
11312 | for (f = fragp; | |
11313 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
11314 | f = f->fr_next) | |
cc5703cd | 11315 | { |
cc5703cd ILT |
11316 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
11317 | { | |
11318 | if (stretch < 0) | |
11319 | stretch = - ((- stretch) | |
11320 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11321 | else | |
11322 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11323 | if (stretch == 0) | |
11324 | break; | |
11325 | } | |
11326 | } | |
a941619c ILT |
11327 | if (f != NULL) |
11328 | val += stretch; | |
cc5703cd ILT |
11329 | } |
11330 | ||
a677feeb ILT |
11331 | addr = fragp->fr_address + fragp->fr_fix; |
11332 | ||
11333 | /* The base address rules are complicated. The base address of | |
11334 | a branch is the following instruction. The base address of a | |
11335 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
11336 | is in a delay slot (in which case it can not be extended) use |
11337 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 11338 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
11339 | { |
11340 | addr += 2; | |
319305a7 ILT |
11341 | |
11342 | /* If we are currently assuming that this frag should be | |
11343 | extended, then, the current address is two bytes | |
11344 | higher. */ | |
11345 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11346 | addr += 2; | |
11347 | ||
fbcfacb7 ILT |
11348 | /* Ignore the low bit in the target, since it will be set |
11349 | for a text label. */ | |
11350 | if ((val & 1) != 0) | |
11351 | --val; | |
11352 | } | |
a677feeb ILT |
11353 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11354 | addr -= 4; | |
11355 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11356 | addr -= 2; | |
cc5703cd | 11357 | |
cc5703cd ILT |
11358 | val -= addr & ~ ((1 << op->shift) - 1); |
11359 | ||
11360 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11361 | if (type == 'p' || type == 'q') | |
11362 | val /= 2; | |
11363 | ||
11364 | /* If any of the shifted bits are set, we must use an extended | |
11365 | opcode. If the address depends on the size of this | |
11366 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
11367 | use an extended opcode. We only check this when we are in |
11368 | the main relaxation loop, when SEC is NULL. */ | |
11369 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11370 | { | |
11371 | fragp->fr_subtype = | |
11372 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11373 | return 1; | |
11374 | } | |
11375 | ||
11376 | /* If we are about to mark a frag as extended because the value | |
11377 | is precisely maxtiny + 1, then there is a chance of an | |
11378 | infinite loop as in the following code: | |
11379 | la $4,foo | |
11380 | .skip 1020 | |
11381 | .align 2 | |
11382 | foo: | |
11383 | In this case when the la is extended, foo is 0x3fc bytes | |
11384 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11385 | the la must be extended. To avoid this loop, we mark the | |
11386 | frag as extended if it was small, and is about to become | |
11387 | extended with a value of maxtiny + 1. */ | |
11388 | if (val == ((maxtiny + 1) << op->shift) | |
11389 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11390 | && sec == NULL) | |
cc5703cd ILT |
11391 | { |
11392 | fragp->fr_subtype = | |
11393 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11394 | return 1; | |
11395 | } | |
11396 | } | |
41a0ed22 | 11397 | else if (symsec != absolute_section && sec != NULL) |
48401fcf | 11398 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
cc5703cd ILT |
11399 | |
11400 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11401 | || val < (mintiny << op->shift) | |
11402 | || val > (maxtiny << op->shift)) | |
11403 | return 1; | |
11404 | else | |
11405 | return 0; | |
11406 | } | |
11407 | ||
11408 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11409 | mips16, we are not really relaxing here, and the final size is | |
11410 | encoded in the subtype information. For the mips16, we have to | |
11411 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 11412 | |
0dd2d296 ILT |
11413 | /*ARGSUSED*/ |
11414 | int | |
11415 | md_estimate_size_before_relax (fragp, segtype) | |
11416 | fragS *fragp; | |
11417 | asection *segtype; | |
11418 | { | |
11419 | int change; | |
11420 | ||
cc5703cd ILT |
11421 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11422 | { | |
11423 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11424 | { | |
11425 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11426 | return 4; | |
11427 | } | |
11428 | else | |
11429 | { | |
11430 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11431 | return 2; | |
11432 | } | |
11433 | } | |
11434 | ||
d9aba805 | 11435 | if (mips_pic == NO_PIC) |
0dd2d296 | 11436 | { |
85ce5635 | 11437 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 11438 | } |
d9aba805 | 11439 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11440 | { |
46a92fde ILT |
11441 | symbolS *sym; |
11442 | asection *symsec; | |
11443 | ||
11444 | sym = fragp->fr_symbol; | |
11445 | ||
11446 | /* Handle the case of a symbol equated to another symbol. */ | |
11447 | while (sym->sy_value.X_op == O_symbol | |
11448 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
11449 | { | |
11450 | symbolS *n; | |
11451 | ||
11452 | /* It's possible to get a loop here in a badly written | |
11453 | program. */ | |
11454 | n = sym->sy_value.X_add_symbol; | |
11455 | if (n == sym) | |
11456 | break; | |
11457 | sym = n; | |
11458 | } | |
11459 | ||
11460 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
11461 | |
11462 | /* This must duplicate the test in adjust_reloc_syms. */ | |
11463 | change = (symsec != &bfd_und_section | |
11464 | && symsec != &bfd_abs_section | |
11465 | && ! bfd_is_com_section (symsec)); | |
11466 | } | |
d9aba805 ILT |
11467 | else |
11468 | abort (); | |
0dd2d296 ILT |
11469 | |
11470 | if (change) | |
11471 | { | |
11472 | /* Record the offset to the first reloc in the fr_opcode field. | |
11473 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11474 | must be expanded. */ | |
11475 | fragp->fr_opcode = (fragp->fr_literal | |
11476 | + fragp->fr_fix | |
11477 | - RELAX_OLD (fragp->fr_subtype) | |
11478 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11479 | /* FIXME: This really needs as_warn_where. */ | |
11480 | if (RELAX_WARN (fragp->fr_subtype)) | |
48401fcf | 11481 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); |
0dd2d296 ILT |
11482 | } |
11483 | ||
11484 | if (! change) | |
11485 | return 0; | |
11486 | else | |
11487 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11488 | } | |
11489 | ||
0d7f9025 ILT |
11490 | /* This is called to see whether a reloc against a defined symbol |
11491 | should be converted into a reloc against a section. Don't adjust | |
11492 | MIPS16 jump relocations, so we don't have to worry about the format | |
11493 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
11494 | mips16 symbols, so that the linker can find them if it needs to set |
11495 | up a stub. */ | |
0d7f9025 ILT |
11496 | |
11497 | int | |
11498 | mips_fix_adjustable (fixp) | |
11499 | fixS *fixp; | |
11500 | { | |
11501 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11502 | return 0; | |
7e656649 RH |
11503 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
11504 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11505 | return 0; | |
0d7f9025 ILT |
11506 | if (fixp->fx_addsy == NULL) |
11507 | return 1; | |
68952421 | 11508 | #ifdef OBJ_ELF |
0d7f9025 | 11509 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
11510 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
11511 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
11512 | return 0; |
11513 | #endif | |
11514 | return 1; | |
11515 | } | |
11516 | ||
0dd2d296 ILT |
11517 | /* Translate internal representation of relocation info to BFD target |
11518 | format. */ | |
11519 | ||
11520 | arelent ** | |
3d3c5039 ILT |
11521 | tc_gen_reloc (section, fixp) |
11522 | asection *section; | |
11523 | fixS *fixp; | |
11524 | { | |
0dd2d296 | 11525 | static arelent *retval[4]; |
3d3c5039 | 11526 | arelent *reloc; |
a8aed9dd | 11527 | bfd_reloc_code_real_type code; |
3d3c5039 | 11528 | |
0dd2d296 ILT |
11529 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
11530 | retval[1] = NULL; | |
3d3c5039 ILT |
11531 | |
11532 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11533 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
11534 | |
11535 | if (mips_pic == EMBEDDED_PIC | |
11536 | && SWITCH_TABLE (fixp)) | |
11537 | { | |
11538 | /* For a switch table entry we use a special reloc. The addend | |
11539 | is actually the difference between the reloc address and the | |
11540 | subtrahend. */ | |
11541 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 | 11542 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
48401fcf | 11543 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
1c803e52 ILT |
11544 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
11545 | } | |
ecd4ca1c ILT |
11546 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11547 | { | |
11548 | /* We use a special addend for an internal RELLO reloc. */ | |
11549 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11550 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11551 | else | |
11552 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11553 | } | |
11554 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11555 | { | |
11556 | assert (fixp->fx_next != NULL | |
11557 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11558 | /* We use a special addend for an internal RELHI reloc. The | |
11559 | reloc is relative to the RELLO; adjust the addend | |
11560 | accordingly. */ | |
11561 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11562 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
11563 | + fixp->fx_next->fx_where | |
11564 | - S_GET_VALUE (fixp->fx_subsy)); | |
11565 | else | |
11566 | reloc->addend = (fixp->fx_addnumber | |
11567 | + fixp->fx_next->fx_frag->fr_address | |
11568 | + fixp->fx_next->fx_where); | |
11569 | } | |
1c803e52 | 11570 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
11571 | reloc->addend = fixp->fx_addnumber; |
11572 | else | |
5b63f465 | 11573 | { |
1dc1e798 KR |
11574 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
11575 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11576 | handling. */ | |
11577 | reloc->addend = reloc->address; | |
11578 | else | |
11579 | reloc->addend = -reloc->address; | |
5b63f465 | 11580 | } |
0dd2d296 ILT |
11581 | |
11582 | /* If this is a variant frag, we may need to adjust the existing | |
11583 | reloc and generate a new one. */ | |
11584 | if (fixp->fx_frag->fr_opcode != NULL | |
11585 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11586 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
11587 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
11588 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11589 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11590 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11591 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
11592 | { |
11593 | arelent *reloc2; | |
11594 | ||
cc5703cd ILT |
11595 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
11596 | ||
0dd2d296 | 11597 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
11598 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
11599 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11600 | the second one handle all of them. */ | |
0dd2d296 ILT |
11601 | if (fixp->fx_next != NULL |
11602 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11603 | { | |
fb251650 ILT |
11604 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
11605 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11606 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11607 | && (fixp->fx_next->fx_r_type | |
11608 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11609 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11610 | && (fixp->fx_next->fx_r_type | |
11611 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
11612 | retval[0] = NULL; |
11613 | return retval; | |
11614 | } | |
11615 | ||
11616 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11617 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11618 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11619 | retval[2] = NULL; | |
11620 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11621 | reloc2->address = (reloc->address | |
11622 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11623 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11624 | reloc2->addend = fixp->fx_addnumber; | |
11625 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11626 | assert (reloc2->howto != NULL); | |
11627 | ||
11628 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11629 | { | |
11630 | arelent *reloc3; | |
11631 | ||
11632 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11633 | retval[3] = NULL; | |
11634 | *reloc3 = *reloc2; | |
11635 | reloc3->address += 4; | |
11636 | } | |
11637 | ||
d9aba805 | 11638 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11639 | { |
11640 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11641 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11642 | } | |
d9aba805 | 11643 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11644 | { |
fb251650 | 11645 | switch (fixp->fx_r_type) |
0dd2d296 | 11646 | { |
fb251650 ILT |
11647 | default: |
11648 | abort (); | |
11649 | case BFD_RELOC_MIPS_GOT16: | |
11650 | break; | |
11651 | case BFD_RELOC_MIPS_CALL16: | |
11652 | case BFD_RELOC_MIPS_GOT_LO16: | |
11653 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11654 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11655 | break; |
0dd2d296 ILT |
11656 | } |
11657 | } | |
d9aba805 ILT |
11658 | else |
11659 | abort (); | |
0dd2d296 ILT |
11660 | } |
11661 | ||
7e656649 RH |
11662 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry |
11663 | to be used in the relocation's section offset. */ | |
11664 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11665 | { | |
11666 | reloc->address = reloc->addend; | |
11667 | reloc->addend = 0; | |
11668 | } | |
11669 | ||
a8aed9dd ILT |
11670 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11671 | fixup_segment converted a non-PC relative reloc into a PC | |
11672 | relative reloc. In such a case, we need to convert the reloc | |
11673 | code. */ | |
11674 | code = fixp->fx_r_type; | |
11675 | if (fixp->fx_pcrel) | |
11676 | { | |
11677 | switch (code) | |
11678 | { | |
11679 | case BFD_RELOC_8: | |
11680 | code = BFD_RELOC_8_PCREL; | |
11681 | break; | |
11682 | case BFD_RELOC_16: | |
11683 | code = BFD_RELOC_16_PCREL; | |
11684 | break; | |
11685 | case BFD_RELOC_32: | |
11686 | code = BFD_RELOC_32_PCREL; | |
11687 | break; | |
bf39474f ILT |
11688 | case BFD_RELOC_64: |
11689 | code = BFD_RELOC_64_PCREL; | |
11690 | break; | |
a8aed9dd ILT |
11691 | case BFD_RELOC_8_PCREL: |
11692 | case BFD_RELOC_16_PCREL: | |
11693 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11694 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11695 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11696 | case BFD_RELOC_PCREL_HI16_S: |
11697 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11698 | break; |
11699 | default: | |
11700 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11701 | _("Cannot make %s relocation PC relative"), |
a8aed9dd ILT |
11702 | bfd_get_reloc_code_name (code)); |
11703 | } | |
11704 | } | |
11705 | ||
d9aba805 ILT |
11706 | /* To support a PC relative reloc when generating embedded PIC code |
11707 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11708 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11709 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11710 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11711 | && mips_pic != EMBEDDED_PIC) |
11712 | reloc->howto = NULL; | |
11713 | else | |
a8aed9dd | 11714 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11715 | |
52aa70b5 JW |
11716 | if (reloc->howto == NULL) |
11717 | { | |
11718 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11719 | _("Can not represent %s relocation in this object file format"), |
a8aed9dd | 11720 | bfd_get_reloc_code_name (code)); |
0dd2d296 | 11721 | retval[0] = NULL; |
52aa70b5 | 11722 | } |
3d3c5039 | 11723 | |
0dd2d296 | 11724 | return retval; |
3d3c5039 ILT |
11725 | } |
11726 | ||
cc5703cd ILT |
11727 | /* Relax a machine dependent frag. This returns the amount by which |
11728 | the current size of the frag should change. */ | |
11729 | ||
11730 | int | |
11731 | mips_relax_frag (fragp, stretch) | |
11732 | fragS *fragp; | |
11733 | long stretch; | |
11734 | { | |
11735 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11736 | return 0; | |
11737 | ||
11738 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11739 | { | |
11740 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11741 | return 0; | |
11742 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11743 | return 2; | |
11744 | } | |
11745 | else | |
11746 | { | |
11747 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11748 | return 0; | |
11749 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11750 | return -2; | |
11751 | } | |
11752 | ||
11753 | return 0; | |
11754 | } | |
11755 | ||
0dd2d296 ILT |
11756 | /* Convert a machine dependent frag. */ |
11757 | ||
11758 | void | |
11759 | md_convert_frag (abfd, asec, fragp) | |
11760 | bfd *abfd; | |
11761 | segT asec; | |
11762 | fragS *fragp; | |
3d3c5039 | 11763 | { |
0dd2d296 ILT |
11764 | int old, new; |
11765 | char *fixptr; | |
3d3c5039 | 11766 | |
cc5703cd ILT |
11767 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11768 | { | |
11769 | int type; | |
11770 | register const struct mips16_immed_operand *op; | |
11771 | boolean small, ext; | |
11772 | offsetT val; | |
11773 | bfd_byte *buf; | |
11774 | unsigned long insn; | |
11775 | boolean use_extend; | |
11776 | unsigned short extend; | |
11777 | ||
11778 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11779 | op = mips16_immed_operands; | |
11780 | while (op->type != type) | |
11781 | ++op; | |
11782 | ||
11783 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11784 | { | |
11785 | small = false; | |
11786 | ext = true; | |
11787 | } | |
11788 | else | |
11789 | { | |
11790 | small = true; | |
11791 | ext = false; | |
11792 | } | |
11793 | ||
b637f306 | 11794 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11795 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11796 | if (op->pcrel) |
11797 | { | |
11798 | addressT addr; | |
11799 | ||
a677feeb ILT |
11800 | addr = fragp->fr_address + fragp->fr_fix; |
11801 | ||
11802 | /* The rules for the base address of a PC relative reloc are | |
11803 | complicated; see mips16_extended_frag. */ | |
11804 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11805 | { |
11806 | addr += 2; | |
319305a7 ILT |
11807 | if (ext) |
11808 | addr += 2; | |
fbcfacb7 ILT |
11809 | /* Ignore the low bit in the target, since it will be |
11810 | set for a text label. */ | |
11811 | if ((val & 1) != 0) | |
11812 | --val; | |
11813 | } | |
a677feeb ILT |
11814 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11815 | addr -= 4; | |
11816 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11817 | addr -= 2; | |
11818 | ||
cc5703cd ILT |
11819 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11820 | val -= addr; | |
a677feeb ILT |
11821 | |
11822 | /* Make sure the section winds up with the alignment we have | |
11823 | assumed. */ | |
11824 | if (op->shift > 0) | |
11825 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11826 | } |
11827 | ||
035936da ILT |
11828 | if (ext |
11829 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11830 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11831 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11832 | _("extended instruction in delay slot")); |
035936da | 11833 | |
cc5703cd ILT |
11834 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
11835 | ||
b9129c6f ILT |
11836 | if (target_big_endian) |
11837 | insn = bfd_getb16 (buf); | |
11838 | else | |
11839 | insn = bfd_getl16 (buf); | |
cc5703cd | 11840 | |
31a2c6ff ILT |
11841 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
11842 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11843 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
11844 | |
11845 | if (use_extend) | |
11846 | { | |
11847 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11848 | fragp->fr_fix += 2; | |
11849 | buf += 2; | |
11850 | } | |
3d3c5039 | 11851 | |
cc5703cd ILT |
11852 | md_number_to_chars (buf, insn, 2); |
11853 | fragp->fr_fix += 2; | |
11854 | buf += 2; | |
11855 | } | |
11856 | else | |
11857 | { | |
11858 | if (fragp->fr_opcode == NULL) | |
11859 | return; | |
0dd2d296 | 11860 | |
cc5703cd ILT |
11861 | old = RELAX_OLD (fragp->fr_subtype); |
11862 | new = RELAX_NEW (fragp->fr_subtype); | |
11863 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 11864 | |
cc5703cd ILT |
11865 | if (new > 0) |
11866 | memcpy (fixptr - old, fixptr, new); | |
11867 | ||
11868 | fragp->fr_fix += new - old; | |
11869 | } | |
0dd2d296 | 11870 | } |
becfe05e | 11871 | |
fbcfacb7 ILT |
11872 | #ifdef OBJ_ELF |
11873 | ||
11874 | /* This function is called after the relocs have been generated. | |
11875 | We've been storing mips16 text labels as odd. Here we convert them | |
11876 | back to even for the convenience of the debugger. */ | |
11877 | ||
11878 | void | |
11879 | mips_frob_file_after_relocs () | |
11880 | { | |
11881 | asymbol **syms; | |
11882 | unsigned int count, i; | |
11883 | ||
11884 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11885 | return; | |
11886 | ||
11887 | syms = bfd_get_outsymbols (stdoutput); | |
11888 | count = bfd_get_symcount (stdoutput); | |
11889 | for (i = 0; i < count; i++, syms++) | |
11890 | { | |
11891 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11892 | && ((*syms)->value & 1) != 0) | |
11893 | { | |
11894 | (*syms)->value &= ~1; | |
11895 | /* If the symbol has an odd size, it was probably computed | |
11896 | incorrectly, so adjust that as well. */ | |
11897 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11898 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11899 | } | |
11900 | } | |
11901 | } | |
11902 | ||
11903 | #endif | |
11904 | ||
becfe05e ILT |
11905 | /* This function is called whenever a label is defined. It is used |
11906 | when handling branch delays; if a branch has a label, we assume we | |
11907 | can not move it. */ | |
11908 | ||
11909 | void | |
11910 | mips_define_label (sym) | |
11911 | symbolS *sym; | |
11912 | { | |
fbcfacb7 ILT |
11913 | struct insn_label_list *l; |
11914 | ||
11915 | if (free_insn_labels == NULL) | |
11916 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11917 | else | |
11918 | { | |
11919 | l = free_insn_labels; | |
11920 | free_insn_labels = l->next; | |
11921 | } | |
11922 | ||
11923 | l->label = sym; | |
11924 | l->next = insn_labels; | |
11925 | insn_labels = l; | |
becfe05e | 11926 | } |
3d3c5039 | 11927 | \f |
739708fa | 11928 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11929 | |
0dd2d296 | 11930 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11931 | |
11932 | void | |
11933 | mips_elf_final_processing () | |
11934 | { | |
87178180 ILT |
11935 | /* Write out the register information. */ |
11936 | if (! mips_64) | |
11937 | { | |
11938 | Elf32_RegInfo s; | |
11939 | ||
11940 | s.ri_gprmask = mips_gprmask; | |
11941 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11942 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11943 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11944 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11945 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11946 | ||
11947 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11948 | ((Elf32_External_RegInfo *) | |
11949 | mips_regmask_frag)); | |
11950 | } | |
11951 | else | |
11952 | { | |
11953 | Elf64_Internal_RegInfo s; | |
11954 | ||
11955 | s.ri_gprmask = mips_gprmask; | |
11956 | s.ri_pad = 0; | |
11957 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11958 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11959 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11960 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11961 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11962 | ||
11963 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11964 | ((Elf64_External_RegInfo *) | |
11965 | mips_regmask_frag)); | |
11966 | } | |
0dd2d296 ILT |
11967 | |
11968 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11969 | sort of BFD interface for this. */ | |
11970 | if (mips_any_noreorder) | |
11971 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11972 | if (mips_pic != NO_PIC) |
0dd2d296 | 11973 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11974 | } |
11975 | ||
739708fa | 11976 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11977 | \f |
3d3c5039 ILT |
11978 | /* These functions should really be defined by the object file format, |
11979 | since they are related to debugging information. However, this | |
11980 | code has to work for the a.out format, which does not define them, | |
11981 | so we provide simple versions here. These don't actually generate | |
11982 | any debugging information, but they do simple checking and someday | |
11983 | somebody may make them useful. */ | |
11984 | ||
670a50eb ILT |
11985 | typedef struct loc |
11986 | { | |
11987 | struct loc *loc_next; | |
11988 | unsigned long loc_fileno; | |
11989 | unsigned long loc_lineno; | |
11990 | unsigned long loc_offset; | |
11991 | unsigned short loc_delta; | |
11992 | unsigned short loc_count; | |
3d3c5039 | 11993 | #if 0 |
670a50eb | 11994 | fragS *loc_frag; |
3d3c5039 | 11995 | #endif |
670a50eb ILT |
11996 | } |
11997 | locS; | |
3d3c5039 | 11998 | |
670a50eb ILT |
11999 | typedef struct proc |
12000 | { | |
3d3c5039 ILT |
12001 | struct proc *proc_next; |
12002 | struct symbol *proc_isym; | |
12003 | struct symbol *proc_end; | |
12004 | unsigned long proc_reg_mask; | |
12005 | unsigned long proc_reg_offset; | |
12006 | unsigned long proc_fpreg_mask; | |
12007 | unsigned long proc_fpreg_offset; | |
12008 | unsigned long proc_frameoffset; | |
12009 | unsigned long proc_framereg; | |
12010 | unsigned long proc_pcreg; | |
12011 | locS *proc_iline; | |
12012 | struct file *proc_file; | |
12013 | int proc_index; | |
670a50eb ILT |
12014 | } |
12015 | procS; | |
3d3c5039 | 12016 | |
670a50eb ILT |
12017 | typedef struct file |
12018 | { | |
3d3c5039 ILT |
12019 | struct file *file_next; |
12020 | unsigned long file_fileno; | |
12021 | struct symbol *file_symbol; | |
12022 | struct symbol *file_end; | |
12023 | struct proc *file_proc; | |
12024 | int file_numprocs; | |
670a50eb ILT |
12025 | } |
12026 | fileS; | |
3d3c5039 ILT |
12027 | |
12028 | static struct obstack proc_frags; | |
12029 | static procS *proc_lastP; | |
12030 | static procS *proc_rootP; | |
12031 | static int numprocs; | |
12032 | ||
12033 | static void | |
12034 | md_obj_begin () | |
12035 | { | |
670a50eb | 12036 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
12037 | } |
12038 | ||
12039 | static void | |
12040 | md_obj_end () | |
12041 | { | |
12042 | /* check for premature end, nesting errors, etc */ | |
12043 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
48401fcf | 12044 | as_warn (_("missing `.end' at end of assembly")); |
3d3c5039 ILT |
12045 | } |
12046 | ||
3d3c5039 ILT |
12047 | static long |
12048 | get_number () | |
12049 | { | |
670a50eb ILT |
12050 | int negative = 0; |
12051 | long val = 0; | |
3d3c5039 | 12052 | |
670a50eb ILT |
12053 | if (*input_line_pointer == '-') |
12054 | { | |
12055 | ++input_line_pointer; | |
12056 | negative = 1; | |
3d3c5039 | 12057 | } |
670a50eb | 12058 | if (!isdigit (*input_line_pointer)) |
48401fcf | 12059 | as_bad (_("Expected simple number.")); |
670a50eb ILT |
12060 | if (input_line_pointer[0] == '0') |
12061 | { | |
12062 | if (input_line_pointer[1] == 'x') | |
12063 | { | |
12064 | input_line_pointer += 2; | |
12065 | while (isxdigit (*input_line_pointer)) | |
12066 | { | |
12067 | val <<= 4; | |
3a762a0b | 12068 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 12069 | } |
670a50eb ILT |
12070 | return negative ? -val : val; |
12071 | } | |
12072 | else | |
12073 | { | |
12074 | ++input_line_pointer; | |
12075 | while (isdigit (*input_line_pointer)) | |
12076 | { | |
12077 | val <<= 3; | |
12078 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 12079 | } |
670a50eb | 12080 | return negative ? -val : val; |
3d3c5039 ILT |
12081 | } |
12082 | } | |
670a50eb ILT |
12083 | if (!isdigit (*input_line_pointer)) |
12084 | { | |
48401fcf | 12085 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
670a50eb | 12086 | *input_line_pointer, *input_line_pointer); |
48401fcf | 12087 | as_warn (_("Invalid number")); |
670a50eb | 12088 | return -1; |
3d3c5039 | 12089 | } |
670a50eb ILT |
12090 | while (isdigit (*input_line_pointer)) |
12091 | { | |
12092 | val *= 10; | |
12093 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 12094 | } |
670a50eb | 12095 | return negative ? -val : val; |
3d3c5039 ILT |
12096 | } |
12097 | ||
12098 | /* The .file directive; just like the usual .file directive, but there | |
12099 | is an initial number which is the ECOFF file index. */ | |
12100 | ||
12101 | static void | |
12102 | s_file (x) | |
12103 | int x; | |
12104 | { | |
670a50eb | 12105 | int line; |
3d3c5039 | 12106 | |
670a50eb | 12107 | line = get_number (); |
9a7d824a | 12108 | s_app_file (0); |
3d3c5039 ILT |
12109 | } |
12110 | ||
12111 | ||
12112 | /* The .end directive. */ | |
12113 | ||
12114 | static void | |
12115 | s_mipsend (x) | |
12116 | int x; | |
12117 | { | |
670a50eb ILT |
12118 | symbolS *p; |
12119 | ||
12120 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
12121 | { | |
12122 | p = get_symbol (); | |
12123 | demand_empty_rest_of_line (); | |
12124 | } | |
12125 | else | |
12126 | p = NULL; | |
12127 | if (now_seg != text_section) | |
48401fcf | 12128 | as_warn (_(".end not in text section")); |
670a50eb ILT |
12129 | if (!proc_lastP) |
12130 | { | |
48401fcf | 12131 | as_warn (_(".end and no .ent seen yet.")); |
670a50eb | 12132 | return; |
3d3c5039 ILT |
12133 | } |
12134 | ||
670a50eb ILT |
12135 | if (p != NULL) |
12136 | { | |
12137 | assert (S_GET_NAME (p)); | |
12138 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
48401fcf | 12139 | as_warn (_(".end symbol does not match .ent symbol.")); |
3d3c5039 ILT |
12140 | } |
12141 | ||
670a50eb | 12142 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
12143 | } |
12144 | ||
12145 | /* The .aent and .ent directives. */ | |
12146 | ||
12147 | static void | |
12148 | s_ent (aent) | |
12149 | int aent; | |
12150 | { | |
670a50eb ILT |
12151 | int number = 0; |
12152 | procS *procP; | |
12153 | symbolS *symbolP; | |
12154 | ||
12155 | symbolP = get_symbol (); | |
12156 | if (*input_line_pointer == ',') | |
12157 | input_line_pointer++; | |
dd3f1f76 | 12158 | SKIP_WHITESPACE (); |
670a50eb ILT |
12159 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
12160 | number = get_number (); | |
12161 | if (now_seg != text_section) | |
48401fcf | 12162 | as_warn (_(".ent or .aent not in text section.")); |
670a50eb ILT |
12163 | |
12164 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
48401fcf | 12165 | as_warn (_("missing `.end'")); |
670a50eb ILT |
12166 | |
12167 | if (!aent) | |
12168 | { | |
12169 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
12170 | procP->proc_isym = symbolP; | |
12171 | procP->proc_reg_mask = 0; | |
12172 | procP->proc_reg_offset = 0; | |
12173 | procP->proc_fpreg_mask = 0; | |
12174 | procP->proc_fpreg_offset = 0; | |
12175 | procP->proc_frameoffset = 0; | |
12176 | procP->proc_framereg = 0; | |
12177 | procP->proc_pcreg = 0; | |
12178 | procP->proc_end = NULL; | |
12179 | procP->proc_next = NULL; | |
12180 | if (proc_lastP) | |
12181 | proc_lastP->proc_next = procP; | |
12182 | else | |
12183 | proc_rootP = procP; | |
12184 | proc_lastP = procP; | |
6b34ac5a ILT |
12185 | |
12186 | symbolP->bsym->flags |= BSF_FUNCTION; | |
12187 | ||
670a50eb | 12188 | numprocs++; |
3d3c5039 | 12189 | } |
670a50eb | 12190 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
12191 | } |
12192 | ||
12193 | /* The .frame directive. */ | |
12194 | ||
88225433 | 12195 | #if 0 |
3d3c5039 ILT |
12196 | static void |
12197 | s_frame (x) | |
670a50eb | 12198 | int x; |
3d3c5039 | 12199 | { |
670a50eb ILT |
12200 | char str[100]; |
12201 | symbolS *symP; | |
12202 | int frame_reg; | |
12203 | int frame_off; | |
12204 | int pcreg; | |
12205 | ||
0dd2d296 | 12206 | frame_reg = tc_get_register (1); |
670a50eb ILT |
12207 | if (*input_line_pointer == ',') |
12208 | input_line_pointer++; | |
5ac34ac3 | 12209 | frame_off = get_absolute_expression (); |
670a50eb ILT |
12210 | if (*input_line_pointer == ',') |
12211 | input_line_pointer++; | |
0dd2d296 | 12212 | pcreg = tc_get_register (0); |
670a50eb ILT |
12213 | |
12214 | /* bob third eye */ | |
12215 | assert (proc_rootP); | |
12216 | proc_rootP->proc_framereg = frame_reg; | |
12217 | proc_rootP->proc_frameoffset = frame_off; | |
12218 | proc_rootP->proc_pcreg = pcreg; | |
12219 | /* bob macho .frame */ | |
12220 | ||
12221 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 12222 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
12223 | { |
12224 | if (!proc_lastP) | |
48401fcf | 12225 | as_warn (_("No .ent for .frame to use.")); |
670a50eb ILT |
12226 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); |
12227 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
12228 | S_SET_TYPE (symP, N_RMASK); | |
12229 | S_SET_OTHER (symP, 0); | |
12230 | S_SET_DESC (symP, 0); | |
12231 | symP->sy_forward = proc_lastP->proc_isym; | |
12232 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 12233 | } |
670a50eb | 12234 | demand_empty_rest_of_line (); |
3d3c5039 | 12235 | } |
88225433 | 12236 | #endif |
3d3c5039 ILT |
12237 | |
12238 | /* The .fmask and .mask directives. */ | |
12239 | ||
88225433 | 12240 | #if 0 |
3d3c5039 ILT |
12241 | static void |
12242 | s_mask (reg_type) | |
12243 | char reg_type; | |
12244 | { | |
670a50eb ILT |
12245 | char str[100], *strP; |
12246 | symbolS *symP; | |
12247 | int i; | |
12248 | unsigned int mask; | |
12249 | int off; | |
12250 | ||
12251 | mask = get_number (); | |
12252 | if (*input_line_pointer == ',') | |
12253 | input_line_pointer++; | |
12254 | off = get_absolute_expression (); | |
12255 | ||
12256 | /* bob only for coff */ | |
12257 | assert (proc_rootP); | |
12258 | if (reg_type == 'F') | |
12259 | { | |
12260 | proc_rootP->proc_fpreg_mask = mask; | |
12261 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 12262 | } |
670a50eb ILT |
12263 | else |
12264 | { | |
12265 | proc_rootP->proc_reg_mask = mask; | |
12266 | proc_rootP->proc_reg_offset = off; | |
12267 | } | |
12268 | ||
12269 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 12270 | |
670a50eb ILT |
12271 | /* We don't have to write out a mask stab if no saved regs. */ |
12272 | if (!(mask == 0)) | |
12273 | { | |
12274 | if (!proc_lastP) | |
48401fcf | 12275 | as_warn (_("No .ent for .mask to use.")); |
670a50eb ILT |
12276 | strP = str; |
12277 | for (i = 0; i < 32; i++) | |
12278 | { | |
12279 | if (mask % 2) | |
12280 | { | |
12281 | sprintf (strP, "%c%d,", reg_type, i); | |
12282 | strP += strlen (strP); | |
12283 | } | |
3d3c5039 | 12284 | mask /= 2; |
670a50eb ILT |
12285 | } |
12286 | sprintf (strP, ";%d,", off); | |
12287 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
12288 | S_SET_TYPE (symP, N_RMASK); | |
12289 | S_SET_OTHER (symP, 0); | |
12290 | S_SET_DESC (symP, 0); | |
12291 | symP->sy_forward = proc_lastP->proc_isym; | |
12292 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 12293 | } |
3d3c5039 | 12294 | } |
88225433 | 12295 | #endif |
3d3c5039 ILT |
12296 | |
12297 | /* The .loc directive. */ | |
12298 | ||
88225433 | 12299 | #if 0 |
3d3c5039 ILT |
12300 | static void |
12301 | s_loc (x) | |
12302 | int x; | |
12303 | { | |
670a50eb ILT |
12304 | symbolS *symbolP; |
12305 | int lineno; | |
12306 | int addroff; | |
3d3c5039 | 12307 | |
670a50eb | 12308 | assert (now_seg == text_section); |
3d3c5039 | 12309 | |
670a50eb | 12310 | lineno = get_number (); |
87e48495 | 12311 | addroff = frag_now_fix (); |
3d3c5039 | 12312 | |
670a50eb ILT |
12313 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
12314 | S_SET_TYPE (symbolP, N_SLINE); | |
12315 | S_SET_OTHER (symbolP, 0); | |
12316 | S_SET_DESC (symbolP, lineno); | |
12317 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 12318 | } |
88225433 | 12319 | #endif |