Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
252b5132 RH |
139 | /* This is the set of options which may be modified by the .set |
140 | pseudo-op. We use a struct so that .set push and .set pop are more | |
141 | reliable. */ | |
142 | ||
e972090a NC |
143 | struct mips_set_options |
144 | { | |
252b5132 RH |
145 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
146 | if it has not been initialized. Changed by `.set mipsN', and the | |
147 | -mipsN command line option, and the default CPU. */ | |
148 | int isa; | |
1f25f5d3 CD |
149 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
150 | if they have not been initialized. Changed by `.set <asename>', by | |
151 | command line options, and based on the default architecture. */ | |
152 | int ase_mips3d; | |
deec1734 | 153 | int ase_mdmx; |
252b5132 RH |
154 | /* Whether we are assembling for the mips16 processor. 0 if we are |
155 | not, 1 if we are, and -1 if the value has not been initialized. | |
156 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
157 | -nomips16 command line options, and the default CPU. */ | |
158 | int mips16; | |
159 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
160 | reorder' and `.set noreorder'. */ | |
161 | int noreorder; | |
162 | /* Non-zero if we should not permit the $at ($1) register to be used | |
163 | in instructions. Changed by `.set at' and `.set noat'. */ | |
164 | int noat; | |
165 | /* Non-zero if we should warn when a macro instruction expands into | |
166 | more than one machine instruction. Changed by `.set nomacro' and | |
167 | `.set macro'. */ | |
168 | int warn_about_macros; | |
169 | /* Non-zero if we should not move instructions. Changed by `.set | |
170 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
171 | int nomove; | |
172 | /* Non-zero if we should not optimize branches by moving the target | |
173 | of the branch into the delay slot. Actually, we don't perform | |
174 | this optimization anyhow. Changed by `.set bopt' and `.set | |
175 | nobopt'. */ | |
176 | int nobopt; | |
177 | /* Non-zero if we should not autoextend mips16 instructions. | |
178 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
179 | int noautoextend; | |
a325df1d TS |
180 | /* Restrict general purpose registers and floating point registers |
181 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
182 | is passed but can changed if the assembler code uses .set mipsN. */ | |
183 | int gp32; | |
184 | int fp32; | |
fef14a42 TS |
185 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
186 | command line option, and the default CPU. */ | |
187 | int arch; | |
252b5132 RH |
188 | }; |
189 | ||
a325df1d | 190 | /* True if -mgp32 was passed. */ |
a8e8e863 | 191 | static int file_mips_gp32 = -1; |
a325df1d TS |
192 | |
193 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 194 | static int file_mips_fp32 = -1; |
a325df1d | 195 | |
252b5132 | 196 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 197 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 198 | -1 to indicate that they have not been initialized. */ |
252b5132 | 199 | |
e972090a NC |
200 | static struct mips_set_options mips_opts = |
201 | { | |
fef14a42 | 202 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 203 | }; |
252b5132 RH |
204 | |
205 | /* These variables are filled in with the masks of registers used. | |
206 | The object format code reads them and puts them in the appropriate | |
207 | place. */ | |
208 | unsigned long mips_gprmask; | |
209 | unsigned long mips_cprmask[4]; | |
210 | ||
211 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 212 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 213 | |
a4672219 TS |
214 | /* True if -mips16 was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mips16; | |
217 | ||
1f25f5d3 CD |
218 | /* True if -mips3d was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips3d; | |
221 | ||
deec1734 CD |
222 | /* True if -mdmx was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mdmx; | |
225 | ||
ec68c924 | 226 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 227 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 228 | static const char *mips_arch_string; |
ec68c924 EC |
229 | |
230 | /* The argument of the -mtune= flag. The architecture for which we | |
231 | are optimizing. */ | |
232 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 233 | static const char *mips_tune_string; |
ec68c924 | 234 | |
316f5878 | 235 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
236 | static int mips_32bitmode = 0; |
237 | ||
316f5878 RS |
238 | /* True if the given ABI requires 32-bit registers. */ |
239 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
240 | ||
241 | /* Likewise 64-bit registers. */ | |
242 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
243 | ((ABI) == N32_ABI \ | |
244 | || (ABI) == N64_ABI \ | |
245 | || (ABI) == O64_ABI) | |
246 | ||
bdaaa2e1 | 247 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 248 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
249 | (ISA) == ISA_MIPS3 \ |
250 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 251 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 252 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 253 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
254 | ) |
255 | ||
af7ee8bf CD |
256 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
257 | instructions. */ | |
258 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 259 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
260 | ) |
261 | ||
262 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
263 | instructions. */ | |
264 | #define ISA_HAS_ROR(ISA) ( \ | |
265 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 266 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
267 | ) |
268 | ||
e013f690 | 269 | #define HAVE_32BIT_GPRS \ |
316f5878 | 270 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 271 | |
e013f690 | 272 | #define HAVE_32BIT_FPRS \ |
316f5878 | 273 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
274 | |
275 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
276 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
277 | ||
316f5878 | 278 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 279 | |
316f5878 | 280 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 281 | |
3b91255e RS |
282 | /* True if relocations are stored in-place. */ |
283 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
284 | ||
3e722fb5 | 285 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
286 | #define HAVE_32BIT_ADDRESSES \ |
287 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
288 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
289 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
290 | |
291 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 292 | |
b7c7d6c1 TS |
293 | /* Addresses are loaded in different ways, depending on the address size |
294 | in use. The n32 ABI Documentation also mandates the use of additions | |
295 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 296 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 297 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
298 | |
299 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 300 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
301 | |
302 | #define ADDRESS_LOAD_INSN \ | |
303 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
304 | ||
305 | #define ADDRESS_STORE_INSN \ | |
306 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
307 | ||
a4672219 | 308 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
309 | #define CPU_HAS_MIPS16(cpu) \ |
310 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
311 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 312 | |
1f25f5d3 CD |
313 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
314 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
315 | ) | |
316 | ||
deec1734 | 317 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 318 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
319 | ) |
320 | ||
60b63b72 RS |
321 | /* True if CPU has a dror instruction. */ |
322 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
323 | ||
324 | /* True if CPU has a ror instruction. */ | |
325 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
326 | ||
c8978940 CD |
327 | /* True if mflo and mfhi can be immediately followed by instructions |
328 | which write to the HI and LO registers. | |
329 | ||
330 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
331 | (at least) two instructions between the reads of HI/LO and | |
332 | instructions which write them, and later ISAs do not. Contradicting | |
333 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
334 | the UM for the NEC Vr5000) document needing the instructions between | |
335 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
336 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
337 | earlier-ISA CPUs for which CPU documentation declares that the | |
338 | instructions are really interlocked. */ | |
339 | #define hilo_interlocks \ | |
340 | (mips_opts.isa == ISA_MIPS32 \ | |
341 | || mips_opts.isa == ISA_MIPS32R2 \ | |
342 | || mips_opts.isa == ISA_MIPS64 \ | |
343 | || mips_opts.isa == ISA_MIPS64R2 \ | |
344 | || mips_opts.arch == CPU_R4010 \ | |
345 | || mips_opts.arch == CPU_R10000 \ | |
346 | || mips_opts.arch == CPU_R12000 \ | |
347 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
348 | || mips_opts.arch == CPU_VR5500 \ |
349 | ) | |
252b5132 RH |
350 | |
351 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
352 | from the GPRs after they are loaded from memory, and thus does not |
353 | require nops to be inserted. This applies to instructions marked | |
354 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
355 | level I. */ | |
252b5132 | 356 | #define gpr_interlocks \ |
e7af610e | 357 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 358 | || mips_opts.arch == CPU_R3900) |
252b5132 | 359 | |
81912461 ILT |
360 | /* Whether the processor uses hardware interlocks to avoid delays |
361 | required by coprocessor instructions, and thus does not require | |
362 | nops to be inserted. This applies to instructions marked | |
363 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
364 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
365 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
366 | levels I, II, and III. */ | |
bdaaa2e1 | 367 | /* Itbl support may require additional care here. */ |
81912461 ILT |
368 | #define cop_interlocks \ |
369 | ((mips_opts.isa != ISA_MIPS1 \ | |
370 | && mips_opts.isa != ISA_MIPS2 \ | |
371 | && mips_opts.isa != ISA_MIPS3) \ | |
372 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
373 | ) |
374 | ||
375 | /* Whether the processor uses hardware interlocks to protect reads | |
376 | from coprocessor registers after they are loaded from memory, and | |
377 | thus does not require nops to be inserted. This applies to | |
378 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
379 | requires at MIPS ISA level I. */ | |
380 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 381 | |
6b76fefe CM |
382 | /* Is this a mfhi or mflo instruction? */ |
383 | #define MF_HILO_INSN(PINFO) \ | |
384 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
385 | ||
252b5132 RH |
386 | /* MIPS PIC level. */ |
387 | ||
a161fe53 | 388 | enum mips_pic_level mips_pic; |
252b5132 | 389 | |
c9914766 | 390 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 391 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 392 | static int mips_big_got = 0; |
252b5132 RH |
393 | |
394 | /* 1 if trap instructions should used for overflow rather than break | |
395 | instructions. */ | |
c9914766 | 396 | static int mips_trap = 0; |
252b5132 | 397 | |
119d663a | 398 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 399 | by assembling two single width halves into two single width floating |
119d663a NC |
400 | point registers which just happen to alias the double width destination |
401 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 402 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
403 | automatically at assemble time. */ |
404 | static int mips_disable_float_construction; | |
405 | ||
252b5132 RH |
406 | /* Non-zero if any .set noreorder directives were used. */ |
407 | ||
408 | static int mips_any_noreorder; | |
409 | ||
6b76fefe CM |
410 | /* Non-zero if nops should be inserted when the register referenced in |
411 | an mfhi/mflo instruction is read in the next two instructions. */ | |
412 | static int mips_7000_hilo_fix; | |
413 | ||
252b5132 | 414 | /* The size of the small data section. */ |
156c2f8b | 415 | static unsigned int g_switch_value = 8; |
252b5132 RH |
416 | /* Whether the -G option was used. */ |
417 | static int g_switch_seen = 0; | |
418 | ||
419 | #define N_RMASK 0xc4 | |
420 | #define N_VFP 0xd4 | |
421 | ||
422 | /* If we can determine in advance that GP optimization won't be | |
423 | possible, we can skip the relaxation stuff that tries to produce | |
424 | GP-relative references. This makes delay slot optimization work | |
425 | better. | |
426 | ||
427 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
428 | gcc output. It needs to guess right for gcc, otherwise gcc |
429 | will put what it thinks is a GP-relative instruction in a branch | |
430 | delay slot. | |
252b5132 RH |
431 | |
432 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
433 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 434 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
435 | |
436 | /* handle of the OPCODE hash table */ | |
437 | static struct hash_control *op_hash = NULL; | |
438 | ||
439 | /* The opcode hash table we use for the mips16. */ | |
440 | static struct hash_control *mips16_op_hash = NULL; | |
441 | ||
442 | /* This array holds the chars that always start a comment. If the | |
443 | pre-processor is disabled, these aren't very useful */ | |
444 | const char comment_chars[] = "#"; | |
445 | ||
446 | /* This array holds the chars that only start a comment at the beginning of | |
447 | a line. If the line seems to have the form '# 123 filename' | |
448 | .line and .file directives will appear in the pre-processed output */ | |
449 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
450 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 451 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
452 | /* Also note that C style comments are always supported. */ |
453 | const char line_comment_chars[] = "#"; | |
454 | ||
bdaaa2e1 | 455 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 456 | const char line_separator_chars[] = ";"; |
252b5132 RH |
457 | |
458 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
459 | const char EXP_CHARS[] = "eE"; | |
460 | ||
461 | /* Chars that mean this number is a floating point constant */ | |
462 | /* As in 0f12.456 */ | |
463 | /* or 0d1.2345e12 */ | |
464 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
465 | ||
466 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
467 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
468 | but nothing is ideal around here. | |
469 | */ | |
470 | ||
471 | static char *insn_error; | |
472 | ||
473 | static int auto_align = 1; | |
474 | ||
475 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
476 | offset in the stack frame from which to restore the $gp register. | |
477 | This is set by the .cprestore pseudo-op, and saved in this | |
478 | variable. */ | |
479 | static offsetT mips_cprestore_offset = -1; | |
480 | ||
67c1ffbe | 481 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 482 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 483 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
484 | static offsetT mips_cpreturn_offset = -1; |
485 | static int mips_cpreturn_register = -1; | |
486 | static int mips_gp_register = GP; | |
def2e0dd | 487 | static int mips_gprel_offset = 0; |
6478892d | 488 | |
7a621144 DJ |
489 | /* Whether mips_cprestore_offset has been set in the current function |
490 | (or whether it has already been warned about, if not). */ | |
491 | static int mips_cprestore_valid = 0; | |
492 | ||
252b5132 RH |
493 | /* This is the register which holds the stack frame, as set by the |
494 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
495 | static int mips_frame_reg = SP; | |
496 | ||
7a621144 DJ |
497 | /* Whether mips_frame_reg has been set in the current function |
498 | (or whether it has already been warned about, if not). */ | |
499 | static int mips_frame_reg_valid = 0; | |
500 | ||
252b5132 RH |
501 | /* To output NOP instructions correctly, we need to keep information |
502 | about the previous two instructions. */ | |
503 | ||
504 | /* Whether we are optimizing. The default value of 2 means to remove | |
505 | unneeded NOPs and swap branch instructions when possible. A value | |
506 | of 1 means to not swap branches. A value of 0 means to always | |
507 | insert NOPs. */ | |
508 | static int mips_optimize = 2; | |
509 | ||
510 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
511 | equivalent to seeing no -g option at all. */ | |
512 | static int mips_debug = 0; | |
513 | ||
514 | /* The previous instruction. */ | |
515 | static struct mips_cl_insn prev_insn; | |
516 | ||
517 | /* The instruction before prev_insn. */ | |
518 | static struct mips_cl_insn prev_prev_insn; | |
519 | ||
520 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
521 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 522 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
523 | |
524 | /* Non-zero if prev_insn is valid. */ | |
525 | static int prev_insn_valid; | |
526 | ||
527 | /* The frag for the previous instruction. */ | |
528 | static struct frag *prev_insn_frag; | |
529 | ||
530 | /* The offset into prev_insn_frag for the previous instruction. */ | |
531 | static long prev_insn_where; | |
532 | ||
533 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 534 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
535 | |
536 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 537 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
538 | |
539 | /* Non-zero if the previous instruction was in a delay slot. */ | |
540 | static int prev_insn_is_delay_slot; | |
541 | ||
542 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
543 | static int prev_insn_unreordered; | |
544 | ||
545 | /* Non-zero if the previous instruction uses an extend opcode (if | |
546 | mips16). */ | |
547 | static int prev_insn_extended; | |
548 | ||
549 | /* Non-zero if the previous previous instruction was in a .set | |
550 | noreorder. */ | |
551 | static int prev_prev_insn_unreordered; | |
552 | ||
553 | /* If this is set, it points to a frag holding nop instructions which | |
554 | were inserted before the start of a noreorder section. If those | |
555 | nops turn out to be unnecessary, the size of the frag can be | |
556 | decreased. */ | |
557 | static fragS *prev_nop_frag; | |
558 | ||
559 | /* The number of nop instructions we created in prev_nop_frag. */ | |
560 | static int prev_nop_frag_holds; | |
561 | ||
562 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 563 | prev_nop_frag. */ |
252b5132 RH |
564 | static int prev_nop_frag_required; |
565 | ||
566 | /* The number of instructions we've seen since prev_nop_frag. */ | |
567 | static int prev_nop_frag_since; | |
568 | ||
569 | /* For ECOFF and ELF, relocations against symbols are done in two | |
570 | parts, with a HI relocation and a LO relocation. Each relocation | |
571 | has only 16 bits of space to store an addend. This means that in | |
572 | order for the linker to handle carries correctly, it must be able | |
573 | to locate both the HI and the LO relocation. This means that the | |
574 | relocations must appear in order in the relocation table. | |
575 | ||
576 | In order to implement this, we keep track of each unmatched HI | |
577 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 578 | corresponding LO relocation. */ |
252b5132 | 579 | |
e972090a NC |
580 | struct mips_hi_fixup |
581 | { | |
252b5132 RH |
582 | /* Next HI fixup. */ |
583 | struct mips_hi_fixup *next; | |
584 | /* This fixup. */ | |
585 | fixS *fixp; | |
586 | /* The section this fixup is in. */ | |
587 | segT seg; | |
588 | }; | |
589 | ||
590 | /* The list of unmatched HI relocs. */ | |
591 | ||
592 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
593 | ||
64bdfcaf RS |
594 | /* The frag containing the last explicit relocation operator. |
595 | Null if explicit relocations have not been used. */ | |
596 | ||
597 | static fragS *prev_reloc_op_frag; | |
598 | ||
252b5132 RH |
599 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
600 | ||
601 | #define X ILLEGAL_REG | |
e972090a NC |
602 | static const int mips32_to_16_reg_map[] = |
603 | { | |
252b5132 RH |
604 | X, X, 2, 3, 4, 5, 6, 7, |
605 | X, X, X, X, X, X, X, X, | |
606 | 0, 1, X, X, X, X, X, X, | |
607 | X, X, X, X, X, X, X, X | |
608 | }; | |
609 | #undef X | |
610 | ||
611 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
612 | ||
e972090a NC |
613 | static const unsigned int mips16_to_32_reg_map[] = |
614 | { | |
252b5132 RH |
615 | 16, 17, 2, 3, 4, 5, 6, 7 |
616 | }; | |
60b63b72 | 617 | |
d766e8ec | 618 | static int mips_fix_vr4120; |
4a6a3df4 AO |
619 | |
620 | /* We don't relax branches by default, since this causes us to expand | |
621 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
622 | fail to compute the offset before expanding the macro to the most | |
623 | efficient expansion. */ | |
624 | ||
625 | static int mips_relax_branch; | |
252b5132 | 626 | \f |
4d7206a2 RS |
627 | /* The expansion of many macros depends on the type of symbol that |
628 | they refer to. For example, when generating position-dependent code, | |
629 | a macro that refers to a symbol may have two different expansions, | |
630 | one which uses GP-relative addresses and one which uses absolute | |
631 | addresses. When generating SVR4-style PIC, a macro may have | |
632 | different expansions for local and global symbols. | |
633 | ||
634 | We handle these situations by generating both sequences and putting | |
635 | them in variant frags. In position-dependent code, the first sequence | |
636 | will be the GP-relative one and the second sequence will be the | |
637 | absolute one. In SVR4 PIC, the first sequence will be for global | |
638 | symbols and the second will be for local symbols. | |
639 | ||
584892a6 RS |
640 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
641 | SECOND are the lengths of the two sequences in bytes. These fields | |
642 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
643 | the subtype has the following flags: | |
4d7206a2 | 644 | |
584892a6 RS |
645 | RELAX_USE_SECOND |
646 | Set if it has been decided that we should use the second | |
647 | sequence instead of the first. | |
648 | ||
649 | RELAX_SECOND_LONGER | |
650 | Set in the first variant frag if the macro's second implementation | |
651 | is longer than its first. This refers to the macro as a whole, | |
652 | not an individual relaxation. | |
653 | ||
654 | RELAX_NOMACRO | |
655 | Set in the first variant frag if the macro appeared in a .set nomacro | |
656 | block and if one alternative requires a warning but the other does not. | |
657 | ||
658 | RELAX_DELAY_SLOT | |
659 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
660 | delay slot. | |
4d7206a2 RS |
661 | |
662 | The frag's "opcode" points to the first fixup for relaxable code. | |
663 | ||
664 | Relaxable macros are generated using a sequence such as: | |
665 | ||
666 | relax_start (SYMBOL); | |
667 | ... generate first expansion ... | |
668 | relax_switch (); | |
669 | ... generate second expansion ... | |
670 | relax_end (); | |
671 | ||
672 | The code and fixups for the unwanted alternative are discarded | |
673 | by md_convert_frag. */ | |
584892a6 | 674 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 675 | |
584892a6 RS |
676 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
677 | #define RELAX_SECOND(X) ((X) & 0xff) | |
678 | #define RELAX_USE_SECOND 0x10000 | |
679 | #define RELAX_SECOND_LONGER 0x20000 | |
680 | #define RELAX_NOMACRO 0x40000 | |
681 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 682 | |
4a6a3df4 AO |
683 | /* Branch without likely bit. If label is out of range, we turn: |
684 | ||
685 | beq reg1, reg2, label | |
686 | delay slot | |
687 | ||
688 | into | |
689 | ||
690 | bne reg1, reg2, 0f | |
691 | nop | |
692 | j label | |
693 | 0: delay slot | |
694 | ||
695 | with the following opcode replacements: | |
696 | ||
697 | beq <-> bne | |
698 | blez <-> bgtz | |
699 | bltz <-> bgez | |
700 | bc1f <-> bc1t | |
701 | ||
702 | bltzal <-> bgezal (with jal label instead of j label) | |
703 | ||
704 | Even though keeping the delay slot instruction in the delay slot of | |
705 | the branch would be more efficient, it would be very tricky to do | |
706 | correctly, because we'd have to introduce a variable frag *after* | |
707 | the delay slot instruction, and expand that instead. Let's do it | |
708 | the easy way for now, even if the branch-not-taken case now costs | |
709 | one additional instruction. Out-of-range branches are not supposed | |
710 | to be common, anyway. | |
711 | ||
712 | Branch likely. If label is out of range, we turn: | |
713 | ||
714 | beql reg1, reg2, label | |
715 | delay slot (annulled if branch not taken) | |
716 | ||
717 | into | |
718 | ||
719 | beql reg1, reg2, 1f | |
720 | nop | |
721 | beql $0, $0, 2f | |
722 | nop | |
723 | 1: j[al] label | |
724 | delay slot (executed only if branch taken) | |
725 | 2: | |
726 | ||
727 | It would be possible to generate a shorter sequence by losing the | |
728 | likely bit, generating something like: | |
b34976b6 | 729 | |
4a6a3df4 AO |
730 | bne reg1, reg2, 0f |
731 | nop | |
732 | j[al] label | |
733 | delay slot (executed only if branch taken) | |
734 | 0: | |
735 | ||
736 | beql -> bne | |
737 | bnel -> beq | |
738 | blezl -> bgtz | |
739 | bgtzl -> blez | |
740 | bltzl -> bgez | |
741 | bgezl -> bltz | |
742 | bc1fl -> bc1t | |
743 | bc1tl -> bc1f | |
744 | ||
745 | bltzall -> bgezal (with jal label instead of j label) | |
746 | bgezall -> bltzal (ditto) | |
747 | ||
748 | ||
749 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 750 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
751 | ((relax_substateT) \ |
752 | (0xc0000000 \ | |
753 | | ((toofar) ? 1 : 0) \ | |
754 | | ((link) ? 2 : 0) \ | |
755 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 756 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 757 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
758 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
759 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
760 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 761 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 762 | |
252b5132 RH |
763 | /* For mips16 code, we use an entirely different form of relaxation. |
764 | mips16 supports two versions of most instructions which take | |
765 | immediate values: a small one which takes some small value, and a | |
766 | larger one which takes a 16 bit value. Since branches also follow | |
767 | this pattern, relaxing these values is required. | |
768 | ||
769 | We can assemble both mips16 and normal MIPS code in a single | |
770 | object. Therefore, we need to support this type of relaxation at | |
771 | the same time that we support the relaxation described above. We | |
772 | use the high bit of the subtype field to distinguish these cases. | |
773 | ||
774 | The information we store for this type of relaxation is the | |
775 | argument code found in the opcode file for this relocation, whether | |
776 | the user explicitly requested a small or extended form, and whether | |
777 | the relocation is in a jump or jal delay slot. That tells us the | |
778 | size of the value, and how it should be stored. We also store | |
779 | whether the fragment is considered to be extended or not. We also | |
780 | store whether this is known to be a branch to a different section, | |
781 | whether we have tried to relax this frag yet, and whether we have | |
782 | ever extended a PC relative fragment because of a shift count. */ | |
783 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
784 | (0x80000000 \ | |
785 | | ((type) & 0xff) \ | |
786 | | ((small) ? 0x100 : 0) \ | |
787 | | ((ext) ? 0x200 : 0) \ | |
788 | | ((dslot) ? 0x400 : 0) \ | |
789 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 790 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
791 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
792 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
793 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
794 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
795 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
796 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
797 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
798 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
799 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
800 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
801 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
802 | |
803 | /* Is the given value a sign-extended 32-bit value? */ | |
804 | #define IS_SEXT_32BIT_NUM(x) \ | |
805 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
806 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
807 | ||
808 | /* Is the given value a sign-extended 16-bit value? */ | |
809 | #define IS_SEXT_16BIT_NUM(x) \ | |
810 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
811 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
812 | ||
4d7206a2 RS |
813 | \f |
814 | /* Global variables used when generating relaxable macros. See the | |
815 | comment above RELAX_ENCODE for more details about how relaxation | |
816 | is used. */ | |
817 | static struct { | |
818 | /* 0 if we're not emitting a relaxable macro. | |
819 | 1 if we're emitting the first of the two relaxation alternatives. | |
820 | 2 if we're emitting the second alternative. */ | |
821 | int sequence; | |
822 | ||
823 | /* The first relaxable fixup in the current frag. (In other words, | |
824 | the first fixup that refers to relaxable code.) */ | |
825 | fixS *first_fixup; | |
826 | ||
827 | /* sizes[0] says how many bytes of the first alternative are stored in | |
828 | the current frag. Likewise sizes[1] for the second alternative. */ | |
829 | unsigned int sizes[2]; | |
830 | ||
831 | /* The symbol on which the choice of sequence depends. */ | |
832 | symbolS *symbol; | |
833 | } mips_relax; | |
252b5132 | 834 | \f |
584892a6 RS |
835 | /* Global variables used to decide whether a macro needs a warning. */ |
836 | static struct { | |
837 | /* True if the macro is in a branch delay slot. */ | |
838 | bfd_boolean delay_slot_p; | |
839 | ||
840 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
841 | in bytes and sizes[1] is the length of the second alternative. | |
842 | For non-relaxable macros, both elements give the length of the | |
843 | macro in bytes. */ | |
844 | unsigned int sizes[2]; | |
845 | ||
846 | /* The first variant frag for this macro. */ | |
847 | fragS *first_frag; | |
848 | } mips_macro_warning; | |
849 | \f | |
252b5132 RH |
850 | /* Prototypes for static functions. */ |
851 | ||
17a2f251 | 852 | #define internalError() \ |
252b5132 | 853 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
854 | |
855 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
856 | ||
b34976b6 | 857 | static void append_insn |
4d7206a2 | 858 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 859 | static void mips_no_prev_insn (int); |
b34976b6 | 860 | static void mips16_macro_build |
67c0d1eb RS |
861 | (expressionS *, const char *, const char *, va_list); |
862 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
863 | static void macro_start (void); |
864 | static void macro_end (void); | |
17a2f251 TS |
865 | static void macro (struct mips_cl_insn * ip); |
866 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 867 | #ifdef LOSING_COMPILER |
17a2f251 | 868 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 869 | #endif |
17a2f251 TS |
870 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
871 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 872 | static void mips16_immed |
17a2f251 TS |
873 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
874 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 875 | static size_t my_getSmallExpression |
17a2f251 TS |
876 | (expressionS *, bfd_reloc_code_real_type *, char *); |
877 | static void my_getExpression (expressionS *, char *); | |
878 | static void s_align (int); | |
879 | static void s_change_sec (int); | |
880 | static void s_change_section (int); | |
881 | static void s_cons (int); | |
882 | static void s_float_cons (int); | |
883 | static void s_mips_globl (int); | |
884 | static void s_option (int); | |
885 | static void s_mipsset (int); | |
886 | static void s_abicalls (int); | |
887 | static void s_cpload (int); | |
888 | static void s_cpsetup (int); | |
889 | static void s_cplocal (int); | |
890 | static void s_cprestore (int); | |
891 | static void s_cpreturn (int); | |
892 | static void s_gpvalue (int); | |
893 | static void s_gpword (int); | |
894 | static void s_gpdword (int); | |
895 | static void s_cpadd (int); | |
896 | static void s_insn (int); | |
897 | static void md_obj_begin (void); | |
898 | static void md_obj_end (void); | |
899 | static void s_mips_ent (int); | |
900 | static void s_mips_end (int); | |
901 | static void s_mips_frame (int); | |
902 | static void s_mips_mask (int reg_type); | |
903 | static void s_mips_stab (int); | |
904 | static void s_mips_weakext (int); | |
905 | static void s_mips_file (int); | |
906 | static void s_mips_loc (int); | |
907 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 908 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 909 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
910 | |
911 | /* Table and functions used to map between CPU/ISA names, and | |
912 | ISA levels, and CPU numbers. */ | |
913 | ||
e972090a NC |
914 | struct mips_cpu_info |
915 | { | |
e7af610e NC |
916 | const char *name; /* CPU or ISA name. */ |
917 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
918 | int isa; /* ISA level. */ | |
919 | int cpu; /* CPU number (default CPU if ISA). */ | |
920 | }; | |
921 | ||
17a2f251 TS |
922 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
923 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
924 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
925 | \f |
926 | /* Pseudo-op table. | |
927 | ||
928 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
929 | should be defined here, but are currently unsupported: .alias, | |
930 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
931 | ||
932 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
933 | specific to the type of debugging information being generated, and | |
934 | should be defined by the object format: .aent, .begin, .bend, | |
935 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
936 | .vreg. | |
937 | ||
938 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
939 | not MIPS CPU specific, but are also not specific to the object file | |
940 | format. This file is probably the best place to define them, but | |
941 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
942 | .struct. */ | |
943 | ||
e972090a NC |
944 | static const pseudo_typeS mips_pseudo_table[] = |
945 | { | |
beae10d5 | 946 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
947 | {"option", s_option, 0}, |
948 | {"set", s_mipsset, 0}, | |
949 | {"rdata", s_change_sec, 'r'}, | |
950 | {"sdata", s_change_sec, 's'}, | |
951 | {"livereg", s_ignore, 0}, | |
952 | {"abicalls", s_abicalls, 0}, | |
953 | {"cpload", s_cpload, 0}, | |
6478892d TS |
954 | {"cpsetup", s_cpsetup, 0}, |
955 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 956 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
957 | {"cpreturn", s_cpreturn, 0}, |
958 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 959 | {"gpword", s_gpword, 0}, |
10181a0d | 960 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
961 | {"cpadd", s_cpadd, 0}, |
962 | {"insn", s_insn, 0}, | |
963 | ||
beae10d5 | 964 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
965 | chips. */ |
966 | {"asciiz", stringer, 1}, | |
967 | {"bss", s_change_sec, 'b'}, | |
968 | {"err", s_err, 0}, | |
969 | {"half", s_cons, 1}, | |
970 | {"dword", s_cons, 3}, | |
971 | {"weakext", s_mips_weakext, 0}, | |
972 | ||
beae10d5 | 973 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
974 | here for one reason or another. */ |
975 | {"align", s_align, 0}, | |
976 | {"byte", s_cons, 0}, | |
977 | {"data", s_change_sec, 'd'}, | |
978 | {"double", s_float_cons, 'd'}, | |
979 | {"float", s_float_cons, 'f'}, | |
980 | {"globl", s_mips_globl, 0}, | |
981 | {"global", s_mips_globl, 0}, | |
982 | {"hword", s_cons, 1}, | |
983 | {"int", s_cons, 2}, | |
984 | {"long", s_cons, 2}, | |
985 | {"octa", s_cons, 4}, | |
986 | {"quad", s_cons, 3}, | |
cca86cc8 | 987 | {"section", s_change_section, 0}, |
252b5132 RH |
988 | {"short", s_cons, 1}, |
989 | {"single", s_float_cons, 'f'}, | |
990 | {"stabn", s_mips_stab, 'n'}, | |
991 | {"text", s_change_sec, 't'}, | |
992 | {"word", s_cons, 2}, | |
add56521 | 993 | |
add56521 | 994 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 995 | |
43841e91 | 996 | { NULL, NULL, 0 }, |
252b5132 RH |
997 | }; |
998 | ||
e972090a NC |
999 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1000 | { | |
beae10d5 KH |
1001 | /* These pseudo-ops should be defined by the object file format. |
1002 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1003 | {"aent", s_mips_ent, 1}, |
1004 | {"bgnb", s_ignore, 0}, | |
1005 | {"end", s_mips_end, 0}, | |
1006 | {"endb", s_ignore, 0}, | |
1007 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1008 | {"file", s_mips_file, 0}, |
252b5132 RH |
1009 | {"fmask", s_mips_mask, 'F'}, |
1010 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1011 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1012 | {"mask", s_mips_mask, 'R'}, |
1013 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1014 | { NULL, NULL, 0 }, |
252b5132 RH |
1015 | }; |
1016 | ||
17a2f251 | 1017 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1018 | |
1019 | void | |
17a2f251 | 1020 | mips_pop_insert (void) |
252b5132 RH |
1021 | { |
1022 | pop_insert (mips_pseudo_table); | |
1023 | if (! ECOFF_DEBUGGING) | |
1024 | pop_insert (mips_nonecoff_pseudo_table); | |
1025 | } | |
1026 | \f | |
1027 | /* Symbols labelling the current insn. */ | |
1028 | ||
e972090a NC |
1029 | struct insn_label_list |
1030 | { | |
252b5132 RH |
1031 | struct insn_label_list *next; |
1032 | symbolS *label; | |
1033 | }; | |
1034 | ||
1035 | static struct insn_label_list *insn_labels; | |
1036 | static struct insn_label_list *free_insn_labels; | |
1037 | ||
17a2f251 | 1038 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1039 | |
1040 | static inline void | |
17a2f251 | 1041 | mips_clear_insn_labels (void) |
252b5132 RH |
1042 | { |
1043 | register struct insn_label_list **pl; | |
1044 | ||
1045 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1046 | ; | |
1047 | *pl = insn_labels; | |
1048 | insn_labels = NULL; | |
1049 | } | |
1050 | \f | |
1051 | static char *expr_end; | |
1052 | ||
1053 | /* Expressions which appear in instructions. These are set by | |
1054 | mips_ip. */ | |
1055 | ||
1056 | static expressionS imm_expr; | |
5f74bc13 | 1057 | static expressionS imm2_expr; |
252b5132 RH |
1058 | static expressionS offset_expr; |
1059 | ||
1060 | /* Relocs associated with imm_expr and offset_expr. */ | |
1061 | ||
f6688943 TS |
1062 | static bfd_reloc_code_real_type imm_reloc[3] |
1063 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1064 | static bfd_reloc_code_real_type offset_reloc[3] | |
1065 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1066 | |
252b5132 RH |
1067 | /* These are set by mips16_ip if an explicit extension is used. */ |
1068 | ||
b34976b6 | 1069 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1070 | |
7ed4a06a | 1071 | #ifdef OBJ_ELF |
ecb4347a DJ |
1072 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1073 | ECOFF debugging. */ | |
252b5132 RH |
1074 | |
1075 | static segT pdr_seg; | |
7ed4a06a | 1076 | #endif |
252b5132 | 1077 | |
e013f690 TS |
1078 | /* The default target format to use. */ |
1079 | ||
1080 | const char * | |
17a2f251 | 1081 | mips_target_format (void) |
e013f690 TS |
1082 | { |
1083 | switch (OUTPUT_FLAVOR) | |
1084 | { | |
e013f690 TS |
1085 | case bfd_target_ecoff_flavour: |
1086 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1087 | case bfd_target_coff_flavour: | |
1088 | return "pe-mips"; | |
1089 | case bfd_target_elf_flavour: | |
1090 | #ifdef TE_TMIPS | |
cfe86eaa | 1091 | /* This is traditional mips. */ |
e013f690 | 1092 | return (target_big_endian |
cfe86eaa TS |
1093 | ? (HAVE_64BIT_OBJECTS |
1094 | ? "elf64-tradbigmips" | |
1095 | : (HAVE_NEWABI | |
1096 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1097 | : (HAVE_64BIT_OBJECTS | |
1098 | ? "elf64-tradlittlemips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1101 | #else |
1102 | return (target_big_endian | |
cfe86eaa TS |
1103 | ? (HAVE_64BIT_OBJECTS |
1104 | ? "elf64-bigmips" | |
1105 | : (HAVE_NEWABI | |
1106 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1107 | : (HAVE_64BIT_OBJECTS | |
1108 | ? "elf64-littlemips" | |
1109 | : (HAVE_NEWABI | |
1110 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1111 | #endif |
1112 | default: | |
1113 | abort (); | |
1114 | return NULL; | |
1115 | } | |
1116 | } | |
1117 | ||
156c2f8b NC |
1118 | /* This function is called once, at assembler startup time. It should |
1119 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1120 | ||
252b5132 | 1121 | void |
17a2f251 | 1122 | md_begin (void) |
252b5132 | 1123 | { |
252b5132 | 1124 | register const char *retval = NULL; |
156c2f8b | 1125 | int i = 0; |
252b5132 | 1126 | int broken = 0; |
1f25f5d3 | 1127 | |
fef14a42 | 1128 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1129 | as_warn (_("Could not set architecture and machine")); |
1130 | ||
252b5132 RH |
1131 | op_hash = hash_new (); |
1132 | ||
1133 | for (i = 0; i < NUMOPCODES;) | |
1134 | { | |
1135 | const char *name = mips_opcodes[i].name; | |
1136 | ||
17a2f251 | 1137 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1138 | if (retval != NULL) |
1139 | { | |
1140 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1141 | mips_opcodes[i].name, retval); | |
1142 | /* Probably a memory allocation problem? Give up now. */ | |
1143 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1144 | } | |
1145 | do | |
1146 | { | |
1147 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1148 | { | |
1149 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1150 | broken = 1; | |
1151 | } | |
1152 | ++i; | |
1153 | } | |
1154 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1155 | } | |
1156 | ||
1157 | mips16_op_hash = hash_new (); | |
1158 | ||
1159 | i = 0; | |
1160 | while (i < bfd_mips16_num_opcodes) | |
1161 | { | |
1162 | const char *name = mips16_opcodes[i].name; | |
1163 | ||
17a2f251 | 1164 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1165 | if (retval != NULL) |
1166 | as_fatal (_("internal: can't hash `%s': %s"), | |
1167 | mips16_opcodes[i].name, retval); | |
1168 | do | |
1169 | { | |
1170 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1171 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1172 | != mips16_opcodes[i].match)) | |
1173 | { | |
1174 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1175 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1176 | broken = 1; | |
1177 | } | |
1178 | ++i; | |
1179 | } | |
1180 | while (i < bfd_mips16_num_opcodes | |
1181 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1182 | } | |
1183 | ||
1184 | if (broken) | |
1185 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1186 | ||
1187 | /* We add all the general register names to the symbol table. This | |
1188 | helps us detect invalid uses of them. */ | |
1189 | for (i = 0; i < 32; i++) | |
1190 | { | |
1191 | char buf[5]; | |
1192 | ||
1193 | sprintf (buf, "$%d", i); | |
1194 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1195 | &zero_address_frag)); | |
1196 | } | |
76db943d TS |
1197 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1198 | &zero_address_frag)); | |
252b5132 RH |
1199 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1200 | &zero_address_frag)); | |
1201 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1202 | &zero_address_frag)); | |
1203 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1204 | &zero_address_frag)); | |
1205 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1206 | &zero_address_frag)); | |
1207 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1208 | &zero_address_frag)); | |
1209 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1210 | &zero_address_frag)); | |
85b51719 TS |
1211 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1212 | &zero_address_frag)); | |
252b5132 RH |
1213 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1214 | &zero_address_frag)); | |
1215 | ||
6047c971 AO |
1216 | /* If we don't add these register names to the symbol table, they |
1217 | may end up being added as regular symbols by operand(), and then | |
1218 | make it to the object file as undefined in case they're not | |
1219 | regarded as local symbols. They're local in o32, since `$' is a | |
1220 | local symbol prefix, but not in n32 or n64. */ | |
1221 | for (i = 0; i < 8; i++) | |
1222 | { | |
1223 | char buf[6]; | |
1224 | ||
1225 | sprintf (buf, "$fcc%i", i); | |
1226 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1227 | &zero_address_frag)); | |
1228 | } | |
1229 | ||
b34976b6 | 1230 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1231 | |
1232 | mips_gprmask = 0; | |
1233 | mips_cprmask[0] = 0; | |
1234 | mips_cprmask[1] = 0; | |
1235 | mips_cprmask[2] = 0; | |
1236 | mips_cprmask[3] = 0; | |
1237 | ||
1238 | /* set the default alignment for the text section (2**2) */ | |
1239 | record_alignment (text_section, 2); | |
1240 | ||
4d0d148d | 1241 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1242 | |
1243 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1244 | { | |
1245 | /* On a native system, sections must be aligned to 16 byte | |
1246 | boundaries. When configured for an embedded ELF target, we | |
1247 | don't bother. */ | |
1248 | if (strcmp (TARGET_OS, "elf") != 0) | |
1249 | { | |
1250 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1251 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1252 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1253 | } | |
1254 | ||
1255 | /* Create a .reginfo section for register masks and a .mdebug | |
1256 | section for debugging information. */ | |
1257 | { | |
1258 | segT seg; | |
1259 | subsegT subseg; | |
1260 | flagword flags; | |
1261 | segT sec; | |
1262 | ||
1263 | seg = now_seg; | |
1264 | subseg = now_subseg; | |
1265 | ||
1266 | /* The ABI says this section should be loaded so that the | |
1267 | running program can access it. However, we don't load it | |
1268 | if we are configured for an embedded target */ | |
1269 | flags = SEC_READONLY | SEC_DATA; | |
1270 | if (strcmp (TARGET_OS, "elf") != 0) | |
1271 | flags |= SEC_ALLOC | SEC_LOAD; | |
1272 | ||
316f5878 | 1273 | if (mips_abi != N64_ABI) |
252b5132 RH |
1274 | { |
1275 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1276 | ||
195325d2 TS |
1277 | bfd_set_section_flags (stdoutput, sec, flags); |
1278 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1279 | |
252b5132 RH |
1280 | #ifdef OBJ_ELF |
1281 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1282 | #endif | |
1283 | } | |
1284 | else | |
1285 | { | |
1286 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1287 | .reginfo section. */ | |
1288 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1289 | bfd_set_section_flags (stdoutput, sec, flags); |
1290 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1291 | |
1292 | #ifdef OBJ_ELF | |
1293 | /* Set up the option header. */ | |
1294 | { | |
1295 | Elf_Internal_Options opthdr; | |
1296 | char *f; | |
1297 | ||
1298 | opthdr.kind = ODK_REGINFO; | |
1299 | opthdr.size = (sizeof (Elf_External_Options) | |
1300 | + sizeof (Elf64_External_RegInfo)); | |
1301 | opthdr.section = 0; | |
1302 | opthdr.info = 0; | |
1303 | f = frag_more (sizeof (Elf_External_Options)); | |
1304 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1305 | (Elf_External_Options *) f); | |
1306 | ||
1307 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1308 | } | |
1309 | #endif | |
1310 | } | |
1311 | ||
1312 | if (ECOFF_DEBUGGING) | |
1313 | { | |
1314 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1315 | (void) bfd_set_section_flags (stdoutput, sec, | |
1316 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1317 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1318 | } | |
ecb4347a | 1319 | #ifdef OBJ_ELF |
dcd410fe | 1320 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1321 | { |
1322 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1323 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1324 | SEC_READONLY | SEC_RELOC | |
1325 | | SEC_DEBUGGING); | |
1326 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1327 | } | |
252b5132 RH |
1328 | #endif |
1329 | ||
1330 | subseg_set (seg, subseg); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | if (! ECOFF_DEBUGGING) | |
1335 | md_obj_begin (); | |
1336 | } | |
1337 | ||
1338 | void | |
17a2f251 | 1339 | md_mips_end (void) |
252b5132 RH |
1340 | { |
1341 | if (! ECOFF_DEBUGGING) | |
1342 | md_obj_end (); | |
1343 | } | |
1344 | ||
1345 | void | |
17a2f251 | 1346 | md_assemble (char *str) |
252b5132 RH |
1347 | { |
1348 | struct mips_cl_insn insn; | |
f6688943 TS |
1349 | bfd_reloc_code_real_type unused_reloc[3] |
1350 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1351 | |
1352 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1353 | imm2_expr.X_op = O_absent; |
252b5132 | 1354 | offset_expr.X_op = O_absent; |
f6688943 TS |
1355 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1356 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1357 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1358 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1359 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1360 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1361 | |
1362 | if (mips_opts.mips16) | |
1363 | mips16_ip (str, &insn); | |
1364 | else | |
1365 | { | |
1366 | mips_ip (str, &insn); | |
beae10d5 KH |
1367 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1368 | str, insn.insn_opcode)); | |
252b5132 RH |
1369 | } |
1370 | ||
1371 | if (insn_error) | |
1372 | { | |
1373 | as_bad ("%s `%s'", insn_error, str); | |
1374 | return; | |
1375 | } | |
1376 | ||
1377 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1378 | { | |
584892a6 | 1379 | macro_start (); |
252b5132 RH |
1380 | if (mips_opts.mips16) |
1381 | mips16_macro (&insn); | |
1382 | else | |
1383 | macro (&insn); | |
584892a6 | 1384 | macro_end (); |
252b5132 RH |
1385 | } |
1386 | else | |
1387 | { | |
1388 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1389 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1390 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1391 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1392 | else |
4d7206a2 | 1393 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1394 | } |
1395 | } | |
1396 | ||
5919d012 RS |
1397 | /* Return true if the given relocation might need a matching %lo(). |
1398 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1399 | applied to local symbols. */ | |
1400 | ||
1401 | static inline bfd_boolean | |
17a2f251 | 1402 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1403 | { |
3b91255e RS |
1404 | return (HAVE_IN_PLACE_ADDENDS |
1405 | && (reloc == BFD_RELOC_HI16_S | |
1406 | || reloc == BFD_RELOC_MIPS_GOT16)); | |
5919d012 RS |
1407 | } |
1408 | ||
1409 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1410 | relocation. */ | |
1411 | ||
1412 | static inline bfd_boolean | |
17a2f251 | 1413 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1414 | { |
1415 | return (fixp->fx_next != NULL | |
1416 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1417 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1418 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1419 | } | |
1420 | ||
252b5132 RH |
1421 | /* See whether instruction IP reads register REG. CLASS is the type |
1422 | of register. */ | |
1423 | ||
1424 | static int | |
17a2f251 TS |
1425 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1426 | enum mips_regclass class) | |
252b5132 RH |
1427 | { |
1428 | if (class == MIPS16_REG) | |
1429 | { | |
1430 | assert (mips_opts.mips16); | |
1431 | reg = mips16_to_32_reg_map[reg]; | |
1432 | class = MIPS_GR_REG; | |
1433 | } | |
1434 | ||
85b51719 TS |
1435 | /* Don't report on general register ZERO, since it never changes. */ |
1436 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1437 | return 0; |
1438 | ||
1439 | if (class == MIPS_FP_REG) | |
1440 | { | |
1441 | assert (! mips_opts.mips16); | |
1442 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1443 | This is not optimal, because it will introduce an unnecessary | |
1444 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1445 | need to distinguish reading both $f0 and $f1 or just one of | |
1446 | them. Note that we don't have to check the other way, | |
1447 | because there is no instruction that sets both $f0 and $f1 | |
1448 | and requires a delay. */ | |
1449 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1450 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1451 | == (reg &~ (unsigned) 1))) | |
1452 | return 1; | |
1453 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1454 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1455 | == (reg &~ (unsigned) 1))) | |
1456 | return 1; | |
1457 | } | |
1458 | else if (! mips_opts.mips16) | |
1459 | { | |
1460 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1461 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1462 | return 1; | |
1463 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1464 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1465 | return 1; | |
1466 | } | |
1467 | else | |
1468 | { | |
1469 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1470 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1471 | & MIPS16OP_MASK_RX)] | |
1472 | == reg)) | |
1473 | return 1; | |
1474 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1475 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1476 | & MIPS16OP_MASK_RY)] | |
1477 | == reg)) | |
1478 | return 1; | |
1479 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1480 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1481 | & MIPS16OP_MASK_MOVE32Z)] | |
1482 | == reg)) | |
1483 | return 1; | |
1484 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1485 | return 1; | |
1486 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1487 | return 1; | |
1488 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1489 | return 1; | |
1490 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1491 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1492 | & MIPS16OP_MASK_REGR32) == reg) | |
1493 | return 1; | |
1494 | } | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | /* This function returns true if modifying a register requires a | |
1500 | delay. */ | |
1501 | ||
1502 | static int | |
17a2f251 | 1503 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1504 | { |
1505 | unsigned long prev_pinfo; | |
1506 | ||
1507 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1508 | if (! mips_opts.noreorder | |
81912461 ILT |
1509 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1510 | && ! gpr_interlocks) | |
1511 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1512 | && ! cop_interlocks))) | |
252b5132 | 1513 | { |
81912461 ILT |
1514 | /* A load from a coprocessor or from memory. All load delays |
1515 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1516 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1517 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1518 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1519 | return 1; | |
1520 | } | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1526 | handle them specially, such as generating jalx instructions when | |
1527 | needed. We also make them odd for the duration of the assembly, in | |
1528 | order to generate the right sort of code. We will make them even | |
1529 | in the adjust_symtab routine, while leaving them marked. This is | |
1530 | convenient for the debugger and the disassembler. The linker knows | |
1531 | to make them odd again. */ | |
1532 | ||
1533 | static void | |
17a2f251 | 1534 | mips16_mark_labels (void) |
252b5132 RH |
1535 | { |
1536 | if (mips_opts.mips16) | |
1537 | { | |
1538 | struct insn_label_list *l; | |
98aa84af | 1539 | valueT val; |
252b5132 RH |
1540 | |
1541 | for (l = insn_labels; l != NULL; l = l->next) | |
1542 | { | |
1543 | #ifdef OBJ_ELF | |
1544 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1545 | S_SET_OTHER (l->label, STO_MIPS16); | |
1546 | #endif | |
98aa84af AM |
1547 | val = S_GET_VALUE (l->label); |
1548 | if ((val & 1) == 0) | |
1549 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1550 | } |
1551 | } | |
1552 | } | |
1553 | ||
4d7206a2 RS |
1554 | /* End the current frag. Make it a variant frag and record the |
1555 | relaxation info. */ | |
1556 | ||
1557 | static void | |
1558 | relax_close_frag (void) | |
1559 | { | |
584892a6 | 1560 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1561 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1562 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1563 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1564 | ||
1565 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1566 | mips_relax.first_fixup = 0; | |
1567 | } | |
1568 | ||
1569 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1570 | See the comment above RELAX_ENCODE for more details. */ | |
1571 | ||
1572 | static void | |
1573 | relax_start (symbolS *symbol) | |
1574 | { | |
1575 | assert (mips_relax.sequence == 0); | |
1576 | mips_relax.sequence = 1; | |
1577 | mips_relax.symbol = symbol; | |
1578 | } | |
1579 | ||
1580 | /* Start generating the second version of a relaxable sequence. | |
1581 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1582 | |
1583 | static void | |
4d7206a2 RS |
1584 | relax_switch (void) |
1585 | { | |
1586 | assert (mips_relax.sequence == 1); | |
1587 | mips_relax.sequence = 2; | |
1588 | } | |
1589 | ||
1590 | /* End the current relaxable sequence. */ | |
1591 | ||
1592 | static void | |
1593 | relax_end (void) | |
1594 | { | |
1595 | assert (mips_relax.sequence == 2); | |
1596 | relax_close_frag (); | |
1597 | mips_relax.sequence = 0; | |
1598 | } | |
1599 | ||
1600 | /* Output an instruction. IP is the instruction information. | |
1601 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1602 | RELOC_TYPE. */ | |
1603 | ||
1604 | static void | |
1605 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1606 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1607 | { |
1608 | register unsigned long prev_pinfo, pinfo; | |
1609 | char *f; | |
f6688943 | 1610 | fixS *fixp[3]; |
252b5132 | 1611 | int nops = 0; |
895921c9 MR |
1612 | relax_stateT prev_insn_frag_type = 0; |
1613 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1614 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1615 | |
1616 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1617 | mips16_mark_labels (); |
252b5132 RH |
1618 | |
1619 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1620 | pinfo = ip->insn_mo->pinfo; | |
1621 | ||
4d7206a2 RS |
1622 | if (mips_relax.sequence != 2 |
1623 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1624 | { |
1625 | int prev_prev_nop; | |
1626 | ||
1627 | /* If the previous insn required any delay slots, see if we need | |
1628 | to insert a NOP or two. There are eight kinds of possible | |
1629 | hazards, of which an instruction can have at most one type. | |
1630 | (1) a load from memory delay | |
1631 | (2) a load from a coprocessor delay | |
1632 | (3) an unconditional branch delay | |
1633 | (4) a conditional branch delay | |
1634 | (5) a move to coprocessor register delay | |
1635 | (6) a load coprocessor register from memory delay | |
1636 | (7) a coprocessor condition code delay | |
1637 | (8) a HI/LO special register delay | |
1638 | ||
1639 | There are a lot of optimizations we could do that we don't. | |
1640 | In particular, we do not, in general, reorder instructions. | |
1641 | If you use gcc with optimization, it will reorder | |
1642 | instructions and generally do much more optimization then we | |
1643 | do here; repeating all that work in the assembler would only | |
1644 | benefit hand written assembly code, and does not seem worth | |
1645 | it. */ | |
1646 | ||
1647 | /* This is how a NOP is emitted. */ | |
1648 | #define emit_nop() \ | |
1649 | (mips_opts.mips16 \ | |
1650 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1651 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1652 | ||
1653 | /* The previous insn might require a delay slot, depending upon | |
1654 | the contents of the current insn. */ | |
1655 | if (! mips_opts.mips16 | |
81912461 ILT |
1656 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1657 | && ! gpr_interlocks) | |
1658 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1659 | && ! cop_interlocks))) | |
252b5132 RH |
1660 | { |
1661 | /* A load from a coprocessor or from memory. All load | |
1662 | delays delay the use of general register rt for one | |
81912461 | 1663 | instruction. */ |
beae10d5 | 1664 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1665 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1666 | if (mips_optimize == 0 | |
1667 | || insn_uses_reg (ip, | |
1668 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1669 | & OP_MASK_RT), | |
1670 | MIPS_GR_REG)) | |
1671 | ++nops; | |
1672 | } | |
1673 | else if (! mips_opts.mips16 | |
252b5132 | 1674 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1675 | && ! cop_interlocks) |
81912461 ILT |
1676 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1677 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1678 | { |
1679 | /* A generic coprocessor delay. The previous instruction | |
1680 | modified a coprocessor general or control register. If | |
1681 | it modified a control register, we need to avoid any | |
1682 | coprocessor instruction (this is probably not always | |
1683 | required, but it sometimes is). If it modified a general | |
1684 | register, we avoid using that register. | |
1685 | ||
252b5132 RH |
1686 | This case is not handled very well. There is no special |
1687 | knowledge of CP0 handling, and the coprocessors other | |
1688 | than the floating point unit are not distinguished at | |
1689 | all. */ | |
1690 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1691 | Need to modify this to include knowledge about |
252b5132 RH |
1692 | user specified delays! */ |
1693 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1694 | { | |
1695 | if (mips_optimize == 0 | |
1696 | || insn_uses_reg (ip, | |
1697 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1698 | & OP_MASK_FT), | |
1699 | MIPS_FP_REG)) | |
1700 | ++nops; | |
1701 | } | |
1702 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1703 | { | |
1704 | if (mips_optimize == 0 | |
1705 | || insn_uses_reg (ip, | |
1706 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1707 | & OP_MASK_FS), | |
1708 | MIPS_FP_REG)) | |
1709 | ++nops; | |
1710 | } | |
1711 | else | |
1712 | { | |
1713 | /* We don't know exactly what the previous instruction | |
1714 | does. If the current instruction uses a coprocessor | |
1715 | register, we must insert a NOP. If previous | |
1716 | instruction may set the condition codes, and the | |
1717 | current instruction uses them, we must insert two | |
1718 | NOPS. */ | |
bdaaa2e1 | 1719 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1720 | if (mips_optimize == 0 |
1721 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1722 | && (pinfo & INSN_READ_COND_CODE))) | |
1723 | nops += 2; | |
1724 | else if (pinfo & INSN_COP) | |
1725 | ++nops; | |
1726 | } | |
1727 | } | |
1728 | else if (! mips_opts.mips16 | |
252b5132 RH |
1729 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1730 | && ! cop_interlocks) | |
1731 | { | |
1732 | /* The previous instruction sets the coprocessor condition | |
1733 | codes, but does not require a general coprocessor delay | |
1734 | (this means it is a floating point comparison | |
1735 | instruction). If this instruction uses the condition | |
1736 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1738 | if (mips_optimize == 0 |
1739 | || (pinfo & INSN_READ_COND_CODE)) | |
1740 | ++nops; | |
1741 | } | |
6b76fefe CM |
1742 | |
1743 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1744 | previous insn was an mfhi/mflo and the current insn | |
1745 | reads the register that the mfhi/mflo wrote to, then | |
1746 | insert two nops. */ | |
1747 | ||
1748 | else if (mips_7000_hilo_fix | |
1749 | && MF_HILO_INSN (prev_pinfo) | |
1750 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1751 | & OP_MASK_RD), |
1752 | MIPS_GR_REG)) | |
6b76fefe CM |
1753 | { |
1754 | nops += 2; | |
1755 | } | |
1756 | ||
1757 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1758 | 2nd previous insn was an mfhi/mflo and the current insn | |
1759 | reads the register that the mfhi/mflo wrote to, then | |
1760 | insert one nop. */ | |
1761 | ||
1762 | else if (mips_7000_hilo_fix | |
1763 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1764 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1765 | & OP_MASK_RD), | |
1766 | MIPS_GR_REG)) | |
bdaaa2e1 | 1767 | |
6b76fefe | 1768 | { |
f9419b05 | 1769 | ++nops; |
6b76fefe | 1770 | } |
bdaaa2e1 | 1771 | |
252b5132 RH |
1772 | else if (prev_pinfo & INSN_READ_LO) |
1773 | { | |
1774 | /* The previous instruction reads the LO register; if the | |
1775 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1776 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1777 | Also the tx39's multiply instructions can be executed |
1778 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1779 | though the tx39's divide insns still do require the |
1780 | delay. */ | |
252b5132 | 1781 | if (! (hilo_interlocks |
048cdf86 | 1782 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1783 | && (mips_optimize == 0 |
1784 | || (pinfo & INSN_WRITE_LO))) | |
1785 | nops += 2; | |
1786 | /* Most mips16 branch insns don't have a delay slot. | |
1787 | If a read from LO is immediately followed by a branch | |
1788 | to a write to LO we have a read followed by a write | |
1789 | less than 2 insns away. We assume the target of | |
1790 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1791 | between a read and an immediately following branch. */ |
252b5132 RH |
1792 | else if (mips_opts.mips16 |
1793 | && (mips_optimize == 0 | |
1794 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1795 | ++nops; |
252b5132 RH |
1796 | } |
1797 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1798 | { | |
1799 | /* The previous instruction reads the HI register; if the | |
1800 | current instruction writes to the HI register, we must | |
1801 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1802 | Also the note tx39's multiply above. */ |
252b5132 | 1803 | if (! (hilo_interlocks |
048cdf86 | 1804 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1805 | && (mips_optimize == 0 |
1806 | || (pinfo & INSN_WRITE_HI))) | |
1807 | nops += 2; | |
1808 | /* Most mips16 branch insns don't have a delay slot. | |
1809 | If a read from HI is immediately followed by a branch | |
1810 | to a write to HI we have a read followed by a write | |
1811 | less than 2 insns away. We assume the target of | |
1812 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1813 | between a read and an immediately following branch. */ |
252b5132 RH |
1814 | else if (mips_opts.mips16 |
1815 | && (mips_optimize == 0 | |
1816 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1817 | ++nops; |
252b5132 RH |
1818 | } |
1819 | ||
1820 | /* If the previous instruction was in a noreorder section, then | |
1821 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1822 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1823 | if (prev_insn_unreordered) |
1824 | nops = 0; | |
1825 | ||
1826 | /* There are two cases which require two intervening | |
1827 | instructions: 1) setting the condition codes using a move to | |
1828 | coprocessor instruction which requires a general coprocessor | |
1829 | delay and then reading the condition codes 2) reading the HI | |
1830 | or LO register and then writing to it (except on processors | |
1831 | which have interlocks). If we are not already emitting a NOP | |
1832 | instruction, we must check for these cases compared to the | |
1833 | instruction previous to the previous instruction. */ | |
1834 | if ((! mips_opts.mips16 | |
252b5132 RH |
1835 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1836 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1837 | && (pinfo & INSN_READ_COND_CODE) | |
1838 | && ! cop_interlocks) | |
1839 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1840 | && (pinfo & INSN_WRITE_LO) | |
1841 | && ! (hilo_interlocks | |
048cdf86 | 1842 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1843 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1844 | && (pinfo & INSN_WRITE_HI) | |
1845 | && ! (hilo_interlocks | |
048cdf86 | 1846 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1847 | prev_prev_nop = 1; |
1848 | else | |
1849 | prev_prev_nop = 0; | |
1850 | ||
1851 | if (prev_prev_insn_unreordered) | |
1852 | prev_prev_nop = 0; | |
1853 | ||
1854 | if (prev_prev_nop && nops == 0) | |
1855 | ++nops; | |
1856 | ||
d766e8ec | 1857 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1858 | { |
1859 | /* We're out of bits in pinfo, so we must resort to string | |
1860 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1861 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1862 | int min_nops = 0; |
1863 | const char *pn = prev_insn.insn_mo->name; | |
1864 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1865 | if (strncmp (pn, "macc", 4) == 0 |
1866 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1867 | { |
1868 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1869 | if (strstr (tn, "div")) | |
532c738a | 1870 | min_nops = 1; |
60b63b72 | 1871 | |
532c738a RS |
1872 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1873 | instruction is executed immediately after a MACC or | |
1874 | DMACC instruction, the result of [either instruction] | |
1875 | is incorrect." */ | |
1876 | if (strncmp (tn, "mult", 4) == 0 | |
1877 | || strncmp (tn, "dmult", 5) == 0) | |
1878 | min_nops = 1; | |
1879 | ||
1880 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1881 | Applies on top of VR4181A MD(1) errata. */ | |
1882 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1883 | min_nops = 1; | |
60b63b72 RS |
1884 | |
1885 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1886 | if (strcmp (tn, "mtlo") == 0 | |
1887 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1888 | min_nops = 1; |
60b63b72 | 1889 | } |
532c738a RS |
1890 | else if (strncmp (pn, "dmult", 5) == 0 |
1891 | && (strncmp (tn, "dmult", 5) == 0 | |
1892 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1893 | { |
1894 | /* Here is the rest of errata 23. */ | |
1895 | min_nops = 1; | |
1896 | } | |
532c738a RS |
1897 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1898 | && (strncmp (tn, "macc", 4) == 0 | |
1899 | || strncmp (tn, "dmacc", 5) == 0)) | |
1900 | { | |
1901 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1902 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1903 | DDIV or DDIVU instruction, the result of the MACC or | |
1904 | DMACC instruction is incorrect.". This partly overlaps | |
1905 | the workaround for errata 23. */ | |
1906 | min_nops = 1; | |
1907 | } | |
60b63b72 RS |
1908 | if (nops < min_nops) |
1909 | nops = min_nops; | |
1910 | } | |
1911 | ||
252b5132 RH |
1912 | /* If we are being given a nop instruction, don't bother with |
1913 | one of the nops we would otherwise output. This will only | |
1914 | happen when a nop instruction is used with mips_optimize set | |
1915 | to 0. */ | |
1916 | if (nops > 0 | |
1917 | && ! mips_opts.noreorder | |
156c2f8b | 1918 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1919 | --nops; |
1920 | ||
1921 | /* Now emit the right number of NOP instructions. */ | |
1922 | if (nops > 0 && ! mips_opts.noreorder) | |
1923 | { | |
1924 | fragS *old_frag; | |
1925 | unsigned long old_frag_offset; | |
1926 | int i; | |
1927 | struct insn_label_list *l; | |
1928 | ||
1929 | old_frag = frag_now; | |
1930 | old_frag_offset = frag_now_fix (); | |
1931 | ||
1932 | for (i = 0; i < nops; i++) | |
1933 | emit_nop (); | |
1934 | ||
1935 | if (listing) | |
1936 | { | |
1937 | listing_prev_line (); | |
1938 | /* We may be at the start of a variant frag. In case we | |
1939 | are, make sure there is enough space for the frag | |
1940 | after the frags created by listing_prev_line. The | |
1941 | argument to frag_grow here must be at least as large | |
1942 | as the argument to all other calls to frag_grow in | |
1943 | this file. We don't have to worry about being in the | |
1944 | middle of a variant frag, because the variants insert | |
1945 | all needed nop instructions themselves. */ | |
1946 | frag_grow (40); | |
1947 | } | |
1948 | ||
1949 | for (l = insn_labels; l != NULL; l = l->next) | |
1950 | { | |
98aa84af AM |
1951 | valueT val; |
1952 | ||
252b5132 | 1953 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1954 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1955 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1956 | /* mips16 text labels are stored as odd. */ |
1957 | if (mips_opts.mips16) | |
f9419b05 | 1958 | ++val; |
98aa84af | 1959 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1960 | } |
1961 | ||
1962 | #ifndef NO_ECOFF_DEBUGGING | |
1963 | if (ECOFF_DEBUGGING) | |
1964 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1965 | #endif | |
1966 | } | |
1967 | else if (prev_nop_frag != NULL) | |
1968 | { | |
1969 | /* We have a frag holding nops we may be able to remove. If | |
1970 | we don't need any nops, we can decrease the size of | |
1971 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1972 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1973 | if (prev_nop_frag_since == 0) |
1974 | { | |
1975 | if (nops == 0) | |
1976 | { | |
1977 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1978 | --prev_nop_frag_holds; | |
1979 | } | |
1980 | else | |
1981 | prev_nop_frag_required += nops; | |
1982 | } | |
1983 | else | |
1984 | { | |
1985 | if (prev_prev_nop == 0) | |
1986 | { | |
1987 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1988 | --prev_nop_frag_holds; | |
1989 | } | |
1990 | else | |
1991 | ++prev_nop_frag_required; | |
1992 | } | |
1993 | ||
1994 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1995 | prev_nop_frag = NULL; | |
1996 | ||
1997 | ++prev_nop_frag_since; | |
1998 | ||
1999 | /* Sanity check: by the time we reach the second instruction | |
2000 | after prev_nop_frag, we should have used up all the nops | |
2001 | one way or another. */ | |
2002 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2003 | } | |
2004 | } | |
2005 | ||
895921c9 MR |
2006 | /* Record the frag type before frag_var. */ |
2007 | if (prev_insn_frag) | |
2008 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2009 | ||
4d7206a2 | 2010 | if (address_expr |
0b25d3e6 | 2011 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2012 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2013 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2014 | && mips_relax_branch | |
2015 | /* Don't try branch relaxation within .set nomacro, or within | |
2016 | .set noat if we use $at for PIC computations. If it turns | |
2017 | out that the branch was out-of-range, we'll get an error. */ | |
2018 | && !mips_opts.warn_about_macros | |
2019 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2020 | && !mips_opts.mips16) | |
2021 | { | |
895921c9 | 2022 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2023 | f = frag_var (rs_machine_dependent, |
2024 | relaxed_branch_length | |
2025 | (NULL, NULL, | |
2026 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2027 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2028 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2029 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2030 | pinfo & INSN_COND_BRANCH_LIKELY, |
2031 | pinfo & INSN_WRITE_GPR_31, | |
2032 | 0), | |
2033 | address_expr->X_add_symbol, | |
2034 | address_expr->X_add_number, | |
2035 | 0); | |
2036 | *reloc_type = BFD_RELOC_UNUSED; | |
2037 | } | |
2038 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2039 | { |
2040 | /* We need to set up a variant frag. */ | |
2041 | assert (mips_opts.mips16 && address_expr != NULL); | |
2042 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2043 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2044 | mips16_small, mips16_ext, |
2045 | (prev_pinfo | |
2046 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2047 | (*prev_insn_reloc_type |
252b5132 | 2048 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2049 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2050 | } |
252b5132 RH |
2051 | else if (mips_opts.mips16 |
2052 | && ! ip->use_extend | |
f6688943 | 2053 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2054 | { |
2055 | /* Make sure there is enough room to swap this instruction with | |
2056 | a following jump instruction. */ | |
2057 | frag_grow (6); | |
2058 | f = frag_more (2); | |
2059 | } | |
2060 | else | |
2061 | { | |
2062 | if (mips_opts.mips16 | |
2063 | && mips_opts.noreorder | |
2064 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2065 | as_warn (_("extended instruction in delay slot")); | |
2066 | ||
4d7206a2 RS |
2067 | if (mips_relax.sequence) |
2068 | { | |
2069 | /* If we've reached the end of this frag, turn it into a variant | |
2070 | frag and record the information for the instructions we've | |
2071 | written so far. */ | |
2072 | if (frag_room () < 4) | |
2073 | relax_close_frag (); | |
2074 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2075 | } | |
2076 | ||
584892a6 RS |
2077 | if (mips_relax.sequence != 2) |
2078 | mips_macro_warning.sizes[0] += 4; | |
2079 | if (mips_relax.sequence != 1) | |
2080 | mips_macro_warning.sizes[1] += 4; | |
2081 | ||
252b5132 RH |
2082 | f = frag_more (4); |
2083 | } | |
2084 | ||
f6688943 | 2085 | fixp[0] = fixp[1] = fixp[2] = NULL; |
01a3f561 | 2086 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2087 | { |
2088 | if (address_expr->X_op == O_constant) | |
2089 | { | |
4db1a35d | 2090 | valueT tmp; |
f6688943 TS |
2091 | |
2092 | switch (*reloc_type) | |
252b5132 RH |
2093 | { |
2094 | case BFD_RELOC_32: | |
2095 | ip->insn_opcode |= address_expr->X_add_number; | |
2096 | break; | |
2097 | ||
f6688943 | 2098 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2099 | tmp = (address_expr->X_add_number |
2100 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2101 | tmp >>= 16; |
2102 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2103 | break; | |
2104 | ||
2105 | case BFD_RELOC_MIPS_HIGHER: | |
2106 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2107 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2108 | break; | |
2109 | ||
2110 | case BFD_RELOC_HI16_S: | |
2111 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2112 | >> 16) & 0xffff; | |
2113 | break; | |
2114 | ||
2115 | case BFD_RELOC_HI16: | |
2116 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2117 | break; | |
2118 | ||
01a3f561 | 2119 | case BFD_RELOC_UNUSED: |
252b5132 | 2120 | case BFD_RELOC_LO16: |
ed6fb7bd | 2121 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2122 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2123 | break; | |
2124 | ||
2125 | case BFD_RELOC_MIPS_JMP: | |
2126 | if ((address_expr->X_add_number & 3) != 0) | |
2127 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2128 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2129 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2130 | as_bad (_("jump address range overflow (0x%lx)"), |
2131 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2132 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2133 | break; | |
2134 | ||
2135 | case BFD_RELOC_MIPS16_JMP: | |
2136 | if ((address_expr->X_add_number & 3) != 0) | |
2137 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2138 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2139 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2140 | as_bad (_("jump address range overflow (0x%lx)"), |
2141 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2142 | ip->insn_opcode |= |
2143 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2144 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2145 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2146 | break; | |
2147 | ||
252b5132 RH |
2148 | case BFD_RELOC_16_PCREL_S2: |
2149 | goto need_reloc; | |
2150 | ||
2151 | default: | |
2152 | internalError (); | |
2153 | } | |
2154 | } | |
01a3f561 | 2155 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2156 | need_reloc: |
4d7206a2 RS |
2157 | { |
2158 | reloc_howto_type *howto; | |
2159 | int i; | |
34ce925e | 2160 | |
4d7206a2 RS |
2161 | /* In a compound relocation, it is the final (outermost) |
2162 | operator that determines the relocated field. */ | |
2163 | for (i = 1; i < 3; i++) | |
2164 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2165 | break; | |
34ce925e | 2166 | |
4d7206a2 RS |
2167 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2168 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2169 | bfd_get_reloc_size(howto), | |
2170 | address_expr, | |
2171 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2172 | reloc_type[0]); | |
2173 | ||
2174 | /* These relocations can have an addend that won't fit in | |
2175 | 4 octets for 64bit assembly. */ | |
2176 | if (HAVE_64BIT_GPRS | |
2177 | && ! howto->partial_inplace | |
2178 | && (reloc_type[0] == BFD_RELOC_16 | |
2179 | || reloc_type[0] == BFD_RELOC_32 | |
2180 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2181 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2182 | || reloc_type[0] == BFD_RELOC_LO16 | |
2183 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2184 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2185 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2186 | || reloc_type[0] == BFD_RELOC_64 | |
2187 | || reloc_type[0] == BFD_RELOC_CTOR | |
2188 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2189 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2190 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2191 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2192 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2193 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
2194 | fixp[0]->fx_no_overflow = 1; | |
2195 | ||
2196 | if (mips_relax.sequence) | |
2197 | { | |
2198 | if (mips_relax.first_fixup == 0) | |
2199 | mips_relax.first_fixup = fixp[0]; | |
2200 | } | |
2201 | else if (reloc_needs_lo_p (*reloc_type)) | |
2202 | { | |
2203 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2204 | |
4d7206a2 RS |
2205 | /* Reuse the last entry if it already has a matching %lo. */ |
2206 | hi_fixup = mips_hi_fixup_list; | |
2207 | if (hi_fixup == 0 | |
2208 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2209 | { | |
2210 | hi_fixup = ((struct mips_hi_fixup *) | |
2211 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2212 | hi_fixup->next = mips_hi_fixup_list; | |
2213 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2214 | } |
4d7206a2 RS |
2215 | hi_fixup->fixp = fixp[0]; |
2216 | hi_fixup->seg = now_seg; | |
2217 | } | |
f6688943 | 2218 | |
4d7206a2 RS |
2219 | /* Add fixups for the second and third relocations, if given. |
2220 | Note that the ABI allows the second relocation to be | |
2221 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2222 | moment we only use RSS_UNDEF, but we could add support | |
2223 | for the others if it ever becomes necessary. */ | |
2224 | for (i = 1; i < 3; i++) | |
2225 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2226 | { | |
6e1304d8 RS |
2227 | fixp[i] = fix_new (frag_now, fixp[0]->fx_where, |
2228 | fixp[0]->fx_size, NULL, 0, | |
2229 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2230 | |
2231 | /* Use fx_tcbit to mark compound relocs. */ | |
2232 | fixp[0]->fx_tcbit = 1; | |
2233 | fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2234 | } |
252b5132 RH |
2235 | } |
2236 | } | |
2237 | ||
2238 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2239 | { |
2240 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2241 | #ifdef OBJ_ELF | |
2242 | dwarf2_emit_insn (4); | |
2243 | #endif | |
2244 | } | |
f6688943 | 2245 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2246 | { |
2247 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2248 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab | 2249 | #ifdef OBJ_ELF |
20e56c33 RS |
2250 | /* The value passed to dwarf2_emit_insn is the distance between |
2251 | the end of the current instruction and the address that should | |
2252 | be recorded in the debug tables. Since we want to use ISA-encoded | |
2253 | addresses in MIPS16 debug info, the value is one byte less than | |
2254 | the real instruction length. */ | |
2255 | dwarf2_emit_insn (3); | |
c5dd6aab | 2256 | #endif |
252b5132 RH |
2257 | } |
2258 | else | |
2259 | { | |
2260 | if (ip->use_extend) | |
2261 | { | |
2262 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2263 | f += 2; | |
2264 | } | |
2265 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab | 2266 | #ifdef OBJ_ELF |
20e56c33 | 2267 | dwarf2_emit_insn (ip->use_extend ? 3 : 1); |
c5dd6aab | 2268 | #endif |
252b5132 RH |
2269 | } |
2270 | ||
2271 | /* Update the register mask information. */ | |
2272 | if (! mips_opts.mips16) | |
2273 | { | |
2274 | if (pinfo & INSN_WRITE_GPR_D) | |
2275 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2276 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2277 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2278 | if (pinfo & INSN_READ_GPR_S) | |
2279 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2280 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2281 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2282 | if (pinfo & INSN_WRITE_FPR_D) |
2283 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2284 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2285 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2286 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2287 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2288 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2289 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2290 | if (pinfo & INSN_COP) | |
2291 | { | |
bdaaa2e1 KH |
2292 | /* We don't keep enough information to sort these cases out. |
2293 | The itbl support does keep this information however, although | |
2294 | we currently don't support itbl fprmats as part of the cop | |
2295 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2296 | } |
2297 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2298 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2299 | } |
2300 | else | |
2301 | { | |
2302 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2303 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2304 | & MIPS16OP_MASK_RX); | |
2305 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2306 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2307 | & MIPS16OP_MASK_RY); | |
2308 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2309 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2310 | & MIPS16OP_MASK_RZ); | |
2311 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2312 | mips_gprmask |= 1 << TREG; | |
2313 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2314 | mips_gprmask |= 1 << SP; | |
2315 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2316 | mips_gprmask |= 1 << RA; | |
2317 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2318 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2319 | if (pinfo & MIPS16_INSN_READ_Z) | |
2320 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2321 | & MIPS16OP_MASK_MOVE32Z); | |
2322 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2323 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2324 | & MIPS16OP_MASK_REGR32); | |
2325 | } | |
2326 | ||
4d7206a2 | 2327 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2328 | { |
2329 | /* Filling the branch delay slot is more complex. We try to | |
2330 | switch the branch with the previous instruction, which we can | |
2331 | do if the previous instruction does not set up a condition | |
2332 | that the branch tests and if the branch is not itself the | |
2333 | target of any branch. */ | |
2334 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2335 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2336 | { | |
2337 | if (mips_optimize < 2 | |
2338 | /* If we have seen .set volatile or .set nomove, don't | |
2339 | optimize. */ | |
2340 | || mips_opts.nomove != 0 | |
2341 | /* If we had to emit any NOP instructions, then we | |
2342 | already know we can not swap. */ | |
2343 | || nops != 0 | |
2344 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2345 | swap. */ |
252b5132 RH |
2346 | || ! prev_insn_valid |
2347 | /* If the previous insn is already in a branch delay | |
2348 | slot, then we can not swap. */ | |
2349 | || prev_insn_is_delay_slot | |
2350 | /* If the previous previous insn was in a .set | |
2351 | noreorder, we can't swap. Actually, the MIPS | |
2352 | assembler will swap in this situation. However, gcc | |
2353 | configured -with-gnu-as will generate code like | |
2354 | .set noreorder | |
2355 | lw $4,XXX | |
2356 | .set reorder | |
2357 | INSN | |
2358 | bne $4,$0,foo | |
2359 | in which we can not swap the bne and INSN. If gcc is | |
2360 | not configured -with-gnu-as, it does not output the | |
2361 | .set pseudo-ops. We don't have to check | |
2362 | prev_insn_unreordered, because prev_insn_valid will | |
2363 | be 0 in that case. We don't want to use | |
2364 | prev_prev_insn_valid, because we do want to be able | |
2365 | to swap at the start of a function. */ | |
2366 | || prev_prev_insn_unreordered | |
2367 | /* If the branch is itself the target of a branch, we | |
2368 | can not swap. We cheat on this; all we check for is | |
2369 | whether there is a label on this instruction. If | |
2370 | there are any branches to anything other than a | |
2371 | label, users must use .set noreorder. */ | |
2372 | || insn_labels != NULL | |
895921c9 MR |
2373 | /* If the previous instruction is in a variant frag |
2374 | other than this branch's one, we cannot do the swap. | |
2375 | This does not apply to the mips16, which uses variant | |
2376 | frags for different purposes. */ | |
252b5132 | 2377 | || (! mips_opts.mips16 |
895921c9 | 2378 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2379 | /* If the branch reads the condition codes, we don't |
2380 | even try to swap, because in the sequence | |
2381 | ctc1 $X,$31 | |
2382 | INSN | |
2383 | INSN | |
2384 | bc1t LABEL | |
2385 | we can not swap, and I don't feel like handling that | |
2386 | case. */ | |
2387 | || (! mips_opts.mips16 | |
81912461 ILT |
2388 | && (pinfo & INSN_READ_COND_CODE) |
2389 | && ! cop_interlocks) | |
252b5132 | 2390 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2391 | delay slot, because the target of the branch might |
252b5132 RH |
2392 | interfere with that instruction. */ |
2393 | || (! mips_opts.mips16 | |
252b5132 | 2394 | && (prev_pinfo |
bdaaa2e1 | 2395 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2396 | & (INSN_LOAD_COPROC_DELAY |
2397 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2398 | | INSN_WRITE_COND_CODE)) |
2399 | && ! cop_interlocks) | |
252b5132 | 2400 | || (! (hilo_interlocks |
048cdf86 | 2401 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2402 | && (prev_pinfo |
2403 | & (INSN_READ_LO | |
2404 | | INSN_READ_HI))) | |
2405 | || (! mips_opts.mips16 | |
81912461 ILT |
2406 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2407 | && ! gpr_interlocks) | |
252b5132 | 2408 | || (! mips_opts.mips16 |
bdaaa2e1 | 2409 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2410 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2411 | && ! cop_mem_interlocks) | |
252b5132 RH |
2412 | /* We can not swap with a branch instruction. */ |
2413 | || (prev_pinfo | |
2414 | & (INSN_UNCOND_BRANCH_DELAY | |
2415 | | INSN_COND_BRANCH_DELAY | |
2416 | | INSN_COND_BRANCH_LIKELY)) | |
2417 | /* We do not swap with a trap instruction, since it | |
2418 | complicates trap handlers to have the trap | |
2419 | instruction be in a delay slot. */ | |
2420 | || (prev_pinfo & INSN_TRAP) | |
2421 | /* If the branch reads a register that the previous | |
2422 | instruction sets, we can not swap. */ | |
2423 | || (! mips_opts.mips16 | |
2424 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2425 | && insn_uses_reg (ip, | |
2426 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2427 | & OP_MASK_RT), | |
2428 | MIPS_GR_REG)) | |
2429 | || (! mips_opts.mips16 | |
2430 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2431 | && insn_uses_reg (ip, | |
2432 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2433 | & OP_MASK_RD), | |
2434 | MIPS_GR_REG)) | |
2435 | || (mips_opts.mips16 | |
2436 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2437 | && insn_uses_reg (ip, | |
2438 | ((prev_insn.insn_opcode | |
2439 | >> MIPS16OP_SH_RX) | |
2440 | & MIPS16OP_MASK_RX), | |
2441 | MIPS16_REG)) | |
2442 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2443 | && insn_uses_reg (ip, | |
2444 | ((prev_insn.insn_opcode | |
2445 | >> MIPS16OP_SH_RY) | |
2446 | & MIPS16OP_MASK_RY), | |
2447 | MIPS16_REG)) | |
2448 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2449 | && insn_uses_reg (ip, | |
2450 | ((prev_insn.insn_opcode | |
2451 | >> MIPS16OP_SH_RZ) | |
2452 | & MIPS16OP_MASK_RZ), | |
2453 | MIPS16_REG)) | |
2454 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2455 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2456 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2457 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2458 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2459 | && insn_uses_reg (ip, | |
2460 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2461 | insn_opcode), | |
2462 | MIPS_GR_REG)))) | |
2463 | /* If the branch writes a register that the previous | |
2464 | instruction sets, we can not swap (we know that | |
2465 | branches write only to RD or to $31). */ | |
2466 | || (! mips_opts.mips16 | |
2467 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2468 | && (((pinfo & INSN_WRITE_GPR_D) | |
2469 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2470 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2471 | || ((pinfo & INSN_WRITE_GPR_31) | |
2472 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2473 | & OP_MASK_RT) | |
f9419b05 | 2474 | == RA)))) |
252b5132 RH |
2475 | || (! mips_opts.mips16 |
2476 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2477 | && (((pinfo & INSN_WRITE_GPR_D) | |
2478 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2479 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2480 | || ((pinfo & INSN_WRITE_GPR_31) | |
2481 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2482 | & OP_MASK_RD) | |
f9419b05 | 2483 | == RA)))) |
252b5132 RH |
2484 | || (mips_opts.mips16 |
2485 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2486 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2487 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2488 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2489 | == RA)))) | |
2490 | /* If the branch writes a register that the previous | |
2491 | instruction reads, we can not swap (we know that | |
2492 | branches only write to RD or to $31). */ | |
2493 | || (! mips_opts.mips16 | |
2494 | && (pinfo & INSN_WRITE_GPR_D) | |
2495 | && insn_uses_reg (&prev_insn, | |
2496 | ((ip->insn_opcode >> OP_SH_RD) | |
2497 | & OP_MASK_RD), | |
2498 | MIPS_GR_REG)) | |
2499 | || (! mips_opts.mips16 | |
2500 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2501 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2502 | || (mips_opts.mips16 |
2503 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2504 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2505 | /* If the previous previous instruction has a load |
2506 | delay, and sets a register that the branch reads, we | |
2507 | can not swap. */ | |
2508 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2509 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2510 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2511 | && ! cop_interlocks) | |
2512 | || ((prev_prev_insn.insn_mo->pinfo | |
2513 | & INSN_LOAD_MEMORY_DELAY) | |
2514 | && ! gpr_interlocks)) | |
252b5132 RH |
2515 | && insn_uses_reg (ip, |
2516 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2517 | & OP_MASK_RT), | |
2518 | MIPS_GR_REG)) | |
2519 | /* If one instruction sets a condition code and the | |
2520 | other one uses a condition code, we can not swap. */ | |
2521 | || ((pinfo & INSN_READ_COND_CODE) | |
2522 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2523 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2524 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2525 | /* If the previous instruction uses the PC, we can not | |
2526 | swap. */ | |
2527 | || (mips_opts.mips16 | |
2528 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2529 | /* If the previous instruction was extended, we can not | |
2530 | swap. */ | |
2531 | || (mips_opts.mips16 && prev_insn_extended) | |
2532 | /* If the previous instruction had a fixup in mips16 | |
2533 | mode, we can not swap. This normally means that the | |
2534 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2535 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2536 | /* If the previous instruction is a sync, sync.l, or |
2537 | sync.p, we can not swap. */ | |
f173e82e | 2538 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2539 | { |
2540 | /* We could do even better for unconditional branches to | |
2541 | portions of this object file; we could pick up the | |
2542 | instruction at the destination, put it in the delay | |
2543 | slot, and bump the destination address. */ | |
2544 | emit_nop (); | |
dd22970f ILT |
2545 | if (mips_relax.sequence) |
2546 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2547 | /* Update the previous insn information. */ |
2548 | prev_prev_insn = *ip; | |
2549 | prev_insn.insn_mo = &dummy_opcode; | |
2550 | } | |
2551 | else | |
2552 | { | |
2553 | /* It looks like we can actually do the swap. */ | |
2554 | if (! mips_opts.mips16) | |
2555 | { | |
2556 | char *prev_f; | |
2557 | char temp[4]; | |
2558 | ||
2559 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2560 | if (!relaxed_branch) |
2561 | { | |
2562 | /* If this is not a relaxed branch, then just | |
2563 | swap the instructions. */ | |
2564 | memcpy (temp, prev_f, 4); | |
2565 | memcpy (prev_f, f, 4); | |
2566 | memcpy (f, temp, 4); | |
2567 | } | |
2568 | else | |
2569 | { | |
2570 | /* If this is a relaxed branch, then we move the | |
2571 | instruction to be placed in the delay slot to | |
2572 | the current frag, shrinking the fixed part of | |
2573 | the originating frag. If the branch occupies | |
2574 | the tail of the latter, we move it backwards, | |
2575 | into the space freed by the moved instruction. */ | |
2576 | f = frag_more (4); | |
2577 | memcpy (f, prev_f, 4); | |
2578 | prev_insn_frag->fr_fix -= 4; | |
2579 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2580 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2581 | } | |
2582 | ||
f6688943 TS |
2583 | if (prev_insn_fixp[0]) |
2584 | { | |
2585 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2586 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2587 | } | |
2588 | if (prev_insn_fixp[1]) | |
2589 | { | |
2590 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2591 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2592 | } | |
2593 | if (prev_insn_fixp[2]) | |
252b5132 | 2594 | { |
f6688943 TS |
2595 | prev_insn_fixp[2]->fx_frag = frag_now; |
2596 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2597 | } |
f5040a92 AO |
2598 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2599 | && prev_insn_frag != frag_now | |
2600 | && (prev_insn_fixp[0]->fx_r_type | |
2601 | == BFD_RELOC_MIPS_GOT_DISP | |
2602 | || (prev_insn_fixp[0]->fx_r_type | |
2603 | == BFD_RELOC_MIPS_CALL16))) | |
2604 | { | |
2605 | /* To avoid confusion in tc_gen_reloc, we must | |
2606 | ensure that this does not become a variant | |
2607 | frag. */ | |
2608 | force_new_frag = TRUE; | |
2609 | } | |
895921c9 MR |
2610 | |
2611 | if (!relaxed_branch) | |
f6688943 | 2612 | { |
895921c9 MR |
2613 | if (fixp[0]) |
2614 | { | |
2615 | fixp[0]->fx_frag = prev_insn_frag; | |
2616 | fixp[0]->fx_where = prev_insn_where; | |
2617 | } | |
2618 | if (fixp[1]) | |
2619 | { | |
2620 | fixp[1]->fx_frag = prev_insn_frag; | |
2621 | fixp[1]->fx_where = prev_insn_where; | |
2622 | } | |
2623 | if (fixp[2]) | |
2624 | { | |
2625 | fixp[2]->fx_frag = prev_insn_frag; | |
2626 | fixp[2]->fx_where = prev_insn_where; | |
2627 | } | |
f6688943 | 2628 | } |
895921c9 | 2629 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2630 | { |
895921c9 MR |
2631 | if (fixp[0]) |
2632 | fixp[0]->fx_where -= 4; | |
2633 | if (fixp[1]) | |
2634 | fixp[1]->fx_where -= 4; | |
2635 | if (fixp[2]) | |
2636 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2637 | } |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | char *prev_f; | |
2642 | char temp[2]; | |
2643 | ||
f6688943 TS |
2644 | assert (prev_insn_fixp[0] == NULL); |
2645 | assert (prev_insn_fixp[1] == NULL); | |
2646 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2647 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2648 | memcpy (temp, prev_f, 2); | |
2649 | memcpy (prev_f, f, 2); | |
f6688943 | 2650 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2651 | { |
f6688943 | 2652 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2653 | memcpy (f, temp, 2); |
2654 | } | |
2655 | else | |
2656 | { | |
2657 | memcpy (f, f + 2, 2); | |
2658 | memcpy (f + 2, temp, 2); | |
2659 | } | |
f6688943 TS |
2660 | if (fixp[0]) |
2661 | { | |
2662 | fixp[0]->fx_frag = prev_insn_frag; | |
2663 | fixp[0]->fx_where = prev_insn_where; | |
2664 | } | |
2665 | if (fixp[1]) | |
2666 | { | |
2667 | fixp[1]->fx_frag = prev_insn_frag; | |
2668 | fixp[1]->fx_where = prev_insn_where; | |
2669 | } | |
2670 | if (fixp[2]) | |
252b5132 | 2671 | { |
f6688943 TS |
2672 | fixp[2]->fx_frag = prev_insn_frag; |
2673 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2674 | } |
2675 | } | |
2676 | ||
2677 | /* Update the previous insn information; leave prev_insn | |
2678 | unchanged. */ | |
2679 | prev_prev_insn = *ip; | |
2680 | } | |
2681 | prev_insn_is_delay_slot = 1; | |
2682 | ||
2683 | /* If that was an unconditional branch, forget the previous | |
2684 | insn information. */ | |
2685 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2686 | { | |
2687 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2688 | prev_insn.insn_mo = &dummy_opcode; | |
2689 | } | |
2690 | ||
f6688943 TS |
2691 | prev_insn_fixp[0] = NULL; |
2692 | prev_insn_fixp[1] = NULL; | |
2693 | prev_insn_fixp[2] = NULL; | |
2694 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2695 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2696 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2697 | prev_insn_extended = 0; |
2698 | } | |
2699 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2700 | { | |
2701 | /* We don't yet optimize a branch likely. What we should do | |
2702 | is look at the target, copy the instruction found there | |
2703 | into the delay slot, and increment the branch to jump to | |
2704 | the next instruction. */ | |
2705 | emit_nop (); | |
2706 | /* Update the previous insn information. */ | |
2707 | prev_prev_insn = *ip; | |
2708 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2709 | prev_insn_fixp[0] = NULL; |
2710 | prev_insn_fixp[1] = NULL; | |
2711 | prev_insn_fixp[2] = NULL; | |
2712 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2713 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2714 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2715 | prev_insn_extended = 0; |
f7870c8d | 2716 | prev_insn_is_delay_slot = 1; |
252b5132 RH |
2717 | } |
2718 | else | |
2719 | { | |
2720 | /* Update the previous insn information. */ | |
2721 | if (nops > 0) | |
2722 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2723 | else | |
2724 | prev_prev_insn = prev_insn; | |
2725 | prev_insn = *ip; | |
2726 | ||
2727 | /* Any time we see a branch, we always fill the delay slot | |
2728 | immediately; since this insn is not a branch, we know it | |
2729 | is not in a delay slot. */ | |
2730 | prev_insn_is_delay_slot = 0; | |
2731 | ||
f6688943 TS |
2732 | prev_insn_fixp[0] = fixp[0]; |
2733 | prev_insn_fixp[1] = fixp[1]; | |
2734 | prev_insn_fixp[2] = fixp[2]; | |
2735 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2736 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2737 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2738 | if (mips_opts.mips16) |
2739 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2740 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2741 | } |
2742 | ||
2743 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2744 | prev_insn_unreordered = 0; | |
2745 | prev_insn_frag = frag_now; | |
2746 | prev_insn_where = f - frag_now->fr_literal; | |
2747 | prev_insn_valid = 1; | |
2748 | } | |
4d7206a2 | 2749 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2750 | { |
2751 | /* We need to record a bit of information even when we are not | |
2752 | reordering, in order to determine the base address for mips16 | |
2753 | PC relative relocs. */ | |
2754 | prev_prev_insn = prev_insn; | |
2755 | prev_insn = *ip; | |
f6688943 TS |
2756 | prev_insn_reloc_type[0] = reloc_type[0]; |
2757 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2758 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2759 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2760 | prev_insn_unreordered = 1; | |
2761 | } | |
2762 | ||
2763 | /* We just output an insn, so the next one doesn't have a label. */ | |
2764 | mips_clear_insn_labels (); | |
252b5132 RH |
2765 | } |
2766 | ||
2767 | /* This function forgets that there was any previous instruction or | |
2768 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2769 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2770 | |
2771 | static void | |
17a2f251 | 2772 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2773 | { |
2774 | if (! preserve) | |
2775 | { | |
2776 | prev_insn.insn_mo = &dummy_opcode; | |
2777 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2778 | prev_nop_frag = NULL; | |
2779 | prev_nop_frag_holds = 0; | |
2780 | prev_nop_frag_required = 0; | |
2781 | prev_nop_frag_since = 0; | |
2782 | } | |
2783 | prev_insn_valid = 0; | |
2784 | prev_insn_is_delay_slot = 0; | |
2785 | prev_insn_unreordered = 0; | |
2786 | prev_insn_extended = 0; | |
f6688943 TS |
2787 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2788 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2789 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2790 | prev_prev_insn_unreordered = 0; |
2791 | mips_clear_insn_labels (); | |
2792 | } | |
2793 | ||
2794 | /* This function must be called whenever we turn on noreorder or emit | |
2795 | something other than instructions. It inserts any NOPS which might | |
2796 | be needed by the previous instruction, and clears the information | |
2797 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2798 | instructions are to follow. */ |
252b5132 RH |
2799 | |
2800 | static void | |
17a2f251 | 2801 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2802 | { |
2803 | if (! mips_opts.noreorder) | |
2804 | { | |
2805 | int nops; | |
2806 | ||
2807 | nops = 0; | |
2808 | if ((! mips_opts.mips16 | |
81912461 ILT |
2809 | && ((prev_insn.insn_mo->pinfo |
2810 | & (INSN_LOAD_COPROC_DELAY | |
2811 | | INSN_COPROC_MOVE_DELAY | |
2812 | | INSN_WRITE_COND_CODE)) | |
2813 | && ! cop_interlocks)) | |
252b5132 RH |
2814 | || (! hilo_interlocks |
2815 | && (prev_insn.insn_mo->pinfo | |
2816 | & (INSN_READ_LO | |
2817 | | INSN_READ_HI))) | |
2818 | || (! mips_opts.mips16 | |
81912461 ILT |
2819 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2820 | && ! gpr_interlocks) | |
252b5132 | 2821 | || (! mips_opts.mips16 |
81912461 ILT |
2822 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2823 | && ! cop_mem_interlocks)) | |
252b5132 | 2824 | { |
beae10d5 | 2825 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2826 | ++nops; |
2827 | if ((! mips_opts.mips16 | |
81912461 ILT |
2828 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2829 | && ! cop_interlocks)) | |
252b5132 RH |
2830 | || (! hilo_interlocks |
2831 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2832 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2833 | ++nops; | |
2834 | ||
2835 | if (prev_insn_unreordered) | |
2836 | nops = 0; | |
2837 | } | |
2838 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2839 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2840 | && ! cop_interlocks)) | |
252b5132 RH |
2841 | || (! hilo_interlocks |
2842 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2843 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2844 | { | |
beae10d5 | 2845 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2846 | if (! prev_prev_insn_unreordered) |
2847 | ++nops; | |
2848 | } | |
2849 | ||
d766e8ec | 2850 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2851 | { |
2852 | int min_nops = 0; | |
2853 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2854 | if (strncmp (pn, "macc", 4) == 0 |
2855 | || strncmp (pn, "dmacc", 5) == 0 | |
2856 | || strncmp (pn, "dmult", 5) == 0 | |
2857 | || strstr (pn, "div")) | |
2858 | min_nops = 1; | |
60b63b72 RS |
2859 | if (nops < min_nops) |
2860 | nops = min_nops; | |
2861 | } | |
2862 | ||
252b5132 RH |
2863 | if (nops > 0) |
2864 | { | |
2865 | struct insn_label_list *l; | |
2866 | ||
2867 | if (insns) | |
2868 | { | |
2869 | /* Record the frag which holds the nop instructions, so | |
2870 | that we can remove them if we don't need them. */ | |
2871 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2872 | prev_nop_frag = frag_now; | |
2873 | prev_nop_frag_holds = nops; | |
2874 | prev_nop_frag_required = 0; | |
2875 | prev_nop_frag_since = 0; | |
2876 | } | |
2877 | ||
2878 | for (; nops > 0; --nops) | |
2879 | emit_nop (); | |
2880 | ||
2881 | if (insns) | |
2882 | { | |
2883 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2884 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2885 | frag_wane (frag_now); |
2886 | frag_new (0); | |
2887 | } | |
2888 | ||
2889 | for (l = insn_labels; l != NULL; l = l->next) | |
2890 | { | |
98aa84af AM |
2891 | valueT val; |
2892 | ||
252b5132 | 2893 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2894 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2895 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2896 | /* mips16 text labels are stored as odd. */ |
2897 | if (mips_opts.mips16) | |
f9419b05 | 2898 | ++val; |
98aa84af | 2899 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2900 | } |
2901 | } | |
2902 | } | |
2903 | ||
2904 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2905 | if (insns) |
252b5132 RH |
2906 | mips16_mark_labels (); |
2907 | ||
2908 | mips_no_prev_insn (insns); | |
2909 | } | |
2910 | ||
584892a6 RS |
2911 | /* Set up global variables for the start of a new macro. */ |
2912 | ||
2913 | static void | |
2914 | macro_start (void) | |
2915 | { | |
2916 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2917 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2918 | && (prev_insn.insn_mo->pinfo | |
2919 | & (INSN_UNCOND_BRANCH_DELAY | |
2920 | | INSN_COND_BRANCH_DELAY | |
2921 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2922 | } | |
2923 | ||
2924 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2925 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2926 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2927 | ||
2928 | static const char * | |
2929 | macro_warning (relax_substateT subtype) | |
2930 | { | |
2931 | if (subtype & RELAX_DELAY_SLOT) | |
2932 | return _("Macro instruction expanded into multiple instructions" | |
2933 | " in a branch delay slot"); | |
2934 | else if (subtype & RELAX_NOMACRO) | |
2935 | return _("Macro instruction expanded into multiple instructions"); | |
2936 | else | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2941 | ||
2942 | static void | |
2943 | macro_end (void) | |
2944 | { | |
2945 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2946 | { | |
2947 | relax_substateT subtype; | |
2948 | ||
2949 | /* Set up the relaxation warning flags. */ | |
2950 | subtype = 0; | |
2951 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2952 | subtype |= RELAX_SECOND_LONGER; | |
2953 | if (mips_opts.warn_about_macros) | |
2954 | subtype |= RELAX_NOMACRO; | |
2955 | if (mips_macro_warning.delay_slot_p) | |
2956 | subtype |= RELAX_DELAY_SLOT; | |
2957 | ||
2958 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2959 | { | |
2960 | /* Either the macro has a single implementation or both | |
2961 | implementations are longer than 4 bytes. Emit the | |
2962 | warning now. */ | |
2963 | const char *msg = macro_warning (subtype); | |
2964 | if (msg != 0) | |
2965 | as_warn (msg); | |
2966 | } | |
2967 | else | |
2968 | { | |
2969 | /* One implementation might need a warning but the other | |
2970 | definitely doesn't. */ | |
2971 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2972 | } | |
2973 | } | |
2974 | } | |
2975 | ||
6e1304d8 RS |
2976 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2977 | The first argument in *ARGS will be either the code for a single | |
2978 | relocation or -1 followed by the three codes that make up a | |
2979 | composite relocation. */ | |
2980 | ||
2981 | static void | |
2982 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2983 | { | |
2984 | int i, next; | |
2985 | ||
2986 | next = va_arg (*args, int); | |
2987 | if (next >= 0) | |
2988 | r[0] = (bfd_reloc_code_real_type) next; | |
2989 | else | |
2990 | for (i = 0; i < 3; i++) | |
2991 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2992 | } | |
2993 | ||
252b5132 RH |
2994 | /* Build an instruction created by a macro expansion. This is passed |
2995 | a pointer to the count of instructions created so far, an | |
2996 | expression, the name of the instruction to build, an operand format | |
2997 | string, and corresponding arguments. */ | |
2998 | ||
252b5132 | 2999 | static void |
67c0d1eb | 3000 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
3001 | { |
3002 | struct mips_cl_insn insn; | |
f6688943 | 3003 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3004 | va_list args; |
252b5132 | 3005 | |
252b5132 | 3006 | va_start (args, fmt); |
252b5132 | 3007 | |
252b5132 RH |
3008 | if (mips_opts.mips16) |
3009 | { | |
67c0d1eb | 3010 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3011 | va_end (args); |
3012 | return; | |
3013 | } | |
3014 | ||
f6688943 TS |
3015 | r[0] = BFD_RELOC_UNUSED; |
3016 | r[1] = BFD_RELOC_UNUSED; | |
3017 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
3018 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3019 | assert (insn.insn_mo); | |
3020 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3021 | ||
3022 | /* Search until we get a match for NAME. */ | |
3023 | while (1) | |
3024 | { | |
b34976b6 | 3025 | /* It is assumed here that macros will never generate |
deec1734 | 3026 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3027 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3028 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3029 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3030 | (mips_opts.isa | |
3396de36 | 3031 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3032 | mips_opts.arch) |
3033 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3034 | break; |
3035 | ||
3036 | ++insn.insn_mo; | |
3037 | assert (insn.insn_mo->name); | |
3038 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3039 | } | |
3040 | ||
3041 | insn.insn_opcode = insn.insn_mo->match; | |
3042 | for (;;) | |
3043 | { | |
3044 | switch (*fmt++) | |
3045 | { | |
3046 | case '\0': | |
3047 | break; | |
3048 | ||
3049 | case ',': | |
3050 | case '(': | |
3051 | case ')': | |
3052 | continue; | |
3053 | ||
5f74bc13 CD |
3054 | case '+': |
3055 | switch (*fmt++) | |
3056 | { | |
3057 | case 'A': | |
3058 | case 'E': | |
3059 | insn.insn_opcode |= (va_arg (args, int) | |
3060 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3061 | continue; | |
3062 | ||
3063 | case 'B': | |
3064 | case 'F': | |
3065 | /* Note that in the macro case, these arguments are already | |
3066 | in MSB form. (When handling the instruction in the | |
3067 | non-macro case, these arguments are sizes from which | |
3068 | MSB values must be calculated.) */ | |
3069 | insn.insn_opcode |= (va_arg (args, int) | |
3070 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3071 | continue; | |
3072 | ||
3073 | case 'C': | |
3074 | case 'G': | |
3075 | case 'H': | |
3076 | /* Note that in the macro case, these arguments are already | |
3077 | in MSBD form. (When handling the instruction in the | |
3078 | non-macro case, these arguments are sizes from which | |
3079 | MSBD values must be calculated.) */ | |
3080 | insn.insn_opcode |= (va_arg (args, int) | |
3081 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3082 | continue; | |
3083 | ||
3084 | default: | |
3085 | internalError (); | |
3086 | } | |
3087 | continue; | |
3088 | ||
252b5132 RH |
3089 | case 't': |
3090 | case 'w': | |
3091 | case 'E': | |
38487616 | 3092 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3093 | continue; |
3094 | ||
3095 | case 'c': | |
38487616 TS |
3096 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3097 | continue; | |
3098 | ||
252b5132 RH |
3099 | case 'T': |
3100 | case 'W': | |
38487616 | 3101 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3102 | continue; |
3103 | ||
3104 | case 'd': | |
3105 | case 'G': | |
af7ee8bf | 3106 | case 'K': |
38487616 | 3107 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3108 | continue; |
3109 | ||
4372b673 NC |
3110 | case 'U': |
3111 | { | |
3112 | int tmp = va_arg (args, int); | |
3113 | ||
38487616 TS |
3114 | insn.insn_opcode |= tmp << OP_SH_RT; |
3115 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3116 | continue; |
4372b673 NC |
3117 | } |
3118 | ||
252b5132 RH |
3119 | case 'V': |
3120 | case 'S': | |
38487616 | 3121 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3122 | continue; |
3123 | ||
3124 | case 'z': | |
3125 | continue; | |
3126 | ||
3127 | case '<': | |
38487616 | 3128 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3129 | continue; |
3130 | ||
3131 | case 'D': | |
38487616 | 3132 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3133 | continue; |
3134 | ||
3135 | case 'B': | |
38487616 | 3136 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3137 | continue; |
3138 | ||
4372b673 | 3139 | case 'J': |
38487616 | 3140 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3141 | continue; |
3142 | ||
252b5132 | 3143 | case 'q': |
38487616 | 3144 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3145 | continue; |
3146 | ||
3147 | case 'b': | |
3148 | case 's': | |
3149 | case 'r': | |
3150 | case 'v': | |
38487616 | 3151 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3152 | continue; |
3153 | ||
3154 | case 'i': | |
3155 | case 'j': | |
3156 | case 'o': | |
6e1304d8 | 3157 | macro_read_relocs (&args, r); |
cdf6fd85 | 3158 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3159 | || *r == BFD_RELOC_MIPS_LITERAL |
3160 | || *r == BFD_RELOC_MIPS_HIGHER | |
3161 | || *r == BFD_RELOC_HI16_S | |
3162 | || *r == BFD_RELOC_LO16 | |
3163 | || *r == BFD_RELOC_MIPS_GOT16 | |
3164 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3165 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3166 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3167 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3168 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3169 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3170 | continue; |
3171 | ||
3172 | case 'u': | |
6e1304d8 | 3173 | macro_read_relocs (&args, r); |
252b5132 RH |
3174 | assert (ep != NULL |
3175 | && (ep->X_op == O_constant | |
3176 | || (ep->X_op == O_symbol | |
f6688943 TS |
3177 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3178 | || *r == BFD_RELOC_HI16_S | |
3179 | || *r == BFD_RELOC_HI16 | |
3180 | || *r == BFD_RELOC_GPREL16 | |
3181 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3182 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3183 | continue; |
3184 | ||
3185 | case 'p': | |
3186 | assert (ep != NULL); | |
3187 | /* | |
3188 | * This allows macro() to pass an immediate expression for | |
3189 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3190 | * Note that the expression still might come from the assembly |
3191 | * input, in which case the value is not checked for range nor | |
3192 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3193 | */ |
3194 | if (ep->X_op == O_constant) | |
3195 | { | |
3196 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3197 | ep = NULL; | |
3198 | } | |
3199 | else | |
0b25d3e6 | 3200 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3201 | continue; |
3202 | ||
3203 | case 'a': | |
3204 | assert (ep != NULL); | |
f6688943 | 3205 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3206 | continue; |
3207 | ||
3208 | case 'C': | |
3209 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3210 | continue; | |
3211 | ||
3212 | default: | |
3213 | internalError (); | |
3214 | } | |
3215 | break; | |
3216 | } | |
3217 | va_end (args); | |
f6688943 | 3218 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3219 | |
4d7206a2 | 3220 | append_insn (&insn, ep, r); |
252b5132 RH |
3221 | } |
3222 | ||
3223 | static void | |
67c0d1eb | 3224 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3225 | va_list args) |
252b5132 RH |
3226 | { |
3227 | struct mips_cl_insn insn; | |
f6688943 TS |
3228 | bfd_reloc_code_real_type r[3] |
3229 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3230 | |
252b5132 RH |
3231 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3232 | assert (insn.insn_mo); | |
3233 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3234 | ||
3235 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3236 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3237 | { | |
3238 | ++insn.insn_mo; | |
3239 | assert (insn.insn_mo->name); | |
3240 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3241 | } | |
3242 | ||
3243 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3244 | insn.use_extend = FALSE; |
252b5132 RH |
3245 | |
3246 | for (;;) | |
3247 | { | |
3248 | int c; | |
3249 | ||
3250 | c = *fmt++; | |
3251 | switch (c) | |
3252 | { | |
3253 | case '\0': | |
3254 | break; | |
3255 | ||
3256 | case ',': | |
3257 | case '(': | |
3258 | case ')': | |
3259 | continue; | |
3260 | ||
3261 | case 'y': | |
3262 | case 'w': | |
3263 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3264 | continue; | |
3265 | ||
3266 | case 'x': | |
3267 | case 'v': | |
3268 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3269 | continue; | |
3270 | ||
3271 | case 'z': | |
3272 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3273 | continue; | |
3274 | ||
3275 | case 'Z': | |
3276 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3277 | continue; | |
3278 | ||
3279 | case '0': | |
3280 | case 'S': | |
3281 | case 'P': | |
3282 | case 'R': | |
3283 | continue; | |
3284 | ||
3285 | case 'X': | |
3286 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3287 | continue; | |
3288 | ||
3289 | case 'Y': | |
3290 | { | |
3291 | int regno; | |
3292 | ||
3293 | regno = va_arg (args, int); | |
3294 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3295 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3296 | } | |
3297 | continue; | |
3298 | ||
3299 | case '<': | |
3300 | case '>': | |
3301 | case '4': | |
3302 | case '5': | |
3303 | case 'H': | |
3304 | case 'W': | |
3305 | case 'D': | |
3306 | case 'j': | |
3307 | case '8': | |
3308 | case 'V': | |
3309 | case 'C': | |
3310 | case 'U': | |
3311 | case 'k': | |
3312 | case 'K': | |
3313 | case 'p': | |
3314 | case 'q': | |
3315 | { | |
3316 | assert (ep != NULL); | |
3317 | ||
3318 | if (ep->X_op != O_constant) | |
874e8986 | 3319 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3320 | else |
3321 | { | |
b34976b6 AM |
3322 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3323 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3324 | &insn.extend); |
252b5132 | 3325 | ep = NULL; |
f6688943 | 3326 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3327 | } |
3328 | } | |
3329 | continue; | |
3330 | ||
3331 | case '6': | |
3332 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3333 | continue; | |
3334 | } | |
3335 | ||
3336 | break; | |
3337 | } | |
3338 | ||
f6688943 | 3339 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3340 | |
4d7206a2 | 3341 | append_insn (&insn, ep, r); |
252b5132 RH |
3342 | } |
3343 | ||
438c16b8 TS |
3344 | /* |
3345 | * Generate a "jalr" instruction with a relocation hint to the called | |
3346 | * function. This occurs in NewABI PIC code. | |
3347 | */ | |
3348 | static void | |
67c0d1eb | 3349 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3350 | { |
685736be | 3351 | char *f = NULL; |
b34976b6 | 3352 | |
438c16b8 | 3353 | if (HAVE_NEWABI) |
f21f8242 | 3354 | { |
cc3d92a5 | 3355 | frag_grow (8); |
f21f8242 AO |
3356 | f = frag_more (0); |
3357 | } | |
67c0d1eb | 3358 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3359 | if (HAVE_NEWABI) |
f21f8242 | 3360 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3361 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3362 | } |
3363 | ||
252b5132 RH |
3364 | /* |
3365 | * Generate a "lui" instruction. | |
3366 | */ | |
3367 | static void | |
67c0d1eb | 3368 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3369 | { |
3370 | expressionS high_expr; | |
3371 | struct mips_cl_insn insn; | |
f6688943 TS |
3372 | bfd_reloc_code_real_type r[3] |
3373 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3374 | const char *name = "lui"; |
3375 | const char *fmt = "t,u"; | |
252b5132 RH |
3376 | |
3377 | assert (! mips_opts.mips16); | |
3378 | ||
4d7206a2 | 3379 | high_expr = *ep; |
252b5132 RH |
3380 | |
3381 | if (high_expr.X_op == O_constant) | |
3382 | { | |
3383 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3384 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3385 | >> 16) & 0xffff; | |
f6688943 | 3386 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3387 | } |
78e1bb40 | 3388 | else |
252b5132 RH |
3389 | { |
3390 | assert (ep->X_op == O_symbol); | |
3391 | /* _gp_disp is a special case, used from s_cpload. */ | |
3392 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3393 | || (! HAVE_NEWABI |
3394 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3395 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3396 | } |
3397 | ||
252b5132 RH |
3398 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3399 | assert (insn.insn_mo); | |
3400 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3401 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3402 | ||
3403 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3404 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3405 | { |
3406 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3407 | append_insn (&insn, NULL, r); |
252b5132 RH |
3408 | } |
3409 | else | |
4d7206a2 | 3410 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3411 | } |
3412 | ||
885add95 CD |
3413 | /* Generate a sequence of instructions to do a load or store from a constant |
3414 | offset off of a base register (breg) into/from a target register (treg), | |
3415 | using AT if necessary. */ | |
3416 | static void | |
67c0d1eb RS |
3417 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3418 | int treg, int breg, int dbl) | |
885add95 CD |
3419 | { |
3420 | assert (ep->X_op == O_constant); | |
3421 | ||
256ab948 | 3422 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3423 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3424 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3425 | { |
d17e7bce | 3426 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3427 | as_bad (_("constant too large")); |
ae826530 | 3428 | |
1b8e29e5 TS |
3429 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3430 | - 0x80000000); | |
ae826530 | 3431 | } |
256ab948 | 3432 | |
67c1ffbe | 3433 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3434 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3435 | as_warn (_("operand overflow")); |
3436 | ||
3437 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3438 | { | |
3439 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3440 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3441 | } |
3442 | else | |
3443 | { | |
3444 | /* 32-bit offset, need multiple instructions and AT, like: | |
3445 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3446 | addu $tempreg,$tempreg,$breg | |
3447 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3448 | to handle the complete offset. */ | |
67c0d1eb RS |
3449 | macro_build_lui (ep, AT); |
3450 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3451 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3452 | |
3453 | if (mips_opts.noat) | |
3454 | as_warn (_("Macro used $at after \".set noat\"")); | |
3455 | } | |
3456 | } | |
3457 | ||
252b5132 RH |
3458 | /* set_at() |
3459 | * Generates code to set the $at register to true (one) | |
3460 | * if reg is less than the immediate expression. | |
3461 | */ | |
3462 | static void | |
67c0d1eb | 3463 | set_at (int reg, int unsignedp) |
252b5132 RH |
3464 | { |
3465 | if (imm_expr.X_op == O_constant | |
3466 | && imm_expr.X_add_number >= -0x8000 | |
3467 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3468 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3469 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3470 | else |
3471 | { | |
67c0d1eb RS |
3472 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3473 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3474 | } |
3475 | } | |
3476 | ||
13757d0c TS |
3477 | static void |
3478 | normalize_constant_expr (expressionS *ex) | |
3479 | { | |
3480 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3481 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3482 | - 0x80000000); | |
3483 | } | |
3484 | ||
252b5132 RH |
3485 | /* Warn if an expression is not a constant. */ |
3486 | ||
3487 | static void | |
17a2f251 | 3488 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3489 | { |
3490 | if (ex->X_op == O_big) | |
3491 | as_bad (_("unsupported large constant")); | |
3492 | else if (ex->X_op != O_constant) | |
3493 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3494 | |
3495 | normalize_constant_expr (ex); | |
252b5132 RH |
3496 | } |
3497 | ||
3498 | /* Count the leading zeroes by performing a binary chop. This is a | |
3499 | bulky bit of source, but performance is a LOT better for the | |
3500 | majority of values than a simple loop to count the bits: | |
3501 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3502 | if ((v) & (1 << (31 - lcnt))) | |
3503 | break; | |
3504 | However it is not code size friendly, and the gain will drop a bit | |
3505 | on certain cached systems. | |
3506 | */ | |
3507 | #define COUNT_TOP_ZEROES(v) \ | |
3508 | (((v) & ~0xffff) == 0 \ | |
3509 | ? ((v) & ~0xff) == 0 \ | |
3510 | ? ((v) & ~0xf) == 0 \ | |
3511 | ? ((v) & ~0x3) == 0 \ | |
3512 | ? ((v) & ~0x1) == 0 \ | |
3513 | ? !(v) \ | |
3514 | ? 32 \ | |
3515 | : 31 \ | |
3516 | : 30 \ | |
3517 | : ((v) & ~0x7) == 0 \ | |
3518 | ? 29 \ | |
3519 | : 28 \ | |
3520 | : ((v) & ~0x3f) == 0 \ | |
3521 | ? ((v) & ~0x1f) == 0 \ | |
3522 | ? 27 \ | |
3523 | : 26 \ | |
3524 | : ((v) & ~0x7f) == 0 \ | |
3525 | ? 25 \ | |
3526 | : 24 \ | |
3527 | : ((v) & ~0xfff) == 0 \ | |
3528 | ? ((v) & ~0x3ff) == 0 \ | |
3529 | ? ((v) & ~0x1ff) == 0 \ | |
3530 | ? 23 \ | |
3531 | : 22 \ | |
3532 | : ((v) & ~0x7ff) == 0 \ | |
3533 | ? 21 \ | |
3534 | : 20 \ | |
3535 | : ((v) & ~0x3fff) == 0 \ | |
3536 | ? ((v) & ~0x1fff) == 0 \ | |
3537 | ? 19 \ | |
3538 | : 18 \ | |
3539 | : ((v) & ~0x7fff) == 0 \ | |
3540 | ? 17 \ | |
3541 | : 16 \ | |
3542 | : ((v) & ~0xffffff) == 0 \ | |
3543 | ? ((v) & ~0xfffff) == 0 \ | |
3544 | ? ((v) & ~0x3ffff) == 0 \ | |
3545 | ? ((v) & ~0x1ffff) == 0 \ | |
3546 | ? 15 \ | |
3547 | : 14 \ | |
3548 | : ((v) & ~0x7ffff) == 0 \ | |
3549 | ? 13 \ | |
3550 | : 12 \ | |
3551 | : ((v) & ~0x3fffff) == 0 \ | |
3552 | ? ((v) & ~0x1fffff) == 0 \ | |
3553 | ? 11 \ | |
3554 | : 10 \ | |
3555 | : ((v) & ~0x7fffff) == 0 \ | |
3556 | ? 9 \ | |
3557 | : 8 \ | |
3558 | : ((v) & ~0xfffffff) == 0 \ | |
3559 | ? ((v) & ~0x3ffffff) == 0 \ | |
3560 | ? ((v) & ~0x1ffffff) == 0 \ | |
3561 | ? 7 \ | |
3562 | : 6 \ | |
3563 | : ((v) & ~0x7ffffff) == 0 \ | |
3564 | ? 5 \ | |
3565 | : 4 \ | |
3566 | : ((v) & ~0x3fffffff) == 0 \ | |
3567 | ? ((v) & ~0x1fffffff) == 0 \ | |
3568 | ? 3 \ | |
3569 | : 2 \ | |
3570 | : ((v) & ~0x7fffffff) == 0 \ | |
3571 | ? 1 \ | |
3572 | : 0) | |
3573 | ||
3574 | /* load_register() | |
67c1ffbe | 3575 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3576 | * an absolute expression value into a register. |
3577 | */ | |
3578 | static void | |
67c0d1eb | 3579 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3580 | { |
3581 | int freg; | |
3582 | expressionS hi32, lo32; | |
3583 | ||
3584 | if (ep->X_op != O_big) | |
3585 | { | |
3586 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3587 | |
3588 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3589 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3590 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3591 | { |
d17e7bce | 3592 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3593 | as_bad (_("constant too large")); |
ae826530 | 3594 | |
1b8e29e5 TS |
3595 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3596 | - 0x80000000); | |
ae826530 | 3597 | } |
256ab948 TS |
3598 | |
3599 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3600 | { |
3601 | /* We can handle 16 bit signed values with an addiu to | |
3602 | $zero. No need to ever use daddiu here, since $zero and | |
3603 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3604 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3605 | return; |
3606 | } | |
3607 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3608 | { | |
3609 | /* We can handle 16 bit unsigned values with an ori to | |
3610 | $zero. */ | |
67c0d1eb | 3611 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3612 | return; |
3613 | } | |
256ab948 | 3614 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3615 | { |
3616 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3617 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3618 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3619 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3620 | return; |
3621 | } | |
3622 | } | |
3623 | ||
3624 | /* The value is larger than 32 bits. */ | |
3625 | ||
ca4e0257 | 3626 | if (HAVE_32BIT_GPRS) |
252b5132 | 3627 | { |
956cd1d6 TS |
3628 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3629 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3630 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3631 | return; |
3632 | } | |
3633 | ||
3634 | if (ep->X_op != O_big) | |
3635 | { | |
3636 | hi32 = *ep; | |
3637 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3638 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3639 | hi32.X_add_number &= 0xffffffff; | |
3640 | lo32 = *ep; | |
3641 | lo32.X_add_number &= 0xffffffff; | |
3642 | } | |
3643 | else | |
3644 | { | |
3645 | assert (ep->X_add_number > 2); | |
3646 | if (ep->X_add_number == 3) | |
3647 | generic_bignum[3] = 0; | |
3648 | else if (ep->X_add_number > 4) | |
3649 | as_bad (_("Number larger than 64 bits")); | |
3650 | lo32.X_op = O_constant; | |
3651 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3652 | hi32.X_op = O_constant; | |
3653 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3654 | } | |
3655 | ||
3656 | if (hi32.X_add_number == 0) | |
3657 | freg = 0; | |
3658 | else | |
3659 | { | |
3660 | int shift, bit; | |
3661 | unsigned long hi, lo; | |
3662 | ||
956cd1d6 | 3663 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3664 | { |
3665 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3666 | { | |
67c0d1eb | 3667 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3668 | return; |
3669 | } | |
3670 | if (lo32.X_add_number & 0x80000000) | |
3671 | { | |
67c0d1eb | 3672 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3673 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3674 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3675 | return; |
3676 | } | |
3677 | } | |
252b5132 RH |
3678 | |
3679 | /* Check for 16bit shifted constant. We know that hi32 is | |
3680 | non-zero, so start the mask on the first bit of the hi32 | |
3681 | value. */ | |
3682 | shift = 17; | |
3683 | do | |
beae10d5 KH |
3684 | { |
3685 | unsigned long himask, lomask; | |
3686 | ||
3687 | if (shift < 32) | |
3688 | { | |
3689 | himask = 0xffff >> (32 - shift); | |
3690 | lomask = (0xffff << shift) & 0xffffffff; | |
3691 | } | |
3692 | else | |
3693 | { | |
3694 | himask = 0xffff << (shift - 32); | |
3695 | lomask = 0; | |
3696 | } | |
3697 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3698 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3699 | { | |
3700 | expressionS tmp; | |
3701 | ||
3702 | tmp.X_op = O_constant; | |
3703 | if (shift < 32) | |
3704 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3705 | | (lo32.X_add_number >> shift)); | |
3706 | else | |
3707 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3708 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3709 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3710 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3711 | return; |
3712 | } | |
f9419b05 | 3713 | ++shift; |
beae10d5 KH |
3714 | } |
3715 | while (shift <= (64 - 16)); | |
252b5132 RH |
3716 | |
3717 | /* Find the bit number of the lowest one bit, and store the | |
3718 | shifted value in hi/lo. */ | |
3719 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3720 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3721 | if (lo != 0) | |
3722 | { | |
3723 | bit = 0; | |
3724 | while ((lo & 1) == 0) | |
3725 | { | |
3726 | lo >>= 1; | |
3727 | ++bit; | |
3728 | } | |
3729 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3730 | hi >>= bit; | |
3731 | } | |
3732 | else | |
3733 | { | |
3734 | bit = 32; | |
3735 | while ((hi & 1) == 0) | |
3736 | { | |
3737 | hi >>= 1; | |
3738 | ++bit; | |
3739 | } | |
3740 | lo = hi; | |
3741 | hi = 0; | |
3742 | } | |
3743 | ||
3744 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3745 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3746 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3747 | { |
3748 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3749 | if (shift != 0) |
beae10d5 | 3750 | { |
252b5132 RH |
3751 | expressionS tmp; |
3752 | ||
3753 | /* This instruction will set the register to be all | |
3754 | ones. */ | |
beae10d5 KH |
3755 | tmp.X_op = O_constant; |
3756 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3757 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3758 | if (bit != 0) |
3759 | { | |
3760 | bit += shift; | |
67c0d1eb RS |
3761 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3762 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3763 | } |
67c0d1eb RS |
3764 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3765 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3766 | return; |
3767 | } | |
3768 | } | |
252b5132 RH |
3769 | |
3770 | /* Sign extend hi32 before calling load_register, because we can | |
3771 | generally get better code when we load a sign extended value. */ | |
3772 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3773 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3774 | load_register (reg, &hi32, 0); |
252b5132 RH |
3775 | freg = reg; |
3776 | } | |
3777 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3778 | { | |
3779 | if (freg != 0) | |
3780 | { | |
67c0d1eb | 3781 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3782 | freg = reg; |
3783 | } | |
3784 | } | |
3785 | else | |
3786 | { | |
3787 | expressionS mid16; | |
3788 | ||
956cd1d6 | 3789 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3790 | { |
67c0d1eb RS |
3791 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3792 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3793 | return; |
3794 | } | |
252b5132 RH |
3795 | |
3796 | if (freg != 0) | |
3797 | { | |
67c0d1eb | 3798 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3799 | freg = reg; |
3800 | } | |
3801 | mid16 = lo32; | |
3802 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3803 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3804 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3805 | freg = reg; |
3806 | } | |
3807 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3808 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3809 | } |
3810 | ||
269137b2 TS |
3811 | static inline void |
3812 | load_delay_nop (void) | |
3813 | { | |
3814 | if (!gpr_interlocks) | |
3815 | macro_build (NULL, "nop", ""); | |
3816 | } | |
3817 | ||
252b5132 RH |
3818 | /* Load an address into a register. */ |
3819 | ||
3820 | static void | |
67c0d1eb | 3821 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3822 | { |
252b5132 RH |
3823 | if (ep->X_op != O_constant |
3824 | && ep->X_op != O_symbol) | |
3825 | { | |
3826 | as_bad (_("expression too complex")); | |
3827 | ep->X_op = O_constant; | |
3828 | } | |
3829 | ||
3830 | if (ep->X_op == O_constant) | |
3831 | { | |
67c0d1eb | 3832 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3833 | return; |
3834 | } | |
3835 | ||
3836 | if (mips_pic == NO_PIC) | |
3837 | { | |
3838 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3839 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3840 | Otherwise we want |
3841 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3842 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3843 | If we have an addend, we always use the latter form. |
76b3015f | 3844 | |
d6bc6245 TS |
3845 | With 64bit address space and a usable $at we want |
3846 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3847 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3848 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3849 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3850 | dsll32 $reg,0 | |
3a482fd5 | 3851 | daddu $reg,$reg,$at |
76b3015f | 3852 | |
c03099e6 | 3853 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3854 | on superscalar processors. |
3855 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3856 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3857 | dsll $reg,16 | |
3858 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3859 | dsll $reg,16 | |
3860 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3861 | */ | |
c9914766 | 3862 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3863 | { |
e864ceca RS |
3864 | /* ??? We don't provide a GP-relative alternative for these macros. |
3865 | It used not to be possible with the original relaxation code, | |
3866 | but it could be done now. */ | |
d6bc6245 | 3867 | |
460597ba | 3868 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 3869 | { |
67c0d1eb RS |
3870 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3871 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3872 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3873 | BFD_RELOC_MIPS_HIGHER); | |
3874 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3875 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3876 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3877 | *used_at = 1; |
3878 | } | |
3879 | else | |
3880 | { | |
67c0d1eb RS |
3881 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3882 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3883 | BFD_RELOC_MIPS_HIGHER); | |
3884 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3885 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3886 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3887 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3888 | } |
3889 | } | |
252b5132 RH |
3890 | else |
3891 | { | |
d6bc6245 TS |
3892 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3893 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3894 | { | |
4d7206a2 | 3895 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3896 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3897 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3898 | relax_switch (); |
d6bc6245 | 3899 | } |
67c0d1eb RS |
3900 | macro_build_lui (ep, reg); |
3901 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3902 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3903 | if (mips_relax.sequence) |
3904 | relax_end (); | |
d6bc6245 | 3905 | } |
252b5132 RH |
3906 | } |
3907 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3908 | { | |
3909 | expressionS ex; | |
3910 | ||
3911 | /* If this is a reference to an external symbol, we want | |
3912 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3913 | Otherwise we want | |
3914 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3915 | nop | |
3916 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3917 | If there is a constant, it must be added in after. |
3918 | ||
ed6fb7bd | 3919 | If we have NewABI, we want |
f5040a92 AO |
3920 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3921 | unless we're referencing a global symbol with a non-zero | |
3922 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3923 | if (HAVE_NEWABI) |
3924 | { | |
f5040a92 AO |
3925 | if (ep->X_add_number) |
3926 | { | |
4d7206a2 | 3927 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3928 | ep->X_add_number = 0; |
4d7206a2 | 3929 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3930 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3931 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3932 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3933 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3934 | ex.X_op = O_constant; | |
67c0d1eb | 3935 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3936 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3937 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3938 | relax_switch (); |
f5040a92 | 3939 | } |
67c0d1eb | 3940 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3941 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3942 | if (mips_relax.sequence) |
3943 | relax_end (); | |
ed6fb7bd SC |
3944 | } |
3945 | else | |
3946 | { | |
f5040a92 AO |
3947 | ex.X_add_number = ep->X_add_number; |
3948 | ep->X_add_number = 0; | |
67c0d1eb RS |
3949 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3950 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3951 | load_delay_nop (); |
4d7206a2 RS |
3952 | relax_start (ep->X_add_symbol); |
3953 | relax_switch (); | |
67c0d1eb | 3954 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3955 | BFD_RELOC_LO16); |
4d7206a2 | 3956 | relax_end (); |
ed6fb7bd | 3957 | |
f5040a92 AO |
3958 | if (ex.X_add_number != 0) |
3959 | { | |
3960 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3961 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3962 | ex.X_op = O_constant; | |
67c0d1eb | 3963 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3964 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3965 | } |
252b5132 RH |
3966 | } |
3967 | } | |
3968 | else if (mips_pic == SVR4_PIC) | |
3969 | { | |
3970 | expressionS ex; | |
252b5132 RH |
3971 | |
3972 | /* This is the large GOT case. If this is a reference to an | |
3973 | external symbol, we want | |
3974 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3975 | addu $reg,$reg,$gp | |
3976 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3977 | |
3978 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3979 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3980 | nop | |
3981 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3982 | If there is a constant, it must be added in after. |
f5040a92 AO |
3983 | |
3984 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3985 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3986 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3987 | */ |
438c16b8 TS |
3988 | if (HAVE_NEWABI) |
3989 | { | |
4d7206a2 | 3990 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3991 | ep->X_add_number = 0; |
4d7206a2 | 3992 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3993 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3994 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3995 | reg, reg, mips_gp_register); | |
3996 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3997 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3998 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3999 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4000 | else if (ex.X_add_number) | |
4001 | { | |
4002 | ex.X_op = O_constant; | |
67c0d1eb RS |
4003 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4004 | BFD_RELOC_LO16); | |
f5040a92 AO |
4005 | } |
4006 | ||
4007 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4008 | relax_switch (); |
67c0d1eb | 4009 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4010 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4011 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4012 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4013 | relax_end (); |
438c16b8 | 4014 | } |
252b5132 | 4015 | else |
438c16b8 | 4016 | { |
f5040a92 AO |
4017 | ex.X_add_number = ep->X_add_number; |
4018 | ep->X_add_number = 0; | |
4d7206a2 | 4019 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4020 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4021 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4022 | reg, reg, mips_gp_register); | |
4023 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4024 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4025 | relax_switch (); |
4026 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4027 | { |
4028 | /* We need a nop before loading from $gp. This special | |
4029 | check is required because the lui which starts the main | |
4030 | instruction stream does not refer to $gp, and so will not | |
4031 | insert the nop which may be required. */ | |
67c0d1eb | 4032 | macro_build (NULL, "nop", ""); |
438c16b8 | 4033 | } |
67c0d1eb | 4034 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4035 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4036 | load_delay_nop (); |
67c0d1eb | 4037 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4038 | BFD_RELOC_LO16); |
4d7206a2 | 4039 | relax_end (); |
438c16b8 | 4040 | |
f5040a92 AO |
4041 | if (ex.X_add_number != 0) |
4042 | { | |
4043 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4044 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4045 | ex.X_op = O_constant; | |
67c0d1eb RS |
4046 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4047 | BFD_RELOC_LO16); | |
f5040a92 | 4048 | } |
252b5132 RH |
4049 | } |
4050 | } | |
252b5132 RH |
4051 | else |
4052 | abort (); | |
4053 | } | |
4054 | ||
ea1fb5dc RS |
4055 | /* Move the contents of register SOURCE into register DEST. */ |
4056 | ||
4057 | static void | |
67c0d1eb | 4058 | move_register (int dest, int source) |
ea1fb5dc | 4059 | { |
67c0d1eb RS |
4060 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4061 | dest, source, 0); | |
ea1fb5dc RS |
4062 | } |
4063 | ||
4d7206a2 | 4064 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4065 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4066 | The two alternatives are: | |
4d7206a2 RS |
4067 | |
4068 | Global symbol Local sybmol | |
4069 | ------------- ------------ | |
4070 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4071 | ... ... | |
4072 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4073 | ||
4074 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4075 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4076 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4077 | |
4078 | static void | |
67c0d1eb | 4079 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4080 | { |
4081 | expressionS global; | |
4082 | ||
4083 | global = *local; | |
4084 | global.X_add_number = 0; | |
4085 | ||
4086 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4087 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4088 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4089 | relax_switch (); |
67c0d1eb RS |
4090 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4091 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4092 | relax_end (); |
4093 | } | |
4094 | ||
4095 | static void | |
67c0d1eb | 4096 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4097 | { |
4098 | expressionS global; | |
4099 | ||
4100 | global.X_op = O_constant; | |
4101 | global.X_op_symbol = NULL; | |
4102 | global.X_add_symbol = NULL; | |
4103 | global.X_add_number = local->X_add_number; | |
4104 | ||
4105 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4106 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4107 | dest, dest, BFD_RELOC_LO16); |
4108 | relax_switch (); | |
67c0d1eb | 4109 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4110 | relax_end (); |
4111 | } | |
4112 | ||
f6a22291 MR |
4113 | static void |
4114 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4115 | { | |
4116 | expressionS global; | |
4117 | int hold_mips_optimize; | |
4118 | ||
4119 | global.X_op = O_constant; | |
4120 | global.X_op_symbol = NULL; | |
4121 | global.X_add_symbol = NULL; | |
4122 | global.X_add_number = local->X_add_number; | |
4123 | ||
4124 | relax_start (local->X_add_symbol); | |
4125 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4126 | relax_switch (); | |
4127 | /* Set mips_optimize around the lui instruction to avoid | |
4128 | inserting an unnecessary nop after the lw. */ | |
4129 | hold_mips_optimize = mips_optimize; | |
4130 | mips_optimize = 2; | |
4131 | macro_build_lui (&global, tmp); | |
4132 | mips_optimize = hold_mips_optimize; | |
4133 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4134 | relax_end (); | |
4135 | ||
4136 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4137 | } | |
4138 | ||
252b5132 RH |
4139 | /* |
4140 | * Build macros | |
4141 | * This routine implements the seemingly endless macro or synthesized | |
4142 | * instructions and addressing modes in the mips assembly language. Many | |
4143 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4144 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4145 | * this verbose method. Others are not simple macros but are more like |
4146 | * optimizing code generation. | |
4147 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4148 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4149 | * The ensuing load upper instructions are ommited. This implies some kind |
4150 | * of global optimization. We currently only optimize within a single macro. | |
4151 | * For many of the load and store macros if the address is specified as a | |
4152 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4153 | * first load register 'at' with zero and use it as the base register. The | |
4154 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4155 | * we're missing. | |
4156 | */ | |
4157 | static void | |
17a2f251 | 4158 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4159 | { |
4160 | register int treg, sreg, dreg, breg; | |
4161 | int tempreg; | |
4162 | int mask; | |
43841e91 | 4163 | int used_at = 0; |
252b5132 RH |
4164 | expressionS expr1; |
4165 | const char *s; | |
4166 | const char *s2; | |
4167 | const char *fmt; | |
4168 | int likely = 0; | |
4169 | int dbl = 0; | |
4170 | int coproc = 0; | |
4171 | int lr = 0; | |
4172 | int imm = 0; | |
1abe91b1 | 4173 | int call = 0; |
252b5132 | 4174 | int off; |
67c0d1eb | 4175 | offsetT maxnum; |
252b5132 | 4176 | bfd_reloc_code_real_type r; |
252b5132 RH |
4177 | int hold_mips_optimize; |
4178 | ||
4179 | assert (! mips_opts.mips16); | |
4180 | ||
4181 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4182 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4183 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4184 | mask = ip->insn_mo->mask; | |
4185 | ||
4186 | expr1.X_op = O_constant; | |
4187 | expr1.X_op_symbol = NULL; | |
4188 | expr1.X_add_symbol = NULL; | |
4189 | expr1.X_add_number = 1; | |
4190 | ||
4191 | switch (mask) | |
4192 | { | |
4193 | case M_DABS: | |
4194 | dbl = 1; | |
4195 | case M_ABS: | |
4196 | /* bgez $a0,.+12 | |
4197 | move v0,$a0 | |
4198 | sub v0,$zero,$a0 | |
4199 | */ | |
4200 | ||
b34976b6 | 4201 | mips_emit_delays (TRUE); |
252b5132 RH |
4202 | ++mips_opts.noreorder; |
4203 | mips_any_noreorder = 1; | |
4204 | ||
4205 | expr1.X_add_number = 8; | |
67c0d1eb | 4206 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4207 | if (dreg == sreg) |
67c0d1eb | 4208 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4209 | else |
67c0d1eb RS |
4210 | move_register (dreg, sreg); |
4211 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4212 | |
4213 | --mips_opts.noreorder; | |
4214 | return; | |
4215 | ||
4216 | case M_ADD_I: | |
4217 | s = "addi"; | |
4218 | s2 = "add"; | |
4219 | goto do_addi; | |
4220 | case M_ADDU_I: | |
4221 | s = "addiu"; | |
4222 | s2 = "addu"; | |
4223 | goto do_addi; | |
4224 | case M_DADD_I: | |
4225 | dbl = 1; | |
4226 | s = "daddi"; | |
4227 | s2 = "dadd"; | |
4228 | goto do_addi; | |
4229 | case M_DADDU_I: | |
4230 | dbl = 1; | |
4231 | s = "daddiu"; | |
4232 | s2 = "daddu"; | |
4233 | do_addi: | |
4234 | if (imm_expr.X_op == O_constant | |
4235 | && imm_expr.X_add_number >= -0x8000 | |
4236 | && imm_expr.X_add_number < 0x8000) | |
4237 | { | |
67c0d1eb | 4238 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4239 | return; |
4240 | } | |
67c0d1eb RS |
4241 | load_register (AT, &imm_expr, dbl); |
4242 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4243 | break; |
4244 | ||
4245 | case M_AND_I: | |
4246 | s = "andi"; | |
4247 | s2 = "and"; | |
4248 | goto do_bit; | |
4249 | case M_OR_I: | |
4250 | s = "ori"; | |
4251 | s2 = "or"; | |
4252 | goto do_bit; | |
4253 | case M_NOR_I: | |
4254 | s = ""; | |
4255 | s2 = "nor"; | |
4256 | goto do_bit; | |
4257 | case M_XOR_I: | |
4258 | s = "xori"; | |
4259 | s2 = "xor"; | |
4260 | do_bit: | |
4261 | if (imm_expr.X_op == O_constant | |
4262 | && imm_expr.X_add_number >= 0 | |
4263 | && imm_expr.X_add_number < 0x10000) | |
4264 | { | |
4265 | if (mask != M_NOR_I) | |
67c0d1eb | 4266 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4267 | else |
4268 | { | |
67c0d1eb RS |
4269 | macro_build (&imm_expr, "ori", "t,r,i", |
4270 | treg, sreg, BFD_RELOC_LO16); | |
4271 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4272 | } |
4273 | return; | |
4274 | } | |
4275 | ||
67c0d1eb RS |
4276 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4277 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4278 | break; |
4279 | ||
4280 | case M_BEQ_I: | |
4281 | s = "beq"; | |
4282 | goto beq_i; | |
4283 | case M_BEQL_I: | |
4284 | s = "beql"; | |
4285 | likely = 1; | |
4286 | goto beq_i; | |
4287 | case M_BNE_I: | |
4288 | s = "bne"; | |
4289 | goto beq_i; | |
4290 | case M_BNEL_I: | |
4291 | s = "bnel"; | |
4292 | likely = 1; | |
4293 | beq_i: | |
4294 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4295 | { | |
67c0d1eb | 4296 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4297 | return; |
4298 | } | |
67c0d1eb RS |
4299 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4300 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4301 | break; |
4302 | ||
4303 | case M_BGEL: | |
4304 | likely = 1; | |
4305 | case M_BGE: | |
4306 | if (treg == 0) | |
4307 | { | |
67c0d1eb | 4308 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4309 | return; |
4310 | } | |
4311 | if (sreg == 0) | |
4312 | { | |
67c0d1eb | 4313 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4314 | return; |
4315 | } | |
67c0d1eb RS |
4316 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4317 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4318 | break; |
4319 | ||
4320 | case M_BGTL_I: | |
4321 | likely = 1; | |
4322 | case M_BGT_I: | |
4323 | /* check for > max integer */ | |
4324 | maxnum = 0x7fffffff; | |
ca4e0257 | 4325 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4326 | { |
4327 | maxnum <<= 16; | |
4328 | maxnum |= 0xffff; | |
4329 | maxnum <<= 16; | |
4330 | maxnum |= 0xffff; | |
4331 | } | |
4332 | if (imm_expr.X_op == O_constant | |
4333 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4334 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4335 | { |
4336 | do_false: | |
4337 | /* result is always false */ | |
4338 | if (! likely) | |
67c0d1eb | 4339 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4340 | else |
67c0d1eb | 4341 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4342 | return; |
4343 | } | |
4344 | if (imm_expr.X_op != O_constant) | |
4345 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4346 | ++imm_expr.X_add_number; |
252b5132 RH |
4347 | /* FALLTHROUGH */ |
4348 | case M_BGE_I: | |
4349 | case M_BGEL_I: | |
4350 | if (mask == M_BGEL_I) | |
4351 | likely = 1; | |
4352 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4353 | { | |
67c0d1eb | 4354 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4355 | return; |
4356 | } | |
4357 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4358 | { | |
67c0d1eb | 4359 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4360 | return; |
4361 | } | |
4362 | maxnum = 0x7fffffff; | |
ca4e0257 | 4363 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4364 | { |
4365 | maxnum <<= 16; | |
4366 | maxnum |= 0xffff; | |
4367 | maxnum <<= 16; | |
4368 | maxnum |= 0xffff; | |
4369 | } | |
4370 | maxnum = - maxnum - 1; | |
4371 | if (imm_expr.X_op == O_constant | |
4372 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4373 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4374 | { |
4375 | do_true: | |
4376 | /* result is always true */ | |
4377 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4378 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4379 | return; |
4380 | } | |
67c0d1eb RS |
4381 | set_at (sreg, 0); |
4382 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4383 | break; |
4384 | ||
4385 | case M_BGEUL: | |
4386 | likely = 1; | |
4387 | case M_BGEU: | |
4388 | if (treg == 0) | |
4389 | goto do_true; | |
4390 | if (sreg == 0) | |
4391 | { | |
67c0d1eb | 4392 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4393 | "s,t,p", 0, treg); |
252b5132 RH |
4394 | return; |
4395 | } | |
67c0d1eb RS |
4396 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4397 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4398 | break; |
4399 | ||
4400 | case M_BGTUL_I: | |
4401 | likely = 1; | |
4402 | case M_BGTU_I: | |
4403 | if (sreg == 0 | |
ca4e0257 | 4404 | || (HAVE_32BIT_GPRS |
252b5132 | 4405 | && imm_expr.X_op == O_constant |
956cd1d6 | 4406 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4407 | goto do_false; |
4408 | if (imm_expr.X_op != O_constant) | |
4409 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4410 | ++imm_expr.X_add_number; |
252b5132 RH |
4411 | /* FALLTHROUGH */ |
4412 | case M_BGEU_I: | |
4413 | case M_BGEUL_I: | |
4414 | if (mask == M_BGEUL_I) | |
4415 | likely = 1; | |
4416 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4417 | goto do_true; | |
4418 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4419 | { | |
67c0d1eb | 4420 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4421 | "s,t,p", sreg, 0); |
252b5132 RH |
4422 | return; |
4423 | } | |
67c0d1eb RS |
4424 | set_at (sreg, 1); |
4425 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4426 | break; |
4427 | ||
4428 | case M_BGTL: | |
4429 | likely = 1; | |
4430 | case M_BGT: | |
4431 | if (treg == 0) | |
4432 | { | |
67c0d1eb | 4433 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4434 | return; |
4435 | } | |
4436 | if (sreg == 0) | |
4437 | { | |
67c0d1eb | 4438 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4439 | return; |
4440 | } | |
67c0d1eb RS |
4441 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4442 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4443 | break; |
4444 | ||
4445 | case M_BGTUL: | |
4446 | likely = 1; | |
4447 | case M_BGTU: | |
4448 | if (treg == 0) | |
4449 | { | |
67c0d1eb | 4450 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4451 | "s,t,p", sreg, 0); |
252b5132 RH |
4452 | return; |
4453 | } | |
4454 | if (sreg == 0) | |
4455 | goto do_false; | |
67c0d1eb RS |
4456 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4457 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4458 | break; |
4459 | ||
4460 | case M_BLEL: | |
4461 | likely = 1; | |
4462 | case M_BLE: | |
4463 | if (treg == 0) | |
4464 | { | |
67c0d1eb | 4465 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4466 | return; |
4467 | } | |
4468 | if (sreg == 0) | |
4469 | { | |
67c0d1eb | 4470 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4471 | return; |
4472 | } | |
67c0d1eb RS |
4473 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4474 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4475 | break; |
4476 | ||
4477 | case M_BLEL_I: | |
4478 | likely = 1; | |
4479 | case M_BLE_I: | |
4480 | maxnum = 0x7fffffff; | |
ca4e0257 | 4481 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4482 | { |
4483 | maxnum <<= 16; | |
4484 | maxnum |= 0xffff; | |
4485 | maxnum <<= 16; | |
4486 | maxnum |= 0xffff; | |
4487 | } | |
4488 | if (imm_expr.X_op == O_constant | |
4489 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4490 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4491 | goto do_true; |
4492 | if (imm_expr.X_op != O_constant) | |
4493 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4494 | ++imm_expr.X_add_number; |
252b5132 RH |
4495 | /* FALLTHROUGH */ |
4496 | case M_BLT_I: | |
4497 | case M_BLTL_I: | |
4498 | if (mask == M_BLTL_I) | |
4499 | likely = 1; | |
4500 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4501 | { | |
67c0d1eb | 4502 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4503 | return; |
4504 | } | |
4505 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4506 | { | |
67c0d1eb | 4507 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4508 | return; |
4509 | } | |
67c0d1eb RS |
4510 | set_at (sreg, 0); |
4511 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4512 | break; |
4513 | ||
4514 | case M_BLEUL: | |
4515 | likely = 1; | |
4516 | case M_BLEU: | |
4517 | if (treg == 0) | |
4518 | { | |
67c0d1eb | 4519 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4520 | "s,t,p", sreg, 0); |
252b5132 RH |
4521 | return; |
4522 | } | |
4523 | if (sreg == 0) | |
4524 | goto do_true; | |
67c0d1eb RS |
4525 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4526 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4527 | break; |
4528 | ||
4529 | case M_BLEUL_I: | |
4530 | likely = 1; | |
4531 | case M_BLEU_I: | |
4532 | if (sreg == 0 | |
ca4e0257 | 4533 | || (HAVE_32BIT_GPRS |
252b5132 | 4534 | && imm_expr.X_op == O_constant |
956cd1d6 | 4535 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4536 | goto do_true; |
4537 | if (imm_expr.X_op != O_constant) | |
4538 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4539 | ++imm_expr.X_add_number; |
252b5132 RH |
4540 | /* FALLTHROUGH */ |
4541 | case M_BLTU_I: | |
4542 | case M_BLTUL_I: | |
4543 | if (mask == M_BLTUL_I) | |
4544 | likely = 1; | |
4545 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4546 | goto do_false; | |
4547 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4548 | { | |
67c0d1eb | 4549 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4550 | "s,t,p", sreg, 0); |
4551 | return; | |
4552 | } | |
67c0d1eb RS |
4553 | set_at (sreg, 1); |
4554 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4555 | break; |
4556 | ||
4557 | case M_BLTL: | |
4558 | likely = 1; | |
4559 | case M_BLT: | |
4560 | if (treg == 0) | |
4561 | { | |
67c0d1eb | 4562 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4563 | return; |
4564 | } | |
4565 | if (sreg == 0) | |
4566 | { | |
67c0d1eb | 4567 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4568 | return; |
4569 | } | |
67c0d1eb RS |
4570 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4571 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4572 | break; |
4573 | ||
4574 | case M_BLTUL: | |
4575 | likely = 1; | |
4576 | case M_BLTU: | |
4577 | if (treg == 0) | |
4578 | goto do_false; | |
4579 | if (sreg == 0) | |
4580 | { | |
67c0d1eb | 4581 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4582 | "s,t,p", 0, treg); |
252b5132 RH |
4583 | return; |
4584 | } | |
67c0d1eb RS |
4585 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4586 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4587 | break; |
4588 | ||
5f74bc13 CD |
4589 | case M_DEXT: |
4590 | { | |
4591 | unsigned long pos; | |
4592 | unsigned long size; | |
4593 | ||
4594 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4595 | { | |
4596 | as_bad (_("Unsupported large constant")); | |
4597 | pos = size = 1; | |
4598 | } | |
4599 | else | |
4600 | { | |
4601 | pos = (unsigned long) imm_expr.X_add_number; | |
4602 | size = (unsigned long) imm2_expr.X_add_number; | |
4603 | } | |
4604 | ||
4605 | if (pos > 63) | |
4606 | { | |
4607 | as_bad (_("Improper position (%lu)"), pos); | |
4608 | pos = 1; | |
4609 | } | |
4610 | if (size == 0 || size > 64 | |
4611 | || (pos + size - 1) > 63) | |
4612 | { | |
4613 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4614 | size, pos); | |
4615 | size = 1; | |
4616 | } | |
4617 | ||
4618 | if (size <= 32 && pos < 32) | |
4619 | { | |
4620 | s = "dext"; | |
4621 | fmt = "t,r,+A,+C"; | |
4622 | } | |
4623 | else if (size <= 32) | |
4624 | { | |
4625 | s = "dextu"; | |
4626 | fmt = "t,r,+E,+H"; | |
4627 | } | |
4628 | else | |
4629 | { | |
4630 | s = "dextm"; | |
4631 | fmt = "t,r,+A,+G"; | |
4632 | } | |
67c0d1eb | 4633 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4634 | } |
4635 | return; | |
4636 | ||
4637 | case M_DINS: | |
4638 | { | |
4639 | unsigned long pos; | |
4640 | unsigned long size; | |
4641 | ||
4642 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4643 | { | |
4644 | as_bad (_("Unsupported large constant")); | |
4645 | pos = size = 1; | |
4646 | } | |
4647 | else | |
4648 | { | |
4649 | pos = (unsigned long) imm_expr.X_add_number; | |
4650 | size = (unsigned long) imm2_expr.X_add_number; | |
4651 | } | |
4652 | ||
4653 | if (pos > 63) | |
4654 | { | |
4655 | as_bad (_("Improper position (%lu)"), pos); | |
4656 | pos = 1; | |
4657 | } | |
4658 | if (size == 0 || size > 64 | |
4659 | || (pos + size - 1) > 63) | |
4660 | { | |
4661 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4662 | size, pos); | |
4663 | size = 1; | |
4664 | } | |
4665 | ||
4666 | if (pos < 32 && (pos + size - 1) < 32) | |
4667 | { | |
4668 | s = "dins"; | |
4669 | fmt = "t,r,+A,+B"; | |
4670 | } | |
4671 | else if (pos >= 32) | |
4672 | { | |
4673 | s = "dinsu"; | |
4674 | fmt = "t,r,+E,+F"; | |
4675 | } | |
4676 | else | |
4677 | { | |
4678 | s = "dinsm"; | |
4679 | fmt = "t,r,+A,+F"; | |
4680 | } | |
67c0d1eb RS |
4681 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4682 | pos + size - 1); | |
5f74bc13 CD |
4683 | } |
4684 | return; | |
4685 | ||
252b5132 RH |
4686 | case M_DDIV_3: |
4687 | dbl = 1; | |
4688 | case M_DIV_3: | |
4689 | s = "mflo"; | |
4690 | goto do_div3; | |
4691 | case M_DREM_3: | |
4692 | dbl = 1; | |
4693 | case M_REM_3: | |
4694 | s = "mfhi"; | |
4695 | do_div3: | |
4696 | if (treg == 0) | |
4697 | { | |
4698 | as_warn (_("Divide by zero.")); | |
4699 | if (mips_trap) | |
67c0d1eb | 4700 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4701 | else |
67c0d1eb | 4702 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4703 | return; |
4704 | } | |
4705 | ||
b34976b6 | 4706 | mips_emit_delays (TRUE); |
252b5132 RH |
4707 | ++mips_opts.noreorder; |
4708 | mips_any_noreorder = 1; | |
4709 | if (mips_trap) | |
4710 | { | |
67c0d1eb RS |
4711 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4712 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4713 | } |
4714 | else | |
4715 | { | |
4716 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4717 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4718 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4719 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4720 | } |
4721 | expr1.X_add_number = -1; | |
f6a22291 | 4722 | load_register (AT, &expr1, dbl); |
252b5132 | 4723 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4724 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4725 | if (dbl) |
4726 | { | |
4727 | expr1.X_add_number = 1; | |
f6a22291 | 4728 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4729 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4730 | } |
4731 | else | |
4732 | { | |
4733 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4734 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4735 | } |
4736 | if (mips_trap) | |
4737 | { | |
67c0d1eb | 4738 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4739 | /* We want to close the noreorder block as soon as possible, so |
4740 | that later insns are available for delay slot filling. */ | |
4741 | --mips_opts.noreorder; | |
4742 | } | |
4743 | else | |
4744 | { | |
4745 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4746 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4747 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4748 | |
4749 | /* We want to close the noreorder block as soon as possible, so | |
4750 | that later insns are available for delay slot filling. */ | |
4751 | --mips_opts.noreorder; | |
4752 | ||
67c0d1eb | 4753 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4754 | } |
67c0d1eb | 4755 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4756 | break; |
4757 | ||
4758 | case M_DIV_3I: | |
4759 | s = "div"; | |
4760 | s2 = "mflo"; | |
4761 | goto do_divi; | |
4762 | case M_DIVU_3I: | |
4763 | s = "divu"; | |
4764 | s2 = "mflo"; | |
4765 | goto do_divi; | |
4766 | case M_REM_3I: | |
4767 | s = "div"; | |
4768 | s2 = "mfhi"; | |
4769 | goto do_divi; | |
4770 | case M_REMU_3I: | |
4771 | s = "divu"; | |
4772 | s2 = "mfhi"; | |
4773 | goto do_divi; | |
4774 | case M_DDIV_3I: | |
4775 | dbl = 1; | |
4776 | s = "ddiv"; | |
4777 | s2 = "mflo"; | |
4778 | goto do_divi; | |
4779 | case M_DDIVU_3I: | |
4780 | dbl = 1; | |
4781 | s = "ddivu"; | |
4782 | s2 = "mflo"; | |
4783 | goto do_divi; | |
4784 | case M_DREM_3I: | |
4785 | dbl = 1; | |
4786 | s = "ddiv"; | |
4787 | s2 = "mfhi"; | |
4788 | goto do_divi; | |
4789 | case M_DREMU_3I: | |
4790 | dbl = 1; | |
4791 | s = "ddivu"; | |
4792 | s2 = "mfhi"; | |
4793 | do_divi: | |
4794 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4795 | { | |
4796 | as_warn (_("Divide by zero.")); | |
4797 | if (mips_trap) | |
67c0d1eb | 4798 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4799 | else |
67c0d1eb | 4800 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4801 | return; |
4802 | } | |
4803 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4804 | { | |
4805 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4806 | move_register (dreg, sreg); |
252b5132 | 4807 | else |
67c0d1eb | 4808 | move_register (dreg, 0); |
252b5132 RH |
4809 | return; |
4810 | } | |
4811 | if (imm_expr.X_op == O_constant | |
4812 | && imm_expr.X_add_number == -1 | |
4813 | && s[strlen (s) - 1] != 'u') | |
4814 | { | |
4815 | if (strcmp (s2, "mflo") == 0) | |
4816 | { | |
67c0d1eb | 4817 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4818 | } |
4819 | else | |
67c0d1eb | 4820 | move_register (dreg, 0); |
252b5132 RH |
4821 | return; |
4822 | } | |
4823 | ||
67c0d1eb RS |
4824 | load_register (AT, &imm_expr, dbl); |
4825 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4826 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4827 | break; |
4828 | ||
4829 | case M_DIVU_3: | |
4830 | s = "divu"; | |
4831 | s2 = "mflo"; | |
4832 | goto do_divu3; | |
4833 | case M_REMU_3: | |
4834 | s = "divu"; | |
4835 | s2 = "mfhi"; | |
4836 | goto do_divu3; | |
4837 | case M_DDIVU_3: | |
4838 | s = "ddivu"; | |
4839 | s2 = "mflo"; | |
4840 | goto do_divu3; | |
4841 | case M_DREMU_3: | |
4842 | s = "ddivu"; | |
4843 | s2 = "mfhi"; | |
4844 | do_divu3: | |
b34976b6 | 4845 | mips_emit_delays (TRUE); |
252b5132 RH |
4846 | ++mips_opts.noreorder; |
4847 | mips_any_noreorder = 1; | |
4848 | if (mips_trap) | |
4849 | { | |
67c0d1eb RS |
4850 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4851 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4852 | /* We want to close the noreorder block as soon as possible, so |
4853 | that later insns are available for delay slot filling. */ | |
4854 | --mips_opts.noreorder; | |
4855 | } | |
4856 | else | |
4857 | { | |
4858 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4859 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4860 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4861 | |
4862 | /* We want to close the noreorder block as soon as possible, so | |
4863 | that later insns are available for delay slot filling. */ | |
4864 | --mips_opts.noreorder; | |
67c0d1eb | 4865 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4866 | } |
67c0d1eb | 4867 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4868 | return; |
4869 | ||
1abe91b1 MR |
4870 | case M_DLCA_AB: |
4871 | dbl = 1; | |
4872 | case M_LCA_AB: | |
4873 | call = 1; | |
4874 | goto do_la; | |
252b5132 RH |
4875 | case M_DLA_AB: |
4876 | dbl = 1; | |
4877 | case M_LA_AB: | |
1abe91b1 | 4878 | do_la: |
252b5132 RH |
4879 | /* Load the address of a symbol into a register. If breg is not |
4880 | zero, we then add a base register to it. */ | |
4881 | ||
3bec30a8 TS |
4882 | if (dbl && HAVE_32BIT_GPRS) |
4883 | as_warn (_("dla used to load 32-bit register")); | |
4884 | ||
c90bbe5b | 4885 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4886 | as_warn (_("la used to load 64-bit address")); |
4887 | ||
0c11417f MR |
4888 | if (offset_expr.X_op == O_constant |
4889 | && offset_expr.X_add_number >= -0x8000 | |
4890 | && offset_expr.X_add_number < 0x8000) | |
4891 | { | |
67c0d1eb | 4892 | macro_build (&offset_expr, |
b7c7d6c1 | 4893 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4894 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4895 | return; |
4896 | } | |
4897 | ||
afdbd6d0 CD |
4898 | if (treg == breg) |
4899 | { | |
4900 | tempreg = AT; | |
4901 | used_at = 1; | |
4902 | } | |
4903 | else | |
4904 | { | |
4905 | tempreg = treg; | |
4906 | used_at = 0; | |
4907 | } | |
4908 | ||
252b5132 RH |
4909 | if (offset_expr.X_op != O_symbol |
4910 | && offset_expr.X_op != O_constant) | |
4911 | { | |
4912 | as_bad (_("expression too complex")); | |
4913 | offset_expr.X_op = O_constant; | |
4914 | } | |
4915 | ||
252b5132 | 4916 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4917 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4918 | (mips_pic == NO_PIC |
4d34fb5f TS |
4919 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4920 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4921 | else if (mips_pic == NO_PIC) |
4922 | { | |
d6bc6245 | 4923 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4924 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4925 | Otherwise we want |
4926 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4927 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4928 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4929 | so we may as well always use the latter form. |
76b3015f | 4930 | |
d6bc6245 TS |
4931 | With 64bit address space and a usable $at we want |
4932 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4933 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4934 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4935 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4936 | dsll32 $tempreg,0 | |
3a482fd5 | 4937 | daddu $tempreg,$tempreg,$at |
76b3015f | 4938 | |
c03099e6 | 4939 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4940 | on superscalar processors. |
4941 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4942 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4943 | dsll $tempreg,16 | |
4944 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4945 | dsll $tempreg,16 | |
4946 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4947 | */ | |
d6bc6245 | 4948 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4949 | { |
e864ceca RS |
4950 | /* ??? We don't provide a GP-relative alternative for |
4951 | these macros. It used not to be possible with the | |
4952 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4953 | |
460597ba | 4954 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f | 4955 | { |
67c0d1eb | 4956 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4957 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4958 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4959 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4960 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4961 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4962 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4963 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4964 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4965 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4966 | used_at = 1; |
4967 | } | |
4968 | else | |
4969 | { | |
67c0d1eb | 4970 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4971 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4972 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4973 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4974 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4975 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4976 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4977 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4978 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4979 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4980 | } |
4981 | } | |
4982 | else | |
4983 | { | |
4984 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4985 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4986 | { | |
4d7206a2 | 4987 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4988 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4989 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4990 | relax_switch (); |
98d3f06f | 4991 | } |
67c0d1eb RS |
4992 | macro_build_lui (&offset_expr, tempreg); |
4993 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4994 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4995 | if (mips_relax.sequence) |
4996 | relax_end (); | |
98d3f06f | 4997 | } |
252b5132 | 4998 | } |
f5040a92 | 4999 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5000 | { |
9117d219 NC |
5001 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5002 | ||
252b5132 RH |
5003 | /* If this is a reference to an external symbol, and there |
5004 | is no constant, we want | |
5005 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5006 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5007 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5008 | For a local symbol, we want |
5009 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5010 | nop | |
5011 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5012 | ||
5013 | If we have a small constant, and this is a reference to | |
5014 | an external symbol, we want | |
5015 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5016 | nop | |
5017 | addiu $tempreg,$tempreg,<constant> | |
5018 | For a local symbol, we want the same instruction | |
5019 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5020 | addiu instruction. | |
5021 | ||
5022 | If we have a large constant, and this is a reference to | |
5023 | an external symbol, we want | |
5024 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5025 | lui $at,<hiconstant> | |
5026 | addiu $at,$at,<loconstant> | |
5027 | addu $tempreg,$tempreg,$at | |
5028 | For a local symbol, we want the same instruction | |
5029 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5030 | addiu instruction. |
ed6fb7bd SC |
5031 | */ |
5032 | ||
4d7206a2 | 5033 | if (offset_expr.X_add_number == 0) |
252b5132 | 5034 | { |
4d7206a2 RS |
5035 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5036 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5037 | ||
5038 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5039 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5040 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5041 | if (breg != 0) |
252b5132 RH |
5042 | { |
5043 | /* We're going to put in an addu instruction using | |
5044 | tempreg, so we may as well insert the nop right | |
5045 | now. */ | |
269137b2 | 5046 | load_delay_nop (); |
252b5132 | 5047 | } |
4d7206a2 | 5048 | relax_switch (); |
67c0d1eb RS |
5049 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5050 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5051 | load_delay_nop (); |
67c0d1eb RS |
5052 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5053 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5054 | relax_end (); |
252b5132 RH |
5055 | /* FIXME: If breg == 0, and the next instruction uses |
5056 | $tempreg, then if this variant case is used an extra | |
5057 | nop will be generated. */ | |
5058 | } | |
4d7206a2 RS |
5059 | else if (offset_expr.X_add_number >= -0x8000 |
5060 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5061 | { |
67c0d1eb | 5062 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5063 | load_delay_nop (); |
67c0d1eb | 5064 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5065 | } |
5066 | else | |
5067 | { | |
4d7206a2 RS |
5068 | expr1.X_add_number = offset_expr.X_add_number; |
5069 | offset_expr.X_add_number = | |
5070 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5071 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5072 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5073 | /* If we are going to add in a base register, and the |
5074 | target register and the base register are the same, | |
5075 | then we are using AT as a temporary register. Since | |
5076 | we want to load the constant into AT, we add our | |
5077 | current AT (from the global offset table) and the | |
5078 | register into the register now, and pretend we were | |
5079 | not using a base register. */ | |
67c0d1eb | 5080 | if (breg == treg) |
252b5132 | 5081 | { |
269137b2 | 5082 | load_delay_nop (); |
67c0d1eb | 5083 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5084 | treg, AT, breg); |
252b5132 RH |
5085 | breg = 0; |
5086 | tempreg = treg; | |
252b5132 | 5087 | } |
f6a22291 | 5088 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5089 | used_at = 1; |
5090 | } | |
5091 | } | |
f5040a92 AO |
5092 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5093 | { | |
67c0d1eb | 5094 | int add_breg_early = 0; |
f5040a92 AO |
5095 | |
5096 | /* If this is a reference to an external, and there is no | |
5097 | constant, or local symbol (*), with or without a | |
5098 | constant, we want | |
5099 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5100 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5101 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5102 | ||
5103 | If we have a small constant, and this is a reference to | |
5104 | an external symbol, we want | |
5105 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5106 | addiu $tempreg,$tempreg,<constant> | |
5107 | ||
5108 | If we have a large constant, and this is a reference to | |
5109 | an external symbol, we want | |
5110 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5111 | lui $at,<hiconstant> | |
5112 | addiu $at,$at,<loconstant> | |
5113 | addu $tempreg,$tempreg,$at | |
5114 | ||
5115 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5116 | local symbols, even though it introduces an additional | |
5117 | instruction. */ | |
5118 | ||
f5040a92 AO |
5119 | if (offset_expr.X_add_number) |
5120 | { | |
4d7206a2 | 5121 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5122 | offset_expr.X_add_number = 0; |
5123 | ||
4d7206a2 | 5124 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5125 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5126 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5127 | |
5128 | if (expr1.X_add_number >= -0x8000 | |
5129 | && expr1.X_add_number < 0x8000) | |
5130 | { | |
67c0d1eb RS |
5131 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5132 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5133 | } |
ecd13cd3 | 5134 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5135 | { |
5136 | int dreg; | |
5137 | ||
5138 | /* If we are going to add in a base register, and the | |
5139 | target register and the base register are the same, | |
5140 | then we are using AT as a temporary register. Since | |
5141 | we want to load the constant into AT, we add our | |
5142 | current AT (from the global offset table) and the | |
5143 | register into the register now, and pretend we were | |
5144 | not using a base register. */ | |
5145 | if (breg != treg) | |
5146 | dreg = tempreg; | |
5147 | else | |
5148 | { | |
5149 | assert (tempreg == AT); | |
67c0d1eb RS |
5150 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5151 | treg, AT, breg); | |
f5040a92 | 5152 | dreg = treg; |
67c0d1eb | 5153 | add_breg_early = 1; |
f5040a92 AO |
5154 | } |
5155 | ||
f6a22291 | 5156 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5158 | dreg, dreg, AT); |
f5040a92 | 5159 | |
f5040a92 AO |
5160 | used_at = 1; |
5161 | } | |
5162 | else | |
5163 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5164 | ||
4d7206a2 | 5165 | relax_switch (); |
f5040a92 AO |
5166 | offset_expr.X_add_number = expr1.X_add_number; |
5167 | ||
67c0d1eb RS |
5168 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5169 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5170 | if (add_breg_early) | |
f5040a92 | 5171 | { |
67c0d1eb | 5172 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5173 | treg, tempreg, breg); |
f5040a92 AO |
5174 | breg = 0; |
5175 | tempreg = treg; | |
5176 | } | |
4d7206a2 | 5177 | relax_end (); |
f5040a92 | 5178 | } |
4d7206a2 | 5179 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5180 | { |
4d7206a2 | 5181 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5182 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5183 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5184 | relax_switch (); |
67c0d1eb RS |
5185 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5186 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5187 | relax_end (); |
f5040a92 | 5188 | } |
4d7206a2 | 5189 | else |
f5040a92 | 5190 | { |
67c0d1eb RS |
5191 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5192 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5193 | } |
5194 | } | |
5195 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5196 | { |
67c0d1eb | 5197 | int gpdelay; |
9117d219 NC |
5198 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5199 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5200 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5201 | |
5202 | /* This is the large GOT case. If this is a reference to an | |
5203 | external symbol, and there is no constant, we want | |
5204 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5205 | addu $tempreg,$tempreg,$gp | |
5206 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5207 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5208 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5209 | addu $tempreg,$tempreg,$gp | |
5210 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5211 | For a local symbol, we want |
5212 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5213 | nop | |
5214 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5215 | ||
5216 | If we have a small constant, and this is a reference to | |
5217 | an external symbol, we want | |
5218 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5219 | addu $tempreg,$tempreg,$gp | |
5220 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5221 | nop | |
5222 | addiu $tempreg,$tempreg,<constant> | |
5223 | For a local symbol, we want | |
5224 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5225 | nop | |
5226 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5227 | ||
5228 | If we have a large constant, and this is a reference to | |
5229 | an external symbol, we want | |
5230 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5231 | addu $tempreg,$tempreg,$gp | |
5232 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5233 | lui $at,<hiconstant> | |
5234 | addiu $at,$at,<loconstant> | |
5235 | addu $tempreg,$tempreg,$at | |
5236 | For a local symbol, we want | |
5237 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5238 | lui $at,<hiconstant> | |
5239 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5240 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5241 | */ |
438c16b8 | 5242 | |
252b5132 RH |
5243 | expr1.X_add_number = offset_expr.X_add_number; |
5244 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5245 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5246 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5247 | if (expr1.X_add_number == 0 && breg == 0 |
5248 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5249 | { |
5250 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5251 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5252 | } | |
67c0d1eb RS |
5253 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5254 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5255 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5256 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5257 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5258 | if (expr1.X_add_number == 0) |
5259 | { | |
67c0d1eb | 5260 | if (breg != 0) |
252b5132 RH |
5261 | { |
5262 | /* We're going to put in an addu instruction using | |
5263 | tempreg, so we may as well insert the nop right | |
5264 | now. */ | |
269137b2 | 5265 | load_delay_nop (); |
252b5132 | 5266 | } |
252b5132 RH |
5267 | } |
5268 | else if (expr1.X_add_number >= -0x8000 | |
5269 | && expr1.X_add_number < 0x8000) | |
5270 | { | |
269137b2 | 5271 | load_delay_nop (); |
67c0d1eb | 5272 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5273 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5274 | } |
5275 | else | |
5276 | { | |
67c0d1eb | 5277 | int dreg; |
252b5132 RH |
5278 | |
5279 | /* If we are going to add in a base register, and the | |
5280 | target register and the base register are the same, | |
5281 | then we are using AT as a temporary register. Since | |
5282 | we want to load the constant into AT, we add our | |
5283 | current AT (from the global offset table) and the | |
5284 | register into the register now, and pretend we were | |
5285 | not using a base register. */ | |
5286 | if (breg != treg) | |
67c0d1eb | 5287 | dreg = tempreg; |
252b5132 RH |
5288 | else |
5289 | { | |
5290 | assert (tempreg == AT); | |
269137b2 | 5291 | load_delay_nop (); |
67c0d1eb | 5292 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5293 | treg, AT, breg); |
252b5132 | 5294 | dreg = treg; |
252b5132 RH |
5295 | } |
5296 | ||
f6a22291 | 5297 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5298 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5299 | |
252b5132 RH |
5300 | used_at = 1; |
5301 | } | |
4d7206a2 RS |
5302 | offset_expr.X_add_number = |
5303 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5304 | relax_switch (); | |
252b5132 | 5305 | |
67c0d1eb | 5306 | if (gpdelay) |
252b5132 RH |
5307 | { |
5308 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5309 | the first instruction on the main stream does not. */ |
67c0d1eb | 5310 | macro_build (NULL, "nop", ""); |
252b5132 | 5311 | } |
ed6fb7bd | 5312 | |
67c0d1eb RS |
5313 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5314 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5315 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5316 | && expr1.X_add_number < 0x8000) |
5317 | { | |
269137b2 | 5318 | load_delay_nop (); |
67c0d1eb RS |
5319 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5320 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5321 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5322 | register, the external symbol case ended with a load, |
5323 | so if the symbol turns out to not be external, and | |
5324 | the next instruction uses tempreg, an unnecessary nop | |
5325 | will be inserted. */ | |
252b5132 RH |
5326 | } |
5327 | else | |
5328 | { | |
5329 | if (breg == treg) | |
5330 | { | |
5331 | /* We must add in the base register now, as in the | |
f5040a92 | 5332 | external symbol case. */ |
252b5132 | 5333 | assert (tempreg == AT); |
269137b2 | 5334 | load_delay_nop (); |
67c0d1eb | 5335 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5336 | treg, AT, breg); |
252b5132 RH |
5337 | tempreg = treg; |
5338 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5339 | it in in both cases. */ |
252b5132 RH |
5340 | breg = 0; |
5341 | } | |
5342 | ||
67c0d1eb RS |
5343 | macro_build_lui (&expr1, AT); |
5344 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5345 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5346 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5347 | tempreg, tempreg, AT); |
252b5132 | 5348 | } |
4d7206a2 | 5349 | relax_end (); |
252b5132 | 5350 | } |
f5040a92 AO |
5351 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5352 | { | |
f5040a92 AO |
5353 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5354 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5355 | int add_breg_early = 0; |
f5040a92 AO |
5356 | |
5357 | /* This is the large GOT case. If this is a reference to an | |
5358 | external symbol, and there is no constant, we want | |
5359 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5360 | add $tempreg,$tempreg,$gp | |
5361 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5362 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5363 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5364 | add $tempreg,$tempreg,$gp | |
5365 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5366 | ||
5367 | If we have a small constant, and this is a reference to | |
5368 | an external symbol, we want | |
5369 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5370 | add $tempreg,$tempreg,$gp | |
5371 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5372 | addi $tempreg,$tempreg,<constant> | |
5373 | ||
5374 | If we have a large constant, and this is a reference to | |
5375 | an external symbol, we want | |
5376 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5377 | addu $tempreg,$tempreg,$gp | |
5378 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5379 | lui $at,<hiconstant> | |
5380 | addi $at,$at,<loconstant> | |
5381 | add $tempreg,$tempreg,$at | |
5382 | ||
5383 | If we have NewABI, and we know it's a local symbol, we want | |
5384 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5385 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5386 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5387 | ||
4d7206a2 | 5388 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5389 | |
4d7206a2 | 5390 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5391 | offset_expr.X_add_number = 0; |
5392 | ||
1abe91b1 MR |
5393 | if (expr1.X_add_number == 0 && breg == 0 |
5394 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5395 | { |
5396 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5397 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5398 | } | |
67c0d1eb RS |
5399 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5401 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5402 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5403 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5404 | |
5405 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5406 | ; |
f5040a92 AO |
5407 | else if (expr1.X_add_number >= -0x8000 |
5408 | && expr1.X_add_number < 0x8000) | |
5409 | { | |
67c0d1eb | 5410 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5411 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5412 | } |
ecd13cd3 | 5413 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5414 | { |
5415 | int dreg; | |
5416 | ||
5417 | /* If we are going to add in a base register, and the | |
5418 | target register and the base register are the same, | |
5419 | then we are using AT as a temporary register. Since | |
5420 | we want to load the constant into AT, we add our | |
5421 | current AT (from the global offset table) and the | |
5422 | register into the register now, and pretend we were | |
5423 | not using a base register. */ | |
5424 | if (breg != treg) | |
5425 | dreg = tempreg; | |
5426 | else | |
5427 | { | |
5428 | assert (tempreg == AT); | |
67c0d1eb | 5429 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5430 | treg, AT, breg); |
f5040a92 | 5431 | dreg = treg; |
67c0d1eb | 5432 | add_breg_early = 1; |
f5040a92 AO |
5433 | } |
5434 | ||
f6a22291 | 5435 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5436 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5437 | |
f5040a92 AO |
5438 | used_at = 1; |
5439 | } | |
5440 | else | |
5441 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5442 | ||
4d7206a2 | 5443 | relax_switch (); |
f5040a92 | 5444 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5445 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5446 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5447 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5448 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5449 | if (add_breg_early) | |
f5040a92 | 5450 | { |
67c0d1eb | 5451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5452 | treg, tempreg, breg); |
f5040a92 AO |
5453 | breg = 0; |
5454 | tempreg = treg; | |
5455 | } | |
4d7206a2 | 5456 | relax_end (); |
f5040a92 | 5457 | } |
252b5132 RH |
5458 | else |
5459 | abort (); | |
5460 | ||
5461 | if (breg != 0) | |
4d34fb5f TS |
5462 | { |
5463 | char *s; | |
5464 | ||
3e722fb5 | 5465 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5466 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5467 | else |
f899b4b8 | 5468 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5469 | |
67c0d1eb | 5470 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5471 | } |
252b5132 RH |
5472 | |
5473 | if (! used_at) | |
5474 | return; | |
5475 | ||
5476 | break; | |
5477 | ||
5478 | case M_J_A: | |
5479 | /* The j instruction may not be used in PIC code, since it | |
5480 | requires an absolute address. We convert it to a b | |
5481 | instruction. */ | |
5482 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5483 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5484 | else |
67c0d1eb | 5485 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5486 | return; |
5487 | ||
5488 | /* The jal instructions must be handled as macros because when | |
5489 | generating PIC code they expand to multi-instruction | |
5490 | sequences. Normally they are simple instructions. */ | |
5491 | case M_JAL_1: | |
5492 | dreg = RA; | |
5493 | /* Fall through. */ | |
5494 | case M_JAL_2: | |
3e722fb5 | 5495 | if (mips_pic == NO_PIC) |
67c0d1eb | 5496 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5497 | else if (mips_pic == SVR4_PIC) |
5498 | { | |
5499 | if (sreg != PIC_CALL_REG) | |
5500 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5501 | |
67c0d1eb | 5502 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5503 | if (! HAVE_NEWABI) |
252b5132 | 5504 | { |
6478892d TS |
5505 | if (mips_cprestore_offset < 0) |
5506 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5507 | else | |
5508 | { | |
7a621144 DJ |
5509 | if (! mips_frame_reg_valid) |
5510 | { | |
5511 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5512 | /* Quiet this warning. */ | |
5513 | mips_frame_reg_valid = 1; | |
5514 | } | |
5515 | if (! mips_cprestore_valid) | |
5516 | { | |
5517 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5518 | /* Quiet this warning. */ | |
5519 | mips_cprestore_valid = 1; | |
5520 | } | |
6478892d | 5521 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5522 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5523 | mips_gp_register, |
256ab948 TS |
5524 | mips_frame_reg, |
5525 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5526 | } |
252b5132 RH |
5527 | } |
5528 | } | |
5529 | else | |
5530 | abort (); | |
5531 | ||
5532 | return; | |
5533 | ||
5534 | case M_JAL_A: | |
5535 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5536 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5537 | else if (mips_pic == SVR4_PIC) |
5538 | { | |
5539 | /* If this is a reference to an external symbol, and we are | |
5540 | using a small GOT, we want | |
5541 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5542 | nop | |
f9419b05 | 5543 | jalr $ra,$25 |
252b5132 RH |
5544 | nop |
5545 | lw $gp,cprestore($sp) | |
5546 | The cprestore value is set using the .cprestore | |
5547 | pseudo-op. If we are using a big GOT, we want | |
5548 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5549 | addu $25,$25,$gp | |
5550 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5551 | nop | |
f9419b05 | 5552 | jalr $ra,$25 |
252b5132 RH |
5553 | nop |
5554 | lw $gp,cprestore($sp) | |
5555 | If the symbol is not external, we want | |
5556 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5557 | nop | |
5558 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5559 | jalr $ra,$25 |
252b5132 | 5560 | nop |
438c16b8 | 5561 | lw $gp,cprestore($sp) |
f5040a92 AO |
5562 | |
5563 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5564 | sequences above, minus nops, unless the symbol is local, | |
5565 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5566 | GOT_DISP. */ | |
438c16b8 | 5567 | if (HAVE_NEWABI) |
252b5132 | 5568 | { |
f5040a92 AO |
5569 | if (! mips_big_got) |
5570 | { | |
4d7206a2 | 5571 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5572 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5573 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5574 | mips_gp_register); |
4d7206a2 | 5575 | relax_switch (); |
67c0d1eb RS |
5576 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5577 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5578 | mips_gp_register); |
5579 | relax_end (); | |
f5040a92 AO |
5580 | } |
5581 | else | |
5582 | { | |
4d7206a2 | 5583 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5584 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5585 | BFD_RELOC_MIPS_CALL_HI16); | |
5586 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5587 | PIC_CALL_REG, mips_gp_register); | |
5588 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5589 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5590 | PIC_CALL_REG); | |
4d7206a2 | 5591 | relax_switch (); |
67c0d1eb RS |
5592 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5593 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5594 | mips_gp_register); | |
5595 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5596 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5597 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5598 | relax_end (); |
f5040a92 | 5599 | } |
684022ea | 5600 | |
67c0d1eb | 5601 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5602 | } |
5603 | else | |
5604 | { | |
4d7206a2 | 5605 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5606 | if (! mips_big_got) |
5607 | { | |
67c0d1eb RS |
5608 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5609 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5610 | mips_gp_register); |
269137b2 | 5611 | load_delay_nop (); |
4d7206a2 | 5612 | relax_switch (); |
438c16b8 | 5613 | } |
252b5132 | 5614 | else |
252b5132 | 5615 | { |
67c0d1eb RS |
5616 | int gpdelay; |
5617 | ||
5618 | gpdelay = reg_needs_delay (mips_gp_register); | |
5619 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5620 | BFD_RELOC_MIPS_CALL_HI16); | |
5621 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5622 | PIC_CALL_REG, mips_gp_register); | |
5623 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5624 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5625 | PIC_CALL_REG); | |
269137b2 | 5626 | load_delay_nop (); |
4d7206a2 | 5627 | relax_switch (); |
67c0d1eb RS |
5628 | if (gpdelay) |
5629 | macro_build (NULL, "nop", ""); | |
252b5132 | 5630 | } |
67c0d1eb RS |
5631 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5632 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5633 | mips_gp_register); |
269137b2 | 5634 | load_delay_nop (); |
67c0d1eb RS |
5635 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5636 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5637 | relax_end (); |
67c0d1eb | 5638 | macro_build_jalr (&offset_expr); |
438c16b8 | 5639 | |
6478892d TS |
5640 | if (mips_cprestore_offset < 0) |
5641 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5642 | else | |
5643 | { | |
7a621144 DJ |
5644 | if (! mips_frame_reg_valid) |
5645 | { | |
5646 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5647 | /* Quiet this warning. */ | |
5648 | mips_frame_reg_valid = 1; | |
5649 | } | |
5650 | if (! mips_cprestore_valid) | |
5651 | { | |
5652 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5653 | /* Quiet this warning. */ | |
5654 | mips_cprestore_valid = 1; | |
5655 | } | |
6478892d | 5656 | if (mips_opts.noreorder) |
67c0d1eb | 5657 | macro_build (NULL, "nop", ""); |
6478892d | 5658 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5659 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5660 | mips_gp_register, |
256ab948 TS |
5661 | mips_frame_reg, |
5662 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5663 | } |
252b5132 RH |
5664 | } |
5665 | } | |
252b5132 RH |
5666 | else |
5667 | abort (); | |
5668 | ||
5669 | return; | |
5670 | ||
5671 | case M_LB_AB: | |
5672 | s = "lb"; | |
5673 | goto ld; | |
5674 | case M_LBU_AB: | |
5675 | s = "lbu"; | |
5676 | goto ld; | |
5677 | case M_LH_AB: | |
5678 | s = "lh"; | |
5679 | goto ld; | |
5680 | case M_LHU_AB: | |
5681 | s = "lhu"; | |
5682 | goto ld; | |
5683 | case M_LW_AB: | |
5684 | s = "lw"; | |
5685 | goto ld; | |
5686 | case M_LWC0_AB: | |
5687 | s = "lwc0"; | |
bdaaa2e1 | 5688 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5689 | coproc = 1; |
5690 | goto ld; | |
5691 | case M_LWC1_AB: | |
5692 | s = "lwc1"; | |
bdaaa2e1 | 5693 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5694 | coproc = 1; |
5695 | goto ld; | |
5696 | case M_LWC2_AB: | |
5697 | s = "lwc2"; | |
bdaaa2e1 | 5698 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5699 | coproc = 1; |
5700 | goto ld; | |
5701 | case M_LWC3_AB: | |
5702 | s = "lwc3"; | |
bdaaa2e1 | 5703 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5704 | coproc = 1; |
5705 | goto ld; | |
5706 | case M_LWL_AB: | |
5707 | s = "lwl"; | |
5708 | lr = 1; | |
5709 | goto ld; | |
5710 | case M_LWR_AB: | |
5711 | s = "lwr"; | |
5712 | lr = 1; | |
5713 | goto ld; | |
5714 | case M_LDC1_AB: | |
fef14a42 | 5715 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5716 | { |
5717 | as_bad (_("opcode not supported on this processor")); | |
5718 | return; | |
5719 | } | |
5720 | s = "ldc1"; | |
bdaaa2e1 | 5721 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5722 | coproc = 1; |
5723 | goto ld; | |
5724 | case M_LDC2_AB: | |
5725 | s = "ldc2"; | |
bdaaa2e1 | 5726 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5727 | coproc = 1; |
5728 | goto ld; | |
5729 | case M_LDC3_AB: | |
5730 | s = "ldc3"; | |
bdaaa2e1 | 5731 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5732 | coproc = 1; |
5733 | goto ld; | |
5734 | case M_LDL_AB: | |
5735 | s = "ldl"; | |
5736 | lr = 1; | |
5737 | goto ld; | |
5738 | case M_LDR_AB: | |
5739 | s = "ldr"; | |
5740 | lr = 1; | |
5741 | goto ld; | |
5742 | case M_LL_AB: | |
5743 | s = "ll"; | |
5744 | goto ld; | |
5745 | case M_LLD_AB: | |
5746 | s = "lld"; | |
5747 | goto ld; | |
5748 | case M_LWU_AB: | |
5749 | s = "lwu"; | |
5750 | ld: | |
5751 | if (breg == treg || coproc || lr) | |
5752 | { | |
5753 | tempreg = AT; | |
5754 | used_at = 1; | |
5755 | } | |
5756 | else | |
5757 | { | |
5758 | tempreg = treg; | |
5759 | used_at = 0; | |
5760 | } | |
5761 | goto ld_st; | |
5762 | case M_SB_AB: | |
5763 | s = "sb"; | |
5764 | goto st; | |
5765 | case M_SH_AB: | |
5766 | s = "sh"; | |
5767 | goto st; | |
5768 | case M_SW_AB: | |
5769 | s = "sw"; | |
5770 | goto st; | |
5771 | case M_SWC0_AB: | |
5772 | s = "swc0"; | |
bdaaa2e1 | 5773 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5774 | coproc = 1; |
5775 | goto st; | |
5776 | case M_SWC1_AB: | |
5777 | s = "swc1"; | |
bdaaa2e1 | 5778 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5779 | coproc = 1; |
5780 | goto st; | |
5781 | case M_SWC2_AB: | |
5782 | s = "swc2"; | |
bdaaa2e1 | 5783 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5784 | coproc = 1; |
5785 | goto st; | |
5786 | case M_SWC3_AB: | |
5787 | s = "swc3"; | |
bdaaa2e1 | 5788 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5789 | coproc = 1; |
5790 | goto st; | |
5791 | case M_SWL_AB: | |
5792 | s = "swl"; | |
5793 | goto st; | |
5794 | case M_SWR_AB: | |
5795 | s = "swr"; | |
5796 | goto st; | |
5797 | case M_SC_AB: | |
5798 | s = "sc"; | |
5799 | goto st; | |
5800 | case M_SCD_AB: | |
5801 | s = "scd"; | |
5802 | goto st; | |
5803 | case M_SDC1_AB: | |
fef14a42 | 5804 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5805 | { |
5806 | as_bad (_("opcode not supported on this processor")); | |
5807 | return; | |
5808 | } | |
5809 | s = "sdc1"; | |
5810 | coproc = 1; | |
bdaaa2e1 | 5811 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5812 | goto st; |
5813 | case M_SDC2_AB: | |
5814 | s = "sdc2"; | |
bdaaa2e1 | 5815 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5816 | coproc = 1; |
5817 | goto st; | |
5818 | case M_SDC3_AB: | |
5819 | s = "sdc3"; | |
bdaaa2e1 | 5820 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5821 | coproc = 1; |
5822 | goto st; | |
5823 | case M_SDL_AB: | |
5824 | s = "sdl"; | |
5825 | goto st; | |
5826 | case M_SDR_AB: | |
5827 | s = "sdr"; | |
5828 | st: | |
5829 | tempreg = AT; | |
5830 | used_at = 1; | |
5831 | ld_st: | |
bdaaa2e1 | 5832 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5833 | if (mask == M_LWC1_AB |
5834 | || mask == M_SWC1_AB | |
5835 | || mask == M_LDC1_AB | |
5836 | || mask == M_SDC1_AB | |
5837 | || mask == M_L_DAB | |
5838 | || mask == M_S_DAB) | |
5839 | fmt = "T,o(b)"; | |
5840 | else if (coproc) | |
5841 | fmt = "E,o(b)"; | |
5842 | else | |
5843 | fmt = "t,o(b)"; | |
5844 | ||
256ab948 TS |
5845 | /* Sign-extending 32-bit constants makes their handling easier. |
5846 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5847 | described below. */ | |
5848 | if ((! HAVE_64BIT_ADDRESSES | |
5849 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5850 | && (offset_expr.X_op == O_constant) |
5851 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5852 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5853 | { |
d17e7bce | 5854 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5855 | as_bad (_("constant too large")); |
ae826530 | 5856 | |
1b8e29e5 TS |
5857 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5858 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5859 | } |
256ab948 | 5860 | |
252b5132 RH |
5861 | if (offset_expr.X_op != O_constant |
5862 | && offset_expr.X_op != O_symbol) | |
5863 | { | |
5864 | as_bad (_("expression too complex")); | |
5865 | offset_expr.X_op = O_constant; | |
5866 | } | |
5867 | ||
5868 | /* A constant expression in PIC code can be handled just as it | |
5869 | is in non PIC code. */ | |
5870 | if (mips_pic == NO_PIC | |
5871 | || offset_expr.X_op == O_constant) | |
5872 | { | |
5873 | /* If this is a reference to a GP relative symbol, and there | |
5874 | is no base register, we want | |
cdf6fd85 | 5875 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5876 | Otherwise, if there is no base register, we want |
5877 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5878 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5879 | If we have a constant, we need two instructions anyhow, | |
5880 | so we always use the latter form. | |
5881 | ||
5882 | If we have a base register, and this is a reference to a | |
5883 | GP relative symbol, we want | |
5884 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5885 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5886 | Otherwise we want |
5887 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5888 | addu $tempreg,$tempreg,$breg | |
5889 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5890 | With a constant we always use the latter case. |
76b3015f | 5891 | |
d6bc6245 TS |
5892 | With 64bit address space and no base register and $at usable, |
5893 | we want | |
5894 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5895 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5896 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5897 | dsll32 $tempreg,0 | |
5898 | daddu $tempreg,$at | |
5899 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5900 | If we have a base register, we want | |
5901 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5902 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5903 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5904 | daddu $at,$breg | |
5905 | dsll32 $tempreg,0 | |
5906 | daddu $tempreg,$at | |
5907 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5908 | ||
5909 | Without $at we can't generate the optimal path for superscalar | |
5910 | processors here since this would require two temporary registers. | |
5911 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5912 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5913 | dsll $tempreg,16 | |
5914 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5915 | dsll $tempreg,16 | |
5916 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5917 | If we have a base register, we want | |
5918 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5919 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5920 | dsll $tempreg,16 | |
5921 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5922 | dsll $tempreg,16 | |
5923 | daddu $tempreg,$tempreg,$breg | |
5924 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5925 | |
5926 | If we have 64-bit addresses, as an optimization, for | |
5927 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5928 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5929 | mechanism since it is more efficient. Note that due to |
5930 | the signed offset used by memory operations, the 32-bit | |
5931 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5932 | probably attempt to generate 64-bit constants more |
5933 | efficiently in general. | |
9214dd3b AO |
5934 | |
5935 | As an extension for architectures with 64-bit registers, | |
5936 | we don't truncate 64-bit addresses given as literal | |
5937 | constants down to 32 bits, to support existing practice | |
5938 | in the mips64 Linux (the kernel), that compiles source | |
5939 | files with -mabi=64, assembling them as o32 or n32 (with | |
5940 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5941 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5942 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5943 | wasteful to compute the upper 32 bits of every |
5944 | non-literal address, that takes more space and time. | |
5945 | Some day this should probably be implemented as an | |
5946 | assembler option, such that the kernel doesn't have to | |
5947 | use such ugly hacks, even though it will still have to | |
5948 | end up converting the binary to ELF32 for a number of | |
5949 | platforms whose boot loaders don't support ELF64 | |
5950 | binaries. */ | |
256ab948 TS |
5951 | if ((HAVE_64BIT_ADDRESSES |
5952 | && ! (offset_expr.X_op == O_constant | |
5953 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5954 | || (HAVE_64BIT_GPRS | |
5955 | && offset_expr.X_op == O_constant | |
5956 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5957 | { |
e864ceca RS |
5958 | /* ??? We don't provide a GP-relative alternative for |
5959 | these macros. It used not to be possible with the | |
5960 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5961 | |
460597ba | 5962 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 5963 | { |
67c0d1eb RS |
5964 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5965 | BFD_RELOC_MIPS_HIGHEST); | |
5966 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5967 | BFD_RELOC_HI16_S); | |
5968 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5969 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5970 | if (breg != 0) |
67c0d1eb RS |
5971 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5972 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5973 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5974 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5975 | tempreg); | |
d6bc6245 TS |
5976 | used_at = 1; |
5977 | } | |
5978 | else | |
5979 | { | |
67c0d1eb RS |
5980 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5981 | BFD_RELOC_MIPS_HIGHEST); | |
5982 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5983 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5984 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5985 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5986 | tempreg, BFD_RELOC_HI16_S); | |
5987 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5988 | if (breg != 0) |
67c0d1eb | 5989 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5990 | tempreg, tempreg, breg); |
67c0d1eb | 5991 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5992 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
5993 | } |
5994 | ||
5995 | return; | |
5996 | } | |
256ab948 TS |
5997 | |
5998 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 5999 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6000 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6001 | |
252b5132 RH |
6002 | if (breg == 0) |
6003 | { | |
67c0d1eb RS |
6004 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6005 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6006 | { |
4d7206a2 | 6007 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6008 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6009 | mips_gp_register); | |
4d7206a2 | 6010 | relax_switch (); |
252b5132 RH |
6011 | used_at = 0; |
6012 | } | |
67c0d1eb RS |
6013 | macro_build_lui (&offset_expr, tempreg); |
6014 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6015 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6016 | if (mips_relax.sequence) |
6017 | relax_end (); | |
252b5132 RH |
6018 | } |
6019 | else | |
6020 | { | |
67c0d1eb RS |
6021 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6022 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6023 | { |
4d7206a2 | 6024 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6025 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6026 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6027 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6028 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6029 | relax_switch (); |
252b5132 | 6030 | } |
67c0d1eb RS |
6031 | macro_build_lui (&offset_expr, tempreg); |
6032 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6033 | tempreg, tempreg, breg); |
67c0d1eb | 6034 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6035 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6036 | if (mips_relax.sequence) |
6037 | relax_end (); | |
252b5132 RH |
6038 | } |
6039 | } | |
6040 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6041 | { | |
ed6fb7bd | 6042 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6043 | |
252b5132 RH |
6044 | /* If this is a reference to an external symbol, we want |
6045 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6046 | nop | |
6047 | <op> $treg,0($tempreg) | |
6048 | Otherwise we want | |
6049 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6050 | nop | |
6051 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6052 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6053 | |
6054 | For NewABI, we want | |
6055 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6056 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6057 | ||
252b5132 RH |
6058 | If there is a base register, we add it to $tempreg before |
6059 | the <op>. If there is a constant, we stick it in the | |
6060 | <op> instruction. We don't handle constants larger than | |
6061 | 16 bits, because we have no way to load the upper 16 bits | |
6062 | (actually, we could handle them for the subset of cases | |
6063 | in which we are not using $at). */ | |
6064 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6065 | if (HAVE_NEWABI) |
6066 | { | |
67c0d1eb RS |
6067 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6068 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6069 | if (breg != 0) |
67c0d1eb | 6070 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6071 | tempreg, tempreg, breg); |
67c0d1eb | 6072 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6073 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6074 | |
6075 | if (! used_at) | |
6076 | return; | |
6077 | ||
6078 | break; | |
6079 | } | |
252b5132 RH |
6080 | expr1.X_add_number = offset_expr.X_add_number; |
6081 | offset_expr.X_add_number = 0; | |
6082 | if (expr1.X_add_number < -0x8000 | |
6083 | || expr1.X_add_number >= 0x8000) | |
6084 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6085 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6086 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6087 | load_delay_nop (); |
4d7206a2 RS |
6088 | relax_start (offset_expr.X_add_symbol); |
6089 | relax_switch (); | |
67c0d1eb RS |
6090 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6091 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6092 | relax_end (); |
252b5132 | 6093 | if (breg != 0) |
67c0d1eb | 6094 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6095 | tempreg, tempreg, breg); |
67c0d1eb | 6096 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6097 | } |
f5040a92 | 6098 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6099 | { |
67c0d1eb | 6100 | int gpdelay; |
252b5132 RH |
6101 | |
6102 | /* If this is a reference to an external symbol, we want | |
6103 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6104 | addu $tempreg,$tempreg,$gp | |
6105 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6106 | <op> $treg,0($tempreg) | |
6107 | Otherwise we want | |
6108 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6109 | nop | |
6110 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6111 | <op> $treg,0($tempreg) | |
6112 | If there is a base register, we add it to $tempreg before | |
6113 | the <op>. If there is a constant, we stick it in the | |
6114 | <op> instruction. We don't handle constants larger than | |
6115 | 16 bits, because we have no way to load the upper 16 bits | |
6116 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6117 | in which we are not using $at). */ |
252b5132 RH |
6118 | assert (offset_expr.X_op == O_symbol); |
6119 | expr1.X_add_number = offset_expr.X_add_number; | |
6120 | offset_expr.X_add_number = 0; | |
6121 | if (expr1.X_add_number < -0x8000 | |
6122 | || expr1.X_add_number >= 0x8000) | |
6123 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6124 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6125 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6126 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6127 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6128 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6129 | mips_gp_register); | |
6130 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6131 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6132 | relax_switch (); |
67c0d1eb RS |
6133 | if (gpdelay) |
6134 | macro_build (NULL, "nop", ""); | |
6135 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6136 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6137 | load_delay_nop (); |
67c0d1eb RS |
6138 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6139 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6140 | relax_end (); |
6141 | ||
252b5132 | 6142 | if (breg != 0) |
67c0d1eb | 6143 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6144 | tempreg, tempreg, breg); |
67c0d1eb | 6145 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6146 | } |
f5040a92 AO |
6147 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6148 | { | |
f5040a92 AO |
6149 | /* If this is a reference to an external symbol, we want |
6150 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6151 | add $tempreg,$tempreg,$gp | |
6152 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6153 | <op> $treg,<ofst>($tempreg) | |
6154 | Otherwise, for local symbols, we want: | |
6155 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6156 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6157 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6158 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6159 | offset_expr.X_add_number = 0; |
6160 | if (expr1.X_add_number < -0x8000 | |
6161 | || expr1.X_add_number >= 0x8000) | |
6162 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6163 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6164 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6165 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6166 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6167 | mips_gp_register); | |
6168 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6169 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6170 | if (breg != 0) |
67c0d1eb | 6171 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6172 | tempreg, tempreg, breg); |
67c0d1eb | 6173 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6174 | |
4d7206a2 | 6175 | relax_switch (); |
f5040a92 | 6176 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6177 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6178 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6179 | if (breg != 0) |
67c0d1eb | 6180 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6181 | tempreg, tempreg, breg); |
67c0d1eb | 6182 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6183 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6184 | relax_end (); |
f5040a92 | 6185 | } |
252b5132 RH |
6186 | else |
6187 | abort (); | |
6188 | ||
6189 | if (! used_at) | |
6190 | return; | |
6191 | ||
6192 | break; | |
6193 | ||
6194 | case M_LI: | |
6195 | case M_LI_S: | |
67c0d1eb | 6196 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6197 | return; |
6198 | ||
6199 | case M_DLI: | |
67c0d1eb | 6200 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6201 | return; |
6202 | ||
6203 | case M_LI_SS: | |
6204 | if (imm_expr.X_op == O_constant) | |
6205 | { | |
67c0d1eb RS |
6206 | load_register (AT, &imm_expr, 0); |
6207 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6208 | break; |
6209 | } | |
6210 | else | |
6211 | { | |
6212 | assert (offset_expr.X_op == O_symbol | |
6213 | && strcmp (segment_name (S_GET_SEGMENT | |
6214 | (offset_expr.X_add_symbol)), | |
6215 | ".lit4") == 0 | |
6216 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6217 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6218 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6219 | return; |
6220 | } | |
6221 | ||
6222 | case M_LI_D: | |
ca4e0257 RS |
6223 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6224 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6225 | order 32 bits of the value and the low order 32 bits are either | |
6226 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6227 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6228 | { | |
ca4e0257 | 6229 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6230 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6231 | else |
6232 | { | |
6233 | int hreg, lreg; | |
6234 | ||
6235 | if (target_big_endian) | |
6236 | { | |
6237 | hreg = treg; | |
6238 | lreg = treg + 1; | |
6239 | } | |
6240 | else | |
6241 | { | |
6242 | hreg = treg + 1; | |
6243 | lreg = treg; | |
6244 | } | |
6245 | ||
6246 | if (hreg <= 31) | |
67c0d1eb | 6247 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6248 | if (lreg <= 31) |
6249 | { | |
6250 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6251 | move_register (lreg, 0); |
252b5132 RH |
6252 | else |
6253 | { | |
6254 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6255 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6256 | } |
6257 | } | |
6258 | } | |
6259 | return; | |
6260 | } | |
6261 | ||
6262 | /* We know that sym is in the .rdata section. First we get the | |
6263 | upper 16 bits of the address. */ | |
6264 | if (mips_pic == NO_PIC) | |
6265 | { | |
67c0d1eb | 6266 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6267 | } |
6268 | else if (mips_pic == SVR4_PIC) | |
6269 | { | |
67c0d1eb RS |
6270 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6271 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6272 | } |
252b5132 RH |
6273 | else |
6274 | abort (); | |
bdaaa2e1 | 6275 | |
252b5132 | 6276 | /* Now we load the register(s). */ |
ca4e0257 | 6277 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6278 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6279 | else |
6280 | { | |
67c0d1eb | 6281 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6282 | if (treg != RA) |
252b5132 RH |
6283 | { |
6284 | /* FIXME: How in the world do we deal with the possible | |
6285 | overflow here? */ | |
6286 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6287 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6288 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6289 | } |
6290 | } | |
252b5132 RH |
6291 | break; |
6292 | ||
6293 | case M_LI_DD: | |
ca4e0257 RS |
6294 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6295 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6296 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6297 | the value and the low order 32 bits are either zero or in | |
6298 | OFFSET_EXPR. */ | |
252b5132 RH |
6299 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6300 | { | |
67c0d1eb | 6301 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6302 | if (HAVE_64BIT_FPRS) |
6303 | { | |
6304 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6305 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6306 | } |
252b5132 RH |
6307 | else |
6308 | { | |
67c0d1eb | 6309 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6310 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6311 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6312 | else |
6313 | { | |
6314 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6315 | load_register (AT, &offset_expr, 0); |
6316 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6317 | } |
6318 | } | |
6319 | break; | |
6320 | } | |
6321 | ||
6322 | assert (offset_expr.X_op == O_symbol | |
6323 | && offset_expr.X_add_number == 0); | |
6324 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6325 | if (strcmp (s, ".lit8") == 0) | |
6326 | { | |
e7af610e | 6327 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6328 | { |
67c0d1eb | 6329 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6330 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6331 | return; |
6332 | } | |
c9914766 | 6333 | breg = mips_gp_register; |
252b5132 RH |
6334 | r = BFD_RELOC_MIPS_LITERAL; |
6335 | goto dob; | |
6336 | } | |
6337 | else | |
6338 | { | |
6339 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6340 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6341 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6342 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6343 | else |
6344 | { | |
6345 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6346 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6347 | } |
bdaaa2e1 | 6348 | |
e7af610e | 6349 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6350 | { |
67c0d1eb RS |
6351 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6352 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6353 | break; |
6354 | } | |
6355 | breg = AT; | |
6356 | r = BFD_RELOC_LO16; | |
6357 | goto dob; | |
6358 | } | |
6359 | ||
6360 | case M_L_DOB: | |
fef14a42 | 6361 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6362 | { |
6363 | as_bad (_("opcode not supported on this processor")); | |
6364 | return; | |
6365 | } | |
6366 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6367 | to adjust when loading from memory. */ | |
6368 | r = BFD_RELOC_LO16; | |
6369 | dob: | |
e7af610e | 6370 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6371 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6372 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6373 | /* FIXME: A possible overflow which I don't know how to deal |
6374 | with. */ | |
6375 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6376 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6377 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6378 | |
252b5132 RH |
6379 | if (breg != AT) |
6380 | return; | |
6381 | break; | |
6382 | ||
6383 | case M_L_DAB: | |
6384 | /* | |
6385 | * The MIPS assembler seems to check for X_add_number not | |
6386 | * being double aligned and generating: | |
6387 | * lui at,%hi(foo+1) | |
6388 | * addu at,at,v1 | |
6389 | * addiu at,at,%lo(foo+1) | |
6390 | * lwc1 f2,0(at) | |
6391 | * lwc1 f3,4(at) | |
6392 | * But, the resulting address is the same after relocation so why | |
6393 | * generate the extra instruction? | |
6394 | */ | |
fef14a42 | 6395 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6396 | { |
6397 | as_bad (_("opcode not supported on this processor")); | |
6398 | return; | |
6399 | } | |
bdaaa2e1 | 6400 | /* Itbl support may require additional care here. */ |
252b5132 | 6401 | coproc = 1; |
e7af610e | 6402 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6403 | { |
6404 | s = "ldc1"; | |
6405 | goto ld; | |
6406 | } | |
6407 | ||
6408 | s = "lwc1"; | |
6409 | fmt = "T,o(b)"; | |
6410 | goto ldd_std; | |
6411 | ||
6412 | case M_S_DAB: | |
fef14a42 | 6413 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6414 | { |
6415 | as_bad (_("opcode not supported on this processor")); | |
6416 | return; | |
6417 | } | |
6418 | ||
e7af610e | 6419 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6420 | { |
6421 | s = "sdc1"; | |
6422 | goto st; | |
6423 | } | |
6424 | ||
6425 | s = "swc1"; | |
6426 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6427 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6428 | coproc = 1; |
6429 | goto ldd_std; | |
6430 | ||
6431 | case M_LD_AB: | |
ca4e0257 | 6432 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6433 | { |
6434 | s = "ld"; | |
6435 | goto ld; | |
6436 | } | |
6437 | ||
6438 | s = "lw"; | |
6439 | fmt = "t,o(b)"; | |
6440 | goto ldd_std; | |
6441 | ||
6442 | case M_SD_AB: | |
ca4e0257 | 6443 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6444 | { |
6445 | s = "sd"; | |
6446 | goto st; | |
6447 | } | |
6448 | ||
6449 | s = "sw"; | |
6450 | fmt = "t,o(b)"; | |
6451 | ||
6452 | ldd_std: | |
6453 | if (offset_expr.X_op != O_symbol | |
6454 | && offset_expr.X_op != O_constant) | |
6455 | { | |
6456 | as_bad (_("expression too complex")); | |
6457 | offset_expr.X_op = O_constant; | |
6458 | } | |
6459 | ||
6460 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6461 | to adjust when loading from memory. We set coproc if we must | |
6462 | load $fn+1 first. */ | |
bdaaa2e1 | 6463 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6464 | if (! target_big_endian) |
6465 | coproc = 0; | |
6466 | ||
6467 | if (mips_pic == NO_PIC | |
6468 | || offset_expr.X_op == O_constant) | |
6469 | { | |
6470 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6471 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6472 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6473 | If we have a base register, we use this |
6474 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6475 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6476 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6477 | If this is not a GP relative symbol, we want |
6478 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6479 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6480 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6481 | If there is a base register, we add it to $at after the | |
6482 | lui instruction. If there is a constant, we always use | |
6483 | the last case. */ | |
e7d556df | 6484 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6485 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6486 | used_at = 1; |
252b5132 RH |
6487 | else |
6488 | { | |
4d7206a2 | 6489 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6490 | if (breg == 0) |
6491 | { | |
c9914766 | 6492 | tempreg = mips_gp_register; |
252b5132 RH |
6493 | used_at = 0; |
6494 | } | |
6495 | else | |
6496 | { | |
67c0d1eb | 6497 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6498 | AT, breg, mips_gp_register); |
252b5132 | 6499 | tempreg = AT; |
252b5132 RH |
6500 | used_at = 1; |
6501 | } | |
6502 | ||
beae10d5 | 6503 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6504 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6505 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6506 | offset_expr.X_add_number += 4; |
6507 | ||
6508 | /* Set mips_optimize to 2 to avoid inserting an | |
6509 | undesired nop. */ | |
6510 | hold_mips_optimize = mips_optimize; | |
6511 | mips_optimize = 2; | |
beae10d5 | 6512 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6513 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6514 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6515 | mips_optimize = hold_mips_optimize; |
6516 | ||
4d7206a2 | 6517 | relax_switch (); |
252b5132 RH |
6518 | |
6519 | /* We just generated two relocs. When tc_gen_reloc | |
6520 | handles this case, it will skip the first reloc and | |
6521 | handle the second. The second reloc already has an | |
6522 | extra addend of 4, which we added above. We must | |
6523 | subtract it out, and then subtract another 4 to make | |
6524 | the first reloc come out right. The second reloc | |
6525 | will come out right because we are going to add 4 to | |
6526 | offset_expr when we build its instruction below. | |
6527 | ||
6528 | If we have a symbol, then we don't want to include | |
6529 | the offset, because it will wind up being included | |
6530 | when we generate the reloc. */ | |
6531 | ||
6532 | if (offset_expr.X_op == O_constant) | |
6533 | offset_expr.X_add_number -= 8; | |
6534 | else | |
6535 | { | |
6536 | offset_expr.X_add_number = -4; | |
6537 | offset_expr.X_op = O_constant; | |
6538 | } | |
6539 | } | |
67c0d1eb | 6540 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6541 | if (breg != 0) |
67c0d1eb | 6542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6543 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6544 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6545 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6546 | /* FIXME: How do we handle overflow here? */ |
6547 | offset_expr.X_add_number += 4; | |
beae10d5 | 6548 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6549 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6550 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6551 | if (mips_relax.sequence) |
6552 | relax_end (); | |
bdaaa2e1 | 6553 | } |
252b5132 RH |
6554 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6555 | { | |
252b5132 RH |
6556 | /* If this is a reference to an external symbol, we want |
6557 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6558 | nop | |
6559 | <op> $treg,0($at) | |
6560 | <op> $treg+1,4($at) | |
6561 | Otherwise we want | |
6562 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6563 | nop | |
6564 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6565 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6566 | If there is a base register we add it to $at before the | |
6567 | lwc1 instructions. If there is a constant we include it | |
6568 | in the lwc1 instructions. */ | |
6569 | used_at = 1; | |
6570 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6571 | if (expr1.X_add_number < -0x8000 |
6572 | || expr1.X_add_number >= 0x8000 - 4) | |
6573 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6574 | load_got_offset (AT, &offset_expr); |
269137b2 | 6575 | load_delay_nop (); |
252b5132 | 6576 | if (breg != 0) |
67c0d1eb | 6577 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6578 | |
6579 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6580 | nop. */ | |
6581 | hold_mips_optimize = mips_optimize; | |
6582 | mips_optimize = 2; | |
4d7206a2 | 6583 | |
beae10d5 | 6584 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6585 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6586 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6587 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6588 | expr1.X_add_number += 4; |
67c0d1eb RS |
6589 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6590 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6591 | relax_switch (); |
67c0d1eb RS |
6592 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6593 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6594 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6595 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6596 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6597 | relax_end (); |
252b5132 | 6598 | |
4d7206a2 | 6599 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6600 | } |
6601 | else if (mips_pic == SVR4_PIC) | |
6602 | { | |
67c0d1eb | 6603 | int gpdelay; |
252b5132 RH |
6604 | |
6605 | /* If this is a reference to an external symbol, we want | |
6606 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6607 | addu $at,$at,$gp | |
6608 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6609 | nop | |
6610 | <op> $treg,0($at) | |
6611 | <op> $treg+1,4($at) | |
6612 | Otherwise we want | |
6613 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6614 | nop | |
6615 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6616 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6617 | If there is a base register we add it to $at before the | |
6618 | lwc1 instructions. If there is a constant we include it | |
6619 | in the lwc1 instructions. */ | |
6620 | used_at = 1; | |
6621 | expr1.X_add_number = offset_expr.X_add_number; | |
6622 | offset_expr.X_add_number = 0; | |
6623 | if (expr1.X_add_number < -0x8000 | |
6624 | || expr1.X_add_number >= 0x8000 - 4) | |
6625 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6626 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6627 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6628 | macro_build (&offset_expr, "lui", "t,u", |
6629 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6630 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6631 | AT, AT, mips_gp_register); |
67c0d1eb | 6632 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6633 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6634 | load_delay_nop (); |
252b5132 | 6635 | if (breg != 0) |
67c0d1eb | 6636 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6637 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6638 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6639 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6640 | expr1.X_add_number += 4; |
6641 | ||
6642 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6643 | nop. */ | |
6644 | hold_mips_optimize = mips_optimize; | |
6645 | mips_optimize = 2; | |
beae10d5 | 6646 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6647 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6648 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6649 | mips_optimize = hold_mips_optimize; |
6650 | expr1.X_add_number -= 4; | |
6651 | ||
4d7206a2 RS |
6652 | relax_switch (); |
6653 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6654 | if (gpdelay) |
6655 | macro_build (NULL, "nop", ""); | |
6656 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6657 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6658 | load_delay_nop (); |
252b5132 | 6659 | if (breg != 0) |
67c0d1eb | 6660 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6661 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6662 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6663 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6664 | offset_expr.X_add_number += 4; |
252b5132 RH |
6665 | |
6666 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6667 | nop. */ | |
6668 | hold_mips_optimize = mips_optimize; | |
6669 | mips_optimize = 2; | |
beae10d5 | 6670 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6671 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6672 | BFD_RELOC_LO16, AT); | |
252b5132 | 6673 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6674 | relax_end (); |
252b5132 | 6675 | } |
252b5132 RH |
6676 | else |
6677 | abort (); | |
6678 | ||
6679 | if (! used_at) | |
6680 | return; | |
6681 | ||
6682 | break; | |
6683 | ||
6684 | case M_LD_OB: | |
6685 | s = "lw"; | |
6686 | goto sd_ob; | |
6687 | case M_SD_OB: | |
6688 | s = "sw"; | |
6689 | sd_ob: | |
ca4e0257 | 6690 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6691 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6692 | offset_expr.X_add_number += 4; |
67c0d1eb | 6693 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6694 | return; |
6695 | ||
6696 | /* New code added to support COPZ instructions. | |
6697 | This code builds table entries out of the macros in mip_opcodes. | |
6698 | R4000 uses interlocks to handle coproc delays. | |
6699 | Other chips (like the R3000) require nops to be inserted for delays. | |
6700 | ||
f72c8c98 | 6701 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6702 | In order to fill delay slots for non-interlocked chips, |
6703 | we must have a way to specify delays based on the coprocessor. | |
6704 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6705 | What are the side-effects of the cop instruction? | |
6706 | What cache support might we have and what are its effects? | |
6707 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6708 | What registers are read/set/modified? |
252b5132 RH |
6709 | |
6710 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6711 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6712 | |
6713 | case M_COP0: | |
6714 | s = "c0"; | |
6715 | goto copz; | |
6716 | case M_COP1: | |
6717 | s = "c1"; | |
6718 | goto copz; | |
6719 | case M_COP2: | |
6720 | s = "c2"; | |
6721 | goto copz; | |
6722 | case M_COP3: | |
6723 | s = "c3"; | |
6724 | copz: | |
6725 | /* For now we just do C (same as Cz). The parameter will be | |
6726 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6727 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6728 | return; |
6729 | ||
ea1fb5dc | 6730 | case M_MOVE: |
67c0d1eb | 6731 | move_register (dreg, sreg); |
ea1fb5dc RS |
6732 | return; |
6733 | ||
252b5132 RH |
6734 | #ifdef LOSING_COMPILER |
6735 | default: | |
6736 | /* Try and see if this is a new itbl instruction. | |
6737 | This code builds table entries out of the macros in mip_opcodes. | |
6738 | FIXME: For now we just assemble the expression and pass it's | |
6739 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6740 | We may want to have the assembler assemble this value, |
252b5132 RH |
6741 | so that we gain the assembler's knowledge of delay slots, |
6742 | symbols, etc. | |
6743 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6744 | if (itbl_have_entries |
252b5132 | 6745 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6746 | { |
252b5132 RH |
6747 | s = ip->insn_mo->name; |
6748 | s2 = "cop3"; | |
6749 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6750 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6751 | return; |
beae10d5 | 6752 | } |
252b5132 RH |
6753 | macro2 (ip); |
6754 | return; | |
6755 | } | |
6756 | if (mips_opts.noat) | |
6757 | as_warn (_("Macro used $at after \".set noat\"")); | |
6758 | } | |
bdaaa2e1 | 6759 | |
252b5132 | 6760 | static void |
17a2f251 | 6761 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6762 | { |
6763 | register int treg, sreg, dreg, breg; | |
6764 | int tempreg; | |
6765 | int mask; | |
252b5132 RH |
6766 | int used_at; |
6767 | expressionS expr1; | |
6768 | const char *s; | |
6769 | const char *s2; | |
6770 | const char *fmt; | |
6771 | int likely = 0; | |
6772 | int dbl = 0; | |
6773 | int coproc = 0; | |
6774 | int lr = 0; | |
6775 | int imm = 0; | |
6776 | int off; | |
6777 | offsetT maxnum; | |
6778 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6779 | |
252b5132 RH |
6780 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6781 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6782 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6783 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6784 | |
252b5132 RH |
6785 | expr1.X_op = O_constant; |
6786 | expr1.X_op_symbol = NULL; | |
6787 | expr1.X_add_symbol = NULL; | |
6788 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6789 | |
252b5132 RH |
6790 | switch (mask) |
6791 | { | |
6792 | #endif /* LOSING_COMPILER */ | |
6793 | ||
6794 | case M_DMUL: | |
6795 | dbl = 1; | |
6796 | case M_MUL: | |
67c0d1eb RS |
6797 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6798 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6799 | return; |
6800 | ||
6801 | case M_DMUL_I: | |
6802 | dbl = 1; | |
6803 | case M_MUL_I: | |
6804 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6805 | not trying to be that fancy. GCC should do this for us | |
6806 | anyway. */ | |
67c0d1eb RS |
6807 | load_register (AT, &imm_expr, dbl); |
6808 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6809 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6810 | break; |
6811 | ||
6812 | case M_DMULO_I: | |
6813 | dbl = 1; | |
6814 | case M_MULO_I: | |
6815 | imm = 1; | |
6816 | goto do_mulo; | |
6817 | ||
6818 | case M_DMULO: | |
6819 | dbl = 1; | |
6820 | case M_MULO: | |
6821 | do_mulo: | |
b34976b6 | 6822 | mips_emit_delays (TRUE); |
252b5132 RH |
6823 | ++mips_opts.noreorder; |
6824 | mips_any_noreorder = 1; | |
6825 | if (imm) | |
67c0d1eb RS |
6826 | load_register (AT, &imm_expr, dbl); |
6827 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6828 | macro_build (NULL, "mflo", "d", dreg); | |
6829 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6830 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6831 | if (mips_trap) |
67c0d1eb | 6832 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6833 | else |
6834 | { | |
6835 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6836 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6837 | macro_build (NULL, "nop", "", 0); | |
6838 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6839 | } |
6840 | --mips_opts.noreorder; | |
67c0d1eb | 6841 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6842 | break; |
6843 | ||
6844 | case M_DMULOU_I: | |
6845 | dbl = 1; | |
6846 | case M_MULOU_I: | |
6847 | imm = 1; | |
6848 | goto do_mulou; | |
6849 | ||
6850 | case M_DMULOU: | |
6851 | dbl = 1; | |
6852 | case M_MULOU: | |
6853 | do_mulou: | |
b34976b6 | 6854 | mips_emit_delays (TRUE); |
252b5132 RH |
6855 | ++mips_opts.noreorder; |
6856 | mips_any_noreorder = 1; | |
6857 | if (imm) | |
67c0d1eb RS |
6858 | load_register (AT, &imm_expr, dbl); |
6859 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6860 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6861 | macro_build (NULL, "mfhi", "d", AT); |
6862 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6863 | if (mips_trap) |
67c0d1eb | 6864 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6865 | else |
6866 | { | |
6867 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6868 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6869 | macro_build (NULL, "nop", "", 0); | |
6870 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6871 | } |
6872 | --mips_opts.noreorder; | |
6873 | break; | |
6874 | ||
771c7ce4 | 6875 | case M_DROL: |
fef14a42 | 6876 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6877 | { |
6878 | if (dreg == sreg) | |
6879 | { | |
6880 | tempreg = AT; | |
6881 | used_at = 1; | |
6882 | } | |
6883 | else | |
6884 | { | |
6885 | tempreg = dreg; | |
6886 | used_at = 0; | |
6887 | } | |
67c0d1eb RS |
6888 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6889 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6890 | if (used_at) |
6891 | break; | |
6892 | return; | |
6893 | } | |
67c0d1eb RS |
6894 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6895 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6896 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6897 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6898 | break; |
6899 | ||
252b5132 | 6900 | case M_ROL: |
fef14a42 | 6901 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6902 | { |
6903 | if (dreg == sreg) | |
6904 | { | |
6905 | tempreg = AT; | |
6906 | used_at = 1; | |
6907 | } | |
6908 | else | |
6909 | { | |
6910 | tempreg = dreg; | |
6911 | used_at = 0; | |
6912 | } | |
67c0d1eb RS |
6913 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6914 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6915 | if (used_at) |
6916 | break; | |
6917 | return; | |
6918 | } | |
67c0d1eb RS |
6919 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6920 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6921 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6922 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6923 | break; |
6924 | ||
771c7ce4 TS |
6925 | case M_DROL_I: |
6926 | { | |
6927 | unsigned int rot; | |
82dd0097 | 6928 | char *l, *r; |
771c7ce4 TS |
6929 | |
6930 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6931 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6932 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6933 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6934 | { |
6935 | rot = (64 - rot) & 0x3f; | |
6936 | if (rot >= 32) | |
67c0d1eb | 6937 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6938 | else |
67c0d1eb | 6939 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 6940 | return; |
60b63b72 | 6941 | } |
483fc7cd | 6942 | if (rot == 0) |
483fc7cd | 6943 | { |
67c0d1eb | 6944 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6945 | return; |
483fc7cd | 6946 | } |
82dd0097 CD |
6947 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6948 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6949 | rot &= 0x1f; | |
67c0d1eb RS |
6950 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6951 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6952 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6953 | } |
6954 | break; | |
6955 | ||
252b5132 | 6956 | case M_ROL_I: |
771c7ce4 TS |
6957 | { |
6958 | unsigned int rot; | |
6959 | ||
6960 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6961 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6962 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6963 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6964 | { |
67c0d1eb | 6965 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 6966 | return; |
60b63b72 | 6967 | } |
483fc7cd | 6968 | if (rot == 0) |
483fc7cd | 6969 | { |
67c0d1eb | 6970 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6971 | return; |
483fc7cd | 6972 | } |
67c0d1eb RS |
6973 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6974 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6975 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6976 | } |
6977 | break; | |
6978 | ||
6979 | case M_DROR: | |
fef14a42 | 6980 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6981 | { |
67c0d1eb | 6982 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6983 | return; |
6984 | } | |
67c0d1eb RS |
6985 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6986 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6987 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6988 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6989 | break; |
6990 | ||
6991 | case M_ROR: | |
fef14a42 | 6992 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6993 | { |
67c0d1eb | 6994 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6995 | return; |
6996 | } | |
67c0d1eb RS |
6997 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6998 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6999 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7000 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7001 | break; |
7002 | ||
771c7ce4 TS |
7003 | case M_DROR_I: |
7004 | { | |
7005 | unsigned int rot; | |
82dd0097 | 7006 | char *l, *r; |
771c7ce4 TS |
7007 | |
7008 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7009 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7010 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7011 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7012 | { |
7013 | if (rot >= 32) | |
67c0d1eb | 7014 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7015 | else |
67c0d1eb | 7016 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7017 | return; |
7018 | } | |
483fc7cd | 7019 | if (rot == 0) |
483fc7cd | 7020 | { |
67c0d1eb | 7021 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7022 | return; |
483fc7cd | 7023 | } |
82dd0097 CD |
7024 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7025 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7026 | rot &= 0x1f; | |
67c0d1eb RS |
7027 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7028 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7029 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7030 | } |
7031 | break; | |
7032 | ||
252b5132 | 7033 | case M_ROR_I: |
771c7ce4 TS |
7034 | { |
7035 | unsigned int rot; | |
7036 | ||
7037 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7038 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7039 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7040 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7041 | { |
67c0d1eb | 7042 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7043 | return; |
7044 | } | |
483fc7cd | 7045 | if (rot == 0) |
483fc7cd | 7046 | { |
67c0d1eb | 7047 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7048 | return; |
483fc7cd | 7049 | } |
67c0d1eb RS |
7050 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7051 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7052 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7053 | } |
252b5132 RH |
7054 | break; |
7055 | ||
7056 | case M_S_DOB: | |
fef14a42 | 7057 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7058 | { |
7059 | as_bad (_("opcode not supported on this processor")); | |
7060 | return; | |
7061 | } | |
e7af610e | 7062 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7063 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7064 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7065 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7066 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7067 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7068 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7069 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7070 | return; |
7071 | ||
7072 | case M_SEQ: | |
7073 | if (sreg == 0) | |
67c0d1eb | 7074 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7075 | else if (treg == 0) |
67c0d1eb | 7076 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7077 | else |
7078 | { | |
67c0d1eb RS |
7079 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7080 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7081 | } |
7082 | return; | |
7083 | ||
7084 | case M_SEQ_I: | |
7085 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7086 | { | |
67c0d1eb | 7087 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7088 | return; |
7089 | } | |
7090 | if (sreg == 0) | |
7091 | { | |
7092 | as_warn (_("Instruction %s: result is always false"), | |
7093 | ip->insn_mo->name); | |
67c0d1eb | 7094 | move_register (dreg, 0); |
252b5132 RH |
7095 | return; |
7096 | } | |
7097 | if (imm_expr.X_op == O_constant | |
7098 | && imm_expr.X_add_number >= 0 | |
7099 | && imm_expr.X_add_number < 0x10000) | |
7100 | { | |
67c0d1eb | 7101 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7102 | used_at = 0; |
7103 | } | |
7104 | else if (imm_expr.X_op == O_constant | |
7105 | && imm_expr.X_add_number > -0x8000 | |
7106 | && imm_expr.X_add_number < 0) | |
7107 | { | |
7108 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7109 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7110 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7111 | used_at = 0; |
7112 | } | |
7113 | else | |
7114 | { | |
67c0d1eb RS |
7115 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7116 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7117 | used_at = 1; |
7118 | } | |
67c0d1eb | 7119 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7120 | if (used_at) |
7121 | break; | |
7122 | return; | |
7123 | ||
7124 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7125 | s = "slt"; | |
7126 | goto sge; | |
7127 | case M_SGEU: | |
7128 | s = "sltu"; | |
7129 | sge: | |
67c0d1eb RS |
7130 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7131 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7132 | return; |
7133 | ||
7134 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7135 | case M_SGEU_I: | |
7136 | if (imm_expr.X_op == O_constant | |
7137 | && imm_expr.X_add_number >= -0x8000 | |
7138 | && imm_expr.X_add_number < 0x8000) | |
7139 | { | |
67c0d1eb RS |
7140 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7141 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7142 | used_at = 0; |
7143 | } | |
7144 | else | |
7145 | { | |
67c0d1eb RS |
7146 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7147 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7148 | dreg, sreg, AT); | |
252b5132 RH |
7149 | used_at = 1; |
7150 | } | |
67c0d1eb | 7151 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7152 | if (used_at) |
7153 | break; | |
7154 | return; | |
7155 | ||
7156 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7157 | s = "slt"; | |
7158 | goto sgt; | |
7159 | case M_SGTU: | |
7160 | s = "sltu"; | |
7161 | sgt: | |
67c0d1eb | 7162 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7163 | return; |
7164 | ||
7165 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7166 | s = "slt"; | |
7167 | goto sgti; | |
7168 | case M_SGTU_I: | |
7169 | s = "sltu"; | |
7170 | sgti: | |
67c0d1eb RS |
7171 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7172 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7173 | break; |
7174 | ||
2396cfb9 | 7175 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7176 | s = "slt"; |
7177 | goto sle; | |
7178 | case M_SLEU: | |
7179 | s = "sltu"; | |
7180 | sle: | |
67c0d1eb RS |
7181 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7182 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7183 | return; |
7184 | ||
2396cfb9 | 7185 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7186 | s = "slt"; |
7187 | goto slei; | |
7188 | case M_SLEU_I: | |
7189 | s = "sltu"; | |
7190 | slei: | |
67c0d1eb RS |
7191 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7192 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7193 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7194 | break; |
7195 | ||
7196 | case M_SLT_I: | |
7197 | if (imm_expr.X_op == O_constant | |
7198 | && imm_expr.X_add_number >= -0x8000 | |
7199 | && imm_expr.X_add_number < 0x8000) | |
7200 | { | |
67c0d1eb | 7201 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7202 | return; |
7203 | } | |
67c0d1eb RS |
7204 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7205 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7206 | break; |
7207 | ||
7208 | case M_SLTU_I: | |
7209 | if (imm_expr.X_op == O_constant | |
7210 | && imm_expr.X_add_number >= -0x8000 | |
7211 | && imm_expr.X_add_number < 0x8000) | |
7212 | { | |
67c0d1eb | 7213 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7214 | BFD_RELOC_LO16); |
252b5132 RH |
7215 | return; |
7216 | } | |
67c0d1eb RS |
7217 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7218 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7219 | break; |
7220 | ||
7221 | case M_SNE: | |
7222 | if (sreg == 0) | |
67c0d1eb | 7223 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7224 | else if (treg == 0) |
67c0d1eb | 7225 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7226 | else |
7227 | { | |
67c0d1eb RS |
7228 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7229 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7230 | } |
7231 | return; | |
7232 | ||
7233 | case M_SNE_I: | |
7234 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7235 | { | |
67c0d1eb | 7236 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7237 | return; |
7238 | } | |
7239 | if (sreg == 0) | |
7240 | { | |
7241 | as_warn (_("Instruction %s: result is always true"), | |
7242 | ip->insn_mo->name); | |
67c0d1eb RS |
7243 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7244 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7245 | return; |
7246 | } | |
7247 | if (imm_expr.X_op == O_constant | |
7248 | && imm_expr.X_add_number >= 0 | |
7249 | && imm_expr.X_add_number < 0x10000) | |
7250 | { | |
67c0d1eb | 7251 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7252 | used_at = 0; |
7253 | } | |
7254 | else if (imm_expr.X_op == O_constant | |
7255 | && imm_expr.X_add_number > -0x8000 | |
7256 | && imm_expr.X_add_number < 0) | |
7257 | { | |
7258 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7259 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7260 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7261 | used_at = 0; |
7262 | } | |
7263 | else | |
7264 | { | |
67c0d1eb RS |
7265 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7266 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7267 | used_at = 1; |
7268 | } | |
67c0d1eb | 7269 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7270 | if (used_at) |
7271 | break; | |
7272 | return; | |
7273 | ||
7274 | case M_DSUB_I: | |
7275 | dbl = 1; | |
7276 | case M_SUB_I: | |
7277 | if (imm_expr.X_op == O_constant | |
7278 | && imm_expr.X_add_number > -0x8000 | |
7279 | && imm_expr.X_add_number <= 0x8000) | |
7280 | { | |
7281 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7282 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7283 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7284 | return; |
7285 | } | |
67c0d1eb RS |
7286 | load_register (AT, &imm_expr, dbl); |
7287 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7288 | break; |
7289 | ||
7290 | case M_DSUBU_I: | |
7291 | dbl = 1; | |
7292 | case M_SUBU_I: | |
7293 | if (imm_expr.X_op == O_constant | |
7294 | && imm_expr.X_add_number > -0x8000 | |
7295 | && imm_expr.X_add_number <= 0x8000) | |
7296 | { | |
7297 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7298 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7299 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7300 | return; |
7301 | } | |
67c0d1eb RS |
7302 | load_register (AT, &imm_expr, dbl); |
7303 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7304 | break; |
7305 | ||
7306 | case M_TEQ_I: | |
7307 | s = "teq"; | |
7308 | goto trap; | |
7309 | case M_TGE_I: | |
7310 | s = "tge"; | |
7311 | goto trap; | |
7312 | case M_TGEU_I: | |
7313 | s = "tgeu"; | |
7314 | goto trap; | |
7315 | case M_TLT_I: | |
7316 | s = "tlt"; | |
7317 | goto trap; | |
7318 | case M_TLTU_I: | |
7319 | s = "tltu"; | |
7320 | goto trap; | |
7321 | case M_TNE_I: | |
7322 | s = "tne"; | |
7323 | trap: | |
67c0d1eb RS |
7324 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7325 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7326 | break; |
7327 | ||
252b5132 | 7328 | case M_TRUNCWS: |
43841e91 | 7329 | case M_TRUNCWD: |
e7af610e | 7330 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7331 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7332 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7333 | ||
7334 | /* | |
7335 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7336 | * or is there a reason for it? | |
7337 | */ | |
b34976b6 | 7338 | mips_emit_delays (TRUE); |
252b5132 RH |
7339 | ++mips_opts.noreorder; |
7340 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7341 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7342 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7343 | macro_build (NULL, "nop", ""); | |
252b5132 | 7344 | expr1.X_add_number = 3; |
67c0d1eb | 7345 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7346 | expr1.X_add_number = 2; |
67c0d1eb RS |
7347 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7348 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7349 | macro_build (NULL, "nop", ""); | |
7350 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7351 | dreg, sreg); | |
7352 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7353 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7354 | --mips_opts.noreorder; |
7355 | break; | |
7356 | ||
7357 | case M_ULH: | |
7358 | s = "lb"; | |
7359 | goto ulh; | |
7360 | case M_ULHU: | |
7361 | s = "lbu"; | |
7362 | ulh: | |
7363 | if (offset_expr.X_add_number >= 0x7fff) | |
7364 | as_bad (_("operand overflow")); | |
252b5132 | 7365 | if (! target_big_endian) |
f9419b05 | 7366 | ++offset_expr.X_add_number; |
67c0d1eb | 7367 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7368 | if (! target_big_endian) |
f9419b05 | 7369 | --offset_expr.X_add_number; |
252b5132 | 7370 | else |
f9419b05 | 7371 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7372 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7373 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7374 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7375 | break; |
7376 | ||
7377 | case M_ULD: | |
7378 | s = "ldl"; | |
7379 | s2 = "ldr"; | |
7380 | off = 7; | |
7381 | goto ulw; | |
7382 | case M_ULW: | |
7383 | s = "lwl"; | |
7384 | s2 = "lwr"; | |
7385 | off = 3; | |
7386 | ulw: | |
7387 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7388 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7389 | if (treg != breg) |
7390 | tempreg = treg; | |
7391 | else | |
7392 | tempreg = AT; | |
252b5132 RH |
7393 | if (! target_big_endian) |
7394 | offset_expr.X_add_number += off; | |
67c0d1eb | 7395 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7396 | if (! target_big_endian) |
7397 | offset_expr.X_add_number -= off; | |
7398 | else | |
7399 | offset_expr.X_add_number += off; | |
67c0d1eb | 7400 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7401 | |
7402 | /* If necessary, move the result in tempreg the final destination. */ | |
7403 | if (treg == tempreg) | |
7404 | return; | |
7405 | /* Protect second load's delay slot. */ | |
017315e4 | 7406 | load_delay_nop (); |
67c0d1eb | 7407 | move_register (treg, tempreg); |
af22f5b2 | 7408 | break; |
252b5132 RH |
7409 | |
7410 | case M_ULD_A: | |
7411 | s = "ldl"; | |
7412 | s2 = "ldr"; | |
7413 | off = 7; | |
7414 | goto ulwa; | |
7415 | case M_ULW_A: | |
7416 | s = "lwl"; | |
7417 | s2 = "lwr"; | |
7418 | off = 3; | |
7419 | ulwa: | |
d6bc6245 | 7420 | used_at = 1; |
67c0d1eb | 7421 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7422 | if (breg != 0) |
67c0d1eb | 7423 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7424 | if (! target_big_endian) |
7425 | expr1.X_add_number = off; | |
7426 | else | |
7427 | expr1.X_add_number = 0; | |
67c0d1eb | 7428 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7429 | if (! target_big_endian) |
7430 | expr1.X_add_number = 0; | |
7431 | else | |
7432 | expr1.X_add_number = off; | |
67c0d1eb | 7433 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7434 | break; |
7435 | ||
7436 | case M_ULH_A: | |
7437 | case M_ULHU_A: | |
d6bc6245 | 7438 | used_at = 1; |
67c0d1eb | 7439 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7440 | if (breg != 0) |
67c0d1eb | 7441 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7442 | if (target_big_endian) |
7443 | expr1.X_add_number = 0; | |
67c0d1eb | 7444 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7445 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7446 | if (target_big_endian) |
7447 | expr1.X_add_number = 1; | |
7448 | else | |
7449 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7450 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7451 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7452 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7453 | break; |
7454 | ||
7455 | case M_USH: | |
7456 | if (offset_expr.X_add_number >= 0x7fff) | |
7457 | as_bad (_("operand overflow")); | |
7458 | if (target_big_endian) | |
f9419b05 | 7459 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7460 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7461 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7462 | if (target_big_endian) |
f9419b05 | 7463 | --offset_expr.X_add_number; |
252b5132 | 7464 | else |
f9419b05 | 7465 | ++offset_expr.X_add_number; |
67c0d1eb | 7466 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7467 | break; |
7468 | ||
7469 | case M_USD: | |
7470 | s = "sdl"; | |
7471 | s2 = "sdr"; | |
7472 | off = 7; | |
7473 | goto usw; | |
7474 | case M_USW: | |
7475 | s = "swl"; | |
7476 | s2 = "swr"; | |
7477 | off = 3; | |
7478 | usw: | |
7479 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7480 | as_bad (_("operand overflow")); | |
7481 | if (! target_big_endian) | |
7482 | offset_expr.X_add_number += off; | |
67c0d1eb | 7483 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7484 | if (! target_big_endian) |
7485 | offset_expr.X_add_number -= off; | |
7486 | else | |
7487 | offset_expr.X_add_number += off; | |
67c0d1eb | 7488 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7489 | return; |
7490 | ||
7491 | case M_USD_A: | |
7492 | s = "sdl"; | |
7493 | s2 = "sdr"; | |
7494 | off = 7; | |
7495 | goto uswa; | |
7496 | case M_USW_A: | |
7497 | s = "swl"; | |
7498 | s2 = "swr"; | |
7499 | off = 3; | |
7500 | uswa: | |
d6bc6245 | 7501 | used_at = 1; |
67c0d1eb | 7502 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7503 | if (breg != 0) |
67c0d1eb | 7504 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7505 | if (! target_big_endian) |
7506 | expr1.X_add_number = off; | |
7507 | else | |
7508 | expr1.X_add_number = 0; | |
67c0d1eb | 7509 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7510 | if (! target_big_endian) |
7511 | expr1.X_add_number = 0; | |
7512 | else | |
7513 | expr1.X_add_number = off; | |
67c0d1eb | 7514 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7515 | break; |
7516 | ||
7517 | case M_USH_A: | |
d6bc6245 | 7518 | used_at = 1; |
67c0d1eb | 7519 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7520 | if (breg != 0) |
67c0d1eb | 7521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7522 | if (! target_big_endian) |
7523 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7524 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7525 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7526 | if (! target_big_endian) |
7527 | expr1.X_add_number = 1; | |
7528 | else | |
7529 | expr1.X_add_number = 0; | |
67c0d1eb | 7530 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7531 | if (! target_big_endian) |
7532 | expr1.X_add_number = 0; | |
7533 | else | |
7534 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7535 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7536 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7537 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7538 | break; |
7539 | ||
7540 | default: | |
7541 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7542 | are added dynamically. */ |
252b5132 RH |
7543 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7544 | break; | |
7545 | } | |
7546 | if (mips_opts.noat) | |
7547 | as_warn (_("Macro used $at after \".set noat\"")); | |
7548 | } | |
7549 | ||
7550 | /* Implement macros in mips16 mode. */ | |
7551 | ||
7552 | static void | |
17a2f251 | 7553 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7554 | { |
7555 | int mask; | |
7556 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7557 | expressionS expr1; |
7558 | int dbl; | |
7559 | const char *s, *s2, *s3; | |
7560 | ||
7561 | mask = ip->insn_mo->mask; | |
7562 | ||
7563 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7564 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7565 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7566 | ||
252b5132 RH |
7567 | expr1.X_op = O_constant; |
7568 | expr1.X_op_symbol = NULL; | |
7569 | expr1.X_add_symbol = NULL; | |
7570 | expr1.X_add_number = 1; | |
7571 | ||
7572 | dbl = 0; | |
7573 | ||
7574 | switch (mask) | |
7575 | { | |
7576 | default: | |
7577 | internalError (); | |
7578 | ||
7579 | case M_DDIV_3: | |
7580 | dbl = 1; | |
7581 | case M_DIV_3: | |
7582 | s = "mflo"; | |
7583 | goto do_div3; | |
7584 | case M_DREM_3: | |
7585 | dbl = 1; | |
7586 | case M_REM_3: | |
7587 | s = "mfhi"; | |
7588 | do_div3: | |
b34976b6 | 7589 | mips_emit_delays (TRUE); |
252b5132 RH |
7590 | ++mips_opts.noreorder; |
7591 | mips_any_noreorder = 1; | |
67c0d1eb | 7592 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7593 | expr1.X_add_number = 2; |
67c0d1eb RS |
7594 | macro_build (&expr1, "bnez", "x,p", yreg); |
7595 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7596 | |
252b5132 RH |
7597 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7598 | since that causes an overflow. We should do that as well, | |
7599 | but I don't see how to do the comparisons without a temporary | |
7600 | register. */ | |
7601 | --mips_opts.noreorder; | |
67c0d1eb | 7602 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7603 | break; |
7604 | ||
7605 | case M_DIVU_3: | |
7606 | s = "divu"; | |
7607 | s2 = "mflo"; | |
7608 | goto do_divu3; | |
7609 | case M_REMU_3: | |
7610 | s = "divu"; | |
7611 | s2 = "mfhi"; | |
7612 | goto do_divu3; | |
7613 | case M_DDIVU_3: | |
7614 | s = "ddivu"; | |
7615 | s2 = "mflo"; | |
7616 | goto do_divu3; | |
7617 | case M_DREMU_3: | |
7618 | s = "ddivu"; | |
7619 | s2 = "mfhi"; | |
7620 | do_divu3: | |
b34976b6 | 7621 | mips_emit_delays (TRUE); |
252b5132 RH |
7622 | ++mips_opts.noreorder; |
7623 | mips_any_noreorder = 1; | |
67c0d1eb | 7624 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7625 | expr1.X_add_number = 2; |
67c0d1eb RS |
7626 | macro_build (&expr1, "bnez", "x,p", yreg); |
7627 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7628 | --mips_opts.noreorder; |
67c0d1eb | 7629 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7630 | break; |
7631 | ||
7632 | case M_DMUL: | |
7633 | dbl = 1; | |
7634 | case M_MUL: | |
67c0d1eb RS |
7635 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7636 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7637 | return; |
7638 | ||
7639 | case M_DSUBU_I: | |
7640 | dbl = 1; | |
7641 | goto do_subu; | |
7642 | case M_SUBU_I: | |
7643 | do_subu: | |
7644 | if (imm_expr.X_op != O_constant) | |
7645 | as_bad (_("Unsupported large constant")); | |
7646 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7647 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7648 | break; |
7649 | ||
7650 | case M_SUBU_I_2: | |
7651 | if (imm_expr.X_op != O_constant) | |
7652 | as_bad (_("Unsupported large constant")); | |
7653 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7654 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7655 | break; |
7656 | ||
7657 | case M_DSUBU_I_2: | |
7658 | if (imm_expr.X_op != O_constant) | |
7659 | as_bad (_("Unsupported large constant")); | |
7660 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7661 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7662 | break; |
7663 | ||
7664 | case M_BEQ: | |
7665 | s = "cmp"; | |
7666 | s2 = "bteqz"; | |
7667 | goto do_branch; | |
7668 | case M_BNE: | |
7669 | s = "cmp"; | |
7670 | s2 = "btnez"; | |
7671 | goto do_branch; | |
7672 | case M_BLT: | |
7673 | s = "slt"; | |
7674 | s2 = "btnez"; | |
7675 | goto do_branch; | |
7676 | case M_BLTU: | |
7677 | s = "sltu"; | |
7678 | s2 = "btnez"; | |
7679 | goto do_branch; | |
7680 | case M_BLE: | |
7681 | s = "slt"; | |
7682 | s2 = "bteqz"; | |
7683 | goto do_reverse_branch; | |
7684 | case M_BLEU: | |
7685 | s = "sltu"; | |
7686 | s2 = "bteqz"; | |
7687 | goto do_reverse_branch; | |
7688 | case M_BGE: | |
7689 | s = "slt"; | |
7690 | s2 = "bteqz"; | |
7691 | goto do_branch; | |
7692 | case M_BGEU: | |
7693 | s = "sltu"; | |
7694 | s2 = "bteqz"; | |
7695 | goto do_branch; | |
7696 | case M_BGT: | |
7697 | s = "slt"; | |
7698 | s2 = "btnez"; | |
7699 | goto do_reverse_branch; | |
7700 | case M_BGTU: | |
7701 | s = "sltu"; | |
7702 | s2 = "btnez"; | |
7703 | ||
7704 | do_reverse_branch: | |
7705 | tmp = xreg; | |
7706 | xreg = yreg; | |
7707 | yreg = tmp; | |
7708 | ||
7709 | do_branch: | |
67c0d1eb RS |
7710 | macro_build (NULL, s, "x,y", xreg, yreg); |
7711 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7712 | break; |
7713 | ||
7714 | case M_BEQ_I: | |
7715 | s = "cmpi"; | |
7716 | s2 = "bteqz"; | |
7717 | s3 = "x,U"; | |
7718 | goto do_branch_i; | |
7719 | case M_BNE_I: | |
7720 | s = "cmpi"; | |
7721 | s2 = "btnez"; | |
7722 | s3 = "x,U"; | |
7723 | goto do_branch_i; | |
7724 | case M_BLT_I: | |
7725 | s = "slti"; | |
7726 | s2 = "btnez"; | |
7727 | s3 = "x,8"; | |
7728 | goto do_branch_i; | |
7729 | case M_BLTU_I: | |
7730 | s = "sltiu"; | |
7731 | s2 = "btnez"; | |
7732 | s3 = "x,8"; | |
7733 | goto do_branch_i; | |
7734 | case M_BLE_I: | |
7735 | s = "slti"; | |
7736 | s2 = "btnez"; | |
7737 | s3 = "x,8"; | |
7738 | goto do_addone_branch_i; | |
7739 | case M_BLEU_I: | |
7740 | s = "sltiu"; | |
7741 | s2 = "btnez"; | |
7742 | s3 = "x,8"; | |
7743 | goto do_addone_branch_i; | |
7744 | case M_BGE_I: | |
7745 | s = "slti"; | |
7746 | s2 = "bteqz"; | |
7747 | s3 = "x,8"; | |
7748 | goto do_branch_i; | |
7749 | case M_BGEU_I: | |
7750 | s = "sltiu"; | |
7751 | s2 = "bteqz"; | |
7752 | s3 = "x,8"; | |
7753 | goto do_branch_i; | |
7754 | case M_BGT_I: | |
7755 | s = "slti"; | |
7756 | s2 = "bteqz"; | |
7757 | s3 = "x,8"; | |
7758 | goto do_addone_branch_i; | |
7759 | case M_BGTU_I: | |
7760 | s = "sltiu"; | |
7761 | s2 = "bteqz"; | |
7762 | s3 = "x,8"; | |
7763 | ||
7764 | do_addone_branch_i: | |
7765 | if (imm_expr.X_op != O_constant) | |
7766 | as_bad (_("Unsupported large constant")); | |
7767 | ++imm_expr.X_add_number; | |
7768 | ||
7769 | do_branch_i: | |
67c0d1eb RS |
7770 | macro_build (&imm_expr, s, s3, xreg); |
7771 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7772 | break; |
7773 | ||
7774 | case M_ABS: | |
7775 | expr1.X_add_number = 0; | |
67c0d1eb | 7776 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7777 | if (xreg != yreg) |
67c0d1eb | 7778 | move_register (xreg, yreg); |
252b5132 | 7779 | expr1.X_add_number = 2; |
67c0d1eb RS |
7780 | macro_build (&expr1, "bteqz", "p"); |
7781 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7782 | } |
7783 | } | |
7784 | ||
7785 | /* For consistency checking, verify that all bits are specified either | |
7786 | by the match/mask part of the instruction definition, or by the | |
7787 | operand list. */ | |
7788 | static int | |
17a2f251 | 7789 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7790 | { |
7791 | const char *p = opc->args; | |
7792 | char c; | |
7793 | unsigned long used_bits = opc->mask; | |
7794 | ||
7795 | if ((used_bits & opc->match) != opc->match) | |
7796 | { | |
7797 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7798 | opc->name, opc->args); | |
7799 | return 0; | |
7800 | } | |
7801 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7802 | while (*p) | |
7803 | switch (c = *p++) | |
7804 | { | |
7805 | case ',': break; | |
7806 | case '(': break; | |
7807 | case ')': break; | |
af7ee8bf CD |
7808 | case '+': |
7809 | switch (c = *p++) | |
7810 | { | |
7811 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7812 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7813 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7814 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7815 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7816 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7817 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7818 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7819 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7820 | case 'I': break; | |
af7ee8bf CD |
7821 | default: |
7822 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7823 | c, opc->name, opc->args); | |
7824 | return 0; | |
7825 | } | |
7826 | break; | |
252b5132 RH |
7827 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7828 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7829 | case 'A': break; | |
4372b673 | 7830 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7831 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7832 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7833 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7834 | case 'F': break; | |
7835 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7836 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7837 | case 'I': break; |
e972090a | 7838 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7839 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7840 | case 'L': break; |
7841 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7842 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7843 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7844 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7845 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7846 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7847 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7848 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7849 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7850 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7851 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7852 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7853 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7854 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7855 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7856 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7857 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7858 | case 'f': break; | |
7859 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7860 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7861 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7862 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7863 | case 'l': break; | |
7864 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7865 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7866 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7867 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7868 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7869 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7870 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7871 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7872 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7873 | case 'x': break; | |
7874 | case 'z': break; | |
7875 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7876 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7877 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7878 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7879 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7880 | case '[': break; | |
7881 | case ']': break; | |
252b5132 RH |
7882 | default: |
7883 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7884 | c, opc->name, opc->args); | |
7885 | return 0; | |
7886 | } | |
7887 | #undef USE_BITS | |
7888 | if (used_bits != 0xffffffff) | |
7889 | { | |
7890 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7891 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7892 | return 0; | |
7893 | } | |
7894 | return 1; | |
7895 | } | |
7896 | ||
7897 | /* This routine assembles an instruction into its binary format. As a | |
7898 | side effect, it sets one of the global variables imm_reloc or | |
7899 | offset_reloc to the type of relocation to do if one of the operands | |
7900 | is an address expression. */ | |
7901 | ||
7902 | static void | |
17a2f251 | 7903 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7904 | { |
7905 | char *s; | |
7906 | const char *args; | |
43841e91 | 7907 | char c = 0; |
252b5132 RH |
7908 | struct mips_opcode *insn; |
7909 | char *argsStart; | |
7910 | unsigned int regno; | |
7911 | unsigned int lastregno = 0; | |
af7ee8bf | 7912 | unsigned int lastpos = 0; |
071742cf | 7913 | unsigned int limlo, limhi; |
252b5132 RH |
7914 | char *s_reset; |
7915 | char save_c = 0; | |
252b5132 RH |
7916 | |
7917 | insn_error = NULL; | |
7918 | ||
7919 | /* If the instruction contains a '.', we first try to match an instruction | |
7920 | including the '.'. Then we try again without the '.'. */ | |
7921 | insn = NULL; | |
3882b010 | 7922 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7923 | continue; |
7924 | ||
7925 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7926 | the call to hash_find. Save the character we replaced just in case we | |
7927 | have to re-parse the instruction. */ | |
3882b010 | 7928 | if (ISSPACE (*s)) |
252b5132 RH |
7929 | { |
7930 | save_c = *s; | |
7931 | *s++ = '\0'; | |
7932 | } | |
bdaaa2e1 | 7933 | |
252b5132 RH |
7934 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7935 | ||
7936 | /* If we didn't find the instruction in the opcode table, try again, but | |
7937 | this time with just the instruction up to, but not including the | |
7938 | first '.'. */ | |
7939 | if (insn == NULL) | |
7940 | { | |
bdaaa2e1 | 7941 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7942 | if (save_c) |
7943 | *(--s) = save_c; | |
7944 | ||
7945 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7946 | for (s = str; |
7947 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7948 | ++s) | |
252b5132 RH |
7949 | continue; |
7950 | ||
7951 | /* If we did not find a '.', then we can quit now. */ | |
7952 | if (*s != '.') | |
7953 | { | |
7954 | insn_error = "unrecognized opcode"; | |
7955 | return; | |
7956 | } | |
7957 | ||
7958 | /* Lookup the instruction in the hash table. */ | |
7959 | *s++ = '\0'; | |
7960 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7961 | { | |
7962 | insn_error = "unrecognized opcode"; | |
7963 | return; | |
7964 | } | |
252b5132 RH |
7965 | } |
7966 | ||
7967 | argsStart = s; | |
7968 | for (;;) | |
7969 | { | |
b34976b6 | 7970 | bfd_boolean ok; |
252b5132 RH |
7971 | |
7972 | assert (strcmp (insn->name, str) == 0); | |
7973 | ||
1f25f5d3 CD |
7974 | if (OPCODE_IS_MEMBER (insn, |
7975 | (mips_opts.isa | |
3396de36 | 7976 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7977 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7978 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7979 | mips_opts.arch)) |
b34976b6 | 7980 | ok = TRUE; |
bdaaa2e1 | 7981 | else |
b34976b6 | 7982 | ok = FALSE; |
bdaaa2e1 | 7983 | |
252b5132 RH |
7984 | if (insn->pinfo != INSN_MACRO) |
7985 | { | |
fef14a42 | 7986 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7987 | ok = FALSE; |
252b5132 RH |
7988 | } |
7989 | ||
7990 | if (! ok) | |
7991 | { | |
7992 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7993 | && strcmp (insn->name, insn[1].name) == 0) | |
7994 | { | |
7995 | ++insn; | |
7996 | continue; | |
7997 | } | |
252b5132 | 7998 | else |
beae10d5 | 7999 | { |
268f6bed L |
8000 | if (!insn_error) |
8001 | { | |
8002 | static char buf[100]; | |
fef14a42 TS |
8003 | sprintf (buf, |
8004 | _("opcode not supported on this processor: %s (%s)"), | |
8005 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8006 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8007 | insn_error = buf; |
8008 | } | |
8009 | if (save_c) | |
8010 | *(--s) = save_c; | |
2bd7f1f3 | 8011 | return; |
252b5132 | 8012 | } |
252b5132 RH |
8013 | } |
8014 | ||
8015 | ip->insn_mo = insn; | |
8016 | ip->insn_opcode = insn->match; | |
268f6bed | 8017 | insn_error = NULL; |
252b5132 RH |
8018 | for (args = insn->args;; ++args) |
8019 | { | |
deec1734 CD |
8020 | int is_mdmx; |
8021 | ||
ad8d3bb3 | 8022 | s += strspn (s, " \t"); |
deec1734 | 8023 | is_mdmx = 0; |
252b5132 RH |
8024 | switch (*args) |
8025 | { | |
8026 | case '\0': /* end of args */ | |
8027 | if (*s == '\0') | |
8028 | return; | |
8029 | break; | |
8030 | ||
8031 | case ',': | |
8032 | if (*s++ == *args) | |
8033 | continue; | |
8034 | s--; | |
8035 | switch (*++args) | |
8036 | { | |
8037 | case 'r': | |
8038 | case 'v': | |
38487616 | 8039 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8040 | continue; |
8041 | ||
8042 | case 'w': | |
38487616 TS |
8043 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8044 | continue; | |
8045 | ||
252b5132 | 8046 | case 'W': |
38487616 | 8047 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8048 | continue; |
8049 | ||
8050 | case 'V': | |
38487616 | 8051 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8052 | continue; |
8053 | } | |
8054 | break; | |
8055 | ||
8056 | case '(': | |
8057 | /* Handle optional base register. | |
8058 | Either the base register is omitted or | |
bdaaa2e1 | 8059 | we must have a left paren. */ |
252b5132 RH |
8060 | /* This is dependent on the next operand specifier |
8061 | is a base register specification. */ | |
8062 | assert (args[1] == 'b' || args[1] == '5' | |
8063 | || args[1] == '-' || args[1] == '4'); | |
8064 | if (*s == '\0') | |
8065 | return; | |
8066 | ||
8067 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8068 | case '[': |
8069 | case ']': | |
252b5132 RH |
8070 | if (*s++ == *args) |
8071 | continue; | |
8072 | break; | |
8073 | ||
af7ee8bf CD |
8074 | case '+': /* Opcode extension character. */ |
8075 | switch (*++args) | |
8076 | { | |
071742cf CD |
8077 | case 'A': /* ins/ext position, becomes LSB. */ |
8078 | limlo = 0; | |
8079 | limhi = 31; | |
5f74bc13 CD |
8080 | goto do_lsb; |
8081 | case 'E': | |
8082 | limlo = 32; | |
8083 | limhi = 63; | |
8084 | goto do_lsb; | |
8085 | do_lsb: | |
071742cf CD |
8086 | my_getExpression (&imm_expr, s); |
8087 | check_absolute_expr (ip, &imm_expr); | |
8088 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8089 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8090 | { | |
8091 | as_bad (_("Improper position (%lu)"), | |
8092 | (unsigned long) imm_expr.X_add_number); | |
8093 | imm_expr.X_add_number = limlo; | |
8094 | } | |
8095 | lastpos = imm_expr.X_add_number; | |
8096 | ip->insn_opcode |= (imm_expr.X_add_number | |
8097 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8098 | imm_expr.X_op = O_absent; | |
8099 | s = expr_end; | |
8100 | continue; | |
8101 | ||
8102 | case 'B': /* ins size, becomes MSB. */ | |
8103 | limlo = 1; | |
8104 | limhi = 32; | |
5f74bc13 CD |
8105 | goto do_msb; |
8106 | case 'F': | |
8107 | limlo = 33; | |
8108 | limhi = 64; | |
8109 | goto do_msb; | |
8110 | do_msb: | |
071742cf CD |
8111 | my_getExpression (&imm_expr, s); |
8112 | check_absolute_expr (ip, &imm_expr); | |
8113 | /* Check for negative input so that small negative numbers | |
8114 | will not succeed incorrectly. The checks against | |
8115 | (pos+size) transitively check "size" itself, | |
8116 | assuming that "pos" is reasonable. */ | |
8117 | if ((long) imm_expr.X_add_number < 0 | |
8118 | || ((unsigned long) imm_expr.X_add_number | |
8119 | + lastpos) < limlo | |
8120 | || ((unsigned long) imm_expr.X_add_number | |
8121 | + lastpos) > limhi) | |
8122 | { | |
8123 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8124 | (unsigned long) imm_expr.X_add_number, | |
8125 | (unsigned long) lastpos); | |
8126 | imm_expr.X_add_number = limlo - lastpos; | |
8127 | } | |
8128 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8129 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8130 | imm_expr.X_op = O_absent; | |
8131 | s = expr_end; | |
8132 | continue; | |
8133 | ||
8134 | case 'C': /* ext size, becomes MSBD. */ | |
8135 | limlo = 1; | |
8136 | limhi = 32; | |
5f74bc13 CD |
8137 | goto do_msbd; |
8138 | case 'G': | |
8139 | limlo = 33; | |
8140 | limhi = 64; | |
8141 | goto do_msbd; | |
8142 | case 'H': | |
8143 | limlo = 33; | |
8144 | limhi = 64; | |
8145 | goto do_msbd; | |
8146 | do_msbd: | |
071742cf CD |
8147 | my_getExpression (&imm_expr, s); |
8148 | check_absolute_expr (ip, &imm_expr); | |
8149 | /* Check for negative input so that small negative numbers | |
8150 | will not succeed incorrectly. The checks against | |
8151 | (pos+size) transitively check "size" itself, | |
8152 | assuming that "pos" is reasonable. */ | |
8153 | if ((long) imm_expr.X_add_number < 0 | |
8154 | || ((unsigned long) imm_expr.X_add_number | |
8155 | + lastpos) < limlo | |
8156 | || ((unsigned long) imm_expr.X_add_number | |
8157 | + lastpos) > limhi) | |
8158 | { | |
8159 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8160 | (unsigned long) imm_expr.X_add_number, | |
8161 | (unsigned long) lastpos); | |
8162 | imm_expr.X_add_number = limlo - lastpos; | |
8163 | } | |
8164 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8165 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8166 | imm_expr.X_op = O_absent; | |
8167 | s = expr_end; | |
8168 | continue; | |
af7ee8bf | 8169 | |
bbcc0807 CD |
8170 | case 'D': |
8171 | /* +D is for disassembly only; never match. */ | |
8172 | break; | |
8173 | ||
5f74bc13 CD |
8174 | case 'I': |
8175 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8176 | my_getExpression (&imm2_expr, s); | |
8177 | if (imm2_expr.X_op != O_big | |
8178 | && imm2_expr.X_op != O_constant) | |
8179 | insn_error = _("absolute expression required"); | |
13757d0c | 8180 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8181 | s = expr_end; |
8182 | continue; | |
8183 | ||
af7ee8bf CD |
8184 | default: |
8185 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8186 | *args, insn->name, insn->args); | |
8187 | /* Further processing is fruitless. */ | |
8188 | return; | |
8189 | } | |
8190 | break; | |
8191 | ||
252b5132 RH |
8192 | case '<': /* must be at least one digit */ |
8193 | /* | |
8194 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8195 | * than 31 or less than 0, then the shift amount should be |
8196 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8197 | * We issue a warning and mask out all but the low 5 bits. |
8198 | */ | |
8199 | my_getExpression (&imm_expr, s); | |
8200 | check_absolute_expr (ip, &imm_expr); | |
8201 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8202 | { | |
793b27f4 TS |
8203 | as_warn (_("Improper shift amount (%lu)"), |
8204 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8205 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8206 | } |
38487616 | 8207 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8208 | imm_expr.X_op = O_absent; |
8209 | s = expr_end; | |
8210 | continue; | |
8211 | ||
8212 | case '>': /* shift amount minus 32 */ | |
8213 | my_getExpression (&imm_expr, s); | |
8214 | check_absolute_expr (ip, &imm_expr); | |
8215 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8216 | || (unsigned long) imm_expr.X_add_number > 63) | |
8217 | break; | |
38487616 | 8218 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8219 | imm_expr.X_op = O_absent; |
8220 | s = expr_end; | |
8221 | continue; | |
8222 | ||
252b5132 RH |
8223 | case 'k': /* cache code */ |
8224 | case 'h': /* prefx code */ | |
8225 | my_getExpression (&imm_expr, s); | |
8226 | check_absolute_expr (ip, &imm_expr); | |
8227 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8228 | { | |
8229 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8230 | ip->insn_mo->name, | |
8231 | (unsigned long) imm_expr.X_add_number); | |
8232 | imm_expr.X_add_number &= 0x1f; | |
8233 | } | |
8234 | if (*args == 'k') | |
8235 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8236 | else | |
8237 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8238 | imm_expr.X_op = O_absent; | |
8239 | s = expr_end; | |
8240 | continue; | |
8241 | ||
8242 | case 'c': /* break code */ | |
8243 | my_getExpression (&imm_expr, s); | |
8244 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8245 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8246 | { |
793b27f4 TS |
8247 | as_warn (_("Illegal break code (%lu)"), |
8248 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8249 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8250 | } |
38487616 | 8251 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8252 | imm_expr.X_op = O_absent; |
8253 | s = expr_end; | |
8254 | continue; | |
8255 | ||
8256 | case 'q': /* lower break code */ | |
8257 | my_getExpression (&imm_expr, s); | |
8258 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8259 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8260 | { |
793b27f4 TS |
8261 | as_warn (_("Illegal lower break code (%lu)"), |
8262 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8263 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8264 | } |
38487616 | 8265 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8266 | imm_expr.X_op = O_absent; |
8267 | s = expr_end; | |
8268 | continue; | |
8269 | ||
4372b673 | 8270 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8271 | my_getExpression (&imm_expr, s); |
156c2f8b | 8272 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8273 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8274 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8275 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8276 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8277 | imm_expr.X_op = O_absent; |
8278 | s = expr_end; | |
8279 | continue; | |
8280 | ||
98d3f06f | 8281 | case 'C': /* Coprocessor code */ |
beae10d5 | 8282 | my_getExpression (&imm_expr, s); |
252b5132 | 8283 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8284 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8285 | { |
793b27f4 TS |
8286 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8287 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8288 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8289 | } |
beae10d5 KH |
8290 | ip->insn_opcode |= imm_expr.X_add_number; |
8291 | imm_expr.X_op = O_absent; | |
8292 | s = expr_end; | |
8293 | continue; | |
252b5132 | 8294 | |
4372b673 NC |
8295 | case 'J': /* 19-bit wait code. */ |
8296 | my_getExpression (&imm_expr, s); | |
8297 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8298 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8299 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8300 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8301 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8302 | imm_expr.X_op = O_absent; |
8303 | s = expr_end; | |
8304 | continue; | |
8305 | ||
252b5132 | 8306 | case 'P': /* Performance register */ |
beae10d5 | 8307 | my_getExpression (&imm_expr, s); |
252b5132 | 8308 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8309 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8310 | { |
793b27f4 TS |
8311 | as_warn (_("Invalid performance register (%lu)"), |
8312 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8313 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8314 | } |
38487616 | 8315 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8316 | imm_expr.X_op = O_absent; |
8317 | s = expr_end; | |
8318 | continue; | |
252b5132 RH |
8319 | |
8320 | case 'b': /* base register */ | |
8321 | case 'd': /* destination register */ | |
8322 | case 's': /* source register */ | |
8323 | case 't': /* target register */ | |
8324 | case 'r': /* both target and source */ | |
8325 | case 'v': /* both dest and source */ | |
8326 | case 'w': /* both dest and target */ | |
8327 | case 'E': /* coprocessor target register */ | |
8328 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8329 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8330 | case 'x': /* ignore register name */ |
8331 | case 'z': /* must be zero register */ | |
4372b673 | 8332 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8333 | s_reset = s; |
8334 | if (s[0] == '$') | |
8335 | { | |
8336 | ||
3882b010 | 8337 | if (ISDIGIT (s[1])) |
252b5132 RH |
8338 | { |
8339 | ++s; | |
8340 | regno = 0; | |
8341 | do | |
8342 | { | |
8343 | regno *= 10; | |
8344 | regno += *s - '0'; | |
8345 | ++s; | |
8346 | } | |
3882b010 | 8347 | while (ISDIGIT (*s)); |
252b5132 RH |
8348 | if (regno > 31) |
8349 | as_bad (_("Invalid register number (%d)"), regno); | |
8350 | } | |
af7ee8bf | 8351 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8352 | goto notreg; |
8353 | else | |
8354 | { | |
76db943d TS |
8355 | if (s[1] == 'r' && s[2] == 'a') |
8356 | { | |
8357 | s += 3; | |
8358 | regno = RA; | |
8359 | } | |
8360 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8361 | { |
8362 | s += 3; | |
8363 | regno = FP; | |
8364 | } | |
8365 | else if (s[1] == 's' && s[2] == 'p') | |
8366 | { | |
8367 | s += 3; | |
8368 | regno = SP; | |
8369 | } | |
8370 | else if (s[1] == 'g' && s[2] == 'p') | |
8371 | { | |
8372 | s += 3; | |
8373 | regno = GP; | |
8374 | } | |
8375 | else if (s[1] == 'a' && s[2] == 't') | |
8376 | { | |
8377 | s += 3; | |
8378 | regno = AT; | |
8379 | } | |
8380 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8381 | { | |
8382 | s += 4; | |
8383 | regno = KT0; | |
8384 | } | |
8385 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8386 | { | |
8387 | s += 4; | |
8388 | regno = KT1; | |
8389 | } | |
85b51719 TS |
8390 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8391 | { | |
8392 | s += 5; | |
8393 | regno = ZERO; | |
8394 | } | |
252b5132 RH |
8395 | else if (itbl_have_entries) |
8396 | { | |
8397 | char *p, *n; | |
d7ba4a77 | 8398 | unsigned long r; |
252b5132 | 8399 | |
d7ba4a77 | 8400 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8401 | n = itbl_get_field (&p); /* n is name */ |
8402 | ||
d7ba4a77 ILT |
8403 | /* See if this is a register defined in an |
8404 | itbl entry. */ | |
8405 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8406 | { |
8407 | /* Get_field advances to the start of | |
8408 | the next field, so we need to back | |
d7ba4a77 | 8409 | rack to the end of the last field. */ |
bdaaa2e1 | 8410 | if (p) |
252b5132 | 8411 | s = p - 1; |
bdaaa2e1 | 8412 | else |
d7ba4a77 | 8413 | s = strchr (s, '\0'); |
252b5132 RH |
8414 | regno = r; |
8415 | } | |
8416 | else | |
8417 | goto notreg; | |
beae10d5 | 8418 | } |
252b5132 RH |
8419 | else |
8420 | goto notreg; | |
8421 | } | |
8422 | if (regno == AT | |
8423 | && ! mips_opts.noat | |
8424 | && *args != 'E' | |
af7ee8bf CD |
8425 | && *args != 'G' |
8426 | && *args != 'K') | |
252b5132 RH |
8427 | as_warn (_("Used $at without \".set noat\"")); |
8428 | c = *args; | |
8429 | if (*s == ' ') | |
f9419b05 | 8430 | ++s; |
252b5132 RH |
8431 | if (args[1] != *s) |
8432 | { | |
8433 | if (c == 'r' || c == 'v' || c == 'w') | |
8434 | { | |
8435 | regno = lastregno; | |
8436 | s = s_reset; | |
f9419b05 | 8437 | ++args; |
252b5132 RH |
8438 | } |
8439 | } | |
8440 | /* 'z' only matches $0. */ | |
8441 | if (c == 'z' && regno != 0) | |
8442 | break; | |
8443 | ||
bdaaa2e1 KH |
8444 | /* Now that we have assembled one operand, we use the args string |
8445 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8446 | switch (c) |
8447 | { | |
8448 | case 'r': | |
8449 | case 's': | |
8450 | case 'v': | |
8451 | case 'b': | |
38487616 | 8452 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8453 | break; |
8454 | case 'd': | |
8455 | case 'G': | |
af7ee8bf | 8456 | case 'K': |
38487616 | 8457 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8458 | break; |
4372b673 | 8459 | case 'U': |
38487616 TS |
8460 | ip->insn_opcode |= regno << OP_SH_RD; |
8461 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8462 | break; |
252b5132 RH |
8463 | case 'w': |
8464 | case 't': | |
8465 | case 'E': | |
38487616 | 8466 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8467 | break; |
8468 | case 'x': | |
8469 | /* This case exists because on the r3000 trunc | |
8470 | expands into a macro which requires a gp | |
8471 | register. On the r6000 or r4000 it is | |
8472 | assembled into a single instruction which | |
8473 | ignores the register. Thus the insn version | |
8474 | is MIPS_ISA2 and uses 'x', and the macro | |
8475 | version is MIPS_ISA1 and uses 't'. */ | |
8476 | break; | |
8477 | case 'z': | |
8478 | /* This case is for the div instruction, which | |
8479 | acts differently if the destination argument | |
8480 | is $0. This only matches $0, and is checked | |
8481 | outside the switch. */ | |
8482 | break; | |
8483 | case 'D': | |
8484 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8485 | break; | |
8486 | /* What about all other operands like 'i', which | |
8487 | can be specified in the opcode table? */ | |
8488 | } | |
8489 | lastregno = regno; | |
8490 | continue; | |
8491 | } | |
8492 | notreg: | |
8493 | switch (*args++) | |
8494 | { | |
8495 | case 'r': | |
8496 | case 'v': | |
38487616 | 8497 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8498 | continue; |
8499 | case 'w': | |
38487616 | 8500 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8501 | continue; |
8502 | } | |
8503 | break; | |
8504 | ||
deec1734 CD |
8505 | case 'O': /* MDMX alignment immediate constant. */ |
8506 | my_getExpression (&imm_expr, s); | |
8507 | check_absolute_expr (ip, &imm_expr); | |
8508 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8509 | { | |
8510 | as_warn ("Improper align amount (%ld), using low bits", | |
8511 | (long) imm_expr.X_add_number); | |
8512 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8513 | } | |
8514 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8515 | imm_expr.X_op = O_absent; | |
8516 | s = expr_end; | |
8517 | continue; | |
8518 | ||
8519 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8520 | if (s[0] != '$') | |
8521 | { | |
8522 | /* MDMX Immediate. */ | |
8523 | my_getExpression (&imm_expr, s); | |
8524 | check_absolute_expr (ip, &imm_expr); | |
8525 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8526 | { | |
8527 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8528 | (long) imm_expr.X_add_number); | |
8529 | imm_expr.X_add_number &= OP_MASK_FT; | |
8530 | } | |
8531 | imm_expr.X_add_number &= OP_MASK_FT; | |
8532 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8533 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8534 | else | |
8535 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8536 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8537 | imm_expr.X_op = O_absent; | |
8538 | s = expr_end; | |
8539 | continue; | |
8540 | } | |
8541 | /* Not MDMX Immediate. Fall through. */ | |
8542 | case 'X': /* MDMX destination register. */ | |
8543 | case 'Y': /* MDMX source register. */ | |
8544 | case 'Z': /* MDMX target register. */ | |
8545 | is_mdmx = 1; | |
252b5132 RH |
8546 | case 'D': /* floating point destination register */ |
8547 | case 'S': /* floating point source register */ | |
8548 | case 'T': /* floating point target register */ | |
8549 | case 'R': /* floating point source register */ | |
8550 | case 'V': | |
8551 | case 'W': | |
8552 | s_reset = s; | |
deec1734 CD |
8553 | /* Accept $fN for FP and MDMX register numbers, and in |
8554 | addition accept $vN for MDMX register numbers. */ | |
8555 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8556 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8557 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8558 | { |
8559 | s += 2; | |
8560 | regno = 0; | |
8561 | do | |
8562 | { | |
8563 | regno *= 10; | |
8564 | regno += *s - '0'; | |
8565 | ++s; | |
8566 | } | |
3882b010 | 8567 | while (ISDIGIT (*s)); |
252b5132 RH |
8568 | |
8569 | if (regno > 31) | |
8570 | as_bad (_("Invalid float register number (%d)"), regno); | |
8571 | ||
8572 | if ((regno & 1) != 0 | |
ca4e0257 | 8573 | && HAVE_32BIT_FPRS |
252b5132 RH |
8574 | && ! (strcmp (str, "mtc1") == 0 |
8575 | || strcmp (str, "mfc1") == 0 | |
8576 | || strcmp (str, "lwc1") == 0 | |
8577 | || strcmp (str, "swc1") == 0 | |
8578 | || strcmp (str, "l.s") == 0 | |
8579 | || strcmp (str, "s.s") == 0)) | |
8580 | as_warn (_("Float register should be even, was %d"), | |
8581 | regno); | |
8582 | ||
8583 | c = *args; | |
8584 | if (*s == ' ') | |
f9419b05 | 8585 | ++s; |
252b5132 RH |
8586 | if (args[1] != *s) |
8587 | { | |
8588 | if (c == 'V' || c == 'W') | |
8589 | { | |
8590 | regno = lastregno; | |
8591 | s = s_reset; | |
f9419b05 | 8592 | ++args; |
252b5132 RH |
8593 | } |
8594 | } | |
8595 | switch (c) | |
8596 | { | |
8597 | case 'D': | |
deec1734 | 8598 | case 'X': |
38487616 | 8599 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8600 | break; |
8601 | case 'V': | |
8602 | case 'S': | |
deec1734 | 8603 | case 'Y': |
38487616 | 8604 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8605 | break; |
deec1734 CD |
8606 | case 'Q': |
8607 | /* This is like 'Z', but also needs to fix the MDMX | |
8608 | vector/scalar select bits. Note that the | |
8609 | scalar immediate case is handled above. */ | |
8610 | if (*s == '[') | |
8611 | { | |
8612 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8613 | int max_el = (is_qh ? 3 : 7); | |
8614 | s++; | |
8615 | my_getExpression(&imm_expr, s); | |
8616 | check_absolute_expr (ip, &imm_expr); | |
8617 | s = expr_end; | |
8618 | if (imm_expr.X_add_number > max_el) | |
8619 | as_bad(_("Bad element selector %ld"), | |
8620 | (long) imm_expr.X_add_number); | |
8621 | imm_expr.X_add_number &= max_el; | |
8622 | ip->insn_opcode |= (imm_expr.X_add_number | |
8623 | << (OP_SH_VSEL + | |
8624 | (is_qh ? 2 : 1))); | |
01a3f561 | 8625 | imm_expr.X_op = O_absent; |
deec1734 CD |
8626 | if (*s != ']') |
8627 | as_warn(_("Expecting ']' found '%s'"), s); | |
8628 | else | |
8629 | s++; | |
8630 | } | |
8631 | else | |
8632 | { | |
8633 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8634 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8635 | << OP_SH_VSEL); | |
8636 | else | |
8637 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8638 | OP_SH_VSEL); | |
8639 | } | |
8640 | /* Fall through */ | |
252b5132 RH |
8641 | case 'W': |
8642 | case 'T': | |
deec1734 | 8643 | case 'Z': |
38487616 | 8644 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8645 | break; |
8646 | case 'R': | |
38487616 | 8647 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8648 | break; |
8649 | } | |
8650 | lastregno = regno; | |
8651 | continue; | |
8652 | } | |
8653 | ||
252b5132 RH |
8654 | switch (*args++) |
8655 | { | |
8656 | case 'V': | |
38487616 | 8657 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8658 | continue; |
8659 | case 'W': | |
38487616 | 8660 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8661 | continue; |
8662 | } | |
8663 | break; | |
8664 | ||
8665 | case 'I': | |
8666 | my_getExpression (&imm_expr, s); | |
8667 | if (imm_expr.X_op != O_big | |
8668 | && imm_expr.X_op != O_constant) | |
8669 | insn_error = _("absolute expression required"); | |
13757d0c | 8670 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8671 | s = expr_end; |
8672 | continue; | |
8673 | ||
8674 | case 'A': | |
8675 | my_getExpression (&offset_expr, s); | |
f6688943 | 8676 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8677 | s = expr_end; |
8678 | continue; | |
8679 | ||
8680 | case 'F': | |
8681 | case 'L': | |
8682 | case 'f': | |
8683 | case 'l': | |
8684 | { | |
8685 | int f64; | |
ca4e0257 | 8686 | int using_gprs; |
252b5132 RH |
8687 | char *save_in; |
8688 | char *err; | |
8689 | unsigned char temp[8]; | |
8690 | int len; | |
8691 | unsigned int length; | |
8692 | segT seg; | |
8693 | subsegT subseg; | |
8694 | char *p; | |
8695 | ||
8696 | /* These only appear as the last operand in an | |
8697 | instruction, and every instruction that accepts | |
8698 | them in any variant accepts them in all variants. | |
8699 | This means we don't have to worry about backing out | |
8700 | any changes if the instruction does not match. | |
8701 | ||
8702 | The difference between them is the size of the | |
8703 | floating point constant and where it goes. For 'F' | |
8704 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8705 | is 32 bits. Where the constant is placed is based | |
8706 | on how the MIPS assembler does things: | |
8707 | F -- .rdata | |
8708 | L -- .lit8 | |
8709 | f -- immediate value | |
8710 | l -- .lit4 | |
8711 | ||
8712 | The .lit4 and .lit8 sections are only used if | |
8713 | permitted by the -G argument. | |
8714 | ||
ca4e0257 RS |
8715 | The code below needs to know whether the target register |
8716 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8717 | 'F' are used with GPR-based instructions and 'l' and | |
8718 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8719 | |
8720 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8721 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8722 | |
8723 | save_in = input_line_pointer; | |
8724 | input_line_pointer = s; | |
8725 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8726 | length = len; | |
8727 | s = input_line_pointer; | |
8728 | input_line_pointer = save_in; | |
8729 | if (err != NULL && *err != '\0') | |
8730 | { | |
8731 | as_bad (_("Bad floating point constant: %s"), err); | |
8732 | memset (temp, '\0', sizeof temp); | |
8733 | length = f64 ? 8 : 4; | |
8734 | } | |
8735 | ||
156c2f8b | 8736 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8737 | |
8738 | if (*args == 'f' | |
8739 | || (*args == 'l' | |
3e722fb5 | 8740 | && (g_switch_value < 4 |
252b5132 RH |
8741 | || (temp[0] == 0 && temp[1] == 0) |
8742 | || (temp[2] == 0 && temp[3] == 0)))) | |
8743 | { | |
8744 | imm_expr.X_op = O_constant; | |
8745 | if (! target_big_endian) | |
8746 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8747 | else | |
8748 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8749 | } | |
8750 | else if (length > 4 | |
119d663a | 8751 | && ! mips_disable_float_construction |
ca4e0257 RS |
8752 | /* Constants can only be constructed in GPRs and |
8753 | copied to FPRs if the GPRs are at least as wide | |
8754 | as the FPRs. Force the constant into memory if | |
8755 | we are using 64-bit FPRs but the GPRs are only | |
8756 | 32 bits wide. */ | |
8757 | && (using_gprs | |
8758 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8759 | && ((temp[0] == 0 && temp[1] == 0) |
8760 | || (temp[2] == 0 && temp[3] == 0)) | |
8761 | && ((temp[4] == 0 && temp[5] == 0) | |
8762 | || (temp[6] == 0 && temp[7] == 0))) | |
8763 | { | |
ca4e0257 RS |
8764 | /* The value is simple enough to load with a couple of |
8765 | instructions. If using 32-bit registers, set | |
8766 | imm_expr to the high order 32 bits and offset_expr to | |
8767 | the low order 32 bits. Otherwise, set imm_expr to | |
8768 | the entire 64 bit constant. */ | |
8769 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8770 | { |
8771 | imm_expr.X_op = O_constant; | |
8772 | offset_expr.X_op = O_constant; | |
8773 | if (! target_big_endian) | |
8774 | { | |
8775 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8776 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8777 | } | |
8778 | else | |
8779 | { | |
8780 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8781 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8782 | } | |
8783 | if (offset_expr.X_add_number == 0) | |
8784 | offset_expr.X_op = O_absent; | |
8785 | } | |
8786 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8787 | { | |
8788 | imm_expr.X_op = O_constant; | |
8789 | if (! target_big_endian) | |
8790 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8791 | else | |
8792 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8793 | } | |
8794 | else | |
8795 | { | |
8796 | imm_expr.X_op = O_big; | |
8797 | imm_expr.X_add_number = 4; | |
8798 | if (! target_big_endian) | |
8799 | { | |
8800 | generic_bignum[0] = bfd_getl16 (temp); | |
8801 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8802 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8803 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8804 | } | |
8805 | else | |
8806 | { | |
8807 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8808 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8809 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8810 | generic_bignum[3] = bfd_getb16 (temp); | |
8811 | } | |
8812 | } | |
8813 | } | |
8814 | else | |
8815 | { | |
8816 | const char *newname; | |
8817 | segT new_seg; | |
8818 | ||
8819 | /* Switch to the right section. */ | |
8820 | seg = now_seg; | |
8821 | subseg = now_subseg; | |
8822 | switch (*args) | |
8823 | { | |
8824 | default: /* unused default case avoids warnings. */ | |
8825 | case 'L': | |
8826 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8827 | if (g_switch_value >= 8) |
252b5132 RH |
8828 | newname = ".lit8"; |
8829 | break; | |
8830 | case 'F': | |
3e722fb5 | 8831 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8832 | break; |
8833 | case 'l': | |
4d0d148d | 8834 | assert (g_switch_value >= 4); |
252b5132 RH |
8835 | newname = ".lit4"; |
8836 | break; | |
8837 | } | |
8838 | new_seg = subseg_new (newname, (subsegT) 0); | |
8839 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8840 | bfd_set_section_flags (stdoutput, new_seg, | |
8841 | (SEC_ALLOC | |
8842 | | SEC_LOAD | |
8843 | | SEC_READONLY | |
8844 | | SEC_DATA)); | |
8845 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8846 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8847 | && strcmp (TARGET_OS, "elf") != 0) | |
8848 | record_alignment (new_seg, 4); | |
8849 | else | |
8850 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8851 | if (seg == now_seg) | |
8852 | as_bad (_("Can't use floating point insn in this section")); | |
8853 | ||
8854 | /* Set the argument to the current address in the | |
8855 | section. */ | |
8856 | offset_expr.X_op = O_symbol; | |
8857 | offset_expr.X_add_symbol = | |
8858 | symbol_new ("L0\001", now_seg, | |
8859 | (valueT) frag_now_fix (), frag_now); | |
8860 | offset_expr.X_add_number = 0; | |
8861 | ||
8862 | /* Put the floating point number into the section. */ | |
8863 | p = frag_more ((int) length); | |
8864 | memcpy (p, temp, length); | |
8865 | ||
8866 | /* Switch back to the original section. */ | |
8867 | subseg_set (seg, subseg); | |
8868 | } | |
8869 | } | |
8870 | continue; | |
8871 | ||
8872 | case 'i': /* 16 bit unsigned immediate */ | |
8873 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8874 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8875 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8876 | { |
8877 | int more; | |
5e0116d5 RS |
8878 | offsetT minval, maxval; |
8879 | ||
8880 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8881 | && strcmp (insn->name, insn[1].name) == 0); | |
8882 | ||
8883 | /* If the expression was written as an unsigned number, | |
8884 | only treat it as signed if there are no more | |
8885 | alternatives. */ | |
8886 | if (more | |
8887 | && *args == 'j' | |
8888 | && sizeof (imm_expr.X_add_number) <= 4 | |
8889 | && imm_expr.X_op == O_constant | |
8890 | && imm_expr.X_add_number < 0 | |
8891 | && imm_expr.X_unsigned | |
8892 | && HAVE_64BIT_GPRS) | |
8893 | break; | |
8894 | ||
8895 | /* For compatibility with older assemblers, we accept | |
8896 | 0x8000-0xffff as signed 16-bit numbers when only | |
8897 | signed numbers are allowed. */ | |
8898 | if (*args == 'i') | |
8899 | minval = 0, maxval = 0xffff; | |
8900 | else if (more) | |
8901 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8902 | else |
5e0116d5 RS |
8903 | minval = -0x8000, maxval = 0xffff; |
8904 | ||
8905 | if (imm_expr.X_op != O_constant | |
8906 | || imm_expr.X_add_number < minval | |
8907 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8908 | { |
8909 | if (more) | |
8910 | break; | |
2ae7e77b AH |
8911 | if (imm_expr.X_op == O_constant |
8912 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8913 | as_bad (_("expression out of range")); |
252b5132 RH |
8914 | } |
8915 | } | |
8916 | s = expr_end; | |
8917 | continue; | |
8918 | ||
8919 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8920 | /* Check whether there is only a single bracketed expression |
8921 | left. If so, it must be the base register and the | |
8922 | constant must be zero. */ | |
8923 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8924 | { | |
8925 | offset_expr.X_op = O_constant; | |
8926 | offset_expr.X_add_number = 0; | |
8927 | continue; | |
8928 | } | |
252b5132 RH |
8929 | |
8930 | /* If this value won't fit into a 16 bit offset, then go | |
8931 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8932 | code pattern. */ |
5e0116d5 | 8933 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8934 | && (offset_expr.X_op != O_constant |
8935 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8936 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8937 | break; |
8938 | ||
252b5132 RH |
8939 | s = expr_end; |
8940 | continue; | |
8941 | ||
8942 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8943 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8944 | my_getExpression (&offset_expr, s); |
8945 | s = expr_end; | |
8946 | continue; | |
8947 | ||
8948 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8949 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8950 | && imm_expr.X_op == O_constant | |
8951 | && (imm_expr.X_add_number < 0 | |
8952 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8953 | as_bad (_("lui expression not in range 0..65535")); |
8954 | s = expr_end; | |
8955 | continue; | |
8956 | ||
8957 | case 'a': /* 26 bit address */ | |
8958 | my_getExpression (&offset_expr, s); | |
8959 | s = expr_end; | |
f6688943 | 8960 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8961 | continue; |
8962 | ||
8963 | case 'N': /* 3 bit branch condition code */ | |
8964 | case 'M': /* 3 bit compare condition code */ | |
8965 | if (strncmp (s, "$fcc", 4) != 0) | |
8966 | break; | |
8967 | s += 4; | |
8968 | regno = 0; | |
8969 | do | |
8970 | { | |
8971 | regno *= 10; | |
8972 | regno += *s - '0'; | |
8973 | ++s; | |
8974 | } | |
3882b010 | 8975 | while (ISDIGIT (*s)); |
252b5132 | 8976 | if (regno > 7) |
30c378fd CD |
8977 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8978 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8979 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8980 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8981 | && (regno & 1) != 0) | |
8982 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8983 | str, regno); | |
8984 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8985 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8986 | && (regno & 3) != 0) | |
8987 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8988 | str, regno); | |
252b5132 RH |
8989 | if (*args == 'N') |
8990 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8991 | else | |
8992 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8993 | continue; |
252b5132 | 8994 | |
156c2f8b NC |
8995 | case 'H': |
8996 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8997 | s += 2; | |
3882b010 | 8998 | if (ISDIGIT (*s)) |
156c2f8b NC |
8999 | { |
9000 | c = 0; | |
9001 | do | |
9002 | { | |
9003 | c *= 10; | |
9004 | c += *s - '0'; | |
9005 | ++s; | |
9006 | } | |
3882b010 | 9007 | while (ISDIGIT (*s)); |
156c2f8b NC |
9008 | } |
9009 | else | |
9010 | c = 8; /* Invalid sel value. */ | |
9011 | ||
9012 | if (c > 7) | |
9013 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9014 | ip->insn_opcode |= c; | |
9015 | continue; | |
9016 | ||
60b63b72 RS |
9017 | case 'e': |
9018 | /* Must be at least one digit. */ | |
9019 | my_getExpression (&imm_expr, s); | |
9020 | check_absolute_expr (ip, &imm_expr); | |
9021 | ||
9022 | if ((unsigned long) imm_expr.X_add_number | |
9023 | > (unsigned long) OP_MASK_VECBYTE) | |
9024 | { | |
9025 | as_bad (_("bad byte vector index (%ld)"), | |
9026 | (long) imm_expr.X_add_number); | |
9027 | imm_expr.X_add_number = 0; | |
9028 | } | |
9029 | ||
9030 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9031 | imm_expr.X_op = O_absent; | |
9032 | s = expr_end; | |
9033 | continue; | |
9034 | ||
9035 | case '%': | |
9036 | my_getExpression (&imm_expr, s); | |
9037 | check_absolute_expr (ip, &imm_expr); | |
9038 | ||
9039 | if ((unsigned long) imm_expr.X_add_number | |
9040 | > (unsigned long) OP_MASK_VECALIGN) | |
9041 | { | |
9042 | as_bad (_("bad byte vector index (%ld)"), | |
9043 | (long) imm_expr.X_add_number); | |
9044 | imm_expr.X_add_number = 0; | |
9045 | } | |
9046 | ||
9047 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9048 | imm_expr.X_op = O_absent; | |
9049 | s = expr_end; | |
9050 | continue; | |
9051 | ||
252b5132 RH |
9052 | default: |
9053 | as_bad (_("bad char = '%c'\n"), *args); | |
9054 | internalError (); | |
9055 | } | |
9056 | break; | |
9057 | } | |
9058 | /* Args don't match. */ | |
9059 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9060 | !strcmp (insn->name, insn[1].name)) | |
9061 | { | |
9062 | ++insn; | |
9063 | s = argsStart; | |
268f6bed | 9064 | insn_error = _("illegal operands"); |
252b5132 RH |
9065 | continue; |
9066 | } | |
268f6bed L |
9067 | if (save_c) |
9068 | *(--s) = save_c; | |
252b5132 RH |
9069 | insn_error = _("illegal operands"); |
9070 | return; | |
9071 | } | |
9072 | } | |
9073 | ||
9074 | /* This routine assembles an instruction into its binary format when | |
9075 | assembling for the mips16. As a side effect, it sets one of the | |
9076 | global variables imm_reloc or offset_reloc to the type of | |
9077 | relocation to do if one of the operands is an address expression. | |
9078 | It also sets mips16_small and mips16_ext if the user explicitly | |
9079 | requested a small or extended instruction. */ | |
9080 | ||
9081 | static void | |
17a2f251 | 9082 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9083 | { |
9084 | char *s; | |
9085 | const char *args; | |
9086 | struct mips_opcode *insn; | |
9087 | char *argsstart; | |
9088 | unsigned int regno; | |
9089 | unsigned int lastregno = 0; | |
9090 | char *s_reset; | |
9091 | ||
9092 | insn_error = NULL; | |
9093 | ||
b34976b6 AM |
9094 | mips16_small = FALSE; |
9095 | mips16_ext = FALSE; | |
252b5132 | 9096 | |
3882b010 | 9097 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9098 | ; |
9099 | switch (*s) | |
9100 | { | |
9101 | case '\0': | |
9102 | break; | |
9103 | ||
9104 | case ' ': | |
9105 | *s++ = '\0'; | |
9106 | break; | |
9107 | ||
9108 | case '.': | |
9109 | if (s[1] == 't' && s[2] == ' ') | |
9110 | { | |
9111 | *s = '\0'; | |
b34976b6 | 9112 | mips16_small = TRUE; |
252b5132 RH |
9113 | s += 3; |
9114 | break; | |
9115 | } | |
9116 | else if (s[1] == 'e' && s[2] == ' ') | |
9117 | { | |
9118 | *s = '\0'; | |
b34976b6 | 9119 | mips16_ext = TRUE; |
252b5132 RH |
9120 | s += 3; |
9121 | break; | |
9122 | } | |
9123 | /* Fall through. */ | |
9124 | default: | |
9125 | insn_error = _("unknown opcode"); | |
9126 | return; | |
9127 | } | |
9128 | ||
9129 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9130 | mips16_small = TRUE; |
252b5132 RH |
9131 | |
9132 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9133 | { | |
9134 | insn_error = _("unrecognized opcode"); | |
9135 | return; | |
9136 | } | |
9137 | ||
9138 | argsstart = s; | |
9139 | for (;;) | |
9140 | { | |
9141 | assert (strcmp (insn->name, str) == 0); | |
9142 | ||
9143 | ip->insn_mo = insn; | |
9144 | ip->insn_opcode = insn->match; | |
b34976b6 | 9145 | ip->use_extend = FALSE; |
252b5132 | 9146 | imm_expr.X_op = O_absent; |
f6688943 TS |
9147 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9148 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9149 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9150 | imm2_expr.X_op = O_absent; |
252b5132 | 9151 | offset_expr.X_op = O_absent; |
f6688943 TS |
9152 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9153 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9154 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9155 | for (args = insn->args; 1; ++args) |
9156 | { | |
9157 | int c; | |
9158 | ||
9159 | if (*s == ' ') | |
9160 | ++s; | |
9161 | ||
9162 | /* In this switch statement we call break if we did not find | |
9163 | a match, continue if we did find a match, or return if we | |
9164 | are done. */ | |
9165 | ||
9166 | c = *args; | |
9167 | switch (c) | |
9168 | { | |
9169 | case '\0': | |
9170 | if (*s == '\0') | |
9171 | { | |
9172 | /* Stuff the immediate value in now, if we can. */ | |
9173 | if (imm_expr.X_op == O_constant | |
f6688943 | 9174 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9175 | && insn->pinfo != INSN_MACRO) |
9176 | { | |
c4e7957c | 9177 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9178 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9179 | mips16_ext, &ip->insn_opcode, |
9180 | &ip->use_extend, &ip->extend); | |
9181 | imm_expr.X_op = O_absent; | |
f6688943 | 9182 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9183 | } |
9184 | ||
9185 | return; | |
9186 | } | |
9187 | break; | |
9188 | ||
9189 | case ',': | |
9190 | if (*s++ == c) | |
9191 | continue; | |
9192 | s--; | |
9193 | switch (*++args) | |
9194 | { | |
9195 | case 'v': | |
9196 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9197 | continue; | |
9198 | case 'w': | |
9199 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9200 | continue; | |
9201 | } | |
9202 | break; | |
9203 | ||
9204 | case '(': | |
9205 | case ')': | |
9206 | if (*s++ == c) | |
9207 | continue; | |
9208 | break; | |
9209 | ||
9210 | case 'v': | |
9211 | case 'w': | |
9212 | if (s[0] != '$') | |
9213 | { | |
9214 | if (c == 'v') | |
9215 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9216 | else | |
9217 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9218 | ++args; | |
9219 | continue; | |
9220 | } | |
9221 | /* Fall through. */ | |
9222 | case 'x': | |
9223 | case 'y': | |
9224 | case 'z': | |
9225 | case 'Z': | |
9226 | case '0': | |
9227 | case 'S': | |
9228 | case 'R': | |
9229 | case 'X': | |
9230 | case 'Y': | |
9231 | if (s[0] != '$') | |
9232 | break; | |
9233 | s_reset = s; | |
3882b010 | 9234 | if (ISDIGIT (s[1])) |
252b5132 RH |
9235 | { |
9236 | ++s; | |
9237 | regno = 0; | |
9238 | do | |
9239 | { | |
9240 | regno *= 10; | |
9241 | regno += *s - '0'; | |
9242 | ++s; | |
9243 | } | |
3882b010 | 9244 | while (ISDIGIT (*s)); |
252b5132 RH |
9245 | if (regno > 31) |
9246 | { | |
9247 | as_bad (_("invalid register number (%d)"), regno); | |
9248 | regno = 2; | |
9249 | } | |
9250 | } | |
9251 | else | |
9252 | { | |
76db943d TS |
9253 | if (s[1] == 'r' && s[2] == 'a') |
9254 | { | |
9255 | s += 3; | |
9256 | regno = RA; | |
9257 | } | |
9258 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9259 | { |
9260 | s += 3; | |
9261 | regno = FP; | |
9262 | } | |
9263 | else if (s[1] == 's' && s[2] == 'p') | |
9264 | { | |
9265 | s += 3; | |
9266 | regno = SP; | |
9267 | } | |
9268 | else if (s[1] == 'g' && s[2] == 'p') | |
9269 | { | |
9270 | s += 3; | |
9271 | regno = GP; | |
9272 | } | |
9273 | else if (s[1] == 'a' && s[2] == 't') | |
9274 | { | |
9275 | s += 3; | |
9276 | regno = AT; | |
9277 | } | |
9278 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9279 | { | |
9280 | s += 4; | |
9281 | regno = KT0; | |
9282 | } | |
9283 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9284 | { | |
9285 | s += 4; | |
9286 | regno = KT1; | |
9287 | } | |
85b51719 TS |
9288 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9289 | { | |
9290 | s += 5; | |
9291 | regno = ZERO; | |
9292 | } | |
252b5132 RH |
9293 | else |
9294 | break; | |
9295 | } | |
9296 | ||
9297 | if (*s == ' ') | |
9298 | ++s; | |
9299 | if (args[1] != *s) | |
9300 | { | |
9301 | if (c == 'v' || c == 'w') | |
9302 | { | |
9303 | regno = mips16_to_32_reg_map[lastregno]; | |
9304 | s = s_reset; | |
f9419b05 | 9305 | ++args; |
252b5132 RH |
9306 | } |
9307 | } | |
9308 | ||
9309 | switch (c) | |
9310 | { | |
9311 | case 'x': | |
9312 | case 'y': | |
9313 | case 'z': | |
9314 | case 'v': | |
9315 | case 'w': | |
9316 | case 'Z': | |
9317 | regno = mips32_to_16_reg_map[regno]; | |
9318 | break; | |
9319 | ||
9320 | case '0': | |
9321 | if (regno != 0) | |
9322 | regno = ILLEGAL_REG; | |
9323 | break; | |
9324 | ||
9325 | case 'S': | |
9326 | if (regno != SP) | |
9327 | regno = ILLEGAL_REG; | |
9328 | break; | |
9329 | ||
9330 | case 'R': | |
9331 | if (regno != RA) | |
9332 | regno = ILLEGAL_REG; | |
9333 | break; | |
9334 | ||
9335 | case 'X': | |
9336 | case 'Y': | |
9337 | if (regno == AT && ! mips_opts.noat) | |
9338 | as_warn (_("used $at without \".set noat\"")); | |
9339 | break; | |
9340 | ||
9341 | default: | |
9342 | internalError (); | |
9343 | } | |
9344 | ||
9345 | if (regno == ILLEGAL_REG) | |
9346 | break; | |
9347 | ||
9348 | switch (c) | |
9349 | { | |
9350 | case 'x': | |
9351 | case 'v': | |
9352 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9353 | break; | |
9354 | case 'y': | |
9355 | case 'w': | |
9356 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9357 | break; | |
9358 | case 'z': | |
9359 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9360 | break; | |
9361 | case 'Z': | |
9362 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9363 | case '0': | |
9364 | case 'S': | |
9365 | case 'R': | |
9366 | break; | |
9367 | case 'X': | |
9368 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9369 | break; | |
9370 | case 'Y': | |
9371 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9372 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9373 | break; | |
9374 | default: | |
9375 | internalError (); | |
9376 | } | |
9377 | ||
9378 | lastregno = regno; | |
9379 | continue; | |
9380 | ||
9381 | case 'P': | |
9382 | if (strncmp (s, "$pc", 3) == 0) | |
9383 | { | |
9384 | s += 3; | |
9385 | continue; | |
9386 | } | |
9387 | break; | |
9388 | ||
9389 | case '<': | |
9390 | case '>': | |
9391 | case '[': | |
9392 | case ']': | |
9393 | case '4': | |
9394 | case '5': | |
9395 | case 'H': | |
9396 | case 'W': | |
9397 | case 'D': | |
9398 | case 'j': | |
9399 | case '8': | |
9400 | case 'V': | |
9401 | case 'C': | |
9402 | case 'U': | |
9403 | case 'k': | |
9404 | case 'K': | |
9405 | if (s[0] == '%' | |
9406 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9407 | { | |
9408 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9409 | and generate the appropriate reloc. If the text | |
9410 | inside %gprel is not a symbol name with an | |
9411 | optional offset, then we generate a normal reloc | |
9412 | and will probably fail later. */ | |
9413 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9414 | if (imm_expr.X_op == O_symbol) | |
9415 | { | |
b34976b6 | 9416 | mips16_ext = TRUE; |
f6688943 | 9417 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9418 | s = expr_end; |
b34976b6 | 9419 | ip->use_extend = TRUE; |
252b5132 RH |
9420 | ip->extend = 0; |
9421 | continue; | |
9422 | } | |
9423 | } | |
9424 | else | |
9425 | { | |
9426 | /* Just pick up a normal expression. */ | |
9427 | my_getExpression (&imm_expr, s); | |
9428 | } | |
9429 | ||
9430 | if (imm_expr.X_op == O_register) | |
9431 | { | |
9432 | /* What we thought was an expression turned out to | |
9433 | be a register. */ | |
9434 | ||
9435 | if (s[0] == '(' && args[1] == '(') | |
9436 | { | |
9437 | /* It looks like the expression was omitted | |
9438 | before a register indirection, which means | |
9439 | that the expression is implicitly zero. We | |
9440 | still set up imm_expr, so that we handle | |
9441 | explicit extensions correctly. */ | |
9442 | imm_expr.X_op = O_constant; | |
9443 | imm_expr.X_add_number = 0; | |
f6688943 | 9444 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9445 | continue; |
9446 | } | |
9447 | ||
9448 | break; | |
9449 | } | |
9450 | ||
9451 | /* We need to relax this instruction. */ | |
f6688943 | 9452 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9453 | s = expr_end; |
9454 | continue; | |
9455 | ||
9456 | case 'p': | |
9457 | case 'q': | |
9458 | case 'A': | |
9459 | case 'B': | |
9460 | case 'E': | |
9461 | /* We use offset_reloc rather than imm_reloc for the PC | |
9462 | relative operands. This lets macros with both | |
9463 | immediate and address operands work correctly. */ | |
9464 | my_getExpression (&offset_expr, s); | |
9465 | ||
9466 | if (offset_expr.X_op == O_register) | |
9467 | break; | |
9468 | ||
9469 | /* We need to relax this instruction. */ | |
f6688943 | 9470 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9471 | s = expr_end; |
9472 | continue; | |
9473 | ||
9474 | case '6': /* break code */ | |
9475 | my_getExpression (&imm_expr, s); | |
9476 | check_absolute_expr (ip, &imm_expr); | |
9477 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9478 | { | |
9479 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9480 | ip->insn_mo->name, | |
9481 | (unsigned long) imm_expr.X_add_number); | |
9482 | imm_expr.X_add_number &= 0x3f; | |
9483 | } | |
9484 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9485 | imm_expr.X_op = O_absent; | |
9486 | s = expr_end; | |
9487 | continue; | |
9488 | ||
9489 | case 'a': /* 26 bit address */ | |
9490 | my_getExpression (&offset_expr, s); | |
9491 | s = expr_end; | |
f6688943 | 9492 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9493 | ip->insn_opcode <<= 16; |
9494 | continue; | |
9495 | ||
9496 | case 'l': /* register list for entry macro */ | |
9497 | case 'L': /* register list for exit macro */ | |
9498 | { | |
9499 | int mask; | |
9500 | ||
9501 | if (c == 'l') | |
9502 | mask = 0; | |
9503 | else | |
9504 | mask = 7 << 3; | |
9505 | while (*s != '\0') | |
9506 | { | |
9507 | int freg, reg1, reg2; | |
9508 | ||
9509 | while (*s == ' ' || *s == ',') | |
9510 | ++s; | |
9511 | if (*s != '$') | |
9512 | { | |
9513 | as_bad (_("can't parse register list")); | |
9514 | break; | |
9515 | } | |
9516 | ++s; | |
9517 | if (*s != 'f') | |
9518 | freg = 0; | |
9519 | else | |
9520 | { | |
9521 | freg = 1; | |
9522 | ++s; | |
9523 | } | |
9524 | reg1 = 0; | |
3882b010 | 9525 | while (ISDIGIT (*s)) |
252b5132 RH |
9526 | { |
9527 | reg1 *= 10; | |
9528 | reg1 += *s - '0'; | |
9529 | ++s; | |
9530 | } | |
9531 | if (*s == ' ') | |
9532 | ++s; | |
9533 | if (*s != '-') | |
9534 | reg2 = reg1; | |
9535 | else | |
9536 | { | |
9537 | ++s; | |
9538 | if (*s != '$') | |
9539 | break; | |
9540 | ++s; | |
9541 | if (freg) | |
9542 | { | |
9543 | if (*s == 'f') | |
9544 | ++s; | |
9545 | else | |
9546 | { | |
9547 | as_bad (_("invalid register list")); | |
9548 | break; | |
9549 | } | |
9550 | } | |
9551 | reg2 = 0; | |
3882b010 | 9552 | while (ISDIGIT (*s)) |
252b5132 RH |
9553 | { |
9554 | reg2 *= 10; | |
9555 | reg2 += *s - '0'; | |
9556 | ++s; | |
9557 | } | |
9558 | } | |
9559 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9560 | { | |
9561 | mask &= ~ (7 << 3); | |
9562 | mask |= 5 << 3; | |
9563 | } | |
9564 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9565 | { | |
9566 | mask &= ~ (7 << 3); | |
9567 | mask |= 6 << 3; | |
9568 | } | |
9569 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9570 | mask |= (reg2 - 3) << 3; | |
9571 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9572 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9573 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9574 | mask |= 1; |
9575 | else | |
9576 | { | |
9577 | as_bad (_("invalid register list")); | |
9578 | break; | |
9579 | } | |
9580 | } | |
9581 | /* The mask is filled in in the opcode table for the | |
9582 | benefit of the disassembler. We remove it before | |
9583 | applying the actual mask. */ | |
9584 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9585 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9586 | } | |
9587 | continue; | |
9588 | ||
9589 | case 'e': /* extend code */ | |
9590 | my_getExpression (&imm_expr, s); | |
9591 | check_absolute_expr (ip, &imm_expr); | |
9592 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9593 | { | |
9594 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9595 | ip->insn_mo->name, | |
9596 | (unsigned long) imm_expr.X_add_number); | |
9597 | imm_expr.X_add_number &= 0x7ff; | |
9598 | } | |
9599 | ip->insn_opcode |= imm_expr.X_add_number; | |
9600 | imm_expr.X_op = O_absent; | |
9601 | s = expr_end; | |
9602 | continue; | |
9603 | ||
9604 | default: | |
9605 | internalError (); | |
9606 | } | |
9607 | break; | |
9608 | } | |
9609 | ||
9610 | /* Args don't match. */ | |
9611 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9612 | strcmp (insn->name, insn[1].name) == 0) | |
9613 | { | |
9614 | ++insn; | |
9615 | s = argsstart; | |
9616 | continue; | |
9617 | } | |
9618 | ||
9619 | insn_error = _("illegal operands"); | |
9620 | ||
9621 | return; | |
9622 | } | |
9623 | } | |
9624 | ||
9625 | /* This structure holds information we know about a mips16 immediate | |
9626 | argument type. */ | |
9627 | ||
e972090a NC |
9628 | struct mips16_immed_operand |
9629 | { | |
252b5132 RH |
9630 | /* The type code used in the argument string in the opcode table. */ |
9631 | int type; | |
9632 | /* The number of bits in the short form of the opcode. */ | |
9633 | int nbits; | |
9634 | /* The number of bits in the extended form of the opcode. */ | |
9635 | int extbits; | |
9636 | /* The amount by which the short form is shifted when it is used; | |
9637 | for example, the sw instruction has a shift count of 2. */ | |
9638 | int shift; | |
9639 | /* The amount by which the short form is shifted when it is stored | |
9640 | into the instruction code. */ | |
9641 | int op_shift; | |
9642 | /* Non-zero if the short form is unsigned. */ | |
9643 | int unsp; | |
9644 | /* Non-zero if the extended form is unsigned. */ | |
9645 | int extu; | |
9646 | /* Non-zero if the value is PC relative. */ | |
9647 | int pcrel; | |
9648 | }; | |
9649 | ||
9650 | /* The mips16 immediate operand types. */ | |
9651 | ||
9652 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9653 | { | |
9654 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9655 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9656 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9657 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9658 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9659 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9660 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9661 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9662 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9663 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9664 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9665 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9666 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9667 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9668 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9669 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9670 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9671 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9672 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9673 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9674 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9675 | }; | |
9676 | ||
9677 | #define MIPS16_NUM_IMMED \ | |
9678 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9679 | ||
9680 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9681 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9682 | whether an extended value is needed; if one is needed, it sets | |
9683 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9684 | If SMALL is true, an unextended opcode was explicitly requested. | |
9685 | If EXT is true, an extended opcode was explicitly requested. If | |
9686 | WARN is true, warn if EXT does not match reality. */ | |
9687 | ||
9688 | static void | |
17a2f251 TS |
9689 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9690 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9691 | unsigned long *insn, bfd_boolean *use_extend, | |
9692 | unsigned short *extend) | |
252b5132 RH |
9693 | { |
9694 | register const struct mips16_immed_operand *op; | |
9695 | int mintiny, maxtiny; | |
b34976b6 | 9696 | bfd_boolean needext; |
252b5132 RH |
9697 | |
9698 | op = mips16_immed_operands; | |
9699 | while (op->type != type) | |
9700 | { | |
9701 | ++op; | |
9702 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9703 | } | |
9704 | ||
9705 | if (op->unsp) | |
9706 | { | |
9707 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9708 | { | |
9709 | mintiny = 1; | |
9710 | maxtiny = 1 << op->nbits; | |
9711 | } | |
9712 | else | |
9713 | { | |
9714 | mintiny = 0; | |
9715 | maxtiny = (1 << op->nbits) - 1; | |
9716 | } | |
9717 | } | |
9718 | else | |
9719 | { | |
9720 | mintiny = - (1 << (op->nbits - 1)); | |
9721 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9722 | } | |
9723 | ||
9724 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9725 | if (type == 'p' || type == 'q') | |
9726 | val /= 2; | |
9727 | ||
9728 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9729 | || val < (mintiny << op->shift) | |
9730 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9731 | needext = TRUE; |
252b5132 | 9732 | else |
b34976b6 | 9733 | needext = FALSE; |
252b5132 RH |
9734 | |
9735 | if (warn && ext && ! needext) | |
beae10d5 KH |
9736 | as_warn_where (file, line, |
9737 | _("extended operand requested but not required")); | |
252b5132 RH |
9738 | if (small && needext) |
9739 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9740 | ||
9741 | if (small || (! ext && ! needext)) | |
9742 | { | |
9743 | int insnval; | |
9744 | ||
b34976b6 | 9745 | *use_extend = FALSE; |
252b5132 RH |
9746 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9747 | insnval <<= op->op_shift; | |
9748 | *insn |= insnval; | |
9749 | } | |
9750 | else | |
9751 | { | |
9752 | long minext, maxext; | |
9753 | int extval; | |
9754 | ||
9755 | if (op->extu) | |
9756 | { | |
9757 | minext = 0; | |
9758 | maxext = (1 << op->extbits) - 1; | |
9759 | } | |
9760 | else | |
9761 | { | |
9762 | minext = - (1 << (op->extbits - 1)); | |
9763 | maxext = (1 << (op->extbits - 1)) - 1; | |
9764 | } | |
9765 | if (val < minext || val > maxext) | |
9766 | as_bad_where (file, line, | |
9767 | _("operand value out of range for instruction")); | |
9768 | ||
b34976b6 | 9769 | *use_extend = TRUE; |
252b5132 RH |
9770 | if (op->extbits == 16) |
9771 | { | |
9772 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9773 | val &= 0x1f; | |
9774 | } | |
9775 | else if (op->extbits == 15) | |
9776 | { | |
9777 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9778 | val &= 0xf; | |
9779 | } | |
9780 | else | |
9781 | { | |
9782 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9783 | val = 0; | |
9784 | } | |
9785 | ||
9786 | *extend = (unsigned short) extval; | |
9787 | *insn |= val; | |
9788 | } | |
9789 | } | |
9790 | \f | |
5e0116d5 | 9791 | static const struct percent_op_match |
ad8d3bb3 | 9792 | { |
5e0116d5 RS |
9793 | const char *str; |
9794 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9795 | } percent_op[] = |
9796 | { | |
5e0116d5 | 9797 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9798 | #ifdef OBJ_ELF |
5e0116d5 RS |
9799 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9800 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9801 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9802 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9803 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9804 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9805 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9806 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9807 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9808 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9809 | {"%half", BFD_RELOC_16}, | |
9810 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9811 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9812 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9813 | #endif |
5e0116d5 | 9814 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9815 | }; |
9816 | ||
252b5132 | 9817 | |
5e0116d5 RS |
9818 | /* Return true if *STR points to a relocation operator. When returning true, |
9819 | move *STR over the operator and store its relocation code in *RELOC. | |
9820 | Leave both *STR and *RELOC alone when returning false. */ | |
9821 | ||
9822 | static bfd_boolean | |
17a2f251 | 9823 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9824 | { |
5e0116d5 | 9825 | size_t i; |
76b3015f | 9826 | |
5e0116d5 RS |
9827 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
9828 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 9829 | { |
5e0116d5 RS |
9830 | *str += strlen (percent_op[i].str); |
9831 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9832 | |
5e0116d5 RS |
9833 | /* Check whether the output BFD supports this relocation. |
9834 | If not, issue an error and fall back on something safe. */ | |
9835 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9836 | { |
5e0116d5 RS |
9837 | as_bad ("relocation %s isn't supported by the current ABI", |
9838 | percent_op[i].str); | |
01a3f561 | 9839 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9840 | } |
5e0116d5 | 9841 | return TRUE; |
394f9b3a | 9842 | } |
5e0116d5 | 9843 | return FALSE; |
394f9b3a | 9844 | } |
ad8d3bb3 | 9845 | |
ad8d3bb3 | 9846 | |
5e0116d5 RS |
9847 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9848 | expression in *EP and the relocations in the array starting | |
9849 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9850 | |
01a3f561 | 9851 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9852 | |
5e0116d5 | 9853 | static size_t |
17a2f251 TS |
9854 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9855 | char *str) | |
ad8d3bb3 | 9856 | { |
5e0116d5 RS |
9857 | bfd_reloc_code_real_type reversed_reloc[3]; |
9858 | size_t reloc_index, i; | |
09b8f35a RS |
9859 | int crux_depth, str_depth; |
9860 | char *crux; | |
5e0116d5 RS |
9861 | |
9862 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9863 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9864 | of the main expression and with CRUX_DEPTH containing the number | |
9865 | of open brackets at that point. */ | |
9866 | reloc_index = -1; | |
9867 | str_depth = 0; | |
9868 | do | |
fb1b3232 | 9869 | { |
09b8f35a RS |
9870 | reloc_index++; |
9871 | crux = str; | |
9872 | crux_depth = str_depth; | |
9873 | ||
9874 | /* Skip over whitespace and brackets, keeping count of the number | |
9875 | of brackets. */ | |
9876 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9877 | if (*str++ == '(') | |
9878 | str_depth++; | |
5e0116d5 | 9879 | } |
09b8f35a RS |
9880 | while (*str == '%' |
9881 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9882 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9883 | |
09b8f35a | 9884 | my_getExpression (ep, crux); |
5e0116d5 | 9885 | str = expr_end; |
394f9b3a | 9886 | |
5e0116d5 | 9887 | /* Match every open bracket. */ |
09b8f35a | 9888 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9889 | if (*str++ == ')') |
09b8f35a | 9890 | crux_depth--; |
394f9b3a | 9891 | |
09b8f35a | 9892 | if (crux_depth > 0) |
5e0116d5 | 9893 | as_bad ("unclosed '('"); |
394f9b3a | 9894 | |
5e0116d5 | 9895 | expr_end = str; |
252b5132 | 9896 | |
01a3f561 | 9897 | if (reloc_index != 0) |
64bdfcaf RS |
9898 | { |
9899 | prev_reloc_op_frag = frag_now; | |
9900 | for (i = 0; i < reloc_index; i++) | |
9901 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9902 | } | |
fb1b3232 | 9903 | |
5e0116d5 | 9904 | return reloc_index; |
252b5132 RH |
9905 | } |
9906 | ||
9907 | static void | |
17a2f251 | 9908 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9909 | { |
9910 | char *save_in; | |
98aa84af | 9911 | valueT val; |
252b5132 RH |
9912 | |
9913 | save_in = input_line_pointer; | |
9914 | input_line_pointer = str; | |
9915 | expression (ep); | |
9916 | expr_end = input_line_pointer; | |
9917 | input_line_pointer = save_in; | |
9918 | ||
9919 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9920 | then we bump the value of the symbol by 1 since that is how other | |
9921 | text symbols are handled. We don't bother to handle complex | |
9922 | expressions, just `.' plus or minus a constant. */ | |
9923 | if (mips_opts.mips16 | |
9924 | && ep->X_op == O_symbol | |
9925 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9926 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9927 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9928 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9929 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9930 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9931 | } |
9932 | ||
9933 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9934 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9935 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9936 | returned, or NULL on OK. */ |
9937 | ||
9938 | char * | |
17a2f251 | 9939 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9940 | { |
9941 | int prec; | |
9942 | LITTLENUM_TYPE words[4]; | |
9943 | char *t; | |
9944 | int i; | |
9945 | ||
9946 | switch (type) | |
9947 | { | |
9948 | case 'f': | |
9949 | prec = 2; | |
9950 | break; | |
9951 | ||
9952 | case 'd': | |
9953 | prec = 4; | |
9954 | break; | |
9955 | ||
9956 | default: | |
9957 | *sizeP = 0; | |
9958 | return _("bad call to md_atof"); | |
9959 | } | |
9960 | ||
9961 | t = atof_ieee (input_line_pointer, type, words); | |
9962 | if (t) | |
9963 | input_line_pointer = t; | |
9964 | ||
9965 | *sizeP = prec * 2; | |
9966 | ||
9967 | if (! target_big_endian) | |
9968 | { | |
9969 | for (i = prec - 1; i >= 0; i--) | |
9970 | { | |
17a2f251 | 9971 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9972 | litP += 2; |
9973 | } | |
9974 | } | |
9975 | else | |
9976 | { | |
9977 | for (i = 0; i < prec; i++) | |
9978 | { | |
17a2f251 | 9979 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9980 | litP += 2; |
9981 | } | |
9982 | } | |
bdaaa2e1 | 9983 | |
252b5132 RH |
9984 | return NULL; |
9985 | } | |
9986 | ||
9987 | void | |
17a2f251 | 9988 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9989 | { |
9990 | if (target_big_endian) | |
9991 | number_to_chars_bigendian (buf, val, n); | |
9992 | else | |
9993 | number_to_chars_littleendian (buf, val, n); | |
9994 | } | |
9995 | \f | |
ae948b86 | 9996 | #ifdef OBJ_ELF |
e013f690 TS |
9997 | static int support_64bit_objects(void) |
9998 | { | |
9999 | const char **list, **l; | |
aa3d8fdf | 10000 | int yes; |
e013f690 TS |
10001 | |
10002 | list = bfd_target_list (); | |
10003 | for (l = list; *l != NULL; l++) | |
10004 | #ifdef TE_TMIPS | |
10005 | /* This is traditional mips */ | |
10006 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10007 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10008 | #else | |
10009 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10010 | || strcmp (*l, "elf64-littlemips") == 0) | |
10011 | #endif | |
10012 | break; | |
aa3d8fdf | 10013 | yes = (*l != NULL); |
e013f690 | 10014 | free (list); |
aa3d8fdf | 10015 | return yes; |
e013f690 | 10016 | } |
ae948b86 | 10017 | #endif /* OBJ_ELF */ |
e013f690 | 10018 | |
78849248 | 10019 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10020 | |
e972090a NC |
10021 | struct option md_longopts[] = |
10022 | { | |
f9b4148d CD |
10023 | /* Options which specify architecture. */ |
10024 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10025 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10026 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10027 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10028 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10029 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10030 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10031 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10032 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10033 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10034 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10035 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10036 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10037 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10038 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10039 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10040 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10041 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10042 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10043 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10044 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10045 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10046 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10047 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10048 | |
10049 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10050 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10051 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10052 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10053 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10054 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10055 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10056 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10057 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10058 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10059 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10060 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10061 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10062 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10063 | ||
10064 | /* Old-style architecture options. Don't add more of these. */ | |
10065 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10066 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10067 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10068 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10069 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10070 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10071 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10072 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10073 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10074 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10075 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10076 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10077 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10078 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10079 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10080 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10081 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10082 | ||
10083 | /* Options which enable bug fixes. */ | |
10084 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10085 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10086 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10087 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10088 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10089 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10090 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10091 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10092 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10093 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10094 | |
10095 | /* Miscellaneous options. */ | |
10096 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10097 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10098 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10099 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10100 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10101 | {"break", no_argument, NULL, OPTION_BREAK}, |
10102 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10103 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10104 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10105 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10106 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10107 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10108 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10109 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10110 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10111 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10112 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10113 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10114 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10115 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10116 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10117 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10118 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10119 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10120 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10121 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10122 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10123 | |
10124 | /* ELF-specific options. */ | |
156c2f8b | 10125 | #ifdef OBJ_ELF |
1ffcab4b | 10126 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12) |
156c2f8b | 10127 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10128 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10129 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10130 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10131 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10132 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10133 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10134 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10135 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10136 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10137 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10138 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10139 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10140 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10141 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10142 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10143 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10144 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10145 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10146 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10147 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10148 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10149 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10150 | #endif /* OBJ_ELF */ |
f9b4148d | 10151 | |
252b5132 RH |
10152 | {NULL, no_argument, NULL, 0} |
10153 | }; | |
156c2f8b | 10154 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10155 | |
316f5878 RS |
10156 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10157 | NEW_VALUE. Warn if another value was already specified. Note: | |
10158 | we have to defer parsing the -march and -mtune arguments in order | |
10159 | to handle 'from-abi' correctly, since the ABI might be specified | |
10160 | in a later argument. */ | |
10161 | ||
10162 | static void | |
17a2f251 | 10163 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10164 | { |
10165 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10166 | as_warn (_("A different %s was already specified, is now %s"), | |
10167 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10168 | new_value); | |
10169 | ||
10170 | *string_ptr = new_value; | |
10171 | } | |
10172 | ||
252b5132 | 10173 | int |
17a2f251 | 10174 | md_parse_option (int c, char *arg) |
252b5132 RH |
10175 | { |
10176 | switch (c) | |
10177 | { | |
119d663a NC |
10178 | case OPTION_CONSTRUCT_FLOATS: |
10179 | mips_disable_float_construction = 0; | |
10180 | break; | |
bdaaa2e1 | 10181 | |
119d663a NC |
10182 | case OPTION_NO_CONSTRUCT_FLOATS: |
10183 | mips_disable_float_construction = 1; | |
10184 | break; | |
bdaaa2e1 | 10185 | |
252b5132 RH |
10186 | case OPTION_TRAP: |
10187 | mips_trap = 1; | |
10188 | break; | |
10189 | ||
10190 | case OPTION_BREAK: | |
10191 | mips_trap = 0; | |
10192 | break; | |
10193 | ||
10194 | case OPTION_EB: | |
10195 | target_big_endian = 1; | |
10196 | break; | |
10197 | ||
10198 | case OPTION_EL: | |
10199 | target_big_endian = 0; | |
10200 | break; | |
10201 | ||
10202 | case 'O': | |
10203 | if (arg && arg[1] == '0') | |
10204 | mips_optimize = 1; | |
10205 | else | |
10206 | mips_optimize = 2; | |
10207 | break; | |
10208 | ||
10209 | case 'g': | |
10210 | if (arg == NULL) | |
10211 | mips_debug = 2; | |
10212 | else | |
10213 | mips_debug = atoi (arg); | |
10214 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10215 | optimizations which limit full symbolic debugging. We take | |
10216 | that to be equivalent to -O0. */ | |
10217 | if (mips_debug == 2) | |
10218 | mips_optimize = 1; | |
10219 | break; | |
10220 | ||
10221 | case OPTION_MIPS1: | |
316f5878 | 10222 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10223 | break; |
10224 | ||
10225 | case OPTION_MIPS2: | |
316f5878 | 10226 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10227 | break; |
10228 | ||
10229 | case OPTION_MIPS3: | |
316f5878 | 10230 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10231 | break; |
10232 | ||
10233 | case OPTION_MIPS4: | |
316f5878 | 10234 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10235 | break; |
10236 | ||
84ea6cf2 | 10237 | case OPTION_MIPS5: |
316f5878 | 10238 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10239 | break; |
10240 | ||
e7af610e | 10241 | case OPTION_MIPS32: |
316f5878 | 10242 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10243 | break; |
10244 | ||
af7ee8bf CD |
10245 | case OPTION_MIPS32R2: |
10246 | file_mips_isa = ISA_MIPS32R2; | |
10247 | break; | |
10248 | ||
5f74bc13 CD |
10249 | case OPTION_MIPS64R2: |
10250 | file_mips_isa = ISA_MIPS64R2; | |
10251 | break; | |
10252 | ||
84ea6cf2 | 10253 | case OPTION_MIPS64: |
316f5878 | 10254 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10255 | break; |
10256 | ||
ec68c924 | 10257 | case OPTION_MTUNE: |
316f5878 RS |
10258 | mips_set_option_string (&mips_tune_string, arg); |
10259 | break; | |
ec68c924 | 10260 | |
316f5878 RS |
10261 | case OPTION_MARCH: |
10262 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10263 | break; |
10264 | ||
10265 | case OPTION_M4650: | |
316f5878 RS |
10266 | mips_set_option_string (&mips_arch_string, "4650"); |
10267 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10268 | break; |
10269 | ||
10270 | case OPTION_NO_M4650: | |
10271 | break; | |
10272 | ||
10273 | case OPTION_M4010: | |
316f5878 RS |
10274 | mips_set_option_string (&mips_arch_string, "4010"); |
10275 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10276 | break; |
10277 | ||
10278 | case OPTION_NO_M4010: | |
10279 | break; | |
10280 | ||
10281 | case OPTION_M4100: | |
316f5878 RS |
10282 | mips_set_option_string (&mips_arch_string, "4100"); |
10283 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10284 | break; |
10285 | ||
10286 | case OPTION_NO_M4100: | |
10287 | break; | |
10288 | ||
252b5132 | 10289 | case OPTION_M3900: |
316f5878 RS |
10290 | mips_set_option_string (&mips_arch_string, "3900"); |
10291 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10292 | break; |
bdaaa2e1 | 10293 | |
252b5132 RH |
10294 | case OPTION_NO_M3900: |
10295 | break; | |
10296 | ||
deec1734 CD |
10297 | case OPTION_MDMX: |
10298 | mips_opts.ase_mdmx = 1; | |
10299 | break; | |
10300 | ||
10301 | case OPTION_NO_MDMX: | |
10302 | mips_opts.ase_mdmx = 0; | |
10303 | break; | |
10304 | ||
252b5132 RH |
10305 | case OPTION_MIPS16: |
10306 | mips_opts.mips16 = 1; | |
b34976b6 | 10307 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10308 | break; |
10309 | ||
10310 | case OPTION_NO_MIPS16: | |
10311 | mips_opts.mips16 = 0; | |
b34976b6 | 10312 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10313 | break; |
10314 | ||
1f25f5d3 CD |
10315 | case OPTION_MIPS3D: |
10316 | mips_opts.ase_mips3d = 1; | |
10317 | break; | |
10318 | ||
10319 | case OPTION_NO_MIPS3D: | |
10320 | mips_opts.ase_mips3d = 0; | |
10321 | break; | |
10322 | ||
d766e8ec RS |
10323 | case OPTION_FIX_VR4120: |
10324 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10325 | break; |
10326 | ||
d766e8ec RS |
10327 | case OPTION_NO_FIX_VR4120: |
10328 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10329 | break; |
10330 | ||
4a6a3df4 AO |
10331 | case OPTION_RELAX_BRANCH: |
10332 | mips_relax_branch = 1; | |
10333 | break; | |
10334 | ||
10335 | case OPTION_NO_RELAX_BRANCH: | |
10336 | mips_relax_branch = 0; | |
10337 | break; | |
10338 | ||
0f074f60 | 10339 | #ifdef OBJ_ELF |
252b5132 RH |
10340 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10341 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10342 | intended to be compatible with Irix 5. */ | |
10343 | case OPTION_CALL_SHARED: | |
10344 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10345 | { | |
10346 | as_bad (_("-call_shared is supported only for ELF format")); | |
10347 | return 0; | |
10348 | } | |
10349 | mips_pic = SVR4_PIC; | |
143d77c5 | 10350 | mips_abicalls = TRUE; |
252b5132 RH |
10351 | if (g_switch_seen && g_switch_value != 0) |
10352 | { | |
10353 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10354 | return 0; | |
10355 | } | |
10356 | g_switch_value = 0; | |
10357 | break; | |
10358 | ||
10359 | case OPTION_NON_SHARED: | |
10360 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10361 | { | |
10362 | as_bad (_("-non_shared is supported only for ELF format")); | |
10363 | return 0; | |
10364 | } | |
10365 | mips_pic = NO_PIC; | |
143d77c5 | 10366 | mips_abicalls = FALSE; |
252b5132 RH |
10367 | break; |
10368 | ||
10369 | /* The -xgot option tells the assembler to use 32 offsets when | |
10370 | accessing the got in SVR4_PIC mode. It is for Irix | |
10371 | compatibility. */ | |
10372 | case OPTION_XGOT: | |
10373 | mips_big_got = 1; | |
10374 | break; | |
0f074f60 | 10375 | #endif /* OBJ_ELF */ |
252b5132 RH |
10376 | |
10377 | case 'G': | |
3e722fb5 | 10378 | if (mips_pic == SVR4_PIC) |
252b5132 | 10379 | { |
3e722fb5 | 10380 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10381 | return 0; |
10382 | } | |
10383 | else | |
10384 | g_switch_value = atoi (arg); | |
10385 | g_switch_seen = 1; | |
10386 | break; | |
10387 | ||
0f074f60 | 10388 | #ifdef OBJ_ELF |
34ba82a8 TS |
10389 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10390 | and -mabi=64. */ | |
252b5132 | 10391 | case OPTION_32: |
34ba82a8 TS |
10392 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10393 | { | |
10394 | as_bad (_("-32 is supported for ELF format only")); | |
10395 | return 0; | |
10396 | } | |
316f5878 | 10397 | mips_abi = O32_ABI; |
252b5132 RH |
10398 | break; |
10399 | ||
e013f690 | 10400 | case OPTION_N32: |
34ba82a8 TS |
10401 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10402 | { | |
10403 | as_bad (_("-n32 is supported for ELF format only")); | |
10404 | return 0; | |
10405 | } | |
316f5878 | 10406 | mips_abi = N32_ABI; |
e013f690 | 10407 | break; |
252b5132 | 10408 | |
e013f690 | 10409 | case OPTION_64: |
34ba82a8 TS |
10410 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10411 | { | |
10412 | as_bad (_("-64 is supported for ELF format only")); | |
10413 | return 0; | |
10414 | } | |
316f5878 | 10415 | mips_abi = N64_ABI; |
e013f690 TS |
10416 | if (! support_64bit_objects()) |
10417 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10418 | break; |
ae948b86 | 10419 | #endif /* OBJ_ELF */ |
252b5132 | 10420 | |
c97ef257 | 10421 | case OPTION_GP32: |
a325df1d | 10422 | file_mips_gp32 = 1; |
c97ef257 AH |
10423 | break; |
10424 | ||
10425 | case OPTION_GP64: | |
a325df1d | 10426 | file_mips_gp32 = 0; |
c97ef257 | 10427 | break; |
252b5132 | 10428 | |
ca4e0257 | 10429 | case OPTION_FP32: |
a325df1d | 10430 | file_mips_fp32 = 1; |
316f5878 RS |
10431 | break; |
10432 | ||
10433 | case OPTION_FP64: | |
10434 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10435 | break; |
10436 | ||
ae948b86 | 10437 | #ifdef OBJ_ELF |
252b5132 | 10438 | case OPTION_MABI: |
34ba82a8 TS |
10439 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10440 | { | |
10441 | as_bad (_("-mabi is supported for ELF format only")); | |
10442 | return 0; | |
10443 | } | |
e013f690 | 10444 | if (strcmp (arg, "32") == 0) |
316f5878 | 10445 | mips_abi = O32_ABI; |
e013f690 | 10446 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10447 | mips_abi = O64_ABI; |
e013f690 | 10448 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10449 | mips_abi = N32_ABI; |
e013f690 TS |
10450 | else if (strcmp (arg, "64") == 0) |
10451 | { | |
316f5878 | 10452 | mips_abi = N64_ABI; |
e013f690 TS |
10453 | if (! support_64bit_objects()) |
10454 | as_fatal (_("No compiled in support for 64 bit object file " | |
10455 | "format")); | |
10456 | } | |
10457 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10458 | mips_abi = EABI_ABI; |
e013f690 | 10459 | else |
da0e507f TS |
10460 | { |
10461 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10462 | return 0; | |
10463 | } | |
252b5132 | 10464 | break; |
e013f690 | 10465 | #endif /* OBJ_ELF */ |
252b5132 | 10466 | |
6b76fefe | 10467 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10468 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10469 | break; |
10470 | ||
9ee72ff1 | 10471 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10472 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10473 | break; |
10474 | ||
ecb4347a DJ |
10475 | #ifdef OBJ_ELF |
10476 | case OPTION_MDEBUG: | |
b34976b6 | 10477 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10478 | break; |
10479 | ||
10480 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10481 | mips_flag_mdebug = FALSE; |
ecb4347a | 10482 | break; |
dcd410fe RO |
10483 | |
10484 | case OPTION_PDR: | |
10485 | mips_flag_pdr = TRUE; | |
10486 | break; | |
10487 | ||
10488 | case OPTION_NO_PDR: | |
10489 | mips_flag_pdr = FALSE; | |
10490 | break; | |
ecb4347a DJ |
10491 | #endif /* OBJ_ELF */ |
10492 | ||
252b5132 RH |
10493 | default: |
10494 | return 0; | |
10495 | } | |
10496 | ||
10497 | return 1; | |
10498 | } | |
316f5878 RS |
10499 | \f |
10500 | /* Set up globals to generate code for the ISA or processor | |
10501 | described by INFO. */ | |
252b5132 | 10502 | |
252b5132 | 10503 | static void |
17a2f251 | 10504 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10505 | { |
316f5878 | 10506 | if (info != 0) |
252b5132 | 10507 | { |
fef14a42 TS |
10508 | file_mips_arch = info->cpu; |
10509 | mips_opts.arch = info->cpu; | |
316f5878 | 10510 | mips_opts.isa = info->isa; |
252b5132 | 10511 | } |
252b5132 RH |
10512 | } |
10513 | ||
252b5132 | 10514 | |
316f5878 | 10515 | /* Likewise for tuning. */ |
252b5132 | 10516 | |
316f5878 | 10517 | static void |
17a2f251 | 10518 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10519 | { |
10520 | if (info != 0) | |
fef14a42 | 10521 | mips_tune = info->cpu; |
316f5878 | 10522 | } |
80cc45a5 | 10523 | |
34ba82a8 | 10524 | |
252b5132 | 10525 | void |
17a2f251 | 10526 | mips_after_parse_args (void) |
e9670677 | 10527 | { |
fef14a42 TS |
10528 | const struct mips_cpu_info *arch_info = 0; |
10529 | const struct mips_cpu_info *tune_info = 0; | |
10530 | ||
e9670677 MR |
10531 | /* GP relative stuff not working for PE */ |
10532 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10533 | && g_switch_value != 0) | |
10534 | { | |
10535 | if (g_switch_seen) | |
10536 | as_bad (_("-G not supported in this configuration.")); | |
10537 | g_switch_value = 0; | |
10538 | } | |
10539 | ||
cac012d6 AO |
10540 | if (mips_abi == NO_ABI) |
10541 | mips_abi = MIPS_DEFAULT_ABI; | |
10542 | ||
22923709 RS |
10543 | /* The following code determines the architecture and register size. |
10544 | Similar code was added to GCC 3.3 (see override_options() in | |
10545 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10546 | as much as possible. */ | |
e9670677 | 10547 | |
316f5878 | 10548 | if (mips_arch_string != 0) |
fef14a42 | 10549 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10550 | |
316f5878 | 10551 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10552 | { |
316f5878 | 10553 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10554 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10555 | the -march selection (if any). */ |
fef14a42 | 10556 | if (arch_info != 0) |
e9670677 | 10557 | { |
316f5878 RS |
10558 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10559 | There's no harm in specifying both as long as the ISA levels | |
10560 | are the same. */ | |
fef14a42 | 10561 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10562 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10563 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10564 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10565 | } |
316f5878 | 10566 | else |
fef14a42 | 10567 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10568 | } |
10569 | ||
fef14a42 TS |
10570 | if (arch_info == 0) |
10571 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10572 | |
fef14a42 | 10573 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10574 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10575 | arch_info->name); |
10576 | ||
10577 | mips_set_architecture (arch_info); | |
10578 | ||
10579 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10580 | if (mips_tune_string != 0) | |
10581 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10582 | |
fef14a42 TS |
10583 | if (tune_info == 0) |
10584 | mips_set_tune (arch_info); | |
10585 | else | |
10586 | mips_set_tune (tune_info); | |
e9670677 | 10587 | |
316f5878 | 10588 | if (file_mips_gp32 >= 0) |
e9670677 | 10589 | { |
316f5878 RS |
10590 | /* The user specified the size of the integer registers. Make sure |
10591 | it agrees with the ABI and ISA. */ | |
10592 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10593 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10594 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10595 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10596 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10597 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10598 | } |
10599 | else | |
10600 | { | |
316f5878 RS |
10601 | /* Infer the integer register size from the ABI and processor. |
10602 | Restrict ourselves to 32-bit registers if that's all the | |
10603 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10604 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10605 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10606 | } |
10607 | ||
316f5878 RS |
10608 | /* ??? GAS treats single-float processors as though they had 64-bit |
10609 | float registers (although it complains when double-precision | |
10610 | instructions are used). As things stand, saying they have 32-bit | |
10611 | registers would lead to spurious "register must be even" messages. | |
10612 | So here we assume float registers are always the same size as | |
10613 | integer ones, unless the user says otherwise. */ | |
10614 | if (file_mips_fp32 < 0) | |
10615 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10616 | |
316f5878 | 10617 | /* End of GCC-shared inference code. */ |
e9670677 | 10618 | |
17a2f251 TS |
10619 | /* This flag is set when we have a 64-bit capable CPU but use only |
10620 | 32-bit wide registers. Note that EABI does not use it. */ | |
10621 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10622 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10623 | || mips_abi == O32_ABI)) | |
316f5878 | 10624 | mips_32bitmode = 1; |
e9670677 MR |
10625 | |
10626 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10627 | as_bad (_("trap exception not supported at ISA 1")); | |
10628 | ||
e9670677 MR |
10629 | /* If the selected architecture includes support for ASEs, enable |
10630 | generation of code for them. */ | |
a4672219 | 10631 | if (mips_opts.mips16 == -1) |
fef14a42 | 10632 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10633 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10634 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10635 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10636 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10637 | |
e9670677 | 10638 | file_mips_isa = mips_opts.isa; |
a4672219 | 10639 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10640 | file_ase_mips3d = mips_opts.ase_mips3d; |
10641 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10642 | mips_opts.gp32 = file_mips_gp32; | |
10643 | mips_opts.fp32 = file_mips_fp32; | |
10644 | ||
ecb4347a DJ |
10645 | if (mips_flag_mdebug < 0) |
10646 | { | |
10647 | #ifdef OBJ_MAYBE_ECOFF | |
10648 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10649 | mips_flag_mdebug = 1; | |
10650 | else | |
10651 | #endif /* OBJ_MAYBE_ECOFF */ | |
10652 | mips_flag_mdebug = 0; | |
10653 | } | |
e9670677 MR |
10654 | } |
10655 | \f | |
10656 | void | |
17a2f251 | 10657 | mips_init_after_args (void) |
252b5132 RH |
10658 | { |
10659 | /* initialize opcodes */ | |
10660 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10661 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10662 | } |
10663 | ||
10664 | long | |
17a2f251 | 10665 | md_pcrel_from (fixS *fixP) |
252b5132 | 10666 | { |
a7ebbfdf TS |
10667 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10668 | switch (fixP->fx_r_type) | |
10669 | { | |
10670 | case BFD_RELOC_16_PCREL_S2: | |
10671 | case BFD_RELOC_MIPS_JMP: | |
10672 | /* Return the address of the delay slot. */ | |
10673 | return addr + 4; | |
10674 | default: | |
10675 | return addr; | |
10676 | } | |
252b5132 RH |
10677 | } |
10678 | ||
252b5132 RH |
10679 | /* This is called before the symbol table is processed. In order to |
10680 | work with gcc when using mips-tfile, we must keep all local labels. | |
10681 | However, in other cases, we want to discard them. If we were | |
10682 | called with -g, but we didn't see any debugging information, it may | |
10683 | mean that gcc is smuggling debugging information through to | |
10684 | mips-tfile, in which case we must generate all local labels. */ | |
10685 | ||
10686 | void | |
17a2f251 | 10687 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10688 | { |
10689 | #ifndef NO_ECOFF_DEBUGGING | |
10690 | if (ECOFF_DEBUGGING | |
10691 | && mips_debug != 0 | |
10692 | && ! ecoff_debugging_seen) | |
10693 | flag_keep_locals = 1; | |
10694 | #endif | |
10695 | } | |
10696 | ||
3b91255e RS |
10697 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10698 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10699 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10700 | relocation operators. | |
10701 | ||
10702 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10703 | expression if: | |
10704 | ||
10705 | (a) it refers to the same symbol; and | |
10706 | (b) the offset applied in the %lo() expression is no lower than | |
10707 | the offset applied in the %got() or %hi(). | |
10708 | ||
10709 | (b) allows us to cope with code like: | |
10710 | ||
10711 | lui $4,%hi(foo) | |
10712 | lh $4,%lo(foo+2)($4) | |
10713 | ||
10714 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10715 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10716 | the high 16 bits. | |
10717 | ||
10718 | When several %lo()s match a particular %got() or %hi(), we use the | |
10719 | following rules to distinguish them: | |
10720 | ||
10721 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10722 | higher offsets. | |
10723 | ||
10724 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10725 | that already have a matching %got() or %hi(). | |
10726 | ||
10727 | (3) later %lo()s are better than earlier %lo()s. | |
10728 | ||
10729 | These rules are applied in order. | |
10730 | ||
10731 | (1) means, among other things, that %lo()s with identical offsets are | |
10732 | chosen if they exist. | |
10733 | ||
10734 | (2) means that we won't associate several high-part relocations with | |
10735 | the same low-part relocation unless there's no alternative. Having | |
10736 | several high parts for the same low part is a GNU extension; this rule | |
10737 | allows careful users to avoid it. | |
10738 | ||
10739 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10740 | with the last high-part relocation being at the front of the list. | |
10741 | It therefore makes sense to choose the last matching low-part | |
10742 | relocation, all other things being equal. It's also easier | |
10743 | to code that way. */ | |
252b5132 RH |
10744 | |
10745 | void | |
17a2f251 | 10746 | mips_frob_file (void) |
252b5132 RH |
10747 | { |
10748 | struct mips_hi_fixup *l; | |
10749 | ||
10750 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10751 | { | |
10752 | segment_info_type *seginfo; | |
3b91255e RS |
10753 | bfd_boolean matched_lo_p; |
10754 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10755 | |
5919d012 | 10756 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10757 | |
5919d012 RS |
10758 | /* If a GOT16 relocation turns out to be against a global symbol, |
10759 | there isn't supposed to be a matching LO. */ | |
10760 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10761 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10762 | continue; | |
10763 | ||
10764 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10765 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10766 | continue; |
10767 | ||
252b5132 | 10768 | seginfo = seg_info (l->seg); |
252b5132 | 10769 | |
3b91255e RS |
10770 | /* Set HI_POS to the position of this relocation in the chain. |
10771 | Set LO_POS to the position of the chosen low-part relocation. | |
10772 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10773 | relocation that matches an immediately-preceding high-part | |
10774 | relocation. */ | |
10775 | hi_pos = NULL; | |
10776 | lo_pos = NULL; | |
10777 | matched_lo_p = FALSE; | |
10778 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10779 | { | |
10780 | if (*pos == l->fixp) | |
10781 | hi_pos = pos; | |
10782 | ||
10783 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10784 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10785 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10786 | && (lo_pos == NULL | |
10787 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10788 | || (!matched_lo_p | |
10789 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10790 | lo_pos = pos; | |
10791 | ||
10792 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10793 | && fixup_has_matching_lo_p (*pos)); | |
10794 | } | |
10795 | ||
10796 | /* If we found a match, remove the high-part relocation from its | |
10797 | current position and insert it before the low-part relocation. | |
10798 | Make the offsets match so that fixup_has_matching_lo_p() | |
10799 | will return true. | |
10800 | ||
10801 | We don't warn about unmatched high-part relocations since some | |
10802 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10803 | instructions. */ | |
10804 | if (lo_pos != NULL) | |
10805 | { | |
10806 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10807 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10808 | { |
3b91255e RS |
10809 | *hi_pos = l->fixp->fx_next; |
10810 | l->fixp->fx_next = *lo_pos; | |
10811 | *lo_pos = l->fixp; | |
252b5132 | 10812 | } |
252b5132 RH |
10813 | } |
10814 | } | |
10815 | } | |
10816 | ||
3e722fb5 | 10817 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10818 | We have to prevent gas from dropping them. */ |
252b5132 | 10819 | |
252b5132 | 10820 | int |
17a2f251 | 10821 | mips_force_relocation (fixS *fixp) |
252b5132 | 10822 | { |
ae6063d4 | 10823 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10824 | return 1; |
10825 | ||
f6688943 TS |
10826 | if (HAVE_NEWABI |
10827 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10828 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10829 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10830 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10831 | return 1; | |
10832 | ||
3e722fb5 | 10833 | return 0; |
252b5132 RH |
10834 | } |
10835 | ||
45f8dfe8 AO |
10836 | /* This hook is called before a fix is simplified. We don't really |
10837 | decide whether to skip a fix here. Rather, we turn global symbols | |
10838 | used as branch targets into local symbols, such that they undergo | |
10839 | simplification. We can only do this if the symbol is defined and | |
10840 | it is in the same section as the branch. If this doesn't hold, we | |
10841 | emit a better error message than just saying the relocation is not | |
10842 | valid for the selected object format. | |
10843 | ||
10844 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10845 | segment in which the fix up occurs. The return value should be | |
10846 | non-zero to indicate the fix-up is valid for further | |
10847 | simplifications. */ | |
10848 | ||
10849 | int | |
17a2f251 | 10850 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10851 | { |
10852 | /* There's a lot of discussion on whether it should be possible to | |
10853 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10854 | seems to be that it can, but gas/bfd are very broken in creating | |
10855 | RELA relocations for this, so for now we only accept branches to | |
10856 | symbols in the same section. Anything else is of dubious value, | |
10857 | since there's no guarantee that at link time the symbol would be | |
10858 | in range. Even for branches to local symbols this is arguably | |
10859 | wrong, since it we assume the symbol is not going to be | |
10860 | overridden, which should be possible per ELF library semantics, | |
10861 | but then, there isn't a dynamic relocation that could be used to | |
10862 | this effect, and the target would likely be out of range as well. | |
10863 | ||
10864 | Unfortunately, it seems that there is too much code out there | |
10865 | that relies on branches to symbols that are global to be resolved | |
10866 | as if they were local, like the IRIX tools do, so we do it as | |
10867 | well, but with a warning so that people are reminded to fix their | |
10868 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10869 | targets, this entire block should go away (and probably the | |
10870 | whole function). */ | |
10871 | ||
10872 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10873 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10874 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10875 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10876 | && fixP->fx_addsy) | |
10877 | { | |
10878 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10879 | { | |
10880 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10881 | _("Cannot branch to undefined symbol.")); | |
10882 | /* Avoid any further errors about this fixup. */ | |
10883 | fixP->fx_done = 1; | |
10884 | } | |
10885 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10886 | { | |
10887 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10888 | _("Cannot branch to symbol in another section.")); | |
10889 | fixP->fx_done = 1; | |
10890 | } | |
10891 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10892 | { | |
10893 | symbolS *sym = fixP->fx_addsy; | |
10894 | ||
115695a8 CD |
10895 | if (mips_pic == SVR4_PIC) |
10896 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10897 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10898 | |
10899 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10900 | S_GET_SEGMENT (sym), | |
10901 | S_GET_VALUE (sym), | |
10902 | symbol_get_frag (sym)); | |
10903 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10904 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10905 | assert (symbol_resolved_p (sym)); | |
10906 | symbol_mark_resolved (fixP->fx_addsy); | |
10907 | } | |
10908 | } | |
10909 | ||
10910 | return 1; | |
10911 | } | |
10912 | ||
252b5132 RH |
10913 | /* Apply a fixup to the object file. */ |
10914 | ||
94f592af | 10915 | void |
17a2f251 | 10916 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10917 | { |
874e8986 | 10918 | bfd_byte *buf; |
98aa84af | 10919 | long insn; |
a7ebbfdf | 10920 | reloc_howto_type *howto; |
252b5132 | 10921 | |
a7ebbfdf TS |
10922 | /* We ignore generic BFD relocations we don't know about. */ |
10923 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10924 | if (! howto) | |
10925 | return; | |
65551fa4 | 10926 | |
252b5132 RH |
10927 | assert (fixP->fx_size == 4 |
10928 | || fixP->fx_r_type == BFD_RELOC_16 | |
10929 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10930 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10931 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10932 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10933 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10934 | |
a7ebbfdf | 10935 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10936 | |
3e722fb5 | 10937 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10938 | |
10939 | /* Don't treat parts of a composite relocation as done. There are two | |
10940 | reasons for this: | |
10941 | ||
10942 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
10943 | should nevertheless be emitted if the first part is. | |
10944 | ||
10945 | (2) In normal usage, composite relocations are never assembly-time | |
10946 | constants. The easiest way of dealing with the pathological | |
10947 | exceptions is to generate a relocation against STN_UNDEF and | |
10948 | leave everything up to the linker. */ | |
10949 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
10950 | fixP->fx_done = 1; |
10951 | ||
10952 | switch (fixP->fx_r_type) | |
10953 | { | |
10954 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10955 | case BFD_RELOC_MIPS_SHIFT5: |
10956 | case BFD_RELOC_MIPS_SHIFT6: | |
10957 | case BFD_RELOC_MIPS_GOT_DISP: | |
10958 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10959 | case BFD_RELOC_MIPS_GOT_OFST: | |
10960 | case BFD_RELOC_MIPS_SUB: | |
10961 | case BFD_RELOC_MIPS_INSERT_A: | |
10962 | case BFD_RELOC_MIPS_INSERT_B: | |
10963 | case BFD_RELOC_MIPS_DELETE: | |
10964 | case BFD_RELOC_MIPS_HIGHEST: | |
10965 | case BFD_RELOC_MIPS_HIGHER: | |
10966 | case BFD_RELOC_MIPS_SCN_DISP: | |
10967 | case BFD_RELOC_MIPS_REL16: | |
10968 | case BFD_RELOC_MIPS_RELGOT: | |
10969 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10970 | case BFD_RELOC_HI16: |
10971 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10972 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10973 | case BFD_RELOC_MIPS_LITERAL: |
10974 | case BFD_RELOC_MIPS_CALL16: | |
10975 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10976 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10977 | case BFD_RELOC_MIPS_GOT_HI16: |
10978 | case BFD_RELOC_MIPS_GOT_LO16: | |
10979 | case BFD_RELOC_MIPS_CALL_HI16: | |
10980 | case BFD_RELOC_MIPS_CALL_LO16: | |
10981 | case BFD_RELOC_MIPS16_GPREL: | |
3e722fb5 | 10982 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10983 | /* Nothing needed to do. The value comes from the reloc entry */ |
10984 | break; | |
10985 | ||
10986 | case BFD_RELOC_MIPS16_JMP: | |
10987 | /* We currently always generate a reloc against a symbol, which | |
10988 | means that we don't want an addend even if the symbol is | |
10989 | defined. */ | |
a7ebbfdf | 10990 | *valP = 0; |
252b5132 RH |
10991 | break; |
10992 | ||
252b5132 RH |
10993 | case BFD_RELOC_64: |
10994 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10995 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10996 | if (fixP->fx_done) |
252b5132 RH |
10997 | { |
10998 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 10999 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11000 | else |
11001 | { | |
a7ebbfdf | 11002 | valueT hiv; |
252b5132 | 11003 | |
a7ebbfdf | 11004 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11005 | hiv = 0xffffffff; |
11006 | else | |
11007 | hiv = 0; | |
a7ebbfdf TS |
11008 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11009 | *valP, 4); | |
11010 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11011 | hiv, 4); | |
252b5132 RH |
11012 | } |
11013 | } | |
11014 | break; | |
11015 | ||
056350c6 | 11016 | case BFD_RELOC_RVA: |
252b5132 RH |
11017 | case BFD_RELOC_32: |
11018 | /* If we are deleting this reloc entry, we must fill in the | |
11019 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11020 | resolved when it appears but is later defined. */ |
11021 | if (fixP->fx_done) | |
a7ebbfdf | 11022 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11023 | break; |
11024 | ||
11025 | case BFD_RELOC_16: | |
11026 | /* If we are deleting this reloc entry, we must fill in the | |
11027 | value now. */ | |
252b5132 | 11028 | if (fixP->fx_done) |
a7ebbfdf | 11029 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11030 | break; |
11031 | ||
11032 | case BFD_RELOC_LO16: | |
3e722fb5 CD |
11033 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11034 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11035 | /* When handling an embedded PIC switch statement, we can wind |
11036 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11037 | if (fixP->fx_done) | |
11038 | { | |
a7ebbfdf | 11039 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11040 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11041 | _("relocation overflow")); | |
252b5132 RH |
11042 | if (target_big_endian) |
11043 | buf += 2; | |
17a2f251 | 11044 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11045 | } |
11046 | break; | |
11047 | ||
11048 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11049 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11050 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11051 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11052 | |
252b5132 RH |
11053 | /* |
11054 | * We need to save the bits in the instruction since fixup_segment() | |
11055 | * might be deleting the relocation entry (i.e., a branch within | |
11056 | * the current segment). | |
11057 | */ | |
a7ebbfdf | 11058 | if (! fixP->fx_done) |
bb2d6cd7 | 11059 | break; |
252b5132 RH |
11060 | |
11061 | /* update old instruction data */ | |
252b5132 RH |
11062 | if (target_big_endian) |
11063 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11064 | else | |
11065 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11066 | ||
a7ebbfdf TS |
11067 | if (*valP + 0x20000 <= 0x3ffff) |
11068 | { | |
11069 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11070 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11071 | } |
11072 | else if (mips_pic == NO_PIC | |
11073 | && fixP->fx_done | |
11074 | && fixP->fx_frag->fr_address >= text_section->vma | |
11075 | && (fixP->fx_frag->fr_address | |
587aac4e | 11076 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11077 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11078 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11079 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11080 | { |
11081 | /* The branch offset is too large. If this is an | |
11082 | unconditional branch, and we are not generating PIC code, | |
11083 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11084 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11085 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11086 | else |
a7ebbfdf TS |
11087 | insn = 0x08000000; /* j */ |
11088 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11089 | fixP->fx_done = 0; | |
11090 | fixP->fx_addsy = section_symbol (text_section); | |
11091 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11092 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11093 | } |
11094 | else | |
11095 | { | |
11096 | /* If we got here, we have branch-relaxation disabled, | |
11097 | and there's nothing we can do to fix this instruction | |
11098 | without turning it into a longer sequence. */ | |
11099 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11100 | _("Branch out of range")); | |
252b5132 | 11101 | } |
252b5132 RH |
11102 | break; |
11103 | ||
11104 | case BFD_RELOC_VTABLE_INHERIT: | |
11105 | fixP->fx_done = 0; | |
11106 | if (fixP->fx_addsy | |
11107 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11108 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11109 | S_SET_WEAK (fixP->fx_addsy); | |
11110 | break; | |
11111 | ||
11112 | case BFD_RELOC_VTABLE_ENTRY: | |
11113 | fixP->fx_done = 0; | |
11114 | break; | |
11115 | ||
11116 | default: | |
11117 | internalError (); | |
11118 | } | |
a7ebbfdf TS |
11119 | |
11120 | /* Remember value for tc_gen_reloc. */ | |
11121 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11122 | } |
11123 | ||
11124 | #if 0 | |
11125 | void | |
17a2f251 | 11126 | printInsn (unsigned long oc) |
252b5132 RH |
11127 | { |
11128 | const struct mips_opcode *p; | |
11129 | int treg, sreg, dreg, shamt; | |
11130 | short imm; | |
11131 | const char *args; | |
11132 | int i; | |
11133 | ||
11134 | for (i = 0; i < NUMOPCODES; ++i) | |
11135 | { | |
11136 | p = &mips_opcodes[i]; | |
11137 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11138 | { | |
11139 | printf ("%08lx %s\t", oc, p->name); | |
11140 | treg = (oc >> 16) & 0x1f; | |
11141 | sreg = (oc >> 21) & 0x1f; | |
11142 | dreg = (oc >> 11) & 0x1f; | |
11143 | shamt = (oc >> 6) & 0x1f; | |
11144 | imm = oc; | |
11145 | for (args = p->args;; ++args) | |
11146 | { | |
11147 | switch (*args) | |
11148 | { | |
11149 | case '\0': | |
11150 | printf ("\n"); | |
11151 | break; | |
11152 | ||
11153 | case ',': | |
11154 | case '(': | |
11155 | case ')': | |
11156 | printf ("%c", *args); | |
11157 | continue; | |
11158 | ||
11159 | case 'r': | |
11160 | assert (treg == sreg); | |
11161 | printf ("$%d,$%d", treg, sreg); | |
11162 | continue; | |
11163 | ||
11164 | case 'd': | |
11165 | case 'G': | |
11166 | printf ("$%d", dreg); | |
11167 | continue; | |
11168 | ||
11169 | case 't': | |
11170 | case 'E': | |
11171 | printf ("$%d", treg); | |
11172 | continue; | |
11173 | ||
11174 | case 'k': | |
11175 | printf ("0x%x", treg); | |
11176 | continue; | |
11177 | ||
11178 | case 'b': | |
11179 | case 's': | |
11180 | printf ("$%d", sreg); | |
11181 | continue; | |
11182 | ||
11183 | case 'a': | |
11184 | printf ("0x%08lx", oc & 0x1ffffff); | |
11185 | continue; | |
11186 | ||
11187 | case 'i': | |
11188 | case 'j': | |
11189 | case 'o': | |
11190 | case 'u': | |
11191 | printf ("%d", imm); | |
11192 | continue; | |
11193 | ||
11194 | case '<': | |
11195 | case '>': | |
11196 | printf ("$%d", shamt); | |
11197 | continue; | |
11198 | ||
11199 | default: | |
11200 | internalError (); | |
11201 | } | |
11202 | break; | |
11203 | } | |
11204 | return; | |
11205 | } | |
11206 | } | |
11207 | printf (_("%08lx UNDEFINED\n"), oc); | |
11208 | } | |
11209 | #endif | |
11210 | ||
11211 | static symbolS * | |
17a2f251 | 11212 | get_symbol (void) |
252b5132 RH |
11213 | { |
11214 | int c; | |
11215 | char *name; | |
11216 | symbolS *p; | |
11217 | ||
11218 | name = input_line_pointer; | |
11219 | c = get_symbol_end (); | |
11220 | p = (symbolS *) symbol_find_or_make (name); | |
11221 | *input_line_pointer = c; | |
11222 | return p; | |
11223 | } | |
11224 | ||
11225 | /* Align the current frag to a given power of two. The MIPS assembler | |
11226 | also automatically adjusts any preceding label. */ | |
11227 | ||
11228 | static void | |
17a2f251 | 11229 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11230 | { |
b34976b6 | 11231 | mips_emit_delays (FALSE); |
252b5132 RH |
11232 | frag_align (to, fill, 0); |
11233 | record_alignment (now_seg, to); | |
11234 | if (label != NULL) | |
11235 | { | |
11236 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11237 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11238 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11239 | } | |
11240 | } | |
11241 | ||
11242 | /* Align to a given power of two. .align 0 turns off the automatic | |
11243 | alignment used by the data creating pseudo-ops. */ | |
11244 | ||
11245 | static void | |
17a2f251 | 11246 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11247 | { |
11248 | register int temp; | |
11249 | register long temp_fill; | |
11250 | long max_alignment = 15; | |
11251 | ||
11252 | /* | |
11253 | ||
67c1ffbe | 11254 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11255 | to the aligned address. |
11256 | o It's not documented but auto alignment is reinstated by | |
11257 | a .align pseudo instruction. | |
11258 | o Note also that after auto alignment is turned off the mips assembler | |
11259 | issues an error on attempt to assemble an improperly aligned data item. | |
11260 | We don't. | |
11261 | ||
11262 | */ | |
11263 | ||
11264 | temp = get_absolute_expression (); | |
11265 | if (temp > max_alignment) | |
11266 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11267 | else if (temp < 0) | |
11268 | { | |
11269 | as_warn (_("Alignment negative: 0 assumed.")); | |
11270 | temp = 0; | |
11271 | } | |
11272 | if (*input_line_pointer == ',') | |
11273 | { | |
f9419b05 | 11274 | ++input_line_pointer; |
252b5132 RH |
11275 | temp_fill = get_absolute_expression (); |
11276 | } | |
11277 | else | |
11278 | temp_fill = 0; | |
11279 | if (temp) | |
11280 | { | |
11281 | auto_align = 1; | |
11282 | mips_align (temp, (int) temp_fill, | |
11283 | insn_labels != NULL ? insn_labels->label : NULL); | |
11284 | } | |
11285 | else | |
11286 | { | |
11287 | auto_align = 0; | |
11288 | } | |
11289 | ||
11290 | demand_empty_rest_of_line (); | |
11291 | } | |
11292 | ||
11293 | void | |
17a2f251 | 11294 | mips_flush_pending_output (void) |
252b5132 | 11295 | { |
b34976b6 | 11296 | mips_emit_delays (FALSE); |
252b5132 RH |
11297 | mips_clear_insn_labels (); |
11298 | } | |
11299 | ||
11300 | static void | |
17a2f251 | 11301 | s_change_sec (int sec) |
252b5132 RH |
11302 | { |
11303 | segT seg; | |
11304 | ||
252b5132 RH |
11305 | #ifdef OBJ_ELF |
11306 | /* The ELF backend needs to know that we are changing sections, so | |
11307 | that .previous works correctly. We could do something like check | |
b6ff326e | 11308 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11309 | as it would not be appropriate to use it in the section changing |
11310 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11311 | This should be cleaner, somehow. */ | |
11312 | obj_elf_section_change_hook (); | |
11313 | #endif | |
11314 | ||
b34976b6 | 11315 | mips_emit_delays (FALSE); |
252b5132 RH |
11316 | switch (sec) |
11317 | { | |
11318 | case 't': | |
11319 | s_text (0); | |
11320 | break; | |
11321 | case 'd': | |
11322 | s_data (0); | |
11323 | break; | |
11324 | case 'b': | |
11325 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11326 | demand_empty_rest_of_line (); | |
11327 | break; | |
11328 | ||
11329 | case 'r': | |
4d0d148d TS |
11330 | seg = subseg_new (RDATA_SECTION_NAME, |
11331 | (subsegT) get_absolute_expression ()); | |
11332 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11333 | { |
4d0d148d TS |
11334 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11335 | | SEC_READONLY | SEC_RELOC | |
11336 | | SEC_DATA)); | |
11337 | if (strcmp (TARGET_OS, "elf") != 0) | |
11338 | record_alignment (seg, 4); | |
252b5132 | 11339 | } |
4d0d148d | 11340 | demand_empty_rest_of_line (); |
252b5132 RH |
11341 | break; |
11342 | ||
11343 | case 's': | |
4d0d148d TS |
11344 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11345 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11346 | { |
4d0d148d TS |
11347 | bfd_set_section_flags (stdoutput, seg, |
11348 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11349 | if (strcmp (TARGET_OS, "elf") != 0) | |
11350 | record_alignment (seg, 4); | |
252b5132 | 11351 | } |
4d0d148d TS |
11352 | demand_empty_rest_of_line (); |
11353 | break; | |
252b5132 RH |
11354 | } |
11355 | ||
11356 | auto_align = 1; | |
11357 | } | |
b34976b6 | 11358 | |
cca86cc8 | 11359 | void |
17a2f251 | 11360 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11361 | { |
7ed4a06a | 11362 | #ifdef OBJ_ELF |
cca86cc8 SC |
11363 | char *section_name; |
11364 | char c; | |
684022ea | 11365 | char next_c = 0; |
cca86cc8 SC |
11366 | int section_type; |
11367 | int section_flag; | |
11368 | int section_entry_size; | |
11369 | int section_alignment; | |
b34976b6 | 11370 | |
7ed4a06a TS |
11371 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11372 | return; | |
11373 | ||
cca86cc8 SC |
11374 | section_name = input_line_pointer; |
11375 | c = get_symbol_end (); | |
a816d1ed AO |
11376 | if (c) |
11377 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11378 | |
4cf0dd0d TS |
11379 | /* Do we have .section Name<,"flags">? */ |
11380 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11381 | { |
4cf0dd0d TS |
11382 | /* just after name is now '\0'. */ |
11383 | *input_line_pointer = c; | |
cca86cc8 SC |
11384 | input_line_pointer = section_name; |
11385 | obj_elf_section (ignore); | |
11386 | return; | |
11387 | } | |
11388 | input_line_pointer++; | |
11389 | ||
11390 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11391 | if (c == ',') | |
11392 | section_type = get_absolute_expression (); | |
11393 | else | |
11394 | section_type = 0; | |
11395 | if (*input_line_pointer++ == ',') | |
11396 | section_flag = get_absolute_expression (); | |
11397 | else | |
11398 | section_flag = 0; | |
11399 | if (*input_line_pointer++ == ',') | |
11400 | section_entry_size = get_absolute_expression (); | |
11401 | else | |
11402 | section_entry_size = 0; | |
11403 | if (*input_line_pointer++ == ',') | |
11404 | section_alignment = get_absolute_expression (); | |
11405 | else | |
11406 | section_alignment = 0; | |
11407 | ||
a816d1ed AO |
11408 | section_name = xstrdup (section_name); |
11409 | ||
8ab8a5c8 RS |
11410 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11411 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11412 | traditionally had to fall back on the more common @progbits instead. | |
11413 | ||
11414 | There's nothing really harmful in this, since bfd will correct | |
11415 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11416 | means that, for backwards compatibiltiy, the special_section entries | |
11417 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11418 | ||
11419 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11420 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11421 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11422 | generic type-checking code. */ | |
11423 | if (section_type == SHT_MIPS_DWARF) | |
11424 | section_type = SHT_PROGBITS; | |
11425 | ||
cca86cc8 SC |
11426 | obj_elf_change_section (section_name, section_type, section_flag, |
11427 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11428 | |
11429 | if (now_seg->name != section_name) | |
11430 | free (section_name); | |
7ed4a06a | 11431 | #endif /* OBJ_ELF */ |
cca86cc8 | 11432 | } |
252b5132 RH |
11433 | |
11434 | void | |
17a2f251 | 11435 | mips_enable_auto_align (void) |
252b5132 RH |
11436 | { |
11437 | auto_align = 1; | |
11438 | } | |
11439 | ||
11440 | static void | |
17a2f251 | 11441 | s_cons (int log_size) |
252b5132 RH |
11442 | { |
11443 | symbolS *label; | |
11444 | ||
11445 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11446 | mips_emit_delays (FALSE); |
252b5132 RH |
11447 | if (log_size > 0 && auto_align) |
11448 | mips_align (log_size, 0, label); | |
11449 | mips_clear_insn_labels (); | |
11450 | cons (1 << log_size); | |
11451 | } | |
11452 | ||
11453 | static void | |
17a2f251 | 11454 | s_float_cons (int type) |
252b5132 RH |
11455 | { |
11456 | symbolS *label; | |
11457 | ||
11458 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11459 | ||
b34976b6 | 11460 | mips_emit_delays (FALSE); |
252b5132 RH |
11461 | |
11462 | if (auto_align) | |
49309057 ILT |
11463 | { |
11464 | if (type == 'd') | |
11465 | mips_align (3, 0, label); | |
11466 | else | |
11467 | mips_align (2, 0, label); | |
11468 | } | |
252b5132 RH |
11469 | |
11470 | mips_clear_insn_labels (); | |
11471 | ||
11472 | float_cons (type); | |
11473 | } | |
11474 | ||
11475 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11476 | permitted to say | |
11477 | .globl foo .text | |
11478 | where foo is an undefined symbol, to mean that foo should be | |
11479 | considered to be the address of a function. */ | |
11480 | ||
11481 | static void | |
17a2f251 | 11482 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11483 | { |
11484 | char *name; | |
11485 | int c; | |
11486 | symbolS *symbolP; | |
11487 | flagword flag; | |
11488 | ||
11489 | name = input_line_pointer; | |
11490 | c = get_symbol_end (); | |
11491 | symbolP = symbol_find_or_make (name); | |
11492 | *input_line_pointer = c; | |
11493 | SKIP_WHITESPACE (); | |
11494 | ||
11495 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11496 | being a function is apparently labelled as being an object. */ | |
11497 | flag = BSF_OBJECT; | |
11498 | ||
11499 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11500 | { | |
11501 | char *secname; | |
11502 | asection *sec; | |
11503 | ||
11504 | secname = input_line_pointer; | |
11505 | c = get_symbol_end (); | |
11506 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11507 | if (sec == NULL) | |
11508 | as_bad (_("%s: no such section"), secname); | |
11509 | *input_line_pointer = c; | |
11510 | ||
11511 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11512 | flag = BSF_FUNCTION; | |
11513 | } | |
11514 | ||
49309057 | 11515 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11516 | |
11517 | S_SET_EXTERNAL (symbolP); | |
11518 | demand_empty_rest_of_line (); | |
11519 | } | |
11520 | ||
11521 | static void | |
17a2f251 | 11522 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11523 | { |
11524 | char *opt; | |
11525 | char c; | |
11526 | ||
11527 | opt = input_line_pointer; | |
11528 | c = get_symbol_end (); | |
11529 | ||
11530 | if (*opt == 'O') | |
11531 | { | |
11532 | /* FIXME: What does this mean? */ | |
11533 | } | |
11534 | else if (strncmp (opt, "pic", 3) == 0) | |
11535 | { | |
11536 | int i; | |
11537 | ||
11538 | i = atoi (opt + 3); | |
11539 | if (i == 0) | |
11540 | mips_pic = NO_PIC; | |
11541 | else if (i == 2) | |
143d77c5 | 11542 | { |
252b5132 | 11543 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11544 | mips_abicalls = TRUE; |
11545 | } | |
252b5132 RH |
11546 | else |
11547 | as_bad (_(".option pic%d not supported"), i); | |
11548 | ||
4d0d148d | 11549 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11550 | { |
11551 | if (g_switch_seen && g_switch_value != 0) | |
11552 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11553 | g_switch_value = 0; | |
11554 | bfd_set_gp_size (stdoutput, 0); | |
11555 | } | |
11556 | } | |
11557 | else | |
11558 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11559 | ||
11560 | *input_line_pointer = c; | |
11561 | demand_empty_rest_of_line (); | |
11562 | } | |
11563 | ||
11564 | /* This structure is used to hold a stack of .set values. */ | |
11565 | ||
e972090a NC |
11566 | struct mips_option_stack |
11567 | { | |
252b5132 RH |
11568 | struct mips_option_stack *next; |
11569 | struct mips_set_options options; | |
11570 | }; | |
11571 | ||
11572 | static struct mips_option_stack *mips_opts_stack; | |
11573 | ||
11574 | /* Handle the .set pseudo-op. */ | |
11575 | ||
11576 | static void | |
17a2f251 | 11577 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11578 | { |
11579 | char *name = input_line_pointer, ch; | |
11580 | ||
11581 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11582 | ++input_line_pointer; |
252b5132 RH |
11583 | ch = *input_line_pointer; |
11584 | *input_line_pointer = '\0'; | |
11585 | ||
11586 | if (strcmp (name, "reorder") == 0) | |
11587 | { | |
11588 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11589 | { | |
11590 | /* If we still have pending nops, we can discard them. The | |
11591 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11592 | needed. */ |
252b5132 RH |
11593 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11594 | * (mips_opts.mips16 ? 2 : 4)); | |
11595 | prev_nop_frag = NULL; | |
11596 | } | |
11597 | mips_opts.noreorder = 0; | |
11598 | } | |
11599 | else if (strcmp (name, "noreorder") == 0) | |
11600 | { | |
b34976b6 | 11601 | mips_emit_delays (TRUE); |
252b5132 RH |
11602 | mips_opts.noreorder = 1; |
11603 | mips_any_noreorder = 1; | |
11604 | } | |
11605 | else if (strcmp (name, "at") == 0) | |
11606 | { | |
11607 | mips_opts.noat = 0; | |
11608 | } | |
11609 | else if (strcmp (name, "noat") == 0) | |
11610 | { | |
11611 | mips_opts.noat = 1; | |
11612 | } | |
11613 | else if (strcmp (name, "macro") == 0) | |
11614 | { | |
11615 | mips_opts.warn_about_macros = 0; | |
11616 | } | |
11617 | else if (strcmp (name, "nomacro") == 0) | |
11618 | { | |
11619 | if (mips_opts.noreorder == 0) | |
11620 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11621 | mips_opts.warn_about_macros = 1; | |
11622 | } | |
11623 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11624 | { | |
11625 | mips_opts.nomove = 0; | |
11626 | } | |
11627 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11628 | { | |
11629 | mips_opts.nomove = 1; | |
11630 | } | |
11631 | else if (strcmp (name, "bopt") == 0) | |
11632 | { | |
11633 | mips_opts.nobopt = 0; | |
11634 | } | |
11635 | else if (strcmp (name, "nobopt") == 0) | |
11636 | { | |
11637 | mips_opts.nobopt = 1; | |
11638 | } | |
11639 | else if (strcmp (name, "mips16") == 0 | |
11640 | || strcmp (name, "MIPS-16") == 0) | |
11641 | mips_opts.mips16 = 1; | |
11642 | else if (strcmp (name, "nomips16") == 0 | |
11643 | || strcmp (name, "noMIPS-16") == 0) | |
11644 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11645 | else if (strcmp (name, "mips3d") == 0) |
11646 | mips_opts.ase_mips3d = 1; | |
11647 | else if (strcmp (name, "nomips3d") == 0) | |
11648 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11649 | else if (strcmp (name, "mdmx") == 0) |
11650 | mips_opts.ase_mdmx = 1; | |
11651 | else if (strcmp (name, "nomdmx") == 0) | |
11652 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11653 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11654 | { |
af7ee8bf | 11655 | int reset = 0; |
252b5132 | 11656 | |
1a2c1fad CD |
11657 | /* Permit the user to change the ISA and architecture on the fly. |
11658 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11659 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11660 | { |
11661 | reset = 1; | |
11662 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11663 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11664 | } |
11665 | else if (strncmp (name, "arch=", 5) == 0) | |
11666 | { | |
11667 | const struct mips_cpu_info *p; | |
11668 | ||
11669 | p = mips_parse_cpu("internal use", name + 5); | |
11670 | if (!p) | |
11671 | as_bad (_("unknown architecture %s"), name + 5); | |
11672 | else | |
11673 | { | |
11674 | mips_opts.arch = p->cpu; | |
11675 | mips_opts.isa = p->isa; | |
11676 | } | |
11677 | } | |
81a21e38 TS |
11678 | else if (strncmp (name, "mips", 4) == 0) |
11679 | { | |
11680 | const struct mips_cpu_info *p; | |
11681 | ||
11682 | p = mips_parse_cpu("internal use", name); | |
11683 | if (!p) | |
11684 | as_bad (_("unknown ISA level %s"), name + 4); | |
11685 | else | |
11686 | { | |
11687 | mips_opts.arch = p->cpu; | |
11688 | mips_opts.isa = p->isa; | |
11689 | } | |
11690 | } | |
af7ee8bf | 11691 | else |
81a21e38 | 11692 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11693 | |
11694 | switch (mips_opts.isa) | |
98d3f06f KH |
11695 | { |
11696 | case 0: | |
98d3f06f | 11697 | break; |
af7ee8bf CD |
11698 | case ISA_MIPS1: |
11699 | case ISA_MIPS2: | |
11700 | case ISA_MIPS32: | |
11701 | case ISA_MIPS32R2: | |
98d3f06f KH |
11702 | mips_opts.gp32 = 1; |
11703 | mips_opts.fp32 = 1; | |
11704 | break; | |
af7ee8bf CD |
11705 | case ISA_MIPS3: |
11706 | case ISA_MIPS4: | |
11707 | case ISA_MIPS5: | |
11708 | case ISA_MIPS64: | |
5f74bc13 | 11709 | case ISA_MIPS64R2: |
98d3f06f KH |
11710 | mips_opts.gp32 = 0; |
11711 | mips_opts.fp32 = 0; | |
11712 | break; | |
11713 | default: | |
11714 | as_bad (_("unknown ISA level %s"), name + 4); | |
11715 | break; | |
11716 | } | |
af7ee8bf | 11717 | if (reset) |
98d3f06f | 11718 | { |
af7ee8bf CD |
11719 | mips_opts.gp32 = file_mips_gp32; |
11720 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11721 | } |
252b5132 RH |
11722 | } |
11723 | else if (strcmp (name, "autoextend") == 0) | |
11724 | mips_opts.noautoextend = 0; | |
11725 | else if (strcmp (name, "noautoextend") == 0) | |
11726 | mips_opts.noautoextend = 1; | |
11727 | else if (strcmp (name, "push") == 0) | |
11728 | { | |
11729 | struct mips_option_stack *s; | |
11730 | ||
11731 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11732 | s->next = mips_opts_stack; | |
11733 | s->options = mips_opts; | |
11734 | mips_opts_stack = s; | |
11735 | } | |
11736 | else if (strcmp (name, "pop") == 0) | |
11737 | { | |
11738 | struct mips_option_stack *s; | |
11739 | ||
11740 | s = mips_opts_stack; | |
11741 | if (s == NULL) | |
11742 | as_bad (_(".set pop with no .set push")); | |
11743 | else | |
11744 | { | |
11745 | /* If we're changing the reorder mode we need to handle | |
11746 | delay slots correctly. */ | |
11747 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11748 | mips_emit_delays (TRUE); |
252b5132 RH |
11749 | else if (! s->options.noreorder && mips_opts.noreorder) |
11750 | { | |
11751 | if (prev_nop_frag != NULL) | |
11752 | { | |
11753 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11754 | * (mips_opts.mips16 ? 2 : 4)); | |
11755 | prev_nop_frag = NULL; | |
11756 | } | |
11757 | } | |
11758 | ||
11759 | mips_opts = s->options; | |
11760 | mips_opts_stack = s->next; | |
11761 | free (s); | |
11762 | } | |
11763 | } | |
11764 | else | |
11765 | { | |
11766 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11767 | } | |
11768 | *input_line_pointer = ch; | |
11769 | demand_empty_rest_of_line (); | |
11770 | } | |
11771 | ||
11772 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11773 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11774 | ||
11775 | static void | |
17a2f251 | 11776 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11777 | { |
11778 | mips_pic = SVR4_PIC; | |
143d77c5 | 11779 | mips_abicalls = TRUE; |
4d0d148d TS |
11780 | |
11781 | if (g_switch_seen && g_switch_value != 0) | |
11782 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11783 | g_switch_value = 0; | |
11784 | ||
252b5132 RH |
11785 | bfd_set_gp_size (stdoutput, 0); |
11786 | demand_empty_rest_of_line (); | |
11787 | } | |
11788 | ||
11789 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11790 | PIC code. It sets the $gp register for the function based on the | |
11791 | function address, which is in the register named in the argument. | |
11792 | This uses a relocation against _gp_disp, which is handled specially | |
11793 | by the linker. The result is: | |
11794 | lui $gp,%hi(_gp_disp) | |
11795 | addiu $gp,$gp,%lo(_gp_disp) | |
11796 | addu $gp,$gp,.cpload argument | |
11797 | The .cpload argument is normally $25 == $t9. */ | |
11798 | ||
11799 | static void | |
17a2f251 | 11800 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11801 | { |
11802 | expressionS ex; | |
252b5132 | 11803 | |
6478892d TS |
11804 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11805 | .cpload is ignored. */ | |
11806 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11807 | { |
11808 | s_ignore (0); | |
11809 | return; | |
11810 | } | |
11811 | ||
d3ecfc59 | 11812 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11813 | if (mips_opts.noreorder == 0) |
11814 | as_warn (_(".cpload not in noreorder section")); | |
11815 | ||
11816 | ex.X_op = O_symbol; | |
11817 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11818 | ex.X_op_symbol = NULL; | |
11819 | ex.X_add_number = 0; | |
11820 | ||
11821 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11822 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11823 | |
584892a6 | 11824 | macro_start (); |
67c0d1eb RS |
11825 | macro_build_lui (&ex, mips_gp_register); |
11826 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11827 | mips_gp_register, BFD_RELOC_LO16); |
67c0d1eb | 11828 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
17a2f251 | 11829 | mips_gp_register, tc_get_register (0)); |
584892a6 | 11830 | macro_end (); |
252b5132 RH |
11831 | |
11832 | demand_empty_rest_of_line (); | |
11833 | } | |
11834 | ||
6478892d TS |
11835 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11836 | .cpsetup $reg1, offset|$reg2, label | |
11837 | ||
11838 | If offset is given, this results in: | |
11839 | sd $gp, offset($sp) | |
956cd1d6 | 11840 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11841 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11842 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11843 | |
11844 | If $reg2 is given, this results in: | |
11845 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11846 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11847 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11848 | daddu $gp, $gp, $reg1 | |
11849 | $reg1 is normally $25 == $t9. */ | |
6478892d | 11850 | static void |
17a2f251 | 11851 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11852 | { |
11853 | expressionS ex_off; | |
11854 | expressionS ex_sym; | |
11855 | int reg1; | |
6478892d | 11856 | |
8586fc66 | 11857 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11858 | We also need NewABI support. */ |
11859 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11860 | { | |
11861 | s_ignore (0); | |
11862 | return; | |
11863 | } | |
11864 | ||
11865 | reg1 = tc_get_register (0); | |
11866 | SKIP_WHITESPACE (); | |
11867 | if (*input_line_pointer != ',') | |
11868 | { | |
11869 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11870 | return; | |
11871 | } | |
11872 | else | |
80245285 | 11873 | ++input_line_pointer; |
6478892d TS |
11874 | SKIP_WHITESPACE (); |
11875 | if (*input_line_pointer == '$') | |
80245285 TS |
11876 | { |
11877 | mips_cpreturn_register = tc_get_register (0); | |
11878 | mips_cpreturn_offset = -1; | |
11879 | } | |
6478892d | 11880 | else |
80245285 TS |
11881 | { |
11882 | mips_cpreturn_offset = get_absolute_expression (); | |
11883 | mips_cpreturn_register = -1; | |
11884 | } | |
6478892d TS |
11885 | SKIP_WHITESPACE (); |
11886 | if (*input_line_pointer != ',') | |
11887 | { | |
11888 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11889 | return; | |
11890 | } | |
11891 | else | |
f9419b05 | 11892 | ++input_line_pointer; |
6478892d | 11893 | SKIP_WHITESPACE (); |
f21f8242 | 11894 | expression (&ex_sym); |
6478892d | 11895 | |
584892a6 | 11896 | macro_start (); |
6478892d TS |
11897 | if (mips_cpreturn_register == -1) |
11898 | { | |
11899 | ex_off.X_op = O_constant; | |
11900 | ex_off.X_add_symbol = NULL; | |
11901 | ex_off.X_op_symbol = NULL; | |
11902 | ex_off.X_add_number = mips_cpreturn_offset; | |
11903 | ||
67c0d1eb | 11904 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11905 | BFD_RELOC_LO16, SP); |
6478892d TS |
11906 | } |
11907 | else | |
67c0d1eb | 11908 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11909 | mips_gp_register, 0); |
6478892d | 11910 | |
6e1304d8 RS |
11911 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, |
11912 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, BFD_RELOC_HI16_S); | |
11913 | ||
67c0d1eb | 11914 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
6e1304d8 RS |
11915 | mips_gp_register, -1, BFD_RELOC_GPREL16, |
11916 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
f21f8242 | 11917 | |
67c0d1eb | 11918 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
17a2f251 | 11919 | mips_gp_register, reg1); |
584892a6 | 11920 | macro_end (); |
6478892d TS |
11921 | |
11922 | demand_empty_rest_of_line (); | |
11923 | } | |
11924 | ||
11925 | static void | |
17a2f251 | 11926 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11927 | { |
11928 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11929 | .cplocal is ignored. */ | |
11930 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11931 | { | |
11932 | s_ignore (0); | |
11933 | return; | |
11934 | } | |
11935 | ||
11936 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11937 | demand_empty_rest_of_line (); |
6478892d TS |
11938 | } |
11939 | ||
252b5132 RH |
11940 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11941 | offset from $sp. The offset is remembered, and after making a PIC | |
11942 | call $gp is restored from that location. */ | |
11943 | ||
11944 | static void | |
17a2f251 | 11945 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11946 | { |
11947 | expressionS ex; | |
252b5132 | 11948 | |
6478892d | 11949 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11950 | .cprestore is ignored. */ |
6478892d | 11951 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11952 | { |
11953 | s_ignore (0); | |
11954 | return; | |
11955 | } | |
11956 | ||
11957 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11958 | mips_cprestore_valid = 1; |
252b5132 RH |
11959 | |
11960 | ex.X_op = O_constant; | |
11961 | ex.X_add_symbol = NULL; | |
11962 | ex.X_op_symbol = NULL; | |
11963 | ex.X_add_number = mips_cprestore_offset; | |
11964 | ||
584892a6 | 11965 | macro_start (); |
67c0d1eb RS |
11966 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11967 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11968 | macro_end (); |
252b5132 RH |
11969 | |
11970 | demand_empty_rest_of_line (); | |
11971 | } | |
11972 | ||
6478892d | 11973 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11974 | was given in the preceding .cpsetup, it results in: |
6478892d | 11975 | ld $gp, offset($sp) |
76b3015f | 11976 | |
6478892d | 11977 | If a register $reg2 was given there, it results in: |
609f23f4 | 11978 | daddu $gp, $reg2, $0 |
6478892d TS |
11979 | */ |
11980 | static void | |
17a2f251 | 11981 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11982 | { |
11983 | expressionS ex; | |
6478892d TS |
11984 | |
11985 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11986 | We also need NewABI support. */ | |
11987 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11988 | { | |
11989 | s_ignore (0); | |
11990 | return; | |
11991 | } | |
11992 | ||
584892a6 | 11993 | macro_start (); |
6478892d TS |
11994 | if (mips_cpreturn_register == -1) |
11995 | { | |
11996 | ex.X_op = O_constant; | |
11997 | ex.X_add_symbol = NULL; | |
11998 | ex.X_op_symbol = NULL; | |
11999 | ex.X_add_number = mips_cpreturn_offset; | |
12000 | ||
67c0d1eb | 12001 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12002 | } |
12003 | else | |
67c0d1eb | 12004 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12005 | mips_cpreturn_register, 0); |
584892a6 | 12006 | macro_end (); |
6478892d TS |
12007 | |
12008 | demand_empty_rest_of_line (); | |
12009 | } | |
12010 | ||
12011 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12012 | code. It sets the offset to use in gp_rel relocations. */ | |
12013 | ||
12014 | static void | |
17a2f251 | 12015 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12016 | { |
12017 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12018 | We also need NewABI support. */ | |
12019 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12020 | { | |
12021 | s_ignore (0); | |
12022 | return; | |
12023 | } | |
12024 | ||
def2e0dd | 12025 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12026 | |
12027 | demand_empty_rest_of_line (); | |
12028 | } | |
12029 | ||
252b5132 RH |
12030 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12031 | code. It generates a 32 bit GP relative reloc. */ | |
12032 | ||
12033 | static void | |
17a2f251 | 12034 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12035 | { |
12036 | symbolS *label; | |
12037 | expressionS ex; | |
12038 | char *p; | |
12039 | ||
12040 | /* When not generating PIC code, this is treated as .word. */ | |
12041 | if (mips_pic != SVR4_PIC) | |
12042 | { | |
12043 | s_cons (2); | |
12044 | return; | |
12045 | } | |
12046 | ||
12047 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12048 | mips_emit_delays (TRUE); |
252b5132 RH |
12049 | if (auto_align) |
12050 | mips_align (2, 0, label); | |
12051 | mips_clear_insn_labels (); | |
12052 | ||
12053 | expression (&ex); | |
12054 | ||
12055 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12056 | { | |
12057 | as_bad (_("Unsupported use of .gpword")); | |
12058 | ignore_rest_of_line (); | |
12059 | } | |
12060 | ||
12061 | p = frag_more (4); | |
17a2f251 | 12062 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12063 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12064 | BFD_RELOC_GPREL32); |
252b5132 RH |
12065 | |
12066 | demand_empty_rest_of_line (); | |
12067 | } | |
12068 | ||
10181a0d | 12069 | static void |
17a2f251 | 12070 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12071 | { |
12072 | symbolS *label; | |
12073 | expressionS ex; | |
12074 | char *p; | |
12075 | ||
12076 | /* When not generating PIC code, this is treated as .dword. */ | |
12077 | if (mips_pic != SVR4_PIC) | |
12078 | { | |
12079 | s_cons (3); | |
12080 | return; | |
12081 | } | |
12082 | ||
12083 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12084 | mips_emit_delays (TRUE); |
10181a0d AO |
12085 | if (auto_align) |
12086 | mips_align (3, 0, label); | |
12087 | mips_clear_insn_labels (); | |
12088 | ||
12089 | expression (&ex); | |
12090 | ||
12091 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12092 | { | |
12093 | as_bad (_("Unsupported use of .gpdword")); | |
12094 | ignore_rest_of_line (); | |
12095 | } | |
12096 | ||
12097 | p = frag_more (8); | |
17a2f251 | 12098 | md_number_to_chars (p, 0, 8); |
a105a300 | 12099 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12100 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12101 | |
12102 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12103 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12104 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12105 | |
12106 | demand_empty_rest_of_line (); | |
12107 | } | |
12108 | ||
252b5132 RH |
12109 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12110 | tables in SVR4 PIC code. */ | |
12111 | ||
12112 | static void | |
17a2f251 | 12113 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12114 | { |
252b5132 RH |
12115 | int reg; |
12116 | ||
10181a0d AO |
12117 | /* This is ignored when not generating SVR4 PIC code. */ |
12118 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12119 | { |
12120 | s_ignore (0); | |
12121 | return; | |
12122 | } | |
12123 | ||
12124 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12125 | macro_start (); |
252b5132 | 12126 | reg = tc_get_register (0); |
67c0d1eb | 12127 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12128 | macro_end (); |
252b5132 | 12129 | |
bdaaa2e1 | 12130 | demand_empty_rest_of_line (); |
252b5132 RH |
12131 | } |
12132 | ||
12133 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12134 | mips16 mode. This permits the linker to handle them specially, | |
12135 | such as generating jalx instructions when needed. We also make | |
12136 | them odd for the duration of the assembly, in order to generate the | |
12137 | right sort of code. We will make them even in the adjust_symtab | |
12138 | routine, while leaving them marked. This is convenient for the | |
12139 | debugger and the disassembler. The linker knows to make them odd | |
12140 | again. */ | |
12141 | ||
12142 | static void | |
17a2f251 | 12143 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12144 | { |
f9419b05 | 12145 | mips16_mark_labels (); |
252b5132 RH |
12146 | |
12147 | demand_empty_rest_of_line (); | |
12148 | } | |
12149 | ||
12150 | /* Handle a .stabn directive. We need these in order to mark a label | |
12151 | as being a mips16 text label correctly. Sometimes the compiler | |
12152 | will emit a label, followed by a .stabn, and then switch sections. | |
12153 | If the label and .stabn are in mips16 mode, then the label is | |
12154 | really a mips16 text label. */ | |
12155 | ||
12156 | static void | |
17a2f251 | 12157 | s_mips_stab (int type) |
252b5132 | 12158 | { |
f9419b05 | 12159 | if (type == 'n') |
252b5132 RH |
12160 | mips16_mark_labels (); |
12161 | ||
12162 | s_stab (type); | |
12163 | } | |
12164 | ||
12165 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12166 | */ | |
12167 | ||
12168 | static void | |
17a2f251 | 12169 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12170 | { |
12171 | char *name; | |
12172 | int c; | |
12173 | symbolS *symbolP; | |
12174 | expressionS exp; | |
12175 | ||
12176 | name = input_line_pointer; | |
12177 | c = get_symbol_end (); | |
12178 | symbolP = symbol_find_or_make (name); | |
12179 | S_SET_WEAK (symbolP); | |
12180 | *input_line_pointer = c; | |
12181 | ||
12182 | SKIP_WHITESPACE (); | |
12183 | ||
12184 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12185 | { | |
12186 | if (S_IS_DEFINED (symbolP)) | |
12187 | { | |
956cd1d6 | 12188 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12189 | S_GET_NAME (symbolP)); |
12190 | ignore_rest_of_line (); | |
12191 | return; | |
12192 | } | |
bdaaa2e1 | 12193 | |
252b5132 RH |
12194 | if (*input_line_pointer == ',') |
12195 | { | |
12196 | ++input_line_pointer; | |
12197 | SKIP_WHITESPACE (); | |
12198 | } | |
bdaaa2e1 | 12199 | |
252b5132 RH |
12200 | expression (&exp); |
12201 | if (exp.X_op != O_symbol) | |
12202 | { | |
12203 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12204 | ignore_rest_of_line (); |
252b5132 RH |
12205 | return; |
12206 | } | |
49309057 | 12207 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12208 | } |
12209 | ||
12210 | demand_empty_rest_of_line (); | |
12211 | } | |
12212 | ||
12213 | /* Parse a register string into a number. Called from the ECOFF code | |
12214 | to parse .frame. The argument is non-zero if this is the frame | |
12215 | register, so that we can record it in mips_frame_reg. */ | |
12216 | ||
12217 | int | |
17a2f251 | 12218 | tc_get_register (int frame) |
252b5132 RH |
12219 | { |
12220 | int reg; | |
12221 | ||
12222 | SKIP_WHITESPACE (); | |
12223 | if (*input_line_pointer++ != '$') | |
12224 | { | |
12225 | as_warn (_("expected `$'")); | |
85b51719 | 12226 | reg = ZERO; |
252b5132 | 12227 | } |
3882b010 | 12228 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12229 | { |
12230 | reg = get_absolute_expression (); | |
12231 | if (reg < 0 || reg >= 32) | |
12232 | { | |
12233 | as_warn (_("Bad register number")); | |
85b51719 | 12234 | reg = ZERO; |
252b5132 RH |
12235 | } |
12236 | } | |
12237 | else | |
12238 | { | |
76db943d | 12239 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12240 | { |
12241 | reg = RA; | |
12242 | input_line_pointer += 2; | |
12243 | } | |
76db943d | 12244 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12245 | { |
12246 | reg = FP; | |
12247 | input_line_pointer += 2; | |
12248 | } | |
252b5132 | 12249 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12250 | { |
12251 | reg = SP; | |
12252 | input_line_pointer += 2; | |
12253 | } | |
252b5132 | 12254 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12255 | { |
12256 | reg = GP; | |
12257 | input_line_pointer += 2; | |
12258 | } | |
252b5132 | 12259 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12260 | { |
12261 | reg = AT; | |
12262 | input_line_pointer += 2; | |
12263 | } | |
12264 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12265 | { | |
12266 | reg = KT0; | |
12267 | input_line_pointer += 3; | |
12268 | } | |
12269 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12270 | { | |
12271 | reg = KT1; | |
12272 | input_line_pointer += 3; | |
12273 | } | |
12274 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12275 | { | |
12276 | reg = ZERO; | |
12277 | input_line_pointer += 4; | |
12278 | } | |
252b5132 RH |
12279 | else |
12280 | { | |
12281 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12282 | reg = ZERO; |
12283 | while (ISALNUM(*input_line_pointer)) | |
12284 | input_line_pointer++; | |
252b5132 | 12285 | } |
252b5132 RH |
12286 | } |
12287 | if (frame) | |
7a621144 DJ |
12288 | { |
12289 | mips_frame_reg = reg != 0 ? reg : SP; | |
12290 | mips_frame_reg_valid = 1; | |
12291 | mips_cprestore_valid = 0; | |
12292 | } | |
252b5132 RH |
12293 | return reg; |
12294 | } | |
12295 | ||
12296 | valueT | |
17a2f251 | 12297 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12298 | { |
12299 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12300 | ||
12301 | #ifdef OBJ_ELF | |
12302 | /* We don't need to align ELF sections to the full alignment. | |
12303 | However, Irix 5 may prefer that we align them at least to a 16 | |
12304 | byte boundary. We don't bother to align the sections if we are | |
12305 | targeted for an embedded system. */ | |
12306 | if (strcmp (TARGET_OS, "elf") == 0) | |
12307 | return addr; | |
12308 | if (align > 4) | |
12309 | align = 4; | |
12310 | #endif | |
12311 | ||
12312 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12313 | } | |
12314 | ||
12315 | /* Utility routine, called from above as well. If called while the | |
12316 | input file is still being read, it's only an approximation. (For | |
12317 | example, a symbol may later become defined which appeared to be | |
12318 | undefined earlier.) */ | |
12319 | ||
12320 | static int | |
17a2f251 | 12321 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12322 | { |
12323 | if (sym == 0) | |
12324 | return 0; | |
12325 | ||
4d0d148d | 12326 | if (g_switch_value > 0) |
252b5132 RH |
12327 | { |
12328 | const char *symname; | |
12329 | int change; | |
12330 | ||
c9914766 | 12331 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12332 | register. It can be if it is smaller than the -G size or if |
12333 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12334 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12335 | they can. */ |
12336 | symname = S_GET_NAME (sym); | |
12337 | if (symname != (const char *) NULL | |
12338 | && (strcmp (symname, "eprol") == 0 | |
12339 | || strcmp (symname, "etext") == 0 | |
12340 | || strcmp (symname, "_gp") == 0 | |
12341 | || strcmp (symname, "edata") == 0 | |
12342 | || strcmp (symname, "_fbss") == 0 | |
12343 | || strcmp (symname, "_fdata") == 0 | |
12344 | || strcmp (symname, "_ftext") == 0 | |
12345 | || strcmp (symname, "end") == 0 | |
12346 | || strcmp (symname, "_gp_disp") == 0)) | |
12347 | change = 1; | |
12348 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12349 | && (0 | |
12350 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12351 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12352 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12353 | <= g_switch_value)) | |
252b5132 RH |
12354 | #endif |
12355 | /* We must defer this decision until after the whole | |
12356 | file has been read, since there might be a .extern | |
12357 | after the first use of this symbol. */ | |
12358 | || (before_relaxing | |
12359 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12360 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12361 | #endif |
12362 | && S_GET_VALUE (sym) == 0) | |
12363 | || (S_GET_VALUE (sym) != 0 | |
12364 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12365 | change = 0; | |
12366 | else | |
12367 | { | |
12368 | const char *segname; | |
12369 | ||
12370 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12371 | assert (strcmp (segname, ".lit8") != 0 | |
12372 | && strcmp (segname, ".lit4") != 0); | |
12373 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12374 | && strcmp (segname, ".sbss") != 0 |
12375 | && strncmp (segname, ".sdata.", 7) != 0 | |
12376 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12377 | } |
12378 | return change; | |
12379 | } | |
12380 | else | |
c9914766 | 12381 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12382 | return 1; |
12383 | } | |
12384 | ||
5919d012 RS |
12385 | |
12386 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12387 | ||
12388 | static bfd_boolean | |
17a2f251 | 12389 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12390 | { |
12391 | asection *symsec; | |
12392 | bfd_boolean linkonce; | |
12393 | ||
12394 | /* Handle the case of a symbol equated to another symbol. */ | |
12395 | while (symbol_equated_reloc_p (sym)) | |
12396 | { | |
12397 | symbolS *n; | |
12398 | ||
12399 | /* It's possible to get a loop here in a badly written | |
12400 | program. */ | |
12401 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12402 | if (n == sym) | |
12403 | break; | |
12404 | sym = n; | |
12405 | } | |
12406 | ||
12407 | symsec = S_GET_SEGMENT (sym); | |
12408 | ||
12409 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12410 | linkonce = FALSE; | |
12411 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12412 | { | |
12413 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12414 | != 0) | |
12415 | linkonce = TRUE; | |
12416 | ||
12417 | /* The GNU toolchain uses an extension for ELF: a section | |
12418 | beginning with the magic string .gnu.linkonce is a linkonce | |
12419 | section. */ | |
12420 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12421 | sizeof ".gnu.linkonce" - 1) == 0) | |
12422 | linkonce = TRUE; | |
12423 | } | |
12424 | ||
12425 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12426 | return (symsec != &bfd_und_section | |
12427 | && symsec != &bfd_abs_section | |
12428 | && ! bfd_is_com_section (symsec) | |
12429 | && !linkonce | |
12430 | #ifdef OBJ_ELF | |
12431 | /* A global or weak symbol is treated as external. */ | |
12432 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12433 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12434 | #endif |
12435 | ); | |
12436 | } | |
12437 | ||
12438 | ||
252b5132 RH |
12439 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12440 | extended opcode. SEC is the section the frag is in. */ | |
12441 | ||
12442 | static int | |
17a2f251 | 12443 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12444 | { |
12445 | int type; | |
12446 | register const struct mips16_immed_operand *op; | |
12447 | offsetT val; | |
12448 | int mintiny, maxtiny; | |
12449 | segT symsec; | |
98aa84af | 12450 | fragS *sym_frag; |
252b5132 RH |
12451 | |
12452 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12453 | return 0; | |
12454 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12455 | return 1; | |
12456 | ||
12457 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12458 | op = mips16_immed_operands; | |
12459 | while (op->type != type) | |
12460 | { | |
12461 | ++op; | |
12462 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12463 | } | |
12464 | ||
12465 | if (op->unsp) | |
12466 | { | |
12467 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12468 | { | |
12469 | mintiny = 1; | |
12470 | maxtiny = 1 << op->nbits; | |
12471 | } | |
12472 | else | |
12473 | { | |
12474 | mintiny = 0; | |
12475 | maxtiny = (1 << op->nbits) - 1; | |
12476 | } | |
12477 | } | |
12478 | else | |
12479 | { | |
12480 | mintiny = - (1 << (op->nbits - 1)); | |
12481 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12482 | } | |
12483 | ||
98aa84af | 12484 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12485 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12486 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12487 | |
12488 | if (op->pcrel) | |
12489 | { | |
12490 | addressT addr; | |
12491 | ||
12492 | /* We won't have the section when we are called from | |
12493 | mips_relax_frag. However, we will always have been called | |
12494 | from md_estimate_size_before_relax first. If this is a | |
12495 | branch to a different section, we mark it as such. If SEC is | |
12496 | NULL, and the frag is not marked, then it must be a branch to | |
12497 | the same section. */ | |
12498 | if (sec == NULL) | |
12499 | { | |
12500 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12501 | return 1; | |
12502 | } | |
12503 | else | |
12504 | { | |
98aa84af | 12505 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12506 | if (symsec != sec) |
12507 | { | |
12508 | fragp->fr_subtype = | |
12509 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12510 | ||
12511 | /* FIXME: We should support this, and let the linker | |
12512 | catch branches and loads that are out of range. */ | |
12513 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12514 | _("unsupported PC relative reference to different section")); | |
12515 | ||
12516 | return 1; | |
12517 | } | |
98aa84af AM |
12518 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12519 | /* Assume non-extended on the first relaxation pass. | |
12520 | The address we have calculated will be bogus if this is | |
12521 | a forward branch to another frag, as the forward frag | |
12522 | will have fr_address == 0. */ | |
12523 | return 0; | |
252b5132 RH |
12524 | } |
12525 | ||
12526 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12527 | the same section. If the relax_marker of the symbol fragment |
12528 | differs from the relax_marker of this fragment, we have not | |
12529 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12530 | in STRETCH in order to get a better estimate of the address. |
12531 | This particularly matters because of the shift bits. */ | |
12532 | if (stretch != 0 | |
98aa84af | 12533 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12534 | { |
12535 | fragS *f; | |
12536 | ||
12537 | /* Adjust stretch for any alignment frag. Note that if have | |
12538 | been expanding the earlier code, the symbol may be | |
12539 | defined in what appears to be an earlier frag. FIXME: | |
12540 | This doesn't handle the fr_subtype field, which specifies | |
12541 | a maximum number of bytes to skip when doing an | |
12542 | alignment. */ | |
98aa84af | 12543 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12544 | { |
12545 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12546 | { | |
12547 | if (stretch < 0) | |
12548 | stretch = - ((- stretch) | |
12549 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12550 | else | |
12551 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12552 | if (stretch == 0) | |
12553 | break; | |
12554 | } | |
12555 | } | |
12556 | if (f != NULL) | |
12557 | val += stretch; | |
12558 | } | |
12559 | ||
12560 | addr = fragp->fr_address + fragp->fr_fix; | |
12561 | ||
12562 | /* The base address rules are complicated. The base address of | |
12563 | a branch is the following instruction. The base address of a | |
12564 | PC relative load or add is the instruction itself, but if it | |
12565 | is in a delay slot (in which case it can not be extended) use | |
12566 | the address of the instruction whose delay slot it is in. */ | |
12567 | if (type == 'p' || type == 'q') | |
12568 | { | |
12569 | addr += 2; | |
12570 | ||
12571 | /* If we are currently assuming that this frag should be | |
12572 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12573 | higher. */ |
252b5132 RH |
12574 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12575 | addr += 2; | |
12576 | ||
12577 | /* Ignore the low bit in the target, since it will be set | |
12578 | for a text label. */ | |
12579 | if ((val & 1) != 0) | |
12580 | --val; | |
12581 | } | |
12582 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12583 | addr -= 4; | |
12584 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12585 | addr -= 2; | |
12586 | ||
12587 | val -= addr & ~ ((1 << op->shift) - 1); | |
12588 | ||
12589 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12590 | if (type == 'p' || type == 'q') | |
12591 | val /= 2; | |
12592 | ||
12593 | /* If any of the shifted bits are set, we must use an extended | |
12594 | opcode. If the address depends on the size of this | |
12595 | instruction, this can lead to a loop, so we arrange to always | |
12596 | use an extended opcode. We only check this when we are in | |
12597 | the main relaxation loop, when SEC is NULL. */ | |
12598 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12599 | { | |
12600 | fragp->fr_subtype = | |
12601 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12602 | return 1; | |
12603 | } | |
12604 | ||
12605 | /* If we are about to mark a frag as extended because the value | |
12606 | is precisely maxtiny + 1, then there is a chance of an | |
12607 | infinite loop as in the following code: | |
12608 | la $4,foo | |
12609 | .skip 1020 | |
12610 | .align 2 | |
12611 | foo: | |
12612 | In this case when the la is extended, foo is 0x3fc bytes | |
12613 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12614 | the la must be extended. To avoid this loop, we mark the | |
12615 | frag as extended if it was small, and is about to become | |
12616 | extended with a value of maxtiny + 1. */ | |
12617 | if (val == ((maxtiny + 1) << op->shift) | |
12618 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12619 | && sec == NULL) | |
12620 | { | |
12621 | fragp->fr_subtype = | |
12622 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12623 | return 1; | |
12624 | } | |
12625 | } | |
12626 | else if (symsec != absolute_section && sec != NULL) | |
12627 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12628 | ||
12629 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12630 | || val < (mintiny << op->shift) | |
12631 | || val > (maxtiny << op->shift)) | |
12632 | return 1; | |
12633 | else | |
12634 | return 0; | |
12635 | } | |
12636 | ||
4a6a3df4 AO |
12637 | /* Compute the length of a branch sequence, and adjust the |
12638 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12639 | worst-case length is computed, with UPDATE being used to indicate | |
12640 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12641 | branch is to be computed. */ | |
12642 | static int | |
17a2f251 | 12643 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12644 | { |
b34976b6 | 12645 | bfd_boolean toofar; |
4a6a3df4 AO |
12646 | int length; |
12647 | ||
12648 | if (fragp | |
12649 | && S_IS_DEFINED (fragp->fr_symbol) | |
12650 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12651 | { | |
12652 | addressT addr; | |
12653 | offsetT val; | |
12654 | ||
12655 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12656 | ||
12657 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12658 | ||
12659 | val -= addr; | |
12660 | ||
12661 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12662 | } | |
12663 | else if (fragp) | |
12664 | /* If the symbol is not defined or it's in a different segment, | |
12665 | assume the user knows what's going on and emit a short | |
12666 | branch. */ | |
b34976b6 | 12667 | toofar = FALSE; |
4a6a3df4 | 12668 | else |
b34976b6 | 12669 | toofar = TRUE; |
4a6a3df4 AO |
12670 | |
12671 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12672 | fragp->fr_subtype | |
af6ae2ad | 12673 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12674 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12675 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12676 | toofar); | |
12677 | ||
12678 | length = 4; | |
12679 | if (toofar) | |
12680 | { | |
12681 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12682 | length += 8; | |
12683 | ||
12684 | if (mips_pic != NO_PIC) | |
12685 | { | |
12686 | /* Additional space for PIC loading of target address. */ | |
12687 | length += 8; | |
12688 | if (mips_opts.isa == ISA_MIPS1) | |
12689 | /* Additional space for $at-stabilizing nop. */ | |
12690 | length += 4; | |
12691 | } | |
12692 | ||
12693 | /* If branch is conditional. */ | |
12694 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12695 | length += 8; | |
12696 | } | |
b34976b6 | 12697 | |
4a6a3df4 AO |
12698 | return length; |
12699 | } | |
12700 | ||
252b5132 RH |
12701 | /* Estimate the size of a frag before relaxing. Unless this is the |
12702 | mips16, we are not really relaxing here, and the final size is | |
12703 | encoded in the subtype information. For the mips16, we have to | |
12704 | decide whether we are using an extended opcode or not. */ | |
12705 | ||
252b5132 | 12706 | int |
17a2f251 | 12707 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12708 | { |
5919d012 | 12709 | int change; |
252b5132 | 12710 | |
4a6a3df4 AO |
12711 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12712 | { | |
12713 | ||
b34976b6 AM |
12714 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12715 | ||
4a6a3df4 AO |
12716 | return fragp->fr_var; |
12717 | } | |
12718 | ||
252b5132 | 12719 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12720 | /* We don't want to modify the EXTENDED bit here; it might get us |
12721 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12722 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12723 | |
12724 | if (mips_pic == NO_PIC) | |
5919d012 | 12725 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12726 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12727 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12728 | else |
12729 | abort (); | |
12730 | ||
12731 | if (change) | |
12732 | { | |
4d7206a2 | 12733 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12734 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12735 | } |
4d7206a2 RS |
12736 | else |
12737 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12738 | } |
12739 | ||
12740 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12741 | should be converted into a reloc against a section. */ |
252b5132 RH |
12742 | |
12743 | int | |
17a2f251 | 12744 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12745 | { |
de7e6852 RS |
12746 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12747 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12748 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12749 | return 0; | |
a161fe53 | 12750 | |
252b5132 RH |
12751 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12752 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12753 | return 0; | |
a161fe53 | 12754 | |
252b5132 RH |
12755 | if (fixp->fx_addsy == NULL) |
12756 | return 1; | |
a161fe53 | 12757 | |
de7e6852 RS |
12758 | /* If symbol SYM is in a mergeable section, relocations of the form |
12759 | SYM + 0 can usually be made section-relative. The mergeable data | |
12760 | is then identified by the section offset rather than by the symbol. | |
12761 | ||
12762 | However, if we're generating REL LO16 relocations, the offset is split | |
12763 | between the LO16 and parterning high part relocation. The linker will | |
12764 | need to recalculate the complete offset in order to correctly identify | |
12765 | the merge data. | |
12766 | ||
12767 | The linker has traditionally not looked for the parterning high part | |
12768 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12769 | placed anywhere. Rather than break backwards compatibility by changing | |
12770 | this, it seems better not to force the issue, and instead keep the | |
12771 | original symbol. This will work with either linker behavior. */ | |
12772 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12773 | && HAVE_IN_PLACE_ADDENDS | |
12774 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12775 | return 0; | |
12776 | ||
252b5132 | 12777 | #ifdef OBJ_ELF |
de7e6852 RS |
12778 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12779 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12780 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12781 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12782 | && fixp->fx_subsy == NULL) | |
12783 | return 0; | |
12784 | #endif | |
a161fe53 | 12785 | |
252b5132 RH |
12786 | return 1; |
12787 | } | |
12788 | ||
12789 | /* Translate internal representation of relocation info to BFD target | |
12790 | format. */ | |
12791 | ||
12792 | arelent ** | |
17a2f251 | 12793 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12794 | { |
12795 | static arelent *retval[4]; | |
12796 | arelent *reloc; | |
12797 | bfd_reloc_code_real_type code; | |
12798 | ||
4b0cff4e TS |
12799 | memset (retval, 0, sizeof(retval)); |
12800 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12801 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12802 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12803 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12804 | ||
3e722fb5 CD |
12805 | assert (! fixp->fx_pcrel); |
12806 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12807 | |
438c16b8 TS |
12808 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12809 | entry to be used in the relocation's section offset. */ | |
12810 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12811 | { |
12812 | reloc->address = reloc->addend; | |
12813 | reloc->addend = 0; | |
12814 | } | |
12815 | ||
252b5132 | 12816 | code = fixp->fx_r_type; |
252b5132 | 12817 | |
3e722fb5 CD |
12818 | /* To support a PC relative reloc, we used a Cygnus extension. |
12819 | We check for that here to make sure that we don't let such a | |
12820 | reloc escape normally. (FIXME: This was formerly used by | |
12821 | embedded-PIC support, but is now used by branch handling in | |
12822 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12823 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12824 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12825 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12826 | reloc->howto = NULL; |
12827 | else | |
12828 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12829 | ||
252b5132 RH |
12830 | if (reloc->howto == NULL) |
12831 | { | |
12832 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12833 | _("Can not represent %s relocation in this object file format"), | |
12834 | bfd_get_reloc_code_name (code)); | |
12835 | retval[0] = NULL; | |
12836 | } | |
12837 | ||
12838 | return retval; | |
12839 | } | |
12840 | ||
12841 | /* Relax a machine dependent frag. This returns the amount by which | |
12842 | the current size of the frag should change. */ | |
12843 | ||
12844 | int | |
17a2f251 | 12845 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12846 | { |
4a6a3df4 AO |
12847 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12848 | { | |
12849 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12850 | |
12851 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12852 | |
12853 | return fragp->fr_var - old_var; | |
12854 | } | |
12855 | ||
252b5132 RH |
12856 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12857 | return 0; | |
12858 | ||
c4e7957c | 12859 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12860 | { |
12861 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12862 | return 0; | |
12863 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12864 | return 2; | |
12865 | } | |
12866 | else | |
12867 | { | |
12868 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12869 | return 0; | |
12870 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12871 | return -2; | |
12872 | } | |
12873 | ||
12874 | return 0; | |
12875 | } | |
12876 | ||
12877 | /* Convert a machine dependent frag. */ | |
12878 | ||
12879 | void | |
17a2f251 | 12880 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12881 | { |
4a6a3df4 AO |
12882 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12883 | { | |
12884 | bfd_byte *buf; | |
12885 | unsigned long insn; | |
12886 | expressionS exp; | |
12887 | fixS *fixp; | |
b34976b6 | 12888 | |
4a6a3df4 AO |
12889 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12890 | ||
12891 | if (target_big_endian) | |
12892 | insn = bfd_getb32 (buf); | |
12893 | else | |
12894 | insn = bfd_getl32 (buf); | |
b34976b6 | 12895 | |
4a6a3df4 AO |
12896 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12897 | { | |
12898 | /* We generate a fixup instead of applying it right now | |
12899 | because, if there are linker relaxations, we're going to | |
12900 | need the relocations. */ | |
12901 | exp.X_op = O_symbol; | |
12902 | exp.X_add_symbol = fragp->fr_symbol; | |
12903 | exp.X_add_number = fragp->fr_offset; | |
12904 | ||
12905 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12906 | 4, &exp, 1, |
12907 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12908 | fixp->fx_file = fragp->fr_file; |
12909 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12910 | |
17a2f251 | 12911 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12912 | buf += 4; |
12913 | } | |
12914 | else | |
12915 | { | |
12916 | int i; | |
12917 | ||
12918 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12919 | _("relaxed out-of-range branch into a jump")); | |
12920 | ||
12921 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12922 | goto uncond; | |
12923 | ||
12924 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12925 | { | |
12926 | /* Reverse the branch. */ | |
12927 | switch ((insn >> 28) & 0xf) | |
12928 | { | |
12929 | case 4: | |
12930 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12931 | have the condition reversed by tweaking a single | |
12932 | bit, and their opcodes all have 0x4???????. */ | |
12933 | assert ((insn & 0xf1000000) == 0x41000000); | |
12934 | insn ^= 0x00010000; | |
12935 | break; | |
12936 | ||
12937 | case 0: | |
12938 | /* bltz 0x04000000 bgez 0x04010000 | |
12939 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12940 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12941 | insn ^= 0x00010000; | |
12942 | break; | |
b34976b6 | 12943 | |
4a6a3df4 AO |
12944 | case 1: |
12945 | /* beq 0x10000000 bne 0x14000000 | |
12946 | blez 0x18000000 bgtz 0x1c000000 */ | |
12947 | insn ^= 0x04000000; | |
12948 | break; | |
12949 | ||
12950 | default: | |
12951 | abort (); | |
12952 | } | |
12953 | } | |
12954 | ||
12955 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12956 | { | |
12957 | /* Clear the and-link bit. */ | |
12958 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12959 | ||
12960 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12961 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12962 | insn &= ~0x00100000; | |
12963 | } | |
12964 | ||
12965 | /* Branch over the branch (if the branch was likely) or the | |
12966 | full jump (not likely case). Compute the offset from the | |
12967 | current instruction to branch to. */ | |
12968 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12969 | i = 16; | |
12970 | else | |
12971 | { | |
12972 | /* How many bytes in instructions we've already emitted? */ | |
12973 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12974 | /* How many bytes in instructions from here to the end? */ | |
12975 | i = fragp->fr_var - i; | |
12976 | } | |
12977 | /* Convert to instruction count. */ | |
12978 | i >>= 2; | |
12979 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12980 | i--; |
4a6a3df4 AO |
12981 | insn |= i; |
12982 | /* Branch over the jump. */ | |
17a2f251 | 12983 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12984 | buf += 4; |
12985 | ||
12986 | /* Nop */ | |
17a2f251 | 12987 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12988 | buf += 4; |
12989 | ||
12990 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12991 | { | |
12992 | /* beql $0, $0, 2f */ | |
12993 | insn = 0x50000000; | |
12994 | /* Compute the PC offset from the current instruction to | |
12995 | the end of the variable frag. */ | |
12996 | /* How many bytes in instructions we've already emitted? */ | |
12997 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12998 | /* How many bytes in instructions from here to the end? */ | |
12999 | i = fragp->fr_var - i; | |
13000 | /* Convert to instruction count. */ | |
13001 | i >>= 2; | |
13002 | /* Don't decrement i, because we want to branch over the | |
13003 | delay slot. */ | |
13004 | ||
13005 | insn |= i; | |
17a2f251 | 13006 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13007 | buf += 4; |
13008 | ||
17a2f251 | 13009 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13010 | buf += 4; |
13011 | } | |
13012 | ||
13013 | uncond: | |
13014 | if (mips_pic == NO_PIC) | |
13015 | { | |
13016 | /* j or jal. */ | |
13017 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13018 | ? 0x0c000000 : 0x08000000); | |
13019 | exp.X_op = O_symbol; | |
13020 | exp.X_add_symbol = fragp->fr_symbol; | |
13021 | exp.X_add_number = fragp->fr_offset; | |
13022 | ||
13023 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13024 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13025 | fixp->fx_file = fragp->fr_file; | |
13026 | fixp->fx_line = fragp->fr_line; | |
13027 | ||
17a2f251 | 13028 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13029 | buf += 4; |
13030 | } | |
13031 | else | |
13032 | { | |
13033 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13034 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13035 | exp.X_op = O_symbol; | |
13036 | exp.X_add_symbol = fragp->fr_symbol; | |
13037 | exp.X_add_number = fragp->fr_offset; | |
13038 | ||
13039 | if (fragp->fr_offset) | |
13040 | { | |
13041 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13042 | exp.X_add_number = 0; | |
13043 | } | |
13044 | ||
13045 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13046 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13047 | fixp->fx_file = fragp->fr_file; | |
13048 | fixp->fx_line = fragp->fr_line; | |
13049 | ||
17a2f251 | 13050 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13051 | buf += 4; |
b34976b6 | 13052 | |
4a6a3df4 AO |
13053 | if (mips_opts.isa == ISA_MIPS1) |
13054 | { | |
13055 | /* nop */ | |
17a2f251 | 13056 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13057 | buf += 4; |
13058 | } | |
13059 | ||
13060 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13061 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13062 | ||
13063 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13064 | 4, &exp, 0, BFD_RELOC_LO16); | |
13065 | fixp->fx_file = fragp->fr_file; | |
13066 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13067 | |
17a2f251 | 13068 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13069 | buf += 4; |
13070 | ||
13071 | /* j(al)r $at. */ | |
13072 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13073 | insn = 0x0020f809; | |
13074 | else | |
13075 | insn = 0x00200008; | |
13076 | ||
17a2f251 | 13077 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13078 | buf += 4; |
13079 | } | |
13080 | } | |
13081 | ||
13082 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13083 | + fragp->fr_fix + fragp->fr_var); | |
13084 | ||
13085 | fragp->fr_fix += fragp->fr_var; | |
13086 | ||
13087 | return; | |
13088 | } | |
13089 | ||
252b5132 RH |
13090 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13091 | { | |
13092 | int type; | |
13093 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13094 | bfd_boolean small, ext; |
252b5132 RH |
13095 | offsetT val; |
13096 | bfd_byte *buf; | |
13097 | unsigned long insn; | |
b34976b6 | 13098 | bfd_boolean use_extend; |
252b5132 RH |
13099 | unsigned short extend; |
13100 | ||
13101 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13102 | op = mips16_immed_operands; | |
13103 | while (op->type != type) | |
13104 | ++op; | |
13105 | ||
13106 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13107 | { | |
b34976b6 AM |
13108 | small = FALSE; |
13109 | ext = TRUE; | |
252b5132 RH |
13110 | } |
13111 | else | |
13112 | { | |
b34976b6 AM |
13113 | small = TRUE; |
13114 | ext = FALSE; | |
252b5132 RH |
13115 | } |
13116 | ||
6386f3a7 | 13117 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13118 | val = S_GET_VALUE (fragp->fr_symbol); |
13119 | if (op->pcrel) | |
13120 | { | |
13121 | addressT addr; | |
13122 | ||
13123 | addr = fragp->fr_address + fragp->fr_fix; | |
13124 | ||
13125 | /* The rules for the base address of a PC relative reloc are | |
13126 | complicated; see mips16_extended_frag. */ | |
13127 | if (type == 'p' || type == 'q') | |
13128 | { | |
13129 | addr += 2; | |
13130 | if (ext) | |
13131 | addr += 2; | |
13132 | /* Ignore the low bit in the target, since it will be | |
13133 | set for a text label. */ | |
13134 | if ((val & 1) != 0) | |
13135 | --val; | |
13136 | } | |
13137 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13138 | addr -= 4; | |
13139 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13140 | addr -= 2; | |
13141 | ||
13142 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13143 | val -= addr; | |
13144 | ||
13145 | /* Make sure the section winds up with the alignment we have | |
13146 | assumed. */ | |
13147 | if (op->shift > 0) | |
13148 | record_alignment (asec, op->shift); | |
13149 | } | |
13150 | ||
13151 | if (ext | |
13152 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13153 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13154 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13155 | _("extended instruction in delay slot")); | |
13156 | ||
13157 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13158 | ||
13159 | if (target_big_endian) | |
13160 | insn = bfd_getb16 (buf); | |
13161 | else | |
13162 | insn = bfd_getl16 (buf); | |
13163 | ||
13164 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13165 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13166 | small, ext, &insn, &use_extend, &extend); | |
13167 | ||
13168 | if (use_extend) | |
13169 | { | |
17a2f251 | 13170 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13171 | fragp->fr_fix += 2; |
13172 | buf += 2; | |
13173 | } | |
13174 | ||
17a2f251 | 13175 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13176 | fragp->fr_fix += 2; |
13177 | buf += 2; | |
13178 | } | |
13179 | else | |
13180 | { | |
4d7206a2 RS |
13181 | int first, second; |
13182 | fixS *fixp; | |
252b5132 | 13183 | |
4d7206a2 RS |
13184 | first = RELAX_FIRST (fragp->fr_subtype); |
13185 | second = RELAX_SECOND (fragp->fr_subtype); | |
13186 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13187 | |
584892a6 RS |
13188 | /* Possibly emit a warning if we've chosen the longer option. */ |
13189 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13190 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13191 | { | |
13192 | const char *msg = macro_warning (fragp->fr_subtype); | |
13193 | if (msg != 0) | |
13194 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13195 | } | |
13196 | ||
4d7206a2 RS |
13197 | /* Go through all the fixups for the first sequence. Disable them |
13198 | (by marking them as done) if we're going to use the second | |
13199 | sequence instead. */ | |
13200 | while (fixp | |
13201 | && fixp->fx_frag == fragp | |
13202 | && fixp->fx_where < fragp->fr_fix - second) | |
13203 | { | |
13204 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13205 | fixp->fx_done = 1; | |
13206 | fixp = fixp->fx_next; | |
13207 | } | |
252b5132 | 13208 | |
4d7206a2 RS |
13209 | /* Go through the fixups for the second sequence. Disable them if |
13210 | we're going to use the first sequence, otherwise adjust their | |
13211 | addresses to account for the relaxation. */ | |
13212 | while (fixp && fixp->fx_frag == fragp) | |
13213 | { | |
13214 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13215 | fixp->fx_where -= first; | |
13216 | else | |
13217 | fixp->fx_done = 1; | |
13218 | fixp = fixp->fx_next; | |
13219 | } | |
13220 | ||
13221 | /* Now modify the frag contents. */ | |
13222 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13223 | { | |
13224 | char *start; | |
13225 | ||
13226 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13227 | memmove (start, start + first, second); | |
13228 | fragp->fr_fix -= first; | |
13229 | } | |
13230 | else | |
13231 | fragp->fr_fix -= second; | |
252b5132 RH |
13232 | } |
13233 | } | |
13234 | ||
13235 | #ifdef OBJ_ELF | |
13236 | ||
13237 | /* This function is called after the relocs have been generated. | |
13238 | We've been storing mips16 text labels as odd. Here we convert them | |
13239 | back to even for the convenience of the debugger. */ | |
13240 | ||
13241 | void | |
17a2f251 | 13242 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13243 | { |
13244 | asymbol **syms; | |
13245 | unsigned int count, i; | |
13246 | ||
13247 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13248 | return; | |
13249 | ||
13250 | syms = bfd_get_outsymbols (stdoutput); | |
13251 | count = bfd_get_symcount (stdoutput); | |
13252 | for (i = 0; i < count; i++, syms++) | |
13253 | { | |
13254 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13255 | && ((*syms)->value & 1) != 0) | |
13256 | { | |
13257 | (*syms)->value &= ~1; | |
13258 | /* If the symbol has an odd size, it was probably computed | |
13259 | incorrectly, so adjust that as well. */ | |
13260 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13261 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13262 | } | |
13263 | } | |
13264 | } | |
13265 | ||
13266 | #endif | |
13267 | ||
13268 | /* This function is called whenever a label is defined. It is used | |
13269 | when handling branch delays; if a branch has a label, we assume we | |
13270 | can not move it. */ | |
13271 | ||
13272 | void | |
17a2f251 | 13273 | mips_define_label (symbolS *sym) |
252b5132 RH |
13274 | { |
13275 | struct insn_label_list *l; | |
13276 | ||
13277 | if (free_insn_labels == NULL) | |
13278 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13279 | else | |
13280 | { | |
13281 | l = free_insn_labels; | |
13282 | free_insn_labels = l->next; | |
13283 | } | |
13284 | ||
13285 | l->label = sym; | |
13286 | l->next = insn_labels; | |
13287 | insn_labels = l; | |
13288 | } | |
13289 | \f | |
13290 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13291 | ||
13292 | /* Some special processing for a MIPS ELF file. */ | |
13293 | ||
13294 | void | |
17a2f251 | 13295 | mips_elf_final_processing (void) |
252b5132 RH |
13296 | { |
13297 | /* Write out the register information. */ | |
316f5878 | 13298 | if (mips_abi != N64_ABI) |
252b5132 RH |
13299 | { |
13300 | Elf32_RegInfo s; | |
13301 | ||
13302 | s.ri_gprmask = mips_gprmask; | |
13303 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13304 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13305 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13306 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13307 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13308 | ||
13309 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13310 | ((Elf32_External_RegInfo *) | |
13311 | mips_regmask_frag)); | |
13312 | } | |
13313 | else | |
13314 | { | |
13315 | Elf64_Internal_RegInfo s; | |
13316 | ||
13317 | s.ri_gprmask = mips_gprmask; | |
13318 | s.ri_pad = 0; | |
13319 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13320 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13321 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13322 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13323 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13324 | ||
13325 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13326 | ((Elf64_External_RegInfo *) | |
13327 | mips_regmask_frag)); | |
13328 | } | |
13329 | ||
13330 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13331 | sort of BFD interface for this. */ | |
13332 | if (mips_any_noreorder) | |
13333 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13334 | if (mips_pic != NO_PIC) | |
143d77c5 | 13335 | { |
252b5132 | 13336 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13337 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13338 | } | |
13339 | if (mips_abicalls) | |
13340 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13341 | |
98d3f06f | 13342 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13343 | if (file_ase_mips16) |
13344 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13345 | #if 0 /* XXX FIXME */ |
13346 | if (file_ase_mips3d) | |
13347 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13348 | #endif | |
deec1734 CD |
13349 | if (file_ase_mdmx) |
13350 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13351 | |
bdaaa2e1 | 13352 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13353 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13354 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13355 | else if (mips_abi == O64_ABI) |
252b5132 | 13356 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13357 | else if (mips_abi == EABI_ABI) |
252b5132 | 13358 | { |
316f5878 | 13359 | if (!file_mips_gp32) |
252b5132 RH |
13360 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13361 | else | |
13362 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13363 | } | |
316f5878 | 13364 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13365 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13366 | ||
c9914766 | 13367 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13368 | |
13369 | if (mips_32bitmode) | |
13370 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13371 | } | |
13372 | ||
13373 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13374 | \f | |
beae10d5 KH |
13375 | typedef struct proc { |
13376 | symbolS *isym; | |
13377 | unsigned long reg_mask; | |
13378 | unsigned long reg_offset; | |
13379 | unsigned long fpreg_mask; | |
13380 | unsigned long fpreg_offset; | |
13381 | unsigned long frame_offset; | |
13382 | unsigned long frame_reg; | |
13383 | unsigned long pc_reg; | |
13384 | } procS; | |
252b5132 RH |
13385 | |
13386 | static procS cur_proc; | |
13387 | static procS *cur_proc_ptr; | |
13388 | static int numprocs; | |
13389 | ||
0a9ef439 | 13390 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13391 | |
0a9ef439 | 13392 | void |
17a2f251 | 13393 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13394 | { |
0a9ef439 RH |
13395 | if (fragp->fr_type != rs_align_code) |
13396 | return; | |
13397 | ||
13398 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13399 | { |
13400 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13401 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13402 | ||
0a9ef439 RH |
13403 | int bytes; |
13404 | char *p; | |
a19d8eb0 | 13405 | |
0a9ef439 RH |
13406 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13407 | p = fragp->fr_literal + fragp->fr_fix; | |
13408 | ||
13409 | if (bytes & 1) | |
13410 | { | |
13411 | *p++ = 0; | |
f9419b05 | 13412 | fragp->fr_fix++; |
0a9ef439 RH |
13413 | } |
13414 | ||
13415 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13416 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13417 | } |
13418 | ||
0a9ef439 | 13419 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13420 | } |
13421 | ||
252b5132 | 13422 | static void |
17a2f251 | 13423 | md_obj_begin (void) |
252b5132 RH |
13424 | { |
13425 | } | |
13426 | ||
13427 | static void | |
17a2f251 | 13428 | md_obj_end (void) |
252b5132 RH |
13429 | { |
13430 | /* check for premature end, nesting errors, etc */ | |
13431 | if (cur_proc_ptr) | |
9a41af64 | 13432 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13433 | } |
13434 | ||
13435 | static long | |
17a2f251 | 13436 | get_number (void) |
252b5132 RH |
13437 | { |
13438 | int negative = 0; | |
13439 | long val = 0; | |
13440 | ||
13441 | if (*input_line_pointer == '-') | |
13442 | { | |
13443 | ++input_line_pointer; | |
13444 | negative = 1; | |
13445 | } | |
3882b010 | 13446 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13447 | as_bad (_("expected simple number")); |
252b5132 RH |
13448 | if (input_line_pointer[0] == '0') |
13449 | { | |
13450 | if (input_line_pointer[1] == 'x') | |
13451 | { | |
13452 | input_line_pointer += 2; | |
3882b010 | 13453 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13454 | { |
13455 | val <<= 4; | |
13456 | val |= hex_value (*input_line_pointer++); | |
13457 | } | |
13458 | return negative ? -val : val; | |
13459 | } | |
13460 | else | |
13461 | { | |
13462 | ++input_line_pointer; | |
3882b010 | 13463 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13464 | { |
13465 | val <<= 3; | |
13466 | val |= *input_line_pointer++ - '0'; | |
13467 | } | |
13468 | return negative ? -val : val; | |
13469 | } | |
13470 | } | |
3882b010 | 13471 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13472 | { |
13473 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13474 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13475 | as_warn (_("invalid number")); |
252b5132 RH |
13476 | return -1; |
13477 | } | |
3882b010 | 13478 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13479 | { |
13480 | val *= 10; | |
13481 | val += *input_line_pointer++ - '0'; | |
13482 | } | |
13483 | return negative ? -val : val; | |
13484 | } | |
13485 | ||
13486 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13487 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13488 | case .file implies DWARF-2. */ | |
13489 | ||
13490 | static void | |
17a2f251 | 13491 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13492 | { |
ecb4347a DJ |
13493 | static int first_file_directive = 0; |
13494 | ||
c5dd6aab DJ |
13495 | if (ECOFF_DEBUGGING) |
13496 | { | |
13497 | get_number (); | |
13498 | s_app_file (0); | |
13499 | } | |
13500 | else | |
ecb4347a DJ |
13501 | { |
13502 | char *filename; | |
13503 | ||
13504 | filename = dwarf2_directive_file (0); | |
13505 | ||
13506 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13507 | directive even for stabs output. Make sure that this | |
13508 | ".file" is handled. Note that you need a version of GCC | |
13509 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13510 | if (filename != NULL && ! first_file_directive) | |
13511 | { | |
13512 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13513 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13514 | } |
13515 | first_file_directive = 1; | |
13516 | } | |
c5dd6aab DJ |
13517 | } |
13518 | ||
13519 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13520 | |
13521 | static void | |
17a2f251 | 13522 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13523 | { |
c5dd6aab DJ |
13524 | if (!ECOFF_DEBUGGING) |
13525 | dwarf2_directive_loc (0); | |
252b5132 RH |
13526 | } |
13527 | ||
252b5132 RH |
13528 | /* The .end directive. */ |
13529 | ||
13530 | static void | |
17a2f251 | 13531 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13532 | { |
13533 | symbolS *p; | |
252b5132 | 13534 | |
7a621144 DJ |
13535 | /* Following functions need their own .frame and .cprestore directives. */ |
13536 | mips_frame_reg_valid = 0; | |
13537 | mips_cprestore_valid = 0; | |
13538 | ||
252b5132 RH |
13539 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13540 | { | |
13541 | p = get_symbol (); | |
13542 | demand_empty_rest_of_line (); | |
13543 | } | |
13544 | else | |
13545 | p = NULL; | |
13546 | ||
14949570 | 13547 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13548 | as_warn (_(".end not in text section")); |
13549 | ||
13550 | if (!cur_proc_ptr) | |
13551 | { | |
13552 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13553 | demand_empty_rest_of_line (); | |
13554 | return; | |
13555 | } | |
13556 | ||
13557 | if (p != NULL) | |
13558 | { | |
13559 | assert (S_GET_NAME (p)); | |
13560 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13561 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13562 | |
13563 | if (debug_type == DEBUG_STABS) | |
13564 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13565 | S_GET_NAME (p)); | |
252b5132 RH |
13566 | } |
13567 | else | |
13568 | as_warn (_(".end directive missing or unknown symbol")); | |
13569 | ||
ecb4347a DJ |
13570 | #ifdef OBJ_ELF |
13571 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13572 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13573 | && mips_flag_pdr) | |
ecb4347a DJ |
13574 | { |
13575 | segT saved_seg = now_seg; | |
13576 | subsegT saved_subseg = now_subseg; | |
13577 | valueT dot; | |
13578 | expressionS exp; | |
13579 | char *fragp; | |
252b5132 | 13580 | |
ecb4347a | 13581 | dot = frag_now_fix (); |
252b5132 RH |
13582 | |
13583 | #ifdef md_flush_pending_output | |
ecb4347a | 13584 | md_flush_pending_output (); |
252b5132 RH |
13585 | #endif |
13586 | ||
ecb4347a DJ |
13587 | assert (pdr_seg); |
13588 | subseg_set (pdr_seg, 0); | |
252b5132 | 13589 | |
ecb4347a DJ |
13590 | /* Write the symbol. */ |
13591 | exp.X_op = O_symbol; | |
13592 | exp.X_add_symbol = p; | |
13593 | exp.X_add_number = 0; | |
13594 | emit_expr (&exp, 4); | |
252b5132 | 13595 | |
ecb4347a | 13596 | fragp = frag_more (7 * 4); |
252b5132 | 13597 | |
17a2f251 TS |
13598 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13599 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13600 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13601 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13602 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13603 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13604 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13605 | |
ecb4347a DJ |
13606 | subseg_set (saved_seg, saved_subseg); |
13607 | } | |
13608 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13609 | |
13610 | cur_proc_ptr = NULL; | |
13611 | } | |
13612 | ||
13613 | /* The .aent and .ent directives. */ | |
13614 | ||
13615 | static void | |
17a2f251 | 13616 | s_mips_ent (int aent) |
252b5132 | 13617 | { |
252b5132 | 13618 | symbolS *symbolP; |
252b5132 RH |
13619 | |
13620 | symbolP = get_symbol (); | |
13621 | if (*input_line_pointer == ',') | |
f9419b05 | 13622 | ++input_line_pointer; |
252b5132 | 13623 | SKIP_WHITESPACE (); |
3882b010 | 13624 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13625 | || *input_line_pointer == '-') |
874e8986 | 13626 | get_number (); |
252b5132 | 13627 | |
14949570 | 13628 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13629 | as_warn (_(".ent or .aent not in text section.")); |
13630 | ||
13631 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13632 | as_warn (_("missing .end")); |
252b5132 RH |
13633 | |
13634 | if (!aent) | |
13635 | { | |
7a621144 DJ |
13636 | /* This function needs its own .frame and .cprestore directives. */ |
13637 | mips_frame_reg_valid = 0; | |
13638 | mips_cprestore_valid = 0; | |
13639 | ||
252b5132 RH |
13640 | cur_proc_ptr = &cur_proc; |
13641 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13642 | ||
13643 | cur_proc_ptr->isym = symbolP; | |
13644 | ||
49309057 | 13645 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13646 | |
f9419b05 | 13647 | ++numprocs; |
ecb4347a DJ |
13648 | |
13649 | if (debug_type == DEBUG_STABS) | |
13650 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13651 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13652 | } |
13653 | ||
13654 | demand_empty_rest_of_line (); | |
13655 | } | |
13656 | ||
13657 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13658 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13659 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13660 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13661 | symbol table (in the mdebug section). */ |
13662 | ||
13663 | static void | |
17a2f251 | 13664 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13665 | { |
ecb4347a DJ |
13666 | #ifdef OBJ_ELF |
13667 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13668 | { | |
13669 | long val; | |
252b5132 | 13670 | |
ecb4347a DJ |
13671 | if (cur_proc_ptr == (procS *) NULL) |
13672 | { | |
13673 | as_warn (_(".frame outside of .ent")); | |
13674 | demand_empty_rest_of_line (); | |
13675 | return; | |
13676 | } | |
252b5132 | 13677 | |
ecb4347a DJ |
13678 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13679 | ||
13680 | SKIP_WHITESPACE (); | |
13681 | if (*input_line_pointer++ != ',' | |
13682 | || get_absolute_expression_and_terminator (&val) != ',') | |
13683 | { | |
13684 | as_warn (_("Bad .frame directive")); | |
13685 | --input_line_pointer; | |
13686 | demand_empty_rest_of_line (); | |
13687 | return; | |
13688 | } | |
252b5132 | 13689 | |
ecb4347a DJ |
13690 | cur_proc_ptr->frame_offset = val; |
13691 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13692 | |
252b5132 | 13693 | demand_empty_rest_of_line (); |
252b5132 | 13694 | } |
ecb4347a DJ |
13695 | else |
13696 | #endif /* OBJ_ELF */ | |
13697 | s_ignore (ignore); | |
252b5132 RH |
13698 | } |
13699 | ||
bdaaa2e1 KH |
13700 | /* The .fmask and .mask directives. If the mdebug section is present |
13701 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13702 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13703 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13704 | make reference to the ecoff symbol table (in the mdebug section). */ |
13705 | ||
13706 | static void | |
17a2f251 | 13707 | s_mips_mask (int reg_type) |
252b5132 | 13708 | { |
ecb4347a DJ |
13709 | #ifdef OBJ_ELF |
13710 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13711 | { |
ecb4347a | 13712 | long mask, off; |
252b5132 | 13713 | |
ecb4347a DJ |
13714 | if (cur_proc_ptr == (procS *) NULL) |
13715 | { | |
13716 | as_warn (_(".mask/.fmask outside of .ent")); | |
13717 | demand_empty_rest_of_line (); | |
13718 | return; | |
13719 | } | |
252b5132 | 13720 | |
ecb4347a DJ |
13721 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13722 | { | |
13723 | as_warn (_("Bad .mask/.fmask directive")); | |
13724 | --input_line_pointer; | |
13725 | demand_empty_rest_of_line (); | |
13726 | return; | |
13727 | } | |
252b5132 | 13728 | |
ecb4347a DJ |
13729 | off = get_absolute_expression (); |
13730 | ||
13731 | if (reg_type == 'F') | |
13732 | { | |
13733 | cur_proc_ptr->fpreg_mask = mask; | |
13734 | cur_proc_ptr->fpreg_offset = off; | |
13735 | } | |
13736 | else | |
13737 | { | |
13738 | cur_proc_ptr->reg_mask = mask; | |
13739 | cur_proc_ptr->reg_offset = off; | |
13740 | } | |
13741 | ||
13742 | demand_empty_rest_of_line (); | |
252b5132 RH |
13743 | } |
13744 | else | |
ecb4347a DJ |
13745 | #endif /* OBJ_ELF */ |
13746 | s_ignore (reg_type); | |
252b5132 RH |
13747 | } |
13748 | ||
13749 | /* The .loc directive. */ | |
13750 | ||
13751 | #if 0 | |
13752 | static void | |
17a2f251 | 13753 | s_loc (int x) |
252b5132 RH |
13754 | { |
13755 | symbolS *symbolP; | |
13756 | int lineno; | |
13757 | int addroff; | |
13758 | ||
13759 | assert (now_seg == text_section); | |
13760 | ||
13761 | lineno = get_number (); | |
13762 | addroff = frag_now_fix (); | |
13763 | ||
13764 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13765 | S_SET_TYPE (symbolP, N_SLINE); | |
13766 | S_SET_OTHER (symbolP, 0); | |
13767 | S_SET_DESC (symbolP, lineno); | |
13768 | symbolP->sy_segment = now_seg; | |
13769 | } | |
13770 | #endif | |
e7af610e | 13771 | |
316f5878 RS |
13772 | /* A table describing all the processors gas knows about. Names are |
13773 | matched in the order listed. | |
e7af610e | 13774 | |
316f5878 RS |
13775 | To ease comparison, please keep this table in the same order as |
13776 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13777 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13778 | { | |
316f5878 RS |
13779 | /* Entries for generic ISAs */ |
13780 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13781 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13782 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13783 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13784 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13785 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13786 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13787 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13788 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13789 | |
13790 | /* MIPS I */ | |
13791 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13792 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13793 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13794 | ||
13795 | /* MIPS II */ | |
13796 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13797 | ||
13798 | /* MIPS III */ | |
13799 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13800 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13801 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13802 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13803 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13804 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13805 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13806 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13807 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13808 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13809 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13810 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13811 | ||
13812 | /* MIPS IV */ | |
13813 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13814 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13815 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13816 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13817 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13818 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13819 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13820 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13821 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13822 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13823 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13824 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13825 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13826 | |
13827 | /* MIPS 32 */ | |
fef14a42 | 13828 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13829 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13830 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13831 | |
316f5878 RS |
13832 | /* MIPS 64 */ |
13833 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13834 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13835 | |
c7a23324 | 13836 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13837 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13838 | |
316f5878 RS |
13839 | /* End marker */ |
13840 | { NULL, 0, 0, 0 } | |
13841 | }; | |
e7af610e | 13842 | |
84ea6cf2 | 13843 | |
316f5878 RS |
13844 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13845 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13846 | |
316f5878 | 13847 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13848 | |
b34976b6 | 13849 | static bfd_boolean |
17a2f251 | 13850 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13851 | { |
13852 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13853 | given++, canonical++; | |
13854 | ||
13855 | return ((*given == 0 && *canonical == 0) | |
13856 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13857 | } | |
13858 | ||
13859 | ||
13860 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13861 | CPU name. We've traditionally allowed a lot of variation here. | |
13862 | ||
13863 | Note: this function is shared between GCC and GAS. */ | |
13864 | ||
b34976b6 | 13865 | static bfd_boolean |
17a2f251 | 13866 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13867 | { |
13868 | /* First see if the name matches exactly, or with a final "000" | |
13869 | turned into "k". */ | |
13870 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13871 | return TRUE; |
316f5878 RS |
13872 | |
13873 | /* If not, try comparing based on numerical designation alone. | |
13874 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13875 | if (TOLOWER (*given) == 'r') | |
13876 | given++; | |
13877 | if (!ISDIGIT (*given)) | |
b34976b6 | 13878 | return FALSE; |
316f5878 RS |
13879 | |
13880 | /* Skip over some well-known prefixes in the canonical name, | |
13881 | hoping to find a number there too. */ | |
13882 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13883 | canonical += 2; | |
13884 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13885 | canonical += 2; | |
13886 | else if (TOLOWER (canonical[0]) == 'r') | |
13887 | canonical += 1; | |
13888 | ||
13889 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13890 | } | |
13891 | ||
13892 | ||
13893 | /* Parse an option that takes the name of a processor as its argument. | |
13894 | OPTION is the name of the option and CPU_STRING is the argument. | |
13895 | Return the corresponding processor enumeration if the CPU_STRING is | |
13896 | recognized, otherwise report an error and return null. | |
13897 | ||
13898 | A similar function exists in GCC. */ | |
e7af610e NC |
13899 | |
13900 | static const struct mips_cpu_info * | |
17a2f251 | 13901 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13902 | { |
316f5878 | 13903 | const struct mips_cpu_info *p; |
e7af610e | 13904 | |
316f5878 RS |
13905 | /* 'from-abi' selects the most compatible architecture for the given |
13906 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13907 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13908 | version. Look first at the -mgp options, if given, otherwise base | |
13909 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13910 | |
316f5878 RS |
13911 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13912 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13913 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13914 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13915 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13916 | { | |
13917 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13918 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13919 | ||
13920 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13921 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13922 | ||
13923 | if (file_mips_gp32 >= 0) | |
13924 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13925 | ||
13926 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13927 | ? ISA_MIPS3 | |
13928 | : ISA_MIPS1); | |
13929 | } | |
13930 | ||
13931 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13932 | if (strcasecmp (cpu_string, "default") == 0) | |
13933 | return 0; | |
13934 | ||
13935 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13936 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13937 | return p; | |
13938 | ||
13939 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13940 | return 0; | |
e7af610e NC |
13941 | } |
13942 | ||
316f5878 RS |
13943 | /* Return the canonical processor information for ISA (a member of the |
13944 | ISA_MIPS* enumeration). */ | |
13945 | ||
e7af610e | 13946 | static const struct mips_cpu_info * |
17a2f251 | 13947 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13948 | { |
13949 | int i; | |
13950 | ||
13951 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13952 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13953 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13954 | return (&mips_cpu_info_table[i]); |
13955 | ||
e972090a | 13956 | return NULL; |
e7af610e | 13957 | } |
fef14a42 TS |
13958 | |
13959 | static const struct mips_cpu_info * | |
17a2f251 | 13960 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13961 | { |
13962 | int i; | |
13963 | ||
13964 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13965 | if (arch == mips_cpu_info_table[i].cpu) | |
13966 | return (&mips_cpu_info_table[i]); | |
13967 | ||
13968 | return NULL; | |
13969 | } | |
316f5878 RS |
13970 | \f |
13971 | static void | |
17a2f251 | 13972 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13973 | { |
13974 | if (*first_p) | |
13975 | { | |
13976 | fprintf (stream, "%24s", ""); | |
13977 | *col_p = 24; | |
13978 | } | |
13979 | else | |
13980 | { | |
13981 | fprintf (stream, ", "); | |
13982 | *col_p += 2; | |
13983 | } | |
e7af610e | 13984 | |
316f5878 RS |
13985 | if (*col_p + strlen (string) > 72) |
13986 | { | |
13987 | fprintf (stream, "\n%24s", ""); | |
13988 | *col_p = 24; | |
13989 | } | |
13990 | ||
13991 | fprintf (stream, "%s", string); | |
13992 | *col_p += strlen (string); | |
13993 | ||
13994 | *first_p = 0; | |
13995 | } | |
13996 | ||
13997 | void | |
17a2f251 | 13998 | md_show_usage (FILE *stream) |
e7af610e | 13999 | { |
316f5878 RS |
14000 | int column, first; |
14001 | size_t i; | |
14002 | ||
14003 | fprintf (stream, _("\ | |
14004 | MIPS options:\n\ | |
316f5878 RS |
14005 | -EB generate big endian output\n\ |
14006 | -EL generate little endian output\n\ | |
14007 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14008 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14009 | implicitly with the gp register [default 8]\n")); | |
14010 | fprintf (stream, _("\ | |
14011 | -mips1 generate MIPS ISA I instructions\n\ | |
14012 | -mips2 generate MIPS ISA II instructions\n\ | |
14013 | -mips3 generate MIPS ISA III instructions\n\ | |
14014 | -mips4 generate MIPS ISA IV instructions\n\ | |
14015 | -mips5 generate MIPS ISA V instructions\n\ | |
14016 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14017 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14018 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14019 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14020 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14021 | ||
14022 | first = 1; | |
e7af610e NC |
14023 | |
14024 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14025 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14026 | show (stream, "from-abi", &column, &first); | |
14027 | fputc ('\n', stream); | |
e7af610e | 14028 | |
316f5878 RS |
14029 | fprintf (stream, _("\ |
14030 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14031 | -no-mCPU don't generate code specific to CPU.\n\ | |
14032 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14033 | ||
14034 | first = 1; | |
14035 | ||
14036 | show (stream, "3900", &column, &first); | |
14037 | show (stream, "4010", &column, &first); | |
14038 | show (stream, "4100", &column, &first); | |
14039 | show (stream, "4650", &column, &first); | |
14040 | fputc ('\n', stream); | |
14041 | ||
14042 | fprintf (stream, _("\ | |
14043 | -mips16 generate mips16 instructions\n\ | |
14044 | -no-mips16 do not generate mips16 instructions\n")); | |
14045 | fprintf (stream, _("\ | |
d766e8ec | 14046 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14047 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14048 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14049 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14050 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14051 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14052 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14053 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14054 | #ifdef OBJ_ELF | |
14055 | fprintf (stream, _("\ | |
14056 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14057 | -non_shared do not generate position independent code\n\ | |
14058 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14059 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14060 | -mabi=ABI create ABI conformant object file for:\n")); |
14061 | ||
14062 | first = 1; | |
14063 | ||
14064 | show (stream, "32", &column, &first); | |
14065 | show (stream, "o64", &column, &first); | |
14066 | show (stream, "n32", &column, &first); | |
14067 | show (stream, "64", &column, &first); | |
14068 | show (stream, "eabi", &column, &first); | |
14069 | ||
14070 | fputc ('\n', stream); | |
14071 | ||
14072 | fprintf (stream, _("\ | |
14073 | -32 create o32 ABI object file (default)\n\ | |
14074 | -n32 create n32 ABI object file\n\ | |
14075 | -64 create 64 ABI object file\n")); | |
14076 | #endif | |
e7af610e | 14077 | } |
14e777e0 KB |
14078 | |
14079 | enum dwarf2_format | |
17a2f251 | 14080 | mips_dwarf2_format (void) |
14e777e0 KB |
14081 | { |
14082 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14083 | { |
14084 | #ifdef TE_IRIX | |
14085 | return dwarf2_format_64bit_irix; | |
14086 | #else | |
14087 | return dwarf2_format_64bit; | |
14088 | #endif | |
14089 | } | |
14e777e0 KB |
14090 | else |
14091 | return dwarf2_format_32bit; | |
14092 | } | |
73369e65 EC |
14093 | |
14094 | int | |
14095 | mips_dwarf2_addr_size (void) | |
14096 | { | |
14097 | if (mips_abi == N64_ABI) | |
14098 | return 8; | |
73369e65 EC |
14099 | else |
14100 | return 4; | |
14101 | } |