Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
252b5132 RH |
139 | /* This is the set of options which may be modified by the .set |
140 | pseudo-op. We use a struct so that .set push and .set pop are more | |
141 | reliable. */ | |
142 | ||
e972090a NC |
143 | struct mips_set_options |
144 | { | |
252b5132 RH |
145 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
146 | if it has not been initialized. Changed by `.set mipsN', and the | |
147 | -mipsN command line option, and the default CPU. */ | |
148 | int isa; | |
1f25f5d3 CD |
149 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
150 | if they have not been initialized. Changed by `.set <asename>', by | |
151 | command line options, and based on the default architecture. */ | |
152 | int ase_mips3d; | |
deec1734 | 153 | int ase_mdmx; |
252b5132 RH |
154 | /* Whether we are assembling for the mips16 processor. 0 if we are |
155 | not, 1 if we are, and -1 if the value has not been initialized. | |
156 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
157 | -nomips16 command line options, and the default CPU. */ | |
158 | int mips16; | |
159 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
160 | reorder' and `.set noreorder'. */ | |
161 | int noreorder; | |
162 | /* Non-zero if we should not permit the $at ($1) register to be used | |
163 | in instructions. Changed by `.set at' and `.set noat'. */ | |
164 | int noat; | |
165 | /* Non-zero if we should warn when a macro instruction expands into | |
166 | more than one machine instruction. Changed by `.set nomacro' and | |
167 | `.set macro'. */ | |
168 | int warn_about_macros; | |
169 | /* Non-zero if we should not move instructions. Changed by `.set | |
170 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
171 | int nomove; | |
172 | /* Non-zero if we should not optimize branches by moving the target | |
173 | of the branch into the delay slot. Actually, we don't perform | |
174 | this optimization anyhow. Changed by `.set bopt' and `.set | |
175 | nobopt'. */ | |
176 | int nobopt; | |
177 | /* Non-zero if we should not autoextend mips16 instructions. | |
178 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
179 | int noautoextend; | |
a325df1d TS |
180 | /* Restrict general purpose registers and floating point registers |
181 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
182 | is passed but can changed if the assembler code uses .set mipsN. */ | |
183 | int gp32; | |
184 | int fp32; | |
fef14a42 TS |
185 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
186 | command line option, and the default CPU. */ | |
187 | int arch; | |
252b5132 RH |
188 | }; |
189 | ||
a325df1d | 190 | /* True if -mgp32 was passed. */ |
a8e8e863 | 191 | static int file_mips_gp32 = -1; |
a325df1d TS |
192 | |
193 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 194 | static int file_mips_fp32 = -1; |
a325df1d | 195 | |
252b5132 | 196 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 197 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 198 | -1 to indicate that they have not been initialized. */ |
252b5132 | 199 | |
e972090a NC |
200 | static struct mips_set_options mips_opts = |
201 | { | |
fef14a42 | 202 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 203 | }; |
252b5132 RH |
204 | |
205 | /* These variables are filled in with the masks of registers used. | |
206 | The object format code reads them and puts them in the appropriate | |
207 | place. */ | |
208 | unsigned long mips_gprmask; | |
209 | unsigned long mips_cprmask[4]; | |
210 | ||
211 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 212 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 213 | |
a4672219 TS |
214 | /* True if -mips16 was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mips16; | |
217 | ||
1f25f5d3 CD |
218 | /* True if -mips3d was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips3d; | |
221 | ||
deec1734 CD |
222 | /* True if -mdmx was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mdmx; | |
225 | ||
ec68c924 | 226 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 227 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 228 | static const char *mips_arch_string; |
ec68c924 EC |
229 | |
230 | /* The argument of the -mtune= flag. The architecture for which we | |
231 | are optimizing. */ | |
232 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 233 | static const char *mips_tune_string; |
ec68c924 | 234 | |
316f5878 | 235 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
236 | static int mips_32bitmode = 0; |
237 | ||
316f5878 RS |
238 | /* True if the given ABI requires 32-bit registers. */ |
239 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
240 | ||
241 | /* Likewise 64-bit registers. */ | |
242 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
243 | ((ABI) == N32_ABI \ | |
244 | || (ABI) == N64_ABI \ | |
245 | || (ABI) == O64_ABI) | |
246 | ||
bdaaa2e1 | 247 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 248 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
249 | (ISA) == ISA_MIPS3 \ |
250 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 251 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 252 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 253 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
254 | ) |
255 | ||
af7ee8bf CD |
256 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
257 | instructions. */ | |
258 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 259 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
260 | ) |
261 | ||
262 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
263 | instructions. */ | |
264 | #define ISA_HAS_ROR(ISA) ( \ | |
265 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 266 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
267 | ) |
268 | ||
e013f690 | 269 | #define HAVE_32BIT_GPRS \ |
316f5878 | 270 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 271 | |
e013f690 | 272 | #define HAVE_32BIT_FPRS \ |
316f5878 | 273 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
274 | |
275 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
276 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
277 | ||
316f5878 | 278 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 279 | |
316f5878 | 280 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 281 | |
3e722fb5 | 282 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
283 | #define HAVE_32BIT_ADDRESSES \ |
284 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
285 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
286 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
287 | |
288 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 289 | |
b7c7d6c1 TS |
290 | /* Addresses are loaded in different ways, depending on the address size |
291 | in use. The n32 ABI Documentation also mandates the use of additions | |
292 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 293 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 294 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
295 | |
296 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 297 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
298 | |
299 | #define ADDRESS_LOAD_INSN \ | |
300 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
301 | ||
302 | #define ADDRESS_STORE_INSN \ | |
303 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
304 | ||
a4672219 | 305 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
306 | #define CPU_HAS_MIPS16(cpu) \ |
307 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
308 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 309 | |
1f25f5d3 CD |
310 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
311 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
312 | ) | |
313 | ||
deec1734 | 314 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 315 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
316 | ) |
317 | ||
60b63b72 RS |
318 | /* True if CPU has a dror instruction. */ |
319 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
320 | ||
321 | /* True if CPU has a ror instruction. */ | |
322 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
323 | ||
c8978940 CD |
324 | /* True if mflo and mfhi can be immediately followed by instructions |
325 | which write to the HI and LO registers. | |
326 | ||
327 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
328 | (at least) two instructions between the reads of HI/LO and | |
329 | instructions which write them, and later ISAs do not. Contradicting | |
330 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
331 | the UM for the NEC Vr5000) document needing the instructions between | |
332 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
333 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
334 | earlier-ISA CPUs for which CPU documentation declares that the | |
335 | instructions are really interlocked. */ | |
336 | #define hilo_interlocks \ | |
337 | (mips_opts.isa == ISA_MIPS32 \ | |
338 | || mips_opts.isa == ISA_MIPS32R2 \ | |
339 | || mips_opts.isa == ISA_MIPS64 \ | |
340 | || mips_opts.isa == ISA_MIPS64R2 \ | |
341 | || mips_opts.arch == CPU_R4010 \ | |
342 | || mips_opts.arch == CPU_R10000 \ | |
343 | || mips_opts.arch == CPU_R12000 \ | |
344 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
345 | || mips_opts.arch == CPU_VR5500 \ |
346 | ) | |
252b5132 RH |
347 | |
348 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
349 | from the GPRs after they are loaded from memory, and thus does not |
350 | require nops to be inserted. This applies to instructions marked | |
351 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
352 | level I. */ | |
252b5132 | 353 | #define gpr_interlocks \ |
e7af610e | 354 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 355 | || mips_opts.arch == CPU_R3900) |
252b5132 | 356 | |
81912461 ILT |
357 | /* Whether the processor uses hardware interlocks to avoid delays |
358 | required by coprocessor instructions, and thus does not require | |
359 | nops to be inserted. This applies to instructions marked | |
360 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
361 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
362 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
363 | levels I, II, and III. */ | |
bdaaa2e1 | 364 | /* Itbl support may require additional care here. */ |
81912461 ILT |
365 | #define cop_interlocks \ |
366 | ((mips_opts.isa != ISA_MIPS1 \ | |
367 | && mips_opts.isa != ISA_MIPS2 \ | |
368 | && mips_opts.isa != ISA_MIPS3) \ | |
369 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
370 | ) |
371 | ||
372 | /* Whether the processor uses hardware interlocks to protect reads | |
373 | from coprocessor registers after they are loaded from memory, and | |
374 | thus does not require nops to be inserted. This applies to | |
375 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
376 | requires at MIPS ISA level I. */ | |
377 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 378 | |
6b76fefe CM |
379 | /* Is this a mfhi or mflo instruction? */ |
380 | #define MF_HILO_INSN(PINFO) \ | |
381 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
382 | ||
252b5132 RH |
383 | /* MIPS PIC level. */ |
384 | ||
a161fe53 | 385 | enum mips_pic_level mips_pic; |
252b5132 | 386 | |
c9914766 | 387 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 388 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 389 | static int mips_big_got = 0; |
252b5132 RH |
390 | |
391 | /* 1 if trap instructions should used for overflow rather than break | |
392 | instructions. */ | |
c9914766 | 393 | static int mips_trap = 0; |
252b5132 | 394 | |
119d663a | 395 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 396 | by assembling two single width halves into two single width floating |
119d663a NC |
397 | point registers which just happen to alias the double width destination |
398 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 399 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
400 | automatically at assemble time. */ |
401 | static int mips_disable_float_construction; | |
402 | ||
252b5132 RH |
403 | /* Non-zero if any .set noreorder directives were used. */ |
404 | ||
405 | static int mips_any_noreorder; | |
406 | ||
6b76fefe CM |
407 | /* Non-zero if nops should be inserted when the register referenced in |
408 | an mfhi/mflo instruction is read in the next two instructions. */ | |
409 | static int mips_7000_hilo_fix; | |
410 | ||
252b5132 | 411 | /* The size of the small data section. */ |
156c2f8b | 412 | static unsigned int g_switch_value = 8; |
252b5132 RH |
413 | /* Whether the -G option was used. */ |
414 | static int g_switch_seen = 0; | |
415 | ||
416 | #define N_RMASK 0xc4 | |
417 | #define N_VFP 0xd4 | |
418 | ||
419 | /* If we can determine in advance that GP optimization won't be | |
420 | possible, we can skip the relaxation stuff that tries to produce | |
421 | GP-relative references. This makes delay slot optimization work | |
422 | better. | |
423 | ||
424 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
425 | gcc output. It needs to guess right for gcc, otherwise gcc |
426 | will put what it thinks is a GP-relative instruction in a branch | |
427 | delay slot. | |
252b5132 RH |
428 | |
429 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
430 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 431 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
432 | |
433 | /* handle of the OPCODE hash table */ | |
434 | static struct hash_control *op_hash = NULL; | |
435 | ||
436 | /* The opcode hash table we use for the mips16. */ | |
437 | static struct hash_control *mips16_op_hash = NULL; | |
438 | ||
439 | /* This array holds the chars that always start a comment. If the | |
440 | pre-processor is disabled, these aren't very useful */ | |
441 | const char comment_chars[] = "#"; | |
442 | ||
443 | /* This array holds the chars that only start a comment at the beginning of | |
444 | a line. If the line seems to have the form '# 123 filename' | |
445 | .line and .file directives will appear in the pre-processed output */ | |
446 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
447 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 448 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
449 | /* Also note that C style comments are always supported. */ |
450 | const char line_comment_chars[] = "#"; | |
451 | ||
bdaaa2e1 | 452 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 453 | const char line_separator_chars[] = ";"; |
252b5132 RH |
454 | |
455 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
456 | const char EXP_CHARS[] = "eE"; | |
457 | ||
458 | /* Chars that mean this number is a floating point constant */ | |
459 | /* As in 0f12.456 */ | |
460 | /* or 0d1.2345e12 */ | |
461 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
462 | ||
463 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
464 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
465 | but nothing is ideal around here. | |
466 | */ | |
467 | ||
468 | static char *insn_error; | |
469 | ||
470 | static int auto_align = 1; | |
471 | ||
472 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
473 | offset in the stack frame from which to restore the $gp register. | |
474 | This is set by the .cprestore pseudo-op, and saved in this | |
475 | variable. */ | |
476 | static offsetT mips_cprestore_offset = -1; | |
477 | ||
67c1ffbe | 478 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 479 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 480 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
481 | static offsetT mips_cpreturn_offset = -1; |
482 | static int mips_cpreturn_register = -1; | |
483 | static int mips_gp_register = GP; | |
def2e0dd | 484 | static int mips_gprel_offset = 0; |
6478892d | 485 | |
7a621144 DJ |
486 | /* Whether mips_cprestore_offset has been set in the current function |
487 | (or whether it has already been warned about, if not). */ | |
488 | static int mips_cprestore_valid = 0; | |
489 | ||
252b5132 RH |
490 | /* This is the register which holds the stack frame, as set by the |
491 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
492 | static int mips_frame_reg = SP; | |
493 | ||
7a621144 DJ |
494 | /* Whether mips_frame_reg has been set in the current function |
495 | (or whether it has already been warned about, if not). */ | |
496 | static int mips_frame_reg_valid = 0; | |
497 | ||
252b5132 RH |
498 | /* To output NOP instructions correctly, we need to keep information |
499 | about the previous two instructions. */ | |
500 | ||
501 | /* Whether we are optimizing. The default value of 2 means to remove | |
502 | unneeded NOPs and swap branch instructions when possible. A value | |
503 | of 1 means to not swap branches. A value of 0 means to always | |
504 | insert NOPs. */ | |
505 | static int mips_optimize = 2; | |
506 | ||
507 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
508 | equivalent to seeing no -g option at all. */ | |
509 | static int mips_debug = 0; | |
510 | ||
511 | /* The previous instruction. */ | |
512 | static struct mips_cl_insn prev_insn; | |
513 | ||
514 | /* The instruction before prev_insn. */ | |
515 | static struct mips_cl_insn prev_prev_insn; | |
516 | ||
517 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
518 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 519 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
520 | |
521 | /* Non-zero if prev_insn is valid. */ | |
522 | static int prev_insn_valid; | |
523 | ||
524 | /* The frag for the previous instruction. */ | |
525 | static struct frag *prev_insn_frag; | |
526 | ||
527 | /* The offset into prev_insn_frag for the previous instruction. */ | |
528 | static long prev_insn_where; | |
529 | ||
530 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 531 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
532 | |
533 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 534 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
535 | |
536 | /* Non-zero if the previous instruction was in a delay slot. */ | |
537 | static int prev_insn_is_delay_slot; | |
538 | ||
539 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
540 | static int prev_insn_unreordered; | |
541 | ||
542 | /* Non-zero if the previous instruction uses an extend opcode (if | |
543 | mips16). */ | |
544 | static int prev_insn_extended; | |
545 | ||
546 | /* Non-zero if the previous previous instruction was in a .set | |
547 | noreorder. */ | |
548 | static int prev_prev_insn_unreordered; | |
549 | ||
550 | /* If this is set, it points to a frag holding nop instructions which | |
551 | were inserted before the start of a noreorder section. If those | |
552 | nops turn out to be unnecessary, the size of the frag can be | |
553 | decreased. */ | |
554 | static fragS *prev_nop_frag; | |
555 | ||
556 | /* The number of nop instructions we created in prev_nop_frag. */ | |
557 | static int prev_nop_frag_holds; | |
558 | ||
559 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 560 | prev_nop_frag. */ |
252b5132 RH |
561 | static int prev_nop_frag_required; |
562 | ||
563 | /* The number of instructions we've seen since prev_nop_frag. */ | |
564 | static int prev_nop_frag_since; | |
565 | ||
566 | /* For ECOFF and ELF, relocations against symbols are done in two | |
567 | parts, with a HI relocation and a LO relocation. Each relocation | |
568 | has only 16 bits of space to store an addend. This means that in | |
569 | order for the linker to handle carries correctly, it must be able | |
570 | to locate both the HI and the LO relocation. This means that the | |
571 | relocations must appear in order in the relocation table. | |
572 | ||
573 | In order to implement this, we keep track of each unmatched HI | |
574 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 575 | corresponding LO relocation. */ |
252b5132 | 576 | |
e972090a NC |
577 | struct mips_hi_fixup |
578 | { | |
252b5132 RH |
579 | /* Next HI fixup. */ |
580 | struct mips_hi_fixup *next; | |
581 | /* This fixup. */ | |
582 | fixS *fixp; | |
583 | /* The section this fixup is in. */ | |
584 | segT seg; | |
585 | }; | |
586 | ||
587 | /* The list of unmatched HI relocs. */ | |
588 | ||
589 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
590 | ||
64bdfcaf RS |
591 | /* The frag containing the last explicit relocation operator. |
592 | Null if explicit relocations have not been used. */ | |
593 | ||
594 | static fragS *prev_reloc_op_frag; | |
595 | ||
252b5132 RH |
596 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
597 | ||
598 | #define X ILLEGAL_REG | |
e972090a NC |
599 | static const int mips32_to_16_reg_map[] = |
600 | { | |
252b5132 RH |
601 | X, X, 2, 3, 4, 5, 6, 7, |
602 | X, X, X, X, X, X, X, X, | |
603 | 0, 1, X, X, X, X, X, X, | |
604 | X, X, X, X, X, X, X, X | |
605 | }; | |
606 | #undef X | |
607 | ||
608 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
609 | ||
e972090a NC |
610 | static const unsigned int mips16_to_32_reg_map[] = |
611 | { | |
252b5132 RH |
612 | 16, 17, 2, 3, 4, 5, 6, 7 |
613 | }; | |
60b63b72 | 614 | |
d766e8ec | 615 | static int mips_fix_vr4120; |
4a6a3df4 AO |
616 | |
617 | /* We don't relax branches by default, since this causes us to expand | |
618 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
619 | fail to compute the offset before expanding the macro to the most | |
620 | efficient expansion. */ | |
621 | ||
622 | static int mips_relax_branch; | |
252b5132 | 623 | \f |
4d7206a2 RS |
624 | /* The expansion of many macros depends on the type of symbol that |
625 | they refer to. For example, when generating position-dependent code, | |
626 | a macro that refers to a symbol may have two different expansions, | |
627 | one which uses GP-relative addresses and one which uses absolute | |
628 | addresses. When generating SVR4-style PIC, a macro may have | |
629 | different expansions for local and global symbols. | |
630 | ||
631 | We handle these situations by generating both sequences and putting | |
632 | them in variant frags. In position-dependent code, the first sequence | |
633 | will be the GP-relative one and the second sequence will be the | |
634 | absolute one. In SVR4 PIC, the first sequence will be for global | |
635 | symbols and the second will be for local symbols. | |
636 | ||
584892a6 RS |
637 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
638 | SECOND are the lengths of the two sequences in bytes. These fields | |
639 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
640 | the subtype has the following flags: | |
4d7206a2 | 641 | |
584892a6 RS |
642 | RELAX_USE_SECOND |
643 | Set if it has been decided that we should use the second | |
644 | sequence instead of the first. | |
645 | ||
646 | RELAX_SECOND_LONGER | |
647 | Set in the first variant frag if the macro's second implementation | |
648 | is longer than its first. This refers to the macro as a whole, | |
649 | not an individual relaxation. | |
650 | ||
651 | RELAX_NOMACRO | |
652 | Set in the first variant frag if the macro appeared in a .set nomacro | |
653 | block and if one alternative requires a warning but the other does not. | |
654 | ||
655 | RELAX_DELAY_SLOT | |
656 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
657 | delay slot. | |
4d7206a2 RS |
658 | |
659 | The frag's "opcode" points to the first fixup for relaxable code. | |
660 | ||
661 | Relaxable macros are generated using a sequence such as: | |
662 | ||
663 | relax_start (SYMBOL); | |
664 | ... generate first expansion ... | |
665 | relax_switch (); | |
666 | ... generate second expansion ... | |
667 | relax_end (); | |
668 | ||
669 | The code and fixups for the unwanted alternative are discarded | |
670 | by md_convert_frag. */ | |
584892a6 | 671 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 672 | |
584892a6 RS |
673 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
674 | #define RELAX_SECOND(X) ((X) & 0xff) | |
675 | #define RELAX_USE_SECOND 0x10000 | |
676 | #define RELAX_SECOND_LONGER 0x20000 | |
677 | #define RELAX_NOMACRO 0x40000 | |
678 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 679 | |
4a6a3df4 AO |
680 | /* Branch without likely bit. If label is out of range, we turn: |
681 | ||
682 | beq reg1, reg2, label | |
683 | delay slot | |
684 | ||
685 | into | |
686 | ||
687 | bne reg1, reg2, 0f | |
688 | nop | |
689 | j label | |
690 | 0: delay slot | |
691 | ||
692 | with the following opcode replacements: | |
693 | ||
694 | beq <-> bne | |
695 | blez <-> bgtz | |
696 | bltz <-> bgez | |
697 | bc1f <-> bc1t | |
698 | ||
699 | bltzal <-> bgezal (with jal label instead of j label) | |
700 | ||
701 | Even though keeping the delay slot instruction in the delay slot of | |
702 | the branch would be more efficient, it would be very tricky to do | |
703 | correctly, because we'd have to introduce a variable frag *after* | |
704 | the delay slot instruction, and expand that instead. Let's do it | |
705 | the easy way for now, even if the branch-not-taken case now costs | |
706 | one additional instruction. Out-of-range branches are not supposed | |
707 | to be common, anyway. | |
708 | ||
709 | Branch likely. If label is out of range, we turn: | |
710 | ||
711 | beql reg1, reg2, label | |
712 | delay slot (annulled if branch not taken) | |
713 | ||
714 | into | |
715 | ||
716 | beql reg1, reg2, 1f | |
717 | nop | |
718 | beql $0, $0, 2f | |
719 | nop | |
720 | 1: j[al] label | |
721 | delay slot (executed only if branch taken) | |
722 | 2: | |
723 | ||
724 | It would be possible to generate a shorter sequence by losing the | |
725 | likely bit, generating something like: | |
b34976b6 | 726 | |
4a6a3df4 AO |
727 | bne reg1, reg2, 0f |
728 | nop | |
729 | j[al] label | |
730 | delay slot (executed only if branch taken) | |
731 | 0: | |
732 | ||
733 | beql -> bne | |
734 | bnel -> beq | |
735 | blezl -> bgtz | |
736 | bgtzl -> blez | |
737 | bltzl -> bgez | |
738 | bgezl -> bltz | |
739 | bc1fl -> bc1t | |
740 | bc1tl -> bc1f | |
741 | ||
742 | bltzall -> bgezal (with jal label instead of j label) | |
743 | bgezall -> bltzal (ditto) | |
744 | ||
745 | ||
746 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 747 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
748 | ((relax_substateT) \ |
749 | (0xc0000000 \ | |
750 | | ((toofar) ? 1 : 0) \ | |
751 | | ((link) ? 2 : 0) \ | |
752 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 753 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 754 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
755 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
756 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
757 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 758 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 759 | |
252b5132 RH |
760 | /* For mips16 code, we use an entirely different form of relaxation. |
761 | mips16 supports two versions of most instructions which take | |
762 | immediate values: a small one which takes some small value, and a | |
763 | larger one which takes a 16 bit value. Since branches also follow | |
764 | this pattern, relaxing these values is required. | |
765 | ||
766 | We can assemble both mips16 and normal MIPS code in a single | |
767 | object. Therefore, we need to support this type of relaxation at | |
768 | the same time that we support the relaxation described above. We | |
769 | use the high bit of the subtype field to distinguish these cases. | |
770 | ||
771 | The information we store for this type of relaxation is the | |
772 | argument code found in the opcode file for this relocation, whether | |
773 | the user explicitly requested a small or extended form, and whether | |
774 | the relocation is in a jump or jal delay slot. That tells us the | |
775 | size of the value, and how it should be stored. We also store | |
776 | whether the fragment is considered to be extended or not. We also | |
777 | store whether this is known to be a branch to a different section, | |
778 | whether we have tried to relax this frag yet, and whether we have | |
779 | ever extended a PC relative fragment because of a shift count. */ | |
780 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
781 | (0x80000000 \ | |
782 | | ((type) & 0xff) \ | |
783 | | ((small) ? 0x100 : 0) \ | |
784 | | ((ext) ? 0x200 : 0) \ | |
785 | | ((dslot) ? 0x400 : 0) \ | |
786 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 787 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
788 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
789 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
790 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
791 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
792 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
793 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
794 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
795 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
796 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
797 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
798 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
799 | |
800 | /* Is the given value a sign-extended 32-bit value? */ | |
801 | #define IS_SEXT_32BIT_NUM(x) \ | |
802 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
803 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
804 | ||
805 | /* Is the given value a sign-extended 16-bit value? */ | |
806 | #define IS_SEXT_16BIT_NUM(x) \ | |
807 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
808 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
809 | ||
4d7206a2 RS |
810 | \f |
811 | /* Global variables used when generating relaxable macros. See the | |
812 | comment above RELAX_ENCODE for more details about how relaxation | |
813 | is used. */ | |
814 | static struct { | |
815 | /* 0 if we're not emitting a relaxable macro. | |
816 | 1 if we're emitting the first of the two relaxation alternatives. | |
817 | 2 if we're emitting the second alternative. */ | |
818 | int sequence; | |
819 | ||
820 | /* The first relaxable fixup in the current frag. (In other words, | |
821 | the first fixup that refers to relaxable code.) */ | |
822 | fixS *first_fixup; | |
823 | ||
824 | /* sizes[0] says how many bytes of the first alternative are stored in | |
825 | the current frag. Likewise sizes[1] for the second alternative. */ | |
826 | unsigned int sizes[2]; | |
827 | ||
828 | /* The symbol on which the choice of sequence depends. */ | |
829 | symbolS *symbol; | |
830 | } mips_relax; | |
252b5132 | 831 | \f |
584892a6 RS |
832 | /* Global variables used to decide whether a macro needs a warning. */ |
833 | static struct { | |
834 | /* True if the macro is in a branch delay slot. */ | |
835 | bfd_boolean delay_slot_p; | |
836 | ||
837 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
838 | in bytes and sizes[1] is the length of the second alternative. | |
839 | For non-relaxable macros, both elements give the length of the | |
840 | macro in bytes. */ | |
841 | unsigned int sizes[2]; | |
842 | ||
843 | /* The first variant frag for this macro. */ | |
844 | fragS *first_frag; | |
845 | } mips_macro_warning; | |
846 | \f | |
252b5132 RH |
847 | /* Prototypes for static functions. */ |
848 | ||
17a2f251 | 849 | #define internalError() \ |
252b5132 | 850 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
851 | |
852 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
853 | ||
b34976b6 | 854 | static void append_insn |
4d7206a2 | 855 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 856 | static void mips_no_prev_insn (int); |
b34976b6 | 857 | static void mips16_macro_build |
67c0d1eb RS |
858 | (expressionS *, const char *, const char *, va_list); |
859 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
860 | static void macro_start (void); |
861 | static void macro_end (void); | |
17a2f251 TS |
862 | static void macro (struct mips_cl_insn * ip); |
863 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 864 | #ifdef LOSING_COMPILER |
17a2f251 | 865 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 866 | #endif |
17a2f251 TS |
867 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
868 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 869 | static void mips16_immed |
17a2f251 TS |
870 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
871 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 872 | static size_t my_getSmallExpression |
17a2f251 TS |
873 | (expressionS *, bfd_reloc_code_real_type *, char *); |
874 | static void my_getExpression (expressionS *, char *); | |
875 | static void s_align (int); | |
876 | static void s_change_sec (int); | |
877 | static void s_change_section (int); | |
878 | static void s_cons (int); | |
879 | static void s_float_cons (int); | |
880 | static void s_mips_globl (int); | |
881 | static void s_option (int); | |
882 | static void s_mipsset (int); | |
883 | static void s_abicalls (int); | |
884 | static void s_cpload (int); | |
885 | static void s_cpsetup (int); | |
886 | static void s_cplocal (int); | |
887 | static void s_cprestore (int); | |
888 | static void s_cpreturn (int); | |
889 | static void s_gpvalue (int); | |
890 | static void s_gpword (int); | |
891 | static void s_gpdword (int); | |
892 | static void s_cpadd (int); | |
893 | static void s_insn (int); | |
894 | static void md_obj_begin (void); | |
895 | static void md_obj_end (void); | |
896 | static void s_mips_ent (int); | |
897 | static void s_mips_end (int); | |
898 | static void s_mips_frame (int); | |
899 | static void s_mips_mask (int reg_type); | |
900 | static void s_mips_stab (int); | |
901 | static void s_mips_weakext (int); | |
902 | static void s_mips_file (int); | |
903 | static void s_mips_loc (int); | |
904 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 905 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 906 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
907 | |
908 | /* Table and functions used to map between CPU/ISA names, and | |
909 | ISA levels, and CPU numbers. */ | |
910 | ||
e972090a NC |
911 | struct mips_cpu_info |
912 | { | |
e7af610e NC |
913 | const char *name; /* CPU or ISA name. */ |
914 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
915 | int isa; /* ISA level. */ | |
916 | int cpu; /* CPU number (default CPU if ISA). */ | |
917 | }; | |
918 | ||
17a2f251 TS |
919 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
920 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
921 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
922 | \f |
923 | /* Pseudo-op table. | |
924 | ||
925 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
926 | should be defined here, but are currently unsupported: .alias, | |
927 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
928 | ||
929 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
930 | specific to the type of debugging information being generated, and | |
931 | should be defined by the object format: .aent, .begin, .bend, | |
932 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
933 | .vreg. | |
934 | ||
935 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
936 | not MIPS CPU specific, but are also not specific to the object file | |
937 | format. This file is probably the best place to define them, but | |
938 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
939 | .struct. */ | |
940 | ||
e972090a NC |
941 | static const pseudo_typeS mips_pseudo_table[] = |
942 | { | |
beae10d5 | 943 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
944 | {"option", s_option, 0}, |
945 | {"set", s_mipsset, 0}, | |
946 | {"rdata", s_change_sec, 'r'}, | |
947 | {"sdata", s_change_sec, 's'}, | |
948 | {"livereg", s_ignore, 0}, | |
949 | {"abicalls", s_abicalls, 0}, | |
950 | {"cpload", s_cpload, 0}, | |
6478892d TS |
951 | {"cpsetup", s_cpsetup, 0}, |
952 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 953 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
954 | {"cpreturn", s_cpreturn, 0}, |
955 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 956 | {"gpword", s_gpword, 0}, |
10181a0d | 957 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
958 | {"cpadd", s_cpadd, 0}, |
959 | {"insn", s_insn, 0}, | |
960 | ||
beae10d5 | 961 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
962 | chips. */ |
963 | {"asciiz", stringer, 1}, | |
964 | {"bss", s_change_sec, 'b'}, | |
965 | {"err", s_err, 0}, | |
966 | {"half", s_cons, 1}, | |
967 | {"dword", s_cons, 3}, | |
968 | {"weakext", s_mips_weakext, 0}, | |
969 | ||
beae10d5 | 970 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
971 | here for one reason or another. */ |
972 | {"align", s_align, 0}, | |
973 | {"byte", s_cons, 0}, | |
974 | {"data", s_change_sec, 'd'}, | |
975 | {"double", s_float_cons, 'd'}, | |
976 | {"float", s_float_cons, 'f'}, | |
977 | {"globl", s_mips_globl, 0}, | |
978 | {"global", s_mips_globl, 0}, | |
979 | {"hword", s_cons, 1}, | |
980 | {"int", s_cons, 2}, | |
981 | {"long", s_cons, 2}, | |
982 | {"octa", s_cons, 4}, | |
983 | {"quad", s_cons, 3}, | |
cca86cc8 | 984 | {"section", s_change_section, 0}, |
252b5132 RH |
985 | {"short", s_cons, 1}, |
986 | {"single", s_float_cons, 'f'}, | |
987 | {"stabn", s_mips_stab, 'n'}, | |
988 | {"text", s_change_sec, 't'}, | |
989 | {"word", s_cons, 2}, | |
add56521 | 990 | |
add56521 | 991 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 992 | |
43841e91 | 993 | { NULL, NULL, 0 }, |
252b5132 RH |
994 | }; |
995 | ||
e972090a NC |
996 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
997 | { | |
beae10d5 KH |
998 | /* These pseudo-ops should be defined by the object file format. |
999 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1000 | {"aent", s_mips_ent, 1}, |
1001 | {"bgnb", s_ignore, 0}, | |
1002 | {"end", s_mips_end, 0}, | |
1003 | {"endb", s_ignore, 0}, | |
1004 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1005 | {"file", s_mips_file, 0}, |
252b5132 RH |
1006 | {"fmask", s_mips_mask, 'F'}, |
1007 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1008 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1009 | {"mask", s_mips_mask, 'R'}, |
1010 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1011 | { NULL, NULL, 0 }, |
252b5132 RH |
1012 | }; |
1013 | ||
17a2f251 | 1014 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1015 | |
1016 | void | |
17a2f251 | 1017 | mips_pop_insert (void) |
252b5132 RH |
1018 | { |
1019 | pop_insert (mips_pseudo_table); | |
1020 | if (! ECOFF_DEBUGGING) | |
1021 | pop_insert (mips_nonecoff_pseudo_table); | |
1022 | } | |
1023 | \f | |
1024 | /* Symbols labelling the current insn. */ | |
1025 | ||
e972090a NC |
1026 | struct insn_label_list |
1027 | { | |
252b5132 RH |
1028 | struct insn_label_list *next; |
1029 | symbolS *label; | |
1030 | }; | |
1031 | ||
1032 | static struct insn_label_list *insn_labels; | |
1033 | static struct insn_label_list *free_insn_labels; | |
1034 | ||
17a2f251 | 1035 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1036 | |
1037 | static inline void | |
17a2f251 | 1038 | mips_clear_insn_labels (void) |
252b5132 RH |
1039 | { |
1040 | register struct insn_label_list **pl; | |
1041 | ||
1042 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1043 | ; | |
1044 | *pl = insn_labels; | |
1045 | insn_labels = NULL; | |
1046 | } | |
1047 | \f | |
1048 | static char *expr_end; | |
1049 | ||
1050 | /* Expressions which appear in instructions. These are set by | |
1051 | mips_ip. */ | |
1052 | ||
1053 | static expressionS imm_expr; | |
5f74bc13 | 1054 | static expressionS imm2_expr; |
252b5132 RH |
1055 | static expressionS offset_expr; |
1056 | ||
1057 | /* Relocs associated with imm_expr and offset_expr. */ | |
1058 | ||
f6688943 TS |
1059 | static bfd_reloc_code_real_type imm_reloc[3] |
1060 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1061 | static bfd_reloc_code_real_type offset_reloc[3] | |
1062 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1063 | |
252b5132 RH |
1064 | /* These are set by mips16_ip if an explicit extension is used. */ |
1065 | ||
b34976b6 | 1066 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1067 | |
7ed4a06a | 1068 | #ifdef OBJ_ELF |
ecb4347a DJ |
1069 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1070 | ECOFF debugging. */ | |
252b5132 RH |
1071 | |
1072 | static segT pdr_seg; | |
7ed4a06a | 1073 | #endif |
252b5132 | 1074 | |
e013f690 TS |
1075 | /* The default target format to use. */ |
1076 | ||
1077 | const char * | |
17a2f251 | 1078 | mips_target_format (void) |
e013f690 TS |
1079 | { |
1080 | switch (OUTPUT_FLAVOR) | |
1081 | { | |
e013f690 TS |
1082 | case bfd_target_ecoff_flavour: |
1083 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1084 | case bfd_target_coff_flavour: | |
1085 | return "pe-mips"; | |
1086 | case bfd_target_elf_flavour: | |
1087 | #ifdef TE_TMIPS | |
cfe86eaa | 1088 | /* This is traditional mips. */ |
e013f690 | 1089 | return (target_big_endian |
cfe86eaa TS |
1090 | ? (HAVE_64BIT_OBJECTS |
1091 | ? "elf64-tradbigmips" | |
1092 | : (HAVE_NEWABI | |
1093 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1094 | : (HAVE_64BIT_OBJECTS | |
1095 | ? "elf64-tradlittlemips" | |
1096 | : (HAVE_NEWABI | |
1097 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1098 | #else |
1099 | return (target_big_endian | |
cfe86eaa TS |
1100 | ? (HAVE_64BIT_OBJECTS |
1101 | ? "elf64-bigmips" | |
1102 | : (HAVE_NEWABI | |
1103 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1104 | : (HAVE_64BIT_OBJECTS | |
1105 | ? "elf64-littlemips" | |
1106 | : (HAVE_NEWABI | |
1107 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1108 | #endif |
1109 | default: | |
1110 | abort (); | |
1111 | return NULL; | |
1112 | } | |
1113 | } | |
1114 | ||
156c2f8b NC |
1115 | /* This function is called once, at assembler startup time. It should |
1116 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1117 | ||
252b5132 | 1118 | void |
17a2f251 | 1119 | md_begin (void) |
252b5132 | 1120 | { |
252b5132 | 1121 | register const char *retval = NULL; |
156c2f8b | 1122 | int i = 0; |
252b5132 | 1123 | int broken = 0; |
1f25f5d3 | 1124 | |
fef14a42 | 1125 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1126 | as_warn (_("Could not set architecture and machine")); |
1127 | ||
252b5132 RH |
1128 | op_hash = hash_new (); |
1129 | ||
1130 | for (i = 0; i < NUMOPCODES;) | |
1131 | { | |
1132 | const char *name = mips_opcodes[i].name; | |
1133 | ||
17a2f251 | 1134 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1135 | if (retval != NULL) |
1136 | { | |
1137 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1138 | mips_opcodes[i].name, retval); | |
1139 | /* Probably a memory allocation problem? Give up now. */ | |
1140 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1141 | } | |
1142 | do | |
1143 | { | |
1144 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1145 | { | |
1146 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1147 | broken = 1; | |
1148 | } | |
1149 | ++i; | |
1150 | } | |
1151 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1152 | } | |
1153 | ||
1154 | mips16_op_hash = hash_new (); | |
1155 | ||
1156 | i = 0; | |
1157 | while (i < bfd_mips16_num_opcodes) | |
1158 | { | |
1159 | const char *name = mips16_opcodes[i].name; | |
1160 | ||
17a2f251 | 1161 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1162 | if (retval != NULL) |
1163 | as_fatal (_("internal: can't hash `%s': %s"), | |
1164 | mips16_opcodes[i].name, retval); | |
1165 | do | |
1166 | { | |
1167 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1168 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1169 | != mips16_opcodes[i].match)) | |
1170 | { | |
1171 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1172 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1173 | broken = 1; | |
1174 | } | |
1175 | ++i; | |
1176 | } | |
1177 | while (i < bfd_mips16_num_opcodes | |
1178 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1179 | } | |
1180 | ||
1181 | if (broken) | |
1182 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1183 | ||
1184 | /* We add all the general register names to the symbol table. This | |
1185 | helps us detect invalid uses of them. */ | |
1186 | for (i = 0; i < 32; i++) | |
1187 | { | |
1188 | char buf[5]; | |
1189 | ||
1190 | sprintf (buf, "$%d", i); | |
1191 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1192 | &zero_address_frag)); | |
1193 | } | |
76db943d TS |
1194 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1195 | &zero_address_frag)); | |
252b5132 RH |
1196 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1197 | &zero_address_frag)); | |
1198 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1199 | &zero_address_frag)); | |
1200 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1201 | &zero_address_frag)); | |
1202 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1203 | &zero_address_frag)); | |
1204 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1205 | &zero_address_frag)); | |
1206 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1207 | &zero_address_frag)); | |
85b51719 TS |
1208 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1209 | &zero_address_frag)); | |
252b5132 RH |
1210 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1211 | &zero_address_frag)); | |
1212 | ||
6047c971 AO |
1213 | /* If we don't add these register names to the symbol table, they |
1214 | may end up being added as regular symbols by operand(), and then | |
1215 | make it to the object file as undefined in case they're not | |
1216 | regarded as local symbols. They're local in o32, since `$' is a | |
1217 | local symbol prefix, but not in n32 or n64. */ | |
1218 | for (i = 0; i < 8; i++) | |
1219 | { | |
1220 | char buf[6]; | |
1221 | ||
1222 | sprintf (buf, "$fcc%i", i); | |
1223 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1224 | &zero_address_frag)); | |
1225 | } | |
1226 | ||
b34976b6 | 1227 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1228 | |
1229 | mips_gprmask = 0; | |
1230 | mips_cprmask[0] = 0; | |
1231 | mips_cprmask[1] = 0; | |
1232 | mips_cprmask[2] = 0; | |
1233 | mips_cprmask[3] = 0; | |
1234 | ||
1235 | /* set the default alignment for the text section (2**2) */ | |
1236 | record_alignment (text_section, 2); | |
1237 | ||
4d0d148d | 1238 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1239 | |
1240 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1241 | { | |
1242 | /* On a native system, sections must be aligned to 16 byte | |
1243 | boundaries. When configured for an embedded ELF target, we | |
1244 | don't bother. */ | |
1245 | if (strcmp (TARGET_OS, "elf") != 0) | |
1246 | { | |
1247 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1248 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1249 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1250 | } | |
1251 | ||
1252 | /* Create a .reginfo section for register masks and a .mdebug | |
1253 | section for debugging information. */ | |
1254 | { | |
1255 | segT seg; | |
1256 | subsegT subseg; | |
1257 | flagword flags; | |
1258 | segT sec; | |
1259 | ||
1260 | seg = now_seg; | |
1261 | subseg = now_subseg; | |
1262 | ||
1263 | /* The ABI says this section should be loaded so that the | |
1264 | running program can access it. However, we don't load it | |
1265 | if we are configured for an embedded target */ | |
1266 | flags = SEC_READONLY | SEC_DATA; | |
1267 | if (strcmp (TARGET_OS, "elf") != 0) | |
1268 | flags |= SEC_ALLOC | SEC_LOAD; | |
1269 | ||
316f5878 | 1270 | if (mips_abi != N64_ABI) |
252b5132 RH |
1271 | { |
1272 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1273 | ||
195325d2 TS |
1274 | bfd_set_section_flags (stdoutput, sec, flags); |
1275 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1276 | |
252b5132 RH |
1277 | #ifdef OBJ_ELF |
1278 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1279 | #endif | |
1280 | } | |
1281 | else | |
1282 | { | |
1283 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1284 | .reginfo section. */ | |
1285 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1286 | bfd_set_section_flags (stdoutput, sec, flags); |
1287 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1288 | |
1289 | #ifdef OBJ_ELF | |
1290 | /* Set up the option header. */ | |
1291 | { | |
1292 | Elf_Internal_Options opthdr; | |
1293 | char *f; | |
1294 | ||
1295 | opthdr.kind = ODK_REGINFO; | |
1296 | opthdr.size = (sizeof (Elf_External_Options) | |
1297 | + sizeof (Elf64_External_RegInfo)); | |
1298 | opthdr.section = 0; | |
1299 | opthdr.info = 0; | |
1300 | f = frag_more (sizeof (Elf_External_Options)); | |
1301 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1302 | (Elf_External_Options *) f); | |
1303 | ||
1304 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1305 | } | |
1306 | #endif | |
1307 | } | |
1308 | ||
1309 | if (ECOFF_DEBUGGING) | |
1310 | { | |
1311 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1312 | (void) bfd_set_section_flags (stdoutput, sec, | |
1313 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1314 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1315 | } | |
ecb4347a | 1316 | #ifdef OBJ_ELF |
dcd410fe | 1317 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1318 | { |
1319 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1320 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1321 | SEC_READONLY | SEC_RELOC | |
1322 | | SEC_DEBUGGING); | |
1323 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1324 | } | |
252b5132 RH |
1325 | #endif |
1326 | ||
1327 | subseg_set (seg, subseg); | |
1328 | } | |
1329 | } | |
1330 | ||
1331 | if (! ECOFF_DEBUGGING) | |
1332 | md_obj_begin (); | |
1333 | } | |
1334 | ||
1335 | void | |
17a2f251 | 1336 | md_mips_end (void) |
252b5132 RH |
1337 | { |
1338 | if (! ECOFF_DEBUGGING) | |
1339 | md_obj_end (); | |
1340 | } | |
1341 | ||
1342 | void | |
17a2f251 | 1343 | md_assemble (char *str) |
252b5132 RH |
1344 | { |
1345 | struct mips_cl_insn insn; | |
f6688943 TS |
1346 | bfd_reloc_code_real_type unused_reloc[3] |
1347 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1348 | |
1349 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1350 | imm2_expr.X_op = O_absent; |
252b5132 | 1351 | offset_expr.X_op = O_absent; |
f6688943 TS |
1352 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1353 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1354 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1355 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1356 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1357 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1358 | |
1359 | if (mips_opts.mips16) | |
1360 | mips16_ip (str, &insn); | |
1361 | else | |
1362 | { | |
1363 | mips_ip (str, &insn); | |
beae10d5 KH |
1364 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1365 | str, insn.insn_opcode)); | |
252b5132 RH |
1366 | } |
1367 | ||
1368 | if (insn_error) | |
1369 | { | |
1370 | as_bad ("%s `%s'", insn_error, str); | |
1371 | return; | |
1372 | } | |
1373 | ||
1374 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1375 | { | |
584892a6 | 1376 | macro_start (); |
252b5132 RH |
1377 | if (mips_opts.mips16) |
1378 | mips16_macro (&insn); | |
1379 | else | |
1380 | macro (&insn); | |
584892a6 | 1381 | macro_end (); |
252b5132 RH |
1382 | } |
1383 | else | |
1384 | { | |
1385 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1386 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1387 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1388 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1389 | else |
4d7206a2 | 1390 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1391 | } |
1392 | } | |
1393 | ||
5919d012 RS |
1394 | /* Return true if the given relocation might need a matching %lo(). |
1395 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1396 | applied to local symbols. */ | |
1397 | ||
1398 | static inline bfd_boolean | |
17a2f251 | 1399 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1400 | { |
1401 | return (reloc == BFD_RELOC_HI16_S | |
1402 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1403 | } | |
1404 | ||
1405 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1406 | relocation. */ | |
1407 | ||
1408 | static inline bfd_boolean | |
17a2f251 | 1409 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1410 | { |
1411 | return (fixp->fx_next != NULL | |
1412 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1413 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1414 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1415 | } | |
1416 | ||
252b5132 RH |
1417 | /* See whether instruction IP reads register REG. CLASS is the type |
1418 | of register. */ | |
1419 | ||
1420 | static int | |
17a2f251 TS |
1421 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1422 | enum mips_regclass class) | |
252b5132 RH |
1423 | { |
1424 | if (class == MIPS16_REG) | |
1425 | { | |
1426 | assert (mips_opts.mips16); | |
1427 | reg = mips16_to_32_reg_map[reg]; | |
1428 | class = MIPS_GR_REG; | |
1429 | } | |
1430 | ||
85b51719 TS |
1431 | /* Don't report on general register ZERO, since it never changes. */ |
1432 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1433 | return 0; |
1434 | ||
1435 | if (class == MIPS_FP_REG) | |
1436 | { | |
1437 | assert (! mips_opts.mips16); | |
1438 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1439 | This is not optimal, because it will introduce an unnecessary | |
1440 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1441 | need to distinguish reading both $f0 and $f1 or just one of | |
1442 | them. Note that we don't have to check the other way, | |
1443 | because there is no instruction that sets both $f0 and $f1 | |
1444 | and requires a delay. */ | |
1445 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1446 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1447 | == (reg &~ (unsigned) 1))) | |
1448 | return 1; | |
1449 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1450 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1451 | == (reg &~ (unsigned) 1))) | |
1452 | return 1; | |
1453 | } | |
1454 | else if (! mips_opts.mips16) | |
1455 | { | |
1456 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1457 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1460 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1461 | return 1; | |
1462 | } | |
1463 | else | |
1464 | { | |
1465 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1466 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1467 | & MIPS16OP_MASK_RX)] | |
1468 | == reg)) | |
1469 | return 1; | |
1470 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1471 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1472 | & MIPS16OP_MASK_RY)] | |
1473 | == reg)) | |
1474 | return 1; | |
1475 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1476 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1477 | & MIPS16OP_MASK_MOVE32Z)] | |
1478 | == reg)) | |
1479 | return 1; | |
1480 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1481 | return 1; | |
1482 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1483 | return 1; | |
1484 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1485 | return 1; | |
1486 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1487 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1488 | & MIPS16OP_MASK_REGR32) == reg) | |
1489 | return 1; | |
1490 | } | |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
1495 | /* This function returns true if modifying a register requires a | |
1496 | delay. */ | |
1497 | ||
1498 | static int | |
17a2f251 | 1499 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1500 | { |
1501 | unsigned long prev_pinfo; | |
1502 | ||
1503 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1504 | if (! mips_opts.noreorder | |
81912461 ILT |
1505 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1506 | && ! gpr_interlocks) | |
1507 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1508 | && ! cop_interlocks))) | |
252b5132 | 1509 | { |
81912461 ILT |
1510 | /* A load from a coprocessor or from memory. All load delays |
1511 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1512 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1513 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1514 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1515 | return 1; | |
1516 | } | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1522 | handle them specially, such as generating jalx instructions when | |
1523 | needed. We also make them odd for the duration of the assembly, in | |
1524 | order to generate the right sort of code. We will make them even | |
1525 | in the adjust_symtab routine, while leaving them marked. This is | |
1526 | convenient for the debugger and the disassembler. The linker knows | |
1527 | to make them odd again. */ | |
1528 | ||
1529 | static void | |
17a2f251 | 1530 | mips16_mark_labels (void) |
252b5132 RH |
1531 | { |
1532 | if (mips_opts.mips16) | |
1533 | { | |
1534 | struct insn_label_list *l; | |
98aa84af | 1535 | valueT val; |
252b5132 RH |
1536 | |
1537 | for (l = insn_labels; l != NULL; l = l->next) | |
1538 | { | |
1539 | #ifdef OBJ_ELF | |
1540 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1541 | S_SET_OTHER (l->label, STO_MIPS16); | |
1542 | #endif | |
98aa84af AM |
1543 | val = S_GET_VALUE (l->label); |
1544 | if ((val & 1) == 0) | |
1545 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1546 | } |
1547 | } | |
1548 | } | |
1549 | ||
4d7206a2 RS |
1550 | /* End the current frag. Make it a variant frag and record the |
1551 | relaxation info. */ | |
1552 | ||
1553 | static void | |
1554 | relax_close_frag (void) | |
1555 | { | |
584892a6 | 1556 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1557 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1558 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1559 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1560 | ||
1561 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1562 | mips_relax.first_fixup = 0; | |
1563 | } | |
1564 | ||
1565 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1566 | See the comment above RELAX_ENCODE for more details. */ | |
1567 | ||
1568 | static void | |
1569 | relax_start (symbolS *symbol) | |
1570 | { | |
1571 | assert (mips_relax.sequence == 0); | |
1572 | mips_relax.sequence = 1; | |
1573 | mips_relax.symbol = symbol; | |
1574 | } | |
1575 | ||
1576 | /* Start generating the second version of a relaxable sequence. | |
1577 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1578 | |
1579 | static void | |
4d7206a2 RS |
1580 | relax_switch (void) |
1581 | { | |
1582 | assert (mips_relax.sequence == 1); | |
1583 | mips_relax.sequence = 2; | |
1584 | } | |
1585 | ||
1586 | /* End the current relaxable sequence. */ | |
1587 | ||
1588 | static void | |
1589 | relax_end (void) | |
1590 | { | |
1591 | assert (mips_relax.sequence == 2); | |
1592 | relax_close_frag (); | |
1593 | mips_relax.sequence = 0; | |
1594 | } | |
1595 | ||
1596 | /* Output an instruction. IP is the instruction information. | |
1597 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1598 | RELOC_TYPE. */ | |
1599 | ||
1600 | static void | |
1601 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1602 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1603 | { |
1604 | register unsigned long prev_pinfo, pinfo; | |
1605 | char *f; | |
f6688943 | 1606 | fixS *fixp[3]; |
252b5132 | 1607 | int nops = 0; |
895921c9 MR |
1608 | relax_stateT prev_insn_frag_type = 0; |
1609 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1610 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1611 | |
1612 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1613 | mips16_mark_labels (); |
252b5132 RH |
1614 | |
1615 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1616 | pinfo = ip->insn_mo->pinfo; | |
1617 | ||
4d7206a2 RS |
1618 | if (mips_relax.sequence != 2 |
1619 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1620 | { |
1621 | int prev_prev_nop; | |
1622 | ||
1623 | /* If the previous insn required any delay slots, see if we need | |
1624 | to insert a NOP or two. There are eight kinds of possible | |
1625 | hazards, of which an instruction can have at most one type. | |
1626 | (1) a load from memory delay | |
1627 | (2) a load from a coprocessor delay | |
1628 | (3) an unconditional branch delay | |
1629 | (4) a conditional branch delay | |
1630 | (5) a move to coprocessor register delay | |
1631 | (6) a load coprocessor register from memory delay | |
1632 | (7) a coprocessor condition code delay | |
1633 | (8) a HI/LO special register delay | |
1634 | ||
1635 | There are a lot of optimizations we could do that we don't. | |
1636 | In particular, we do not, in general, reorder instructions. | |
1637 | If you use gcc with optimization, it will reorder | |
1638 | instructions and generally do much more optimization then we | |
1639 | do here; repeating all that work in the assembler would only | |
1640 | benefit hand written assembly code, and does not seem worth | |
1641 | it. */ | |
1642 | ||
1643 | /* This is how a NOP is emitted. */ | |
1644 | #define emit_nop() \ | |
1645 | (mips_opts.mips16 \ | |
1646 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1647 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1648 | ||
1649 | /* The previous insn might require a delay slot, depending upon | |
1650 | the contents of the current insn. */ | |
1651 | if (! mips_opts.mips16 | |
81912461 ILT |
1652 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1653 | && ! gpr_interlocks) | |
1654 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1655 | && ! cop_interlocks))) | |
252b5132 RH |
1656 | { |
1657 | /* A load from a coprocessor or from memory. All load | |
1658 | delays delay the use of general register rt for one | |
81912461 | 1659 | instruction. */ |
beae10d5 | 1660 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1661 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1662 | if (mips_optimize == 0 | |
1663 | || insn_uses_reg (ip, | |
1664 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1665 | & OP_MASK_RT), | |
1666 | MIPS_GR_REG)) | |
1667 | ++nops; | |
1668 | } | |
1669 | else if (! mips_opts.mips16 | |
252b5132 | 1670 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1671 | && ! cop_interlocks) |
81912461 ILT |
1672 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1673 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1674 | { |
1675 | /* A generic coprocessor delay. The previous instruction | |
1676 | modified a coprocessor general or control register. If | |
1677 | it modified a control register, we need to avoid any | |
1678 | coprocessor instruction (this is probably not always | |
1679 | required, but it sometimes is). If it modified a general | |
1680 | register, we avoid using that register. | |
1681 | ||
252b5132 RH |
1682 | This case is not handled very well. There is no special |
1683 | knowledge of CP0 handling, and the coprocessors other | |
1684 | than the floating point unit are not distinguished at | |
1685 | all. */ | |
1686 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1687 | Need to modify this to include knowledge about |
252b5132 RH |
1688 | user specified delays! */ |
1689 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1690 | { | |
1691 | if (mips_optimize == 0 | |
1692 | || insn_uses_reg (ip, | |
1693 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1694 | & OP_MASK_FT), | |
1695 | MIPS_FP_REG)) | |
1696 | ++nops; | |
1697 | } | |
1698 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1699 | { | |
1700 | if (mips_optimize == 0 | |
1701 | || insn_uses_reg (ip, | |
1702 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1703 | & OP_MASK_FS), | |
1704 | MIPS_FP_REG)) | |
1705 | ++nops; | |
1706 | } | |
1707 | else | |
1708 | { | |
1709 | /* We don't know exactly what the previous instruction | |
1710 | does. If the current instruction uses a coprocessor | |
1711 | register, we must insert a NOP. If previous | |
1712 | instruction may set the condition codes, and the | |
1713 | current instruction uses them, we must insert two | |
1714 | NOPS. */ | |
bdaaa2e1 | 1715 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1716 | if (mips_optimize == 0 |
1717 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1718 | && (pinfo & INSN_READ_COND_CODE))) | |
1719 | nops += 2; | |
1720 | else if (pinfo & INSN_COP) | |
1721 | ++nops; | |
1722 | } | |
1723 | } | |
1724 | else if (! mips_opts.mips16 | |
252b5132 RH |
1725 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1726 | && ! cop_interlocks) | |
1727 | { | |
1728 | /* The previous instruction sets the coprocessor condition | |
1729 | codes, but does not require a general coprocessor delay | |
1730 | (this means it is a floating point comparison | |
1731 | instruction). If this instruction uses the condition | |
1732 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1733 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1734 | if (mips_optimize == 0 |
1735 | || (pinfo & INSN_READ_COND_CODE)) | |
1736 | ++nops; | |
1737 | } | |
6b76fefe CM |
1738 | |
1739 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1740 | previous insn was an mfhi/mflo and the current insn | |
1741 | reads the register that the mfhi/mflo wrote to, then | |
1742 | insert two nops. */ | |
1743 | ||
1744 | else if (mips_7000_hilo_fix | |
1745 | && MF_HILO_INSN (prev_pinfo) | |
1746 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1747 | & OP_MASK_RD), |
1748 | MIPS_GR_REG)) | |
6b76fefe CM |
1749 | { |
1750 | nops += 2; | |
1751 | } | |
1752 | ||
1753 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1754 | 2nd previous insn was an mfhi/mflo and the current insn | |
1755 | reads the register that the mfhi/mflo wrote to, then | |
1756 | insert one nop. */ | |
1757 | ||
1758 | else if (mips_7000_hilo_fix | |
1759 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1760 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1761 | & OP_MASK_RD), | |
1762 | MIPS_GR_REG)) | |
bdaaa2e1 | 1763 | |
6b76fefe | 1764 | { |
f9419b05 | 1765 | ++nops; |
6b76fefe | 1766 | } |
bdaaa2e1 | 1767 | |
252b5132 RH |
1768 | else if (prev_pinfo & INSN_READ_LO) |
1769 | { | |
1770 | /* The previous instruction reads the LO register; if the | |
1771 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1772 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1773 | Also the tx39's multiply instructions can be executed |
1774 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1775 | though the tx39's divide insns still do require the |
1776 | delay. */ | |
252b5132 | 1777 | if (! (hilo_interlocks |
048cdf86 | 1778 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1779 | && (mips_optimize == 0 |
1780 | || (pinfo & INSN_WRITE_LO))) | |
1781 | nops += 2; | |
1782 | /* Most mips16 branch insns don't have a delay slot. | |
1783 | If a read from LO is immediately followed by a branch | |
1784 | to a write to LO we have a read followed by a write | |
1785 | less than 2 insns away. We assume the target of | |
1786 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1787 | between a read and an immediately following branch. */ |
252b5132 RH |
1788 | else if (mips_opts.mips16 |
1789 | && (mips_optimize == 0 | |
1790 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1791 | ++nops; |
252b5132 RH |
1792 | } |
1793 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1794 | { | |
1795 | /* The previous instruction reads the HI register; if the | |
1796 | current instruction writes to the HI register, we must | |
1797 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1798 | Also the note tx39's multiply above. */ |
252b5132 | 1799 | if (! (hilo_interlocks |
048cdf86 | 1800 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1801 | && (mips_optimize == 0 |
1802 | || (pinfo & INSN_WRITE_HI))) | |
1803 | nops += 2; | |
1804 | /* Most mips16 branch insns don't have a delay slot. | |
1805 | If a read from HI is immediately followed by a branch | |
1806 | to a write to HI we have a read followed by a write | |
1807 | less than 2 insns away. We assume the target of | |
1808 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1809 | between a read and an immediately following branch. */ |
252b5132 RH |
1810 | else if (mips_opts.mips16 |
1811 | && (mips_optimize == 0 | |
1812 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1813 | ++nops; |
252b5132 RH |
1814 | } |
1815 | ||
1816 | /* If the previous instruction was in a noreorder section, then | |
1817 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1818 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1819 | if (prev_insn_unreordered) |
1820 | nops = 0; | |
1821 | ||
1822 | /* There are two cases which require two intervening | |
1823 | instructions: 1) setting the condition codes using a move to | |
1824 | coprocessor instruction which requires a general coprocessor | |
1825 | delay and then reading the condition codes 2) reading the HI | |
1826 | or LO register and then writing to it (except on processors | |
1827 | which have interlocks). If we are not already emitting a NOP | |
1828 | instruction, we must check for these cases compared to the | |
1829 | instruction previous to the previous instruction. */ | |
1830 | if ((! mips_opts.mips16 | |
252b5132 RH |
1831 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1832 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1833 | && (pinfo & INSN_READ_COND_CODE) | |
1834 | && ! cop_interlocks) | |
1835 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1836 | && (pinfo & INSN_WRITE_LO) | |
1837 | && ! (hilo_interlocks | |
048cdf86 | 1838 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1839 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1840 | && (pinfo & INSN_WRITE_HI) | |
1841 | && ! (hilo_interlocks | |
048cdf86 | 1842 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1843 | prev_prev_nop = 1; |
1844 | else | |
1845 | prev_prev_nop = 0; | |
1846 | ||
1847 | if (prev_prev_insn_unreordered) | |
1848 | prev_prev_nop = 0; | |
1849 | ||
1850 | if (prev_prev_nop && nops == 0) | |
1851 | ++nops; | |
1852 | ||
d766e8ec | 1853 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1854 | { |
1855 | /* We're out of bits in pinfo, so we must resort to string | |
1856 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1857 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1858 | int min_nops = 0; |
1859 | const char *pn = prev_insn.insn_mo->name; | |
1860 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1861 | if (strncmp (pn, "macc", 4) == 0 |
1862 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1863 | { |
1864 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1865 | if (strstr (tn, "div")) | |
532c738a | 1866 | min_nops = 1; |
60b63b72 | 1867 | |
532c738a RS |
1868 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1869 | instruction is executed immediately after a MACC or | |
1870 | DMACC instruction, the result of [either instruction] | |
1871 | is incorrect." */ | |
1872 | if (strncmp (tn, "mult", 4) == 0 | |
1873 | || strncmp (tn, "dmult", 5) == 0) | |
1874 | min_nops = 1; | |
1875 | ||
1876 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1877 | Applies on top of VR4181A MD(1) errata. */ | |
1878 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1879 | min_nops = 1; | |
60b63b72 RS |
1880 | |
1881 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1882 | if (strcmp (tn, "mtlo") == 0 | |
1883 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1884 | min_nops = 1; |
60b63b72 | 1885 | } |
532c738a RS |
1886 | else if (strncmp (pn, "dmult", 5) == 0 |
1887 | && (strncmp (tn, "dmult", 5) == 0 | |
1888 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1889 | { |
1890 | /* Here is the rest of errata 23. */ | |
1891 | min_nops = 1; | |
1892 | } | |
532c738a RS |
1893 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1894 | && (strncmp (tn, "macc", 4) == 0 | |
1895 | || strncmp (tn, "dmacc", 5) == 0)) | |
1896 | { | |
1897 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1898 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1899 | DDIV or DDIVU instruction, the result of the MACC or | |
1900 | DMACC instruction is incorrect.". This partly overlaps | |
1901 | the workaround for errata 23. */ | |
1902 | min_nops = 1; | |
1903 | } | |
60b63b72 RS |
1904 | if (nops < min_nops) |
1905 | nops = min_nops; | |
1906 | } | |
1907 | ||
252b5132 RH |
1908 | /* If we are being given a nop instruction, don't bother with |
1909 | one of the nops we would otherwise output. This will only | |
1910 | happen when a nop instruction is used with mips_optimize set | |
1911 | to 0. */ | |
1912 | if (nops > 0 | |
1913 | && ! mips_opts.noreorder | |
156c2f8b | 1914 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1915 | --nops; |
1916 | ||
1917 | /* Now emit the right number of NOP instructions. */ | |
1918 | if (nops > 0 && ! mips_opts.noreorder) | |
1919 | { | |
1920 | fragS *old_frag; | |
1921 | unsigned long old_frag_offset; | |
1922 | int i; | |
1923 | struct insn_label_list *l; | |
1924 | ||
1925 | old_frag = frag_now; | |
1926 | old_frag_offset = frag_now_fix (); | |
1927 | ||
1928 | for (i = 0; i < nops; i++) | |
1929 | emit_nop (); | |
1930 | ||
1931 | if (listing) | |
1932 | { | |
1933 | listing_prev_line (); | |
1934 | /* We may be at the start of a variant frag. In case we | |
1935 | are, make sure there is enough space for the frag | |
1936 | after the frags created by listing_prev_line. The | |
1937 | argument to frag_grow here must be at least as large | |
1938 | as the argument to all other calls to frag_grow in | |
1939 | this file. We don't have to worry about being in the | |
1940 | middle of a variant frag, because the variants insert | |
1941 | all needed nop instructions themselves. */ | |
1942 | frag_grow (40); | |
1943 | } | |
1944 | ||
1945 | for (l = insn_labels; l != NULL; l = l->next) | |
1946 | { | |
98aa84af AM |
1947 | valueT val; |
1948 | ||
252b5132 | 1949 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1950 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1951 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1952 | /* mips16 text labels are stored as odd. */ |
1953 | if (mips_opts.mips16) | |
f9419b05 | 1954 | ++val; |
98aa84af | 1955 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1956 | } |
1957 | ||
1958 | #ifndef NO_ECOFF_DEBUGGING | |
1959 | if (ECOFF_DEBUGGING) | |
1960 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1961 | #endif | |
1962 | } | |
1963 | else if (prev_nop_frag != NULL) | |
1964 | { | |
1965 | /* We have a frag holding nops we may be able to remove. If | |
1966 | we don't need any nops, we can decrease the size of | |
1967 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1968 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1969 | if (prev_nop_frag_since == 0) |
1970 | { | |
1971 | if (nops == 0) | |
1972 | { | |
1973 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1974 | --prev_nop_frag_holds; | |
1975 | } | |
1976 | else | |
1977 | prev_nop_frag_required += nops; | |
1978 | } | |
1979 | else | |
1980 | { | |
1981 | if (prev_prev_nop == 0) | |
1982 | { | |
1983 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1984 | --prev_nop_frag_holds; | |
1985 | } | |
1986 | else | |
1987 | ++prev_nop_frag_required; | |
1988 | } | |
1989 | ||
1990 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1991 | prev_nop_frag = NULL; | |
1992 | ||
1993 | ++prev_nop_frag_since; | |
1994 | ||
1995 | /* Sanity check: by the time we reach the second instruction | |
1996 | after prev_nop_frag, we should have used up all the nops | |
1997 | one way or another. */ | |
1998 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1999 | } | |
2000 | } | |
2001 | ||
895921c9 MR |
2002 | /* Record the frag type before frag_var. */ |
2003 | if (prev_insn_frag) | |
2004 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2005 | ||
4d7206a2 | 2006 | if (address_expr |
0b25d3e6 | 2007 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2008 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2009 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2010 | && mips_relax_branch | |
2011 | /* Don't try branch relaxation within .set nomacro, or within | |
2012 | .set noat if we use $at for PIC computations. If it turns | |
2013 | out that the branch was out-of-range, we'll get an error. */ | |
2014 | && !mips_opts.warn_about_macros | |
2015 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2016 | && !mips_opts.mips16) | |
2017 | { | |
895921c9 | 2018 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2019 | f = frag_var (rs_machine_dependent, |
2020 | relaxed_branch_length | |
2021 | (NULL, NULL, | |
2022 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2023 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2024 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2025 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2026 | pinfo & INSN_COND_BRANCH_LIKELY, |
2027 | pinfo & INSN_WRITE_GPR_31, | |
2028 | 0), | |
2029 | address_expr->X_add_symbol, | |
2030 | address_expr->X_add_number, | |
2031 | 0); | |
2032 | *reloc_type = BFD_RELOC_UNUSED; | |
2033 | } | |
2034 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2035 | { |
2036 | /* We need to set up a variant frag. */ | |
2037 | assert (mips_opts.mips16 && address_expr != NULL); | |
2038 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2039 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2040 | mips16_small, mips16_ext, |
2041 | (prev_pinfo | |
2042 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2043 | (*prev_insn_reloc_type |
252b5132 | 2044 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2045 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2046 | } |
252b5132 RH |
2047 | else if (mips_opts.mips16 |
2048 | && ! ip->use_extend | |
f6688943 | 2049 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2050 | { |
2051 | /* Make sure there is enough room to swap this instruction with | |
2052 | a following jump instruction. */ | |
2053 | frag_grow (6); | |
2054 | f = frag_more (2); | |
2055 | } | |
2056 | else | |
2057 | { | |
2058 | if (mips_opts.mips16 | |
2059 | && mips_opts.noreorder | |
2060 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2061 | as_warn (_("extended instruction in delay slot")); | |
2062 | ||
4d7206a2 RS |
2063 | if (mips_relax.sequence) |
2064 | { | |
2065 | /* If we've reached the end of this frag, turn it into a variant | |
2066 | frag and record the information for the instructions we've | |
2067 | written so far. */ | |
2068 | if (frag_room () < 4) | |
2069 | relax_close_frag (); | |
2070 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2071 | } | |
2072 | ||
584892a6 RS |
2073 | if (mips_relax.sequence != 2) |
2074 | mips_macro_warning.sizes[0] += 4; | |
2075 | if (mips_relax.sequence != 1) | |
2076 | mips_macro_warning.sizes[1] += 4; | |
2077 | ||
252b5132 RH |
2078 | f = frag_more (4); |
2079 | } | |
2080 | ||
f6688943 TS |
2081 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2082 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2083 | { |
2084 | if (address_expr->X_op == O_constant) | |
2085 | { | |
4db1a35d | 2086 | valueT tmp; |
f6688943 TS |
2087 | |
2088 | switch (*reloc_type) | |
252b5132 RH |
2089 | { |
2090 | case BFD_RELOC_32: | |
2091 | ip->insn_opcode |= address_expr->X_add_number; | |
2092 | break; | |
2093 | ||
f6688943 | 2094 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2095 | tmp = (address_expr->X_add_number |
2096 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2097 | tmp >>= 16; |
2098 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2099 | break; | |
2100 | ||
2101 | case BFD_RELOC_MIPS_HIGHER: | |
2102 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2103 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2104 | break; | |
2105 | ||
2106 | case BFD_RELOC_HI16_S: | |
2107 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2108 | >> 16) & 0xffff; | |
2109 | break; | |
2110 | ||
2111 | case BFD_RELOC_HI16: | |
2112 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2113 | break; | |
2114 | ||
252b5132 | 2115 | case BFD_RELOC_LO16: |
ed6fb7bd | 2116 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2117 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2118 | break; | |
2119 | ||
2120 | case BFD_RELOC_MIPS_JMP: | |
2121 | if ((address_expr->X_add_number & 3) != 0) | |
2122 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2123 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2124 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2125 | as_bad (_("jump address range overflow (0x%lx)"), |
2126 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2127 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2128 | break; | |
2129 | ||
2130 | case BFD_RELOC_MIPS16_JMP: | |
2131 | if ((address_expr->X_add_number & 3) != 0) | |
2132 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2133 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2134 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2135 | as_bad (_("jump address range overflow (0x%lx)"), |
2136 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2137 | ip->insn_opcode |= |
2138 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2139 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2140 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2141 | break; | |
2142 | ||
252b5132 RH |
2143 | case BFD_RELOC_16_PCREL_S2: |
2144 | goto need_reloc; | |
2145 | ||
2146 | default: | |
2147 | internalError (); | |
2148 | } | |
2149 | } | |
2150 | else | |
252b5132 | 2151 | need_reloc: |
4d7206a2 RS |
2152 | { |
2153 | reloc_howto_type *howto; | |
2154 | int i; | |
34ce925e | 2155 | |
4d7206a2 RS |
2156 | /* In a compound relocation, it is the final (outermost) |
2157 | operator that determines the relocated field. */ | |
2158 | for (i = 1; i < 3; i++) | |
2159 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2160 | break; | |
34ce925e | 2161 | |
4d7206a2 RS |
2162 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2163 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2164 | bfd_get_reloc_size(howto), | |
2165 | address_expr, | |
2166 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2167 | reloc_type[0]); | |
2168 | ||
2169 | /* These relocations can have an addend that won't fit in | |
2170 | 4 octets for 64bit assembly. */ | |
2171 | if (HAVE_64BIT_GPRS | |
2172 | && ! howto->partial_inplace | |
2173 | && (reloc_type[0] == BFD_RELOC_16 | |
2174 | || reloc_type[0] == BFD_RELOC_32 | |
2175 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2176 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2177 | || reloc_type[0] == BFD_RELOC_LO16 | |
2178 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2179 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2180 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2181 | || reloc_type[0] == BFD_RELOC_64 | |
2182 | || reloc_type[0] == BFD_RELOC_CTOR | |
2183 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2184 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2185 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2186 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2187 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2188 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
2189 | fixp[0]->fx_no_overflow = 1; | |
2190 | ||
2191 | if (mips_relax.sequence) | |
2192 | { | |
2193 | if (mips_relax.first_fixup == 0) | |
2194 | mips_relax.first_fixup = fixp[0]; | |
2195 | } | |
2196 | else if (reloc_needs_lo_p (*reloc_type)) | |
2197 | { | |
2198 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2199 | |
4d7206a2 RS |
2200 | /* Reuse the last entry if it already has a matching %lo. */ |
2201 | hi_fixup = mips_hi_fixup_list; | |
2202 | if (hi_fixup == 0 | |
2203 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2204 | { | |
2205 | hi_fixup = ((struct mips_hi_fixup *) | |
2206 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2207 | hi_fixup->next = mips_hi_fixup_list; | |
2208 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2209 | } |
4d7206a2 RS |
2210 | hi_fixup->fixp = fixp[0]; |
2211 | hi_fixup->seg = now_seg; | |
2212 | } | |
f6688943 | 2213 | |
4d7206a2 RS |
2214 | /* Add fixups for the second and third relocations, if given. |
2215 | Note that the ABI allows the second relocation to be | |
2216 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2217 | moment we only use RSS_UNDEF, but we could add support | |
2218 | for the others if it ever becomes necessary. */ | |
2219 | for (i = 1; i < 3; i++) | |
2220 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2221 | { | |
2222 | address_expr->X_op = O_absent; | |
2223 | address_expr->X_add_symbol = 0; | |
2224 | address_expr->X_add_number = 0; | |
34ce925e | 2225 | |
4d7206a2 RS |
2226 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, |
2227 | fixp[0]->fx_size, address_expr, | |
2228 | FALSE, reloc_type[i]); | |
2229 | } | |
252b5132 RH |
2230 | } |
2231 | } | |
2232 | ||
2233 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2234 | { |
2235 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2236 | #ifdef OBJ_ELF | |
2237 | dwarf2_emit_insn (4); | |
2238 | #endif | |
2239 | } | |
f6688943 | 2240 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2241 | { |
2242 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2243 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab | 2244 | #ifdef OBJ_ELF |
20e56c33 RS |
2245 | /* The value passed to dwarf2_emit_insn is the distance between |
2246 | the end of the current instruction and the address that should | |
2247 | be recorded in the debug tables. Since we want to use ISA-encoded | |
2248 | addresses in MIPS16 debug info, the value is one byte less than | |
2249 | the real instruction length. */ | |
2250 | dwarf2_emit_insn (3); | |
c5dd6aab | 2251 | #endif |
252b5132 RH |
2252 | } |
2253 | else | |
2254 | { | |
2255 | if (ip->use_extend) | |
2256 | { | |
2257 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2258 | f += 2; | |
2259 | } | |
2260 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab | 2261 | #ifdef OBJ_ELF |
20e56c33 | 2262 | dwarf2_emit_insn (ip->use_extend ? 3 : 1); |
c5dd6aab | 2263 | #endif |
252b5132 RH |
2264 | } |
2265 | ||
2266 | /* Update the register mask information. */ | |
2267 | if (! mips_opts.mips16) | |
2268 | { | |
2269 | if (pinfo & INSN_WRITE_GPR_D) | |
2270 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2271 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2272 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2273 | if (pinfo & INSN_READ_GPR_S) | |
2274 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2275 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2276 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2277 | if (pinfo & INSN_WRITE_FPR_D) |
2278 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2279 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2280 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2281 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2282 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2283 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2284 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2285 | if (pinfo & INSN_COP) | |
2286 | { | |
bdaaa2e1 KH |
2287 | /* We don't keep enough information to sort these cases out. |
2288 | The itbl support does keep this information however, although | |
2289 | we currently don't support itbl fprmats as part of the cop | |
2290 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2291 | } |
2292 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2293 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2294 | } |
2295 | else | |
2296 | { | |
2297 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2298 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2299 | & MIPS16OP_MASK_RX); | |
2300 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2301 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2302 | & MIPS16OP_MASK_RY); | |
2303 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2304 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2305 | & MIPS16OP_MASK_RZ); | |
2306 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2307 | mips_gprmask |= 1 << TREG; | |
2308 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2309 | mips_gprmask |= 1 << SP; | |
2310 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2311 | mips_gprmask |= 1 << RA; | |
2312 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2313 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2314 | if (pinfo & MIPS16_INSN_READ_Z) | |
2315 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2316 | & MIPS16OP_MASK_MOVE32Z); | |
2317 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2318 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2319 | & MIPS16OP_MASK_REGR32); | |
2320 | } | |
2321 | ||
4d7206a2 | 2322 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2323 | { |
2324 | /* Filling the branch delay slot is more complex. We try to | |
2325 | switch the branch with the previous instruction, which we can | |
2326 | do if the previous instruction does not set up a condition | |
2327 | that the branch tests and if the branch is not itself the | |
2328 | target of any branch. */ | |
2329 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2330 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2331 | { | |
2332 | if (mips_optimize < 2 | |
2333 | /* If we have seen .set volatile or .set nomove, don't | |
2334 | optimize. */ | |
2335 | || mips_opts.nomove != 0 | |
2336 | /* If we had to emit any NOP instructions, then we | |
2337 | already know we can not swap. */ | |
2338 | || nops != 0 | |
2339 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2340 | swap. */ |
252b5132 RH |
2341 | || ! prev_insn_valid |
2342 | /* If the previous insn is already in a branch delay | |
2343 | slot, then we can not swap. */ | |
2344 | || prev_insn_is_delay_slot | |
2345 | /* If the previous previous insn was in a .set | |
2346 | noreorder, we can't swap. Actually, the MIPS | |
2347 | assembler will swap in this situation. However, gcc | |
2348 | configured -with-gnu-as will generate code like | |
2349 | .set noreorder | |
2350 | lw $4,XXX | |
2351 | .set reorder | |
2352 | INSN | |
2353 | bne $4,$0,foo | |
2354 | in which we can not swap the bne and INSN. If gcc is | |
2355 | not configured -with-gnu-as, it does not output the | |
2356 | .set pseudo-ops. We don't have to check | |
2357 | prev_insn_unreordered, because prev_insn_valid will | |
2358 | be 0 in that case. We don't want to use | |
2359 | prev_prev_insn_valid, because we do want to be able | |
2360 | to swap at the start of a function. */ | |
2361 | || prev_prev_insn_unreordered | |
2362 | /* If the branch is itself the target of a branch, we | |
2363 | can not swap. We cheat on this; all we check for is | |
2364 | whether there is a label on this instruction. If | |
2365 | there are any branches to anything other than a | |
2366 | label, users must use .set noreorder. */ | |
2367 | || insn_labels != NULL | |
895921c9 MR |
2368 | /* If the previous instruction is in a variant frag |
2369 | other than this branch's one, we cannot do the swap. | |
2370 | This does not apply to the mips16, which uses variant | |
2371 | frags for different purposes. */ | |
252b5132 | 2372 | || (! mips_opts.mips16 |
895921c9 | 2373 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2374 | /* If the branch reads the condition codes, we don't |
2375 | even try to swap, because in the sequence | |
2376 | ctc1 $X,$31 | |
2377 | INSN | |
2378 | INSN | |
2379 | bc1t LABEL | |
2380 | we can not swap, and I don't feel like handling that | |
2381 | case. */ | |
2382 | || (! mips_opts.mips16 | |
81912461 ILT |
2383 | && (pinfo & INSN_READ_COND_CODE) |
2384 | && ! cop_interlocks) | |
252b5132 | 2385 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2386 | delay slot, because the target of the branch might |
252b5132 RH |
2387 | interfere with that instruction. */ |
2388 | || (! mips_opts.mips16 | |
252b5132 | 2389 | && (prev_pinfo |
bdaaa2e1 | 2390 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2391 | & (INSN_LOAD_COPROC_DELAY |
2392 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2393 | | INSN_WRITE_COND_CODE)) |
2394 | && ! cop_interlocks) | |
252b5132 | 2395 | || (! (hilo_interlocks |
048cdf86 | 2396 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2397 | && (prev_pinfo |
2398 | & (INSN_READ_LO | |
2399 | | INSN_READ_HI))) | |
2400 | || (! mips_opts.mips16 | |
81912461 ILT |
2401 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2402 | && ! gpr_interlocks) | |
252b5132 | 2403 | || (! mips_opts.mips16 |
bdaaa2e1 | 2404 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2405 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2406 | && ! cop_mem_interlocks) | |
252b5132 RH |
2407 | /* We can not swap with a branch instruction. */ |
2408 | || (prev_pinfo | |
2409 | & (INSN_UNCOND_BRANCH_DELAY | |
2410 | | INSN_COND_BRANCH_DELAY | |
2411 | | INSN_COND_BRANCH_LIKELY)) | |
2412 | /* We do not swap with a trap instruction, since it | |
2413 | complicates trap handlers to have the trap | |
2414 | instruction be in a delay slot. */ | |
2415 | || (prev_pinfo & INSN_TRAP) | |
2416 | /* If the branch reads a register that the previous | |
2417 | instruction sets, we can not swap. */ | |
2418 | || (! mips_opts.mips16 | |
2419 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2420 | && insn_uses_reg (ip, | |
2421 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2422 | & OP_MASK_RT), | |
2423 | MIPS_GR_REG)) | |
2424 | || (! mips_opts.mips16 | |
2425 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2426 | && insn_uses_reg (ip, | |
2427 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2428 | & OP_MASK_RD), | |
2429 | MIPS_GR_REG)) | |
2430 | || (mips_opts.mips16 | |
2431 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2432 | && insn_uses_reg (ip, | |
2433 | ((prev_insn.insn_opcode | |
2434 | >> MIPS16OP_SH_RX) | |
2435 | & MIPS16OP_MASK_RX), | |
2436 | MIPS16_REG)) | |
2437 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2438 | && insn_uses_reg (ip, | |
2439 | ((prev_insn.insn_opcode | |
2440 | >> MIPS16OP_SH_RY) | |
2441 | & MIPS16OP_MASK_RY), | |
2442 | MIPS16_REG)) | |
2443 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2444 | && insn_uses_reg (ip, | |
2445 | ((prev_insn.insn_opcode | |
2446 | >> MIPS16OP_SH_RZ) | |
2447 | & MIPS16OP_MASK_RZ), | |
2448 | MIPS16_REG)) | |
2449 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2450 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2451 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2452 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2453 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2454 | && insn_uses_reg (ip, | |
2455 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2456 | insn_opcode), | |
2457 | MIPS_GR_REG)))) | |
2458 | /* If the branch writes a register that the previous | |
2459 | instruction sets, we can not swap (we know that | |
2460 | branches write only to RD or to $31). */ | |
2461 | || (! mips_opts.mips16 | |
2462 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2463 | && (((pinfo & INSN_WRITE_GPR_D) | |
2464 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2465 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2466 | || ((pinfo & INSN_WRITE_GPR_31) | |
2467 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2468 | & OP_MASK_RT) | |
f9419b05 | 2469 | == RA)))) |
252b5132 RH |
2470 | || (! mips_opts.mips16 |
2471 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2472 | && (((pinfo & INSN_WRITE_GPR_D) | |
2473 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2474 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2475 | || ((pinfo & INSN_WRITE_GPR_31) | |
2476 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2477 | & OP_MASK_RD) | |
f9419b05 | 2478 | == RA)))) |
252b5132 RH |
2479 | || (mips_opts.mips16 |
2480 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2481 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2482 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2483 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2484 | == RA)))) | |
2485 | /* If the branch writes a register that the previous | |
2486 | instruction reads, we can not swap (we know that | |
2487 | branches only write to RD or to $31). */ | |
2488 | || (! mips_opts.mips16 | |
2489 | && (pinfo & INSN_WRITE_GPR_D) | |
2490 | && insn_uses_reg (&prev_insn, | |
2491 | ((ip->insn_opcode >> OP_SH_RD) | |
2492 | & OP_MASK_RD), | |
2493 | MIPS_GR_REG)) | |
2494 | || (! mips_opts.mips16 | |
2495 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2496 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2497 | || (mips_opts.mips16 |
2498 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2499 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2500 | /* If the previous previous instruction has a load |
2501 | delay, and sets a register that the branch reads, we | |
2502 | can not swap. */ | |
2503 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2504 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2505 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2506 | && ! cop_interlocks) | |
2507 | || ((prev_prev_insn.insn_mo->pinfo | |
2508 | & INSN_LOAD_MEMORY_DELAY) | |
2509 | && ! gpr_interlocks)) | |
252b5132 RH |
2510 | && insn_uses_reg (ip, |
2511 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2512 | & OP_MASK_RT), | |
2513 | MIPS_GR_REG)) | |
2514 | /* If one instruction sets a condition code and the | |
2515 | other one uses a condition code, we can not swap. */ | |
2516 | || ((pinfo & INSN_READ_COND_CODE) | |
2517 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2518 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2519 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2520 | /* If the previous instruction uses the PC, we can not | |
2521 | swap. */ | |
2522 | || (mips_opts.mips16 | |
2523 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2524 | /* If the previous instruction was extended, we can not | |
2525 | swap. */ | |
2526 | || (mips_opts.mips16 && prev_insn_extended) | |
2527 | /* If the previous instruction had a fixup in mips16 | |
2528 | mode, we can not swap. This normally means that the | |
2529 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2530 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2531 | /* If the previous instruction is a sync, sync.l, or |
2532 | sync.p, we can not swap. */ | |
f173e82e | 2533 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2534 | { |
2535 | /* We could do even better for unconditional branches to | |
2536 | portions of this object file; we could pick up the | |
2537 | instruction at the destination, put it in the delay | |
2538 | slot, and bump the destination address. */ | |
2539 | emit_nop (); | |
2540 | /* Update the previous insn information. */ | |
2541 | prev_prev_insn = *ip; | |
2542 | prev_insn.insn_mo = &dummy_opcode; | |
2543 | } | |
2544 | else | |
2545 | { | |
2546 | /* It looks like we can actually do the swap. */ | |
2547 | if (! mips_opts.mips16) | |
2548 | { | |
2549 | char *prev_f; | |
2550 | char temp[4]; | |
2551 | ||
2552 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2553 | if (!relaxed_branch) |
2554 | { | |
2555 | /* If this is not a relaxed branch, then just | |
2556 | swap the instructions. */ | |
2557 | memcpy (temp, prev_f, 4); | |
2558 | memcpy (prev_f, f, 4); | |
2559 | memcpy (f, temp, 4); | |
2560 | } | |
2561 | else | |
2562 | { | |
2563 | /* If this is a relaxed branch, then we move the | |
2564 | instruction to be placed in the delay slot to | |
2565 | the current frag, shrinking the fixed part of | |
2566 | the originating frag. If the branch occupies | |
2567 | the tail of the latter, we move it backwards, | |
2568 | into the space freed by the moved instruction. */ | |
2569 | f = frag_more (4); | |
2570 | memcpy (f, prev_f, 4); | |
2571 | prev_insn_frag->fr_fix -= 4; | |
2572 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2573 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2574 | } | |
2575 | ||
f6688943 TS |
2576 | if (prev_insn_fixp[0]) |
2577 | { | |
2578 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2579 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2580 | } | |
2581 | if (prev_insn_fixp[1]) | |
2582 | { | |
2583 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2584 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2585 | } | |
2586 | if (prev_insn_fixp[2]) | |
252b5132 | 2587 | { |
f6688943 TS |
2588 | prev_insn_fixp[2]->fx_frag = frag_now; |
2589 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2590 | } |
f5040a92 AO |
2591 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2592 | && prev_insn_frag != frag_now | |
2593 | && (prev_insn_fixp[0]->fx_r_type | |
2594 | == BFD_RELOC_MIPS_GOT_DISP | |
2595 | || (prev_insn_fixp[0]->fx_r_type | |
2596 | == BFD_RELOC_MIPS_CALL16))) | |
2597 | { | |
2598 | /* To avoid confusion in tc_gen_reloc, we must | |
2599 | ensure that this does not become a variant | |
2600 | frag. */ | |
2601 | force_new_frag = TRUE; | |
2602 | } | |
895921c9 MR |
2603 | |
2604 | if (!relaxed_branch) | |
f6688943 | 2605 | { |
895921c9 MR |
2606 | if (fixp[0]) |
2607 | { | |
2608 | fixp[0]->fx_frag = prev_insn_frag; | |
2609 | fixp[0]->fx_where = prev_insn_where; | |
2610 | } | |
2611 | if (fixp[1]) | |
2612 | { | |
2613 | fixp[1]->fx_frag = prev_insn_frag; | |
2614 | fixp[1]->fx_where = prev_insn_where; | |
2615 | } | |
2616 | if (fixp[2]) | |
2617 | { | |
2618 | fixp[2]->fx_frag = prev_insn_frag; | |
2619 | fixp[2]->fx_where = prev_insn_where; | |
2620 | } | |
f6688943 | 2621 | } |
895921c9 | 2622 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2623 | { |
895921c9 MR |
2624 | if (fixp[0]) |
2625 | fixp[0]->fx_where -= 4; | |
2626 | if (fixp[1]) | |
2627 | fixp[1]->fx_where -= 4; | |
2628 | if (fixp[2]) | |
2629 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2630 | } |
2631 | } | |
2632 | else | |
2633 | { | |
2634 | char *prev_f; | |
2635 | char temp[2]; | |
2636 | ||
f6688943 TS |
2637 | assert (prev_insn_fixp[0] == NULL); |
2638 | assert (prev_insn_fixp[1] == NULL); | |
2639 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2640 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2641 | memcpy (temp, prev_f, 2); | |
2642 | memcpy (prev_f, f, 2); | |
f6688943 | 2643 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2644 | { |
f6688943 | 2645 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2646 | memcpy (f, temp, 2); |
2647 | } | |
2648 | else | |
2649 | { | |
2650 | memcpy (f, f + 2, 2); | |
2651 | memcpy (f + 2, temp, 2); | |
2652 | } | |
f6688943 TS |
2653 | if (fixp[0]) |
2654 | { | |
2655 | fixp[0]->fx_frag = prev_insn_frag; | |
2656 | fixp[0]->fx_where = prev_insn_where; | |
2657 | } | |
2658 | if (fixp[1]) | |
2659 | { | |
2660 | fixp[1]->fx_frag = prev_insn_frag; | |
2661 | fixp[1]->fx_where = prev_insn_where; | |
2662 | } | |
2663 | if (fixp[2]) | |
252b5132 | 2664 | { |
f6688943 TS |
2665 | fixp[2]->fx_frag = prev_insn_frag; |
2666 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2667 | } |
2668 | } | |
2669 | ||
2670 | /* Update the previous insn information; leave prev_insn | |
2671 | unchanged. */ | |
2672 | prev_prev_insn = *ip; | |
2673 | } | |
2674 | prev_insn_is_delay_slot = 1; | |
2675 | ||
2676 | /* If that was an unconditional branch, forget the previous | |
2677 | insn information. */ | |
2678 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2679 | { | |
2680 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2681 | prev_insn.insn_mo = &dummy_opcode; | |
2682 | } | |
2683 | ||
f6688943 TS |
2684 | prev_insn_fixp[0] = NULL; |
2685 | prev_insn_fixp[1] = NULL; | |
2686 | prev_insn_fixp[2] = NULL; | |
2687 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2688 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2689 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2690 | prev_insn_extended = 0; |
2691 | } | |
2692 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2693 | { | |
2694 | /* We don't yet optimize a branch likely. What we should do | |
2695 | is look at the target, copy the instruction found there | |
2696 | into the delay slot, and increment the branch to jump to | |
2697 | the next instruction. */ | |
2698 | emit_nop (); | |
2699 | /* Update the previous insn information. */ | |
2700 | prev_prev_insn = *ip; | |
2701 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2702 | prev_insn_fixp[0] = NULL; |
2703 | prev_insn_fixp[1] = NULL; | |
2704 | prev_insn_fixp[2] = NULL; | |
2705 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2706 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2707 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2708 | prev_insn_extended = 0; |
2709 | } | |
2710 | else | |
2711 | { | |
2712 | /* Update the previous insn information. */ | |
2713 | if (nops > 0) | |
2714 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2715 | else | |
2716 | prev_prev_insn = prev_insn; | |
2717 | prev_insn = *ip; | |
2718 | ||
2719 | /* Any time we see a branch, we always fill the delay slot | |
2720 | immediately; since this insn is not a branch, we know it | |
2721 | is not in a delay slot. */ | |
2722 | prev_insn_is_delay_slot = 0; | |
2723 | ||
f6688943 TS |
2724 | prev_insn_fixp[0] = fixp[0]; |
2725 | prev_insn_fixp[1] = fixp[1]; | |
2726 | prev_insn_fixp[2] = fixp[2]; | |
2727 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2728 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2729 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2730 | if (mips_opts.mips16) |
2731 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2732 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2733 | } |
2734 | ||
2735 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2736 | prev_insn_unreordered = 0; | |
2737 | prev_insn_frag = frag_now; | |
2738 | prev_insn_where = f - frag_now->fr_literal; | |
2739 | prev_insn_valid = 1; | |
2740 | } | |
4d7206a2 | 2741 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2742 | { |
2743 | /* We need to record a bit of information even when we are not | |
2744 | reordering, in order to determine the base address for mips16 | |
2745 | PC relative relocs. */ | |
2746 | prev_prev_insn = prev_insn; | |
2747 | prev_insn = *ip; | |
f6688943 TS |
2748 | prev_insn_reloc_type[0] = reloc_type[0]; |
2749 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2750 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2751 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2752 | prev_insn_unreordered = 1; | |
2753 | } | |
2754 | ||
2755 | /* We just output an insn, so the next one doesn't have a label. */ | |
2756 | mips_clear_insn_labels (); | |
252b5132 RH |
2757 | } |
2758 | ||
2759 | /* This function forgets that there was any previous instruction or | |
2760 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2761 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2762 | |
2763 | static void | |
17a2f251 | 2764 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2765 | { |
2766 | if (! preserve) | |
2767 | { | |
2768 | prev_insn.insn_mo = &dummy_opcode; | |
2769 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2770 | prev_nop_frag = NULL; | |
2771 | prev_nop_frag_holds = 0; | |
2772 | prev_nop_frag_required = 0; | |
2773 | prev_nop_frag_since = 0; | |
2774 | } | |
2775 | prev_insn_valid = 0; | |
2776 | prev_insn_is_delay_slot = 0; | |
2777 | prev_insn_unreordered = 0; | |
2778 | prev_insn_extended = 0; | |
f6688943 TS |
2779 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2780 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2781 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2782 | prev_prev_insn_unreordered = 0; |
2783 | mips_clear_insn_labels (); | |
2784 | } | |
2785 | ||
2786 | /* This function must be called whenever we turn on noreorder or emit | |
2787 | something other than instructions. It inserts any NOPS which might | |
2788 | be needed by the previous instruction, and clears the information | |
2789 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2790 | instructions are to follow. */ |
252b5132 RH |
2791 | |
2792 | static void | |
17a2f251 | 2793 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2794 | { |
2795 | if (! mips_opts.noreorder) | |
2796 | { | |
2797 | int nops; | |
2798 | ||
2799 | nops = 0; | |
2800 | if ((! mips_opts.mips16 | |
81912461 ILT |
2801 | && ((prev_insn.insn_mo->pinfo |
2802 | & (INSN_LOAD_COPROC_DELAY | |
2803 | | INSN_COPROC_MOVE_DELAY | |
2804 | | INSN_WRITE_COND_CODE)) | |
2805 | && ! cop_interlocks)) | |
252b5132 RH |
2806 | || (! hilo_interlocks |
2807 | && (prev_insn.insn_mo->pinfo | |
2808 | & (INSN_READ_LO | |
2809 | | INSN_READ_HI))) | |
2810 | || (! mips_opts.mips16 | |
81912461 ILT |
2811 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2812 | && ! gpr_interlocks) | |
252b5132 | 2813 | || (! mips_opts.mips16 |
81912461 ILT |
2814 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2815 | && ! cop_mem_interlocks)) | |
252b5132 | 2816 | { |
beae10d5 | 2817 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2818 | ++nops; |
2819 | if ((! mips_opts.mips16 | |
81912461 ILT |
2820 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2821 | && ! cop_interlocks)) | |
252b5132 RH |
2822 | || (! hilo_interlocks |
2823 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2824 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2825 | ++nops; | |
2826 | ||
2827 | if (prev_insn_unreordered) | |
2828 | nops = 0; | |
2829 | } | |
2830 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2831 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2832 | && ! cop_interlocks)) | |
252b5132 RH |
2833 | || (! hilo_interlocks |
2834 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2835 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2836 | { | |
beae10d5 | 2837 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2838 | if (! prev_prev_insn_unreordered) |
2839 | ++nops; | |
2840 | } | |
2841 | ||
d766e8ec | 2842 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2843 | { |
2844 | int min_nops = 0; | |
2845 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2846 | if (strncmp (pn, "macc", 4) == 0 |
2847 | || strncmp (pn, "dmacc", 5) == 0 | |
2848 | || strncmp (pn, "dmult", 5) == 0 | |
2849 | || strstr (pn, "div")) | |
2850 | min_nops = 1; | |
60b63b72 RS |
2851 | if (nops < min_nops) |
2852 | nops = min_nops; | |
2853 | } | |
2854 | ||
252b5132 RH |
2855 | if (nops > 0) |
2856 | { | |
2857 | struct insn_label_list *l; | |
2858 | ||
2859 | if (insns) | |
2860 | { | |
2861 | /* Record the frag which holds the nop instructions, so | |
2862 | that we can remove them if we don't need them. */ | |
2863 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2864 | prev_nop_frag = frag_now; | |
2865 | prev_nop_frag_holds = nops; | |
2866 | prev_nop_frag_required = 0; | |
2867 | prev_nop_frag_since = 0; | |
2868 | } | |
2869 | ||
2870 | for (; nops > 0; --nops) | |
2871 | emit_nop (); | |
2872 | ||
2873 | if (insns) | |
2874 | { | |
2875 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2876 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2877 | frag_wane (frag_now); |
2878 | frag_new (0); | |
2879 | } | |
2880 | ||
2881 | for (l = insn_labels; l != NULL; l = l->next) | |
2882 | { | |
98aa84af AM |
2883 | valueT val; |
2884 | ||
252b5132 | 2885 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2886 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2887 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2888 | /* mips16 text labels are stored as odd. */ |
2889 | if (mips_opts.mips16) | |
f9419b05 | 2890 | ++val; |
98aa84af | 2891 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2892 | } |
2893 | } | |
2894 | } | |
2895 | ||
2896 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2897 | if (insns) |
252b5132 RH |
2898 | mips16_mark_labels (); |
2899 | ||
2900 | mips_no_prev_insn (insns); | |
2901 | } | |
2902 | ||
584892a6 RS |
2903 | /* Set up global variables for the start of a new macro. */ |
2904 | ||
2905 | static void | |
2906 | macro_start (void) | |
2907 | { | |
2908 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2909 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2910 | && (prev_insn.insn_mo->pinfo | |
2911 | & (INSN_UNCOND_BRANCH_DELAY | |
2912 | | INSN_COND_BRANCH_DELAY | |
2913 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2914 | } | |
2915 | ||
2916 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2917 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2918 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2919 | ||
2920 | static const char * | |
2921 | macro_warning (relax_substateT subtype) | |
2922 | { | |
2923 | if (subtype & RELAX_DELAY_SLOT) | |
2924 | return _("Macro instruction expanded into multiple instructions" | |
2925 | " in a branch delay slot"); | |
2926 | else if (subtype & RELAX_NOMACRO) | |
2927 | return _("Macro instruction expanded into multiple instructions"); | |
2928 | else | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2933 | ||
2934 | static void | |
2935 | macro_end (void) | |
2936 | { | |
2937 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2938 | { | |
2939 | relax_substateT subtype; | |
2940 | ||
2941 | /* Set up the relaxation warning flags. */ | |
2942 | subtype = 0; | |
2943 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2944 | subtype |= RELAX_SECOND_LONGER; | |
2945 | if (mips_opts.warn_about_macros) | |
2946 | subtype |= RELAX_NOMACRO; | |
2947 | if (mips_macro_warning.delay_slot_p) | |
2948 | subtype |= RELAX_DELAY_SLOT; | |
2949 | ||
2950 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2951 | { | |
2952 | /* Either the macro has a single implementation or both | |
2953 | implementations are longer than 4 bytes. Emit the | |
2954 | warning now. */ | |
2955 | const char *msg = macro_warning (subtype); | |
2956 | if (msg != 0) | |
2957 | as_warn (msg); | |
2958 | } | |
2959 | else | |
2960 | { | |
2961 | /* One implementation might need a warning but the other | |
2962 | definitely doesn't. */ | |
2963 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2964 | } | |
2965 | } | |
2966 | } | |
2967 | ||
252b5132 RH |
2968 | /* Build an instruction created by a macro expansion. This is passed |
2969 | a pointer to the count of instructions created so far, an | |
2970 | expression, the name of the instruction to build, an operand format | |
2971 | string, and corresponding arguments. */ | |
2972 | ||
252b5132 | 2973 | static void |
67c0d1eb | 2974 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
2975 | { |
2976 | struct mips_cl_insn insn; | |
f6688943 | 2977 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2978 | va_list args; |
252b5132 | 2979 | |
252b5132 | 2980 | va_start (args, fmt); |
252b5132 | 2981 | |
252b5132 RH |
2982 | if (mips_opts.mips16) |
2983 | { | |
67c0d1eb | 2984 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2985 | va_end (args); |
2986 | return; | |
2987 | } | |
2988 | ||
f6688943 TS |
2989 | r[0] = BFD_RELOC_UNUSED; |
2990 | r[1] = BFD_RELOC_UNUSED; | |
2991 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2992 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2993 | assert (insn.insn_mo); | |
2994 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2995 | ||
2996 | /* Search until we get a match for NAME. */ | |
2997 | while (1) | |
2998 | { | |
b34976b6 | 2999 | /* It is assumed here that macros will never generate |
deec1734 | 3000 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3001 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3002 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3003 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3004 | (mips_opts.isa | |
3396de36 | 3005 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3006 | mips_opts.arch) |
3007 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3008 | break; |
3009 | ||
3010 | ++insn.insn_mo; | |
3011 | assert (insn.insn_mo->name); | |
3012 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3013 | } | |
3014 | ||
3015 | insn.insn_opcode = insn.insn_mo->match; | |
3016 | for (;;) | |
3017 | { | |
3018 | switch (*fmt++) | |
3019 | { | |
3020 | case '\0': | |
3021 | break; | |
3022 | ||
3023 | case ',': | |
3024 | case '(': | |
3025 | case ')': | |
3026 | continue; | |
3027 | ||
5f74bc13 CD |
3028 | case '+': |
3029 | switch (*fmt++) | |
3030 | { | |
3031 | case 'A': | |
3032 | case 'E': | |
3033 | insn.insn_opcode |= (va_arg (args, int) | |
3034 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3035 | continue; | |
3036 | ||
3037 | case 'B': | |
3038 | case 'F': | |
3039 | /* Note that in the macro case, these arguments are already | |
3040 | in MSB form. (When handling the instruction in the | |
3041 | non-macro case, these arguments are sizes from which | |
3042 | MSB values must be calculated.) */ | |
3043 | insn.insn_opcode |= (va_arg (args, int) | |
3044 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3045 | continue; | |
3046 | ||
3047 | case 'C': | |
3048 | case 'G': | |
3049 | case 'H': | |
3050 | /* Note that in the macro case, these arguments are already | |
3051 | in MSBD form. (When handling the instruction in the | |
3052 | non-macro case, these arguments are sizes from which | |
3053 | MSBD values must be calculated.) */ | |
3054 | insn.insn_opcode |= (va_arg (args, int) | |
3055 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3056 | continue; | |
3057 | ||
3058 | default: | |
3059 | internalError (); | |
3060 | } | |
3061 | continue; | |
3062 | ||
252b5132 RH |
3063 | case 't': |
3064 | case 'w': | |
3065 | case 'E': | |
38487616 | 3066 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3067 | continue; |
3068 | ||
3069 | case 'c': | |
38487616 TS |
3070 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3071 | continue; | |
3072 | ||
252b5132 RH |
3073 | case 'T': |
3074 | case 'W': | |
38487616 | 3075 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3076 | continue; |
3077 | ||
3078 | case 'd': | |
3079 | case 'G': | |
af7ee8bf | 3080 | case 'K': |
38487616 | 3081 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3082 | continue; |
3083 | ||
4372b673 NC |
3084 | case 'U': |
3085 | { | |
3086 | int tmp = va_arg (args, int); | |
3087 | ||
38487616 TS |
3088 | insn.insn_opcode |= tmp << OP_SH_RT; |
3089 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3090 | continue; |
4372b673 NC |
3091 | } |
3092 | ||
252b5132 RH |
3093 | case 'V': |
3094 | case 'S': | |
38487616 | 3095 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3096 | continue; |
3097 | ||
3098 | case 'z': | |
3099 | continue; | |
3100 | ||
3101 | case '<': | |
38487616 | 3102 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3103 | continue; |
3104 | ||
3105 | case 'D': | |
38487616 | 3106 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3107 | continue; |
3108 | ||
3109 | case 'B': | |
38487616 | 3110 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3111 | continue; |
3112 | ||
4372b673 | 3113 | case 'J': |
38487616 | 3114 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3115 | continue; |
3116 | ||
252b5132 | 3117 | case 'q': |
38487616 | 3118 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3119 | continue; |
3120 | ||
3121 | case 'b': | |
3122 | case 's': | |
3123 | case 'r': | |
3124 | case 'v': | |
38487616 | 3125 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3126 | continue; |
3127 | ||
3128 | case 'i': | |
3129 | case 'j': | |
3130 | case 'o': | |
f6688943 | 3131 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3132 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3133 | || *r == BFD_RELOC_MIPS_LITERAL |
3134 | || *r == BFD_RELOC_MIPS_HIGHER | |
3135 | || *r == BFD_RELOC_HI16_S | |
3136 | || *r == BFD_RELOC_LO16 | |
3137 | || *r == BFD_RELOC_MIPS_GOT16 | |
3138 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3139 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3140 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3141 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3142 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3143 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3144 | continue; |
3145 | ||
3146 | case 'u': | |
f6688943 | 3147 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3148 | assert (ep != NULL |
3149 | && (ep->X_op == O_constant | |
3150 | || (ep->X_op == O_symbol | |
f6688943 TS |
3151 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3152 | || *r == BFD_RELOC_HI16_S | |
3153 | || *r == BFD_RELOC_HI16 | |
3154 | || *r == BFD_RELOC_GPREL16 | |
3155 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3156 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3157 | continue; |
3158 | ||
3159 | case 'p': | |
3160 | assert (ep != NULL); | |
3161 | /* | |
3162 | * This allows macro() to pass an immediate expression for | |
3163 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3164 | * Note that the expression still might come from the assembly |
3165 | * input, in which case the value is not checked for range nor | |
3166 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3167 | */ |
3168 | if (ep->X_op == O_constant) | |
3169 | { | |
3170 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3171 | ep = NULL; | |
3172 | } | |
3173 | else | |
0b25d3e6 | 3174 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3175 | continue; |
3176 | ||
3177 | case 'a': | |
3178 | assert (ep != NULL); | |
f6688943 | 3179 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3180 | continue; |
3181 | ||
3182 | case 'C': | |
3183 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3184 | continue; | |
3185 | ||
3186 | default: | |
3187 | internalError (); | |
3188 | } | |
3189 | break; | |
3190 | } | |
3191 | va_end (args); | |
f6688943 | 3192 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3193 | |
4d7206a2 | 3194 | append_insn (&insn, ep, r); |
252b5132 RH |
3195 | } |
3196 | ||
3197 | static void | |
67c0d1eb | 3198 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3199 | va_list args) |
252b5132 RH |
3200 | { |
3201 | struct mips_cl_insn insn; | |
f6688943 TS |
3202 | bfd_reloc_code_real_type r[3] |
3203 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3204 | |
252b5132 RH |
3205 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3206 | assert (insn.insn_mo); | |
3207 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3208 | ||
3209 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3210 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3211 | { | |
3212 | ++insn.insn_mo; | |
3213 | assert (insn.insn_mo->name); | |
3214 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3215 | } | |
3216 | ||
3217 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3218 | insn.use_extend = FALSE; |
252b5132 RH |
3219 | |
3220 | for (;;) | |
3221 | { | |
3222 | int c; | |
3223 | ||
3224 | c = *fmt++; | |
3225 | switch (c) | |
3226 | { | |
3227 | case '\0': | |
3228 | break; | |
3229 | ||
3230 | case ',': | |
3231 | case '(': | |
3232 | case ')': | |
3233 | continue; | |
3234 | ||
3235 | case 'y': | |
3236 | case 'w': | |
3237 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3238 | continue; | |
3239 | ||
3240 | case 'x': | |
3241 | case 'v': | |
3242 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3243 | continue; | |
3244 | ||
3245 | case 'z': | |
3246 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3247 | continue; | |
3248 | ||
3249 | case 'Z': | |
3250 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3251 | continue; | |
3252 | ||
3253 | case '0': | |
3254 | case 'S': | |
3255 | case 'P': | |
3256 | case 'R': | |
3257 | continue; | |
3258 | ||
3259 | case 'X': | |
3260 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3261 | continue; | |
3262 | ||
3263 | case 'Y': | |
3264 | { | |
3265 | int regno; | |
3266 | ||
3267 | regno = va_arg (args, int); | |
3268 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3269 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3270 | } | |
3271 | continue; | |
3272 | ||
3273 | case '<': | |
3274 | case '>': | |
3275 | case '4': | |
3276 | case '5': | |
3277 | case 'H': | |
3278 | case 'W': | |
3279 | case 'D': | |
3280 | case 'j': | |
3281 | case '8': | |
3282 | case 'V': | |
3283 | case 'C': | |
3284 | case 'U': | |
3285 | case 'k': | |
3286 | case 'K': | |
3287 | case 'p': | |
3288 | case 'q': | |
3289 | { | |
3290 | assert (ep != NULL); | |
3291 | ||
3292 | if (ep->X_op != O_constant) | |
874e8986 | 3293 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3294 | else |
3295 | { | |
b34976b6 AM |
3296 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3297 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3298 | &insn.extend); |
252b5132 | 3299 | ep = NULL; |
f6688943 | 3300 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3301 | } |
3302 | } | |
3303 | continue; | |
3304 | ||
3305 | case '6': | |
3306 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3307 | continue; | |
3308 | } | |
3309 | ||
3310 | break; | |
3311 | } | |
3312 | ||
f6688943 | 3313 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3314 | |
4d7206a2 | 3315 | append_insn (&insn, ep, r); |
252b5132 RH |
3316 | } |
3317 | ||
438c16b8 TS |
3318 | /* |
3319 | * Generate a "jalr" instruction with a relocation hint to the called | |
3320 | * function. This occurs in NewABI PIC code. | |
3321 | */ | |
3322 | static void | |
67c0d1eb | 3323 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3324 | { |
685736be | 3325 | char *f = NULL; |
b34976b6 | 3326 | |
438c16b8 | 3327 | if (HAVE_NEWABI) |
f21f8242 | 3328 | { |
cc3d92a5 | 3329 | frag_grow (8); |
f21f8242 AO |
3330 | f = frag_more (0); |
3331 | } | |
67c0d1eb | 3332 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3333 | if (HAVE_NEWABI) |
f21f8242 | 3334 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3335 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3336 | } |
3337 | ||
252b5132 RH |
3338 | /* |
3339 | * Generate a "lui" instruction. | |
3340 | */ | |
3341 | static void | |
67c0d1eb | 3342 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3343 | { |
3344 | expressionS high_expr; | |
3345 | struct mips_cl_insn insn; | |
f6688943 TS |
3346 | bfd_reloc_code_real_type r[3] |
3347 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3348 | const char *name = "lui"; |
3349 | const char *fmt = "t,u"; | |
252b5132 RH |
3350 | |
3351 | assert (! mips_opts.mips16); | |
3352 | ||
4d7206a2 | 3353 | high_expr = *ep; |
252b5132 RH |
3354 | |
3355 | if (high_expr.X_op == O_constant) | |
3356 | { | |
3357 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3358 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3359 | >> 16) & 0xffff; | |
f6688943 | 3360 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3361 | } |
78e1bb40 | 3362 | else |
252b5132 RH |
3363 | { |
3364 | assert (ep->X_op == O_symbol); | |
3365 | /* _gp_disp is a special case, used from s_cpload. */ | |
3366 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3367 | || (! HAVE_NEWABI |
3368 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3369 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3370 | } |
3371 | ||
252b5132 RH |
3372 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3373 | assert (insn.insn_mo); | |
3374 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3375 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3376 | ||
3377 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3378 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3379 | { |
3380 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3381 | append_insn (&insn, NULL, r); |
252b5132 RH |
3382 | } |
3383 | else | |
4d7206a2 | 3384 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3385 | } |
3386 | ||
885add95 CD |
3387 | /* Generate a sequence of instructions to do a load or store from a constant |
3388 | offset off of a base register (breg) into/from a target register (treg), | |
3389 | using AT if necessary. */ | |
3390 | static void | |
67c0d1eb RS |
3391 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3392 | int treg, int breg, int dbl) | |
885add95 CD |
3393 | { |
3394 | assert (ep->X_op == O_constant); | |
3395 | ||
256ab948 | 3396 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3397 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3398 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3399 | { |
d17e7bce | 3400 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3401 | as_bad (_("constant too large")); |
ae826530 | 3402 | |
1b8e29e5 TS |
3403 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3404 | - 0x80000000); | |
ae826530 | 3405 | } |
256ab948 | 3406 | |
67c1ffbe | 3407 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3408 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3409 | as_warn (_("operand overflow")); |
3410 | ||
3411 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3412 | { | |
3413 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3414 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3415 | } |
3416 | else | |
3417 | { | |
3418 | /* 32-bit offset, need multiple instructions and AT, like: | |
3419 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3420 | addu $tempreg,$tempreg,$breg | |
3421 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3422 | to handle the complete offset. */ | |
67c0d1eb RS |
3423 | macro_build_lui (ep, AT); |
3424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3425 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3426 | |
3427 | if (mips_opts.noat) | |
3428 | as_warn (_("Macro used $at after \".set noat\"")); | |
3429 | } | |
3430 | } | |
3431 | ||
252b5132 RH |
3432 | /* set_at() |
3433 | * Generates code to set the $at register to true (one) | |
3434 | * if reg is less than the immediate expression. | |
3435 | */ | |
3436 | static void | |
67c0d1eb | 3437 | set_at (int reg, int unsignedp) |
252b5132 RH |
3438 | { |
3439 | if (imm_expr.X_op == O_constant | |
3440 | && imm_expr.X_add_number >= -0x8000 | |
3441 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3442 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3443 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3444 | else |
3445 | { | |
67c0d1eb RS |
3446 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3447 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3448 | } |
3449 | } | |
3450 | ||
13757d0c TS |
3451 | static void |
3452 | normalize_constant_expr (expressionS *ex) | |
3453 | { | |
3454 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3455 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3456 | - 0x80000000); | |
3457 | } | |
3458 | ||
252b5132 RH |
3459 | /* Warn if an expression is not a constant. */ |
3460 | ||
3461 | static void | |
17a2f251 | 3462 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3463 | { |
3464 | if (ex->X_op == O_big) | |
3465 | as_bad (_("unsupported large constant")); | |
3466 | else if (ex->X_op != O_constant) | |
3467 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3468 | |
3469 | normalize_constant_expr (ex); | |
252b5132 RH |
3470 | } |
3471 | ||
3472 | /* Count the leading zeroes by performing a binary chop. This is a | |
3473 | bulky bit of source, but performance is a LOT better for the | |
3474 | majority of values than a simple loop to count the bits: | |
3475 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3476 | if ((v) & (1 << (31 - lcnt))) | |
3477 | break; | |
3478 | However it is not code size friendly, and the gain will drop a bit | |
3479 | on certain cached systems. | |
3480 | */ | |
3481 | #define COUNT_TOP_ZEROES(v) \ | |
3482 | (((v) & ~0xffff) == 0 \ | |
3483 | ? ((v) & ~0xff) == 0 \ | |
3484 | ? ((v) & ~0xf) == 0 \ | |
3485 | ? ((v) & ~0x3) == 0 \ | |
3486 | ? ((v) & ~0x1) == 0 \ | |
3487 | ? !(v) \ | |
3488 | ? 32 \ | |
3489 | : 31 \ | |
3490 | : 30 \ | |
3491 | : ((v) & ~0x7) == 0 \ | |
3492 | ? 29 \ | |
3493 | : 28 \ | |
3494 | : ((v) & ~0x3f) == 0 \ | |
3495 | ? ((v) & ~0x1f) == 0 \ | |
3496 | ? 27 \ | |
3497 | : 26 \ | |
3498 | : ((v) & ~0x7f) == 0 \ | |
3499 | ? 25 \ | |
3500 | : 24 \ | |
3501 | : ((v) & ~0xfff) == 0 \ | |
3502 | ? ((v) & ~0x3ff) == 0 \ | |
3503 | ? ((v) & ~0x1ff) == 0 \ | |
3504 | ? 23 \ | |
3505 | : 22 \ | |
3506 | : ((v) & ~0x7ff) == 0 \ | |
3507 | ? 21 \ | |
3508 | : 20 \ | |
3509 | : ((v) & ~0x3fff) == 0 \ | |
3510 | ? ((v) & ~0x1fff) == 0 \ | |
3511 | ? 19 \ | |
3512 | : 18 \ | |
3513 | : ((v) & ~0x7fff) == 0 \ | |
3514 | ? 17 \ | |
3515 | : 16 \ | |
3516 | : ((v) & ~0xffffff) == 0 \ | |
3517 | ? ((v) & ~0xfffff) == 0 \ | |
3518 | ? ((v) & ~0x3ffff) == 0 \ | |
3519 | ? ((v) & ~0x1ffff) == 0 \ | |
3520 | ? 15 \ | |
3521 | : 14 \ | |
3522 | : ((v) & ~0x7ffff) == 0 \ | |
3523 | ? 13 \ | |
3524 | : 12 \ | |
3525 | : ((v) & ~0x3fffff) == 0 \ | |
3526 | ? ((v) & ~0x1fffff) == 0 \ | |
3527 | ? 11 \ | |
3528 | : 10 \ | |
3529 | : ((v) & ~0x7fffff) == 0 \ | |
3530 | ? 9 \ | |
3531 | : 8 \ | |
3532 | : ((v) & ~0xfffffff) == 0 \ | |
3533 | ? ((v) & ~0x3ffffff) == 0 \ | |
3534 | ? ((v) & ~0x1ffffff) == 0 \ | |
3535 | ? 7 \ | |
3536 | : 6 \ | |
3537 | : ((v) & ~0x7ffffff) == 0 \ | |
3538 | ? 5 \ | |
3539 | : 4 \ | |
3540 | : ((v) & ~0x3fffffff) == 0 \ | |
3541 | ? ((v) & ~0x1fffffff) == 0 \ | |
3542 | ? 3 \ | |
3543 | : 2 \ | |
3544 | : ((v) & ~0x7fffffff) == 0 \ | |
3545 | ? 1 \ | |
3546 | : 0) | |
3547 | ||
3548 | /* load_register() | |
67c1ffbe | 3549 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3550 | * an absolute expression value into a register. |
3551 | */ | |
3552 | static void | |
67c0d1eb | 3553 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3554 | { |
3555 | int freg; | |
3556 | expressionS hi32, lo32; | |
3557 | ||
3558 | if (ep->X_op != O_big) | |
3559 | { | |
3560 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3561 | |
3562 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3563 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3564 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3565 | { |
d17e7bce | 3566 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3567 | as_bad (_("constant too large")); |
ae826530 | 3568 | |
1b8e29e5 TS |
3569 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3570 | - 0x80000000); | |
ae826530 | 3571 | } |
256ab948 TS |
3572 | |
3573 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3574 | { |
3575 | /* We can handle 16 bit signed values with an addiu to | |
3576 | $zero. No need to ever use daddiu here, since $zero and | |
3577 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3578 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3579 | return; |
3580 | } | |
3581 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3582 | { | |
3583 | /* We can handle 16 bit unsigned values with an ori to | |
3584 | $zero. */ | |
67c0d1eb | 3585 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3586 | return; |
3587 | } | |
256ab948 | 3588 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3589 | { |
3590 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3591 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3592 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3593 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3594 | return; |
3595 | } | |
3596 | } | |
3597 | ||
3598 | /* The value is larger than 32 bits. */ | |
3599 | ||
ca4e0257 | 3600 | if (HAVE_32BIT_GPRS) |
252b5132 | 3601 | { |
956cd1d6 TS |
3602 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3603 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3604 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3605 | return; |
3606 | } | |
3607 | ||
3608 | if (ep->X_op != O_big) | |
3609 | { | |
3610 | hi32 = *ep; | |
3611 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3612 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3613 | hi32.X_add_number &= 0xffffffff; | |
3614 | lo32 = *ep; | |
3615 | lo32.X_add_number &= 0xffffffff; | |
3616 | } | |
3617 | else | |
3618 | { | |
3619 | assert (ep->X_add_number > 2); | |
3620 | if (ep->X_add_number == 3) | |
3621 | generic_bignum[3] = 0; | |
3622 | else if (ep->X_add_number > 4) | |
3623 | as_bad (_("Number larger than 64 bits")); | |
3624 | lo32.X_op = O_constant; | |
3625 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3626 | hi32.X_op = O_constant; | |
3627 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3628 | } | |
3629 | ||
3630 | if (hi32.X_add_number == 0) | |
3631 | freg = 0; | |
3632 | else | |
3633 | { | |
3634 | int shift, bit; | |
3635 | unsigned long hi, lo; | |
3636 | ||
956cd1d6 | 3637 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3638 | { |
3639 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3640 | { | |
67c0d1eb | 3641 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3642 | return; |
3643 | } | |
3644 | if (lo32.X_add_number & 0x80000000) | |
3645 | { | |
67c0d1eb | 3646 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3647 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3648 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3649 | return; |
3650 | } | |
3651 | } | |
252b5132 RH |
3652 | |
3653 | /* Check for 16bit shifted constant. We know that hi32 is | |
3654 | non-zero, so start the mask on the first bit of the hi32 | |
3655 | value. */ | |
3656 | shift = 17; | |
3657 | do | |
beae10d5 KH |
3658 | { |
3659 | unsigned long himask, lomask; | |
3660 | ||
3661 | if (shift < 32) | |
3662 | { | |
3663 | himask = 0xffff >> (32 - shift); | |
3664 | lomask = (0xffff << shift) & 0xffffffff; | |
3665 | } | |
3666 | else | |
3667 | { | |
3668 | himask = 0xffff << (shift - 32); | |
3669 | lomask = 0; | |
3670 | } | |
3671 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3672 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3673 | { | |
3674 | expressionS tmp; | |
3675 | ||
3676 | tmp.X_op = O_constant; | |
3677 | if (shift < 32) | |
3678 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3679 | | (lo32.X_add_number >> shift)); | |
3680 | else | |
3681 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3682 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3683 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3684 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3685 | return; |
3686 | } | |
f9419b05 | 3687 | ++shift; |
beae10d5 KH |
3688 | } |
3689 | while (shift <= (64 - 16)); | |
252b5132 RH |
3690 | |
3691 | /* Find the bit number of the lowest one bit, and store the | |
3692 | shifted value in hi/lo. */ | |
3693 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3694 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3695 | if (lo != 0) | |
3696 | { | |
3697 | bit = 0; | |
3698 | while ((lo & 1) == 0) | |
3699 | { | |
3700 | lo >>= 1; | |
3701 | ++bit; | |
3702 | } | |
3703 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3704 | hi >>= bit; | |
3705 | } | |
3706 | else | |
3707 | { | |
3708 | bit = 32; | |
3709 | while ((hi & 1) == 0) | |
3710 | { | |
3711 | hi >>= 1; | |
3712 | ++bit; | |
3713 | } | |
3714 | lo = hi; | |
3715 | hi = 0; | |
3716 | } | |
3717 | ||
3718 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3719 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3720 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3721 | { |
3722 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3723 | if (shift != 0) |
beae10d5 | 3724 | { |
252b5132 RH |
3725 | expressionS tmp; |
3726 | ||
3727 | /* This instruction will set the register to be all | |
3728 | ones. */ | |
beae10d5 KH |
3729 | tmp.X_op = O_constant; |
3730 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3731 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3732 | if (bit != 0) |
3733 | { | |
3734 | bit += shift; | |
67c0d1eb RS |
3735 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3736 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3737 | } |
67c0d1eb RS |
3738 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3739 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3740 | return; |
3741 | } | |
3742 | } | |
252b5132 RH |
3743 | |
3744 | /* Sign extend hi32 before calling load_register, because we can | |
3745 | generally get better code when we load a sign extended value. */ | |
3746 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3747 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3748 | load_register (reg, &hi32, 0); |
252b5132 RH |
3749 | freg = reg; |
3750 | } | |
3751 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3752 | { | |
3753 | if (freg != 0) | |
3754 | { | |
67c0d1eb | 3755 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3756 | freg = reg; |
3757 | } | |
3758 | } | |
3759 | else | |
3760 | { | |
3761 | expressionS mid16; | |
3762 | ||
956cd1d6 | 3763 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3764 | { |
67c0d1eb RS |
3765 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3766 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3767 | return; |
3768 | } | |
252b5132 RH |
3769 | |
3770 | if (freg != 0) | |
3771 | { | |
67c0d1eb | 3772 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3773 | freg = reg; |
3774 | } | |
3775 | mid16 = lo32; | |
3776 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3777 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3778 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3779 | freg = reg; |
3780 | } | |
3781 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3782 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3783 | } |
3784 | ||
269137b2 TS |
3785 | static inline void |
3786 | load_delay_nop (void) | |
3787 | { | |
3788 | if (!gpr_interlocks) | |
3789 | macro_build (NULL, "nop", ""); | |
3790 | } | |
3791 | ||
252b5132 RH |
3792 | /* Load an address into a register. */ |
3793 | ||
3794 | static void | |
67c0d1eb | 3795 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3796 | { |
252b5132 RH |
3797 | if (ep->X_op != O_constant |
3798 | && ep->X_op != O_symbol) | |
3799 | { | |
3800 | as_bad (_("expression too complex")); | |
3801 | ep->X_op = O_constant; | |
3802 | } | |
3803 | ||
3804 | if (ep->X_op == O_constant) | |
3805 | { | |
67c0d1eb | 3806 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3807 | return; |
3808 | } | |
3809 | ||
3810 | if (mips_pic == NO_PIC) | |
3811 | { | |
3812 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3813 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3814 | Otherwise we want |
3815 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3816 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3817 | If we have an addend, we always use the latter form. |
76b3015f | 3818 | |
d6bc6245 TS |
3819 | With 64bit address space and a usable $at we want |
3820 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3821 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3822 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3823 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3824 | dsll32 $reg,0 | |
3a482fd5 | 3825 | daddu $reg,$reg,$at |
76b3015f | 3826 | |
c03099e6 | 3827 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3828 | on superscalar processors. |
3829 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3830 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3831 | dsll $reg,16 | |
3832 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3833 | dsll $reg,16 | |
3834 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3835 | */ | |
c9914766 | 3836 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3837 | { |
e864ceca RS |
3838 | /* ??? We don't provide a GP-relative alternative for these macros. |
3839 | It used not to be possible with the original relaxation code, | |
3840 | but it could be done now. */ | |
d6bc6245 | 3841 | |
460597ba | 3842 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 3843 | { |
67c0d1eb RS |
3844 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3845 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3846 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3847 | BFD_RELOC_MIPS_HIGHER); | |
3848 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3849 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3850 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3851 | *used_at = 1; |
3852 | } | |
3853 | else | |
3854 | { | |
67c0d1eb RS |
3855 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3856 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3857 | BFD_RELOC_MIPS_HIGHER); | |
3858 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3859 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3860 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3861 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3862 | } |
3863 | } | |
252b5132 RH |
3864 | else |
3865 | { | |
d6bc6245 TS |
3866 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3867 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3868 | { | |
4d7206a2 | 3869 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3870 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3871 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3872 | relax_switch (); |
d6bc6245 | 3873 | } |
67c0d1eb RS |
3874 | macro_build_lui (ep, reg); |
3875 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3876 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3877 | if (mips_relax.sequence) |
3878 | relax_end (); | |
d6bc6245 | 3879 | } |
252b5132 RH |
3880 | } |
3881 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3882 | { | |
3883 | expressionS ex; | |
3884 | ||
3885 | /* If this is a reference to an external symbol, we want | |
3886 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3887 | Otherwise we want | |
3888 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3889 | nop | |
3890 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3891 | If there is a constant, it must be added in after. |
3892 | ||
ed6fb7bd | 3893 | If we have NewABI, we want |
f5040a92 AO |
3894 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3895 | unless we're referencing a global symbol with a non-zero | |
3896 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3897 | if (HAVE_NEWABI) |
3898 | { | |
f5040a92 AO |
3899 | if (ep->X_add_number) |
3900 | { | |
4d7206a2 | 3901 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3902 | ep->X_add_number = 0; |
4d7206a2 | 3903 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3904 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3905 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3906 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3907 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3908 | ex.X_op = O_constant; | |
67c0d1eb | 3909 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3910 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3911 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3912 | relax_switch (); |
f5040a92 | 3913 | } |
67c0d1eb | 3914 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3915 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3916 | if (mips_relax.sequence) |
3917 | relax_end (); | |
ed6fb7bd SC |
3918 | } |
3919 | else | |
3920 | { | |
f5040a92 AO |
3921 | ex.X_add_number = ep->X_add_number; |
3922 | ep->X_add_number = 0; | |
67c0d1eb RS |
3923 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3924 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3925 | load_delay_nop (); |
4d7206a2 RS |
3926 | relax_start (ep->X_add_symbol); |
3927 | relax_switch (); | |
67c0d1eb | 3928 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3929 | BFD_RELOC_LO16); |
4d7206a2 | 3930 | relax_end (); |
ed6fb7bd | 3931 | |
f5040a92 AO |
3932 | if (ex.X_add_number != 0) |
3933 | { | |
3934 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3935 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3936 | ex.X_op = O_constant; | |
67c0d1eb | 3937 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3938 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3939 | } |
252b5132 RH |
3940 | } |
3941 | } | |
3942 | else if (mips_pic == SVR4_PIC) | |
3943 | { | |
3944 | expressionS ex; | |
252b5132 RH |
3945 | |
3946 | /* This is the large GOT case. If this is a reference to an | |
3947 | external symbol, we want | |
3948 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3949 | addu $reg,$reg,$gp | |
3950 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3951 | |
3952 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3953 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3954 | nop | |
3955 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3956 | If there is a constant, it must be added in after. |
f5040a92 AO |
3957 | |
3958 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3959 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3960 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3961 | */ |
438c16b8 TS |
3962 | if (HAVE_NEWABI) |
3963 | { | |
4d7206a2 | 3964 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3965 | ep->X_add_number = 0; |
4d7206a2 | 3966 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3967 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3968 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3969 | reg, reg, mips_gp_register); | |
3970 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3971 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3972 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3973 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3974 | else if (ex.X_add_number) | |
3975 | { | |
3976 | ex.X_op = O_constant; | |
67c0d1eb RS |
3977 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3978 | BFD_RELOC_LO16); | |
f5040a92 AO |
3979 | } |
3980 | ||
3981 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3982 | relax_switch (); |
67c0d1eb | 3983 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3984 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3985 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3986 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3987 | relax_end (); |
438c16b8 | 3988 | } |
252b5132 | 3989 | else |
438c16b8 | 3990 | { |
f5040a92 AO |
3991 | ex.X_add_number = ep->X_add_number; |
3992 | ep->X_add_number = 0; | |
4d7206a2 | 3993 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3994 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3995 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3996 | reg, reg, mips_gp_register); | |
3997 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3998 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3999 | relax_switch (); |
4000 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4001 | { |
4002 | /* We need a nop before loading from $gp. This special | |
4003 | check is required because the lui which starts the main | |
4004 | instruction stream does not refer to $gp, and so will not | |
4005 | insert the nop which may be required. */ | |
67c0d1eb | 4006 | macro_build (NULL, "nop", ""); |
438c16b8 | 4007 | } |
67c0d1eb | 4008 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4009 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4010 | load_delay_nop (); |
67c0d1eb | 4011 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4012 | BFD_RELOC_LO16); |
4d7206a2 | 4013 | relax_end (); |
438c16b8 | 4014 | |
f5040a92 AO |
4015 | if (ex.X_add_number != 0) |
4016 | { | |
4017 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4018 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4019 | ex.X_op = O_constant; | |
67c0d1eb RS |
4020 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4021 | BFD_RELOC_LO16); | |
f5040a92 | 4022 | } |
252b5132 RH |
4023 | } |
4024 | } | |
252b5132 RH |
4025 | else |
4026 | abort (); | |
4027 | } | |
4028 | ||
ea1fb5dc RS |
4029 | /* Move the contents of register SOURCE into register DEST. */ |
4030 | ||
4031 | static void | |
67c0d1eb | 4032 | move_register (int dest, int source) |
ea1fb5dc | 4033 | { |
67c0d1eb RS |
4034 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4035 | dest, source, 0); | |
ea1fb5dc RS |
4036 | } |
4037 | ||
4d7206a2 | 4038 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4039 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4040 | The two alternatives are: | |
4d7206a2 RS |
4041 | |
4042 | Global symbol Local sybmol | |
4043 | ------------- ------------ | |
4044 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4045 | ... ... | |
4046 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4047 | ||
4048 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4049 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4050 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4051 | |
4052 | static void | |
67c0d1eb | 4053 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4054 | { |
4055 | expressionS global; | |
4056 | ||
4057 | global = *local; | |
4058 | global.X_add_number = 0; | |
4059 | ||
4060 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4061 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4062 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4063 | relax_switch (); |
67c0d1eb RS |
4064 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4065 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4066 | relax_end (); |
4067 | } | |
4068 | ||
4069 | static void | |
67c0d1eb | 4070 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4071 | { |
4072 | expressionS global; | |
4073 | ||
4074 | global.X_op = O_constant; | |
4075 | global.X_op_symbol = NULL; | |
4076 | global.X_add_symbol = NULL; | |
4077 | global.X_add_number = local->X_add_number; | |
4078 | ||
4079 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4080 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4081 | dest, dest, BFD_RELOC_LO16); |
4082 | relax_switch (); | |
67c0d1eb | 4083 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4084 | relax_end (); |
4085 | } | |
4086 | ||
f6a22291 MR |
4087 | static void |
4088 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4089 | { | |
4090 | expressionS global; | |
4091 | int hold_mips_optimize; | |
4092 | ||
4093 | global.X_op = O_constant; | |
4094 | global.X_op_symbol = NULL; | |
4095 | global.X_add_symbol = NULL; | |
4096 | global.X_add_number = local->X_add_number; | |
4097 | ||
4098 | relax_start (local->X_add_symbol); | |
4099 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4100 | relax_switch (); | |
4101 | /* Set mips_optimize around the lui instruction to avoid | |
4102 | inserting an unnecessary nop after the lw. */ | |
4103 | hold_mips_optimize = mips_optimize; | |
4104 | mips_optimize = 2; | |
4105 | macro_build_lui (&global, tmp); | |
4106 | mips_optimize = hold_mips_optimize; | |
4107 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4108 | relax_end (); | |
4109 | ||
4110 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4111 | } | |
4112 | ||
252b5132 RH |
4113 | /* |
4114 | * Build macros | |
4115 | * This routine implements the seemingly endless macro or synthesized | |
4116 | * instructions and addressing modes in the mips assembly language. Many | |
4117 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4118 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4119 | * this verbose method. Others are not simple macros but are more like |
4120 | * optimizing code generation. | |
4121 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4122 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4123 | * The ensuing load upper instructions are ommited. This implies some kind |
4124 | * of global optimization. We currently only optimize within a single macro. | |
4125 | * For many of the load and store macros if the address is specified as a | |
4126 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4127 | * first load register 'at' with zero and use it as the base register. The | |
4128 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4129 | * we're missing. | |
4130 | */ | |
4131 | static void | |
17a2f251 | 4132 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4133 | { |
4134 | register int treg, sreg, dreg, breg; | |
4135 | int tempreg; | |
4136 | int mask; | |
43841e91 | 4137 | int used_at = 0; |
252b5132 RH |
4138 | expressionS expr1; |
4139 | const char *s; | |
4140 | const char *s2; | |
4141 | const char *fmt; | |
4142 | int likely = 0; | |
4143 | int dbl = 0; | |
4144 | int coproc = 0; | |
4145 | int lr = 0; | |
4146 | int imm = 0; | |
1abe91b1 | 4147 | int call = 0; |
252b5132 | 4148 | int off; |
67c0d1eb | 4149 | offsetT maxnum; |
252b5132 | 4150 | bfd_reloc_code_real_type r; |
252b5132 RH |
4151 | int hold_mips_optimize; |
4152 | ||
4153 | assert (! mips_opts.mips16); | |
4154 | ||
4155 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4156 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4157 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4158 | mask = ip->insn_mo->mask; | |
4159 | ||
4160 | expr1.X_op = O_constant; | |
4161 | expr1.X_op_symbol = NULL; | |
4162 | expr1.X_add_symbol = NULL; | |
4163 | expr1.X_add_number = 1; | |
4164 | ||
4165 | switch (mask) | |
4166 | { | |
4167 | case M_DABS: | |
4168 | dbl = 1; | |
4169 | case M_ABS: | |
4170 | /* bgez $a0,.+12 | |
4171 | move v0,$a0 | |
4172 | sub v0,$zero,$a0 | |
4173 | */ | |
4174 | ||
b34976b6 | 4175 | mips_emit_delays (TRUE); |
252b5132 RH |
4176 | ++mips_opts.noreorder; |
4177 | mips_any_noreorder = 1; | |
4178 | ||
4179 | expr1.X_add_number = 8; | |
67c0d1eb | 4180 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4181 | if (dreg == sreg) |
67c0d1eb | 4182 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4183 | else |
67c0d1eb RS |
4184 | move_register (dreg, sreg); |
4185 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4186 | |
4187 | --mips_opts.noreorder; | |
4188 | return; | |
4189 | ||
4190 | case M_ADD_I: | |
4191 | s = "addi"; | |
4192 | s2 = "add"; | |
4193 | goto do_addi; | |
4194 | case M_ADDU_I: | |
4195 | s = "addiu"; | |
4196 | s2 = "addu"; | |
4197 | goto do_addi; | |
4198 | case M_DADD_I: | |
4199 | dbl = 1; | |
4200 | s = "daddi"; | |
4201 | s2 = "dadd"; | |
4202 | goto do_addi; | |
4203 | case M_DADDU_I: | |
4204 | dbl = 1; | |
4205 | s = "daddiu"; | |
4206 | s2 = "daddu"; | |
4207 | do_addi: | |
4208 | if (imm_expr.X_op == O_constant | |
4209 | && imm_expr.X_add_number >= -0x8000 | |
4210 | && imm_expr.X_add_number < 0x8000) | |
4211 | { | |
67c0d1eb | 4212 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4213 | return; |
4214 | } | |
67c0d1eb RS |
4215 | load_register (AT, &imm_expr, dbl); |
4216 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4217 | break; |
4218 | ||
4219 | case M_AND_I: | |
4220 | s = "andi"; | |
4221 | s2 = "and"; | |
4222 | goto do_bit; | |
4223 | case M_OR_I: | |
4224 | s = "ori"; | |
4225 | s2 = "or"; | |
4226 | goto do_bit; | |
4227 | case M_NOR_I: | |
4228 | s = ""; | |
4229 | s2 = "nor"; | |
4230 | goto do_bit; | |
4231 | case M_XOR_I: | |
4232 | s = "xori"; | |
4233 | s2 = "xor"; | |
4234 | do_bit: | |
4235 | if (imm_expr.X_op == O_constant | |
4236 | && imm_expr.X_add_number >= 0 | |
4237 | && imm_expr.X_add_number < 0x10000) | |
4238 | { | |
4239 | if (mask != M_NOR_I) | |
67c0d1eb | 4240 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4241 | else |
4242 | { | |
67c0d1eb RS |
4243 | macro_build (&imm_expr, "ori", "t,r,i", |
4244 | treg, sreg, BFD_RELOC_LO16); | |
4245 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4246 | } |
4247 | return; | |
4248 | } | |
4249 | ||
67c0d1eb RS |
4250 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4251 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4252 | break; |
4253 | ||
4254 | case M_BEQ_I: | |
4255 | s = "beq"; | |
4256 | goto beq_i; | |
4257 | case M_BEQL_I: | |
4258 | s = "beql"; | |
4259 | likely = 1; | |
4260 | goto beq_i; | |
4261 | case M_BNE_I: | |
4262 | s = "bne"; | |
4263 | goto beq_i; | |
4264 | case M_BNEL_I: | |
4265 | s = "bnel"; | |
4266 | likely = 1; | |
4267 | beq_i: | |
4268 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4269 | { | |
67c0d1eb | 4270 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4271 | return; |
4272 | } | |
67c0d1eb RS |
4273 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4274 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4275 | break; |
4276 | ||
4277 | case M_BGEL: | |
4278 | likely = 1; | |
4279 | case M_BGE: | |
4280 | if (treg == 0) | |
4281 | { | |
67c0d1eb | 4282 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4283 | return; |
4284 | } | |
4285 | if (sreg == 0) | |
4286 | { | |
67c0d1eb | 4287 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4288 | return; |
4289 | } | |
67c0d1eb RS |
4290 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4291 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4292 | break; |
4293 | ||
4294 | case M_BGTL_I: | |
4295 | likely = 1; | |
4296 | case M_BGT_I: | |
4297 | /* check for > max integer */ | |
4298 | maxnum = 0x7fffffff; | |
ca4e0257 | 4299 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4300 | { |
4301 | maxnum <<= 16; | |
4302 | maxnum |= 0xffff; | |
4303 | maxnum <<= 16; | |
4304 | maxnum |= 0xffff; | |
4305 | } | |
4306 | if (imm_expr.X_op == O_constant | |
4307 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4308 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4309 | { |
4310 | do_false: | |
4311 | /* result is always false */ | |
4312 | if (! likely) | |
67c0d1eb | 4313 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4314 | else |
67c0d1eb | 4315 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4316 | return; |
4317 | } | |
4318 | if (imm_expr.X_op != O_constant) | |
4319 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4320 | ++imm_expr.X_add_number; |
252b5132 RH |
4321 | /* FALLTHROUGH */ |
4322 | case M_BGE_I: | |
4323 | case M_BGEL_I: | |
4324 | if (mask == M_BGEL_I) | |
4325 | likely = 1; | |
4326 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4327 | { | |
67c0d1eb | 4328 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4329 | return; |
4330 | } | |
4331 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4332 | { | |
67c0d1eb | 4333 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4334 | return; |
4335 | } | |
4336 | maxnum = 0x7fffffff; | |
ca4e0257 | 4337 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4338 | { |
4339 | maxnum <<= 16; | |
4340 | maxnum |= 0xffff; | |
4341 | maxnum <<= 16; | |
4342 | maxnum |= 0xffff; | |
4343 | } | |
4344 | maxnum = - maxnum - 1; | |
4345 | if (imm_expr.X_op == O_constant | |
4346 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4347 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4348 | { |
4349 | do_true: | |
4350 | /* result is always true */ | |
4351 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4352 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4353 | return; |
4354 | } | |
67c0d1eb RS |
4355 | set_at (sreg, 0); |
4356 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4357 | break; |
4358 | ||
4359 | case M_BGEUL: | |
4360 | likely = 1; | |
4361 | case M_BGEU: | |
4362 | if (treg == 0) | |
4363 | goto do_true; | |
4364 | if (sreg == 0) | |
4365 | { | |
67c0d1eb | 4366 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4367 | "s,t,p", 0, treg); |
252b5132 RH |
4368 | return; |
4369 | } | |
67c0d1eb RS |
4370 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4371 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4372 | break; |
4373 | ||
4374 | case M_BGTUL_I: | |
4375 | likely = 1; | |
4376 | case M_BGTU_I: | |
4377 | if (sreg == 0 | |
ca4e0257 | 4378 | || (HAVE_32BIT_GPRS |
252b5132 | 4379 | && imm_expr.X_op == O_constant |
956cd1d6 | 4380 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4381 | goto do_false; |
4382 | if (imm_expr.X_op != O_constant) | |
4383 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4384 | ++imm_expr.X_add_number; |
252b5132 RH |
4385 | /* FALLTHROUGH */ |
4386 | case M_BGEU_I: | |
4387 | case M_BGEUL_I: | |
4388 | if (mask == M_BGEUL_I) | |
4389 | likely = 1; | |
4390 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4391 | goto do_true; | |
4392 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4393 | { | |
67c0d1eb | 4394 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4395 | "s,t,p", sreg, 0); |
252b5132 RH |
4396 | return; |
4397 | } | |
67c0d1eb RS |
4398 | set_at (sreg, 1); |
4399 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4400 | break; |
4401 | ||
4402 | case M_BGTL: | |
4403 | likely = 1; | |
4404 | case M_BGT: | |
4405 | if (treg == 0) | |
4406 | { | |
67c0d1eb | 4407 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4408 | return; |
4409 | } | |
4410 | if (sreg == 0) | |
4411 | { | |
67c0d1eb | 4412 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4413 | return; |
4414 | } | |
67c0d1eb RS |
4415 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4416 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4417 | break; |
4418 | ||
4419 | case M_BGTUL: | |
4420 | likely = 1; | |
4421 | case M_BGTU: | |
4422 | if (treg == 0) | |
4423 | { | |
67c0d1eb | 4424 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4425 | "s,t,p", sreg, 0); |
252b5132 RH |
4426 | return; |
4427 | } | |
4428 | if (sreg == 0) | |
4429 | goto do_false; | |
67c0d1eb RS |
4430 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4431 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4432 | break; |
4433 | ||
4434 | case M_BLEL: | |
4435 | likely = 1; | |
4436 | case M_BLE: | |
4437 | if (treg == 0) | |
4438 | { | |
67c0d1eb | 4439 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4440 | return; |
4441 | } | |
4442 | if (sreg == 0) | |
4443 | { | |
67c0d1eb | 4444 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4445 | return; |
4446 | } | |
67c0d1eb RS |
4447 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4448 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4449 | break; |
4450 | ||
4451 | case M_BLEL_I: | |
4452 | likely = 1; | |
4453 | case M_BLE_I: | |
4454 | maxnum = 0x7fffffff; | |
ca4e0257 | 4455 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4456 | { |
4457 | maxnum <<= 16; | |
4458 | maxnum |= 0xffff; | |
4459 | maxnum <<= 16; | |
4460 | maxnum |= 0xffff; | |
4461 | } | |
4462 | if (imm_expr.X_op == O_constant | |
4463 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4464 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4465 | goto do_true; |
4466 | if (imm_expr.X_op != O_constant) | |
4467 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4468 | ++imm_expr.X_add_number; |
252b5132 RH |
4469 | /* FALLTHROUGH */ |
4470 | case M_BLT_I: | |
4471 | case M_BLTL_I: | |
4472 | if (mask == M_BLTL_I) | |
4473 | likely = 1; | |
4474 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4475 | { | |
67c0d1eb | 4476 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4477 | return; |
4478 | } | |
4479 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4480 | { | |
67c0d1eb | 4481 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4482 | return; |
4483 | } | |
67c0d1eb RS |
4484 | set_at (sreg, 0); |
4485 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4486 | break; |
4487 | ||
4488 | case M_BLEUL: | |
4489 | likely = 1; | |
4490 | case M_BLEU: | |
4491 | if (treg == 0) | |
4492 | { | |
67c0d1eb | 4493 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4494 | "s,t,p", sreg, 0); |
252b5132 RH |
4495 | return; |
4496 | } | |
4497 | if (sreg == 0) | |
4498 | goto do_true; | |
67c0d1eb RS |
4499 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4500 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4501 | break; |
4502 | ||
4503 | case M_BLEUL_I: | |
4504 | likely = 1; | |
4505 | case M_BLEU_I: | |
4506 | if (sreg == 0 | |
ca4e0257 | 4507 | || (HAVE_32BIT_GPRS |
252b5132 | 4508 | && imm_expr.X_op == O_constant |
956cd1d6 | 4509 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4510 | goto do_true; |
4511 | if (imm_expr.X_op != O_constant) | |
4512 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4513 | ++imm_expr.X_add_number; |
252b5132 RH |
4514 | /* FALLTHROUGH */ |
4515 | case M_BLTU_I: | |
4516 | case M_BLTUL_I: | |
4517 | if (mask == M_BLTUL_I) | |
4518 | likely = 1; | |
4519 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4520 | goto do_false; | |
4521 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4522 | { | |
67c0d1eb | 4523 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4524 | "s,t,p", sreg, 0); |
4525 | return; | |
4526 | } | |
67c0d1eb RS |
4527 | set_at (sreg, 1); |
4528 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4529 | break; |
4530 | ||
4531 | case M_BLTL: | |
4532 | likely = 1; | |
4533 | case M_BLT: | |
4534 | if (treg == 0) | |
4535 | { | |
67c0d1eb | 4536 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4537 | return; |
4538 | } | |
4539 | if (sreg == 0) | |
4540 | { | |
67c0d1eb | 4541 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4542 | return; |
4543 | } | |
67c0d1eb RS |
4544 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4545 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4546 | break; |
4547 | ||
4548 | case M_BLTUL: | |
4549 | likely = 1; | |
4550 | case M_BLTU: | |
4551 | if (treg == 0) | |
4552 | goto do_false; | |
4553 | if (sreg == 0) | |
4554 | { | |
67c0d1eb | 4555 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4556 | "s,t,p", 0, treg); |
252b5132 RH |
4557 | return; |
4558 | } | |
67c0d1eb RS |
4559 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4560 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4561 | break; |
4562 | ||
5f74bc13 CD |
4563 | case M_DEXT: |
4564 | { | |
4565 | unsigned long pos; | |
4566 | unsigned long size; | |
4567 | ||
4568 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4569 | { | |
4570 | as_bad (_("Unsupported large constant")); | |
4571 | pos = size = 1; | |
4572 | } | |
4573 | else | |
4574 | { | |
4575 | pos = (unsigned long) imm_expr.X_add_number; | |
4576 | size = (unsigned long) imm2_expr.X_add_number; | |
4577 | } | |
4578 | ||
4579 | if (pos > 63) | |
4580 | { | |
4581 | as_bad (_("Improper position (%lu)"), pos); | |
4582 | pos = 1; | |
4583 | } | |
4584 | if (size == 0 || size > 64 | |
4585 | || (pos + size - 1) > 63) | |
4586 | { | |
4587 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4588 | size, pos); | |
4589 | size = 1; | |
4590 | } | |
4591 | ||
4592 | if (size <= 32 && pos < 32) | |
4593 | { | |
4594 | s = "dext"; | |
4595 | fmt = "t,r,+A,+C"; | |
4596 | } | |
4597 | else if (size <= 32) | |
4598 | { | |
4599 | s = "dextu"; | |
4600 | fmt = "t,r,+E,+H"; | |
4601 | } | |
4602 | else | |
4603 | { | |
4604 | s = "dextm"; | |
4605 | fmt = "t,r,+A,+G"; | |
4606 | } | |
67c0d1eb | 4607 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4608 | } |
4609 | return; | |
4610 | ||
4611 | case M_DINS: | |
4612 | { | |
4613 | unsigned long pos; | |
4614 | unsigned long size; | |
4615 | ||
4616 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4617 | { | |
4618 | as_bad (_("Unsupported large constant")); | |
4619 | pos = size = 1; | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | pos = (unsigned long) imm_expr.X_add_number; | |
4624 | size = (unsigned long) imm2_expr.X_add_number; | |
4625 | } | |
4626 | ||
4627 | if (pos > 63) | |
4628 | { | |
4629 | as_bad (_("Improper position (%lu)"), pos); | |
4630 | pos = 1; | |
4631 | } | |
4632 | if (size == 0 || size > 64 | |
4633 | || (pos + size - 1) > 63) | |
4634 | { | |
4635 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4636 | size, pos); | |
4637 | size = 1; | |
4638 | } | |
4639 | ||
4640 | if (pos < 32 && (pos + size - 1) < 32) | |
4641 | { | |
4642 | s = "dins"; | |
4643 | fmt = "t,r,+A,+B"; | |
4644 | } | |
4645 | else if (pos >= 32) | |
4646 | { | |
4647 | s = "dinsu"; | |
4648 | fmt = "t,r,+E,+F"; | |
4649 | } | |
4650 | else | |
4651 | { | |
4652 | s = "dinsm"; | |
4653 | fmt = "t,r,+A,+F"; | |
4654 | } | |
67c0d1eb RS |
4655 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4656 | pos + size - 1); | |
5f74bc13 CD |
4657 | } |
4658 | return; | |
4659 | ||
252b5132 RH |
4660 | case M_DDIV_3: |
4661 | dbl = 1; | |
4662 | case M_DIV_3: | |
4663 | s = "mflo"; | |
4664 | goto do_div3; | |
4665 | case M_DREM_3: | |
4666 | dbl = 1; | |
4667 | case M_REM_3: | |
4668 | s = "mfhi"; | |
4669 | do_div3: | |
4670 | if (treg == 0) | |
4671 | { | |
4672 | as_warn (_("Divide by zero.")); | |
4673 | if (mips_trap) | |
67c0d1eb | 4674 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4675 | else |
67c0d1eb | 4676 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4677 | return; |
4678 | } | |
4679 | ||
b34976b6 | 4680 | mips_emit_delays (TRUE); |
252b5132 RH |
4681 | ++mips_opts.noreorder; |
4682 | mips_any_noreorder = 1; | |
4683 | if (mips_trap) | |
4684 | { | |
67c0d1eb RS |
4685 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4686 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4687 | } |
4688 | else | |
4689 | { | |
4690 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4691 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4692 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4693 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4694 | } |
4695 | expr1.X_add_number = -1; | |
f6a22291 | 4696 | load_register (AT, &expr1, dbl); |
252b5132 | 4697 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4698 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4699 | if (dbl) |
4700 | { | |
4701 | expr1.X_add_number = 1; | |
f6a22291 | 4702 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4703 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4704 | } |
4705 | else | |
4706 | { | |
4707 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4708 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4709 | } |
4710 | if (mips_trap) | |
4711 | { | |
67c0d1eb | 4712 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4713 | /* We want to close the noreorder block as soon as possible, so |
4714 | that later insns are available for delay slot filling. */ | |
4715 | --mips_opts.noreorder; | |
4716 | } | |
4717 | else | |
4718 | { | |
4719 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4720 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4721 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4722 | |
4723 | /* We want to close the noreorder block as soon as possible, so | |
4724 | that later insns are available for delay slot filling. */ | |
4725 | --mips_opts.noreorder; | |
4726 | ||
67c0d1eb | 4727 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4728 | } |
67c0d1eb | 4729 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4730 | break; |
4731 | ||
4732 | case M_DIV_3I: | |
4733 | s = "div"; | |
4734 | s2 = "mflo"; | |
4735 | goto do_divi; | |
4736 | case M_DIVU_3I: | |
4737 | s = "divu"; | |
4738 | s2 = "mflo"; | |
4739 | goto do_divi; | |
4740 | case M_REM_3I: | |
4741 | s = "div"; | |
4742 | s2 = "mfhi"; | |
4743 | goto do_divi; | |
4744 | case M_REMU_3I: | |
4745 | s = "divu"; | |
4746 | s2 = "mfhi"; | |
4747 | goto do_divi; | |
4748 | case M_DDIV_3I: | |
4749 | dbl = 1; | |
4750 | s = "ddiv"; | |
4751 | s2 = "mflo"; | |
4752 | goto do_divi; | |
4753 | case M_DDIVU_3I: | |
4754 | dbl = 1; | |
4755 | s = "ddivu"; | |
4756 | s2 = "mflo"; | |
4757 | goto do_divi; | |
4758 | case M_DREM_3I: | |
4759 | dbl = 1; | |
4760 | s = "ddiv"; | |
4761 | s2 = "mfhi"; | |
4762 | goto do_divi; | |
4763 | case M_DREMU_3I: | |
4764 | dbl = 1; | |
4765 | s = "ddivu"; | |
4766 | s2 = "mfhi"; | |
4767 | do_divi: | |
4768 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4769 | { | |
4770 | as_warn (_("Divide by zero.")); | |
4771 | if (mips_trap) | |
67c0d1eb | 4772 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4773 | else |
67c0d1eb | 4774 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4775 | return; |
4776 | } | |
4777 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4778 | { | |
4779 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4780 | move_register (dreg, sreg); |
252b5132 | 4781 | else |
67c0d1eb | 4782 | move_register (dreg, 0); |
252b5132 RH |
4783 | return; |
4784 | } | |
4785 | if (imm_expr.X_op == O_constant | |
4786 | && imm_expr.X_add_number == -1 | |
4787 | && s[strlen (s) - 1] != 'u') | |
4788 | { | |
4789 | if (strcmp (s2, "mflo") == 0) | |
4790 | { | |
67c0d1eb | 4791 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4792 | } |
4793 | else | |
67c0d1eb | 4794 | move_register (dreg, 0); |
252b5132 RH |
4795 | return; |
4796 | } | |
4797 | ||
67c0d1eb RS |
4798 | load_register (AT, &imm_expr, dbl); |
4799 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4800 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4801 | break; |
4802 | ||
4803 | case M_DIVU_3: | |
4804 | s = "divu"; | |
4805 | s2 = "mflo"; | |
4806 | goto do_divu3; | |
4807 | case M_REMU_3: | |
4808 | s = "divu"; | |
4809 | s2 = "mfhi"; | |
4810 | goto do_divu3; | |
4811 | case M_DDIVU_3: | |
4812 | s = "ddivu"; | |
4813 | s2 = "mflo"; | |
4814 | goto do_divu3; | |
4815 | case M_DREMU_3: | |
4816 | s = "ddivu"; | |
4817 | s2 = "mfhi"; | |
4818 | do_divu3: | |
b34976b6 | 4819 | mips_emit_delays (TRUE); |
252b5132 RH |
4820 | ++mips_opts.noreorder; |
4821 | mips_any_noreorder = 1; | |
4822 | if (mips_trap) | |
4823 | { | |
67c0d1eb RS |
4824 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4825 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4826 | /* We want to close the noreorder block as soon as possible, so |
4827 | that later insns are available for delay slot filling. */ | |
4828 | --mips_opts.noreorder; | |
4829 | } | |
4830 | else | |
4831 | { | |
4832 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4833 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4834 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4835 | |
4836 | /* We want to close the noreorder block as soon as possible, so | |
4837 | that later insns are available for delay slot filling. */ | |
4838 | --mips_opts.noreorder; | |
67c0d1eb | 4839 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4840 | } |
67c0d1eb | 4841 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4842 | return; |
4843 | ||
1abe91b1 MR |
4844 | case M_DLCA_AB: |
4845 | dbl = 1; | |
4846 | case M_LCA_AB: | |
4847 | call = 1; | |
4848 | goto do_la; | |
252b5132 RH |
4849 | case M_DLA_AB: |
4850 | dbl = 1; | |
4851 | case M_LA_AB: | |
1abe91b1 | 4852 | do_la: |
252b5132 RH |
4853 | /* Load the address of a symbol into a register. If breg is not |
4854 | zero, we then add a base register to it. */ | |
4855 | ||
3bec30a8 TS |
4856 | if (dbl && HAVE_32BIT_GPRS) |
4857 | as_warn (_("dla used to load 32-bit register")); | |
4858 | ||
c90bbe5b | 4859 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4860 | as_warn (_("la used to load 64-bit address")); |
4861 | ||
0c11417f MR |
4862 | if (offset_expr.X_op == O_constant |
4863 | && offset_expr.X_add_number >= -0x8000 | |
4864 | && offset_expr.X_add_number < 0x8000) | |
4865 | { | |
67c0d1eb | 4866 | macro_build (&offset_expr, |
b7c7d6c1 | 4867 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4868 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4869 | return; |
4870 | } | |
4871 | ||
afdbd6d0 CD |
4872 | if (treg == breg) |
4873 | { | |
4874 | tempreg = AT; | |
4875 | used_at = 1; | |
4876 | } | |
4877 | else | |
4878 | { | |
4879 | tempreg = treg; | |
4880 | used_at = 0; | |
4881 | } | |
4882 | ||
252b5132 RH |
4883 | if (offset_expr.X_op != O_symbol |
4884 | && offset_expr.X_op != O_constant) | |
4885 | { | |
4886 | as_bad (_("expression too complex")); | |
4887 | offset_expr.X_op = O_constant; | |
4888 | } | |
4889 | ||
252b5132 | 4890 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4891 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4892 | (mips_pic == NO_PIC |
4d34fb5f TS |
4893 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4894 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4895 | else if (mips_pic == NO_PIC) |
4896 | { | |
d6bc6245 | 4897 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4898 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4899 | Otherwise we want |
4900 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4901 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4902 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4903 | so we may as well always use the latter form. |
76b3015f | 4904 | |
d6bc6245 TS |
4905 | With 64bit address space and a usable $at we want |
4906 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4907 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4908 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4909 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4910 | dsll32 $tempreg,0 | |
3a482fd5 | 4911 | daddu $tempreg,$tempreg,$at |
76b3015f | 4912 | |
c03099e6 | 4913 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4914 | on superscalar processors. |
4915 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4916 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4917 | dsll $tempreg,16 | |
4918 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4919 | dsll $tempreg,16 | |
4920 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4921 | */ | |
d6bc6245 | 4922 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4923 | { |
e864ceca RS |
4924 | /* ??? We don't provide a GP-relative alternative for |
4925 | these macros. It used not to be possible with the | |
4926 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4927 | |
460597ba | 4928 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f | 4929 | { |
67c0d1eb | 4930 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4931 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4932 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4933 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4934 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4935 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4936 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4937 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4938 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4939 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4940 | used_at = 1; |
4941 | } | |
4942 | else | |
4943 | { | |
67c0d1eb | 4944 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4945 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4946 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4947 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4948 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4949 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4950 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4951 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4952 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4953 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4954 | } |
4955 | } | |
4956 | else | |
4957 | { | |
4958 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4959 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4960 | { | |
4d7206a2 | 4961 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4962 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4963 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4964 | relax_switch (); |
98d3f06f | 4965 | } |
67c0d1eb RS |
4966 | macro_build_lui (&offset_expr, tempreg); |
4967 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4968 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4969 | if (mips_relax.sequence) |
4970 | relax_end (); | |
98d3f06f | 4971 | } |
252b5132 | 4972 | } |
f5040a92 | 4973 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4974 | { |
9117d219 NC |
4975 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4976 | ||
252b5132 RH |
4977 | /* If this is a reference to an external symbol, and there |
4978 | is no constant, we want | |
4979 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4980 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4981 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4982 | For a local symbol, we want |
4983 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4984 | nop | |
4985 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4986 | ||
4987 | If we have a small constant, and this is a reference to | |
4988 | an external symbol, we want | |
4989 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4990 | nop | |
4991 | addiu $tempreg,$tempreg,<constant> | |
4992 | For a local symbol, we want the same instruction | |
4993 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4994 | addiu instruction. | |
4995 | ||
4996 | If we have a large constant, and this is a reference to | |
4997 | an external symbol, we want | |
4998 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4999 | lui $at,<hiconstant> | |
5000 | addiu $at,$at,<loconstant> | |
5001 | addu $tempreg,$tempreg,$at | |
5002 | For a local symbol, we want the same instruction | |
5003 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5004 | addiu instruction. |
ed6fb7bd SC |
5005 | */ |
5006 | ||
4d7206a2 | 5007 | if (offset_expr.X_add_number == 0) |
252b5132 | 5008 | { |
4d7206a2 RS |
5009 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5010 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5011 | ||
5012 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5013 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5014 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5015 | if (breg != 0) |
252b5132 RH |
5016 | { |
5017 | /* We're going to put in an addu instruction using | |
5018 | tempreg, so we may as well insert the nop right | |
5019 | now. */ | |
269137b2 | 5020 | load_delay_nop (); |
252b5132 | 5021 | } |
4d7206a2 | 5022 | relax_switch (); |
67c0d1eb RS |
5023 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5024 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5025 | load_delay_nop (); |
67c0d1eb RS |
5026 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5027 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5028 | relax_end (); |
252b5132 RH |
5029 | /* FIXME: If breg == 0, and the next instruction uses |
5030 | $tempreg, then if this variant case is used an extra | |
5031 | nop will be generated. */ | |
5032 | } | |
4d7206a2 RS |
5033 | else if (offset_expr.X_add_number >= -0x8000 |
5034 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5035 | { |
67c0d1eb | 5036 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5037 | load_delay_nop (); |
67c0d1eb | 5038 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5039 | } |
5040 | else | |
5041 | { | |
4d7206a2 RS |
5042 | expr1.X_add_number = offset_expr.X_add_number; |
5043 | offset_expr.X_add_number = | |
5044 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5045 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5046 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5047 | /* If we are going to add in a base register, and the |
5048 | target register and the base register are the same, | |
5049 | then we are using AT as a temporary register. Since | |
5050 | we want to load the constant into AT, we add our | |
5051 | current AT (from the global offset table) and the | |
5052 | register into the register now, and pretend we were | |
5053 | not using a base register. */ | |
67c0d1eb | 5054 | if (breg == treg) |
252b5132 | 5055 | { |
269137b2 | 5056 | load_delay_nop (); |
67c0d1eb | 5057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5058 | treg, AT, breg); |
252b5132 RH |
5059 | breg = 0; |
5060 | tempreg = treg; | |
252b5132 | 5061 | } |
f6a22291 | 5062 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5063 | used_at = 1; |
5064 | } | |
5065 | } | |
f5040a92 AO |
5066 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5067 | { | |
67c0d1eb | 5068 | int add_breg_early = 0; |
f5040a92 AO |
5069 | |
5070 | /* If this is a reference to an external, and there is no | |
5071 | constant, or local symbol (*), with or without a | |
5072 | constant, we want | |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5074 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5076 | ||
5077 | If we have a small constant, and this is a reference to | |
5078 | an external symbol, we want | |
5079 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5080 | addiu $tempreg,$tempreg,<constant> | |
5081 | ||
5082 | If we have a large constant, and this is a reference to | |
5083 | an external symbol, we want | |
5084 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5085 | lui $at,<hiconstant> | |
5086 | addiu $at,$at,<loconstant> | |
5087 | addu $tempreg,$tempreg,$at | |
5088 | ||
5089 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5090 | local symbols, even though it introduces an additional | |
5091 | instruction. */ | |
5092 | ||
f5040a92 AO |
5093 | if (offset_expr.X_add_number) |
5094 | { | |
4d7206a2 | 5095 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5096 | offset_expr.X_add_number = 0; |
5097 | ||
4d7206a2 | 5098 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5099 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5100 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5101 | |
5102 | if (expr1.X_add_number >= -0x8000 | |
5103 | && expr1.X_add_number < 0x8000) | |
5104 | { | |
67c0d1eb RS |
5105 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5106 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5107 | } |
ecd13cd3 | 5108 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5109 | { |
5110 | int dreg; | |
5111 | ||
5112 | /* If we are going to add in a base register, and the | |
5113 | target register and the base register are the same, | |
5114 | then we are using AT as a temporary register. Since | |
5115 | we want to load the constant into AT, we add our | |
5116 | current AT (from the global offset table) and the | |
5117 | register into the register now, and pretend we were | |
5118 | not using a base register. */ | |
5119 | if (breg != treg) | |
5120 | dreg = tempreg; | |
5121 | else | |
5122 | { | |
5123 | assert (tempreg == AT); | |
67c0d1eb RS |
5124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5125 | treg, AT, breg); | |
f5040a92 | 5126 | dreg = treg; |
67c0d1eb | 5127 | add_breg_early = 1; |
f5040a92 AO |
5128 | } |
5129 | ||
f6a22291 | 5130 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5131 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5132 | dreg, dreg, AT); |
f5040a92 | 5133 | |
f5040a92 AO |
5134 | used_at = 1; |
5135 | } | |
5136 | else | |
5137 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5138 | ||
4d7206a2 | 5139 | relax_switch (); |
f5040a92 AO |
5140 | offset_expr.X_add_number = expr1.X_add_number; |
5141 | ||
67c0d1eb RS |
5142 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5143 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5144 | if (add_breg_early) | |
f5040a92 | 5145 | { |
67c0d1eb | 5146 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5147 | treg, tempreg, breg); |
f5040a92 AO |
5148 | breg = 0; |
5149 | tempreg = treg; | |
5150 | } | |
4d7206a2 | 5151 | relax_end (); |
f5040a92 | 5152 | } |
4d7206a2 | 5153 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5154 | { |
4d7206a2 | 5155 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5156 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5157 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5158 | relax_switch (); |
67c0d1eb RS |
5159 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5160 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5161 | relax_end (); |
f5040a92 | 5162 | } |
4d7206a2 | 5163 | else |
f5040a92 | 5164 | { |
67c0d1eb RS |
5165 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5166 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5167 | } |
5168 | } | |
5169 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5170 | { |
67c0d1eb | 5171 | int gpdelay; |
9117d219 NC |
5172 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5173 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5174 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5175 | |
5176 | /* This is the large GOT case. If this is a reference to an | |
5177 | external symbol, and there is no constant, we want | |
5178 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5179 | addu $tempreg,$tempreg,$gp | |
5180 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5181 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5182 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5183 | addu $tempreg,$tempreg,$gp | |
5184 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5185 | For a local symbol, we want |
5186 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5187 | nop | |
5188 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5189 | ||
5190 | If we have a small constant, and this is a reference to | |
5191 | an external symbol, we want | |
5192 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5193 | addu $tempreg,$tempreg,$gp | |
5194 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5195 | nop | |
5196 | addiu $tempreg,$tempreg,<constant> | |
5197 | For a local symbol, we want | |
5198 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5199 | nop | |
5200 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5201 | ||
5202 | If we have a large constant, and this is a reference to | |
5203 | an external symbol, we want | |
5204 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5205 | addu $tempreg,$tempreg,$gp | |
5206 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5207 | lui $at,<hiconstant> | |
5208 | addiu $at,$at,<loconstant> | |
5209 | addu $tempreg,$tempreg,$at | |
5210 | For a local symbol, we want | |
5211 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5212 | lui $at,<hiconstant> | |
5213 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5214 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5215 | */ |
438c16b8 | 5216 | |
252b5132 RH |
5217 | expr1.X_add_number = offset_expr.X_add_number; |
5218 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5219 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5220 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5221 | if (expr1.X_add_number == 0 && breg == 0 |
5222 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5223 | { |
5224 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5225 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5226 | } | |
67c0d1eb RS |
5227 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5228 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5229 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5230 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5231 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5232 | if (expr1.X_add_number == 0) |
5233 | { | |
67c0d1eb | 5234 | if (breg != 0) |
252b5132 RH |
5235 | { |
5236 | /* We're going to put in an addu instruction using | |
5237 | tempreg, so we may as well insert the nop right | |
5238 | now. */ | |
269137b2 | 5239 | load_delay_nop (); |
252b5132 | 5240 | } |
252b5132 RH |
5241 | } |
5242 | else if (expr1.X_add_number >= -0x8000 | |
5243 | && expr1.X_add_number < 0x8000) | |
5244 | { | |
269137b2 | 5245 | load_delay_nop (); |
67c0d1eb | 5246 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5247 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5248 | } |
5249 | else | |
5250 | { | |
67c0d1eb | 5251 | int dreg; |
252b5132 RH |
5252 | |
5253 | /* If we are going to add in a base register, and the | |
5254 | target register and the base register are the same, | |
5255 | then we are using AT as a temporary register. Since | |
5256 | we want to load the constant into AT, we add our | |
5257 | current AT (from the global offset table) and the | |
5258 | register into the register now, and pretend we were | |
5259 | not using a base register. */ | |
5260 | if (breg != treg) | |
67c0d1eb | 5261 | dreg = tempreg; |
252b5132 RH |
5262 | else |
5263 | { | |
5264 | assert (tempreg == AT); | |
269137b2 | 5265 | load_delay_nop (); |
67c0d1eb | 5266 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5267 | treg, AT, breg); |
252b5132 | 5268 | dreg = treg; |
252b5132 RH |
5269 | } |
5270 | ||
f6a22291 | 5271 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5272 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5273 | |
252b5132 RH |
5274 | used_at = 1; |
5275 | } | |
4d7206a2 RS |
5276 | offset_expr.X_add_number = |
5277 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5278 | relax_switch (); | |
252b5132 | 5279 | |
67c0d1eb | 5280 | if (gpdelay) |
252b5132 RH |
5281 | { |
5282 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5283 | the first instruction on the main stream does not. */ |
67c0d1eb | 5284 | macro_build (NULL, "nop", ""); |
252b5132 | 5285 | } |
ed6fb7bd | 5286 | |
67c0d1eb RS |
5287 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5288 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5289 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5290 | && expr1.X_add_number < 0x8000) |
5291 | { | |
269137b2 | 5292 | load_delay_nop (); |
67c0d1eb RS |
5293 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5294 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5295 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5296 | register, the external symbol case ended with a load, |
5297 | so if the symbol turns out to not be external, and | |
5298 | the next instruction uses tempreg, an unnecessary nop | |
5299 | will be inserted. */ | |
252b5132 RH |
5300 | } |
5301 | else | |
5302 | { | |
5303 | if (breg == treg) | |
5304 | { | |
5305 | /* We must add in the base register now, as in the | |
f5040a92 | 5306 | external symbol case. */ |
252b5132 | 5307 | assert (tempreg == AT); |
269137b2 | 5308 | load_delay_nop (); |
67c0d1eb | 5309 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5310 | treg, AT, breg); |
252b5132 RH |
5311 | tempreg = treg; |
5312 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5313 | it in in both cases. */ |
252b5132 RH |
5314 | breg = 0; |
5315 | } | |
5316 | ||
67c0d1eb RS |
5317 | macro_build_lui (&expr1, AT); |
5318 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5319 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5320 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5321 | tempreg, tempreg, AT); |
252b5132 | 5322 | } |
4d7206a2 | 5323 | relax_end (); |
252b5132 | 5324 | } |
f5040a92 AO |
5325 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5326 | { | |
f5040a92 AO |
5327 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5328 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5329 | int add_breg_early = 0; |
f5040a92 AO |
5330 | |
5331 | /* This is the large GOT case. If this is a reference to an | |
5332 | external symbol, and there is no constant, we want | |
5333 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5334 | add $tempreg,$tempreg,$gp | |
5335 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5336 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5337 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5338 | add $tempreg,$tempreg,$gp | |
5339 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5340 | ||
5341 | If we have a small constant, and this is a reference to | |
5342 | an external symbol, we want | |
5343 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5344 | add $tempreg,$tempreg,$gp | |
5345 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5346 | addi $tempreg,$tempreg,<constant> | |
5347 | ||
5348 | If we have a large constant, and this is a reference to | |
5349 | an external symbol, we want | |
5350 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5351 | addu $tempreg,$tempreg,$gp | |
5352 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5353 | lui $at,<hiconstant> | |
5354 | addi $at,$at,<loconstant> | |
5355 | add $tempreg,$tempreg,$at | |
5356 | ||
5357 | If we have NewABI, and we know it's a local symbol, we want | |
5358 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5359 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5360 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5361 | ||
4d7206a2 | 5362 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5363 | |
4d7206a2 | 5364 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5365 | offset_expr.X_add_number = 0; |
5366 | ||
1abe91b1 MR |
5367 | if (expr1.X_add_number == 0 && breg == 0 |
5368 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5369 | { |
5370 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5371 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5372 | } | |
67c0d1eb RS |
5373 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5374 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5375 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5376 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5377 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5378 | |
5379 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5380 | ; |
f5040a92 AO |
5381 | else if (expr1.X_add_number >= -0x8000 |
5382 | && expr1.X_add_number < 0x8000) | |
5383 | { | |
67c0d1eb | 5384 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5385 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5386 | } |
ecd13cd3 | 5387 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5388 | { |
5389 | int dreg; | |
5390 | ||
5391 | /* If we are going to add in a base register, and the | |
5392 | target register and the base register are the same, | |
5393 | then we are using AT as a temporary register. Since | |
5394 | we want to load the constant into AT, we add our | |
5395 | current AT (from the global offset table) and the | |
5396 | register into the register now, and pretend we were | |
5397 | not using a base register. */ | |
5398 | if (breg != treg) | |
5399 | dreg = tempreg; | |
5400 | else | |
5401 | { | |
5402 | assert (tempreg == AT); | |
67c0d1eb | 5403 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5404 | treg, AT, breg); |
f5040a92 | 5405 | dreg = treg; |
67c0d1eb | 5406 | add_breg_early = 1; |
f5040a92 AO |
5407 | } |
5408 | ||
f6a22291 | 5409 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5410 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5411 | |
f5040a92 AO |
5412 | used_at = 1; |
5413 | } | |
5414 | else | |
5415 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5416 | ||
4d7206a2 | 5417 | relax_switch (); |
f5040a92 | 5418 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5419 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5420 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5421 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5422 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5423 | if (add_breg_early) | |
f5040a92 | 5424 | { |
67c0d1eb | 5425 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5426 | treg, tempreg, breg); |
f5040a92 AO |
5427 | breg = 0; |
5428 | tempreg = treg; | |
5429 | } | |
4d7206a2 | 5430 | relax_end (); |
f5040a92 | 5431 | } |
252b5132 RH |
5432 | else |
5433 | abort (); | |
5434 | ||
5435 | if (breg != 0) | |
4d34fb5f TS |
5436 | { |
5437 | char *s; | |
5438 | ||
3e722fb5 | 5439 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5440 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5441 | else |
f899b4b8 | 5442 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5443 | |
67c0d1eb | 5444 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5445 | } |
252b5132 RH |
5446 | |
5447 | if (! used_at) | |
5448 | return; | |
5449 | ||
5450 | break; | |
5451 | ||
5452 | case M_J_A: | |
5453 | /* The j instruction may not be used in PIC code, since it | |
5454 | requires an absolute address. We convert it to a b | |
5455 | instruction. */ | |
5456 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5457 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5458 | else |
67c0d1eb | 5459 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5460 | return; |
5461 | ||
5462 | /* The jal instructions must be handled as macros because when | |
5463 | generating PIC code they expand to multi-instruction | |
5464 | sequences. Normally they are simple instructions. */ | |
5465 | case M_JAL_1: | |
5466 | dreg = RA; | |
5467 | /* Fall through. */ | |
5468 | case M_JAL_2: | |
3e722fb5 | 5469 | if (mips_pic == NO_PIC) |
67c0d1eb | 5470 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5471 | else if (mips_pic == SVR4_PIC) |
5472 | { | |
5473 | if (sreg != PIC_CALL_REG) | |
5474 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5475 | |
67c0d1eb | 5476 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5477 | if (! HAVE_NEWABI) |
252b5132 | 5478 | { |
6478892d TS |
5479 | if (mips_cprestore_offset < 0) |
5480 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5481 | else | |
5482 | { | |
7a621144 DJ |
5483 | if (! mips_frame_reg_valid) |
5484 | { | |
5485 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5486 | /* Quiet this warning. */ | |
5487 | mips_frame_reg_valid = 1; | |
5488 | } | |
5489 | if (! mips_cprestore_valid) | |
5490 | { | |
5491 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5492 | /* Quiet this warning. */ | |
5493 | mips_cprestore_valid = 1; | |
5494 | } | |
6478892d | 5495 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5496 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5497 | mips_gp_register, |
256ab948 TS |
5498 | mips_frame_reg, |
5499 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5500 | } |
252b5132 RH |
5501 | } |
5502 | } | |
5503 | else | |
5504 | abort (); | |
5505 | ||
5506 | return; | |
5507 | ||
5508 | case M_JAL_A: | |
5509 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5510 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5511 | else if (mips_pic == SVR4_PIC) |
5512 | { | |
5513 | /* If this is a reference to an external symbol, and we are | |
5514 | using a small GOT, we want | |
5515 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5516 | nop | |
f9419b05 | 5517 | jalr $ra,$25 |
252b5132 RH |
5518 | nop |
5519 | lw $gp,cprestore($sp) | |
5520 | The cprestore value is set using the .cprestore | |
5521 | pseudo-op. If we are using a big GOT, we want | |
5522 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5523 | addu $25,$25,$gp | |
5524 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5525 | nop | |
f9419b05 | 5526 | jalr $ra,$25 |
252b5132 RH |
5527 | nop |
5528 | lw $gp,cprestore($sp) | |
5529 | If the symbol is not external, we want | |
5530 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5531 | nop | |
5532 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5533 | jalr $ra,$25 |
252b5132 | 5534 | nop |
438c16b8 | 5535 | lw $gp,cprestore($sp) |
f5040a92 AO |
5536 | |
5537 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5538 | sequences above, minus nops, unless the symbol is local, | |
5539 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5540 | GOT_DISP. */ | |
438c16b8 | 5541 | if (HAVE_NEWABI) |
252b5132 | 5542 | { |
f5040a92 AO |
5543 | if (! mips_big_got) |
5544 | { | |
4d7206a2 | 5545 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5547 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5548 | mips_gp_register); |
4d7206a2 | 5549 | relax_switch (); |
67c0d1eb RS |
5550 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5551 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5552 | mips_gp_register); |
5553 | relax_end (); | |
f5040a92 AO |
5554 | } |
5555 | else | |
5556 | { | |
4d7206a2 | 5557 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5558 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5559 | BFD_RELOC_MIPS_CALL_HI16); | |
5560 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5561 | PIC_CALL_REG, mips_gp_register); | |
5562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5563 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5564 | PIC_CALL_REG); | |
4d7206a2 | 5565 | relax_switch (); |
67c0d1eb RS |
5566 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5567 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5568 | mips_gp_register); | |
5569 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5570 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5571 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5572 | relax_end (); |
f5040a92 | 5573 | } |
684022ea | 5574 | |
67c0d1eb | 5575 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5576 | } |
5577 | else | |
5578 | { | |
4d7206a2 | 5579 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5580 | if (! mips_big_got) |
5581 | { | |
67c0d1eb RS |
5582 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5583 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5584 | mips_gp_register); |
269137b2 | 5585 | load_delay_nop (); |
4d7206a2 | 5586 | relax_switch (); |
438c16b8 | 5587 | } |
252b5132 | 5588 | else |
252b5132 | 5589 | { |
67c0d1eb RS |
5590 | int gpdelay; |
5591 | ||
5592 | gpdelay = reg_needs_delay (mips_gp_register); | |
5593 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5594 | BFD_RELOC_MIPS_CALL_HI16); | |
5595 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5596 | PIC_CALL_REG, mips_gp_register); | |
5597 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5598 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5599 | PIC_CALL_REG); | |
269137b2 | 5600 | load_delay_nop (); |
4d7206a2 | 5601 | relax_switch (); |
67c0d1eb RS |
5602 | if (gpdelay) |
5603 | macro_build (NULL, "nop", ""); | |
252b5132 | 5604 | } |
67c0d1eb RS |
5605 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5606 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5607 | mips_gp_register); |
269137b2 | 5608 | load_delay_nop (); |
67c0d1eb RS |
5609 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5610 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5611 | relax_end (); |
67c0d1eb | 5612 | macro_build_jalr (&offset_expr); |
438c16b8 | 5613 | |
6478892d TS |
5614 | if (mips_cprestore_offset < 0) |
5615 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5616 | else | |
5617 | { | |
7a621144 DJ |
5618 | if (! mips_frame_reg_valid) |
5619 | { | |
5620 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5621 | /* Quiet this warning. */ | |
5622 | mips_frame_reg_valid = 1; | |
5623 | } | |
5624 | if (! mips_cprestore_valid) | |
5625 | { | |
5626 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5627 | /* Quiet this warning. */ | |
5628 | mips_cprestore_valid = 1; | |
5629 | } | |
6478892d | 5630 | if (mips_opts.noreorder) |
67c0d1eb | 5631 | macro_build (NULL, "nop", ""); |
6478892d | 5632 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5633 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5634 | mips_gp_register, |
256ab948 TS |
5635 | mips_frame_reg, |
5636 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5637 | } |
252b5132 RH |
5638 | } |
5639 | } | |
252b5132 RH |
5640 | else |
5641 | abort (); | |
5642 | ||
5643 | return; | |
5644 | ||
5645 | case M_LB_AB: | |
5646 | s = "lb"; | |
5647 | goto ld; | |
5648 | case M_LBU_AB: | |
5649 | s = "lbu"; | |
5650 | goto ld; | |
5651 | case M_LH_AB: | |
5652 | s = "lh"; | |
5653 | goto ld; | |
5654 | case M_LHU_AB: | |
5655 | s = "lhu"; | |
5656 | goto ld; | |
5657 | case M_LW_AB: | |
5658 | s = "lw"; | |
5659 | goto ld; | |
5660 | case M_LWC0_AB: | |
5661 | s = "lwc0"; | |
bdaaa2e1 | 5662 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5663 | coproc = 1; |
5664 | goto ld; | |
5665 | case M_LWC1_AB: | |
5666 | s = "lwc1"; | |
bdaaa2e1 | 5667 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5668 | coproc = 1; |
5669 | goto ld; | |
5670 | case M_LWC2_AB: | |
5671 | s = "lwc2"; | |
bdaaa2e1 | 5672 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5673 | coproc = 1; |
5674 | goto ld; | |
5675 | case M_LWC3_AB: | |
5676 | s = "lwc3"; | |
bdaaa2e1 | 5677 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5678 | coproc = 1; |
5679 | goto ld; | |
5680 | case M_LWL_AB: | |
5681 | s = "lwl"; | |
5682 | lr = 1; | |
5683 | goto ld; | |
5684 | case M_LWR_AB: | |
5685 | s = "lwr"; | |
5686 | lr = 1; | |
5687 | goto ld; | |
5688 | case M_LDC1_AB: | |
fef14a42 | 5689 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5690 | { |
5691 | as_bad (_("opcode not supported on this processor")); | |
5692 | return; | |
5693 | } | |
5694 | s = "ldc1"; | |
bdaaa2e1 | 5695 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5696 | coproc = 1; |
5697 | goto ld; | |
5698 | case M_LDC2_AB: | |
5699 | s = "ldc2"; | |
bdaaa2e1 | 5700 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5701 | coproc = 1; |
5702 | goto ld; | |
5703 | case M_LDC3_AB: | |
5704 | s = "ldc3"; | |
bdaaa2e1 | 5705 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5706 | coproc = 1; |
5707 | goto ld; | |
5708 | case M_LDL_AB: | |
5709 | s = "ldl"; | |
5710 | lr = 1; | |
5711 | goto ld; | |
5712 | case M_LDR_AB: | |
5713 | s = "ldr"; | |
5714 | lr = 1; | |
5715 | goto ld; | |
5716 | case M_LL_AB: | |
5717 | s = "ll"; | |
5718 | goto ld; | |
5719 | case M_LLD_AB: | |
5720 | s = "lld"; | |
5721 | goto ld; | |
5722 | case M_LWU_AB: | |
5723 | s = "lwu"; | |
5724 | ld: | |
5725 | if (breg == treg || coproc || lr) | |
5726 | { | |
5727 | tempreg = AT; | |
5728 | used_at = 1; | |
5729 | } | |
5730 | else | |
5731 | { | |
5732 | tempreg = treg; | |
5733 | used_at = 0; | |
5734 | } | |
5735 | goto ld_st; | |
5736 | case M_SB_AB: | |
5737 | s = "sb"; | |
5738 | goto st; | |
5739 | case M_SH_AB: | |
5740 | s = "sh"; | |
5741 | goto st; | |
5742 | case M_SW_AB: | |
5743 | s = "sw"; | |
5744 | goto st; | |
5745 | case M_SWC0_AB: | |
5746 | s = "swc0"; | |
bdaaa2e1 | 5747 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5748 | coproc = 1; |
5749 | goto st; | |
5750 | case M_SWC1_AB: | |
5751 | s = "swc1"; | |
bdaaa2e1 | 5752 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5753 | coproc = 1; |
5754 | goto st; | |
5755 | case M_SWC2_AB: | |
5756 | s = "swc2"; | |
bdaaa2e1 | 5757 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5758 | coproc = 1; |
5759 | goto st; | |
5760 | case M_SWC3_AB: | |
5761 | s = "swc3"; | |
bdaaa2e1 | 5762 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5763 | coproc = 1; |
5764 | goto st; | |
5765 | case M_SWL_AB: | |
5766 | s = "swl"; | |
5767 | goto st; | |
5768 | case M_SWR_AB: | |
5769 | s = "swr"; | |
5770 | goto st; | |
5771 | case M_SC_AB: | |
5772 | s = "sc"; | |
5773 | goto st; | |
5774 | case M_SCD_AB: | |
5775 | s = "scd"; | |
5776 | goto st; | |
5777 | case M_SDC1_AB: | |
fef14a42 | 5778 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5779 | { |
5780 | as_bad (_("opcode not supported on this processor")); | |
5781 | return; | |
5782 | } | |
5783 | s = "sdc1"; | |
5784 | coproc = 1; | |
bdaaa2e1 | 5785 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5786 | goto st; |
5787 | case M_SDC2_AB: | |
5788 | s = "sdc2"; | |
bdaaa2e1 | 5789 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5790 | coproc = 1; |
5791 | goto st; | |
5792 | case M_SDC3_AB: | |
5793 | s = "sdc3"; | |
bdaaa2e1 | 5794 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5795 | coproc = 1; |
5796 | goto st; | |
5797 | case M_SDL_AB: | |
5798 | s = "sdl"; | |
5799 | goto st; | |
5800 | case M_SDR_AB: | |
5801 | s = "sdr"; | |
5802 | st: | |
5803 | tempreg = AT; | |
5804 | used_at = 1; | |
5805 | ld_st: | |
bdaaa2e1 | 5806 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5807 | if (mask == M_LWC1_AB |
5808 | || mask == M_SWC1_AB | |
5809 | || mask == M_LDC1_AB | |
5810 | || mask == M_SDC1_AB | |
5811 | || mask == M_L_DAB | |
5812 | || mask == M_S_DAB) | |
5813 | fmt = "T,o(b)"; | |
5814 | else if (coproc) | |
5815 | fmt = "E,o(b)"; | |
5816 | else | |
5817 | fmt = "t,o(b)"; | |
5818 | ||
256ab948 TS |
5819 | /* Sign-extending 32-bit constants makes their handling easier. |
5820 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5821 | described below. */ | |
5822 | if ((! HAVE_64BIT_ADDRESSES | |
5823 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5824 | && (offset_expr.X_op == O_constant) |
5825 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5826 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5827 | { |
d17e7bce | 5828 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5829 | as_bad (_("constant too large")); |
ae826530 | 5830 | |
1b8e29e5 TS |
5831 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5832 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5833 | } |
256ab948 | 5834 | |
252b5132 RH |
5835 | if (offset_expr.X_op != O_constant |
5836 | && offset_expr.X_op != O_symbol) | |
5837 | { | |
5838 | as_bad (_("expression too complex")); | |
5839 | offset_expr.X_op = O_constant; | |
5840 | } | |
5841 | ||
5842 | /* A constant expression in PIC code can be handled just as it | |
5843 | is in non PIC code. */ | |
5844 | if (mips_pic == NO_PIC | |
5845 | || offset_expr.X_op == O_constant) | |
5846 | { | |
5847 | /* If this is a reference to a GP relative symbol, and there | |
5848 | is no base register, we want | |
cdf6fd85 | 5849 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5850 | Otherwise, if there is no base register, we want |
5851 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5852 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5853 | If we have a constant, we need two instructions anyhow, | |
5854 | so we always use the latter form. | |
5855 | ||
5856 | If we have a base register, and this is a reference to a | |
5857 | GP relative symbol, we want | |
5858 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5859 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5860 | Otherwise we want |
5861 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5862 | addu $tempreg,$tempreg,$breg | |
5863 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5864 | With a constant we always use the latter case. |
76b3015f | 5865 | |
d6bc6245 TS |
5866 | With 64bit address space and no base register and $at usable, |
5867 | we want | |
5868 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5869 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5870 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5871 | dsll32 $tempreg,0 | |
5872 | daddu $tempreg,$at | |
5873 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5874 | If we have a base register, we want | |
5875 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5876 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5877 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5878 | daddu $at,$breg | |
5879 | dsll32 $tempreg,0 | |
5880 | daddu $tempreg,$at | |
5881 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5882 | ||
5883 | Without $at we can't generate the optimal path for superscalar | |
5884 | processors here since this would require two temporary registers. | |
5885 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5886 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5887 | dsll $tempreg,16 | |
5888 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5889 | dsll $tempreg,16 | |
5890 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5891 | If we have a base register, we want | |
5892 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5893 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5894 | dsll $tempreg,16 | |
5895 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5896 | dsll $tempreg,16 | |
5897 | daddu $tempreg,$tempreg,$breg | |
5898 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5899 | |
5900 | If we have 64-bit addresses, as an optimization, for | |
5901 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5902 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5903 | mechanism since it is more efficient. Note that due to |
5904 | the signed offset used by memory operations, the 32-bit | |
5905 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5906 | probably attempt to generate 64-bit constants more |
5907 | efficiently in general. | |
9214dd3b AO |
5908 | |
5909 | As an extension for architectures with 64-bit registers, | |
5910 | we don't truncate 64-bit addresses given as literal | |
5911 | constants down to 32 bits, to support existing practice | |
5912 | in the mips64 Linux (the kernel), that compiles source | |
5913 | files with -mabi=64, assembling them as o32 or n32 (with | |
5914 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5915 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5916 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5917 | wasteful to compute the upper 32 bits of every |
5918 | non-literal address, that takes more space and time. | |
5919 | Some day this should probably be implemented as an | |
5920 | assembler option, such that the kernel doesn't have to | |
5921 | use such ugly hacks, even though it will still have to | |
5922 | end up converting the binary to ELF32 for a number of | |
5923 | platforms whose boot loaders don't support ELF64 | |
5924 | binaries. */ | |
256ab948 TS |
5925 | if ((HAVE_64BIT_ADDRESSES |
5926 | && ! (offset_expr.X_op == O_constant | |
5927 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5928 | || (HAVE_64BIT_GPRS | |
5929 | && offset_expr.X_op == O_constant | |
5930 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5931 | { |
e864ceca RS |
5932 | /* ??? We don't provide a GP-relative alternative for |
5933 | these macros. It used not to be possible with the | |
5934 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5935 | |
460597ba | 5936 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 5937 | { |
67c0d1eb RS |
5938 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5939 | BFD_RELOC_MIPS_HIGHEST); | |
5940 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5941 | BFD_RELOC_HI16_S); | |
5942 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5943 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5944 | if (breg != 0) |
67c0d1eb RS |
5945 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5946 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5947 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5948 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5949 | tempreg); | |
d6bc6245 TS |
5950 | used_at = 1; |
5951 | } | |
5952 | else | |
5953 | { | |
67c0d1eb RS |
5954 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5955 | BFD_RELOC_MIPS_HIGHEST); | |
5956 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5957 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5958 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5959 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5960 | tempreg, BFD_RELOC_HI16_S); | |
5961 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5962 | if (breg != 0) |
67c0d1eb | 5963 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5964 | tempreg, tempreg, breg); |
67c0d1eb | 5965 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5966 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
5967 | } |
5968 | ||
5969 | return; | |
5970 | } | |
256ab948 TS |
5971 | |
5972 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 5973 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 5974 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 5975 | |
252b5132 RH |
5976 | if (breg == 0) |
5977 | { | |
67c0d1eb RS |
5978 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5979 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 5980 | { |
4d7206a2 | 5981 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5982 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5983 | mips_gp_register); | |
4d7206a2 | 5984 | relax_switch (); |
252b5132 RH |
5985 | used_at = 0; |
5986 | } | |
67c0d1eb RS |
5987 | macro_build_lui (&offset_expr, tempreg); |
5988 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5989 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5990 | if (mips_relax.sequence) |
5991 | relax_end (); | |
252b5132 RH |
5992 | } |
5993 | else | |
5994 | { | |
67c0d1eb RS |
5995 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5996 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 5997 | { |
4d7206a2 | 5998 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5999 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6000 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6001 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6002 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6003 | relax_switch (); |
252b5132 | 6004 | } |
67c0d1eb RS |
6005 | macro_build_lui (&offset_expr, tempreg); |
6006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6007 | tempreg, tempreg, breg); |
67c0d1eb | 6008 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6009 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6010 | if (mips_relax.sequence) |
6011 | relax_end (); | |
252b5132 RH |
6012 | } |
6013 | } | |
6014 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6015 | { | |
ed6fb7bd | 6016 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6017 | |
252b5132 RH |
6018 | /* If this is a reference to an external symbol, we want |
6019 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6020 | nop | |
6021 | <op> $treg,0($tempreg) | |
6022 | Otherwise we want | |
6023 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6024 | nop | |
6025 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6026 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6027 | |
6028 | For NewABI, we want | |
6029 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6030 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6031 | ||
252b5132 RH |
6032 | If there is a base register, we add it to $tempreg before |
6033 | the <op>. If there is a constant, we stick it in the | |
6034 | <op> instruction. We don't handle constants larger than | |
6035 | 16 bits, because we have no way to load the upper 16 bits | |
6036 | (actually, we could handle them for the subset of cases | |
6037 | in which we are not using $at). */ | |
6038 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6039 | if (HAVE_NEWABI) |
6040 | { | |
67c0d1eb RS |
6041 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6042 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6043 | if (breg != 0) |
67c0d1eb | 6044 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6045 | tempreg, tempreg, breg); |
67c0d1eb | 6046 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6047 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6048 | |
6049 | if (! used_at) | |
6050 | return; | |
6051 | ||
6052 | break; | |
6053 | } | |
252b5132 RH |
6054 | expr1.X_add_number = offset_expr.X_add_number; |
6055 | offset_expr.X_add_number = 0; | |
6056 | if (expr1.X_add_number < -0x8000 | |
6057 | || expr1.X_add_number >= 0x8000) | |
6058 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6059 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6060 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6061 | load_delay_nop (); |
4d7206a2 RS |
6062 | relax_start (offset_expr.X_add_symbol); |
6063 | relax_switch (); | |
67c0d1eb RS |
6064 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6065 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6066 | relax_end (); |
252b5132 | 6067 | if (breg != 0) |
67c0d1eb | 6068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6069 | tempreg, tempreg, breg); |
67c0d1eb | 6070 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6071 | } |
f5040a92 | 6072 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6073 | { |
67c0d1eb | 6074 | int gpdelay; |
252b5132 RH |
6075 | |
6076 | /* If this is a reference to an external symbol, we want | |
6077 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6078 | addu $tempreg,$tempreg,$gp | |
6079 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6080 | <op> $treg,0($tempreg) | |
6081 | Otherwise we want | |
6082 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6083 | nop | |
6084 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6085 | <op> $treg,0($tempreg) | |
6086 | If there is a base register, we add it to $tempreg before | |
6087 | the <op>. If there is a constant, we stick it in the | |
6088 | <op> instruction. We don't handle constants larger than | |
6089 | 16 bits, because we have no way to load the upper 16 bits | |
6090 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6091 | in which we are not using $at). */ |
252b5132 RH |
6092 | assert (offset_expr.X_op == O_symbol); |
6093 | expr1.X_add_number = offset_expr.X_add_number; | |
6094 | offset_expr.X_add_number = 0; | |
6095 | if (expr1.X_add_number < -0x8000 | |
6096 | || expr1.X_add_number >= 0x8000) | |
6097 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6098 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6099 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6100 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6101 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6102 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6103 | mips_gp_register); | |
6104 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6105 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6106 | relax_switch (); |
67c0d1eb RS |
6107 | if (gpdelay) |
6108 | macro_build (NULL, "nop", ""); | |
6109 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6110 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6111 | load_delay_nop (); |
67c0d1eb RS |
6112 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6113 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6114 | relax_end (); |
6115 | ||
252b5132 | 6116 | if (breg != 0) |
67c0d1eb | 6117 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6118 | tempreg, tempreg, breg); |
67c0d1eb | 6119 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6120 | } |
f5040a92 AO |
6121 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6122 | { | |
f5040a92 AO |
6123 | /* If this is a reference to an external symbol, we want |
6124 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6125 | add $tempreg,$tempreg,$gp | |
6126 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6127 | <op> $treg,<ofst>($tempreg) | |
6128 | Otherwise, for local symbols, we want: | |
6129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6130 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6131 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6132 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6133 | offset_expr.X_add_number = 0; |
6134 | if (expr1.X_add_number < -0x8000 | |
6135 | || expr1.X_add_number >= 0x8000) | |
6136 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6137 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6138 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6139 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6140 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6141 | mips_gp_register); | |
6142 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6143 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6144 | if (breg != 0) |
67c0d1eb | 6145 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6146 | tempreg, tempreg, breg); |
67c0d1eb | 6147 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6148 | |
4d7206a2 | 6149 | relax_switch (); |
f5040a92 | 6150 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6151 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6152 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6153 | if (breg != 0) |
67c0d1eb | 6154 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6155 | tempreg, tempreg, breg); |
67c0d1eb | 6156 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6157 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6158 | relax_end (); |
f5040a92 | 6159 | } |
252b5132 RH |
6160 | else |
6161 | abort (); | |
6162 | ||
6163 | if (! used_at) | |
6164 | return; | |
6165 | ||
6166 | break; | |
6167 | ||
6168 | case M_LI: | |
6169 | case M_LI_S: | |
67c0d1eb | 6170 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6171 | return; |
6172 | ||
6173 | case M_DLI: | |
67c0d1eb | 6174 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6175 | return; |
6176 | ||
6177 | case M_LI_SS: | |
6178 | if (imm_expr.X_op == O_constant) | |
6179 | { | |
67c0d1eb RS |
6180 | load_register (AT, &imm_expr, 0); |
6181 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6182 | break; |
6183 | } | |
6184 | else | |
6185 | { | |
6186 | assert (offset_expr.X_op == O_symbol | |
6187 | && strcmp (segment_name (S_GET_SEGMENT | |
6188 | (offset_expr.X_add_symbol)), | |
6189 | ".lit4") == 0 | |
6190 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6191 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6192 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6193 | return; |
6194 | } | |
6195 | ||
6196 | case M_LI_D: | |
ca4e0257 RS |
6197 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6198 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6199 | order 32 bits of the value and the low order 32 bits are either | |
6200 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6201 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6202 | { | |
ca4e0257 | 6203 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6204 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6205 | else |
6206 | { | |
6207 | int hreg, lreg; | |
6208 | ||
6209 | if (target_big_endian) | |
6210 | { | |
6211 | hreg = treg; | |
6212 | lreg = treg + 1; | |
6213 | } | |
6214 | else | |
6215 | { | |
6216 | hreg = treg + 1; | |
6217 | lreg = treg; | |
6218 | } | |
6219 | ||
6220 | if (hreg <= 31) | |
67c0d1eb | 6221 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6222 | if (lreg <= 31) |
6223 | { | |
6224 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6225 | move_register (lreg, 0); |
252b5132 RH |
6226 | else |
6227 | { | |
6228 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6229 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6230 | } |
6231 | } | |
6232 | } | |
6233 | return; | |
6234 | } | |
6235 | ||
6236 | /* We know that sym is in the .rdata section. First we get the | |
6237 | upper 16 bits of the address. */ | |
6238 | if (mips_pic == NO_PIC) | |
6239 | { | |
67c0d1eb | 6240 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6241 | } |
6242 | else if (mips_pic == SVR4_PIC) | |
6243 | { | |
67c0d1eb RS |
6244 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6245 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6246 | } |
252b5132 RH |
6247 | else |
6248 | abort (); | |
bdaaa2e1 | 6249 | |
252b5132 | 6250 | /* Now we load the register(s). */ |
ca4e0257 | 6251 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6252 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6253 | else |
6254 | { | |
67c0d1eb | 6255 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6256 | if (treg != RA) |
252b5132 RH |
6257 | { |
6258 | /* FIXME: How in the world do we deal with the possible | |
6259 | overflow here? */ | |
6260 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6261 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6262 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6263 | } |
6264 | } | |
252b5132 RH |
6265 | break; |
6266 | ||
6267 | case M_LI_DD: | |
ca4e0257 RS |
6268 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6269 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6270 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6271 | the value and the low order 32 bits are either zero or in | |
6272 | OFFSET_EXPR. */ | |
252b5132 RH |
6273 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6274 | { | |
67c0d1eb | 6275 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6276 | if (HAVE_64BIT_FPRS) |
6277 | { | |
6278 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6279 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6280 | } |
252b5132 RH |
6281 | else |
6282 | { | |
67c0d1eb | 6283 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6284 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6285 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6286 | else |
6287 | { | |
6288 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6289 | load_register (AT, &offset_expr, 0); |
6290 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6291 | } |
6292 | } | |
6293 | break; | |
6294 | } | |
6295 | ||
6296 | assert (offset_expr.X_op == O_symbol | |
6297 | && offset_expr.X_add_number == 0); | |
6298 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6299 | if (strcmp (s, ".lit8") == 0) | |
6300 | { | |
e7af610e | 6301 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6302 | { |
67c0d1eb | 6303 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6304 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6305 | return; |
6306 | } | |
c9914766 | 6307 | breg = mips_gp_register; |
252b5132 RH |
6308 | r = BFD_RELOC_MIPS_LITERAL; |
6309 | goto dob; | |
6310 | } | |
6311 | else | |
6312 | { | |
6313 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6314 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6315 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6316 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6317 | else |
6318 | { | |
6319 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6320 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6321 | } |
bdaaa2e1 | 6322 | |
e7af610e | 6323 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6324 | { |
67c0d1eb RS |
6325 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6326 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6327 | break; |
6328 | } | |
6329 | breg = AT; | |
6330 | r = BFD_RELOC_LO16; | |
6331 | goto dob; | |
6332 | } | |
6333 | ||
6334 | case M_L_DOB: | |
fef14a42 | 6335 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6336 | { |
6337 | as_bad (_("opcode not supported on this processor")); | |
6338 | return; | |
6339 | } | |
6340 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6341 | to adjust when loading from memory. */ | |
6342 | r = BFD_RELOC_LO16; | |
6343 | dob: | |
e7af610e | 6344 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6345 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6346 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6347 | /* FIXME: A possible overflow which I don't know how to deal |
6348 | with. */ | |
6349 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6350 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6351 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6352 | |
252b5132 RH |
6353 | if (breg != AT) |
6354 | return; | |
6355 | break; | |
6356 | ||
6357 | case M_L_DAB: | |
6358 | /* | |
6359 | * The MIPS assembler seems to check for X_add_number not | |
6360 | * being double aligned and generating: | |
6361 | * lui at,%hi(foo+1) | |
6362 | * addu at,at,v1 | |
6363 | * addiu at,at,%lo(foo+1) | |
6364 | * lwc1 f2,0(at) | |
6365 | * lwc1 f3,4(at) | |
6366 | * But, the resulting address is the same after relocation so why | |
6367 | * generate the extra instruction? | |
6368 | */ | |
fef14a42 | 6369 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6370 | { |
6371 | as_bad (_("opcode not supported on this processor")); | |
6372 | return; | |
6373 | } | |
bdaaa2e1 | 6374 | /* Itbl support may require additional care here. */ |
252b5132 | 6375 | coproc = 1; |
e7af610e | 6376 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6377 | { |
6378 | s = "ldc1"; | |
6379 | goto ld; | |
6380 | } | |
6381 | ||
6382 | s = "lwc1"; | |
6383 | fmt = "T,o(b)"; | |
6384 | goto ldd_std; | |
6385 | ||
6386 | case M_S_DAB: | |
fef14a42 | 6387 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6388 | { |
6389 | as_bad (_("opcode not supported on this processor")); | |
6390 | return; | |
6391 | } | |
6392 | ||
e7af610e | 6393 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6394 | { |
6395 | s = "sdc1"; | |
6396 | goto st; | |
6397 | } | |
6398 | ||
6399 | s = "swc1"; | |
6400 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6401 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6402 | coproc = 1; |
6403 | goto ldd_std; | |
6404 | ||
6405 | case M_LD_AB: | |
ca4e0257 | 6406 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6407 | { |
6408 | s = "ld"; | |
6409 | goto ld; | |
6410 | } | |
6411 | ||
6412 | s = "lw"; | |
6413 | fmt = "t,o(b)"; | |
6414 | goto ldd_std; | |
6415 | ||
6416 | case M_SD_AB: | |
ca4e0257 | 6417 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6418 | { |
6419 | s = "sd"; | |
6420 | goto st; | |
6421 | } | |
6422 | ||
6423 | s = "sw"; | |
6424 | fmt = "t,o(b)"; | |
6425 | ||
6426 | ldd_std: | |
6427 | if (offset_expr.X_op != O_symbol | |
6428 | && offset_expr.X_op != O_constant) | |
6429 | { | |
6430 | as_bad (_("expression too complex")); | |
6431 | offset_expr.X_op = O_constant; | |
6432 | } | |
6433 | ||
6434 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6435 | to adjust when loading from memory. We set coproc if we must | |
6436 | load $fn+1 first. */ | |
bdaaa2e1 | 6437 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6438 | if (! target_big_endian) |
6439 | coproc = 0; | |
6440 | ||
6441 | if (mips_pic == NO_PIC | |
6442 | || offset_expr.X_op == O_constant) | |
6443 | { | |
6444 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6445 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6446 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6447 | If we have a base register, we use this |
6448 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6449 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6450 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6451 | If this is not a GP relative symbol, we want |
6452 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6453 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6454 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6455 | If there is a base register, we add it to $at after the | |
6456 | lui instruction. If there is a constant, we always use | |
6457 | the last case. */ | |
e7d556df | 6458 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6459 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6460 | used_at = 1; |
252b5132 RH |
6461 | else |
6462 | { | |
4d7206a2 | 6463 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6464 | if (breg == 0) |
6465 | { | |
c9914766 | 6466 | tempreg = mips_gp_register; |
252b5132 RH |
6467 | used_at = 0; |
6468 | } | |
6469 | else | |
6470 | { | |
67c0d1eb | 6471 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6472 | AT, breg, mips_gp_register); |
252b5132 | 6473 | tempreg = AT; |
252b5132 RH |
6474 | used_at = 1; |
6475 | } | |
6476 | ||
beae10d5 | 6477 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6478 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6479 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6480 | offset_expr.X_add_number += 4; |
6481 | ||
6482 | /* Set mips_optimize to 2 to avoid inserting an | |
6483 | undesired nop. */ | |
6484 | hold_mips_optimize = mips_optimize; | |
6485 | mips_optimize = 2; | |
beae10d5 | 6486 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6487 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6488 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6489 | mips_optimize = hold_mips_optimize; |
6490 | ||
4d7206a2 | 6491 | relax_switch (); |
252b5132 RH |
6492 | |
6493 | /* We just generated two relocs. When tc_gen_reloc | |
6494 | handles this case, it will skip the first reloc and | |
6495 | handle the second. The second reloc already has an | |
6496 | extra addend of 4, which we added above. We must | |
6497 | subtract it out, and then subtract another 4 to make | |
6498 | the first reloc come out right. The second reloc | |
6499 | will come out right because we are going to add 4 to | |
6500 | offset_expr when we build its instruction below. | |
6501 | ||
6502 | If we have a symbol, then we don't want to include | |
6503 | the offset, because it will wind up being included | |
6504 | when we generate the reloc. */ | |
6505 | ||
6506 | if (offset_expr.X_op == O_constant) | |
6507 | offset_expr.X_add_number -= 8; | |
6508 | else | |
6509 | { | |
6510 | offset_expr.X_add_number = -4; | |
6511 | offset_expr.X_op = O_constant; | |
6512 | } | |
6513 | } | |
67c0d1eb | 6514 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6515 | if (breg != 0) |
67c0d1eb | 6516 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6517 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6518 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6519 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6520 | /* FIXME: How do we handle overflow here? */ |
6521 | offset_expr.X_add_number += 4; | |
beae10d5 | 6522 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6523 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6524 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6525 | if (mips_relax.sequence) |
6526 | relax_end (); | |
bdaaa2e1 | 6527 | } |
252b5132 RH |
6528 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6529 | { | |
252b5132 RH |
6530 | /* If this is a reference to an external symbol, we want |
6531 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6532 | nop | |
6533 | <op> $treg,0($at) | |
6534 | <op> $treg+1,4($at) | |
6535 | Otherwise we want | |
6536 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6537 | nop | |
6538 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6539 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6540 | If there is a base register we add it to $at before the | |
6541 | lwc1 instructions. If there is a constant we include it | |
6542 | in the lwc1 instructions. */ | |
6543 | used_at = 1; | |
6544 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6545 | if (expr1.X_add_number < -0x8000 |
6546 | || expr1.X_add_number >= 0x8000 - 4) | |
6547 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6548 | load_got_offset (AT, &offset_expr); |
269137b2 | 6549 | load_delay_nop (); |
252b5132 | 6550 | if (breg != 0) |
67c0d1eb | 6551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6552 | |
6553 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6554 | nop. */ | |
6555 | hold_mips_optimize = mips_optimize; | |
6556 | mips_optimize = 2; | |
4d7206a2 | 6557 | |
beae10d5 | 6558 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6559 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6560 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6561 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6562 | expr1.X_add_number += 4; |
67c0d1eb RS |
6563 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6564 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6565 | relax_switch (); |
67c0d1eb RS |
6566 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6567 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6568 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6569 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6570 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6571 | relax_end (); |
252b5132 | 6572 | |
4d7206a2 | 6573 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6574 | } |
6575 | else if (mips_pic == SVR4_PIC) | |
6576 | { | |
67c0d1eb | 6577 | int gpdelay; |
252b5132 RH |
6578 | |
6579 | /* If this is a reference to an external symbol, we want | |
6580 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6581 | addu $at,$at,$gp | |
6582 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6583 | nop | |
6584 | <op> $treg,0($at) | |
6585 | <op> $treg+1,4($at) | |
6586 | Otherwise we want | |
6587 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6588 | nop | |
6589 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6590 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6591 | If there is a base register we add it to $at before the | |
6592 | lwc1 instructions. If there is a constant we include it | |
6593 | in the lwc1 instructions. */ | |
6594 | used_at = 1; | |
6595 | expr1.X_add_number = offset_expr.X_add_number; | |
6596 | offset_expr.X_add_number = 0; | |
6597 | if (expr1.X_add_number < -0x8000 | |
6598 | || expr1.X_add_number >= 0x8000 - 4) | |
6599 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6600 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6601 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6602 | macro_build (&offset_expr, "lui", "t,u", |
6603 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6604 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6605 | AT, AT, mips_gp_register); |
67c0d1eb | 6606 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6607 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6608 | load_delay_nop (); |
252b5132 | 6609 | if (breg != 0) |
67c0d1eb | 6610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6611 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6612 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6613 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6614 | expr1.X_add_number += 4; |
6615 | ||
6616 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6617 | nop. */ | |
6618 | hold_mips_optimize = mips_optimize; | |
6619 | mips_optimize = 2; | |
beae10d5 | 6620 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6621 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6622 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6623 | mips_optimize = hold_mips_optimize; |
6624 | expr1.X_add_number -= 4; | |
6625 | ||
4d7206a2 RS |
6626 | relax_switch (); |
6627 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6628 | if (gpdelay) |
6629 | macro_build (NULL, "nop", ""); | |
6630 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6631 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6632 | load_delay_nop (); |
252b5132 | 6633 | if (breg != 0) |
67c0d1eb | 6634 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6635 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6636 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6637 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6638 | offset_expr.X_add_number += 4; |
252b5132 RH |
6639 | |
6640 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6641 | nop. */ | |
6642 | hold_mips_optimize = mips_optimize; | |
6643 | mips_optimize = 2; | |
beae10d5 | 6644 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6645 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6646 | BFD_RELOC_LO16, AT); | |
252b5132 | 6647 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6648 | relax_end (); |
252b5132 | 6649 | } |
252b5132 RH |
6650 | else |
6651 | abort (); | |
6652 | ||
6653 | if (! used_at) | |
6654 | return; | |
6655 | ||
6656 | break; | |
6657 | ||
6658 | case M_LD_OB: | |
6659 | s = "lw"; | |
6660 | goto sd_ob; | |
6661 | case M_SD_OB: | |
6662 | s = "sw"; | |
6663 | sd_ob: | |
ca4e0257 | 6664 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6665 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6666 | offset_expr.X_add_number += 4; |
67c0d1eb | 6667 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6668 | return; |
6669 | ||
6670 | /* New code added to support COPZ instructions. | |
6671 | This code builds table entries out of the macros in mip_opcodes. | |
6672 | R4000 uses interlocks to handle coproc delays. | |
6673 | Other chips (like the R3000) require nops to be inserted for delays. | |
6674 | ||
f72c8c98 | 6675 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6676 | In order to fill delay slots for non-interlocked chips, |
6677 | we must have a way to specify delays based on the coprocessor. | |
6678 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6679 | What are the side-effects of the cop instruction? | |
6680 | What cache support might we have and what are its effects? | |
6681 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6682 | What registers are read/set/modified? |
252b5132 RH |
6683 | |
6684 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6685 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6686 | |
6687 | case M_COP0: | |
6688 | s = "c0"; | |
6689 | goto copz; | |
6690 | case M_COP1: | |
6691 | s = "c1"; | |
6692 | goto copz; | |
6693 | case M_COP2: | |
6694 | s = "c2"; | |
6695 | goto copz; | |
6696 | case M_COP3: | |
6697 | s = "c3"; | |
6698 | copz: | |
6699 | /* For now we just do C (same as Cz). The parameter will be | |
6700 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6701 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6702 | return; |
6703 | ||
ea1fb5dc | 6704 | case M_MOVE: |
67c0d1eb | 6705 | move_register (dreg, sreg); |
ea1fb5dc RS |
6706 | return; |
6707 | ||
252b5132 RH |
6708 | #ifdef LOSING_COMPILER |
6709 | default: | |
6710 | /* Try and see if this is a new itbl instruction. | |
6711 | This code builds table entries out of the macros in mip_opcodes. | |
6712 | FIXME: For now we just assemble the expression and pass it's | |
6713 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6714 | We may want to have the assembler assemble this value, |
252b5132 RH |
6715 | so that we gain the assembler's knowledge of delay slots, |
6716 | symbols, etc. | |
6717 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6718 | if (itbl_have_entries |
252b5132 | 6719 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6720 | { |
252b5132 RH |
6721 | s = ip->insn_mo->name; |
6722 | s2 = "cop3"; | |
6723 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6724 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6725 | return; |
beae10d5 | 6726 | } |
252b5132 RH |
6727 | macro2 (ip); |
6728 | return; | |
6729 | } | |
6730 | if (mips_opts.noat) | |
6731 | as_warn (_("Macro used $at after \".set noat\"")); | |
6732 | } | |
bdaaa2e1 | 6733 | |
252b5132 | 6734 | static void |
17a2f251 | 6735 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6736 | { |
6737 | register int treg, sreg, dreg, breg; | |
6738 | int tempreg; | |
6739 | int mask; | |
252b5132 RH |
6740 | int used_at; |
6741 | expressionS expr1; | |
6742 | const char *s; | |
6743 | const char *s2; | |
6744 | const char *fmt; | |
6745 | int likely = 0; | |
6746 | int dbl = 0; | |
6747 | int coproc = 0; | |
6748 | int lr = 0; | |
6749 | int imm = 0; | |
6750 | int off; | |
6751 | offsetT maxnum; | |
6752 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6753 | |
252b5132 RH |
6754 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6755 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6756 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6757 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6758 | |
252b5132 RH |
6759 | expr1.X_op = O_constant; |
6760 | expr1.X_op_symbol = NULL; | |
6761 | expr1.X_add_symbol = NULL; | |
6762 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6763 | |
252b5132 RH |
6764 | switch (mask) |
6765 | { | |
6766 | #endif /* LOSING_COMPILER */ | |
6767 | ||
6768 | case M_DMUL: | |
6769 | dbl = 1; | |
6770 | case M_MUL: | |
67c0d1eb RS |
6771 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6772 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6773 | return; |
6774 | ||
6775 | case M_DMUL_I: | |
6776 | dbl = 1; | |
6777 | case M_MUL_I: | |
6778 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6779 | not trying to be that fancy. GCC should do this for us | |
6780 | anyway. */ | |
67c0d1eb RS |
6781 | load_register (AT, &imm_expr, dbl); |
6782 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6783 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6784 | break; |
6785 | ||
6786 | case M_DMULO_I: | |
6787 | dbl = 1; | |
6788 | case M_MULO_I: | |
6789 | imm = 1; | |
6790 | goto do_mulo; | |
6791 | ||
6792 | case M_DMULO: | |
6793 | dbl = 1; | |
6794 | case M_MULO: | |
6795 | do_mulo: | |
b34976b6 | 6796 | mips_emit_delays (TRUE); |
252b5132 RH |
6797 | ++mips_opts.noreorder; |
6798 | mips_any_noreorder = 1; | |
6799 | if (imm) | |
67c0d1eb RS |
6800 | load_register (AT, &imm_expr, dbl); |
6801 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6802 | macro_build (NULL, "mflo", "d", dreg); | |
6803 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6804 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6805 | if (mips_trap) |
67c0d1eb | 6806 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6807 | else |
6808 | { | |
6809 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6810 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6811 | macro_build (NULL, "nop", "", 0); | |
6812 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6813 | } |
6814 | --mips_opts.noreorder; | |
67c0d1eb | 6815 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6816 | break; |
6817 | ||
6818 | case M_DMULOU_I: | |
6819 | dbl = 1; | |
6820 | case M_MULOU_I: | |
6821 | imm = 1; | |
6822 | goto do_mulou; | |
6823 | ||
6824 | case M_DMULOU: | |
6825 | dbl = 1; | |
6826 | case M_MULOU: | |
6827 | do_mulou: | |
b34976b6 | 6828 | mips_emit_delays (TRUE); |
252b5132 RH |
6829 | ++mips_opts.noreorder; |
6830 | mips_any_noreorder = 1; | |
6831 | if (imm) | |
67c0d1eb RS |
6832 | load_register (AT, &imm_expr, dbl); |
6833 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6834 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6835 | macro_build (NULL, "mfhi", "d", AT); |
6836 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6837 | if (mips_trap) |
67c0d1eb | 6838 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6839 | else |
6840 | { | |
6841 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6842 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6843 | macro_build (NULL, "nop", "", 0); | |
6844 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6845 | } |
6846 | --mips_opts.noreorder; | |
6847 | break; | |
6848 | ||
771c7ce4 | 6849 | case M_DROL: |
fef14a42 | 6850 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6851 | { |
6852 | if (dreg == sreg) | |
6853 | { | |
6854 | tempreg = AT; | |
6855 | used_at = 1; | |
6856 | } | |
6857 | else | |
6858 | { | |
6859 | tempreg = dreg; | |
6860 | used_at = 0; | |
6861 | } | |
67c0d1eb RS |
6862 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6863 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6864 | if (used_at) |
6865 | break; | |
6866 | return; | |
6867 | } | |
67c0d1eb RS |
6868 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6869 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6870 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6871 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6872 | break; |
6873 | ||
252b5132 | 6874 | case M_ROL: |
fef14a42 | 6875 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6876 | { |
6877 | if (dreg == sreg) | |
6878 | { | |
6879 | tempreg = AT; | |
6880 | used_at = 1; | |
6881 | } | |
6882 | else | |
6883 | { | |
6884 | tempreg = dreg; | |
6885 | used_at = 0; | |
6886 | } | |
67c0d1eb RS |
6887 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6888 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6889 | if (used_at) |
6890 | break; | |
6891 | return; | |
6892 | } | |
67c0d1eb RS |
6893 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6894 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6895 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6896 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6897 | break; |
6898 | ||
771c7ce4 TS |
6899 | case M_DROL_I: |
6900 | { | |
6901 | unsigned int rot; | |
82dd0097 | 6902 | char *l, *r; |
771c7ce4 TS |
6903 | |
6904 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6905 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6906 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6907 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6908 | { |
6909 | rot = (64 - rot) & 0x3f; | |
6910 | if (rot >= 32) | |
67c0d1eb | 6911 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6912 | else |
67c0d1eb | 6913 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 6914 | return; |
60b63b72 | 6915 | } |
483fc7cd | 6916 | if (rot == 0) |
483fc7cd | 6917 | { |
67c0d1eb | 6918 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6919 | return; |
483fc7cd | 6920 | } |
82dd0097 CD |
6921 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6922 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6923 | rot &= 0x1f; | |
67c0d1eb RS |
6924 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6925 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6926 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6927 | } |
6928 | break; | |
6929 | ||
252b5132 | 6930 | case M_ROL_I: |
771c7ce4 TS |
6931 | { |
6932 | unsigned int rot; | |
6933 | ||
6934 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6935 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6936 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6937 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6938 | { |
67c0d1eb | 6939 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 6940 | return; |
60b63b72 | 6941 | } |
483fc7cd | 6942 | if (rot == 0) |
483fc7cd | 6943 | { |
67c0d1eb | 6944 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6945 | return; |
483fc7cd | 6946 | } |
67c0d1eb RS |
6947 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6948 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6949 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6950 | } |
6951 | break; | |
6952 | ||
6953 | case M_DROR: | |
fef14a42 | 6954 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6955 | { |
67c0d1eb | 6956 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6957 | return; |
6958 | } | |
67c0d1eb RS |
6959 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6960 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6961 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6962 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6963 | break; |
6964 | ||
6965 | case M_ROR: | |
fef14a42 | 6966 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6967 | { |
67c0d1eb | 6968 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6969 | return; |
6970 | } | |
67c0d1eb RS |
6971 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6972 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6973 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6974 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6975 | break; |
6976 | ||
771c7ce4 TS |
6977 | case M_DROR_I: |
6978 | { | |
6979 | unsigned int rot; | |
82dd0097 | 6980 | char *l, *r; |
771c7ce4 TS |
6981 | |
6982 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6983 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6984 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6985 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6986 | { |
6987 | if (rot >= 32) | |
67c0d1eb | 6988 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6989 | else |
67c0d1eb | 6990 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
6991 | return; |
6992 | } | |
483fc7cd | 6993 | if (rot == 0) |
483fc7cd | 6994 | { |
67c0d1eb | 6995 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6996 | return; |
483fc7cd | 6997 | } |
82dd0097 CD |
6998 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6999 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7000 | rot &= 0x1f; | |
67c0d1eb RS |
7001 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7002 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7003 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7004 | } |
7005 | break; | |
7006 | ||
252b5132 | 7007 | case M_ROR_I: |
771c7ce4 TS |
7008 | { |
7009 | unsigned int rot; | |
7010 | ||
7011 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7012 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7013 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7014 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7015 | { |
67c0d1eb | 7016 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7017 | return; |
7018 | } | |
483fc7cd | 7019 | if (rot == 0) |
483fc7cd | 7020 | { |
67c0d1eb | 7021 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7022 | return; |
483fc7cd | 7023 | } |
67c0d1eb RS |
7024 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7025 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7026 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7027 | } |
252b5132 RH |
7028 | break; |
7029 | ||
7030 | case M_S_DOB: | |
fef14a42 | 7031 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7032 | { |
7033 | as_bad (_("opcode not supported on this processor")); | |
7034 | return; | |
7035 | } | |
e7af610e | 7036 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7037 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7038 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7039 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7040 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7041 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7042 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7043 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7044 | return; |
7045 | ||
7046 | case M_SEQ: | |
7047 | if (sreg == 0) | |
67c0d1eb | 7048 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7049 | else if (treg == 0) |
67c0d1eb | 7050 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7051 | else |
7052 | { | |
67c0d1eb RS |
7053 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7054 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7055 | } |
7056 | return; | |
7057 | ||
7058 | case M_SEQ_I: | |
7059 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7060 | { | |
67c0d1eb | 7061 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7062 | return; |
7063 | } | |
7064 | if (sreg == 0) | |
7065 | { | |
7066 | as_warn (_("Instruction %s: result is always false"), | |
7067 | ip->insn_mo->name); | |
67c0d1eb | 7068 | move_register (dreg, 0); |
252b5132 RH |
7069 | return; |
7070 | } | |
7071 | if (imm_expr.X_op == O_constant | |
7072 | && imm_expr.X_add_number >= 0 | |
7073 | && imm_expr.X_add_number < 0x10000) | |
7074 | { | |
67c0d1eb | 7075 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7076 | used_at = 0; |
7077 | } | |
7078 | else if (imm_expr.X_op == O_constant | |
7079 | && imm_expr.X_add_number > -0x8000 | |
7080 | && imm_expr.X_add_number < 0) | |
7081 | { | |
7082 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7083 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7084 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7085 | used_at = 0; |
7086 | } | |
7087 | else | |
7088 | { | |
67c0d1eb RS |
7089 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7090 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7091 | used_at = 1; |
7092 | } | |
67c0d1eb | 7093 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7094 | if (used_at) |
7095 | break; | |
7096 | return; | |
7097 | ||
7098 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7099 | s = "slt"; | |
7100 | goto sge; | |
7101 | case M_SGEU: | |
7102 | s = "sltu"; | |
7103 | sge: | |
67c0d1eb RS |
7104 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7105 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7106 | return; |
7107 | ||
7108 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7109 | case M_SGEU_I: | |
7110 | if (imm_expr.X_op == O_constant | |
7111 | && imm_expr.X_add_number >= -0x8000 | |
7112 | && imm_expr.X_add_number < 0x8000) | |
7113 | { | |
67c0d1eb RS |
7114 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7115 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7116 | used_at = 0; |
7117 | } | |
7118 | else | |
7119 | { | |
67c0d1eb RS |
7120 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7121 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7122 | dreg, sreg, AT); | |
252b5132 RH |
7123 | used_at = 1; |
7124 | } | |
67c0d1eb | 7125 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7126 | if (used_at) |
7127 | break; | |
7128 | return; | |
7129 | ||
7130 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7131 | s = "slt"; | |
7132 | goto sgt; | |
7133 | case M_SGTU: | |
7134 | s = "sltu"; | |
7135 | sgt: | |
67c0d1eb | 7136 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7137 | return; |
7138 | ||
7139 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7140 | s = "slt"; | |
7141 | goto sgti; | |
7142 | case M_SGTU_I: | |
7143 | s = "sltu"; | |
7144 | sgti: | |
67c0d1eb RS |
7145 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7146 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7147 | break; |
7148 | ||
2396cfb9 | 7149 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7150 | s = "slt"; |
7151 | goto sle; | |
7152 | case M_SLEU: | |
7153 | s = "sltu"; | |
7154 | sle: | |
67c0d1eb RS |
7155 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7156 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7157 | return; |
7158 | ||
2396cfb9 | 7159 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7160 | s = "slt"; |
7161 | goto slei; | |
7162 | case M_SLEU_I: | |
7163 | s = "sltu"; | |
7164 | slei: | |
67c0d1eb RS |
7165 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7166 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7167 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7168 | break; |
7169 | ||
7170 | case M_SLT_I: | |
7171 | if (imm_expr.X_op == O_constant | |
7172 | && imm_expr.X_add_number >= -0x8000 | |
7173 | && imm_expr.X_add_number < 0x8000) | |
7174 | { | |
67c0d1eb | 7175 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7176 | return; |
7177 | } | |
67c0d1eb RS |
7178 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7179 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7180 | break; |
7181 | ||
7182 | case M_SLTU_I: | |
7183 | if (imm_expr.X_op == O_constant | |
7184 | && imm_expr.X_add_number >= -0x8000 | |
7185 | && imm_expr.X_add_number < 0x8000) | |
7186 | { | |
67c0d1eb | 7187 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7188 | BFD_RELOC_LO16); |
252b5132 RH |
7189 | return; |
7190 | } | |
67c0d1eb RS |
7191 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7192 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7193 | break; |
7194 | ||
7195 | case M_SNE: | |
7196 | if (sreg == 0) | |
67c0d1eb | 7197 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7198 | else if (treg == 0) |
67c0d1eb | 7199 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7200 | else |
7201 | { | |
67c0d1eb RS |
7202 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7203 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7204 | } |
7205 | return; | |
7206 | ||
7207 | case M_SNE_I: | |
7208 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7209 | { | |
67c0d1eb | 7210 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7211 | return; |
7212 | } | |
7213 | if (sreg == 0) | |
7214 | { | |
7215 | as_warn (_("Instruction %s: result is always true"), | |
7216 | ip->insn_mo->name); | |
67c0d1eb RS |
7217 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7218 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7219 | return; |
7220 | } | |
7221 | if (imm_expr.X_op == O_constant | |
7222 | && imm_expr.X_add_number >= 0 | |
7223 | && imm_expr.X_add_number < 0x10000) | |
7224 | { | |
67c0d1eb | 7225 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7226 | used_at = 0; |
7227 | } | |
7228 | else if (imm_expr.X_op == O_constant | |
7229 | && imm_expr.X_add_number > -0x8000 | |
7230 | && imm_expr.X_add_number < 0) | |
7231 | { | |
7232 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7233 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7234 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7235 | used_at = 0; |
7236 | } | |
7237 | else | |
7238 | { | |
67c0d1eb RS |
7239 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7240 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7241 | used_at = 1; |
7242 | } | |
67c0d1eb | 7243 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7244 | if (used_at) |
7245 | break; | |
7246 | return; | |
7247 | ||
7248 | case M_DSUB_I: | |
7249 | dbl = 1; | |
7250 | case M_SUB_I: | |
7251 | if (imm_expr.X_op == O_constant | |
7252 | && imm_expr.X_add_number > -0x8000 | |
7253 | && imm_expr.X_add_number <= 0x8000) | |
7254 | { | |
7255 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7256 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7257 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7258 | return; |
7259 | } | |
67c0d1eb RS |
7260 | load_register (AT, &imm_expr, dbl); |
7261 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7262 | break; |
7263 | ||
7264 | case M_DSUBU_I: | |
7265 | dbl = 1; | |
7266 | case M_SUBU_I: | |
7267 | if (imm_expr.X_op == O_constant | |
7268 | && imm_expr.X_add_number > -0x8000 | |
7269 | && imm_expr.X_add_number <= 0x8000) | |
7270 | { | |
7271 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7272 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7273 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7274 | return; |
7275 | } | |
67c0d1eb RS |
7276 | load_register (AT, &imm_expr, dbl); |
7277 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7278 | break; |
7279 | ||
7280 | case M_TEQ_I: | |
7281 | s = "teq"; | |
7282 | goto trap; | |
7283 | case M_TGE_I: | |
7284 | s = "tge"; | |
7285 | goto trap; | |
7286 | case M_TGEU_I: | |
7287 | s = "tgeu"; | |
7288 | goto trap; | |
7289 | case M_TLT_I: | |
7290 | s = "tlt"; | |
7291 | goto trap; | |
7292 | case M_TLTU_I: | |
7293 | s = "tltu"; | |
7294 | goto trap; | |
7295 | case M_TNE_I: | |
7296 | s = "tne"; | |
7297 | trap: | |
67c0d1eb RS |
7298 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7299 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7300 | break; |
7301 | ||
252b5132 | 7302 | case M_TRUNCWS: |
43841e91 | 7303 | case M_TRUNCWD: |
e7af610e | 7304 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7305 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7306 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7307 | ||
7308 | /* | |
7309 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7310 | * or is there a reason for it? | |
7311 | */ | |
b34976b6 | 7312 | mips_emit_delays (TRUE); |
252b5132 RH |
7313 | ++mips_opts.noreorder; |
7314 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7315 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7316 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7317 | macro_build (NULL, "nop", ""); | |
252b5132 | 7318 | expr1.X_add_number = 3; |
67c0d1eb | 7319 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7320 | expr1.X_add_number = 2; |
67c0d1eb RS |
7321 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7322 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7323 | macro_build (NULL, "nop", ""); | |
7324 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7325 | dreg, sreg); | |
7326 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7327 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7328 | --mips_opts.noreorder; |
7329 | break; | |
7330 | ||
7331 | case M_ULH: | |
7332 | s = "lb"; | |
7333 | goto ulh; | |
7334 | case M_ULHU: | |
7335 | s = "lbu"; | |
7336 | ulh: | |
7337 | if (offset_expr.X_add_number >= 0x7fff) | |
7338 | as_bad (_("operand overflow")); | |
252b5132 | 7339 | if (! target_big_endian) |
f9419b05 | 7340 | ++offset_expr.X_add_number; |
67c0d1eb | 7341 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7342 | if (! target_big_endian) |
f9419b05 | 7343 | --offset_expr.X_add_number; |
252b5132 | 7344 | else |
f9419b05 | 7345 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7346 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7347 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7348 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7349 | break; |
7350 | ||
7351 | case M_ULD: | |
7352 | s = "ldl"; | |
7353 | s2 = "ldr"; | |
7354 | off = 7; | |
7355 | goto ulw; | |
7356 | case M_ULW: | |
7357 | s = "lwl"; | |
7358 | s2 = "lwr"; | |
7359 | off = 3; | |
7360 | ulw: | |
7361 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7362 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7363 | if (treg != breg) |
7364 | tempreg = treg; | |
7365 | else | |
7366 | tempreg = AT; | |
252b5132 RH |
7367 | if (! target_big_endian) |
7368 | offset_expr.X_add_number += off; | |
67c0d1eb | 7369 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7370 | if (! target_big_endian) |
7371 | offset_expr.X_add_number -= off; | |
7372 | else | |
7373 | offset_expr.X_add_number += off; | |
67c0d1eb | 7374 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7375 | |
7376 | /* If necessary, move the result in tempreg the final destination. */ | |
7377 | if (treg == tempreg) | |
7378 | return; | |
7379 | /* Protect second load's delay slot. */ | |
017315e4 | 7380 | load_delay_nop (); |
67c0d1eb | 7381 | move_register (treg, tempreg); |
af22f5b2 | 7382 | break; |
252b5132 RH |
7383 | |
7384 | case M_ULD_A: | |
7385 | s = "ldl"; | |
7386 | s2 = "ldr"; | |
7387 | off = 7; | |
7388 | goto ulwa; | |
7389 | case M_ULW_A: | |
7390 | s = "lwl"; | |
7391 | s2 = "lwr"; | |
7392 | off = 3; | |
7393 | ulwa: | |
d6bc6245 | 7394 | used_at = 1; |
67c0d1eb | 7395 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7396 | if (breg != 0) |
67c0d1eb | 7397 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7398 | if (! target_big_endian) |
7399 | expr1.X_add_number = off; | |
7400 | else | |
7401 | expr1.X_add_number = 0; | |
67c0d1eb | 7402 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7403 | if (! target_big_endian) |
7404 | expr1.X_add_number = 0; | |
7405 | else | |
7406 | expr1.X_add_number = off; | |
67c0d1eb | 7407 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7408 | break; |
7409 | ||
7410 | case M_ULH_A: | |
7411 | case M_ULHU_A: | |
d6bc6245 | 7412 | used_at = 1; |
67c0d1eb | 7413 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7414 | if (breg != 0) |
67c0d1eb | 7415 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7416 | if (target_big_endian) |
7417 | expr1.X_add_number = 0; | |
67c0d1eb | 7418 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7419 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7420 | if (target_big_endian) |
7421 | expr1.X_add_number = 1; | |
7422 | else | |
7423 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7424 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7425 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7426 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7427 | break; |
7428 | ||
7429 | case M_USH: | |
7430 | if (offset_expr.X_add_number >= 0x7fff) | |
7431 | as_bad (_("operand overflow")); | |
7432 | if (target_big_endian) | |
f9419b05 | 7433 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7434 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7435 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7436 | if (target_big_endian) |
f9419b05 | 7437 | --offset_expr.X_add_number; |
252b5132 | 7438 | else |
f9419b05 | 7439 | ++offset_expr.X_add_number; |
67c0d1eb | 7440 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7441 | break; |
7442 | ||
7443 | case M_USD: | |
7444 | s = "sdl"; | |
7445 | s2 = "sdr"; | |
7446 | off = 7; | |
7447 | goto usw; | |
7448 | case M_USW: | |
7449 | s = "swl"; | |
7450 | s2 = "swr"; | |
7451 | off = 3; | |
7452 | usw: | |
7453 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7454 | as_bad (_("operand overflow")); | |
7455 | if (! target_big_endian) | |
7456 | offset_expr.X_add_number += off; | |
67c0d1eb | 7457 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7458 | if (! target_big_endian) |
7459 | offset_expr.X_add_number -= off; | |
7460 | else | |
7461 | offset_expr.X_add_number += off; | |
67c0d1eb | 7462 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7463 | return; |
7464 | ||
7465 | case M_USD_A: | |
7466 | s = "sdl"; | |
7467 | s2 = "sdr"; | |
7468 | off = 7; | |
7469 | goto uswa; | |
7470 | case M_USW_A: | |
7471 | s = "swl"; | |
7472 | s2 = "swr"; | |
7473 | off = 3; | |
7474 | uswa: | |
d6bc6245 | 7475 | used_at = 1; |
67c0d1eb | 7476 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7477 | if (breg != 0) |
67c0d1eb | 7478 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7479 | if (! target_big_endian) |
7480 | expr1.X_add_number = off; | |
7481 | else | |
7482 | expr1.X_add_number = 0; | |
67c0d1eb | 7483 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7484 | if (! target_big_endian) |
7485 | expr1.X_add_number = 0; | |
7486 | else | |
7487 | expr1.X_add_number = off; | |
67c0d1eb | 7488 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7489 | break; |
7490 | ||
7491 | case M_USH_A: | |
d6bc6245 | 7492 | used_at = 1; |
67c0d1eb | 7493 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7494 | if (breg != 0) |
67c0d1eb | 7495 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7496 | if (! target_big_endian) |
7497 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7498 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7499 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7500 | if (! target_big_endian) |
7501 | expr1.X_add_number = 1; | |
7502 | else | |
7503 | expr1.X_add_number = 0; | |
67c0d1eb | 7504 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7505 | if (! target_big_endian) |
7506 | expr1.X_add_number = 0; | |
7507 | else | |
7508 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7509 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7510 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7511 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7512 | break; |
7513 | ||
7514 | default: | |
7515 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7516 | are added dynamically. */ |
252b5132 RH |
7517 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7518 | break; | |
7519 | } | |
7520 | if (mips_opts.noat) | |
7521 | as_warn (_("Macro used $at after \".set noat\"")); | |
7522 | } | |
7523 | ||
7524 | /* Implement macros in mips16 mode. */ | |
7525 | ||
7526 | static void | |
17a2f251 | 7527 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7528 | { |
7529 | int mask; | |
7530 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7531 | expressionS expr1; |
7532 | int dbl; | |
7533 | const char *s, *s2, *s3; | |
7534 | ||
7535 | mask = ip->insn_mo->mask; | |
7536 | ||
7537 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7538 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7539 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7540 | ||
252b5132 RH |
7541 | expr1.X_op = O_constant; |
7542 | expr1.X_op_symbol = NULL; | |
7543 | expr1.X_add_symbol = NULL; | |
7544 | expr1.X_add_number = 1; | |
7545 | ||
7546 | dbl = 0; | |
7547 | ||
7548 | switch (mask) | |
7549 | { | |
7550 | default: | |
7551 | internalError (); | |
7552 | ||
7553 | case M_DDIV_3: | |
7554 | dbl = 1; | |
7555 | case M_DIV_3: | |
7556 | s = "mflo"; | |
7557 | goto do_div3; | |
7558 | case M_DREM_3: | |
7559 | dbl = 1; | |
7560 | case M_REM_3: | |
7561 | s = "mfhi"; | |
7562 | do_div3: | |
b34976b6 | 7563 | mips_emit_delays (TRUE); |
252b5132 RH |
7564 | ++mips_opts.noreorder; |
7565 | mips_any_noreorder = 1; | |
67c0d1eb | 7566 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7567 | expr1.X_add_number = 2; |
67c0d1eb RS |
7568 | macro_build (&expr1, "bnez", "x,p", yreg); |
7569 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7570 | |
252b5132 RH |
7571 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7572 | since that causes an overflow. We should do that as well, | |
7573 | but I don't see how to do the comparisons without a temporary | |
7574 | register. */ | |
7575 | --mips_opts.noreorder; | |
67c0d1eb | 7576 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7577 | break; |
7578 | ||
7579 | case M_DIVU_3: | |
7580 | s = "divu"; | |
7581 | s2 = "mflo"; | |
7582 | goto do_divu3; | |
7583 | case M_REMU_3: | |
7584 | s = "divu"; | |
7585 | s2 = "mfhi"; | |
7586 | goto do_divu3; | |
7587 | case M_DDIVU_3: | |
7588 | s = "ddivu"; | |
7589 | s2 = "mflo"; | |
7590 | goto do_divu3; | |
7591 | case M_DREMU_3: | |
7592 | s = "ddivu"; | |
7593 | s2 = "mfhi"; | |
7594 | do_divu3: | |
b34976b6 | 7595 | mips_emit_delays (TRUE); |
252b5132 RH |
7596 | ++mips_opts.noreorder; |
7597 | mips_any_noreorder = 1; | |
67c0d1eb | 7598 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7599 | expr1.X_add_number = 2; |
67c0d1eb RS |
7600 | macro_build (&expr1, "bnez", "x,p", yreg); |
7601 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7602 | --mips_opts.noreorder; |
67c0d1eb | 7603 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7604 | break; |
7605 | ||
7606 | case M_DMUL: | |
7607 | dbl = 1; | |
7608 | case M_MUL: | |
67c0d1eb RS |
7609 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7610 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7611 | return; |
7612 | ||
7613 | case M_DSUBU_I: | |
7614 | dbl = 1; | |
7615 | goto do_subu; | |
7616 | case M_SUBU_I: | |
7617 | do_subu: | |
7618 | if (imm_expr.X_op != O_constant) | |
7619 | as_bad (_("Unsupported large constant")); | |
7620 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7621 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7622 | break; |
7623 | ||
7624 | case M_SUBU_I_2: | |
7625 | if (imm_expr.X_op != O_constant) | |
7626 | as_bad (_("Unsupported large constant")); | |
7627 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7628 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7629 | break; |
7630 | ||
7631 | case M_DSUBU_I_2: | |
7632 | if (imm_expr.X_op != O_constant) | |
7633 | as_bad (_("Unsupported large constant")); | |
7634 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7635 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7636 | break; |
7637 | ||
7638 | case M_BEQ: | |
7639 | s = "cmp"; | |
7640 | s2 = "bteqz"; | |
7641 | goto do_branch; | |
7642 | case M_BNE: | |
7643 | s = "cmp"; | |
7644 | s2 = "btnez"; | |
7645 | goto do_branch; | |
7646 | case M_BLT: | |
7647 | s = "slt"; | |
7648 | s2 = "btnez"; | |
7649 | goto do_branch; | |
7650 | case M_BLTU: | |
7651 | s = "sltu"; | |
7652 | s2 = "btnez"; | |
7653 | goto do_branch; | |
7654 | case M_BLE: | |
7655 | s = "slt"; | |
7656 | s2 = "bteqz"; | |
7657 | goto do_reverse_branch; | |
7658 | case M_BLEU: | |
7659 | s = "sltu"; | |
7660 | s2 = "bteqz"; | |
7661 | goto do_reverse_branch; | |
7662 | case M_BGE: | |
7663 | s = "slt"; | |
7664 | s2 = "bteqz"; | |
7665 | goto do_branch; | |
7666 | case M_BGEU: | |
7667 | s = "sltu"; | |
7668 | s2 = "bteqz"; | |
7669 | goto do_branch; | |
7670 | case M_BGT: | |
7671 | s = "slt"; | |
7672 | s2 = "btnez"; | |
7673 | goto do_reverse_branch; | |
7674 | case M_BGTU: | |
7675 | s = "sltu"; | |
7676 | s2 = "btnez"; | |
7677 | ||
7678 | do_reverse_branch: | |
7679 | tmp = xreg; | |
7680 | xreg = yreg; | |
7681 | yreg = tmp; | |
7682 | ||
7683 | do_branch: | |
67c0d1eb RS |
7684 | macro_build (NULL, s, "x,y", xreg, yreg); |
7685 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7686 | break; |
7687 | ||
7688 | case M_BEQ_I: | |
7689 | s = "cmpi"; | |
7690 | s2 = "bteqz"; | |
7691 | s3 = "x,U"; | |
7692 | goto do_branch_i; | |
7693 | case M_BNE_I: | |
7694 | s = "cmpi"; | |
7695 | s2 = "btnez"; | |
7696 | s3 = "x,U"; | |
7697 | goto do_branch_i; | |
7698 | case M_BLT_I: | |
7699 | s = "slti"; | |
7700 | s2 = "btnez"; | |
7701 | s3 = "x,8"; | |
7702 | goto do_branch_i; | |
7703 | case M_BLTU_I: | |
7704 | s = "sltiu"; | |
7705 | s2 = "btnez"; | |
7706 | s3 = "x,8"; | |
7707 | goto do_branch_i; | |
7708 | case M_BLE_I: | |
7709 | s = "slti"; | |
7710 | s2 = "btnez"; | |
7711 | s3 = "x,8"; | |
7712 | goto do_addone_branch_i; | |
7713 | case M_BLEU_I: | |
7714 | s = "sltiu"; | |
7715 | s2 = "btnez"; | |
7716 | s3 = "x,8"; | |
7717 | goto do_addone_branch_i; | |
7718 | case M_BGE_I: | |
7719 | s = "slti"; | |
7720 | s2 = "bteqz"; | |
7721 | s3 = "x,8"; | |
7722 | goto do_branch_i; | |
7723 | case M_BGEU_I: | |
7724 | s = "sltiu"; | |
7725 | s2 = "bteqz"; | |
7726 | s3 = "x,8"; | |
7727 | goto do_branch_i; | |
7728 | case M_BGT_I: | |
7729 | s = "slti"; | |
7730 | s2 = "bteqz"; | |
7731 | s3 = "x,8"; | |
7732 | goto do_addone_branch_i; | |
7733 | case M_BGTU_I: | |
7734 | s = "sltiu"; | |
7735 | s2 = "bteqz"; | |
7736 | s3 = "x,8"; | |
7737 | ||
7738 | do_addone_branch_i: | |
7739 | if (imm_expr.X_op != O_constant) | |
7740 | as_bad (_("Unsupported large constant")); | |
7741 | ++imm_expr.X_add_number; | |
7742 | ||
7743 | do_branch_i: | |
67c0d1eb RS |
7744 | macro_build (&imm_expr, s, s3, xreg); |
7745 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7746 | break; |
7747 | ||
7748 | case M_ABS: | |
7749 | expr1.X_add_number = 0; | |
67c0d1eb | 7750 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7751 | if (xreg != yreg) |
67c0d1eb | 7752 | move_register (xreg, yreg); |
252b5132 | 7753 | expr1.X_add_number = 2; |
67c0d1eb RS |
7754 | macro_build (&expr1, "bteqz", "p"); |
7755 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7756 | } |
7757 | } | |
7758 | ||
7759 | /* For consistency checking, verify that all bits are specified either | |
7760 | by the match/mask part of the instruction definition, or by the | |
7761 | operand list. */ | |
7762 | static int | |
17a2f251 | 7763 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7764 | { |
7765 | const char *p = opc->args; | |
7766 | char c; | |
7767 | unsigned long used_bits = opc->mask; | |
7768 | ||
7769 | if ((used_bits & opc->match) != opc->match) | |
7770 | { | |
7771 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7772 | opc->name, opc->args); | |
7773 | return 0; | |
7774 | } | |
7775 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7776 | while (*p) | |
7777 | switch (c = *p++) | |
7778 | { | |
7779 | case ',': break; | |
7780 | case '(': break; | |
7781 | case ')': break; | |
af7ee8bf CD |
7782 | case '+': |
7783 | switch (c = *p++) | |
7784 | { | |
7785 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7786 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7787 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7788 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7789 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7790 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7791 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7792 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7793 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7794 | case 'I': break; | |
af7ee8bf CD |
7795 | default: |
7796 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7797 | c, opc->name, opc->args); | |
7798 | return 0; | |
7799 | } | |
7800 | break; | |
252b5132 RH |
7801 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7802 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7803 | case 'A': break; | |
4372b673 | 7804 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7805 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7806 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7807 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7808 | case 'F': break; | |
7809 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7810 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7811 | case 'I': break; |
e972090a | 7812 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7813 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7814 | case 'L': break; |
7815 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7816 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7817 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7818 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7819 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7820 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7821 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7822 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7823 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7824 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7825 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7826 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7827 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7828 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7829 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7830 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7831 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7832 | case 'f': break; | |
7833 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7834 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7835 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7836 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7837 | case 'l': break; | |
7838 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7839 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7840 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7841 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7842 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7843 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7844 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7845 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7846 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7847 | case 'x': break; | |
7848 | case 'z': break; | |
7849 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7850 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7851 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7852 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7853 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7854 | case '[': break; | |
7855 | case ']': break; | |
252b5132 RH |
7856 | default: |
7857 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7858 | c, opc->name, opc->args); | |
7859 | return 0; | |
7860 | } | |
7861 | #undef USE_BITS | |
7862 | if (used_bits != 0xffffffff) | |
7863 | { | |
7864 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7865 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7866 | return 0; | |
7867 | } | |
7868 | return 1; | |
7869 | } | |
7870 | ||
7871 | /* This routine assembles an instruction into its binary format. As a | |
7872 | side effect, it sets one of the global variables imm_reloc or | |
7873 | offset_reloc to the type of relocation to do if one of the operands | |
7874 | is an address expression. */ | |
7875 | ||
7876 | static void | |
17a2f251 | 7877 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7878 | { |
7879 | char *s; | |
7880 | const char *args; | |
43841e91 | 7881 | char c = 0; |
252b5132 RH |
7882 | struct mips_opcode *insn; |
7883 | char *argsStart; | |
7884 | unsigned int regno; | |
7885 | unsigned int lastregno = 0; | |
af7ee8bf | 7886 | unsigned int lastpos = 0; |
071742cf | 7887 | unsigned int limlo, limhi; |
252b5132 RH |
7888 | char *s_reset; |
7889 | char save_c = 0; | |
252b5132 RH |
7890 | |
7891 | insn_error = NULL; | |
7892 | ||
7893 | /* If the instruction contains a '.', we first try to match an instruction | |
7894 | including the '.'. Then we try again without the '.'. */ | |
7895 | insn = NULL; | |
3882b010 | 7896 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7897 | continue; |
7898 | ||
7899 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7900 | the call to hash_find. Save the character we replaced just in case we | |
7901 | have to re-parse the instruction. */ | |
3882b010 | 7902 | if (ISSPACE (*s)) |
252b5132 RH |
7903 | { |
7904 | save_c = *s; | |
7905 | *s++ = '\0'; | |
7906 | } | |
bdaaa2e1 | 7907 | |
252b5132 RH |
7908 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7909 | ||
7910 | /* If we didn't find the instruction in the opcode table, try again, but | |
7911 | this time with just the instruction up to, but not including the | |
7912 | first '.'. */ | |
7913 | if (insn == NULL) | |
7914 | { | |
bdaaa2e1 | 7915 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7916 | if (save_c) |
7917 | *(--s) = save_c; | |
7918 | ||
7919 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7920 | for (s = str; |
7921 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7922 | ++s) | |
252b5132 RH |
7923 | continue; |
7924 | ||
7925 | /* If we did not find a '.', then we can quit now. */ | |
7926 | if (*s != '.') | |
7927 | { | |
7928 | insn_error = "unrecognized opcode"; | |
7929 | return; | |
7930 | } | |
7931 | ||
7932 | /* Lookup the instruction in the hash table. */ | |
7933 | *s++ = '\0'; | |
7934 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7935 | { | |
7936 | insn_error = "unrecognized opcode"; | |
7937 | return; | |
7938 | } | |
252b5132 RH |
7939 | } |
7940 | ||
7941 | argsStart = s; | |
7942 | for (;;) | |
7943 | { | |
b34976b6 | 7944 | bfd_boolean ok; |
252b5132 RH |
7945 | |
7946 | assert (strcmp (insn->name, str) == 0); | |
7947 | ||
1f25f5d3 CD |
7948 | if (OPCODE_IS_MEMBER (insn, |
7949 | (mips_opts.isa | |
3396de36 | 7950 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7951 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7952 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7953 | mips_opts.arch)) |
b34976b6 | 7954 | ok = TRUE; |
bdaaa2e1 | 7955 | else |
b34976b6 | 7956 | ok = FALSE; |
bdaaa2e1 | 7957 | |
252b5132 RH |
7958 | if (insn->pinfo != INSN_MACRO) |
7959 | { | |
fef14a42 | 7960 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7961 | ok = FALSE; |
252b5132 RH |
7962 | } |
7963 | ||
7964 | if (! ok) | |
7965 | { | |
7966 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7967 | && strcmp (insn->name, insn[1].name) == 0) | |
7968 | { | |
7969 | ++insn; | |
7970 | continue; | |
7971 | } | |
252b5132 | 7972 | else |
beae10d5 | 7973 | { |
268f6bed L |
7974 | if (!insn_error) |
7975 | { | |
7976 | static char buf[100]; | |
fef14a42 TS |
7977 | sprintf (buf, |
7978 | _("opcode not supported on this processor: %s (%s)"), | |
7979 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7980 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7981 | insn_error = buf; |
7982 | } | |
7983 | if (save_c) | |
7984 | *(--s) = save_c; | |
2bd7f1f3 | 7985 | return; |
252b5132 | 7986 | } |
252b5132 RH |
7987 | } |
7988 | ||
7989 | ip->insn_mo = insn; | |
7990 | ip->insn_opcode = insn->match; | |
268f6bed | 7991 | insn_error = NULL; |
252b5132 RH |
7992 | for (args = insn->args;; ++args) |
7993 | { | |
deec1734 CD |
7994 | int is_mdmx; |
7995 | ||
ad8d3bb3 | 7996 | s += strspn (s, " \t"); |
deec1734 | 7997 | is_mdmx = 0; |
252b5132 RH |
7998 | switch (*args) |
7999 | { | |
8000 | case '\0': /* end of args */ | |
8001 | if (*s == '\0') | |
8002 | return; | |
8003 | break; | |
8004 | ||
8005 | case ',': | |
8006 | if (*s++ == *args) | |
8007 | continue; | |
8008 | s--; | |
8009 | switch (*++args) | |
8010 | { | |
8011 | case 'r': | |
8012 | case 'v': | |
38487616 | 8013 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8014 | continue; |
8015 | ||
8016 | case 'w': | |
38487616 TS |
8017 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8018 | continue; | |
8019 | ||
252b5132 | 8020 | case 'W': |
38487616 | 8021 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8022 | continue; |
8023 | ||
8024 | case 'V': | |
38487616 | 8025 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8026 | continue; |
8027 | } | |
8028 | break; | |
8029 | ||
8030 | case '(': | |
8031 | /* Handle optional base register. | |
8032 | Either the base register is omitted or | |
bdaaa2e1 | 8033 | we must have a left paren. */ |
252b5132 RH |
8034 | /* This is dependent on the next operand specifier |
8035 | is a base register specification. */ | |
8036 | assert (args[1] == 'b' || args[1] == '5' | |
8037 | || args[1] == '-' || args[1] == '4'); | |
8038 | if (*s == '\0') | |
8039 | return; | |
8040 | ||
8041 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8042 | case '[': |
8043 | case ']': | |
252b5132 RH |
8044 | if (*s++ == *args) |
8045 | continue; | |
8046 | break; | |
8047 | ||
af7ee8bf CD |
8048 | case '+': /* Opcode extension character. */ |
8049 | switch (*++args) | |
8050 | { | |
071742cf CD |
8051 | case 'A': /* ins/ext position, becomes LSB. */ |
8052 | limlo = 0; | |
8053 | limhi = 31; | |
5f74bc13 CD |
8054 | goto do_lsb; |
8055 | case 'E': | |
8056 | limlo = 32; | |
8057 | limhi = 63; | |
8058 | goto do_lsb; | |
8059 | do_lsb: | |
071742cf CD |
8060 | my_getExpression (&imm_expr, s); |
8061 | check_absolute_expr (ip, &imm_expr); | |
8062 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8063 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8064 | { | |
8065 | as_bad (_("Improper position (%lu)"), | |
8066 | (unsigned long) imm_expr.X_add_number); | |
8067 | imm_expr.X_add_number = limlo; | |
8068 | } | |
8069 | lastpos = imm_expr.X_add_number; | |
8070 | ip->insn_opcode |= (imm_expr.X_add_number | |
8071 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8072 | imm_expr.X_op = O_absent; | |
8073 | s = expr_end; | |
8074 | continue; | |
8075 | ||
8076 | case 'B': /* ins size, becomes MSB. */ | |
8077 | limlo = 1; | |
8078 | limhi = 32; | |
5f74bc13 CD |
8079 | goto do_msb; |
8080 | case 'F': | |
8081 | limlo = 33; | |
8082 | limhi = 64; | |
8083 | goto do_msb; | |
8084 | do_msb: | |
071742cf CD |
8085 | my_getExpression (&imm_expr, s); |
8086 | check_absolute_expr (ip, &imm_expr); | |
8087 | /* Check for negative input so that small negative numbers | |
8088 | will not succeed incorrectly. The checks against | |
8089 | (pos+size) transitively check "size" itself, | |
8090 | assuming that "pos" is reasonable. */ | |
8091 | if ((long) imm_expr.X_add_number < 0 | |
8092 | || ((unsigned long) imm_expr.X_add_number | |
8093 | + lastpos) < limlo | |
8094 | || ((unsigned long) imm_expr.X_add_number | |
8095 | + lastpos) > limhi) | |
8096 | { | |
8097 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8098 | (unsigned long) imm_expr.X_add_number, | |
8099 | (unsigned long) lastpos); | |
8100 | imm_expr.X_add_number = limlo - lastpos; | |
8101 | } | |
8102 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8103 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8104 | imm_expr.X_op = O_absent; | |
8105 | s = expr_end; | |
8106 | continue; | |
8107 | ||
8108 | case 'C': /* ext size, becomes MSBD. */ | |
8109 | limlo = 1; | |
8110 | limhi = 32; | |
5f74bc13 CD |
8111 | goto do_msbd; |
8112 | case 'G': | |
8113 | limlo = 33; | |
8114 | limhi = 64; | |
8115 | goto do_msbd; | |
8116 | case 'H': | |
8117 | limlo = 33; | |
8118 | limhi = 64; | |
8119 | goto do_msbd; | |
8120 | do_msbd: | |
071742cf CD |
8121 | my_getExpression (&imm_expr, s); |
8122 | check_absolute_expr (ip, &imm_expr); | |
8123 | /* Check for negative input so that small negative numbers | |
8124 | will not succeed incorrectly. The checks against | |
8125 | (pos+size) transitively check "size" itself, | |
8126 | assuming that "pos" is reasonable. */ | |
8127 | if ((long) imm_expr.X_add_number < 0 | |
8128 | || ((unsigned long) imm_expr.X_add_number | |
8129 | + lastpos) < limlo | |
8130 | || ((unsigned long) imm_expr.X_add_number | |
8131 | + lastpos) > limhi) | |
8132 | { | |
8133 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8134 | (unsigned long) imm_expr.X_add_number, | |
8135 | (unsigned long) lastpos); | |
8136 | imm_expr.X_add_number = limlo - lastpos; | |
8137 | } | |
8138 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8139 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8140 | imm_expr.X_op = O_absent; | |
8141 | s = expr_end; | |
8142 | continue; | |
af7ee8bf | 8143 | |
bbcc0807 CD |
8144 | case 'D': |
8145 | /* +D is for disassembly only; never match. */ | |
8146 | break; | |
8147 | ||
5f74bc13 CD |
8148 | case 'I': |
8149 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8150 | my_getExpression (&imm2_expr, s); | |
8151 | if (imm2_expr.X_op != O_big | |
8152 | && imm2_expr.X_op != O_constant) | |
8153 | insn_error = _("absolute expression required"); | |
13757d0c | 8154 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8155 | s = expr_end; |
8156 | continue; | |
8157 | ||
af7ee8bf CD |
8158 | default: |
8159 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8160 | *args, insn->name, insn->args); | |
8161 | /* Further processing is fruitless. */ | |
8162 | return; | |
8163 | } | |
8164 | break; | |
8165 | ||
252b5132 RH |
8166 | case '<': /* must be at least one digit */ |
8167 | /* | |
8168 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8169 | * than 31 or less than 0, then the shift amount should be |
8170 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8171 | * We issue a warning and mask out all but the low 5 bits. |
8172 | */ | |
8173 | my_getExpression (&imm_expr, s); | |
8174 | check_absolute_expr (ip, &imm_expr); | |
8175 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8176 | { | |
793b27f4 TS |
8177 | as_warn (_("Improper shift amount (%lu)"), |
8178 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8179 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8180 | } |
38487616 | 8181 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8182 | imm_expr.X_op = O_absent; |
8183 | s = expr_end; | |
8184 | continue; | |
8185 | ||
8186 | case '>': /* shift amount minus 32 */ | |
8187 | my_getExpression (&imm_expr, s); | |
8188 | check_absolute_expr (ip, &imm_expr); | |
8189 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8190 | || (unsigned long) imm_expr.X_add_number > 63) | |
8191 | break; | |
38487616 | 8192 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8193 | imm_expr.X_op = O_absent; |
8194 | s = expr_end; | |
8195 | continue; | |
8196 | ||
252b5132 RH |
8197 | case 'k': /* cache code */ |
8198 | case 'h': /* prefx code */ | |
8199 | my_getExpression (&imm_expr, s); | |
8200 | check_absolute_expr (ip, &imm_expr); | |
8201 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8202 | { | |
8203 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8204 | ip->insn_mo->name, | |
8205 | (unsigned long) imm_expr.X_add_number); | |
8206 | imm_expr.X_add_number &= 0x1f; | |
8207 | } | |
8208 | if (*args == 'k') | |
8209 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8210 | else | |
8211 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8212 | imm_expr.X_op = O_absent; | |
8213 | s = expr_end; | |
8214 | continue; | |
8215 | ||
8216 | case 'c': /* break code */ | |
8217 | my_getExpression (&imm_expr, s); | |
8218 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8219 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8220 | { |
793b27f4 TS |
8221 | as_warn (_("Illegal break code (%lu)"), |
8222 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8223 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8224 | } |
38487616 | 8225 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8226 | imm_expr.X_op = O_absent; |
8227 | s = expr_end; | |
8228 | continue; | |
8229 | ||
8230 | case 'q': /* lower break code */ | |
8231 | my_getExpression (&imm_expr, s); | |
8232 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8233 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8234 | { |
793b27f4 TS |
8235 | as_warn (_("Illegal lower break code (%lu)"), |
8236 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8237 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8238 | } |
38487616 | 8239 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8240 | imm_expr.X_op = O_absent; |
8241 | s = expr_end; | |
8242 | continue; | |
8243 | ||
4372b673 | 8244 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8245 | my_getExpression (&imm_expr, s); |
156c2f8b | 8246 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8247 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8248 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8249 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8250 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8251 | imm_expr.X_op = O_absent; |
8252 | s = expr_end; | |
8253 | continue; | |
8254 | ||
98d3f06f | 8255 | case 'C': /* Coprocessor code */ |
beae10d5 | 8256 | my_getExpression (&imm_expr, s); |
252b5132 | 8257 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8258 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8259 | { |
793b27f4 TS |
8260 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8261 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8262 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8263 | } |
beae10d5 KH |
8264 | ip->insn_opcode |= imm_expr.X_add_number; |
8265 | imm_expr.X_op = O_absent; | |
8266 | s = expr_end; | |
8267 | continue; | |
252b5132 | 8268 | |
4372b673 NC |
8269 | case 'J': /* 19-bit wait code. */ |
8270 | my_getExpression (&imm_expr, s); | |
8271 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8272 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8273 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8274 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8275 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8276 | imm_expr.X_op = O_absent; |
8277 | s = expr_end; | |
8278 | continue; | |
8279 | ||
252b5132 | 8280 | case 'P': /* Performance register */ |
beae10d5 | 8281 | my_getExpression (&imm_expr, s); |
252b5132 | 8282 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8283 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8284 | { |
793b27f4 TS |
8285 | as_warn (_("Invalid performance register (%lu)"), |
8286 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8287 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8288 | } |
38487616 | 8289 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8290 | imm_expr.X_op = O_absent; |
8291 | s = expr_end; | |
8292 | continue; | |
252b5132 RH |
8293 | |
8294 | case 'b': /* base register */ | |
8295 | case 'd': /* destination register */ | |
8296 | case 's': /* source register */ | |
8297 | case 't': /* target register */ | |
8298 | case 'r': /* both target and source */ | |
8299 | case 'v': /* both dest and source */ | |
8300 | case 'w': /* both dest and target */ | |
8301 | case 'E': /* coprocessor target register */ | |
8302 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8303 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8304 | case 'x': /* ignore register name */ |
8305 | case 'z': /* must be zero register */ | |
4372b673 | 8306 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8307 | s_reset = s; |
8308 | if (s[0] == '$') | |
8309 | { | |
8310 | ||
3882b010 | 8311 | if (ISDIGIT (s[1])) |
252b5132 RH |
8312 | { |
8313 | ++s; | |
8314 | regno = 0; | |
8315 | do | |
8316 | { | |
8317 | regno *= 10; | |
8318 | regno += *s - '0'; | |
8319 | ++s; | |
8320 | } | |
3882b010 | 8321 | while (ISDIGIT (*s)); |
252b5132 RH |
8322 | if (regno > 31) |
8323 | as_bad (_("Invalid register number (%d)"), regno); | |
8324 | } | |
af7ee8bf | 8325 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8326 | goto notreg; |
8327 | else | |
8328 | { | |
76db943d TS |
8329 | if (s[1] == 'r' && s[2] == 'a') |
8330 | { | |
8331 | s += 3; | |
8332 | regno = RA; | |
8333 | } | |
8334 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8335 | { |
8336 | s += 3; | |
8337 | regno = FP; | |
8338 | } | |
8339 | else if (s[1] == 's' && s[2] == 'p') | |
8340 | { | |
8341 | s += 3; | |
8342 | regno = SP; | |
8343 | } | |
8344 | else if (s[1] == 'g' && s[2] == 'p') | |
8345 | { | |
8346 | s += 3; | |
8347 | regno = GP; | |
8348 | } | |
8349 | else if (s[1] == 'a' && s[2] == 't') | |
8350 | { | |
8351 | s += 3; | |
8352 | regno = AT; | |
8353 | } | |
8354 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8355 | { | |
8356 | s += 4; | |
8357 | regno = KT0; | |
8358 | } | |
8359 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8360 | { | |
8361 | s += 4; | |
8362 | regno = KT1; | |
8363 | } | |
85b51719 TS |
8364 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8365 | { | |
8366 | s += 5; | |
8367 | regno = ZERO; | |
8368 | } | |
252b5132 RH |
8369 | else if (itbl_have_entries) |
8370 | { | |
8371 | char *p, *n; | |
d7ba4a77 | 8372 | unsigned long r; |
252b5132 | 8373 | |
d7ba4a77 | 8374 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8375 | n = itbl_get_field (&p); /* n is name */ |
8376 | ||
d7ba4a77 ILT |
8377 | /* See if this is a register defined in an |
8378 | itbl entry. */ | |
8379 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8380 | { |
8381 | /* Get_field advances to the start of | |
8382 | the next field, so we need to back | |
d7ba4a77 | 8383 | rack to the end of the last field. */ |
bdaaa2e1 | 8384 | if (p) |
252b5132 | 8385 | s = p - 1; |
bdaaa2e1 | 8386 | else |
d7ba4a77 | 8387 | s = strchr (s, '\0'); |
252b5132 RH |
8388 | regno = r; |
8389 | } | |
8390 | else | |
8391 | goto notreg; | |
beae10d5 | 8392 | } |
252b5132 RH |
8393 | else |
8394 | goto notreg; | |
8395 | } | |
8396 | if (regno == AT | |
8397 | && ! mips_opts.noat | |
8398 | && *args != 'E' | |
af7ee8bf CD |
8399 | && *args != 'G' |
8400 | && *args != 'K') | |
252b5132 RH |
8401 | as_warn (_("Used $at without \".set noat\"")); |
8402 | c = *args; | |
8403 | if (*s == ' ') | |
f9419b05 | 8404 | ++s; |
252b5132 RH |
8405 | if (args[1] != *s) |
8406 | { | |
8407 | if (c == 'r' || c == 'v' || c == 'w') | |
8408 | { | |
8409 | regno = lastregno; | |
8410 | s = s_reset; | |
f9419b05 | 8411 | ++args; |
252b5132 RH |
8412 | } |
8413 | } | |
8414 | /* 'z' only matches $0. */ | |
8415 | if (c == 'z' && regno != 0) | |
8416 | break; | |
8417 | ||
bdaaa2e1 KH |
8418 | /* Now that we have assembled one operand, we use the args string |
8419 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8420 | switch (c) |
8421 | { | |
8422 | case 'r': | |
8423 | case 's': | |
8424 | case 'v': | |
8425 | case 'b': | |
38487616 | 8426 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8427 | break; |
8428 | case 'd': | |
8429 | case 'G': | |
af7ee8bf | 8430 | case 'K': |
38487616 | 8431 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8432 | break; |
4372b673 | 8433 | case 'U': |
38487616 TS |
8434 | ip->insn_opcode |= regno << OP_SH_RD; |
8435 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8436 | break; |
252b5132 RH |
8437 | case 'w': |
8438 | case 't': | |
8439 | case 'E': | |
38487616 | 8440 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8441 | break; |
8442 | case 'x': | |
8443 | /* This case exists because on the r3000 trunc | |
8444 | expands into a macro which requires a gp | |
8445 | register. On the r6000 or r4000 it is | |
8446 | assembled into a single instruction which | |
8447 | ignores the register. Thus the insn version | |
8448 | is MIPS_ISA2 and uses 'x', and the macro | |
8449 | version is MIPS_ISA1 and uses 't'. */ | |
8450 | break; | |
8451 | case 'z': | |
8452 | /* This case is for the div instruction, which | |
8453 | acts differently if the destination argument | |
8454 | is $0. This only matches $0, and is checked | |
8455 | outside the switch. */ | |
8456 | break; | |
8457 | case 'D': | |
8458 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8459 | break; | |
8460 | /* What about all other operands like 'i', which | |
8461 | can be specified in the opcode table? */ | |
8462 | } | |
8463 | lastregno = regno; | |
8464 | continue; | |
8465 | } | |
8466 | notreg: | |
8467 | switch (*args++) | |
8468 | { | |
8469 | case 'r': | |
8470 | case 'v': | |
38487616 | 8471 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8472 | continue; |
8473 | case 'w': | |
38487616 | 8474 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8475 | continue; |
8476 | } | |
8477 | break; | |
8478 | ||
deec1734 CD |
8479 | case 'O': /* MDMX alignment immediate constant. */ |
8480 | my_getExpression (&imm_expr, s); | |
8481 | check_absolute_expr (ip, &imm_expr); | |
8482 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8483 | { | |
8484 | as_warn ("Improper align amount (%ld), using low bits", | |
8485 | (long) imm_expr.X_add_number); | |
8486 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8487 | } | |
8488 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8489 | imm_expr.X_op = O_absent; | |
8490 | s = expr_end; | |
8491 | continue; | |
8492 | ||
8493 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8494 | if (s[0] != '$') | |
8495 | { | |
8496 | /* MDMX Immediate. */ | |
8497 | my_getExpression (&imm_expr, s); | |
8498 | check_absolute_expr (ip, &imm_expr); | |
8499 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8500 | { | |
8501 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8502 | (long) imm_expr.X_add_number); | |
8503 | imm_expr.X_add_number &= OP_MASK_FT; | |
8504 | } | |
8505 | imm_expr.X_add_number &= OP_MASK_FT; | |
8506 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8507 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8508 | else | |
8509 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8510 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8511 | imm_expr.X_op = O_absent; | |
8512 | s = expr_end; | |
8513 | continue; | |
8514 | } | |
8515 | /* Not MDMX Immediate. Fall through. */ | |
8516 | case 'X': /* MDMX destination register. */ | |
8517 | case 'Y': /* MDMX source register. */ | |
8518 | case 'Z': /* MDMX target register. */ | |
8519 | is_mdmx = 1; | |
252b5132 RH |
8520 | case 'D': /* floating point destination register */ |
8521 | case 'S': /* floating point source register */ | |
8522 | case 'T': /* floating point target register */ | |
8523 | case 'R': /* floating point source register */ | |
8524 | case 'V': | |
8525 | case 'W': | |
8526 | s_reset = s; | |
deec1734 CD |
8527 | /* Accept $fN for FP and MDMX register numbers, and in |
8528 | addition accept $vN for MDMX register numbers. */ | |
8529 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8530 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8531 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8532 | { |
8533 | s += 2; | |
8534 | regno = 0; | |
8535 | do | |
8536 | { | |
8537 | regno *= 10; | |
8538 | regno += *s - '0'; | |
8539 | ++s; | |
8540 | } | |
3882b010 | 8541 | while (ISDIGIT (*s)); |
252b5132 RH |
8542 | |
8543 | if (regno > 31) | |
8544 | as_bad (_("Invalid float register number (%d)"), regno); | |
8545 | ||
8546 | if ((regno & 1) != 0 | |
ca4e0257 | 8547 | && HAVE_32BIT_FPRS |
252b5132 RH |
8548 | && ! (strcmp (str, "mtc1") == 0 |
8549 | || strcmp (str, "mfc1") == 0 | |
8550 | || strcmp (str, "lwc1") == 0 | |
8551 | || strcmp (str, "swc1") == 0 | |
8552 | || strcmp (str, "l.s") == 0 | |
8553 | || strcmp (str, "s.s") == 0)) | |
8554 | as_warn (_("Float register should be even, was %d"), | |
8555 | regno); | |
8556 | ||
8557 | c = *args; | |
8558 | if (*s == ' ') | |
f9419b05 | 8559 | ++s; |
252b5132 RH |
8560 | if (args[1] != *s) |
8561 | { | |
8562 | if (c == 'V' || c == 'W') | |
8563 | { | |
8564 | regno = lastregno; | |
8565 | s = s_reset; | |
f9419b05 | 8566 | ++args; |
252b5132 RH |
8567 | } |
8568 | } | |
8569 | switch (c) | |
8570 | { | |
8571 | case 'D': | |
deec1734 | 8572 | case 'X': |
38487616 | 8573 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8574 | break; |
8575 | case 'V': | |
8576 | case 'S': | |
deec1734 | 8577 | case 'Y': |
38487616 | 8578 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8579 | break; |
deec1734 CD |
8580 | case 'Q': |
8581 | /* This is like 'Z', but also needs to fix the MDMX | |
8582 | vector/scalar select bits. Note that the | |
8583 | scalar immediate case is handled above. */ | |
8584 | if (*s == '[') | |
8585 | { | |
8586 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8587 | int max_el = (is_qh ? 3 : 7); | |
8588 | s++; | |
8589 | my_getExpression(&imm_expr, s); | |
8590 | check_absolute_expr (ip, &imm_expr); | |
8591 | s = expr_end; | |
8592 | if (imm_expr.X_add_number > max_el) | |
8593 | as_bad(_("Bad element selector %ld"), | |
8594 | (long) imm_expr.X_add_number); | |
8595 | imm_expr.X_add_number &= max_el; | |
8596 | ip->insn_opcode |= (imm_expr.X_add_number | |
8597 | << (OP_SH_VSEL + | |
8598 | (is_qh ? 2 : 1))); | |
8599 | if (*s != ']') | |
8600 | as_warn(_("Expecting ']' found '%s'"), s); | |
8601 | else | |
8602 | s++; | |
8603 | } | |
8604 | else | |
8605 | { | |
8606 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8607 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8608 | << OP_SH_VSEL); | |
8609 | else | |
8610 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8611 | OP_SH_VSEL); | |
8612 | } | |
8613 | /* Fall through */ | |
252b5132 RH |
8614 | case 'W': |
8615 | case 'T': | |
deec1734 | 8616 | case 'Z': |
38487616 | 8617 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8618 | break; |
8619 | case 'R': | |
38487616 | 8620 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8621 | break; |
8622 | } | |
8623 | lastregno = regno; | |
8624 | continue; | |
8625 | } | |
8626 | ||
252b5132 RH |
8627 | switch (*args++) |
8628 | { | |
8629 | case 'V': | |
38487616 | 8630 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8631 | continue; |
8632 | case 'W': | |
38487616 | 8633 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8634 | continue; |
8635 | } | |
8636 | break; | |
8637 | ||
8638 | case 'I': | |
8639 | my_getExpression (&imm_expr, s); | |
8640 | if (imm_expr.X_op != O_big | |
8641 | && imm_expr.X_op != O_constant) | |
8642 | insn_error = _("absolute expression required"); | |
13757d0c | 8643 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8644 | s = expr_end; |
8645 | continue; | |
8646 | ||
8647 | case 'A': | |
8648 | my_getExpression (&offset_expr, s); | |
f6688943 | 8649 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8650 | s = expr_end; |
8651 | continue; | |
8652 | ||
8653 | case 'F': | |
8654 | case 'L': | |
8655 | case 'f': | |
8656 | case 'l': | |
8657 | { | |
8658 | int f64; | |
ca4e0257 | 8659 | int using_gprs; |
252b5132 RH |
8660 | char *save_in; |
8661 | char *err; | |
8662 | unsigned char temp[8]; | |
8663 | int len; | |
8664 | unsigned int length; | |
8665 | segT seg; | |
8666 | subsegT subseg; | |
8667 | char *p; | |
8668 | ||
8669 | /* These only appear as the last operand in an | |
8670 | instruction, and every instruction that accepts | |
8671 | them in any variant accepts them in all variants. | |
8672 | This means we don't have to worry about backing out | |
8673 | any changes if the instruction does not match. | |
8674 | ||
8675 | The difference between them is the size of the | |
8676 | floating point constant and where it goes. For 'F' | |
8677 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8678 | is 32 bits. Where the constant is placed is based | |
8679 | on how the MIPS assembler does things: | |
8680 | F -- .rdata | |
8681 | L -- .lit8 | |
8682 | f -- immediate value | |
8683 | l -- .lit4 | |
8684 | ||
8685 | The .lit4 and .lit8 sections are only used if | |
8686 | permitted by the -G argument. | |
8687 | ||
ca4e0257 RS |
8688 | The code below needs to know whether the target register |
8689 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8690 | 'F' are used with GPR-based instructions and 'l' and | |
8691 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8692 | |
8693 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8694 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8695 | |
8696 | save_in = input_line_pointer; | |
8697 | input_line_pointer = s; | |
8698 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8699 | length = len; | |
8700 | s = input_line_pointer; | |
8701 | input_line_pointer = save_in; | |
8702 | if (err != NULL && *err != '\0') | |
8703 | { | |
8704 | as_bad (_("Bad floating point constant: %s"), err); | |
8705 | memset (temp, '\0', sizeof temp); | |
8706 | length = f64 ? 8 : 4; | |
8707 | } | |
8708 | ||
156c2f8b | 8709 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8710 | |
8711 | if (*args == 'f' | |
8712 | || (*args == 'l' | |
3e722fb5 | 8713 | && (g_switch_value < 4 |
252b5132 RH |
8714 | || (temp[0] == 0 && temp[1] == 0) |
8715 | || (temp[2] == 0 && temp[3] == 0)))) | |
8716 | { | |
8717 | imm_expr.X_op = O_constant; | |
8718 | if (! target_big_endian) | |
8719 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8720 | else | |
8721 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8722 | } | |
8723 | else if (length > 4 | |
119d663a | 8724 | && ! mips_disable_float_construction |
ca4e0257 RS |
8725 | /* Constants can only be constructed in GPRs and |
8726 | copied to FPRs if the GPRs are at least as wide | |
8727 | as the FPRs. Force the constant into memory if | |
8728 | we are using 64-bit FPRs but the GPRs are only | |
8729 | 32 bits wide. */ | |
8730 | && (using_gprs | |
8731 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8732 | && ((temp[0] == 0 && temp[1] == 0) |
8733 | || (temp[2] == 0 && temp[3] == 0)) | |
8734 | && ((temp[4] == 0 && temp[5] == 0) | |
8735 | || (temp[6] == 0 && temp[7] == 0))) | |
8736 | { | |
ca4e0257 RS |
8737 | /* The value is simple enough to load with a couple of |
8738 | instructions. If using 32-bit registers, set | |
8739 | imm_expr to the high order 32 bits and offset_expr to | |
8740 | the low order 32 bits. Otherwise, set imm_expr to | |
8741 | the entire 64 bit constant. */ | |
8742 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8743 | { |
8744 | imm_expr.X_op = O_constant; | |
8745 | offset_expr.X_op = O_constant; | |
8746 | if (! target_big_endian) | |
8747 | { | |
8748 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8749 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8750 | } | |
8751 | else | |
8752 | { | |
8753 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8754 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8755 | } | |
8756 | if (offset_expr.X_add_number == 0) | |
8757 | offset_expr.X_op = O_absent; | |
8758 | } | |
8759 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8760 | { | |
8761 | imm_expr.X_op = O_constant; | |
8762 | if (! target_big_endian) | |
8763 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8764 | else | |
8765 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8766 | } | |
8767 | else | |
8768 | { | |
8769 | imm_expr.X_op = O_big; | |
8770 | imm_expr.X_add_number = 4; | |
8771 | if (! target_big_endian) | |
8772 | { | |
8773 | generic_bignum[0] = bfd_getl16 (temp); | |
8774 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8775 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8776 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8777 | } | |
8778 | else | |
8779 | { | |
8780 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8781 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8782 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8783 | generic_bignum[3] = bfd_getb16 (temp); | |
8784 | } | |
8785 | } | |
8786 | } | |
8787 | else | |
8788 | { | |
8789 | const char *newname; | |
8790 | segT new_seg; | |
8791 | ||
8792 | /* Switch to the right section. */ | |
8793 | seg = now_seg; | |
8794 | subseg = now_subseg; | |
8795 | switch (*args) | |
8796 | { | |
8797 | default: /* unused default case avoids warnings. */ | |
8798 | case 'L': | |
8799 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8800 | if (g_switch_value >= 8) |
252b5132 RH |
8801 | newname = ".lit8"; |
8802 | break; | |
8803 | case 'F': | |
3e722fb5 | 8804 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8805 | break; |
8806 | case 'l': | |
4d0d148d | 8807 | assert (g_switch_value >= 4); |
252b5132 RH |
8808 | newname = ".lit4"; |
8809 | break; | |
8810 | } | |
8811 | new_seg = subseg_new (newname, (subsegT) 0); | |
8812 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8813 | bfd_set_section_flags (stdoutput, new_seg, | |
8814 | (SEC_ALLOC | |
8815 | | SEC_LOAD | |
8816 | | SEC_READONLY | |
8817 | | SEC_DATA)); | |
8818 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8819 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8820 | && strcmp (TARGET_OS, "elf") != 0) | |
8821 | record_alignment (new_seg, 4); | |
8822 | else | |
8823 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8824 | if (seg == now_seg) | |
8825 | as_bad (_("Can't use floating point insn in this section")); | |
8826 | ||
8827 | /* Set the argument to the current address in the | |
8828 | section. */ | |
8829 | offset_expr.X_op = O_symbol; | |
8830 | offset_expr.X_add_symbol = | |
8831 | symbol_new ("L0\001", now_seg, | |
8832 | (valueT) frag_now_fix (), frag_now); | |
8833 | offset_expr.X_add_number = 0; | |
8834 | ||
8835 | /* Put the floating point number into the section. */ | |
8836 | p = frag_more ((int) length); | |
8837 | memcpy (p, temp, length); | |
8838 | ||
8839 | /* Switch back to the original section. */ | |
8840 | subseg_set (seg, subseg); | |
8841 | } | |
8842 | } | |
8843 | continue; | |
8844 | ||
8845 | case 'i': /* 16 bit unsigned immediate */ | |
8846 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8847 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8848 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8849 | { |
8850 | int more; | |
5e0116d5 RS |
8851 | offsetT minval, maxval; |
8852 | ||
8853 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8854 | && strcmp (insn->name, insn[1].name) == 0); | |
8855 | ||
8856 | /* If the expression was written as an unsigned number, | |
8857 | only treat it as signed if there are no more | |
8858 | alternatives. */ | |
8859 | if (more | |
8860 | && *args == 'j' | |
8861 | && sizeof (imm_expr.X_add_number) <= 4 | |
8862 | && imm_expr.X_op == O_constant | |
8863 | && imm_expr.X_add_number < 0 | |
8864 | && imm_expr.X_unsigned | |
8865 | && HAVE_64BIT_GPRS) | |
8866 | break; | |
8867 | ||
8868 | /* For compatibility with older assemblers, we accept | |
8869 | 0x8000-0xffff as signed 16-bit numbers when only | |
8870 | signed numbers are allowed. */ | |
8871 | if (*args == 'i') | |
8872 | minval = 0, maxval = 0xffff; | |
8873 | else if (more) | |
8874 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8875 | else |
5e0116d5 RS |
8876 | minval = -0x8000, maxval = 0xffff; |
8877 | ||
8878 | if (imm_expr.X_op != O_constant | |
8879 | || imm_expr.X_add_number < minval | |
8880 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8881 | { |
8882 | if (more) | |
8883 | break; | |
2ae7e77b AH |
8884 | if (imm_expr.X_op == O_constant |
8885 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8886 | as_bad (_("expression out of range")); |
252b5132 RH |
8887 | } |
8888 | } | |
8889 | s = expr_end; | |
8890 | continue; | |
8891 | ||
8892 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8893 | /* Check whether there is only a single bracketed expression |
8894 | left. If so, it must be the base register and the | |
8895 | constant must be zero. */ | |
8896 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8897 | { | |
8898 | offset_expr.X_op = O_constant; | |
8899 | offset_expr.X_add_number = 0; | |
8900 | continue; | |
8901 | } | |
252b5132 RH |
8902 | |
8903 | /* If this value won't fit into a 16 bit offset, then go | |
8904 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8905 | code pattern. */ |
5e0116d5 | 8906 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8907 | && (offset_expr.X_op != O_constant |
8908 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8909 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8910 | break; |
8911 | ||
252b5132 RH |
8912 | s = expr_end; |
8913 | continue; | |
8914 | ||
8915 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8916 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8917 | my_getExpression (&offset_expr, s); |
8918 | s = expr_end; | |
8919 | continue; | |
8920 | ||
8921 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8922 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8923 | && imm_expr.X_op == O_constant | |
8924 | && (imm_expr.X_add_number < 0 | |
8925 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8926 | as_bad (_("lui expression not in range 0..65535")); |
8927 | s = expr_end; | |
8928 | continue; | |
8929 | ||
8930 | case 'a': /* 26 bit address */ | |
8931 | my_getExpression (&offset_expr, s); | |
8932 | s = expr_end; | |
f6688943 | 8933 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8934 | continue; |
8935 | ||
8936 | case 'N': /* 3 bit branch condition code */ | |
8937 | case 'M': /* 3 bit compare condition code */ | |
8938 | if (strncmp (s, "$fcc", 4) != 0) | |
8939 | break; | |
8940 | s += 4; | |
8941 | regno = 0; | |
8942 | do | |
8943 | { | |
8944 | regno *= 10; | |
8945 | regno += *s - '0'; | |
8946 | ++s; | |
8947 | } | |
3882b010 | 8948 | while (ISDIGIT (*s)); |
252b5132 | 8949 | if (regno > 7) |
30c378fd CD |
8950 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8951 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8952 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8953 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8954 | && (regno & 1) != 0) | |
8955 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8956 | str, regno); | |
8957 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8958 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8959 | && (regno & 3) != 0) | |
8960 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8961 | str, regno); | |
252b5132 RH |
8962 | if (*args == 'N') |
8963 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8964 | else | |
8965 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8966 | continue; |
252b5132 | 8967 | |
156c2f8b NC |
8968 | case 'H': |
8969 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8970 | s += 2; | |
3882b010 | 8971 | if (ISDIGIT (*s)) |
156c2f8b NC |
8972 | { |
8973 | c = 0; | |
8974 | do | |
8975 | { | |
8976 | c *= 10; | |
8977 | c += *s - '0'; | |
8978 | ++s; | |
8979 | } | |
3882b010 | 8980 | while (ISDIGIT (*s)); |
156c2f8b NC |
8981 | } |
8982 | else | |
8983 | c = 8; /* Invalid sel value. */ | |
8984 | ||
8985 | if (c > 7) | |
8986 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8987 | ip->insn_opcode |= c; | |
8988 | continue; | |
8989 | ||
60b63b72 RS |
8990 | case 'e': |
8991 | /* Must be at least one digit. */ | |
8992 | my_getExpression (&imm_expr, s); | |
8993 | check_absolute_expr (ip, &imm_expr); | |
8994 | ||
8995 | if ((unsigned long) imm_expr.X_add_number | |
8996 | > (unsigned long) OP_MASK_VECBYTE) | |
8997 | { | |
8998 | as_bad (_("bad byte vector index (%ld)"), | |
8999 | (long) imm_expr.X_add_number); | |
9000 | imm_expr.X_add_number = 0; | |
9001 | } | |
9002 | ||
9003 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9004 | imm_expr.X_op = O_absent; | |
9005 | s = expr_end; | |
9006 | continue; | |
9007 | ||
9008 | case '%': | |
9009 | my_getExpression (&imm_expr, s); | |
9010 | check_absolute_expr (ip, &imm_expr); | |
9011 | ||
9012 | if ((unsigned long) imm_expr.X_add_number | |
9013 | > (unsigned long) OP_MASK_VECALIGN) | |
9014 | { | |
9015 | as_bad (_("bad byte vector index (%ld)"), | |
9016 | (long) imm_expr.X_add_number); | |
9017 | imm_expr.X_add_number = 0; | |
9018 | } | |
9019 | ||
9020 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9021 | imm_expr.X_op = O_absent; | |
9022 | s = expr_end; | |
9023 | continue; | |
9024 | ||
252b5132 RH |
9025 | default: |
9026 | as_bad (_("bad char = '%c'\n"), *args); | |
9027 | internalError (); | |
9028 | } | |
9029 | break; | |
9030 | } | |
9031 | /* Args don't match. */ | |
9032 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9033 | !strcmp (insn->name, insn[1].name)) | |
9034 | { | |
9035 | ++insn; | |
9036 | s = argsStart; | |
268f6bed | 9037 | insn_error = _("illegal operands"); |
252b5132 RH |
9038 | continue; |
9039 | } | |
268f6bed L |
9040 | if (save_c) |
9041 | *(--s) = save_c; | |
252b5132 RH |
9042 | insn_error = _("illegal operands"); |
9043 | return; | |
9044 | } | |
9045 | } | |
9046 | ||
9047 | /* This routine assembles an instruction into its binary format when | |
9048 | assembling for the mips16. As a side effect, it sets one of the | |
9049 | global variables imm_reloc or offset_reloc to the type of | |
9050 | relocation to do if one of the operands is an address expression. | |
9051 | It also sets mips16_small and mips16_ext if the user explicitly | |
9052 | requested a small or extended instruction. */ | |
9053 | ||
9054 | static void | |
17a2f251 | 9055 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9056 | { |
9057 | char *s; | |
9058 | const char *args; | |
9059 | struct mips_opcode *insn; | |
9060 | char *argsstart; | |
9061 | unsigned int regno; | |
9062 | unsigned int lastregno = 0; | |
9063 | char *s_reset; | |
9064 | ||
9065 | insn_error = NULL; | |
9066 | ||
b34976b6 AM |
9067 | mips16_small = FALSE; |
9068 | mips16_ext = FALSE; | |
252b5132 | 9069 | |
3882b010 | 9070 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9071 | ; |
9072 | switch (*s) | |
9073 | { | |
9074 | case '\0': | |
9075 | break; | |
9076 | ||
9077 | case ' ': | |
9078 | *s++ = '\0'; | |
9079 | break; | |
9080 | ||
9081 | case '.': | |
9082 | if (s[1] == 't' && s[2] == ' ') | |
9083 | { | |
9084 | *s = '\0'; | |
b34976b6 | 9085 | mips16_small = TRUE; |
252b5132 RH |
9086 | s += 3; |
9087 | break; | |
9088 | } | |
9089 | else if (s[1] == 'e' && s[2] == ' ') | |
9090 | { | |
9091 | *s = '\0'; | |
b34976b6 | 9092 | mips16_ext = TRUE; |
252b5132 RH |
9093 | s += 3; |
9094 | break; | |
9095 | } | |
9096 | /* Fall through. */ | |
9097 | default: | |
9098 | insn_error = _("unknown opcode"); | |
9099 | return; | |
9100 | } | |
9101 | ||
9102 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9103 | mips16_small = TRUE; |
252b5132 RH |
9104 | |
9105 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9106 | { | |
9107 | insn_error = _("unrecognized opcode"); | |
9108 | return; | |
9109 | } | |
9110 | ||
9111 | argsstart = s; | |
9112 | for (;;) | |
9113 | { | |
9114 | assert (strcmp (insn->name, str) == 0); | |
9115 | ||
9116 | ip->insn_mo = insn; | |
9117 | ip->insn_opcode = insn->match; | |
b34976b6 | 9118 | ip->use_extend = FALSE; |
252b5132 | 9119 | imm_expr.X_op = O_absent; |
f6688943 TS |
9120 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9121 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9122 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9123 | imm2_expr.X_op = O_absent; |
252b5132 | 9124 | offset_expr.X_op = O_absent; |
f6688943 TS |
9125 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9126 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9127 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9128 | for (args = insn->args; 1; ++args) |
9129 | { | |
9130 | int c; | |
9131 | ||
9132 | if (*s == ' ') | |
9133 | ++s; | |
9134 | ||
9135 | /* In this switch statement we call break if we did not find | |
9136 | a match, continue if we did find a match, or return if we | |
9137 | are done. */ | |
9138 | ||
9139 | c = *args; | |
9140 | switch (c) | |
9141 | { | |
9142 | case '\0': | |
9143 | if (*s == '\0') | |
9144 | { | |
9145 | /* Stuff the immediate value in now, if we can. */ | |
9146 | if (imm_expr.X_op == O_constant | |
f6688943 | 9147 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9148 | && insn->pinfo != INSN_MACRO) |
9149 | { | |
c4e7957c | 9150 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9151 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9152 | mips16_ext, &ip->insn_opcode, |
9153 | &ip->use_extend, &ip->extend); | |
9154 | imm_expr.X_op = O_absent; | |
f6688943 | 9155 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9156 | } |
9157 | ||
9158 | return; | |
9159 | } | |
9160 | break; | |
9161 | ||
9162 | case ',': | |
9163 | if (*s++ == c) | |
9164 | continue; | |
9165 | s--; | |
9166 | switch (*++args) | |
9167 | { | |
9168 | case 'v': | |
9169 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9170 | continue; | |
9171 | case 'w': | |
9172 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9173 | continue; | |
9174 | } | |
9175 | break; | |
9176 | ||
9177 | case '(': | |
9178 | case ')': | |
9179 | if (*s++ == c) | |
9180 | continue; | |
9181 | break; | |
9182 | ||
9183 | case 'v': | |
9184 | case 'w': | |
9185 | if (s[0] != '$') | |
9186 | { | |
9187 | if (c == 'v') | |
9188 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9189 | else | |
9190 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9191 | ++args; | |
9192 | continue; | |
9193 | } | |
9194 | /* Fall through. */ | |
9195 | case 'x': | |
9196 | case 'y': | |
9197 | case 'z': | |
9198 | case 'Z': | |
9199 | case '0': | |
9200 | case 'S': | |
9201 | case 'R': | |
9202 | case 'X': | |
9203 | case 'Y': | |
9204 | if (s[0] != '$') | |
9205 | break; | |
9206 | s_reset = s; | |
3882b010 | 9207 | if (ISDIGIT (s[1])) |
252b5132 RH |
9208 | { |
9209 | ++s; | |
9210 | regno = 0; | |
9211 | do | |
9212 | { | |
9213 | regno *= 10; | |
9214 | regno += *s - '0'; | |
9215 | ++s; | |
9216 | } | |
3882b010 | 9217 | while (ISDIGIT (*s)); |
252b5132 RH |
9218 | if (regno > 31) |
9219 | { | |
9220 | as_bad (_("invalid register number (%d)"), regno); | |
9221 | regno = 2; | |
9222 | } | |
9223 | } | |
9224 | else | |
9225 | { | |
76db943d TS |
9226 | if (s[1] == 'r' && s[2] == 'a') |
9227 | { | |
9228 | s += 3; | |
9229 | regno = RA; | |
9230 | } | |
9231 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9232 | { |
9233 | s += 3; | |
9234 | regno = FP; | |
9235 | } | |
9236 | else if (s[1] == 's' && s[2] == 'p') | |
9237 | { | |
9238 | s += 3; | |
9239 | regno = SP; | |
9240 | } | |
9241 | else if (s[1] == 'g' && s[2] == 'p') | |
9242 | { | |
9243 | s += 3; | |
9244 | regno = GP; | |
9245 | } | |
9246 | else if (s[1] == 'a' && s[2] == 't') | |
9247 | { | |
9248 | s += 3; | |
9249 | regno = AT; | |
9250 | } | |
9251 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9252 | { | |
9253 | s += 4; | |
9254 | regno = KT0; | |
9255 | } | |
9256 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9257 | { | |
9258 | s += 4; | |
9259 | regno = KT1; | |
9260 | } | |
85b51719 TS |
9261 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9262 | { | |
9263 | s += 5; | |
9264 | regno = ZERO; | |
9265 | } | |
252b5132 RH |
9266 | else |
9267 | break; | |
9268 | } | |
9269 | ||
9270 | if (*s == ' ') | |
9271 | ++s; | |
9272 | if (args[1] != *s) | |
9273 | { | |
9274 | if (c == 'v' || c == 'w') | |
9275 | { | |
9276 | regno = mips16_to_32_reg_map[lastregno]; | |
9277 | s = s_reset; | |
f9419b05 | 9278 | ++args; |
252b5132 RH |
9279 | } |
9280 | } | |
9281 | ||
9282 | switch (c) | |
9283 | { | |
9284 | case 'x': | |
9285 | case 'y': | |
9286 | case 'z': | |
9287 | case 'v': | |
9288 | case 'w': | |
9289 | case 'Z': | |
9290 | regno = mips32_to_16_reg_map[regno]; | |
9291 | break; | |
9292 | ||
9293 | case '0': | |
9294 | if (regno != 0) | |
9295 | regno = ILLEGAL_REG; | |
9296 | break; | |
9297 | ||
9298 | case 'S': | |
9299 | if (regno != SP) | |
9300 | regno = ILLEGAL_REG; | |
9301 | break; | |
9302 | ||
9303 | case 'R': | |
9304 | if (regno != RA) | |
9305 | regno = ILLEGAL_REG; | |
9306 | break; | |
9307 | ||
9308 | case 'X': | |
9309 | case 'Y': | |
9310 | if (regno == AT && ! mips_opts.noat) | |
9311 | as_warn (_("used $at without \".set noat\"")); | |
9312 | break; | |
9313 | ||
9314 | default: | |
9315 | internalError (); | |
9316 | } | |
9317 | ||
9318 | if (regno == ILLEGAL_REG) | |
9319 | break; | |
9320 | ||
9321 | switch (c) | |
9322 | { | |
9323 | case 'x': | |
9324 | case 'v': | |
9325 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9326 | break; | |
9327 | case 'y': | |
9328 | case 'w': | |
9329 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9330 | break; | |
9331 | case 'z': | |
9332 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9333 | break; | |
9334 | case 'Z': | |
9335 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9336 | case '0': | |
9337 | case 'S': | |
9338 | case 'R': | |
9339 | break; | |
9340 | case 'X': | |
9341 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9342 | break; | |
9343 | case 'Y': | |
9344 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9345 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9346 | break; | |
9347 | default: | |
9348 | internalError (); | |
9349 | } | |
9350 | ||
9351 | lastregno = regno; | |
9352 | continue; | |
9353 | ||
9354 | case 'P': | |
9355 | if (strncmp (s, "$pc", 3) == 0) | |
9356 | { | |
9357 | s += 3; | |
9358 | continue; | |
9359 | } | |
9360 | break; | |
9361 | ||
9362 | case '<': | |
9363 | case '>': | |
9364 | case '[': | |
9365 | case ']': | |
9366 | case '4': | |
9367 | case '5': | |
9368 | case 'H': | |
9369 | case 'W': | |
9370 | case 'D': | |
9371 | case 'j': | |
9372 | case '8': | |
9373 | case 'V': | |
9374 | case 'C': | |
9375 | case 'U': | |
9376 | case 'k': | |
9377 | case 'K': | |
9378 | if (s[0] == '%' | |
9379 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9380 | { | |
9381 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9382 | and generate the appropriate reloc. If the text | |
9383 | inside %gprel is not a symbol name with an | |
9384 | optional offset, then we generate a normal reloc | |
9385 | and will probably fail later. */ | |
9386 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9387 | if (imm_expr.X_op == O_symbol) | |
9388 | { | |
b34976b6 | 9389 | mips16_ext = TRUE; |
f6688943 | 9390 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9391 | s = expr_end; |
b34976b6 | 9392 | ip->use_extend = TRUE; |
252b5132 RH |
9393 | ip->extend = 0; |
9394 | continue; | |
9395 | } | |
9396 | } | |
9397 | else | |
9398 | { | |
9399 | /* Just pick up a normal expression. */ | |
9400 | my_getExpression (&imm_expr, s); | |
9401 | } | |
9402 | ||
9403 | if (imm_expr.X_op == O_register) | |
9404 | { | |
9405 | /* What we thought was an expression turned out to | |
9406 | be a register. */ | |
9407 | ||
9408 | if (s[0] == '(' && args[1] == '(') | |
9409 | { | |
9410 | /* It looks like the expression was omitted | |
9411 | before a register indirection, which means | |
9412 | that the expression is implicitly zero. We | |
9413 | still set up imm_expr, so that we handle | |
9414 | explicit extensions correctly. */ | |
9415 | imm_expr.X_op = O_constant; | |
9416 | imm_expr.X_add_number = 0; | |
f6688943 | 9417 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9418 | continue; |
9419 | } | |
9420 | ||
9421 | break; | |
9422 | } | |
9423 | ||
9424 | /* We need to relax this instruction. */ | |
f6688943 | 9425 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9426 | s = expr_end; |
9427 | continue; | |
9428 | ||
9429 | case 'p': | |
9430 | case 'q': | |
9431 | case 'A': | |
9432 | case 'B': | |
9433 | case 'E': | |
9434 | /* We use offset_reloc rather than imm_reloc for the PC | |
9435 | relative operands. This lets macros with both | |
9436 | immediate and address operands work correctly. */ | |
9437 | my_getExpression (&offset_expr, s); | |
9438 | ||
9439 | if (offset_expr.X_op == O_register) | |
9440 | break; | |
9441 | ||
9442 | /* We need to relax this instruction. */ | |
f6688943 | 9443 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9444 | s = expr_end; |
9445 | continue; | |
9446 | ||
9447 | case '6': /* break code */ | |
9448 | my_getExpression (&imm_expr, s); | |
9449 | check_absolute_expr (ip, &imm_expr); | |
9450 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9451 | { | |
9452 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9453 | ip->insn_mo->name, | |
9454 | (unsigned long) imm_expr.X_add_number); | |
9455 | imm_expr.X_add_number &= 0x3f; | |
9456 | } | |
9457 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9458 | imm_expr.X_op = O_absent; | |
9459 | s = expr_end; | |
9460 | continue; | |
9461 | ||
9462 | case 'a': /* 26 bit address */ | |
9463 | my_getExpression (&offset_expr, s); | |
9464 | s = expr_end; | |
f6688943 | 9465 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9466 | ip->insn_opcode <<= 16; |
9467 | continue; | |
9468 | ||
9469 | case 'l': /* register list for entry macro */ | |
9470 | case 'L': /* register list for exit macro */ | |
9471 | { | |
9472 | int mask; | |
9473 | ||
9474 | if (c == 'l') | |
9475 | mask = 0; | |
9476 | else | |
9477 | mask = 7 << 3; | |
9478 | while (*s != '\0') | |
9479 | { | |
9480 | int freg, reg1, reg2; | |
9481 | ||
9482 | while (*s == ' ' || *s == ',') | |
9483 | ++s; | |
9484 | if (*s != '$') | |
9485 | { | |
9486 | as_bad (_("can't parse register list")); | |
9487 | break; | |
9488 | } | |
9489 | ++s; | |
9490 | if (*s != 'f') | |
9491 | freg = 0; | |
9492 | else | |
9493 | { | |
9494 | freg = 1; | |
9495 | ++s; | |
9496 | } | |
9497 | reg1 = 0; | |
3882b010 | 9498 | while (ISDIGIT (*s)) |
252b5132 RH |
9499 | { |
9500 | reg1 *= 10; | |
9501 | reg1 += *s - '0'; | |
9502 | ++s; | |
9503 | } | |
9504 | if (*s == ' ') | |
9505 | ++s; | |
9506 | if (*s != '-') | |
9507 | reg2 = reg1; | |
9508 | else | |
9509 | { | |
9510 | ++s; | |
9511 | if (*s != '$') | |
9512 | break; | |
9513 | ++s; | |
9514 | if (freg) | |
9515 | { | |
9516 | if (*s == 'f') | |
9517 | ++s; | |
9518 | else | |
9519 | { | |
9520 | as_bad (_("invalid register list")); | |
9521 | break; | |
9522 | } | |
9523 | } | |
9524 | reg2 = 0; | |
3882b010 | 9525 | while (ISDIGIT (*s)) |
252b5132 RH |
9526 | { |
9527 | reg2 *= 10; | |
9528 | reg2 += *s - '0'; | |
9529 | ++s; | |
9530 | } | |
9531 | } | |
9532 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9533 | { | |
9534 | mask &= ~ (7 << 3); | |
9535 | mask |= 5 << 3; | |
9536 | } | |
9537 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9538 | { | |
9539 | mask &= ~ (7 << 3); | |
9540 | mask |= 6 << 3; | |
9541 | } | |
9542 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9543 | mask |= (reg2 - 3) << 3; | |
9544 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9545 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9546 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9547 | mask |= 1; |
9548 | else | |
9549 | { | |
9550 | as_bad (_("invalid register list")); | |
9551 | break; | |
9552 | } | |
9553 | } | |
9554 | /* The mask is filled in in the opcode table for the | |
9555 | benefit of the disassembler. We remove it before | |
9556 | applying the actual mask. */ | |
9557 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9558 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9559 | } | |
9560 | continue; | |
9561 | ||
9562 | case 'e': /* extend code */ | |
9563 | my_getExpression (&imm_expr, s); | |
9564 | check_absolute_expr (ip, &imm_expr); | |
9565 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9566 | { | |
9567 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9568 | ip->insn_mo->name, | |
9569 | (unsigned long) imm_expr.X_add_number); | |
9570 | imm_expr.X_add_number &= 0x7ff; | |
9571 | } | |
9572 | ip->insn_opcode |= imm_expr.X_add_number; | |
9573 | imm_expr.X_op = O_absent; | |
9574 | s = expr_end; | |
9575 | continue; | |
9576 | ||
9577 | default: | |
9578 | internalError (); | |
9579 | } | |
9580 | break; | |
9581 | } | |
9582 | ||
9583 | /* Args don't match. */ | |
9584 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9585 | strcmp (insn->name, insn[1].name) == 0) | |
9586 | { | |
9587 | ++insn; | |
9588 | s = argsstart; | |
9589 | continue; | |
9590 | } | |
9591 | ||
9592 | insn_error = _("illegal operands"); | |
9593 | ||
9594 | return; | |
9595 | } | |
9596 | } | |
9597 | ||
9598 | /* This structure holds information we know about a mips16 immediate | |
9599 | argument type. */ | |
9600 | ||
e972090a NC |
9601 | struct mips16_immed_operand |
9602 | { | |
252b5132 RH |
9603 | /* The type code used in the argument string in the opcode table. */ |
9604 | int type; | |
9605 | /* The number of bits in the short form of the opcode. */ | |
9606 | int nbits; | |
9607 | /* The number of bits in the extended form of the opcode. */ | |
9608 | int extbits; | |
9609 | /* The amount by which the short form is shifted when it is used; | |
9610 | for example, the sw instruction has a shift count of 2. */ | |
9611 | int shift; | |
9612 | /* The amount by which the short form is shifted when it is stored | |
9613 | into the instruction code. */ | |
9614 | int op_shift; | |
9615 | /* Non-zero if the short form is unsigned. */ | |
9616 | int unsp; | |
9617 | /* Non-zero if the extended form is unsigned. */ | |
9618 | int extu; | |
9619 | /* Non-zero if the value is PC relative. */ | |
9620 | int pcrel; | |
9621 | }; | |
9622 | ||
9623 | /* The mips16 immediate operand types. */ | |
9624 | ||
9625 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9626 | { | |
9627 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9628 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9629 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9630 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9631 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9632 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9633 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9634 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9635 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9636 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9637 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9638 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9639 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9640 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9641 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9642 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9643 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9644 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9645 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9646 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9647 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9648 | }; | |
9649 | ||
9650 | #define MIPS16_NUM_IMMED \ | |
9651 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9652 | ||
9653 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9654 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9655 | whether an extended value is needed; if one is needed, it sets | |
9656 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9657 | If SMALL is true, an unextended opcode was explicitly requested. | |
9658 | If EXT is true, an extended opcode was explicitly requested. If | |
9659 | WARN is true, warn if EXT does not match reality. */ | |
9660 | ||
9661 | static void | |
17a2f251 TS |
9662 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9663 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9664 | unsigned long *insn, bfd_boolean *use_extend, | |
9665 | unsigned short *extend) | |
252b5132 RH |
9666 | { |
9667 | register const struct mips16_immed_operand *op; | |
9668 | int mintiny, maxtiny; | |
b34976b6 | 9669 | bfd_boolean needext; |
252b5132 RH |
9670 | |
9671 | op = mips16_immed_operands; | |
9672 | while (op->type != type) | |
9673 | { | |
9674 | ++op; | |
9675 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9676 | } | |
9677 | ||
9678 | if (op->unsp) | |
9679 | { | |
9680 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9681 | { | |
9682 | mintiny = 1; | |
9683 | maxtiny = 1 << op->nbits; | |
9684 | } | |
9685 | else | |
9686 | { | |
9687 | mintiny = 0; | |
9688 | maxtiny = (1 << op->nbits) - 1; | |
9689 | } | |
9690 | } | |
9691 | else | |
9692 | { | |
9693 | mintiny = - (1 << (op->nbits - 1)); | |
9694 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9695 | } | |
9696 | ||
9697 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9698 | if (type == 'p' || type == 'q') | |
9699 | val /= 2; | |
9700 | ||
9701 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9702 | || val < (mintiny << op->shift) | |
9703 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9704 | needext = TRUE; |
252b5132 | 9705 | else |
b34976b6 | 9706 | needext = FALSE; |
252b5132 RH |
9707 | |
9708 | if (warn && ext && ! needext) | |
beae10d5 KH |
9709 | as_warn_where (file, line, |
9710 | _("extended operand requested but not required")); | |
252b5132 RH |
9711 | if (small && needext) |
9712 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9713 | ||
9714 | if (small || (! ext && ! needext)) | |
9715 | { | |
9716 | int insnval; | |
9717 | ||
b34976b6 | 9718 | *use_extend = FALSE; |
252b5132 RH |
9719 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9720 | insnval <<= op->op_shift; | |
9721 | *insn |= insnval; | |
9722 | } | |
9723 | else | |
9724 | { | |
9725 | long minext, maxext; | |
9726 | int extval; | |
9727 | ||
9728 | if (op->extu) | |
9729 | { | |
9730 | minext = 0; | |
9731 | maxext = (1 << op->extbits) - 1; | |
9732 | } | |
9733 | else | |
9734 | { | |
9735 | minext = - (1 << (op->extbits - 1)); | |
9736 | maxext = (1 << (op->extbits - 1)) - 1; | |
9737 | } | |
9738 | if (val < minext || val > maxext) | |
9739 | as_bad_where (file, line, | |
9740 | _("operand value out of range for instruction")); | |
9741 | ||
b34976b6 | 9742 | *use_extend = TRUE; |
252b5132 RH |
9743 | if (op->extbits == 16) |
9744 | { | |
9745 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9746 | val &= 0x1f; | |
9747 | } | |
9748 | else if (op->extbits == 15) | |
9749 | { | |
9750 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9751 | val &= 0xf; | |
9752 | } | |
9753 | else | |
9754 | { | |
9755 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9756 | val = 0; | |
9757 | } | |
9758 | ||
9759 | *extend = (unsigned short) extval; | |
9760 | *insn |= val; | |
9761 | } | |
9762 | } | |
9763 | \f | |
5e0116d5 | 9764 | static const struct percent_op_match |
ad8d3bb3 | 9765 | { |
5e0116d5 RS |
9766 | const char *str; |
9767 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9768 | } percent_op[] = |
9769 | { | |
5e0116d5 | 9770 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9771 | #ifdef OBJ_ELF |
5e0116d5 RS |
9772 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9773 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9774 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9775 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9776 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9777 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9778 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9779 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9780 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9781 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9782 | {"%half", BFD_RELOC_16}, | |
9783 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9784 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9785 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9786 | #endif |
5e0116d5 | 9787 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9788 | }; |
9789 | ||
252b5132 | 9790 | |
5e0116d5 RS |
9791 | /* Return true if *STR points to a relocation operator. When returning true, |
9792 | move *STR over the operator and store its relocation code in *RELOC. | |
9793 | Leave both *STR and *RELOC alone when returning false. */ | |
9794 | ||
9795 | static bfd_boolean | |
17a2f251 | 9796 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9797 | { |
5e0116d5 | 9798 | size_t i; |
76b3015f | 9799 | |
5e0116d5 RS |
9800 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
9801 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 9802 | { |
5e0116d5 RS |
9803 | *str += strlen (percent_op[i].str); |
9804 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9805 | |
5e0116d5 RS |
9806 | /* Check whether the output BFD supports this relocation. |
9807 | If not, issue an error and fall back on something safe. */ | |
9808 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9809 | { |
5e0116d5 RS |
9810 | as_bad ("relocation %s isn't supported by the current ABI", |
9811 | percent_op[i].str); | |
9812 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 9813 | } |
5e0116d5 | 9814 | return TRUE; |
394f9b3a | 9815 | } |
5e0116d5 | 9816 | return FALSE; |
394f9b3a | 9817 | } |
ad8d3bb3 | 9818 | |
ad8d3bb3 | 9819 | |
5e0116d5 RS |
9820 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9821 | expression in *EP and the relocations in the array starting | |
9822 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9823 | |
5e0116d5 RS |
9824 | On exit, EXPR_END points to the first character after the expression. |
9825 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 9826 | |
5e0116d5 | 9827 | static size_t |
17a2f251 TS |
9828 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9829 | char *str) | |
ad8d3bb3 | 9830 | { |
5e0116d5 RS |
9831 | bfd_reloc_code_real_type reversed_reloc[3]; |
9832 | size_t reloc_index, i; | |
09b8f35a RS |
9833 | int crux_depth, str_depth; |
9834 | char *crux; | |
5e0116d5 RS |
9835 | |
9836 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9837 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9838 | of the main expression and with CRUX_DEPTH containing the number | |
9839 | of open brackets at that point. */ | |
9840 | reloc_index = -1; | |
9841 | str_depth = 0; | |
9842 | do | |
fb1b3232 | 9843 | { |
09b8f35a RS |
9844 | reloc_index++; |
9845 | crux = str; | |
9846 | crux_depth = str_depth; | |
9847 | ||
9848 | /* Skip over whitespace and brackets, keeping count of the number | |
9849 | of brackets. */ | |
9850 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9851 | if (*str++ == '(') | |
9852 | str_depth++; | |
5e0116d5 | 9853 | } |
09b8f35a RS |
9854 | while (*str == '%' |
9855 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9856 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9857 | |
09b8f35a | 9858 | my_getExpression (ep, crux); |
5e0116d5 | 9859 | str = expr_end; |
394f9b3a | 9860 | |
5e0116d5 | 9861 | /* Match every open bracket. */ |
09b8f35a | 9862 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9863 | if (*str++ == ')') |
09b8f35a | 9864 | crux_depth--; |
394f9b3a | 9865 | |
09b8f35a | 9866 | if (crux_depth > 0) |
5e0116d5 | 9867 | as_bad ("unclosed '('"); |
394f9b3a | 9868 | |
5e0116d5 | 9869 | expr_end = str; |
252b5132 | 9870 | |
64bdfcaf RS |
9871 | if (reloc_index == 0) |
9872 | reloc[0] = BFD_RELOC_LO16; | |
9873 | else | |
9874 | { | |
9875 | prev_reloc_op_frag = frag_now; | |
9876 | for (i = 0; i < reloc_index; i++) | |
9877 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9878 | } | |
fb1b3232 | 9879 | |
5e0116d5 | 9880 | return reloc_index; |
252b5132 RH |
9881 | } |
9882 | ||
9883 | static void | |
17a2f251 | 9884 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9885 | { |
9886 | char *save_in; | |
98aa84af | 9887 | valueT val; |
252b5132 RH |
9888 | |
9889 | save_in = input_line_pointer; | |
9890 | input_line_pointer = str; | |
9891 | expression (ep); | |
9892 | expr_end = input_line_pointer; | |
9893 | input_line_pointer = save_in; | |
9894 | ||
9895 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9896 | then we bump the value of the symbol by 1 since that is how other | |
9897 | text symbols are handled. We don't bother to handle complex | |
9898 | expressions, just `.' plus or minus a constant. */ | |
9899 | if (mips_opts.mips16 | |
9900 | && ep->X_op == O_symbol | |
9901 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9902 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9903 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9904 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9905 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9906 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9907 | } |
9908 | ||
9909 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9910 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9911 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9912 | returned, or NULL on OK. */ |
9913 | ||
9914 | char * | |
17a2f251 | 9915 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9916 | { |
9917 | int prec; | |
9918 | LITTLENUM_TYPE words[4]; | |
9919 | char *t; | |
9920 | int i; | |
9921 | ||
9922 | switch (type) | |
9923 | { | |
9924 | case 'f': | |
9925 | prec = 2; | |
9926 | break; | |
9927 | ||
9928 | case 'd': | |
9929 | prec = 4; | |
9930 | break; | |
9931 | ||
9932 | default: | |
9933 | *sizeP = 0; | |
9934 | return _("bad call to md_atof"); | |
9935 | } | |
9936 | ||
9937 | t = atof_ieee (input_line_pointer, type, words); | |
9938 | if (t) | |
9939 | input_line_pointer = t; | |
9940 | ||
9941 | *sizeP = prec * 2; | |
9942 | ||
9943 | if (! target_big_endian) | |
9944 | { | |
9945 | for (i = prec - 1; i >= 0; i--) | |
9946 | { | |
17a2f251 | 9947 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9948 | litP += 2; |
9949 | } | |
9950 | } | |
9951 | else | |
9952 | { | |
9953 | for (i = 0; i < prec; i++) | |
9954 | { | |
17a2f251 | 9955 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9956 | litP += 2; |
9957 | } | |
9958 | } | |
bdaaa2e1 | 9959 | |
252b5132 RH |
9960 | return NULL; |
9961 | } | |
9962 | ||
9963 | void | |
17a2f251 | 9964 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9965 | { |
9966 | if (target_big_endian) | |
9967 | number_to_chars_bigendian (buf, val, n); | |
9968 | else | |
9969 | number_to_chars_littleendian (buf, val, n); | |
9970 | } | |
9971 | \f | |
ae948b86 | 9972 | #ifdef OBJ_ELF |
e013f690 TS |
9973 | static int support_64bit_objects(void) |
9974 | { | |
9975 | const char **list, **l; | |
aa3d8fdf | 9976 | int yes; |
e013f690 TS |
9977 | |
9978 | list = bfd_target_list (); | |
9979 | for (l = list; *l != NULL; l++) | |
9980 | #ifdef TE_TMIPS | |
9981 | /* This is traditional mips */ | |
9982 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9983 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9984 | #else | |
9985 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9986 | || strcmp (*l, "elf64-littlemips") == 0) | |
9987 | #endif | |
9988 | break; | |
aa3d8fdf | 9989 | yes = (*l != NULL); |
e013f690 | 9990 | free (list); |
aa3d8fdf | 9991 | return yes; |
e013f690 | 9992 | } |
ae948b86 | 9993 | #endif /* OBJ_ELF */ |
e013f690 | 9994 | |
78849248 | 9995 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 9996 | |
e972090a NC |
9997 | struct option md_longopts[] = |
9998 | { | |
f9b4148d CD |
9999 | /* Options which specify architecture. */ |
10000 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10001 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10002 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10003 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10004 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10005 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10006 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10007 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10008 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10009 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10010 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10011 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10012 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10013 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10014 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10015 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10016 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10017 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10018 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10019 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10020 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10021 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10022 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10023 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10024 | |
10025 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10026 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10027 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10028 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10029 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10030 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10031 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10032 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10033 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10034 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10035 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10036 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10037 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10038 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10039 | ||
10040 | /* Old-style architecture options. Don't add more of these. */ | |
10041 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10042 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10043 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10044 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10045 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10046 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10047 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10048 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10049 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10050 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10051 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10052 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10053 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10054 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10055 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10056 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10057 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10058 | ||
10059 | /* Options which enable bug fixes. */ | |
10060 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10061 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10062 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10063 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10064 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10065 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10066 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10067 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10068 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10069 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10070 | |
10071 | /* Miscellaneous options. */ | |
10072 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10073 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10074 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10075 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10076 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10077 | {"break", no_argument, NULL, OPTION_BREAK}, |
10078 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10079 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10080 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10081 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10082 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10083 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10084 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10085 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10086 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10087 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10088 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10089 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10090 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10091 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10092 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10093 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10094 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10095 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10096 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10097 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10098 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10099 | |
10100 | /* ELF-specific options. */ | |
156c2f8b | 10101 | #ifdef OBJ_ELF |
1ffcab4b | 10102 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12) |
156c2f8b | 10103 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10104 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10105 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10106 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10107 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10108 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10109 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10110 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10111 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10112 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10113 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10114 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10115 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10116 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10117 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10118 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10119 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10120 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10121 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10122 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10123 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10124 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10125 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10126 | #endif /* OBJ_ELF */ |
f9b4148d | 10127 | |
252b5132 RH |
10128 | {NULL, no_argument, NULL, 0} |
10129 | }; | |
156c2f8b | 10130 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10131 | |
316f5878 RS |
10132 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10133 | NEW_VALUE. Warn if another value was already specified. Note: | |
10134 | we have to defer parsing the -march and -mtune arguments in order | |
10135 | to handle 'from-abi' correctly, since the ABI might be specified | |
10136 | in a later argument. */ | |
10137 | ||
10138 | static void | |
17a2f251 | 10139 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10140 | { |
10141 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10142 | as_warn (_("A different %s was already specified, is now %s"), | |
10143 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10144 | new_value); | |
10145 | ||
10146 | *string_ptr = new_value; | |
10147 | } | |
10148 | ||
252b5132 | 10149 | int |
17a2f251 | 10150 | md_parse_option (int c, char *arg) |
252b5132 RH |
10151 | { |
10152 | switch (c) | |
10153 | { | |
119d663a NC |
10154 | case OPTION_CONSTRUCT_FLOATS: |
10155 | mips_disable_float_construction = 0; | |
10156 | break; | |
bdaaa2e1 | 10157 | |
119d663a NC |
10158 | case OPTION_NO_CONSTRUCT_FLOATS: |
10159 | mips_disable_float_construction = 1; | |
10160 | break; | |
bdaaa2e1 | 10161 | |
252b5132 RH |
10162 | case OPTION_TRAP: |
10163 | mips_trap = 1; | |
10164 | break; | |
10165 | ||
10166 | case OPTION_BREAK: | |
10167 | mips_trap = 0; | |
10168 | break; | |
10169 | ||
10170 | case OPTION_EB: | |
10171 | target_big_endian = 1; | |
10172 | break; | |
10173 | ||
10174 | case OPTION_EL: | |
10175 | target_big_endian = 0; | |
10176 | break; | |
10177 | ||
10178 | case 'O': | |
10179 | if (arg && arg[1] == '0') | |
10180 | mips_optimize = 1; | |
10181 | else | |
10182 | mips_optimize = 2; | |
10183 | break; | |
10184 | ||
10185 | case 'g': | |
10186 | if (arg == NULL) | |
10187 | mips_debug = 2; | |
10188 | else | |
10189 | mips_debug = atoi (arg); | |
10190 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10191 | optimizations which limit full symbolic debugging. We take | |
10192 | that to be equivalent to -O0. */ | |
10193 | if (mips_debug == 2) | |
10194 | mips_optimize = 1; | |
10195 | break; | |
10196 | ||
10197 | case OPTION_MIPS1: | |
316f5878 | 10198 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10199 | break; |
10200 | ||
10201 | case OPTION_MIPS2: | |
316f5878 | 10202 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10203 | break; |
10204 | ||
10205 | case OPTION_MIPS3: | |
316f5878 | 10206 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10207 | break; |
10208 | ||
10209 | case OPTION_MIPS4: | |
316f5878 | 10210 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10211 | break; |
10212 | ||
84ea6cf2 | 10213 | case OPTION_MIPS5: |
316f5878 | 10214 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10215 | break; |
10216 | ||
e7af610e | 10217 | case OPTION_MIPS32: |
316f5878 | 10218 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10219 | break; |
10220 | ||
af7ee8bf CD |
10221 | case OPTION_MIPS32R2: |
10222 | file_mips_isa = ISA_MIPS32R2; | |
10223 | break; | |
10224 | ||
5f74bc13 CD |
10225 | case OPTION_MIPS64R2: |
10226 | file_mips_isa = ISA_MIPS64R2; | |
10227 | break; | |
10228 | ||
84ea6cf2 | 10229 | case OPTION_MIPS64: |
316f5878 | 10230 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10231 | break; |
10232 | ||
ec68c924 | 10233 | case OPTION_MTUNE: |
316f5878 RS |
10234 | mips_set_option_string (&mips_tune_string, arg); |
10235 | break; | |
ec68c924 | 10236 | |
316f5878 RS |
10237 | case OPTION_MARCH: |
10238 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10239 | break; |
10240 | ||
10241 | case OPTION_M4650: | |
316f5878 RS |
10242 | mips_set_option_string (&mips_arch_string, "4650"); |
10243 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10244 | break; |
10245 | ||
10246 | case OPTION_NO_M4650: | |
10247 | break; | |
10248 | ||
10249 | case OPTION_M4010: | |
316f5878 RS |
10250 | mips_set_option_string (&mips_arch_string, "4010"); |
10251 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10252 | break; |
10253 | ||
10254 | case OPTION_NO_M4010: | |
10255 | break; | |
10256 | ||
10257 | case OPTION_M4100: | |
316f5878 RS |
10258 | mips_set_option_string (&mips_arch_string, "4100"); |
10259 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10260 | break; |
10261 | ||
10262 | case OPTION_NO_M4100: | |
10263 | break; | |
10264 | ||
252b5132 | 10265 | case OPTION_M3900: |
316f5878 RS |
10266 | mips_set_option_string (&mips_arch_string, "3900"); |
10267 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10268 | break; |
bdaaa2e1 | 10269 | |
252b5132 RH |
10270 | case OPTION_NO_M3900: |
10271 | break; | |
10272 | ||
deec1734 CD |
10273 | case OPTION_MDMX: |
10274 | mips_opts.ase_mdmx = 1; | |
10275 | break; | |
10276 | ||
10277 | case OPTION_NO_MDMX: | |
10278 | mips_opts.ase_mdmx = 0; | |
10279 | break; | |
10280 | ||
252b5132 RH |
10281 | case OPTION_MIPS16: |
10282 | mips_opts.mips16 = 1; | |
b34976b6 | 10283 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10284 | break; |
10285 | ||
10286 | case OPTION_NO_MIPS16: | |
10287 | mips_opts.mips16 = 0; | |
b34976b6 | 10288 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10289 | break; |
10290 | ||
1f25f5d3 CD |
10291 | case OPTION_MIPS3D: |
10292 | mips_opts.ase_mips3d = 1; | |
10293 | break; | |
10294 | ||
10295 | case OPTION_NO_MIPS3D: | |
10296 | mips_opts.ase_mips3d = 0; | |
10297 | break; | |
10298 | ||
d766e8ec RS |
10299 | case OPTION_FIX_VR4120: |
10300 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10301 | break; |
10302 | ||
d766e8ec RS |
10303 | case OPTION_NO_FIX_VR4120: |
10304 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10305 | break; |
10306 | ||
4a6a3df4 AO |
10307 | case OPTION_RELAX_BRANCH: |
10308 | mips_relax_branch = 1; | |
10309 | break; | |
10310 | ||
10311 | case OPTION_NO_RELAX_BRANCH: | |
10312 | mips_relax_branch = 0; | |
10313 | break; | |
10314 | ||
0f074f60 | 10315 | #ifdef OBJ_ELF |
252b5132 RH |
10316 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10317 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10318 | intended to be compatible with Irix 5. */ | |
10319 | case OPTION_CALL_SHARED: | |
10320 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10321 | { | |
10322 | as_bad (_("-call_shared is supported only for ELF format")); | |
10323 | return 0; | |
10324 | } | |
10325 | mips_pic = SVR4_PIC; | |
143d77c5 | 10326 | mips_abicalls = TRUE; |
252b5132 RH |
10327 | if (g_switch_seen && g_switch_value != 0) |
10328 | { | |
10329 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10330 | return 0; | |
10331 | } | |
10332 | g_switch_value = 0; | |
10333 | break; | |
10334 | ||
10335 | case OPTION_NON_SHARED: | |
10336 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10337 | { | |
10338 | as_bad (_("-non_shared is supported only for ELF format")); | |
10339 | return 0; | |
10340 | } | |
10341 | mips_pic = NO_PIC; | |
143d77c5 | 10342 | mips_abicalls = FALSE; |
252b5132 RH |
10343 | break; |
10344 | ||
10345 | /* The -xgot option tells the assembler to use 32 offsets when | |
10346 | accessing the got in SVR4_PIC mode. It is for Irix | |
10347 | compatibility. */ | |
10348 | case OPTION_XGOT: | |
10349 | mips_big_got = 1; | |
10350 | break; | |
0f074f60 | 10351 | #endif /* OBJ_ELF */ |
252b5132 RH |
10352 | |
10353 | case 'G': | |
3e722fb5 | 10354 | if (mips_pic == SVR4_PIC) |
252b5132 | 10355 | { |
3e722fb5 | 10356 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10357 | return 0; |
10358 | } | |
10359 | else | |
10360 | g_switch_value = atoi (arg); | |
10361 | g_switch_seen = 1; | |
10362 | break; | |
10363 | ||
0f074f60 | 10364 | #ifdef OBJ_ELF |
34ba82a8 TS |
10365 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10366 | and -mabi=64. */ | |
252b5132 | 10367 | case OPTION_32: |
34ba82a8 TS |
10368 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10369 | { | |
10370 | as_bad (_("-32 is supported for ELF format only")); | |
10371 | return 0; | |
10372 | } | |
316f5878 | 10373 | mips_abi = O32_ABI; |
252b5132 RH |
10374 | break; |
10375 | ||
e013f690 | 10376 | case OPTION_N32: |
34ba82a8 TS |
10377 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10378 | { | |
10379 | as_bad (_("-n32 is supported for ELF format only")); | |
10380 | return 0; | |
10381 | } | |
316f5878 | 10382 | mips_abi = N32_ABI; |
e013f690 | 10383 | break; |
252b5132 | 10384 | |
e013f690 | 10385 | case OPTION_64: |
34ba82a8 TS |
10386 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10387 | { | |
10388 | as_bad (_("-64 is supported for ELF format only")); | |
10389 | return 0; | |
10390 | } | |
316f5878 | 10391 | mips_abi = N64_ABI; |
e013f690 TS |
10392 | if (! support_64bit_objects()) |
10393 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10394 | break; |
ae948b86 | 10395 | #endif /* OBJ_ELF */ |
252b5132 | 10396 | |
c97ef257 | 10397 | case OPTION_GP32: |
a325df1d | 10398 | file_mips_gp32 = 1; |
c97ef257 AH |
10399 | break; |
10400 | ||
10401 | case OPTION_GP64: | |
a325df1d | 10402 | file_mips_gp32 = 0; |
c97ef257 | 10403 | break; |
252b5132 | 10404 | |
ca4e0257 | 10405 | case OPTION_FP32: |
a325df1d | 10406 | file_mips_fp32 = 1; |
316f5878 RS |
10407 | break; |
10408 | ||
10409 | case OPTION_FP64: | |
10410 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10411 | break; |
10412 | ||
ae948b86 | 10413 | #ifdef OBJ_ELF |
252b5132 | 10414 | case OPTION_MABI: |
34ba82a8 TS |
10415 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10416 | { | |
10417 | as_bad (_("-mabi is supported for ELF format only")); | |
10418 | return 0; | |
10419 | } | |
e013f690 | 10420 | if (strcmp (arg, "32") == 0) |
316f5878 | 10421 | mips_abi = O32_ABI; |
e013f690 | 10422 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10423 | mips_abi = O64_ABI; |
e013f690 | 10424 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10425 | mips_abi = N32_ABI; |
e013f690 TS |
10426 | else if (strcmp (arg, "64") == 0) |
10427 | { | |
316f5878 | 10428 | mips_abi = N64_ABI; |
e013f690 TS |
10429 | if (! support_64bit_objects()) |
10430 | as_fatal (_("No compiled in support for 64 bit object file " | |
10431 | "format")); | |
10432 | } | |
10433 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10434 | mips_abi = EABI_ABI; |
e013f690 | 10435 | else |
da0e507f TS |
10436 | { |
10437 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10438 | return 0; | |
10439 | } | |
252b5132 | 10440 | break; |
e013f690 | 10441 | #endif /* OBJ_ELF */ |
252b5132 | 10442 | |
6b76fefe | 10443 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10444 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10445 | break; |
10446 | ||
9ee72ff1 | 10447 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10448 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10449 | break; |
10450 | ||
ecb4347a DJ |
10451 | #ifdef OBJ_ELF |
10452 | case OPTION_MDEBUG: | |
b34976b6 | 10453 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10454 | break; |
10455 | ||
10456 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10457 | mips_flag_mdebug = FALSE; |
ecb4347a | 10458 | break; |
dcd410fe RO |
10459 | |
10460 | case OPTION_PDR: | |
10461 | mips_flag_pdr = TRUE; | |
10462 | break; | |
10463 | ||
10464 | case OPTION_NO_PDR: | |
10465 | mips_flag_pdr = FALSE; | |
10466 | break; | |
ecb4347a DJ |
10467 | #endif /* OBJ_ELF */ |
10468 | ||
252b5132 RH |
10469 | default: |
10470 | return 0; | |
10471 | } | |
10472 | ||
10473 | return 1; | |
10474 | } | |
316f5878 RS |
10475 | \f |
10476 | /* Set up globals to generate code for the ISA or processor | |
10477 | described by INFO. */ | |
252b5132 | 10478 | |
252b5132 | 10479 | static void |
17a2f251 | 10480 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10481 | { |
316f5878 | 10482 | if (info != 0) |
252b5132 | 10483 | { |
fef14a42 TS |
10484 | file_mips_arch = info->cpu; |
10485 | mips_opts.arch = info->cpu; | |
316f5878 | 10486 | mips_opts.isa = info->isa; |
252b5132 | 10487 | } |
252b5132 RH |
10488 | } |
10489 | ||
252b5132 | 10490 | |
316f5878 | 10491 | /* Likewise for tuning. */ |
252b5132 | 10492 | |
316f5878 | 10493 | static void |
17a2f251 | 10494 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10495 | { |
10496 | if (info != 0) | |
fef14a42 | 10497 | mips_tune = info->cpu; |
316f5878 | 10498 | } |
80cc45a5 | 10499 | |
34ba82a8 | 10500 | |
252b5132 | 10501 | void |
17a2f251 | 10502 | mips_after_parse_args (void) |
e9670677 | 10503 | { |
fef14a42 TS |
10504 | const struct mips_cpu_info *arch_info = 0; |
10505 | const struct mips_cpu_info *tune_info = 0; | |
10506 | ||
e9670677 MR |
10507 | /* GP relative stuff not working for PE */ |
10508 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10509 | && g_switch_value != 0) | |
10510 | { | |
10511 | if (g_switch_seen) | |
10512 | as_bad (_("-G not supported in this configuration.")); | |
10513 | g_switch_value = 0; | |
10514 | } | |
10515 | ||
cac012d6 AO |
10516 | if (mips_abi == NO_ABI) |
10517 | mips_abi = MIPS_DEFAULT_ABI; | |
10518 | ||
22923709 RS |
10519 | /* The following code determines the architecture and register size. |
10520 | Similar code was added to GCC 3.3 (see override_options() in | |
10521 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10522 | as much as possible. */ | |
e9670677 | 10523 | |
316f5878 | 10524 | if (mips_arch_string != 0) |
fef14a42 | 10525 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10526 | |
316f5878 | 10527 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10528 | { |
316f5878 | 10529 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10530 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10531 | the -march selection (if any). */ |
fef14a42 | 10532 | if (arch_info != 0) |
e9670677 | 10533 | { |
316f5878 RS |
10534 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10535 | There's no harm in specifying both as long as the ISA levels | |
10536 | are the same. */ | |
fef14a42 | 10537 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10538 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10539 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10540 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10541 | } |
316f5878 | 10542 | else |
fef14a42 | 10543 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10544 | } |
10545 | ||
fef14a42 TS |
10546 | if (arch_info == 0) |
10547 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10548 | |
fef14a42 | 10549 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10550 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10551 | arch_info->name); |
10552 | ||
10553 | mips_set_architecture (arch_info); | |
10554 | ||
10555 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10556 | if (mips_tune_string != 0) | |
10557 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10558 | |
fef14a42 TS |
10559 | if (tune_info == 0) |
10560 | mips_set_tune (arch_info); | |
10561 | else | |
10562 | mips_set_tune (tune_info); | |
e9670677 | 10563 | |
316f5878 | 10564 | if (file_mips_gp32 >= 0) |
e9670677 | 10565 | { |
316f5878 RS |
10566 | /* The user specified the size of the integer registers. Make sure |
10567 | it agrees with the ABI and ISA. */ | |
10568 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10569 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10570 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10571 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10572 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10573 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10574 | } |
10575 | else | |
10576 | { | |
316f5878 RS |
10577 | /* Infer the integer register size from the ABI and processor. |
10578 | Restrict ourselves to 32-bit registers if that's all the | |
10579 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10580 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10581 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10582 | } |
10583 | ||
316f5878 RS |
10584 | /* ??? GAS treats single-float processors as though they had 64-bit |
10585 | float registers (although it complains when double-precision | |
10586 | instructions are used). As things stand, saying they have 32-bit | |
10587 | registers would lead to spurious "register must be even" messages. | |
10588 | So here we assume float registers are always the same size as | |
10589 | integer ones, unless the user says otherwise. */ | |
10590 | if (file_mips_fp32 < 0) | |
10591 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10592 | |
316f5878 | 10593 | /* End of GCC-shared inference code. */ |
e9670677 | 10594 | |
17a2f251 TS |
10595 | /* This flag is set when we have a 64-bit capable CPU but use only |
10596 | 32-bit wide registers. Note that EABI does not use it. */ | |
10597 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10598 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10599 | || mips_abi == O32_ABI)) | |
316f5878 | 10600 | mips_32bitmode = 1; |
e9670677 MR |
10601 | |
10602 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10603 | as_bad (_("trap exception not supported at ISA 1")); | |
10604 | ||
e9670677 MR |
10605 | /* If the selected architecture includes support for ASEs, enable |
10606 | generation of code for them. */ | |
a4672219 | 10607 | if (mips_opts.mips16 == -1) |
fef14a42 | 10608 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10609 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10610 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10611 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10612 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10613 | |
e9670677 | 10614 | file_mips_isa = mips_opts.isa; |
a4672219 | 10615 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10616 | file_ase_mips3d = mips_opts.ase_mips3d; |
10617 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10618 | mips_opts.gp32 = file_mips_gp32; | |
10619 | mips_opts.fp32 = file_mips_fp32; | |
10620 | ||
ecb4347a DJ |
10621 | if (mips_flag_mdebug < 0) |
10622 | { | |
10623 | #ifdef OBJ_MAYBE_ECOFF | |
10624 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10625 | mips_flag_mdebug = 1; | |
10626 | else | |
10627 | #endif /* OBJ_MAYBE_ECOFF */ | |
10628 | mips_flag_mdebug = 0; | |
10629 | } | |
e9670677 MR |
10630 | } |
10631 | \f | |
10632 | void | |
17a2f251 | 10633 | mips_init_after_args (void) |
252b5132 RH |
10634 | { |
10635 | /* initialize opcodes */ | |
10636 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10637 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10638 | } |
10639 | ||
10640 | long | |
17a2f251 | 10641 | md_pcrel_from (fixS *fixP) |
252b5132 | 10642 | { |
a7ebbfdf TS |
10643 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10644 | switch (fixP->fx_r_type) | |
10645 | { | |
10646 | case BFD_RELOC_16_PCREL_S2: | |
10647 | case BFD_RELOC_MIPS_JMP: | |
10648 | /* Return the address of the delay slot. */ | |
10649 | return addr + 4; | |
10650 | default: | |
10651 | return addr; | |
10652 | } | |
252b5132 RH |
10653 | } |
10654 | ||
252b5132 RH |
10655 | /* This is called before the symbol table is processed. In order to |
10656 | work with gcc when using mips-tfile, we must keep all local labels. | |
10657 | However, in other cases, we want to discard them. If we were | |
10658 | called with -g, but we didn't see any debugging information, it may | |
10659 | mean that gcc is smuggling debugging information through to | |
10660 | mips-tfile, in which case we must generate all local labels. */ | |
10661 | ||
10662 | void | |
17a2f251 | 10663 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10664 | { |
10665 | #ifndef NO_ECOFF_DEBUGGING | |
10666 | if (ECOFF_DEBUGGING | |
10667 | && mips_debug != 0 | |
10668 | && ! ecoff_debugging_seen) | |
10669 | flag_keep_locals = 1; | |
10670 | #endif | |
10671 | } | |
10672 | ||
10673 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10674 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10675 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10676 | explicit use of the %hi modifier. */ | |
10677 | ||
10678 | void | |
17a2f251 | 10679 | mips_frob_file (void) |
252b5132 RH |
10680 | { |
10681 | struct mips_hi_fixup *l; | |
10682 | ||
10683 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10684 | { | |
10685 | segment_info_type *seginfo; | |
10686 | int pass; | |
10687 | ||
5919d012 | 10688 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10689 | |
5919d012 RS |
10690 | /* If a GOT16 relocation turns out to be against a global symbol, |
10691 | there isn't supposed to be a matching LO. */ | |
10692 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10693 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10694 | continue; | |
10695 | ||
10696 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10697 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10698 | continue; |
10699 | ||
10700 | /* Look through the fixups for this segment for a matching %lo. | |
10701 | When we find one, move the %hi just in front of it. We do | |
10702 | this in two passes. In the first pass, we try to find a | |
10703 | unique %lo. In the second pass, we permit multiple %hi | |
10704 | relocs for a single %lo (this is a GNU extension). */ | |
10705 | seginfo = seg_info (l->seg); | |
10706 | for (pass = 0; pass < 2; pass++) | |
10707 | { | |
10708 | fixS *f, *prev; | |
10709 | ||
10710 | prev = NULL; | |
10711 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10712 | { | |
10713 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10714 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10715 | && f->fx_addsy == l->fixp->fx_addsy | |
10716 | && f->fx_offset == l->fixp->fx_offset | |
10717 | && (pass == 1 | |
10718 | || prev == NULL | |
5919d012 RS |
10719 | || !reloc_needs_lo_p (prev->fx_r_type) |
10720 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10721 | { |
10722 | fixS **pf; | |
10723 | ||
10724 | /* Move l->fixp before f. */ | |
10725 | for (pf = &seginfo->fix_root; | |
10726 | *pf != l->fixp; | |
10727 | pf = &(*pf)->fx_next) | |
10728 | assert (*pf != NULL); | |
10729 | ||
10730 | *pf = l->fixp->fx_next; | |
10731 | ||
10732 | l->fixp->fx_next = f; | |
10733 | if (prev == NULL) | |
10734 | seginfo->fix_root = l->fixp; | |
10735 | else | |
10736 | prev->fx_next = l->fixp; | |
10737 | ||
10738 | break; | |
10739 | } | |
10740 | ||
10741 | prev = f; | |
10742 | } | |
10743 | ||
10744 | if (f != NULL) | |
10745 | break; | |
10746 | ||
10747 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10748 | can leave a %hi without a %lo. */ | |
10749 | if (pass == 1) | |
10750 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10751 | _("Unmatched %%hi reloc")); | |
10752 | #endif | |
10753 | } | |
10754 | } | |
10755 | } | |
10756 | ||
3e722fb5 | 10757 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10758 | We have to prevent gas from dropping them. */ |
252b5132 | 10759 | |
252b5132 | 10760 | int |
17a2f251 | 10761 | mips_force_relocation (fixS *fixp) |
252b5132 | 10762 | { |
ae6063d4 | 10763 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10764 | return 1; |
10765 | ||
f6688943 TS |
10766 | if (HAVE_NEWABI |
10767 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10768 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10769 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10770 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10771 | return 1; | |
10772 | ||
3e722fb5 | 10773 | return 0; |
252b5132 RH |
10774 | } |
10775 | ||
45f8dfe8 AO |
10776 | /* This hook is called before a fix is simplified. We don't really |
10777 | decide whether to skip a fix here. Rather, we turn global symbols | |
10778 | used as branch targets into local symbols, such that they undergo | |
10779 | simplification. We can only do this if the symbol is defined and | |
10780 | it is in the same section as the branch. If this doesn't hold, we | |
10781 | emit a better error message than just saying the relocation is not | |
10782 | valid for the selected object format. | |
10783 | ||
10784 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10785 | segment in which the fix up occurs. The return value should be | |
10786 | non-zero to indicate the fix-up is valid for further | |
10787 | simplifications. */ | |
10788 | ||
10789 | int | |
17a2f251 | 10790 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10791 | { |
10792 | /* There's a lot of discussion on whether it should be possible to | |
10793 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10794 | seems to be that it can, but gas/bfd are very broken in creating | |
10795 | RELA relocations for this, so for now we only accept branches to | |
10796 | symbols in the same section. Anything else is of dubious value, | |
10797 | since there's no guarantee that at link time the symbol would be | |
10798 | in range. Even for branches to local symbols this is arguably | |
10799 | wrong, since it we assume the symbol is not going to be | |
10800 | overridden, which should be possible per ELF library semantics, | |
10801 | but then, there isn't a dynamic relocation that could be used to | |
10802 | this effect, and the target would likely be out of range as well. | |
10803 | ||
10804 | Unfortunately, it seems that there is too much code out there | |
10805 | that relies on branches to symbols that are global to be resolved | |
10806 | as if they were local, like the IRIX tools do, so we do it as | |
10807 | well, but with a warning so that people are reminded to fix their | |
10808 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10809 | targets, this entire block should go away (and probably the | |
10810 | whole function). */ | |
10811 | ||
10812 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10813 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10814 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10815 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10816 | && fixP->fx_addsy) | |
10817 | { | |
10818 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10819 | { | |
10820 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10821 | _("Cannot branch to undefined symbol.")); | |
10822 | /* Avoid any further errors about this fixup. */ | |
10823 | fixP->fx_done = 1; | |
10824 | } | |
10825 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10826 | { | |
10827 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10828 | _("Cannot branch to symbol in another section.")); | |
10829 | fixP->fx_done = 1; | |
10830 | } | |
10831 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10832 | { | |
10833 | symbolS *sym = fixP->fx_addsy; | |
10834 | ||
115695a8 CD |
10835 | if (mips_pic == SVR4_PIC) |
10836 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10837 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10838 | |
10839 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10840 | S_GET_SEGMENT (sym), | |
10841 | S_GET_VALUE (sym), | |
10842 | symbol_get_frag (sym)); | |
10843 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10844 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10845 | assert (symbol_resolved_p (sym)); | |
10846 | symbol_mark_resolved (fixP->fx_addsy); | |
10847 | } | |
10848 | } | |
10849 | ||
10850 | return 1; | |
10851 | } | |
10852 | ||
252b5132 RH |
10853 | /* Apply a fixup to the object file. */ |
10854 | ||
94f592af | 10855 | void |
17a2f251 | 10856 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10857 | { |
874e8986 | 10858 | bfd_byte *buf; |
98aa84af | 10859 | long insn; |
ed6fb7bd | 10860 | static int previous_fx_r_type = 0; |
a7ebbfdf | 10861 | reloc_howto_type *howto; |
252b5132 | 10862 | |
a7ebbfdf TS |
10863 | /* We ignore generic BFD relocations we don't know about. */ |
10864 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10865 | if (! howto) | |
10866 | return; | |
65551fa4 | 10867 | |
252b5132 RH |
10868 | assert (fixP->fx_size == 4 |
10869 | || fixP->fx_r_type == BFD_RELOC_16 | |
10870 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10871 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10872 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10873 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10874 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10875 | |
a7ebbfdf | 10876 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10877 | |
ed6fb7bd | 10878 | /* We are not done if this is a composite relocation to set up gp. */ |
3e722fb5 CD |
10879 | assert (! fixP->fx_pcrel); |
10880 | if (fixP->fx_addsy == NULL | |
ed6fb7bd | 10881 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB |
10181a0d AO |
10882 | || (fixP->fx_r_type == BFD_RELOC_64 |
10883 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
10884 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
10885 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
10886 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
10887 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 10888 | fixP->fx_done = 1; |
ed6fb7bd | 10889 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
10890 | |
10891 | switch (fixP->fx_r_type) | |
10892 | { | |
10893 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10894 | case BFD_RELOC_MIPS_SHIFT5: |
10895 | case BFD_RELOC_MIPS_SHIFT6: | |
10896 | case BFD_RELOC_MIPS_GOT_DISP: | |
10897 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10898 | case BFD_RELOC_MIPS_GOT_OFST: | |
10899 | case BFD_RELOC_MIPS_SUB: | |
10900 | case BFD_RELOC_MIPS_INSERT_A: | |
10901 | case BFD_RELOC_MIPS_INSERT_B: | |
10902 | case BFD_RELOC_MIPS_DELETE: | |
10903 | case BFD_RELOC_MIPS_HIGHEST: | |
10904 | case BFD_RELOC_MIPS_HIGHER: | |
10905 | case BFD_RELOC_MIPS_SCN_DISP: | |
10906 | case BFD_RELOC_MIPS_REL16: | |
10907 | case BFD_RELOC_MIPS_RELGOT: | |
10908 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10909 | case BFD_RELOC_HI16: |
10910 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10911 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10912 | case BFD_RELOC_MIPS_LITERAL: |
10913 | case BFD_RELOC_MIPS_CALL16: | |
10914 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10915 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10916 | case BFD_RELOC_MIPS_GOT_HI16: |
10917 | case BFD_RELOC_MIPS_GOT_LO16: | |
10918 | case BFD_RELOC_MIPS_CALL_HI16: | |
10919 | case BFD_RELOC_MIPS_CALL_LO16: | |
10920 | case BFD_RELOC_MIPS16_GPREL: | |
3e722fb5 | 10921 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10922 | /* Nothing needed to do. The value comes from the reloc entry */ |
10923 | break; | |
10924 | ||
10925 | case BFD_RELOC_MIPS16_JMP: | |
10926 | /* We currently always generate a reloc against a symbol, which | |
10927 | means that we don't want an addend even if the symbol is | |
10928 | defined. */ | |
a7ebbfdf | 10929 | *valP = 0; |
252b5132 RH |
10930 | break; |
10931 | ||
252b5132 RH |
10932 | case BFD_RELOC_64: |
10933 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10934 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10935 | if (fixP->fx_done) |
252b5132 RH |
10936 | { |
10937 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 10938 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
10939 | else |
10940 | { | |
a7ebbfdf | 10941 | valueT hiv; |
252b5132 | 10942 | |
a7ebbfdf | 10943 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
10944 | hiv = 0xffffffff; |
10945 | else | |
10946 | hiv = 0; | |
a7ebbfdf TS |
10947 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
10948 | *valP, 4); | |
10949 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
10950 | hiv, 4); | |
252b5132 RH |
10951 | } |
10952 | } | |
10953 | break; | |
10954 | ||
056350c6 | 10955 | case BFD_RELOC_RVA: |
252b5132 RH |
10956 | case BFD_RELOC_32: |
10957 | /* If we are deleting this reloc entry, we must fill in the | |
10958 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
10959 | resolved when it appears but is later defined. */ |
10960 | if (fixP->fx_done) | |
a7ebbfdf | 10961 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
10962 | break; |
10963 | ||
10964 | case BFD_RELOC_16: | |
10965 | /* If we are deleting this reloc entry, we must fill in the | |
10966 | value now. */ | |
10967 | assert (fixP->fx_size == 2); | |
10968 | if (fixP->fx_done) | |
a7ebbfdf | 10969 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
10970 | break; |
10971 | ||
10972 | case BFD_RELOC_LO16: | |
3e722fb5 CD |
10973 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
10974 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
10975 | /* When handling an embedded PIC switch statement, we can wind |
10976 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10977 | if (fixP->fx_done) | |
10978 | { | |
a7ebbfdf | 10979 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
10980 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10981 | _("relocation overflow")); | |
252b5132 RH |
10982 | if (target_big_endian) |
10983 | buf += 2; | |
17a2f251 | 10984 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
10985 | } |
10986 | break; | |
10987 | ||
10988 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 10989 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 10990 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 10991 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 10992 | |
252b5132 RH |
10993 | /* |
10994 | * We need to save the bits in the instruction since fixup_segment() | |
10995 | * might be deleting the relocation entry (i.e., a branch within | |
10996 | * the current segment). | |
10997 | */ | |
a7ebbfdf | 10998 | if (! fixP->fx_done) |
bb2d6cd7 | 10999 | break; |
252b5132 RH |
11000 | |
11001 | /* update old instruction data */ | |
252b5132 RH |
11002 | if (target_big_endian) |
11003 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11004 | else | |
11005 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11006 | ||
a7ebbfdf TS |
11007 | if (*valP + 0x20000 <= 0x3ffff) |
11008 | { | |
11009 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11010 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11011 | } |
11012 | else if (mips_pic == NO_PIC | |
11013 | && fixP->fx_done | |
11014 | && fixP->fx_frag->fr_address >= text_section->vma | |
11015 | && (fixP->fx_frag->fr_address | |
587aac4e | 11016 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11017 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11018 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11019 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11020 | { |
11021 | /* The branch offset is too large. If this is an | |
11022 | unconditional branch, and we are not generating PIC code, | |
11023 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11024 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11025 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11026 | else |
a7ebbfdf TS |
11027 | insn = 0x08000000; /* j */ |
11028 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11029 | fixP->fx_done = 0; | |
11030 | fixP->fx_addsy = section_symbol (text_section); | |
11031 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11032 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11033 | } |
11034 | else | |
11035 | { | |
11036 | /* If we got here, we have branch-relaxation disabled, | |
11037 | and there's nothing we can do to fix this instruction | |
11038 | without turning it into a longer sequence. */ | |
11039 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11040 | _("Branch out of range")); | |
252b5132 | 11041 | } |
252b5132 RH |
11042 | break; |
11043 | ||
11044 | case BFD_RELOC_VTABLE_INHERIT: | |
11045 | fixP->fx_done = 0; | |
11046 | if (fixP->fx_addsy | |
11047 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11048 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11049 | S_SET_WEAK (fixP->fx_addsy); | |
11050 | break; | |
11051 | ||
11052 | case BFD_RELOC_VTABLE_ENTRY: | |
11053 | fixP->fx_done = 0; | |
11054 | break; | |
11055 | ||
11056 | default: | |
11057 | internalError (); | |
11058 | } | |
a7ebbfdf TS |
11059 | |
11060 | /* Remember value for tc_gen_reloc. */ | |
11061 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11062 | } |
11063 | ||
11064 | #if 0 | |
11065 | void | |
17a2f251 | 11066 | printInsn (unsigned long oc) |
252b5132 RH |
11067 | { |
11068 | const struct mips_opcode *p; | |
11069 | int treg, sreg, dreg, shamt; | |
11070 | short imm; | |
11071 | const char *args; | |
11072 | int i; | |
11073 | ||
11074 | for (i = 0; i < NUMOPCODES; ++i) | |
11075 | { | |
11076 | p = &mips_opcodes[i]; | |
11077 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11078 | { | |
11079 | printf ("%08lx %s\t", oc, p->name); | |
11080 | treg = (oc >> 16) & 0x1f; | |
11081 | sreg = (oc >> 21) & 0x1f; | |
11082 | dreg = (oc >> 11) & 0x1f; | |
11083 | shamt = (oc >> 6) & 0x1f; | |
11084 | imm = oc; | |
11085 | for (args = p->args;; ++args) | |
11086 | { | |
11087 | switch (*args) | |
11088 | { | |
11089 | case '\0': | |
11090 | printf ("\n"); | |
11091 | break; | |
11092 | ||
11093 | case ',': | |
11094 | case '(': | |
11095 | case ')': | |
11096 | printf ("%c", *args); | |
11097 | continue; | |
11098 | ||
11099 | case 'r': | |
11100 | assert (treg == sreg); | |
11101 | printf ("$%d,$%d", treg, sreg); | |
11102 | continue; | |
11103 | ||
11104 | case 'd': | |
11105 | case 'G': | |
11106 | printf ("$%d", dreg); | |
11107 | continue; | |
11108 | ||
11109 | case 't': | |
11110 | case 'E': | |
11111 | printf ("$%d", treg); | |
11112 | continue; | |
11113 | ||
11114 | case 'k': | |
11115 | printf ("0x%x", treg); | |
11116 | continue; | |
11117 | ||
11118 | case 'b': | |
11119 | case 's': | |
11120 | printf ("$%d", sreg); | |
11121 | continue; | |
11122 | ||
11123 | case 'a': | |
11124 | printf ("0x%08lx", oc & 0x1ffffff); | |
11125 | continue; | |
11126 | ||
11127 | case 'i': | |
11128 | case 'j': | |
11129 | case 'o': | |
11130 | case 'u': | |
11131 | printf ("%d", imm); | |
11132 | continue; | |
11133 | ||
11134 | case '<': | |
11135 | case '>': | |
11136 | printf ("$%d", shamt); | |
11137 | continue; | |
11138 | ||
11139 | default: | |
11140 | internalError (); | |
11141 | } | |
11142 | break; | |
11143 | } | |
11144 | return; | |
11145 | } | |
11146 | } | |
11147 | printf (_("%08lx UNDEFINED\n"), oc); | |
11148 | } | |
11149 | #endif | |
11150 | ||
11151 | static symbolS * | |
17a2f251 | 11152 | get_symbol (void) |
252b5132 RH |
11153 | { |
11154 | int c; | |
11155 | char *name; | |
11156 | symbolS *p; | |
11157 | ||
11158 | name = input_line_pointer; | |
11159 | c = get_symbol_end (); | |
11160 | p = (symbolS *) symbol_find_or_make (name); | |
11161 | *input_line_pointer = c; | |
11162 | return p; | |
11163 | } | |
11164 | ||
11165 | /* Align the current frag to a given power of two. The MIPS assembler | |
11166 | also automatically adjusts any preceding label. */ | |
11167 | ||
11168 | static void | |
17a2f251 | 11169 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11170 | { |
b34976b6 | 11171 | mips_emit_delays (FALSE); |
252b5132 RH |
11172 | frag_align (to, fill, 0); |
11173 | record_alignment (now_seg, to); | |
11174 | if (label != NULL) | |
11175 | { | |
11176 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11177 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11178 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11179 | } | |
11180 | } | |
11181 | ||
11182 | /* Align to a given power of two. .align 0 turns off the automatic | |
11183 | alignment used by the data creating pseudo-ops. */ | |
11184 | ||
11185 | static void | |
17a2f251 | 11186 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11187 | { |
11188 | register int temp; | |
11189 | register long temp_fill; | |
11190 | long max_alignment = 15; | |
11191 | ||
11192 | /* | |
11193 | ||
67c1ffbe | 11194 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11195 | to the aligned address. |
11196 | o It's not documented but auto alignment is reinstated by | |
11197 | a .align pseudo instruction. | |
11198 | o Note also that after auto alignment is turned off the mips assembler | |
11199 | issues an error on attempt to assemble an improperly aligned data item. | |
11200 | We don't. | |
11201 | ||
11202 | */ | |
11203 | ||
11204 | temp = get_absolute_expression (); | |
11205 | if (temp > max_alignment) | |
11206 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11207 | else if (temp < 0) | |
11208 | { | |
11209 | as_warn (_("Alignment negative: 0 assumed.")); | |
11210 | temp = 0; | |
11211 | } | |
11212 | if (*input_line_pointer == ',') | |
11213 | { | |
f9419b05 | 11214 | ++input_line_pointer; |
252b5132 RH |
11215 | temp_fill = get_absolute_expression (); |
11216 | } | |
11217 | else | |
11218 | temp_fill = 0; | |
11219 | if (temp) | |
11220 | { | |
11221 | auto_align = 1; | |
11222 | mips_align (temp, (int) temp_fill, | |
11223 | insn_labels != NULL ? insn_labels->label : NULL); | |
11224 | } | |
11225 | else | |
11226 | { | |
11227 | auto_align = 0; | |
11228 | } | |
11229 | ||
11230 | demand_empty_rest_of_line (); | |
11231 | } | |
11232 | ||
11233 | void | |
17a2f251 | 11234 | mips_flush_pending_output (void) |
252b5132 | 11235 | { |
b34976b6 | 11236 | mips_emit_delays (FALSE); |
252b5132 RH |
11237 | mips_clear_insn_labels (); |
11238 | } | |
11239 | ||
11240 | static void | |
17a2f251 | 11241 | s_change_sec (int sec) |
252b5132 RH |
11242 | { |
11243 | segT seg; | |
11244 | ||
252b5132 RH |
11245 | #ifdef OBJ_ELF |
11246 | /* The ELF backend needs to know that we are changing sections, so | |
11247 | that .previous works correctly. We could do something like check | |
b6ff326e | 11248 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11249 | as it would not be appropriate to use it in the section changing |
11250 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11251 | This should be cleaner, somehow. */ | |
11252 | obj_elf_section_change_hook (); | |
11253 | #endif | |
11254 | ||
b34976b6 | 11255 | mips_emit_delays (FALSE); |
252b5132 RH |
11256 | switch (sec) |
11257 | { | |
11258 | case 't': | |
11259 | s_text (0); | |
11260 | break; | |
11261 | case 'd': | |
11262 | s_data (0); | |
11263 | break; | |
11264 | case 'b': | |
11265 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11266 | demand_empty_rest_of_line (); | |
11267 | break; | |
11268 | ||
11269 | case 'r': | |
4d0d148d TS |
11270 | seg = subseg_new (RDATA_SECTION_NAME, |
11271 | (subsegT) get_absolute_expression ()); | |
11272 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11273 | { |
4d0d148d TS |
11274 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11275 | | SEC_READONLY | SEC_RELOC | |
11276 | | SEC_DATA)); | |
11277 | if (strcmp (TARGET_OS, "elf") != 0) | |
11278 | record_alignment (seg, 4); | |
252b5132 | 11279 | } |
4d0d148d | 11280 | demand_empty_rest_of_line (); |
252b5132 RH |
11281 | break; |
11282 | ||
11283 | case 's': | |
4d0d148d TS |
11284 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11285 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11286 | { |
4d0d148d TS |
11287 | bfd_set_section_flags (stdoutput, seg, |
11288 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11289 | if (strcmp (TARGET_OS, "elf") != 0) | |
11290 | record_alignment (seg, 4); | |
252b5132 | 11291 | } |
4d0d148d TS |
11292 | demand_empty_rest_of_line (); |
11293 | break; | |
252b5132 RH |
11294 | } |
11295 | ||
11296 | auto_align = 1; | |
11297 | } | |
b34976b6 | 11298 | |
cca86cc8 | 11299 | void |
17a2f251 | 11300 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11301 | { |
7ed4a06a | 11302 | #ifdef OBJ_ELF |
cca86cc8 SC |
11303 | char *section_name; |
11304 | char c; | |
684022ea | 11305 | char next_c = 0; |
cca86cc8 SC |
11306 | int section_type; |
11307 | int section_flag; | |
11308 | int section_entry_size; | |
11309 | int section_alignment; | |
b34976b6 | 11310 | |
7ed4a06a TS |
11311 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11312 | return; | |
11313 | ||
cca86cc8 SC |
11314 | section_name = input_line_pointer; |
11315 | c = get_symbol_end (); | |
a816d1ed AO |
11316 | if (c) |
11317 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11318 | |
4cf0dd0d TS |
11319 | /* Do we have .section Name<,"flags">? */ |
11320 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11321 | { |
4cf0dd0d TS |
11322 | /* just after name is now '\0'. */ |
11323 | *input_line_pointer = c; | |
cca86cc8 SC |
11324 | input_line_pointer = section_name; |
11325 | obj_elf_section (ignore); | |
11326 | return; | |
11327 | } | |
11328 | input_line_pointer++; | |
11329 | ||
11330 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11331 | if (c == ',') | |
11332 | section_type = get_absolute_expression (); | |
11333 | else | |
11334 | section_type = 0; | |
11335 | if (*input_line_pointer++ == ',') | |
11336 | section_flag = get_absolute_expression (); | |
11337 | else | |
11338 | section_flag = 0; | |
11339 | if (*input_line_pointer++ == ',') | |
11340 | section_entry_size = get_absolute_expression (); | |
11341 | else | |
11342 | section_entry_size = 0; | |
11343 | if (*input_line_pointer++ == ',') | |
11344 | section_alignment = get_absolute_expression (); | |
11345 | else | |
11346 | section_alignment = 0; | |
11347 | ||
a816d1ed AO |
11348 | section_name = xstrdup (section_name); |
11349 | ||
8ab8a5c8 RS |
11350 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11351 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11352 | traditionally had to fall back on the more common @progbits instead. | |
11353 | ||
11354 | There's nothing really harmful in this, since bfd will correct | |
11355 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11356 | means that, for backwards compatibiltiy, the special_section entries | |
11357 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11358 | ||
11359 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11360 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11361 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11362 | generic type-checking code. */ | |
11363 | if (section_type == SHT_MIPS_DWARF) | |
11364 | section_type = SHT_PROGBITS; | |
11365 | ||
cca86cc8 SC |
11366 | obj_elf_change_section (section_name, section_type, section_flag, |
11367 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11368 | |
11369 | if (now_seg->name != section_name) | |
11370 | free (section_name); | |
7ed4a06a | 11371 | #endif /* OBJ_ELF */ |
cca86cc8 | 11372 | } |
252b5132 RH |
11373 | |
11374 | void | |
17a2f251 | 11375 | mips_enable_auto_align (void) |
252b5132 RH |
11376 | { |
11377 | auto_align = 1; | |
11378 | } | |
11379 | ||
11380 | static void | |
17a2f251 | 11381 | s_cons (int log_size) |
252b5132 RH |
11382 | { |
11383 | symbolS *label; | |
11384 | ||
11385 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11386 | mips_emit_delays (FALSE); |
252b5132 RH |
11387 | if (log_size > 0 && auto_align) |
11388 | mips_align (log_size, 0, label); | |
11389 | mips_clear_insn_labels (); | |
11390 | cons (1 << log_size); | |
11391 | } | |
11392 | ||
11393 | static void | |
17a2f251 | 11394 | s_float_cons (int type) |
252b5132 RH |
11395 | { |
11396 | symbolS *label; | |
11397 | ||
11398 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11399 | ||
b34976b6 | 11400 | mips_emit_delays (FALSE); |
252b5132 RH |
11401 | |
11402 | if (auto_align) | |
49309057 ILT |
11403 | { |
11404 | if (type == 'd') | |
11405 | mips_align (3, 0, label); | |
11406 | else | |
11407 | mips_align (2, 0, label); | |
11408 | } | |
252b5132 RH |
11409 | |
11410 | mips_clear_insn_labels (); | |
11411 | ||
11412 | float_cons (type); | |
11413 | } | |
11414 | ||
11415 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11416 | permitted to say | |
11417 | .globl foo .text | |
11418 | where foo is an undefined symbol, to mean that foo should be | |
11419 | considered to be the address of a function. */ | |
11420 | ||
11421 | static void | |
17a2f251 | 11422 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11423 | { |
11424 | char *name; | |
11425 | int c; | |
11426 | symbolS *symbolP; | |
11427 | flagword flag; | |
11428 | ||
11429 | name = input_line_pointer; | |
11430 | c = get_symbol_end (); | |
11431 | symbolP = symbol_find_or_make (name); | |
11432 | *input_line_pointer = c; | |
11433 | SKIP_WHITESPACE (); | |
11434 | ||
11435 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11436 | being a function is apparently labelled as being an object. */ | |
11437 | flag = BSF_OBJECT; | |
11438 | ||
11439 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11440 | { | |
11441 | char *secname; | |
11442 | asection *sec; | |
11443 | ||
11444 | secname = input_line_pointer; | |
11445 | c = get_symbol_end (); | |
11446 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11447 | if (sec == NULL) | |
11448 | as_bad (_("%s: no such section"), secname); | |
11449 | *input_line_pointer = c; | |
11450 | ||
11451 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11452 | flag = BSF_FUNCTION; | |
11453 | } | |
11454 | ||
49309057 | 11455 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11456 | |
11457 | S_SET_EXTERNAL (symbolP); | |
11458 | demand_empty_rest_of_line (); | |
11459 | } | |
11460 | ||
11461 | static void | |
17a2f251 | 11462 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11463 | { |
11464 | char *opt; | |
11465 | char c; | |
11466 | ||
11467 | opt = input_line_pointer; | |
11468 | c = get_symbol_end (); | |
11469 | ||
11470 | if (*opt == 'O') | |
11471 | { | |
11472 | /* FIXME: What does this mean? */ | |
11473 | } | |
11474 | else if (strncmp (opt, "pic", 3) == 0) | |
11475 | { | |
11476 | int i; | |
11477 | ||
11478 | i = atoi (opt + 3); | |
11479 | if (i == 0) | |
11480 | mips_pic = NO_PIC; | |
11481 | else if (i == 2) | |
143d77c5 | 11482 | { |
252b5132 | 11483 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11484 | mips_abicalls = TRUE; |
11485 | } | |
252b5132 RH |
11486 | else |
11487 | as_bad (_(".option pic%d not supported"), i); | |
11488 | ||
4d0d148d | 11489 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11490 | { |
11491 | if (g_switch_seen && g_switch_value != 0) | |
11492 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11493 | g_switch_value = 0; | |
11494 | bfd_set_gp_size (stdoutput, 0); | |
11495 | } | |
11496 | } | |
11497 | else | |
11498 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11499 | ||
11500 | *input_line_pointer = c; | |
11501 | demand_empty_rest_of_line (); | |
11502 | } | |
11503 | ||
11504 | /* This structure is used to hold a stack of .set values. */ | |
11505 | ||
e972090a NC |
11506 | struct mips_option_stack |
11507 | { | |
252b5132 RH |
11508 | struct mips_option_stack *next; |
11509 | struct mips_set_options options; | |
11510 | }; | |
11511 | ||
11512 | static struct mips_option_stack *mips_opts_stack; | |
11513 | ||
11514 | /* Handle the .set pseudo-op. */ | |
11515 | ||
11516 | static void | |
17a2f251 | 11517 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11518 | { |
11519 | char *name = input_line_pointer, ch; | |
11520 | ||
11521 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11522 | ++input_line_pointer; |
252b5132 RH |
11523 | ch = *input_line_pointer; |
11524 | *input_line_pointer = '\0'; | |
11525 | ||
11526 | if (strcmp (name, "reorder") == 0) | |
11527 | { | |
11528 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11529 | { | |
11530 | /* If we still have pending nops, we can discard them. The | |
11531 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11532 | needed. */ |
252b5132 RH |
11533 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11534 | * (mips_opts.mips16 ? 2 : 4)); | |
11535 | prev_nop_frag = NULL; | |
11536 | } | |
11537 | mips_opts.noreorder = 0; | |
11538 | } | |
11539 | else if (strcmp (name, "noreorder") == 0) | |
11540 | { | |
b34976b6 | 11541 | mips_emit_delays (TRUE); |
252b5132 RH |
11542 | mips_opts.noreorder = 1; |
11543 | mips_any_noreorder = 1; | |
11544 | } | |
11545 | else if (strcmp (name, "at") == 0) | |
11546 | { | |
11547 | mips_opts.noat = 0; | |
11548 | } | |
11549 | else if (strcmp (name, "noat") == 0) | |
11550 | { | |
11551 | mips_opts.noat = 1; | |
11552 | } | |
11553 | else if (strcmp (name, "macro") == 0) | |
11554 | { | |
11555 | mips_opts.warn_about_macros = 0; | |
11556 | } | |
11557 | else if (strcmp (name, "nomacro") == 0) | |
11558 | { | |
11559 | if (mips_opts.noreorder == 0) | |
11560 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11561 | mips_opts.warn_about_macros = 1; | |
11562 | } | |
11563 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11564 | { | |
11565 | mips_opts.nomove = 0; | |
11566 | } | |
11567 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11568 | { | |
11569 | mips_opts.nomove = 1; | |
11570 | } | |
11571 | else if (strcmp (name, "bopt") == 0) | |
11572 | { | |
11573 | mips_opts.nobopt = 0; | |
11574 | } | |
11575 | else if (strcmp (name, "nobopt") == 0) | |
11576 | { | |
11577 | mips_opts.nobopt = 1; | |
11578 | } | |
11579 | else if (strcmp (name, "mips16") == 0 | |
11580 | || strcmp (name, "MIPS-16") == 0) | |
11581 | mips_opts.mips16 = 1; | |
11582 | else if (strcmp (name, "nomips16") == 0 | |
11583 | || strcmp (name, "noMIPS-16") == 0) | |
11584 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11585 | else if (strcmp (name, "mips3d") == 0) |
11586 | mips_opts.ase_mips3d = 1; | |
11587 | else if (strcmp (name, "nomips3d") == 0) | |
11588 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11589 | else if (strcmp (name, "mdmx") == 0) |
11590 | mips_opts.ase_mdmx = 1; | |
11591 | else if (strcmp (name, "nomdmx") == 0) | |
11592 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11593 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11594 | { |
af7ee8bf | 11595 | int reset = 0; |
252b5132 | 11596 | |
1a2c1fad CD |
11597 | /* Permit the user to change the ISA and architecture on the fly. |
11598 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11599 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11600 | { |
11601 | reset = 1; | |
11602 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11603 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11604 | } |
11605 | else if (strncmp (name, "arch=", 5) == 0) | |
11606 | { | |
11607 | const struct mips_cpu_info *p; | |
11608 | ||
11609 | p = mips_parse_cpu("internal use", name + 5); | |
11610 | if (!p) | |
11611 | as_bad (_("unknown architecture %s"), name + 5); | |
11612 | else | |
11613 | { | |
11614 | mips_opts.arch = p->cpu; | |
11615 | mips_opts.isa = p->isa; | |
11616 | } | |
11617 | } | |
81a21e38 TS |
11618 | else if (strncmp (name, "mips", 4) == 0) |
11619 | { | |
11620 | const struct mips_cpu_info *p; | |
11621 | ||
11622 | p = mips_parse_cpu("internal use", name); | |
11623 | if (!p) | |
11624 | as_bad (_("unknown ISA level %s"), name + 4); | |
11625 | else | |
11626 | { | |
11627 | mips_opts.arch = p->cpu; | |
11628 | mips_opts.isa = p->isa; | |
11629 | } | |
11630 | } | |
af7ee8bf | 11631 | else |
81a21e38 | 11632 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11633 | |
11634 | switch (mips_opts.isa) | |
98d3f06f KH |
11635 | { |
11636 | case 0: | |
98d3f06f | 11637 | break; |
af7ee8bf CD |
11638 | case ISA_MIPS1: |
11639 | case ISA_MIPS2: | |
11640 | case ISA_MIPS32: | |
11641 | case ISA_MIPS32R2: | |
98d3f06f KH |
11642 | mips_opts.gp32 = 1; |
11643 | mips_opts.fp32 = 1; | |
11644 | break; | |
af7ee8bf CD |
11645 | case ISA_MIPS3: |
11646 | case ISA_MIPS4: | |
11647 | case ISA_MIPS5: | |
11648 | case ISA_MIPS64: | |
5f74bc13 | 11649 | case ISA_MIPS64R2: |
98d3f06f KH |
11650 | mips_opts.gp32 = 0; |
11651 | mips_opts.fp32 = 0; | |
11652 | break; | |
11653 | default: | |
11654 | as_bad (_("unknown ISA level %s"), name + 4); | |
11655 | break; | |
11656 | } | |
af7ee8bf | 11657 | if (reset) |
98d3f06f | 11658 | { |
af7ee8bf CD |
11659 | mips_opts.gp32 = file_mips_gp32; |
11660 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11661 | } |
252b5132 RH |
11662 | } |
11663 | else if (strcmp (name, "autoextend") == 0) | |
11664 | mips_opts.noautoextend = 0; | |
11665 | else if (strcmp (name, "noautoextend") == 0) | |
11666 | mips_opts.noautoextend = 1; | |
11667 | else if (strcmp (name, "push") == 0) | |
11668 | { | |
11669 | struct mips_option_stack *s; | |
11670 | ||
11671 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11672 | s->next = mips_opts_stack; | |
11673 | s->options = mips_opts; | |
11674 | mips_opts_stack = s; | |
11675 | } | |
11676 | else if (strcmp (name, "pop") == 0) | |
11677 | { | |
11678 | struct mips_option_stack *s; | |
11679 | ||
11680 | s = mips_opts_stack; | |
11681 | if (s == NULL) | |
11682 | as_bad (_(".set pop with no .set push")); | |
11683 | else | |
11684 | { | |
11685 | /* If we're changing the reorder mode we need to handle | |
11686 | delay slots correctly. */ | |
11687 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11688 | mips_emit_delays (TRUE); |
252b5132 RH |
11689 | else if (! s->options.noreorder && mips_opts.noreorder) |
11690 | { | |
11691 | if (prev_nop_frag != NULL) | |
11692 | { | |
11693 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11694 | * (mips_opts.mips16 ? 2 : 4)); | |
11695 | prev_nop_frag = NULL; | |
11696 | } | |
11697 | } | |
11698 | ||
11699 | mips_opts = s->options; | |
11700 | mips_opts_stack = s->next; | |
11701 | free (s); | |
11702 | } | |
11703 | } | |
11704 | else | |
11705 | { | |
11706 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11707 | } | |
11708 | *input_line_pointer = ch; | |
11709 | demand_empty_rest_of_line (); | |
11710 | } | |
11711 | ||
11712 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11713 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11714 | ||
11715 | static void | |
17a2f251 | 11716 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11717 | { |
11718 | mips_pic = SVR4_PIC; | |
143d77c5 | 11719 | mips_abicalls = TRUE; |
4d0d148d TS |
11720 | |
11721 | if (g_switch_seen && g_switch_value != 0) | |
11722 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11723 | g_switch_value = 0; | |
11724 | ||
252b5132 RH |
11725 | bfd_set_gp_size (stdoutput, 0); |
11726 | demand_empty_rest_of_line (); | |
11727 | } | |
11728 | ||
11729 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11730 | PIC code. It sets the $gp register for the function based on the | |
11731 | function address, which is in the register named in the argument. | |
11732 | This uses a relocation against _gp_disp, which is handled specially | |
11733 | by the linker. The result is: | |
11734 | lui $gp,%hi(_gp_disp) | |
11735 | addiu $gp,$gp,%lo(_gp_disp) | |
11736 | addu $gp,$gp,.cpload argument | |
11737 | The .cpload argument is normally $25 == $t9. */ | |
11738 | ||
11739 | static void | |
17a2f251 | 11740 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11741 | { |
11742 | expressionS ex; | |
252b5132 | 11743 | |
6478892d TS |
11744 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11745 | .cpload is ignored. */ | |
11746 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11747 | { |
11748 | s_ignore (0); | |
11749 | return; | |
11750 | } | |
11751 | ||
d3ecfc59 | 11752 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11753 | if (mips_opts.noreorder == 0) |
11754 | as_warn (_(".cpload not in noreorder section")); | |
11755 | ||
11756 | ex.X_op = O_symbol; | |
11757 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11758 | ex.X_op_symbol = NULL; | |
11759 | ex.X_add_number = 0; | |
11760 | ||
11761 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11762 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11763 | |
584892a6 | 11764 | macro_start (); |
67c0d1eb RS |
11765 | macro_build_lui (&ex, mips_gp_register); |
11766 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11767 | mips_gp_register, BFD_RELOC_LO16); |
67c0d1eb | 11768 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
17a2f251 | 11769 | mips_gp_register, tc_get_register (0)); |
584892a6 | 11770 | macro_end (); |
252b5132 RH |
11771 | |
11772 | demand_empty_rest_of_line (); | |
11773 | } | |
11774 | ||
6478892d TS |
11775 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11776 | .cpsetup $reg1, offset|$reg2, label | |
11777 | ||
11778 | If offset is given, this results in: | |
11779 | sd $gp, offset($sp) | |
956cd1d6 | 11780 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11781 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11782 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11783 | |
11784 | If $reg2 is given, this results in: | |
11785 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11786 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11787 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11788 | daddu $gp, $gp, $reg1 | |
11789 | $reg1 is normally $25 == $t9. */ | |
6478892d | 11790 | static void |
17a2f251 | 11791 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11792 | { |
11793 | expressionS ex_off; | |
11794 | expressionS ex_sym; | |
11795 | int reg1; | |
f21f8242 | 11796 | char *f; |
6478892d | 11797 | |
8586fc66 | 11798 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11799 | We also need NewABI support. */ |
11800 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11801 | { | |
11802 | s_ignore (0); | |
11803 | return; | |
11804 | } | |
11805 | ||
11806 | reg1 = tc_get_register (0); | |
11807 | SKIP_WHITESPACE (); | |
11808 | if (*input_line_pointer != ',') | |
11809 | { | |
11810 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11811 | return; | |
11812 | } | |
11813 | else | |
80245285 | 11814 | ++input_line_pointer; |
6478892d TS |
11815 | SKIP_WHITESPACE (); |
11816 | if (*input_line_pointer == '$') | |
80245285 TS |
11817 | { |
11818 | mips_cpreturn_register = tc_get_register (0); | |
11819 | mips_cpreturn_offset = -1; | |
11820 | } | |
6478892d | 11821 | else |
80245285 TS |
11822 | { |
11823 | mips_cpreturn_offset = get_absolute_expression (); | |
11824 | mips_cpreturn_register = -1; | |
11825 | } | |
6478892d TS |
11826 | SKIP_WHITESPACE (); |
11827 | if (*input_line_pointer != ',') | |
11828 | { | |
11829 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11830 | return; | |
11831 | } | |
11832 | else | |
f9419b05 | 11833 | ++input_line_pointer; |
6478892d | 11834 | SKIP_WHITESPACE (); |
f21f8242 | 11835 | expression (&ex_sym); |
6478892d | 11836 | |
584892a6 | 11837 | macro_start (); |
6478892d TS |
11838 | if (mips_cpreturn_register == -1) |
11839 | { | |
11840 | ex_off.X_op = O_constant; | |
11841 | ex_off.X_add_symbol = NULL; | |
11842 | ex_off.X_op_symbol = NULL; | |
11843 | ex_off.X_add_number = mips_cpreturn_offset; | |
11844 | ||
67c0d1eb | 11845 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11846 | BFD_RELOC_LO16, SP); |
6478892d TS |
11847 | } |
11848 | else | |
67c0d1eb | 11849 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11850 | mips_gp_register, 0); |
6478892d | 11851 | |
f21f8242 AO |
11852 | /* Ensure there's room for the next two instructions, so that `f' |
11853 | doesn't end up with an address in the wrong frag. */ | |
11854 | frag_grow (8); | |
11855 | f = frag_more (0); | |
67c0d1eb | 11856 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 11857 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11858 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 11859 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11860 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
11861 | |
11862 | f = frag_more (0); | |
67c0d1eb | 11863 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
17a2f251 | 11864 | mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 11865 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11866 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 11867 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11868 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 11869 | |
67c0d1eb | 11870 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
17a2f251 | 11871 | mips_gp_register, reg1); |
584892a6 | 11872 | macro_end (); |
6478892d TS |
11873 | |
11874 | demand_empty_rest_of_line (); | |
11875 | } | |
11876 | ||
11877 | static void | |
17a2f251 | 11878 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11879 | { |
11880 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11881 | .cplocal is ignored. */ | |
11882 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11883 | { | |
11884 | s_ignore (0); | |
11885 | return; | |
11886 | } | |
11887 | ||
11888 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11889 | demand_empty_rest_of_line (); |
6478892d TS |
11890 | } |
11891 | ||
252b5132 RH |
11892 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11893 | offset from $sp. The offset is remembered, and after making a PIC | |
11894 | call $gp is restored from that location. */ | |
11895 | ||
11896 | static void | |
17a2f251 | 11897 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11898 | { |
11899 | expressionS ex; | |
252b5132 | 11900 | |
6478892d | 11901 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11902 | .cprestore is ignored. */ |
6478892d | 11903 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11904 | { |
11905 | s_ignore (0); | |
11906 | return; | |
11907 | } | |
11908 | ||
11909 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11910 | mips_cprestore_valid = 1; |
252b5132 RH |
11911 | |
11912 | ex.X_op = O_constant; | |
11913 | ex.X_add_symbol = NULL; | |
11914 | ex.X_op_symbol = NULL; | |
11915 | ex.X_add_number = mips_cprestore_offset; | |
11916 | ||
584892a6 | 11917 | macro_start (); |
67c0d1eb RS |
11918 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11919 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11920 | macro_end (); |
252b5132 RH |
11921 | |
11922 | demand_empty_rest_of_line (); | |
11923 | } | |
11924 | ||
6478892d | 11925 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11926 | was given in the preceding .cpsetup, it results in: |
6478892d | 11927 | ld $gp, offset($sp) |
76b3015f | 11928 | |
6478892d | 11929 | If a register $reg2 was given there, it results in: |
609f23f4 | 11930 | daddu $gp, $reg2, $0 |
6478892d TS |
11931 | */ |
11932 | static void | |
17a2f251 | 11933 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11934 | { |
11935 | expressionS ex; | |
6478892d TS |
11936 | |
11937 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11938 | We also need NewABI support. */ | |
11939 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11940 | { | |
11941 | s_ignore (0); | |
11942 | return; | |
11943 | } | |
11944 | ||
584892a6 | 11945 | macro_start (); |
6478892d TS |
11946 | if (mips_cpreturn_register == -1) |
11947 | { | |
11948 | ex.X_op = O_constant; | |
11949 | ex.X_add_symbol = NULL; | |
11950 | ex.X_op_symbol = NULL; | |
11951 | ex.X_add_number = mips_cpreturn_offset; | |
11952 | ||
67c0d1eb | 11953 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11954 | } |
11955 | else | |
67c0d1eb | 11956 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11957 | mips_cpreturn_register, 0); |
584892a6 | 11958 | macro_end (); |
6478892d TS |
11959 | |
11960 | demand_empty_rest_of_line (); | |
11961 | } | |
11962 | ||
11963 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11964 | code. It sets the offset to use in gp_rel relocations. */ | |
11965 | ||
11966 | static void | |
17a2f251 | 11967 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11968 | { |
11969 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11970 | We also need NewABI support. */ | |
11971 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11972 | { | |
11973 | s_ignore (0); | |
11974 | return; | |
11975 | } | |
11976 | ||
def2e0dd | 11977 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11978 | |
11979 | demand_empty_rest_of_line (); | |
11980 | } | |
11981 | ||
252b5132 RH |
11982 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11983 | code. It generates a 32 bit GP relative reloc. */ | |
11984 | ||
11985 | static void | |
17a2f251 | 11986 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11987 | { |
11988 | symbolS *label; | |
11989 | expressionS ex; | |
11990 | char *p; | |
11991 | ||
11992 | /* When not generating PIC code, this is treated as .word. */ | |
11993 | if (mips_pic != SVR4_PIC) | |
11994 | { | |
11995 | s_cons (2); | |
11996 | return; | |
11997 | } | |
11998 | ||
11999 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12000 | mips_emit_delays (TRUE); |
252b5132 RH |
12001 | if (auto_align) |
12002 | mips_align (2, 0, label); | |
12003 | mips_clear_insn_labels (); | |
12004 | ||
12005 | expression (&ex); | |
12006 | ||
12007 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12008 | { | |
12009 | as_bad (_("Unsupported use of .gpword")); | |
12010 | ignore_rest_of_line (); | |
12011 | } | |
12012 | ||
12013 | p = frag_more (4); | |
17a2f251 | 12014 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12015 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12016 | BFD_RELOC_GPREL32); |
252b5132 RH |
12017 | |
12018 | demand_empty_rest_of_line (); | |
12019 | } | |
12020 | ||
10181a0d | 12021 | static void |
17a2f251 | 12022 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12023 | { |
12024 | symbolS *label; | |
12025 | expressionS ex; | |
12026 | char *p; | |
12027 | ||
12028 | /* When not generating PIC code, this is treated as .dword. */ | |
12029 | if (mips_pic != SVR4_PIC) | |
12030 | { | |
12031 | s_cons (3); | |
12032 | return; | |
12033 | } | |
12034 | ||
12035 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12036 | mips_emit_delays (TRUE); |
10181a0d AO |
12037 | if (auto_align) |
12038 | mips_align (3, 0, label); | |
12039 | mips_clear_insn_labels (); | |
12040 | ||
12041 | expression (&ex); | |
12042 | ||
12043 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12044 | { | |
12045 | as_bad (_("Unsupported use of .gpdword")); | |
12046 | ignore_rest_of_line (); | |
12047 | } | |
12048 | ||
12049 | p = frag_more (8); | |
17a2f251 | 12050 | md_number_to_chars (p, 0, 8); |
a105a300 | 12051 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12052 | BFD_RELOC_GPREL32); |
12053 | ||
12054 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12055 | ex.X_op = O_absent; | |
12056 | ex.X_add_symbol = 0; | |
12057 | ex.X_add_number = 0; | |
b34976b6 | 12058 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12059 | BFD_RELOC_64); |
12060 | ||
12061 | demand_empty_rest_of_line (); | |
12062 | } | |
12063 | ||
252b5132 RH |
12064 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12065 | tables in SVR4 PIC code. */ | |
12066 | ||
12067 | static void | |
17a2f251 | 12068 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12069 | { |
252b5132 RH |
12070 | int reg; |
12071 | ||
10181a0d AO |
12072 | /* This is ignored when not generating SVR4 PIC code. */ |
12073 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12074 | { |
12075 | s_ignore (0); | |
12076 | return; | |
12077 | } | |
12078 | ||
12079 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12080 | macro_start (); |
252b5132 | 12081 | reg = tc_get_register (0); |
67c0d1eb | 12082 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12083 | macro_end (); |
252b5132 | 12084 | |
bdaaa2e1 | 12085 | demand_empty_rest_of_line (); |
252b5132 RH |
12086 | } |
12087 | ||
12088 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12089 | mips16 mode. This permits the linker to handle them specially, | |
12090 | such as generating jalx instructions when needed. We also make | |
12091 | them odd for the duration of the assembly, in order to generate the | |
12092 | right sort of code. We will make them even in the adjust_symtab | |
12093 | routine, while leaving them marked. This is convenient for the | |
12094 | debugger and the disassembler. The linker knows to make them odd | |
12095 | again. */ | |
12096 | ||
12097 | static void | |
17a2f251 | 12098 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12099 | { |
f9419b05 | 12100 | mips16_mark_labels (); |
252b5132 RH |
12101 | |
12102 | demand_empty_rest_of_line (); | |
12103 | } | |
12104 | ||
12105 | /* Handle a .stabn directive. We need these in order to mark a label | |
12106 | as being a mips16 text label correctly. Sometimes the compiler | |
12107 | will emit a label, followed by a .stabn, and then switch sections. | |
12108 | If the label and .stabn are in mips16 mode, then the label is | |
12109 | really a mips16 text label. */ | |
12110 | ||
12111 | static void | |
17a2f251 | 12112 | s_mips_stab (int type) |
252b5132 | 12113 | { |
f9419b05 | 12114 | if (type == 'n') |
252b5132 RH |
12115 | mips16_mark_labels (); |
12116 | ||
12117 | s_stab (type); | |
12118 | } | |
12119 | ||
12120 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12121 | */ | |
12122 | ||
12123 | static void | |
17a2f251 | 12124 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12125 | { |
12126 | char *name; | |
12127 | int c; | |
12128 | symbolS *symbolP; | |
12129 | expressionS exp; | |
12130 | ||
12131 | name = input_line_pointer; | |
12132 | c = get_symbol_end (); | |
12133 | symbolP = symbol_find_or_make (name); | |
12134 | S_SET_WEAK (symbolP); | |
12135 | *input_line_pointer = c; | |
12136 | ||
12137 | SKIP_WHITESPACE (); | |
12138 | ||
12139 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12140 | { | |
12141 | if (S_IS_DEFINED (symbolP)) | |
12142 | { | |
956cd1d6 | 12143 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12144 | S_GET_NAME (symbolP)); |
12145 | ignore_rest_of_line (); | |
12146 | return; | |
12147 | } | |
bdaaa2e1 | 12148 | |
252b5132 RH |
12149 | if (*input_line_pointer == ',') |
12150 | { | |
12151 | ++input_line_pointer; | |
12152 | SKIP_WHITESPACE (); | |
12153 | } | |
bdaaa2e1 | 12154 | |
252b5132 RH |
12155 | expression (&exp); |
12156 | if (exp.X_op != O_symbol) | |
12157 | { | |
12158 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12159 | ignore_rest_of_line (); |
252b5132 RH |
12160 | return; |
12161 | } | |
49309057 | 12162 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12163 | } |
12164 | ||
12165 | demand_empty_rest_of_line (); | |
12166 | } | |
12167 | ||
12168 | /* Parse a register string into a number. Called from the ECOFF code | |
12169 | to parse .frame. The argument is non-zero if this is the frame | |
12170 | register, so that we can record it in mips_frame_reg. */ | |
12171 | ||
12172 | int | |
17a2f251 | 12173 | tc_get_register (int frame) |
252b5132 RH |
12174 | { |
12175 | int reg; | |
12176 | ||
12177 | SKIP_WHITESPACE (); | |
12178 | if (*input_line_pointer++ != '$') | |
12179 | { | |
12180 | as_warn (_("expected `$'")); | |
85b51719 | 12181 | reg = ZERO; |
252b5132 | 12182 | } |
3882b010 | 12183 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12184 | { |
12185 | reg = get_absolute_expression (); | |
12186 | if (reg < 0 || reg >= 32) | |
12187 | { | |
12188 | as_warn (_("Bad register number")); | |
85b51719 | 12189 | reg = ZERO; |
252b5132 RH |
12190 | } |
12191 | } | |
12192 | else | |
12193 | { | |
76db943d | 12194 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12195 | { |
12196 | reg = RA; | |
12197 | input_line_pointer += 2; | |
12198 | } | |
76db943d | 12199 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12200 | { |
12201 | reg = FP; | |
12202 | input_line_pointer += 2; | |
12203 | } | |
252b5132 | 12204 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12205 | { |
12206 | reg = SP; | |
12207 | input_line_pointer += 2; | |
12208 | } | |
252b5132 | 12209 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12210 | { |
12211 | reg = GP; | |
12212 | input_line_pointer += 2; | |
12213 | } | |
252b5132 | 12214 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12215 | { |
12216 | reg = AT; | |
12217 | input_line_pointer += 2; | |
12218 | } | |
12219 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12220 | { | |
12221 | reg = KT0; | |
12222 | input_line_pointer += 3; | |
12223 | } | |
12224 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12225 | { | |
12226 | reg = KT1; | |
12227 | input_line_pointer += 3; | |
12228 | } | |
12229 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12230 | { | |
12231 | reg = ZERO; | |
12232 | input_line_pointer += 4; | |
12233 | } | |
252b5132 RH |
12234 | else |
12235 | { | |
12236 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12237 | reg = ZERO; |
12238 | while (ISALNUM(*input_line_pointer)) | |
12239 | input_line_pointer++; | |
252b5132 | 12240 | } |
252b5132 RH |
12241 | } |
12242 | if (frame) | |
7a621144 DJ |
12243 | { |
12244 | mips_frame_reg = reg != 0 ? reg : SP; | |
12245 | mips_frame_reg_valid = 1; | |
12246 | mips_cprestore_valid = 0; | |
12247 | } | |
252b5132 RH |
12248 | return reg; |
12249 | } | |
12250 | ||
12251 | valueT | |
17a2f251 | 12252 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12253 | { |
12254 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12255 | ||
12256 | #ifdef OBJ_ELF | |
12257 | /* We don't need to align ELF sections to the full alignment. | |
12258 | However, Irix 5 may prefer that we align them at least to a 16 | |
12259 | byte boundary. We don't bother to align the sections if we are | |
12260 | targeted for an embedded system. */ | |
12261 | if (strcmp (TARGET_OS, "elf") == 0) | |
12262 | return addr; | |
12263 | if (align > 4) | |
12264 | align = 4; | |
12265 | #endif | |
12266 | ||
12267 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12268 | } | |
12269 | ||
12270 | /* Utility routine, called from above as well. If called while the | |
12271 | input file is still being read, it's only an approximation. (For | |
12272 | example, a symbol may later become defined which appeared to be | |
12273 | undefined earlier.) */ | |
12274 | ||
12275 | static int | |
17a2f251 | 12276 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12277 | { |
12278 | if (sym == 0) | |
12279 | return 0; | |
12280 | ||
4d0d148d | 12281 | if (g_switch_value > 0) |
252b5132 RH |
12282 | { |
12283 | const char *symname; | |
12284 | int change; | |
12285 | ||
c9914766 | 12286 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12287 | register. It can be if it is smaller than the -G size or if |
12288 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12289 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12290 | they can. */ |
12291 | symname = S_GET_NAME (sym); | |
12292 | if (symname != (const char *) NULL | |
12293 | && (strcmp (symname, "eprol") == 0 | |
12294 | || strcmp (symname, "etext") == 0 | |
12295 | || strcmp (symname, "_gp") == 0 | |
12296 | || strcmp (symname, "edata") == 0 | |
12297 | || strcmp (symname, "_fbss") == 0 | |
12298 | || strcmp (symname, "_fdata") == 0 | |
12299 | || strcmp (symname, "_ftext") == 0 | |
12300 | || strcmp (symname, "end") == 0 | |
12301 | || strcmp (symname, "_gp_disp") == 0)) | |
12302 | change = 1; | |
12303 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12304 | && (0 | |
12305 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12306 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12307 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12308 | <= g_switch_value)) | |
252b5132 RH |
12309 | #endif |
12310 | /* We must defer this decision until after the whole | |
12311 | file has been read, since there might be a .extern | |
12312 | after the first use of this symbol. */ | |
12313 | || (before_relaxing | |
12314 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12315 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12316 | #endif |
12317 | && S_GET_VALUE (sym) == 0) | |
12318 | || (S_GET_VALUE (sym) != 0 | |
12319 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12320 | change = 0; | |
12321 | else | |
12322 | { | |
12323 | const char *segname; | |
12324 | ||
12325 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12326 | assert (strcmp (segname, ".lit8") != 0 | |
12327 | && strcmp (segname, ".lit4") != 0); | |
12328 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12329 | && strcmp (segname, ".sbss") != 0 |
12330 | && strncmp (segname, ".sdata.", 7) != 0 | |
12331 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12332 | } |
12333 | return change; | |
12334 | } | |
12335 | else | |
c9914766 | 12336 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12337 | return 1; |
12338 | } | |
12339 | ||
5919d012 RS |
12340 | |
12341 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12342 | ||
12343 | static bfd_boolean | |
17a2f251 | 12344 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12345 | { |
12346 | asection *symsec; | |
12347 | bfd_boolean linkonce; | |
12348 | ||
12349 | /* Handle the case of a symbol equated to another symbol. */ | |
12350 | while (symbol_equated_reloc_p (sym)) | |
12351 | { | |
12352 | symbolS *n; | |
12353 | ||
12354 | /* It's possible to get a loop here in a badly written | |
12355 | program. */ | |
12356 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12357 | if (n == sym) | |
12358 | break; | |
12359 | sym = n; | |
12360 | } | |
12361 | ||
12362 | symsec = S_GET_SEGMENT (sym); | |
12363 | ||
12364 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12365 | linkonce = FALSE; | |
12366 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12367 | { | |
12368 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12369 | != 0) | |
12370 | linkonce = TRUE; | |
12371 | ||
12372 | /* The GNU toolchain uses an extension for ELF: a section | |
12373 | beginning with the magic string .gnu.linkonce is a linkonce | |
12374 | section. */ | |
12375 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12376 | sizeof ".gnu.linkonce" - 1) == 0) | |
12377 | linkonce = TRUE; | |
12378 | } | |
12379 | ||
12380 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12381 | return (symsec != &bfd_und_section | |
12382 | && symsec != &bfd_abs_section | |
12383 | && ! bfd_is_com_section (symsec) | |
12384 | && !linkonce | |
12385 | #ifdef OBJ_ELF | |
12386 | /* A global or weak symbol is treated as external. */ | |
12387 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12388 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12389 | #endif |
12390 | ); | |
12391 | } | |
12392 | ||
12393 | ||
252b5132 RH |
12394 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12395 | extended opcode. SEC is the section the frag is in. */ | |
12396 | ||
12397 | static int | |
17a2f251 | 12398 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12399 | { |
12400 | int type; | |
12401 | register const struct mips16_immed_operand *op; | |
12402 | offsetT val; | |
12403 | int mintiny, maxtiny; | |
12404 | segT symsec; | |
98aa84af | 12405 | fragS *sym_frag; |
252b5132 RH |
12406 | |
12407 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12408 | return 0; | |
12409 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12410 | return 1; | |
12411 | ||
12412 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12413 | op = mips16_immed_operands; | |
12414 | while (op->type != type) | |
12415 | { | |
12416 | ++op; | |
12417 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12418 | } | |
12419 | ||
12420 | if (op->unsp) | |
12421 | { | |
12422 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12423 | { | |
12424 | mintiny = 1; | |
12425 | maxtiny = 1 << op->nbits; | |
12426 | } | |
12427 | else | |
12428 | { | |
12429 | mintiny = 0; | |
12430 | maxtiny = (1 << op->nbits) - 1; | |
12431 | } | |
12432 | } | |
12433 | else | |
12434 | { | |
12435 | mintiny = - (1 << (op->nbits - 1)); | |
12436 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12437 | } | |
12438 | ||
98aa84af | 12439 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12440 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12441 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12442 | |
12443 | if (op->pcrel) | |
12444 | { | |
12445 | addressT addr; | |
12446 | ||
12447 | /* We won't have the section when we are called from | |
12448 | mips_relax_frag. However, we will always have been called | |
12449 | from md_estimate_size_before_relax first. If this is a | |
12450 | branch to a different section, we mark it as such. If SEC is | |
12451 | NULL, and the frag is not marked, then it must be a branch to | |
12452 | the same section. */ | |
12453 | if (sec == NULL) | |
12454 | { | |
12455 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12456 | return 1; | |
12457 | } | |
12458 | else | |
12459 | { | |
98aa84af | 12460 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12461 | if (symsec != sec) |
12462 | { | |
12463 | fragp->fr_subtype = | |
12464 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12465 | ||
12466 | /* FIXME: We should support this, and let the linker | |
12467 | catch branches and loads that are out of range. */ | |
12468 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12469 | _("unsupported PC relative reference to different section")); | |
12470 | ||
12471 | return 1; | |
12472 | } | |
98aa84af AM |
12473 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12474 | /* Assume non-extended on the first relaxation pass. | |
12475 | The address we have calculated will be bogus if this is | |
12476 | a forward branch to another frag, as the forward frag | |
12477 | will have fr_address == 0. */ | |
12478 | return 0; | |
252b5132 RH |
12479 | } |
12480 | ||
12481 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12482 | the same section. If the relax_marker of the symbol fragment |
12483 | differs from the relax_marker of this fragment, we have not | |
12484 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12485 | in STRETCH in order to get a better estimate of the address. |
12486 | This particularly matters because of the shift bits. */ | |
12487 | if (stretch != 0 | |
98aa84af | 12488 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12489 | { |
12490 | fragS *f; | |
12491 | ||
12492 | /* Adjust stretch for any alignment frag. Note that if have | |
12493 | been expanding the earlier code, the symbol may be | |
12494 | defined in what appears to be an earlier frag. FIXME: | |
12495 | This doesn't handle the fr_subtype field, which specifies | |
12496 | a maximum number of bytes to skip when doing an | |
12497 | alignment. */ | |
98aa84af | 12498 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12499 | { |
12500 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12501 | { | |
12502 | if (stretch < 0) | |
12503 | stretch = - ((- stretch) | |
12504 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12505 | else | |
12506 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12507 | if (stretch == 0) | |
12508 | break; | |
12509 | } | |
12510 | } | |
12511 | if (f != NULL) | |
12512 | val += stretch; | |
12513 | } | |
12514 | ||
12515 | addr = fragp->fr_address + fragp->fr_fix; | |
12516 | ||
12517 | /* The base address rules are complicated. The base address of | |
12518 | a branch is the following instruction. The base address of a | |
12519 | PC relative load or add is the instruction itself, but if it | |
12520 | is in a delay slot (in which case it can not be extended) use | |
12521 | the address of the instruction whose delay slot it is in. */ | |
12522 | if (type == 'p' || type == 'q') | |
12523 | { | |
12524 | addr += 2; | |
12525 | ||
12526 | /* If we are currently assuming that this frag should be | |
12527 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12528 | higher. */ |
252b5132 RH |
12529 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12530 | addr += 2; | |
12531 | ||
12532 | /* Ignore the low bit in the target, since it will be set | |
12533 | for a text label. */ | |
12534 | if ((val & 1) != 0) | |
12535 | --val; | |
12536 | } | |
12537 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12538 | addr -= 4; | |
12539 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12540 | addr -= 2; | |
12541 | ||
12542 | val -= addr & ~ ((1 << op->shift) - 1); | |
12543 | ||
12544 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12545 | if (type == 'p' || type == 'q') | |
12546 | val /= 2; | |
12547 | ||
12548 | /* If any of the shifted bits are set, we must use an extended | |
12549 | opcode. If the address depends on the size of this | |
12550 | instruction, this can lead to a loop, so we arrange to always | |
12551 | use an extended opcode. We only check this when we are in | |
12552 | the main relaxation loop, when SEC is NULL. */ | |
12553 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12554 | { | |
12555 | fragp->fr_subtype = | |
12556 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12557 | return 1; | |
12558 | } | |
12559 | ||
12560 | /* If we are about to mark a frag as extended because the value | |
12561 | is precisely maxtiny + 1, then there is a chance of an | |
12562 | infinite loop as in the following code: | |
12563 | la $4,foo | |
12564 | .skip 1020 | |
12565 | .align 2 | |
12566 | foo: | |
12567 | In this case when the la is extended, foo is 0x3fc bytes | |
12568 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12569 | the la must be extended. To avoid this loop, we mark the | |
12570 | frag as extended if it was small, and is about to become | |
12571 | extended with a value of maxtiny + 1. */ | |
12572 | if (val == ((maxtiny + 1) << op->shift) | |
12573 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12574 | && sec == NULL) | |
12575 | { | |
12576 | fragp->fr_subtype = | |
12577 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12578 | return 1; | |
12579 | } | |
12580 | } | |
12581 | else if (symsec != absolute_section && sec != NULL) | |
12582 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12583 | ||
12584 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12585 | || val < (mintiny << op->shift) | |
12586 | || val > (maxtiny << op->shift)) | |
12587 | return 1; | |
12588 | else | |
12589 | return 0; | |
12590 | } | |
12591 | ||
4a6a3df4 AO |
12592 | /* Compute the length of a branch sequence, and adjust the |
12593 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12594 | worst-case length is computed, with UPDATE being used to indicate | |
12595 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12596 | branch is to be computed. */ | |
12597 | static int | |
17a2f251 | 12598 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12599 | { |
b34976b6 | 12600 | bfd_boolean toofar; |
4a6a3df4 AO |
12601 | int length; |
12602 | ||
12603 | if (fragp | |
12604 | && S_IS_DEFINED (fragp->fr_symbol) | |
12605 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12606 | { | |
12607 | addressT addr; | |
12608 | offsetT val; | |
12609 | ||
12610 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12611 | ||
12612 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12613 | ||
12614 | val -= addr; | |
12615 | ||
12616 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12617 | } | |
12618 | else if (fragp) | |
12619 | /* If the symbol is not defined or it's in a different segment, | |
12620 | assume the user knows what's going on and emit a short | |
12621 | branch. */ | |
b34976b6 | 12622 | toofar = FALSE; |
4a6a3df4 | 12623 | else |
b34976b6 | 12624 | toofar = TRUE; |
4a6a3df4 AO |
12625 | |
12626 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12627 | fragp->fr_subtype | |
af6ae2ad | 12628 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12629 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12630 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12631 | toofar); | |
12632 | ||
12633 | length = 4; | |
12634 | if (toofar) | |
12635 | { | |
12636 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12637 | length += 8; | |
12638 | ||
12639 | if (mips_pic != NO_PIC) | |
12640 | { | |
12641 | /* Additional space for PIC loading of target address. */ | |
12642 | length += 8; | |
12643 | if (mips_opts.isa == ISA_MIPS1) | |
12644 | /* Additional space for $at-stabilizing nop. */ | |
12645 | length += 4; | |
12646 | } | |
12647 | ||
12648 | /* If branch is conditional. */ | |
12649 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12650 | length += 8; | |
12651 | } | |
b34976b6 | 12652 | |
4a6a3df4 AO |
12653 | return length; |
12654 | } | |
12655 | ||
252b5132 RH |
12656 | /* Estimate the size of a frag before relaxing. Unless this is the |
12657 | mips16, we are not really relaxing here, and the final size is | |
12658 | encoded in the subtype information. For the mips16, we have to | |
12659 | decide whether we are using an extended opcode or not. */ | |
12660 | ||
252b5132 | 12661 | int |
17a2f251 | 12662 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12663 | { |
5919d012 | 12664 | int change; |
252b5132 | 12665 | |
4a6a3df4 AO |
12666 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12667 | { | |
12668 | ||
b34976b6 AM |
12669 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12670 | ||
4a6a3df4 AO |
12671 | return fragp->fr_var; |
12672 | } | |
12673 | ||
252b5132 | 12674 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12675 | /* We don't want to modify the EXTENDED bit here; it might get us |
12676 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12677 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12678 | |
12679 | if (mips_pic == NO_PIC) | |
5919d012 | 12680 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12681 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12682 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12683 | else |
12684 | abort (); | |
12685 | ||
12686 | if (change) | |
12687 | { | |
4d7206a2 | 12688 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12689 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12690 | } |
4d7206a2 RS |
12691 | else |
12692 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12693 | } |
12694 | ||
12695 | /* This is called to see whether a reloc against a defined symbol | |
12696 | should be converted into a reloc against a section. Don't adjust | |
12697 | MIPS16 jump relocations, so we don't have to worry about the format | |
12698 | of the offset in the .o file. Don't adjust relocations against | |
12699 | mips16 symbols, so that the linker can find them if it needs to set | |
12700 | up a stub. */ | |
12701 | ||
12702 | int | |
17a2f251 | 12703 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
12704 | { |
12705 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
12706 | return 0; | |
a161fe53 | 12707 | |
252b5132 RH |
12708 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12709 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12710 | return 0; | |
a161fe53 | 12711 | |
252b5132 RH |
12712 | if (fixp->fx_addsy == NULL) |
12713 | return 1; | |
a161fe53 | 12714 | |
252b5132 RH |
12715 | #ifdef OBJ_ELF |
12716 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12717 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12718 | && fixp->fx_subsy == NULL) | |
12719 | return 0; | |
12720 | #endif | |
a161fe53 | 12721 | |
252b5132 RH |
12722 | return 1; |
12723 | } | |
12724 | ||
12725 | /* Translate internal representation of relocation info to BFD target | |
12726 | format. */ | |
12727 | ||
12728 | arelent ** | |
17a2f251 | 12729 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12730 | { |
12731 | static arelent *retval[4]; | |
12732 | arelent *reloc; | |
12733 | bfd_reloc_code_real_type code; | |
12734 | ||
4b0cff4e TS |
12735 | memset (retval, 0, sizeof(retval)); |
12736 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12737 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12738 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12739 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12740 | ||
3e722fb5 CD |
12741 | assert (! fixp->fx_pcrel); |
12742 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12743 | |
438c16b8 TS |
12744 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12745 | entry to be used in the relocation's section offset. */ | |
12746 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12747 | { |
12748 | reloc->address = reloc->addend; | |
12749 | reloc->addend = 0; | |
12750 | } | |
12751 | ||
252b5132 | 12752 | code = fixp->fx_r_type; |
252b5132 | 12753 | |
3e722fb5 CD |
12754 | /* To support a PC relative reloc, we used a Cygnus extension. |
12755 | We check for that here to make sure that we don't let such a | |
12756 | reloc escape normally. (FIXME: This was formerly used by | |
12757 | embedded-PIC support, but is now used by branch handling in | |
12758 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12759 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12760 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12761 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12762 | reloc->howto = NULL; |
12763 | else | |
12764 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12765 | ||
252b5132 RH |
12766 | if (reloc->howto == NULL) |
12767 | { | |
12768 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12769 | _("Can not represent %s relocation in this object file format"), | |
12770 | bfd_get_reloc_code_name (code)); | |
12771 | retval[0] = NULL; | |
12772 | } | |
12773 | ||
12774 | return retval; | |
12775 | } | |
12776 | ||
12777 | /* Relax a machine dependent frag. This returns the amount by which | |
12778 | the current size of the frag should change. */ | |
12779 | ||
12780 | int | |
17a2f251 | 12781 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12782 | { |
4a6a3df4 AO |
12783 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12784 | { | |
12785 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12786 | |
12787 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12788 | |
12789 | return fragp->fr_var - old_var; | |
12790 | } | |
12791 | ||
252b5132 RH |
12792 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12793 | return 0; | |
12794 | ||
c4e7957c | 12795 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12796 | { |
12797 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12798 | return 0; | |
12799 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12800 | return 2; | |
12801 | } | |
12802 | else | |
12803 | { | |
12804 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12805 | return 0; | |
12806 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12807 | return -2; | |
12808 | } | |
12809 | ||
12810 | return 0; | |
12811 | } | |
12812 | ||
12813 | /* Convert a machine dependent frag. */ | |
12814 | ||
12815 | void | |
17a2f251 | 12816 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12817 | { |
4a6a3df4 AO |
12818 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12819 | { | |
12820 | bfd_byte *buf; | |
12821 | unsigned long insn; | |
12822 | expressionS exp; | |
12823 | fixS *fixp; | |
b34976b6 | 12824 | |
4a6a3df4 AO |
12825 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12826 | ||
12827 | if (target_big_endian) | |
12828 | insn = bfd_getb32 (buf); | |
12829 | else | |
12830 | insn = bfd_getl32 (buf); | |
b34976b6 | 12831 | |
4a6a3df4 AO |
12832 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12833 | { | |
12834 | /* We generate a fixup instead of applying it right now | |
12835 | because, if there are linker relaxations, we're going to | |
12836 | need the relocations. */ | |
12837 | exp.X_op = O_symbol; | |
12838 | exp.X_add_symbol = fragp->fr_symbol; | |
12839 | exp.X_add_number = fragp->fr_offset; | |
12840 | ||
12841 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12842 | 4, &exp, 1, |
12843 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12844 | fixp->fx_file = fragp->fr_file; |
12845 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12846 | |
17a2f251 | 12847 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12848 | buf += 4; |
12849 | } | |
12850 | else | |
12851 | { | |
12852 | int i; | |
12853 | ||
12854 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12855 | _("relaxed out-of-range branch into a jump")); | |
12856 | ||
12857 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12858 | goto uncond; | |
12859 | ||
12860 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12861 | { | |
12862 | /* Reverse the branch. */ | |
12863 | switch ((insn >> 28) & 0xf) | |
12864 | { | |
12865 | case 4: | |
12866 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12867 | have the condition reversed by tweaking a single | |
12868 | bit, and their opcodes all have 0x4???????. */ | |
12869 | assert ((insn & 0xf1000000) == 0x41000000); | |
12870 | insn ^= 0x00010000; | |
12871 | break; | |
12872 | ||
12873 | case 0: | |
12874 | /* bltz 0x04000000 bgez 0x04010000 | |
12875 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12876 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12877 | insn ^= 0x00010000; | |
12878 | break; | |
b34976b6 | 12879 | |
4a6a3df4 AO |
12880 | case 1: |
12881 | /* beq 0x10000000 bne 0x14000000 | |
12882 | blez 0x18000000 bgtz 0x1c000000 */ | |
12883 | insn ^= 0x04000000; | |
12884 | break; | |
12885 | ||
12886 | default: | |
12887 | abort (); | |
12888 | } | |
12889 | } | |
12890 | ||
12891 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12892 | { | |
12893 | /* Clear the and-link bit. */ | |
12894 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12895 | ||
12896 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12897 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12898 | insn &= ~0x00100000; | |
12899 | } | |
12900 | ||
12901 | /* Branch over the branch (if the branch was likely) or the | |
12902 | full jump (not likely case). Compute the offset from the | |
12903 | current instruction to branch to. */ | |
12904 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12905 | i = 16; | |
12906 | else | |
12907 | { | |
12908 | /* How many bytes in instructions we've already emitted? */ | |
12909 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12910 | /* How many bytes in instructions from here to the end? */ | |
12911 | i = fragp->fr_var - i; | |
12912 | } | |
12913 | /* Convert to instruction count. */ | |
12914 | i >>= 2; | |
12915 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12916 | i--; |
4a6a3df4 AO |
12917 | insn |= i; |
12918 | /* Branch over the jump. */ | |
17a2f251 | 12919 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12920 | buf += 4; |
12921 | ||
12922 | /* Nop */ | |
17a2f251 | 12923 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12924 | buf += 4; |
12925 | ||
12926 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12927 | { | |
12928 | /* beql $0, $0, 2f */ | |
12929 | insn = 0x50000000; | |
12930 | /* Compute the PC offset from the current instruction to | |
12931 | the end of the variable frag. */ | |
12932 | /* How many bytes in instructions we've already emitted? */ | |
12933 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12934 | /* How many bytes in instructions from here to the end? */ | |
12935 | i = fragp->fr_var - i; | |
12936 | /* Convert to instruction count. */ | |
12937 | i >>= 2; | |
12938 | /* Don't decrement i, because we want to branch over the | |
12939 | delay slot. */ | |
12940 | ||
12941 | insn |= i; | |
17a2f251 | 12942 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12943 | buf += 4; |
12944 | ||
17a2f251 | 12945 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12946 | buf += 4; |
12947 | } | |
12948 | ||
12949 | uncond: | |
12950 | if (mips_pic == NO_PIC) | |
12951 | { | |
12952 | /* j or jal. */ | |
12953 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12954 | ? 0x0c000000 : 0x08000000); | |
12955 | exp.X_op = O_symbol; | |
12956 | exp.X_add_symbol = fragp->fr_symbol; | |
12957 | exp.X_add_number = fragp->fr_offset; | |
12958 | ||
12959 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12960 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
12961 | fixp->fx_file = fragp->fr_file; | |
12962 | fixp->fx_line = fragp->fr_line; | |
12963 | ||
17a2f251 | 12964 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12965 | buf += 4; |
12966 | } | |
12967 | else | |
12968 | { | |
12969 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
12970 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
12971 | exp.X_op = O_symbol; | |
12972 | exp.X_add_symbol = fragp->fr_symbol; | |
12973 | exp.X_add_number = fragp->fr_offset; | |
12974 | ||
12975 | if (fragp->fr_offset) | |
12976 | { | |
12977 | exp.X_add_symbol = make_expr_symbol (&exp); | |
12978 | exp.X_add_number = 0; | |
12979 | } | |
12980 | ||
12981 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12982 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
12983 | fixp->fx_file = fragp->fr_file; | |
12984 | fixp->fx_line = fragp->fr_line; | |
12985 | ||
17a2f251 | 12986 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 12987 | buf += 4; |
b34976b6 | 12988 | |
4a6a3df4 AO |
12989 | if (mips_opts.isa == ISA_MIPS1) |
12990 | { | |
12991 | /* nop */ | |
17a2f251 | 12992 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12993 | buf += 4; |
12994 | } | |
12995 | ||
12996 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
12997 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
12998 | ||
12999 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13000 | 4, &exp, 0, BFD_RELOC_LO16); | |
13001 | fixp->fx_file = fragp->fr_file; | |
13002 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13003 | |
17a2f251 | 13004 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13005 | buf += 4; |
13006 | ||
13007 | /* j(al)r $at. */ | |
13008 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13009 | insn = 0x0020f809; | |
13010 | else | |
13011 | insn = 0x00200008; | |
13012 | ||
17a2f251 | 13013 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13014 | buf += 4; |
13015 | } | |
13016 | } | |
13017 | ||
13018 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13019 | + fragp->fr_fix + fragp->fr_var); | |
13020 | ||
13021 | fragp->fr_fix += fragp->fr_var; | |
13022 | ||
13023 | return; | |
13024 | } | |
13025 | ||
252b5132 RH |
13026 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13027 | { | |
13028 | int type; | |
13029 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13030 | bfd_boolean small, ext; |
252b5132 RH |
13031 | offsetT val; |
13032 | bfd_byte *buf; | |
13033 | unsigned long insn; | |
b34976b6 | 13034 | bfd_boolean use_extend; |
252b5132 RH |
13035 | unsigned short extend; |
13036 | ||
13037 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13038 | op = mips16_immed_operands; | |
13039 | while (op->type != type) | |
13040 | ++op; | |
13041 | ||
13042 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13043 | { | |
b34976b6 AM |
13044 | small = FALSE; |
13045 | ext = TRUE; | |
252b5132 RH |
13046 | } |
13047 | else | |
13048 | { | |
b34976b6 AM |
13049 | small = TRUE; |
13050 | ext = FALSE; | |
252b5132 RH |
13051 | } |
13052 | ||
6386f3a7 | 13053 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13054 | val = S_GET_VALUE (fragp->fr_symbol); |
13055 | if (op->pcrel) | |
13056 | { | |
13057 | addressT addr; | |
13058 | ||
13059 | addr = fragp->fr_address + fragp->fr_fix; | |
13060 | ||
13061 | /* The rules for the base address of a PC relative reloc are | |
13062 | complicated; see mips16_extended_frag. */ | |
13063 | if (type == 'p' || type == 'q') | |
13064 | { | |
13065 | addr += 2; | |
13066 | if (ext) | |
13067 | addr += 2; | |
13068 | /* Ignore the low bit in the target, since it will be | |
13069 | set for a text label. */ | |
13070 | if ((val & 1) != 0) | |
13071 | --val; | |
13072 | } | |
13073 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13074 | addr -= 4; | |
13075 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13076 | addr -= 2; | |
13077 | ||
13078 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13079 | val -= addr; | |
13080 | ||
13081 | /* Make sure the section winds up with the alignment we have | |
13082 | assumed. */ | |
13083 | if (op->shift > 0) | |
13084 | record_alignment (asec, op->shift); | |
13085 | } | |
13086 | ||
13087 | if (ext | |
13088 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13089 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13090 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13091 | _("extended instruction in delay slot")); | |
13092 | ||
13093 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13094 | ||
13095 | if (target_big_endian) | |
13096 | insn = bfd_getb16 (buf); | |
13097 | else | |
13098 | insn = bfd_getl16 (buf); | |
13099 | ||
13100 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13101 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13102 | small, ext, &insn, &use_extend, &extend); | |
13103 | ||
13104 | if (use_extend) | |
13105 | { | |
17a2f251 | 13106 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13107 | fragp->fr_fix += 2; |
13108 | buf += 2; | |
13109 | } | |
13110 | ||
17a2f251 | 13111 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13112 | fragp->fr_fix += 2; |
13113 | buf += 2; | |
13114 | } | |
13115 | else | |
13116 | { | |
4d7206a2 RS |
13117 | int first, second; |
13118 | fixS *fixp; | |
252b5132 | 13119 | |
4d7206a2 RS |
13120 | first = RELAX_FIRST (fragp->fr_subtype); |
13121 | second = RELAX_SECOND (fragp->fr_subtype); | |
13122 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13123 | |
584892a6 RS |
13124 | /* Possibly emit a warning if we've chosen the longer option. */ |
13125 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13126 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13127 | { | |
13128 | const char *msg = macro_warning (fragp->fr_subtype); | |
13129 | if (msg != 0) | |
13130 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13131 | } | |
13132 | ||
4d7206a2 RS |
13133 | /* Go through all the fixups for the first sequence. Disable them |
13134 | (by marking them as done) if we're going to use the second | |
13135 | sequence instead. */ | |
13136 | while (fixp | |
13137 | && fixp->fx_frag == fragp | |
13138 | && fixp->fx_where < fragp->fr_fix - second) | |
13139 | { | |
13140 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13141 | fixp->fx_done = 1; | |
13142 | fixp = fixp->fx_next; | |
13143 | } | |
252b5132 | 13144 | |
4d7206a2 RS |
13145 | /* Go through the fixups for the second sequence. Disable them if |
13146 | we're going to use the first sequence, otherwise adjust their | |
13147 | addresses to account for the relaxation. */ | |
13148 | while (fixp && fixp->fx_frag == fragp) | |
13149 | { | |
13150 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13151 | fixp->fx_where -= first; | |
13152 | else | |
13153 | fixp->fx_done = 1; | |
13154 | fixp = fixp->fx_next; | |
13155 | } | |
13156 | ||
13157 | /* Now modify the frag contents. */ | |
13158 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13159 | { | |
13160 | char *start; | |
13161 | ||
13162 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13163 | memmove (start, start + first, second); | |
13164 | fragp->fr_fix -= first; | |
13165 | } | |
13166 | else | |
13167 | fragp->fr_fix -= second; | |
252b5132 RH |
13168 | } |
13169 | } | |
13170 | ||
13171 | #ifdef OBJ_ELF | |
13172 | ||
13173 | /* This function is called after the relocs have been generated. | |
13174 | We've been storing mips16 text labels as odd. Here we convert them | |
13175 | back to even for the convenience of the debugger. */ | |
13176 | ||
13177 | void | |
17a2f251 | 13178 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13179 | { |
13180 | asymbol **syms; | |
13181 | unsigned int count, i; | |
13182 | ||
13183 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13184 | return; | |
13185 | ||
13186 | syms = bfd_get_outsymbols (stdoutput); | |
13187 | count = bfd_get_symcount (stdoutput); | |
13188 | for (i = 0; i < count; i++, syms++) | |
13189 | { | |
13190 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13191 | && ((*syms)->value & 1) != 0) | |
13192 | { | |
13193 | (*syms)->value &= ~1; | |
13194 | /* If the symbol has an odd size, it was probably computed | |
13195 | incorrectly, so adjust that as well. */ | |
13196 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13197 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13198 | } | |
13199 | } | |
13200 | } | |
13201 | ||
13202 | #endif | |
13203 | ||
13204 | /* This function is called whenever a label is defined. It is used | |
13205 | when handling branch delays; if a branch has a label, we assume we | |
13206 | can not move it. */ | |
13207 | ||
13208 | void | |
17a2f251 | 13209 | mips_define_label (symbolS *sym) |
252b5132 RH |
13210 | { |
13211 | struct insn_label_list *l; | |
13212 | ||
13213 | if (free_insn_labels == NULL) | |
13214 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13215 | else | |
13216 | { | |
13217 | l = free_insn_labels; | |
13218 | free_insn_labels = l->next; | |
13219 | } | |
13220 | ||
13221 | l->label = sym; | |
13222 | l->next = insn_labels; | |
13223 | insn_labels = l; | |
13224 | } | |
13225 | \f | |
13226 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13227 | ||
13228 | /* Some special processing for a MIPS ELF file. */ | |
13229 | ||
13230 | void | |
17a2f251 | 13231 | mips_elf_final_processing (void) |
252b5132 RH |
13232 | { |
13233 | /* Write out the register information. */ | |
316f5878 | 13234 | if (mips_abi != N64_ABI) |
252b5132 RH |
13235 | { |
13236 | Elf32_RegInfo s; | |
13237 | ||
13238 | s.ri_gprmask = mips_gprmask; | |
13239 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13240 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13241 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13242 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13243 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13244 | ||
13245 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13246 | ((Elf32_External_RegInfo *) | |
13247 | mips_regmask_frag)); | |
13248 | } | |
13249 | else | |
13250 | { | |
13251 | Elf64_Internal_RegInfo s; | |
13252 | ||
13253 | s.ri_gprmask = mips_gprmask; | |
13254 | s.ri_pad = 0; | |
13255 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13256 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13257 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13258 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13259 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13260 | ||
13261 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13262 | ((Elf64_External_RegInfo *) | |
13263 | mips_regmask_frag)); | |
13264 | } | |
13265 | ||
13266 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13267 | sort of BFD interface for this. */ | |
13268 | if (mips_any_noreorder) | |
13269 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13270 | if (mips_pic != NO_PIC) | |
143d77c5 | 13271 | { |
252b5132 | 13272 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13273 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13274 | } | |
13275 | if (mips_abicalls) | |
13276 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13277 | |
98d3f06f | 13278 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13279 | if (file_ase_mips16) |
13280 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13281 | #if 0 /* XXX FIXME */ |
13282 | if (file_ase_mips3d) | |
13283 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13284 | #endif | |
deec1734 CD |
13285 | if (file_ase_mdmx) |
13286 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13287 | |
bdaaa2e1 | 13288 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13289 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13290 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13291 | else if (mips_abi == O64_ABI) |
252b5132 | 13292 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13293 | else if (mips_abi == EABI_ABI) |
252b5132 | 13294 | { |
316f5878 | 13295 | if (!file_mips_gp32) |
252b5132 RH |
13296 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13297 | else | |
13298 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13299 | } | |
316f5878 | 13300 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13301 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13302 | ||
c9914766 | 13303 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13304 | |
13305 | if (mips_32bitmode) | |
13306 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13307 | } | |
13308 | ||
13309 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13310 | \f | |
beae10d5 KH |
13311 | typedef struct proc { |
13312 | symbolS *isym; | |
13313 | unsigned long reg_mask; | |
13314 | unsigned long reg_offset; | |
13315 | unsigned long fpreg_mask; | |
13316 | unsigned long fpreg_offset; | |
13317 | unsigned long frame_offset; | |
13318 | unsigned long frame_reg; | |
13319 | unsigned long pc_reg; | |
13320 | } procS; | |
252b5132 RH |
13321 | |
13322 | static procS cur_proc; | |
13323 | static procS *cur_proc_ptr; | |
13324 | static int numprocs; | |
13325 | ||
0a9ef439 | 13326 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13327 | |
0a9ef439 | 13328 | void |
17a2f251 | 13329 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13330 | { |
0a9ef439 RH |
13331 | if (fragp->fr_type != rs_align_code) |
13332 | return; | |
13333 | ||
13334 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13335 | { |
13336 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13337 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13338 | ||
0a9ef439 RH |
13339 | int bytes; |
13340 | char *p; | |
a19d8eb0 | 13341 | |
0a9ef439 RH |
13342 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13343 | p = fragp->fr_literal + fragp->fr_fix; | |
13344 | ||
13345 | if (bytes & 1) | |
13346 | { | |
13347 | *p++ = 0; | |
f9419b05 | 13348 | fragp->fr_fix++; |
0a9ef439 RH |
13349 | } |
13350 | ||
13351 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13352 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13353 | } |
13354 | ||
0a9ef439 | 13355 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13356 | } |
13357 | ||
252b5132 | 13358 | static void |
17a2f251 | 13359 | md_obj_begin (void) |
252b5132 RH |
13360 | { |
13361 | } | |
13362 | ||
13363 | static void | |
17a2f251 | 13364 | md_obj_end (void) |
252b5132 RH |
13365 | { |
13366 | /* check for premature end, nesting errors, etc */ | |
13367 | if (cur_proc_ptr) | |
9a41af64 | 13368 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13369 | } |
13370 | ||
13371 | static long | |
17a2f251 | 13372 | get_number (void) |
252b5132 RH |
13373 | { |
13374 | int negative = 0; | |
13375 | long val = 0; | |
13376 | ||
13377 | if (*input_line_pointer == '-') | |
13378 | { | |
13379 | ++input_line_pointer; | |
13380 | negative = 1; | |
13381 | } | |
3882b010 | 13382 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13383 | as_bad (_("expected simple number")); |
252b5132 RH |
13384 | if (input_line_pointer[0] == '0') |
13385 | { | |
13386 | if (input_line_pointer[1] == 'x') | |
13387 | { | |
13388 | input_line_pointer += 2; | |
3882b010 | 13389 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13390 | { |
13391 | val <<= 4; | |
13392 | val |= hex_value (*input_line_pointer++); | |
13393 | } | |
13394 | return negative ? -val : val; | |
13395 | } | |
13396 | else | |
13397 | { | |
13398 | ++input_line_pointer; | |
3882b010 | 13399 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13400 | { |
13401 | val <<= 3; | |
13402 | val |= *input_line_pointer++ - '0'; | |
13403 | } | |
13404 | return negative ? -val : val; | |
13405 | } | |
13406 | } | |
3882b010 | 13407 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13408 | { |
13409 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13410 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13411 | as_warn (_("invalid number")); |
252b5132 RH |
13412 | return -1; |
13413 | } | |
3882b010 | 13414 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13415 | { |
13416 | val *= 10; | |
13417 | val += *input_line_pointer++ - '0'; | |
13418 | } | |
13419 | return negative ? -val : val; | |
13420 | } | |
13421 | ||
13422 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13423 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13424 | case .file implies DWARF-2. */ | |
13425 | ||
13426 | static void | |
17a2f251 | 13427 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13428 | { |
ecb4347a DJ |
13429 | static int first_file_directive = 0; |
13430 | ||
c5dd6aab DJ |
13431 | if (ECOFF_DEBUGGING) |
13432 | { | |
13433 | get_number (); | |
13434 | s_app_file (0); | |
13435 | } | |
13436 | else | |
ecb4347a DJ |
13437 | { |
13438 | char *filename; | |
13439 | ||
13440 | filename = dwarf2_directive_file (0); | |
13441 | ||
13442 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13443 | directive even for stabs output. Make sure that this | |
13444 | ".file" is handled. Note that you need a version of GCC | |
13445 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13446 | if (filename != NULL && ! first_file_directive) | |
13447 | { | |
13448 | (void) new_logical_line (filename, -1); | |
13449 | s_app_file_string (filename); | |
13450 | } | |
13451 | first_file_directive = 1; | |
13452 | } | |
c5dd6aab DJ |
13453 | } |
13454 | ||
13455 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13456 | |
13457 | static void | |
17a2f251 | 13458 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13459 | { |
c5dd6aab DJ |
13460 | if (!ECOFF_DEBUGGING) |
13461 | dwarf2_directive_loc (0); | |
252b5132 RH |
13462 | } |
13463 | ||
252b5132 RH |
13464 | /* The .end directive. */ |
13465 | ||
13466 | static void | |
17a2f251 | 13467 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13468 | { |
13469 | symbolS *p; | |
252b5132 | 13470 | |
7a621144 DJ |
13471 | /* Following functions need their own .frame and .cprestore directives. */ |
13472 | mips_frame_reg_valid = 0; | |
13473 | mips_cprestore_valid = 0; | |
13474 | ||
252b5132 RH |
13475 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13476 | { | |
13477 | p = get_symbol (); | |
13478 | demand_empty_rest_of_line (); | |
13479 | } | |
13480 | else | |
13481 | p = NULL; | |
13482 | ||
14949570 | 13483 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13484 | as_warn (_(".end not in text section")); |
13485 | ||
13486 | if (!cur_proc_ptr) | |
13487 | { | |
13488 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13489 | demand_empty_rest_of_line (); | |
13490 | return; | |
13491 | } | |
13492 | ||
13493 | if (p != NULL) | |
13494 | { | |
13495 | assert (S_GET_NAME (p)); | |
13496 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13497 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13498 | |
13499 | if (debug_type == DEBUG_STABS) | |
13500 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13501 | S_GET_NAME (p)); | |
252b5132 RH |
13502 | } |
13503 | else | |
13504 | as_warn (_(".end directive missing or unknown symbol")); | |
13505 | ||
ecb4347a DJ |
13506 | #ifdef OBJ_ELF |
13507 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13508 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13509 | && mips_flag_pdr) | |
ecb4347a DJ |
13510 | { |
13511 | segT saved_seg = now_seg; | |
13512 | subsegT saved_subseg = now_subseg; | |
13513 | valueT dot; | |
13514 | expressionS exp; | |
13515 | char *fragp; | |
252b5132 | 13516 | |
ecb4347a | 13517 | dot = frag_now_fix (); |
252b5132 RH |
13518 | |
13519 | #ifdef md_flush_pending_output | |
ecb4347a | 13520 | md_flush_pending_output (); |
252b5132 RH |
13521 | #endif |
13522 | ||
ecb4347a DJ |
13523 | assert (pdr_seg); |
13524 | subseg_set (pdr_seg, 0); | |
252b5132 | 13525 | |
ecb4347a DJ |
13526 | /* Write the symbol. */ |
13527 | exp.X_op = O_symbol; | |
13528 | exp.X_add_symbol = p; | |
13529 | exp.X_add_number = 0; | |
13530 | emit_expr (&exp, 4); | |
252b5132 | 13531 | |
ecb4347a | 13532 | fragp = frag_more (7 * 4); |
252b5132 | 13533 | |
17a2f251 TS |
13534 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13535 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13536 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13537 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13538 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13539 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13540 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13541 | |
ecb4347a DJ |
13542 | subseg_set (saved_seg, saved_subseg); |
13543 | } | |
13544 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13545 | |
13546 | cur_proc_ptr = NULL; | |
13547 | } | |
13548 | ||
13549 | /* The .aent and .ent directives. */ | |
13550 | ||
13551 | static void | |
17a2f251 | 13552 | s_mips_ent (int aent) |
252b5132 | 13553 | { |
252b5132 | 13554 | symbolS *symbolP; |
252b5132 RH |
13555 | |
13556 | symbolP = get_symbol (); | |
13557 | if (*input_line_pointer == ',') | |
f9419b05 | 13558 | ++input_line_pointer; |
252b5132 | 13559 | SKIP_WHITESPACE (); |
3882b010 | 13560 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13561 | || *input_line_pointer == '-') |
874e8986 | 13562 | get_number (); |
252b5132 | 13563 | |
14949570 | 13564 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13565 | as_warn (_(".ent or .aent not in text section.")); |
13566 | ||
13567 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13568 | as_warn (_("missing .end")); |
252b5132 RH |
13569 | |
13570 | if (!aent) | |
13571 | { | |
7a621144 DJ |
13572 | /* This function needs its own .frame and .cprestore directives. */ |
13573 | mips_frame_reg_valid = 0; | |
13574 | mips_cprestore_valid = 0; | |
13575 | ||
252b5132 RH |
13576 | cur_proc_ptr = &cur_proc; |
13577 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13578 | ||
13579 | cur_proc_ptr->isym = symbolP; | |
13580 | ||
49309057 | 13581 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13582 | |
f9419b05 | 13583 | ++numprocs; |
ecb4347a DJ |
13584 | |
13585 | if (debug_type == DEBUG_STABS) | |
13586 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13587 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13588 | } |
13589 | ||
13590 | demand_empty_rest_of_line (); | |
13591 | } | |
13592 | ||
13593 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13594 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13595 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13596 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13597 | symbol table (in the mdebug section). */ |
13598 | ||
13599 | static void | |
17a2f251 | 13600 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13601 | { |
ecb4347a DJ |
13602 | #ifdef OBJ_ELF |
13603 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13604 | { | |
13605 | long val; | |
252b5132 | 13606 | |
ecb4347a DJ |
13607 | if (cur_proc_ptr == (procS *) NULL) |
13608 | { | |
13609 | as_warn (_(".frame outside of .ent")); | |
13610 | demand_empty_rest_of_line (); | |
13611 | return; | |
13612 | } | |
252b5132 | 13613 | |
ecb4347a DJ |
13614 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13615 | ||
13616 | SKIP_WHITESPACE (); | |
13617 | if (*input_line_pointer++ != ',' | |
13618 | || get_absolute_expression_and_terminator (&val) != ',') | |
13619 | { | |
13620 | as_warn (_("Bad .frame directive")); | |
13621 | --input_line_pointer; | |
13622 | demand_empty_rest_of_line (); | |
13623 | return; | |
13624 | } | |
252b5132 | 13625 | |
ecb4347a DJ |
13626 | cur_proc_ptr->frame_offset = val; |
13627 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13628 | |
252b5132 | 13629 | demand_empty_rest_of_line (); |
252b5132 | 13630 | } |
ecb4347a DJ |
13631 | else |
13632 | #endif /* OBJ_ELF */ | |
13633 | s_ignore (ignore); | |
252b5132 RH |
13634 | } |
13635 | ||
bdaaa2e1 KH |
13636 | /* The .fmask and .mask directives. If the mdebug section is present |
13637 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13638 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13639 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13640 | make reference to the ecoff symbol table (in the mdebug section). */ |
13641 | ||
13642 | static void | |
17a2f251 | 13643 | s_mips_mask (int reg_type) |
252b5132 | 13644 | { |
ecb4347a DJ |
13645 | #ifdef OBJ_ELF |
13646 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13647 | { |
ecb4347a | 13648 | long mask, off; |
252b5132 | 13649 | |
ecb4347a DJ |
13650 | if (cur_proc_ptr == (procS *) NULL) |
13651 | { | |
13652 | as_warn (_(".mask/.fmask outside of .ent")); | |
13653 | demand_empty_rest_of_line (); | |
13654 | return; | |
13655 | } | |
252b5132 | 13656 | |
ecb4347a DJ |
13657 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13658 | { | |
13659 | as_warn (_("Bad .mask/.fmask directive")); | |
13660 | --input_line_pointer; | |
13661 | demand_empty_rest_of_line (); | |
13662 | return; | |
13663 | } | |
252b5132 | 13664 | |
ecb4347a DJ |
13665 | off = get_absolute_expression (); |
13666 | ||
13667 | if (reg_type == 'F') | |
13668 | { | |
13669 | cur_proc_ptr->fpreg_mask = mask; | |
13670 | cur_proc_ptr->fpreg_offset = off; | |
13671 | } | |
13672 | else | |
13673 | { | |
13674 | cur_proc_ptr->reg_mask = mask; | |
13675 | cur_proc_ptr->reg_offset = off; | |
13676 | } | |
13677 | ||
13678 | demand_empty_rest_of_line (); | |
252b5132 RH |
13679 | } |
13680 | else | |
ecb4347a DJ |
13681 | #endif /* OBJ_ELF */ |
13682 | s_ignore (reg_type); | |
252b5132 RH |
13683 | } |
13684 | ||
13685 | /* The .loc directive. */ | |
13686 | ||
13687 | #if 0 | |
13688 | static void | |
17a2f251 | 13689 | s_loc (int x) |
252b5132 RH |
13690 | { |
13691 | symbolS *symbolP; | |
13692 | int lineno; | |
13693 | int addroff; | |
13694 | ||
13695 | assert (now_seg == text_section); | |
13696 | ||
13697 | lineno = get_number (); | |
13698 | addroff = frag_now_fix (); | |
13699 | ||
13700 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13701 | S_SET_TYPE (symbolP, N_SLINE); | |
13702 | S_SET_OTHER (symbolP, 0); | |
13703 | S_SET_DESC (symbolP, lineno); | |
13704 | symbolP->sy_segment = now_seg; | |
13705 | } | |
13706 | #endif | |
e7af610e | 13707 | |
316f5878 RS |
13708 | /* A table describing all the processors gas knows about. Names are |
13709 | matched in the order listed. | |
e7af610e | 13710 | |
316f5878 RS |
13711 | To ease comparison, please keep this table in the same order as |
13712 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13713 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13714 | { | |
316f5878 RS |
13715 | /* Entries for generic ISAs */ |
13716 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13717 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13718 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13719 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13720 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13721 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13722 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13723 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13724 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13725 | |
13726 | /* MIPS I */ | |
13727 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13728 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13729 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13730 | ||
13731 | /* MIPS II */ | |
13732 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13733 | ||
13734 | /* MIPS III */ | |
13735 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13736 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13737 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13738 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13739 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13740 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13741 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13742 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13743 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13744 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13745 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13746 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13747 | ||
13748 | /* MIPS IV */ | |
13749 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13750 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13751 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13752 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13753 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13754 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13755 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13756 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13757 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13758 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13759 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
13760 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
13761 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
13762 | |
13763 | /* MIPS 32 */ | |
fef14a42 | 13764 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13765 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13766 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13767 | |
316f5878 RS |
13768 | /* MIPS 64 */ |
13769 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13770 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13771 | |
c7a23324 | 13772 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13773 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13774 | |
316f5878 RS |
13775 | /* End marker */ |
13776 | { NULL, 0, 0, 0 } | |
13777 | }; | |
e7af610e | 13778 | |
84ea6cf2 | 13779 | |
316f5878 RS |
13780 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13781 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13782 | |
316f5878 | 13783 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13784 | |
b34976b6 | 13785 | static bfd_boolean |
17a2f251 | 13786 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13787 | { |
13788 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13789 | given++, canonical++; | |
13790 | ||
13791 | return ((*given == 0 && *canonical == 0) | |
13792 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13793 | } | |
13794 | ||
13795 | ||
13796 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13797 | CPU name. We've traditionally allowed a lot of variation here. | |
13798 | ||
13799 | Note: this function is shared between GCC and GAS. */ | |
13800 | ||
b34976b6 | 13801 | static bfd_boolean |
17a2f251 | 13802 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13803 | { |
13804 | /* First see if the name matches exactly, or with a final "000" | |
13805 | turned into "k". */ | |
13806 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13807 | return TRUE; |
316f5878 RS |
13808 | |
13809 | /* If not, try comparing based on numerical designation alone. | |
13810 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13811 | if (TOLOWER (*given) == 'r') | |
13812 | given++; | |
13813 | if (!ISDIGIT (*given)) | |
b34976b6 | 13814 | return FALSE; |
316f5878 RS |
13815 | |
13816 | /* Skip over some well-known prefixes in the canonical name, | |
13817 | hoping to find a number there too. */ | |
13818 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13819 | canonical += 2; | |
13820 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13821 | canonical += 2; | |
13822 | else if (TOLOWER (canonical[0]) == 'r') | |
13823 | canonical += 1; | |
13824 | ||
13825 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13826 | } | |
13827 | ||
13828 | ||
13829 | /* Parse an option that takes the name of a processor as its argument. | |
13830 | OPTION is the name of the option and CPU_STRING is the argument. | |
13831 | Return the corresponding processor enumeration if the CPU_STRING is | |
13832 | recognized, otherwise report an error and return null. | |
13833 | ||
13834 | A similar function exists in GCC. */ | |
e7af610e NC |
13835 | |
13836 | static const struct mips_cpu_info * | |
17a2f251 | 13837 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13838 | { |
316f5878 | 13839 | const struct mips_cpu_info *p; |
e7af610e | 13840 | |
316f5878 RS |
13841 | /* 'from-abi' selects the most compatible architecture for the given |
13842 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13843 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13844 | version. Look first at the -mgp options, if given, otherwise base | |
13845 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13846 | |
316f5878 RS |
13847 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13848 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13849 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13850 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13851 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13852 | { | |
13853 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13854 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13855 | ||
13856 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13857 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13858 | ||
13859 | if (file_mips_gp32 >= 0) | |
13860 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13861 | ||
13862 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13863 | ? ISA_MIPS3 | |
13864 | : ISA_MIPS1); | |
13865 | } | |
13866 | ||
13867 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13868 | if (strcasecmp (cpu_string, "default") == 0) | |
13869 | return 0; | |
13870 | ||
13871 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13872 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13873 | return p; | |
13874 | ||
13875 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13876 | return 0; | |
e7af610e NC |
13877 | } |
13878 | ||
316f5878 RS |
13879 | /* Return the canonical processor information for ISA (a member of the |
13880 | ISA_MIPS* enumeration). */ | |
13881 | ||
e7af610e | 13882 | static const struct mips_cpu_info * |
17a2f251 | 13883 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13884 | { |
13885 | int i; | |
13886 | ||
13887 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13888 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13889 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13890 | return (&mips_cpu_info_table[i]); |
13891 | ||
e972090a | 13892 | return NULL; |
e7af610e | 13893 | } |
fef14a42 TS |
13894 | |
13895 | static const struct mips_cpu_info * | |
17a2f251 | 13896 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13897 | { |
13898 | int i; | |
13899 | ||
13900 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13901 | if (arch == mips_cpu_info_table[i].cpu) | |
13902 | return (&mips_cpu_info_table[i]); | |
13903 | ||
13904 | return NULL; | |
13905 | } | |
316f5878 RS |
13906 | \f |
13907 | static void | |
17a2f251 | 13908 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13909 | { |
13910 | if (*first_p) | |
13911 | { | |
13912 | fprintf (stream, "%24s", ""); | |
13913 | *col_p = 24; | |
13914 | } | |
13915 | else | |
13916 | { | |
13917 | fprintf (stream, ", "); | |
13918 | *col_p += 2; | |
13919 | } | |
e7af610e | 13920 | |
316f5878 RS |
13921 | if (*col_p + strlen (string) > 72) |
13922 | { | |
13923 | fprintf (stream, "\n%24s", ""); | |
13924 | *col_p = 24; | |
13925 | } | |
13926 | ||
13927 | fprintf (stream, "%s", string); | |
13928 | *col_p += strlen (string); | |
13929 | ||
13930 | *first_p = 0; | |
13931 | } | |
13932 | ||
13933 | void | |
17a2f251 | 13934 | md_show_usage (FILE *stream) |
e7af610e | 13935 | { |
316f5878 RS |
13936 | int column, first; |
13937 | size_t i; | |
13938 | ||
13939 | fprintf (stream, _("\ | |
13940 | MIPS options:\n\ | |
316f5878 RS |
13941 | -EB generate big endian output\n\ |
13942 | -EL generate little endian output\n\ | |
13943 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13944 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13945 | implicitly with the gp register [default 8]\n")); | |
13946 | fprintf (stream, _("\ | |
13947 | -mips1 generate MIPS ISA I instructions\n\ | |
13948 | -mips2 generate MIPS ISA II instructions\n\ | |
13949 | -mips3 generate MIPS ISA III instructions\n\ | |
13950 | -mips4 generate MIPS ISA IV instructions\n\ | |
13951 | -mips5 generate MIPS ISA V instructions\n\ | |
13952 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13953 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13954 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13955 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13956 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13957 | ||
13958 | first = 1; | |
e7af610e NC |
13959 | |
13960 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13961 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13962 | show (stream, "from-abi", &column, &first); | |
13963 | fputc ('\n', stream); | |
e7af610e | 13964 | |
316f5878 RS |
13965 | fprintf (stream, _("\ |
13966 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13967 | -no-mCPU don't generate code specific to CPU.\n\ | |
13968 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13969 | ||
13970 | first = 1; | |
13971 | ||
13972 | show (stream, "3900", &column, &first); | |
13973 | show (stream, "4010", &column, &first); | |
13974 | show (stream, "4100", &column, &first); | |
13975 | show (stream, "4650", &column, &first); | |
13976 | fputc ('\n', stream); | |
13977 | ||
13978 | fprintf (stream, _("\ | |
13979 | -mips16 generate mips16 instructions\n\ | |
13980 | -no-mips16 do not generate mips16 instructions\n")); | |
13981 | fprintf (stream, _("\ | |
d766e8ec | 13982 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
13983 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
13984 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
13985 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
13986 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
13987 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
13988 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
13989 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
13990 | #ifdef OBJ_ELF | |
13991 | fprintf (stream, _("\ | |
13992 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
13993 | -non_shared do not generate position independent code\n\ | |
13994 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 13995 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
13996 | -mabi=ABI create ABI conformant object file for:\n")); |
13997 | ||
13998 | first = 1; | |
13999 | ||
14000 | show (stream, "32", &column, &first); | |
14001 | show (stream, "o64", &column, &first); | |
14002 | show (stream, "n32", &column, &first); | |
14003 | show (stream, "64", &column, &first); | |
14004 | show (stream, "eabi", &column, &first); | |
14005 | ||
14006 | fputc ('\n', stream); | |
14007 | ||
14008 | fprintf (stream, _("\ | |
14009 | -32 create o32 ABI object file (default)\n\ | |
14010 | -n32 create n32 ABI object file\n\ | |
14011 | -64 create 64 ABI object file\n")); | |
14012 | #endif | |
e7af610e | 14013 | } |
14e777e0 KB |
14014 | |
14015 | enum dwarf2_format | |
17a2f251 | 14016 | mips_dwarf2_format (void) |
14e777e0 KB |
14017 | { |
14018 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14019 | { |
14020 | #ifdef TE_IRIX | |
14021 | return dwarf2_format_64bit_irix; | |
14022 | #else | |
14023 | return dwarf2_format_64bit; | |
14024 | #endif | |
14025 | } | |
14e777e0 KB |
14026 | else |
14027 | return dwarf2_format_32bit; | |
14028 | } | |
73369e65 EC |
14029 | |
14030 | int | |
14031 | mips_dwarf2_addr_size (void) | |
14032 | { | |
14033 | if (mips_abi == N64_ABI) | |
14034 | return 8; | |
73369e65 EC |
14035 | else |
14036 | return 4; | |
14037 | } |