Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
159 | }; |
160 | ||
a325df1d TS |
161 | /* The ABI to use. */ |
162 | enum mips_abi_level | |
163 | { | |
164 | NO_ABI = 0, | |
165 | O32_ABI, | |
166 | O64_ABI, | |
167 | N32_ABI, | |
168 | N64_ABI, | |
169 | EABI_ABI | |
170 | }; | |
171 | ||
172 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 173 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 174 | |
143d77c5 EC |
175 | /* Whether or not we have code that can call pic code. */ |
176 | int mips_abicalls = FALSE; | |
177 | ||
aa6975fb ILT |
178 | /* Whether or not we have code which can be put into a shared |
179 | library. */ | |
180 | static bfd_boolean mips_in_shared = TRUE; | |
181 | ||
252b5132 RH |
182 | /* This is the set of options which may be modified by the .set |
183 | pseudo-op. We use a struct so that .set push and .set pop are more | |
184 | reliable. */ | |
185 | ||
e972090a NC |
186 | struct mips_set_options |
187 | { | |
252b5132 RH |
188 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
189 | if it has not been initialized. Changed by `.set mipsN', and the | |
190 | -mipsN command line option, and the default CPU. */ | |
191 | int isa; | |
1f25f5d3 CD |
192 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
193 | if they have not been initialized. Changed by `.set <asename>', by | |
194 | command line options, and based on the default architecture. */ | |
195 | int ase_mips3d; | |
deec1734 | 196 | int ase_mdmx; |
e16bfa71 | 197 | int ase_smartmips; |
74cd071d | 198 | int ase_dsp; |
8b082fb1 | 199 | int ase_dspr2; |
ef2e4d86 | 200 | int ase_mt; |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
206 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
207 | reorder' and `.set noreorder'. */ | |
208 | int noreorder; | |
741fe287 MR |
209 | /* Non-zero if we should not permit the register designated "assembler |
210 | temporary" to be used in instructions. The value is the register | |
211 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
212 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
213 | unsigned int at; | |
252b5132 RH |
214 | /* Non-zero if we should warn when a macro instruction expands into |
215 | more than one machine instruction. Changed by `.set nomacro' and | |
216 | `.set macro'. */ | |
217 | int warn_about_macros; | |
218 | /* Non-zero if we should not move instructions. Changed by `.set | |
219 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
220 | int nomove; | |
221 | /* Non-zero if we should not optimize branches by moving the target | |
222 | of the branch into the delay slot. Actually, we don't perform | |
223 | this optimization anyhow. Changed by `.set bopt' and `.set | |
224 | nobopt'. */ | |
225 | int nobopt; | |
226 | /* Non-zero if we should not autoextend mips16 instructions. | |
227 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
228 | int noautoextend; | |
a325df1d TS |
229 | /* Restrict general purpose registers and floating point registers |
230 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
231 | is passed but can changed if the assembler code uses .set mipsN. */ | |
232 | int gp32; | |
233 | int fp32; | |
fef14a42 TS |
234 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
235 | command line option, and the default CPU. */ | |
236 | int arch; | |
aed1a261 RS |
237 | /* True if ".set sym32" is in effect. */ |
238 | bfd_boolean sym32; | |
037b32b9 AN |
239 | /* True if floating-point operations are not allowed. Changed by .set |
240 | softfloat or .set hardfloat, by command line options -msoft-float or | |
241 | -mhard-float. The default is false. */ | |
242 | bfd_boolean soft_float; | |
243 | ||
244 | /* True if only single-precision floating-point operations are allowed. | |
245 | Changed by .set singlefloat or .set doublefloat, command-line options | |
246 | -msingle-float or -mdouble-float. The default is false. */ | |
247 | bfd_boolean single_float; | |
252b5132 RH |
248 | }; |
249 | ||
037b32b9 AN |
250 | /* This is the struct we use to hold the current set of options. Note |
251 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
252 | -1 to indicate that they have not been initialized. */ | |
253 | ||
a325df1d | 254 | /* True if -mgp32 was passed. */ |
a8e8e863 | 255 | static int file_mips_gp32 = -1; |
a325df1d TS |
256 | |
257 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 258 | static int file_mips_fp32 = -1; |
a325df1d | 259 | |
037b32b9 AN |
260 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
261 | static int file_mips_soft_float = 0; | |
262 | ||
263 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
264 | static int file_mips_single_float = 0; | |
252b5132 | 265 | |
e972090a NC |
266 | static struct mips_set_options mips_opts = |
267 | { | |
037b32b9 AN |
268 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
269 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
270 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
271 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
272 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
273 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 RH |
275 | |
276 | /* These variables are filled in with the masks of registers used. | |
277 | The object format code reads them and puts them in the appropriate | |
278 | place. */ | |
279 | unsigned long mips_gprmask; | |
280 | unsigned long mips_cprmask[4]; | |
281 | ||
282 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 283 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 284 | |
738f4d98 | 285 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
286 | static int file_ase_mips16; |
287 | ||
3994f87e TS |
288 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
289 | || mips_opts.isa == ISA_MIPS32R2 \ | |
290 | || mips_opts.isa == ISA_MIPS64 \ | |
291 | || mips_opts.isa == ISA_MIPS64R2) | |
292 | ||
b12dd2e4 CF |
293 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
294 | #ifdef TE_IRIX | |
1180b5a4 | 295 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 296 | #else |
1180b5a4 RS |
297 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
298 | because there's no place for any addend, the only acceptable | |
299 | expression is a bare symbol. */ | |
300 | #define MIPS_JALR_HINT_P(EXPR) \ | |
301 | (!HAVE_IN_PLACE_ADDENDS \ | |
302 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
303 | #endif |
304 | ||
1f25f5d3 CD |
305 | /* True if -mips3d was passed or implied by arguments passed on the |
306 | command line (e.g., by -march). */ | |
307 | static int file_ase_mips3d; | |
308 | ||
deec1734 CD |
309 | /* True if -mdmx was passed or implied by arguments passed on the |
310 | command line (e.g., by -march). */ | |
311 | static int file_ase_mdmx; | |
312 | ||
e16bfa71 TS |
313 | /* True if -msmartmips was passed or implied by arguments passed on the |
314 | command line (e.g., by -march). */ | |
315 | static int file_ase_smartmips; | |
316 | ||
ad3fea08 TS |
317 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
318 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 319 | |
74cd071d CF |
320 | /* True if -mdsp was passed or implied by arguments passed on the |
321 | command line (e.g., by -march). */ | |
322 | static int file_ase_dsp; | |
323 | ||
ad3fea08 TS |
324 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
325 | || mips_opts.isa == ISA_MIPS64R2) | |
326 | ||
65263ce3 TS |
327 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
328 | ||
8b082fb1 TS |
329 | /* True if -mdspr2 was passed or implied by arguments passed on the |
330 | command line (e.g., by -march). */ | |
331 | static int file_ase_dspr2; | |
332 | ||
333 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
334 | || mips_opts.isa == ISA_MIPS64R2) | |
335 | ||
ef2e4d86 CF |
336 | /* True if -mmt was passed or implied by arguments passed on the |
337 | command line (e.g., by -march). */ | |
338 | static int file_ase_mt; | |
339 | ||
ad3fea08 TS |
340 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
341 | || mips_opts.isa == ISA_MIPS64R2) | |
342 | ||
ec68c924 | 343 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 344 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 345 | static const char *mips_arch_string; |
ec68c924 EC |
346 | |
347 | /* The argument of the -mtune= flag. The architecture for which we | |
348 | are optimizing. */ | |
349 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 350 | static const char *mips_tune_string; |
ec68c924 | 351 | |
316f5878 | 352 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
353 | static int mips_32bitmode = 0; |
354 | ||
316f5878 RS |
355 | /* True if the given ABI requires 32-bit registers. */ |
356 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
357 | ||
358 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
359 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
360 | ((ABI) == N32_ABI \ | |
361 | || (ABI) == N64_ABI \ | |
316f5878 RS |
362 | || (ABI) == O64_ABI) |
363 | ||
ad3fea08 | 364 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
365 | #define ISA_HAS_64BIT_REGS(ISA) \ |
366 | ((ISA) == ISA_MIPS3 \ | |
367 | || (ISA) == ISA_MIPS4 \ | |
368 | || (ISA) == ISA_MIPS5 \ | |
369 | || (ISA) == ISA_MIPS64 \ | |
370 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 371 | |
ad3fea08 TS |
372 | /* Return true if ISA supports 64 bit wide float registers. */ |
373 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
374 | ((ISA) == ISA_MIPS3 \ | |
375 | || (ISA) == ISA_MIPS4 \ | |
376 | || (ISA) == ISA_MIPS5 \ | |
377 | || (ISA) == ISA_MIPS32R2 \ | |
378 | || (ISA) == ISA_MIPS64 \ | |
379 | || (ISA) == ISA_MIPS64R2) | |
380 | ||
af7ee8bf CD |
381 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
382 | instructions. */ | |
707bfff6 TS |
383 | #define ISA_HAS_DROR(ISA) \ |
384 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
385 | |
386 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
387 | instructions. */ | |
707bfff6 TS |
388 | #define ISA_HAS_ROR(ISA) \ |
389 | ((ISA) == ISA_MIPS32R2 \ | |
390 | || (ISA) == ISA_MIPS64R2 \ | |
391 | || mips_opts.ase_smartmips) | |
392 | ||
7455baf8 TS |
393 | /* Return true if ISA supports single-precision floats in odd registers. */ |
394 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
395 | ((ISA) == ISA_MIPS32 \ | |
396 | || (ISA) == ISA_MIPS32R2 \ | |
397 | || (ISA) == ISA_MIPS64 \ | |
398 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 399 | |
ad3fea08 TS |
400 | /* Return true if ISA supports move to/from high part of a 64-bit |
401 | floating-point register. */ | |
402 | #define ISA_HAS_MXHC1(ISA) \ | |
403 | ((ISA) == ISA_MIPS32R2 \ | |
404 | || (ISA) == ISA_MIPS64R2) | |
405 | ||
e013f690 | 406 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 407 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 408 | |
e013f690 | 409 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 410 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 411 | |
ad3fea08 TS |
412 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
413 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 414 | |
316f5878 | 415 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 416 | |
316f5878 | 417 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 418 | |
3b91255e RS |
419 | /* True if relocations are stored in-place. */ |
420 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
421 | ||
aed1a261 RS |
422 | /* The ABI-derived address size. */ |
423 | #define HAVE_64BIT_ADDRESSES \ | |
424 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
425 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 426 | |
aed1a261 RS |
427 | /* The size of symbolic constants (i.e., expressions of the form |
428 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
429 | #define HAVE_32BIT_SYMBOLS \ | |
430 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
431 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 432 | |
b7c7d6c1 TS |
433 | /* Addresses are loaded in different ways, depending on the address size |
434 | in use. The n32 ABI Documentation also mandates the use of additions | |
435 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 436 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 437 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
438 | |
439 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 440 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
441 | |
442 | #define ADDRESS_LOAD_INSN \ | |
443 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
444 | ||
445 | #define ADDRESS_STORE_INSN \ | |
446 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
447 | ||
a4672219 | 448 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
449 | #define CPU_HAS_MIPS16(cpu) \ |
450 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
451 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 452 | |
60b63b72 RS |
453 | /* True if CPU has a dror instruction. */ |
454 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
455 | ||
456 | /* True if CPU has a ror instruction. */ | |
457 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
458 | ||
dd3cbb7e NC |
459 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
460 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
461 | ||
b19e8a9b AN |
462 | /* True if CPU does not implement the all the coprocessor insns. For these |
463 | CPUs only those COP insns are accepted that are explicitly marked to be | |
464 | available on the CPU. ISA membership for COP insns is ignored. */ | |
465 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
466 | ||
c8978940 CD |
467 | /* True if mflo and mfhi can be immediately followed by instructions |
468 | which write to the HI and LO registers. | |
469 | ||
470 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
471 | (at least) two instructions between the reads of HI/LO and | |
472 | instructions which write them, and later ISAs do not. Contradicting | |
473 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
474 | the UM for the NEC Vr5000) document needing the instructions between | |
475 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
476 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
477 | earlier-ISA CPUs for which CPU documentation declares that the | |
478 | instructions are really interlocked. */ | |
479 | #define hilo_interlocks \ | |
480 | (mips_opts.isa == ISA_MIPS32 \ | |
481 | || mips_opts.isa == ISA_MIPS32R2 \ | |
482 | || mips_opts.isa == ISA_MIPS64 \ | |
483 | || mips_opts.isa == ISA_MIPS64R2 \ | |
484 | || mips_opts.arch == CPU_R4010 \ | |
485 | || mips_opts.arch == CPU_R10000 \ | |
486 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
487 | || mips_opts.arch == CPU_R14000 \ |
488 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 489 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
490 | || mips_opts.arch == CPU_VR5500 \ |
491 | ) | |
252b5132 RH |
492 | |
493 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
494 | from the GPRs after they are loaded from memory, and thus does not |
495 | require nops to be inserted. This applies to instructions marked | |
496 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
497 | level I. */ | |
252b5132 | 498 | #define gpr_interlocks \ |
e7af610e | 499 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 500 | || mips_opts.arch == CPU_R3900) |
252b5132 | 501 | |
81912461 ILT |
502 | /* Whether the processor uses hardware interlocks to avoid delays |
503 | required by coprocessor instructions, and thus does not require | |
504 | nops to be inserted. This applies to instructions marked | |
505 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
506 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
507 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
508 | levels I, II, and III. */ | |
bdaaa2e1 | 509 | /* Itbl support may require additional care here. */ |
81912461 ILT |
510 | #define cop_interlocks \ |
511 | ((mips_opts.isa != ISA_MIPS1 \ | |
512 | && mips_opts.isa != ISA_MIPS2 \ | |
513 | && mips_opts.isa != ISA_MIPS3) \ | |
514 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
515 | ) |
516 | ||
517 | /* Whether the processor uses hardware interlocks to protect reads | |
518 | from coprocessor registers after they are loaded from memory, and | |
519 | thus does not require nops to be inserted. This applies to | |
520 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
521 | requires at MIPS ISA level I. */ | |
522 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 523 | |
6b76fefe CM |
524 | /* Is this a mfhi or mflo instruction? */ |
525 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
526 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
527 | ||
528 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
529 | or writing the condition code is only possible on the coprocessors and | |
530 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 531 | condition-code flags. */ |
b19e8a9b AN |
532 | #define COP_INSN(PINFO) \ |
533 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
534 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
535 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 536 | |
252b5132 RH |
537 | /* MIPS PIC level. */ |
538 | ||
a161fe53 | 539 | enum mips_pic_level mips_pic; |
252b5132 | 540 | |
c9914766 | 541 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 542 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 543 | static int mips_big_got = 0; |
252b5132 RH |
544 | |
545 | /* 1 if trap instructions should used for overflow rather than break | |
546 | instructions. */ | |
c9914766 | 547 | static int mips_trap = 0; |
252b5132 | 548 | |
119d663a | 549 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 550 | by assembling two single width halves into two single width floating |
119d663a NC |
551 | point registers which just happen to alias the double width destination |
552 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 553 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
554 | automatically at assemble time. */ |
555 | static int mips_disable_float_construction; | |
556 | ||
252b5132 RH |
557 | /* Non-zero if any .set noreorder directives were used. */ |
558 | ||
559 | static int mips_any_noreorder; | |
560 | ||
6b76fefe CM |
561 | /* Non-zero if nops should be inserted when the register referenced in |
562 | an mfhi/mflo instruction is read in the next two instructions. */ | |
563 | static int mips_7000_hilo_fix; | |
564 | ||
02ffd3e4 | 565 | /* The size of objects in the small data section. */ |
156c2f8b | 566 | static unsigned int g_switch_value = 8; |
252b5132 RH |
567 | /* Whether the -G option was used. */ |
568 | static int g_switch_seen = 0; | |
569 | ||
570 | #define N_RMASK 0xc4 | |
571 | #define N_VFP 0xd4 | |
572 | ||
573 | /* If we can determine in advance that GP optimization won't be | |
574 | possible, we can skip the relaxation stuff that tries to produce | |
575 | GP-relative references. This makes delay slot optimization work | |
576 | better. | |
577 | ||
578 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
579 | gcc output. It needs to guess right for gcc, otherwise gcc |
580 | will put what it thinks is a GP-relative instruction in a branch | |
581 | delay slot. | |
252b5132 RH |
582 | |
583 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
584 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 585 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
586 | |
587 | /* handle of the OPCODE hash table */ | |
588 | static struct hash_control *op_hash = NULL; | |
589 | ||
590 | /* The opcode hash table we use for the mips16. */ | |
591 | static struct hash_control *mips16_op_hash = NULL; | |
592 | ||
593 | /* This array holds the chars that always start a comment. If the | |
594 | pre-processor is disabled, these aren't very useful */ | |
595 | const char comment_chars[] = "#"; | |
596 | ||
597 | /* This array holds the chars that only start a comment at the beginning of | |
598 | a line. If the line seems to have the form '# 123 filename' | |
599 | .line and .file directives will appear in the pre-processed output */ | |
600 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
601 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 602 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
603 | /* Also note that C style comments are always supported. */ |
604 | const char line_comment_chars[] = "#"; | |
605 | ||
bdaaa2e1 | 606 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 607 | const char line_separator_chars[] = ";"; |
252b5132 RH |
608 | |
609 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
610 | const char EXP_CHARS[] = "eE"; | |
611 | ||
612 | /* Chars that mean this number is a floating point constant */ | |
613 | /* As in 0f12.456 */ | |
614 | /* or 0d1.2345e12 */ | |
615 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
616 | ||
617 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
618 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
619 | but nothing is ideal around here. | |
620 | */ | |
621 | ||
622 | static char *insn_error; | |
623 | ||
624 | static int auto_align = 1; | |
625 | ||
626 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
627 | offset in the stack frame from which to restore the $gp register. | |
628 | This is set by the .cprestore pseudo-op, and saved in this | |
629 | variable. */ | |
630 | static offsetT mips_cprestore_offset = -1; | |
631 | ||
67c1ffbe | 632 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 633 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 634 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
635 | static offsetT mips_cpreturn_offset = -1; |
636 | static int mips_cpreturn_register = -1; | |
637 | static int mips_gp_register = GP; | |
def2e0dd | 638 | static int mips_gprel_offset = 0; |
6478892d | 639 | |
7a621144 DJ |
640 | /* Whether mips_cprestore_offset has been set in the current function |
641 | (or whether it has already been warned about, if not). */ | |
642 | static int mips_cprestore_valid = 0; | |
643 | ||
252b5132 RH |
644 | /* This is the register which holds the stack frame, as set by the |
645 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
646 | static int mips_frame_reg = SP; | |
647 | ||
7a621144 DJ |
648 | /* Whether mips_frame_reg has been set in the current function |
649 | (or whether it has already been warned about, if not). */ | |
650 | static int mips_frame_reg_valid = 0; | |
651 | ||
252b5132 RH |
652 | /* To output NOP instructions correctly, we need to keep information |
653 | about the previous two instructions. */ | |
654 | ||
655 | /* Whether we are optimizing. The default value of 2 means to remove | |
656 | unneeded NOPs and swap branch instructions when possible. A value | |
657 | of 1 means to not swap branches. A value of 0 means to always | |
658 | insert NOPs. */ | |
659 | static int mips_optimize = 2; | |
660 | ||
661 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
662 | equivalent to seeing no -g option at all. */ | |
663 | static int mips_debug = 0; | |
664 | ||
7d8e00cf RS |
665 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
666 | #define MAX_VR4130_NOPS 4 | |
667 | ||
668 | /* The maximum number of NOPs needed to fill delay slots. */ | |
669 | #define MAX_DELAY_NOPS 2 | |
670 | ||
671 | /* The maximum number of NOPs needed for any purpose. */ | |
672 | #define MAX_NOPS 4 | |
71400594 RS |
673 | |
674 | /* A list of previous instructions, with index 0 being the most recent. | |
675 | We need to look back MAX_NOPS instructions when filling delay slots | |
676 | or working around processor errata. We need to look back one | |
677 | instruction further if we're thinking about using history[0] to | |
678 | fill a branch delay slot. */ | |
679 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 680 | |
1e915849 RS |
681 | /* Nop instructions used by emit_nop. */ |
682 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
683 | ||
684 | /* The appropriate nop for the current mode. */ | |
685 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 686 | |
252b5132 RH |
687 | /* If this is set, it points to a frag holding nop instructions which |
688 | were inserted before the start of a noreorder section. If those | |
689 | nops turn out to be unnecessary, the size of the frag can be | |
690 | decreased. */ | |
691 | static fragS *prev_nop_frag; | |
692 | ||
693 | /* The number of nop instructions we created in prev_nop_frag. */ | |
694 | static int prev_nop_frag_holds; | |
695 | ||
696 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 697 | prev_nop_frag. */ |
252b5132 RH |
698 | static int prev_nop_frag_required; |
699 | ||
700 | /* The number of instructions we've seen since prev_nop_frag. */ | |
701 | static int prev_nop_frag_since; | |
702 | ||
703 | /* For ECOFF and ELF, relocations against symbols are done in two | |
704 | parts, with a HI relocation and a LO relocation. Each relocation | |
705 | has only 16 bits of space to store an addend. This means that in | |
706 | order for the linker to handle carries correctly, it must be able | |
707 | to locate both the HI and the LO relocation. This means that the | |
708 | relocations must appear in order in the relocation table. | |
709 | ||
710 | In order to implement this, we keep track of each unmatched HI | |
711 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 712 | corresponding LO relocation. */ |
252b5132 | 713 | |
e972090a NC |
714 | struct mips_hi_fixup |
715 | { | |
252b5132 RH |
716 | /* Next HI fixup. */ |
717 | struct mips_hi_fixup *next; | |
718 | /* This fixup. */ | |
719 | fixS *fixp; | |
720 | /* The section this fixup is in. */ | |
721 | segT seg; | |
722 | }; | |
723 | ||
724 | /* The list of unmatched HI relocs. */ | |
725 | ||
726 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
727 | ||
64bdfcaf RS |
728 | /* The frag containing the last explicit relocation operator. |
729 | Null if explicit relocations have not been used. */ | |
730 | ||
731 | static fragS *prev_reloc_op_frag; | |
732 | ||
252b5132 RH |
733 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
734 | ||
735 | #define X ILLEGAL_REG | |
e972090a NC |
736 | static const int mips32_to_16_reg_map[] = |
737 | { | |
252b5132 RH |
738 | X, X, 2, 3, 4, 5, 6, 7, |
739 | X, X, X, X, X, X, X, X, | |
740 | 0, 1, X, X, X, X, X, X, | |
741 | X, X, X, X, X, X, X, X | |
742 | }; | |
743 | #undef X | |
744 | ||
745 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
746 | ||
e972090a NC |
747 | static const unsigned int mips16_to_32_reg_map[] = |
748 | { | |
252b5132 RH |
749 | 16, 17, 2, 3, 4, 5, 6, 7 |
750 | }; | |
60b63b72 | 751 | |
71400594 RS |
752 | /* Classifies the kind of instructions we're interested in when |
753 | implementing -mfix-vr4120. */ | |
c67a084a NC |
754 | enum fix_vr4120_class |
755 | { | |
71400594 RS |
756 | FIX_VR4120_MACC, |
757 | FIX_VR4120_DMACC, | |
758 | FIX_VR4120_MULT, | |
759 | FIX_VR4120_DMULT, | |
760 | FIX_VR4120_DIV, | |
761 | FIX_VR4120_MTHILO, | |
762 | NUM_FIX_VR4120_CLASSES | |
763 | }; | |
764 | ||
c67a084a NC |
765 | /* ...likewise -mfix-loongson2f-jump. */ |
766 | static bfd_boolean mips_fix_loongson2f_jump; | |
767 | ||
768 | /* ...likewise -mfix-loongson2f-nop. */ | |
769 | static bfd_boolean mips_fix_loongson2f_nop; | |
770 | ||
771 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
772 | static bfd_boolean mips_fix_loongson2f; | |
773 | ||
71400594 RS |
774 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
775 | there must be at least one other instruction between an instruction | |
776 | of type X and an instruction of type Y. */ | |
777 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
778 | ||
779 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 780 | static int mips_fix_vr4120; |
4a6a3df4 | 781 | |
7d8e00cf RS |
782 | /* ...likewise -mfix-vr4130. */ |
783 | static int mips_fix_vr4130; | |
784 | ||
6a32d874 CM |
785 | /* ...likewise -mfix-24k. */ |
786 | static int mips_fix_24k; | |
787 | ||
d954098f DD |
788 | /* ...likewise -mfix-cn63xxp1 */ |
789 | static bfd_boolean mips_fix_cn63xxp1; | |
790 | ||
4a6a3df4 AO |
791 | /* We don't relax branches by default, since this causes us to expand |
792 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
793 | fail to compute the offset before expanding the macro to the most | |
794 | efficient expansion. */ | |
795 | ||
796 | static int mips_relax_branch; | |
252b5132 | 797 | \f |
4d7206a2 RS |
798 | /* The expansion of many macros depends on the type of symbol that |
799 | they refer to. For example, when generating position-dependent code, | |
800 | a macro that refers to a symbol may have two different expansions, | |
801 | one which uses GP-relative addresses and one which uses absolute | |
802 | addresses. When generating SVR4-style PIC, a macro may have | |
803 | different expansions for local and global symbols. | |
804 | ||
805 | We handle these situations by generating both sequences and putting | |
806 | them in variant frags. In position-dependent code, the first sequence | |
807 | will be the GP-relative one and the second sequence will be the | |
808 | absolute one. In SVR4 PIC, the first sequence will be for global | |
809 | symbols and the second will be for local symbols. | |
810 | ||
584892a6 RS |
811 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
812 | SECOND are the lengths of the two sequences in bytes. These fields | |
813 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
814 | the subtype has the following flags: | |
4d7206a2 | 815 | |
584892a6 RS |
816 | RELAX_USE_SECOND |
817 | Set if it has been decided that we should use the second | |
818 | sequence instead of the first. | |
819 | ||
820 | RELAX_SECOND_LONGER | |
821 | Set in the first variant frag if the macro's second implementation | |
822 | is longer than its first. This refers to the macro as a whole, | |
823 | not an individual relaxation. | |
824 | ||
825 | RELAX_NOMACRO | |
826 | Set in the first variant frag if the macro appeared in a .set nomacro | |
827 | block and if one alternative requires a warning but the other does not. | |
828 | ||
829 | RELAX_DELAY_SLOT | |
830 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
831 | delay slot. | |
4d7206a2 RS |
832 | |
833 | The frag's "opcode" points to the first fixup for relaxable code. | |
834 | ||
835 | Relaxable macros are generated using a sequence such as: | |
836 | ||
837 | relax_start (SYMBOL); | |
838 | ... generate first expansion ... | |
839 | relax_switch (); | |
840 | ... generate second expansion ... | |
841 | relax_end (); | |
842 | ||
843 | The code and fixups for the unwanted alternative are discarded | |
844 | by md_convert_frag. */ | |
584892a6 | 845 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 846 | |
584892a6 RS |
847 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
848 | #define RELAX_SECOND(X) ((X) & 0xff) | |
849 | #define RELAX_USE_SECOND 0x10000 | |
850 | #define RELAX_SECOND_LONGER 0x20000 | |
851 | #define RELAX_NOMACRO 0x40000 | |
852 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 853 | |
4a6a3df4 AO |
854 | /* Branch without likely bit. If label is out of range, we turn: |
855 | ||
856 | beq reg1, reg2, label | |
857 | delay slot | |
858 | ||
859 | into | |
860 | ||
861 | bne reg1, reg2, 0f | |
862 | nop | |
863 | j label | |
864 | 0: delay slot | |
865 | ||
866 | with the following opcode replacements: | |
867 | ||
868 | beq <-> bne | |
869 | blez <-> bgtz | |
870 | bltz <-> bgez | |
871 | bc1f <-> bc1t | |
872 | ||
873 | bltzal <-> bgezal (with jal label instead of j label) | |
874 | ||
875 | Even though keeping the delay slot instruction in the delay slot of | |
876 | the branch would be more efficient, it would be very tricky to do | |
877 | correctly, because we'd have to introduce a variable frag *after* | |
878 | the delay slot instruction, and expand that instead. Let's do it | |
879 | the easy way for now, even if the branch-not-taken case now costs | |
880 | one additional instruction. Out-of-range branches are not supposed | |
881 | to be common, anyway. | |
882 | ||
883 | Branch likely. If label is out of range, we turn: | |
884 | ||
885 | beql reg1, reg2, label | |
886 | delay slot (annulled if branch not taken) | |
887 | ||
888 | into | |
889 | ||
890 | beql reg1, reg2, 1f | |
891 | nop | |
892 | beql $0, $0, 2f | |
893 | nop | |
894 | 1: j[al] label | |
895 | delay slot (executed only if branch taken) | |
896 | 2: | |
897 | ||
898 | It would be possible to generate a shorter sequence by losing the | |
899 | likely bit, generating something like: | |
b34976b6 | 900 | |
4a6a3df4 AO |
901 | bne reg1, reg2, 0f |
902 | nop | |
903 | j[al] label | |
904 | delay slot (executed only if branch taken) | |
905 | 0: | |
906 | ||
907 | beql -> bne | |
908 | bnel -> beq | |
909 | blezl -> bgtz | |
910 | bgtzl -> blez | |
911 | bltzl -> bgez | |
912 | bgezl -> bltz | |
913 | bc1fl -> bc1t | |
914 | bc1tl -> bc1f | |
915 | ||
916 | bltzall -> bgezal (with jal label instead of j label) | |
917 | bgezall -> bltzal (ditto) | |
918 | ||
919 | ||
920 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
921 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
922 | ((relax_substateT) \ | |
923 | (0xc0000000 \ | |
924 | | ((at) & 0x1f) \ | |
925 | | ((toofar) ? 0x20 : 0) \ | |
926 | | ((link) ? 0x40 : 0) \ | |
927 | | ((likely) ? 0x80 : 0) \ | |
928 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 929 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
930 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
931 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
932 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
933 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
934 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 935 | |
252b5132 RH |
936 | /* For mips16 code, we use an entirely different form of relaxation. |
937 | mips16 supports two versions of most instructions which take | |
938 | immediate values: a small one which takes some small value, and a | |
939 | larger one which takes a 16 bit value. Since branches also follow | |
940 | this pattern, relaxing these values is required. | |
941 | ||
942 | We can assemble both mips16 and normal MIPS code in a single | |
943 | object. Therefore, we need to support this type of relaxation at | |
944 | the same time that we support the relaxation described above. We | |
945 | use the high bit of the subtype field to distinguish these cases. | |
946 | ||
947 | The information we store for this type of relaxation is the | |
948 | argument code found in the opcode file for this relocation, whether | |
949 | the user explicitly requested a small or extended form, and whether | |
950 | the relocation is in a jump or jal delay slot. That tells us the | |
951 | size of the value, and how it should be stored. We also store | |
952 | whether the fragment is considered to be extended or not. We also | |
953 | store whether this is known to be a branch to a different section, | |
954 | whether we have tried to relax this frag yet, and whether we have | |
955 | ever extended a PC relative fragment because of a shift count. */ | |
956 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
957 | (0x80000000 \ | |
958 | | ((type) & 0xff) \ | |
959 | | ((small) ? 0x100 : 0) \ | |
960 | | ((ext) ? 0x200 : 0) \ | |
961 | | ((dslot) ? 0x400 : 0) \ | |
962 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 963 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
964 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
965 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
966 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
967 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
968 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
969 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
970 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
971 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
972 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
973 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
974 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
975 | |
976 | /* Is the given value a sign-extended 32-bit value? */ | |
977 | #define IS_SEXT_32BIT_NUM(x) \ | |
978 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
979 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
980 | ||
981 | /* Is the given value a sign-extended 16-bit value? */ | |
982 | #define IS_SEXT_16BIT_NUM(x) \ | |
983 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
984 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
985 | ||
2051e8c4 MR |
986 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
987 | #define IS_ZEXT_32BIT_NUM(x) \ | |
988 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
989 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
990 | ||
bf12938e RS |
991 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
992 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
993 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
994 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
995 | | (((VALUE) & (MASK)) << (SHIFT))) | |
996 | ||
997 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
998 | SHIFT places. */ | |
999 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1000 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1001 | ||
1002 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1003 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1004 | ||
1005 | include/opcode/mips.h specifies operand fields using the macros | |
1006 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1007 | with "MIPS16OP" instead of "OP". */ | |
1008 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1009 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1010 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1011 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1012 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1013 | ||
1014 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1015 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1016 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1017 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1018 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1019 | MIPS16OP_MASK_##FIELD, \ | |
1020 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1021 | \f |
1022 | /* Global variables used when generating relaxable macros. See the | |
1023 | comment above RELAX_ENCODE for more details about how relaxation | |
1024 | is used. */ | |
1025 | static struct { | |
1026 | /* 0 if we're not emitting a relaxable macro. | |
1027 | 1 if we're emitting the first of the two relaxation alternatives. | |
1028 | 2 if we're emitting the second alternative. */ | |
1029 | int sequence; | |
1030 | ||
1031 | /* The first relaxable fixup in the current frag. (In other words, | |
1032 | the first fixup that refers to relaxable code.) */ | |
1033 | fixS *first_fixup; | |
1034 | ||
1035 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1036 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1037 | unsigned int sizes[2]; | |
1038 | ||
1039 | /* The symbol on which the choice of sequence depends. */ | |
1040 | symbolS *symbol; | |
1041 | } mips_relax; | |
252b5132 | 1042 | \f |
584892a6 RS |
1043 | /* Global variables used to decide whether a macro needs a warning. */ |
1044 | static struct { | |
1045 | /* True if the macro is in a branch delay slot. */ | |
1046 | bfd_boolean delay_slot_p; | |
1047 | ||
1048 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1049 | in bytes and sizes[1] is the length of the second alternative. | |
1050 | For non-relaxable macros, both elements give the length of the | |
1051 | macro in bytes. */ | |
1052 | unsigned int sizes[2]; | |
1053 | ||
1054 | /* The first variant frag for this macro. */ | |
1055 | fragS *first_frag; | |
1056 | } mips_macro_warning; | |
1057 | \f | |
252b5132 RH |
1058 | /* Prototypes for static functions. */ |
1059 | ||
17a2f251 | 1060 | #define internalError() \ |
252b5132 | 1061 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1062 | |
1063 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1064 | ||
b34976b6 | 1065 | static void append_insn |
c67a084a | 1066 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1067 | static void mips_no_prev_insn (void); |
c67a084a | 1068 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1069 | static void mips16_macro_build |
03ea81db | 1070 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1071 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1072 | static void macro_start (void); |
1073 | static void macro_end (void); | |
17a2f251 TS |
1074 | static void macro (struct mips_cl_insn * ip); |
1075 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1076 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1077 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1078 | static void mips16_immed |
17a2f251 TS |
1079 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1080 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1081 | static size_t my_getSmallExpression |
17a2f251 TS |
1082 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1083 | static void my_getExpression (expressionS *, char *); | |
1084 | static void s_align (int); | |
1085 | static void s_change_sec (int); | |
1086 | static void s_change_section (int); | |
1087 | static void s_cons (int); | |
1088 | static void s_float_cons (int); | |
1089 | static void s_mips_globl (int); | |
1090 | static void s_option (int); | |
1091 | static void s_mipsset (int); | |
1092 | static void s_abicalls (int); | |
1093 | static void s_cpload (int); | |
1094 | static void s_cpsetup (int); | |
1095 | static void s_cplocal (int); | |
1096 | static void s_cprestore (int); | |
1097 | static void s_cpreturn (int); | |
741d6ea8 JM |
1098 | static void s_dtprelword (int); |
1099 | static void s_dtpreldword (int); | |
17a2f251 TS |
1100 | static void s_gpvalue (int); |
1101 | static void s_gpword (int); | |
1102 | static void s_gpdword (int); | |
1103 | static void s_cpadd (int); | |
1104 | static void s_insn (int); | |
1105 | static void md_obj_begin (void); | |
1106 | static void md_obj_end (void); | |
1107 | static void s_mips_ent (int); | |
1108 | static void s_mips_end (int); | |
1109 | static void s_mips_frame (int); | |
1110 | static void s_mips_mask (int reg_type); | |
1111 | static void s_mips_stab (int); | |
1112 | static void s_mips_weakext (int); | |
1113 | static void s_mips_file (int); | |
1114 | static void s_mips_loc (int); | |
1115 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1116 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1117 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1118 | |
1119 | /* Table and functions used to map between CPU/ISA names, and | |
1120 | ISA levels, and CPU numbers. */ | |
1121 | ||
e972090a NC |
1122 | struct mips_cpu_info |
1123 | { | |
e7af610e | 1124 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1125 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1126 | int isa; /* ISA level. */ |
1127 | int cpu; /* CPU number (default CPU if ISA). */ | |
1128 | }; | |
1129 | ||
ad3fea08 TS |
1130 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1131 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1132 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1133 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1134 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1135 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1136 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1137 | |
17a2f251 TS |
1138 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1139 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1140 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1141 | \f |
1142 | /* Pseudo-op table. | |
1143 | ||
1144 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1145 | should be defined here, but are currently unsupported: .alias, | |
1146 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1147 | ||
1148 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1149 | specific to the type of debugging information being generated, and | |
1150 | should be defined by the object format: .aent, .begin, .bend, | |
1151 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1152 | .vreg. | |
1153 | ||
1154 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1155 | not MIPS CPU specific, but are also not specific to the object file | |
1156 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1157 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1158 | |
e972090a NC |
1159 | static const pseudo_typeS mips_pseudo_table[] = |
1160 | { | |
beae10d5 | 1161 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1162 | {"option", s_option, 0}, |
1163 | {"set", s_mipsset, 0}, | |
1164 | {"rdata", s_change_sec, 'r'}, | |
1165 | {"sdata", s_change_sec, 's'}, | |
1166 | {"livereg", s_ignore, 0}, | |
1167 | {"abicalls", s_abicalls, 0}, | |
1168 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1169 | {"cpsetup", s_cpsetup, 0}, |
1170 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1171 | {"cprestore", s_cprestore, 0}, |
6478892d | 1172 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1173 | {"dtprelword", s_dtprelword, 0}, |
1174 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1175 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1176 | {"gpword", s_gpword, 0}, |
10181a0d | 1177 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1178 | {"cpadd", s_cpadd, 0}, |
1179 | {"insn", s_insn, 0}, | |
1180 | ||
beae10d5 | 1181 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1182 | chips. */ |
38a57ae7 | 1183 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1184 | {"bss", s_change_sec, 'b'}, |
1185 | {"err", s_err, 0}, | |
1186 | {"half", s_cons, 1}, | |
1187 | {"dword", s_cons, 3}, | |
1188 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1189 | {"origin", s_org, 0}, |
1190 | {"repeat", s_rept, 0}, | |
252b5132 | 1191 | |
998b3c36 MR |
1192 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1193 | {"sbss", s_change_sec, 'B'}, | |
1194 | ||
beae10d5 | 1195 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1196 | here for one reason or another. */ |
1197 | {"align", s_align, 0}, | |
1198 | {"byte", s_cons, 0}, | |
1199 | {"data", s_change_sec, 'd'}, | |
1200 | {"double", s_float_cons, 'd'}, | |
1201 | {"float", s_float_cons, 'f'}, | |
1202 | {"globl", s_mips_globl, 0}, | |
1203 | {"global", s_mips_globl, 0}, | |
1204 | {"hword", s_cons, 1}, | |
1205 | {"int", s_cons, 2}, | |
1206 | {"long", s_cons, 2}, | |
1207 | {"octa", s_cons, 4}, | |
1208 | {"quad", s_cons, 3}, | |
cca86cc8 | 1209 | {"section", s_change_section, 0}, |
252b5132 RH |
1210 | {"short", s_cons, 1}, |
1211 | {"single", s_float_cons, 'f'}, | |
1212 | {"stabn", s_mips_stab, 'n'}, | |
1213 | {"text", s_change_sec, 't'}, | |
1214 | {"word", s_cons, 2}, | |
add56521 | 1215 | |
add56521 | 1216 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1217 | |
43841e91 | 1218 | { NULL, NULL, 0 }, |
252b5132 RH |
1219 | }; |
1220 | ||
e972090a NC |
1221 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1222 | { | |
beae10d5 KH |
1223 | /* These pseudo-ops should be defined by the object file format. |
1224 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1225 | {"aent", s_mips_ent, 1}, |
1226 | {"bgnb", s_ignore, 0}, | |
1227 | {"end", s_mips_end, 0}, | |
1228 | {"endb", s_ignore, 0}, | |
1229 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1230 | {"file", s_mips_file, 0}, |
252b5132 RH |
1231 | {"fmask", s_mips_mask, 'F'}, |
1232 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1233 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1234 | {"mask", s_mips_mask, 'R'}, |
1235 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1236 | { NULL, NULL, 0 }, |
252b5132 RH |
1237 | }; |
1238 | ||
3ae8dd8d MR |
1239 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1240 | purpose of the `.dc.a' internal pseudo-op. */ | |
1241 | ||
1242 | int | |
1243 | mips_address_bytes (void) | |
1244 | { | |
1245 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1246 | } | |
1247 | ||
17a2f251 | 1248 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1249 | |
1250 | void | |
17a2f251 | 1251 | mips_pop_insert (void) |
252b5132 RH |
1252 | { |
1253 | pop_insert (mips_pseudo_table); | |
1254 | if (! ECOFF_DEBUGGING) | |
1255 | pop_insert (mips_nonecoff_pseudo_table); | |
1256 | } | |
1257 | \f | |
1258 | /* Symbols labelling the current insn. */ | |
1259 | ||
e972090a NC |
1260 | struct insn_label_list |
1261 | { | |
252b5132 RH |
1262 | struct insn_label_list *next; |
1263 | symbolS *label; | |
1264 | }; | |
1265 | ||
252b5132 | 1266 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1267 | #define label_list tc_segment_info_data.labels |
252b5132 | 1268 | |
17a2f251 | 1269 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1270 | |
1271 | static inline void | |
17a2f251 | 1272 | mips_clear_insn_labels (void) |
252b5132 RH |
1273 | { |
1274 | register struct insn_label_list **pl; | |
a8dbcb85 | 1275 | segment_info_type *si; |
252b5132 | 1276 | |
a8dbcb85 TS |
1277 | if (now_seg) |
1278 | { | |
1279 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1280 | ; | |
1281 | ||
1282 | si = seg_info (now_seg); | |
1283 | *pl = si->label_list; | |
1284 | si->label_list = NULL; | |
1285 | } | |
252b5132 | 1286 | } |
a8dbcb85 | 1287 | |
252b5132 RH |
1288 | \f |
1289 | static char *expr_end; | |
1290 | ||
1291 | /* Expressions which appear in instructions. These are set by | |
1292 | mips_ip. */ | |
1293 | ||
1294 | static expressionS imm_expr; | |
5f74bc13 | 1295 | static expressionS imm2_expr; |
252b5132 RH |
1296 | static expressionS offset_expr; |
1297 | ||
1298 | /* Relocs associated with imm_expr and offset_expr. */ | |
1299 | ||
f6688943 TS |
1300 | static bfd_reloc_code_real_type imm_reloc[3] |
1301 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1302 | static bfd_reloc_code_real_type offset_reloc[3] | |
1303 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1304 | |
252b5132 RH |
1305 | /* These are set by mips16_ip if an explicit extension is used. */ |
1306 | ||
b34976b6 | 1307 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1308 | |
7ed4a06a | 1309 | #ifdef OBJ_ELF |
ecb4347a DJ |
1310 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1311 | ECOFF debugging. */ | |
252b5132 RH |
1312 | |
1313 | static segT pdr_seg; | |
7ed4a06a | 1314 | #endif |
252b5132 | 1315 | |
e013f690 TS |
1316 | /* The default target format to use. */ |
1317 | ||
aeffff67 RS |
1318 | #if defined (TE_FreeBSD) |
1319 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1320 | #elif defined (TE_TMIPS) | |
1321 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1322 | #else | |
1323 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1324 | #endif | |
1325 | ||
e013f690 | 1326 | const char * |
17a2f251 | 1327 | mips_target_format (void) |
e013f690 TS |
1328 | { |
1329 | switch (OUTPUT_FLAVOR) | |
1330 | { | |
e013f690 TS |
1331 | case bfd_target_ecoff_flavour: |
1332 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1333 | case bfd_target_coff_flavour: | |
1334 | return "pe-mips"; | |
1335 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1336 | #ifdef TE_VXWORKS |
1337 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1338 | return (target_big_endian | |
1339 | ? "elf32-bigmips-vxworks" | |
1340 | : "elf32-littlemips-vxworks"); | |
1341 | #endif | |
e013f690 | 1342 | return (target_big_endian |
cfe86eaa | 1343 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1344 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1345 | : (HAVE_NEWABI |
aeffff67 RS |
1346 | ? ELF_TARGET ("elf32-n", "big") |
1347 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1348 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1349 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1350 | : (HAVE_NEWABI |
aeffff67 RS |
1351 | ? ELF_TARGET ("elf32-n", "little") |
1352 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1353 | default: |
1354 | abort (); | |
1355 | return NULL; | |
1356 | } | |
1357 | } | |
1358 | ||
1e915849 RS |
1359 | /* Return the length of instruction INSN. */ |
1360 | ||
1361 | static inline unsigned int | |
1362 | insn_length (const struct mips_cl_insn *insn) | |
1363 | { | |
1364 | if (!mips_opts.mips16) | |
1365 | return 4; | |
1366 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1367 | } | |
1368 | ||
1369 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1370 | ||
1371 | static void | |
1372 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1373 | { | |
1374 | size_t i; | |
1375 | ||
1376 | insn->insn_mo = mo; | |
1377 | insn->use_extend = FALSE; | |
1378 | insn->extend = 0; | |
1379 | insn->insn_opcode = mo->match; | |
1380 | insn->frag = NULL; | |
1381 | insn->where = 0; | |
1382 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1383 | insn->fixp[i] = NULL; | |
1384 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1385 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1386 | insn->mips16_absolute_jump_p = 0; | |
1387 | } | |
1388 | ||
742a56fe RS |
1389 | /* Record the current MIPS16 mode in now_seg. */ |
1390 | ||
1391 | static void | |
1392 | mips_record_mips16_mode (void) | |
1393 | { | |
1394 | segment_info_type *si; | |
1395 | ||
1396 | si = seg_info (now_seg); | |
1397 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1398 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1399 | } | |
1400 | ||
1e915849 RS |
1401 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1402 | ||
1403 | static void | |
1404 | install_insn (const struct mips_cl_insn *insn) | |
1405 | { | |
1406 | char *f = insn->frag->fr_literal + insn->where; | |
1407 | if (!mips_opts.mips16) | |
1408 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1409 | else if (insn->mips16_absolute_jump_p) | |
1410 | { | |
1411 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1412 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1413 | } | |
1414 | else | |
1415 | { | |
1416 | if (insn->use_extend) | |
1417 | { | |
1418 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1419 | f += 2; | |
1420 | } | |
1421 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1422 | } | |
742a56fe | 1423 | mips_record_mips16_mode (); |
1e915849 RS |
1424 | } |
1425 | ||
1426 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1427 | and install the opcode in the new location. */ | |
1428 | ||
1429 | static void | |
1430 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1431 | { | |
1432 | size_t i; | |
1433 | ||
1434 | insn->frag = frag; | |
1435 | insn->where = where; | |
1436 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1437 | if (insn->fixp[i] != NULL) | |
1438 | { | |
1439 | insn->fixp[i]->fx_frag = frag; | |
1440 | insn->fixp[i]->fx_where = where; | |
1441 | } | |
1442 | install_insn (insn); | |
1443 | } | |
1444 | ||
1445 | /* Add INSN to the end of the output. */ | |
1446 | ||
1447 | static void | |
1448 | add_fixed_insn (struct mips_cl_insn *insn) | |
1449 | { | |
1450 | char *f = frag_more (insn_length (insn)); | |
1451 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1452 | } | |
1453 | ||
1454 | /* Start a variant frag and move INSN to the start of the variant part, | |
1455 | marking it as fixed. The other arguments are as for frag_var. */ | |
1456 | ||
1457 | static void | |
1458 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1459 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1460 | { | |
1461 | frag_grow (max_chars); | |
1462 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1463 | insn->fixed_p = 1; | |
1464 | frag_var (rs_machine_dependent, max_chars, var, | |
1465 | subtype, symbol, offset, NULL); | |
1466 | } | |
1467 | ||
1468 | /* Insert N copies of INSN into the history buffer, starting at | |
1469 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1470 | ||
1471 | static void | |
1472 | insert_into_history (unsigned int first, unsigned int n, | |
1473 | const struct mips_cl_insn *insn) | |
1474 | { | |
1475 | if (mips_relax.sequence != 2) | |
1476 | { | |
1477 | unsigned int i; | |
1478 | ||
1479 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1480 | if (i >= first + n) | |
1481 | history[i] = history[i - n]; | |
1482 | else | |
1483 | history[i] = *insn; | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1488 | ||
1489 | static void | |
1490 | emit_nop (void) | |
1491 | { | |
1492 | add_fixed_insn (NOP_INSN); | |
1493 | insert_into_history (0, 1, NOP_INSN); | |
1494 | } | |
1495 | ||
71400594 RS |
1496 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1497 | the idea is to make it obvious at a glance that each errata is | |
1498 | included. */ | |
1499 | ||
1500 | static void | |
1501 | init_vr4120_conflicts (void) | |
1502 | { | |
1503 | #define CONFLICT(FIRST, SECOND) \ | |
1504 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1505 | ||
1506 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1507 | CONFLICT (MACC, DIV); | |
1508 | CONFLICT (DMACC, DIV); | |
1509 | ||
1510 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1511 | CONFLICT (DMULT, DMULT); | |
1512 | CONFLICT (DMULT, DMACC); | |
1513 | CONFLICT (DMACC, DMULT); | |
1514 | CONFLICT (DMACC, DMACC); | |
1515 | ||
1516 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1517 | CONFLICT (MACC, MTHILO); | |
1518 | CONFLICT (DMACC, MTHILO); | |
1519 | ||
1520 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1521 | instruction is executed immediately after a MACC or DMACC | |
1522 | instruction, the result of [either instruction] is incorrect." */ | |
1523 | CONFLICT (MACC, MULT); | |
1524 | CONFLICT (MACC, DMULT); | |
1525 | CONFLICT (DMACC, MULT); | |
1526 | CONFLICT (DMACC, DMULT); | |
1527 | ||
1528 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1529 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1530 | DDIV or DDIVU instruction, the result of the MACC or | |
1531 | DMACC instruction is incorrect.". */ | |
1532 | CONFLICT (DMULT, MACC); | |
1533 | CONFLICT (DMULT, DMACC); | |
1534 | CONFLICT (DIV, MACC); | |
1535 | CONFLICT (DIV, DMACC); | |
1536 | ||
1537 | #undef CONFLICT | |
1538 | } | |
1539 | ||
707bfff6 TS |
1540 | struct regname { |
1541 | const char *name; | |
1542 | unsigned int num; | |
1543 | }; | |
1544 | ||
1545 | #define RTYPE_MASK 0x1ff00 | |
1546 | #define RTYPE_NUM 0x00100 | |
1547 | #define RTYPE_FPU 0x00200 | |
1548 | #define RTYPE_FCC 0x00400 | |
1549 | #define RTYPE_VEC 0x00800 | |
1550 | #define RTYPE_GP 0x01000 | |
1551 | #define RTYPE_CP0 0x02000 | |
1552 | #define RTYPE_PC 0x04000 | |
1553 | #define RTYPE_ACC 0x08000 | |
1554 | #define RTYPE_CCC 0x10000 | |
1555 | #define RNUM_MASK 0x000ff | |
1556 | #define RWARN 0x80000 | |
1557 | ||
1558 | #define GENERIC_REGISTER_NUMBERS \ | |
1559 | {"$0", RTYPE_NUM | 0}, \ | |
1560 | {"$1", RTYPE_NUM | 1}, \ | |
1561 | {"$2", RTYPE_NUM | 2}, \ | |
1562 | {"$3", RTYPE_NUM | 3}, \ | |
1563 | {"$4", RTYPE_NUM | 4}, \ | |
1564 | {"$5", RTYPE_NUM | 5}, \ | |
1565 | {"$6", RTYPE_NUM | 6}, \ | |
1566 | {"$7", RTYPE_NUM | 7}, \ | |
1567 | {"$8", RTYPE_NUM | 8}, \ | |
1568 | {"$9", RTYPE_NUM | 9}, \ | |
1569 | {"$10", RTYPE_NUM | 10}, \ | |
1570 | {"$11", RTYPE_NUM | 11}, \ | |
1571 | {"$12", RTYPE_NUM | 12}, \ | |
1572 | {"$13", RTYPE_NUM | 13}, \ | |
1573 | {"$14", RTYPE_NUM | 14}, \ | |
1574 | {"$15", RTYPE_NUM | 15}, \ | |
1575 | {"$16", RTYPE_NUM | 16}, \ | |
1576 | {"$17", RTYPE_NUM | 17}, \ | |
1577 | {"$18", RTYPE_NUM | 18}, \ | |
1578 | {"$19", RTYPE_NUM | 19}, \ | |
1579 | {"$20", RTYPE_NUM | 20}, \ | |
1580 | {"$21", RTYPE_NUM | 21}, \ | |
1581 | {"$22", RTYPE_NUM | 22}, \ | |
1582 | {"$23", RTYPE_NUM | 23}, \ | |
1583 | {"$24", RTYPE_NUM | 24}, \ | |
1584 | {"$25", RTYPE_NUM | 25}, \ | |
1585 | {"$26", RTYPE_NUM | 26}, \ | |
1586 | {"$27", RTYPE_NUM | 27}, \ | |
1587 | {"$28", RTYPE_NUM | 28}, \ | |
1588 | {"$29", RTYPE_NUM | 29}, \ | |
1589 | {"$30", RTYPE_NUM | 30}, \ | |
1590 | {"$31", RTYPE_NUM | 31} | |
1591 | ||
1592 | #define FPU_REGISTER_NAMES \ | |
1593 | {"$f0", RTYPE_FPU | 0}, \ | |
1594 | {"$f1", RTYPE_FPU | 1}, \ | |
1595 | {"$f2", RTYPE_FPU | 2}, \ | |
1596 | {"$f3", RTYPE_FPU | 3}, \ | |
1597 | {"$f4", RTYPE_FPU | 4}, \ | |
1598 | {"$f5", RTYPE_FPU | 5}, \ | |
1599 | {"$f6", RTYPE_FPU | 6}, \ | |
1600 | {"$f7", RTYPE_FPU | 7}, \ | |
1601 | {"$f8", RTYPE_FPU | 8}, \ | |
1602 | {"$f9", RTYPE_FPU | 9}, \ | |
1603 | {"$f10", RTYPE_FPU | 10}, \ | |
1604 | {"$f11", RTYPE_FPU | 11}, \ | |
1605 | {"$f12", RTYPE_FPU | 12}, \ | |
1606 | {"$f13", RTYPE_FPU | 13}, \ | |
1607 | {"$f14", RTYPE_FPU | 14}, \ | |
1608 | {"$f15", RTYPE_FPU | 15}, \ | |
1609 | {"$f16", RTYPE_FPU | 16}, \ | |
1610 | {"$f17", RTYPE_FPU | 17}, \ | |
1611 | {"$f18", RTYPE_FPU | 18}, \ | |
1612 | {"$f19", RTYPE_FPU | 19}, \ | |
1613 | {"$f20", RTYPE_FPU | 20}, \ | |
1614 | {"$f21", RTYPE_FPU | 21}, \ | |
1615 | {"$f22", RTYPE_FPU | 22}, \ | |
1616 | {"$f23", RTYPE_FPU | 23}, \ | |
1617 | {"$f24", RTYPE_FPU | 24}, \ | |
1618 | {"$f25", RTYPE_FPU | 25}, \ | |
1619 | {"$f26", RTYPE_FPU | 26}, \ | |
1620 | {"$f27", RTYPE_FPU | 27}, \ | |
1621 | {"$f28", RTYPE_FPU | 28}, \ | |
1622 | {"$f29", RTYPE_FPU | 29}, \ | |
1623 | {"$f30", RTYPE_FPU | 30}, \ | |
1624 | {"$f31", RTYPE_FPU | 31} | |
1625 | ||
1626 | #define FPU_CONDITION_CODE_NAMES \ | |
1627 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1628 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1629 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1630 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1631 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1632 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1633 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1634 | {"$fcc7", RTYPE_FCC | 7} | |
1635 | ||
1636 | #define COPROC_CONDITION_CODE_NAMES \ | |
1637 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1638 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1639 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1640 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1641 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1642 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1643 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1644 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1645 | ||
1646 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1647 | {"$a4", RTYPE_GP | 8}, \ | |
1648 | {"$a5", RTYPE_GP | 9}, \ | |
1649 | {"$a6", RTYPE_GP | 10}, \ | |
1650 | {"$a7", RTYPE_GP | 11}, \ | |
1651 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1652 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1653 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1654 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1655 | {"$t0", RTYPE_GP | 12}, \ | |
1656 | {"$t1", RTYPE_GP | 13}, \ | |
1657 | {"$t2", RTYPE_GP | 14}, \ | |
1658 | {"$t3", RTYPE_GP | 15} | |
1659 | ||
1660 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1661 | {"$t0", RTYPE_GP | 8}, \ | |
1662 | {"$t1", RTYPE_GP | 9}, \ | |
1663 | {"$t2", RTYPE_GP | 10}, \ | |
1664 | {"$t3", RTYPE_GP | 11}, \ | |
1665 | {"$t4", RTYPE_GP | 12}, \ | |
1666 | {"$t5", RTYPE_GP | 13}, \ | |
1667 | {"$t6", RTYPE_GP | 14}, \ | |
1668 | {"$t7", RTYPE_GP | 15}, \ | |
1669 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1670 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1671 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1672 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1673 | ||
1674 | /* Remaining symbolic register names */ | |
1675 | #define SYMBOLIC_REGISTER_NAMES \ | |
1676 | {"$zero", RTYPE_GP | 0}, \ | |
1677 | {"$at", RTYPE_GP | 1}, \ | |
1678 | {"$AT", RTYPE_GP | 1}, \ | |
1679 | {"$v0", RTYPE_GP | 2}, \ | |
1680 | {"$v1", RTYPE_GP | 3}, \ | |
1681 | {"$a0", RTYPE_GP | 4}, \ | |
1682 | {"$a1", RTYPE_GP | 5}, \ | |
1683 | {"$a2", RTYPE_GP | 6}, \ | |
1684 | {"$a3", RTYPE_GP | 7}, \ | |
1685 | {"$s0", RTYPE_GP | 16}, \ | |
1686 | {"$s1", RTYPE_GP | 17}, \ | |
1687 | {"$s2", RTYPE_GP | 18}, \ | |
1688 | {"$s3", RTYPE_GP | 19}, \ | |
1689 | {"$s4", RTYPE_GP | 20}, \ | |
1690 | {"$s5", RTYPE_GP | 21}, \ | |
1691 | {"$s6", RTYPE_GP | 22}, \ | |
1692 | {"$s7", RTYPE_GP | 23}, \ | |
1693 | {"$t8", RTYPE_GP | 24}, \ | |
1694 | {"$t9", RTYPE_GP | 25}, \ | |
1695 | {"$k0", RTYPE_GP | 26}, \ | |
1696 | {"$kt0", RTYPE_GP | 26}, \ | |
1697 | {"$k1", RTYPE_GP | 27}, \ | |
1698 | {"$kt1", RTYPE_GP | 27}, \ | |
1699 | {"$gp", RTYPE_GP | 28}, \ | |
1700 | {"$sp", RTYPE_GP | 29}, \ | |
1701 | {"$s8", RTYPE_GP | 30}, \ | |
1702 | {"$fp", RTYPE_GP | 30}, \ | |
1703 | {"$ra", RTYPE_GP | 31} | |
1704 | ||
1705 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1706 | {"$pc", RTYPE_PC | 0} | |
1707 | ||
1708 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1709 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1710 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1711 | {"$v2", RTYPE_VEC | 2}, \ | |
1712 | {"$v3", RTYPE_VEC | 3}, \ | |
1713 | {"$v4", RTYPE_VEC | 4}, \ | |
1714 | {"$v5", RTYPE_VEC | 5}, \ | |
1715 | {"$v6", RTYPE_VEC | 6}, \ | |
1716 | {"$v7", RTYPE_VEC | 7}, \ | |
1717 | {"$v8", RTYPE_VEC | 8}, \ | |
1718 | {"$v9", RTYPE_VEC | 9}, \ | |
1719 | {"$v10", RTYPE_VEC | 10}, \ | |
1720 | {"$v11", RTYPE_VEC | 11}, \ | |
1721 | {"$v12", RTYPE_VEC | 12}, \ | |
1722 | {"$v13", RTYPE_VEC | 13}, \ | |
1723 | {"$v14", RTYPE_VEC | 14}, \ | |
1724 | {"$v15", RTYPE_VEC | 15}, \ | |
1725 | {"$v16", RTYPE_VEC | 16}, \ | |
1726 | {"$v17", RTYPE_VEC | 17}, \ | |
1727 | {"$v18", RTYPE_VEC | 18}, \ | |
1728 | {"$v19", RTYPE_VEC | 19}, \ | |
1729 | {"$v20", RTYPE_VEC | 20}, \ | |
1730 | {"$v21", RTYPE_VEC | 21}, \ | |
1731 | {"$v22", RTYPE_VEC | 22}, \ | |
1732 | {"$v23", RTYPE_VEC | 23}, \ | |
1733 | {"$v24", RTYPE_VEC | 24}, \ | |
1734 | {"$v25", RTYPE_VEC | 25}, \ | |
1735 | {"$v26", RTYPE_VEC | 26}, \ | |
1736 | {"$v27", RTYPE_VEC | 27}, \ | |
1737 | {"$v28", RTYPE_VEC | 28}, \ | |
1738 | {"$v29", RTYPE_VEC | 29}, \ | |
1739 | {"$v30", RTYPE_VEC | 30}, \ | |
1740 | {"$v31", RTYPE_VEC | 31} | |
1741 | ||
1742 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1743 | {"$ac0", RTYPE_ACC | 0}, \ | |
1744 | {"$ac1", RTYPE_ACC | 1}, \ | |
1745 | {"$ac2", RTYPE_ACC | 2}, \ | |
1746 | {"$ac3", RTYPE_ACC | 3} | |
1747 | ||
1748 | static const struct regname reg_names[] = { | |
1749 | GENERIC_REGISTER_NUMBERS, | |
1750 | FPU_REGISTER_NAMES, | |
1751 | FPU_CONDITION_CODE_NAMES, | |
1752 | COPROC_CONDITION_CODE_NAMES, | |
1753 | ||
1754 | /* The $txx registers depends on the abi, | |
1755 | these will be added later into the symbol table from | |
1756 | one of the tables below once mips_abi is set after | |
1757 | parsing of arguments from the command line. */ | |
1758 | SYMBOLIC_REGISTER_NAMES, | |
1759 | ||
1760 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1761 | MDMX_VECTOR_REGISTER_NAMES, | |
1762 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1763 | {0, 0} | |
1764 | }; | |
1765 | ||
1766 | static const struct regname reg_names_o32[] = { | |
1767 | O32_SYMBOLIC_REGISTER_NAMES, | |
1768 | {0, 0} | |
1769 | }; | |
1770 | ||
1771 | static const struct regname reg_names_n32n64[] = { | |
1772 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1773 | {0, 0} | |
1774 | }; | |
1775 | ||
1776 | static int | |
1777 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1778 | { | |
1779 | symbolS *symbolP; | |
1780 | char *e; | |
1781 | char save_c; | |
1782 | int reg = -1; | |
1783 | ||
1784 | /* Find end of name. */ | |
1785 | e = *s; | |
1786 | if (is_name_beginner (*e)) | |
1787 | ++e; | |
1788 | while (is_part_of_name (*e)) | |
1789 | ++e; | |
1790 | ||
1791 | /* Terminate name. */ | |
1792 | save_c = *e; | |
1793 | *e = '\0'; | |
1794 | ||
1795 | /* Look for a register symbol. */ | |
1796 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1797 | { | |
1798 | int r = S_GET_VALUE (symbolP); | |
1799 | if (r & types) | |
1800 | reg = r & RNUM_MASK; | |
1801 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1802 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1803 | reg = (r & RNUM_MASK) - 2; | |
1804 | } | |
1805 | /* Else see if this is a register defined in an itbl entry. */ | |
1806 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1807 | { | |
1808 | char *n = *s; | |
1809 | unsigned long r; | |
1810 | ||
1811 | if (*n == '$') | |
1812 | ++n; | |
1813 | if (itbl_get_reg_val (n, &r)) | |
1814 | reg = r & RNUM_MASK; | |
1815 | } | |
1816 | ||
1817 | /* Advance to next token if a register was recognised. */ | |
1818 | if (reg >= 0) | |
1819 | *s = e; | |
1820 | else if (types & RWARN) | |
20203fb9 | 1821 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1822 | |
1823 | *e = save_c; | |
1824 | if (regnop) | |
1825 | *regnop = reg; | |
1826 | return reg >= 0; | |
1827 | } | |
1828 | ||
037b32b9 | 1829 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1830 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1831 | |
1832 | static bfd_boolean | |
f79e2745 | 1833 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1834 | { |
1835 | int isa = mips_opts.isa; | |
1836 | int fp_s, fp_d; | |
1837 | ||
1838 | if (mips_opts.ase_mdmx) | |
1839 | isa |= INSN_MDMX; | |
1840 | if (mips_opts.ase_dsp) | |
1841 | isa |= INSN_DSP; | |
1842 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1843 | isa |= INSN_DSP64; | |
1844 | if (mips_opts.ase_dspr2) | |
1845 | isa |= INSN_DSPR2; | |
1846 | if (mips_opts.ase_mt) | |
1847 | isa |= INSN_MT; | |
1848 | if (mips_opts.ase_mips3d) | |
1849 | isa |= INSN_MIPS3D; | |
1850 | if (mips_opts.ase_smartmips) | |
1851 | isa |= INSN_SMARTMIPS; | |
1852 | ||
b19e8a9b AN |
1853 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1854 | all the coprocessor insns. */ | |
1855 | if (NO_ISA_COP (mips_opts.arch) | |
1856 | && COP_INSN (mo->pinfo)) | |
1857 | isa = 0; | |
1858 | ||
037b32b9 AN |
1859 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1860 | return FALSE; | |
1861 | ||
1862 | /* Check whether the instruction or macro requires single-precision or | |
1863 | double-precision floating-point support. Note that this information is | |
1864 | stored differently in the opcode table for insns and macros. */ | |
1865 | if (mo->pinfo == INSN_MACRO) | |
1866 | { | |
1867 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1868 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1869 | } | |
1870 | else | |
1871 | { | |
1872 | fp_s = mo->pinfo & FP_S; | |
1873 | fp_d = mo->pinfo & FP_D; | |
1874 | } | |
1875 | ||
1876 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1877 | return FALSE; | |
1878 | ||
1879 | if (fp_s && mips_opts.soft_float) | |
1880 | return FALSE; | |
1881 | ||
1882 | return TRUE; | |
1883 | } | |
1884 | ||
1885 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1886 | selected ISA and architecture. */ | |
1887 | ||
1888 | static bfd_boolean | |
1889 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1890 | { | |
1891 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1892 | } | |
1893 | ||
707bfff6 TS |
1894 | /* This function is called once, at assembler startup time. It should set up |
1895 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1896 | |
252b5132 | 1897 | void |
17a2f251 | 1898 | md_begin (void) |
252b5132 | 1899 | { |
3994f87e | 1900 | const char *retval = NULL; |
156c2f8b | 1901 | int i = 0; |
252b5132 | 1902 | int broken = 0; |
1f25f5d3 | 1903 | |
0a44bf69 RS |
1904 | if (mips_pic != NO_PIC) |
1905 | { | |
1906 | if (g_switch_seen && g_switch_value != 0) | |
1907 | as_bad (_("-G may not be used in position-independent code")); | |
1908 | g_switch_value = 0; | |
1909 | } | |
1910 | ||
fef14a42 | 1911 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1912 | as_warn (_("Could not set architecture and machine")); |
1913 | ||
252b5132 RH |
1914 | op_hash = hash_new (); |
1915 | ||
1916 | for (i = 0; i < NUMOPCODES;) | |
1917 | { | |
1918 | const char *name = mips_opcodes[i].name; | |
1919 | ||
17a2f251 | 1920 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1921 | if (retval != NULL) |
1922 | { | |
1923 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1924 | mips_opcodes[i].name, retval); | |
1925 | /* Probably a memory allocation problem? Give up now. */ | |
1926 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1927 | } | |
1928 | do | |
1929 | { | |
1930 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1931 | { | |
1932 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1933 | broken = 1; | |
1e915849 RS |
1934 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1935 | { | |
1936 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1937 | if (mips_fix_loongson2f_nop) |
1938 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1939 | nop_insn.fixed_p = 1; |
1940 | } | |
252b5132 RH |
1941 | } |
1942 | ++i; | |
1943 | } | |
1944 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1945 | } | |
1946 | ||
1947 | mips16_op_hash = hash_new (); | |
1948 | ||
1949 | i = 0; | |
1950 | while (i < bfd_mips16_num_opcodes) | |
1951 | { | |
1952 | const char *name = mips16_opcodes[i].name; | |
1953 | ||
17a2f251 | 1954 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1955 | if (retval != NULL) |
1956 | as_fatal (_("internal: can't hash `%s': %s"), | |
1957 | mips16_opcodes[i].name, retval); | |
1958 | do | |
1959 | { | |
1960 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1961 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1962 | != mips16_opcodes[i].match)) | |
1963 | { | |
1964 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1965 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1966 | broken = 1; | |
1967 | } | |
1e915849 RS |
1968 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1969 | { | |
1970 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1971 | mips16_nop_insn.fixed_p = 1; | |
1972 | } | |
252b5132 RH |
1973 | ++i; |
1974 | } | |
1975 | while (i < bfd_mips16_num_opcodes | |
1976 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1977 | } | |
1978 | ||
1979 | if (broken) | |
1980 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1981 | ||
1982 | /* We add all the general register names to the symbol table. This | |
1983 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1984 | for (i = 0; reg_names[i].name; i++) |
1985 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1986 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1987 | &zero_address_frag)); |
1988 | if (HAVE_NEWABI) | |
1989 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1990 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1991 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1992 | &zero_address_frag)); |
707bfff6 TS |
1993 | else |
1994 | for (i = 0; reg_names_o32[i].name; i++) | |
1995 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1996 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1997 | &zero_address_frag)); |
6047c971 | 1998 | |
7d10b47d | 1999 | mips_no_prev_insn (); |
252b5132 RH |
2000 | |
2001 | mips_gprmask = 0; | |
2002 | mips_cprmask[0] = 0; | |
2003 | mips_cprmask[1] = 0; | |
2004 | mips_cprmask[2] = 0; | |
2005 | mips_cprmask[3] = 0; | |
2006 | ||
2007 | /* set the default alignment for the text section (2**2) */ | |
2008 | record_alignment (text_section, 2); | |
2009 | ||
4d0d148d | 2010 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2011 | |
707bfff6 | 2012 | #ifdef OBJ_ELF |
f43abd2b | 2013 | if (IS_ELF) |
252b5132 | 2014 | { |
0a44bf69 RS |
2015 | /* On a native system other than VxWorks, sections must be aligned |
2016 | to 16 byte boundaries. When configured for an embedded ELF | |
2017 | target, we don't bother. */ | |
c41e87e3 CF |
2018 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2019 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2020 | { |
2021 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2022 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2023 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2024 | } | |
2025 | ||
2026 | /* Create a .reginfo section for register masks and a .mdebug | |
2027 | section for debugging information. */ | |
2028 | { | |
2029 | segT seg; | |
2030 | subsegT subseg; | |
2031 | flagword flags; | |
2032 | segT sec; | |
2033 | ||
2034 | seg = now_seg; | |
2035 | subseg = now_subseg; | |
2036 | ||
2037 | /* The ABI says this section should be loaded so that the | |
2038 | running program can access it. However, we don't load it | |
2039 | if we are configured for an embedded target */ | |
2040 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2041 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2042 | flags |= SEC_ALLOC | SEC_LOAD; |
2043 | ||
316f5878 | 2044 | if (mips_abi != N64_ABI) |
252b5132 RH |
2045 | { |
2046 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2047 | ||
195325d2 TS |
2048 | bfd_set_section_flags (stdoutput, sec, flags); |
2049 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2050 | |
252b5132 | 2051 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2052 | } |
2053 | else | |
2054 | { | |
2055 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2056 | .reginfo section. */ | |
2057 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2058 | bfd_set_section_flags (stdoutput, sec, flags); |
2059 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2060 | |
252b5132 RH |
2061 | /* Set up the option header. */ |
2062 | { | |
2063 | Elf_Internal_Options opthdr; | |
2064 | char *f; | |
2065 | ||
2066 | opthdr.kind = ODK_REGINFO; | |
2067 | opthdr.size = (sizeof (Elf_External_Options) | |
2068 | + sizeof (Elf64_External_RegInfo)); | |
2069 | opthdr.section = 0; | |
2070 | opthdr.info = 0; | |
2071 | f = frag_more (sizeof (Elf_External_Options)); | |
2072 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2073 | (Elf_External_Options *) f); | |
2074 | ||
2075 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2076 | } | |
252b5132 RH |
2077 | } |
2078 | ||
2079 | if (ECOFF_DEBUGGING) | |
2080 | { | |
2081 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2082 | (void) bfd_set_section_flags (stdoutput, sec, | |
2083 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2084 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2085 | } | |
f43abd2b | 2086 | else if (mips_flag_pdr) |
ecb4347a DJ |
2087 | { |
2088 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2089 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2090 | SEC_READONLY | SEC_RELOC | |
2091 | | SEC_DEBUGGING); | |
2092 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2093 | } | |
252b5132 RH |
2094 | |
2095 | subseg_set (seg, subseg); | |
2096 | } | |
2097 | } | |
707bfff6 | 2098 | #endif /* OBJ_ELF */ |
252b5132 RH |
2099 | |
2100 | if (! ECOFF_DEBUGGING) | |
2101 | md_obj_begin (); | |
71400594 RS |
2102 | |
2103 | if (mips_fix_vr4120) | |
2104 | init_vr4120_conflicts (); | |
252b5132 RH |
2105 | } |
2106 | ||
2107 | void | |
17a2f251 | 2108 | md_mips_end (void) |
252b5132 RH |
2109 | { |
2110 | if (! ECOFF_DEBUGGING) | |
2111 | md_obj_end (); | |
2112 | } | |
2113 | ||
2114 | void | |
17a2f251 | 2115 | md_assemble (char *str) |
252b5132 RH |
2116 | { |
2117 | struct mips_cl_insn insn; | |
f6688943 TS |
2118 | bfd_reloc_code_real_type unused_reloc[3] |
2119 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2120 | |
2121 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2122 | imm2_expr.X_op = O_absent; |
252b5132 | 2123 | offset_expr.X_op = O_absent; |
f6688943 TS |
2124 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2125 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2126 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2127 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2128 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2129 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2130 | |
2131 | if (mips_opts.mips16) | |
2132 | mips16_ip (str, &insn); | |
2133 | else | |
2134 | { | |
2135 | mips_ip (str, &insn); | |
beae10d5 KH |
2136 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2137 | str, insn.insn_opcode)); | |
252b5132 RH |
2138 | } |
2139 | ||
2140 | if (insn_error) | |
2141 | { | |
2142 | as_bad ("%s `%s'", insn_error, str); | |
2143 | return; | |
2144 | } | |
2145 | ||
2146 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2147 | { | |
584892a6 | 2148 | macro_start (); |
252b5132 RH |
2149 | if (mips_opts.mips16) |
2150 | mips16_macro (&insn); | |
2151 | else | |
2152 | macro (&insn); | |
584892a6 | 2153 | macro_end (); |
252b5132 RH |
2154 | } |
2155 | else | |
2156 | { | |
2157 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2158 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2159 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2160 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2161 | else |
4d7206a2 | 2162 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2163 | } |
2164 | } | |
2165 | ||
738e5348 RS |
2166 | /* Convenience functions for abstracting away the differences between |
2167 | MIPS16 and non-MIPS16 relocations. */ | |
2168 | ||
2169 | static inline bfd_boolean | |
2170 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2171 | { | |
2172 | switch (reloc) | |
2173 | { | |
2174 | case BFD_RELOC_MIPS16_JMP: | |
2175 | case BFD_RELOC_MIPS16_GPREL: | |
2176 | case BFD_RELOC_MIPS16_GOT16: | |
2177 | case BFD_RELOC_MIPS16_CALL16: | |
2178 | case BFD_RELOC_MIPS16_HI16_S: | |
2179 | case BFD_RELOC_MIPS16_HI16: | |
2180 | case BFD_RELOC_MIPS16_LO16: | |
2181 | return TRUE; | |
2182 | ||
2183 | default: | |
2184 | return FALSE; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | static inline bfd_boolean | |
2189 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2190 | { | |
2191 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2192 | } | |
2193 | ||
2194 | static inline bfd_boolean | |
2195 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2196 | { | |
2197 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2198 | } | |
2199 | ||
2200 | static inline bfd_boolean | |
2201 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2202 | { | |
2203 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2204 | } | |
2205 | ||
5919d012 | 2206 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2207 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2208 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2209 | |
2210 | static inline bfd_boolean | |
17a2f251 | 2211 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2212 | { |
3b91255e | 2213 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2214 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2215 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2216 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2217 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2218 | } | |
2219 | ||
2220 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2221 | reloc_needs_lo_p. */ | |
2222 | ||
2223 | static inline bfd_reloc_code_real_type | |
2224 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2225 | { | |
2226 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2227 | } |
2228 | ||
2229 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2230 | relocation. */ | |
2231 | ||
2232 | static inline bfd_boolean | |
17a2f251 | 2233 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2234 | { |
2235 | return (fixp->fx_next != NULL | |
738e5348 | 2236 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2237 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2238 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2239 | } | |
2240 | ||
252b5132 RH |
2241 | /* See whether instruction IP reads register REG. CLASS is the type |
2242 | of register. */ | |
2243 | ||
2244 | static int | |
71400594 | 2245 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2246 | enum mips_regclass regclass) |
252b5132 | 2247 | { |
96d56e9f | 2248 | if (regclass == MIPS16_REG) |
252b5132 | 2249 | { |
9c2799c2 | 2250 | gas_assert (mips_opts.mips16); |
252b5132 | 2251 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2252 | regclass = MIPS_GR_REG; |
252b5132 RH |
2253 | } |
2254 | ||
85b51719 | 2255 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2256 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2257 | return 0; |
2258 | ||
96d56e9f | 2259 | if (regclass == MIPS_FP_REG) |
252b5132 | 2260 | { |
9c2799c2 | 2261 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2262 | /* If we are called with either $f0 or $f1, we must check $f0. |
2263 | This is not optimal, because it will introduce an unnecessary | |
2264 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2265 | need to distinguish reading both $f0 and $f1 or just one of | |
2266 | them. Note that we don't have to check the other way, | |
2267 | because there is no instruction that sets both $f0 and $f1 | |
2268 | and requires a delay. */ | |
2269 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2270 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2271 | == (reg &~ (unsigned) 1))) |
2272 | return 1; | |
2273 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2274 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2275 | == (reg &~ (unsigned) 1))) |
2276 | return 1; | |
98675402 RS |
2277 | if ((ip->insn_mo->pinfo2 & INSN2_READ_FPR_Z) |
2278 | && ((EXTRACT_OPERAND (FZ, *ip) & ~(unsigned) 1) | |
2279 | == (reg &~ (unsigned) 1))) | |
2280 | return 1; | |
252b5132 RH |
2281 | } |
2282 | else if (! mips_opts.mips16) | |
2283 | { | |
2284 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2285 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2286 | return 1; |
2287 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2288 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 | 2289 | return 1; |
98675402 RS |
2290 | if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_D) |
2291 | && EXTRACT_OPERAND (RD, *ip) == reg) | |
2292 | return 1; | |
2293 | if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_Z) | |
2294 | && EXTRACT_OPERAND (RZ, *ip) == reg) | |
2295 | return 1; | |
252b5132 RH |
2296 | } |
2297 | else | |
2298 | { | |
2299 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2300 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2301 | return 1; |
2302 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2303 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2304 | return 1; |
2305 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2306 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2307 | == reg)) |
2308 | return 1; | |
2309 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2310 | return 1; | |
2311 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2312 | return 1; | |
2313 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2314 | return 1; | |
2315 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2316 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2317 | return 1; |
2318 | } | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | /* This function returns true if modifying a register requires a | |
2324 | delay. */ | |
2325 | ||
2326 | static int | |
17a2f251 | 2327 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2328 | { |
2329 | unsigned long prev_pinfo; | |
2330 | ||
47e39b9d | 2331 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2332 | if (! mips_opts.noreorder |
81912461 ILT |
2333 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2334 | && ! gpr_interlocks) | |
2335 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2336 | && ! cop_interlocks))) | |
252b5132 | 2337 | { |
81912461 ILT |
2338 | /* A load from a coprocessor or from memory. All load delays |
2339 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2340 | /* Itbl support may require additional care here. */ |
252b5132 | 2341 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2342 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2343 | return 1; |
2344 | } | |
2345 | ||
2346 | return 0; | |
2347 | } | |
2348 | ||
404a8071 RS |
2349 | /* Move all labels in insn_labels to the current insertion point. */ |
2350 | ||
2351 | static void | |
2352 | mips_move_labels (void) | |
2353 | { | |
a8dbcb85 | 2354 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2355 | struct insn_label_list *l; |
2356 | valueT val; | |
2357 | ||
a8dbcb85 | 2358 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2359 | { |
9c2799c2 | 2360 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2361 | symbol_set_frag (l->label, frag_now); |
2362 | val = (valueT) frag_now_fix (); | |
2363 | /* mips16 text labels are stored as odd. */ | |
2364 | if (mips_opts.mips16) | |
2365 | ++val; | |
2366 | S_SET_VALUE (l->label, val); | |
2367 | } | |
2368 | } | |
2369 | ||
5f0fe04b TS |
2370 | static bfd_boolean |
2371 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2372 | { | |
2373 | bfd_boolean linkonce = FALSE; | |
2374 | segT symseg = S_GET_SEGMENT (sym); | |
2375 | ||
2376 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2377 | { | |
2378 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2379 | linkonce = TRUE; | |
2380 | #ifdef OBJ_ELF | |
2381 | /* The GNU toolchain uses an extension for ELF: a section | |
2382 | beginning with the magic string .gnu.linkonce is a | |
2383 | linkonce section. */ | |
2384 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2385 | sizeof ".gnu.linkonce" - 1) == 0) | |
2386 | linkonce = TRUE; | |
2387 | #endif | |
2388 | } | |
2389 | return linkonce; | |
2390 | } | |
2391 | ||
252b5132 RH |
2392 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2393 | handle them specially, such as generating jalx instructions when | |
2394 | needed. We also make them odd for the duration of the assembly, in | |
2395 | order to generate the right sort of code. We will make them even | |
2396 | in the adjust_symtab routine, while leaving them marked. This is | |
2397 | convenient for the debugger and the disassembler. The linker knows | |
2398 | to make them odd again. */ | |
2399 | ||
2400 | static void | |
17a2f251 | 2401 | mips16_mark_labels (void) |
252b5132 | 2402 | { |
a8dbcb85 TS |
2403 | segment_info_type *si = seg_info (now_seg); |
2404 | struct insn_label_list *l; | |
252b5132 | 2405 | |
a8dbcb85 TS |
2406 | if (!mips_opts.mips16) |
2407 | return; | |
2408 | ||
2409 | for (l = si->label_list; l != NULL; l = l->next) | |
2410 | { | |
2411 | symbolS *label = l->label; | |
2412 | ||
2413 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2414 | if (IS_ELF) |
30c09090 | 2415 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2416 | #endif |
5f0fe04b TS |
2417 | if ((S_GET_VALUE (label) & 1) == 0 |
2418 | /* Don't adjust the address if the label is global or weak, or | |
2419 | in a link-once section, since we'll be emitting symbol reloc | |
2420 | references to it which will be patched up by the linker, and | |
2421 | the final value of the symbol may or may not be MIPS16. */ | |
2422 | && ! S_IS_WEAK (label) | |
2423 | && ! S_IS_EXTERNAL (label) | |
2424 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2425 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2426 | } |
2427 | } | |
2428 | ||
4d7206a2 RS |
2429 | /* End the current frag. Make it a variant frag and record the |
2430 | relaxation info. */ | |
2431 | ||
2432 | static void | |
2433 | relax_close_frag (void) | |
2434 | { | |
584892a6 | 2435 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2436 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2437 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2438 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2439 | ||
2440 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2441 | mips_relax.first_fixup = 0; | |
2442 | } | |
2443 | ||
2444 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2445 | See the comment above RELAX_ENCODE for more details. */ | |
2446 | ||
2447 | static void | |
2448 | relax_start (symbolS *symbol) | |
2449 | { | |
9c2799c2 | 2450 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2451 | mips_relax.sequence = 1; |
2452 | mips_relax.symbol = symbol; | |
2453 | } | |
2454 | ||
2455 | /* Start generating the second version of a relaxable sequence. | |
2456 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2457 | |
2458 | static void | |
4d7206a2 RS |
2459 | relax_switch (void) |
2460 | { | |
9c2799c2 | 2461 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2462 | mips_relax.sequence = 2; |
2463 | } | |
2464 | ||
2465 | /* End the current relaxable sequence. */ | |
2466 | ||
2467 | static void | |
2468 | relax_end (void) | |
2469 | { | |
9c2799c2 | 2470 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2471 | relax_close_frag (); |
2472 | mips_relax.sequence = 0; | |
2473 | } | |
2474 | ||
71400594 RS |
2475 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2476 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2477 | by VR4120 errata. */ | |
4d7206a2 | 2478 | |
71400594 RS |
2479 | static unsigned int |
2480 | classify_vr4120_insn (const char *name) | |
252b5132 | 2481 | { |
71400594 RS |
2482 | if (strncmp (name, "macc", 4) == 0) |
2483 | return FIX_VR4120_MACC; | |
2484 | if (strncmp (name, "dmacc", 5) == 0) | |
2485 | return FIX_VR4120_DMACC; | |
2486 | if (strncmp (name, "mult", 4) == 0) | |
2487 | return FIX_VR4120_MULT; | |
2488 | if (strncmp (name, "dmult", 5) == 0) | |
2489 | return FIX_VR4120_DMULT; | |
2490 | if (strstr (name, "div")) | |
2491 | return FIX_VR4120_DIV; | |
2492 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2493 | return FIX_VR4120_MTHILO; | |
2494 | return NUM_FIX_VR4120_CLASSES; | |
2495 | } | |
252b5132 | 2496 | |
ff239038 CM |
2497 | #define INSN_ERET 0x42000018 |
2498 | #define INSN_DERET 0x4200001f | |
2499 | ||
71400594 RS |
2500 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2501 | where INSN1 is the earlier instruction. Return the worst-case value | |
2502 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2503 | |
71400594 RS |
2504 | static unsigned int |
2505 | insns_between (const struct mips_cl_insn *insn1, | |
2506 | const struct mips_cl_insn *insn2) | |
2507 | { | |
2508 | unsigned long pinfo1, pinfo2; | |
2509 | ||
2510 | /* This function needs to know which pinfo flags are set for INSN2 | |
2511 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2512 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2513 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2514 | pinfo1 = insn1->insn_mo->pinfo; | |
2515 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2516 | |
71400594 RS |
2517 | #define INSN2_USES_REG(REG, CLASS) \ |
2518 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2519 | ||
2520 | /* For most targets, write-after-read dependencies on the HI and LO | |
2521 | registers must be separated by at least two instructions. */ | |
2522 | if (!hilo_interlocks) | |
252b5132 | 2523 | { |
71400594 RS |
2524 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2525 | return 2; | |
2526 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2527 | return 2; | |
2528 | } | |
2529 | ||
2530 | /* If we're working around r7000 errata, there must be two instructions | |
2531 | between an mfhi or mflo and any instruction that uses the result. */ | |
2532 | if (mips_7000_hilo_fix | |
2533 | && MF_HILO_INSN (pinfo1) | |
2534 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2535 | return 2; | |
2536 | ||
ff239038 CM |
2537 | /* If we're working around 24K errata, one instruction is required |
2538 | if an ERET or DERET is followed by a branch instruction. */ | |
2539 | if (mips_fix_24k) | |
2540 | { | |
2541 | if (insn1->insn_opcode == INSN_ERET | |
2542 | || insn1->insn_opcode == INSN_DERET) | |
2543 | { | |
2544 | if (insn2 == NULL | |
2545 | || insn2->insn_opcode == INSN_ERET | |
2546 | || insn2->insn_opcode == INSN_DERET | |
2547 | || (insn2->insn_mo->pinfo | |
2548 | & (INSN_UNCOND_BRANCH_DELAY | |
2549 | | INSN_COND_BRANCH_DELAY | |
2550 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2551 | return 1; | |
2552 | } | |
2553 | } | |
2554 | ||
71400594 RS |
2555 | /* If working around VR4120 errata, check for combinations that need |
2556 | a single intervening instruction. */ | |
2557 | if (mips_fix_vr4120) | |
2558 | { | |
2559 | unsigned int class1, class2; | |
252b5132 | 2560 | |
71400594 RS |
2561 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2562 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2563 | { |
71400594 RS |
2564 | if (insn2 == NULL) |
2565 | return 1; | |
2566 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2567 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2568 | return 1; | |
252b5132 | 2569 | } |
71400594 RS |
2570 | } |
2571 | ||
2572 | if (!mips_opts.mips16) | |
2573 | { | |
2574 | /* Check for GPR or coprocessor load delays. All such delays | |
2575 | are on the RT register. */ | |
2576 | /* Itbl support may require additional care here. */ | |
2577 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2578 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2579 | { |
71400594 RS |
2580 | know (pinfo1 & INSN_WRITE_GPR_T); |
2581 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2582 | return 1; | |
2583 | } | |
2584 | ||
2585 | /* Check for generic coprocessor hazards. | |
2586 | ||
2587 | This case is not handled very well. There is no special | |
2588 | knowledge of CP0 handling, and the coprocessors other than | |
2589 | the floating point unit are not distinguished at all. */ | |
2590 | /* Itbl support may require additional care here. FIXME! | |
2591 | Need to modify this to include knowledge about | |
2592 | user specified delays! */ | |
2593 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2594 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2595 | { | |
2596 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2597 | register. There must be a one instruction delay before INSN2 | |
2598 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2599 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2600 | { |
71400594 RS |
2601 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2602 | return 1; | |
252b5132 | 2603 | } |
71400594 | 2604 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2605 | { |
71400594 RS |
2606 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2607 | return 1; | |
252b5132 RH |
2608 | } |
2609 | else | |
2610 | { | |
71400594 RS |
2611 | /* Read-after-write dependencies on the control registers |
2612 | require a two-instruction gap. */ | |
2613 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2614 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2615 | return 2; | |
2616 | ||
2617 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2618 | also a coprocessor instruction, assume there must be | |
2619 | a one instruction gap. */ | |
2620 | if (pinfo2 & INSN_COP) | |
2621 | return 1; | |
252b5132 RH |
2622 | } |
2623 | } | |
6b76fefe | 2624 | |
71400594 RS |
2625 | /* Check for read-after-write dependencies on the coprocessor |
2626 | control registers in cases where INSN1 does not need a general | |
2627 | coprocessor delay. This means that INSN1 is a floating point | |
2628 | comparison instruction. */ | |
2629 | /* Itbl support may require additional care here. */ | |
2630 | else if (!cop_interlocks | |
2631 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2632 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2633 | return 1; | |
2634 | } | |
6b76fefe | 2635 | |
71400594 | 2636 | #undef INSN2_USES_REG |
6b76fefe | 2637 | |
71400594 RS |
2638 | return 0; |
2639 | } | |
6b76fefe | 2640 | |
7d8e00cf RS |
2641 | /* Return the number of nops that would be needed to work around the |
2642 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
91d6fa6a | 2643 | the MAX_VR4130_NOPS instructions described by HIST. */ |
7d8e00cf RS |
2644 | |
2645 | static int | |
91d6fa6a | 2646 | nops_for_vr4130 (const struct mips_cl_insn *hist, |
7d8e00cf RS |
2647 | const struct mips_cl_insn *insn) |
2648 | { | |
2649 | int i, j, reg; | |
2650 | ||
2651 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2652 | are not affected by the errata. */ | |
2653 | if (insn != 0 | |
2654 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2655 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2656 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2657 | return 0; | |
2658 | ||
2659 | /* Search for the first MFLO or MFHI. */ | |
2660 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2661 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2662 | { |
2663 | /* Extract the destination register. */ | |
2664 | if (mips_opts.mips16) | |
91d6fa6a | 2665 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])]; |
7d8e00cf | 2666 | else |
91d6fa6a | 2667 | reg = EXTRACT_OPERAND (RD, hist[i]); |
7d8e00cf RS |
2668 | |
2669 | /* No nops are needed if INSN reads that register. */ | |
2670 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2671 | return 0; | |
2672 | ||
2673 | /* ...or if any of the intervening instructions do. */ | |
2674 | for (j = 0; j < i; j++) | |
91d6fa6a | 2675 | if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG)) |
7d8e00cf RS |
2676 | return 0; |
2677 | ||
2678 | return MAX_VR4130_NOPS - i; | |
2679 | } | |
2680 | return 0; | |
2681 | } | |
2682 | ||
71400594 | 2683 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a NC |
2684 | immediately followed the MAX_NOPS instructions given by HIST, |
2685 | where HIST[0] is the most recent instruction. If INSN is null, | |
71400594 | 2686 | return the worse-case number of nops for any instruction. */ |
bdaaa2e1 | 2687 | |
71400594 | 2688 | static int |
91d6fa6a | 2689 | nops_for_insn (const struct mips_cl_insn *hist, |
71400594 RS |
2690 | const struct mips_cl_insn *insn) |
2691 | { | |
2692 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2693 | |
71400594 | 2694 | nops = 0; |
7d8e00cf | 2695 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2696 | { |
91d6fa6a | 2697 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2698 | if (tmp_nops > nops) |
2699 | nops = tmp_nops; | |
2700 | } | |
7d8e00cf RS |
2701 | |
2702 | if (mips_fix_vr4130) | |
2703 | { | |
91d6fa6a | 2704 | tmp_nops = nops_for_vr4130 (hist, insn); |
7d8e00cf RS |
2705 | if (tmp_nops > nops) |
2706 | nops = tmp_nops; | |
2707 | } | |
2708 | ||
71400594 RS |
2709 | return nops; |
2710 | } | |
252b5132 | 2711 | |
71400594 | 2712 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2713 | might be added to HIST. Return the largest number of nops that |
71400594 | 2714 | would be needed after the extended sequence. */ |
252b5132 | 2715 | |
71400594 | 2716 | static int |
91d6fa6a | 2717 | nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...) |
71400594 RS |
2718 | { |
2719 | va_list args; | |
2720 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2721 | struct mips_cl_insn *cursor; | |
2722 | int nops; | |
2723 | ||
91d6fa6a | 2724 | va_start (args, hist); |
71400594 | 2725 | cursor = buffer + num_insns; |
91d6fa6a | 2726 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2727 | while (cursor > buffer) |
2728 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2729 | ||
2730 | nops = nops_for_insn (buffer, NULL); | |
2731 | va_end (args); | |
2732 | return nops; | |
2733 | } | |
252b5132 | 2734 | |
71400594 RS |
2735 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2736 | worst-case delay for the branch target. */ | |
252b5132 | 2737 | |
71400594 | 2738 | static int |
91d6fa6a | 2739 | nops_for_insn_or_target (const struct mips_cl_insn *hist, |
71400594 RS |
2740 | const struct mips_cl_insn *insn) |
2741 | { | |
2742 | int nops, tmp_nops; | |
60b63b72 | 2743 | |
91d6fa6a | 2744 | nops = nops_for_insn (hist, insn); |
71400594 RS |
2745 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
2746 | | INSN_COND_BRANCH_DELAY | |
2747 | | INSN_COND_BRANCH_LIKELY)) | |
2748 | { | |
91d6fa6a | 2749 | tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN); |
71400594 RS |
2750 | if (tmp_nops > nops) |
2751 | nops = tmp_nops; | |
2752 | } | |
9a2c7088 MR |
2753 | else if (mips_opts.mips16 |
2754 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2755 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 2756 | { |
91d6fa6a | 2757 | tmp_nops = nops_for_sequence (1, hist, insn); |
71400594 RS |
2758 | if (tmp_nops > nops) |
2759 | nops = tmp_nops; | |
2760 | } | |
2761 | return nops; | |
2762 | } | |
2763 | ||
c67a084a NC |
2764 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
2765 | ||
2766 | static void | |
2767 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
2768 | { | |
2769 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
2770 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
2771 | } | |
2772 | ||
2773 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
2774 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
2775 | ||
2776 | static void | |
2777 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
2778 | { | |
2779 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
2780 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
2781 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
2782 | { | |
2783 | int sreg; | |
2784 | expressionS ep; | |
2785 | ||
2786 | if (! mips_opts.at) | |
2787 | return; | |
2788 | ||
2789 | sreg = EXTRACT_OPERAND (RS, *ip); | |
2790 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
2791 | return; | |
2792 | ||
2793 | ep.X_op = O_constant; | |
2794 | ep.X_add_number = 0xcfff0000; | |
2795 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
2796 | ep.X_add_number = 0xffff; | |
2797 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
2798 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
2799 | } | |
2800 | } | |
2801 | ||
2802 | static void | |
2803 | fix_loongson2f (struct mips_cl_insn * ip) | |
2804 | { | |
2805 | if (mips_fix_loongson2f_nop) | |
2806 | fix_loongson2f_nop (ip); | |
2807 | ||
2808 | if (mips_fix_loongson2f_jump) | |
2809 | fix_loongson2f_jump (ip); | |
2810 | } | |
2811 | ||
71400594 RS |
2812 | /* Output an instruction. IP is the instruction information. |
2813 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2814 | RELOC_TYPE. */ | |
2815 | ||
2816 | static void | |
2817 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2818 | bfd_reloc_code_real_type *reloc_type) | |
2819 | { | |
3994f87e | 2820 | unsigned long prev_pinfo, pinfo; |
98675402 | 2821 | unsigned long prev_pinfo2, pinfo2; |
71400594 RS |
2822 | relax_stateT prev_insn_frag_type = 0; |
2823 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2824 | segment_info_type *si = seg_info (now_seg); |
71400594 | 2825 | |
c67a084a NC |
2826 | if (mips_fix_loongson2f) |
2827 | fix_loongson2f (ip); | |
2828 | ||
71400594 RS |
2829 | /* Mark instruction labels in mips16 mode. */ |
2830 | mips16_mark_labels (); | |
2831 | ||
738f4d98 MR |
2832 | file_ase_mips16 |= mips_opts.mips16; |
2833 | ||
71400594 | 2834 | prev_pinfo = history[0].insn_mo->pinfo; |
98675402 | 2835 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 2836 | pinfo = ip->insn_mo->pinfo; |
98675402 | 2837 | pinfo2 = ip->insn_mo->pinfo2; |
71400594 RS |
2838 | |
2839 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2840 | { | |
2841 | /* There are a lot of optimizations we could do that we don't. | |
2842 | In particular, we do not, in general, reorder instructions. | |
2843 | If you use gcc with optimization, it will reorder | |
2844 | instructions and generally do much more optimization then we | |
2845 | do here; repeating all that work in the assembler would only | |
2846 | benefit hand written assembly code, and does not seem worth | |
2847 | it. */ | |
2848 | int nops = (mips_optimize == 0 | |
2849 | ? nops_for_insn (history, NULL) | |
2850 | : nops_for_insn_or_target (history, ip)); | |
2851 | if (nops > 0) | |
252b5132 RH |
2852 | { |
2853 | fragS *old_frag; | |
2854 | unsigned long old_frag_offset; | |
2855 | int i; | |
252b5132 RH |
2856 | |
2857 | old_frag = frag_now; | |
2858 | old_frag_offset = frag_now_fix (); | |
2859 | ||
2860 | for (i = 0; i < nops; i++) | |
2861 | emit_nop (); | |
2862 | ||
2863 | if (listing) | |
2864 | { | |
2865 | listing_prev_line (); | |
2866 | /* We may be at the start of a variant frag. In case we | |
2867 | are, make sure there is enough space for the frag | |
2868 | after the frags created by listing_prev_line. The | |
2869 | argument to frag_grow here must be at least as large | |
2870 | as the argument to all other calls to frag_grow in | |
2871 | this file. We don't have to worry about being in the | |
2872 | middle of a variant frag, because the variants insert | |
2873 | all needed nop instructions themselves. */ | |
2874 | frag_grow (40); | |
2875 | } | |
2876 | ||
404a8071 | 2877 | mips_move_labels (); |
252b5132 RH |
2878 | |
2879 | #ifndef NO_ECOFF_DEBUGGING | |
2880 | if (ECOFF_DEBUGGING) | |
2881 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2882 | #endif | |
2883 | } | |
71400594 RS |
2884 | } |
2885 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2886 | { | |
2887 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2888 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2889 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2890 | |
71400594 RS |
2891 | /* Enforce NOPS as a minimum. */ |
2892 | if (nops > prev_nop_frag_required) | |
2893 | prev_nop_frag_required = nops; | |
252b5132 | 2894 | |
71400594 RS |
2895 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2896 | { | |
2897 | /* Settle for the current number of nops. Update the history | |
2898 | accordingly (for the benefit of any future .set reorder code). */ | |
2899 | prev_nop_frag = NULL; | |
2900 | insert_into_history (prev_nop_frag_since, | |
2901 | prev_nop_frag_holds, NOP_INSN); | |
2902 | } | |
2903 | else | |
2904 | { | |
2905 | /* Allow this instruction to replace one of the nops that was | |
2906 | tentatively added to prev_nop_frag. */ | |
2907 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2908 | prev_nop_frag_holds--; | |
2909 | prev_nop_frag_since++; | |
252b5132 RH |
2910 | } |
2911 | } | |
2912 | ||
58e2ea4d MR |
2913 | #ifdef OBJ_ELF |
2914 | /* The value passed to dwarf2_emit_insn is the distance between | |
2915 | the beginning of the current instruction and the address that | |
2916 | should be recorded in the debug tables. For MIPS16 debug info | |
2917 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2918 | address higher by one than the current. */ | |
2919 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2920 | #endif | |
2921 | ||
895921c9 | 2922 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2923 | if (history[0].frag) |
2924 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2925 | |
4d7206a2 | 2926 | if (address_expr |
0b25d3e6 | 2927 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2928 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2929 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2930 | && mips_relax_branch | |
2931 | /* Don't try branch relaxation within .set nomacro, or within | |
2932 | .set noat if we use $at for PIC computations. If it turns | |
2933 | out that the branch was out-of-range, we'll get an error. */ | |
2934 | && !mips_opts.warn_about_macros | |
741fe287 | 2935 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2936 | && !mips_opts.mips16) |
2937 | { | |
895921c9 | 2938 | relaxed_branch = TRUE; |
1e915849 RS |
2939 | add_relaxed_insn (ip, (relaxed_branch_length |
2940 | (NULL, NULL, | |
2941 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2942 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2943 | : 0)), 4, | |
2944 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
2945 | (AT, |
2946 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
2947 | pinfo & INSN_COND_BRANCH_LIKELY, |
2948 | pinfo & INSN_WRITE_GPR_31, | |
2949 | 0), | |
2950 | address_expr->X_add_symbol, | |
2951 | address_expr->X_add_number); | |
4a6a3df4 AO |
2952 | *reloc_type = BFD_RELOC_UNUSED; |
2953 | } | |
2954 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2955 | { |
2956 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2957 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2958 | add_relaxed_insn (ip, 4, 0, |
2959 | RELAX_MIPS16_ENCODE | |
2960 | (*reloc_type - BFD_RELOC_UNUSED, | |
2961 | mips16_small, mips16_ext, | |
2962 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2963 | history[0].mips16_absolute_jump_p), | |
2964 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2965 | } |
252b5132 RH |
2966 | else if (mips_opts.mips16 |
2967 | && ! ip->use_extend | |
f6688943 | 2968 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2969 | { |
b8ee1a6e DU |
2970 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2971 | /* Make sure there is enough room to swap this instruction with | |
2972 | a following jump instruction. */ | |
2973 | frag_grow (6); | |
1e915849 | 2974 | add_fixed_insn (ip); |
252b5132 RH |
2975 | } |
2976 | else | |
2977 | { | |
2978 | if (mips_opts.mips16 | |
2979 | && mips_opts.noreorder | |
2980 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2981 | as_warn (_("extended instruction in delay slot")); | |
2982 | ||
4d7206a2 RS |
2983 | if (mips_relax.sequence) |
2984 | { | |
2985 | /* If we've reached the end of this frag, turn it into a variant | |
2986 | frag and record the information for the instructions we've | |
2987 | written so far. */ | |
2988 | if (frag_room () < 4) | |
2989 | relax_close_frag (); | |
2990 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2991 | } | |
2992 | ||
584892a6 RS |
2993 | if (mips_relax.sequence != 2) |
2994 | mips_macro_warning.sizes[0] += 4; | |
2995 | if (mips_relax.sequence != 1) | |
2996 | mips_macro_warning.sizes[1] += 4; | |
2997 | ||
1e915849 RS |
2998 | if (mips_opts.mips16) |
2999 | { | |
3000 | ip->fixed_p = 1; | |
3001 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
3002 | } | |
3003 | add_fixed_insn (ip); | |
252b5132 RH |
3004 | } |
3005 | ||
01a3f561 | 3006 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
3007 | { |
3008 | if (address_expr->X_op == O_constant) | |
3009 | { | |
f17c130b | 3010 | unsigned int tmp; |
f6688943 TS |
3011 | |
3012 | switch (*reloc_type) | |
252b5132 RH |
3013 | { |
3014 | case BFD_RELOC_32: | |
3015 | ip->insn_opcode |= address_expr->X_add_number; | |
3016 | break; | |
3017 | ||
f6688943 | 3018 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
3019 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
3020 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3021 | break; |
3022 | ||
3023 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
3024 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
3025 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3026 | break; |
3027 | ||
3028 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
3029 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
3030 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3031 | break; |
3032 | ||
3033 | case BFD_RELOC_HI16: | |
3034 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3035 | break; | |
3036 | ||
01a3f561 | 3037 | case BFD_RELOC_UNUSED: |
252b5132 | 3038 | case BFD_RELOC_LO16: |
ed6fb7bd | 3039 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
3040 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
3041 | break; | |
3042 | ||
3043 | case BFD_RELOC_MIPS_JMP: | |
3044 | if ((address_expr->X_add_number & 3) != 0) | |
3045 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3046 | (unsigned long) address_expr->X_add_number); | |
3047 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3048 | break; | |
3049 | ||
3050 | case BFD_RELOC_MIPS16_JMP: | |
3051 | if ((address_expr->X_add_number & 3) != 0) | |
3052 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3053 | (unsigned long) address_expr->X_add_number); | |
3054 | ip->insn_opcode |= | |
3055 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3056 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3057 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3058 | break; | |
3059 | ||
252b5132 | 3060 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
3061 | if ((address_expr->X_add_number & 3) != 0) |
3062 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3063 | (unsigned long) address_expr->X_add_number); | |
3064 | if (mips_relax_branch) | |
3065 | goto need_reloc; | |
3066 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3067 | as_bad (_("branch address range overflow (0x%lx)"), | |
3068 | (unsigned long) address_expr->X_add_number); | |
3069 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3070 | break; | |
252b5132 RH |
3071 | |
3072 | default: | |
3073 | internalError (); | |
3074 | } | |
3075 | } | |
01a3f561 | 3076 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3077 | need_reloc: |
4d7206a2 RS |
3078 | { |
3079 | reloc_howto_type *howto; | |
3080 | int i; | |
34ce925e | 3081 | |
4d7206a2 RS |
3082 | /* In a compound relocation, it is the final (outermost) |
3083 | operator that determines the relocated field. */ | |
3084 | for (i = 1; i < 3; i++) | |
3085 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3086 | break; | |
34ce925e | 3087 | |
4d7206a2 | 3088 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3089 | if (howto == NULL) |
3090 | { | |
3091 | /* To reproduce this failure try assembling gas/testsuites/ | |
3092 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3093 | assembler. */ | |
3094 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3095 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3096 | } | |
3097 | ||
1e915849 RS |
3098 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3099 | bfd_get_reloc_size (howto), | |
3100 | address_expr, | |
3101 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3102 | reloc_type[0]); | |
4d7206a2 | 3103 | |
b314ec0e RS |
3104 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3105 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3106 | && ip->fixp[0]->fx_addsy) | |
3107 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3108 | ||
4d7206a2 RS |
3109 | /* These relocations can have an addend that won't fit in |
3110 | 4 octets for 64bit assembly. */ | |
3111 | if (HAVE_64BIT_GPRS | |
3112 | && ! howto->partial_inplace | |
3113 | && (reloc_type[0] == BFD_RELOC_16 | |
3114 | || reloc_type[0] == BFD_RELOC_32 | |
3115 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3116 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3117 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3118 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3119 | || reloc_type[0] == BFD_RELOC_64 | |
3120 | || reloc_type[0] == BFD_RELOC_CTOR | |
3121 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3122 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3123 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3124 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3125 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3126 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3127 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3128 | || hi16_reloc_p (reloc_type[0]) |
3129 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3130 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3131 | |
3132 | if (mips_relax.sequence) | |
3133 | { | |
3134 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3135 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3136 | } |
3137 | else if (reloc_needs_lo_p (*reloc_type)) | |
3138 | { | |
3139 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3140 | |
4d7206a2 RS |
3141 | /* Reuse the last entry if it already has a matching %lo. */ |
3142 | hi_fixup = mips_hi_fixup_list; | |
3143 | if (hi_fixup == 0 | |
3144 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3145 | { | |
3146 | hi_fixup = ((struct mips_hi_fixup *) | |
3147 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3148 | hi_fixup->next = mips_hi_fixup_list; | |
3149 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3150 | } |
1e915849 | 3151 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3152 | hi_fixup->seg = now_seg; |
3153 | } | |
f6688943 | 3154 | |
4d7206a2 RS |
3155 | /* Add fixups for the second and third relocations, if given. |
3156 | Note that the ABI allows the second relocation to be | |
3157 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3158 | moment we only use RSS_UNDEF, but we could add support | |
3159 | for the others if it ever becomes necessary. */ | |
3160 | for (i = 1; i < 3; i++) | |
3161 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3162 | { | |
1e915849 RS |
3163 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3164 | ip->fixp[0]->fx_size, NULL, 0, | |
3165 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3166 | |
3167 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3168 | ip->fixp[0]->fx_tcbit = 1; |
3169 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3170 | } |
252b5132 RH |
3171 | } |
3172 | } | |
1e915849 | 3173 | install_insn (ip); |
252b5132 RH |
3174 | |
3175 | /* Update the register mask information. */ | |
3176 | if (! mips_opts.mips16) | |
3177 | { | |
98675402 | 3178 | if ((pinfo & INSN_WRITE_GPR_D) || (pinfo2 & INSN2_READ_GPR_D)) |
bf12938e | 3179 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3180 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3181 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3182 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3183 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3184 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3185 | mips_gprmask |= 1 << RA; |
98675402 RS |
3186 | if (pinfo2 & (INSN2_WRITE_GPR_Z | INSN2_READ_GPR_Z)) |
3187 | mips_gprmask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 3188 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3189 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3190 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3191 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3192 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3193 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3194 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3195 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
98675402 RS |
3196 | if (pinfo2 & (INSN2_WRITE_FPR_Z | INSN2_READ_FPR_Z)) |
3197 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
252b5132 RH |
3198 | if (pinfo & INSN_COP) |
3199 | { | |
bdaaa2e1 KH |
3200 | /* We don't keep enough information to sort these cases out. |
3201 | The itbl support does keep this information however, although | |
3202 | we currently don't support itbl fprmats as part of the cop | |
3203 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3204 | } |
3205 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3206 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3207 | } |
3208 | else | |
3209 | { | |
3210 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3211 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3212 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3213 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3214 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3215 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3216 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3217 | mips_gprmask |= 1 << TREG; | |
3218 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3219 | mips_gprmask |= 1 << SP; | |
3220 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3221 | mips_gprmask |= 1 << RA; | |
3222 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3223 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3224 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3225 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3226 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3227 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3228 | } |
3229 | ||
4d7206a2 | 3230 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3231 | { |
3232 | /* Filling the branch delay slot is more complex. We try to | |
3233 | switch the branch with the previous instruction, which we can | |
3234 | do if the previous instruction does not set up a condition | |
3235 | that the branch tests and if the branch is not itself the | |
3236 | target of any branch. */ | |
3237 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3238 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3239 | { | |
3240 | if (mips_optimize < 2 | |
3241 | /* If we have seen .set volatile or .set nomove, don't | |
3242 | optimize. */ | |
3243 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3244 | /* We can't swap if the previous instruction's position |
3245 | is fixed. */ | |
3246 | || history[0].fixed_p | |
252b5132 RH |
3247 | /* If the previous previous insn was in a .set |
3248 | noreorder, we can't swap. Actually, the MIPS | |
3249 | assembler will swap in this situation. However, gcc | |
3250 | configured -with-gnu-as will generate code like | |
3251 | .set noreorder | |
3252 | lw $4,XXX | |
3253 | .set reorder | |
3254 | INSN | |
3255 | bne $4,$0,foo | |
3256 | in which we can not swap the bne and INSN. If gcc is | |
3257 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3258 | .set pseudo-ops. */ |
47e39b9d | 3259 | || history[1].noreorder_p |
252b5132 RH |
3260 | /* If the branch is itself the target of a branch, we |
3261 | can not swap. We cheat on this; all we check for is | |
3262 | whether there is a label on this instruction. If | |
3263 | there are any branches to anything other than a | |
3264 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3265 | || si->label_list != NULL |
895921c9 MR |
3266 | /* If the previous instruction is in a variant frag |
3267 | other than this branch's one, we cannot do the swap. | |
3268 | This does not apply to the mips16, which uses variant | |
3269 | frags for different purposes. */ | |
252b5132 | 3270 | || (! mips_opts.mips16 |
895921c9 | 3271 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3272 | /* Check for conflicts between the branch and the instructions |
3273 | before the candidate delay slot. */ | |
3274 | || nops_for_insn (history + 1, ip) > 0 | |
3275 | /* Check for conflicts between the swapped sequence and the | |
3276 | target of the branch. */ | |
3277 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3278 | /* We do not swap with a trap instruction, since it |
3279 | complicates trap handlers to have the trap | |
3280 | instruction be in a delay slot. */ | |
3281 | || (prev_pinfo & INSN_TRAP) | |
3282 | /* If the branch reads a register that the previous | |
3283 | instruction sets, we can not swap. */ | |
3284 | || (! mips_opts.mips16 | |
3285 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3286 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3287 | MIPS_GR_REG)) |
3288 | || (! mips_opts.mips16 | |
3289 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3290 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 | 3291 | MIPS_GR_REG)) |
98675402 RS |
3292 | || (! mips_opts.mips16 |
3293 | && (prev_pinfo2 & INSN2_WRITE_GPR_Z) | |
3294 | && insn_uses_reg (ip, EXTRACT_OPERAND (RZ, history[0]), | |
3295 | MIPS_GR_REG)) | |
252b5132 RH |
3296 | || (mips_opts.mips16 |
3297 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3298 | && (insn_uses_reg |
3299 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3300 | MIPS16_REG))) | |
252b5132 | 3301 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3302 | && (insn_uses_reg |
3303 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3304 | MIPS16_REG))) | |
252b5132 | 3305 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3306 | && (insn_uses_reg |
3307 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3308 | MIPS16_REG))) | |
252b5132 RH |
3309 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3310 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3311 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3312 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3313 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3314 | && insn_uses_reg (ip, | |
47e39b9d RS |
3315 | MIPS16OP_EXTRACT_REG32R |
3316 | (history[0].insn_opcode), | |
252b5132 RH |
3317 | MIPS_GR_REG)))) |
3318 | /* If the branch writes a register that the previous | |
3319 | instruction sets, we can not swap (we know that | |
3320 | branches write only to RD or to $31). */ | |
3321 | || (! mips_opts.mips16 | |
3322 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3323 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3324 | && (EXTRACT_OPERAND (RT, history[0]) |
3325 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3326 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3327 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3328 | || (! mips_opts.mips16 |
3329 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3330 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3331 | && (EXTRACT_OPERAND (RD, history[0]) |
3332 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3333 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3334 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3335 | || (mips_opts.mips16 |
3336 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3337 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3338 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3339 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3340 | == RA)))) |
3341 | /* If the branch writes a register that the previous | |
3342 | instruction reads, we can not swap (we know that | |
3343 | branches only write to RD or to $31). */ | |
3344 | || (! mips_opts.mips16 | |
3345 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3346 | && insn_uses_reg (&history[0], |
bf12938e | 3347 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3348 | MIPS_GR_REG)) |
3349 | || (! mips_opts.mips16 | |
3350 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3351 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3352 | || (mips_opts.mips16 |
3353 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3354 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3355 | /* If one instruction sets a condition code and the |
3356 | other one uses a condition code, we can not swap. */ | |
3357 | || ((pinfo & INSN_READ_COND_CODE) | |
3358 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3359 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3360 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3361 | /* If the previous instruction uses the PC, we can not | |
3362 | swap. */ | |
3363 | || (mips_opts.mips16 | |
3364 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3365 | /* If the previous instruction had a fixup in mips16 |
3366 | mode, we can not swap. This normally means that the | |
3367 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3368 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3369 | /* If the previous instruction is a sync, sync.l, or |
3370 | sync.p, we can not swap. */ | |
6a32d874 CM |
3371 | || (prev_pinfo & INSN_SYNC) |
3372 | /* If the previous instruction is an ERET or | |
3373 | DERET, avoid the swap. */ | |
3374 | || (history[0].insn_opcode == INSN_ERET) | |
3375 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3376 | { |
29024861 DU |
3377 | if (mips_opts.mips16 |
3378 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3379 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3380 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3381 | { |
3382 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3383 | ip->insn_opcode |= 0x0080; | |
3384 | install_insn (ip); | |
3385 | insert_into_history (0, 1, ip); | |
3386 | } | |
3387 | else | |
3388 | { | |
3389 | /* We could do even better for unconditional branches to | |
3390 | portions of this object file; we could pick up the | |
3391 | instruction at the destination, put it in the delay | |
3392 | slot, and bump the destination address. */ | |
3393 | insert_into_history (0, 1, ip); | |
3394 | emit_nop (); | |
3395 | } | |
3396 | ||
dd22970f ILT |
3397 | if (mips_relax.sequence) |
3398 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3399 | } |
3400 | else | |
3401 | { | |
3402 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3403 | struct mips_cl_insn delay = history[0]; |
3404 | if (mips_opts.mips16) | |
252b5132 | 3405 | { |
b8ee1a6e DU |
3406 | know (delay.frag == ip->frag); |
3407 | move_insn (ip, delay.frag, delay.where); | |
3408 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3409 | } |
3410 | else if (relaxed_branch) | |
3411 | { | |
3412 | /* Add the delay slot instruction to the end of the | |
3413 | current frag and shrink the fixed part of the | |
3414 | original frag. If the branch occupies the tail of | |
3415 | the latter, move it backwards to cover the gap. */ | |
3416 | delay.frag->fr_fix -= 4; | |
3417 | if (delay.frag == ip->frag) | |
3418 | move_insn (ip, ip->frag, ip->where - 4); | |
3419 | add_fixed_insn (&delay); | |
252b5132 RH |
3420 | } |
3421 | else | |
3422 | { | |
1e915849 RS |
3423 | move_insn (&delay, ip->frag, ip->where); |
3424 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3425 | } |
1e915849 RS |
3426 | history[0] = *ip; |
3427 | delay.fixed_p = 1; | |
3428 | insert_into_history (0, 1, &delay); | |
252b5132 | 3429 | } |
252b5132 RH |
3430 | |
3431 | /* If that was an unconditional branch, forget the previous | |
3432 | insn information. */ | |
3433 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3434 | { |
6a32d874 CM |
3435 | mips_no_prev_insn (); |
3436 | } | |
252b5132 RH |
3437 | } |
3438 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3439 | { | |
3440 | /* We don't yet optimize a branch likely. What we should do | |
3441 | is look at the target, copy the instruction found there | |
3442 | into the delay slot, and increment the branch to jump to | |
3443 | the next instruction. */ | |
1e915849 | 3444 | insert_into_history (0, 1, ip); |
252b5132 | 3445 | emit_nop (); |
252b5132 RH |
3446 | } |
3447 | else | |
1e915849 | 3448 | insert_into_history (0, 1, ip); |
252b5132 | 3449 | } |
1e915849 RS |
3450 | else |
3451 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3452 | |
3453 | /* We just output an insn, so the next one doesn't have a label. */ | |
3454 | mips_clear_insn_labels (); | |
252b5132 RH |
3455 | } |
3456 | ||
7d10b47d | 3457 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3458 | |
3459 | static void | |
7d10b47d | 3460 | mips_no_prev_insn (void) |
252b5132 | 3461 | { |
7d10b47d RS |
3462 | prev_nop_frag = NULL; |
3463 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3464 | mips_clear_insn_labels (); |
3465 | } | |
3466 | ||
7d10b47d RS |
3467 | /* This function must be called before we emit something other than |
3468 | instructions. It is like mips_no_prev_insn except that it inserts | |
3469 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3470 | |
7d10b47d RS |
3471 | void |
3472 | mips_emit_delays (void) | |
252b5132 RH |
3473 | { |
3474 | if (! mips_opts.noreorder) | |
3475 | { | |
71400594 | 3476 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3477 | if (nops > 0) |
3478 | { | |
7d10b47d RS |
3479 | while (nops-- > 0) |
3480 | add_fixed_insn (NOP_INSN); | |
3481 | mips_move_labels (); | |
3482 | } | |
3483 | } | |
3484 | mips_no_prev_insn (); | |
3485 | } | |
3486 | ||
3487 | /* Start a (possibly nested) noreorder block. */ | |
3488 | ||
3489 | static void | |
3490 | start_noreorder (void) | |
3491 | { | |
3492 | if (mips_opts.noreorder == 0) | |
3493 | { | |
3494 | unsigned int i; | |
3495 | int nops; | |
3496 | ||
3497 | /* None of the instructions before the .set noreorder can be moved. */ | |
3498 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3499 | history[i].fixed_p = 1; | |
3500 | ||
3501 | /* Insert any nops that might be needed between the .set noreorder | |
3502 | block and the previous instructions. We will later remove any | |
3503 | nops that turn out not to be needed. */ | |
3504 | nops = nops_for_insn (history, NULL); | |
3505 | if (nops > 0) | |
3506 | { | |
3507 | if (mips_optimize != 0) | |
252b5132 RH |
3508 | { |
3509 | /* Record the frag which holds the nop instructions, so | |
3510 | that we can remove them if we don't need them. */ | |
3511 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3512 | prev_nop_frag = frag_now; | |
3513 | prev_nop_frag_holds = nops; | |
3514 | prev_nop_frag_required = 0; | |
3515 | prev_nop_frag_since = 0; | |
3516 | } | |
3517 | ||
3518 | for (; nops > 0; --nops) | |
1e915849 | 3519 | add_fixed_insn (NOP_INSN); |
252b5132 | 3520 | |
7d10b47d RS |
3521 | /* Move on to a new frag, so that it is safe to simply |
3522 | decrease the size of prev_nop_frag. */ | |
3523 | frag_wane (frag_now); | |
3524 | frag_new (0); | |
404a8071 | 3525 | mips_move_labels (); |
252b5132 | 3526 | } |
7d10b47d RS |
3527 | mips16_mark_labels (); |
3528 | mips_clear_insn_labels (); | |
252b5132 | 3529 | } |
7d10b47d RS |
3530 | mips_opts.noreorder++; |
3531 | mips_any_noreorder = 1; | |
3532 | } | |
252b5132 | 3533 | |
7d10b47d | 3534 | /* End a nested noreorder block. */ |
252b5132 | 3535 | |
7d10b47d RS |
3536 | static void |
3537 | end_noreorder (void) | |
3538 | { | |
6a32d874 | 3539 | |
7d10b47d RS |
3540 | mips_opts.noreorder--; |
3541 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3542 | { | |
3543 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3544 | handling nop insertion the .set reorder way. */ | |
3545 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3546 | * (mips_opts.mips16 ? 2 : 4)); | |
3547 | insert_into_history (prev_nop_frag_since, | |
3548 | prev_nop_frag_required, NOP_INSN); | |
3549 | prev_nop_frag = NULL; | |
3550 | } | |
252b5132 RH |
3551 | } |
3552 | ||
584892a6 RS |
3553 | /* Set up global variables for the start of a new macro. */ |
3554 | ||
3555 | static void | |
3556 | macro_start (void) | |
3557 | { | |
3558 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3559 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3560 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3561 | & (INSN_UNCOND_BRANCH_DELAY |
3562 | | INSN_COND_BRANCH_DELAY | |
3563 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3564 | } | |
3565 | ||
3566 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3567 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3568 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3569 | ||
3570 | static const char * | |
3571 | macro_warning (relax_substateT subtype) | |
3572 | { | |
3573 | if (subtype & RELAX_DELAY_SLOT) | |
3574 | return _("Macro instruction expanded into multiple instructions" | |
3575 | " in a branch delay slot"); | |
3576 | else if (subtype & RELAX_NOMACRO) | |
3577 | return _("Macro instruction expanded into multiple instructions"); | |
3578 | else | |
3579 | return 0; | |
3580 | } | |
3581 | ||
3582 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3583 | ||
3584 | static void | |
3585 | macro_end (void) | |
3586 | { | |
3587 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3588 | { | |
3589 | relax_substateT subtype; | |
3590 | ||
3591 | /* Set up the relaxation warning flags. */ | |
3592 | subtype = 0; | |
3593 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3594 | subtype |= RELAX_SECOND_LONGER; | |
3595 | if (mips_opts.warn_about_macros) | |
3596 | subtype |= RELAX_NOMACRO; | |
3597 | if (mips_macro_warning.delay_slot_p) | |
3598 | subtype |= RELAX_DELAY_SLOT; | |
3599 | ||
3600 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3601 | { | |
3602 | /* Either the macro has a single implementation or both | |
3603 | implementations are longer than 4 bytes. Emit the | |
3604 | warning now. */ | |
3605 | const char *msg = macro_warning (subtype); | |
3606 | if (msg != 0) | |
520725ea | 3607 | as_warn ("%s", msg); |
584892a6 RS |
3608 | } |
3609 | else | |
3610 | { | |
3611 | /* One implementation might need a warning but the other | |
3612 | definitely doesn't. */ | |
3613 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3614 | } | |
3615 | } | |
3616 | } | |
3617 | ||
6e1304d8 RS |
3618 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3619 | The first argument in *ARGS will be either the code for a single | |
3620 | relocation or -1 followed by the three codes that make up a | |
3621 | composite relocation. */ | |
3622 | ||
3623 | static void | |
3624 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3625 | { | |
3626 | int i, next; | |
3627 | ||
3628 | next = va_arg (*args, int); | |
3629 | if (next >= 0) | |
3630 | r[0] = (bfd_reloc_code_real_type) next; | |
3631 | else | |
3632 | for (i = 0; i < 3; i++) | |
3633 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3634 | } | |
3635 | ||
252b5132 RH |
3636 | /* Build an instruction created by a macro expansion. This is passed |
3637 | a pointer to the count of instructions created so far, an | |
3638 | expression, the name of the instruction to build, an operand format | |
3639 | string, and corresponding arguments. */ | |
3640 | ||
252b5132 | 3641 | static void |
67c0d1eb | 3642 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3643 | { |
1e915849 | 3644 | const struct mips_opcode *mo; |
252b5132 | 3645 | struct mips_cl_insn insn; |
f6688943 | 3646 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3647 | va_list args; |
252b5132 | 3648 | |
252b5132 | 3649 | va_start (args, fmt); |
252b5132 | 3650 | |
252b5132 RH |
3651 | if (mips_opts.mips16) |
3652 | { | |
03ea81db | 3653 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3654 | va_end (args); |
3655 | return; | |
3656 | } | |
3657 | ||
f6688943 TS |
3658 | r[0] = BFD_RELOC_UNUSED; |
3659 | r[1] = BFD_RELOC_UNUSED; | |
3660 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3661 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3662 | gas_assert (mo); |
3663 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3664 | |
8b082fb1 TS |
3665 | while (1) |
3666 | { | |
3667 | /* Search until we get a match for NAME. It is assumed here that | |
3668 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3669 | if (strcmp (fmt, mo->args) == 0 | |
3670 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3671 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3672 | break; |
3673 | ||
1e915849 | 3674 | ++mo; |
9c2799c2 NC |
3675 | gas_assert (mo->name); |
3676 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3677 | } |
3678 | ||
1e915849 | 3679 | create_insn (&insn, mo); |
252b5132 RH |
3680 | for (;;) |
3681 | { | |
3682 | switch (*fmt++) | |
3683 | { | |
3684 | case '\0': | |
3685 | break; | |
3686 | ||
3687 | case ',': | |
3688 | case '(': | |
3689 | case ')': | |
3690 | continue; | |
3691 | ||
5f74bc13 CD |
3692 | case '+': |
3693 | switch (*fmt++) | |
3694 | { | |
3695 | case 'A': | |
3696 | case 'E': | |
bf12938e | 3697 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3698 | continue; |
3699 | ||
3700 | case 'B': | |
3701 | case 'F': | |
3702 | /* Note that in the macro case, these arguments are already | |
3703 | in MSB form. (When handling the instruction in the | |
3704 | non-macro case, these arguments are sizes from which | |
3705 | MSB values must be calculated.) */ | |
bf12938e | 3706 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3707 | continue; |
3708 | ||
3709 | case 'C': | |
3710 | case 'G': | |
3711 | case 'H': | |
3712 | /* Note that in the macro case, these arguments are already | |
3713 | in MSBD form. (When handling the instruction in the | |
3714 | non-macro case, these arguments are sizes from which | |
3715 | MSBD values must be calculated.) */ | |
bf12938e | 3716 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3717 | continue; |
3718 | ||
dd3cbb7e NC |
3719 | case 'Q': |
3720 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3721 | continue; | |
3722 | ||
5f74bc13 CD |
3723 | default: |
3724 | internalError (); | |
3725 | } | |
3726 | continue; | |
3727 | ||
8b082fb1 TS |
3728 | case '2': |
3729 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3730 | continue; | |
3731 | ||
252b5132 RH |
3732 | case 't': |
3733 | case 'w': | |
3734 | case 'E': | |
bf12938e | 3735 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3736 | continue; |
3737 | ||
3738 | case 'c': | |
bf12938e | 3739 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3740 | continue; |
3741 | ||
252b5132 RH |
3742 | case 'T': |
3743 | case 'W': | |
bf12938e | 3744 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3745 | continue; |
3746 | ||
3747 | case 'd': | |
3748 | case 'G': | |
af7ee8bf | 3749 | case 'K': |
bf12938e | 3750 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3751 | continue; |
3752 | ||
4372b673 NC |
3753 | case 'U': |
3754 | { | |
3755 | int tmp = va_arg (args, int); | |
3756 | ||
bf12938e RS |
3757 | INSERT_OPERAND (RT, insn, tmp); |
3758 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3759 | continue; |
4372b673 NC |
3760 | } |
3761 | ||
252b5132 RH |
3762 | case 'V': |
3763 | case 'S': | |
bf12938e | 3764 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3765 | continue; |
3766 | ||
3767 | case 'z': | |
3768 | continue; | |
3769 | ||
3770 | case '<': | |
bf12938e | 3771 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3772 | continue; |
3773 | ||
3774 | case 'D': | |
bf12938e | 3775 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3776 | continue; |
3777 | ||
3778 | case 'B': | |
bf12938e | 3779 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3780 | continue; |
3781 | ||
4372b673 | 3782 | case 'J': |
bf12938e | 3783 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3784 | continue; |
3785 | ||
252b5132 | 3786 | case 'q': |
bf12938e | 3787 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3788 | continue; |
3789 | ||
3790 | case 'b': | |
3791 | case 's': | |
3792 | case 'r': | |
3793 | case 'v': | |
bf12938e | 3794 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3795 | continue; |
3796 | ||
3797 | case 'i': | |
3798 | case 'j': | |
6e1304d8 | 3799 | macro_read_relocs (&args, r); |
9c2799c2 | 3800 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
3801 | || *r == BFD_RELOC_MIPS_HIGHER |
3802 | || *r == BFD_RELOC_HI16_S | |
3803 | || *r == BFD_RELOC_LO16 | |
3804 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
3805 | continue; | |
3806 | ||
3807 | case 'o': | |
3808 | macro_read_relocs (&args, r); | |
252b5132 RH |
3809 | continue; |
3810 | ||
3811 | case 'u': | |
6e1304d8 | 3812 | macro_read_relocs (&args, r); |
9c2799c2 | 3813 | gas_assert (ep != NULL |
90ecf173 MR |
3814 | && (ep->X_op == O_constant |
3815 | || (ep->X_op == O_symbol | |
3816 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
3817 | || *r == BFD_RELOC_HI16_S | |
3818 | || *r == BFD_RELOC_HI16 | |
3819 | || *r == BFD_RELOC_GPREL16 | |
3820 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3821 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
3822 | continue; |
3823 | ||
3824 | case 'p': | |
9c2799c2 | 3825 | gas_assert (ep != NULL); |
bad36eac | 3826 | |
252b5132 RH |
3827 | /* |
3828 | * This allows macro() to pass an immediate expression for | |
3829 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3830 | * |
3831 | * We don't allow branch relaxation for these branches, as | |
3832 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3833 | */ |
3834 | if (ep->X_op == O_constant) | |
3835 | { | |
bad36eac DJ |
3836 | if ((ep->X_add_number & 3) != 0) |
3837 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3838 | (unsigned long) ep->X_add_number); | |
3839 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3840 | as_bad (_("branch address range overflow (0x%lx)"), | |
3841 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3842 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3843 | ep = NULL; | |
3844 | } | |
3845 | else | |
0b25d3e6 | 3846 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3847 | continue; |
3848 | ||
3849 | case 'a': | |
9c2799c2 | 3850 | gas_assert (ep != NULL); |
f6688943 | 3851 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3852 | continue; |
3853 | ||
3854 | case 'C': | |
a9e24354 | 3855 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3856 | continue; |
3857 | ||
d43b4baf | 3858 | case 'k': |
a9e24354 | 3859 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3860 | continue; |
3861 | ||
252b5132 RH |
3862 | default: |
3863 | internalError (); | |
3864 | } | |
3865 | break; | |
3866 | } | |
3867 | va_end (args); | |
9c2799c2 | 3868 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3869 | |
4d7206a2 | 3870 | append_insn (&insn, ep, r); |
252b5132 RH |
3871 | } |
3872 | ||
3873 | static void | |
67c0d1eb | 3874 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 3875 | va_list *args) |
252b5132 | 3876 | { |
1e915849 | 3877 | struct mips_opcode *mo; |
252b5132 | 3878 | struct mips_cl_insn insn; |
f6688943 TS |
3879 | bfd_reloc_code_real_type r[3] |
3880 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3881 | |
1e915849 | 3882 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3883 | gas_assert (mo); |
3884 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3885 | |
1e915849 | 3886 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3887 | { |
1e915849 | 3888 | ++mo; |
9c2799c2 NC |
3889 | gas_assert (mo->name); |
3890 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3891 | } |
3892 | ||
1e915849 | 3893 | create_insn (&insn, mo); |
252b5132 RH |
3894 | for (;;) |
3895 | { | |
3896 | int c; | |
3897 | ||
3898 | c = *fmt++; | |
3899 | switch (c) | |
3900 | { | |
3901 | case '\0': | |
3902 | break; | |
3903 | ||
3904 | case ',': | |
3905 | case '(': | |
3906 | case ')': | |
3907 | continue; | |
3908 | ||
3909 | case 'y': | |
3910 | case 'w': | |
03ea81db | 3911 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
3912 | continue; |
3913 | ||
3914 | case 'x': | |
3915 | case 'v': | |
03ea81db | 3916 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
3917 | continue; |
3918 | ||
3919 | case 'z': | |
03ea81db | 3920 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
3921 | continue; |
3922 | ||
3923 | case 'Z': | |
03ea81db | 3924 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
3925 | continue; |
3926 | ||
3927 | case '0': | |
3928 | case 'S': | |
3929 | case 'P': | |
3930 | case 'R': | |
3931 | continue; | |
3932 | ||
3933 | case 'X': | |
03ea81db | 3934 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
3935 | continue; |
3936 | ||
3937 | case 'Y': | |
3938 | { | |
3939 | int regno; | |
3940 | ||
03ea81db | 3941 | regno = va_arg (*args, int); |
252b5132 | 3942 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 3943 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3944 | } |
3945 | continue; | |
3946 | ||
3947 | case '<': | |
3948 | case '>': | |
3949 | case '4': | |
3950 | case '5': | |
3951 | case 'H': | |
3952 | case 'W': | |
3953 | case 'D': | |
3954 | case 'j': | |
3955 | case '8': | |
3956 | case 'V': | |
3957 | case 'C': | |
3958 | case 'U': | |
3959 | case 'k': | |
3960 | case 'K': | |
3961 | case 'p': | |
3962 | case 'q': | |
3963 | { | |
9c2799c2 | 3964 | gas_assert (ep != NULL); |
252b5132 RH |
3965 | |
3966 | if (ep->X_op != O_constant) | |
874e8986 | 3967 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3968 | else |
3969 | { | |
b34976b6 AM |
3970 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3971 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3972 | &insn.extend); |
252b5132 | 3973 | ep = NULL; |
f6688943 | 3974 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3975 | } |
3976 | } | |
3977 | continue; | |
3978 | ||
3979 | case '6': | |
03ea81db | 3980 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
3981 | continue; |
3982 | } | |
3983 | ||
3984 | break; | |
3985 | } | |
3986 | ||
9c2799c2 | 3987 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3988 | |
4d7206a2 | 3989 | append_insn (&insn, ep, r); |
252b5132 RH |
3990 | } |
3991 | ||
2051e8c4 MR |
3992 | /* |
3993 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3994 | * higher bits unset. | |
3995 | */ | |
9f872bbe | 3996 | static void |
2051e8c4 MR |
3997 | normalize_constant_expr (expressionS *ex) |
3998 | { | |
9ee2a2d4 | 3999 | if (ex->X_op == O_constant |
2051e8c4 MR |
4000 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
4001 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4002 | - 0x80000000); | |
4003 | } | |
4004 | ||
4005 | /* | |
4006 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
4007 | * all higher bits unset. | |
4008 | */ | |
4009 | static void | |
4010 | normalize_address_expr (expressionS *ex) | |
4011 | { | |
4012 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
4013 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
4014 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
4015 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4016 | - 0x80000000); | |
4017 | } | |
4018 | ||
438c16b8 TS |
4019 | /* |
4020 | * Generate a "jalr" instruction with a relocation hint to the called | |
4021 | * function. This occurs in NewABI PIC code. | |
4022 | */ | |
4023 | static void | |
67c0d1eb | 4024 | macro_build_jalr (expressionS *ep) |
438c16b8 | 4025 | { |
685736be | 4026 | char *f = NULL; |
b34976b6 | 4027 | |
1180b5a4 | 4028 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4029 | { |
cc3d92a5 | 4030 | frag_grow (8); |
f21f8242 AO |
4031 | f = frag_more (0); |
4032 | } | |
67c0d1eb | 4033 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4034 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4035 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4036 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4037 | } |
4038 | ||
252b5132 RH |
4039 | /* |
4040 | * Generate a "lui" instruction. | |
4041 | */ | |
4042 | static void | |
67c0d1eb | 4043 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4044 | { |
4045 | expressionS high_expr; | |
1e915849 | 4046 | const struct mips_opcode *mo; |
252b5132 | 4047 | struct mips_cl_insn insn; |
f6688943 TS |
4048 | bfd_reloc_code_real_type r[3] |
4049 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4050 | const char *name = "lui"; |
4051 | const char *fmt = "t,u"; | |
252b5132 | 4052 | |
9c2799c2 | 4053 | gas_assert (! mips_opts.mips16); |
252b5132 | 4054 | |
4d7206a2 | 4055 | high_expr = *ep; |
252b5132 RH |
4056 | |
4057 | if (high_expr.X_op == O_constant) | |
4058 | { | |
54f4ddb3 | 4059 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4060 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4061 | >> 16) & 0xffff; | |
f6688943 | 4062 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4063 | } |
78e1bb40 | 4064 | else |
252b5132 | 4065 | { |
9c2799c2 | 4066 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4067 | /* _gp_disp is a special case, used from s_cpload. |
4068 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4069 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4070 | || (! HAVE_NEWABI |
aa6975fb ILT |
4071 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4072 | || (! mips_in_shared | |
bbe506e8 TS |
4073 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4074 | "__gnu_local_gp") == 0)); | |
f6688943 | 4075 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4076 | } |
4077 | ||
1e915849 | 4078 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4079 | gas_assert (strcmp (name, mo->name) == 0); |
4080 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4081 | create_insn (&insn, mo); |
252b5132 | 4082 | |
bf12938e RS |
4083 | insn.insn_opcode = insn.insn_mo->match; |
4084 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4085 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4086 | { |
4087 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4088 | append_insn (&insn, NULL, r); |
252b5132 RH |
4089 | } |
4090 | else | |
4d7206a2 | 4091 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4092 | } |
4093 | ||
885add95 CD |
4094 | /* Generate a sequence of instructions to do a load or store from a constant |
4095 | offset off of a base register (breg) into/from a target register (treg), | |
4096 | using AT if necessary. */ | |
4097 | static void | |
67c0d1eb RS |
4098 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4099 | int treg, int breg, int dbl) | |
885add95 | 4100 | { |
9c2799c2 | 4101 | gas_assert (ep->X_op == O_constant); |
885add95 | 4102 | |
256ab948 | 4103 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4104 | if (!dbl) |
4105 | normalize_constant_expr (ep); | |
256ab948 | 4106 | |
67c1ffbe | 4107 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4108 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4109 | as_warn (_("operand overflow")); |
4110 | ||
4111 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4112 | { | |
4113 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4114 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4115 | } |
4116 | else | |
4117 | { | |
4118 | /* 32-bit offset, need multiple instructions and AT, like: | |
4119 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4120 | addu $tempreg,$tempreg,$breg | |
4121 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4122 | to handle the complete offset. */ | |
67c0d1eb RS |
4123 | macro_build_lui (ep, AT); |
4124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4125 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4126 | |
741fe287 | 4127 | if (!mips_opts.at) |
8fc2e39e | 4128 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4129 | } |
4130 | } | |
4131 | ||
252b5132 RH |
4132 | /* set_at() |
4133 | * Generates code to set the $at register to true (one) | |
4134 | * if reg is less than the immediate expression. | |
4135 | */ | |
4136 | static void | |
67c0d1eb | 4137 | set_at (int reg, int unsignedp) |
252b5132 RH |
4138 | { |
4139 | if (imm_expr.X_op == O_constant | |
4140 | && imm_expr.X_add_number >= -0x8000 | |
4141 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4142 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4143 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4144 | else |
4145 | { | |
67c0d1eb RS |
4146 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4147 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4148 | } |
4149 | } | |
4150 | ||
4151 | /* Warn if an expression is not a constant. */ | |
4152 | ||
4153 | static void | |
17a2f251 | 4154 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4155 | { |
4156 | if (ex->X_op == O_big) | |
4157 | as_bad (_("unsupported large constant")); | |
4158 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4159 | as_bad (_("Instruction %s requires absolute expression"), |
4160 | ip->insn_mo->name); | |
13757d0c | 4161 | |
9ee2a2d4 MR |
4162 | if (HAVE_32BIT_GPRS) |
4163 | normalize_constant_expr (ex); | |
252b5132 RH |
4164 | } |
4165 | ||
4166 | /* Count the leading zeroes by performing a binary chop. This is a | |
4167 | bulky bit of source, but performance is a LOT better for the | |
4168 | majority of values than a simple loop to count the bits: | |
4169 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4170 | if ((v) & (1 << (31 - lcnt))) | |
4171 | break; | |
4172 | However it is not code size friendly, and the gain will drop a bit | |
4173 | on certain cached systems. | |
4174 | */ | |
4175 | #define COUNT_TOP_ZEROES(v) \ | |
4176 | (((v) & ~0xffff) == 0 \ | |
4177 | ? ((v) & ~0xff) == 0 \ | |
4178 | ? ((v) & ~0xf) == 0 \ | |
4179 | ? ((v) & ~0x3) == 0 \ | |
4180 | ? ((v) & ~0x1) == 0 \ | |
4181 | ? !(v) \ | |
4182 | ? 32 \ | |
4183 | : 31 \ | |
4184 | : 30 \ | |
4185 | : ((v) & ~0x7) == 0 \ | |
4186 | ? 29 \ | |
4187 | : 28 \ | |
4188 | : ((v) & ~0x3f) == 0 \ | |
4189 | ? ((v) & ~0x1f) == 0 \ | |
4190 | ? 27 \ | |
4191 | : 26 \ | |
4192 | : ((v) & ~0x7f) == 0 \ | |
4193 | ? 25 \ | |
4194 | : 24 \ | |
4195 | : ((v) & ~0xfff) == 0 \ | |
4196 | ? ((v) & ~0x3ff) == 0 \ | |
4197 | ? ((v) & ~0x1ff) == 0 \ | |
4198 | ? 23 \ | |
4199 | : 22 \ | |
4200 | : ((v) & ~0x7ff) == 0 \ | |
4201 | ? 21 \ | |
4202 | : 20 \ | |
4203 | : ((v) & ~0x3fff) == 0 \ | |
4204 | ? ((v) & ~0x1fff) == 0 \ | |
4205 | ? 19 \ | |
4206 | : 18 \ | |
4207 | : ((v) & ~0x7fff) == 0 \ | |
4208 | ? 17 \ | |
4209 | : 16 \ | |
4210 | : ((v) & ~0xffffff) == 0 \ | |
4211 | ? ((v) & ~0xfffff) == 0 \ | |
4212 | ? ((v) & ~0x3ffff) == 0 \ | |
4213 | ? ((v) & ~0x1ffff) == 0 \ | |
4214 | ? 15 \ | |
4215 | : 14 \ | |
4216 | : ((v) & ~0x7ffff) == 0 \ | |
4217 | ? 13 \ | |
4218 | : 12 \ | |
4219 | : ((v) & ~0x3fffff) == 0 \ | |
4220 | ? ((v) & ~0x1fffff) == 0 \ | |
4221 | ? 11 \ | |
4222 | : 10 \ | |
4223 | : ((v) & ~0x7fffff) == 0 \ | |
4224 | ? 9 \ | |
4225 | : 8 \ | |
4226 | : ((v) & ~0xfffffff) == 0 \ | |
4227 | ? ((v) & ~0x3ffffff) == 0 \ | |
4228 | ? ((v) & ~0x1ffffff) == 0 \ | |
4229 | ? 7 \ | |
4230 | : 6 \ | |
4231 | : ((v) & ~0x7ffffff) == 0 \ | |
4232 | ? 5 \ | |
4233 | : 4 \ | |
4234 | : ((v) & ~0x3fffffff) == 0 \ | |
4235 | ? ((v) & ~0x1fffffff) == 0 \ | |
4236 | ? 3 \ | |
4237 | : 2 \ | |
4238 | : ((v) & ~0x7fffffff) == 0 \ | |
4239 | ? 1 \ | |
4240 | : 0) | |
4241 | ||
4242 | /* load_register() | |
67c1ffbe | 4243 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4244 | * an absolute expression value into a register. |
4245 | */ | |
4246 | static void | |
67c0d1eb | 4247 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4248 | { |
4249 | int freg; | |
4250 | expressionS hi32, lo32; | |
4251 | ||
4252 | if (ep->X_op != O_big) | |
4253 | { | |
9c2799c2 | 4254 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4255 | |
4256 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4257 | if (!dbl) |
4258 | normalize_constant_expr (ep); | |
256ab948 TS |
4259 | |
4260 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4261 | { |
4262 | /* We can handle 16 bit signed values with an addiu to | |
4263 | $zero. No need to ever use daddiu here, since $zero and | |
4264 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4265 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4266 | return; |
4267 | } | |
4268 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4269 | { | |
4270 | /* We can handle 16 bit unsigned values with an ori to | |
4271 | $zero. */ | |
67c0d1eb | 4272 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4273 | return; |
4274 | } | |
256ab948 | 4275 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4276 | { |
4277 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4278 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4279 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4280 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4281 | return; |
4282 | } | |
4283 | } | |
4284 | ||
4285 | /* The value is larger than 32 bits. */ | |
4286 | ||
2051e8c4 | 4287 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4288 | { |
55e08f71 NC |
4289 | char value[32]; |
4290 | ||
4291 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4292 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4293 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4294 | return; |
4295 | } | |
4296 | ||
4297 | if (ep->X_op != O_big) | |
4298 | { | |
4299 | hi32 = *ep; | |
4300 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4301 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4302 | hi32.X_add_number &= 0xffffffff; | |
4303 | lo32 = *ep; | |
4304 | lo32.X_add_number &= 0xffffffff; | |
4305 | } | |
4306 | else | |
4307 | { | |
9c2799c2 | 4308 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4309 | if (ep->X_add_number == 3) |
4310 | generic_bignum[3] = 0; | |
4311 | else if (ep->X_add_number > 4) | |
4312 | as_bad (_("Number larger than 64 bits")); | |
4313 | lo32.X_op = O_constant; | |
4314 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4315 | hi32.X_op = O_constant; | |
4316 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4317 | } | |
4318 | ||
4319 | if (hi32.X_add_number == 0) | |
4320 | freg = 0; | |
4321 | else | |
4322 | { | |
4323 | int shift, bit; | |
4324 | unsigned long hi, lo; | |
4325 | ||
956cd1d6 | 4326 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4327 | { |
4328 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4329 | { | |
67c0d1eb | 4330 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4331 | return; |
4332 | } | |
4333 | if (lo32.X_add_number & 0x80000000) | |
4334 | { | |
67c0d1eb | 4335 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4336 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4337 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4338 | return; |
4339 | } | |
4340 | } | |
252b5132 RH |
4341 | |
4342 | /* Check for 16bit shifted constant. We know that hi32 is | |
4343 | non-zero, so start the mask on the first bit of the hi32 | |
4344 | value. */ | |
4345 | shift = 17; | |
4346 | do | |
beae10d5 KH |
4347 | { |
4348 | unsigned long himask, lomask; | |
4349 | ||
4350 | if (shift < 32) | |
4351 | { | |
4352 | himask = 0xffff >> (32 - shift); | |
4353 | lomask = (0xffff << shift) & 0xffffffff; | |
4354 | } | |
4355 | else | |
4356 | { | |
4357 | himask = 0xffff << (shift - 32); | |
4358 | lomask = 0; | |
4359 | } | |
4360 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4361 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4362 | { | |
4363 | expressionS tmp; | |
4364 | ||
4365 | tmp.X_op = O_constant; | |
4366 | if (shift < 32) | |
4367 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4368 | | (lo32.X_add_number >> shift)); | |
4369 | else | |
4370 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4371 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4372 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4373 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4374 | return; |
4375 | } | |
f9419b05 | 4376 | ++shift; |
beae10d5 KH |
4377 | } |
4378 | while (shift <= (64 - 16)); | |
252b5132 RH |
4379 | |
4380 | /* Find the bit number of the lowest one bit, and store the | |
4381 | shifted value in hi/lo. */ | |
4382 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4383 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4384 | if (lo != 0) | |
4385 | { | |
4386 | bit = 0; | |
4387 | while ((lo & 1) == 0) | |
4388 | { | |
4389 | lo >>= 1; | |
4390 | ++bit; | |
4391 | } | |
4392 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4393 | hi >>= bit; | |
4394 | } | |
4395 | else | |
4396 | { | |
4397 | bit = 32; | |
4398 | while ((hi & 1) == 0) | |
4399 | { | |
4400 | hi >>= 1; | |
4401 | ++bit; | |
4402 | } | |
4403 | lo = hi; | |
4404 | hi = 0; | |
4405 | } | |
4406 | ||
4407 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4408 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4409 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4410 | { |
4411 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4412 | if (shift != 0) |
beae10d5 | 4413 | { |
252b5132 RH |
4414 | expressionS tmp; |
4415 | ||
4416 | /* This instruction will set the register to be all | |
4417 | ones. */ | |
beae10d5 KH |
4418 | tmp.X_op = O_constant; |
4419 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4420 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4421 | if (bit != 0) |
4422 | { | |
4423 | bit += shift; | |
67c0d1eb RS |
4424 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4425 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4426 | } |
67c0d1eb RS |
4427 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4428 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4429 | return; |
4430 | } | |
4431 | } | |
252b5132 RH |
4432 | |
4433 | /* Sign extend hi32 before calling load_register, because we can | |
4434 | generally get better code when we load a sign extended value. */ | |
4435 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4436 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4437 | load_register (reg, &hi32, 0); |
252b5132 RH |
4438 | freg = reg; |
4439 | } | |
4440 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4441 | { | |
4442 | if (freg != 0) | |
4443 | { | |
67c0d1eb | 4444 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4445 | freg = reg; |
4446 | } | |
4447 | } | |
4448 | else | |
4449 | { | |
4450 | expressionS mid16; | |
4451 | ||
956cd1d6 | 4452 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4453 | { |
67c0d1eb RS |
4454 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4455 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4456 | return; |
4457 | } | |
252b5132 RH |
4458 | |
4459 | if (freg != 0) | |
4460 | { | |
67c0d1eb | 4461 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4462 | freg = reg; |
4463 | } | |
4464 | mid16 = lo32; | |
4465 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4466 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4467 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4468 | freg = reg; |
4469 | } | |
4470 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4471 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4472 | } |
4473 | ||
269137b2 TS |
4474 | static inline void |
4475 | load_delay_nop (void) | |
4476 | { | |
4477 | if (!gpr_interlocks) | |
4478 | macro_build (NULL, "nop", ""); | |
4479 | } | |
4480 | ||
252b5132 RH |
4481 | /* Load an address into a register. */ |
4482 | ||
4483 | static void | |
67c0d1eb | 4484 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4485 | { |
252b5132 RH |
4486 | if (ep->X_op != O_constant |
4487 | && ep->X_op != O_symbol) | |
4488 | { | |
4489 | as_bad (_("expression too complex")); | |
4490 | ep->X_op = O_constant; | |
4491 | } | |
4492 | ||
4493 | if (ep->X_op == O_constant) | |
4494 | { | |
67c0d1eb | 4495 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4496 | return; |
4497 | } | |
4498 | ||
4499 | if (mips_pic == NO_PIC) | |
4500 | { | |
4501 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4502 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4503 | Otherwise we want |
4504 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4505 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4506 | If we have an addend, we always use the latter form. |
76b3015f | 4507 | |
d6bc6245 TS |
4508 | With 64bit address space and a usable $at we want |
4509 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4510 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4511 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4512 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4513 | dsll32 $reg,0 | |
3a482fd5 | 4514 | daddu $reg,$reg,$at |
76b3015f | 4515 | |
c03099e6 | 4516 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4517 | on superscalar processors. |
4518 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4519 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4520 | dsll $reg,16 | |
4521 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4522 | dsll $reg,16 | |
4523 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4524 | |
4525 | For GP relative symbols in 64bit address space we can use | |
4526 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4527 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4528 | { |
6caf9ef4 TS |
4529 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4530 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4531 | { | |
4532 | relax_start (ep->X_add_symbol); | |
4533 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4534 | mips_gp_register, BFD_RELOC_GPREL16); | |
4535 | relax_switch (); | |
4536 | } | |
d6bc6245 | 4537 | |
741fe287 | 4538 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4539 | { |
67c0d1eb RS |
4540 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4541 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4542 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4543 | BFD_RELOC_MIPS_HIGHER); | |
4544 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4545 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4546 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4547 | *used_at = 1; |
4548 | } | |
4549 | else | |
4550 | { | |
67c0d1eb RS |
4551 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4552 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4553 | BFD_RELOC_MIPS_HIGHER); | |
4554 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4555 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4556 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4557 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4558 | } |
6caf9ef4 TS |
4559 | |
4560 | if (mips_relax.sequence) | |
4561 | relax_end (); | |
d6bc6245 | 4562 | } |
252b5132 RH |
4563 | else |
4564 | { | |
d6bc6245 | 4565 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4566 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4567 | { |
4d7206a2 | 4568 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4569 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4570 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4571 | relax_switch (); |
d6bc6245 | 4572 | } |
67c0d1eb RS |
4573 | macro_build_lui (ep, reg); |
4574 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4575 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4576 | if (mips_relax.sequence) |
4577 | relax_end (); | |
d6bc6245 | 4578 | } |
252b5132 | 4579 | } |
0a44bf69 | 4580 | else if (!mips_big_got) |
252b5132 RH |
4581 | { |
4582 | expressionS ex; | |
4583 | ||
4584 | /* If this is a reference to an external symbol, we want | |
4585 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4586 | Otherwise we want | |
4587 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4588 | nop | |
4589 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4590 | If there is a constant, it must be added in after. |
4591 | ||
ed6fb7bd | 4592 | If we have NewABI, we want |
f5040a92 AO |
4593 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4594 | unless we're referencing a global symbol with a non-zero | |
4595 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4596 | if (HAVE_NEWABI) |
4597 | { | |
f5040a92 AO |
4598 | if (ep->X_add_number) |
4599 | { | |
4d7206a2 | 4600 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4601 | ep->X_add_number = 0; |
4d7206a2 | 4602 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4603 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4604 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4605 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4606 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4607 | ex.X_op = O_constant; | |
67c0d1eb | 4608 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4609 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4610 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4611 | relax_switch (); |
f5040a92 | 4612 | } |
67c0d1eb | 4613 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4614 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4615 | if (mips_relax.sequence) |
4616 | relax_end (); | |
ed6fb7bd SC |
4617 | } |
4618 | else | |
4619 | { | |
f5040a92 AO |
4620 | ex.X_add_number = ep->X_add_number; |
4621 | ep->X_add_number = 0; | |
67c0d1eb RS |
4622 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4623 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4624 | load_delay_nop (); |
4d7206a2 RS |
4625 | relax_start (ep->X_add_symbol); |
4626 | relax_switch (); | |
67c0d1eb | 4627 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4628 | BFD_RELOC_LO16); |
4d7206a2 | 4629 | relax_end (); |
ed6fb7bd | 4630 | |
f5040a92 AO |
4631 | if (ex.X_add_number != 0) |
4632 | { | |
4633 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4634 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4635 | ex.X_op = O_constant; | |
67c0d1eb | 4636 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4637 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4638 | } |
252b5132 RH |
4639 | } |
4640 | } | |
0a44bf69 | 4641 | else if (mips_big_got) |
252b5132 RH |
4642 | { |
4643 | expressionS ex; | |
252b5132 RH |
4644 | |
4645 | /* This is the large GOT case. If this is a reference to an | |
4646 | external symbol, we want | |
4647 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4648 | addu $reg,$reg,$gp | |
4649 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4650 | |
4651 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4652 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4653 | nop | |
4654 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4655 | If there is a constant, it must be added in after. |
f5040a92 AO |
4656 | |
4657 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4658 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4659 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4660 | */ |
438c16b8 TS |
4661 | if (HAVE_NEWABI) |
4662 | { | |
4d7206a2 | 4663 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4664 | ep->X_add_number = 0; |
4d7206a2 | 4665 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4666 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4667 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4668 | reg, reg, mips_gp_register); | |
4669 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4670 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4671 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4672 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4673 | else if (ex.X_add_number) | |
4674 | { | |
4675 | ex.X_op = O_constant; | |
67c0d1eb RS |
4676 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4677 | BFD_RELOC_LO16); | |
f5040a92 AO |
4678 | } |
4679 | ||
4680 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4681 | relax_switch (); |
67c0d1eb | 4682 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4683 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4684 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4685 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4686 | relax_end (); |
438c16b8 | 4687 | } |
252b5132 | 4688 | else |
438c16b8 | 4689 | { |
f5040a92 AO |
4690 | ex.X_add_number = ep->X_add_number; |
4691 | ep->X_add_number = 0; | |
4d7206a2 | 4692 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4693 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4694 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4695 | reg, reg, mips_gp_register); | |
4696 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4697 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4698 | relax_switch (); |
4699 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4700 | { |
4701 | /* We need a nop before loading from $gp. This special | |
4702 | check is required because the lui which starts the main | |
4703 | instruction stream does not refer to $gp, and so will not | |
4704 | insert the nop which may be required. */ | |
67c0d1eb | 4705 | macro_build (NULL, "nop", ""); |
438c16b8 | 4706 | } |
67c0d1eb | 4707 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4708 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4709 | load_delay_nop (); |
67c0d1eb | 4710 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4711 | BFD_RELOC_LO16); |
4d7206a2 | 4712 | relax_end (); |
438c16b8 | 4713 | |
f5040a92 AO |
4714 | if (ex.X_add_number != 0) |
4715 | { | |
4716 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4717 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4718 | ex.X_op = O_constant; | |
67c0d1eb RS |
4719 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4720 | BFD_RELOC_LO16); | |
f5040a92 | 4721 | } |
252b5132 RH |
4722 | } |
4723 | } | |
252b5132 RH |
4724 | else |
4725 | abort (); | |
8fc2e39e | 4726 | |
741fe287 | 4727 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4728 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4729 | } |
4730 | ||
ea1fb5dc RS |
4731 | /* Move the contents of register SOURCE into register DEST. */ |
4732 | ||
4733 | static void | |
67c0d1eb | 4734 | move_register (int dest, int source) |
ea1fb5dc | 4735 | { |
67c0d1eb RS |
4736 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4737 | dest, source, 0); | |
ea1fb5dc RS |
4738 | } |
4739 | ||
4d7206a2 | 4740 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4741 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4742 | The two alternatives are: | |
4d7206a2 RS |
4743 | |
4744 | Global symbol Local sybmol | |
4745 | ------------- ------------ | |
4746 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4747 | ... ... | |
4748 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4749 | ||
4750 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4751 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4752 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4753 | |
4754 | static void | |
67c0d1eb | 4755 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4756 | { |
4757 | expressionS global; | |
4758 | ||
4759 | global = *local; | |
4760 | global.X_add_number = 0; | |
4761 | ||
4762 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4763 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4764 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4765 | relax_switch (); |
67c0d1eb RS |
4766 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4767 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4768 | relax_end (); |
4769 | } | |
4770 | ||
4771 | static void | |
67c0d1eb | 4772 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4773 | { |
4774 | expressionS global; | |
4775 | ||
4776 | global.X_op = O_constant; | |
4777 | global.X_op_symbol = NULL; | |
4778 | global.X_add_symbol = NULL; | |
4779 | global.X_add_number = local->X_add_number; | |
4780 | ||
4781 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4782 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4783 | dest, dest, BFD_RELOC_LO16); |
4784 | relax_switch (); | |
67c0d1eb | 4785 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4786 | relax_end (); |
4787 | } | |
4788 | ||
f6a22291 MR |
4789 | static void |
4790 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4791 | { | |
4792 | expressionS global; | |
4793 | int hold_mips_optimize; | |
4794 | ||
4795 | global.X_op = O_constant; | |
4796 | global.X_op_symbol = NULL; | |
4797 | global.X_add_symbol = NULL; | |
4798 | global.X_add_number = local->X_add_number; | |
4799 | ||
4800 | relax_start (local->X_add_symbol); | |
4801 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4802 | relax_switch (); | |
4803 | /* Set mips_optimize around the lui instruction to avoid | |
4804 | inserting an unnecessary nop after the lw. */ | |
4805 | hold_mips_optimize = mips_optimize; | |
4806 | mips_optimize = 2; | |
4807 | macro_build_lui (&global, tmp); | |
4808 | mips_optimize = hold_mips_optimize; | |
4809 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4810 | relax_end (); | |
4811 | ||
4812 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4813 | } | |
4814 | ||
252b5132 RH |
4815 | /* |
4816 | * Build macros | |
4817 | * This routine implements the seemingly endless macro or synthesized | |
4818 | * instructions and addressing modes in the mips assembly language. Many | |
4819 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4820 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4821 | * this verbose method. Others are not simple macros but are more like |
4822 | * optimizing code generation. | |
4823 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4824 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4825 | * The ensuing load upper instructions are ommited. This implies some kind |
4826 | * of global optimization. We currently only optimize within a single macro. | |
4827 | * For many of the load and store macros if the address is specified as a | |
4828 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4829 | * first load register 'at' with zero and use it as the base register. The | |
4830 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4831 | * we're missing. | |
4832 | */ | |
4833 | static void | |
17a2f251 | 4834 | macro (struct mips_cl_insn *ip) |
252b5132 | 4835 | { |
741fe287 MR |
4836 | unsigned int treg, sreg, dreg, breg; |
4837 | unsigned int tempreg; | |
252b5132 | 4838 | int mask; |
43841e91 | 4839 | int used_at = 0; |
252b5132 RH |
4840 | expressionS expr1; |
4841 | const char *s; | |
4842 | const char *s2; | |
4843 | const char *fmt; | |
4844 | int likely = 0; | |
4845 | int dbl = 0; | |
4846 | int coproc = 0; | |
4847 | int lr = 0; | |
4848 | int imm = 0; | |
1abe91b1 | 4849 | int call = 0; |
252b5132 | 4850 | int off; |
67c0d1eb | 4851 | offsetT maxnum; |
252b5132 | 4852 | bfd_reloc_code_real_type r; |
252b5132 RH |
4853 | int hold_mips_optimize; |
4854 | ||
9c2799c2 | 4855 | gas_assert (! mips_opts.mips16); |
252b5132 | 4856 | |
bbea7ebc MR |
4857 | treg = EXTRACT_OPERAND (RT, *ip); |
4858 | dreg = EXTRACT_OPERAND (RD, *ip); | |
4859 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
4860 | mask = ip->insn_mo->mask; |
4861 | ||
4862 | expr1.X_op = O_constant; | |
4863 | expr1.X_op_symbol = NULL; | |
4864 | expr1.X_add_symbol = NULL; | |
4865 | expr1.X_add_number = 1; | |
4866 | ||
4867 | switch (mask) | |
4868 | { | |
4869 | case M_DABS: | |
4870 | dbl = 1; | |
4871 | case M_ABS: | |
4872 | /* bgez $a0,.+12 | |
4873 | move v0,$a0 | |
4874 | sub v0,$zero,$a0 | |
4875 | */ | |
4876 | ||
7d10b47d | 4877 | start_noreorder (); |
252b5132 RH |
4878 | |
4879 | expr1.X_add_number = 8; | |
67c0d1eb | 4880 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4881 | if (dreg == sreg) |
a605d2b3 | 4882 | macro_build (NULL, "nop", ""); |
252b5132 | 4883 | else |
67c0d1eb RS |
4884 | move_register (dreg, sreg); |
4885 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4886 | |
7d10b47d | 4887 | end_noreorder (); |
8fc2e39e | 4888 | break; |
252b5132 RH |
4889 | |
4890 | case M_ADD_I: | |
4891 | s = "addi"; | |
4892 | s2 = "add"; | |
4893 | goto do_addi; | |
4894 | case M_ADDU_I: | |
4895 | s = "addiu"; | |
4896 | s2 = "addu"; | |
4897 | goto do_addi; | |
4898 | case M_DADD_I: | |
4899 | dbl = 1; | |
4900 | s = "daddi"; | |
4901 | s2 = "dadd"; | |
4902 | goto do_addi; | |
4903 | case M_DADDU_I: | |
4904 | dbl = 1; | |
4905 | s = "daddiu"; | |
4906 | s2 = "daddu"; | |
4907 | do_addi: | |
4908 | if (imm_expr.X_op == O_constant | |
4909 | && imm_expr.X_add_number >= -0x8000 | |
4910 | && imm_expr.X_add_number < 0x8000) | |
4911 | { | |
67c0d1eb | 4912 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4913 | break; |
252b5132 | 4914 | } |
8fc2e39e | 4915 | used_at = 1; |
67c0d1eb RS |
4916 | load_register (AT, &imm_expr, dbl); |
4917 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4918 | break; |
4919 | ||
4920 | case M_AND_I: | |
4921 | s = "andi"; | |
4922 | s2 = "and"; | |
4923 | goto do_bit; | |
4924 | case M_OR_I: | |
4925 | s = "ori"; | |
4926 | s2 = "or"; | |
4927 | goto do_bit; | |
4928 | case M_NOR_I: | |
4929 | s = ""; | |
4930 | s2 = "nor"; | |
4931 | goto do_bit; | |
4932 | case M_XOR_I: | |
4933 | s = "xori"; | |
4934 | s2 = "xor"; | |
4935 | do_bit: | |
4936 | if (imm_expr.X_op == O_constant | |
4937 | && imm_expr.X_add_number >= 0 | |
4938 | && imm_expr.X_add_number < 0x10000) | |
4939 | { | |
4940 | if (mask != M_NOR_I) | |
67c0d1eb | 4941 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4942 | else |
4943 | { | |
67c0d1eb RS |
4944 | macro_build (&imm_expr, "ori", "t,r,i", |
4945 | treg, sreg, BFD_RELOC_LO16); | |
4946 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4947 | } |
8fc2e39e | 4948 | break; |
252b5132 RH |
4949 | } |
4950 | ||
8fc2e39e | 4951 | used_at = 1; |
67c0d1eb RS |
4952 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4953 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4954 | break; |
4955 | ||
8b082fb1 TS |
4956 | case M_BALIGN: |
4957 | switch (imm_expr.X_add_number) | |
4958 | { | |
4959 | case 0: | |
4960 | macro_build (NULL, "nop", ""); | |
4961 | break; | |
4962 | case 2: | |
4963 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4964 | break; | |
4965 | default: | |
4966 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 4967 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
4968 | break; |
4969 | } | |
4970 | break; | |
4971 | ||
252b5132 RH |
4972 | case M_BEQ_I: |
4973 | s = "beq"; | |
4974 | goto beq_i; | |
4975 | case M_BEQL_I: | |
4976 | s = "beql"; | |
4977 | likely = 1; | |
4978 | goto beq_i; | |
4979 | case M_BNE_I: | |
4980 | s = "bne"; | |
4981 | goto beq_i; | |
4982 | case M_BNEL_I: | |
4983 | s = "bnel"; | |
4984 | likely = 1; | |
4985 | beq_i: | |
4986 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4987 | { | |
c80c840e | 4988 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 4989 | break; |
252b5132 | 4990 | } |
8fc2e39e | 4991 | used_at = 1; |
67c0d1eb RS |
4992 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4993 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4994 | break; |
4995 | ||
4996 | case M_BGEL: | |
4997 | likely = 1; | |
4998 | case M_BGE: | |
4999 | if (treg == 0) | |
5000 | { | |
67c0d1eb | 5001 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5002 | break; |
252b5132 RH |
5003 | } |
5004 | if (sreg == 0) | |
5005 | { | |
67c0d1eb | 5006 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 5007 | break; |
252b5132 | 5008 | } |
8fc2e39e | 5009 | used_at = 1; |
67c0d1eb | 5010 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5011 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5012 | break; |
5013 | ||
5014 | case M_BGTL_I: | |
5015 | likely = 1; | |
5016 | case M_BGT_I: | |
90ecf173 | 5017 | /* Check for > max integer. */ |
252b5132 | 5018 | maxnum = 0x7fffffff; |
ca4e0257 | 5019 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5020 | { |
5021 | maxnum <<= 16; | |
5022 | maxnum |= 0xffff; | |
5023 | maxnum <<= 16; | |
5024 | maxnum |= 0xffff; | |
5025 | } | |
5026 | if (imm_expr.X_op == O_constant | |
5027 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5028 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5029 | { |
5030 | do_false: | |
90ecf173 | 5031 | /* Result is always false. */ |
252b5132 | 5032 | if (! likely) |
a605d2b3 | 5033 | macro_build (NULL, "nop", ""); |
252b5132 | 5034 | else |
c80c840e | 5035 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5036 | break; |
252b5132 RH |
5037 | } |
5038 | if (imm_expr.X_op != O_constant) | |
5039 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5040 | ++imm_expr.X_add_number; |
252b5132 RH |
5041 | /* FALLTHROUGH */ |
5042 | case M_BGE_I: | |
5043 | case M_BGEL_I: | |
5044 | if (mask == M_BGEL_I) | |
5045 | likely = 1; | |
5046 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5047 | { | |
67c0d1eb | 5048 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5049 | break; |
252b5132 RH |
5050 | } |
5051 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5052 | { | |
67c0d1eb | 5053 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5054 | break; |
252b5132 RH |
5055 | } |
5056 | maxnum = 0x7fffffff; | |
ca4e0257 | 5057 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5058 | { |
5059 | maxnum <<= 16; | |
5060 | maxnum |= 0xffff; | |
5061 | maxnum <<= 16; | |
5062 | maxnum |= 0xffff; | |
5063 | } | |
5064 | maxnum = - maxnum - 1; | |
5065 | if (imm_expr.X_op == O_constant | |
5066 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5067 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5068 | { |
5069 | do_true: | |
5070 | /* result is always true */ | |
5071 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5072 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5073 | break; |
252b5132 | 5074 | } |
8fc2e39e | 5075 | used_at = 1; |
67c0d1eb | 5076 | set_at (sreg, 0); |
c80c840e | 5077 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5078 | break; |
5079 | ||
5080 | case M_BGEUL: | |
5081 | likely = 1; | |
5082 | case M_BGEU: | |
5083 | if (treg == 0) | |
5084 | goto do_true; | |
5085 | if (sreg == 0) | |
5086 | { | |
67c0d1eb | 5087 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5088 | "s,t,p", ZERO, treg); |
8fc2e39e | 5089 | break; |
252b5132 | 5090 | } |
8fc2e39e | 5091 | used_at = 1; |
67c0d1eb | 5092 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5093 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5094 | break; |
5095 | ||
5096 | case M_BGTUL_I: | |
5097 | likely = 1; | |
5098 | case M_BGTU_I: | |
5099 | if (sreg == 0 | |
ca4e0257 | 5100 | || (HAVE_32BIT_GPRS |
252b5132 | 5101 | && imm_expr.X_op == O_constant |
f01dc953 | 5102 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5103 | goto do_false; |
5104 | if (imm_expr.X_op != O_constant) | |
5105 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5106 | ++imm_expr.X_add_number; |
252b5132 RH |
5107 | /* FALLTHROUGH */ |
5108 | case M_BGEU_I: | |
5109 | case M_BGEUL_I: | |
5110 | if (mask == M_BGEUL_I) | |
5111 | likely = 1; | |
5112 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5113 | goto do_true; | |
5114 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5115 | { | |
67c0d1eb | 5116 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5117 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5118 | break; |
252b5132 | 5119 | } |
8fc2e39e | 5120 | used_at = 1; |
67c0d1eb | 5121 | set_at (sreg, 1); |
c80c840e | 5122 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5123 | break; |
5124 | ||
5125 | case M_BGTL: | |
5126 | likely = 1; | |
5127 | case M_BGT: | |
5128 | if (treg == 0) | |
5129 | { | |
67c0d1eb | 5130 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5131 | break; |
252b5132 RH |
5132 | } |
5133 | if (sreg == 0) | |
5134 | { | |
67c0d1eb | 5135 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5136 | break; |
252b5132 | 5137 | } |
8fc2e39e | 5138 | used_at = 1; |
67c0d1eb | 5139 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5140 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5141 | break; |
5142 | ||
5143 | case M_BGTUL: | |
5144 | likely = 1; | |
5145 | case M_BGTU: | |
5146 | if (treg == 0) | |
5147 | { | |
67c0d1eb | 5148 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5149 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5150 | break; |
252b5132 RH |
5151 | } |
5152 | if (sreg == 0) | |
5153 | goto do_false; | |
8fc2e39e | 5154 | used_at = 1; |
67c0d1eb | 5155 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5156 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5157 | break; |
5158 | ||
5159 | case M_BLEL: | |
5160 | likely = 1; | |
5161 | case M_BLE: | |
5162 | if (treg == 0) | |
5163 | { | |
67c0d1eb | 5164 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5165 | break; |
252b5132 RH |
5166 | } |
5167 | if (sreg == 0) | |
5168 | { | |
67c0d1eb | 5169 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5170 | break; |
252b5132 | 5171 | } |
8fc2e39e | 5172 | used_at = 1; |
67c0d1eb | 5173 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5174 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5175 | break; |
5176 | ||
5177 | case M_BLEL_I: | |
5178 | likely = 1; | |
5179 | case M_BLE_I: | |
5180 | maxnum = 0x7fffffff; | |
ca4e0257 | 5181 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5182 | { |
5183 | maxnum <<= 16; | |
5184 | maxnum |= 0xffff; | |
5185 | maxnum <<= 16; | |
5186 | maxnum |= 0xffff; | |
5187 | } | |
5188 | if (imm_expr.X_op == O_constant | |
5189 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5190 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5191 | goto do_true; |
5192 | if (imm_expr.X_op != O_constant) | |
5193 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5194 | ++imm_expr.X_add_number; |
252b5132 RH |
5195 | /* FALLTHROUGH */ |
5196 | case M_BLT_I: | |
5197 | case M_BLTL_I: | |
5198 | if (mask == M_BLTL_I) | |
5199 | likely = 1; | |
5200 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5201 | { | |
67c0d1eb | 5202 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5203 | break; |
252b5132 RH |
5204 | } |
5205 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5206 | { | |
67c0d1eb | 5207 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5208 | break; |
252b5132 | 5209 | } |
8fc2e39e | 5210 | used_at = 1; |
67c0d1eb | 5211 | set_at (sreg, 0); |
c80c840e | 5212 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5213 | break; |
5214 | ||
5215 | case M_BLEUL: | |
5216 | likely = 1; | |
5217 | case M_BLEU: | |
5218 | if (treg == 0) | |
5219 | { | |
67c0d1eb | 5220 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5221 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5222 | break; |
252b5132 RH |
5223 | } |
5224 | if (sreg == 0) | |
5225 | goto do_true; | |
8fc2e39e | 5226 | used_at = 1; |
67c0d1eb | 5227 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5228 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5229 | break; |
5230 | ||
5231 | case M_BLEUL_I: | |
5232 | likely = 1; | |
5233 | case M_BLEU_I: | |
5234 | if (sreg == 0 | |
ca4e0257 | 5235 | || (HAVE_32BIT_GPRS |
252b5132 | 5236 | && imm_expr.X_op == O_constant |
f01dc953 | 5237 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5238 | goto do_true; |
5239 | if (imm_expr.X_op != O_constant) | |
5240 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5241 | ++imm_expr.X_add_number; |
252b5132 RH |
5242 | /* FALLTHROUGH */ |
5243 | case M_BLTU_I: | |
5244 | case M_BLTUL_I: | |
5245 | if (mask == M_BLTUL_I) | |
5246 | likely = 1; | |
5247 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5248 | goto do_false; | |
5249 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5250 | { | |
67c0d1eb | 5251 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5252 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5253 | break; |
252b5132 | 5254 | } |
8fc2e39e | 5255 | used_at = 1; |
67c0d1eb | 5256 | set_at (sreg, 1); |
c80c840e | 5257 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5258 | break; |
5259 | ||
5260 | case M_BLTL: | |
5261 | likely = 1; | |
5262 | case M_BLT: | |
5263 | if (treg == 0) | |
5264 | { | |
67c0d1eb | 5265 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5266 | break; |
252b5132 RH |
5267 | } |
5268 | if (sreg == 0) | |
5269 | { | |
67c0d1eb | 5270 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5271 | break; |
252b5132 | 5272 | } |
8fc2e39e | 5273 | used_at = 1; |
67c0d1eb | 5274 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5275 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5276 | break; |
5277 | ||
5278 | case M_BLTUL: | |
5279 | likely = 1; | |
5280 | case M_BLTU: | |
5281 | if (treg == 0) | |
5282 | goto do_false; | |
5283 | if (sreg == 0) | |
5284 | { | |
67c0d1eb | 5285 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5286 | "s,t,p", ZERO, treg); |
8fc2e39e | 5287 | break; |
252b5132 | 5288 | } |
8fc2e39e | 5289 | used_at = 1; |
67c0d1eb | 5290 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5291 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5292 | break; |
5293 | ||
5f74bc13 CD |
5294 | case M_DEXT: |
5295 | { | |
d5818fca MR |
5296 | /* Use unsigned arithmetic. */ |
5297 | addressT pos; | |
5298 | addressT size; | |
5f74bc13 | 5299 | |
90ecf173 | 5300 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5301 | { |
5302 | as_bad (_("Unsupported large constant")); | |
5303 | pos = size = 1; | |
5304 | } | |
5305 | else | |
5306 | { | |
d5818fca MR |
5307 | pos = imm_expr.X_add_number; |
5308 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5309 | } |
5310 | ||
5311 | if (pos > 63) | |
5312 | { | |
d5818fca | 5313 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5314 | pos = 1; |
5315 | } | |
90ecf173 | 5316 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5317 | { |
5318 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5319 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5320 | size = 1; |
5321 | } | |
5322 | ||
5323 | if (size <= 32 && pos < 32) | |
5324 | { | |
5325 | s = "dext"; | |
5326 | fmt = "t,r,+A,+C"; | |
5327 | } | |
5328 | else if (size <= 32) | |
5329 | { | |
5330 | s = "dextu"; | |
5331 | fmt = "t,r,+E,+H"; | |
5332 | } | |
5333 | else | |
5334 | { | |
5335 | s = "dextm"; | |
5336 | fmt = "t,r,+A,+G"; | |
5337 | } | |
d5818fca MR |
5338 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5339 | (int) (size - 1)); | |
5f74bc13 | 5340 | } |
8fc2e39e | 5341 | break; |
5f74bc13 CD |
5342 | |
5343 | case M_DINS: | |
5344 | { | |
d5818fca MR |
5345 | /* Use unsigned arithmetic. */ |
5346 | addressT pos; | |
5347 | addressT size; | |
5f74bc13 | 5348 | |
90ecf173 | 5349 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5350 | { |
5351 | as_bad (_("Unsupported large constant")); | |
5352 | pos = size = 1; | |
5353 | } | |
5354 | else | |
5355 | { | |
d5818fca MR |
5356 | pos = imm_expr.X_add_number; |
5357 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5358 | } |
5359 | ||
5360 | if (pos > 63) | |
5361 | { | |
d5818fca | 5362 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5363 | pos = 1; |
5364 | } | |
90ecf173 | 5365 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5366 | { |
5367 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5368 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5369 | size = 1; |
5370 | } | |
5371 | ||
5372 | if (pos < 32 && (pos + size - 1) < 32) | |
5373 | { | |
5374 | s = "dins"; | |
5375 | fmt = "t,r,+A,+B"; | |
5376 | } | |
5377 | else if (pos >= 32) | |
5378 | { | |
5379 | s = "dinsu"; | |
5380 | fmt = "t,r,+E,+F"; | |
5381 | } | |
5382 | else | |
5383 | { | |
5384 | s = "dinsm"; | |
5385 | fmt = "t,r,+A,+F"; | |
5386 | } | |
750bdd57 AS |
5387 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5388 | (int) (pos + size - 1)); | |
5f74bc13 | 5389 | } |
8fc2e39e | 5390 | break; |
5f74bc13 | 5391 | |
252b5132 RH |
5392 | case M_DDIV_3: |
5393 | dbl = 1; | |
5394 | case M_DIV_3: | |
5395 | s = "mflo"; | |
5396 | goto do_div3; | |
5397 | case M_DREM_3: | |
5398 | dbl = 1; | |
5399 | case M_REM_3: | |
5400 | s = "mfhi"; | |
5401 | do_div3: | |
5402 | if (treg == 0) | |
5403 | { | |
5404 | as_warn (_("Divide by zero.")); | |
5405 | if (mips_trap) | |
c80c840e | 5406 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5407 | else |
67c0d1eb | 5408 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5409 | break; |
252b5132 RH |
5410 | } |
5411 | ||
7d10b47d | 5412 | start_noreorder (); |
252b5132 RH |
5413 | if (mips_trap) |
5414 | { | |
c80c840e | 5415 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5416 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5417 | } |
5418 | else | |
5419 | { | |
5420 | expr1.X_add_number = 8; | |
c80c840e | 5421 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5422 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5423 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5424 | } |
5425 | expr1.X_add_number = -1; | |
8fc2e39e | 5426 | used_at = 1; |
f6a22291 | 5427 | load_register (AT, &expr1, dbl); |
252b5132 | 5428 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5429 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5430 | if (dbl) |
5431 | { | |
5432 | expr1.X_add_number = 1; | |
f6a22291 | 5433 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5434 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5435 | } |
5436 | else | |
5437 | { | |
5438 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5439 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5440 | } |
5441 | if (mips_trap) | |
5442 | { | |
67c0d1eb | 5443 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5444 | /* We want to close the noreorder block as soon as possible, so |
5445 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5446 | end_noreorder (); |
252b5132 RH |
5447 | } |
5448 | else | |
5449 | { | |
5450 | expr1.X_add_number = 8; | |
67c0d1eb | 5451 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5452 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5453 | |
5454 | /* We want to close the noreorder block as soon as possible, so | |
5455 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5456 | end_noreorder (); |
252b5132 | 5457 | |
67c0d1eb | 5458 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5459 | } |
67c0d1eb | 5460 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5461 | break; |
5462 | ||
5463 | case M_DIV_3I: | |
5464 | s = "div"; | |
5465 | s2 = "mflo"; | |
5466 | goto do_divi; | |
5467 | case M_DIVU_3I: | |
5468 | s = "divu"; | |
5469 | s2 = "mflo"; | |
5470 | goto do_divi; | |
5471 | case M_REM_3I: | |
5472 | s = "div"; | |
5473 | s2 = "mfhi"; | |
5474 | goto do_divi; | |
5475 | case M_REMU_3I: | |
5476 | s = "divu"; | |
5477 | s2 = "mfhi"; | |
5478 | goto do_divi; | |
5479 | case M_DDIV_3I: | |
5480 | dbl = 1; | |
5481 | s = "ddiv"; | |
5482 | s2 = "mflo"; | |
5483 | goto do_divi; | |
5484 | case M_DDIVU_3I: | |
5485 | dbl = 1; | |
5486 | s = "ddivu"; | |
5487 | s2 = "mflo"; | |
5488 | goto do_divi; | |
5489 | case M_DREM_3I: | |
5490 | dbl = 1; | |
5491 | s = "ddiv"; | |
5492 | s2 = "mfhi"; | |
5493 | goto do_divi; | |
5494 | case M_DREMU_3I: | |
5495 | dbl = 1; | |
5496 | s = "ddivu"; | |
5497 | s2 = "mfhi"; | |
5498 | do_divi: | |
5499 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5500 | { | |
5501 | as_warn (_("Divide by zero.")); | |
5502 | if (mips_trap) | |
c80c840e | 5503 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5504 | else |
67c0d1eb | 5505 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5506 | break; |
252b5132 RH |
5507 | } |
5508 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5509 | { | |
5510 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5511 | move_register (dreg, sreg); |
252b5132 | 5512 | else |
c80c840e | 5513 | move_register (dreg, ZERO); |
8fc2e39e | 5514 | break; |
252b5132 RH |
5515 | } |
5516 | if (imm_expr.X_op == O_constant | |
5517 | && imm_expr.X_add_number == -1 | |
5518 | && s[strlen (s) - 1] != 'u') | |
5519 | { | |
5520 | if (strcmp (s2, "mflo") == 0) | |
5521 | { | |
67c0d1eb | 5522 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5523 | } |
5524 | else | |
c80c840e | 5525 | move_register (dreg, ZERO); |
8fc2e39e | 5526 | break; |
252b5132 RH |
5527 | } |
5528 | ||
8fc2e39e | 5529 | used_at = 1; |
67c0d1eb RS |
5530 | load_register (AT, &imm_expr, dbl); |
5531 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5532 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5533 | break; |
5534 | ||
5535 | case M_DIVU_3: | |
5536 | s = "divu"; | |
5537 | s2 = "mflo"; | |
5538 | goto do_divu3; | |
5539 | case M_REMU_3: | |
5540 | s = "divu"; | |
5541 | s2 = "mfhi"; | |
5542 | goto do_divu3; | |
5543 | case M_DDIVU_3: | |
5544 | s = "ddivu"; | |
5545 | s2 = "mflo"; | |
5546 | goto do_divu3; | |
5547 | case M_DREMU_3: | |
5548 | s = "ddivu"; | |
5549 | s2 = "mfhi"; | |
5550 | do_divu3: | |
7d10b47d | 5551 | start_noreorder (); |
252b5132 RH |
5552 | if (mips_trap) |
5553 | { | |
c80c840e | 5554 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5555 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5556 | /* We want to close the noreorder block as soon as possible, so |
5557 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5558 | end_noreorder (); |
252b5132 RH |
5559 | } |
5560 | else | |
5561 | { | |
5562 | expr1.X_add_number = 8; | |
c80c840e | 5563 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5564 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5565 | |
5566 | /* We want to close the noreorder block as soon as possible, so | |
5567 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5568 | end_noreorder (); |
67c0d1eb | 5569 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5570 | } |
67c0d1eb | 5571 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5572 | break; |
252b5132 | 5573 | |
1abe91b1 MR |
5574 | case M_DLCA_AB: |
5575 | dbl = 1; | |
5576 | case M_LCA_AB: | |
5577 | call = 1; | |
5578 | goto do_la; | |
252b5132 RH |
5579 | case M_DLA_AB: |
5580 | dbl = 1; | |
5581 | case M_LA_AB: | |
1abe91b1 | 5582 | do_la: |
252b5132 RH |
5583 | /* Load the address of a symbol into a register. If breg is not |
5584 | zero, we then add a base register to it. */ | |
5585 | ||
3bec30a8 TS |
5586 | if (dbl && HAVE_32BIT_GPRS) |
5587 | as_warn (_("dla used to load 32-bit register")); | |
5588 | ||
90ecf173 | 5589 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5590 | as_warn (_("la used to load 64-bit address")); |
5591 | ||
0c11417f MR |
5592 | if (offset_expr.X_op == O_constant |
5593 | && offset_expr.X_add_number >= -0x8000 | |
5594 | && offset_expr.X_add_number < 0x8000) | |
5595 | { | |
aed1a261 | 5596 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5597 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5598 | break; |
0c11417f MR |
5599 | } |
5600 | ||
741fe287 | 5601 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5602 | { |
5603 | tempreg = AT; | |
5604 | used_at = 1; | |
5605 | } | |
5606 | else | |
5607 | { | |
5608 | tempreg = treg; | |
afdbd6d0 CD |
5609 | } |
5610 | ||
252b5132 RH |
5611 | if (offset_expr.X_op != O_symbol |
5612 | && offset_expr.X_op != O_constant) | |
5613 | { | |
f71d0d44 | 5614 | as_bad (_("Expression too complex")); |
252b5132 RH |
5615 | offset_expr.X_op = O_constant; |
5616 | } | |
5617 | ||
252b5132 | 5618 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5619 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5620 | else if (mips_pic == NO_PIC) |
5621 | { | |
d6bc6245 | 5622 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5623 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5624 | Otherwise we want |
5625 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5626 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5627 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5628 | so we may as well always use the latter form. |
76b3015f | 5629 | |
6caf9ef4 TS |
5630 | With 64bit address space and a usable $at we want |
5631 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5632 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5633 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5634 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5635 | dsll32 $tempreg,0 | |
5636 | daddu $tempreg,$tempreg,$at | |
5637 | ||
5638 | If $at is already in use, we use a path which is suboptimal | |
5639 | on superscalar processors. | |
5640 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5641 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5642 | dsll $tempreg,16 | |
5643 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5644 | dsll $tempreg,16 | |
5645 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5646 | ||
5647 | For GP relative symbols in 64bit address space we can use | |
5648 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5649 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5650 | { |
6caf9ef4 TS |
5651 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5652 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5653 | { | |
5654 | relax_start (offset_expr.X_add_symbol); | |
5655 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5656 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5657 | relax_switch (); | |
5658 | } | |
d6bc6245 | 5659 | |
741fe287 | 5660 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5661 | { |
67c0d1eb | 5662 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5663 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5664 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5665 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5666 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5667 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5668 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5669 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5670 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5671 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5672 | used_at = 1; |
5673 | } | |
5674 | else | |
5675 | { | |
67c0d1eb | 5676 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5677 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5678 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5679 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5680 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5681 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5682 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5683 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5684 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5685 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5686 | } |
6caf9ef4 TS |
5687 | |
5688 | if (mips_relax.sequence) | |
5689 | relax_end (); | |
98d3f06f KH |
5690 | } |
5691 | else | |
5692 | { | |
5693 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5694 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5695 | { |
4d7206a2 | 5696 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5697 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5698 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5699 | relax_switch (); |
98d3f06f | 5700 | } |
6943caf0 | 5701 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5702 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5703 | macro_build_lui (&offset_expr, tempreg); |
5704 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5705 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5706 | if (mips_relax.sequence) |
5707 | relax_end (); | |
98d3f06f | 5708 | } |
252b5132 | 5709 | } |
0a44bf69 | 5710 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5711 | { |
9117d219 NC |
5712 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5713 | ||
252b5132 RH |
5714 | /* If this is a reference to an external symbol, and there |
5715 | is no constant, we want | |
5716 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5717 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5718 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5719 | For a local symbol, we want |
5720 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5721 | nop | |
5722 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5723 | ||
5724 | If we have a small constant, and this is a reference to | |
5725 | an external symbol, we want | |
5726 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5727 | nop | |
5728 | addiu $tempreg,$tempreg,<constant> | |
5729 | For a local symbol, we want the same instruction | |
5730 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5731 | addiu instruction. | |
5732 | ||
5733 | If we have a large constant, and this is a reference to | |
5734 | an external symbol, we want | |
5735 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5736 | lui $at,<hiconstant> | |
5737 | addiu $at,$at,<loconstant> | |
5738 | addu $tempreg,$tempreg,$at | |
5739 | For a local symbol, we want the same instruction | |
5740 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5741 | addiu instruction. |
ed6fb7bd SC |
5742 | */ |
5743 | ||
4d7206a2 | 5744 | if (offset_expr.X_add_number == 0) |
252b5132 | 5745 | { |
0a44bf69 RS |
5746 | if (mips_pic == SVR4_PIC |
5747 | && breg == 0 | |
5748 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5749 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5750 | ||
5751 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5752 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5753 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5754 | if (breg != 0) |
252b5132 RH |
5755 | { |
5756 | /* We're going to put in an addu instruction using | |
5757 | tempreg, so we may as well insert the nop right | |
5758 | now. */ | |
269137b2 | 5759 | load_delay_nop (); |
252b5132 | 5760 | } |
4d7206a2 | 5761 | relax_switch (); |
67c0d1eb RS |
5762 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5763 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5764 | load_delay_nop (); |
67c0d1eb RS |
5765 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5766 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5767 | relax_end (); |
252b5132 RH |
5768 | /* FIXME: If breg == 0, and the next instruction uses |
5769 | $tempreg, then if this variant case is used an extra | |
5770 | nop will be generated. */ | |
5771 | } | |
4d7206a2 RS |
5772 | else if (offset_expr.X_add_number >= -0x8000 |
5773 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5774 | { |
67c0d1eb | 5775 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5776 | load_delay_nop (); |
67c0d1eb | 5777 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5778 | } |
5779 | else | |
5780 | { | |
4d7206a2 RS |
5781 | expr1.X_add_number = offset_expr.X_add_number; |
5782 | offset_expr.X_add_number = | |
5783 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5784 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5785 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5786 | /* If we are going to add in a base register, and the |
5787 | target register and the base register are the same, | |
5788 | then we are using AT as a temporary register. Since | |
5789 | we want to load the constant into AT, we add our | |
5790 | current AT (from the global offset table) and the | |
5791 | register into the register now, and pretend we were | |
5792 | not using a base register. */ | |
67c0d1eb | 5793 | if (breg == treg) |
252b5132 | 5794 | { |
269137b2 | 5795 | load_delay_nop (); |
67c0d1eb | 5796 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5797 | treg, AT, breg); |
252b5132 RH |
5798 | breg = 0; |
5799 | tempreg = treg; | |
252b5132 | 5800 | } |
f6a22291 | 5801 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5802 | used_at = 1; |
5803 | } | |
5804 | } | |
0a44bf69 | 5805 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5806 | { |
67c0d1eb | 5807 | int add_breg_early = 0; |
f5040a92 AO |
5808 | |
5809 | /* If this is a reference to an external, and there is no | |
5810 | constant, or local symbol (*), with or without a | |
5811 | constant, we want | |
5812 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5813 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5814 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5815 | ||
5816 | If we have a small constant, and this is a reference to | |
5817 | an external symbol, we want | |
5818 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5819 | addiu $tempreg,$tempreg,<constant> | |
5820 | ||
5821 | If we have a large constant, and this is a reference to | |
5822 | an external symbol, we want | |
5823 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5824 | lui $at,<hiconstant> | |
5825 | addiu $at,$at,<loconstant> | |
5826 | addu $tempreg,$tempreg,$at | |
5827 | ||
5828 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5829 | local symbols, even though it introduces an additional | |
5830 | instruction. */ | |
5831 | ||
f5040a92 AO |
5832 | if (offset_expr.X_add_number) |
5833 | { | |
4d7206a2 | 5834 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5835 | offset_expr.X_add_number = 0; |
5836 | ||
4d7206a2 | 5837 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5838 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5839 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5840 | |
5841 | if (expr1.X_add_number >= -0x8000 | |
5842 | && expr1.X_add_number < 0x8000) | |
5843 | { | |
67c0d1eb RS |
5844 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5845 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5846 | } |
ecd13cd3 | 5847 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 5848 | { |
f5040a92 AO |
5849 | /* If we are going to add in a base register, and the |
5850 | target register and the base register are the same, | |
5851 | then we are using AT as a temporary register. Since | |
5852 | we want to load the constant into AT, we add our | |
5853 | current AT (from the global offset table) and the | |
5854 | register into the register now, and pretend we were | |
5855 | not using a base register. */ | |
5856 | if (breg != treg) | |
5857 | dreg = tempreg; | |
5858 | else | |
5859 | { | |
9c2799c2 | 5860 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5861 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5862 | treg, AT, breg); | |
f5040a92 | 5863 | dreg = treg; |
67c0d1eb | 5864 | add_breg_early = 1; |
f5040a92 AO |
5865 | } |
5866 | ||
f6a22291 | 5867 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5868 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5869 | dreg, dreg, AT); |
f5040a92 | 5870 | |
f5040a92 AO |
5871 | used_at = 1; |
5872 | } | |
5873 | else | |
5874 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5875 | ||
4d7206a2 | 5876 | relax_switch (); |
f5040a92 AO |
5877 | offset_expr.X_add_number = expr1.X_add_number; |
5878 | ||
67c0d1eb RS |
5879 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5880 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5881 | if (add_breg_early) | |
f5040a92 | 5882 | { |
67c0d1eb | 5883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5884 | treg, tempreg, breg); |
f5040a92 AO |
5885 | breg = 0; |
5886 | tempreg = treg; | |
5887 | } | |
4d7206a2 | 5888 | relax_end (); |
f5040a92 | 5889 | } |
4d7206a2 | 5890 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5891 | { |
4d7206a2 | 5892 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5893 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5894 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5895 | relax_switch (); |
67c0d1eb RS |
5896 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5897 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5898 | relax_end (); |
f5040a92 | 5899 | } |
4d7206a2 | 5900 | else |
f5040a92 | 5901 | { |
67c0d1eb RS |
5902 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5903 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5904 | } |
5905 | } | |
0a44bf69 | 5906 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5907 | { |
67c0d1eb | 5908 | int gpdelay; |
9117d219 NC |
5909 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5910 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5911 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5912 | |
5913 | /* This is the large GOT case. If this is a reference to an | |
5914 | external symbol, and there is no constant, we want | |
5915 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5916 | addu $tempreg,$tempreg,$gp | |
5917 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5918 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5919 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5920 | addu $tempreg,$tempreg,$gp | |
5921 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5922 | For a local symbol, we want |
5923 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5924 | nop | |
5925 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5926 | ||
5927 | If we have a small constant, and this is a reference to | |
5928 | an external symbol, we want | |
5929 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5930 | addu $tempreg,$tempreg,$gp | |
5931 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5932 | nop | |
5933 | addiu $tempreg,$tempreg,<constant> | |
5934 | For a local symbol, we want | |
5935 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5936 | nop | |
5937 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5938 | ||
5939 | If we have a large constant, and this is a reference to | |
5940 | an external symbol, we want | |
5941 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5942 | addu $tempreg,$tempreg,$gp | |
5943 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5944 | lui $at,<hiconstant> | |
5945 | addiu $at,$at,<loconstant> | |
5946 | addu $tempreg,$tempreg,$at | |
5947 | For a local symbol, we want | |
5948 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5949 | lui $at,<hiconstant> | |
5950 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5951 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5952 | */ |
438c16b8 | 5953 | |
252b5132 RH |
5954 | expr1.X_add_number = offset_expr.X_add_number; |
5955 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5956 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5957 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5958 | if (expr1.X_add_number == 0 && breg == 0 |
5959 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5960 | { |
5961 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5962 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5963 | } | |
67c0d1eb RS |
5964 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5965 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5966 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5967 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5968 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5969 | if (expr1.X_add_number == 0) |
5970 | { | |
67c0d1eb | 5971 | if (breg != 0) |
252b5132 RH |
5972 | { |
5973 | /* We're going to put in an addu instruction using | |
5974 | tempreg, so we may as well insert the nop right | |
5975 | now. */ | |
269137b2 | 5976 | load_delay_nop (); |
252b5132 | 5977 | } |
252b5132 RH |
5978 | } |
5979 | else if (expr1.X_add_number >= -0x8000 | |
5980 | && expr1.X_add_number < 0x8000) | |
5981 | { | |
269137b2 | 5982 | load_delay_nop (); |
67c0d1eb | 5983 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5984 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5985 | } |
5986 | else | |
5987 | { | |
252b5132 RH |
5988 | /* If we are going to add in a base register, and the |
5989 | target register and the base register are the same, | |
5990 | then we are using AT as a temporary register. Since | |
5991 | we want to load the constant into AT, we add our | |
5992 | current AT (from the global offset table) and the | |
5993 | register into the register now, and pretend we were | |
5994 | not using a base register. */ | |
5995 | if (breg != treg) | |
67c0d1eb | 5996 | dreg = tempreg; |
252b5132 RH |
5997 | else |
5998 | { | |
9c2799c2 | 5999 | gas_assert (tempreg == AT); |
269137b2 | 6000 | load_delay_nop (); |
67c0d1eb | 6001 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6002 | treg, AT, breg); |
252b5132 | 6003 | dreg = treg; |
252b5132 RH |
6004 | } |
6005 | ||
f6a22291 | 6006 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6007 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 6008 | |
252b5132 RH |
6009 | used_at = 1; |
6010 | } | |
4d7206a2 RS |
6011 | offset_expr.X_add_number = |
6012 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
6013 | relax_switch (); | |
252b5132 | 6014 | |
67c0d1eb | 6015 | if (gpdelay) |
252b5132 RH |
6016 | { |
6017 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 6018 | the first instruction on the main stream does not. */ |
67c0d1eb | 6019 | macro_build (NULL, "nop", ""); |
252b5132 | 6020 | } |
ed6fb7bd | 6021 | |
67c0d1eb RS |
6022 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6023 | local_reloc_type, mips_gp_register); | |
f5040a92 | 6024 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
6025 | && expr1.X_add_number < 0x8000) |
6026 | { | |
269137b2 | 6027 | load_delay_nop (); |
67c0d1eb RS |
6028 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6029 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6030 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6031 | register, the external symbol case ended with a load, |
6032 | so if the symbol turns out to not be external, and | |
6033 | the next instruction uses tempreg, an unnecessary nop | |
6034 | will be inserted. */ | |
252b5132 RH |
6035 | } |
6036 | else | |
6037 | { | |
6038 | if (breg == treg) | |
6039 | { | |
6040 | /* We must add in the base register now, as in the | |
f5040a92 | 6041 | external symbol case. */ |
9c2799c2 | 6042 | gas_assert (tempreg == AT); |
269137b2 | 6043 | load_delay_nop (); |
67c0d1eb | 6044 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6045 | treg, AT, breg); |
252b5132 RH |
6046 | tempreg = treg; |
6047 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6048 | it in in both cases. */ |
252b5132 RH |
6049 | breg = 0; |
6050 | } | |
6051 | ||
67c0d1eb RS |
6052 | macro_build_lui (&expr1, AT); |
6053 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6054 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6056 | tempreg, tempreg, AT); |
8fc2e39e | 6057 | used_at = 1; |
252b5132 | 6058 | } |
4d7206a2 | 6059 | relax_end (); |
252b5132 | 6060 | } |
0a44bf69 | 6061 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6062 | { |
f5040a92 AO |
6063 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6064 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6065 | int add_breg_early = 0; |
f5040a92 AO |
6066 | |
6067 | /* This is the large GOT case. If this is a reference to an | |
6068 | external symbol, and there is no constant, we want | |
6069 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6070 | add $tempreg,$tempreg,$gp | |
6071 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6072 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6073 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6074 | add $tempreg,$tempreg,$gp | |
6075 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6076 | ||
6077 | If we have a small constant, and this is a reference to | |
6078 | an external symbol, we want | |
6079 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6080 | add $tempreg,$tempreg,$gp | |
6081 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6082 | addi $tempreg,$tempreg,<constant> | |
6083 | ||
6084 | If we have a large constant, and this is a reference to | |
6085 | an external symbol, we want | |
6086 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6087 | addu $tempreg,$tempreg,$gp | |
6088 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6089 | lui $at,<hiconstant> | |
6090 | addi $at,$at,<loconstant> | |
6091 | add $tempreg,$tempreg,$at | |
6092 | ||
6093 | If we have NewABI, and we know it's a local symbol, we want | |
6094 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6095 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6096 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6097 | ||
4d7206a2 | 6098 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6099 | |
4d7206a2 | 6100 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6101 | offset_expr.X_add_number = 0; |
6102 | ||
1abe91b1 MR |
6103 | if (expr1.X_add_number == 0 && breg == 0 |
6104 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6105 | { |
6106 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6107 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6108 | } | |
67c0d1eb RS |
6109 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6110 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6111 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6112 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6113 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6114 | |
6115 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6116 | ; |
f5040a92 AO |
6117 | else if (expr1.X_add_number >= -0x8000 |
6118 | && expr1.X_add_number < 0x8000) | |
6119 | { | |
67c0d1eb | 6120 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6121 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6122 | } |
ecd13cd3 | 6123 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6124 | { |
f5040a92 AO |
6125 | /* If we are going to add in a base register, and the |
6126 | target register and the base register are the same, | |
6127 | then we are using AT as a temporary register. Since | |
6128 | we want to load the constant into AT, we add our | |
6129 | current AT (from the global offset table) and the | |
6130 | register into the register now, and pretend we were | |
6131 | not using a base register. */ | |
6132 | if (breg != treg) | |
6133 | dreg = tempreg; | |
6134 | else | |
6135 | { | |
9c2799c2 | 6136 | gas_assert (tempreg == AT); |
67c0d1eb | 6137 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6138 | treg, AT, breg); |
f5040a92 | 6139 | dreg = treg; |
67c0d1eb | 6140 | add_breg_early = 1; |
f5040a92 AO |
6141 | } |
6142 | ||
f6a22291 | 6143 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6145 | |
f5040a92 AO |
6146 | used_at = 1; |
6147 | } | |
6148 | else | |
6149 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6150 | ||
4d7206a2 | 6151 | relax_switch (); |
f5040a92 | 6152 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6153 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6154 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6155 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6156 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6157 | if (add_breg_early) | |
f5040a92 | 6158 | { |
67c0d1eb | 6159 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6160 | treg, tempreg, breg); |
f5040a92 AO |
6161 | breg = 0; |
6162 | tempreg = treg; | |
6163 | } | |
4d7206a2 | 6164 | relax_end (); |
f5040a92 | 6165 | } |
252b5132 RH |
6166 | else |
6167 | abort (); | |
6168 | ||
6169 | if (breg != 0) | |
aed1a261 | 6170 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6171 | break; |
6172 | ||
52b6b6b9 JM |
6173 | case M_MSGSND: |
6174 | { | |
6175 | unsigned long temp = (treg << 16) | (0x01); | |
6176 | macro_build (NULL, "c2", "C", temp); | |
6177 | } | |
c7af4273 | 6178 | break; |
52b6b6b9 JM |
6179 | |
6180 | case M_MSGLD: | |
6181 | { | |
6182 | unsigned long temp = (0x02); | |
6183 | macro_build (NULL, "c2", "C", temp); | |
6184 | } | |
c7af4273 | 6185 | break; |
52b6b6b9 JM |
6186 | |
6187 | case M_MSGLD_T: | |
6188 | { | |
6189 | unsigned long temp = (treg << 16) | (0x02); | |
6190 | macro_build (NULL, "c2", "C", temp); | |
6191 | } | |
c7af4273 | 6192 | break; |
52b6b6b9 JM |
6193 | |
6194 | case M_MSGWAIT: | |
6195 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6196 | break; |
52b6b6b9 JM |
6197 | |
6198 | case M_MSGWAIT_T: | |
6199 | { | |
6200 | unsigned long temp = (treg << 16) | 0x03; | |
6201 | macro_build (NULL, "c2", "C", temp); | |
6202 | } | |
c7af4273 | 6203 | break; |
52b6b6b9 | 6204 | |
252b5132 RH |
6205 | case M_J_A: |
6206 | /* The j instruction may not be used in PIC code, since it | |
6207 | requires an absolute address. We convert it to a b | |
6208 | instruction. */ | |
6209 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6210 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6211 | else |
67c0d1eb | 6212 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6213 | break; |
252b5132 RH |
6214 | |
6215 | /* The jal instructions must be handled as macros because when | |
6216 | generating PIC code they expand to multi-instruction | |
6217 | sequences. Normally they are simple instructions. */ | |
6218 | case M_JAL_1: | |
6219 | dreg = RA; | |
6220 | /* Fall through. */ | |
6221 | case M_JAL_2: | |
3e722fb5 | 6222 | if (mips_pic == NO_PIC) |
67c0d1eb | 6223 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6224 | else |
252b5132 RH |
6225 | { |
6226 | if (sreg != PIC_CALL_REG) | |
6227 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6228 | |
67c0d1eb | 6229 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6230 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6231 | { |
6478892d TS |
6232 | if (mips_cprestore_offset < 0) |
6233 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6234 | else | |
6235 | { | |
90ecf173 | 6236 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6237 | { |
6238 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6239 | /* Quiet this warning. */ | |
6240 | mips_frame_reg_valid = 1; | |
6241 | } | |
90ecf173 | 6242 | if (!mips_cprestore_valid) |
7a621144 DJ |
6243 | { |
6244 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6245 | /* Quiet this warning. */ | |
6246 | mips_cprestore_valid = 1; | |
6247 | } | |
d3fca0b5 MR |
6248 | if (mips_opts.noreorder) |
6249 | macro_build (NULL, "nop", ""); | |
6478892d | 6250 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6251 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6252 | mips_gp_register, |
256ab948 TS |
6253 | mips_frame_reg, |
6254 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6255 | } |
252b5132 RH |
6256 | } |
6257 | } | |
252b5132 | 6258 | |
8fc2e39e | 6259 | break; |
252b5132 RH |
6260 | |
6261 | case M_JAL_A: | |
6262 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6263 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6264 | else if (mips_pic == SVR4_PIC) |
6265 | { | |
6266 | /* If this is a reference to an external symbol, and we are | |
6267 | using a small GOT, we want | |
6268 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6269 | nop | |
f9419b05 | 6270 | jalr $ra,$25 |
252b5132 RH |
6271 | nop |
6272 | lw $gp,cprestore($sp) | |
6273 | The cprestore value is set using the .cprestore | |
6274 | pseudo-op. If we are using a big GOT, we want | |
6275 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6276 | addu $25,$25,$gp | |
6277 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6278 | nop | |
f9419b05 | 6279 | jalr $ra,$25 |
252b5132 RH |
6280 | nop |
6281 | lw $gp,cprestore($sp) | |
6282 | If the symbol is not external, we want | |
6283 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6284 | nop | |
6285 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6286 | jalr $ra,$25 |
252b5132 | 6287 | nop |
438c16b8 | 6288 | lw $gp,cprestore($sp) |
f5040a92 AO |
6289 | |
6290 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6291 | sequences above, minus nops, unless the symbol is local, | |
6292 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6293 | GOT_DISP. */ | |
438c16b8 | 6294 | if (HAVE_NEWABI) |
252b5132 | 6295 | { |
90ecf173 | 6296 | if (!mips_big_got) |
f5040a92 | 6297 | { |
4d7206a2 | 6298 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6299 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6300 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6301 | mips_gp_register); |
4d7206a2 | 6302 | relax_switch (); |
67c0d1eb RS |
6303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6304 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6305 | mips_gp_register); |
6306 | relax_end (); | |
f5040a92 AO |
6307 | } |
6308 | else | |
6309 | { | |
4d7206a2 | 6310 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6311 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6312 | BFD_RELOC_MIPS_CALL_HI16); | |
6313 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6314 | PIC_CALL_REG, mips_gp_register); | |
6315 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6316 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6317 | PIC_CALL_REG); | |
4d7206a2 | 6318 | relax_switch (); |
67c0d1eb RS |
6319 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6320 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6321 | mips_gp_register); | |
6322 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6323 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6324 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6325 | relax_end (); |
f5040a92 | 6326 | } |
684022ea | 6327 | |
67c0d1eb | 6328 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6329 | } |
6330 | else | |
6331 | { | |
4d7206a2 | 6332 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6333 | if (!mips_big_got) |
438c16b8 | 6334 | { |
67c0d1eb RS |
6335 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6336 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6337 | mips_gp_register); |
269137b2 | 6338 | load_delay_nop (); |
4d7206a2 | 6339 | relax_switch (); |
438c16b8 | 6340 | } |
252b5132 | 6341 | else |
252b5132 | 6342 | { |
67c0d1eb RS |
6343 | int gpdelay; |
6344 | ||
6345 | gpdelay = reg_needs_delay (mips_gp_register); | |
6346 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6347 | BFD_RELOC_MIPS_CALL_HI16); | |
6348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6349 | PIC_CALL_REG, mips_gp_register); | |
6350 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6351 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6352 | PIC_CALL_REG); | |
269137b2 | 6353 | load_delay_nop (); |
4d7206a2 | 6354 | relax_switch (); |
67c0d1eb RS |
6355 | if (gpdelay) |
6356 | macro_build (NULL, "nop", ""); | |
252b5132 | 6357 | } |
67c0d1eb RS |
6358 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6359 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6360 | mips_gp_register); |
269137b2 | 6361 | load_delay_nop (); |
67c0d1eb RS |
6362 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6363 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6364 | relax_end (); |
67c0d1eb | 6365 | macro_build_jalr (&offset_expr); |
438c16b8 | 6366 | |
6478892d TS |
6367 | if (mips_cprestore_offset < 0) |
6368 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6369 | else | |
6370 | { | |
90ecf173 | 6371 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6372 | { |
6373 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6374 | /* Quiet this warning. */ | |
6375 | mips_frame_reg_valid = 1; | |
6376 | } | |
90ecf173 | 6377 | if (!mips_cprestore_valid) |
7a621144 DJ |
6378 | { |
6379 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6380 | /* Quiet this warning. */ | |
6381 | mips_cprestore_valid = 1; | |
6382 | } | |
6478892d | 6383 | if (mips_opts.noreorder) |
67c0d1eb | 6384 | macro_build (NULL, "nop", ""); |
6478892d | 6385 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6386 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6387 | mips_gp_register, |
256ab948 TS |
6388 | mips_frame_reg, |
6389 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6390 | } |
252b5132 RH |
6391 | } |
6392 | } | |
0a44bf69 RS |
6393 | else if (mips_pic == VXWORKS_PIC) |
6394 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6395 | else |
6396 | abort (); | |
6397 | ||
8fc2e39e | 6398 | break; |
252b5132 RH |
6399 | |
6400 | case M_LB_AB: | |
6401 | s = "lb"; | |
6402 | goto ld; | |
6403 | case M_LBU_AB: | |
6404 | s = "lbu"; | |
6405 | goto ld; | |
6406 | case M_LH_AB: | |
6407 | s = "lh"; | |
6408 | goto ld; | |
6409 | case M_LHU_AB: | |
6410 | s = "lhu"; | |
6411 | goto ld; | |
6412 | case M_LW_AB: | |
6413 | s = "lw"; | |
6414 | goto ld; | |
6415 | case M_LWC0_AB: | |
6416 | s = "lwc0"; | |
bdaaa2e1 | 6417 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6418 | coproc = 1; |
6419 | goto ld; | |
6420 | case M_LWC1_AB: | |
6421 | s = "lwc1"; | |
bdaaa2e1 | 6422 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6423 | coproc = 1; |
6424 | goto ld; | |
6425 | case M_LWC2_AB: | |
6426 | s = "lwc2"; | |
bdaaa2e1 | 6427 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6428 | coproc = 1; |
6429 | goto ld; | |
6430 | case M_LWC3_AB: | |
6431 | s = "lwc3"; | |
bdaaa2e1 | 6432 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6433 | coproc = 1; |
6434 | goto ld; | |
6435 | case M_LWL_AB: | |
6436 | s = "lwl"; | |
6437 | lr = 1; | |
6438 | goto ld; | |
6439 | case M_LWR_AB: | |
6440 | s = "lwr"; | |
6441 | lr = 1; | |
6442 | goto ld; | |
6443 | case M_LDC1_AB: | |
252b5132 | 6444 | s = "ldc1"; |
bdaaa2e1 | 6445 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6446 | coproc = 1; |
6447 | goto ld; | |
6448 | case M_LDC2_AB: | |
6449 | s = "ldc2"; | |
bdaaa2e1 | 6450 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6451 | coproc = 1; |
6452 | goto ld; | |
6453 | case M_LDC3_AB: | |
6454 | s = "ldc3"; | |
bdaaa2e1 | 6455 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6456 | coproc = 1; |
6457 | goto ld; | |
6458 | case M_LDL_AB: | |
6459 | s = "ldl"; | |
6460 | lr = 1; | |
6461 | goto ld; | |
6462 | case M_LDR_AB: | |
6463 | s = "ldr"; | |
6464 | lr = 1; | |
6465 | goto ld; | |
6466 | case M_LL_AB: | |
6467 | s = "ll"; | |
6468 | goto ld; | |
6469 | case M_LLD_AB: | |
6470 | s = "lld"; | |
6471 | goto ld; | |
6472 | case M_LWU_AB: | |
6473 | s = "lwu"; | |
6474 | ld: | |
8fc2e39e | 6475 | if (breg == treg || coproc || lr) |
252b5132 RH |
6476 | { |
6477 | tempreg = AT; | |
6478 | used_at = 1; | |
6479 | } | |
6480 | else | |
6481 | { | |
6482 | tempreg = treg; | |
252b5132 RH |
6483 | } |
6484 | goto ld_st; | |
6485 | case M_SB_AB: | |
6486 | s = "sb"; | |
6487 | goto st; | |
6488 | case M_SH_AB: | |
6489 | s = "sh"; | |
6490 | goto st; | |
6491 | case M_SW_AB: | |
6492 | s = "sw"; | |
6493 | goto st; | |
6494 | case M_SWC0_AB: | |
6495 | s = "swc0"; | |
bdaaa2e1 | 6496 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6497 | coproc = 1; |
6498 | goto st; | |
6499 | case M_SWC1_AB: | |
6500 | s = "swc1"; | |
bdaaa2e1 | 6501 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6502 | coproc = 1; |
6503 | goto st; | |
6504 | case M_SWC2_AB: | |
6505 | s = "swc2"; | |
bdaaa2e1 | 6506 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6507 | coproc = 1; |
6508 | goto st; | |
6509 | case M_SWC3_AB: | |
6510 | s = "swc3"; | |
bdaaa2e1 | 6511 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6512 | coproc = 1; |
6513 | goto st; | |
6514 | case M_SWL_AB: | |
6515 | s = "swl"; | |
6516 | goto st; | |
6517 | case M_SWR_AB: | |
6518 | s = "swr"; | |
6519 | goto st; | |
6520 | case M_SC_AB: | |
6521 | s = "sc"; | |
6522 | goto st; | |
6523 | case M_SCD_AB: | |
6524 | s = "scd"; | |
6525 | goto st; | |
d43b4baf TS |
6526 | case M_CACHE_AB: |
6527 | s = "cache"; | |
6528 | goto st; | |
3eebd5eb MR |
6529 | case M_PREF_AB: |
6530 | s = "pref"; | |
6531 | goto st; | |
252b5132 | 6532 | case M_SDC1_AB: |
252b5132 RH |
6533 | s = "sdc1"; |
6534 | coproc = 1; | |
bdaaa2e1 | 6535 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6536 | goto st; |
6537 | case M_SDC2_AB: | |
6538 | s = "sdc2"; | |
bdaaa2e1 | 6539 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6540 | coproc = 1; |
6541 | goto st; | |
6542 | case M_SDC3_AB: | |
6543 | s = "sdc3"; | |
bdaaa2e1 | 6544 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6545 | coproc = 1; |
6546 | goto st; | |
6547 | case M_SDL_AB: | |
6548 | s = "sdl"; | |
6549 | goto st; | |
6550 | case M_SDR_AB: | |
6551 | s = "sdr"; | |
6552 | st: | |
8fc2e39e TS |
6553 | tempreg = AT; |
6554 | used_at = 1; | |
252b5132 | 6555 | ld_st: |
b19e8a9b AN |
6556 | if (coproc |
6557 | && NO_ISA_COP (mips_opts.arch) | |
6558 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6559 | { | |
f71d0d44 | 6560 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6561 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6562 | break; | |
6563 | } | |
6564 | ||
bdaaa2e1 | 6565 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6566 | if (mask == M_LWC1_AB |
6567 | || mask == M_SWC1_AB | |
6568 | || mask == M_LDC1_AB | |
6569 | || mask == M_SDC1_AB | |
6570 | || mask == M_L_DAB | |
6571 | || mask == M_S_DAB) | |
6572 | fmt = "T,o(b)"; | |
3eebd5eb | 6573 | else if (mask == M_CACHE_AB || mask == M_PREF_AB) |
d43b4baf | 6574 | fmt = "k,o(b)"; |
252b5132 RH |
6575 | else if (coproc) |
6576 | fmt = "E,o(b)"; | |
6577 | else | |
6578 | fmt = "t,o(b)"; | |
6579 | ||
6580 | if (offset_expr.X_op != O_constant | |
6581 | && offset_expr.X_op != O_symbol) | |
6582 | { | |
f71d0d44 | 6583 | as_bad (_("Expression too complex")); |
252b5132 RH |
6584 | offset_expr.X_op = O_constant; |
6585 | } | |
6586 | ||
2051e8c4 MR |
6587 | if (HAVE_32BIT_ADDRESSES |
6588 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6589 | { |
6590 | char value [32]; | |
6591 | ||
6592 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6593 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6594 | } |
2051e8c4 | 6595 | |
252b5132 RH |
6596 | /* A constant expression in PIC code can be handled just as it |
6597 | is in non PIC code. */ | |
aed1a261 RS |
6598 | if (offset_expr.X_op == O_constant) |
6599 | { | |
842f8b2a | 6600 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6601 | normalize_address_expr (&expr1); |
842f8b2a MR |
6602 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6603 | { | |
6604 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6605 | & ~(bfd_vma) 0xffff); | |
6606 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6607 | if (breg != 0) | |
6608 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6609 | tempreg, tempreg, breg); | |
6610 | breg = tempreg; | |
6611 | } | |
6612 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6613 | } |
6614 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6615 | { |
6616 | /* If this is a reference to a GP relative symbol, and there | |
6617 | is no base register, we want | |
cdf6fd85 | 6618 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6619 | Otherwise, if there is no base register, we want |
6620 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6621 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6622 | If we have a constant, we need two instructions anyhow, | |
6623 | so we always use the latter form. | |
6624 | ||
6625 | If we have a base register, and this is a reference to a | |
6626 | GP relative symbol, we want | |
6627 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6628 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6629 | Otherwise we want |
6630 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6631 | addu $tempreg,$tempreg,$breg | |
6632 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6633 | With a constant we always use the latter case. |
76b3015f | 6634 | |
d6bc6245 TS |
6635 | With 64bit address space and no base register and $at usable, |
6636 | we want | |
6637 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6638 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6639 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6640 | dsll32 $tempreg,0 | |
6641 | daddu $tempreg,$at | |
6642 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6643 | If we have a base register, we want | |
6644 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6645 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6646 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6647 | daddu $at,$breg | |
6648 | dsll32 $tempreg,0 | |
6649 | daddu $tempreg,$at | |
6650 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6651 | ||
6652 | Without $at we can't generate the optimal path for superscalar | |
6653 | processors here since this would require two temporary registers. | |
6654 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6655 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6656 | dsll $tempreg,16 | |
6657 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6658 | dsll $tempreg,16 | |
6659 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6660 | If we have a base register, we want | |
6661 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6662 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6663 | dsll $tempreg,16 | |
6664 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6665 | dsll $tempreg,16 | |
6666 | daddu $tempreg,$tempreg,$breg | |
6667 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6668 | |
6caf9ef4 | 6669 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6670 | the same sequence as in 32bit address space. */ |
6671 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6672 | { |
aed1a261 | 6673 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6674 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6675 | { | |
6676 | relax_start (offset_expr.X_add_symbol); | |
6677 | if (breg == 0) | |
6678 | { | |
6679 | macro_build (&offset_expr, s, fmt, treg, | |
6680 | BFD_RELOC_GPREL16, mips_gp_register); | |
6681 | } | |
6682 | else | |
6683 | { | |
6684 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6685 | tempreg, breg, mips_gp_register); | |
6686 | macro_build (&offset_expr, s, fmt, treg, | |
6687 | BFD_RELOC_GPREL16, tempreg); | |
6688 | } | |
6689 | relax_switch (); | |
6690 | } | |
d6bc6245 | 6691 | |
741fe287 | 6692 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6693 | { |
67c0d1eb RS |
6694 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6695 | BFD_RELOC_MIPS_HIGHEST); | |
6696 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6697 | BFD_RELOC_HI16_S); | |
6698 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6699 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6700 | if (breg != 0) |
67c0d1eb RS |
6701 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6702 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6703 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6704 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6705 | tempreg); | |
d6bc6245 TS |
6706 | used_at = 1; |
6707 | } | |
6708 | else | |
6709 | { | |
67c0d1eb RS |
6710 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6711 | BFD_RELOC_MIPS_HIGHEST); | |
6712 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6713 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6714 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6715 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6716 | tempreg, BFD_RELOC_HI16_S); | |
6717 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6718 | if (breg != 0) |
67c0d1eb | 6719 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6720 | tempreg, tempreg, breg); |
67c0d1eb | 6721 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6722 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6723 | } |
6caf9ef4 TS |
6724 | |
6725 | if (mips_relax.sequence) | |
6726 | relax_end (); | |
8fc2e39e | 6727 | break; |
d6bc6245 | 6728 | } |
256ab948 | 6729 | |
252b5132 RH |
6730 | if (breg == 0) |
6731 | { | |
67c0d1eb | 6732 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6733 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6734 | { |
4d7206a2 | 6735 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6736 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6737 | mips_gp_register); | |
4d7206a2 | 6738 | relax_switch (); |
252b5132 | 6739 | } |
67c0d1eb RS |
6740 | macro_build_lui (&offset_expr, tempreg); |
6741 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6742 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6743 | if (mips_relax.sequence) |
6744 | relax_end (); | |
252b5132 RH |
6745 | } |
6746 | else | |
6747 | { | |
67c0d1eb | 6748 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6749 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6750 | { |
4d7206a2 | 6751 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6752 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6753 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6754 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6755 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6756 | relax_switch (); |
252b5132 | 6757 | } |
67c0d1eb RS |
6758 | macro_build_lui (&offset_expr, tempreg); |
6759 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6760 | tempreg, tempreg, breg); |
67c0d1eb | 6761 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6762 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6763 | if (mips_relax.sequence) |
6764 | relax_end (); | |
252b5132 RH |
6765 | } |
6766 | } | |
0a44bf69 | 6767 | else if (!mips_big_got) |
252b5132 | 6768 | { |
ed6fb7bd | 6769 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6770 | |
252b5132 RH |
6771 | /* If this is a reference to an external symbol, we want |
6772 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6773 | nop | |
6774 | <op> $treg,0($tempreg) | |
6775 | Otherwise we want | |
6776 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6777 | nop | |
6778 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6779 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6780 | |
6781 | For NewABI, we want | |
6782 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6783 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6784 | ||
252b5132 RH |
6785 | If there is a base register, we add it to $tempreg before |
6786 | the <op>. If there is a constant, we stick it in the | |
6787 | <op> instruction. We don't handle constants larger than | |
6788 | 16 bits, because we have no way to load the upper 16 bits | |
6789 | (actually, we could handle them for the subset of cases | |
6790 | in which we are not using $at). */ | |
9c2799c2 | 6791 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6792 | if (HAVE_NEWABI) |
6793 | { | |
67c0d1eb RS |
6794 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6795 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6796 | if (breg != 0) |
67c0d1eb | 6797 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6798 | tempreg, tempreg, breg); |
67c0d1eb | 6799 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6800 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6801 | break; |
6802 | } | |
252b5132 RH |
6803 | expr1.X_add_number = offset_expr.X_add_number; |
6804 | offset_expr.X_add_number = 0; | |
6805 | if (expr1.X_add_number < -0x8000 | |
6806 | || expr1.X_add_number >= 0x8000) | |
6807 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6808 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6809 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6810 | load_delay_nop (); |
4d7206a2 RS |
6811 | relax_start (offset_expr.X_add_symbol); |
6812 | relax_switch (); | |
67c0d1eb RS |
6813 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6814 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6815 | relax_end (); |
252b5132 | 6816 | if (breg != 0) |
67c0d1eb | 6817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6818 | tempreg, tempreg, breg); |
67c0d1eb | 6819 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6820 | } |
0a44bf69 | 6821 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6822 | { |
67c0d1eb | 6823 | int gpdelay; |
252b5132 RH |
6824 | |
6825 | /* If this is a reference to an external symbol, we want | |
6826 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6827 | addu $tempreg,$tempreg,$gp | |
6828 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6829 | <op> $treg,0($tempreg) | |
6830 | Otherwise we want | |
6831 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6832 | nop | |
6833 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6834 | <op> $treg,0($tempreg) | |
6835 | If there is a base register, we add it to $tempreg before | |
6836 | the <op>. If there is a constant, we stick it in the | |
6837 | <op> instruction. We don't handle constants larger than | |
6838 | 16 bits, because we have no way to load the upper 16 bits | |
6839 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6840 | in which we are not using $at). */ |
9c2799c2 | 6841 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6842 | expr1.X_add_number = offset_expr.X_add_number; |
6843 | offset_expr.X_add_number = 0; | |
6844 | if (expr1.X_add_number < -0x8000 | |
6845 | || expr1.X_add_number >= 0x8000) | |
6846 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6847 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6848 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6849 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6850 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6851 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6852 | mips_gp_register); | |
6853 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6854 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6855 | relax_switch (); |
67c0d1eb RS |
6856 | if (gpdelay) |
6857 | macro_build (NULL, "nop", ""); | |
6858 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6859 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6860 | load_delay_nop (); |
67c0d1eb RS |
6861 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6862 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6863 | relax_end (); |
6864 | ||
252b5132 | 6865 | if (breg != 0) |
67c0d1eb | 6866 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6867 | tempreg, tempreg, breg); |
67c0d1eb | 6868 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6869 | } |
0a44bf69 | 6870 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6871 | { |
f5040a92 AO |
6872 | /* If this is a reference to an external symbol, we want |
6873 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6874 | add $tempreg,$tempreg,$gp | |
6875 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6876 | <op> $treg,<ofst>($tempreg) | |
6877 | Otherwise, for local symbols, we want: | |
6878 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6879 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6880 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6881 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6882 | offset_expr.X_add_number = 0; |
6883 | if (expr1.X_add_number < -0x8000 | |
6884 | || expr1.X_add_number >= 0x8000) | |
6885 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6886 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6887 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6888 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6889 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6890 | mips_gp_register); | |
6891 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6892 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6893 | if (breg != 0) |
67c0d1eb | 6894 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6895 | tempreg, tempreg, breg); |
67c0d1eb | 6896 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6897 | |
4d7206a2 | 6898 | relax_switch (); |
f5040a92 | 6899 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6900 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6901 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6902 | if (breg != 0) |
67c0d1eb | 6903 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6904 | tempreg, tempreg, breg); |
67c0d1eb | 6905 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6906 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6907 | relax_end (); |
f5040a92 | 6908 | } |
252b5132 RH |
6909 | else |
6910 | abort (); | |
6911 | ||
252b5132 RH |
6912 | break; |
6913 | ||
6914 | case M_LI: | |
6915 | case M_LI_S: | |
67c0d1eb | 6916 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6917 | break; |
252b5132 RH |
6918 | |
6919 | case M_DLI: | |
67c0d1eb | 6920 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6921 | break; |
252b5132 RH |
6922 | |
6923 | case M_LI_SS: | |
6924 | if (imm_expr.X_op == O_constant) | |
6925 | { | |
8fc2e39e | 6926 | used_at = 1; |
67c0d1eb RS |
6927 | load_register (AT, &imm_expr, 0); |
6928 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6929 | break; |
6930 | } | |
6931 | else | |
6932 | { | |
9c2799c2 | 6933 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
6934 | && strcmp (segment_name (S_GET_SEGMENT |
6935 | (offset_expr.X_add_symbol)), | |
6936 | ".lit4") == 0 | |
6937 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6938 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6939 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6940 | break; |
252b5132 RH |
6941 | } |
6942 | ||
6943 | case M_LI_D: | |
ca4e0257 RS |
6944 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6945 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6946 | order 32 bits of the value and the low order 32 bits are either | |
6947 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6948 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6949 | { | |
ca4e0257 | 6950 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6951 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6952 | else |
6953 | { | |
6954 | int hreg, lreg; | |
6955 | ||
6956 | if (target_big_endian) | |
6957 | { | |
6958 | hreg = treg; | |
6959 | lreg = treg + 1; | |
6960 | } | |
6961 | else | |
6962 | { | |
6963 | hreg = treg + 1; | |
6964 | lreg = treg; | |
6965 | } | |
6966 | ||
6967 | if (hreg <= 31) | |
67c0d1eb | 6968 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6969 | if (lreg <= 31) |
6970 | { | |
6971 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6972 | move_register (lreg, 0); |
252b5132 RH |
6973 | else |
6974 | { | |
9c2799c2 | 6975 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6976 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6977 | } |
6978 | } | |
6979 | } | |
8fc2e39e | 6980 | break; |
252b5132 RH |
6981 | } |
6982 | ||
6983 | /* We know that sym is in the .rdata section. First we get the | |
6984 | upper 16 bits of the address. */ | |
6985 | if (mips_pic == NO_PIC) | |
6986 | { | |
67c0d1eb | 6987 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6988 | used_at = 1; |
252b5132 | 6989 | } |
0a44bf69 | 6990 | else |
252b5132 | 6991 | { |
67c0d1eb RS |
6992 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6993 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6994 | used_at = 1; |
252b5132 | 6995 | } |
bdaaa2e1 | 6996 | |
252b5132 | 6997 | /* Now we load the register(s). */ |
ca4e0257 | 6998 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6999 | { |
7000 | used_at = 1; | |
7001 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
7002 | } | |
252b5132 RH |
7003 | else |
7004 | { | |
8fc2e39e | 7005 | used_at = 1; |
67c0d1eb | 7006 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 7007 | if (treg != RA) |
252b5132 RH |
7008 | { |
7009 | /* FIXME: How in the world do we deal with the possible | |
7010 | overflow here? */ | |
7011 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7012 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 7013 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
7014 | } |
7015 | } | |
252b5132 RH |
7016 | break; |
7017 | ||
7018 | case M_LI_DD: | |
ca4e0257 RS |
7019 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
7020 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
7021 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
7022 | the value and the low order 32 bits are either zero or in | |
7023 | OFFSET_EXPR. */ | |
252b5132 RH |
7024 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7025 | { | |
8fc2e39e | 7026 | used_at = 1; |
67c0d1eb | 7027 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
7028 | if (HAVE_64BIT_FPRS) |
7029 | { | |
9c2799c2 | 7030 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7031 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7032 | } |
252b5132 RH |
7033 | else |
7034 | { | |
67c0d1eb | 7035 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7036 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7037 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7038 | else |
7039 | { | |
9c2799c2 | 7040 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7041 | load_register (AT, &offset_expr, 0); |
7042 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7043 | } |
7044 | } | |
7045 | break; | |
7046 | } | |
7047 | ||
9c2799c2 | 7048 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7049 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7050 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7051 | if (strcmp (s, ".lit8") == 0) | |
7052 | { | |
e7af610e | 7053 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7054 | { |
67c0d1eb | 7055 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7056 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7057 | break; |
252b5132 | 7058 | } |
c9914766 | 7059 | breg = mips_gp_register; |
252b5132 RH |
7060 | r = BFD_RELOC_MIPS_LITERAL; |
7061 | goto dob; | |
7062 | } | |
7063 | else | |
7064 | { | |
9c2799c2 | 7065 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7066 | used_at = 1; |
0a44bf69 | 7067 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7068 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7069 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7070 | else |
7071 | { | |
7072 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7073 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7074 | } |
bdaaa2e1 | 7075 | |
e7af610e | 7076 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7077 | { |
67c0d1eb RS |
7078 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7079 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7080 | break; |
7081 | } | |
7082 | breg = AT; | |
7083 | r = BFD_RELOC_LO16; | |
7084 | goto dob; | |
7085 | } | |
7086 | ||
7087 | case M_L_DOB: | |
252b5132 RH |
7088 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7089 | to adjust when loading from memory. */ | |
7090 | r = BFD_RELOC_LO16; | |
7091 | dob: | |
9c2799c2 | 7092 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7093 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7094 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7095 | /* FIXME: A possible overflow which I don't know how to deal |
7096 | with. */ | |
7097 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7098 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7099 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7100 | break; |
7101 | ||
c4a68bea MR |
7102 | case M_S_DOB: |
7103 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7104 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7105 | to adjust when storing to memory. */ | |
7106 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7107 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7108 | offset_expr.X_add_number += 4; | |
7109 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7110 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7111 | break; | |
7112 | ||
252b5132 RH |
7113 | case M_L_DAB: |
7114 | /* | |
7115 | * The MIPS assembler seems to check for X_add_number not | |
7116 | * being double aligned and generating: | |
7117 | * lui at,%hi(foo+1) | |
7118 | * addu at,at,v1 | |
7119 | * addiu at,at,%lo(foo+1) | |
7120 | * lwc1 f2,0(at) | |
7121 | * lwc1 f3,4(at) | |
7122 | * But, the resulting address is the same after relocation so why | |
7123 | * generate the extra instruction? | |
7124 | */ | |
bdaaa2e1 | 7125 | /* Itbl support may require additional care here. */ |
252b5132 | 7126 | coproc = 1; |
e7af610e | 7127 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7128 | { |
7129 | s = "ldc1"; | |
7130 | goto ld; | |
7131 | } | |
7132 | ||
7133 | s = "lwc1"; | |
7134 | fmt = "T,o(b)"; | |
7135 | goto ldd_std; | |
7136 | ||
7137 | case M_S_DAB: | |
e7af610e | 7138 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7139 | { |
7140 | s = "sdc1"; | |
7141 | goto st; | |
7142 | } | |
7143 | ||
7144 | s = "swc1"; | |
7145 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7146 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7147 | coproc = 1; |
7148 | goto ldd_std; | |
7149 | ||
7150 | case M_LD_AB: | |
ca4e0257 | 7151 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7152 | { |
7153 | s = "ld"; | |
7154 | goto ld; | |
7155 | } | |
7156 | ||
7157 | s = "lw"; | |
7158 | fmt = "t,o(b)"; | |
7159 | goto ldd_std; | |
7160 | ||
7161 | case M_SD_AB: | |
ca4e0257 | 7162 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7163 | { |
7164 | s = "sd"; | |
7165 | goto st; | |
7166 | } | |
7167 | ||
7168 | s = "sw"; | |
7169 | fmt = "t,o(b)"; | |
7170 | ||
7171 | ldd_std: | |
7172 | if (offset_expr.X_op != O_symbol | |
7173 | && offset_expr.X_op != O_constant) | |
7174 | { | |
f71d0d44 | 7175 | as_bad (_("Expression too complex")); |
252b5132 RH |
7176 | offset_expr.X_op = O_constant; |
7177 | } | |
7178 | ||
2051e8c4 MR |
7179 | if (HAVE_32BIT_ADDRESSES |
7180 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7181 | { |
7182 | char value [32]; | |
7183 | ||
7184 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7185 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7186 | } |
2051e8c4 | 7187 | |
252b5132 RH |
7188 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7189 | to adjust when loading from memory. We set coproc if we must | |
7190 | load $fn+1 first. */ | |
bdaaa2e1 | 7191 | /* Itbl support may require additional care here. */ |
90ecf173 | 7192 | if (!target_big_endian) |
252b5132 RH |
7193 | coproc = 0; |
7194 | ||
90ecf173 | 7195 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7196 | { |
7197 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7198 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7199 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7200 | If we have a base register, we use this |
7201 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7202 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7203 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7204 | If this is not a GP relative symbol, we want |
7205 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7206 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7207 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7208 | If there is a base register, we add it to $at after the | |
7209 | lui instruction. If there is a constant, we always use | |
7210 | the last case. */ | |
39a59cf8 MR |
7211 | if (offset_expr.X_op == O_symbol |
7212 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7213 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7214 | { |
4d7206a2 | 7215 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7216 | if (breg == 0) |
7217 | { | |
c9914766 | 7218 | tempreg = mips_gp_register; |
252b5132 RH |
7219 | } |
7220 | else | |
7221 | { | |
67c0d1eb | 7222 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7223 | AT, breg, mips_gp_register); |
252b5132 | 7224 | tempreg = AT; |
252b5132 RH |
7225 | used_at = 1; |
7226 | } | |
7227 | ||
beae10d5 | 7228 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7229 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7230 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7231 | offset_expr.X_add_number += 4; |
7232 | ||
7233 | /* Set mips_optimize to 2 to avoid inserting an | |
7234 | undesired nop. */ | |
7235 | hold_mips_optimize = mips_optimize; | |
7236 | mips_optimize = 2; | |
beae10d5 | 7237 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7238 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7239 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7240 | mips_optimize = hold_mips_optimize; |
7241 | ||
4d7206a2 | 7242 | relax_switch (); |
252b5132 | 7243 | |
0970e49e | 7244 | offset_expr.X_add_number -= 4; |
252b5132 | 7245 | } |
8fc2e39e | 7246 | used_at = 1; |
67c0d1eb | 7247 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7248 | if (breg != 0) |
67c0d1eb | 7249 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7250 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7251 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7252 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7253 | /* FIXME: How do we handle overflow here? */ |
7254 | offset_expr.X_add_number += 4; | |
beae10d5 | 7255 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7256 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7257 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7258 | if (mips_relax.sequence) |
7259 | relax_end (); | |
bdaaa2e1 | 7260 | } |
0a44bf69 | 7261 | else if (!mips_big_got) |
252b5132 | 7262 | { |
252b5132 RH |
7263 | /* If this is a reference to an external symbol, we want |
7264 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7265 | nop | |
7266 | <op> $treg,0($at) | |
7267 | <op> $treg+1,4($at) | |
7268 | Otherwise we want | |
7269 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7270 | nop | |
7271 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7272 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7273 | If there is a base register we add it to $at before the | |
7274 | lwc1 instructions. If there is a constant we include it | |
7275 | in the lwc1 instructions. */ | |
7276 | used_at = 1; | |
7277 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7278 | if (expr1.X_add_number < -0x8000 |
7279 | || expr1.X_add_number >= 0x8000 - 4) | |
7280 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7281 | load_got_offset (AT, &offset_expr); |
269137b2 | 7282 | load_delay_nop (); |
252b5132 | 7283 | if (breg != 0) |
67c0d1eb | 7284 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7285 | |
7286 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7287 | nop. */ | |
7288 | hold_mips_optimize = mips_optimize; | |
7289 | mips_optimize = 2; | |
4d7206a2 | 7290 | |
beae10d5 | 7291 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7292 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7293 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7294 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7295 | expr1.X_add_number += 4; |
67c0d1eb RS |
7296 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7297 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7298 | relax_switch (); |
67c0d1eb RS |
7299 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7300 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7301 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7302 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7303 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7304 | relax_end (); |
252b5132 | 7305 | |
4d7206a2 | 7306 | mips_optimize = hold_mips_optimize; |
252b5132 | 7307 | } |
0a44bf69 | 7308 | else if (mips_big_got) |
252b5132 | 7309 | { |
67c0d1eb | 7310 | int gpdelay; |
252b5132 RH |
7311 | |
7312 | /* If this is a reference to an external symbol, we want | |
7313 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7314 | addu $at,$at,$gp | |
7315 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7316 | nop | |
7317 | <op> $treg,0($at) | |
7318 | <op> $treg+1,4($at) | |
7319 | Otherwise we want | |
7320 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7321 | nop | |
7322 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7323 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7324 | If there is a base register we add it to $at before the | |
7325 | lwc1 instructions. If there is a constant we include it | |
7326 | in the lwc1 instructions. */ | |
7327 | used_at = 1; | |
7328 | expr1.X_add_number = offset_expr.X_add_number; | |
7329 | offset_expr.X_add_number = 0; | |
7330 | if (expr1.X_add_number < -0x8000 | |
7331 | || expr1.X_add_number >= 0x8000 - 4) | |
7332 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7333 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7334 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7335 | macro_build (&offset_expr, "lui", "t,u", |
7336 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7337 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7338 | AT, AT, mips_gp_register); |
67c0d1eb | 7339 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7340 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7341 | load_delay_nop (); |
252b5132 | 7342 | if (breg != 0) |
67c0d1eb | 7343 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7344 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7345 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7346 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7347 | expr1.X_add_number += 4; |
7348 | ||
7349 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7350 | nop. */ | |
7351 | hold_mips_optimize = mips_optimize; | |
7352 | mips_optimize = 2; | |
beae10d5 | 7353 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7354 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7355 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7356 | mips_optimize = hold_mips_optimize; |
7357 | expr1.X_add_number -= 4; | |
7358 | ||
4d7206a2 RS |
7359 | relax_switch (); |
7360 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7361 | if (gpdelay) |
7362 | macro_build (NULL, "nop", ""); | |
7363 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7364 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7365 | load_delay_nop (); |
252b5132 | 7366 | if (breg != 0) |
67c0d1eb | 7367 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7368 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7369 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7370 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7371 | offset_expr.X_add_number += 4; |
252b5132 RH |
7372 | |
7373 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7374 | nop. */ | |
7375 | hold_mips_optimize = mips_optimize; | |
7376 | mips_optimize = 2; | |
beae10d5 | 7377 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7378 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7379 | BFD_RELOC_LO16, AT); | |
252b5132 | 7380 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7381 | relax_end (); |
252b5132 | 7382 | } |
252b5132 RH |
7383 | else |
7384 | abort (); | |
7385 | ||
252b5132 RH |
7386 | break; |
7387 | ||
7388 | case M_LD_OB: | |
704897fb | 7389 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7390 | goto sd_ob; |
7391 | case M_SD_OB: | |
704897fb | 7392 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7393 | sd_ob: |
4614d845 MR |
7394 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7395 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7396 | breg); | |
704897fb MR |
7397 | if (!HAVE_64BIT_GPRS) |
7398 | { | |
7399 | offset_expr.X_add_number += 4; | |
7400 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7401 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7402 | breg); | |
704897fb | 7403 | } |
8fc2e39e | 7404 | break; |
252b5132 RH |
7405 | |
7406 | /* New code added to support COPZ instructions. | |
7407 | This code builds table entries out of the macros in mip_opcodes. | |
7408 | R4000 uses interlocks to handle coproc delays. | |
7409 | Other chips (like the R3000) require nops to be inserted for delays. | |
7410 | ||
f72c8c98 | 7411 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7412 | In order to fill delay slots for non-interlocked chips, |
7413 | we must have a way to specify delays based on the coprocessor. | |
7414 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7415 | What are the side-effects of the cop instruction? | |
7416 | What cache support might we have and what are its effects? | |
7417 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7418 | What registers are read/set/modified? |
252b5132 RH |
7419 | |
7420 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7421 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7422 | |
7423 | case M_COP0: | |
7424 | s = "c0"; | |
7425 | goto copz; | |
7426 | case M_COP1: | |
7427 | s = "c1"; | |
7428 | goto copz; | |
7429 | case M_COP2: | |
7430 | s = "c2"; | |
7431 | goto copz; | |
7432 | case M_COP3: | |
7433 | s = "c3"; | |
7434 | copz: | |
b19e8a9b AN |
7435 | if (NO_ISA_COP (mips_opts.arch) |
7436 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7437 | { | |
7438 | as_bad (_("opcode not supported on this processor: %s"), | |
7439 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7440 | break; | |
7441 | } | |
7442 | ||
252b5132 RH |
7443 | /* For now we just do C (same as Cz). The parameter will be |
7444 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7445 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7446 | break; |
252b5132 | 7447 | |
ea1fb5dc | 7448 | case M_MOVE: |
67c0d1eb | 7449 | move_register (dreg, sreg); |
8fc2e39e | 7450 | break; |
ea1fb5dc | 7451 | |
252b5132 RH |
7452 | case M_DMUL: |
7453 | dbl = 1; | |
7454 | case M_MUL: | |
67c0d1eb RS |
7455 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7456 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7457 | break; |
252b5132 RH |
7458 | |
7459 | case M_DMUL_I: | |
7460 | dbl = 1; | |
7461 | case M_MUL_I: | |
7462 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7463 | not trying to be that fancy. GCC should do this for us | |
7464 | anyway. */ | |
8fc2e39e | 7465 | used_at = 1; |
67c0d1eb RS |
7466 | load_register (AT, &imm_expr, dbl); |
7467 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7468 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7469 | break; |
7470 | ||
7471 | case M_DMULO_I: | |
7472 | dbl = 1; | |
7473 | case M_MULO_I: | |
7474 | imm = 1; | |
7475 | goto do_mulo; | |
7476 | ||
7477 | case M_DMULO: | |
7478 | dbl = 1; | |
7479 | case M_MULO: | |
7480 | do_mulo: | |
7d10b47d | 7481 | start_noreorder (); |
8fc2e39e | 7482 | used_at = 1; |
252b5132 | 7483 | if (imm) |
67c0d1eb RS |
7484 | load_register (AT, &imm_expr, dbl); |
7485 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7486 | macro_build (NULL, "mflo", "d", dreg); | |
7487 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7488 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7489 | if (mips_trap) |
67c0d1eb | 7490 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7491 | else |
7492 | { | |
7493 | expr1.X_add_number = 8; | |
67c0d1eb | 7494 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7495 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7496 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7497 | } |
7d10b47d | 7498 | end_noreorder (); |
67c0d1eb | 7499 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7500 | break; |
7501 | ||
7502 | case M_DMULOU_I: | |
7503 | dbl = 1; | |
7504 | case M_MULOU_I: | |
7505 | imm = 1; | |
7506 | goto do_mulou; | |
7507 | ||
7508 | case M_DMULOU: | |
7509 | dbl = 1; | |
7510 | case M_MULOU: | |
7511 | do_mulou: | |
7d10b47d | 7512 | start_noreorder (); |
8fc2e39e | 7513 | used_at = 1; |
252b5132 | 7514 | if (imm) |
67c0d1eb RS |
7515 | load_register (AT, &imm_expr, dbl); |
7516 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7517 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7518 | macro_build (NULL, "mfhi", "d", AT); |
7519 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7520 | if (mips_trap) |
c80c840e | 7521 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7522 | else |
7523 | { | |
7524 | expr1.X_add_number = 8; | |
c80c840e | 7525 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7526 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7527 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7528 | } |
7d10b47d | 7529 | end_noreorder (); |
252b5132 RH |
7530 | break; |
7531 | ||
771c7ce4 | 7532 | case M_DROL: |
fef14a42 | 7533 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7534 | { |
7535 | if (dreg == sreg) | |
7536 | { | |
7537 | tempreg = AT; | |
7538 | used_at = 1; | |
7539 | } | |
7540 | else | |
7541 | { | |
7542 | tempreg = dreg; | |
82dd0097 | 7543 | } |
67c0d1eb RS |
7544 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7545 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7546 | break; |
82dd0097 | 7547 | } |
8fc2e39e | 7548 | used_at = 1; |
c80c840e | 7549 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7550 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7551 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7552 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7553 | break; |
7554 | ||
252b5132 | 7555 | case M_ROL: |
fef14a42 | 7556 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7557 | { |
7558 | if (dreg == sreg) | |
7559 | { | |
7560 | tempreg = AT; | |
7561 | used_at = 1; | |
7562 | } | |
7563 | else | |
7564 | { | |
7565 | tempreg = dreg; | |
82dd0097 | 7566 | } |
67c0d1eb RS |
7567 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7568 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7569 | break; |
82dd0097 | 7570 | } |
8fc2e39e | 7571 | used_at = 1; |
c80c840e | 7572 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7573 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7574 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7575 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7576 | break; |
7577 | ||
771c7ce4 TS |
7578 | case M_DROL_I: |
7579 | { | |
7580 | unsigned int rot; | |
91d6fa6a NC |
7581 | char *l; |
7582 | char *rr; | |
771c7ce4 TS |
7583 | |
7584 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7585 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7586 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7587 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7588 | { |
7589 | rot = (64 - rot) & 0x3f; | |
7590 | if (rot >= 32) | |
67c0d1eb | 7591 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7592 | else |
67c0d1eb | 7593 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7594 | break; |
60b63b72 | 7595 | } |
483fc7cd | 7596 | if (rot == 0) |
483fc7cd | 7597 | { |
67c0d1eb | 7598 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7599 | break; |
483fc7cd | 7600 | } |
82dd0097 | 7601 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7602 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7603 | rot &= 0x1f; |
8fc2e39e | 7604 | used_at = 1; |
67c0d1eb | 7605 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7606 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7607 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7608 | } |
7609 | break; | |
7610 | ||
252b5132 | 7611 | case M_ROL_I: |
771c7ce4 TS |
7612 | { |
7613 | unsigned int rot; | |
7614 | ||
7615 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7616 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7617 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7618 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7619 | { |
67c0d1eb | 7620 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7621 | break; |
60b63b72 | 7622 | } |
483fc7cd | 7623 | if (rot == 0) |
483fc7cd | 7624 | { |
67c0d1eb | 7625 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7626 | break; |
483fc7cd | 7627 | } |
8fc2e39e | 7628 | used_at = 1; |
67c0d1eb RS |
7629 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7630 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7631 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7632 | } |
7633 | break; | |
7634 | ||
7635 | case M_DROR: | |
fef14a42 | 7636 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7637 | { |
67c0d1eb | 7638 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7639 | break; |
82dd0097 | 7640 | } |
8fc2e39e | 7641 | used_at = 1; |
c80c840e | 7642 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7643 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7644 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7645 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7646 | break; |
7647 | ||
7648 | case M_ROR: | |
fef14a42 | 7649 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7650 | { |
67c0d1eb | 7651 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7652 | break; |
82dd0097 | 7653 | } |
8fc2e39e | 7654 | used_at = 1; |
c80c840e | 7655 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7656 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7657 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7658 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7659 | break; |
7660 | ||
771c7ce4 TS |
7661 | case M_DROR_I: |
7662 | { | |
7663 | unsigned int rot; | |
91d6fa6a NC |
7664 | char *l; |
7665 | char *rr; | |
771c7ce4 TS |
7666 | |
7667 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7668 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7669 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7670 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7671 | { |
7672 | if (rot >= 32) | |
67c0d1eb | 7673 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7674 | else |
67c0d1eb | 7675 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7676 | break; |
82dd0097 | 7677 | } |
483fc7cd | 7678 | if (rot == 0) |
483fc7cd | 7679 | { |
67c0d1eb | 7680 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7681 | break; |
483fc7cd | 7682 | } |
91d6fa6a | 7683 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7684 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7685 | rot &= 0x1f; | |
8fc2e39e | 7686 | used_at = 1; |
91d6fa6a | 7687 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7688 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7689 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7690 | } |
7691 | break; | |
7692 | ||
252b5132 | 7693 | case M_ROR_I: |
771c7ce4 TS |
7694 | { |
7695 | unsigned int rot; | |
7696 | ||
7697 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7698 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7699 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7700 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7701 | { |
67c0d1eb | 7702 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7703 | break; |
82dd0097 | 7704 | } |
483fc7cd | 7705 | if (rot == 0) |
483fc7cd | 7706 | { |
67c0d1eb | 7707 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7708 | break; |
483fc7cd | 7709 | } |
8fc2e39e | 7710 | used_at = 1; |
67c0d1eb RS |
7711 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7712 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7713 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7714 | } |
252b5132 RH |
7715 | break; |
7716 | ||
252b5132 RH |
7717 | case M_SEQ: |
7718 | if (sreg == 0) | |
67c0d1eb | 7719 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7720 | else if (treg == 0) |
67c0d1eb | 7721 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7722 | else |
7723 | { | |
67c0d1eb RS |
7724 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7725 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7726 | } |
8fc2e39e | 7727 | break; |
252b5132 RH |
7728 | |
7729 | case M_SEQ_I: | |
7730 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7731 | { | |
67c0d1eb | 7732 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7733 | break; |
252b5132 RH |
7734 | } |
7735 | if (sreg == 0) | |
7736 | { | |
7737 | as_warn (_("Instruction %s: result is always false"), | |
7738 | ip->insn_mo->name); | |
67c0d1eb | 7739 | move_register (dreg, 0); |
8fc2e39e | 7740 | break; |
252b5132 | 7741 | } |
dd3cbb7e NC |
7742 | if (CPU_HAS_SEQ (mips_opts.arch) |
7743 | && -512 <= imm_expr.X_add_number | |
7744 | && imm_expr.X_add_number < 512) | |
7745 | { | |
7746 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7747 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7748 | break; |
7749 | } | |
252b5132 RH |
7750 | if (imm_expr.X_op == O_constant |
7751 | && imm_expr.X_add_number >= 0 | |
7752 | && imm_expr.X_add_number < 0x10000) | |
7753 | { | |
67c0d1eb | 7754 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7755 | } |
7756 | else if (imm_expr.X_op == O_constant | |
7757 | && imm_expr.X_add_number > -0x8000 | |
7758 | && imm_expr.X_add_number < 0) | |
7759 | { | |
7760 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7761 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7762 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7763 | } |
dd3cbb7e NC |
7764 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7765 | { | |
7766 | used_at = 1; | |
7767 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7768 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7769 | break; | |
7770 | } | |
252b5132 RH |
7771 | else |
7772 | { | |
67c0d1eb RS |
7773 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7774 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7775 | used_at = 1; |
7776 | } | |
67c0d1eb | 7777 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7778 | break; |
252b5132 RH |
7779 | |
7780 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7781 | s = "slt"; | |
7782 | goto sge; | |
7783 | case M_SGEU: | |
7784 | s = "sltu"; | |
7785 | sge: | |
67c0d1eb RS |
7786 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7787 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7788 | break; |
252b5132 RH |
7789 | |
7790 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7791 | case M_SGEU_I: | |
7792 | if (imm_expr.X_op == O_constant | |
7793 | && imm_expr.X_add_number >= -0x8000 | |
7794 | && imm_expr.X_add_number < 0x8000) | |
7795 | { | |
67c0d1eb RS |
7796 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7797 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7798 | } |
7799 | else | |
7800 | { | |
67c0d1eb RS |
7801 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7802 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7803 | dreg, sreg, AT); | |
252b5132 RH |
7804 | used_at = 1; |
7805 | } | |
67c0d1eb | 7806 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7807 | break; |
252b5132 RH |
7808 | |
7809 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7810 | s = "slt"; | |
7811 | goto sgt; | |
7812 | case M_SGTU: | |
7813 | s = "sltu"; | |
7814 | sgt: | |
67c0d1eb | 7815 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7816 | break; |
252b5132 RH |
7817 | |
7818 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7819 | s = "slt"; | |
7820 | goto sgti; | |
7821 | case M_SGTU_I: | |
7822 | s = "sltu"; | |
7823 | sgti: | |
8fc2e39e | 7824 | used_at = 1; |
67c0d1eb RS |
7825 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7826 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7827 | break; |
7828 | ||
2396cfb9 | 7829 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7830 | s = "slt"; |
7831 | goto sle; | |
7832 | case M_SLEU: | |
7833 | s = "sltu"; | |
7834 | sle: | |
67c0d1eb RS |
7835 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7836 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7837 | break; |
252b5132 | 7838 | |
2396cfb9 | 7839 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7840 | s = "slt"; |
7841 | goto slei; | |
7842 | case M_SLEU_I: | |
7843 | s = "sltu"; | |
7844 | slei: | |
8fc2e39e | 7845 | used_at = 1; |
67c0d1eb RS |
7846 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7847 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7848 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7849 | break; |
7850 | ||
7851 | case M_SLT_I: | |
7852 | if (imm_expr.X_op == O_constant | |
7853 | && imm_expr.X_add_number >= -0x8000 | |
7854 | && imm_expr.X_add_number < 0x8000) | |
7855 | { | |
67c0d1eb | 7856 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7857 | break; |
252b5132 | 7858 | } |
8fc2e39e | 7859 | used_at = 1; |
67c0d1eb RS |
7860 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7861 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7862 | break; |
7863 | ||
7864 | case M_SLTU_I: | |
7865 | if (imm_expr.X_op == O_constant | |
7866 | && imm_expr.X_add_number >= -0x8000 | |
7867 | && imm_expr.X_add_number < 0x8000) | |
7868 | { | |
67c0d1eb | 7869 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7870 | BFD_RELOC_LO16); |
8fc2e39e | 7871 | break; |
252b5132 | 7872 | } |
8fc2e39e | 7873 | used_at = 1; |
67c0d1eb RS |
7874 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7875 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7876 | break; |
7877 | ||
7878 | case M_SNE: | |
7879 | if (sreg == 0) | |
67c0d1eb | 7880 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7881 | else if (treg == 0) |
67c0d1eb | 7882 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7883 | else |
7884 | { | |
67c0d1eb RS |
7885 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7886 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7887 | } |
8fc2e39e | 7888 | break; |
252b5132 RH |
7889 | |
7890 | case M_SNE_I: | |
7891 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7892 | { | |
67c0d1eb | 7893 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7894 | break; |
252b5132 RH |
7895 | } |
7896 | if (sreg == 0) | |
7897 | { | |
7898 | as_warn (_("Instruction %s: result is always true"), | |
7899 | ip->insn_mo->name); | |
67c0d1eb RS |
7900 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7901 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7902 | break; |
252b5132 | 7903 | } |
dd3cbb7e NC |
7904 | if (CPU_HAS_SEQ (mips_opts.arch) |
7905 | && -512 <= imm_expr.X_add_number | |
7906 | && imm_expr.X_add_number < 512) | |
7907 | { | |
7908 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7909 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7910 | break; |
7911 | } | |
252b5132 RH |
7912 | if (imm_expr.X_op == O_constant |
7913 | && imm_expr.X_add_number >= 0 | |
7914 | && imm_expr.X_add_number < 0x10000) | |
7915 | { | |
67c0d1eb | 7916 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7917 | } |
7918 | else if (imm_expr.X_op == O_constant | |
7919 | && imm_expr.X_add_number > -0x8000 | |
7920 | && imm_expr.X_add_number < 0) | |
7921 | { | |
7922 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7923 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7924 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7925 | } |
dd3cbb7e NC |
7926 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7927 | { | |
7928 | used_at = 1; | |
7929 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7930 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7931 | break; | |
7932 | } | |
252b5132 RH |
7933 | else |
7934 | { | |
67c0d1eb RS |
7935 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7936 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7937 | used_at = 1; |
7938 | } | |
67c0d1eb | 7939 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7940 | break; |
252b5132 RH |
7941 | |
7942 | case M_DSUB_I: | |
7943 | dbl = 1; | |
7944 | case M_SUB_I: | |
7945 | if (imm_expr.X_op == O_constant | |
7946 | && imm_expr.X_add_number > -0x8000 | |
7947 | && imm_expr.X_add_number <= 0x8000) | |
7948 | { | |
7949 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7950 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7951 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7952 | break; |
252b5132 | 7953 | } |
8fc2e39e | 7954 | used_at = 1; |
67c0d1eb RS |
7955 | load_register (AT, &imm_expr, dbl); |
7956 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7957 | break; |
7958 | ||
7959 | case M_DSUBU_I: | |
7960 | dbl = 1; | |
7961 | case M_SUBU_I: | |
7962 | if (imm_expr.X_op == O_constant | |
7963 | && imm_expr.X_add_number > -0x8000 | |
7964 | && imm_expr.X_add_number <= 0x8000) | |
7965 | { | |
7966 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7967 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7968 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7969 | break; |
252b5132 | 7970 | } |
8fc2e39e | 7971 | used_at = 1; |
67c0d1eb RS |
7972 | load_register (AT, &imm_expr, dbl); |
7973 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7974 | break; |
7975 | ||
7976 | case M_TEQ_I: | |
7977 | s = "teq"; | |
7978 | goto trap; | |
7979 | case M_TGE_I: | |
7980 | s = "tge"; | |
7981 | goto trap; | |
7982 | case M_TGEU_I: | |
7983 | s = "tgeu"; | |
7984 | goto trap; | |
7985 | case M_TLT_I: | |
7986 | s = "tlt"; | |
7987 | goto trap; | |
7988 | case M_TLTU_I: | |
7989 | s = "tltu"; | |
7990 | goto trap; | |
7991 | case M_TNE_I: | |
7992 | s = "tne"; | |
7993 | trap: | |
8fc2e39e | 7994 | used_at = 1; |
67c0d1eb RS |
7995 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7996 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7997 | break; |
7998 | ||
252b5132 | 7999 | case M_TRUNCWS: |
43841e91 | 8000 | case M_TRUNCWD: |
9c2799c2 | 8001 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8002 | used_at = 1; |
252b5132 RH |
8003 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8004 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8005 | ||
8006 | /* | |
8007 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8008 | * or is there a reason for it? | |
8009 | */ | |
7d10b47d | 8010 | start_noreorder (); |
67c0d1eb RS |
8011 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8012 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8013 | macro_build (NULL, "nop", ""); | |
252b5132 | 8014 | expr1.X_add_number = 3; |
67c0d1eb | 8015 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8016 | expr1.X_add_number = 2; |
67c0d1eb RS |
8017 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8018 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8019 | macro_build (NULL, "nop", ""); | |
8020 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8021 | dreg, sreg); | |
8022 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8023 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8024 | end_noreorder (); |
252b5132 RH |
8025 | break; |
8026 | ||
8027 | case M_ULH: | |
8028 | s = "lb"; | |
8029 | goto ulh; | |
8030 | case M_ULHU: | |
8031 | s = "lbu"; | |
8032 | ulh: | |
8fc2e39e | 8033 | used_at = 1; |
252b5132 | 8034 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8035 | as_bad (_("Operand overflow")); |
90ecf173 | 8036 | if (!target_big_endian) |
f9419b05 | 8037 | ++offset_expr.X_add_number; |
67c0d1eb | 8038 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8039 | if (!target_big_endian) |
f9419b05 | 8040 | --offset_expr.X_add_number; |
252b5132 | 8041 | else |
f9419b05 | 8042 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8043 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8044 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8045 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8046 | break; |
8047 | ||
8048 | case M_ULD: | |
8049 | s = "ldl"; | |
8050 | s2 = "ldr"; | |
8051 | off = 7; | |
8052 | goto ulw; | |
8053 | case M_ULW: | |
8054 | s = "lwl"; | |
8055 | s2 = "lwr"; | |
8056 | off = 3; | |
8057 | ulw: | |
8058 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8059 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8060 | if (treg != breg) |
8061 | tempreg = treg; | |
8062 | else | |
8fc2e39e TS |
8063 | { |
8064 | used_at = 1; | |
8065 | tempreg = AT; | |
8066 | } | |
90ecf173 | 8067 | if (!target_big_endian) |
252b5132 | 8068 | offset_expr.X_add_number += off; |
67c0d1eb | 8069 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8070 | if (!target_big_endian) |
252b5132 RH |
8071 | offset_expr.X_add_number -= off; |
8072 | else | |
8073 | offset_expr.X_add_number += off; | |
67c0d1eb | 8074 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8075 | |
90ecf173 | 8076 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8077 | if (treg == tempreg) |
8fc2e39e | 8078 | break; |
af22f5b2 | 8079 | /* Protect second load's delay slot. */ |
017315e4 | 8080 | load_delay_nop (); |
67c0d1eb | 8081 | move_register (treg, tempreg); |
af22f5b2 | 8082 | break; |
252b5132 RH |
8083 | |
8084 | case M_ULD_A: | |
8085 | s = "ldl"; | |
8086 | s2 = "ldr"; | |
8087 | off = 7; | |
8088 | goto ulwa; | |
8089 | case M_ULW_A: | |
8090 | s = "lwl"; | |
8091 | s2 = "lwr"; | |
8092 | off = 3; | |
8093 | ulwa: | |
d6bc6245 | 8094 | used_at = 1; |
67c0d1eb | 8095 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8096 | if (breg != 0) |
67c0d1eb | 8097 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8098 | if (!target_big_endian) |
252b5132 RH |
8099 | expr1.X_add_number = off; |
8100 | else | |
8101 | expr1.X_add_number = 0; | |
67c0d1eb | 8102 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8103 | if (!target_big_endian) |
252b5132 RH |
8104 | expr1.X_add_number = 0; |
8105 | else | |
8106 | expr1.X_add_number = off; | |
67c0d1eb | 8107 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8108 | break; |
8109 | ||
8110 | case M_ULH_A: | |
8111 | case M_ULHU_A: | |
d6bc6245 | 8112 | used_at = 1; |
67c0d1eb | 8113 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8114 | if (breg != 0) |
67c0d1eb | 8115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8116 | if (target_big_endian) |
8117 | expr1.X_add_number = 0; | |
67c0d1eb | 8118 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8119 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8120 | if (target_big_endian) |
8121 | expr1.X_add_number = 1; | |
8122 | else | |
8123 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8124 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8125 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8126 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8127 | break; |
8128 | ||
8129 | case M_USH: | |
8fc2e39e | 8130 | used_at = 1; |
252b5132 | 8131 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8132 | as_bad (_("Operand overflow")); |
252b5132 | 8133 | if (target_big_endian) |
f9419b05 | 8134 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8135 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8136 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8137 | if (target_big_endian) |
f9419b05 | 8138 | --offset_expr.X_add_number; |
252b5132 | 8139 | else |
f9419b05 | 8140 | ++offset_expr.X_add_number; |
67c0d1eb | 8141 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8142 | break; |
8143 | ||
8144 | case M_USD: | |
8145 | s = "sdl"; | |
8146 | s2 = "sdr"; | |
8147 | off = 7; | |
8148 | goto usw; | |
8149 | case M_USW: | |
8150 | s = "swl"; | |
8151 | s2 = "swr"; | |
8152 | off = 3; | |
8153 | usw: | |
8154 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8155 | as_bad (_("Operand overflow")); |
90ecf173 | 8156 | if (!target_big_endian) |
252b5132 | 8157 | offset_expr.X_add_number += off; |
67c0d1eb | 8158 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8159 | if (!target_big_endian) |
252b5132 RH |
8160 | offset_expr.X_add_number -= off; |
8161 | else | |
8162 | offset_expr.X_add_number += off; | |
67c0d1eb | 8163 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8164 | break; |
252b5132 RH |
8165 | |
8166 | case M_USD_A: | |
8167 | s = "sdl"; | |
8168 | s2 = "sdr"; | |
8169 | off = 7; | |
8170 | goto uswa; | |
8171 | case M_USW_A: | |
8172 | s = "swl"; | |
8173 | s2 = "swr"; | |
8174 | off = 3; | |
8175 | uswa: | |
d6bc6245 | 8176 | used_at = 1; |
67c0d1eb | 8177 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8178 | if (breg != 0) |
67c0d1eb | 8179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8180 | if (!target_big_endian) |
252b5132 RH |
8181 | expr1.X_add_number = off; |
8182 | else | |
8183 | expr1.X_add_number = 0; | |
67c0d1eb | 8184 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8185 | if (!target_big_endian) |
252b5132 RH |
8186 | expr1.X_add_number = 0; |
8187 | else | |
8188 | expr1.X_add_number = off; | |
67c0d1eb | 8189 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8190 | break; |
8191 | ||
8192 | case M_USH_A: | |
d6bc6245 | 8193 | used_at = 1; |
67c0d1eb | 8194 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8195 | if (breg != 0) |
67c0d1eb | 8196 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8197 | if (!target_big_endian) |
252b5132 | 8198 | expr1.X_add_number = 0; |
67c0d1eb RS |
8199 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8200 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8201 | if (!target_big_endian) |
252b5132 RH |
8202 | expr1.X_add_number = 1; |
8203 | else | |
8204 | expr1.X_add_number = 0; | |
67c0d1eb | 8205 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8206 | if (!target_big_endian) |
252b5132 RH |
8207 | expr1.X_add_number = 0; |
8208 | else | |
8209 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8210 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8211 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8212 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8213 | break; |
8214 | ||
8215 | default: | |
8216 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8217 | are added dynamically. */ |
252b5132 RH |
8218 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8219 | break; | |
8220 | } | |
741fe287 | 8221 | if (!mips_opts.at && used_at) |
8fc2e39e | 8222 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8223 | } |
8224 | ||
8225 | /* Implement macros in mips16 mode. */ | |
8226 | ||
8227 | static void | |
17a2f251 | 8228 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8229 | { |
8230 | int mask; | |
8231 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8232 | expressionS expr1; |
8233 | int dbl; | |
8234 | const char *s, *s2, *s3; | |
8235 | ||
8236 | mask = ip->insn_mo->mask; | |
8237 | ||
bf12938e RS |
8238 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8239 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8240 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8241 | |
252b5132 RH |
8242 | expr1.X_op = O_constant; |
8243 | expr1.X_op_symbol = NULL; | |
8244 | expr1.X_add_symbol = NULL; | |
8245 | expr1.X_add_number = 1; | |
8246 | ||
8247 | dbl = 0; | |
8248 | ||
8249 | switch (mask) | |
8250 | { | |
8251 | default: | |
8252 | internalError (); | |
8253 | ||
8254 | case M_DDIV_3: | |
8255 | dbl = 1; | |
8256 | case M_DIV_3: | |
8257 | s = "mflo"; | |
8258 | goto do_div3; | |
8259 | case M_DREM_3: | |
8260 | dbl = 1; | |
8261 | case M_REM_3: | |
8262 | s = "mfhi"; | |
8263 | do_div3: | |
7d10b47d | 8264 | start_noreorder (); |
67c0d1eb | 8265 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8266 | expr1.X_add_number = 2; |
67c0d1eb RS |
8267 | macro_build (&expr1, "bnez", "x,p", yreg); |
8268 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8269 | |
252b5132 RH |
8270 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8271 | since that causes an overflow. We should do that as well, | |
8272 | but I don't see how to do the comparisons without a temporary | |
8273 | register. */ | |
7d10b47d | 8274 | end_noreorder (); |
67c0d1eb | 8275 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8276 | break; |
8277 | ||
8278 | case M_DIVU_3: | |
8279 | s = "divu"; | |
8280 | s2 = "mflo"; | |
8281 | goto do_divu3; | |
8282 | case M_REMU_3: | |
8283 | s = "divu"; | |
8284 | s2 = "mfhi"; | |
8285 | goto do_divu3; | |
8286 | case M_DDIVU_3: | |
8287 | s = "ddivu"; | |
8288 | s2 = "mflo"; | |
8289 | goto do_divu3; | |
8290 | case M_DREMU_3: | |
8291 | s = "ddivu"; | |
8292 | s2 = "mfhi"; | |
8293 | do_divu3: | |
7d10b47d | 8294 | start_noreorder (); |
67c0d1eb | 8295 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8296 | expr1.X_add_number = 2; |
67c0d1eb RS |
8297 | macro_build (&expr1, "bnez", "x,p", yreg); |
8298 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8299 | end_noreorder (); |
67c0d1eb | 8300 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8301 | break; |
8302 | ||
8303 | case M_DMUL: | |
8304 | dbl = 1; | |
8305 | case M_MUL: | |
67c0d1eb RS |
8306 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8307 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8308 | break; |
252b5132 RH |
8309 | |
8310 | case M_DSUBU_I: | |
8311 | dbl = 1; | |
8312 | goto do_subu; | |
8313 | case M_SUBU_I: | |
8314 | do_subu: | |
8315 | if (imm_expr.X_op != O_constant) | |
8316 | as_bad (_("Unsupported large constant")); | |
8317 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8318 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8319 | break; |
8320 | ||
8321 | case M_SUBU_I_2: | |
8322 | if (imm_expr.X_op != O_constant) | |
8323 | as_bad (_("Unsupported large constant")); | |
8324 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8325 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8326 | break; |
8327 | ||
8328 | case M_DSUBU_I_2: | |
8329 | if (imm_expr.X_op != O_constant) | |
8330 | as_bad (_("Unsupported large constant")); | |
8331 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8332 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8333 | break; |
8334 | ||
8335 | case M_BEQ: | |
8336 | s = "cmp"; | |
8337 | s2 = "bteqz"; | |
8338 | goto do_branch; | |
8339 | case M_BNE: | |
8340 | s = "cmp"; | |
8341 | s2 = "btnez"; | |
8342 | goto do_branch; | |
8343 | case M_BLT: | |
8344 | s = "slt"; | |
8345 | s2 = "btnez"; | |
8346 | goto do_branch; | |
8347 | case M_BLTU: | |
8348 | s = "sltu"; | |
8349 | s2 = "btnez"; | |
8350 | goto do_branch; | |
8351 | case M_BLE: | |
8352 | s = "slt"; | |
8353 | s2 = "bteqz"; | |
8354 | goto do_reverse_branch; | |
8355 | case M_BLEU: | |
8356 | s = "sltu"; | |
8357 | s2 = "bteqz"; | |
8358 | goto do_reverse_branch; | |
8359 | case M_BGE: | |
8360 | s = "slt"; | |
8361 | s2 = "bteqz"; | |
8362 | goto do_branch; | |
8363 | case M_BGEU: | |
8364 | s = "sltu"; | |
8365 | s2 = "bteqz"; | |
8366 | goto do_branch; | |
8367 | case M_BGT: | |
8368 | s = "slt"; | |
8369 | s2 = "btnez"; | |
8370 | goto do_reverse_branch; | |
8371 | case M_BGTU: | |
8372 | s = "sltu"; | |
8373 | s2 = "btnez"; | |
8374 | ||
8375 | do_reverse_branch: | |
8376 | tmp = xreg; | |
8377 | xreg = yreg; | |
8378 | yreg = tmp; | |
8379 | ||
8380 | do_branch: | |
67c0d1eb RS |
8381 | macro_build (NULL, s, "x,y", xreg, yreg); |
8382 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8383 | break; |
8384 | ||
8385 | case M_BEQ_I: | |
8386 | s = "cmpi"; | |
8387 | s2 = "bteqz"; | |
8388 | s3 = "x,U"; | |
8389 | goto do_branch_i; | |
8390 | case M_BNE_I: | |
8391 | s = "cmpi"; | |
8392 | s2 = "btnez"; | |
8393 | s3 = "x,U"; | |
8394 | goto do_branch_i; | |
8395 | case M_BLT_I: | |
8396 | s = "slti"; | |
8397 | s2 = "btnez"; | |
8398 | s3 = "x,8"; | |
8399 | goto do_branch_i; | |
8400 | case M_BLTU_I: | |
8401 | s = "sltiu"; | |
8402 | s2 = "btnez"; | |
8403 | s3 = "x,8"; | |
8404 | goto do_branch_i; | |
8405 | case M_BLE_I: | |
8406 | s = "slti"; | |
8407 | s2 = "btnez"; | |
8408 | s3 = "x,8"; | |
8409 | goto do_addone_branch_i; | |
8410 | case M_BLEU_I: | |
8411 | s = "sltiu"; | |
8412 | s2 = "btnez"; | |
8413 | s3 = "x,8"; | |
8414 | goto do_addone_branch_i; | |
8415 | case M_BGE_I: | |
8416 | s = "slti"; | |
8417 | s2 = "bteqz"; | |
8418 | s3 = "x,8"; | |
8419 | goto do_branch_i; | |
8420 | case M_BGEU_I: | |
8421 | s = "sltiu"; | |
8422 | s2 = "bteqz"; | |
8423 | s3 = "x,8"; | |
8424 | goto do_branch_i; | |
8425 | case M_BGT_I: | |
8426 | s = "slti"; | |
8427 | s2 = "bteqz"; | |
8428 | s3 = "x,8"; | |
8429 | goto do_addone_branch_i; | |
8430 | case M_BGTU_I: | |
8431 | s = "sltiu"; | |
8432 | s2 = "bteqz"; | |
8433 | s3 = "x,8"; | |
8434 | ||
8435 | do_addone_branch_i: | |
8436 | if (imm_expr.X_op != O_constant) | |
8437 | as_bad (_("Unsupported large constant")); | |
8438 | ++imm_expr.X_add_number; | |
8439 | ||
8440 | do_branch_i: | |
67c0d1eb RS |
8441 | macro_build (&imm_expr, s, s3, xreg); |
8442 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8443 | break; |
8444 | ||
8445 | case M_ABS: | |
8446 | expr1.X_add_number = 0; | |
67c0d1eb | 8447 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8448 | if (xreg != yreg) |
67c0d1eb | 8449 | move_register (xreg, yreg); |
252b5132 | 8450 | expr1.X_add_number = 2; |
67c0d1eb RS |
8451 | macro_build (&expr1, "bteqz", "p"); |
8452 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8453 | } |
8454 | } | |
8455 | ||
8456 | /* For consistency checking, verify that all bits are specified either | |
8457 | by the match/mask part of the instruction definition, or by the | |
8458 | operand list. */ | |
8459 | static int | |
17a2f251 | 8460 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8461 | { |
8462 | const char *p = opc->args; | |
8463 | char c; | |
8464 | unsigned long used_bits = opc->mask; | |
8465 | ||
8466 | if ((used_bits & opc->match) != opc->match) | |
8467 | { | |
8468 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8469 | opc->name, opc->args); | |
8470 | return 0; | |
8471 | } | |
8472 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8473 | while (*p) | |
8474 | switch (c = *p++) | |
8475 | { | |
8476 | case ',': break; | |
8477 | case '(': break; | |
8478 | case ')': break; | |
af7ee8bf CD |
8479 | case '+': |
8480 | switch (c = *p++) | |
8481 | { | |
9bcd4f99 TS |
8482 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8483 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8484 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8485 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8486 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8487 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8488 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8489 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8490 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8491 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8492 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8493 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8494 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8495 | case 'I': break; | |
ef2e4d86 CF |
8496 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8497 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8498 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8499 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8500 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8501 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8502 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8503 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8504 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8505 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
8506 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
8507 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
8508 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
8509 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
8510 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 8511 | |
af7ee8bf CD |
8512 | default: |
8513 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8514 | c, opc->name, opc->args); | |
8515 | return 0; | |
8516 | } | |
8517 | break; | |
252b5132 RH |
8518 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8519 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8520 | case 'A': break; | |
4372b673 | 8521 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8522 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8523 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8524 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8525 | case 'F': break; | |
8526 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8527 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8528 | case 'I': break; |
e972090a | 8529 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8530 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8531 | case 'L': break; |
8532 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8533 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8534 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8535 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8536 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8537 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8538 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8539 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8540 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8541 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8542 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8543 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8544 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8545 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8546 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8547 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8548 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8549 | case 'f': break; | |
8550 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8551 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8552 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8553 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8554 | case 'l': break; | |
8555 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8556 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8557 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8558 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8559 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8560 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8561 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8562 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8563 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8564 | case 'x': break; | |
8565 | case 'z': break; | |
8566 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8567 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8568 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8569 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8570 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8571 | case '[': break; | |
8572 | case ']': break; | |
620edafd | 8573 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8574 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8575 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8576 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8577 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8578 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8579 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8580 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8581 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8582 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8583 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8584 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8585 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8586 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8587 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8588 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8589 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8590 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8591 | default: |
8592 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8593 | c, opc->name, opc->args); | |
8594 | return 0; | |
8595 | } | |
8596 | #undef USE_BITS | |
8597 | if (used_bits != 0xffffffff) | |
8598 | { | |
8599 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8600 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8601 | return 0; | |
8602 | } | |
8603 | return 1; | |
8604 | } | |
8605 | ||
9bcd4f99 TS |
8606 | /* UDI immediates. */ |
8607 | struct mips_immed { | |
8608 | char type; | |
8609 | unsigned int shift; | |
8610 | unsigned long mask; | |
8611 | const char * desc; | |
8612 | }; | |
8613 | ||
8614 | static const struct mips_immed mips_immed[] = { | |
8615 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8616 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8617 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8618 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8619 | { 0,0,0,0 } | |
8620 | }; | |
8621 | ||
7455baf8 TS |
8622 | /* Check whether an odd floating-point register is allowed. */ |
8623 | static int | |
8624 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8625 | { | |
8626 | const char *s = insn->name; | |
8627 | ||
8628 | if (insn->pinfo == INSN_MACRO) | |
8629 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8630 | return 1; | |
8631 | ||
8632 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8633 | { | |
8634 | /* Allow odd registers for single-precision ops. */ | |
8635 | switch (insn->pinfo & (FP_S | FP_D)) | |
8636 | { | |
8637 | case FP_S: | |
8638 | case 0: | |
8639 | return 1; /* both single precision - ok */ | |
8640 | case FP_D: | |
8641 | return 0; /* both double precision - fail */ | |
8642 | default: | |
8643 | break; | |
8644 | } | |
8645 | ||
8646 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8647 | s = strchr (insn->name, '.'); | |
8648 | if (argnum == 2) | |
8649 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8650 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8651 | } | |
8652 | ||
8653 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8654 | if ((insn->pinfo & FP_S) | |
8655 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8656 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8657 | return 1; | |
8658 | ||
8659 | return 0; | |
8660 | } | |
8661 | ||
252b5132 RH |
8662 | /* This routine assembles an instruction into its binary format. As a |
8663 | side effect, it sets one of the global variables imm_reloc or | |
8664 | offset_reloc to the type of relocation to do if one of the operands | |
8665 | is an address expression. */ | |
8666 | ||
8667 | static void | |
17a2f251 | 8668 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8669 | { |
8670 | char *s; | |
8671 | const char *args; | |
43841e91 | 8672 | char c = 0; |
252b5132 RH |
8673 | struct mips_opcode *insn; |
8674 | char *argsStart; | |
8675 | unsigned int regno; | |
34224acf | 8676 | unsigned int lastregno; |
af7ee8bf | 8677 | unsigned int lastpos = 0; |
071742cf | 8678 | unsigned int limlo, limhi; |
252b5132 RH |
8679 | char *s_reset; |
8680 | char save_c = 0; | |
74cd071d | 8681 | offsetT min_range, max_range; |
707bfff6 TS |
8682 | int argnum; |
8683 | unsigned int rtype; | |
252b5132 RH |
8684 | |
8685 | insn_error = NULL; | |
8686 | ||
8687 | /* If the instruction contains a '.', we first try to match an instruction | |
8688 | including the '.'. Then we try again without the '.'. */ | |
8689 | insn = NULL; | |
3882b010 | 8690 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8691 | continue; |
8692 | ||
8693 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8694 | the call to hash_find. Save the character we replaced just in case we | |
8695 | have to re-parse the instruction. */ | |
3882b010 | 8696 | if (ISSPACE (*s)) |
252b5132 RH |
8697 | { |
8698 | save_c = *s; | |
8699 | *s++ = '\0'; | |
8700 | } | |
bdaaa2e1 | 8701 | |
252b5132 RH |
8702 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8703 | ||
8704 | /* If we didn't find the instruction in the opcode table, try again, but | |
8705 | this time with just the instruction up to, but not including the | |
8706 | first '.'. */ | |
8707 | if (insn == NULL) | |
8708 | { | |
bdaaa2e1 | 8709 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8710 | if (save_c) |
8711 | *(--s) = save_c; | |
8712 | ||
8713 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8714 | for (s = str; |
8715 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8716 | ++s) | |
252b5132 RH |
8717 | continue; |
8718 | ||
8719 | /* If we did not find a '.', then we can quit now. */ | |
8720 | if (*s != '.') | |
8721 | { | |
f71d0d44 | 8722 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8723 | return; |
8724 | } | |
8725 | ||
8726 | /* Lookup the instruction in the hash table. */ | |
8727 | *s++ = '\0'; | |
8728 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8729 | { | |
f71d0d44 | 8730 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8731 | return; |
8732 | } | |
252b5132 RH |
8733 | } |
8734 | ||
8735 | argsStart = s; | |
8736 | for (;;) | |
8737 | { | |
b34976b6 | 8738 | bfd_boolean ok; |
252b5132 | 8739 | |
9c2799c2 | 8740 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8741 | |
f79e2745 | 8742 | ok = is_opcode_valid (insn); |
252b5132 RH |
8743 | if (! ok) |
8744 | { | |
8745 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8746 | && strcmp (insn->name, insn[1].name) == 0) | |
8747 | { | |
8748 | ++insn; | |
8749 | continue; | |
8750 | } | |
252b5132 | 8751 | else |
beae10d5 | 8752 | { |
268f6bed L |
8753 | if (!insn_error) |
8754 | { | |
8755 | static char buf[100]; | |
fef14a42 TS |
8756 | sprintf (buf, |
8757 | _("opcode not supported on this processor: %s (%s)"), | |
8758 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8759 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8760 | insn_error = buf; |
8761 | } | |
8762 | if (save_c) | |
8763 | *(--s) = save_c; | |
2bd7f1f3 | 8764 | return; |
252b5132 | 8765 | } |
252b5132 RH |
8766 | } |
8767 | ||
1e915849 | 8768 | create_insn (ip, insn); |
268f6bed | 8769 | insn_error = NULL; |
707bfff6 | 8770 | argnum = 1; |
24864476 | 8771 | lastregno = 0xffffffff; |
252b5132 RH |
8772 | for (args = insn->args;; ++args) |
8773 | { | |
deec1734 CD |
8774 | int is_mdmx; |
8775 | ||
ad8d3bb3 | 8776 | s += strspn (s, " \t"); |
deec1734 | 8777 | is_mdmx = 0; |
252b5132 RH |
8778 | switch (*args) |
8779 | { | |
8780 | case '\0': /* end of args */ | |
8781 | if (*s == '\0') | |
8782 | return; | |
8783 | break; | |
8784 | ||
90ecf173 | 8785 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
8786 | my_getExpression (&imm_expr, s); |
8787 | check_absolute_expr (ip, &imm_expr); | |
8788 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8789 | && (unsigned long) imm_expr.X_add_number != 3) | |
8790 | { | |
8791 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8792 | (unsigned long) imm_expr.X_add_number); | |
8793 | } | |
8794 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8795 | imm_expr.X_op = O_absent; | |
8796 | s = expr_end; | |
8797 | continue; | |
8798 | ||
90ecf173 | 8799 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8800 | my_getExpression (&imm_expr, s); |
8801 | check_absolute_expr (ip, &imm_expr); | |
8802 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8803 | { | |
a9e24354 TS |
8804 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8805 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8806 | } |
a9e24354 | 8807 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8808 | imm_expr.X_op = O_absent; |
8809 | s = expr_end; | |
8810 | continue; | |
8811 | ||
90ecf173 | 8812 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8813 | my_getExpression (&imm_expr, s); |
8814 | check_absolute_expr (ip, &imm_expr); | |
8815 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8816 | { | |
a9e24354 TS |
8817 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8818 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8819 | } |
a9e24354 | 8820 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8821 | imm_expr.X_op = O_absent; |
8822 | s = expr_end; | |
8823 | continue; | |
8824 | ||
90ecf173 | 8825 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8826 | my_getExpression (&imm_expr, s); |
8827 | check_absolute_expr (ip, &imm_expr); | |
8828 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8829 | { | |
a9e24354 TS |
8830 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8831 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8832 | } |
a9e24354 | 8833 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8834 | imm_expr.X_op = O_absent; |
8835 | s = expr_end; | |
8836 | continue; | |
8837 | ||
90ecf173 | 8838 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8839 | my_getExpression (&imm_expr, s); |
8840 | check_absolute_expr (ip, &imm_expr); | |
8841 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8842 | { | |
a9e24354 TS |
8843 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8844 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8845 | } |
a9e24354 | 8846 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8847 | imm_expr.X_op = O_absent; |
8848 | s = expr_end; | |
8849 | continue; | |
8850 | ||
90ecf173 | 8851 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
8852 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8853 | s[3] >= '0' && s[3] <= '3') | |
8854 | { | |
8855 | regno = s[3] - '0'; | |
8856 | s += 4; | |
a9e24354 | 8857 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8858 | continue; |
8859 | } | |
8860 | else | |
8861 | as_bad (_("Invalid dsp acc register")); | |
8862 | break; | |
8863 | ||
90ecf173 | 8864 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
8865 | my_getExpression (&imm_expr, s); |
8866 | check_absolute_expr (ip, &imm_expr); | |
8867 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8868 | { | |
a9e24354 TS |
8869 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8870 | OP_MASK_WRDSP, | |
8871 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8872 | } |
a9e24354 | 8873 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8874 | imm_expr.X_op = O_absent; |
8875 | s = expr_end; | |
8876 | continue; | |
8877 | ||
90ecf173 | 8878 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
8879 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8880 | s[3] >= '0' && s[3] <= '3') | |
8881 | { | |
8882 | regno = s[3] - '0'; | |
8883 | s += 4; | |
a9e24354 | 8884 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8885 | continue; |
8886 | } | |
8887 | else | |
8888 | as_bad (_("Invalid dsp acc register")); | |
8889 | break; | |
8890 | ||
90ecf173 | 8891 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
8892 | my_getExpression (&imm_expr, s); |
8893 | check_absolute_expr (ip, &imm_expr); | |
8894 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8895 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8896 | if (imm_expr.X_add_number < min_range || | |
8897 | imm_expr.X_add_number > max_range) | |
8898 | { | |
a9e24354 TS |
8899 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8900 | (long) min_range, (long) max_range, | |
8901 | (long) imm_expr.X_add_number); | |
74cd071d | 8902 | } |
a9e24354 | 8903 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8904 | imm_expr.X_op = O_absent; |
8905 | s = expr_end; | |
8906 | continue; | |
8907 | ||
90ecf173 | 8908 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8909 | my_getExpression (&imm_expr, s); |
8910 | check_absolute_expr (ip, &imm_expr); | |
8911 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8912 | { | |
a9e24354 TS |
8913 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8914 | OP_MASK_RDDSP, | |
8915 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8916 | } |
a9e24354 | 8917 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8918 | imm_expr.X_op = O_absent; |
8919 | s = expr_end; | |
8920 | continue; | |
8921 | ||
90ecf173 | 8922 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
8923 | my_getExpression (&imm_expr, s); |
8924 | check_absolute_expr (ip, &imm_expr); | |
8925 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8926 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8927 | if (imm_expr.X_add_number < min_range || | |
8928 | imm_expr.X_add_number > max_range) | |
8929 | { | |
a9e24354 TS |
8930 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8931 | (long) min_range, (long) max_range, | |
8932 | (long) imm_expr.X_add_number); | |
74cd071d | 8933 | } |
a9e24354 | 8934 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8935 | imm_expr.X_op = O_absent; |
8936 | s = expr_end; | |
8937 | continue; | |
8938 | ||
90ecf173 | 8939 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
8940 | my_getExpression (&imm_expr, s); |
8941 | check_absolute_expr (ip, &imm_expr); | |
8942 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8943 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8944 | if (imm_expr.X_add_number < min_range || | |
8945 | imm_expr.X_add_number > max_range) | |
8946 | { | |
a9e24354 TS |
8947 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8948 | (long) min_range, (long) max_range, | |
8949 | (long) imm_expr.X_add_number); | |
74cd071d | 8950 | } |
a9e24354 | 8951 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8952 | imm_expr.X_op = O_absent; |
8953 | s = expr_end; | |
8954 | continue; | |
8955 | ||
a9e24354 | 8956 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8957 | my_getExpression (&imm_expr, s); |
8958 | check_absolute_expr (ip, &imm_expr); | |
8959 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8960 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8961 | (unsigned long) imm_expr.X_add_number); | |
8962 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8963 | imm_expr.X_op = O_absent; |
8964 | s = expr_end; | |
8965 | continue; | |
8966 | ||
a9e24354 | 8967 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8968 | my_getExpression (&imm_expr, s); |
8969 | check_absolute_expr (ip, &imm_expr); | |
8970 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8971 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8972 | (unsigned long) imm_expr.X_add_number); | |
8973 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8974 | imm_expr.X_op = O_absent; |
8975 | s = expr_end; | |
8976 | continue; | |
8977 | ||
90ecf173 | 8978 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
8979 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8980 | s[3] >= '0' && s[3] <= '3') | |
8981 | { | |
8982 | regno = s[3] - '0'; | |
8983 | s += 4; | |
a9e24354 | 8984 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8985 | continue; |
8986 | } | |
8987 | else | |
8988 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8989 | break; | |
8990 | ||
90ecf173 | 8991 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
8992 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8993 | s[3] >= '0' && s[3] <= '3') | |
8994 | { | |
8995 | regno = s[3] - '0'; | |
8996 | s += 4; | |
a9e24354 | 8997 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8998 | continue; |
8999 | } | |
9000 | else | |
9001 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9002 | break; | |
9003 | ||
252b5132 | 9004 | case ',': |
a339155f | 9005 | ++argnum; |
252b5132 RH |
9006 | if (*s++ == *args) |
9007 | continue; | |
9008 | s--; | |
9009 | switch (*++args) | |
9010 | { | |
9011 | case 'r': | |
9012 | case 'v': | |
bf12938e | 9013 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9014 | continue; |
9015 | ||
9016 | case 'w': | |
bf12938e | 9017 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9018 | continue; |
9019 | ||
252b5132 | 9020 | case 'W': |
bf12938e | 9021 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9022 | continue; |
9023 | ||
9024 | case 'V': | |
bf12938e | 9025 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9026 | continue; |
9027 | } | |
9028 | break; | |
9029 | ||
9030 | case '(': | |
9031 | /* Handle optional base register. | |
9032 | Either the base register is omitted or | |
bdaaa2e1 | 9033 | we must have a left paren. */ |
252b5132 RH |
9034 | /* This is dependent on the next operand specifier |
9035 | is a base register specification. */ | |
f9bbfb18 | 9036 | gas_assert (args[1] == 'b'); |
252b5132 RH |
9037 | if (*s == '\0') |
9038 | return; | |
9039 | ||
90ecf173 | 9040 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9041 | case '[': |
9042 | case ']': | |
252b5132 RH |
9043 | if (*s++ == *args) |
9044 | continue; | |
9045 | break; | |
9046 | ||
af7ee8bf CD |
9047 | case '+': /* Opcode extension character. */ |
9048 | switch (*++args) | |
9049 | { | |
9bcd4f99 TS |
9050 | case '1': /* UDI immediates. */ |
9051 | case '2': | |
9052 | case '3': | |
9053 | case '4': | |
9054 | { | |
9055 | const struct mips_immed *imm = mips_immed; | |
9056 | ||
9057 | while (imm->type && imm->type != *args) | |
9058 | ++imm; | |
9059 | if (! imm->type) | |
9060 | internalError (); | |
9061 | my_getExpression (&imm_expr, s); | |
9062 | check_absolute_expr (ip, &imm_expr); | |
9063 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9064 | { | |
9065 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9066 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9067 | (unsigned long) imm_expr.X_add_number, | |
9068 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9069 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9070 | } |
9071 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9072 | << imm->shift); | |
9073 | imm_expr.X_op = O_absent; | |
9074 | s = expr_end; | |
9075 | } | |
9076 | continue; | |
90ecf173 | 9077 | |
071742cf CD |
9078 | case 'A': /* ins/ext position, becomes LSB. */ |
9079 | limlo = 0; | |
9080 | limhi = 31; | |
5f74bc13 CD |
9081 | goto do_lsb; |
9082 | case 'E': | |
9083 | limlo = 32; | |
9084 | limhi = 63; | |
9085 | goto do_lsb; | |
90ecf173 | 9086 | do_lsb: |
071742cf CD |
9087 | my_getExpression (&imm_expr, s); |
9088 | check_absolute_expr (ip, &imm_expr); | |
9089 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9090 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9091 | { | |
9092 | as_bad (_("Improper position (%lu)"), | |
9093 | (unsigned long) imm_expr.X_add_number); | |
9094 | imm_expr.X_add_number = limlo; | |
9095 | } | |
9096 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9097 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9098 | imm_expr.X_op = O_absent; |
9099 | s = expr_end; | |
9100 | continue; | |
9101 | ||
9102 | case 'B': /* ins size, becomes MSB. */ | |
9103 | limlo = 1; | |
9104 | limhi = 32; | |
5f74bc13 CD |
9105 | goto do_msb; |
9106 | case 'F': | |
9107 | limlo = 33; | |
9108 | limhi = 64; | |
9109 | goto do_msb; | |
90ecf173 | 9110 | do_msb: |
071742cf CD |
9111 | my_getExpression (&imm_expr, s); |
9112 | check_absolute_expr (ip, &imm_expr); | |
9113 | /* Check for negative input so that small negative numbers | |
9114 | will not succeed incorrectly. The checks against | |
9115 | (pos+size) transitively check "size" itself, | |
9116 | assuming that "pos" is reasonable. */ | |
9117 | if ((long) imm_expr.X_add_number < 0 | |
9118 | || ((unsigned long) imm_expr.X_add_number | |
9119 | + lastpos) < limlo | |
9120 | || ((unsigned long) imm_expr.X_add_number | |
9121 | + lastpos) > limhi) | |
9122 | { | |
9123 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9124 | (unsigned long) imm_expr.X_add_number, | |
9125 | (unsigned long) lastpos); | |
9126 | imm_expr.X_add_number = limlo - lastpos; | |
9127 | } | |
bf12938e RS |
9128 | INSERT_OPERAND (INSMSB, *ip, |
9129 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9130 | imm_expr.X_op = O_absent; |
9131 | s = expr_end; | |
9132 | continue; | |
9133 | ||
9134 | case 'C': /* ext size, becomes MSBD. */ | |
9135 | limlo = 1; | |
9136 | limhi = 32; | |
5f74bc13 CD |
9137 | goto do_msbd; |
9138 | case 'G': | |
9139 | limlo = 33; | |
9140 | limhi = 64; | |
9141 | goto do_msbd; | |
9142 | case 'H': | |
9143 | limlo = 33; | |
9144 | limhi = 64; | |
9145 | goto do_msbd; | |
90ecf173 | 9146 | do_msbd: |
071742cf CD |
9147 | my_getExpression (&imm_expr, s); |
9148 | check_absolute_expr (ip, &imm_expr); | |
9149 | /* Check for negative input so that small negative numbers | |
9150 | will not succeed incorrectly. The checks against | |
9151 | (pos+size) transitively check "size" itself, | |
9152 | assuming that "pos" is reasonable. */ | |
9153 | if ((long) imm_expr.X_add_number < 0 | |
9154 | || ((unsigned long) imm_expr.X_add_number | |
9155 | + lastpos) < limlo | |
9156 | || ((unsigned long) imm_expr.X_add_number | |
9157 | + lastpos) > limhi) | |
9158 | { | |
9159 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9160 | (unsigned long) imm_expr.X_add_number, | |
9161 | (unsigned long) lastpos); | |
9162 | imm_expr.X_add_number = limlo - lastpos; | |
9163 | } | |
bf12938e | 9164 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9165 | imm_expr.X_op = O_absent; |
9166 | s = expr_end; | |
9167 | continue; | |
af7ee8bf | 9168 | |
bbcc0807 CD |
9169 | case 'D': |
9170 | /* +D is for disassembly only; never match. */ | |
9171 | break; | |
9172 | ||
5f74bc13 CD |
9173 | case 'I': |
9174 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9175 | my_getExpression (&imm2_expr, s); | |
9176 | if (imm2_expr.X_op != O_big | |
9177 | && imm2_expr.X_op != O_constant) | |
9178 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9179 | if (HAVE_32BIT_GPRS) |
9180 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9181 | s = expr_end; |
9182 | continue; | |
9183 | ||
707bfff6 | 9184 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9185 | /* +T is for disassembly only; never match. */ |
9186 | break; | |
9187 | ||
707bfff6 | 9188 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9189 | if (s[0] == '$' && ISDIGIT (s[1])) |
9190 | { | |
9191 | ++s; | |
9192 | regno = 0; | |
9193 | do | |
9194 | { | |
9195 | regno *= 10; | |
9196 | regno += *s - '0'; | |
9197 | ++s; | |
9198 | } | |
9199 | while (ISDIGIT (*s)); | |
9200 | if (regno > 31) | |
9201 | as_bad (_("Invalid register number (%d)"), regno); | |
9202 | else | |
9203 | { | |
a9e24354 | 9204 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9205 | continue; |
9206 | } | |
9207 | } | |
9208 | else | |
9209 | as_bad (_("Invalid coprocessor 0 register number")); | |
9210 | break; | |
9211 | ||
bb35fb24 NC |
9212 | case 'x': |
9213 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9214 | is not in the valid range. */ | |
9215 | my_getExpression (&imm_expr, s); | |
9216 | check_absolute_expr (ip, &imm_expr); | |
9217 | if ((unsigned) imm_expr.X_add_number > 31) | |
9218 | { | |
9219 | as_bad (_("Improper bit index (%lu)"), | |
9220 | (unsigned long) imm_expr.X_add_number); | |
9221 | imm_expr.X_add_number = 0; | |
9222 | } | |
9223 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9224 | imm_expr.X_op = O_absent; | |
9225 | s = expr_end; | |
9226 | continue; | |
9227 | ||
9228 | case 'X': | |
9229 | /* bbit[01] bit index when bbit is used but we generate | |
9230 | bbit[01]32 because the index is over 32. Move to the | |
9231 | next candidate if index is not in the valid range. */ | |
9232 | my_getExpression (&imm_expr, s); | |
9233 | check_absolute_expr (ip, &imm_expr); | |
9234 | if ((unsigned) imm_expr.X_add_number < 32 | |
9235 | || (unsigned) imm_expr.X_add_number > 63) | |
9236 | break; | |
9237 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9238 | imm_expr.X_op = O_absent; | |
9239 | s = expr_end; | |
9240 | continue; | |
9241 | ||
9242 | case 'p': | |
9243 | /* cins, cins32, exts and exts32 position field. Give error | |
9244 | if it's not in the valid range. */ | |
9245 | my_getExpression (&imm_expr, s); | |
9246 | check_absolute_expr (ip, &imm_expr); | |
9247 | if ((unsigned) imm_expr.X_add_number > 31) | |
9248 | { | |
9249 | as_bad (_("Improper position (%lu)"), | |
9250 | (unsigned long) imm_expr.X_add_number); | |
9251 | imm_expr.X_add_number = 0; | |
9252 | } | |
9253 | /* Make the pos explicit to simplify +S. */ | |
9254 | lastpos = imm_expr.X_add_number + 32; | |
9255 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9256 | imm_expr.X_op = O_absent; | |
9257 | s = expr_end; | |
9258 | continue; | |
9259 | ||
9260 | case 'P': | |
9261 | /* cins, cins32, exts and exts32 position field. Move to | |
9262 | the next candidate if it's not in the valid range. */ | |
9263 | my_getExpression (&imm_expr, s); | |
9264 | check_absolute_expr (ip, &imm_expr); | |
9265 | if ((unsigned) imm_expr.X_add_number < 32 | |
9266 | || (unsigned) imm_expr.X_add_number > 63) | |
9267 | break; | |
9268 | lastpos = imm_expr.X_add_number; | |
9269 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9270 | imm_expr.X_op = O_absent; | |
9271 | s = expr_end; | |
9272 | continue; | |
9273 | ||
9274 | case 's': | |
9275 | /* cins and exts length-minus-one field. */ | |
9276 | my_getExpression (&imm_expr, s); | |
9277 | check_absolute_expr (ip, &imm_expr); | |
9278 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9279 | { | |
9280 | as_bad (_("Improper size (%lu)"), | |
9281 | (unsigned long) imm_expr.X_add_number); | |
9282 | imm_expr.X_add_number = 0; | |
9283 | } | |
9284 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9285 | imm_expr.X_op = O_absent; | |
9286 | s = expr_end; | |
9287 | continue; | |
9288 | ||
9289 | case 'S': | |
9290 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9291 | length-minus-one field. */ | |
9292 | my_getExpression (&imm_expr, s); | |
9293 | check_absolute_expr (ip, &imm_expr); | |
9294 | if ((long) imm_expr.X_add_number < 0 | |
9295 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9296 | { | |
9297 | as_bad (_("Improper size (%lu)"), | |
9298 | (unsigned long) imm_expr.X_add_number); | |
9299 | imm_expr.X_add_number = 0; | |
9300 | } | |
9301 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9302 | imm_expr.X_op = O_absent; | |
9303 | s = expr_end; | |
9304 | continue; | |
9305 | ||
dd3cbb7e NC |
9306 | case 'Q': |
9307 | /* seqi/snei immediate field. */ | |
9308 | my_getExpression (&imm_expr, s); | |
9309 | check_absolute_expr (ip, &imm_expr); | |
9310 | if ((long) imm_expr.X_add_number < -512 | |
9311 | || (long) imm_expr.X_add_number >= 512) | |
9312 | { | |
9313 | as_bad (_("Improper immediate (%ld)"), | |
9314 | (long) imm_expr.X_add_number); | |
9315 | imm_expr.X_add_number = 0; | |
9316 | } | |
9317 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9318 | imm_expr.X_op = O_absent; | |
9319 | s = expr_end; | |
9320 | continue; | |
9321 | ||
98675402 RS |
9322 | case 'a': /* 8-bit signed offset in bit 6 */ |
9323 | my_getExpression (&imm_expr, s); | |
9324 | check_absolute_expr (ip, &imm_expr); | |
9325 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
9326 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
9327 | if (imm_expr.X_add_number < min_range | |
9328 | || imm_expr.X_add_number > max_range) | |
9329 | { | |
c95354ed | 9330 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9331 | (long) min_range, (long) max_range, |
9332 | (long) imm_expr.X_add_number); | |
9333 | } | |
9334 | INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number); | |
9335 | imm_expr.X_op = O_absent; | |
9336 | s = expr_end; | |
9337 | continue; | |
9338 | ||
9339 | case 'b': /* 8-bit signed offset in bit 3 */ | |
9340 | my_getExpression (&imm_expr, s); | |
9341 | check_absolute_expr (ip, &imm_expr); | |
9342 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
9343 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
9344 | if (imm_expr.X_add_number < min_range | |
9345 | || imm_expr.X_add_number > max_range) | |
9346 | { | |
c95354ed | 9347 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9348 | (long) min_range, (long) max_range, |
9349 | (long) imm_expr.X_add_number); | |
9350 | } | |
9351 | INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number); | |
9352 | imm_expr.X_op = O_absent; | |
9353 | s = expr_end; | |
9354 | continue; | |
9355 | ||
9356 | case 'c': /* 9-bit signed offset in bit 6 */ | |
9357 | my_getExpression (&imm_expr, s); | |
9358 | check_absolute_expr (ip, &imm_expr); | |
9359 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
9360 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
9361 | /* We check the offset range before adjusted. */ |
9362 | min_range <<= 4; | |
9363 | max_range <<= 4; | |
98675402 RS |
9364 | if (imm_expr.X_add_number < min_range |
9365 | || imm_expr.X_add_number > max_range) | |
9366 | { | |
c95354ed | 9367 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9368 | (long) min_range, (long) max_range, |
9369 | (long) imm_expr.X_add_number); | |
9370 | } | |
c95354ed MX |
9371 | if (imm_expr.X_add_number & 0xf) |
9372 | { | |
9373 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
9374 | (long) imm_expr.X_add_number); | |
9375 | } | |
9376 | /* Right shift 4 bits to adjust the offset operand. */ | |
9377 | INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4); | |
98675402 RS |
9378 | imm_expr.X_op = O_absent; |
9379 | s = expr_end; | |
9380 | continue; | |
9381 | ||
9382 | case 'z': | |
9383 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
9384 | break; | |
9385 | if (regno == AT && mips_opts.at) | |
9386 | { | |
9387 | if (mips_opts.at == ATREG) | |
9388 | as_warn (_("used $at without \".set noat\"")); | |
9389 | else | |
9390 | as_warn (_("used $%u with \".set at=$%u\""), | |
9391 | regno, mips_opts.at); | |
9392 | } | |
9393 | INSERT_OPERAND (RZ, *ip, regno); | |
9394 | continue; | |
9395 | ||
9396 | case 'Z': | |
9397 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) | |
9398 | break; | |
9399 | INSERT_OPERAND (FZ, *ip, regno); | |
9400 | continue; | |
9401 | ||
af7ee8bf | 9402 | default: |
f71d0d44 | 9403 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9404 | "(unknown extension operand type `+%c'): %s %s"), |
9405 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9406 | /* Further processing is fruitless. */ |
9407 | return; | |
9408 | } | |
9409 | break; | |
9410 | ||
252b5132 RH |
9411 | case '<': /* must be at least one digit */ |
9412 | /* | |
9413 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9414 | * than 31 or less than 0, then the shift amount should be |
9415 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9416 | * We issue a warning and mask out all but the low 5 bits. |
9417 | */ | |
9418 | my_getExpression (&imm_expr, s); | |
9419 | check_absolute_expr (ip, &imm_expr); | |
9420 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9421 | as_warn (_("Improper shift amount (%lu)"), |
9422 | (unsigned long) imm_expr.X_add_number); | |
9423 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9424 | imm_expr.X_op = O_absent; |
9425 | s = expr_end; | |
9426 | continue; | |
9427 | ||
9428 | case '>': /* shift amount minus 32 */ | |
9429 | my_getExpression (&imm_expr, s); | |
9430 | check_absolute_expr (ip, &imm_expr); | |
9431 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9432 | || (unsigned long) imm_expr.X_add_number > 63) | |
9433 | break; | |
bf12938e | 9434 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9435 | imm_expr.X_op = O_absent; |
9436 | s = expr_end; | |
9437 | continue; | |
9438 | ||
90ecf173 MR |
9439 | case 'k': /* CACHE code. */ |
9440 | case 'h': /* PREFX code. */ | |
9441 | case '1': /* SYNC type. */ | |
252b5132 RH |
9442 | my_getExpression (&imm_expr, s); |
9443 | check_absolute_expr (ip, &imm_expr); | |
9444 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9445 | as_warn (_("Invalid value for `%s' (%lu)"), |
9446 | ip->insn_mo->name, | |
9447 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9448 | if (*args == 'k') |
d954098f DD |
9449 | { |
9450 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9451 | switch (imm_expr.X_add_number) | |
9452 | { | |
9453 | case 5: | |
9454 | case 25: | |
9455 | case 26: | |
9456 | case 27: | |
9457 | case 28: | |
9458 | case 29: | |
9459 | case 30: | |
9460 | case 31: /* These are ok. */ | |
9461 | break; | |
9462 | ||
9463 | default: /* The rest must be changed to 28. */ | |
9464 | imm_expr.X_add_number = 28; | |
9465 | break; | |
9466 | } | |
9467 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9468 | } | |
620edafd | 9469 | else if (*args == 'h') |
bf12938e | 9470 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9471 | else |
9472 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9473 | imm_expr.X_op = O_absent; |
9474 | s = expr_end; | |
9475 | continue; | |
9476 | ||
90ecf173 | 9477 | case 'c': /* BREAK code. */ |
252b5132 RH |
9478 | my_getExpression (&imm_expr, s); |
9479 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9480 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9481 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9482 | ip->insn_mo->name, | |
bf12938e RS |
9483 | (unsigned long) imm_expr.X_add_number); |
9484 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9485 | imm_expr.X_op = O_absent; |
9486 | s = expr_end; | |
9487 | continue; | |
9488 | ||
90ecf173 | 9489 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9490 | my_getExpression (&imm_expr, s); |
9491 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9492 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9493 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9494 | ip->insn_mo->name, | |
bf12938e RS |
9495 | (unsigned long) imm_expr.X_add_number); |
9496 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9497 | imm_expr.X_op = O_absent; |
9498 | s = expr_end; | |
9499 | continue; | |
9500 | ||
90ecf173 | 9501 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9502 | my_getExpression (&imm_expr, s); |
156c2f8b | 9503 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9504 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9505 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9506 | ip->insn_mo->name, | |
793b27f4 | 9507 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9508 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9509 | imm_expr.X_op = O_absent; |
9510 | s = expr_end; | |
9511 | continue; | |
9512 | ||
90ecf173 | 9513 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9514 | my_getExpression (&imm_expr, s); |
252b5132 | 9515 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9516 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9517 | { |
793b27f4 TS |
9518 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9519 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9520 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9521 | } |
a9e24354 | 9522 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9523 | imm_expr.X_op = O_absent; |
9524 | s = expr_end; | |
9525 | continue; | |
252b5132 | 9526 | |
90ecf173 | 9527 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9528 | my_getExpression (&imm_expr, s); |
9529 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9530 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9531 | { |
9532 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9533 | (unsigned long) imm_expr.X_add_number); | |
9534 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9535 | } | |
bf12938e | 9536 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9537 | imm_expr.X_op = O_absent; |
9538 | s = expr_end; | |
9539 | continue; | |
9540 | ||
707bfff6 | 9541 | case 'P': /* Performance register. */ |
beae10d5 | 9542 | my_getExpression (&imm_expr, s); |
252b5132 | 9543 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9544 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9545 | as_warn (_("Invalid performance register (%lu)"), |
9546 | (unsigned long) imm_expr.X_add_number); | |
9547 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9548 | imm_expr.X_op = O_absent; |
9549 | s = expr_end; | |
9550 | continue; | |
252b5132 | 9551 | |
707bfff6 TS |
9552 | case 'G': /* Coprocessor destination register. */ |
9553 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9554 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9555 | else | |
9556 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9557 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9558 | if (ok) |
9559 | { | |
9560 | lastregno = regno; | |
9561 | continue; | |
9562 | } | |
9563 | else | |
9564 | break; | |
9565 | ||
90ecf173 MR |
9566 | case 'b': /* Base register. */ |
9567 | case 'd': /* Destination register. */ | |
9568 | case 's': /* Source register. */ | |
9569 | case 't': /* Target register. */ | |
9570 | case 'r': /* Both target and source. */ | |
9571 | case 'v': /* Both dest and source. */ | |
9572 | case 'w': /* Both dest and target. */ | |
9573 | case 'E': /* Coprocessor target register. */ | |
9574 | case 'K': /* RDHWR destination register. */ | |
9575 | case 'x': /* Ignore register name. */ | |
9576 | case 'z': /* Must be zero register. */ | |
9577 | case 'U': /* Destination register (CLO/CLZ). */ | |
9578 | case 'g': /* Coprocessor destination register. */ | |
9579 | s_reset = s; | |
707bfff6 TS |
9580 | if (*args == 'E' || *args == 'K') |
9581 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9582 | else | |
9583 | { | |
9584 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9585 | if (regno == AT && mips_opts.at) |
9586 | { | |
9587 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9588 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9589 | else |
f71d0d44 | 9590 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9591 | regno, mips_opts.at); |
9592 | } | |
707bfff6 TS |
9593 | } |
9594 | if (ok) | |
252b5132 | 9595 | { |
252b5132 RH |
9596 | c = *args; |
9597 | if (*s == ' ') | |
f9419b05 | 9598 | ++s; |
252b5132 RH |
9599 | if (args[1] != *s) |
9600 | { | |
9601 | if (c == 'r' || c == 'v' || c == 'w') | |
9602 | { | |
9603 | regno = lastregno; | |
9604 | s = s_reset; | |
f9419b05 | 9605 | ++args; |
252b5132 RH |
9606 | } |
9607 | } | |
9608 | /* 'z' only matches $0. */ | |
9609 | if (c == 'z' && regno != 0) | |
9610 | break; | |
9611 | ||
24864476 | 9612 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9613 | { |
9614 | if (regno == lastregno) | |
90ecf173 MR |
9615 | { |
9616 | insn_error | |
f71d0d44 | 9617 | = _("Source and destination must be different"); |
e7c604dd | 9618 | continue; |
90ecf173 | 9619 | } |
24864476 | 9620 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9621 | { |
9622 | insn_error | |
f71d0d44 | 9623 | = _("A destination register must be supplied"); |
e7c604dd | 9624 | continue; |
90ecf173 | 9625 | } |
e7c604dd | 9626 | } |
90ecf173 MR |
9627 | /* Now that we have assembled one operand, we use the args |
9628 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9629 | switch (c) |
9630 | { | |
9631 | case 'r': | |
9632 | case 's': | |
9633 | case 'v': | |
9634 | case 'b': | |
bf12938e | 9635 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9636 | break; |
9637 | case 'd': | |
af7ee8bf | 9638 | case 'K': |
ef2e4d86 | 9639 | case 'g': |
bf12938e | 9640 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9641 | break; |
4372b673 | 9642 | case 'U': |
bf12938e RS |
9643 | INSERT_OPERAND (RD, *ip, regno); |
9644 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9645 | break; |
252b5132 RH |
9646 | case 'w': |
9647 | case 't': | |
9648 | case 'E': | |
bf12938e | 9649 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9650 | break; |
9651 | case 'x': | |
9652 | /* This case exists because on the r3000 trunc | |
9653 | expands into a macro which requires a gp | |
9654 | register. On the r6000 or r4000 it is | |
9655 | assembled into a single instruction which | |
9656 | ignores the register. Thus the insn version | |
9657 | is MIPS_ISA2 and uses 'x', and the macro | |
9658 | version is MIPS_ISA1 and uses 't'. */ | |
9659 | break; | |
9660 | case 'z': | |
9661 | /* This case is for the div instruction, which | |
9662 | acts differently if the destination argument | |
9663 | is $0. This only matches $0, and is checked | |
9664 | outside the switch. */ | |
9665 | break; | |
252b5132 RH |
9666 | } |
9667 | lastregno = regno; | |
9668 | continue; | |
9669 | } | |
252b5132 RH |
9670 | switch (*args++) |
9671 | { | |
9672 | case 'r': | |
9673 | case 'v': | |
bf12938e | 9674 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9675 | continue; |
9676 | case 'w': | |
bf12938e | 9677 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9678 | continue; |
9679 | } | |
9680 | break; | |
9681 | ||
deec1734 CD |
9682 | case 'O': /* MDMX alignment immediate constant. */ |
9683 | my_getExpression (&imm_expr, s); | |
9684 | check_absolute_expr (ip, &imm_expr); | |
9685 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9686 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9687 | (long) imm_expr.X_add_number); |
9688 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9689 | imm_expr.X_op = O_absent; |
9690 | s = expr_end; | |
9691 | continue; | |
9692 | ||
9693 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9694 | if (s[0] != '$') | |
9695 | { | |
9696 | /* MDMX Immediate. */ | |
9697 | my_getExpression (&imm_expr, s); | |
9698 | check_absolute_expr (ip, &imm_expr); | |
9699 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9700 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9701 | (long) imm_expr.X_add_number); | |
9702 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9703 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9704 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9705 | else | |
9706 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9707 | imm_expr.X_op = O_absent; |
9708 | s = expr_end; | |
9709 | continue; | |
9710 | } | |
9711 | /* Not MDMX Immediate. Fall through. */ | |
9712 | case 'X': /* MDMX destination register. */ | |
9713 | case 'Y': /* MDMX source register. */ | |
9714 | case 'Z': /* MDMX target register. */ | |
9715 | is_mdmx = 1; | |
90ecf173 MR |
9716 | case 'D': /* Floating point destination register. */ |
9717 | case 'S': /* Floating point source register. */ | |
9718 | case 'T': /* Floating point target register. */ | |
9719 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9720 | case 'V': |
9721 | case 'W': | |
707bfff6 TS |
9722 | rtype = RTYPE_FPU; |
9723 | if (is_mdmx | |
9724 | || (mips_opts.ase_mdmx | |
9725 | && (ip->insn_mo->pinfo & FP_D) | |
9726 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9727 | | INSN_COPROC_MEMORY_DELAY | |
9728 | | INSN_LOAD_COPROC_DELAY | |
9729 | | INSN_LOAD_MEMORY_DELAY | |
9730 | | INSN_STORE_MEMORY)))) | |
9731 | rtype |= RTYPE_VEC; | |
252b5132 | 9732 | s_reset = s; |
707bfff6 | 9733 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9734 | { |
252b5132 | 9735 | if ((regno & 1) != 0 |
ca4e0257 | 9736 | && HAVE_32BIT_FPRS |
90ecf173 | 9737 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9738 | as_warn (_("Float register should be even, was %d"), |
9739 | regno); | |
9740 | ||
9741 | c = *args; | |
9742 | if (*s == ' ') | |
f9419b05 | 9743 | ++s; |
252b5132 RH |
9744 | if (args[1] != *s) |
9745 | { | |
9746 | if (c == 'V' || c == 'W') | |
9747 | { | |
9748 | regno = lastregno; | |
9749 | s = s_reset; | |
f9419b05 | 9750 | ++args; |
252b5132 RH |
9751 | } |
9752 | } | |
9753 | switch (c) | |
9754 | { | |
9755 | case 'D': | |
deec1734 | 9756 | case 'X': |
bf12938e | 9757 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9758 | break; |
9759 | case 'V': | |
9760 | case 'S': | |
deec1734 | 9761 | case 'Y': |
bf12938e | 9762 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9763 | break; |
deec1734 CD |
9764 | case 'Q': |
9765 | /* This is like 'Z', but also needs to fix the MDMX | |
9766 | vector/scalar select bits. Note that the | |
9767 | scalar immediate case is handled above. */ | |
9768 | if (*s == '[') | |
9769 | { | |
9770 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9771 | int max_el = (is_qh ? 3 : 7); | |
9772 | s++; | |
9773 | my_getExpression(&imm_expr, s); | |
9774 | check_absolute_expr (ip, &imm_expr); | |
9775 | s = expr_end; | |
9776 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9777 | as_bad (_("Bad element selector %ld"), |
9778 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9779 | imm_expr.X_add_number &= max_el; |
9780 | ip->insn_opcode |= (imm_expr.X_add_number | |
9781 | << (OP_SH_VSEL + | |
9782 | (is_qh ? 2 : 1))); | |
01a3f561 | 9783 | imm_expr.X_op = O_absent; |
deec1734 | 9784 | if (*s != ']') |
20203fb9 | 9785 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9786 | else |
9787 | s++; | |
9788 | } | |
9789 | else | |
9790 | { | |
9791 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9792 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9793 | << OP_SH_VSEL); | |
9794 | else | |
9795 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9796 | OP_SH_VSEL); | |
9797 | } | |
90ecf173 | 9798 | /* Fall through. */ |
252b5132 RH |
9799 | case 'W': |
9800 | case 'T': | |
deec1734 | 9801 | case 'Z': |
bf12938e | 9802 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9803 | break; |
9804 | case 'R': | |
bf12938e | 9805 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9806 | break; |
9807 | } | |
9808 | lastregno = regno; | |
9809 | continue; | |
9810 | } | |
9811 | ||
252b5132 RH |
9812 | switch (*args++) |
9813 | { | |
9814 | case 'V': | |
bf12938e | 9815 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9816 | continue; |
9817 | case 'W': | |
bf12938e | 9818 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9819 | continue; |
9820 | } | |
9821 | break; | |
9822 | ||
9823 | case 'I': | |
9824 | my_getExpression (&imm_expr, s); | |
9825 | if (imm_expr.X_op != O_big | |
9826 | && imm_expr.X_op != O_constant) | |
9827 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9828 | if (HAVE_32BIT_GPRS) |
9829 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9830 | s = expr_end; |
9831 | continue; | |
9832 | ||
9833 | case 'A': | |
9834 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9835 | normalize_address_expr (&offset_expr); |
f6688943 | 9836 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9837 | s = expr_end; |
9838 | continue; | |
9839 | ||
9840 | case 'F': | |
9841 | case 'L': | |
9842 | case 'f': | |
9843 | case 'l': | |
9844 | { | |
9845 | int f64; | |
ca4e0257 | 9846 | int using_gprs; |
252b5132 RH |
9847 | char *save_in; |
9848 | char *err; | |
9849 | unsigned char temp[8]; | |
9850 | int len; | |
9851 | unsigned int length; | |
9852 | segT seg; | |
9853 | subsegT subseg; | |
9854 | char *p; | |
9855 | ||
9856 | /* These only appear as the last operand in an | |
9857 | instruction, and every instruction that accepts | |
9858 | them in any variant accepts them in all variants. | |
9859 | This means we don't have to worry about backing out | |
9860 | any changes if the instruction does not match. | |
9861 | ||
9862 | The difference between them is the size of the | |
9863 | floating point constant and where it goes. For 'F' | |
9864 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9865 | is 32 bits. Where the constant is placed is based | |
9866 | on how the MIPS assembler does things: | |
9867 | F -- .rdata | |
9868 | L -- .lit8 | |
9869 | f -- immediate value | |
9870 | l -- .lit4 | |
9871 | ||
9872 | The .lit4 and .lit8 sections are only used if | |
9873 | permitted by the -G argument. | |
9874 | ||
ca4e0257 RS |
9875 | The code below needs to know whether the target register |
9876 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9877 | 'F' are used with GPR-based instructions and 'l' and | |
9878 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9879 | |
9880 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9881 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9882 | |
9883 | save_in = input_line_pointer; | |
9884 | input_line_pointer = s; | |
9885 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9886 | length = len; | |
9887 | s = input_line_pointer; | |
9888 | input_line_pointer = save_in; | |
9889 | if (err != NULL && *err != '\0') | |
9890 | { | |
9891 | as_bad (_("Bad floating point constant: %s"), err); | |
9892 | memset (temp, '\0', sizeof temp); | |
9893 | length = f64 ? 8 : 4; | |
9894 | } | |
9895 | ||
9c2799c2 | 9896 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9897 | |
9898 | if (*args == 'f' | |
9899 | || (*args == 'l' | |
3e722fb5 | 9900 | && (g_switch_value < 4 |
252b5132 RH |
9901 | || (temp[0] == 0 && temp[1] == 0) |
9902 | || (temp[2] == 0 && temp[3] == 0)))) | |
9903 | { | |
9904 | imm_expr.X_op = O_constant; | |
90ecf173 | 9905 | if (!target_big_endian) |
252b5132 RH |
9906 | imm_expr.X_add_number = bfd_getl32 (temp); |
9907 | else | |
9908 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9909 | } | |
9910 | else if (length > 4 | |
90ecf173 | 9911 | && !mips_disable_float_construction |
ca4e0257 RS |
9912 | /* Constants can only be constructed in GPRs and |
9913 | copied to FPRs if the GPRs are at least as wide | |
9914 | as the FPRs. Force the constant into memory if | |
9915 | we are using 64-bit FPRs but the GPRs are only | |
9916 | 32 bits wide. */ | |
9917 | && (using_gprs | |
90ecf173 | 9918 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
9919 | && ((temp[0] == 0 && temp[1] == 0) |
9920 | || (temp[2] == 0 && temp[3] == 0)) | |
9921 | && ((temp[4] == 0 && temp[5] == 0) | |
9922 | || (temp[6] == 0 && temp[7] == 0))) | |
9923 | { | |
ca4e0257 | 9924 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
9925 | instructions. If using 32-bit registers, set |
9926 | imm_expr to the high order 32 bits and offset_expr to | |
9927 | the low order 32 bits. Otherwise, set imm_expr to | |
9928 | the entire 64 bit constant. */ | |
ca4e0257 | 9929 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
9930 | { |
9931 | imm_expr.X_op = O_constant; | |
9932 | offset_expr.X_op = O_constant; | |
90ecf173 | 9933 | if (!target_big_endian) |
252b5132 RH |
9934 | { |
9935 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9936 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9937 | } | |
9938 | else | |
9939 | { | |
9940 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9941 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9942 | } | |
9943 | if (offset_expr.X_add_number == 0) | |
9944 | offset_expr.X_op = O_absent; | |
9945 | } | |
9946 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9947 | { | |
9948 | imm_expr.X_op = O_constant; | |
90ecf173 | 9949 | if (!target_big_endian) |
252b5132 RH |
9950 | imm_expr.X_add_number = bfd_getl64 (temp); |
9951 | else | |
9952 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9953 | } | |
9954 | else | |
9955 | { | |
9956 | imm_expr.X_op = O_big; | |
9957 | imm_expr.X_add_number = 4; | |
90ecf173 | 9958 | if (!target_big_endian) |
252b5132 RH |
9959 | { |
9960 | generic_bignum[0] = bfd_getl16 (temp); | |
9961 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9962 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9963 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9964 | } | |
9965 | else | |
9966 | { | |
9967 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9968 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9969 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9970 | generic_bignum[3] = bfd_getb16 (temp); | |
9971 | } | |
9972 | } | |
9973 | } | |
9974 | else | |
9975 | { | |
9976 | const char *newname; | |
9977 | segT new_seg; | |
9978 | ||
9979 | /* Switch to the right section. */ | |
9980 | seg = now_seg; | |
9981 | subseg = now_subseg; | |
9982 | switch (*args) | |
9983 | { | |
9984 | default: /* unused default case avoids warnings. */ | |
9985 | case 'L': | |
9986 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9987 | if (g_switch_value >= 8) |
252b5132 RH |
9988 | newname = ".lit8"; |
9989 | break; | |
9990 | case 'F': | |
3e722fb5 | 9991 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9992 | break; |
9993 | case 'l': | |
9c2799c2 | 9994 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9995 | newname = ".lit4"; |
9996 | break; | |
9997 | } | |
9998 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9999 | if (IS_ELF) |
252b5132 RH |
10000 | bfd_set_section_flags (stdoutput, new_seg, |
10001 | (SEC_ALLOC | |
10002 | | SEC_LOAD | |
10003 | | SEC_READONLY | |
10004 | | SEC_DATA)); | |
10005 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 10006 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
10007 | record_alignment (new_seg, 4); |
10008 | else | |
10009 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
10010 | if (seg == now_seg) | |
10011 | as_bad (_("Can't use floating point insn in this section")); | |
10012 | ||
10013 | /* Set the argument to the current address in the | |
10014 | section. */ | |
10015 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 10016 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
10017 | offset_expr.X_add_number = 0; |
10018 | ||
10019 | /* Put the floating point number into the section. */ | |
10020 | p = frag_more ((int) length); | |
10021 | memcpy (p, temp, length); | |
10022 | ||
10023 | /* Switch back to the original section. */ | |
10024 | subseg_set (seg, subseg); | |
10025 | } | |
10026 | } | |
10027 | continue; | |
10028 | ||
90ecf173 MR |
10029 | case 'i': /* 16-bit unsigned immediate. */ |
10030 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 10031 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 10032 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
10033 | { |
10034 | int more; | |
5e0116d5 RS |
10035 | offsetT minval, maxval; |
10036 | ||
10037 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10038 | && strcmp (insn->name, insn[1].name) == 0); | |
10039 | ||
10040 | /* If the expression was written as an unsigned number, | |
10041 | only treat it as signed if there are no more | |
10042 | alternatives. */ | |
10043 | if (more | |
10044 | && *args == 'j' | |
10045 | && sizeof (imm_expr.X_add_number) <= 4 | |
10046 | && imm_expr.X_op == O_constant | |
10047 | && imm_expr.X_add_number < 0 | |
10048 | && imm_expr.X_unsigned | |
10049 | && HAVE_64BIT_GPRS) | |
10050 | break; | |
10051 | ||
10052 | /* For compatibility with older assemblers, we accept | |
10053 | 0x8000-0xffff as signed 16-bit numbers when only | |
10054 | signed numbers are allowed. */ | |
10055 | if (*args == 'i') | |
10056 | minval = 0, maxval = 0xffff; | |
10057 | else if (more) | |
10058 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10059 | else |
5e0116d5 RS |
10060 | minval = -0x8000, maxval = 0xffff; |
10061 | ||
10062 | if (imm_expr.X_op != O_constant | |
10063 | || imm_expr.X_add_number < minval | |
10064 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10065 | { |
10066 | if (more) | |
10067 | break; | |
2ae7e77b AH |
10068 | if (imm_expr.X_op == O_constant |
10069 | || imm_expr.X_op == O_big) | |
f71d0d44 | 10070 | as_bad (_("Expression out of range")); |
252b5132 RH |
10071 | } |
10072 | } | |
10073 | s = expr_end; | |
10074 | continue; | |
10075 | ||
90ecf173 | 10076 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
10077 | offset_reloc[0] = BFD_RELOC_LO16; |
10078 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10079 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
10080 | ||
5e0116d5 RS |
10081 | /* Check whether there is only a single bracketed expression |
10082 | left. If so, it must be the base register and the | |
10083 | constant must be zero. */ | |
10084 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10085 | { | |
10086 | offset_expr.X_op = O_constant; | |
10087 | offset_expr.X_add_number = 0; | |
10088 | continue; | |
10089 | } | |
252b5132 RH |
10090 | |
10091 | /* If this value won't fit into a 16 bit offset, then go | |
10092 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10093 | code pattern. */ |
5e0116d5 | 10094 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10095 | && (offset_expr.X_op != O_constant |
10096 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10097 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10098 | break; |
10099 | ||
252b5132 RH |
10100 | s = expr_end; |
10101 | continue; | |
10102 | ||
90ecf173 | 10103 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 10104 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10105 | my_getExpression (&offset_expr, s); |
10106 | s = expr_end; | |
10107 | continue; | |
10108 | ||
90ecf173 | 10109 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10110 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10111 | && imm_expr.X_op == O_constant | |
10112 | && (imm_expr.X_add_number < 0 | |
10113 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10114 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10115 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10116 | s = expr_end; |
10117 | continue; | |
10118 | ||
90ecf173 | 10119 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10120 | my_getExpression (&offset_expr, s); |
10121 | s = expr_end; | |
f6688943 | 10122 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10123 | continue; |
10124 | ||
90ecf173 MR |
10125 | case 'N': /* 3-bit branch condition code. */ |
10126 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10127 | rtype = RTYPE_CCC; |
90ecf173 | 10128 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10129 | rtype |= RTYPE_FCC; |
10130 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10131 | break; |
90ecf173 MR |
10132 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10133 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10134 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10135 | && (regno & 1) != 0) |
90ecf173 MR |
10136 | as_warn (_("Condition code register should be even for %s, " |
10137 | "was %d"), | |
20203fb9 | 10138 | str, regno); |
90ecf173 MR |
10139 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10140 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10141 | && (regno & 3) != 0) |
90ecf173 MR |
10142 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10143 | "was %d"), | |
20203fb9 | 10144 | str, regno); |
252b5132 | 10145 | if (*args == 'N') |
bf12938e | 10146 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10147 | else |
bf12938e | 10148 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10149 | continue; |
252b5132 | 10150 | |
156c2f8b NC |
10151 | case 'H': |
10152 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10153 | s += 2; | |
3882b010 | 10154 | if (ISDIGIT (*s)) |
156c2f8b NC |
10155 | { |
10156 | c = 0; | |
10157 | do | |
10158 | { | |
10159 | c *= 10; | |
10160 | c += *s - '0'; | |
10161 | ++s; | |
10162 | } | |
3882b010 | 10163 | while (ISDIGIT (*s)); |
156c2f8b NC |
10164 | } |
10165 | else | |
10166 | c = 8; /* Invalid sel value. */ | |
10167 | ||
10168 | if (c > 7) | |
f71d0d44 | 10169 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10170 | ip->insn_opcode |= c; |
10171 | continue; | |
10172 | ||
60b63b72 RS |
10173 | case 'e': |
10174 | /* Must be at least one digit. */ | |
10175 | my_getExpression (&imm_expr, s); | |
10176 | check_absolute_expr (ip, &imm_expr); | |
10177 | ||
10178 | if ((unsigned long) imm_expr.X_add_number | |
10179 | > (unsigned long) OP_MASK_VECBYTE) | |
10180 | { | |
10181 | as_bad (_("bad byte vector index (%ld)"), | |
10182 | (long) imm_expr.X_add_number); | |
10183 | imm_expr.X_add_number = 0; | |
10184 | } | |
10185 | ||
bf12938e | 10186 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10187 | imm_expr.X_op = O_absent; |
10188 | s = expr_end; | |
10189 | continue; | |
10190 | ||
10191 | case '%': | |
10192 | my_getExpression (&imm_expr, s); | |
10193 | check_absolute_expr (ip, &imm_expr); | |
10194 | ||
10195 | if ((unsigned long) imm_expr.X_add_number | |
10196 | > (unsigned long) OP_MASK_VECALIGN) | |
10197 | { | |
10198 | as_bad (_("bad byte vector index (%ld)"), | |
10199 | (long) imm_expr.X_add_number); | |
10200 | imm_expr.X_add_number = 0; | |
10201 | } | |
10202 | ||
bf12938e | 10203 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10204 | imm_expr.X_op = O_absent; |
10205 | s = expr_end; | |
10206 | continue; | |
10207 | ||
252b5132 | 10208 | default: |
f71d0d44 | 10209 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10210 | internalError (); |
10211 | } | |
10212 | break; | |
10213 | } | |
10214 | /* Args don't match. */ | |
10215 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10216 | !strcmp (insn->name, insn[1].name)) | |
10217 | { | |
10218 | ++insn; | |
10219 | s = argsStart; | |
f71d0d44 | 10220 | insn_error = _("Illegal operands"); |
252b5132 RH |
10221 | continue; |
10222 | } | |
268f6bed | 10223 | if (save_c) |
570de991 | 10224 | *(--argsStart) = save_c; |
f71d0d44 | 10225 | insn_error = _("Illegal operands"); |
252b5132 RH |
10226 | return; |
10227 | } | |
10228 | } | |
10229 | ||
0499d65b TS |
10230 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10231 | ||
252b5132 RH |
10232 | /* This routine assembles an instruction into its binary format when |
10233 | assembling for the mips16. As a side effect, it sets one of the | |
10234 | global variables imm_reloc or offset_reloc to the type of | |
10235 | relocation to do if one of the operands is an address expression. | |
10236 | It also sets mips16_small and mips16_ext if the user explicitly | |
10237 | requested a small or extended instruction. */ | |
10238 | ||
10239 | static void | |
17a2f251 | 10240 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10241 | { |
10242 | char *s; | |
10243 | const char *args; | |
10244 | struct mips_opcode *insn; | |
10245 | char *argsstart; | |
10246 | unsigned int regno; | |
10247 | unsigned int lastregno = 0; | |
10248 | char *s_reset; | |
d6f16593 | 10249 | size_t i; |
252b5132 RH |
10250 | |
10251 | insn_error = NULL; | |
10252 | ||
b34976b6 AM |
10253 | mips16_small = FALSE; |
10254 | mips16_ext = FALSE; | |
252b5132 | 10255 | |
3882b010 | 10256 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10257 | ; |
10258 | switch (*s) | |
10259 | { | |
10260 | case '\0': | |
10261 | break; | |
10262 | ||
10263 | case ' ': | |
10264 | *s++ = '\0'; | |
10265 | break; | |
10266 | ||
10267 | case '.': | |
10268 | if (s[1] == 't' && s[2] == ' ') | |
10269 | { | |
10270 | *s = '\0'; | |
b34976b6 | 10271 | mips16_small = TRUE; |
252b5132 RH |
10272 | s += 3; |
10273 | break; | |
10274 | } | |
10275 | else if (s[1] == 'e' && s[2] == ' ') | |
10276 | { | |
10277 | *s = '\0'; | |
b34976b6 | 10278 | mips16_ext = TRUE; |
252b5132 RH |
10279 | s += 3; |
10280 | break; | |
10281 | } | |
10282 | /* Fall through. */ | |
10283 | default: | |
10284 | insn_error = _("unknown opcode"); | |
10285 | return; | |
10286 | } | |
10287 | ||
10288 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10289 | mips16_small = TRUE; |
252b5132 RH |
10290 | |
10291 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10292 | { | |
10293 | insn_error = _("unrecognized opcode"); | |
10294 | return; | |
10295 | } | |
10296 | ||
10297 | argsstart = s; | |
10298 | for (;;) | |
10299 | { | |
9b3f89ee TS |
10300 | bfd_boolean ok; |
10301 | ||
9c2799c2 | 10302 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10303 | |
037b32b9 | 10304 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10305 | if (! ok) |
10306 | { | |
10307 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10308 | && strcmp (insn->name, insn[1].name) == 0) | |
10309 | { | |
10310 | ++insn; | |
10311 | continue; | |
10312 | } | |
10313 | else | |
10314 | { | |
10315 | if (!insn_error) | |
10316 | { | |
10317 | static char buf[100]; | |
10318 | sprintf (buf, | |
10319 | _("opcode not supported on this processor: %s (%s)"), | |
10320 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10321 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10322 | insn_error = buf; | |
10323 | } | |
10324 | return; | |
10325 | } | |
10326 | } | |
10327 | ||
1e915849 | 10328 | create_insn (ip, insn); |
252b5132 | 10329 | imm_expr.X_op = O_absent; |
f6688943 TS |
10330 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10331 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10332 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10333 | imm2_expr.X_op = O_absent; |
252b5132 | 10334 | offset_expr.X_op = O_absent; |
f6688943 TS |
10335 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10336 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10337 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10338 | for (args = insn->args; 1; ++args) |
10339 | { | |
10340 | int c; | |
10341 | ||
10342 | if (*s == ' ') | |
10343 | ++s; | |
10344 | ||
10345 | /* In this switch statement we call break if we did not find | |
10346 | a match, continue if we did find a match, or return if we | |
10347 | are done. */ | |
10348 | ||
10349 | c = *args; | |
10350 | switch (c) | |
10351 | { | |
10352 | case '\0': | |
10353 | if (*s == '\0') | |
10354 | { | |
10355 | /* Stuff the immediate value in now, if we can. */ | |
10356 | if (imm_expr.X_op == O_constant | |
f6688943 | 10357 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10358 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10359 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10360 | && insn->pinfo != INSN_MACRO) |
10361 | { | |
d6f16593 MR |
10362 | valueT tmp; |
10363 | ||
10364 | switch (*offset_reloc) | |
10365 | { | |
10366 | case BFD_RELOC_MIPS16_HI16_S: | |
10367 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10368 | break; | |
10369 | ||
10370 | case BFD_RELOC_MIPS16_HI16: | |
10371 | tmp = imm_expr.X_add_number >> 16; | |
10372 | break; | |
10373 | ||
10374 | case BFD_RELOC_MIPS16_LO16: | |
10375 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10376 | - 0x8000; | |
10377 | break; | |
10378 | ||
10379 | case BFD_RELOC_UNUSED: | |
10380 | tmp = imm_expr.X_add_number; | |
10381 | break; | |
10382 | ||
10383 | default: | |
10384 | internalError (); | |
10385 | } | |
10386 | *offset_reloc = BFD_RELOC_UNUSED; | |
10387 | ||
c4e7957c | 10388 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10389 | tmp, TRUE, mips16_small, |
252b5132 RH |
10390 | mips16_ext, &ip->insn_opcode, |
10391 | &ip->use_extend, &ip->extend); | |
10392 | imm_expr.X_op = O_absent; | |
f6688943 | 10393 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10394 | } |
10395 | ||
10396 | return; | |
10397 | } | |
10398 | break; | |
10399 | ||
10400 | case ',': | |
10401 | if (*s++ == c) | |
10402 | continue; | |
10403 | s--; | |
10404 | switch (*++args) | |
10405 | { | |
10406 | case 'v': | |
bf12938e | 10407 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10408 | continue; |
10409 | case 'w': | |
bf12938e | 10410 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10411 | continue; |
10412 | } | |
10413 | break; | |
10414 | ||
10415 | case '(': | |
10416 | case ')': | |
10417 | if (*s++ == c) | |
10418 | continue; | |
10419 | break; | |
10420 | ||
10421 | case 'v': | |
10422 | case 'w': | |
10423 | if (s[0] != '$') | |
10424 | { | |
10425 | if (c == 'v') | |
bf12938e | 10426 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10427 | else |
bf12938e | 10428 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10429 | ++args; |
10430 | continue; | |
10431 | } | |
10432 | /* Fall through. */ | |
10433 | case 'x': | |
10434 | case 'y': | |
10435 | case 'z': | |
10436 | case 'Z': | |
10437 | case '0': | |
10438 | case 'S': | |
10439 | case 'R': | |
10440 | case 'X': | |
10441 | case 'Y': | |
707bfff6 TS |
10442 | s_reset = s; |
10443 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10444 | { |
707bfff6 | 10445 | if (c == 'v' || c == 'w') |
85b51719 | 10446 | { |
707bfff6 | 10447 | if (c == 'v') |
a9e24354 | 10448 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10449 | else |
a9e24354 | 10450 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10451 | ++args; |
10452 | continue; | |
85b51719 | 10453 | } |
707bfff6 | 10454 | break; |
252b5132 RH |
10455 | } |
10456 | ||
10457 | if (*s == ' ') | |
10458 | ++s; | |
10459 | if (args[1] != *s) | |
10460 | { | |
10461 | if (c == 'v' || c == 'w') | |
10462 | { | |
10463 | regno = mips16_to_32_reg_map[lastregno]; | |
10464 | s = s_reset; | |
f9419b05 | 10465 | ++args; |
252b5132 RH |
10466 | } |
10467 | } | |
10468 | ||
10469 | switch (c) | |
10470 | { | |
10471 | case 'x': | |
10472 | case 'y': | |
10473 | case 'z': | |
10474 | case 'v': | |
10475 | case 'w': | |
10476 | case 'Z': | |
10477 | regno = mips32_to_16_reg_map[regno]; | |
10478 | break; | |
10479 | ||
10480 | case '0': | |
10481 | if (regno != 0) | |
10482 | regno = ILLEGAL_REG; | |
10483 | break; | |
10484 | ||
10485 | case 'S': | |
10486 | if (regno != SP) | |
10487 | regno = ILLEGAL_REG; | |
10488 | break; | |
10489 | ||
10490 | case 'R': | |
10491 | if (regno != RA) | |
10492 | regno = ILLEGAL_REG; | |
10493 | break; | |
10494 | ||
10495 | case 'X': | |
10496 | case 'Y': | |
741fe287 MR |
10497 | if (regno == AT && mips_opts.at) |
10498 | { | |
10499 | if (mips_opts.at == ATREG) | |
10500 | as_warn (_("used $at without \".set noat\"")); | |
10501 | else | |
10502 | as_warn (_("used $%u with \".set at=$%u\""), | |
10503 | regno, mips_opts.at); | |
10504 | } | |
252b5132 RH |
10505 | break; |
10506 | ||
10507 | default: | |
10508 | internalError (); | |
10509 | } | |
10510 | ||
10511 | if (regno == ILLEGAL_REG) | |
10512 | break; | |
10513 | ||
10514 | switch (c) | |
10515 | { | |
10516 | case 'x': | |
10517 | case 'v': | |
bf12938e | 10518 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10519 | break; |
10520 | case 'y': | |
10521 | case 'w': | |
bf12938e | 10522 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10523 | break; |
10524 | case 'z': | |
bf12938e | 10525 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10526 | break; |
10527 | case 'Z': | |
bf12938e | 10528 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10529 | case '0': |
10530 | case 'S': | |
10531 | case 'R': | |
10532 | break; | |
10533 | case 'X': | |
bf12938e | 10534 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10535 | break; |
10536 | case 'Y': | |
10537 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10538 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10539 | break; |
10540 | default: | |
10541 | internalError (); | |
10542 | } | |
10543 | ||
10544 | lastregno = regno; | |
10545 | continue; | |
10546 | ||
10547 | case 'P': | |
10548 | if (strncmp (s, "$pc", 3) == 0) | |
10549 | { | |
10550 | s += 3; | |
10551 | continue; | |
10552 | } | |
10553 | break; | |
10554 | ||
252b5132 RH |
10555 | case '5': |
10556 | case 'H': | |
10557 | case 'W': | |
10558 | case 'D': | |
10559 | case 'j': | |
252b5132 RH |
10560 | case 'V': |
10561 | case 'C': | |
10562 | case 'U': | |
10563 | case 'k': | |
10564 | case 'K': | |
d6f16593 MR |
10565 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10566 | if (i > 0) | |
252b5132 | 10567 | { |
d6f16593 | 10568 | if (imm_expr.X_op != O_constant) |
252b5132 | 10569 | { |
b34976b6 | 10570 | mips16_ext = TRUE; |
b34976b6 | 10571 | ip->use_extend = TRUE; |
252b5132 | 10572 | ip->extend = 0; |
252b5132 | 10573 | } |
d6f16593 MR |
10574 | else |
10575 | { | |
10576 | /* We need to relax this instruction. */ | |
10577 | *offset_reloc = *imm_reloc; | |
10578 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10579 | } | |
10580 | s = expr_end; | |
10581 | continue; | |
252b5132 | 10582 | } |
d6f16593 MR |
10583 | *imm_reloc = BFD_RELOC_UNUSED; |
10584 | /* Fall through. */ | |
10585 | case '<': | |
10586 | case '>': | |
10587 | case '[': | |
10588 | case ']': | |
10589 | case '4': | |
10590 | case '8': | |
10591 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10592 | if (imm_expr.X_op == O_register) |
10593 | { | |
10594 | /* What we thought was an expression turned out to | |
10595 | be a register. */ | |
10596 | ||
10597 | if (s[0] == '(' && args[1] == '(') | |
10598 | { | |
10599 | /* It looks like the expression was omitted | |
10600 | before a register indirection, which means | |
10601 | that the expression is implicitly zero. We | |
10602 | still set up imm_expr, so that we handle | |
10603 | explicit extensions correctly. */ | |
10604 | imm_expr.X_op = O_constant; | |
10605 | imm_expr.X_add_number = 0; | |
f6688943 | 10606 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10607 | continue; |
10608 | } | |
10609 | ||
10610 | break; | |
10611 | } | |
10612 | ||
10613 | /* We need to relax this instruction. */ | |
f6688943 | 10614 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10615 | s = expr_end; |
10616 | continue; | |
10617 | ||
10618 | case 'p': | |
10619 | case 'q': | |
10620 | case 'A': | |
10621 | case 'B': | |
10622 | case 'E': | |
10623 | /* We use offset_reloc rather than imm_reloc for the PC | |
10624 | relative operands. This lets macros with both | |
10625 | immediate and address operands work correctly. */ | |
10626 | my_getExpression (&offset_expr, s); | |
10627 | ||
10628 | if (offset_expr.X_op == O_register) | |
10629 | break; | |
10630 | ||
10631 | /* We need to relax this instruction. */ | |
f6688943 | 10632 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10633 | s = expr_end; |
10634 | continue; | |
10635 | ||
10636 | case '6': /* break code */ | |
10637 | my_getExpression (&imm_expr, s); | |
10638 | check_absolute_expr (ip, &imm_expr); | |
10639 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10640 | as_warn (_("Invalid value for `%s' (%lu)"), |
10641 | ip->insn_mo->name, | |
10642 | (unsigned long) imm_expr.X_add_number); | |
10643 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10644 | imm_expr.X_op = O_absent; |
10645 | s = expr_end; | |
10646 | continue; | |
10647 | ||
10648 | case 'a': /* 26 bit address */ | |
10649 | my_getExpression (&offset_expr, s); | |
10650 | s = expr_end; | |
f6688943 | 10651 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10652 | ip->insn_opcode <<= 16; |
10653 | continue; | |
10654 | ||
10655 | case 'l': /* register list for entry macro */ | |
10656 | case 'L': /* register list for exit macro */ | |
10657 | { | |
10658 | int mask; | |
10659 | ||
10660 | if (c == 'l') | |
10661 | mask = 0; | |
10662 | else | |
10663 | mask = 7 << 3; | |
10664 | while (*s != '\0') | |
10665 | { | |
707bfff6 | 10666 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10667 | |
10668 | while (*s == ' ' || *s == ',') | |
10669 | ++s; | |
707bfff6 | 10670 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10671 | freg = 0; |
707bfff6 TS |
10672 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10673 | freg = 1; | |
252b5132 RH |
10674 | else |
10675 | { | |
707bfff6 TS |
10676 | as_bad (_("can't parse register list")); |
10677 | break; | |
252b5132 RH |
10678 | } |
10679 | if (*s == ' ') | |
10680 | ++s; | |
10681 | if (*s != '-') | |
10682 | reg2 = reg1; | |
10683 | else | |
10684 | { | |
10685 | ++s; | |
707bfff6 TS |
10686 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10687 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10688 | { |
707bfff6 TS |
10689 | as_bad (_("invalid register list")); |
10690 | break; | |
252b5132 RH |
10691 | } |
10692 | } | |
10693 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10694 | { | |
10695 | mask &= ~ (7 << 3); | |
10696 | mask |= 5 << 3; | |
10697 | } | |
10698 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10699 | { | |
10700 | mask &= ~ (7 << 3); | |
10701 | mask |= 6 << 3; | |
10702 | } | |
10703 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10704 | mask |= (reg2 - 3) << 3; | |
10705 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10706 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10707 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10708 | mask |= 1; |
10709 | else | |
10710 | { | |
10711 | as_bad (_("invalid register list")); | |
10712 | break; | |
10713 | } | |
10714 | } | |
10715 | /* The mask is filled in in the opcode table for the | |
10716 | benefit of the disassembler. We remove it before | |
10717 | applying the actual mask. */ | |
10718 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10719 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10720 | } | |
10721 | continue; | |
10722 | ||
0499d65b TS |
10723 | case 'm': /* Register list for save insn. */ |
10724 | case 'M': /* Register list for restore insn. */ | |
10725 | { | |
10726 | int opcode = 0; | |
10727 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10728 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10729 | |
10730 | while (*s != '\0') | |
10731 | { | |
10732 | unsigned int reg1, reg2; | |
10733 | ||
10734 | SKIP_SPACE_TABS (s); | |
10735 | while (*s == ',') | |
10736 | ++s; | |
10737 | SKIP_SPACE_TABS (s); | |
10738 | ||
10739 | my_getExpression (&imm_expr, s); | |
10740 | if (imm_expr.X_op == O_constant) | |
10741 | { | |
10742 | /* Handle the frame size. */ | |
10743 | if (seen_framesz) | |
10744 | { | |
10745 | as_bad (_("more than one frame size in list")); | |
10746 | break; | |
10747 | } | |
10748 | seen_framesz = 1; | |
10749 | framesz = imm_expr.X_add_number; | |
10750 | imm_expr.X_op = O_absent; | |
10751 | s = expr_end; | |
10752 | continue; | |
10753 | } | |
10754 | ||
707bfff6 | 10755 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10756 | { |
10757 | as_bad (_("can't parse register list")); | |
10758 | break; | |
10759 | } | |
0499d65b | 10760 | |
707bfff6 TS |
10761 | while (*s == ' ') |
10762 | ++s; | |
10763 | ||
0499d65b TS |
10764 | if (*s != '-') |
10765 | reg2 = reg1; | |
10766 | else | |
10767 | { | |
10768 | ++s; | |
707bfff6 TS |
10769 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10770 | || reg2 < reg1) | |
0499d65b TS |
10771 | { |
10772 | as_bad (_("can't parse register list")); | |
10773 | break; | |
10774 | } | |
0499d65b TS |
10775 | } |
10776 | ||
10777 | while (reg1 <= reg2) | |
10778 | { | |
10779 | if (reg1 >= 4 && reg1 <= 7) | |
10780 | { | |
3a93f742 | 10781 | if (!seen_framesz) |
0499d65b | 10782 | /* args $a0-$a3 */ |
91d6fa6a | 10783 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10784 | else |
10785 | /* statics $a0-$a3 */ | |
10786 | statics |= 1 << (reg1 - 4); | |
10787 | } | |
10788 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10789 | { | |
10790 | /* $s0-$s8 */ | |
10791 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10792 | } | |
10793 | else if (reg1 == 31) | |
10794 | { | |
10795 | /* Add $ra to insn. */ | |
10796 | opcode |= 0x40; | |
10797 | } | |
10798 | else | |
10799 | { | |
10800 | as_bad (_("unexpected register in list")); | |
10801 | break; | |
10802 | } | |
10803 | if (++reg1 == 24) | |
10804 | reg1 = 30; | |
10805 | } | |
10806 | } | |
10807 | ||
10808 | /* Encode args/statics combination. */ | |
91d6fa6a | 10809 | if (nargs & statics) |
0499d65b | 10810 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10811 | else if (nargs == 0xf) |
0499d65b TS |
10812 | /* All $a0-$a3 are args. */ |
10813 | opcode |= MIPS16_ALL_ARGS << 16; | |
10814 | else if (statics == 0xf) | |
10815 | /* All $a0-$a3 are statics. */ | |
10816 | opcode |= MIPS16_ALL_STATICS << 16; | |
10817 | else | |
10818 | { | |
10819 | int narg = 0, nstat = 0; | |
10820 | ||
10821 | /* Count arg registers. */ | |
91d6fa6a | 10822 | while (nargs & 0x1) |
0499d65b | 10823 | { |
91d6fa6a | 10824 | nargs >>= 1; |
0499d65b TS |
10825 | narg++; |
10826 | } | |
91d6fa6a | 10827 | if (nargs != 0) |
0499d65b TS |
10828 | as_bad (_("invalid arg register list")); |
10829 | ||
10830 | /* Count static registers. */ | |
10831 | while (statics & 0x8) | |
10832 | { | |
10833 | statics = (statics << 1) & 0xf; | |
10834 | nstat++; | |
10835 | } | |
10836 | if (statics != 0) | |
10837 | as_bad (_("invalid static register list")); | |
10838 | ||
10839 | /* Encode args/statics. */ | |
10840 | opcode |= ((narg << 2) | nstat) << 16; | |
10841 | } | |
10842 | ||
10843 | /* Encode $s0/$s1. */ | |
10844 | if (sregs & (1 << 0)) /* $s0 */ | |
10845 | opcode |= 0x20; | |
10846 | if (sregs & (1 << 1)) /* $s1 */ | |
10847 | opcode |= 0x10; | |
10848 | sregs >>= 2; | |
10849 | ||
10850 | if (sregs != 0) | |
10851 | { | |
10852 | /* Count regs $s2-$s8. */ | |
10853 | int nsreg = 0; | |
10854 | while (sregs & 1) | |
10855 | { | |
10856 | sregs >>= 1; | |
10857 | nsreg++; | |
10858 | } | |
10859 | if (sregs != 0) | |
10860 | as_bad (_("invalid static register list")); | |
10861 | /* Encode $s2-$s8. */ | |
10862 | opcode |= nsreg << 24; | |
10863 | } | |
10864 | ||
10865 | /* Encode frame size. */ | |
10866 | if (!seen_framesz) | |
10867 | as_bad (_("missing frame size")); | |
10868 | else if ((framesz & 7) != 0 || framesz < 0 | |
10869 | || framesz > 0xff * 8) | |
10870 | as_bad (_("invalid frame size")); | |
10871 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10872 | { | |
10873 | framesz /= 8; | |
10874 | opcode |= (((framesz & 0xf0) << 16) | |
10875 | | (framesz & 0x0f)); | |
10876 | } | |
10877 | ||
10878 | /* Finally build the instruction. */ | |
10879 | if ((opcode >> 16) != 0 || framesz == 0) | |
10880 | { | |
10881 | ip->use_extend = TRUE; | |
10882 | ip->extend = opcode >> 16; | |
10883 | } | |
10884 | ip->insn_opcode |= opcode & 0x7f; | |
10885 | } | |
10886 | continue; | |
10887 | ||
252b5132 RH |
10888 | case 'e': /* extend code */ |
10889 | my_getExpression (&imm_expr, s); | |
10890 | check_absolute_expr (ip, &imm_expr); | |
10891 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10892 | { | |
10893 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10894 | ip->insn_mo->name, | |
10895 | (unsigned long) imm_expr.X_add_number); | |
10896 | imm_expr.X_add_number &= 0x7ff; | |
10897 | } | |
10898 | ip->insn_opcode |= imm_expr.X_add_number; | |
10899 | imm_expr.X_op = O_absent; | |
10900 | s = expr_end; | |
10901 | continue; | |
10902 | ||
10903 | default: | |
10904 | internalError (); | |
10905 | } | |
10906 | break; | |
10907 | } | |
10908 | ||
10909 | /* Args don't match. */ | |
10910 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10911 | strcmp (insn->name, insn[1].name) == 0) | |
10912 | { | |
10913 | ++insn; | |
10914 | s = argsstart; | |
10915 | continue; | |
10916 | } | |
10917 | ||
10918 | insn_error = _("illegal operands"); | |
10919 | ||
10920 | return; | |
10921 | } | |
10922 | } | |
10923 | ||
10924 | /* This structure holds information we know about a mips16 immediate | |
10925 | argument type. */ | |
10926 | ||
e972090a NC |
10927 | struct mips16_immed_operand |
10928 | { | |
252b5132 RH |
10929 | /* The type code used in the argument string in the opcode table. */ |
10930 | int type; | |
10931 | /* The number of bits in the short form of the opcode. */ | |
10932 | int nbits; | |
10933 | /* The number of bits in the extended form of the opcode. */ | |
10934 | int extbits; | |
10935 | /* The amount by which the short form is shifted when it is used; | |
10936 | for example, the sw instruction has a shift count of 2. */ | |
10937 | int shift; | |
10938 | /* The amount by which the short form is shifted when it is stored | |
10939 | into the instruction code. */ | |
10940 | int op_shift; | |
10941 | /* Non-zero if the short form is unsigned. */ | |
10942 | int unsp; | |
10943 | /* Non-zero if the extended form is unsigned. */ | |
10944 | int extu; | |
10945 | /* Non-zero if the value is PC relative. */ | |
10946 | int pcrel; | |
10947 | }; | |
10948 | ||
10949 | /* The mips16 immediate operand types. */ | |
10950 | ||
10951 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10952 | { | |
10953 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10954 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10955 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10956 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10957 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10958 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10959 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10960 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10961 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10962 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10963 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10964 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10965 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10966 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10967 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10968 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10969 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10970 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10971 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10972 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10973 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10974 | }; | |
10975 | ||
10976 | #define MIPS16_NUM_IMMED \ | |
10977 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10978 | ||
10979 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10980 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10981 | whether an extended value is needed; if one is needed, it sets | |
10982 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10983 | If SMALL is true, an unextended opcode was explicitly requested. | |
10984 | If EXT is true, an extended opcode was explicitly requested. If | |
10985 | WARN is true, warn if EXT does not match reality. */ | |
10986 | ||
10987 | static void | |
17a2f251 TS |
10988 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10989 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10990 | unsigned long *insn, bfd_boolean *use_extend, | |
10991 | unsigned short *extend) | |
252b5132 | 10992 | { |
3994f87e | 10993 | const struct mips16_immed_operand *op; |
252b5132 | 10994 | int mintiny, maxtiny; |
b34976b6 | 10995 | bfd_boolean needext; |
252b5132 RH |
10996 | |
10997 | op = mips16_immed_operands; | |
10998 | while (op->type != type) | |
10999 | { | |
11000 | ++op; | |
9c2799c2 | 11001 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
11002 | } |
11003 | ||
11004 | if (op->unsp) | |
11005 | { | |
11006 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11007 | { | |
11008 | mintiny = 1; | |
11009 | maxtiny = 1 << op->nbits; | |
11010 | } | |
11011 | else | |
11012 | { | |
11013 | mintiny = 0; | |
11014 | maxtiny = (1 << op->nbits) - 1; | |
11015 | } | |
11016 | } | |
11017 | else | |
11018 | { | |
11019 | mintiny = - (1 << (op->nbits - 1)); | |
11020 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11021 | } | |
11022 | ||
11023 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11024 | if (type == 'p' || type == 'q') | |
11025 | val /= 2; | |
11026 | ||
11027 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11028 | || val < (mintiny << op->shift) | |
11029 | || val > (maxtiny << op->shift)) | |
b34976b6 | 11030 | needext = TRUE; |
252b5132 | 11031 | else |
b34976b6 | 11032 | needext = FALSE; |
252b5132 RH |
11033 | |
11034 | if (warn && ext && ! needext) | |
beae10d5 KH |
11035 | as_warn_where (file, line, |
11036 | _("extended operand requested but not required")); | |
252b5132 RH |
11037 | if (small && needext) |
11038 | as_bad_where (file, line, _("invalid unextended operand value")); | |
11039 | ||
11040 | if (small || (! ext && ! needext)) | |
11041 | { | |
11042 | int insnval; | |
11043 | ||
b34976b6 | 11044 | *use_extend = FALSE; |
252b5132 RH |
11045 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11046 | insnval <<= op->op_shift; | |
11047 | *insn |= insnval; | |
11048 | } | |
11049 | else | |
11050 | { | |
11051 | long minext, maxext; | |
11052 | int extval; | |
11053 | ||
11054 | if (op->extu) | |
11055 | { | |
11056 | minext = 0; | |
11057 | maxext = (1 << op->extbits) - 1; | |
11058 | } | |
11059 | else | |
11060 | { | |
11061 | minext = - (1 << (op->extbits - 1)); | |
11062 | maxext = (1 << (op->extbits - 1)) - 1; | |
11063 | } | |
11064 | if (val < minext || val > maxext) | |
11065 | as_bad_where (file, line, | |
11066 | _("operand value out of range for instruction")); | |
11067 | ||
b34976b6 | 11068 | *use_extend = TRUE; |
252b5132 RH |
11069 | if (op->extbits == 16) |
11070 | { | |
11071 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11072 | val &= 0x1f; | |
11073 | } | |
11074 | else if (op->extbits == 15) | |
11075 | { | |
11076 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11077 | val &= 0xf; | |
11078 | } | |
11079 | else | |
11080 | { | |
11081 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11082 | val = 0; | |
11083 | } | |
11084 | ||
11085 | *extend = (unsigned short) extval; | |
11086 | *insn |= val; | |
11087 | } | |
11088 | } | |
11089 | \f | |
d6f16593 | 11090 | struct percent_op_match |
ad8d3bb3 | 11091 | { |
5e0116d5 RS |
11092 | const char *str; |
11093 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11094 | }; |
11095 | ||
11096 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11097 | { |
5e0116d5 | 11098 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11099 | #ifdef OBJ_ELF |
5e0116d5 RS |
11100 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11101 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11102 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11103 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11104 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11105 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11106 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11107 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11108 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11109 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11110 | {"%half", BFD_RELOC_16}, | |
11111 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11112 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11113 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11114 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11115 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11116 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11117 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11118 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11119 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11120 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11121 | #endif |
5e0116d5 | 11122 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11123 | }; |
11124 | ||
d6f16593 MR |
11125 | static const struct percent_op_match mips16_percent_op[] = |
11126 | { | |
11127 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11128 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11129 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11130 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11131 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11132 | }; | |
11133 | ||
252b5132 | 11134 | |
5e0116d5 RS |
11135 | /* Return true if *STR points to a relocation operator. When returning true, |
11136 | move *STR over the operator and store its relocation code in *RELOC. | |
11137 | Leave both *STR and *RELOC alone when returning false. */ | |
11138 | ||
11139 | static bfd_boolean | |
17a2f251 | 11140 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11141 | { |
d6f16593 MR |
11142 | const struct percent_op_match *percent_op; |
11143 | size_t limit, i; | |
11144 | ||
11145 | if (mips_opts.mips16) | |
11146 | { | |
11147 | percent_op = mips16_percent_op; | |
11148 | limit = ARRAY_SIZE (mips16_percent_op); | |
11149 | } | |
11150 | else | |
11151 | { | |
11152 | percent_op = mips_percent_op; | |
11153 | limit = ARRAY_SIZE (mips_percent_op); | |
11154 | } | |
76b3015f | 11155 | |
d6f16593 | 11156 | for (i = 0; i < limit; i++) |
5e0116d5 | 11157 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11158 | { |
3f98094e DJ |
11159 | int len = strlen (percent_op[i].str); |
11160 | ||
11161 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11162 | continue; | |
11163 | ||
5e0116d5 RS |
11164 | *str += strlen (percent_op[i].str); |
11165 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11166 | |
5e0116d5 RS |
11167 | /* Check whether the output BFD supports this relocation. |
11168 | If not, issue an error and fall back on something safe. */ | |
11169 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11170 | { |
20203fb9 | 11171 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11172 | percent_op[i].str); |
01a3f561 | 11173 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11174 | } |
5e0116d5 | 11175 | return TRUE; |
394f9b3a | 11176 | } |
5e0116d5 | 11177 | return FALSE; |
394f9b3a | 11178 | } |
ad8d3bb3 | 11179 | |
ad8d3bb3 | 11180 | |
5e0116d5 RS |
11181 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11182 | expression in *EP and the relocations in the array starting | |
11183 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11184 | |
01a3f561 | 11185 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11186 | |
5e0116d5 | 11187 | static size_t |
17a2f251 TS |
11188 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11189 | char *str) | |
ad8d3bb3 | 11190 | { |
5e0116d5 RS |
11191 | bfd_reloc_code_real_type reversed_reloc[3]; |
11192 | size_t reloc_index, i; | |
09b8f35a RS |
11193 | int crux_depth, str_depth; |
11194 | char *crux; | |
5e0116d5 RS |
11195 | |
11196 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11197 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11198 | of the main expression and with CRUX_DEPTH containing the number | |
11199 | of open brackets at that point. */ | |
11200 | reloc_index = -1; | |
11201 | str_depth = 0; | |
11202 | do | |
fb1b3232 | 11203 | { |
09b8f35a RS |
11204 | reloc_index++; |
11205 | crux = str; | |
11206 | crux_depth = str_depth; | |
11207 | ||
11208 | /* Skip over whitespace and brackets, keeping count of the number | |
11209 | of brackets. */ | |
11210 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11211 | if (*str++ == '(') | |
11212 | str_depth++; | |
5e0116d5 | 11213 | } |
09b8f35a RS |
11214 | while (*str == '%' |
11215 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11216 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11217 | |
09b8f35a | 11218 | my_getExpression (ep, crux); |
5e0116d5 | 11219 | str = expr_end; |
394f9b3a | 11220 | |
5e0116d5 | 11221 | /* Match every open bracket. */ |
09b8f35a | 11222 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11223 | if (*str++ == ')') |
09b8f35a | 11224 | crux_depth--; |
394f9b3a | 11225 | |
09b8f35a | 11226 | if (crux_depth > 0) |
20203fb9 | 11227 | as_bad (_("unclosed '('")); |
394f9b3a | 11228 | |
5e0116d5 | 11229 | expr_end = str; |
252b5132 | 11230 | |
01a3f561 | 11231 | if (reloc_index != 0) |
64bdfcaf RS |
11232 | { |
11233 | prev_reloc_op_frag = frag_now; | |
11234 | for (i = 0; i < reloc_index; i++) | |
11235 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11236 | } | |
fb1b3232 | 11237 | |
5e0116d5 | 11238 | return reloc_index; |
252b5132 RH |
11239 | } |
11240 | ||
11241 | static void | |
17a2f251 | 11242 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11243 | { |
11244 | char *save_in; | |
11245 | ||
11246 | save_in = input_line_pointer; | |
11247 | input_line_pointer = str; | |
11248 | expression (ep); | |
11249 | expr_end = input_line_pointer; | |
11250 | input_line_pointer = save_in; | |
252b5132 RH |
11251 | } |
11252 | ||
252b5132 | 11253 | char * |
17a2f251 | 11254 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11255 | { |
499ac353 | 11256 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11257 | } |
11258 | ||
11259 | void | |
17a2f251 | 11260 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11261 | { |
11262 | if (target_big_endian) | |
11263 | number_to_chars_bigendian (buf, val, n); | |
11264 | else | |
11265 | number_to_chars_littleendian (buf, val, n); | |
11266 | } | |
11267 | \f | |
ae948b86 | 11268 | #ifdef OBJ_ELF |
e013f690 TS |
11269 | static int support_64bit_objects(void) |
11270 | { | |
11271 | const char **list, **l; | |
aa3d8fdf | 11272 | int yes; |
e013f690 TS |
11273 | |
11274 | list = bfd_target_list (); | |
11275 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
11276 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
11277 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 11278 | break; |
aa3d8fdf | 11279 | yes = (*l != NULL); |
e013f690 | 11280 | free (list); |
aa3d8fdf | 11281 | return yes; |
e013f690 | 11282 | } |
ae948b86 | 11283 | #endif /* OBJ_ELF */ |
e013f690 | 11284 | |
78849248 | 11285 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11286 | |
23fce1e3 NC |
11287 | enum options |
11288 | { | |
11289 | OPTION_MARCH = OPTION_MD_BASE, | |
11290 | OPTION_MTUNE, | |
11291 | OPTION_MIPS1, | |
11292 | OPTION_MIPS2, | |
11293 | OPTION_MIPS3, | |
11294 | OPTION_MIPS4, | |
11295 | OPTION_MIPS5, | |
11296 | OPTION_MIPS32, | |
11297 | OPTION_MIPS64, | |
11298 | OPTION_MIPS32R2, | |
11299 | OPTION_MIPS64R2, | |
11300 | OPTION_MIPS16, | |
11301 | OPTION_NO_MIPS16, | |
11302 | OPTION_MIPS3D, | |
11303 | OPTION_NO_MIPS3D, | |
11304 | OPTION_MDMX, | |
11305 | OPTION_NO_MDMX, | |
11306 | OPTION_DSP, | |
11307 | OPTION_NO_DSP, | |
11308 | OPTION_MT, | |
11309 | OPTION_NO_MT, | |
11310 | OPTION_SMARTMIPS, | |
11311 | OPTION_NO_SMARTMIPS, | |
11312 | OPTION_DSPR2, | |
11313 | OPTION_NO_DSPR2, | |
11314 | OPTION_COMPAT_ARCH_BASE, | |
11315 | OPTION_M4650, | |
11316 | OPTION_NO_M4650, | |
11317 | OPTION_M4010, | |
11318 | OPTION_NO_M4010, | |
11319 | OPTION_M4100, | |
11320 | OPTION_NO_M4100, | |
11321 | OPTION_M3900, | |
11322 | OPTION_NO_M3900, | |
11323 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11324 | OPTION_MNO_7000_HILO_FIX, |
11325 | OPTION_FIX_24K, | |
11326 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11327 | OPTION_FIX_LOONGSON2F_JUMP, |
11328 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11329 | OPTION_FIX_LOONGSON2F_NOP, | |
11330 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11331 | OPTION_FIX_VR4120, |
11332 | OPTION_NO_FIX_VR4120, | |
11333 | OPTION_FIX_VR4130, | |
11334 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11335 | OPTION_FIX_CN63XXP1, |
11336 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11337 | OPTION_TRAP, |
11338 | OPTION_BREAK, | |
11339 | OPTION_EB, | |
11340 | OPTION_EL, | |
11341 | OPTION_FP32, | |
11342 | OPTION_GP32, | |
11343 | OPTION_CONSTRUCT_FLOATS, | |
11344 | OPTION_NO_CONSTRUCT_FLOATS, | |
11345 | OPTION_FP64, | |
11346 | OPTION_GP64, | |
11347 | OPTION_RELAX_BRANCH, | |
11348 | OPTION_NO_RELAX_BRANCH, | |
11349 | OPTION_MSHARED, | |
11350 | OPTION_MNO_SHARED, | |
11351 | OPTION_MSYM32, | |
11352 | OPTION_MNO_SYM32, | |
11353 | OPTION_SOFT_FLOAT, | |
11354 | OPTION_HARD_FLOAT, | |
11355 | OPTION_SINGLE_FLOAT, | |
11356 | OPTION_DOUBLE_FLOAT, | |
11357 | OPTION_32, | |
11358 | #ifdef OBJ_ELF | |
11359 | OPTION_CALL_SHARED, | |
11360 | OPTION_CALL_NONPIC, | |
11361 | OPTION_NON_SHARED, | |
11362 | OPTION_XGOT, | |
11363 | OPTION_MABI, | |
11364 | OPTION_N32, | |
11365 | OPTION_64, | |
11366 | OPTION_MDEBUG, | |
11367 | OPTION_NO_MDEBUG, | |
11368 | OPTION_PDR, | |
11369 | OPTION_NO_PDR, | |
11370 | OPTION_MVXWORKS_PIC, | |
11371 | #endif /* OBJ_ELF */ | |
11372 | OPTION_END_OF_ENUM | |
11373 | }; | |
11374 | ||
e972090a NC |
11375 | struct option md_longopts[] = |
11376 | { | |
f9b4148d | 11377 | /* Options which specify architecture. */ |
f9b4148d | 11378 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11379 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11380 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11381 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11382 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11383 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11384 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11385 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11386 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11387 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11388 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11389 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11390 | |
11391 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11392 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11393 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11394 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11395 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11396 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11397 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11398 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11399 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11400 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11401 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11402 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11403 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11404 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11405 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11406 | |
11407 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11408 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11409 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11410 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11411 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11412 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11413 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11414 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11415 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11416 | ||
11417 | /* Options which enable bug fixes. */ | |
f9b4148d | 11418 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11419 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11420 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11421 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11422 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11423 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11424 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11425 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11426 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11427 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11428 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11429 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11430 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11431 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11432 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11433 | |
11434 | /* Miscellaneous options. */ | |
252b5132 RH |
11435 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11436 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11437 | {"break", no_argument, NULL, OPTION_BREAK}, |
11438 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11439 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11440 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11441 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11442 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11443 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11444 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11445 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11446 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11447 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11448 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11449 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11450 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11451 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11452 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11453 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11454 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11455 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11456 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11457 | |
11458 | /* Strictly speaking this next option is ELF specific, | |
11459 | but we allow it for other ports as well in order to | |
11460 | make testing easier. */ | |
11461 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11462 | |
f9b4148d | 11463 | /* ELF-specific options. */ |
156c2f8b | 11464 | #ifdef OBJ_ELF |
156c2f8b NC |
11465 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11466 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11467 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11468 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11469 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11470 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11471 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11472 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11473 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11474 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11475 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11476 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11477 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11478 | #endif /* OBJ_ELF */ |
f9b4148d | 11479 | |
252b5132 RH |
11480 | {NULL, no_argument, NULL, 0} |
11481 | }; | |
156c2f8b | 11482 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11483 | |
316f5878 RS |
11484 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11485 | NEW_VALUE. Warn if another value was already specified. Note: | |
11486 | we have to defer parsing the -march and -mtune arguments in order | |
11487 | to handle 'from-abi' correctly, since the ABI might be specified | |
11488 | in a later argument. */ | |
11489 | ||
11490 | static void | |
17a2f251 | 11491 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11492 | { |
11493 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11494 | as_warn (_("A different %s was already specified, is now %s"), | |
11495 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11496 | new_value); | |
11497 | ||
11498 | *string_ptr = new_value; | |
11499 | } | |
11500 | ||
252b5132 | 11501 | int |
17a2f251 | 11502 | md_parse_option (int c, char *arg) |
252b5132 RH |
11503 | { |
11504 | switch (c) | |
11505 | { | |
119d663a NC |
11506 | case OPTION_CONSTRUCT_FLOATS: |
11507 | mips_disable_float_construction = 0; | |
11508 | break; | |
bdaaa2e1 | 11509 | |
119d663a NC |
11510 | case OPTION_NO_CONSTRUCT_FLOATS: |
11511 | mips_disable_float_construction = 1; | |
11512 | break; | |
bdaaa2e1 | 11513 | |
252b5132 RH |
11514 | case OPTION_TRAP: |
11515 | mips_trap = 1; | |
11516 | break; | |
11517 | ||
11518 | case OPTION_BREAK: | |
11519 | mips_trap = 0; | |
11520 | break; | |
11521 | ||
11522 | case OPTION_EB: | |
11523 | target_big_endian = 1; | |
11524 | break; | |
11525 | ||
11526 | case OPTION_EL: | |
11527 | target_big_endian = 0; | |
11528 | break; | |
11529 | ||
11530 | case 'O': | |
4ffff32f TS |
11531 | if (arg == NULL) |
11532 | mips_optimize = 1; | |
11533 | else if (arg[0] == '0') | |
11534 | mips_optimize = 0; | |
11535 | else if (arg[0] == '1') | |
252b5132 RH |
11536 | mips_optimize = 1; |
11537 | else | |
11538 | mips_optimize = 2; | |
11539 | break; | |
11540 | ||
11541 | case 'g': | |
11542 | if (arg == NULL) | |
11543 | mips_debug = 2; | |
11544 | else | |
11545 | mips_debug = atoi (arg); | |
252b5132 RH |
11546 | break; |
11547 | ||
11548 | case OPTION_MIPS1: | |
316f5878 | 11549 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11550 | break; |
11551 | ||
11552 | case OPTION_MIPS2: | |
316f5878 | 11553 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11554 | break; |
11555 | ||
11556 | case OPTION_MIPS3: | |
316f5878 | 11557 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11558 | break; |
11559 | ||
11560 | case OPTION_MIPS4: | |
316f5878 | 11561 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11562 | break; |
11563 | ||
84ea6cf2 | 11564 | case OPTION_MIPS5: |
316f5878 | 11565 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11566 | break; |
11567 | ||
e7af610e | 11568 | case OPTION_MIPS32: |
316f5878 | 11569 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11570 | break; |
11571 | ||
af7ee8bf CD |
11572 | case OPTION_MIPS32R2: |
11573 | file_mips_isa = ISA_MIPS32R2; | |
11574 | break; | |
11575 | ||
5f74bc13 CD |
11576 | case OPTION_MIPS64R2: |
11577 | file_mips_isa = ISA_MIPS64R2; | |
11578 | break; | |
11579 | ||
84ea6cf2 | 11580 | case OPTION_MIPS64: |
316f5878 | 11581 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11582 | break; |
11583 | ||
ec68c924 | 11584 | case OPTION_MTUNE: |
316f5878 RS |
11585 | mips_set_option_string (&mips_tune_string, arg); |
11586 | break; | |
ec68c924 | 11587 | |
316f5878 RS |
11588 | case OPTION_MARCH: |
11589 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11590 | break; |
11591 | ||
11592 | case OPTION_M4650: | |
316f5878 RS |
11593 | mips_set_option_string (&mips_arch_string, "4650"); |
11594 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11595 | break; |
11596 | ||
11597 | case OPTION_NO_M4650: | |
11598 | break; | |
11599 | ||
11600 | case OPTION_M4010: | |
316f5878 RS |
11601 | mips_set_option_string (&mips_arch_string, "4010"); |
11602 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11603 | break; |
11604 | ||
11605 | case OPTION_NO_M4010: | |
11606 | break; | |
11607 | ||
11608 | case OPTION_M4100: | |
316f5878 RS |
11609 | mips_set_option_string (&mips_arch_string, "4100"); |
11610 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11611 | break; |
11612 | ||
11613 | case OPTION_NO_M4100: | |
11614 | break; | |
11615 | ||
252b5132 | 11616 | case OPTION_M3900: |
316f5878 RS |
11617 | mips_set_option_string (&mips_arch_string, "3900"); |
11618 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11619 | break; |
bdaaa2e1 | 11620 | |
252b5132 RH |
11621 | case OPTION_NO_M3900: |
11622 | break; | |
11623 | ||
deec1734 CD |
11624 | case OPTION_MDMX: |
11625 | mips_opts.ase_mdmx = 1; | |
11626 | break; | |
11627 | ||
11628 | case OPTION_NO_MDMX: | |
11629 | mips_opts.ase_mdmx = 0; | |
11630 | break; | |
11631 | ||
74cd071d CF |
11632 | case OPTION_DSP: |
11633 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11634 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11635 | break; |
11636 | ||
11637 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11638 | mips_opts.ase_dsp = 0; |
11639 | mips_opts.ase_dspr2 = 0; | |
11640 | break; | |
11641 | ||
11642 | case OPTION_DSPR2: | |
11643 | mips_opts.ase_dspr2 = 1; | |
11644 | mips_opts.ase_dsp = 1; | |
11645 | break; | |
11646 | ||
11647 | case OPTION_NO_DSPR2: | |
11648 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11649 | mips_opts.ase_dsp = 0; |
11650 | break; | |
11651 | ||
ef2e4d86 CF |
11652 | case OPTION_MT: |
11653 | mips_opts.ase_mt = 1; | |
11654 | break; | |
11655 | ||
11656 | case OPTION_NO_MT: | |
11657 | mips_opts.ase_mt = 0; | |
11658 | break; | |
11659 | ||
252b5132 RH |
11660 | case OPTION_MIPS16: |
11661 | mips_opts.mips16 = 1; | |
7d10b47d | 11662 | mips_no_prev_insn (); |
252b5132 RH |
11663 | break; |
11664 | ||
11665 | case OPTION_NO_MIPS16: | |
11666 | mips_opts.mips16 = 0; | |
7d10b47d | 11667 | mips_no_prev_insn (); |
252b5132 RH |
11668 | break; |
11669 | ||
1f25f5d3 CD |
11670 | case OPTION_MIPS3D: |
11671 | mips_opts.ase_mips3d = 1; | |
11672 | break; | |
11673 | ||
11674 | case OPTION_NO_MIPS3D: | |
11675 | mips_opts.ase_mips3d = 0; | |
11676 | break; | |
11677 | ||
e16bfa71 TS |
11678 | case OPTION_SMARTMIPS: |
11679 | mips_opts.ase_smartmips = 1; | |
11680 | break; | |
11681 | ||
11682 | case OPTION_NO_SMARTMIPS: | |
11683 | mips_opts.ase_smartmips = 0; | |
11684 | break; | |
11685 | ||
6a32d874 CM |
11686 | case OPTION_FIX_24K: |
11687 | mips_fix_24k = 1; | |
11688 | break; | |
11689 | ||
11690 | case OPTION_NO_FIX_24K: | |
11691 | mips_fix_24k = 0; | |
11692 | break; | |
11693 | ||
c67a084a NC |
11694 | case OPTION_FIX_LOONGSON2F_JUMP: |
11695 | mips_fix_loongson2f_jump = TRUE; | |
11696 | break; | |
11697 | ||
11698 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11699 | mips_fix_loongson2f_jump = FALSE; | |
11700 | break; | |
11701 | ||
11702 | case OPTION_FIX_LOONGSON2F_NOP: | |
11703 | mips_fix_loongson2f_nop = TRUE; | |
11704 | break; | |
11705 | ||
11706 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11707 | mips_fix_loongson2f_nop = FALSE; | |
11708 | break; | |
11709 | ||
d766e8ec RS |
11710 | case OPTION_FIX_VR4120: |
11711 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11712 | break; |
11713 | ||
d766e8ec RS |
11714 | case OPTION_NO_FIX_VR4120: |
11715 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11716 | break; |
11717 | ||
7d8e00cf RS |
11718 | case OPTION_FIX_VR4130: |
11719 | mips_fix_vr4130 = 1; | |
11720 | break; | |
11721 | ||
11722 | case OPTION_NO_FIX_VR4130: | |
11723 | mips_fix_vr4130 = 0; | |
11724 | break; | |
11725 | ||
d954098f DD |
11726 | case OPTION_FIX_CN63XXP1: |
11727 | mips_fix_cn63xxp1 = TRUE; | |
11728 | break; | |
11729 | ||
11730 | case OPTION_NO_FIX_CN63XXP1: | |
11731 | mips_fix_cn63xxp1 = FALSE; | |
11732 | break; | |
11733 | ||
4a6a3df4 AO |
11734 | case OPTION_RELAX_BRANCH: |
11735 | mips_relax_branch = 1; | |
11736 | break; | |
11737 | ||
11738 | case OPTION_NO_RELAX_BRANCH: | |
11739 | mips_relax_branch = 0; | |
11740 | break; | |
11741 | ||
aa6975fb ILT |
11742 | case OPTION_MSHARED: |
11743 | mips_in_shared = TRUE; | |
11744 | break; | |
11745 | ||
11746 | case OPTION_MNO_SHARED: | |
11747 | mips_in_shared = FALSE; | |
11748 | break; | |
11749 | ||
aed1a261 RS |
11750 | case OPTION_MSYM32: |
11751 | mips_opts.sym32 = TRUE; | |
11752 | break; | |
11753 | ||
11754 | case OPTION_MNO_SYM32: | |
11755 | mips_opts.sym32 = FALSE; | |
11756 | break; | |
11757 | ||
0f074f60 | 11758 | #ifdef OBJ_ELF |
252b5132 RH |
11759 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11760 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11761 | intended to be compatible with Irix 5. */ | |
11762 | case OPTION_CALL_SHARED: | |
f43abd2b | 11763 | if (!IS_ELF) |
252b5132 RH |
11764 | { |
11765 | as_bad (_("-call_shared is supported only for ELF format")); | |
11766 | return 0; | |
11767 | } | |
11768 | mips_pic = SVR4_PIC; | |
143d77c5 | 11769 | mips_abicalls = TRUE; |
252b5132 RH |
11770 | break; |
11771 | ||
861fb55a DJ |
11772 | case OPTION_CALL_NONPIC: |
11773 | if (!IS_ELF) | |
11774 | { | |
11775 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11776 | return 0; | |
11777 | } | |
11778 | mips_pic = NO_PIC; | |
11779 | mips_abicalls = TRUE; | |
11780 | break; | |
11781 | ||
252b5132 | 11782 | case OPTION_NON_SHARED: |
f43abd2b | 11783 | if (!IS_ELF) |
252b5132 RH |
11784 | { |
11785 | as_bad (_("-non_shared is supported only for ELF format")); | |
11786 | return 0; | |
11787 | } | |
11788 | mips_pic = NO_PIC; | |
143d77c5 | 11789 | mips_abicalls = FALSE; |
252b5132 RH |
11790 | break; |
11791 | ||
44075ae2 TS |
11792 | /* The -xgot option tells the assembler to use 32 bit offsets |
11793 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11794 | compatibility. */ |
11795 | case OPTION_XGOT: | |
11796 | mips_big_got = 1; | |
11797 | break; | |
0f074f60 | 11798 | #endif /* OBJ_ELF */ |
252b5132 RH |
11799 | |
11800 | case 'G': | |
6caf9ef4 TS |
11801 | g_switch_value = atoi (arg); |
11802 | g_switch_seen = 1; | |
252b5132 RH |
11803 | break; |
11804 | ||
34ba82a8 TS |
11805 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11806 | and -mabi=64. */ | |
252b5132 | 11807 | case OPTION_32: |
23fce1e3 NC |
11808 | if (IS_ELF) |
11809 | mips_abi = O32_ABI; | |
11810 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11811 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11812 | break; |
11813 | ||
23fce1e3 | 11814 | #ifdef OBJ_ELF |
e013f690 | 11815 | case OPTION_N32: |
f43abd2b | 11816 | if (!IS_ELF) |
34ba82a8 TS |
11817 | { |
11818 | as_bad (_("-n32 is supported for ELF format only")); | |
11819 | return 0; | |
11820 | } | |
316f5878 | 11821 | mips_abi = N32_ABI; |
e013f690 | 11822 | break; |
252b5132 | 11823 | |
e013f690 | 11824 | case OPTION_64: |
f43abd2b | 11825 | if (!IS_ELF) |
34ba82a8 TS |
11826 | { |
11827 | as_bad (_("-64 is supported for ELF format only")); | |
11828 | return 0; | |
11829 | } | |
316f5878 | 11830 | mips_abi = N64_ABI; |
f43abd2b | 11831 | if (!support_64bit_objects()) |
e013f690 | 11832 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11833 | break; |
ae948b86 | 11834 | #endif /* OBJ_ELF */ |
252b5132 | 11835 | |
c97ef257 | 11836 | case OPTION_GP32: |
a325df1d | 11837 | file_mips_gp32 = 1; |
c97ef257 AH |
11838 | break; |
11839 | ||
11840 | case OPTION_GP64: | |
a325df1d | 11841 | file_mips_gp32 = 0; |
c97ef257 | 11842 | break; |
252b5132 | 11843 | |
ca4e0257 | 11844 | case OPTION_FP32: |
a325df1d | 11845 | file_mips_fp32 = 1; |
316f5878 RS |
11846 | break; |
11847 | ||
11848 | case OPTION_FP64: | |
11849 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11850 | break; |
11851 | ||
037b32b9 AN |
11852 | case OPTION_SINGLE_FLOAT: |
11853 | file_mips_single_float = 1; | |
11854 | break; | |
11855 | ||
11856 | case OPTION_DOUBLE_FLOAT: | |
11857 | file_mips_single_float = 0; | |
11858 | break; | |
11859 | ||
11860 | case OPTION_SOFT_FLOAT: | |
11861 | file_mips_soft_float = 1; | |
11862 | break; | |
11863 | ||
11864 | case OPTION_HARD_FLOAT: | |
11865 | file_mips_soft_float = 0; | |
11866 | break; | |
11867 | ||
ae948b86 | 11868 | #ifdef OBJ_ELF |
252b5132 | 11869 | case OPTION_MABI: |
f43abd2b | 11870 | if (!IS_ELF) |
34ba82a8 TS |
11871 | { |
11872 | as_bad (_("-mabi is supported for ELF format only")); | |
11873 | return 0; | |
11874 | } | |
e013f690 | 11875 | if (strcmp (arg, "32") == 0) |
316f5878 | 11876 | mips_abi = O32_ABI; |
e013f690 | 11877 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11878 | mips_abi = O64_ABI; |
e013f690 | 11879 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11880 | mips_abi = N32_ABI; |
e013f690 TS |
11881 | else if (strcmp (arg, "64") == 0) |
11882 | { | |
316f5878 | 11883 | mips_abi = N64_ABI; |
e013f690 TS |
11884 | if (! support_64bit_objects()) |
11885 | as_fatal (_("No compiled in support for 64 bit object file " | |
11886 | "format")); | |
11887 | } | |
11888 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11889 | mips_abi = EABI_ABI; |
e013f690 | 11890 | else |
da0e507f TS |
11891 | { |
11892 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11893 | return 0; | |
11894 | } | |
252b5132 | 11895 | break; |
e013f690 | 11896 | #endif /* OBJ_ELF */ |
252b5132 | 11897 | |
6b76fefe | 11898 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11899 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11900 | break; |
11901 | ||
9ee72ff1 | 11902 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11903 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11904 | break; |
11905 | ||
ecb4347a DJ |
11906 | #ifdef OBJ_ELF |
11907 | case OPTION_MDEBUG: | |
b34976b6 | 11908 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11909 | break; |
11910 | ||
11911 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11912 | mips_flag_mdebug = FALSE; |
ecb4347a | 11913 | break; |
dcd410fe RO |
11914 | |
11915 | case OPTION_PDR: | |
11916 | mips_flag_pdr = TRUE; | |
11917 | break; | |
11918 | ||
11919 | case OPTION_NO_PDR: | |
11920 | mips_flag_pdr = FALSE; | |
11921 | break; | |
0a44bf69 RS |
11922 | |
11923 | case OPTION_MVXWORKS_PIC: | |
11924 | mips_pic = VXWORKS_PIC; | |
11925 | break; | |
ecb4347a DJ |
11926 | #endif /* OBJ_ELF */ |
11927 | ||
252b5132 RH |
11928 | default: |
11929 | return 0; | |
11930 | } | |
11931 | ||
c67a084a NC |
11932 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
11933 | ||
252b5132 RH |
11934 | return 1; |
11935 | } | |
316f5878 RS |
11936 | \f |
11937 | /* Set up globals to generate code for the ISA or processor | |
11938 | described by INFO. */ | |
252b5132 | 11939 | |
252b5132 | 11940 | static void |
17a2f251 | 11941 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11942 | { |
316f5878 | 11943 | if (info != 0) |
252b5132 | 11944 | { |
fef14a42 TS |
11945 | file_mips_arch = info->cpu; |
11946 | mips_opts.arch = info->cpu; | |
316f5878 | 11947 | mips_opts.isa = info->isa; |
252b5132 | 11948 | } |
252b5132 RH |
11949 | } |
11950 | ||
252b5132 | 11951 | |
316f5878 | 11952 | /* Likewise for tuning. */ |
252b5132 | 11953 | |
316f5878 | 11954 | static void |
17a2f251 | 11955 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11956 | { |
11957 | if (info != 0) | |
fef14a42 | 11958 | mips_tune = info->cpu; |
316f5878 | 11959 | } |
80cc45a5 | 11960 | |
34ba82a8 | 11961 | |
252b5132 | 11962 | void |
17a2f251 | 11963 | mips_after_parse_args (void) |
e9670677 | 11964 | { |
fef14a42 TS |
11965 | const struct mips_cpu_info *arch_info = 0; |
11966 | const struct mips_cpu_info *tune_info = 0; | |
11967 | ||
e9670677 | 11968 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11969 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11970 | { |
6caf9ef4 | 11971 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11972 | as_bad (_("-G not supported in this configuration.")); |
11973 | g_switch_value = 0; | |
11974 | } | |
11975 | ||
cac012d6 AO |
11976 | if (mips_abi == NO_ABI) |
11977 | mips_abi = MIPS_DEFAULT_ABI; | |
11978 | ||
22923709 RS |
11979 | /* The following code determines the architecture and register size. |
11980 | Similar code was added to GCC 3.3 (see override_options() in | |
11981 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11982 | as much as possible. */ | |
e9670677 | 11983 | |
316f5878 | 11984 | if (mips_arch_string != 0) |
fef14a42 | 11985 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11986 | |
316f5878 | 11987 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11988 | { |
316f5878 | 11989 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11990 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11991 | the -march selection (if any). */ |
fef14a42 | 11992 | if (arch_info != 0) |
e9670677 | 11993 | { |
316f5878 RS |
11994 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11995 | There's no harm in specifying both as long as the ISA levels | |
11996 | are the same. */ | |
fef14a42 | 11997 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11998 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11999 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 12000 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 12001 | } |
316f5878 | 12002 | else |
fef14a42 | 12003 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
12004 | } |
12005 | ||
fef14a42 TS |
12006 | if (arch_info == 0) |
12007 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 12008 | |
fef14a42 | 12009 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 12010 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
12011 | arch_info->name); |
12012 | ||
12013 | mips_set_architecture (arch_info); | |
12014 | ||
12015 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
12016 | if (mips_tune_string != 0) | |
12017 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 12018 | |
fef14a42 TS |
12019 | if (tune_info == 0) |
12020 | mips_set_tune (arch_info); | |
12021 | else | |
12022 | mips_set_tune (tune_info); | |
e9670677 | 12023 | |
316f5878 | 12024 | if (file_mips_gp32 >= 0) |
e9670677 | 12025 | { |
316f5878 RS |
12026 | /* The user specified the size of the integer registers. Make sure |
12027 | it agrees with the ABI and ISA. */ | |
12028 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12029 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12030 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12031 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12032 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12033 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12034 | } |
12035 | else | |
12036 | { | |
316f5878 RS |
12037 | /* Infer the integer register size from the ABI and processor. |
12038 | Restrict ourselves to 32-bit registers if that's all the | |
12039 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12040 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12041 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12042 | } |
12043 | ||
ad3fea08 TS |
12044 | switch (file_mips_fp32) |
12045 | { | |
12046 | default: | |
12047 | case -1: | |
12048 | /* No user specified float register size. | |
12049 | ??? GAS treats single-float processors as though they had 64-bit | |
12050 | float registers (although it complains when double-precision | |
12051 | instructions are used). As things stand, saying they have 32-bit | |
12052 | registers would lead to spurious "register must be even" messages. | |
12053 | So here we assume float registers are never smaller than the | |
12054 | integer ones. */ | |
12055 | if (file_mips_gp32 == 0) | |
12056 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12057 | file_mips_fp32 = 0; | |
12058 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12059 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12060 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12061 | file_mips_fp32 = 0; | |
12062 | else | |
12063 | /* 32-bit float registers. */ | |
12064 | file_mips_fp32 = 1; | |
12065 | break; | |
12066 | ||
12067 | /* The user specified the size of the float registers. Check if it | |
12068 | agrees with the ABI and ISA. */ | |
12069 | case 0: | |
12070 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12071 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12072 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12073 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12074 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12075 | break; | |
12076 | case 1: | |
12077 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12078 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12079 | break; | |
12080 | } | |
e9670677 | 12081 | |
316f5878 | 12082 | /* End of GCC-shared inference code. */ |
e9670677 | 12083 | |
17a2f251 TS |
12084 | /* This flag is set when we have a 64-bit capable CPU but use only |
12085 | 32-bit wide registers. Note that EABI does not use it. */ | |
12086 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12087 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12088 | || mips_abi == O32_ABI)) | |
316f5878 | 12089 | mips_32bitmode = 1; |
e9670677 MR |
12090 | |
12091 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12092 | as_bad (_("trap exception not supported at ISA 1")); | |
12093 | ||
e9670677 MR |
12094 | /* If the selected architecture includes support for ASEs, enable |
12095 | generation of code for them. */ | |
a4672219 | 12096 | if (mips_opts.mips16 == -1) |
fef14a42 | 12097 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12098 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12099 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12100 | && file_mips_fp32 == 0) ? 1 : 0; |
12101 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12102 | as_bad (_("-mfp32 used with -mips3d")); | |
12103 | ||
ffdefa66 | 12104 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12105 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12106 | && file_mips_fp32 == 0) ? 1 : 0; |
12107 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12108 | as_bad (_("-mfp32 used with -mdmx")); | |
12109 | ||
12110 | if (mips_opts.ase_smartmips == -1) | |
12111 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12112 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12113 | as_warn (_("%s ISA does not support SmartMIPS"), |
12114 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12115 | |
74cd071d | 12116 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12117 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12118 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12119 | as_warn (_("%s ISA does not support DSP ASE"), |
12120 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12121 | |
8b082fb1 TS |
12122 | if (mips_opts.ase_dspr2 == -1) |
12123 | { | |
12124 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12125 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12126 | } | |
12127 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12128 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12129 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12130 | |
ef2e4d86 | 12131 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12132 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12133 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12134 | as_warn (_("%s ISA does not support MT ASE"), |
12135 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12136 | |
e9670677 | 12137 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
12138 | file_ase_mips3d = mips_opts.ase_mips3d; |
12139 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12140 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12141 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12142 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12143 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12144 | mips_opts.gp32 = file_mips_gp32; |
12145 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12146 | mips_opts.soft_float = file_mips_soft_float; |
12147 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12148 | |
ecb4347a DJ |
12149 | if (mips_flag_mdebug < 0) |
12150 | { | |
12151 | #ifdef OBJ_MAYBE_ECOFF | |
12152 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12153 | mips_flag_mdebug = 1; | |
12154 | else | |
12155 | #endif /* OBJ_MAYBE_ECOFF */ | |
12156 | mips_flag_mdebug = 0; | |
12157 | } | |
e9670677 MR |
12158 | } |
12159 | \f | |
12160 | void | |
17a2f251 | 12161 | mips_init_after_args (void) |
252b5132 RH |
12162 | { |
12163 | /* initialize opcodes */ | |
12164 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12165 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12166 | } |
12167 | ||
12168 | long | |
17a2f251 | 12169 | md_pcrel_from (fixS *fixP) |
252b5132 | 12170 | { |
a7ebbfdf TS |
12171 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12172 | switch (fixP->fx_r_type) | |
12173 | { | |
12174 | case BFD_RELOC_16_PCREL_S2: | |
12175 | case BFD_RELOC_MIPS_JMP: | |
12176 | /* Return the address of the delay slot. */ | |
12177 | return addr + 4; | |
12178 | default: | |
58ea3d6a | 12179 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12180 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12181 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12182 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12183 | return addr; |
12184 | } | |
252b5132 RH |
12185 | } |
12186 | ||
252b5132 RH |
12187 | /* This is called before the symbol table is processed. In order to |
12188 | work with gcc when using mips-tfile, we must keep all local labels. | |
12189 | However, in other cases, we want to discard them. If we were | |
12190 | called with -g, but we didn't see any debugging information, it may | |
12191 | mean that gcc is smuggling debugging information through to | |
12192 | mips-tfile, in which case we must generate all local labels. */ | |
12193 | ||
12194 | void | |
17a2f251 | 12195 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12196 | { |
12197 | #ifndef NO_ECOFF_DEBUGGING | |
12198 | if (ECOFF_DEBUGGING | |
12199 | && mips_debug != 0 | |
12200 | && ! ecoff_debugging_seen) | |
12201 | flag_keep_locals = 1; | |
12202 | #endif | |
12203 | } | |
12204 | ||
3b91255e | 12205 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12206 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12207 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12208 | relocation operators. | |
12209 | ||
12210 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12211 | expression if: | |
12212 | ||
12213 | (a) it refers to the same symbol; and | |
12214 | (b) the offset applied in the %lo() expression is no lower than | |
12215 | the offset applied in the %got() or %hi(). | |
12216 | ||
12217 | (b) allows us to cope with code like: | |
12218 | ||
12219 | lui $4,%hi(foo) | |
12220 | lh $4,%lo(foo+2)($4) | |
12221 | ||
12222 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12223 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12224 | the high 16 bits. | |
12225 | ||
12226 | When several %lo()s match a particular %got() or %hi(), we use the | |
12227 | following rules to distinguish them: | |
12228 | ||
12229 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12230 | higher offsets. | |
12231 | ||
12232 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12233 | that already have a matching %got() or %hi(). | |
12234 | ||
12235 | (3) later %lo()s are better than earlier %lo()s. | |
12236 | ||
12237 | These rules are applied in order. | |
12238 | ||
12239 | (1) means, among other things, that %lo()s with identical offsets are | |
12240 | chosen if they exist. | |
12241 | ||
12242 | (2) means that we won't associate several high-part relocations with | |
12243 | the same low-part relocation unless there's no alternative. Having | |
12244 | several high parts for the same low part is a GNU extension; this rule | |
12245 | allows careful users to avoid it. | |
12246 | ||
12247 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12248 | with the last high-part relocation being at the front of the list. | |
12249 | It therefore makes sense to choose the last matching low-part | |
12250 | relocation, all other things being equal. It's also easier | |
12251 | to code that way. */ | |
252b5132 RH |
12252 | |
12253 | void | |
17a2f251 | 12254 | mips_frob_file (void) |
252b5132 RH |
12255 | { |
12256 | struct mips_hi_fixup *l; | |
35903be0 | 12257 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12258 | |
12259 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12260 | { | |
12261 | segment_info_type *seginfo; | |
3b91255e RS |
12262 | bfd_boolean matched_lo_p; |
12263 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12264 | |
9c2799c2 | 12265 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12266 | |
5919d012 RS |
12267 | /* If a GOT16 relocation turns out to be against a global symbol, |
12268 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12269 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12270 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12271 | continue; | |
12272 | ||
12273 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12274 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12275 | continue; |
12276 | ||
252b5132 | 12277 | seginfo = seg_info (l->seg); |
252b5132 | 12278 | |
3b91255e RS |
12279 | /* Set HI_POS to the position of this relocation in the chain. |
12280 | Set LO_POS to the position of the chosen low-part relocation. | |
12281 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12282 | relocation that matches an immediately-preceding high-part | |
12283 | relocation. */ | |
12284 | hi_pos = NULL; | |
12285 | lo_pos = NULL; | |
12286 | matched_lo_p = FALSE; | |
738e5348 | 12287 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12288 | |
3b91255e RS |
12289 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12290 | { | |
12291 | if (*pos == l->fixp) | |
12292 | hi_pos = pos; | |
12293 | ||
35903be0 | 12294 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12295 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12296 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12297 | && (lo_pos == NULL | |
12298 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12299 | || (!matched_lo_p | |
12300 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12301 | lo_pos = pos; | |
12302 | ||
12303 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12304 | && fixup_has_matching_lo_p (*pos)); | |
12305 | } | |
12306 | ||
12307 | /* If we found a match, remove the high-part relocation from its | |
12308 | current position and insert it before the low-part relocation. | |
12309 | Make the offsets match so that fixup_has_matching_lo_p() | |
12310 | will return true. | |
12311 | ||
12312 | We don't warn about unmatched high-part relocations since some | |
12313 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12314 | instructions. */ | |
12315 | if (lo_pos != NULL) | |
12316 | { | |
12317 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12318 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12319 | { |
3b91255e RS |
12320 | *hi_pos = l->fixp->fx_next; |
12321 | l->fixp->fx_next = *lo_pos; | |
12322 | *lo_pos = l->fixp; | |
252b5132 | 12323 | } |
252b5132 RH |
12324 | } |
12325 | } | |
12326 | } | |
12327 | ||
3e722fb5 | 12328 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12329 | We have to prevent gas from dropping them. */ |
252b5132 | 12330 | |
252b5132 | 12331 | int |
17a2f251 | 12332 | mips_force_relocation (fixS *fixp) |
252b5132 | 12333 | { |
ae6063d4 | 12334 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12335 | return 1; |
12336 | ||
f6688943 TS |
12337 | if (HAVE_NEWABI |
12338 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12339 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12340 | || hi16_reloc_p (fixp->fx_r_type) |
12341 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12342 | return 1; |
12343 | ||
3e722fb5 | 12344 | return 0; |
252b5132 RH |
12345 | } |
12346 | ||
12347 | /* Apply a fixup to the object file. */ | |
12348 | ||
94f592af | 12349 | void |
55cf6793 | 12350 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12351 | { |
874e8986 | 12352 | bfd_byte *buf; |
98aa84af | 12353 | long insn; |
a7ebbfdf | 12354 | reloc_howto_type *howto; |
252b5132 | 12355 | |
a7ebbfdf TS |
12356 | /* We ignore generic BFD relocations we don't know about. */ |
12357 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12358 | if (! howto) | |
12359 | return; | |
65551fa4 | 12360 | |
9c2799c2 | 12361 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12362 | || fixP->fx_r_type == BFD_RELOC_16 |
12363 | || fixP->fx_r_type == BFD_RELOC_64 | |
12364 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12365 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12366 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12367 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12368 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12369 | |
a7ebbfdf | 12370 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12371 | |
9c2799c2 | 12372 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12373 | |
12374 | /* Don't treat parts of a composite relocation as done. There are two | |
12375 | reasons for this: | |
12376 | ||
12377 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12378 | should nevertheless be emitted if the first part is. | |
12379 | ||
12380 | (2) In normal usage, composite relocations are never assembly-time | |
12381 | constants. The easiest way of dealing with the pathological | |
12382 | exceptions is to generate a relocation against STN_UNDEF and | |
12383 | leave everything up to the linker. */ | |
3994f87e | 12384 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12385 | fixP->fx_done = 1; |
12386 | ||
12387 | switch (fixP->fx_r_type) | |
12388 | { | |
3f98094e DJ |
12389 | case BFD_RELOC_MIPS_TLS_GD: |
12390 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12391 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12392 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12393 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12394 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12395 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12396 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12397 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12398 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12399 | /* fall through */ | |
12400 | ||
252b5132 | 12401 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12402 | case BFD_RELOC_MIPS_SHIFT5: |
12403 | case BFD_RELOC_MIPS_SHIFT6: | |
12404 | case BFD_RELOC_MIPS_GOT_DISP: | |
12405 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12406 | case BFD_RELOC_MIPS_GOT_OFST: | |
12407 | case BFD_RELOC_MIPS_SUB: | |
12408 | case BFD_RELOC_MIPS_INSERT_A: | |
12409 | case BFD_RELOC_MIPS_INSERT_B: | |
12410 | case BFD_RELOC_MIPS_DELETE: | |
12411 | case BFD_RELOC_MIPS_HIGHEST: | |
12412 | case BFD_RELOC_MIPS_HIGHER: | |
12413 | case BFD_RELOC_MIPS_SCN_DISP: | |
12414 | case BFD_RELOC_MIPS_REL16: | |
12415 | case BFD_RELOC_MIPS_RELGOT: | |
12416 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12417 | case BFD_RELOC_HI16: |
12418 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12419 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12420 | case BFD_RELOC_MIPS_LITERAL: |
12421 | case BFD_RELOC_MIPS_CALL16: | |
12422 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12423 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12424 | case BFD_RELOC_MIPS_GOT_HI16: |
12425 | case BFD_RELOC_MIPS_GOT_LO16: | |
12426 | case BFD_RELOC_MIPS_CALL_HI16: | |
12427 | case BFD_RELOC_MIPS_CALL_LO16: | |
12428 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12429 | case BFD_RELOC_MIPS16_GOT16: |
12430 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12431 | case BFD_RELOC_MIPS16_HI16: |
12432 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12433 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12434 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12435 | break; |
12436 | ||
252b5132 RH |
12437 | case BFD_RELOC_64: |
12438 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12439 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12440 | if (fixP->fx_done) |
252b5132 RH |
12441 | { |
12442 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12443 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12444 | else |
12445 | { | |
a7ebbfdf | 12446 | valueT hiv; |
252b5132 | 12447 | |
a7ebbfdf | 12448 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12449 | hiv = 0xffffffff; |
12450 | else | |
12451 | hiv = 0; | |
b215186b | 12452 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12453 | *valP, 4); |
b215186b | 12454 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12455 | hiv, 4); |
252b5132 RH |
12456 | } |
12457 | } | |
12458 | break; | |
12459 | ||
056350c6 | 12460 | case BFD_RELOC_RVA: |
252b5132 | 12461 | case BFD_RELOC_32: |
252b5132 RH |
12462 | case BFD_RELOC_16: |
12463 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12464 | value now. This can happen if we have a .word which is not |
12465 | resolved when it appears but is later defined. */ | |
252b5132 | 12466 | if (fixP->fx_done) |
54f4ddb3 | 12467 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12468 | break; |
12469 | ||
12470 | case BFD_RELOC_LO16: | |
d6f16593 | 12471 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12472 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12473 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12474 | /* When handling an embedded PIC switch statement, we can wind |
12475 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12476 | if (fixP->fx_done) | |
12477 | { | |
a7ebbfdf | 12478 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12479 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12480 | _("relocation overflow")); | |
252b5132 RH |
12481 | if (target_big_endian) |
12482 | buf += 2; | |
2132e3a3 | 12483 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12484 | } |
12485 | break; | |
12486 | ||
12487 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12488 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12489 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12490 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12491 | |
54f4ddb3 TS |
12492 | /* We need to save the bits in the instruction since fixup_segment() |
12493 | might be deleting the relocation entry (i.e., a branch within | |
12494 | the current segment). */ | |
a7ebbfdf | 12495 | if (! fixP->fx_done) |
bb2d6cd7 | 12496 | break; |
252b5132 | 12497 | |
54f4ddb3 | 12498 | /* Update old instruction data. */ |
252b5132 RH |
12499 | if (target_big_endian) |
12500 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12501 | else | |
12502 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12503 | ||
a7ebbfdf TS |
12504 | if (*valP + 0x20000 <= 0x3ffff) |
12505 | { | |
12506 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12507 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12508 | } |
12509 | else if (mips_pic == NO_PIC | |
12510 | && fixP->fx_done | |
12511 | && fixP->fx_frag->fr_address >= text_section->vma | |
12512 | && (fixP->fx_frag->fr_address | |
587aac4e | 12513 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12514 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12515 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12516 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12517 | { |
12518 | /* The branch offset is too large. If this is an | |
12519 | unconditional branch, and we are not generating PIC code, | |
12520 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12521 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12522 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12523 | else |
a7ebbfdf TS |
12524 | insn = 0x08000000; /* j */ |
12525 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12526 | fixP->fx_done = 0; | |
12527 | fixP->fx_addsy = section_symbol (text_section); | |
12528 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12529 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12530 | } |
12531 | else | |
12532 | { | |
12533 | /* If we got here, we have branch-relaxation disabled, | |
12534 | and there's nothing we can do to fix this instruction | |
12535 | without turning it into a longer sequence. */ | |
12536 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12537 | _("Branch out of range")); | |
252b5132 | 12538 | } |
252b5132 RH |
12539 | break; |
12540 | ||
12541 | case BFD_RELOC_VTABLE_INHERIT: | |
12542 | fixP->fx_done = 0; | |
12543 | if (fixP->fx_addsy | |
12544 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12545 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12546 | S_SET_WEAK (fixP->fx_addsy); | |
12547 | break; | |
12548 | ||
12549 | case BFD_RELOC_VTABLE_ENTRY: | |
12550 | fixP->fx_done = 0; | |
12551 | break; | |
12552 | ||
12553 | default: | |
12554 | internalError (); | |
12555 | } | |
a7ebbfdf TS |
12556 | |
12557 | /* Remember value for tc_gen_reloc. */ | |
12558 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12559 | } |
12560 | ||
252b5132 | 12561 | static symbolS * |
17a2f251 | 12562 | get_symbol (void) |
252b5132 RH |
12563 | { |
12564 | int c; | |
12565 | char *name; | |
12566 | symbolS *p; | |
12567 | ||
12568 | name = input_line_pointer; | |
12569 | c = get_symbol_end (); | |
12570 | p = (symbolS *) symbol_find_or_make (name); | |
12571 | *input_line_pointer = c; | |
12572 | return p; | |
12573 | } | |
12574 | ||
742a56fe RS |
12575 | /* Align the current frag to a given power of two. If a particular |
12576 | fill byte should be used, FILL points to an integer that contains | |
12577 | that byte, otherwise FILL is null. | |
12578 | ||
12579 | The MIPS assembler also automatically adjusts any preceding | |
12580 | label. */ | |
252b5132 RH |
12581 | |
12582 | static void | |
742a56fe | 12583 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12584 | { |
7d10b47d | 12585 | mips_emit_delays (); |
742a56fe RS |
12586 | mips_record_mips16_mode (); |
12587 | if (fill == NULL && subseg_text_p (now_seg)) | |
12588 | frag_align_code (to, 0); | |
12589 | else | |
12590 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12591 | record_alignment (now_seg, to); |
12592 | if (label != NULL) | |
12593 | { | |
9c2799c2 | 12594 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12595 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12596 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12597 | } | |
12598 | } | |
12599 | ||
12600 | /* Align to a given power of two. .align 0 turns off the automatic | |
12601 | alignment used by the data creating pseudo-ops. */ | |
12602 | ||
12603 | static void | |
17a2f251 | 12604 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12605 | { |
742a56fe | 12606 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12607 | long max_alignment = 28; |
252b5132 | 12608 | |
54f4ddb3 | 12609 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12610 | to the aligned address. |
54f4ddb3 | 12611 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12612 | a .align pseudo instruction. |
54f4ddb3 | 12613 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12614 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12615 | We don't. */ |
252b5132 RH |
12616 | |
12617 | temp = get_absolute_expression (); | |
12618 | if (temp > max_alignment) | |
12619 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12620 | else if (temp < 0) | |
12621 | { | |
12622 | as_warn (_("Alignment negative: 0 assumed.")); | |
12623 | temp = 0; | |
12624 | } | |
12625 | if (*input_line_pointer == ',') | |
12626 | { | |
f9419b05 | 12627 | ++input_line_pointer; |
742a56fe RS |
12628 | fill_value = get_absolute_expression (); |
12629 | fill_ptr = &fill_value; | |
252b5132 RH |
12630 | } |
12631 | else | |
742a56fe | 12632 | fill_ptr = 0; |
252b5132 RH |
12633 | if (temp) |
12634 | { | |
a8dbcb85 TS |
12635 | segment_info_type *si = seg_info (now_seg); |
12636 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12637 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12638 | auto_align = 1; |
742a56fe | 12639 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12640 | } |
12641 | else | |
12642 | { | |
12643 | auto_align = 0; | |
12644 | } | |
12645 | ||
12646 | demand_empty_rest_of_line (); | |
12647 | } | |
12648 | ||
252b5132 | 12649 | static void |
17a2f251 | 12650 | s_change_sec (int sec) |
252b5132 RH |
12651 | { |
12652 | segT seg; | |
12653 | ||
252b5132 RH |
12654 | #ifdef OBJ_ELF |
12655 | /* The ELF backend needs to know that we are changing sections, so | |
12656 | that .previous works correctly. We could do something like check | |
b6ff326e | 12657 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12658 | as it would not be appropriate to use it in the section changing |
12659 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12660 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12661 | if (IS_ELF) |
12662 | obj_elf_section_change_hook (); | |
252b5132 RH |
12663 | #endif |
12664 | ||
7d10b47d | 12665 | mips_emit_delays (); |
6a32d874 | 12666 | |
252b5132 RH |
12667 | switch (sec) |
12668 | { | |
12669 | case 't': | |
12670 | s_text (0); | |
12671 | break; | |
12672 | case 'd': | |
12673 | s_data (0); | |
12674 | break; | |
12675 | case 'b': | |
12676 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12677 | demand_empty_rest_of_line (); | |
12678 | break; | |
12679 | ||
12680 | case 'r': | |
4d0d148d TS |
12681 | seg = subseg_new (RDATA_SECTION_NAME, |
12682 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12683 | if (IS_ELF) |
252b5132 | 12684 | { |
4d0d148d TS |
12685 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12686 | | SEC_READONLY | SEC_RELOC | |
12687 | | SEC_DATA)); | |
c41e87e3 | 12688 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12689 | record_alignment (seg, 4); |
252b5132 | 12690 | } |
4d0d148d | 12691 | demand_empty_rest_of_line (); |
252b5132 RH |
12692 | break; |
12693 | ||
12694 | case 's': | |
4d0d148d | 12695 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12696 | if (IS_ELF) |
252b5132 | 12697 | { |
4d0d148d TS |
12698 | bfd_set_section_flags (stdoutput, seg, |
12699 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12700 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12701 | record_alignment (seg, 4); |
252b5132 | 12702 | } |
4d0d148d TS |
12703 | demand_empty_rest_of_line (); |
12704 | break; | |
998b3c36 MR |
12705 | |
12706 | case 'B': | |
12707 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12708 | if (IS_ELF) | |
12709 | { | |
12710 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12711 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12712 | record_alignment (seg, 4); | |
12713 | } | |
12714 | demand_empty_rest_of_line (); | |
12715 | break; | |
252b5132 RH |
12716 | } |
12717 | ||
12718 | auto_align = 1; | |
12719 | } | |
b34976b6 | 12720 | |
cca86cc8 | 12721 | void |
17a2f251 | 12722 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12723 | { |
7ed4a06a | 12724 | #ifdef OBJ_ELF |
cca86cc8 SC |
12725 | char *section_name; |
12726 | char c; | |
684022ea | 12727 | char next_c = 0; |
cca86cc8 SC |
12728 | int section_type; |
12729 | int section_flag; | |
12730 | int section_entry_size; | |
12731 | int section_alignment; | |
b34976b6 | 12732 | |
f43abd2b | 12733 | if (!IS_ELF) |
7ed4a06a TS |
12734 | return; |
12735 | ||
cca86cc8 SC |
12736 | section_name = input_line_pointer; |
12737 | c = get_symbol_end (); | |
a816d1ed AO |
12738 | if (c) |
12739 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12740 | |
4cf0dd0d TS |
12741 | /* Do we have .section Name<,"flags">? */ |
12742 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12743 | { |
4cf0dd0d TS |
12744 | /* just after name is now '\0'. */ |
12745 | *input_line_pointer = c; | |
cca86cc8 SC |
12746 | input_line_pointer = section_name; |
12747 | obj_elf_section (ignore); | |
12748 | return; | |
12749 | } | |
12750 | input_line_pointer++; | |
12751 | ||
12752 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12753 | if (c == ',') | |
12754 | section_type = get_absolute_expression (); | |
12755 | else | |
12756 | section_type = 0; | |
12757 | if (*input_line_pointer++ == ',') | |
12758 | section_flag = get_absolute_expression (); | |
12759 | else | |
12760 | section_flag = 0; | |
12761 | if (*input_line_pointer++ == ',') | |
12762 | section_entry_size = get_absolute_expression (); | |
12763 | else | |
12764 | section_entry_size = 0; | |
12765 | if (*input_line_pointer++ == ',') | |
12766 | section_alignment = get_absolute_expression (); | |
12767 | else | |
12768 | section_alignment = 0; | |
87975d2a AM |
12769 | /* FIXME: really ignore? */ |
12770 | (void) section_alignment; | |
cca86cc8 | 12771 | |
a816d1ed AO |
12772 | section_name = xstrdup (section_name); |
12773 | ||
8ab8a5c8 RS |
12774 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12775 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12776 | traditionally had to fall back on the more common @progbits instead. | |
12777 | ||
12778 | There's nothing really harmful in this, since bfd will correct | |
12779 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12780 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12781 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12782 | ||
12783 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12784 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12785 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12786 | generic type-checking code. */ | |
12787 | if (section_type == SHT_MIPS_DWARF) | |
12788 | section_type = SHT_PROGBITS; | |
12789 | ||
cca86cc8 SC |
12790 | obj_elf_change_section (section_name, section_type, section_flag, |
12791 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12792 | |
12793 | if (now_seg->name != section_name) | |
12794 | free (section_name); | |
7ed4a06a | 12795 | #endif /* OBJ_ELF */ |
cca86cc8 | 12796 | } |
252b5132 RH |
12797 | |
12798 | void | |
17a2f251 | 12799 | mips_enable_auto_align (void) |
252b5132 RH |
12800 | { |
12801 | auto_align = 1; | |
12802 | } | |
12803 | ||
12804 | static void | |
17a2f251 | 12805 | s_cons (int log_size) |
252b5132 | 12806 | { |
a8dbcb85 TS |
12807 | segment_info_type *si = seg_info (now_seg); |
12808 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12809 | symbolS *label; |
12810 | ||
a8dbcb85 | 12811 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12812 | mips_emit_delays (); |
252b5132 RH |
12813 | if (log_size > 0 && auto_align) |
12814 | mips_align (log_size, 0, label); | |
252b5132 | 12815 | cons (1 << log_size); |
a1facbec | 12816 | mips_clear_insn_labels (); |
252b5132 RH |
12817 | } |
12818 | ||
12819 | static void | |
17a2f251 | 12820 | s_float_cons (int type) |
252b5132 | 12821 | { |
a8dbcb85 TS |
12822 | segment_info_type *si = seg_info (now_seg); |
12823 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12824 | symbolS *label; |
12825 | ||
a8dbcb85 | 12826 | label = l != NULL ? l->label : NULL; |
252b5132 | 12827 | |
7d10b47d | 12828 | mips_emit_delays (); |
252b5132 RH |
12829 | |
12830 | if (auto_align) | |
49309057 ILT |
12831 | { |
12832 | if (type == 'd') | |
12833 | mips_align (3, 0, label); | |
12834 | else | |
12835 | mips_align (2, 0, label); | |
12836 | } | |
252b5132 | 12837 | |
252b5132 | 12838 | float_cons (type); |
a1facbec | 12839 | mips_clear_insn_labels (); |
252b5132 RH |
12840 | } |
12841 | ||
12842 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12843 | permitted to say | |
12844 | .globl foo .text | |
12845 | where foo is an undefined symbol, to mean that foo should be | |
12846 | considered to be the address of a function. */ | |
12847 | ||
12848 | static void | |
17a2f251 | 12849 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12850 | { |
12851 | char *name; | |
12852 | int c; | |
12853 | symbolS *symbolP; | |
12854 | flagword flag; | |
12855 | ||
8a06b769 | 12856 | do |
252b5132 | 12857 | { |
8a06b769 | 12858 | name = input_line_pointer; |
252b5132 | 12859 | c = get_symbol_end (); |
8a06b769 TS |
12860 | symbolP = symbol_find_or_make (name); |
12861 | S_SET_EXTERNAL (symbolP); | |
12862 | ||
252b5132 | 12863 | *input_line_pointer = c; |
8a06b769 | 12864 | SKIP_WHITESPACE (); |
252b5132 | 12865 | |
8a06b769 TS |
12866 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12867 | being a function is apparently labelled as being an object. */ | |
12868 | flag = BSF_OBJECT; | |
252b5132 | 12869 | |
8a06b769 TS |
12870 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12871 | && (*input_line_pointer != ',')) | |
12872 | { | |
12873 | char *secname; | |
12874 | asection *sec; | |
12875 | ||
12876 | secname = input_line_pointer; | |
12877 | c = get_symbol_end (); | |
12878 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12879 | if (sec == NULL) | |
12880 | as_bad (_("%s: no such section"), secname); | |
12881 | *input_line_pointer = c; | |
12882 | ||
12883 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12884 | flag = BSF_FUNCTION; | |
12885 | } | |
12886 | ||
12887 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12888 | ||
12889 | c = *input_line_pointer; | |
12890 | if (c == ',') | |
12891 | { | |
12892 | input_line_pointer++; | |
12893 | SKIP_WHITESPACE (); | |
12894 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12895 | c = '\n'; | |
12896 | } | |
12897 | } | |
12898 | while (c == ','); | |
252b5132 | 12899 | |
252b5132 RH |
12900 | demand_empty_rest_of_line (); |
12901 | } | |
12902 | ||
12903 | static void | |
17a2f251 | 12904 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12905 | { |
12906 | char *opt; | |
12907 | char c; | |
12908 | ||
12909 | opt = input_line_pointer; | |
12910 | c = get_symbol_end (); | |
12911 | ||
12912 | if (*opt == 'O') | |
12913 | { | |
12914 | /* FIXME: What does this mean? */ | |
12915 | } | |
12916 | else if (strncmp (opt, "pic", 3) == 0) | |
12917 | { | |
12918 | int i; | |
12919 | ||
12920 | i = atoi (opt + 3); | |
12921 | if (i == 0) | |
12922 | mips_pic = NO_PIC; | |
12923 | else if (i == 2) | |
143d77c5 | 12924 | { |
252b5132 | 12925 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12926 | mips_abicalls = TRUE; |
12927 | } | |
252b5132 RH |
12928 | else |
12929 | as_bad (_(".option pic%d not supported"), i); | |
12930 | ||
4d0d148d | 12931 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12932 | { |
12933 | if (g_switch_seen && g_switch_value != 0) | |
12934 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12935 | g_switch_value = 0; | |
12936 | bfd_set_gp_size (stdoutput, 0); | |
12937 | } | |
12938 | } | |
12939 | else | |
12940 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12941 | ||
12942 | *input_line_pointer = c; | |
12943 | demand_empty_rest_of_line (); | |
12944 | } | |
12945 | ||
12946 | /* This structure is used to hold a stack of .set values. */ | |
12947 | ||
e972090a NC |
12948 | struct mips_option_stack |
12949 | { | |
252b5132 RH |
12950 | struct mips_option_stack *next; |
12951 | struct mips_set_options options; | |
12952 | }; | |
12953 | ||
12954 | static struct mips_option_stack *mips_opts_stack; | |
12955 | ||
12956 | /* Handle the .set pseudo-op. */ | |
12957 | ||
12958 | static void | |
17a2f251 | 12959 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12960 | { |
12961 | char *name = input_line_pointer, ch; | |
12962 | ||
12963 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12964 | ++input_line_pointer; |
252b5132 RH |
12965 | ch = *input_line_pointer; |
12966 | *input_line_pointer = '\0'; | |
12967 | ||
12968 | if (strcmp (name, "reorder") == 0) | |
12969 | { | |
7d10b47d RS |
12970 | if (mips_opts.noreorder) |
12971 | end_noreorder (); | |
252b5132 RH |
12972 | } |
12973 | else if (strcmp (name, "noreorder") == 0) | |
12974 | { | |
7d10b47d RS |
12975 | if (!mips_opts.noreorder) |
12976 | start_noreorder (); | |
252b5132 | 12977 | } |
741fe287 MR |
12978 | else if (strncmp (name, "at=", 3) == 0) |
12979 | { | |
12980 | char *s = name + 3; | |
12981 | ||
12982 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12983 | as_bad (_("Unrecognized register name `%s'"), s); | |
12984 | } | |
252b5132 RH |
12985 | else if (strcmp (name, "at") == 0) |
12986 | { | |
741fe287 | 12987 | mips_opts.at = ATREG; |
252b5132 RH |
12988 | } |
12989 | else if (strcmp (name, "noat") == 0) | |
12990 | { | |
741fe287 | 12991 | mips_opts.at = ZERO; |
252b5132 RH |
12992 | } |
12993 | else if (strcmp (name, "macro") == 0) | |
12994 | { | |
12995 | mips_opts.warn_about_macros = 0; | |
12996 | } | |
12997 | else if (strcmp (name, "nomacro") == 0) | |
12998 | { | |
12999 | if (mips_opts.noreorder == 0) | |
13000 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
13001 | mips_opts.warn_about_macros = 1; | |
13002 | } | |
13003 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
13004 | { | |
13005 | mips_opts.nomove = 0; | |
13006 | } | |
13007 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
13008 | { | |
13009 | mips_opts.nomove = 1; | |
13010 | } | |
13011 | else if (strcmp (name, "bopt") == 0) | |
13012 | { | |
13013 | mips_opts.nobopt = 0; | |
13014 | } | |
13015 | else if (strcmp (name, "nobopt") == 0) | |
13016 | { | |
13017 | mips_opts.nobopt = 1; | |
13018 | } | |
ad3fea08 TS |
13019 | else if (strcmp (name, "gp=default") == 0) |
13020 | mips_opts.gp32 = file_mips_gp32; | |
13021 | else if (strcmp (name, "gp=32") == 0) | |
13022 | mips_opts.gp32 = 1; | |
13023 | else if (strcmp (name, "gp=64") == 0) | |
13024 | { | |
13025 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 13026 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
13027 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13028 | mips_opts.gp32 = 0; | |
13029 | } | |
13030 | else if (strcmp (name, "fp=default") == 0) | |
13031 | mips_opts.fp32 = file_mips_fp32; | |
13032 | else if (strcmp (name, "fp=32") == 0) | |
13033 | mips_opts.fp32 = 1; | |
13034 | else if (strcmp (name, "fp=64") == 0) | |
13035 | { | |
13036 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13037 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13038 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13039 | mips_opts.fp32 = 0; | |
13040 | } | |
037b32b9 AN |
13041 | else if (strcmp (name, "softfloat") == 0) |
13042 | mips_opts.soft_float = 1; | |
13043 | else if (strcmp (name, "hardfloat") == 0) | |
13044 | mips_opts.soft_float = 0; | |
13045 | else if (strcmp (name, "singlefloat") == 0) | |
13046 | mips_opts.single_float = 1; | |
13047 | else if (strcmp (name, "doublefloat") == 0) | |
13048 | mips_opts.single_float = 0; | |
252b5132 RH |
13049 | else if (strcmp (name, "mips16") == 0 |
13050 | || strcmp (name, "MIPS-16") == 0) | |
13051 | mips_opts.mips16 = 1; | |
13052 | else if (strcmp (name, "nomips16") == 0 | |
13053 | || strcmp (name, "noMIPS-16") == 0) | |
13054 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13055 | else if (strcmp (name, "smartmips") == 0) |
13056 | { | |
ad3fea08 | 13057 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13058 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13059 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13060 | mips_opts.ase_smartmips = 1; | |
13061 | } | |
13062 | else if (strcmp (name, "nosmartmips") == 0) | |
13063 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13064 | else if (strcmp (name, "mips3d") == 0) |
13065 | mips_opts.ase_mips3d = 1; | |
13066 | else if (strcmp (name, "nomips3d") == 0) | |
13067 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13068 | else if (strcmp (name, "mdmx") == 0) |
13069 | mips_opts.ase_mdmx = 1; | |
13070 | else if (strcmp (name, "nomdmx") == 0) | |
13071 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13072 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13073 | { |
13074 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13075 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13076 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13077 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13078 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13079 | } |
74cd071d | 13080 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13081 | { |
13082 | mips_opts.ase_dsp = 0; | |
13083 | mips_opts.ase_dspr2 = 0; | |
13084 | } | |
13085 | else if (strcmp (name, "dspr2") == 0) | |
13086 | { | |
13087 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13088 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13089 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13090 | mips_opts.ase_dspr2 = 1; | |
13091 | mips_opts.ase_dsp = 1; | |
13092 | } | |
13093 | else if (strcmp (name, "nodspr2") == 0) | |
13094 | { | |
13095 | mips_opts.ase_dspr2 = 0; | |
13096 | mips_opts.ase_dsp = 0; | |
13097 | } | |
ef2e4d86 | 13098 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13099 | { |
13100 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13101 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13102 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13103 | mips_opts.ase_mt = 1; | |
13104 | } | |
ef2e4d86 CF |
13105 | else if (strcmp (name, "nomt") == 0) |
13106 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13107 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13108 | { |
af7ee8bf | 13109 | int reset = 0; |
252b5132 | 13110 | |
1a2c1fad CD |
13111 | /* Permit the user to change the ISA and architecture on the fly. |
13112 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13113 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13114 | { |
13115 | reset = 1; | |
13116 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13117 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13118 | } |
13119 | else if (strncmp (name, "arch=", 5) == 0) | |
13120 | { | |
13121 | const struct mips_cpu_info *p; | |
13122 | ||
13123 | p = mips_parse_cpu("internal use", name + 5); | |
13124 | if (!p) | |
13125 | as_bad (_("unknown architecture %s"), name + 5); | |
13126 | else | |
13127 | { | |
13128 | mips_opts.arch = p->cpu; | |
13129 | mips_opts.isa = p->isa; | |
13130 | } | |
13131 | } | |
81a21e38 TS |
13132 | else if (strncmp (name, "mips", 4) == 0) |
13133 | { | |
13134 | const struct mips_cpu_info *p; | |
13135 | ||
13136 | p = mips_parse_cpu("internal use", name); | |
13137 | if (!p) | |
13138 | as_bad (_("unknown ISA level %s"), name + 4); | |
13139 | else | |
13140 | { | |
13141 | mips_opts.arch = p->cpu; | |
13142 | mips_opts.isa = p->isa; | |
13143 | } | |
13144 | } | |
af7ee8bf | 13145 | else |
81a21e38 | 13146 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13147 | |
13148 | switch (mips_opts.isa) | |
98d3f06f KH |
13149 | { |
13150 | case 0: | |
98d3f06f | 13151 | break; |
af7ee8bf CD |
13152 | case ISA_MIPS1: |
13153 | case ISA_MIPS2: | |
13154 | case ISA_MIPS32: | |
13155 | case ISA_MIPS32R2: | |
98d3f06f KH |
13156 | mips_opts.gp32 = 1; |
13157 | mips_opts.fp32 = 1; | |
13158 | break; | |
af7ee8bf CD |
13159 | case ISA_MIPS3: |
13160 | case ISA_MIPS4: | |
13161 | case ISA_MIPS5: | |
13162 | case ISA_MIPS64: | |
5f74bc13 | 13163 | case ISA_MIPS64R2: |
98d3f06f KH |
13164 | mips_opts.gp32 = 0; |
13165 | mips_opts.fp32 = 0; | |
13166 | break; | |
13167 | default: | |
13168 | as_bad (_("unknown ISA level %s"), name + 4); | |
13169 | break; | |
13170 | } | |
af7ee8bf | 13171 | if (reset) |
98d3f06f | 13172 | { |
af7ee8bf CD |
13173 | mips_opts.gp32 = file_mips_gp32; |
13174 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13175 | } |
252b5132 RH |
13176 | } |
13177 | else if (strcmp (name, "autoextend") == 0) | |
13178 | mips_opts.noautoextend = 0; | |
13179 | else if (strcmp (name, "noautoextend") == 0) | |
13180 | mips_opts.noautoextend = 1; | |
13181 | else if (strcmp (name, "push") == 0) | |
13182 | { | |
13183 | struct mips_option_stack *s; | |
13184 | ||
13185 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13186 | s->next = mips_opts_stack; | |
13187 | s->options = mips_opts; | |
13188 | mips_opts_stack = s; | |
13189 | } | |
13190 | else if (strcmp (name, "pop") == 0) | |
13191 | { | |
13192 | struct mips_option_stack *s; | |
13193 | ||
13194 | s = mips_opts_stack; | |
13195 | if (s == NULL) | |
13196 | as_bad (_(".set pop with no .set push")); | |
13197 | else | |
13198 | { | |
13199 | /* If we're changing the reorder mode we need to handle | |
13200 | delay slots correctly. */ | |
13201 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13202 | start_noreorder (); |
252b5132 | 13203 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13204 | end_noreorder (); |
252b5132 RH |
13205 | |
13206 | mips_opts = s->options; | |
13207 | mips_opts_stack = s->next; | |
13208 | free (s); | |
13209 | } | |
13210 | } | |
aed1a261 RS |
13211 | else if (strcmp (name, "sym32") == 0) |
13212 | mips_opts.sym32 = TRUE; | |
13213 | else if (strcmp (name, "nosym32") == 0) | |
13214 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13215 | else if (strchr (name, ',')) |
13216 | { | |
13217 | /* Generic ".set" directive; use the generic handler. */ | |
13218 | *input_line_pointer = ch; | |
13219 | input_line_pointer = name; | |
13220 | s_set (0); | |
13221 | return; | |
13222 | } | |
252b5132 RH |
13223 | else |
13224 | { | |
13225 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13226 | } | |
13227 | *input_line_pointer = ch; | |
13228 | demand_empty_rest_of_line (); | |
13229 | } | |
13230 | ||
13231 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13232 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13233 | ||
13234 | static void | |
17a2f251 | 13235 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13236 | { |
13237 | mips_pic = SVR4_PIC; | |
143d77c5 | 13238 | mips_abicalls = TRUE; |
4d0d148d TS |
13239 | |
13240 | if (g_switch_seen && g_switch_value != 0) | |
13241 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13242 | g_switch_value = 0; | |
13243 | ||
252b5132 RH |
13244 | bfd_set_gp_size (stdoutput, 0); |
13245 | demand_empty_rest_of_line (); | |
13246 | } | |
13247 | ||
13248 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13249 | PIC code. It sets the $gp register for the function based on the | |
13250 | function address, which is in the register named in the argument. | |
13251 | This uses a relocation against _gp_disp, which is handled specially | |
13252 | by the linker. The result is: | |
13253 | lui $gp,%hi(_gp_disp) | |
13254 | addiu $gp,$gp,%lo(_gp_disp) | |
13255 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13256 | The .cpload argument is normally $25 == $t9. |
13257 | ||
13258 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13259 | lui $gp,%hi(__gnu_local_gp) |
13260 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13261 | and the argument is ignored. This saves an instruction, but the |
13262 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13263 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13264 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13265 | |
13266 | static void | |
17a2f251 | 13267 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13268 | { |
13269 | expressionS ex; | |
aa6975fb ILT |
13270 | int reg; |
13271 | int in_shared; | |
252b5132 | 13272 | |
6478892d TS |
13273 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13274 | .cpload is ignored. */ | |
13275 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13276 | { |
13277 | s_ignore (0); | |
13278 | return; | |
13279 | } | |
13280 | ||
d3ecfc59 | 13281 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13282 | if (mips_opts.noreorder == 0) |
13283 | as_warn (_(".cpload not in noreorder section")); | |
13284 | ||
aa6975fb ILT |
13285 | reg = tc_get_register (0); |
13286 | ||
13287 | /* If we need to produce a 64-bit address, we are better off using | |
13288 | the default instruction sequence. */ | |
aed1a261 | 13289 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13290 | |
252b5132 | 13291 | ex.X_op = O_symbol; |
bbe506e8 TS |
13292 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13293 | "__gnu_local_gp"); | |
252b5132 RH |
13294 | ex.X_op_symbol = NULL; |
13295 | ex.X_add_number = 0; | |
13296 | ||
13297 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13298 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13299 | |
584892a6 | 13300 | macro_start (); |
67c0d1eb RS |
13301 | macro_build_lui (&ex, mips_gp_register); |
13302 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13303 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13304 | if (in_shared) |
13305 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13306 | mips_gp_register, reg); | |
584892a6 | 13307 | macro_end (); |
252b5132 RH |
13308 | |
13309 | demand_empty_rest_of_line (); | |
13310 | } | |
13311 | ||
6478892d TS |
13312 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13313 | .cpsetup $reg1, offset|$reg2, label | |
13314 | ||
13315 | If offset is given, this results in: | |
13316 | sd $gp, offset($sp) | |
956cd1d6 | 13317 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13318 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13319 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13320 | |
13321 | If $reg2 is given, this results in: | |
13322 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13323 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13324 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13325 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13326 | $reg1 is normally $25 == $t9. |
13327 | ||
13328 | The -mno-shared option replaces the last three instructions with | |
13329 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13330 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13331 | |
6478892d | 13332 | static void |
17a2f251 | 13333 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13334 | { |
13335 | expressionS ex_off; | |
13336 | expressionS ex_sym; | |
13337 | int reg1; | |
6478892d | 13338 | |
8586fc66 | 13339 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13340 | We also need NewABI support. */ |
13341 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13342 | { | |
13343 | s_ignore (0); | |
13344 | return; | |
13345 | } | |
13346 | ||
13347 | reg1 = tc_get_register (0); | |
13348 | SKIP_WHITESPACE (); | |
13349 | if (*input_line_pointer != ',') | |
13350 | { | |
13351 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13352 | return; | |
13353 | } | |
13354 | else | |
80245285 | 13355 | ++input_line_pointer; |
6478892d TS |
13356 | SKIP_WHITESPACE (); |
13357 | if (*input_line_pointer == '$') | |
80245285 TS |
13358 | { |
13359 | mips_cpreturn_register = tc_get_register (0); | |
13360 | mips_cpreturn_offset = -1; | |
13361 | } | |
6478892d | 13362 | else |
80245285 TS |
13363 | { |
13364 | mips_cpreturn_offset = get_absolute_expression (); | |
13365 | mips_cpreturn_register = -1; | |
13366 | } | |
6478892d TS |
13367 | SKIP_WHITESPACE (); |
13368 | if (*input_line_pointer != ',') | |
13369 | { | |
13370 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13371 | return; | |
13372 | } | |
13373 | else | |
f9419b05 | 13374 | ++input_line_pointer; |
6478892d | 13375 | SKIP_WHITESPACE (); |
f21f8242 | 13376 | expression (&ex_sym); |
6478892d | 13377 | |
584892a6 | 13378 | macro_start (); |
6478892d TS |
13379 | if (mips_cpreturn_register == -1) |
13380 | { | |
13381 | ex_off.X_op = O_constant; | |
13382 | ex_off.X_add_symbol = NULL; | |
13383 | ex_off.X_op_symbol = NULL; | |
13384 | ex_off.X_add_number = mips_cpreturn_offset; | |
13385 | ||
67c0d1eb | 13386 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13387 | BFD_RELOC_LO16, SP); |
6478892d TS |
13388 | } |
13389 | else | |
67c0d1eb | 13390 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13391 | mips_gp_register, 0); |
6478892d | 13392 | |
aed1a261 | 13393 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13394 | { |
13395 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13396 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13397 | BFD_RELOC_HI16_S); | |
13398 | ||
13399 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13400 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13401 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13402 | ||
13403 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13404 | mips_gp_register, reg1); | |
13405 | } | |
13406 | else | |
13407 | { | |
13408 | expressionS ex; | |
13409 | ||
13410 | ex.X_op = O_symbol; | |
4184909a | 13411 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13412 | ex.X_op_symbol = NULL; |
13413 | ex.X_add_number = 0; | |
6e1304d8 | 13414 | |
aa6975fb ILT |
13415 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13416 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13417 | ||
13418 | macro_build_lui (&ex, mips_gp_register); | |
13419 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13420 | mips_gp_register, BFD_RELOC_LO16); | |
13421 | } | |
f21f8242 | 13422 | |
584892a6 | 13423 | macro_end (); |
6478892d TS |
13424 | |
13425 | demand_empty_rest_of_line (); | |
13426 | } | |
13427 | ||
13428 | static void | |
17a2f251 | 13429 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13430 | { |
13431 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13432 | .cplocal is ignored. */ |
6478892d TS |
13433 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13434 | { | |
13435 | s_ignore (0); | |
13436 | return; | |
13437 | } | |
13438 | ||
13439 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13440 | demand_empty_rest_of_line (); |
6478892d TS |
13441 | } |
13442 | ||
252b5132 RH |
13443 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13444 | offset from $sp. The offset is remembered, and after making a PIC | |
13445 | call $gp is restored from that location. */ | |
13446 | ||
13447 | static void | |
17a2f251 | 13448 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13449 | { |
13450 | expressionS ex; | |
252b5132 | 13451 | |
6478892d | 13452 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13453 | .cprestore is ignored. */ |
6478892d | 13454 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13455 | { |
13456 | s_ignore (0); | |
13457 | return; | |
13458 | } | |
13459 | ||
13460 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13461 | mips_cprestore_valid = 1; |
252b5132 RH |
13462 | |
13463 | ex.X_op = O_constant; | |
13464 | ex.X_add_symbol = NULL; | |
13465 | ex.X_op_symbol = NULL; | |
13466 | ex.X_add_number = mips_cprestore_offset; | |
13467 | ||
584892a6 | 13468 | macro_start (); |
67c0d1eb RS |
13469 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13470 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13471 | macro_end (); |
252b5132 RH |
13472 | |
13473 | demand_empty_rest_of_line (); | |
13474 | } | |
13475 | ||
6478892d | 13476 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13477 | was given in the preceding .cpsetup, it results in: |
6478892d | 13478 | ld $gp, offset($sp) |
76b3015f | 13479 | |
6478892d | 13480 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13481 | daddu $gp, $reg2, $0 */ |
13482 | ||
6478892d | 13483 | static void |
17a2f251 | 13484 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13485 | { |
13486 | expressionS ex; | |
6478892d TS |
13487 | |
13488 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13489 | We also need NewABI support. */ | |
13490 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13491 | { | |
13492 | s_ignore (0); | |
13493 | return; | |
13494 | } | |
13495 | ||
584892a6 | 13496 | macro_start (); |
6478892d TS |
13497 | if (mips_cpreturn_register == -1) |
13498 | { | |
13499 | ex.X_op = O_constant; | |
13500 | ex.X_add_symbol = NULL; | |
13501 | ex.X_op_symbol = NULL; | |
13502 | ex.X_add_number = mips_cpreturn_offset; | |
13503 | ||
67c0d1eb | 13504 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13505 | } |
13506 | else | |
67c0d1eb | 13507 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13508 | mips_cpreturn_register, 0); |
584892a6 | 13509 | macro_end (); |
6478892d TS |
13510 | |
13511 | demand_empty_rest_of_line (); | |
13512 | } | |
13513 | ||
741d6ea8 JM |
13514 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13515 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13516 | use in DWARF debug information. */ | |
13517 | ||
13518 | static void | |
13519 | s_dtprel_internal (size_t bytes) | |
13520 | { | |
13521 | expressionS ex; | |
13522 | char *p; | |
13523 | ||
13524 | expression (&ex); | |
13525 | ||
13526 | if (ex.X_op != O_symbol) | |
13527 | { | |
13528 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13529 | ? ".dtpreldword" | |
13530 | : ".dtprelword")); | |
13531 | ignore_rest_of_line (); | |
13532 | } | |
13533 | ||
13534 | p = frag_more (bytes); | |
13535 | md_number_to_chars (p, 0, bytes); | |
13536 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13537 | (bytes == 8 | |
13538 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13539 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13540 | ||
13541 | demand_empty_rest_of_line (); | |
13542 | } | |
13543 | ||
13544 | /* Handle .dtprelword. */ | |
13545 | ||
13546 | static void | |
13547 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13548 | { | |
13549 | s_dtprel_internal (4); | |
13550 | } | |
13551 | ||
13552 | /* Handle .dtpreldword. */ | |
13553 | ||
13554 | static void | |
13555 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13556 | { | |
13557 | s_dtprel_internal (8); | |
13558 | } | |
13559 | ||
6478892d TS |
13560 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13561 | code. It sets the offset to use in gp_rel relocations. */ | |
13562 | ||
13563 | static void | |
17a2f251 | 13564 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13565 | { |
13566 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13567 | We also need NewABI support. */ | |
13568 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13569 | { | |
13570 | s_ignore (0); | |
13571 | return; | |
13572 | } | |
13573 | ||
def2e0dd | 13574 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13575 | |
13576 | demand_empty_rest_of_line (); | |
13577 | } | |
13578 | ||
252b5132 RH |
13579 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13580 | code. It generates a 32 bit GP relative reloc. */ | |
13581 | ||
13582 | static void | |
17a2f251 | 13583 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13584 | { |
a8dbcb85 TS |
13585 | segment_info_type *si; |
13586 | struct insn_label_list *l; | |
252b5132 RH |
13587 | symbolS *label; |
13588 | expressionS ex; | |
13589 | char *p; | |
13590 | ||
13591 | /* When not generating PIC code, this is treated as .word. */ | |
13592 | if (mips_pic != SVR4_PIC) | |
13593 | { | |
13594 | s_cons (2); | |
13595 | return; | |
13596 | } | |
13597 | ||
a8dbcb85 TS |
13598 | si = seg_info (now_seg); |
13599 | l = si->label_list; | |
13600 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13601 | mips_emit_delays (); |
252b5132 RH |
13602 | if (auto_align) |
13603 | mips_align (2, 0, label); | |
252b5132 RH |
13604 | |
13605 | expression (&ex); | |
a1facbec | 13606 | mips_clear_insn_labels (); |
252b5132 RH |
13607 | |
13608 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13609 | { | |
13610 | as_bad (_("Unsupported use of .gpword")); | |
13611 | ignore_rest_of_line (); | |
13612 | } | |
13613 | ||
13614 | p = frag_more (4); | |
17a2f251 | 13615 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13616 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13617 | BFD_RELOC_GPREL32); |
252b5132 RH |
13618 | |
13619 | demand_empty_rest_of_line (); | |
13620 | } | |
13621 | ||
10181a0d | 13622 | static void |
17a2f251 | 13623 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13624 | { |
a8dbcb85 TS |
13625 | segment_info_type *si; |
13626 | struct insn_label_list *l; | |
10181a0d AO |
13627 | symbolS *label; |
13628 | expressionS ex; | |
13629 | char *p; | |
13630 | ||
13631 | /* When not generating PIC code, this is treated as .dword. */ | |
13632 | if (mips_pic != SVR4_PIC) | |
13633 | { | |
13634 | s_cons (3); | |
13635 | return; | |
13636 | } | |
13637 | ||
a8dbcb85 TS |
13638 | si = seg_info (now_seg); |
13639 | l = si->label_list; | |
13640 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13641 | mips_emit_delays (); |
10181a0d AO |
13642 | if (auto_align) |
13643 | mips_align (3, 0, label); | |
10181a0d AO |
13644 | |
13645 | expression (&ex); | |
a1facbec | 13646 | mips_clear_insn_labels (); |
10181a0d AO |
13647 | |
13648 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13649 | { | |
13650 | as_bad (_("Unsupported use of .gpdword")); | |
13651 | ignore_rest_of_line (); | |
13652 | } | |
13653 | ||
13654 | p = frag_more (8); | |
17a2f251 | 13655 | md_number_to_chars (p, 0, 8); |
a105a300 | 13656 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13657 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13658 | |
13659 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13660 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13661 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13662 | |
13663 | demand_empty_rest_of_line (); | |
13664 | } | |
13665 | ||
252b5132 RH |
13666 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13667 | tables in SVR4 PIC code. */ | |
13668 | ||
13669 | static void | |
17a2f251 | 13670 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13671 | { |
252b5132 RH |
13672 | int reg; |
13673 | ||
10181a0d AO |
13674 | /* This is ignored when not generating SVR4 PIC code. */ |
13675 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13676 | { |
13677 | s_ignore (0); | |
13678 | return; | |
13679 | } | |
13680 | ||
13681 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13682 | macro_start (); |
252b5132 | 13683 | reg = tc_get_register (0); |
67c0d1eb | 13684 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13685 | macro_end (); |
252b5132 | 13686 | |
bdaaa2e1 | 13687 | demand_empty_rest_of_line (); |
252b5132 RH |
13688 | } |
13689 | ||
13690 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13691 | mips16 mode. This permits the linker to handle them specially, | |
13692 | such as generating jalx instructions when needed. We also make | |
13693 | them odd for the duration of the assembly, in order to generate the | |
13694 | right sort of code. We will make them even in the adjust_symtab | |
13695 | routine, while leaving them marked. This is convenient for the | |
13696 | debugger and the disassembler. The linker knows to make them odd | |
13697 | again. */ | |
13698 | ||
13699 | static void | |
17a2f251 | 13700 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13701 | { |
f9419b05 | 13702 | mips16_mark_labels (); |
252b5132 RH |
13703 | |
13704 | demand_empty_rest_of_line (); | |
13705 | } | |
13706 | ||
13707 | /* Handle a .stabn directive. We need these in order to mark a label | |
13708 | as being a mips16 text label correctly. Sometimes the compiler | |
13709 | will emit a label, followed by a .stabn, and then switch sections. | |
13710 | If the label and .stabn are in mips16 mode, then the label is | |
13711 | really a mips16 text label. */ | |
13712 | ||
13713 | static void | |
17a2f251 | 13714 | s_mips_stab (int type) |
252b5132 | 13715 | { |
f9419b05 | 13716 | if (type == 'n') |
252b5132 RH |
13717 | mips16_mark_labels (); |
13718 | ||
13719 | s_stab (type); | |
13720 | } | |
13721 | ||
54f4ddb3 | 13722 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13723 | |
13724 | static void | |
17a2f251 | 13725 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13726 | { |
13727 | char *name; | |
13728 | int c; | |
13729 | symbolS *symbolP; | |
13730 | expressionS exp; | |
13731 | ||
13732 | name = input_line_pointer; | |
13733 | c = get_symbol_end (); | |
13734 | symbolP = symbol_find_or_make (name); | |
13735 | S_SET_WEAK (symbolP); | |
13736 | *input_line_pointer = c; | |
13737 | ||
13738 | SKIP_WHITESPACE (); | |
13739 | ||
13740 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13741 | { | |
13742 | if (S_IS_DEFINED (symbolP)) | |
13743 | { | |
20203fb9 | 13744 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13745 | S_GET_NAME (symbolP)); |
13746 | ignore_rest_of_line (); | |
13747 | return; | |
13748 | } | |
bdaaa2e1 | 13749 | |
252b5132 RH |
13750 | if (*input_line_pointer == ',') |
13751 | { | |
13752 | ++input_line_pointer; | |
13753 | SKIP_WHITESPACE (); | |
13754 | } | |
bdaaa2e1 | 13755 | |
252b5132 RH |
13756 | expression (&exp); |
13757 | if (exp.X_op != O_symbol) | |
13758 | { | |
20203fb9 | 13759 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13760 | ignore_rest_of_line (); |
252b5132 RH |
13761 | return; |
13762 | } | |
49309057 | 13763 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13764 | } |
13765 | ||
13766 | demand_empty_rest_of_line (); | |
13767 | } | |
13768 | ||
13769 | /* Parse a register string into a number. Called from the ECOFF code | |
13770 | to parse .frame. The argument is non-zero if this is the frame | |
13771 | register, so that we can record it in mips_frame_reg. */ | |
13772 | ||
13773 | int | |
17a2f251 | 13774 | tc_get_register (int frame) |
252b5132 | 13775 | { |
707bfff6 | 13776 | unsigned int reg; |
252b5132 RH |
13777 | |
13778 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13779 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13780 | reg = 0; | |
252b5132 | 13781 | if (frame) |
7a621144 DJ |
13782 | { |
13783 | mips_frame_reg = reg != 0 ? reg : SP; | |
13784 | mips_frame_reg_valid = 1; | |
13785 | mips_cprestore_valid = 0; | |
13786 | } | |
252b5132 RH |
13787 | return reg; |
13788 | } | |
13789 | ||
13790 | valueT | |
17a2f251 | 13791 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13792 | { |
13793 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13794 | ||
b4c71f56 TS |
13795 | if (IS_ELF) |
13796 | { | |
13797 | /* We don't need to align ELF sections to the full alignment. | |
13798 | However, Irix 5 may prefer that we align them at least to a 16 | |
13799 | byte boundary. We don't bother to align the sections if we | |
13800 | are targeted for an embedded system. */ | |
c41e87e3 | 13801 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13802 | return addr; |
13803 | if (align > 4) | |
13804 | align = 4; | |
13805 | } | |
252b5132 RH |
13806 | |
13807 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13808 | } | |
13809 | ||
13810 | /* Utility routine, called from above as well. If called while the | |
13811 | input file is still being read, it's only an approximation. (For | |
13812 | example, a symbol may later become defined which appeared to be | |
13813 | undefined earlier.) */ | |
13814 | ||
13815 | static int | |
17a2f251 | 13816 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13817 | { |
13818 | if (sym == 0) | |
13819 | return 0; | |
13820 | ||
4d0d148d | 13821 | if (g_switch_value > 0) |
252b5132 RH |
13822 | { |
13823 | const char *symname; | |
13824 | int change; | |
13825 | ||
c9914766 | 13826 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13827 | register. It can be if it is smaller than the -G size or if |
13828 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13829 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13830 | they can. */ |
13831 | symname = S_GET_NAME (sym); | |
13832 | if (symname != (const char *) NULL | |
13833 | && (strcmp (symname, "eprol") == 0 | |
13834 | || strcmp (symname, "etext") == 0 | |
13835 | || strcmp (symname, "_gp") == 0 | |
13836 | || strcmp (symname, "edata") == 0 | |
13837 | || strcmp (symname, "_fbss") == 0 | |
13838 | || strcmp (symname, "_fdata") == 0 | |
13839 | || strcmp (symname, "_ftext") == 0 | |
13840 | || strcmp (symname, "end") == 0 | |
13841 | || strcmp (symname, "_gp_disp") == 0)) | |
13842 | change = 1; | |
13843 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13844 | && (0 | |
13845 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13846 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13847 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13848 | <= g_switch_value)) | |
252b5132 RH |
13849 | #endif |
13850 | /* We must defer this decision until after the whole | |
13851 | file has been read, since there might be a .extern | |
13852 | after the first use of this symbol. */ | |
13853 | || (before_relaxing | |
13854 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13855 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13856 | #endif |
13857 | && S_GET_VALUE (sym) == 0) | |
13858 | || (S_GET_VALUE (sym) != 0 | |
13859 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13860 | change = 0; | |
13861 | else | |
13862 | { | |
13863 | const char *segname; | |
13864 | ||
13865 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13866 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13867 | && strcmp (segname, ".lit4") != 0); |
13868 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13869 | && strcmp (segname, ".sbss") != 0 |
13870 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13871 | && strncmp (segname, ".sbss.", 6) != 0 |
13872 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13873 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13874 | } |
13875 | return change; | |
13876 | } | |
13877 | else | |
c9914766 | 13878 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13879 | return 1; |
13880 | } | |
13881 | ||
5919d012 RS |
13882 | |
13883 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13884 | ||
13885 | static bfd_boolean | |
17a2f251 | 13886 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13887 | { |
13888 | asection *symsec; | |
5919d012 RS |
13889 | |
13890 | /* Handle the case of a symbol equated to another symbol. */ | |
13891 | while (symbol_equated_reloc_p (sym)) | |
13892 | { | |
13893 | symbolS *n; | |
13894 | ||
5f0fe04b | 13895 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13896 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13897 | if (n == sym) | |
13898 | break; | |
13899 | sym = n; | |
13900 | } | |
13901 | ||
df1f3cda DD |
13902 | if (symbol_section_p (sym)) |
13903 | return TRUE; | |
13904 | ||
5919d012 RS |
13905 | symsec = S_GET_SEGMENT (sym); |
13906 | ||
5919d012 RS |
13907 | /* This must duplicate the test in adjust_reloc_syms. */ |
13908 | return (symsec != &bfd_und_section | |
13909 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13910 | && !bfd_is_com_section (symsec) |
13911 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13912 | #ifdef OBJ_ELF |
13913 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13914 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13915 | #endif |
13916 | ); | |
13917 | } | |
13918 | ||
13919 | ||
252b5132 RH |
13920 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13921 | extended opcode. SEC is the section the frag is in. */ | |
13922 | ||
13923 | static int | |
17a2f251 | 13924 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13925 | { |
13926 | int type; | |
3994f87e | 13927 | const struct mips16_immed_operand *op; |
252b5132 RH |
13928 | offsetT val; |
13929 | int mintiny, maxtiny; | |
13930 | segT symsec; | |
98aa84af | 13931 | fragS *sym_frag; |
252b5132 RH |
13932 | |
13933 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13934 | return 0; | |
13935 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13936 | return 1; | |
13937 | ||
13938 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13939 | op = mips16_immed_operands; | |
13940 | while (op->type != type) | |
13941 | { | |
13942 | ++op; | |
9c2799c2 | 13943 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13944 | } |
13945 | ||
13946 | if (op->unsp) | |
13947 | { | |
13948 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13949 | { | |
13950 | mintiny = 1; | |
13951 | maxtiny = 1 << op->nbits; | |
13952 | } | |
13953 | else | |
13954 | { | |
13955 | mintiny = 0; | |
13956 | maxtiny = (1 << op->nbits) - 1; | |
13957 | } | |
13958 | } | |
13959 | else | |
13960 | { | |
13961 | mintiny = - (1 << (op->nbits - 1)); | |
13962 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13963 | } | |
13964 | ||
98aa84af | 13965 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13966 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13967 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13968 | |
13969 | if (op->pcrel) | |
13970 | { | |
13971 | addressT addr; | |
13972 | ||
13973 | /* We won't have the section when we are called from | |
13974 | mips_relax_frag. However, we will always have been called | |
13975 | from md_estimate_size_before_relax first. If this is a | |
13976 | branch to a different section, we mark it as such. If SEC is | |
13977 | NULL, and the frag is not marked, then it must be a branch to | |
13978 | the same section. */ | |
13979 | if (sec == NULL) | |
13980 | { | |
13981 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13982 | return 1; | |
13983 | } | |
13984 | else | |
13985 | { | |
98aa84af | 13986 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13987 | if (symsec != sec) |
13988 | { | |
13989 | fragp->fr_subtype = | |
13990 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13991 | ||
13992 | /* FIXME: We should support this, and let the linker | |
13993 | catch branches and loads that are out of range. */ | |
13994 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13995 | _("unsupported PC relative reference to different section")); | |
13996 | ||
13997 | return 1; | |
13998 | } | |
98aa84af AM |
13999 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
14000 | /* Assume non-extended on the first relaxation pass. | |
14001 | The address we have calculated will be bogus if this is | |
14002 | a forward branch to another frag, as the forward frag | |
14003 | will have fr_address == 0. */ | |
14004 | return 0; | |
252b5132 RH |
14005 | } |
14006 | ||
14007 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
14008 | the same section. If the relax_marker of the symbol fragment |
14009 | differs from the relax_marker of this fragment, we have not | |
14010 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
14011 | in STRETCH in order to get a better estimate of the address. |
14012 | This particularly matters because of the shift bits. */ | |
14013 | if (stretch != 0 | |
98aa84af | 14014 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
14015 | { |
14016 | fragS *f; | |
14017 | ||
14018 | /* Adjust stretch for any alignment frag. Note that if have | |
14019 | been expanding the earlier code, the symbol may be | |
14020 | defined in what appears to be an earlier frag. FIXME: | |
14021 | This doesn't handle the fr_subtype field, which specifies | |
14022 | a maximum number of bytes to skip when doing an | |
14023 | alignment. */ | |
98aa84af | 14024 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
14025 | { |
14026 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
14027 | { | |
14028 | if (stretch < 0) | |
14029 | stretch = - ((- stretch) | |
14030 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
14031 | else | |
14032 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
14033 | if (stretch == 0) | |
14034 | break; | |
14035 | } | |
14036 | } | |
14037 | if (f != NULL) | |
14038 | val += stretch; | |
14039 | } | |
14040 | ||
14041 | addr = fragp->fr_address + fragp->fr_fix; | |
14042 | ||
14043 | /* The base address rules are complicated. The base address of | |
14044 | a branch is the following instruction. The base address of a | |
14045 | PC relative load or add is the instruction itself, but if it | |
14046 | is in a delay slot (in which case it can not be extended) use | |
14047 | the address of the instruction whose delay slot it is in. */ | |
14048 | if (type == 'p' || type == 'q') | |
14049 | { | |
14050 | addr += 2; | |
14051 | ||
14052 | /* If we are currently assuming that this frag should be | |
14053 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14054 | higher. */ |
252b5132 RH |
14055 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14056 | addr += 2; | |
14057 | ||
14058 | /* Ignore the low bit in the target, since it will be set | |
14059 | for a text label. */ | |
14060 | if ((val & 1) != 0) | |
14061 | --val; | |
14062 | } | |
14063 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14064 | addr -= 4; | |
14065 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14066 | addr -= 2; | |
14067 | ||
14068 | val -= addr & ~ ((1 << op->shift) - 1); | |
14069 | ||
14070 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14071 | if (type == 'p' || type == 'q') | |
14072 | val /= 2; | |
14073 | ||
14074 | /* If any of the shifted bits are set, we must use an extended | |
14075 | opcode. If the address depends on the size of this | |
14076 | instruction, this can lead to a loop, so we arrange to always | |
14077 | use an extended opcode. We only check this when we are in | |
14078 | the main relaxation loop, when SEC is NULL. */ | |
14079 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14080 | { | |
14081 | fragp->fr_subtype = | |
14082 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14083 | return 1; | |
14084 | } | |
14085 | ||
14086 | /* If we are about to mark a frag as extended because the value | |
14087 | is precisely maxtiny + 1, then there is a chance of an | |
14088 | infinite loop as in the following code: | |
14089 | la $4,foo | |
14090 | .skip 1020 | |
14091 | .align 2 | |
14092 | foo: | |
14093 | In this case when the la is extended, foo is 0x3fc bytes | |
14094 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14095 | the la must be extended. To avoid this loop, we mark the | |
14096 | frag as extended if it was small, and is about to become | |
14097 | extended with a value of maxtiny + 1. */ | |
14098 | if (val == ((maxtiny + 1) << op->shift) | |
14099 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14100 | && sec == NULL) | |
14101 | { | |
14102 | fragp->fr_subtype = | |
14103 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14104 | return 1; | |
14105 | } | |
14106 | } | |
14107 | else if (symsec != absolute_section && sec != NULL) | |
14108 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14109 | ||
14110 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14111 | || val < (mintiny << op->shift) | |
14112 | || val > (maxtiny << op->shift)) | |
14113 | return 1; | |
14114 | else | |
14115 | return 0; | |
14116 | } | |
14117 | ||
4a6a3df4 AO |
14118 | /* Compute the length of a branch sequence, and adjust the |
14119 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14120 | worst-case length is computed, with UPDATE being used to indicate | |
14121 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14122 | branch is to be computed. */ | |
14123 | static int | |
17a2f251 | 14124 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14125 | { |
b34976b6 | 14126 | bfd_boolean toofar; |
4a6a3df4 AO |
14127 | int length; |
14128 | ||
14129 | if (fragp | |
14130 | && S_IS_DEFINED (fragp->fr_symbol) | |
14131 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14132 | { | |
14133 | addressT addr; | |
14134 | offsetT val; | |
14135 | ||
14136 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14137 | ||
14138 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14139 | ||
14140 | val -= addr; | |
14141 | ||
14142 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14143 | } | |
14144 | else if (fragp) | |
14145 | /* If the symbol is not defined or it's in a different segment, | |
14146 | assume the user knows what's going on and emit a short | |
14147 | branch. */ | |
b34976b6 | 14148 | toofar = FALSE; |
4a6a3df4 | 14149 | else |
b34976b6 | 14150 | toofar = TRUE; |
4a6a3df4 AO |
14151 | |
14152 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14153 | fragp->fr_subtype | |
66b3e8da MR |
14154 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
14155 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
14156 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14157 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14158 | toofar); | |
14159 | ||
14160 | length = 4; | |
14161 | if (toofar) | |
14162 | { | |
14163 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14164 | length += 8; | |
14165 | ||
14166 | if (mips_pic != NO_PIC) | |
14167 | { | |
14168 | /* Additional space for PIC loading of target address. */ | |
14169 | length += 8; | |
14170 | if (mips_opts.isa == ISA_MIPS1) | |
14171 | /* Additional space for $at-stabilizing nop. */ | |
14172 | length += 4; | |
14173 | } | |
14174 | ||
14175 | /* If branch is conditional. */ | |
14176 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14177 | length += 8; | |
14178 | } | |
b34976b6 | 14179 | |
4a6a3df4 AO |
14180 | return length; |
14181 | } | |
14182 | ||
252b5132 RH |
14183 | /* Estimate the size of a frag before relaxing. Unless this is the |
14184 | mips16, we are not really relaxing here, and the final size is | |
14185 | encoded in the subtype information. For the mips16, we have to | |
14186 | decide whether we are using an extended opcode or not. */ | |
14187 | ||
252b5132 | 14188 | int |
17a2f251 | 14189 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14190 | { |
5919d012 | 14191 | int change; |
252b5132 | 14192 | |
4a6a3df4 AO |
14193 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14194 | { | |
14195 | ||
b34976b6 AM |
14196 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14197 | ||
4a6a3df4 AO |
14198 | return fragp->fr_var; |
14199 | } | |
14200 | ||
252b5132 | 14201 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14202 | /* We don't want to modify the EXTENDED bit here; it might get us |
14203 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14204 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14205 | |
14206 | if (mips_pic == NO_PIC) | |
5919d012 | 14207 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14208 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14209 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14210 | else if (mips_pic == VXWORKS_PIC) |
14211 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14212 | change = 0; | |
252b5132 RH |
14213 | else |
14214 | abort (); | |
14215 | ||
14216 | if (change) | |
14217 | { | |
4d7206a2 | 14218 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14219 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14220 | } |
4d7206a2 RS |
14221 | else |
14222 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14223 | } |
14224 | ||
14225 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14226 | should be converted into a reloc against a section. */ |
252b5132 RH |
14227 | |
14228 | int | |
17a2f251 | 14229 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14230 | { |
252b5132 RH |
14231 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14232 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14233 | return 0; | |
a161fe53 | 14234 | |
252b5132 RH |
14235 | if (fixp->fx_addsy == NULL) |
14236 | return 1; | |
a161fe53 | 14237 | |
de7e6852 RS |
14238 | /* If symbol SYM is in a mergeable section, relocations of the form |
14239 | SYM + 0 can usually be made section-relative. The mergeable data | |
14240 | is then identified by the section offset rather than by the symbol. | |
14241 | ||
14242 | However, if we're generating REL LO16 relocations, the offset is split | |
14243 | between the LO16 and parterning high part relocation. The linker will | |
14244 | need to recalculate the complete offset in order to correctly identify | |
14245 | the merge data. | |
14246 | ||
14247 | The linker has traditionally not looked for the parterning high part | |
14248 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14249 | placed anywhere. Rather than break backwards compatibility by changing | |
14250 | this, it seems better not to force the issue, and instead keep the | |
14251 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14252 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14253 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14254 | && HAVE_IN_PLACE_ADDENDS |
14255 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14256 | return 0; | |
14257 | ||
ce70d90a MR |
14258 | /* There is no place to store an in-place offset for JALR relocations. |
14259 | Likewise an in-range offset of PC-relative relocations may overflow | |
14260 | the in-place relocatable field if recalculated against the start | |
14261 | address of the symbol's containing section. */ | |
14262 | if (HAVE_IN_PLACE_ADDENDS | |
14263 | && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR)) | |
1180b5a4 RS |
14264 | return 0; |
14265 | ||
252b5132 | 14266 | #ifdef OBJ_ELF |
b314ec0e RS |
14267 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14268 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14269 | relocations against MIPS16 functions; in this case, the stub becomes | |
14270 | the function's canonical address. | |
14271 | ||
14272 | Floating-point stubs are stored in unique .mips16.call.* or | |
14273 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14274 | the first relocation in section S must be against F; this is how the | |
14275 | linker determines the target function. All relocations that might | |
14276 | resolve to T must also be against F. We therefore have the following | |
14277 | restrictions, which are given in an intentionally-redundant way: | |
14278 | ||
14279 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14280 | symbols. | |
14281 | ||
14282 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14283 | if that stub might be used. | |
14284 | ||
14285 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14286 | symbols. | |
14287 | ||
14288 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14289 | that stub might be used. | |
14290 | ||
14291 | There is a further restriction: | |
14292 | ||
14293 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14294 | on targets with in-place addends; the relocation field cannot | |
14295 | encode the low bit. | |
14296 | ||
14297 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14298 | against a MIPS16 symbol. | |
14299 | ||
14300 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14301 | relocation against some symbol R, no relocation against R may be | |
14302 | reduced. (Note that this deals with (2) as well as (1) because | |
14303 | relocations against global symbols will never be reduced on ELF | |
14304 | targets.) This approach is a little simpler than trying to detect | |
14305 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14306 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14307 | if (IS_ELF |
b314ec0e | 14308 | && fixp->fx_subsy == NULL |
30c09090 | 14309 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14310 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14311 | return 0; |
14312 | #endif | |
a161fe53 | 14313 | |
252b5132 RH |
14314 | return 1; |
14315 | } | |
14316 | ||
14317 | /* Translate internal representation of relocation info to BFD target | |
14318 | format. */ | |
14319 | ||
14320 | arelent ** | |
17a2f251 | 14321 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14322 | { |
14323 | static arelent *retval[4]; | |
14324 | arelent *reloc; | |
14325 | bfd_reloc_code_real_type code; | |
14326 | ||
4b0cff4e TS |
14327 | memset (retval, 0, sizeof(retval)); |
14328 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14329 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14330 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14331 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14332 | ||
bad36eac DJ |
14333 | if (fixp->fx_pcrel) |
14334 | { | |
9c2799c2 | 14335 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14336 | |
14337 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14338 | Relocations want only the symbol offset. */ | |
14339 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14340 | if (!IS_ELF) |
bad36eac DJ |
14341 | { |
14342 | /* A gruesome hack which is a result of the gruesome gas | |
14343 | reloc handling. What's worse, for COFF (as opposed to | |
14344 | ECOFF), we might need yet another copy of reloc->address. | |
14345 | See bfd_install_relocation. */ | |
14346 | reloc->addend += reloc->address; | |
14347 | } | |
14348 | } | |
14349 | else | |
14350 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14351 | |
438c16b8 TS |
14352 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14353 | entry to be used in the relocation's section offset. */ | |
14354 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14355 | { |
14356 | reloc->address = reloc->addend; | |
14357 | reloc->addend = 0; | |
14358 | } | |
14359 | ||
252b5132 | 14360 | code = fixp->fx_r_type; |
252b5132 | 14361 | |
bad36eac | 14362 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14363 | if (reloc->howto == NULL) |
14364 | { | |
14365 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14366 | _("Can not represent %s relocation in this object file format"), | |
14367 | bfd_get_reloc_code_name (code)); | |
14368 | retval[0] = NULL; | |
14369 | } | |
14370 | ||
14371 | return retval; | |
14372 | } | |
14373 | ||
14374 | /* Relax a machine dependent frag. This returns the amount by which | |
14375 | the current size of the frag should change. */ | |
14376 | ||
14377 | int | |
17a2f251 | 14378 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14379 | { |
4a6a3df4 AO |
14380 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14381 | { | |
14382 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14383 | |
14384 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14385 | |
14386 | return fragp->fr_var - old_var; | |
14387 | } | |
14388 | ||
252b5132 RH |
14389 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14390 | return 0; | |
14391 | ||
c4e7957c | 14392 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14393 | { |
14394 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14395 | return 0; | |
14396 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14397 | return 2; | |
14398 | } | |
14399 | else | |
14400 | { | |
14401 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14402 | return 0; | |
14403 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14404 | return -2; | |
14405 | } | |
14406 | ||
14407 | return 0; | |
14408 | } | |
14409 | ||
14410 | /* Convert a machine dependent frag. */ | |
14411 | ||
14412 | void | |
17a2f251 | 14413 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14414 | { |
4a6a3df4 AO |
14415 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14416 | { | |
14417 | bfd_byte *buf; | |
14418 | unsigned long insn; | |
14419 | expressionS exp; | |
14420 | fixS *fixp; | |
b34976b6 | 14421 | |
4a6a3df4 AO |
14422 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14423 | ||
14424 | if (target_big_endian) | |
14425 | insn = bfd_getb32 (buf); | |
14426 | else | |
14427 | insn = bfd_getl32 (buf); | |
b34976b6 | 14428 | |
4a6a3df4 AO |
14429 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14430 | { | |
14431 | /* We generate a fixup instead of applying it right now | |
14432 | because, if there are linker relaxations, we're going to | |
14433 | need the relocations. */ | |
14434 | exp.X_op = O_symbol; | |
14435 | exp.X_add_symbol = fragp->fr_symbol; | |
14436 | exp.X_add_number = fragp->fr_offset; | |
14437 | ||
14438 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14439 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14440 | fixp->fx_file = fragp->fr_file; |
14441 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14442 | |
2132e3a3 | 14443 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14444 | buf += 4; |
14445 | } | |
14446 | else | |
14447 | { | |
14448 | int i; | |
14449 | ||
14450 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 14451 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
14452 | |
14453 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14454 | goto uncond; | |
14455 | ||
14456 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14457 | { | |
14458 | /* Reverse the branch. */ | |
14459 | switch ((insn >> 28) & 0xf) | |
14460 | { | |
14461 | case 4: | |
14462 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14463 | have the condition reversed by tweaking a single | |
14464 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14465 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14466 | insn ^= 0x00010000; |
14467 | break; | |
14468 | ||
14469 | case 0: | |
14470 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14471 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14472 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14473 | insn ^= 0x00010000; |
14474 | break; | |
b34976b6 | 14475 | |
4a6a3df4 AO |
14476 | case 1: |
14477 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14478 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14479 | insn ^= 0x04000000; |
14480 | break; | |
14481 | ||
14482 | default: | |
14483 | abort (); | |
14484 | } | |
14485 | } | |
14486 | ||
14487 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14488 | { | |
14489 | /* Clear the and-link bit. */ | |
9c2799c2 | 14490 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14491 | |
54f4ddb3 TS |
14492 | /* bltzal 0x04100000 bgezal 0x04110000 |
14493 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14494 | insn &= ~0x00100000; |
14495 | } | |
14496 | ||
14497 | /* Branch over the branch (if the branch was likely) or the | |
14498 | full jump (not likely case). Compute the offset from the | |
14499 | current instruction to branch to. */ | |
14500 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14501 | i = 16; | |
14502 | else | |
14503 | { | |
14504 | /* How many bytes in instructions we've already emitted? */ | |
14505 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14506 | /* How many bytes in instructions from here to the end? */ | |
14507 | i = fragp->fr_var - i; | |
14508 | } | |
14509 | /* Convert to instruction count. */ | |
14510 | i >>= 2; | |
14511 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14512 | i--; |
4a6a3df4 AO |
14513 | insn |= i; |
14514 | /* Branch over the jump. */ | |
2132e3a3 | 14515 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14516 | buf += 4; |
14517 | ||
54f4ddb3 | 14518 | /* nop */ |
2132e3a3 | 14519 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14520 | buf += 4; |
14521 | ||
14522 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14523 | { | |
14524 | /* beql $0, $0, 2f */ | |
14525 | insn = 0x50000000; | |
14526 | /* Compute the PC offset from the current instruction to | |
14527 | the end of the variable frag. */ | |
14528 | /* How many bytes in instructions we've already emitted? */ | |
14529 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14530 | /* How many bytes in instructions from here to the end? */ | |
14531 | i = fragp->fr_var - i; | |
14532 | /* Convert to instruction count. */ | |
14533 | i >>= 2; | |
14534 | /* Don't decrement i, because we want to branch over the | |
14535 | delay slot. */ | |
14536 | ||
14537 | insn |= i; | |
2132e3a3 | 14538 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14539 | buf += 4; |
14540 | ||
2132e3a3 | 14541 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14542 | buf += 4; |
14543 | } | |
14544 | ||
14545 | uncond: | |
14546 | if (mips_pic == NO_PIC) | |
14547 | { | |
14548 | /* j or jal. */ | |
14549 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14550 | ? 0x0c000000 : 0x08000000); | |
14551 | exp.X_op = O_symbol; | |
14552 | exp.X_add_symbol = fragp->fr_symbol; | |
14553 | exp.X_add_number = fragp->fr_offset; | |
14554 | ||
14555 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14556 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14557 | fixp->fx_file = fragp->fr_file; |
14558 | fixp->fx_line = fragp->fr_line; | |
14559 | ||
2132e3a3 | 14560 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14561 | buf += 4; |
14562 | } | |
14563 | else | |
14564 | { | |
66b3e8da MR |
14565 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
14566 | ||
4a6a3df4 | 14567 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
14568 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
14569 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
14570 | exp.X_op = O_symbol; |
14571 | exp.X_add_symbol = fragp->fr_symbol; | |
14572 | exp.X_add_number = fragp->fr_offset; | |
14573 | ||
14574 | if (fragp->fr_offset) | |
14575 | { | |
14576 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14577 | exp.X_add_number = 0; | |
14578 | } | |
14579 | ||
14580 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14581 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14582 | fixp->fx_file = fragp->fr_file; |
14583 | fixp->fx_line = fragp->fr_line; | |
14584 | ||
2132e3a3 | 14585 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14586 | buf += 4; |
b34976b6 | 14587 | |
4a6a3df4 AO |
14588 | if (mips_opts.isa == ISA_MIPS1) |
14589 | { | |
14590 | /* nop */ | |
2132e3a3 | 14591 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14592 | buf += 4; |
14593 | } | |
14594 | ||
14595 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
14596 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
14597 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
14598 | |
14599 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14600 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14601 | fixp->fx_file = fragp->fr_file; |
14602 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14603 | |
2132e3a3 | 14604 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14605 | buf += 4; |
14606 | ||
14607 | /* j(al)r $at. */ | |
14608 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 14609 | insn = 0x0000f809; |
4a6a3df4 | 14610 | else |
66b3e8da MR |
14611 | insn = 0x00000008; |
14612 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 14613 | |
2132e3a3 | 14614 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14615 | buf += 4; |
14616 | } | |
14617 | } | |
14618 | ||
9c2799c2 | 14619 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14620 | + fragp->fr_fix + fragp->fr_var); |
14621 | ||
14622 | fragp->fr_fix += fragp->fr_var; | |
14623 | ||
14624 | return; | |
14625 | } | |
14626 | ||
252b5132 RH |
14627 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14628 | { | |
14629 | int type; | |
3994f87e | 14630 | const struct mips16_immed_operand *op; |
b34976b6 | 14631 | bfd_boolean small, ext; |
252b5132 RH |
14632 | offsetT val; |
14633 | bfd_byte *buf; | |
14634 | unsigned long insn; | |
b34976b6 | 14635 | bfd_boolean use_extend; |
252b5132 RH |
14636 | unsigned short extend; |
14637 | ||
14638 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14639 | op = mips16_immed_operands; | |
14640 | while (op->type != type) | |
14641 | ++op; | |
14642 | ||
14643 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14644 | { | |
b34976b6 AM |
14645 | small = FALSE; |
14646 | ext = TRUE; | |
252b5132 RH |
14647 | } |
14648 | else | |
14649 | { | |
b34976b6 AM |
14650 | small = TRUE; |
14651 | ext = FALSE; | |
252b5132 RH |
14652 | } |
14653 | ||
5f5f22c0 | 14654 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14655 | if (op->pcrel) |
14656 | { | |
14657 | addressT addr; | |
14658 | ||
14659 | addr = fragp->fr_address + fragp->fr_fix; | |
14660 | ||
14661 | /* The rules for the base address of a PC relative reloc are | |
14662 | complicated; see mips16_extended_frag. */ | |
14663 | if (type == 'p' || type == 'q') | |
14664 | { | |
14665 | addr += 2; | |
14666 | if (ext) | |
14667 | addr += 2; | |
14668 | /* Ignore the low bit in the target, since it will be | |
14669 | set for a text label. */ | |
14670 | if ((val & 1) != 0) | |
14671 | --val; | |
14672 | } | |
14673 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14674 | addr -= 4; | |
14675 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14676 | addr -= 2; | |
14677 | ||
14678 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14679 | val -= addr; | |
14680 | ||
14681 | /* Make sure the section winds up with the alignment we have | |
14682 | assumed. */ | |
14683 | if (op->shift > 0) | |
14684 | record_alignment (asec, op->shift); | |
14685 | } | |
14686 | ||
14687 | if (ext | |
14688 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14689 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14690 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14691 | _("extended instruction in delay slot")); | |
14692 | ||
14693 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14694 | ||
14695 | if (target_big_endian) | |
14696 | insn = bfd_getb16 (buf); | |
14697 | else | |
14698 | insn = bfd_getl16 (buf); | |
14699 | ||
14700 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14701 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14702 | small, ext, &insn, &use_extend, &extend); | |
14703 | ||
14704 | if (use_extend) | |
14705 | { | |
2132e3a3 | 14706 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14707 | fragp->fr_fix += 2; |
14708 | buf += 2; | |
14709 | } | |
14710 | ||
2132e3a3 | 14711 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14712 | fragp->fr_fix += 2; |
14713 | buf += 2; | |
14714 | } | |
14715 | else | |
14716 | { | |
4d7206a2 RS |
14717 | int first, second; |
14718 | fixS *fixp; | |
252b5132 | 14719 | |
4d7206a2 RS |
14720 | first = RELAX_FIRST (fragp->fr_subtype); |
14721 | second = RELAX_SECOND (fragp->fr_subtype); | |
14722 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14723 | |
584892a6 RS |
14724 | /* Possibly emit a warning if we've chosen the longer option. */ |
14725 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14726 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14727 | { | |
14728 | const char *msg = macro_warning (fragp->fr_subtype); | |
14729 | if (msg != 0) | |
520725ea | 14730 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14731 | } |
14732 | ||
4d7206a2 RS |
14733 | /* Go through all the fixups for the first sequence. Disable them |
14734 | (by marking them as done) if we're going to use the second | |
14735 | sequence instead. */ | |
14736 | while (fixp | |
14737 | && fixp->fx_frag == fragp | |
14738 | && fixp->fx_where < fragp->fr_fix - second) | |
14739 | { | |
14740 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14741 | fixp->fx_done = 1; | |
14742 | fixp = fixp->fx_next; | |
14743 | } | |
252b5132 | 14744 | |
4d7206a2 RS |
14745 | /* Go through the fixups for the second sequence. Disable them if |
14746 | we're going to use the first sequence, otherwise adjust their | |
14747 | addresses to account for the relaxation. */ | |
14748 | while (fixp && fixp->fx_frag == fragp) | |
14749 | { | |
14750 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14751 | fixp->fx_where -= first; | |
14752 | else | |
14753 | fixp->fx_done = 1; | |
14754 | fixp = fixp->fx_next; | |
14755 | } | |
14756 | ||
14757 | /* Now modify the frag contents. */ | |
14758 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14759 | { | |
14760 | char *start; | |
14761 | ||
14762 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14763 | memmove (start, start + first, second); | |
14764 | fragp->fr_fix -= first; | |
14765 | } | |
14766 | else | |
14767 | fragp->fr_fix -= second; | |
252b5132 RH |
14768 | } |
14769 | } | |
14770 | ||
14771 | #ifdef OBJ_ELF | |
14772 | ||
14773 | /* This function is called after the relocs have been generated. | |
14774 | We've been storing mips16 text labels as odd. Here we convert them | |
14775 | back to even for the convenience of the debugger. */ | |
14776 | ||
14777 | void | |
17a2f251 | 14778 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14779 | { |
14780 | asymbol **syms; | |
14781 | unsigned int count, i; | |
14782 | ||
f43abd2b | 14783 | if (!IS_ELF) |
252b5132 RH |
14784 | return; |
14785 | ||
14786 | syms = bfd_get_outsymbols (stdoutput); | |
14787 | count = bfd_get_symcount (stdoutput); | |
14788 | for (i = 0; i < count; i++, syms++) | |
14789 | { | |
30c09090 | 14790 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14791 | && ((*syms)->value & 1) != 0) |
14792 | { | |
14793 | (*syms)->value &= ~1; | |
14794 | /* If the symbol has an odd size, it was probably computed | |
14795 | incorrectly, so adjust that as well. */ | |
14796 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14797 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14798 | } | |
14799 | } | |
14800 | } | |
14801 | ||
14802 | #endif | |
14803 | ||
a1facbec MR |
14804 | /* This function is called whenever a label is defined, including fake |
14805 | labels instantiated off the dot special symbol. It is used when | |
14806 | handling branch delays; if a branch has a label, we assume we cannot | |
14807 | move it. This also bumps the value of the symbol by 1 in compressed | |
14808 | code. */ | |
252b5132 RH |
14809 | |
14810 | void | |
a1facbec | 14811 | mips_record_label (symbolS *sym) |
252b5132 | 14812 | { |
a8dbcb85 | 14813 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14814 | struct insn_label_list *l; |
14815 | ||
14816 | if (free_insn_labels == NULL) | |
14817 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14818 | else | |
14819 | { | |
14820 | l = free_insn_labels; | |
14821 | free_insn_labels = l->next; | |
14822 | } | |
14823 | ||
14824 | l->label = sym; | |
a8dbcb85 TS |
14825 | l->next = si->label_list; |
14826 | si->label_list = l; | |
a1facbec | 14827 | } |
07a53e5c | 14828 | |
a1facbec MR |
14829 | /* This function is called as tc_frob_label() whenever a label is defined |
14830 | and adds a DWARF-2 record we only want for true labels. */ | |
14831 | ||
14832 | void | |
14833 | mips_define_label (symbolS *sym) | |
14834 | { | |
14835 | mips_record_label (sym); | |
07a53e5c RH |
14836 | #ifdef OBJ_ELF |
14837 | dwarf2_emit_label (sym); | |
14838 | #endif | |
252b5132 RH |
14839 | } |
14840 | \f | |
14841 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14842 | ||
14843 | /* Some special processing for a MIPS ELF file. */ | |
14844 | ||
14845 | void | |
17a2f251 | 14846 | mips_elf_final_processing (void) |
252b5132 RH |
14847 | { |
14848 | /* Write out the register information. */ | |
316f5878 | 14849 | if (mips_abi != N64_ABI) |
252b5132 RH |
14850 | { |
14851 | Elf32_RegInfo s; | |
14852 | ||
14853 | s.ri_gprmask = mips_gprmask; | |
14854 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14855 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14856 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14857 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14858 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14859 | ||
14860 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14861 | ((Elf32_External_RegInfo *) | |
14862 | mips_regmask_frag)); | |
14863 | } | |
14864 | else | |
14865 | { | |
14866 | Elf64_Internal_RegInfo s; | |
14867 | ||
14868 | s.ri_gprmask = mips_gprmask; | |
14869 | s.ri_pad = 0; | |
14870 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14871 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14872 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14873 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14874 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14875 | ||
14876 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14877 | ((Elf64_External_RegInfo *) | |
14878 | mips_regmask_frag)); | |
14879 | } | |
14880 | ||
14881 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14882 | sort of BFD interface for this. */ | |
14883 | if (mips_any_noreorder) | |
14884 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14885 | if (mips_pic != NO_PIC) | |
143d77c5 | 14886 | { |
252b5132 | 14887 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14888 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14889 | } | |
14890 | if (mips_abicalls) | |
14891 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14892 | |
98d3f06f | 14893 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14894 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14895 | file_ase_dsp is true. */ | |
8b082fb1 | 14896 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14897 | /* We may need to define a new flag for MT ASE, and set this flag when |
14898 | file_ase_mt is true. */ | |
a4672219 TS |
14899 | if (file_ase_mips16) |
14900 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14901 | #if 0 /* XXX FIXME */ |
14902 | if (file_ase_mips3d) | |
14903 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14904 | #endif | |
deec1734 CD |
14905 | if (file_ase_mdmx) |
14906 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14907 | |
bdaaa2e1 | 14908 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14909 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14910 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14911 | else if (mips_abi == O64_ABI) |
252b5132 | 14912 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14913 | else if (mips_abi == EABI_ABI) |
252b5132 | 14914 | { |
316f5878 | 14915 | if (!file_mips_gp32) |
252b5132 RH |
14916 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14917 | else | |
14918 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14919 | } | |
316f5878 | 14920 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14921 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14922 | ||
c9914766 | 14923 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14924 | |
14925 | if (mips_32bitmode) | |
14926 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14927 | |
14928 | #if 0 /* XXX FIXME */ | |
14929 | /* 32 bit code with 64 bit FP registers. */ | |
14930 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14931 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14932 | #endif | |
252b5132 RH |
14933 | } |
14934 | ||
14935 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14936 | \f | |
beae10d5 | 14937 | typedef struct proc { |
9b2f1d35 EC |
14938 | symbolS *func_sym; |
14939 | symbolS *func_end_sym; | |
beae10d5 KH |
14940 | unsigned long reg_mask; |
14941 | unsigned long reg_offset; | |
14942 | unsigned long fpreg_mask; | |
14943 | unsigned long fpreg_offset; | |
14944 | unsigned long frame_offset; | |
14945 | unsigned long frame_reg; | |
14946 | unsigned long pc_reg; | |
14947 | } procS; | |
252b5132 RH |
14948 | |
14949 | static procS cur_proc; | |
14950 | static procS *cur_proc_ptr; | |
14951 | static int numprocs; | |
14952 | ||
742a56fe RS |
14953 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14954 | nop as "0". */ | |
14955 | ||
14956 | char | |
14957 | mips_nop_opcode (void) | |
14958 | { | |
14959 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14960 | } | |
14961 | ||
14962 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14963 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14964 | |
0a9ef439 | 14965 | void |
17a2f251 | 14966 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14967 | { |
742a56fe | 14968 | char *p; |
c67a084a NC |
14969 | int bytes, size, excess; |
14970 | valueT opcode; | |
742a56fe | 14971 | |
0a9ef439 RH |
14972 | if (fragp->fr_type != rs_align_code) |
14973 | return; | |
14974 | ||
742a56fe RS |
14975 | p = fragp->fr_literal + fragp->fr_fix; |
14976 | if (*p) | |
a19d8eb0 | 14977 | { |
c67a084a NC |
14978 | opcode = mips16_nop_insn.insn_opcode; |
14979 | size = 2; | |
14980 | } | |
14981 | else | |
14982 | { | |
14983 | opcode = nop_insn.insn_opcode; | |
14984 | size = 4; | |
14985 | } | |
a19d8eb0 | 14986 | |
c67a084a NC |
14987 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14988 | excess = bytes % size; | |
14989 | if (excess != 0) | |
14990 | { | |
14991 | /* If we're not inserting a whole number of instructions, | |
14992 | pad the end of the fixed part of the frag with zeros. */ | |
14993 | memset (p, 0, excess); | |
14994 | p += excess; | |
14995 | fragp->fr_fix += excess; | |
a19d8eb0 | 14996 | } |
c67a084a NC |
14997 | |
14998 | md_number_to_chars (p, opcode, size); | |
14999 | fragp->fr_var = size; | |
a19d8eb0 CP |
15000 | } |
15001 | ||
252b5132 | 15002 | static void |
17a2f251 | 15003 | md_obj_begin (void) |
252b5132 RH |
15004 | { |
15005 | } | |
15006 | ||
15007 | static void | |
17a2f251 | 15008 | md_obj_end (void) |
252b5132 | 15009 | { |
54f4ddb3 | 15010 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 15011 | if (cur_proc_ptr) |
9a41af64 | 15012 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
15013 | } |
15014 | ||
15015 | static long | |
17a2f251 | 15016 | get_number (void) |
252b5132 RH |
15017 | { |
15018 | int negative = 0; | |
15019 | long val = 0; | |
15020 | ||
15021 | if (*input_line_pointer == '-') | |
15022 | { | |
15023 | ++input_line_pointer; | |
15024 | negative = 1; | |
15025 | } | |
3882b010 | 15026 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 15027 | as_bad (_("expected simple number")); |
252b5132 RH |
15028 | if (input_line_pointer[0] == '0') |
15029 | { | |
15030 | if (input_line_pointer[1] == 'x') | |
15031 | { | |
15032 | input_line_pointer += 2; | |
3882b010 | 15033 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
15034 | { |
15035 | val <<= 4; | |
15036 | val |= hex_value (*input_line_pointer++); | |
15037 | } | |
15038 | return negative ? -val : val; | |
15039 | } | |
15040 | else | |
15041 | { | |
15042 | ++input_line_pointer; | |
3882b010 | 15043 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15044 | { |
15045 | val <<= 3; | |
15046 | val |= *input_line_pointer++ - '0'; | |
15047 | } | |
15048 | return negative ? -val : val; | |
15049 | } | |
15050 | } | |
3882b010 | 15051 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15052 | { |
15053 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15054 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15055 | as_warn (_("invalid number")); |
252b5132 RH |
15056 | return -1; |
15057 | } | |
3882b010 | 15058 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15059 | { |
15060 | val *= 10; | |
15061 | val += *input_line_pointer++ - '0'; | |
15062 | } | |
15063 | return negative ? -val : val; | |
15064 | } | |
15065 | ||
15066 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15067 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15068 | case .file implies DWARF-2. */ | |
15069 | ||
15070 | static void | |
17a2f251 | 15071 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15072 | { |
ecb4347a DJ |
15073 | static int first_file_directive = 0; |
15074 | ||
c5dd6aab DJ |
15075 | if (ECOFF_DEBUGGING) |
15076 | { | |
15077 | get_number (); | |
15078 | s_app_file (0); | |
15079 | } | |
15080 | else | |
ecb4347a DJ |
15081 | { |
15082 | char *filename; | |
15083 | ||
15084 | filename = dwarf2_directive_file (0); | |
15085 | ||
15086 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15087 | directive even for stabs output. Make sure that this | |
15088 | ".file" is handled. Note that you need a version of GCC | |
15089 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15090 | if (filename != NULL && ! first_file_directive) | |
15091 | { | |
15092 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15093 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15094 | } |
15095 | first_file_directive = 1; | |
15096 | } | |
c5dd6aab DJ |
15097 | } |
15098 | ||
15099 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15100 | |
15101 | static void | |
17a2f251 | 15102 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15103 | { |
c5dd6aab DJ |
15104 | if (!ECOFF_DEBUGGING) |
15105 | dwarf2_directive_loc (0); | |
252b5132 RH |
15106 | } |
15107 | ||
252b5132 RH |
15108 | /* The .end directive. */ |
15109 | ||
15110 | static void | |
17a2f251 | 15111 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15112 | { |
15113 | symbolS *p; | |
252b5132 | 15114 | |
7a621144 DJ |
15115 | /* Following functions need their own .frame and .cprestore directives. */ |
15116 | mips_frame_reg_valid = 0; | |
15117 | mips_cprestore_valid = 0; | |
15118 | ||
252b5132 RH |
15119 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15120 | { | |
15121 | p = get_symbol (); | |
15122 | demand_empty_rest_of_line (); | |
15123 | } | |
15124 | else | |
15125 | p = NULL; | |
15126 | ||
14949570 | 15127 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15128 | as_warn (_(".end not in text section")); |
15129 | ||
15130 | if (!cur_proc_ptr) | |
15131 | { | |
15132 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15133 | demand_empty_rest_of_line (); | |
15134 | return; | |
15135 | } | |
15136 | ||
15137 | if (p != NULL) | |
15138 | { | |
9c2799c2 | 15139 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15140 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15141 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15142 | |
15143 | if (debug_type == DEBUG_STABS) | |
15144 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15145 | S_GET_NAME (p)); | |
252b5132 RH |
15146 | } |
15147 | else | |
15148 | as_warn (_(".end directive missing or unknown symbol")); | |
15149 | ||
2132e3a3 | 15150 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15151 | /* Create an expression to calculate the size of the function. */ |
15152 | if (p && cur_proc_ptr) | |
15153 | { | |
15154 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15155 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15156 | ||
15157 | obj->size = exp; | |
15158 | exp->X_op = O_subtract; | |
15159 | exp->X_add_symbol = symbol_temp_new_now (); | |
15160 | exp->X_op_symbol = p; | |
15161 | exp->X_add_number = 0; | |
15162 | ||
15163 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15164 | } | |
15165 | ||
ecb4347a | 15166 | /* Generate a .pdr section. */ |
f43abd2b | 15167 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15168 | { |
15169 | segT saved_seg = now_seg; | |
15170 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15171 | expressionS exp; |
15172 | char *fragp; | |
252b5132 | 15173 | |
252b5132 | 15174 | #ifdef md_flush_pending_output |
ecb4347a | 15175 | md_flush_pending_output (); |
252b5132 RH |
15176 | #endif |
15177 | ||
9c2799c2 | 15178 | gas_assert (pdr_seg); |
ecb4347a | 15179 | subseg_set (pdr_seg, 0); |
252b5132 | 15180 | |
ecb4347a DJ |
15181 | /* Write the symbol. */ |
15182 | exp.X_op = O_symbol; | |
15183 | exp.X_add_symbol = p; | |
15184 | exp.X_add_number = 0; | |
15185 | emit_expr (&exp, 4); | |
252b5132 | 15186 | |
ecb4347a | 15187 | fragp = frag_more (7 * 4); |
252b5132 | 15188 | |
17a2f251 TS |
15189 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15190 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15191 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15192 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15193 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15194 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15195 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15196 | |
ecb4347a DJ |
15197 | subseg_set (saved_seg, saved_subseg); |
15198 | } | |
15199 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15200 | |
15201 | cur_proc_ptr = NULL; | |
15202 | } | |
15203 | ||
15204 | /* The .aent and .ent directives. */ | |
15205 | ||
15206 | static void | |
17a2f251 | 15207 | s_mips_ent (int aent) |
252b5132 | 15208 | { |
252b5132 | 15209 | symbolS *symbolP; |
252b5132 RH |
15210 | |
15211 | symbolP = get_symbol (); | |
15212 | if (*input_line_pointer == ',') | |
f9419b05 | 15213 | ++input_line_pointer; |
252b5132 | 15214 | SKIP_WHITESPACE (); |
3882b010 | 15215 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15216 | || *input_line_pointer == '-') |
874e8986 | 15217 | get_number (); |
252b5132 | 15218 | |
14949570 | 15219 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15220 | as_warn (_(".ent or .aent not in text section.")); |
15221 | ||
15222 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15223 | as_warn (_("missing .end")); |
252b5132 RH |
15224 | |
15225 | if (!aent) | |
15226 | { | |
7a621144 DJ |
15227 | /* This function needs its own .frame and .cprestore directives. */ |
15228 | mips_frame_reg_valid = 0; | |
15229 | mips_cprestore_valid = 0; | |
15230 | ||
252b5132 RH |
15231 | cur_proc_ptr = &cur_proc; |
15232 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15233 | ||
9b2f1d35 | 15234 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15235 | |
f9419b05 | 15236 | ++numprocs; |
ecb4347a DJ |
15237 | |
15238 | if (debug_type == DEBUG_STABS) | |
15239 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15240 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15241 | } |
15242 | ||
7c0fc524 MR |
15243 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15244 | ||
252b5132 RH |
15245 | demand_empty_rest_of_line (); |
15246 | } | |
15247 | ||
15248 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15249 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15250 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15251 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15252 | symbol table (in the mdebug section). */ |
15253 | ||
15254 | static void | |
17a2f251 | 15255 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15256 | { |
ecb4347a | 15257 | #ifdef OBJ_ELF |
f43abd2b | 15258 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15259 | { |
15260 | long val; | |
252b5132 | 15261 | |
ecb4347a DJ |
15262 | if (cur_proc_ptr == (procS *) NULL) |
15263 | { | |
15264 | as_warn (_(".frame outside of .ent")); | |
15265 | demand_empty_rest_of_line (); | |
15266 | return; | |
15267 | } | |
252b5132 | 15268 | |
ecb4347a DJ |
15269 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15270 | ||
15271 | SKIP_WHITESPACE (); | |
15272 | if (*input_line_pointer++ != ',' | |
15273 | || get_absolute_expression_and_terminator (&val) != ',') | |
15274 | { | |
15275 | as_warn (_("Bad .frame directive")); | |
15276 | --input_line_pointer; | |
15277 | demand_empty_rest_of_line (); | |
15278 | return; | |
15279 | } | |
252b5132 | 15280 | |
ecb4347a DJ |
15281 | cur_proc_ptr->frame_offset = val; |
15282 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15283 | |
252b5132 | 15284 | demand_empty_rest_of_line (); |
252b5132 | 15285 | } |
ecb4347a DJ |
15286 | else |
15287 | #endif /* OBJ_ELF */ | |
15288 | s_ignore (ignore); | |
252b5132 RH |
15289 | } |
15290 | ||
bdaaa2e1 KH |
15291 | /* The .fmask and .mask directives. If the mdebug section is present |
15292 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15293 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15294 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15295 | make reference to the ecoff symbol table (in the mdebug section). */ |
15296 | ||
15297 | static void | |
17a2f251 | 15298 | s_mips_mask (int reg_type) |
252b5132 | 15299 | { |
ecb4347a | 15300 | #ifdef OBJ_ELF |
f43abd2b | 15301 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15302 | { |
ecb4347a | 15303 | long mask, off; |
252b5132 | 15304 | |
ecb4347a DJ |
15305 | if (cur_proc_ptr == (procS *) NULL) |
15306 | { | |
15307 | as_warn (_(".mask/.fmask outside of .ent")); | |
15308 | demand_empty_rest_of_line (); | |
15309 | return; | |
15310 | } | |
252b5132 | 15311 | |
ecb4347a DJ |
15312 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15313 | { | |
15314 | as_warn (_("Bad .mask/.fmask directive")); | |
15315 | --input_line_pointer; | |
15316 | demand_empty_rest_of_line (); | |
15317 | return; | |
15318 | } | |
252b5132 | 15319 | |
ecb4347a DJ |
15320 | off = get_absolute_expression (); |
15321 | ||
15322 | if (reg_type == 'F') | |
15323 | { | |
15324 | cur_proc_ptr->fpreg_mask = mask; | |
15325 | cur_proc_ptr->fpreg_offset = off; | |
15326 | } | |
15327 | else | |
15328 | { | |
15329 | cur_proc_ptr->reg_mask = mask; | |
15330 | cur_proc_ptr->reg_offset = off; | |
15331 | } | |
15332 | ||
15333 | demand_empty_rest_of_line (); | |
252b5132 RH |
15334 | } |
15335 | else | |
ecb4347a DJ |
15336 | #endif /* OBJ_ELF */ |
15337 | s_ignore (reg_type); | |
252b5132 RH |
15338 | } |
15339 | ||
316f5878 RS |
15340 | /* A table describing all the processors gas knows about. Names are |
15341 | matched in the order listed. | |
e7af610e | 15342 | |
316f5878 RS |
15343 | To ease comparison, please keep this table in the same order as |
15344 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15345 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15346 | { | |
316f5878 | 15347 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15348 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15349 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15350 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15351 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15352 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15353 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15354 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15355 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15356 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15357 | |
15358 | /* MIPS I */ | |
ad3fea08 TS |
15359 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15360 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15361 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15362 | |
15363 | /* MIPS II */ | |
ad3fea08 | 15364 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15365 | |
15366 | /* MIPS III */ | |
ad3fea08 TS |
15367 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15368 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15369 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15370 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15371 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15372 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15373 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15374 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15375 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15376 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15377 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15378 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15379 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15380 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15381 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15382 | |
15383 | /* MIPS IV */ | |
ad3fea08 TS |
15384 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15385 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15386 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15387 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15388 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15389 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15390 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15391 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15392 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15393 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15394 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15395 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15396 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15397 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15398 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15399 | |
15400 | /* MIPS 32 */ | |
ad3fea08 TS |
15401 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15402 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15403 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15404 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15405 | ||
15406 | /* MIPS 32 Release 2 */ | |
15407 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15408 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15409 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15410 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15411 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15412 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15413 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15414 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15415 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15416 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15417 | /* Deprecated forms of the above. */ | |
15418 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15419 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15420 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15421 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15422 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15423 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15424 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15425 | /* Deprecated forms of the above. */ | |
15426 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15427 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15428 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15429 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15430 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15431 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15432 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15433 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15434 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15435 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15436 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15437 | /* Deprecated forms of the above. */ | |
15438 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15439 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15440 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15441 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15442 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15443 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15444 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15445 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15446 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15447 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15448 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15449 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15450 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15451 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15452 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15453 | /* Deprecated forms of the above. */ | |
15454 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15455 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15456 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15457 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15458 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15459 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15460 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15461 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15462 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15463 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15464 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15465 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15466 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15467 | |
316f5878 | 15468 | /* MIPS 64 */ |
ad3fea08 TS |
15469 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15470 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15471 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15472 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15473 | |
c7a23324 | 15474 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15475 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15476 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15477 | /* Broadcom SB-1A CPU core */ |
15478 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15479 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15480 | |
15481 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15482 | |
ed163775 MR |
15483 | /* MIPS 64 Release 2 */ |
15484 | ||
967344c6 AN |
15485 | /* Cavium Networks Octeon CPU core */ |
15486 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15487 | ||
52b6b6b9 JM |
15488 | /* RMI Xlr */ |
15489 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15490 | ||
316f5878 RS |
15491 | /* End marker */ |
15492 | { NULL, 0, 0, 0 } | |
15493 | }; | |
e7af610e | 15494 | |
84ea6cf2 | 15495 | |
316f5878 RS |
15496 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15497 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15498 | |
316f5878 | 15499 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15500 | |
b34976b6 | 15501 | static bfd_boolean |
17a2f251 | 15502 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15503 | { |
15504 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15505 | given++, canonical++; | |
15506 | ||
15507 | return ((*given == 0 && *canonical == 0) | |
15508 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15509 | } | |
15510 | ||
15511 | ||
15512 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15513 | CPU name. We've traditionally allowed a lot of variation here. | |
15514 | ||
15515 | Note: this function is shared between GCC and GAS. */ | |
15516 | ||
b34976b6 | 15517 | static bfd_boolean |
17a2f251 | 15518 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15519 | { |
15520 | /* First see if the name matches exactly, or with a final "000" | |
15521 | turned into "k". */ | |
15522 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15523 | return TRUE; |
316f5878 RS |
15524 | |
15525 | /* If not, try comparing based on numerical designation alone. | |
15526 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15527 | if (TOLOWER (*given) == 'r') | |
15528 | given++; | |
15529 | if (!ISDIGIT (*given)) | |
b34976b6 | 15530 | return FALSE; |
316f5878 RS |
15531 | |
15532 | /* Skip over some well-known prefixes in the canonical name, | |
15533 | hoping to find a number there too. */ | |
15534 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15535 | canonical += 2; | |
15536 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15537 | canonical += 2; | |
15538 | else if (TOLOWER (canonical[0]) == 'r') | |
15539 | canonical += 1; | |
15540 | ||
15541 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15542 | } | |
15543 | ||
15544 | ||
15545 | /* Parse an option that takes the name of a processor as its argument. | |
15546 | OPTION is the name of the option and CPU_STRING is the argument. | |
15547 | Return the corresponding processor enumeration if the CPU_STRING is | |
15548 | recognized, otherwise report an error and return null. | |
15549 | ||
15550 | A similar function exists in GCC. */ | |
e7af610e NC |
15551 | |
15552 | static const struct mips_cpu_info * | |
17a2f251 | 15553 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15554 | { |
316f5878 | 15555 | const struct mips_cpu_info *p; |
e7af610e | 15556 | |
316f5878 RS |
15557 | /* 'from-abi' selects the most compatible architecture for the given |
15558 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15559 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15560 | version. Look first at the -mgp options, if given, otherwise base | |
15561 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15562 | |
316f5878 RS |
15563 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15564 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15565 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15566 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15567 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15568 | { | |
15569 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15570 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15571 | ||
15572 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15573 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15574 | ||
15575 | if (file_mips_gp32 >= 0) | |
15576 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15577 | ||
15578 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15579 | ? ISA_MIPS3 | |
15580 | : ISA_MIPS1); | |
15581 | } | |
15582 | ||
15583 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15584 | if (strcasecmp (cpu_string, "default") == 0) | |
15585 | return 0; | |
15586 | ||
15587 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15588 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15589 | return p; | |
15590 | ||
20203fb9 | 15591 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15592 | return 0; |
e7af610e NC |
15593 | } |
15594 | ||
316f5878 RS |
15595 | /* Return the canonical processor information for ISA (a member of the |
15596 | ISA_MIPS* enumeration). */ | |
15597 | ||
e7af610e | 15598 | static const struct mips_cpu_info * |
17a2f251 | 15599 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15600 | { |
15601 | int i; | |
15602 | ||
15603 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15604 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15605 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15606 | return (&mips_cpu_info_table[i]); |
15607 | ||
e972090a | 15608 | return NULL; |
e7af610e | 15609 | } |
fef14a42 TS |
15610 | |
15611 | static const struct mips_cpu_info * | |
17a2f251 | 15612 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15613 | { |
15614 | int i; | |
15615 | ||
15616 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15617 | if (arch == mips_cpu_info_table[i].cpu) | |
15618 | return (&mips_cpu_info_table[i]); | |
15619 | ||
15620 | return NULL; | |
15621 | } | |
316f5878 RS |
15622 | \f |
15623 | static void | |
17a2f251 | 15624 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15625 | { |
15626 | if (*first_p) | |
15627 | { | |
15628 | fprintf (stream, "%24s", ""); | |
15629 | *col_p = 24; | |
15630 | } | |
15631 | else | |
15632 | { | |
15633 | fprintf (stream, ", "); | |
15634 | *col_p += 2; | |
15635 | } | |
e7af610e | 15636 | |
316f5878 RS |
15637 | if (*col_p + strlen (string) > 72) |
15638 | { | |
15639 | fprintf (stream, "\n%24s", ""); | |
15640 | *col_p = 24; | |
15641 | } | |
15642 | ||
15643 | fprintf (stream, "%s", string); | |
15644 | *col_p += strlen (string); | |
15645 | ||
15646 | *first_p = 0; | |
15647 | } | |
15648 | ||
15649 | void | |
17a2f251 | 15650 | md_show_usage (FILE *stream) |
e7af610e | 15651 | { |
316f5878 RS |
15652 | int column, first; |
15653 | size_t i; | |
15654 | ||
15655 | fprintf (stream, _("\ | |
15656 | MIPS options:\n\ | |
316f5878 RS |
15657 | -EB generate big endian output\n\ |
15658 | -EL generate little endian output\n\ | |
15659 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15660 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15661 | implicitly with the gp register [default 8]\n")); | |
15662 | fprintf (stream, _("\ | |
15663 | -mips1 generate MIPS ISA I instructions\n\ | |
15664 | -mips2 generate MIPS ISA II instructions\n\ | |
15665 | -mips3 generate MIPS ISA III instructions\n\ | |
15666 | -mips4 generate MIPS ISA IV instructions\n\ | |
15667 | -mips5 generate MIPS ISA V instructions\n\ | |
15668 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15669 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15670 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15671 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15672 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15673 | ||
15674 | first = 1; | |
e7af610e NC |
15675 | |
15676 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15677 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15678 | show (stream, "from-abi", &column, &first); | |
15679 | fputc ('\n', stream); | |
e7af610e | 15680 | |
316f5878 RS |
15681 | fprintf (stream, _("\ |
15682 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15683 | -no-mCPU don't generate code specific to CPU.\n\ | |
15684 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15685 | ||
15686 | first = 1; | |
15687 | ||
15688 | show (stream, "3900", &column, &first); | |
15689 | show (stream, "4010", &column, &first); | |
15690 | show (stream, "4100", &column, &first); | |
15691 | show (stream, "4650", &column, &first); | |
15692 | fputc ('\n', stream); | |
15693 | ||
15694 | fprintf (stream, _("\ | |
15695 | -mips16 generate mips16 instructions\n\ | |
15696 | -no-mips16 do not generate mips16 instructions\n")); | |
15697 | fprintf (stream, _("\ | |
e16bfa71 TS |
15698 | -msmartmips generate smartmips instructions\n\ |
15699 | -mno-smartmips do not generate smartmips instructions\n")); | |
15700 | fprintf (stream, _("\ | |
74cd071d CF |
15701 | -mdsp generate DSP instructions\n\ |
15702 | -mno-dsp do not generate DSP instructions\n")); | |
15703 | fprintf (stream, _("\ | |
8b082fb1 TS |
15704 | -mdspr2 generate DSP R2 instructions\n\ |
15705 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15706 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15707 | -mmt generate MT instructions\n\ |
15708 | -mno-mt do not generate MT instructions\n")); | |
15709 | fprintf (stream, _("\ | |
c67a084a NC |
15710 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15711 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15712 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15713 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15714 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15715 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15716 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15717 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15718 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15719 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15720 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15721 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15722 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15723 | fprintf (stream, _("\ |
15724 | -mhard-float allow floating-point instructions\n\ | |
15725 | -msoft-float do not allow floating-point instructions\n\ | |
15726 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15727 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15728 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15729 | )); | |
316f5878 RS |
15730 | #ifdef OBJ_ELF |
15731 | fprintf (stream, _("\ | |
15732 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15733 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15734 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15735 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15736 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15737 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15738 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15739 | position dependent (non shared) code\n\ |
316f5878 RS |
15740 | -mabi=ABI create ABI conformant object file for:\n")); |
15741 | ||
15742 | first = 1; | |
15743 | ||
15744 | show (stream, "32", &column, &first); | |
15745 | show (stream, "o64", &column, &first); | |
15746 | show (stream, "n32", &column, &first); | |
15747 | show (stream, "64", &column, &first); | |
15748 | show (stream, "eabi", &column, &first); | |
15749 | ||
15750 | fputc ('\n', stream); | |
15751 | ||
15752 | fprintf (stream, _("\ | |
15753 | -32 create o32 ABI object file (default)\n\ | |
15754 | -n32 create n32 ABI object file\n\ | |
15755 | -64 create 64 ABI object file\n")); | |
15756 | #endif | |
e7af610e | 15757 | } |
14e777e0 | 15758 | |
1575952e | 15759 | #ifdef TE_IRIX |
14e777e0 | 15760 | enum dwarf2_format |
413a266c | 15761 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15762 | { |
369943fe | 15763 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15764 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15765 | else |
15766 | return dwarf2_format_32bit; | |
15767 | } | |
1575952e | 15768 | #endif |
73369e65 EC |
15769 | |
15770 | int | |
15771 | mips_dwarf2_addr_size (void) | |
15772 | { | |
6b6b3450 | 15773 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15774 | return 8; |
73369e65 EC |
15775 | else |
15776 | return 4; | |
15777 | } | |
5862107c EC |
15778 | |
15779 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15780 | void | |
15781 | mips_cfi_frame_initial_instructions (void) | |
15782 | { | |
15783 | cfi_add_CFA_def_cfa_register (SP); | |
15784 | } | |
15785 | ||
707bfff6 TS |
15786 | int |
15787 | tc_mips_regname_to_dw2regnum (char *regname) | |
15788 | { | |
15789 | unsigned int regnum = -1; | |
15790 | unsigned int reg; | |
15791 | ||
15792 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15793 | regnum = reg; | |
15794 | ||
15795 | return regnum; | |
15796 | } |