Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
a325df1d TS |
122 | /* The ABI to use. */ |
123 | enum mips_abi_level | |
124 | { | |
125 | NO_ABI = 0, | |
126 | O32_ABI, | |
127 | O64_ABI, | |
128 | N32_ABI, | |
129 | N64_ABI, | |
130 | EABI_ABI | |
131 | }; | |
132 | ||
133 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 134 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 135 | |
143d77c5 EC |
136 | /* Whether or not we have code that can call pic code. */ |
137 | int mips_abicalls = FALSE; | |
138 | ||
252b5132 RH |
139 | /* This is the set of options which may be modified by the .set |
140 | pseudo-op. We use a struct so that .set push and .set pop are more | |
141 | reliable. */ | |
142 | ||
e972090a NC |
143 | struct mips_set_options |
144 | { | |
252b5132 RH |
145 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
146 | if it has not been initialized. Changed by `.set mipsN', and the | |
147 | -mipsN command line option, and the default CPU. */ | |
148 | int isa; | |
1f25f5d3 CD |
149 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
150 | if they have not been initialized. Changed by `.set <asename>', by | |
151 | command line options, and based on the default architecture. */ | |
152 | int ase_mips3d; | |
deec1734 | 153 | int ase_mdmx; |
252b5132 RH |
154 | /* Whether we are assembling for the mips16 processor. 0 if we are |
155 | not, 1 if we are, and -1 if the value has not been initialized. | |
156 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
157 | -nomips16 command line options, and the default CPU. */ | |
158 | int mips16; | |
159 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
160 | reorder' and `.set noreorder'. */ | |
161 | int noreorder; | |
162 | /* Non-zero if we should not permit the $at ($1) register to be used | |
163 | in instructions. Changed by `.set at' and `.set noat'. */ | |
164 | int noat; | |
165 | /* Non-zero if we should warn when a macro instruction expands into | |
166 | more than one machine instruction. Changed by `.set nomacro' and | |
167 | `.set macro'. */ | |
168 | int warn_about_macros; | |
169 | /* Non-zero if we should not move instructions. Changed by `.set | |
170 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
171 | int nomove; | |
172 | /* Non-zero if we should not optimize branches by moving the target | |
173 | of the branch into the delay slot. Actually, we don't perform | |
174 | this optimization anyhow. Changed by `.set bopt' and `.set | |
175 | nobopt'. */ | |
176 | int nobopt; | |
177 | /* Non-zero if we should not autoextend mips16 instructions. | |
178 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
179 | int noautoextend; | |
a325df1d TS |
180 | /* Restrict general purpose registers and floating point registers |
181 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
182 | is passed but can changed if the assembler code uses .set mipsN. */ | |
183 | int gp32; | |
184 | int fp32; | |
fef14a42 TS |
185 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
186 | command line option, and the default CPU. */ | |
187 | int arch; | |
252b5132 RH |
188 | }; |
189 | ||
a325df1d | 190 | /* True if -mgp32 was passed. */ |
a8e8e863 | 191 | static int file_mips_gp32 = -1; |
a325df1d TS |
192 | |
193 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 194 | static int file_mips_fp32 = -1; |
a325df1d | 195 | |
252b5132 | 196 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 197 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 198 | -1 to indicate that they have not been initialized. */ |
252b5132 | 199 | |
e972090a NC |
200 | static struct mips_set_options mips_opts = |
201 | { | |
fef14a42 | 202 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 203 | }; |
252b5132 RH |
204 | |
205 | /* These variables are filled in with the masks of registers used. | |
206 | The object format code reads them and puts them in the appropriate | |
207 | place. */ | |
208 | unsigned long mips_gprmask; | |
209 | unsigned long mips_cprmask[4]; | |
210 | ||
211 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 212 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 213 | |
a4672219 TS |
214 | /* True if -mips16 was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mips16; | |
217 | ||
1f25f5d3 CD |
218 | /* True if -mips3d was passed or implied by arguments passed on the |
219 | command line (e.g., by -march). */ | |
220 | static int file_ase_mips3d; | |
221 | ||
deec1734 CD |
222 | /* True if -mdmx was passed or implied by arguments passed on the |
223 | command line (e.g., by -march). */ | |
224 | static int file_ase_mdmx; | |
225 | ||
ec68c924 | 226 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 227 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 228 | static const char *mips_arch_string; |
ec68c924 EC |
229 | |
230 | /* The argument of the -mtune= flag. The architecture for which we | |
231 | are optimizing. */ | |
232 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 233 | static const char *mips_tune_string; |
ec68c924 | 234 | |
316f5878 | 235 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
236 | static int mips_32bitmode = 0; |
237 | ||
316f5878 RS |
238 | /* True if the given ABI requires 32-bit registers. */ |
239 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
240 | ||
241 | /* Likewise 64-bit registers. */ | |
242 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
243 | ((ABI) == N32_ABI \ | |
244 | || (ABI) == N64_ABI \ | |
245 | || (ABI) == O64_ABI) | |
246 | ||
bdaaa2e1 | 247 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 248 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
249 | (ISA) == ISA_MIPS3 \ |
250 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 251 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 252 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 253 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
254 | ) |
255 | ||
af7ee8bf CD |
256 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
257 | instructions. */ | |
258 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 259 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
260 | ) |
261 | ||
262 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
263 | instructions. */ | |
264 | #define ISA_HAS_ROR(ISA) ( \ | |
265 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 266 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
267 | ) |
268 | ||
e013f690 | 269 | #define HAVE_32BIT_GPRS \ |
316f5878 | 270 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 271 | |
e013f690 | 272 | #define HAVE_32BIT_FPRS \ |
316f5878 | 273 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
274 | |
275 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
276 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
277 | ||
316f5878 | 278 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 279 | |
316f5878 | 280 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 281 | |
3b91255e RS |
282 | /* True if relocations are stored in-place. */ |
283 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
284 | ||
3e722fb5 | 285 | /* We can only have 64bit addresses if the object file format supports it. */ |
afdbd6d0 CD |
286 | #define HAVE_32BIT_ADDRESSES \ |
287 | (HAVE_32BIT_GPRS \ | |
3e722fb5 CD |
288 | || (bfd_arch_bits_per_address (stdoutput) == 32 \ |
289 | || ! HAVE_64BIT_OBJECTS)) \ | |
e013f690 TS |
290 | |
291 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 292 | |
b7c7d6c1 TS |
293 | /* Addresses are loaded in different ways, depending on the address size |
294 | in use. The n32 ABI Documentation also mandates the use of additions | |
295 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 296 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 297 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
298 | |
299 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 300 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
301 | |
302 | #define ADDRESS_LOAD_INSN \ | |
303 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
304 | ||
305 | #define ADDRESS_STORE_INSN \ | |
306 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
307 | ||
a4672219 | 308 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
309 | #define CPU_HAS_MIPS16(cpu) \ |
310 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
311 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 312 | |
1f25f5d3 CD |
313 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
314 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
315 | ) | |
316 | ||
deec1734 | 317 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 318 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
319 | ) |
320 | ||
60b63b72 RS |
321 | /* True if CPU has a dror instruction. */ |
322 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
323 | ||
324 | /* True if CPU has a ror instruction. */ | |
325 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
326 | ||
c8978940 CD |
327 | /* True if mflo and mfhi can be immediately followed by instructions |
328 | which write to the HI and LO registers. | |
329 | ||
330 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
331 | (at least) two instructions between the reads of HI/LO and | |
332 | instructions which write them, and later ISAs do not. Contradicting | |
333 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
334 | the UM for the NEC Vr5000) document needing the instructions between | |
335 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
336 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
337 | earlier-ISA CPUs for which CPU documentation declares that the | |
338 | instructions are really interlocked. */ | |
339 | #define hilo_interlocks \ | |
340 | (mips_opts.isa == ISA_MIPS32 \ | |
341 | || mips_opts.isa == ISA_MIPS32R2 \ | |
342 | || mips_opts.isa == ISA_MIPS64 \ | |
343 | || mips_opts.isa == ISA_MIPS64R2 \ | |
344 | || mips_opts.arch == CPU_R4010 \ | |
345 | || mips_opts.arch == CPU_R10000 \ | |
346 | || mips_opts.arch == CPU_R12000 \ | |
347 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
348 | || mips_opts.arch == CPU_VR5500 \ |
349 | ) | |
252b5132 RH |
350 | |
351 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
352 | from the GPRs after they are loaded from memory, and thus does not |
353 | require nops to be inserted. This applies to instructions marked | |
354 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
355 | level I. */ | |
252b5132 | 356 | #define gpr_interlocks \ |
e7af610e | 357 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 358 | || mips_opts.arch == CPU_R3900) |
252b5132 | 359 | |
81912461 ILT |
360 | /* Whether the processor uses hardware interlocks to avoid delays |
361 | required by coprocessor instructions, and thus does not require | |
362 | nops to be inserted. This applies to instructions marked | |
363 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
364 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
365 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
366 | levels I, II, and III. */ | |
bdaaa2e1 | 367 | /* Itbl support may require additional care here. */ |
81912461 ILT |
368 | #define cop_interlocks \ |
369 | ((mips_opts.isa != ISA_MIPS1 \ | |
370 | && mips_opts.isa != ISA_MIPS2 \ | |
371 | && mips_opts.isa != ISA_MIPS3) \ | |
372 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
373 | ) |
374 | ||
375 | /* Whether the processor uses hardware interlocks to protect reads | |
376 | from coprocessor registers after they are loaded from memory, and | |
377 | thus does not require nops to be inserted. This applies to | |
378 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
379 | requires at MIPS ISA level I. */ | |
380 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 381 | |
6b76fefe CM |
382 | /* Is this a mfhi or mflo instruction? */ |
383 | #define MF_HILO_INSN(PINFO) \ | |
384 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
385 | ||
252b5132 RH |
386 | /* MIPS PIC level. */ |
387 | ||
a161fe53 | 388 | enum mips_pic_level mips_pic; |
252b5132 | 389 | |
c9914766 | 390 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 391 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 392 | static int mips_big_got = 0; |
252b5132 RH |
393 | |
394 | /* 1 if trap instructions should used for overflow rather than break | |
395 | instructions. */ | |
c9914766 | 396 | static int mips_trap = 0; |
252b5132 | 397 | |
119d663a | 398 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 399 | by assembling two single width halves into two single width floating |
119d663a NC |
400 | point registers which just happen to alias the double width destination |
401 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 402 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
403 | automatically at assemble time. */ |
404 | static int mips_disable_float_construction; | |
405 | ||
252b5132 RH |
406 | /* Non-zero if any .set noreorder directives were used. */ |
407 | ||
408 | static int mips_any_noreorder; | |
409 | ||
6b76fefe CM |
410 | /* Non-zero if nops should be inserted when the register referenced in |
411 | an mfhi/mflo instruction is read in the next two instructions. */ | |
412 | static int mips_7000_hilo_fix; | |
413 | ||
252b5132 | 414 | /* The size of the small data section. */ |
156c2f8b | 415 | static unsigned int g_switch_value = 8; |
252b5132 RH |
416 | /* Whether the -G option was used. */ |
417 | static int g_switch_seen = 0; | |
418 | ||
419 | #define N_RMASK 0xc4 | |
420 | #define N_VFP 0xd4 | |
421 | ||
422 | /* If we can determine in advance that GP optimization won't be | |
423 | possible, we can skip the relaxation stuff that tries to produce | |
424 | GP-relative references. This makes delay slot optimization work | |
425 | better. | |
426 | ||
427 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
428 | gcc output. It needs to guess right for gcc, otherwise gcc |
429 | will put what it thinks is a GP-relative instruction in a branch | |
430 | delay slot. | |
252b5132 RH |
431 | |
432 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
433 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 434 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
435 | |
436 | /* handle of the OPCODE hash table */ | |
437 | static struct hash_control *op_hash = NULL; | |
438 | ||
439 | /* The opcode hash table we use for the mips16. */ | |
440 | static struct hash_control *mips16_op_hash = NULL; | |
441 | ||
442 | /* This array holds the chars that always start a comment. If the | |
443 | pre-processor is disabled, these aren't very useful */ | |
444 | const char comment_chars[] = "#"; | |
445 | ||
446 | /* This array holds the chars that only start a comment at the beginning of | |
447 | a line. If the line seems to have the form '# 123 filename' | |
448 | .line and .file directives will appear in the pre-processed output */ | |
449 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
450 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 451 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
452 | /* Also note that C style comments are always supported. */ |
453 | const char line_comment_chars[] = "#"; | |
454 | ||
bdaaa2e1 | 455 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 456 | const char line_separator_chars[] = ";"; |
252b5132 RH |
457 | |
458 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
459 | const char EXP_CHARS[] = "eE"; | |
460 | ||
461 | /* Chars that mean this number is a floating point constant */ | |
462 | /* As in 0f12.456 */ | |
463 | /* or 0d1.2345e12 */ | |
464 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
465 | ||
466 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
467 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
468 | but nothing is ideal around here. | |
469 | */ | |
470 | ||
471 | static char *insn_error; | |
472 | ||
473 | static int auto_align = 1; | |
474 | ||
475 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
476 | offset in the stack frame from which to restore the $gp register. | |
477 | This is set by the .cprestore pseudo-op, and saved in this | |
478 | variable. */ | |
479 | static offsetT mips_cprestore_offset = -1; | |
480 | ||
67c1ffbe | 481 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 482 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 483 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
484 | static offsetT mips_cpreturn_offset = -1; |
485 | static int mips_cpreturn_register = -1; | |
486 | static int mips_gp_register = GP; | |
def2e0dd | 487 | static int mips_gprel_offset = 0; |
6478892d | 488 | |
7a621144 DJ |
489 | /* Whether mips_cprestore_offset has been set in the current function |
490 | (or whether it has already been warned about, if not). */ | |
491 | static int mips_cprestore_valid = 0; | |
492 | ||
252b5132 RH |
493 | /* This is the register which holds the stack frame, as set by the |
494 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
495 | static int mips_frame_reg = SP; | |
496 | ||
7a621144 DJ |
497 | /* Whether mips_frame_reg has been set in the current function |
498 | (or whether it has already been warned about, if not). */ | |
499 | static int mips_frame_reg_valid = 0; | |
500 | ||
252b5132 RH |
501 | /* To output NOP instructions correctly, we need to keep information |
502 | about the previous two instructions. */ | |
503 | ||
504 | /* Whether we are optimizing. The default value of 2 means to remove | |
505 | unneeded NOPs and swap branch instructions when possible. A value | |
506 | of 1 means to not swap branches. A value of 0 means to always | |
507 | insert NOPs. */ | |
508 | static int mips_optimize = 2; | |
509 | ||
510 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
511 | equivalent to seeing no -g option at all. */ | |
512 | static int mips_debug = 0; | |
513 | ||
514 | /* The previous instruction. */ | |
515 | static struct mips_cl_insn prev_insn; | |
516 | ||
517 | /* The instruction before prev_insn. */ | |
518 | static struct mips_cl_insn prev_prev_insn; | |
519 | ||
520 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
521 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 522 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
523 | |
524 | /* Non-zero if prev_insn is valid. */ | |
525 | static int prev_insn_valid; | |
526 | ||
527 | /* The frag for the previous instruction. */ | |
528 | static struct frag *prev_insn_frag; | |
529 | ||
530 | /* The offset into prev_insn_frag for the previous instruction. */ | |
531 | static long prev_insn_where; | |
532 | ||
533 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 534 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
535 | |
536 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 537 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
538 | |
539 | /* Non-zero if the previous instruction was in a delay slot. */ | |
540 | static int prev_insn_is_delay_slot; | |
541 | ||
542 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
543 | static int prev_insn_unreordered; | |
544 | ||
545 | /* Non-zero if the previous instruction uses an extend opcode (if | |
546 | mips16). */ | |
547 | static int prev_insn_extended; | |
548 | ||
549 | /* Non-zero if the previous previous instruction was in a .set | |
550 | noreorder. */ | |
551 | static int prev_prev_insn_unreordered; | |
552 | ||
553 | /* If this is set, it points to a frag holding nop instructions which | |
554 | were inserted before the start of a noreorder section. If those | |
555 | nops turn out to be unnecessary, the size of the frag can be | |
556 | decreased. */ | |
557 | static fragS *prev_nop_frag; | |
558 | ||
559 | /* The number of nop instructions we created in prev_nop_frag. */ | |
560 | static int prev_nop_frag_holds; | |
561 | ||
562 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 563 | prev_nop_frag. */ |
252b5132 RH |
564 | static int prev_nop_frag_required; |
565 | ||
566 | /* The number of instructions we've seen since prev_nop_frag. */ | |
567 | static int prev_nop_frag_since; | |
568 | ||
569 | /* For ECOFF and ELF, relocations against symbols are done in two | |
570 | parts, with a HI relocation and a LO relocation. Each relocation | |
571 | has only 16 bits of space to store an addend. This means that in | |
572 | order for the linker to handle carries correctly, it must be able | |
573 | to locate both the HI and the LO relocation. This means that the | |
574 | relocations must appear in order in the relocation table. | |
575 | ||
576 | In order to implement this, we keep track of each unmatched HI | |
577 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 578 | corresponding LO relocation. */ |
252b5132 | 579 | |
e972090a NC |
580 | struct mips_hi_fixup |
581 | { | |
252b5132 RH |
582 | /* Next HI fixup. */ |
583 | struct mips_hi_fixup *next; | |
584 | /* This fixup. */ | |
585 | fixS *fixp; | |
586 | /* The section this fixup is in. */ | |
587 | segT seg; | |
588 | }; | |
589 | ||
590 | /* The list of unmatched HI relocs. */ | |
591 | ||
592 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
593 | ||
64bdfcaf RS |
594 | /* The frag containing the last explicit relocation operator. |
595 | Null if explicit relocations have not been used. */ | |
596 | ||
597 | static fragS *prev_reloc_op_frag; | |
598 | ||
252b5132 RH |
599 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
600 | ||
601 | #define X ILLEGAL_REG | |
e972090a NC |
602 | static const int mips32_to_16_reg_map[] = |
603 | { | |
252b5132 RH |
604 | X, X, 2, 3, 4, 5, 6, 7, |
605 | X, X, X, X, X, X, X, X, | |
606 | 0, 1, X, X, X, X, X, X, | |
607 | X, X, X, X, X, X, X, X | |
608 | }; | |
609 | #undef X | |
610 | ||
611 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
612 | ||
e972090a NC |
613 | static const unsigned int mips16_to_32_reg_map[] = |
614 | { | |
252b5132 RH |
615 | 16, 17, 2, 3, 4, 5, 6, 7 |
616 | }; | |
60b63b72 | 617 | |
d766e8ec | 618 | static int mips_fix_vr4120; |
4a6a3df4 AO |
619 | |
620 | /* We don't relax branches by default, since this causes us to expand | |
621 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
622 | fail to compute the offset before expanding the macro to the most | |
623 | efficient expansion. */ | |
624 | ||
625 | static int mips_relax_branch; | |
252b5132 | 626 | \f |
4d7206a2 RS |
627 | /* The expansion of many macros depends on the type of symbol that |
628 | they refer to. For example, when generating position-dependent code, | |
629 | a macro that refers to a symbol may have two different expansions, | |
630 | one which uses GP-relative addresses and one which uses absolute | |
631 | addresses. When generating SVR4-style PIC, a macro may have | |
632 | different expansions for local and global symbols. | |
633 | ||
634 | We handle these situations by generating both sequences and putting | |
635 | them in variant frags. In position-dependent code, the first sequence | |
636 | will be the GP-relative one and the second sequence will be the | |
637 | absolute one. In SVR4 PIC, the first sequence will be for global | |
638 | symbols and the second will be for local symbols. | |
639 | ||
584892a6 RS |
640 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
641 | SECOND are the lengths of the two sequences in bytes. These fields | |
642 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
643 | the subtype has the following flags: | |
4d7206a2 | 644 | |
584892a6 RS |
645 | RELAX_USE_SECOND |
646 | Set if it has been decided that we should use the second | |
647 | sequence instead of the first. | |
648 | ||
649 | RELAX_SECOND_LONGER | |
650 | Set in the first variant frag if the macro's second implementation | |
651 | is longer than its first. This refers to the macro as a whole, | |
652 | not an individual relaxation. | |
653 | ||
654 | RELAX_NOMACRO | |
655 | Set in the first variant frag if the macro appeared in a .set nomacro | |
656 | block and if one alternative requires a warning but the other does not. | |
657 | ||
658 | RELAX_DELAY_SLOT | |
659 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
660 | delay slot. | |
4d7206a2 RS |
661 | |
662 | The frag's "opcode" points to the first fixup for relaxable code. | |
663 | ||
664 | Relaxable macros are generated using a sequence such as: | |
665 | ||
666 | relax_start (SYMBOL); | |
667 | ... generate first expansion ... | |
668 | relax_switch (); | |
669 | ... generate second expansion ... | |
670 | relax_end (); | |
671 | ||
672 | The code and fixups for the unwanted alternative are discarded | |
673 | by md_convert_frag. */ | |
584892a6 | 674 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 675 | |
584892a6 RS |
676 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
677 | #define RELAX_SECOND(X) ((X) & 0xff) | |
678 | #define RELAX_USE_SECOND 0x10000 | |
679 | #define RELAX_SECOND_LONGER 0x20000 | |
680 | #define RELAX_NOMACRO 0x40000 | |
681 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 682 | |
4a6a3df4 AO |
683 | /* Branch without likely bit. If label is out of range, we turn: |
684 | ||
685 | beq reg1, reg2, label | |
686 | delay slot | |
687 | ||
688 | into | |
689 | ||
690 | bne reg1, reg2, 0f | |
691 | nop | |
692 | j label | |
693 | 0: delay slot | |
694 | ||
695 | with the following opcode replacements: | |
696 | ||
697 | beq <-> bne | |
698 | blez <-> bgtz | |
699 | bltz <-> bgez | |
700 | bc1f <-> bc1t | |
701 | ||
702 | bltzal <-> bgezal (with jal label instead of j label) | |
703 | ||
704 | Even though keeping the delay slot instruction in the delay slot of | |
705 | the branch would be more efficient, it would be very tricky to do | |
706 | correctly, because we'd have to introduce a variable frag *after* | |
707 | the delay slot instruction, and expand that instead. Let's do it | |
708 | the easy way for now, even if the branch-not-taken case now costs | |
709 | one additional instruction. Out-of-range branches are not supposed | |
710 | to be common, anyway. | |
711 | ||
712 | Branch likely. If label is out of range, we turn: | |
713 | ||
714 | beql reg1, reg2, label | |
715 | delay slot (annulled if branch not taken) | |
716 | ||
717 | into | |
718 | ||
719 | beql reg1, reg2, 1f | |
720 | nop | |
721 | beql $0, $0, 2f | |
722 | nop | |
723 | 1: j[al] label | |
724 | delay slot (executed only if branch taken) | |
725 | 2: | |
726 | ||
727 | It would be possible to generate a shorter sequence by losing the | |
728 | likely bit, generating something like: | |
b34976b6 | 729 | |
4a6a3df4 AO |
730 | bne reg1, reg2, 0f |
731 | nop | |
732 | j[al] label | |
733 | delay slot (executed only if branch taken) | |
734 | 0: | |
735 | ||
736 | beql -> bne | |
737 | bnel -> beq | |
738 | blezl -> bgtz | |
739 | bgtzl -> blez | |
740 | bltzl -> bgez | |
741 | bgezl -> bltz | |
742 | bc1fl -> bc1t | |
743 | bc1tl -> bc1f | |
744 | ||
745 | bltzall -> bgezal (with jal label instead of j label) | |
746 | bgezall -> bltzal (ditto) | |
747 | ||
748 | ||
749 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 750 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
751 | ((relax_substateT) \ |
752 | (0xc0000000 \ | |
753 | | ((toofar) ? 1 : 0) \ | |
754 | | ((link) ? 2 : 0) \ | |
755 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 756 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 757 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
758 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
759 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
760 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 761 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 762 | |
252b5132 RH |
763 | /* For mips16 code, we use an entirely different form of relaxation. |
764 | mips16 supports two versions of most instructions which take | |
765 | immediate values: a small one which takes some small value, and a | |
766 | larger one which takes a 16 bit value. Since branches also follow | |
767 | this pattern, relaxing these values is required. | |
768 | ||
769 | We can assemble both mips16 and normal MIPS code in a single | |
770 | object. Therefore, we need to support this type of relaxation at | |
771 | the same time that we support the relaxation described above. We | |
772 | use the high bit of the subtype field to distinguish these cases. | |
773 | ||
774 | The information we store for this type of relaxation is the | |
775 | argument code found in the opcode file for this relocation, whether | |
776 | the user explicitly requested a small or extended form, and whether | |
777 | the relocation is in a jump or jal delay slot. That tells us the | |
778 | size of the value, and how it should be stored. We also store | |
779 | whether the fragment is considered to be extended or not. We also | |
780 | store whether this is known to be a branch to a different section, | |
781 | whether we have tried to relax this frag yet, and whether we have | |
782 | ever extended a PC relative fragment because of a shift count. */ | |
783 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
784 | (0x80000000 \ | |
785 | | ((type) & 0xff) \ | |
786 | | ((small) ? 0x100 : 0) \ | |
787 | | ((ext) ? 0x200 : 0) \ | |
788 | | ((dslot) ? 0x400 : 0) \ | |
789 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 790 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
791 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
792 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
793 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
794 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
795 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
796 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
797 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
798 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
799 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
800 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
801 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
802 | |
803 | /* Is the given value a sign-extended 32-bit value? */ | |
804 | #define IS_SEXT_32BIT_NUM(x) \ | |
805 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
806 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
807 | ||
808 | /* Is the given value a sign-extended 16-bit value? */ | |
809 | #define IS_SEXT_16BIT_NUM(x) \ | |
810 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
811 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
812 | ||
4d7206a2 RS |
813 | \f |
814 | /* Global variables used when generating relaxable macros. See the | |
815 | comment above RELAX_ENCODE for more details about how relaxation | |
816 | is used. */ | |
817 | static struct { | |
818 | /* 0 if we're not emitting a relaxable macro. | |
819 | 1 if we're emitting the first of the two relaxation alternatives. | |
820 | 2 if we're emitting the second alternative. */ | |
821 | int sequence; | |
822 | ||
823 | /* The first relaxable fixup in the current frag. (In other words, | |
824 | the first fixup that refers to relaxable code.) */ | |
825 | fixS *first_fixup; | |
826 | ||
827 | /* sizes[0] says how many bytes of the first alternative are stored in | |
828 | the current frag. Likewise sizes[1] for the second alternative. */ | |
829 | unsigned int sizes[2]; | |
830 | ||
831 | /* The symbol on which the choice of sequence depends. */ | |
832 | symbolS *symbol; | |
833 | } mips_relax; | |
252b5132 | 834 | \f |
584892a6 RS |
835 | /* Global variables used to decide whether a macro needs a warning. */ |
836 | static struct { | |
837 | /* True if the macro is in a branch delay slot. */ | |
838 | bfd_boolean delay_slot_p; | |
839 | ||
840 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
841 | in bytes and sizes[1] is the length of the second alternative. | |
842 | For non-relaxable macros, both elements give the length of the | |
843 | macro in bytes. */ | |
844 | unsigned int sizes[2]; | |
845 | ||
846 | /* The first variant frag for this macro. */ | |
847 | fragS *first_frag; | |
848 | } mips_macro_warning; | |
849 | \f | |
252b5132 RH |
850 | /* Prototypes for static functions. */ |
851 | ||
17a2f251 | 852 | #define internalError() \ |
252b5132 | 853 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
854 | |
855 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
856 | ||
b34976b6 | 857 | static void append_insn |
4d7206a2 | 858 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 859 | static void mips_no_prev_insn (int); |
b34976b6 | 860 | static void mips16_macro_build |
67c0d1eb RS |
861 | (expressionS *, const char *, const char *, va_list); |
862 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
863 | static void macro_start (void); |
864 | static void macro_end (void); | |
17a2f251 TS |
865 | static void macro (struct mips_cl_insn * ip); |
866 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 867 | #ifdef LOSING_COMPILER |
17a2f251 | 868 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 869 | #endif |
17a2f251 TS |
870 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
871 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 872 | static void mips16_immed |
17a2f251 TS |
873 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
874 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 875 | static size_t my_getSmallExpression |
17a2f251 TS |
876 | (expressionS *, bfd_reloc_code_real_type *, char *); |
877 | static void my_getExpression (expressionS *, char *); | |
878 | static void s_align (int); | |
879 | static void s_change_sec (int); | |
880 | static void s_change_section (int); | |
881 | static void s_cons (int); | |
882 | static void s_float_cons (int); | |
883 | static void s_mips_globl (int); | |
884 | static void s_option (int); | |
885 | static void s_mipsset (int); | |
886 | static void s_abicalls (int); | |
887 | static void s_cpload (int); | |
888 | static void s_cpsetup (int); | |
889 | static void s_cplocal (int); | |
890 | static void s_cprestore (int); | |
891 | static void s_cpreturn (int); | |
892 | static void s_gpvalue (int); | |
893 | static void s_gpword (int); | |
894 | static void s_gpdword (int); | |
895 | static void s_cpadd (int); | |
896 | static void s_insn (int); | |
897 | static void md_obj_begin (void); | |
898 | static void md_obj_end (void); | |
899 | static void s_mips_ent (int); | |
900 | static void s_mips_end (int); | |
901 | static void s_mips_frame (int); | |
902 | static void s_mips_mask (int reg_type); | |
903 | static void s_mips_stab (int); | |
904 | static void s_mips_weakext (int); | |
905 | static void s_mips_file (int); | |
906 | static void s_mips_loc (int); | |
907 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 908 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 909 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
910 | |
911 | /* Table and functions used to map between CPU/ISA names, and | |
912 | ISA levels, and CPU numbers. */ | |
913 | ||
e972090a NC |
914 | struct mips_cpu_info |
915 | { | |
e7af610e NC |
916 | const char *name; /* CPU or ISA name. */ |
917 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
918 | int isa; /* ISA level. */ | |
919 | int cpu; /* CPU number (default CPU if ISA). */ | |
920 | }; | |
921 | ||
17a2f251 TS |
922 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
923 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
924 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
925 | \f |
926 | /* Pseudo-op table. | |
927 | ||
928 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
929 | should be defined here, but are currently unsupported: .alias, | |
930 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
931 | ||
932 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
933 | specific to the type of debugging information being generated, and | |
934 | should be defined by the object format: .aent, .begin, .bend, | |
935 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
936 | .vreg. | |
937 | ||
938 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
939 | not MIPS CPU specific, but are also not specific to the object file | |
940 | format. This file is probably the best place to define them, but | |
941 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
942 | .struct. */ | |
943 | ||
e972090a NC |
944 | static const pseudo_typeS mips_pseudo_table[] = |
945 | { | |
beae10d5 | 946 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
947 | {"option", s_option, 0}, |
948 | {"set", s_mipsset, 0}, | |
949 | {"rdata", s_change_sec, 'r'}, | |
950 | {"sdata", s_change_sec, 's'}, | |
951 | {"livereg", s_ignore, 0}, | |
952 | {"abicalls", s_abicalls, 0}, | |
953 | {"cpload", s_cpload, 0}, | |
6478892d TS |
954 | {"cpsetup", s_cpsetup, 0}, |
955 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 956 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
957 | {"cpreturn", s_cpreturn, 0}, |
958 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 959 | {"gpword", s_gpword, 0}, |
10181a0d | 960 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
961 | {"cpadd", s_cpadd, 0}, |
962 | {"insn", s_insn, 0}, | |
963 | ||
beae10d5 | 964 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
965 | chips. */ |
966 | {"asciiz", stringer, 1}, | |
967 | {"bss", s_change_sec, 'b'}, | |
968 | {"err", s_err, 0}, | |
969 | {"half", s_cons, 1}, | |
970 | {"dword", s_cons, 3}, | |
971 | {"weakext", s_mips_weakext, 0}, | |
972 | ||
beae10d5 | 973 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
974 | here for one reason or another. */ |
975 | {"align", s_align, 0}, | |
976 | {"byte", s_cons, 0}, | |
977 | {"data", s_change_sec, 'd'}, | |
978 | {"double", s_float_cons, 'd'}, | |
979 | {"float", s_float_cons, 'f'}, | |
980 | {"globl", s_mips_globl, 0}, | |
981 | {"global", s_mips_globl, 0}, | |
982 | {"hword", s_cons, 1}, | |
983 | {"int", s_cons, 2}, | |
984 | {"long", s_cons, 2}, | |
985 | {"octa", s_cons, 4}, | |
986 | {"quad", s_cons, 3}, | |
cca86cc8 | 987 | {"section", s_change_section, 0}, |
252b5132 RH |
988 | {"short", s_cons, 1}, |
989 | {"single", s_float_cons, 'f'}, | |
990 | {"stabn", s_mips_stab, 'n'}, | |
991 | {"text", s_change_sec, 't'}, | |
992 | {"word", s_cons, 2}, | |
add56521 | 993 | |
add56521 | 994 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 995 | |
43841e91 | 996 | { NULL, NULL, 0 }, |
252b5132 RH |
997 | }; |
998 | ||
e972090a NC |
999 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1000 | { | |
beae10d5 KH |
1001 | /* These pseudo-ops should be defined by the object file format. |
1002 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1003 | {"aent", s_mips_ent, 1}, |
1004 | {"bgnb", s_ignore, 0}, | |
1005 | {"end", s_mips_end, 0}, | |
1006 | {"endb", s_ignore, 0}, | |
1007 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1008 | {"file", s_mips_file, 0}, |
252b5132 RH |
1009 | {"fmask", s_mips_mask, 'F'}, |
1010 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1011 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1012 | {"mask", s_mips_mask, 'R'}, |
1013 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1014 | { NULL, NULL, 0 }, |
252b5132 RH |
1015 | }; |
1016 | ||
17a2f251 | 1017 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1018 | |
1019 | void | |
17a2f251 | 1020 | mips_pop_insert (void) |
252b5132 RH |
1021 | { |
1022 | pop_insert (mips_pseudo_table); | |
1023 | if (! ECOFF_DEBUGGING) | |
1024 | pop_insert (mips_nonecoff_pseudo_table); | |
1025 | } | |
1026 | \f | |
1027 | /* Symbols labelling the current insn. */ | |
1028 | ||
e972090a NC |
1029 | struct insn_label_list |
1030 | { | |
252b5132 RH |
1031 | struct insn_label_list *next; |
1032 | symbolS *label; | |
1033 | }; | |
1034 | ||
1035 | static struct insn_label_list *insn_labels; | |
1036 | static struct insn_label_list *free_insn_labels; | |
1037 | ||
17a2f251 | 1038 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1039 | |
1040 | static inline void | |
17a2f251 | 1041 | mips_clear_insn_labels (void) |
252b5132 RH |
1042 | { |
1043 | register struct insn_label_list **pl; | |
1044 | ||
1045 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1046 | ; | |
1047 | *pl = insn_labels; | |
1048 | insn_labels = NULL; | |
1049 | } | |
1050 | \f | |
1051 | static char *expr_end; | |
1052 | ||
1053 | /* Expressions which appear in instructions. These are set by | |
1054 | mips_ip. */ | |
1055 | ||
1056 | static expressionS imm_expr; | |
5f74bc13 | 1057 | static expressionS imm2_expr; |
252b5132 RH |
1058 | static expressionS offset_expr; |
1059 | ||
1060 | /* Relocs associated with imm_expr and offset_expr. */ | |
1061 | ||
f6688943 TS |
1062 | static bfd_reloc_code_real_type imm_reloc[3] |
1063 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1064 | static bfd_reloc_code_real_type offset_reloc[3] | |
1065 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1066 | |
252b5132 RH |
1067 | /* These are set by mips16_ip if an explicit extension is used. */ |
1068 | ||
b34976b6 | 1069 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1070 | |
7ed4a06a | 1071 | #ifdef OBJ_ELF |
ecb4347a DJ |
1072 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1073 | ECOFF debugging. */ | |
252b5132 RH |
1074 | |
1075 | static segT pdr_seg; | |
7ed4a06a | 1076 | #endif |
252b5132 | 1077 | |
e013f690 TS |
1078 | /* The default target format to use. */ |
1079 | ||
1080 | const char * | |
17a2f251 | 1081 | mips_target_format (void) |
e013f690 TS |
1082 | { |
1083 | switch (OUTPUT_FLAVOR) | |
1084 | { | |
e013f690 TS |
1085 | case bfd_target_ecoff_flavour: |
1086 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1087 | case bfd_target_coff_flavour: | |
1088 | return "pe-mips"; | |
1089 | case bfd_target_elf_flavour: | |
1090 | #ifdef TE_TMIPS | |
cfe86eaa | 1091 | /* This is traditional mips. */ |
e013f690 | 1092 | return (target_big_endian |
cfe86eaa TS |
1093 | ? (HAVE_64BIT_OBJECTS |
1094 | ? "elf64-tradbigmips" | |
1095 | : (HAVE_NEWABI | |
1096 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1097 | : (HAVE_64BIT_OBJECTS | |
1098 | ? "elf64-tradlittlemips" | |
1099 | : (HAVE_NEWABI | |
1100 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1101 | #else |
1102 | return (target_big_endian | |
cfe86eaa TS |
1103 | ? (HAVE_64BIT_OBJECTS |
1104 | ? "elf64-bigmips" | |
1105 | : (HAVE_NEWABI | |
1106 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1107 | : (HAVE_64BIT_OBJECTS | |
1108 | ? "elf64-littlemips" | |
1109 | : (HAVE_NEWABI | |
1110 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1111 | #endif |
1112 | default: | |
1113 | abort (); | |
1114 | return NULL; | |
1115 | } | |
1116 | } | |
1117 | ||
156c2f8b NC |
1118 | /* This function is called once, at assembler startup time. It should |
1119 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1120 | ||
252b5132 | 1121 | void |
17a2f251 | 1122 | md_begin (void) |
252b5132 | 1123 | { |
252b5132 | 1124 | register const char *retval = NULL; |
156c2f8b | 1125 | int i = 0; |
252b5132 | 1126 | int broken = 0; |
1f25f5d3 | 1127 | |
fef14a42 | 1128 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1129 | as_warn (_("Could not set architecture and machine")); |
1130 | ||
252b5132 RH |
1131 | op_hash = hash_new (); |
1132 | ||
1133 | for (i = 0; i < NUMOPCODES;) | |
1134 | { | |
1135 | const char *name = mips_opcodes[i].name; | |
1136 | ||
17a2f251 | 1137 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1138 | if (retval != NULL) |
1139 | { | |
1140 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1141 | mips_opcodes[i].name, retval); | |
1142 | /* Probably a memory allocation problem? Give up now. */ | |
1143 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1144 | } | |
1145 | do | |
1146 | { | |
1147 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1148 | { | |
1149 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1150 | broken = 1; | |
1151 | } | |
1152 | ++i; | |
1153 | } | |
1154 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1155 | } | |
1156 | ||
1157 | mips16_op_hash = hash_new (); | |
1158 | ||
1159 | i = 0; | |
1160 | while (i < bfd_mips16_num_opcodes) | |
1161 | { | |
1162 | const char *name = mips16_opcodes[i].name; | |
1163 | ||
17a2f251 | 1164 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1165 | if (retval != NULL) |
1166 | as_fatal (_("internal: can't hash `%s': %s"), | |
1167 | mips16_opcodes[i].name, retval); | |
1168 | do | |
1169 | { | |
1170 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1171 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1172 | != mips16_opcodes[i].match)) | |
1173 | { | |
1174 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1175 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1176 | broken = 1; | |
1177 | } | |
1178 | ++i; | |
1179 | } | |
1180 | while (i < bfd_mips16_num_opcodes | |
1181 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1182 | } | |
1183 | ||
1184 | if (broken) | |
1185 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1186 | ||
1187 | /* We add all the general register names to the symbol table. This | |
1188 | helps us detect invalid uses of them. */ | |
1189 | for (i = 0; i < 32; i++) | |
1190 | { | |
1191 | char buf[5]; | |
1192 | ||
1193 | sprintf (buf, "$%d", i); | |
1194 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1195 | &zero_address_frag)); | |
1196 | } | |
76db943d TS |
1197 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1198 | &zero_address_frag)); | |
252b5132 RH |
1199 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1200 | &zero_address_frag)); | |
1201 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1202 | &zero_address_frag)); | |
1203 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1204 | &zero_address_frag)); | |
1205 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1206 | &zero_address_frag)); | |
1207 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1208 | &zero_address_frag)); | |
1209 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1210 | &zero_address_frag)); | |
85b51719 TS |
1211 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1212 | &zero_address_frag)); | |
252b5132 RH |
1213 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1214 | &zero_address_frag)); | |
1215 | ||
6047c971 AO |
1216 | /* If we don't add these register names to the symbol table, they |
1217 | may end up being added as regular symbols by operand(), and then | |
1218 | make it to the object file as undefined in case they're not | |
1219 | regarded as local symbols. They're local in o32, since `$' is a | |
1220 | local symbol prefix, but not in n32 or n64. */ | |
1221 | for (i = 0; i < 8; i++) | |
1222 | { | |
1223 | char buf[6]; | |
1224 | ||
1225 | sprintf (buf, "$fcc%i", i); | |
1226 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1227 | &zero_address_frag)); | |
1228 | } | |
1229 | ||
b34976b6 | 1230 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1231 | |
1232 | mips_gprmask = 0; | |
1233 | mips_cprmask[0] = 0; | |
1234 | mips_cprmask[1] = 0; | |
1235 | mips_cprmask[2] = 0; | |
1236 | mips_cprmask[3] = 0; | |
1237 | ||
1238 | /* set the default alignment for the text section (2**2) */ | |
1239 | record_alignment (text_section, 2); | |
1240 | ||
4d0d148d | 1241 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1242 | |
1243 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1244 | { | |
1245 | /* On a native system, sections must be aligned to 16 byte | |
1246 | boundaries. When configured for an embedded ELF target, we | |
1247 | don't bother. */ | |
1248 | if (strcmp (TARGET_OS, "elf") != 0) | |
1249 | { | |
1250 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1251 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1252 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1253 | } | |
1254 | ||
1255 | /* Create a .reginfo section for register masks and a .mdebug | |
1256 | section for debugging information. */ | |
1257 | { | |
1258 | segT seg; | |
1259 | subsegT subseg; | |
1260 | flagword flags; | |
1261 | segT sec; | |
1262 | ||
1263 | seg = now_seg; | |
1264 | subseg = now_subseg; | |
1265 | ||
1266 | /* The ABI says this section should be loaded so that the | |
1267 | running program can access it. However, we don't load it | |
1268 | if we are configured for an embedded target */ | |
1269 | flags = SEC_READONLY | SEC_DATA; | |
1270 | if (strcmp (TARGET_OS, "elf") != 0) | |
1271 | flags |= SEC_ALLOC | SEC_LOAD; | |
1272 | ||
316f5878 | 1273 | if (mips_abi != N64_ABI) |
252b5132 RH |
1274 | { |
1275 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1276 | ||
195325d2 TS |
1277 | bfd_set_section_flags (stdoutput, sec, flags); |
1278 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1279 | |
252b5132 RH |
1280 | #ifdef OBJ_ELF |
1281 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1282 | #endif | |
1283 | } | |
1284 | else | |
1285 | { | |
1286 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1287 | .reginfo section. */ | |
1288 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1289 | bfd_set_section_flags (stdoutput, sec, flags); |
1290 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1291 | |
1292 | #ifdef OBJ_ELF | |
1293 | /* Set up the option header. */ | |
1294 | { | |
1295 | Elf_Internal_Options opthdr; | |
1296 | char *f; | |
1297 | ||
1298 | opthdr.kind = ODK_REGINFO; | |
1299 | opthdr.size = (sizeof (Elf_External_Options) | |
1300 | + sizeof (Elf64_External_RegInfo)); | |
1301 | opthdr.section = 0; | |
1302 | opthdr.info = 0; | |
1303 | f = frag_more (sizeof (Elf_External_Options)); | |
1304 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1305 | (Elf_External_Options *) f); | |
1306 | ||
1307 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1308 | } | |
1309 | #endif | |
1310 | } | |
1311 | ||
1312 | if (ECOFF_DEBUGGING) | |
1313 | { | |
1314 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1315 | (void) bfd_set_section_flags (stdoutput, sec, | |
1316 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1317 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1318 | } | |
ecb4347a | 1319 | #ifdef OBJ_ELF |
dcd410fe | 1320 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1321 | { |
1322 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1323 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1324 | SEC_READONLY | SEC_RELOC | |
1325 | | SEC_DEBUGGING); | |
1326 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1327 | } | |
252b5132 RH |
1328 | #endif |
1329 | ||
1330 | subseg_set (seg, subseg); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | if (! ECOFF_DEBUGGING) | |
1335 | md_obj_begin (); | |
1336 | } | |
1337 | ||
1338 | void | |
17a2f251 | 1339 | md_mips_end (void) |
252b5132 RH |
1340 | { |
1341 | if (! ECOFF_DEBUGGING) | |
1342 | md_obj_end (); | |
1343 | } | |
1344 | ||
1345 | void | |
17a2f251 | 1346 | md_assemble (char *str) |
252b5132 RH |
1347 | { |
1348 | struct mips_cl_insn insn; | |
f6688943 TS |
1349 | bfd_reloc_code_real_type unused_reloc[3] |
1350 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1351 | |
1352 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1353 | imm2_expr.X_op = O_absent; |
252b5132 | 1354 | offset_expr.X_op = O_absent; |
f6688943 TS |
1355 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1356 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1357 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1358 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1359 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1360 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1361 | |
1362 | if (mips_opts.mips16) | |
1363 | mips16_ip (str, &insn); | |
1364 | else | |
1365 | { | |
1366 | mips_ip (str, &insn); | |
beae10d5 KH |
1367 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1368 | str, insn.insn_opcode)); | |
252b5132 RH |
1369 | } |
1370 | ||
1371 | if (insn_error) | |
1372 | { | |
1373 | as_bad ("%s `%s'", insn_error, str); | |
1374 | return; | |
1375 | } | |
1376 | ||
1377 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1378 | { | |
584892a6 | 1379 | macro_start (); |
252b5132 RH |
1380 | if (mips_opts.mips16) |
1381 | mips16_macro (&insn); | |
1382 | else | |
1383 | macro (&insn); | |
584892a6 | 1384 | macro_end (); |
252b5132 RH |
1385 | } |
1386 | else | |
1387 | { | |
1388 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1389 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1390 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1391 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1392 | else |
4d7206a2 | 1393 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1394 | } |
1395 | } | |
1396 | ||
5919d012 RS |
1397 | /* Return true if the given relocation might need a matching %lo(). |
1398 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1399 | applied to local symbols. */ | |
1400 | ||
1401 | static inline bfd_boolean | |
17a2f251 | 1402 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1403 | { |
3b91255e RS |
1404 | return (HAVE_IN_PLACE_ADDENDS |
1405 | && (reloc == BFD_RELOC_HI16_S | |
1406 | || reloc == BFD_RELOC_MIPS_GOT16)); | |
5919d012 RS |
1407 | } |
1408 | ||
1409 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1410 | relocation. */ | |
1411 | ||
1412 | static inline bfd_boolean | |
17a2f251 | 1413 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1414 | { |
1415 | return (fixp->fx_next != NULL | |
1416 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1417 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1418 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1419 | } | |
1420 | ||
252b5132 RH |
1421 | /* See whether instruction IP reads register REG. CLASS is the type |
1422 | of register. */ | |
1423 | ||
1424 | static int | |
17a2f251 TS |
1425 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1426 | enum mips_regclass class) | |
252b5132 RH |
1427 | { |
1428 | if (class == MIPS16_REG) | |
1429 | { | |
1430 | assert (mips_opts.mips16); | |
1431 | reg = mips16_to_32_reg_map[reg]; | |
1432 | class = MIPS_GR_REG; | |
1433 | } | |
1434 | ||
85b51719 TS |
1435 | /* Don't report on general register ZERO, since it never changes. */ |
1436 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1437 | return 0; |
1438 | ||
1439 | if (class == MIPS_FP_REG) | |
1440 | { | |
1441 | assert (! mips_opts.mips16); | |
1442 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1443 | This is not optimal, because it will introduce an unnecessary | |
1444 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1445 | need to distinguish reading both $f0 and $f1 or just one of | |
1446 | them. Note that we don't have to check the other way, | |
1447 | because there is no instruction that sets both $f0 and $f1 | |
1448 | and requires a delay. */ | |
1449 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1450 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1451 | == (reg &~ (unsigned) 1))) | |
1452 | return 1; | |
1453 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1454 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1455 | == (reg &~ (unsigned) 1))) | |
1456 | return 1; | |
1457 | } | |
1458 | else if (! mips_opts.mips16) | |
1459 | { | |
1460 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1461 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1462 | return 1; | |
1463 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1464 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1465 | return 1; | |
1466 | } | |
1467 | else | |
1468 | { | |
1469 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1470 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1471 | & MIPS16OP_MASK_RX)] | |
1472 | == reg)) | |
1473 | return 1; | |
1474 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1475 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1476 | & MIPS16OP_MASK_RY)] | |
1477 | == reg)) | |
1478 | return 1; | |
1479 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1480 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1481 | & MIPS16OP_MASK_MOVE32Z)] | |
1482 | == reg)) | |
1483 | return 1; | |
1484 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1485 | return 1; | |
1486 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1487 | return 1; | |
1488 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1489 | return 1; | |
1490 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1491 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1492 | & MIPS16OP_MASK_REGR32) == reg) | |
1493 | return 1; | |
1494 | } | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | /* This function returns true if modifying a register requires a | |
1500 | delay. */ | |
1501 | ||
1502 | static int | |
17a2f251 | 1503 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1504 | { |
1505 | unsigned long prev_pinfo; | |
1506 | ||
1507 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1508 | if (! mips_opts.noreorder | |
81912461 ILT |
1509 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1510 | && ! gpr_interlocks) | |
1511 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1512 | && ! cop_interlocks))) | |
252b5132 | 1513 | { |
81912461 ILT |
1514 | /* A load from a coprocessor or from memory. All load delays |
1515 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1516 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1517 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1518 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1519 | return 1; | |
1520 | } | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1526 | handle them specially, such as generating jalx instructions when | |
1527 | needed. We also make them odd for the duration of the assembly, in | |
1528 | order to generate the right sort of code. We will make them even | |
1529 | in the adjust_symtab routine, while leaving them marked. This is | |
1530 | convenient for the debugger and the disassembler. The linker knows | |
1531 | to make them odd again. */ | |
1532 | ||
1533 | static void | |
17a2f251 | 1534 | mips16_mark_labels (void) |
252b5132 RH |
1535 | { |
1536 | if (mips_opts.mips16) | |
1537 | { | |
1538 | struct insn_label_list *l; | |
98aa84af | 1539 | valueT val; |
252b5132 RH |
1540 | |
1541 | for (l = insn_labels; l != NULL; l = l->next) | |
1542 | { | |
1543 | #ifdef OBJ_ELF | |
1544 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1545 | S_SET_OTHER (l->label, STO_MIPS16); | |
1546 | #endif | |
98aa84af AM |
1547 | val = S_GET_VALUE (l->label); |
1548 | if ((val & 1) == 0) | |
1549 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1550 | } |
1551 | } | |
1552 | } | |
1553 | ||
4d7206a2 RS |
1554 | /* End the current frag. Make it a variant frag and record the |
1555 | relaxation info. */ | |
1556 | ||
1557 | static void | |
1558 | relax_close_frag (void) | |
1559 | { | |
584892a6 | 1560 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1561 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1562 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1563 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1564 | ||
1565 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1566 | mips_relax.first_fixup = 0; | |
1567 | } | |
1568 | ||
1569 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1570 | See the comment above RELAX_ENCODE for more details. */ | |
1571 | ||
1572 | static void | |
1573 | relax_start (symbolS *symbol) | |
1574 | { | |
1575 | assert (mips_relax.sequence == 0); | |
1576 | mips_relax.sequence = 1; | |
1577 | mips_relax.symbol = symbol; | |
1578 | } | |
1579 | ||
1580 | /* Start generating the second version of a relaxable sequence. | |
1581 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1582 | |
1583 | static void | |
4d7206a2 RS |
1584 | relax_switch (void) |
1585 | { | |
1586 | assert (mips_relax.sequence == 1); | |
1587 | mips_relax.sequence = 2; | |
1588 | } | |
1589 | ||
1590 | /* End the current relaxable sequence. */ | |
1591 | ||
1592 | static void | |
1593 | relax_end (void) | |
1594 | { | |
1595 | assert (mips_relax.sequence == 2); | |
1596 | relax_close_frag (); | |
1597 | mips_relax.sequence = 0; | |
1598 | } | |
1599 | ||
1600 | /* Output an instruction. IP is the instruction information. | |
1601 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1602 | RELOC_TYPE. */ | |
1603 | ||
1604 | static void | |
1605 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1606 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1607 | { |
1608 | register unsigned long prev_pinfo, pinfo; | |
1609 | char *f; | |
f6688943 | 1610 | fixS *fixp[3]; |
252b5132 | 1611 | int nops = 0; |
895921c9 MR |
1612 | relax_stateT prev_insn_frag_type = 0; |
1613 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1614 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1615 | |
1616 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1617 | mips16_mark_labels (); |
252b5132 RH |
1618 | |
1619 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1620 | pinfo = ip->insn_mo->pinfo; | |
1621 | ||
4d7206a2 RS |
1622 | if (mips_relax.sequence != 2 |
1623 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1624 | { |
1625 | int prev_prev_nop; | |
1626 | ||
1627 | /* If the previous insn required any delay slots, see if we need | |
1628 | to insert a NOP or two. There are eight kinds of possible | |
1629 | hazards, of which an instruction can have at most one type. | |
1630 | (1) a load from memory delay | |
1631 | (2) a load from a coprocessor delay | |
1632 | (3) an unconditional branch delay | |
1633 | (4) a conditional branch delay | |
1634 | (5) a move to coprocessor register delay | |
1635 | (6) a load coprocessor register from memory delay | |
1636 | (7) a coprocessor condition code delay | |
1637 | (8) a HI/LO special register delay | |
1638 | ||
1639 | There are a lot of optimizations we could do that we don't. | |
1640 | In particular, we do not, in general, reorder instructions. | |
1641 | If you use gcc with optimization, it will reorder | |
1642 | instructions and generally do much more optimization then we | |
1643 | do here; repeating all that work in the assembler would only | |
1644 | benefit hand written assembly code, and does not seem worth | |
1645 | it. */ | |
1646 | ||
1647 | /* This is how a NOP is emitted. */ | |
1648 | #define emit_nop() \ | |
1649 | (mips_opts.mips16 \ | |
1650 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1651 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1652 | ||
1653 | /* The previous insn might require a delay slot, depending upon | |
1654 | the contents of the current insn. */ | |
1655 | if (! mips_opts.mips16 | |
81912461 ILT |
1656 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1657 | && ! gpr_interlocks) | |
1658 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1659 | && ! cop_interlocks))) | |
252b5132 RH |
1660 | { |
1661 | /* A load from a coprocessor or from memory. All load | |
1662 | delays delay the use of general register rt for one | |
81912461 | 1663 | instruction. */ |
beae10d5 | 1664 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1665 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1666 | if (mips_optimize == 0 | |
1667 | || insn_uses_reg (ip, | |
1668 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1669 | & OP_MASK_RT), | |
1670 | MIPS_GR_REG)) | |
1671 | ++nops; | |
1672 | } | |
1673 | else if (! mips_opts.mips16 | |
252b5132 | 1674 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1675 | && ! cop_interlocks) |
81912461 ILT |
1676 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1677 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1678 | { |
1679 | /* A generic coprocessor delay. The previous instruction | |
1680 | modified a coprocessor general or control register. If | |
1681 | it modified a control register, we need to avoid any | |
1682 | coprocessor instruction (this is probably not always | |
1683 | required, but it sometimes is). If it modified a general | |
1684 | register, we avoid using that register. | |
1685 | ||
252b5132 RH |
1686 | This case is not handled very well. There is no special |
1687 | knowledge of CP0 handling, and the coprocessors other | |
1688 | than the floating point unit are not distinguished at | |
1689 | all. */ | |
1690 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1691 | Need to modify this to include knowledge about |
252b5132 RH |
1692 | user specified delays! */ |
1693 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1694 | { | |
1695 | if (mips_optimize == 0 | |
1696 | || insn_uses_reg (ip, | |
1697 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1698 | & OP_MASK_FT), | |
1699 | MIPS_FP_REG)) | |
1700 | ++nops; | |
1701 | } | |
1702 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1703 | { | |
1704 | if (mips_optimize == 0 | |
1705 | || insn_uses_reg (ip, | |
1706 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1707 | & OP_MASK_FS), | |
1708 | MIPS_FP_REG)) | |
1709 | ++nops; | |
1710 | } | |
1711 | else | |
1712 | { | |
1713 | /* We don't know exactly what the previous instruction | |
1714 | does. If the current instruction uses a coprocessor | |
1715 | register, we must insert a NOP. If previous | |
1716 | instruction may set the condition codes, and the | |
1717 | current instruction uses them, we must insert two | |
1718 | NOPS. */ | |
bdaaa2e1 | 1719 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1720 | if (mips_optimize == 0 |
1721 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1722 | && (pinfo & INSN_READ_COND_CODE))) | |
1723 | nops += 2; | |
1724 | else if (pinfo & INSN_COP) | |
1725 | ++nops; | |
1726 | } | |
1727 | } | |
1728 | else if (! mips_opts.mips16 | |
252b5132 RH |
1729 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1730 | && ! cop_interlocks) | |
1731 | { | |
1732 | /* The previous instruction sets the coprocessor condition | |
1733 | codes, but does not require a general coprocessor delay | |
1734 | (this means it is a floating point comparison | |
1735 | instruction). If this instruction uses the condition | |
1736 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1738 | if (mips_optimize == 0 |
1739 | || (pinfo & INSN_READ_COND_CODE)) | |
1740 | ++nops; | |
1741 | } | |
6b76fefe CM |
1742 | |
1743 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1744 | previous insn was an mfhi/mflo and the current insn | |
1745 | reads the register that the mfhi/mflo wrote to, then | |
1746 | insert two nops. */ | |
1747 | ||
1748 | else if (mips_7000_hilo_fix | |
1749 | && MF_HILO_INSN (prev_pinfo) | |
1750 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1751 | & OP_MASK_RD), |
1752 | MIPS_GR_REG)) | |
6b76fefe CM |
1753 | { |
1754 | nops += 2; | |
1755 | } | |
1756 | ||
1757 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1758 | 2nd previous insn was an mfhi/mflo and the current insn | |
1759 | reads the register that the mfhi/mflo wrote to, then | |
1760 | insert one nop. */ | |
1761 | ||
1762 | else if (mips_7000_hilo_fix | |
1763 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1764 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1765 | & OP_MASK_RD), | |
1766 | MIPS_GR_REG)) | |
bdaaa2e1 | 1767 | |
6b76fefe | 1768 | { |
f9419b05 | 1769 | ++nops; |
6b76fefe | 1770 | } |
bdaaa2e1 | 1771 | |
252b5132 RH |
1772 | else if (prev_pinfo & INSN_READ_LO) |
1773 | { | |
1774 | /* The previous instruction reads the LO register; if the | |
1775 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1776 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1777 | Also the tx39's multiply instructions can be executed |
1778 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1779 | though the tx39's divide insns still do require the |
1780 | delay. */ | |
252b5132 | 1781 | if (! (hilo_interlocks |
048cdf86 | 1782 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1783 | && (mips_optimize == 0 |
1784 | || (pinfo & INSN_WRITE_LO))) | |
1785 | nops += 2; | |
1786 | /* Most mips16 branch insns don't have a delay slot. | |
1787 | If a read from LO is immediately followed by a branch | |
1788 | to a write to LO we have a read followed by a write | |
1789 | less than 2 insns away. We assume the target of | |
1790 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1791 | between a read and an immediately following branch. */ |
252b5132 RH |
1792 | else if (mips_opts.mips16 |
1793 | && (mips_optimize == 0 | |
1794 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1795 | ++nops; |
252b5132 RH |
1796 | } |
1797 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1798 | { | |
1799 | /* The previous instruction reads the HI register; if the | |
1800 | current instruction writes to the HI register, we must | |
1801 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1802 | Also the note tx39's multiply above. */ |
252b5132 | 1803 | if (! (hilo_interlocks |
048cdf86 | 1804 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1805 | && (mips_optimize == 0 |
1806 | || (pinfo & INSN_WRITE_HI))) | |
1807 | nops += 2; | |
1808 | /* Most mips16 branch insns don't have a delay slot. | |
1809 | If a read from HI is immediately followed by a branch | |
1810 | to a write to HI we have a read followed by a write | |
1811 | less than 2 insns away. We assume the target of | |
1812 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1813 | between a read and an immediately following branch. */ |
252b5132 RH |
1814 | else if (mips_opts.mips16 |
1815 | && (mips_optimize == 0 | |
1816 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1817 | ++nops; |
252b5132 RH |
1818 | } |
1819 | ||
1820 | /* If the previous instruction was in a noreorder section, then | |
1821 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1822 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1823 | if (prev_insn_unreordered) |
1824 | nops = 0; | |
1825 | ||
1826 | /* There are two cases which require two intervening | |
1827 | instructions: 1) setting the condition codes using a move to | |
1828 | coprocessor instruction which requires a general coprocessor | |
1829 | delay and then reading the condition codes 2) reading the HI | |
1830 | or LO register and then writing to it (except on processors | |
1831 | which have interlocks). If we are not already emitting a NOP | |
1832 | instruction, we must check for these cases compared to the | |
1833 | instruction previous to the previous instruction. */ | |
1834 | if ((! mips_opts.mips16 | |
252b5132 RH |
1835 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1836 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1837 | && (pinfo & INSN_READ_COND_CODE) | |
1838 | && ! cop_interlocks) | |
1839 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1840 | && (pinfo & INSN_WRITE_LO) | |
1841 | && ! (hilo_interlocks | |
048cdf86 | 1842 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1843 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1844 | && (pinfo & INSN_WRITE_HI) | |
1845 | && ! (hilo_interlocks | |
048cdf86 | 1846 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1847 | prev_prev_nop = 1; |
1848 | else | |
1849 | prev_prev_nop = 0; | |
1850 | ||
1851 | if (prev_prev_insn_unreordered) | |
1852 | prev_prev_nop = 0; | |
1853 | ||
1854 | if (prev_prev_nop && nops == 0) | |
1855 | ++nops; | |
1856 | ||
d766e8ec | 1857 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1858 | { |
1859 | /* We're out of bits in pinfo, so we must resort to string | |
1860 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1861 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1862 | int min_nops = 0; |
1863 | const char *pn = prev_insn.insn_mo->name; | |
1864 | const char *tn = ip->insn_mo->name; | |
532c738a RS |
1865 | if (strncmp (pn, "macc", 4) == 0 |
1866 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1867 | { |
1868 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1869 | if (strstr (tn, "div")) | |
532c738a | 1870 | min_nops = 1; |
60b63b72 | 1871 | |
532c738a RS |
1872 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1873 | instruction is executed immediately after a MACC or | |
1874 | DMACC instruction, the result of [either instruction] | |
1875 | is incorrect." */ | |
1876 | if (strncmp (tn, "mult", 4) == 0 | |
1877 | || strncmp (tn, "dmult", 5) == 0) | |
1878 | min_nops = 1; | |
1879 | ||
1880 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1881 | Applies on top of VR4181A MD(1) errata. */ | |
1882 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1883 | min_nops = 1; | |
60b63b72 RS |
1884 | |
1885 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1886 | if (strcmp (tn, "mtlo") == 0 | |
1887 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1888 | min_nops = 1; |
60b63b72 | 1889 | } |
532c738a RS |
1890 | else if (strncmp (pn, "dmult", 5) == 0 |
1891 | && (strncmp (tn, "dmult", 5) == 0 | |
1892 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1893 | { |
1894 | /* Here is the rest of errata 23. */ | |
1895 | min_nops = 1; | |
1896 | } | |
532c738a RS |
1897 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1898 | && (strncmp (tn, "macc", 4) == 0 | |
1899 | || strncmp (tn, "dmacc", 5) == 0)) | |
1900 | { | |
1901 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1902 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1903 | DDIV or DDIVU instruction, the result of the MACC or | |
1904 | DMACC instruction is incorrect.". This partly overlaps | |
1905 | the workaround for errata 23. */ | |
1906 | min_nops = 1; | |
1907 | } | |
60b63b72 RS |
1908 | if (nops < min_nops) |
1909 | nops = min_nops; | |
1910 | } | |
1911 | ||
252b5132 RH |
1912 | /* If we are being given a nop instruction, don't bother with |
1913 | one of the nops we would otherwise output. This will only | |
1914 | happen when a nop instruction is used with mips_optimize set | |
1915 | to 0. */ | |
1916 | if (nops > 0 | |
1917 | && ! mips_opts.noreorder | |
156c2f8b | 1918 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1919 | --nops; |
1920 | ||
1921 | /* Now emit the right number of NOP instructions. */ | |
1922 | if (nops > 0 && ! mips_opts.noreorder) | |
1923 | { | |
1924 | fragS *old_frag; | |
1925 | unsigned long old_frag_offset; | |
1926 | int i; | |
1927 | struct insn_label_list *l; | |
1928 | ||
1929 | old_frag = frag_now; | |
1930 | old_frag_offset = frag_now_fix (); | |
1931 | ||
1932 | for (i = 0; i < nops; i++) | |
1933 | emit_nop (); | |
1934 | ||
1935 | if (listing) | |
1936 | { | |
1937 | listing_prev_line (); | |
1938 | /* We may be at the start of a variant frag. In case we | |
1939 | are, make sure there is enough space for the frag | |
1940 | after the frags created by listing_prev_line. The | |
1941 | argument to frag_grow here must be at least as large | |
1942 | as the argument to all other calls to frag_grow in | |
1943 | this file. We don't have to worry about being in the | |
1944 | middle of a variant frag, because the variants insert | |
1945 | all needed nop instructions themselves. */ | |
1946 | frag_grow (40); | |
1947 | } | |
1948 | ||
1949 | for (l = insn_labels; l != NULL; l = l->next) | |
1950 | { | |
98aa84af AM |
1951 | valueT val; |
1952 | ||
252b5132 | 1953 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1954 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1955 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1956 | /* mips16 text labels are stored as odd. */ |
1957 | if (mips_opts.mips16) | |
f9419b05 | 1958 | ++val; |
98aa84af | 1959 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1960 | } |
1961 | ||
1962 | #ifndef NO_ECOFF_DEBUGGING | |
1963 | if (ECOFF_DEBUGGING) | |
1964 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1965 | #endif | |
1966 | } | |
1967 | else if (prev_nop_frag != NULL) | |
1968 | { | |
1969 | /* We have a frag holding nops we may be able to remove. If | |
1970 | we don't need any nops, we can decrease the size of | |
1971 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1972 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1973 | if (prev_nop_frag_since == 0) |
1974 | { | |
1975 | if (nops == 0) | |
1976 | { | |
1977 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1978 | --prev_nop_frag_holds; | |
1979 | } | |
1980 | else | |
1981 | prev_nop_frag_required += nops; | |
1982 | } | |
1983 | else | |
1984 | { | |
1985 | if (prev_prev_nop == 0) | |
1986 | { | |
1987 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1988 | --prev_nop_frag_holds; | |
1989 | } | |
1990 | else | |
1991 | ++prev_nop_frag_required; | |
1992 | } | |
1993 | ||
1994 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1995 | prev_nop_frag = NULL; | |
1996 | ||
1997 | ++prev_nop_frag_since; | |
1998 | ||
1999 | /* Sanity check: by the time we reach the second instruction | |
2000 | after prev_nop_frag, we should have used up all the nops | |
2001 | one way or another. */ | |
2002 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2003 | } | |
2004 | } | |
2005 | ||
895921c9 MR |
2006 | /* Record the frag type before frag_var. */ |
2007 | if (prev_insn_frag) | |
2008 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2009 | ||
4d7206a2 | 2010 | if (address_expr |
0b25d3e6 | 2011 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2012 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2013 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2014 | && mips_relax_branch | |
2015 | /* Don't try branch relaxation within .set nomacro, or within | |
2016 | .set noat if we use $at for PIC computations. If it turns | |
2017 | out that the branch was out-of-range, we'll get an error. */ | |
2018 | && !mips_opts.warn_about_macros | |
2019 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2020 | && !mips_opts.mips16) | |
2021 | { | |
895921c9 | 2022 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2023 | f = frag_var (rs_machine_dependent, |
2024 | relaxed_branch_length | |
2025 | (NULL, NULL, | |
2026 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2027 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2028 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2029 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2030 | pinfo & INSN_COND_BRANCH_LIKELY, |
2031 | pinfo & INSN_WRITE_GPR_31, | |
2032 | 0), | |
2033 | address_expr->X_add_symbol, | |
2034 | address_expr->X_add_number, | |
2035 | 0); | |
2036 | *reloc_type = BFD_RELOC_UNUSED; | |
2037 | } | |
2038 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2039 | { |
2040 | /* We need to set up a variant frag. */ | |
2041 | assert (mips_opts.mips16 && address_expr != NULL); | |
2042 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2043 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2044 | mips16_small, mips16_ext, |
2045 | (prev_pinfo | |
2046 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2047 | (*prev_insn_reloc_type |
252b5132 | 2048 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2049 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2050 | } |
252b5132 RH |
2051 | else if (mips_opts.mips16 |
2052 | && ! ip->use_extend | |
f6688943 | 2053 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2054 | { |
2055 | /* Make sure there is enough room to swap this instruction with | |
2056 | a following jump instruction. */ | |
2057 | frag_grow (6); | |
2058 | f = frag_more (2); | |
2059 | } | |
2060 | else | |
2061 | { | |
2062 | if (mips_opts.mips16 | |
2063 | && mips_opts.noreorder | |
2064 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2065 | as_warn (_("extended instruction in delay slot")); | |
2066 | ||
4d7206a2 RS |
2067 | if (mips_relax.sequence) |
2068 | { | |
2069 | /* If we've reached the end of this frag, turn it into a variant | |
2070 | frag and record the information for the instructions we've | |
2071 | written so far. */ | |
2072 | if (frag_room () < 4) | |
2073 | relax_close_frag (); | |
2074 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2075 | } | |
2076 | ||
584892a6 RS |
2077 | if (mips_relax.sequence != 2) |
2078 | mips_macro_warning.sizes[0] += 4; | |
2079 | if (mips_relax.sequence != 1) | |
2080 | mips_macro_warning.sizes[1] += 4; | |
2081 | ||
252b5132 RH |
2082 | f = frag_more (4); |
2083 | } | |
2084 | ||
f6688943 TS |
2085 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2086 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2087 | { |
2088 | if (address_expr->X_op == O_constant) | |
2089 | { | |
4db1a35d | 2090 | valueT tmp; |
f6688943 TS |
2091 | |
2092 | switch (*reloc_type) | |
252b5132 RH |
2093 | { |
2094 | case BFD_RELOC_32: | |
2095 | ip->insn_opcode |= address_expr->X_add_number; | |
2096 | break; | |
2097 | ||
f6688943 | 2098 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2099 | tmp = (address_expr->X_add_number |
2100 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2101 | tmp >>= 16; |
2102 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2103 | break; | |
2104 | ||
2105 | case BFD_RELOC_MIPS_HIGHER: | |
2106 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2107 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2108 | break; | |
2109 | ||
2110 | case BFD_RELOC_HI16_S: | |
2111 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2112 | >> 16) & 0xffff; | |
2113 | break; | |
2114 | ||
2115 | case BFD_RELOC_HI16: | |
2116 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2117 | break; | |
2118 | ||
252b5132 | 2119 | case BFD_RELOC_LO16: |
ed6fb7bd | 2120 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2121 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2122 | break; | |
2123 | ||
2124 | case BFD_RELOC_MIPS_JMP: | |
2125 | if ((address_expr->X_add_number & 3) != 0) | |
2126 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2127 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2128 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2129 | as_bad (_("jump address range overflow (0x%lx)"), |
2130 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2131 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2132 | break; | |
2133 | ||
2134 | case BFD_RELOC_MIPS16_JMP: | |
2135 | if ((address_expr->X_add_number & 3) != 0) | |
2136 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2137 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2138 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2139 | as_bad (_("jump address range overflow (0x%lx)"), |
2140 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2141 | ip->insn_opcode |= |
2142 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2143 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2144 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2145 | break; | |
2146 | ||
252b5132 RH |
2147 | case BFD_RELOC_16_PCREL_S2: |
2148 | goto need_reloc; | |
2149 | ||
2150 | default: | |
2151 | internalError (); | |
2152 | } | |
2153 | } | |
2154 | else | |
252b5132 | 2155 | need_reloc: |
4d7206a2 RS |
2156 | { |
2157 | reloc_howto_type *howto; | |
2158 | int i; | |
34ce925e | 2159 | |
4d7206a2 RS |
2160 | /* In a compound relocation, it is the final (outermost) |
2161 | operator that determines the relocated field. */ | |
2162 | for (i = 1; i < 3; i++) | |
2163 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2164 | break; | |
34ce925e | 2165 | |
4d7206a2 RS |
2166 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2167 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2168 | bfd_get_reloc_size(howto), | |
2169 | address_expr, | |
2170 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2171 | reloc_type[0]); | |
2172 | ||
2173 | /* These relocations can have an addend that won't fit in | |
2174 | 4 octets for 64bit assembly. */ | |
2175 | if (HAVE_64BIT_GPRS | |
2176 | && ! howto->partial_inplace | |
2177 | && (reloc_type[0] == BFD_RELOC_16 | |
2178 | || reloc_type[0] == BFD_RELOC_32 | |
2179 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2180 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2181 | || reloc_type[0] == BFD_RELOC_LO16 | |
2182 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2183 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2184 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2185 | || reloc_type[0] == BFD_RELOC_64 | |
2186 | || reloc_type[0] == BFD_RELOC_CTOR | |
2187 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2188 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2189 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2190 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2191 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2192 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
2193 | fixp[0]->fx_no_overflow = 1; | |
2194 | ||
2195 | if (mips_relax.sequence) | |
2196 | { | |
2197 | if (mips_relax.first_fixup == 0) | |
2198 | mips_relax.first_fixup = fixp[0]; | |
2199 | } | |
2200 | else if (reloc_needs_lo_p (*reloc_type)) | |
2201 | { | |
2202 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2203 | |
4d7206a2 RS |
2204 | /* Reuse the last entry if it already has a matching %lo. */ |
2205 | hi_fixup = mips_hi_fixup_list; | |
2206 | if (hi_fixup == 0 | |
2207 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2208 | { | |
2209 | hi_fixup = ((struct mips_hi_fixup *) | |
2210 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2211 | hi_fixup->next = mips_hi_fixup_list; | |
2212 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2213 | } |
4d7206a2 RS |
2214 | hi_fixup->fixp = fixp[0]; |
2215 | hi_fixup->seg = now_seg; | |
2216 | } | |
f6688943 | 2217 | |
4d7206a2 RS |
2218 | /* Add fixups for the second and third relocations, if given. |
2219 | Note that the ABI allows the second relocation to be | |
2220 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2221 | moment we only use RSS_UNDEF, but we could add support | |
2222 | for the others if it ever becomes necessary. */ | |
2223 | for (i = 1; i < 3; i++) | |
2224 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2225 | { | |
2226 | address_expr->X_op = O_absent; | |
2227 | address_expr->X_add_symbol = 0; | |
2228 | address_expr->X_add_number = 0; | |
34ce925e | 2229 | |
4d7206a2 RS |
2230 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, |
2231 | fixp[0]->fx_size, address_expr, | |
2232 | FALSE, reloc_type[i]); | |
2233 | } | |
252b5132 RH |
2234 | } |
2235 | } | |
2236 | ||
2237 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2238 | { |
2239 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2240 | #ifdef OBJ_ELF | |
2241 | dwarf2_emit_insn (4); | |
2242 | #endif | |
2243 | } | |
f6688943 | 2244 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2245 | { |
2246 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2247 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab | 2248 | #ifdef OBJ_ELF |
20e56c33 RS |
2249 | /* The value passed to dwarf2_emit_insn is the distance between |
2250 | the end of the current instruction and the address that should | |
2251 | be recorded in the debug tables. Since we want to use ISA-encoded | |
2252 | addresses in MIPS16 debug info, the value is one byte less than | |
2253 | the real instruction length. */ | |
2254 | dwarf2_emit_insn (3); | |
c5dd6aab | 2255 | #endif |
252b5132 RH |
2256 | } |
2257 | else | |
2258 | { | |
2259 | if (ip->use_extend) | |
2260 | { | |
2261 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2262 | f += 2; | |
2263 | } | |
2264 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab | 2265 | #ifdef OBJ_ELF |
20e56c33 | 2266 | dwarf2_emit_insn (ip->use_extend ? 3 : 1); |
c5dd6aab | 2267 | #endif |
252b5132 RH |
2268 | } |
2269 | ||
2270 | /* Update the register mask information. */ | |
2271 | if (! mips_opts.mips16) | |
2272 | { | |
2273 | if (pinfo & INSN_WRITE_GPR_D) | |
2274 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2275 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2276 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2277 | if (pinfo & INSN_READ_GPR_S) | |
2278 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2279 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2280 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2281 | if (pinfo & INSN_WRITE_FPR_D) |
2282 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2283 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2284 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2285 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2286 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2287 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2288 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2289 | if (pinfo & INSN_COP) | |
2290 | { | |
bdaaa2e1 KH |
2291 | /* We don't keep enough information to sort these cases out. |
2292 | The itbl support does keep this information however, although | |
2293 | we currently don't support itbl fprmats as part of the cop | |
2294 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2295 | } |
2296 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2297 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2298 | } |
2299 | else | |
2300 | { | |
2301 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2302 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2303 | & MIPS16OP_MASK_RX); | |
2304 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2305 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2306 | & MIPS16OP_MASK_RY); | |
2307 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2308 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2309 | & MIPS16OP_MASK_RZ); | |
2310 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2311 | mips_gprmask |= 1 << TREG; | |
2312 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2313 | mips_gprmask |= 1 << SP; | |
2314 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2315 | mips_gprmask |= 1 << RA; | |
2316 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2317 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2318 | if (pinfo & MIPS16_INSN_READ_Z) | |
2319 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2320 | & MIPS16OP_MASK_MOVE32Z); | |
2321 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2322 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2323 | & MIPS16OP_MASK_REGR32); | |
2324 | } | |
2325 | ||
4d7206a2 | 2326 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2327 | { |
2328 | /* Filling the branch delay slot is more complex. We try to | |
2329 | switch the branch with the previous instruction, which we can | |
2330 | do if the previous instruction does not set up a condition | |
2331 | that the branch tests and if the branch is not itself the | |
2332 | target of any branch. */ | |
2333 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2334 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2335 | { | |
2336 | if (mips_optimize < 2 | |
2337 | /* If we have seen .set volatile or .set nomove, don't | |
2338 | optimize. */ | |
2339 | || mips_opts.nomove != 0 | |
2340 | /* If we had to emit any NOP instructions, then we | |
2341 | already know we can not swap. */ | |
2342 | || nops != 0 | |
2343 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2344 | swap. */ |
252b5132 RH |
2345 | || ! prev_insn_valid |
2346 | /* If the previous insn is already in a branch delay | |
2347 | slot, then we can not swap. */ | |
2348 | || prev_insn_is_delay_slot | |
2349 | /* If the previous previous insn was in a .set | |
2350 | noreorder, we can't swap. Actually, the MIPS | |
2351 | assembler will swap in this situation. However, gcc | |
2352 | configured -with-gnu-as will generate code like | |
2353 | .set noreorder | |
2354 | lw $4,XXX | |
2355 | .set reorder | |
2356 | INSN | |
2357 | bne $4,$0,foo | |
2358 | in which we can not swap the bne and INSN. If gcc is | |
2359 | not configured -with-gnu-as, it does not output the | |
2360 | .set pseudo-ops. We don't have to check | |
2361 | prev_insn_unreordered, because prev_insn_valid will | |
2362 | be 0 in that case. We don't want to use | |
2363 | prev_prev_insn_valid, because we do want to be able | |
2364 | to swap at the start of a function. */ | |
2365 | || prev_prev_insn_unreordered | |
2366 | /* If the branch is itself the target of a branch, we | |
2367 | can not swap. We cheat on this; all we check for is | |
2368 | whether there is a label on this instruction. If | |
2369 | there are any branches to anything other than a | |
2370 | label, users must use .set noreorder. */ | |
2371 | || insn_labels != NULL | |
895921c9 MR |
2372 | /* If the previous instruction is in a variant frag |
2373 | other than this branch's one, we cannot do the swap. | |
2374 | This does not apply to the mips16, which uses variant | |
2375 | frags for different purposes. */ | |
252b5132 | 2376 | || (! mips_opts.mips16 |
895921c9 | 2377 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2378 | /* If the branch reads the condition codes, we don't |
2379 | even try to swap, because in the sequence | |
2380 | ctc1 $X,$31 | |
2381 | INSN | |
2382 | INSN | |
2383 | bc1t LABEL | |
2384 | we can not swap, and I don't feel like handling that | |
2385 | case. */ | |
2386 | || (! mips_opts.mips16 | |
81912461 ILT |
2387 | && (pinfo & INSN_READ_COND_CODE) |
2388 | && ! cop_interlocks) | |
252b5132 | 2389 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2390 | delay slot, because the target of the branch might |
252b5132 RH |
2391 | interfere with that instruction. */ |
2392 | || (! mips_opts.mips16 | |
252b5132 | 2393 | && (prev_pinfo |
bdaaa2e1 | 2394 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2395 | & (INSN_LOAD_COPROC_DELAY |
2396 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2397 | | INSN_WRITE_COND_CODE)) |
2398 | && ! cop_interlocks) | |
252b5132 | 2399 | || (! (hilo_interlocks |
048cdf86 | 2400 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2401 | && (prev_pinfo |
2402 | & (INSN_READ_LO | |
2403 | | INSN_READ_HI))) | |
2404 | || (! mips_opts.mips16 | |
81912461 ILT |
2405 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2406 | && ! gpr_interlocks) | |
252b5132 | 2407 | || (! mips_opts.mips16 |
bdaaa2e1 | 2408 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2409 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2410 | && ! cop_mem_interlocks) | |
252b5132 RH |
2411 | /* We can not swap with a branch instruction. */ |
2412 | || (prev_pinfo | |
2413 | & (INSN_UNCOND_BRANCH_DELAY | |
2414 | | INSN_COND_BRANCH_DELAY | |
2415 | | INSN_COND_BRANCH_LIKELY)) | |
2416 | /* We do not swap with a trap instruction, since it | |
2417 | complicates trap handlers to have the trap | |
2418 | instruction be in a delay slot. */ | |
2419 | || (prev_pinfo & INSN_TRAP) | |
2420 | /* If the branch reads a register that the previous | |
2421 | instruction sets, we can not swap. */ | |
2422 | || (! mips_opts.mips16 | |
2423 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2424 | && insn_uses_reg (ip, | |
2425 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2426 | & OP_MASK_RT), | |
2427 | MIPS_GR_REG)) | |
2428 | || (! mips_opts.mips16 | |
2429 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2430 | && insn_uses_reg (ip, | |
2431 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2432 | & OP_MASK_RD), | |
2433 | MIPS_GR_REG)) | |
2434 | || (mips_opts.mips16 | |
2435 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2436 | && insn_uses_reg (ip, | |
2437 | ((prev_insn.insn_opcode | |
2438 | >> MIPS16OP_SH_RX) | |
2439 | & MIPS16OP_MASK_RX), | |
2440 | MIPS16_REG)) | |
2441 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2442 | && insn_uses_reg (ip, | |
2443 | ((prev_insn.insn_opcode | |
2444 | >> MIPS16OP_SH_RY) | |
2445 | & MIPS16OP_MASK_RY), | |
2446 | MIPS16_REG)) | |
2447 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2448 | && insn_uses_reg (ip, | |
2449 | ((prev_insn.insn_opcode | |
2450 | >> MIPS16OP_SH_RZ) | |
2451 | & MIPS16OP_MASK_RZ), | |
2452 | MIPS16_REG)) | |
2453 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2454 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2455 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2456 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2457 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2458 | && insn_uses_reg (ip, | |
2459 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2460 | insn_opcode), | |
2461 | MIPS_GR_REG)))) | |
2462 | /* If the branch writes a register that the previous | |
2463 | instruction sets, we can not swap (we know that | |
2464 | branches write only to RD or to $31). */ | |
2465 | || (! mips_opts.mips16 | |
2466 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2467 | && (((pinfo & INSN_WRITE_GPR_D) | |
2468 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2469 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2470 | || ((pinfo & INSN_WRITE_GPR_31) | |
2471 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2472 | & OP_MASK_RT) | |
f9419b05 | 2473 | == RA)))) |
252b5132 RH |
2474 | || (! mips_opts.mips16 |
2475 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2476 | && (((pinfo & INSN_WRITE_GPR_D) | |
2477 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2478 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2479 | || ((pinfo & INSN_WRITE_GPR_31) | |
2480 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2481 | & OP_MASK_RD) | |
f9419b05 | 2482 | == RA)))) |
252b5132 RH |
2483 | || (mips_opts.mips16 |
2484 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2485 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2486 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2487 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2488 | == RA)))) | |
2489 | /* If the branch writes a register that the previous | |
2490 | instruction reads, we can not swap (we know that | |
2491 | branches only write to RD or to $31). */ | |
2492 | || (! mips_opts.mips16 | |
2493 | && (pinfo & INSN_WRITE_GPR_D) | |
2494 | && insn_uses_reg (&prev_insn, | |
2495 | ((ip->insn_opcode >> OP_SH_RD) | |
2496 | & OP_MASK_RD), | |
2497 | MIPS_GR_REG)) | |
2498 | || (! mips_opts.mips16 | |
2499 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2500 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2501 | || (mips_opts.mips16 |
2502 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2503 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
252b5132 RH |
2504 | /* If the previous previous instruction has a load |
2505 | delay, and sets a register that the branch reads, we | |
2506 | can not swap. */ | |
2507 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2508 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2509 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2510 | && ! cop_interlocks) | |
2511 | || ((prev_prev_insn.insn_mo->pinfo | |
2512 | & INSN_LOAD_MEMORY_DELAY) | |
2513 | && ! gpr_interlocks)) | |
252b5132 RH |
2514 | && insn_uses_reg (ip, |
2515 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2516 | & OP_MASK_RT), | |
2517 | MIPS_GR_REG)) | |
2518 | /* If one instruction sets a condition code and the | |
2519 | other one uses a condition code, we can not swap. */ | |
2520 | || ((pinfo & INSN_READ_COND_CODE) | |
2521 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2522 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2523 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2524 | /* If the previous instruction uses the PC, we can not | |
2525 | swap. */ | |
2526 | || (mips_opts.mips16 | |
2527 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2528 | /* If the previous instruction was extended, we can not | |
2529 | swap. */ | |
2530 | || (mips_opts.mips16 && prev_insn_extended) | |
2531 | /* If the previous instruction had a fixup in mips16 | |
2532 | mode, we can not swap. This normally means that the | |
2533 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2534 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2535 | /* If the previous instruction is a sync, sync.l, or |
2536 | sync.p, we can not swap. */ | |
f173e82e | 2537 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2538 | { |
2539 | /* We could do even better for unconditional branches to | |
2540 | portions of this object file; we could pick up the | |
2541 | instruction at the destination, put it in the delay | |
2542 | slot, and bump the destination address. */ | |
2543 | emit_nop (); | |
2544 | /* Update the previous insn information. */ | |
2545 | prev_prev_insn = *ip; | |
2546 | prev_insn.insn_mo = &dummy_opcode; | |
2547 | } | |
2548 | else | |
2549 | { | |
2550 | /* It looks like we can actually do the swap. */ | |
2551 | if (! mips_opts.mips16) | |
2552 | { | |
2553 | char *prev_f; | |
2554 | char temp[4]; | |
2555 | ||
2556 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2557 | if (!relaxed_branch) |
2558 | { | |
2559 | /* If this is not a relaxed branch, then just | |
2560 | swap the instructions. */ | |
2561 | memcpy (temp, prev_f, 4); | |
2562 | memcpy (prev_f, f, 4); | |
2563 | memcpy (f, temp, 4); | |
2564 | } | |
2565 | else | |
2566 | { | |
2567 | /* If this is a relaxed branch, then we move the | |
2568 | instruction to be placed in the delay slot to | |
2569 | the current frag, shrinking the fixed part of | |
2570 | the originating frag. If the branch occupies | |
2571 | the tail of the latter, we move it backwards, | |
2572 | into the space freed by the moved instruction. */ | |
2573 | f = frag_more (4); | |
2574 | memcpy (f, prev_f, 4); | |
2575 | prev_insn_frag->fr_fix -= 4; | |
2576 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2577 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2578 | } | |
2579 | ||
f6688943 TS |
2580 | if (prev_insn_fixp[0]) |
2581 | { | |
2582 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2583 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2584 | } | |
2585 | if (prev_insn_fixp[1]) | |
2586 | { | |
2587 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2588 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2589 | } | |
2590 | if (prev_insn_fixp[2]) | |
252b5132 | 2591 | { |
f6688943 TS |
2592 | prev_insn_fixp[2]->fx_frag = frag_now; |
2593 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2594 | } |
f5040a92 AO |
2595 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2596 | && prev_insn_frag != frag_now | |
2597 | && (prev_insn_fixp[0]->fx_r_type | |
2598 | == BFD_RELOC_MIPS_GOT_DISP | |
2599 | || (prev_insn_fixp[0]->fx_r_type | |
2600 | == BFD_RELOC_MIPS_CALL16))) | |
2601 | { | |
2602 | /* To avoid confusion in tc_gen_reloc, we must | |
2603 | ensure that this does not become a variant | |
2604 | frag. */ | |
2605 | force_new_frag = TRUE; | |
2606 | } | |
895921c9 MR |
2607 | |
2608 | if (!relaxed_branch) | |
f6688943 | 2609 | { |
895921c9 MR |
2610 | if (fixp[0]) |
2611 | { | |
2612 | fixp[0]->fx_frag = prev_insn_frag; | |
2613 | fixp[0]->fx_where = prev_insn_where; | |
2614 | } | |
2615 | if (fixp[1]) | |
2616 | { | |
2617 | fixp[1]->fx_frag = prev_insn_frag; | |
2618 | fixp[1]->fx_where = prev_insn_where; | |
2619 | } | |
2620 | if (fixp[2]) | |
2621 | { | |
2622 | fixp[2]->fx_frag = prev_insn_frag; | |
2623 | fixp[2]->fx_where = prev_insn_where; | |
2624 | } | |
f6688943 | 2625 | } |
895921c9 | 2626 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2627 | { |
895921c9 MR |
2628 | if (fixp[0]) |
2629 | fixp[0]->fx_where -= 4; | |
2630 | if (fixp[1]) | |
2631 | fixp[1]->fx_where -= 4; | |
2632 | if (fixp[2]) | |
2633 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2634 | } |
2635 | } | |
2636 | else | |
2637 | { | |
2638 | char *prev_f; | |
2639 | char temp[2]; | |
2640 | ||
f6688943 TS |
2641 | assert (prev_insn_fixp[0] == NULL); |
2642 | assert (prev_insn_fixp[1] == NULL); | |
2643 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2644 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2645 | memcpy (temp, prev_f, 2); | |
2646 | memcpy (prev_f, f, 2); | |
f6688943 | 2647 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2648 | { |
f6688943 | 2649 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2650 | memcpy (f, temp, 2); |
2651 | } | |
2652 | else | |
2653 | { | |
2654 | memcpy (f, f + 2, 2); | |
2655 | memcpy (f + 2, temp, 2); | |
2656 | } | |
f6688943 TS |
2657 | if (fixp[0]) |
2658 | { | |
2659 | fixp[0]->fx_frag = prev_insn_frag; | |
2660 | fixp[0]->fx_where = prev_insn_where; | |
2661 | } | |
2662 | if (fixp[1]) | |
2663 | { | |
2664 | fixp[1]->fx_frag = prev_insn_frag; | |
2665 | fixp[1]->fx_where = prev_insn_where; | |
2666 | } | |
2667 | if (fixp[2]) | |
252b5132 | 2668 | { |
f6688943 TS |
2669 | fixp[2]->fx_frag = prev_insn_frag; |
2670 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2671 | } |
2672 | } | |
2673 | ||
2674 | /* Update the previous insn information; leave prev_insn | |
2675 | unchanged. */ | |
2676 | prev_prev_insn = *ip; | |
2677 | } | |
2678 | prev_insn_is_delay_slot = 1; | |
2679 | ||
2680 | /* If that was an unconditional branch, forget the previous | |
2681 | insn information. */ | |
2682 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2683 | { | |
2684 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2685 | prev_insn.insn_mo = &dummy_opcode; | |
2686 | } | |
2687 | ||
f6688943 TS |
2688 | prev_insn_fixp[0] = NULL; |
2689 | prev_insn_fixp[1] = NULL; | |
2690 | prev_insn_fixp[2] = NULL; | |
2691 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2692 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2693 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2694 | prev_insn_extended = 0; |
2695 | } | |
2696 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2697 | { | |
2698 | /* We don't yet optimize a branch likely. What we should do | |
2699 | is look at the target, copy the instruction found there | |
2700 | into the delay slot, and increment the branch to jump to | |
2701 | the next instruction. */ | |
2702 | emit_nop (); | |
2703 | /* Update the previous insn information. */ | |
2704 | prev_prev_insn = *ip; | |
2705 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2706 | prev_insn_fixp[0] = NULL; |
2707 | prev_insn_fixp[1] = NULL; | |
2708 | prev_insn_fixp[2] = NULL; | |
2709 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2710 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2711 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2712 | prev_insn_extended = 0; |
2713 | } | |
2714 | else | |
2715 | { | |
2716 | /* Update the previous insn information. */ | |
2717 | if (nops > 0) | |
2718 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2719 | else | |
2720 | prev_prev_insn = prev_insn; | |
2721 | prev_insn = *ip; | |
2722 | ||
2723 | /* Any time we see a branch, we always fill the delay slot | |
2724 | immediately; since this insn is not a branch, we know it | |
2725 | is not in a delay slot. */ | |
2726 | prev_insn_is_delay_slot = 0; | |
2727 | ||
f6688943 TS |
2728 | prev_insn_fixp[0] = fixp[0]; |
2729 | prev_insn_fixp[1] = fixp[1]; | |
2730 | prev_insn_fixp[2] = fixp[2]; | |
2731 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2732 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2733 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2734 | if (mips_opts.mips16) |
2735 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2736 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2737 | } |
2738 | ||
2739 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2740 | prev_insn_unreordered = 0; | |
2741 | prev_insn_frag = frag_now; | |
2742 | prev_insn_where = f - frag_now->fr_literal; | |
2743 | prev_insn_valid = 1; | |
2744 | } | |
4d7206a2 | 2745 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2746 | { |
2747 | /* We need to record a bit of information even when we are not | |
2748 | reordering, in order to determine the base address for mips16 | |
2749 | PC relative relocs. */ | |
2750 | prev_prev_insn = prev_insn; | |
2751 | prev_insn = *ip; | |
f6688943 TS |
2752 | prev_insn_reloc_type[0] = reloc_type[0]; |
2753 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2754 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2755 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2756 | prev_insn_unreordered = 1; | |
2757 | } | |
2758 | ||
2759 | /* We just output an insn, so the next one doesn't have a label. */ | |
2760 | mips_clear_insn_labels (); | |
252b5132 RH |
2761 | } |
2762 | ||
2763 | /* This function forgets that there was any previous instruction or | |
2764 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2765 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2766 | |
2767 | static void | |
17a2f251 | 2768 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2769 | { |
2770 | if (! preserve) | |
2771 | { | |
2772 | prev_insn.insn_mo = &dummy_opcode; | |
2773 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2774 | prev_nop_frag = NULL; | |
2775 | prev_nop_frag_holds = 0; | |
2776 | prev_nop_frag_required = 0; | |
2777 | prev_nop_frag_since = 0; | |
2778 | } | |
2779 | prev_insn_valid = 0; | |
2780 | prev_insn_is_delay_slot = 0; | |
2781 | prev_insn_unreordered = 0; | |
2782 | prev_insn_extended = 0; | |
f6688943 TS |
2783 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2784 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2785 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2786 | prev_prev_insn_unreordered = 0; |
2787 | mips_clear_insn_labels (); | |
2788 | } | |
2789 | ||
2790 | /* This function must be called whenever we turn on noreorder or emit | |
2791 | something other than instructions. It inserts any NOPS which might | |
2792 | be needed by the previous instruction, and clears the information | |
2793 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2794 | instructions are to follow. */ |
252b5132 RH |
2795 | |
2796 | static void | |
17a2f251 | 2797 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2798 | { |
2799 | if (! mips_opts.noreorder) | |
2800 | { | |
2801 | int nops; | |
2802 | ||
2803 | nops = 0; | |
2804 | if ((! mips_opts.mips16 | |
81912461 ILT |
2805 | && ((prev_insn.insn_mo->pinfo |
2806 | & (INSN_LOAD_COPROC_DELAY | |
2807 | | INSN_COPROC_MOVE_DELAY | |
2808 | | INSN_WRITE_COND_CODE)) | |
2809 | && ! cop_interlocks)) | |
252b5132 RH |
2810 | || (! hilo_interlocks |
2811 | && (prev_insn.insn_mo->pinfo | |
2812 | & (INSN_READ_LO | |
2813 | | INSN_READ_HI))) | |
2814 | || (! mips_opts.mips16 | |
81912461 ILT |
2815 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2816 | && ! gpr_interlocks) | |
252b5132 | 2817 | || (! mips_opts.mips16 |
81912461 ILT |
2818 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2819 | && ! cop_mem_interlocks)) | |
252b5132 | 2820 | { |
beae10d5 | 2821 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2822 | ++nops; |
2823 | if ((! mips_opts.mips16 | |
81912461 ILT |
2824 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2825 | && ! cop_interlocks)) | |
252b5132 RH |
2826 | || (! hilo_interlocks |
2827 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2828 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2829 | ++nops; | |
2830 | ||
2831 | if (prev_insn_unreordered) | |
2832 | nops = 0; | |
2833 | } | |
2834 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2835 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2836 | && ! cop_interlocks)) | |
252b5132 RH |
2837 | || (! hilo_interlocks |
2838 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2839 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2840 | { | |
beae10d5 | 2841 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2842 | if (! prev_prev_insn_unreordered) |
2843 | ++nops; | |
2844 | } | |
2845 | ||
d766e8ec | 2846 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2847 | { |
2848 | int min_nops = 0; | |
2849 | const char *pn = prev_insn.insn_mo->name; | |
532c738a RS |
2850 | if (strncmp (pn, "macc", 4) == 0 |
2851 | || strncmp (pn, "dmacc", 5) == 0 | |
2852 | || strncmp (pn, "dmult", 5) == 0 | |
2853 | || strstr (pn, "div")) | |
2854 | min_nops = 1; | |
60b63b72 RS |
2855 | if (nops < min_nops) |
2856 | nops = min_nops; | |
2857 | } | |
2858 | ||
252b5132 RH |
2859 | if (nops > 0) |
2860 | { | |
2861 | struct insn_label_list *l; | |
2862 | ||
2863 | if (insns) | |
2864 | { | |
2865 | /* Record the frag which holds the nop instructions, so | |
2866 | that we can remove them if we don't need them. */ | |
2867 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2868 | prev_nop_frag = frag_now; | |
2869 | prev_nop_frag_holds = nops; | |
2870 | prev_nop_frag_required = 0; | |
2871 | prev_nop_frag_since = 0; | |
2872 | } | |
2873 | ||
2874 | for (; nops > 0; --nops) | |
2875 | emit_nop (); | |
2876 | ||
2877 | if (insns) | |
2878 | { | |
2879 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2880 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2881 | frag_wane (frag_now); |
2882 | frag_new (0); | |
2883 | } | |
2884 | ||
2885 | for (l = insn_labels; l != NULL; l = l->next) | |
2886 | { | |
98aa84af AM |
2887 | valueT val; |
2888 | ||
252b5132 | 2889 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2890 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2891 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2892 | /* mips16 text labels are stored as odd. */ |
2893 | if (mips_opts.mips16) | |
f9419b05 | 2894 | ++val; |
98aa84af | 2895 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2896 | } |
2897 | } | |
2898 | } | |
2899 | ||
2900 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2901 | if (insns) |
252b5132 RH |
2902 | mips16_mark_labels (); |
2903 | ||
2904 | mips_no_prev_insn (insns); | |
2905 | } | |
2906 | ||
584892a6 RS |
2907 | /* Set up global variables for the start of a new macro. */ |
2908 | ||
2909 | static void | |
2910 | macro_start (void) | |
2911 | { | |
2912 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2913 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2914 | && (prev_insn.insn_mo->pinfo | |
2915 | & (INSN_UNCOND_BRANCH_DELAY | |
2916 | | INSN_COND_BRANCH_DELAY | |
2917 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2918 | } | |
2919 | ||
2920 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2921 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2922 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2923 | ||
2924 | static const char * | |
2925 | macro_warning (relax_substateT subtype) | |
2926 | { | |
2927 | if (subtype & RELAX_DELAY_SLOT) | |
2928 | return _("Macro instruction expanded into multiple instructions" | |
2929 | " in a branch delay slot"); | |
2930 | else if (subtype & RELAX_NOMACRO) | |
2931 | return _("Macro instruction expanded into multiple instructions"); | |
2932 | else | |
2933 | return 0; | |
2934 | } | |
2935 | ||
2936 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2937 | ||
2938 | static void | |
2939 | macro_end (void) | |
2940 | { | |
2941 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2942 | { | |
2943 | relax_substateT subtype; | |
2944 | ||
2945 | /* Set up the relaxation warning flags. */ | |
2946 | subtype = 0; | |
2947 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2948 | subtype |= RELAX_SECOND_LONGER; | |
2949 | if (mips_opts.warn_about_macros) | |
2950 | subtype |= RELAX_NOMACRO; | |
2951 | if (mips_macro_warning.delay_slot_p) | |
2952 | subtype |= RELAX_DELAY_SLOT; | |
2953 | ||
2954 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2955 | { | |
2956 | /* Either the macro has a single implementation or both | |
2957 | implementations are longer than 4 bytes. Emit the | |
2958 | warning now. */ | |
2959 | const char *msg = macro_warning (subtype); | |
2960 | if (msg != 0) | |
2961 | as_warn (msg); | |
2962 | } | |
2963 | else | |
2964 | { | |
2965 | /* One implementation might need a warning but the other | |
2966 | definitely doesn't. */ | |
2967 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2968 | } | |
2969 | } | |
2970 | } | |
2971 | ||
252b5132 RH |
2972 | /* Build an instruction created by a macro expansion. This is passed |
2973 | a pointer to the count of instructions created so far, an | |
2974 | expression, the name of the instruction to build, an operand format | |
2975 | string, and corresponding arguments. */ | |
2976 | ||
252b5132 | 2977 | static void |
67c0d1eb | 2978 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
2979 | { |
2980 | struct mips_cl_insn insn; | |
f6688943 | 2981 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2982 | va_list args; |
252b5132 | 2983 | |
252b5132 | 2984 | va_start (args, fmt); |
252b5132 | 2985 | |
252b5132 RH |
2986 | if (mips_opts.mips16) |
2987 | { | |
67c0d1eb | 2988 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2989 | va_end (args); |
2990 | return; | |
2991 | } | |
2992 | ||
f6688943 TS |
2993 | r[0] = BFD_RELOC_UNUSED; |
2994 | r[1] = BFD_RELOC_UNUSED; | |
2995 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2996 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2997 | assert (insn.insn_mo); | |
2998 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2999 | ||
3000 | /* Search until we get a match for NAME. */ | |
3001 | while (1) | |
3002 | { | |
b34976b6 | 3003 | /* It is assumed here that macros will never generate |
deec1734 | 3004 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3005 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3006 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3007 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3008 | (mips_opts.isa | |
3396de36 | 3009 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3010 | mips_opts.arch) |
3011 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3012 | break; |
3013 | ||
3014 | ++insn.insn_mo; | |
3015 | assert (insn.insn_mo->name); | |
3016 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3017 | } | |
3018 | ||
3019 | insn.insn_opcode = insn.insn_mo->match; | |
3020 | for (;;) | |
3021 | { | |
3022 | switch (*fmt++) | |
3023 | { | |
3024 | case '\0': | |
3025 | break; | |
3026 | ||
3027 | case ',': | |
3028 | case '(': | |
3029 | case ')': | |
3030 | continue; | |
3031 | ||
5f74bc13 CD |
3032 | case '+': |
3033 | switch (*fmt++) | |
3034 | { | |
3035 | case 'A': | |
3036 | case 'E': | |
3037 | insn.insn_opcode |= (va_arg (args, int) | |
3038 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3039 | continue; | |
3040 | ||
3041 | case 'B': | |
3042 | case 'F': | |
3043 | /* Note that in the macro case, these arguments are already | |
3044 | in MSB form. (When handling the instruction in the | |
3045 | non-macro case, these arguments are sizes from which | |
3046 | MSB values must be calculated.) */ | |
3047 | insn.insn_opcode |= (va_arg (args, int) | |
3048 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3049 | continue; | |
3050 | ||
3051 | case 'C': | |
3052 | case 'G': | |
3053 | case 'H': | |
3054 | /* Note that in the macro case, these arguments are already | |
3055 | in MSBD form. (When handling the instruction in the | |
3056 | non-macro case, these arguments are sizes from which | |
3057 | MSBD values must be calculated.) */ | |
3058 | insn.insn_opcode |= (va_arg (args, int) | |
3059 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3060 | continue; | |
3061 | ||
3062 | default: | |
3063 | internalError (); | |
3064 | } | |
3065 | continue; | |
3066 | ||
252b5132 RH |
3067 | case 't': |
3068 | case 'w': | |
3069 | case 'E': | |
38487616 | 3070 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3071 | continue; |
3072 | ||
3073 | case 'c': | |
38487616 TS |
3074 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3075 | continue; | |
3076 | ||
252b5132 RH |
3077 | case 'T': |
3078 | case 'W': | |
38487616 | 3079 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3080 | continue; |
3081 | ||
3082 | case 'd': | |
3083 | case 'G': | |
af7ee8bf | 3084 | case 'K': |
38487616 | 3085 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3086 | continue; |
3087 | ||
4372b673 NC |
3088 | case 'U': |
3089 | { | |
3090 | int tmp = va_arg (args, int); | |
3091 | ||
38487616 TS |
3092 | insn.insn_opcode |= tmp << OP_SH_RT; |
3093 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3094 | continue; |
4372b673 NC |
3095 | } |
3096 | ||
252b5132 RH |
3097 | case 'V': |
3098 | case 'S': | |
38487616 | 3099 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3100 | continue; |
3101 | ||
3102 | case 'z': | |
3103 | continue; | |
3104 | ||
3105 | case '<': | |
38487616 | 3106 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3107 | continue; |
3108 | ||
3109 | case 'D': | |
38487616 | 3110 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3111 | continue; |
3112 | ||
3113 | case 'B': | |
38487616 | 3114 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3115 | continue; |
3116 | ||
4372b673 | 3117 | case 'J': |
38487616 | 3118 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3119 | continue; |
3120 | ||
252b5132 | 3121 | case 'q': |
38487616 | 3122 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3123 | continue; |
3124 | ||
3125 | case 'b': | |
3126 | case 's': | |
3127 | case 'r': | |
3128 | case 'v': | |
38487616 | 3129 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3130 | continue; |
3131 | ||
3132 | case 'i': | |
3133 | case 'j': | |
3134 | case 'o': | |
f6688943 | 3135 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3136 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3137 | || *r == BFD_RELOC_MIPS_LITERAL |
3138 | || *r == BFD_RELOC_MIPS_HIGHER | |
3139 | || *r == BFD_RELOC_HI16_S | |
3140 | || *r == BFD_RELOC_LO16 | |
3141 | || *r == BFD_RELOC_MIPS_GOT16 | |
3142 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3143 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3144 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3145 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3146 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3147 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3148 | continue; |
3149 | ||
3150 | case 'u': | |
f6688943 | 3151 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3152 | assert (ep != NULL |
3153 | && (ep->X_op == O_constant | |
3154 | || (ep->X_op == O_symbol | |
f6688943 TS |
3155 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3156 | || *r == BFD_RELOC_HI16_S | |
3157 | || *r == BFD_RELOC_HI16 | |
3158 | || *r == BFD_RELOC_GPREL16 | |
3159 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3160 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3161 | continue; |
3162 | ||
3163 | case 'p': | |
3164 | assert (ep != NULL); | |
3165 | /* | |
3166 | * This allows macro() to pass an immediate expression for | |
3167 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3168 | * Note that the expression still might come from the assembly |
3169 | * input, in which case the value is not checked for range nor | |
3170 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3171 | */ |
3172 | if (ep->X_op == O_constant) | |
3173 | { | |
3174 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3175 | ep = NULL; | |
3176 | } | |
3177 | else | |
0b25d3e6 | 3178 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3179 | continue; |
3180 | ||
3181 | case 'a': | |
3182 | assert (ep != NULL); | |
f6688943 | 3183 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3184 | continue; |
3185 | ||
3186 | case 'C': | |
3187 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3188 | continue; | |
3189 | ||
3190 | default: | |
3191 | internalError (); | |
3192 | } | |
3193 | break; | |
3194 | } | |
3195 | va_end (args); | |
f6688943 | 3196 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3197 | |
4d7206a2 | 3198 | append_insn (&insn, ep, r); |
252b5132 RH |
3199 | } |
3200 | ||
3201 | static void | |
67c0d1eb | 3202 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3203 | va_list args) |
252b5132 RH |
3204 | { |
3205 | struct mips_cl_insn insn; | |
f6688943 TS |
3206 | bfd_reloc_code_real_type r[3] |
3207 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3208 | |
252b5132 RH |
3209 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3210 | assert (insn.insn_mo); | |
3211 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3212 | ||
3213 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3214 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3215 | { | |
3216 | ++insn.insn_mo; | |
3217 | assert (insn.insn_mo->name); | |
3218 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3219 | } | |
3220 | ||
3221 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3222 | insn.use_extend = FALSE; |
252b5132 RH |
3223 | |
3224 | for (;;) | |
3225 | { | |
3226 | int c; | |
3227 | ||
3228 | c = *fmt++; | |
3229 | switch (c) | |
3230 | { | |
3231 | case '\0': | |
3232 | break; | |
3233 | ||
3234 | case ',': | |
3235 | case '(': | |
3236 | case ')': | |
3237 | continue; | |
3238 | ||
3239 | case 'y': | |
3240 | case 'w': | |
3241 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3242 | continue; | |
3243 | ||
3244 | case 'x': | |
3245 | case 'v': | |
3246 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3247 | continue; | |
3248 | ||
3249 | case 'z': | |
3250 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3251 | continue; | |
3252 | ||
3253 | case 'Z': | |
3254 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3255 | continue; | |
3256 | ||
3257 | case '0': | |
3258 | case 'S': | |
3259 | case 'P': | |
3260 | case 'R': | |
3261 | continue; | |
3262 | ||
3263 | case 'X': | |
3264 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3265 | continue; | |
3266 | ||
3267 | case 'Y': | |
3268 | { | |
3269 | int regno; | |
3270 | ||
3271 | regno = va_arg (args, int); | |
3272 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3273 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3274 | } | |
3275 | continue; | |
3276 | ||
3277 | case '<': | |
3278 | case '>': | |
3279 | case '4': | |
3280 | case '5': | |
3281 | case 'H': | |
3282 | case 'W': | |
3283 | case 'D': | |
3284 | case 'j': | |
3285 | case '8': | |
3286 | case 'V': | |
3287 | case 'C': | |
3288 | case 'U': | |
3289 | case 'k': | |
3290 | case 'K': | |
3291 | case 'p': | |
3292 | case 'q': | |
3293 | { | |
3294 | assert (ep != NULL); | |
3295 | ||
3296 | if (ep->X_op != O_constant) | |
874e8986 | 3297 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3298 | else |
3299 | { | |
b34976b6 AM |
3300 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3301 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3302 | &insn.extend); |
252b5132 | 3303 | ep = NULL; |
f6688943 | 3304 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3305 | } |
3306 | } | |
3307 | continue; | |
3308 | ||
3309 | case '6': | |
3310 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3311 | continue; | |
3312 | } | |
3313 | ||
3314 | break; | |
3315 | } | |
3316 | ||
f6688943 | 3317 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3318 | |
4d7206a2 | 3319 | append_insn (&insn, ep, r); |
252b5132 RH |
3320 | } |
3321 | ||
438c16b8 TS |
3322 | /* |
3323 | * Generate a "jalr" instruction with a relocation hint to the called | |
3324 | * function. This occurs in NewABI PIC code. | |
3325 | */ | |
3326 | static void | |
67c0d1eb | 3327 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3328 | { |
685736be | 3329 | char *f = NULL; |
b34976b6 | 3330 | |
438c16b8 | 3331 | if (HAVE_NEWABI) |
f21f8242 | 3332 | { |
cc3d92a5 | 3333 | frag_grow (8); |
f21f8242 AO |
3334 | f = frag_more (0); |
3335 | } | |
67c0d1eb | 3336 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3337 | if (HAVE_NEWABI) |
f21f8242 | 3338 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3339 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3340 | } |
3341 | ||
252b5132 RH |
3342 | /* |
3343 | * Generate a "lui" instruction. | |
3344 | */ | |
3345 | static void | |
67c0d1eb | 3346 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3347 | { |
3348 | expressionS high_expr; | |
3349 | struct mips_cl_insn insn; | |
f6688943 TS |
3350 | bfd_reloc_code_real_type r[3] |
3351 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3352 | const char *name = "lui"; |
3353 | const char *fmt = "t,u"; | |
252b5132 RH |
3354 | |
3355 | assert (! mips_opts.mips16); | |
3356 | ||
4d7206a2 | 3357 | high_expr = *ep; |
252b5132 RH |
3358 | |
3359 | if (high_expr.X_op == O_constant) | |
3360 | { | |
3361 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3362 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3363 | >> 16) & 0xffff; | |
f6688943 | 3364 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3365 | } |
78e1bb40 | 3366 | else |
252b5132 RH |
3367 | { |
3368 | assert (ep->X_op == O_symbol); | |
3369 | /* _gp_disp is a special case, used from s_cpload. */ | |
3370 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3371 | || (! HAVE_NEWABI |
3372 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3373 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3374 | } |
3375 | ||
252b5132 RH |
3376 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3377 | assert (insn.insn_mo); | |
3378 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3379 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3380 | ||
3381 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3382 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3383 | { |
3384 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3385 | append_insn (&insn, NULL, r); |
252b5132 RH |
3386 | } |
3387 | else | |
4d7206a2 | 3388 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3389 | } |
3390 | ||
885add95 CD |
3391 | /* Generate a sequence of instructions to do a load or store from a constant |
3392 | offset off of a base register (breg) into/from a target register (treg), | |
3393 | using AT if necessary. */ | |
3394 | static void | |
67c0d1eb RS |
3395 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3396 | int treg, int breg, int dbl) | |
885add95 CD |
3397 | { |
3398 | assert (ep->X_op == O_constant); | |
3399 | ||
256ab948 | 3400 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3401 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3402 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3403 | { |
d17e7bce | 3404 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3405 | as_bad (_("constant too large")); |
ae826530 | 3406 | |
1b8e29e5 TS |
3407 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3408 | - 0x80000000); | |
ae826530 | 3409 | } |
256ab948 | 3410 | |
67c1ffbe | 3411 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3412 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3413 | as_warn (_("operand overflow")); |
3414 | ||
3415 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3416 | { | |
3417 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3418 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3419 | } |
3420 | else | |
3421 | { | |
3422 | /* 32-bit offset, need multiple instructions and AT, like: | |
3423 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3424 | addu $tempreg,$tempreg,$breg | |
3425 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3426 | to handle the complete offset. */ | |
67c0d1eb RS |
3427 | macro_build_lui (ep, AT); |
3428 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3429 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3430 | |
3431 | if (mips_opts.noat) | |
3432 | as_warn (_("Macro used $at after \".set noat\"")); | |
3433 | } | |
3434 | } | |
3435 | ||
252b5132 RH |
3436 | /* set_at() |
3437 | * Generates code to set the $at register to true (one) | |
3438 | * if reg is less than the immediate expression. | |
3439 | */ | |
3440 | static void | |
67c0d1eb | 3441 | set_at (int reg, int unsignedp) |
252b5132 RH |
3442 | { |
3443 | if (imm_expr.X_op == O_constant | |
3444 | && imm_expr.X_add_number >= -0x8000 | |
3445 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3446 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3447 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3448 | else |
3449 | { | |
67c0d1eb RS |
3450 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3451 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3452 | } |
3453 | } | |
3454 | ||
13757d0c TS |
3455 | static void |
3456 | normalize_constant_expr (expressionS *ex) | |
3457 | { | |
3458 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3459 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3460 | - 0x80000000); | |
3461 | } | |
3462 | ||
252b5132 RH |
3463 | /* Warn if an expression is not a constant. */ |
3464 | ||
3465 | static void | |
17a2f251 | 3466 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3467 | { |
3468 | if (ex->X_op == O_big) | |
3469 | as_bad (_("unsupported large constant")); | |
3470 | else if (ex->X_op != O_constant) | |
3471 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3472 | |
3473 | normalize_constant_expr (ex); | |
252b5132 RH |
3474 | } |
3475 | ||
3476 | /* Count the leading zeroes by performing a binary chop. This is a | |
3477 | bulky bit of source, but performance is a LOT better for the | |
3478 | majority of values than a simple loop to count the bits: | |
3479 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3480 | if ((v) & (1 << (31 - lcnt))) | |
3481 | break; | |
3482 | However it is not code size friendly, and the gain will drop a bit | |
3483 | on certain cached systems. | |
3484 | */ | |
3485 | #define COUNT_TOP_ZEROES(v) \ | |
3486 | (((v) & ~0xffff) == 0 \ | |
3487 | ? ((v) & ~0xff) == 0 \ | |
3488 | ? ((v) & ~0xf) == 0 \ | |
3489 | ? ((v) & ~0x3) == 0 \ | |
3490 | ? ((v) & ~0x1) == 0 \ | |
3491 | ? !(v) \ | |
3492 | ? 32 \ | |
3493 | : 31 \ | |
3494 | : 30 \ | |
3495 | : ((v) & ~0x7) == 0 \ | |
3496 | ? 29 \ | |
3497 | : 28 \ | |
3498 | : ((v) & ~0x3f) == 0 \ | |
3499 | ? ((v) & ~0x1f) == 0 \ | |
3500 | ? 27 \ | |
3501 | : 26 \ | |
3502 | : ((v) & ~0x7f) == 0 \ | |
3503 | ? 25 \ | |
3504 | : 24 \ | |
3505 | : ((v) & ~0xfff) == 0 \ | |
3506 | ? ((v) & ~0x3ff) == 0 \ | |
3507 | ? ((v) & ~0x1ff) == 0 \ | |
3508 | ? 23 \ | |
3509 | : 22 \ | |
3510 | : ((v) & ~0x7ff) == 0 \ | |
3511 | ? 21 \ | |
3512 | : 20 \ | |
3513 | : ((v) & ~0x3fff) == 0 \ | |
3514 | ? ((v) & ~0x1fff) == 0 \ | |
3515 | ? 19 \ | |
3516 | : 18 \ | |
3517 | : ((v) & ~0x7fff) == 0 \ | |
3518 | ? 17 \ | |
3519 | : 16 \ | |
3520 | : ((v) & ~0xffffff) == 0 \ | |
3521 | ? ((v) & ~0xfffff) == 0 \ | |
3522 | ? ((v) & ~0x3ffff) == 0 \ | |
3523 | ? ((v) & ~0x1ffff) == 0 \ | |
3524 | ? 15 \ | |
3525 | : 14 \ | |
3526 | : ((v) & ~0x7ffff) == 0 \ | |
3527 | ? 13 \ | |
3528 | : 12 \ | |
3529 | : ((v) & ~0x3fffff) == 0 \ | |
3530 | ? ((v) & ~0x1fffff) == 0 \ | |
3531 | ? 11 \ | |
3532 | : 10 \ | |
3533 | : ((v) & ~0x7fffff) == 0 \ | |
3534 | ? 9 \ | |
3535 | : 8 \ | |
3536 | : ((v) & ~0xfffffff) == 0 \ | |
3537 | ? ((v) & ~0x3ffffff) == 0 \ | |
3538 | ? ((v) & ~0x1ffffff) == 0 \ | |
3539 | ? 7 \ | |
3540 | : 6 \ | |
3541 | : ((v) & ~0x7ffffff) == 0 \ | |
3542 | ? 5 \ | |
3543 | : 4 \ | |
3544 | : ((v) & ~0x3fffffff) == 0 \ | |
3545 | ? ((v) & ~0x1fffffff) == 0 \ | |
3546 | ? 3 \ | |
3547 | : 2 \ | |
3548 | : ((v) & ~0x7fffffff) == 0 \ | |
3549 | ? 1 \ | |
3550 | : 0) | |
3551 | ||
3552 | /* load_register() | |
67c1ffbe | 3553 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3554 | * an absolute expression value into a register. |
3555 | */ | |
3556 | static void | |
67c0d1eb | 3557 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3558 | { |
3559 | int freg; | |
3560 | expressionS hi32, lo32; | |
3561 | ||
3562 | if (ep->X_op != O_big) | |
3563 | { | |
3564 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3565 | |
3566 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3567 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3568 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3569 | { |
d17e7bce | 3570 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3571 | as_bad (_("constant too large")); |
ae826530 | 3572 | |
1b8e29e5 TS |
3573 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3574 | - 0x80000000); | |
ae826530 | 3575 | } |
256ab948 TS |
3576 | |
3577 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3578 | { |
3579 | /* We can handle 16 bit signed values with an addiu to | |
3580 | $zero. No need to ever use daddiu here, since $zero and | |
3581 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3582 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3583 | return; |
3584 | } | |
3585 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3586 | { | |
3587 | /* We can handle 16 bit unsigned values with an ori to | |
3588 | $zero. */ | |
67c0d1eb | 3589 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3590 | return; |
3591 | } | |
256ab948 | 3592 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3593 | { |
3594 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3595 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3596 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3597 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3598 | return; |
3599 | } | |
3600 | } | |
3601 | ||
3602 | /* The value is larger than 32 bits. */ | |
3603 | ||
ca4e0257 | 3604 | if (HAVE_32BIT_GPRS) |
252b5132 | 3605 | { |
956cd1d6 TS |
3606 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3607 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3608 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3609 | return; |
3610 | } | |
3611 | ||
3612 | if (ep->X_op != O_big) | |
3613 | { | |
3614 | hi32 = *ep; | |
3615 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3616 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3617 | hi32.X_add_number &= 0xffffffff; | |
3618 | lo32 = *ep; | |
3619 | lo32.X_add_number &= 0xffffffff; | |
3620 | } | |
3621 | else | |
3622 | { | |
3623 | assert (ep->X_add_number > 2); | |
3624 | if (ep->X_add_number == 3) | |
3625 | generic_bignum[3] = 0; | |
3626 | else if (ep->X_add_number > 4) | |
3627 | as_bad (_("Number larger than 64 bits")); | |
3628 | lo32.X_op = O_constant; | |
3629 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3630 | hi32.X_op = O_constant; | |
3631 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3632 | } | |
3633 | ||
3634 | if (hi32.X_add_number == 0) | |
3635 | freg = 0; | |
3636 | else | |
3637 | { | |
3638 | int shift, bit; | |
3639 | unsigned long hi, lo; | |
3640 | ||
956cd1d6 | 3641 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3642 | { |
3643 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3644 | { | |
67c0d1eb | 3645 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3646 | return; |
3647 | } | |
3648 | if (lo32.X_add_number & 0x80000000) | |
3649 | { | |
67c0d1eb | 3650 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3651 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3652 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3653 | return; |
3654 | } | |
3655 | } | |
252b5132 RH |
3656 | |
3657 | /* Check for 16bit shifted constant. We know that hi32 is | |
3658 | non-zero, so start the mask on the first bit of the hi32 | |
3659 | value. */ | |
3660 | shift = 17; | |
3661 | do | |
beae10d5 KH |
3662 | { |
3663 | unsigned long himask, lomask; | |
3664 | ||
3665 | if (shift < 32) | |
3666 | { | |
3667 | himask = 0xffff >> (32 - shift); | |
3668 | lomask = (0xffff << shift) & 0xffffffff; | |
3669 | } | |
3670 | else | |
3671 | { | |
3672 | himask = 0xffff << (shift - 32); | |
3673 | lomask = 0; | |
3674 | } | |
3675 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3676 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3677 | { | |
3678 | expressionS tmp; | |
3679 | ||
3680 | tmp.X_op = O_constant; | |
3681 | if (shift < 32) | |
3682 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3683 | | (lo32.X_add_number >> shift)); | |
3684 | else | |
3685 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3686 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3687 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3688 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3689 | return; |
3690 | } | |
f9419b05 | 3691 | ++shift; |
beae10d5 KH |
3692 | } |
3693 | while (shift <= (64 - 16)); | |
252b5132 RH |
3694 | |
3695 | /* Find the bit number of the lowest one bit, and store the | |
3696 | shifted value in hi/lo. */ | |
3697 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3698 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3699 | if (lo != 0) | |
3700 | { | |
3701 | bit = 0; | |
3702 | while ((lo & 1) == 0) | |
3703 | { | |
3704 | lo >>= 1; | |
3705 | ++bit; | |
3706 | } | |
3707 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3708 | hi >>= bit; | |
3709 | } | |
3710 | else | |
3711 | { | |
3712 | bit = 32; | |
3713 | while ((hi & 1) == 0) | |
3714 | { | |
3715 | hi >>= 1; | |
3716 | ++bit; | |
3717 | } | |
3718 | lo = hi; | |
3719 | hi = 0; | |
3720 | } | |
3721 | ||
3722 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3723 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3724 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3725 | { |
3726 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3727 | if (shift != 0) |
beae10d5 | 3728 | { |
252b5132 RH |
3729 | expressionS tmp; |
3730 | ||
3731 | /* This instruction will set the register to be all | |
3732 | ones. */ | |
beae10d5 KH |
3733 | tmp.X_op = O_constant; |
3734 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3735 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3736 | if (bit != 0) |
3737 | { | |
3738 | bit += shift; | |
67c0d1eb RS |
3739 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3740 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3741 | } |
67c0d1eb RS |
3742 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3743 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3744 | return; |
3745 | } | |
3746 | } | |
252b5132 RH |
3747 | |
3748 | /* Sign extend hi32 before calling load_register, because we can | |
3749 | generally get better code when we load a sign extended value. */ | |
3750 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3751 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3752 | load_register (reg, &hi32, 0); |
252b5132 RH |
3753 | freg = reg; |
3754 | } | |
3755 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3756 | { | |
3757 | if (freg != 0) | |
3758 | { | |
67c0d1eb | 3759 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3760 | freg = reg; |
3761 | } | |
3762 | } | |
3763 | else | |
3764 | { | |
3765 | expressionS mid16; | |
3766 | ||
956cd1d6 | 3767 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3768 | { |
67c0d1eb RS |
3769 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3770 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3771 | return; |
3772 | } | |
252b5132 RH |
3773 | |
3774 | if (freg != 0) | |
3775 | { | |
67c0d1eb | 3776 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3777 | freg = reg; |
3778 | } | |
3779 | mid16 = lo32; | |
3780 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3781 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3782 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3783 | freg = reg; |
3784 | } | |
3785 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3786 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3787 | } |
3788 | ||
269137b2 TS |
3789 | static inline void |
3790 | load_delay_nop (void) | |
3791 | { | |
3792 | if (!gpr_interlocks) | |
3793 | macro_build (NULL, "nop", ""); | |
3794 | } | |
3795 | ||
252b5132 RH |
3796 | /* Load an address into a register. */ |
3797 | ||
3798 | static void | |
67c0d1eb | 3799 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3800 | { |
252b5132 RH |
3801 | if (ep->X_op != O_constant |
3802 | && ep->X_op != O_symbol) | |
3803 | { | |
3804 | as_bad (_("expression too complex")); | |
3805 | ep->X_op = O_constant; | |
3806 | } | |
3807 | ||
3808 | if (ep->X_op == O_constant) | |
3809 | { | |
67c0d1eb | 3810 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3811 | return; |
3812 | } | |
3813 | ||
3814 | if (mips_pic == NO_PIC) | |
3815 | { | |
3816 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3817 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3818 | Otherwise we want |
3819 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3820 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3821 | If we have an addend, we always use the latter form. |
76b3015f | 3822 | |
d6bc6245 TS |
3823 | With 64bit address space and a usable $at we want |
3824 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3825 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3826 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3827 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3828 | dsll32 $reg,0 | |
3a482fd5 | 3829 | daddu $reg,$reg,$at |
76b3015f | 3830 | |
c03099e6 | 3831 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3832 | on superscalar processors. |
3833 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3834 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3835 | dsll $reg,16 | |
3836 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3837 | dsll $reg,16 | |
3838 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3839 | */ | |
c9914766 | 3840 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3841 | { |
e864ceca RS |
3842 | /* ??? We don't provide a GP-relative alternative for these macros. |
3843 | It used not to be possible with the original relaxation code, | |
3844 | but it could be done now. */ | |
d6bc6245 | 3845 | |
460597ba | 3846 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 3847 | { |
67c0d1eb RS |
3848 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3849 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3850 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3851 | BFD_RELOC_MIPS_HIGHER); | |
3852 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3853 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3854 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3855 | *used_at = 1; |
3856 | } | |
3857 | else | |
3858 | { | |
67c0d1eb RS |
3859 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3860 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3861 | BFD_RELOC_MIPS_HIGHER); | |
3862 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3863 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3864 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3865 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3866 | } |
3867 | } | |
252b5132 RH |
3868 | else |
3869 | { | |
d6bc6245 TS |
3870 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3871 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3872 | { | |
4d7206a2 | 3873 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3874 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3875 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3876 | relax_switch (); |
d6bc6245 | 3877 | } |
67c0d1eb RS |
3878 | macro_build_lui (ep, reg); |
3879 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3880 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3881 | if (mips_relax.sequence) |
3882 | relax_end (); | |
d6bc6245 | 3883 | } |
252b5132 RH |
3884 | } |
3885 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3886 | { | |
3887 | expressionS ex; | |
3888 | ||
3889 | /* If this is a reference to an external symbol, we want | |
3890 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3891 | Otherwise we want | |
3892 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3893 | nop | |
3894 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3895 | If there is a constant, it must be added in after. |
3896 | ||
ed6fb7bd | 3897 | If we have NewABI, we want |
f5040a92 AO |
3898 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3899 | unless we're referencing a global symbol with a non-zero | |
3900 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3901 | if (HAVE_NEWABI) |
3902 | { | |
f5040a92 AO |
3903 | if (ep->X_add_number) |
3904 | { | |
4d7206a2 | 3905 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3906 | ep->X_add_number = 0; |
4d7206a2 | 3907 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3908 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3909 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3910 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3911 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3912 | ex.X_op = O_constant; | |
67c0d1eb | 3913 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3914 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3915 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3916 | relax_switch (); |
f5040a92 | 3917 | } |
67c0d1eb | 3918 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3919 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3920 | if (mips_relax.sequence) |
3921 | relax_end (); | |
ed6fb7bd SC |
3922 | } |
3923 | else | |
3924 | { | |
f5040a92 AO |
3925 | ex.X_add_number = ep->X_add_number; |
3926 | ep->X_add_number = 0; | |
67c0d1eb RS |
3927 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3928 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3929 | load_delay_nop (); |
4d7206a2 RS |
3930 | relax_start (ep->X_add_symbol); |
3931 | relax_switch (); | |
67c0d1eb | 3932 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3933 | BFD_RELOC_LO16); |
4d7206a2 | 3934 | relax_end (); |
ed6fb7bd | 3935 | |
f5040a92 AO |
3936 | if (ex.X_add_number != 0) |
3937 | { | |
3938 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3939 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3940 | ex.X_op = O_constant; | |
67c0d1eb | 3941 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3942 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3943 | } |
252b5132 RH |
3944 | } |
3945 | } | |
3946 | else if (mips_pic == SVR4_PIC) | |
3947 | { | |
3948 | expressionS ex; | |
252b5132 RH |
3949 | |
3950 | /* This is the large GOT case. If this is a reference to an | |
3951 | external symbol, we want | |
3952 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3953 | addu $reg,$reg,$gp | |
3954 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3955 | |
3956 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3957 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3958 | nop | |
3959 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3960 | If there is a constant, it must be added in after. |
f5040a92 AO |
3961 | |
3962 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3963 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3964 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3965 | */ |
438c16b8 TS |
3966 | if (HAVE_NEWABI) |
3967 | { | |
4d7206a2 | 3968 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3969 | ep->X_add_number = 0; |
4d7206a2 | 3970 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3971 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3972 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3973 | reg, reg, mips_gp_register); | |
3974 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3975 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3976 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3977 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3978 | else if (ex.X_add_number) | |
3979 | { | |
3980 | ex.X_op = O_constant; | |
67c0d1eb RS |
3981 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3982 | BFD_RELOC_LO16); | |
f5040a92 AO |
3983 | } |
3984 | ||
3985 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3986 | relax_switch (); |
67c0d1eb | 3987 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3988 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3989 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3990 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3991 | relax_end (); |
438c16b8 | 3992 | } |
252b5132 | 3993 | else |
438c16b8 | 3994 | { |
f5040a92 AO |
3995 | ex.X_add_number = ep->X_add_number; |
3996 | ep->X_add_number = 0; | |
4d7206a2 | 3997 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3998 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3999 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4000 | reg, reg, mips_gp_register); | |
4001 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4002 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4003 | relax_switch (); |
4004 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4005 | { |
4006 | /* We need a nop before loading from $gp. This special | |
4007 | check is required because the lui which starts the main | |
4008 | instruction stream does not refer to $gp, and so will not | |
4009 | insert the nop which may be required. */ | |
67c0d1eb | 4010 | macro_build (NULL, "nop", ""); |
438c16b8 | 4011 | } |
67c0d1eb | 4012 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4013 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4014 | load_delay_nop (); |
67c0d1eb | 4015 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4016 | BFD_RELOC_LO16); |
4d7206a2 | 4017 | relax_end (); |
438c16b8 | 4018 | |
f5040a92 AO |
4019 | if (ex.X_add_number != 0) |
4020 | { | |
4021 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4022 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4023 | ex.X_op = O_constant; | |
67c0d1eb RS |
4024 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4025 | BFD_RELOC_LO16); | |
f5040a92 | 4026 | } |
252b5132 RH |
4027 | } |
4028 | } | |
252b5132 RH |
4029 | else |
4030 | abort (); | |
4031 | } | |
4032 | ||
ea1fb5dc RS |
4033 | /* Move the contents of register SOURCE into register DEST. */ |
4034 | ||
4035 | static void | |
67c0d1eb | 4036 | move_register (int dest, int source) |
ea1fb5dc | 4037 | { |
67c0d1eb RS |
4038 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4039 | dest, source, 0); | |
ea1fb5dc RS |
4040 | } |
4041 | ||
4d7206a2 | 4042 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4043 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4044 | The two alternatives are: | |
4d7206a2 RS |
4045 | |
4046 | Global symbol Local sybmol | |
4047 | ------------- ------------ | |
4048 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4049 | ... ... | |
4050 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4051 | ||
4052 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4053 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4054 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4055 | |
4056 | static void | |
67c0d1eb | 4057 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4058 | { |
4059 | expressionS global; | |
4060 | ||
4061 | global = *local; | |
4062 | global.X_add_number = 0; | |
4063 | ||
4064 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4065 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4066 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4067 | relax_switch (); |
67c0d1eb RS |
4068 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4069 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4070 | relax_end (); |
4071 | } | |
4072 | ||
4073 | static void | |
67c0d1eb | 4074 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4075 | { |
4076 | expressionS global; | |
4077 | ||
4078 | global.X_op = O_constant; | |
4079 | global.X_op_symbol = NULL; | |
4080 | global.X_add_symbol = NULL; | |
4081 | global.X_add_number = local->X_add_number; | |
4082 | ||
4083 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4084 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4085 | dest, dest, BFD_RELOC_LO16); |
4086 | relax_switch (); | |
67c0d1eb | 4087 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4088 | relax_end (); |
4089 | } | |
4090 | ||
f6a22291 MR |
4091 | static void |
4092 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4093 | { | |
4094 | expressionS global; | |
4095 | int hold_mips_optimize; | |
4096 | ||
4097 | global.X_op = O_constant; | |
4098 | global.X_op_symbol = NULL; | |
4099 | global.X_add_symbol = NULL; | |
4100 | global.X_add_number = local->X_add_number; | |
4101 | ||
4102 | relax_start (local->X_add_symbol); | |
4103 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4104 | relax_switch (); | |
4105 | /* Set mips_optimize around the lui instruction to avoid | |
4106 | inserting an unnecessary nop after the lw. */ | |
4107 | hold_mips_optimize = mips_optimize; | |
4108 | mips_optimize = 2; | |
4109 | macro_build_lui (&global, tmp); | |
4110 | mips_optimize = hold_mips_optimize; | |
4111 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4112 | relax_end (); | |
4113 | ||
4114 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4115 | } | |
4116 | ||
252b5132 RH |
4117 | /* |
4118 | * Build macros | |
4119 | * This routine implements the seemingly endless macro or synthesized | |
4120 | * instructions and addressing modes in the mips assembly language. Many | |
4121 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4122 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4123 | * this verbose method. Others are not simple macros but are more like |
4124 | * optimizing code generation. | |
4125 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4126 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4127 | * The ensuing load upper instructions are ommited. This implies some kind |
4128 | * of global optimization. We currently only optimize within a single macro. | |
4129 | * For many of the load and store macros if the address is specified as a | |
4130 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4131 | * first load register 'at' with zero and use it as the base register. The | |
4132 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4133 | * we're missing. | |
4134 | */ | |
4135 | static void | |
17a2f251 | 4136 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4137 | { |
4138 | register int treg, sreg, dreg, breg; | |
4139 | int tempreg; | |
4140 | int mask; | |
43841e91 | 4141 | int used_at = 0; |
252b5132 RH |
4142 | expressionS expr1; |
4143 | const char *s; | |
4144 | const char *s2; | |
4145 | const char *fmt; | |
4146 | int likely = 0; | |
4147 | int dbl = 0; | |
4148 | int coproc = 0; | |
4149 | int lr = 0; | |
4150 | int imm = 0; | |
1abe91b1 | 4151 | int call = 0; |
252b5132 | 4152 | int off; |
67c0d1eb | 4153 | offsetT maxnum; |
252b5132 | 4154 | bfd_reloc_code_real_type r; |
252b5132 RH |
4155 | int hold_mips_optimize; |
4156 | ||
4157 | assert (! mips_opts.mips16); | |
4158 | ||
4159 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4160 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4161 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4162 | mask = ip->insn_mo->mask; | |
4163 | ||
4164 | expr1.X_op = O_constant; | |
4165 | expr1.X_op_symbol = NULL; | |
4166 | expr1.X_add_symbol = NULL; | |
4167 | expr1.X_add_number = 1; | |
4168 | ||
4169 | switch (mask) | |
4170 | { | |
4171 | case M_DABS: | |
4172 | dbl = 1; | |
4173 | case M_ABS: | |
4174 | /* bgez $a0,.+12 | |
4175 | move v0,$a0 | |
4176 | sub v0,$zero,$a0 | |
4177 | */ | |
4178 | ||
b34976b6 | 4179 | mips_emit_delays (TRUE); |
252b5132 RH |
4180 | ++mips_opts.noreorder; |
4181 | mips_any_noreorder = 1; | |
4182 | ||
4183 | expr1.X_add_number = 8; | |
67c0d1eb | 4184 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4185 | if (dreg == sreg) |
67c0d1eb | 4186 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4187 | else |
67c0d1eb RS |
4188 | move_register (dreg, sreg); |
4189 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4190 | |
4191 | --mips_opts.noreorder; | |
4192 | return; | |
4193 | ||
4194 | case M_ADD_I: | |
4195 | s = "addi"; | |
4196 | s2 = "add"; | |
4197 | goto do_addi; | |
4198 | case M_ADDU_I: | |
4199 | s = "addiu"; | |
4200 | s2 = "addu"; | |
4201 | goto do_addi; | |
4202 | case M_DADD_I: | |
4203 | dbl = 1; | |
4204 | s = "daddi"; | |
4205 | s2 = "dadd"; | |
4206 | goto do_addi; | |
4207 | case M_DADDU_I: | |
4208 | dbl = 1; | |
4209 | s = "daddiu"; | |
4210 | s2 = "daddu"; | |
4211 | do_addi: | |
4212 | if (imm_expr.X_op == O_constant | |
4213 | && imm_expr.X_add_number >= -0x8000 | |
4214 | && imm_expr.X_add_number < 0x8000) | |
4215 | { | |
67c0d1eb | 4216 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4217 | return; |
4218 | } | |
67c0d1eb RS |
4219 | load_register (AT, &imm_expr, dbl); |
4220 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4221 | break; |
4222 | ||
4223 | case M_AND_I: | |
4224 | s = "andi"; | |
4225 | s2 = "and"; | |
4226 | goto do_bit; | |
4227 | case M_OR_I: | |
4228 | s = "ori"; | |
4229 | s2 = "or"; | |
4230 | goto do_bit; | |
4231 | case M_NOR_I: | |
4232 | s = ""; | |
4233 | s2 = "nor"; | |
4234 | goto do_bit; | |
4235 | case M_XOR_I: | |
4236 | s = "xori"; | |
4237 | s2 = "xor"; | |
4238 | do_bit: | |
4239 | if (imm_expr.X_op == O_constant | |
4240 | && imm_expr.X_add_number >= 0 | |
4241 | && imm_expr.X_add_number < 0x10000) | |
4242 | { | |
4243 | if (mask != M_NOR_I) | |
67c0d1eb | 4244 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4245 | else |
4246 | { | |
67c0d1eb RS |
4247 | macro_build (&imm_expr, "ori", "t,r,i", |
4248 | treg, sreg, BFD_RELOC_LO16); | |
4249 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4250 | } |
4251 | return; | |
4252 | } | |
4253 | ||
67c0d1eb RS |
4254 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4255 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4256 | break; |
4257 | ||
4258 | case M_BEQ_I: | |
4259 | s = "beq"; | |
4260 | goto beq_i; | |
4261 | case M_BEQL_I: | |
4262 | s = "beql"; | |
4263 | likely = 1; | |
4264 | goto beq_i; | |
4265 | case M_BNE_I: | |
4266 | s = "bne"; | |
4267 | goto beq_i; | |
4268 | case M_BNEL_I: | |
4269 | s = "bnel"; | |
4270 | likely = 1; | |
4271 | beq_i: | |
4272 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4273 | { | |
67c0d1eb | 4274 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4275 | return; |
4276 | } | |
67c0d1eb RS |
4277 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4278 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4279 | break; |
4280 | ||
4281 | case M_BGEL: | |
4282 | likely = 1; | |
4283 | case M_BGE: | |
4284 | if (treg == 0) | |
4285 | { | |
67c0d1eb | 4286 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4287 | return; |
4288 | } | |
4289 | if (sreg == 0) | |
4290 | { | |
67c0d1eb | 4291 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4292 | return; |
4293 | } | |
67c0d1eb RS |
4294 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4295 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4296 | break; |
4297 | ||
4298 | case M_BGTL_I: | |
4299 | likely = 1; | |
4300 | case M_BGT_I: | |
4301 | /* check for > max integer */ | |
4302 | maxnum = 0x7fffffff; | |
ca4e0257 | 4303 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4304 | { |
4305 | maxnum <<= 16; | |
4306 | maxnum |= 0xffff; | |
4307 | maxnum <<= 16; | |
4308 | maxnum |= 0xffff; | |
4309 | } | |
4310 | if (imm_expr.X_op == O_constant | |
4311 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4312 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4313 | { |
4314 | do_false: | |
4315 | /* result is always false */ | |
4316 | if (! likely) | |
67c0d1eb | 4317 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4318 | else |
67c0d1eb | 4319 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4320 | return; |
4321 | } | |
4322 | if (imm_expr.X_op != O_constant) | |
4323 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4324 | ++imm_expr.X_add_number; |
252b5132 RH |
4325 | /* FALLTHROUGH */ |
4326 | case M_BGE_I: | |
4327 | case M_BGEL_I: | |
4328 | if (mask == M_BGEL_I) | |
4329 | likely = 1; | |
4330 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4331 | { | |
67c0d1eb | 4332 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4333 | return; |
4334 | } | |
4335 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4336 | { | |
67c0d1eb | 4337 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4338 | return; |
4339 | } | |
4340 | maxnum = 0x7fffffff; | |
ca4e0257 | 4341 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4342 | { |
4343 | maxnum <<= 16; | |
4344 | maxnum |= 0xffff; | |
4345 | maxnum <<= 16; | |
4346 | maxnum |= 0xffff; | |
4347 | } | |
4348 | maxnum = - maxnum - 1; | |
4349 | if (imm_expr.X_op == O_constant | |
4350 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4351 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4352 | { |
4353 | do_true: | |
4354 | /* result is always true */ | |
4355 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4356 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4357 | return; |
4358 | } | |
67c0d1eb RS |
4359 | set_at (sreg, 0); |
4360 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4361 | break; |
4362 | ||
4363 | case M_BGEUL: | |
4364 | likely = 1; | |
4365 | case M_BGEU: | |
4366 | if (treg == 0) | |
4367 | goto do_true; | |
4368 | if (sreg == 0) | |
4369 | { | |
67c0d1eb | 4370 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4371 | "s,t,p", 0, treg); |
252b5132 RH |
4372 | return; |
4373 | } | |
67c0d1eb RS |
4374 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4375 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4376 | break; |
4377 | ||
4378 | case M_BGTUL_I: | |
4379 | likely = 1; | |
4380 | case M_BGTU_I: | |
4381 | if (sreg == 0 | |
ca4e0257 | 4382 | || (HAVE_32BIT_GPRS |
252b5132 | 4383 | && imm_expr.X_op == O_constant |
956cd1d6 | 4384 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4385 | goto do_false; |
4386 | if (imm_expr.X_op != O_constant) | |
4387 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4388 | ++imm_expr.X_add_number; |
252b5132 RH |
4389 | /* FALLTHROUGH */ |
4390 | case M_BGEU_I: | |
4391 | case M_BGEUL_I: | |
4392 | if (mask == M_BGEUL_I) | |
4393 | likely = 1; | |
4394 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4395 | goto do_true; | |
4396 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4397 | { | |
67c0d1eb | 4398 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4399 | "s,t,p", sreg, 0); |
252b5132 RH |
4400 | return; |
4401 | } | |
67c0d1eb RS |
4402 | set_at (sreg, 1); |
4403 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4404 | break; |
4405 | ||
4406 | case M_BGTL: | |
4407 | likely = 1; | |
4408 | case M_BGT: | |
4409 | if (treg == 0) | |
4410 | { | |
67c0d1eb | 4411 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4412 | return; |
4413 | } | |
4414 | if (sreg == 0) | |
4415 | { | |
67c0d1eb | 4416 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4417 | return; |
4418 | } | |
67c0d1eb RS |
4419 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4420 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4421 | break; |
4422 | ||
4423 | case M_BGTUL: | |
4424 | likely = 1; | |
4425 | case M_BGTU: | |
4426 | if (treg == 0) | |
4427 | { | |
67c0d1eb | 4428 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4429 | "s,t,p", sreg, 0); |
252b5132 RH |
4430 | return; |
4431 | } | |
4432 | if (sreg == 0) | |
4433 | goto do_false; | |
67c0d1eb RS |
4434 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4435 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4436 | break; |
4437 | ||
4438 | case M_BLEL: | |
4439 | likely = 1; | |
4440 | case M_BLE: | |
4441 | if (treg == 0) | |
4442 | { | |
67c0d1eb | 4443 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4444 | return; |
4445 | } | |
4446 | if (sreg == 0) | |
4447 | { | |
67c0d1eb | 4448 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4449 | return; |
4450 | } | |
67c0d1eb RS |
4451 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4452 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4453 | break; |
4454 | ||
4455 | case M_BLEL_I: | |
4456 | likely = 1; | |
4457 | case M_BLE_I: | |
4458 | maxnum = 0x7fffffff; | |
ca4e0257 | 4459 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4460 | { |
4461 | maxnum <<= 16; | |
4462 | maxnum |= 0xffff; | |
4463 | maxnum <<= 16; | |
4464 | maxnum |= 0xffff; | |
4465 | } | |
4466 | if (imm_expr.X_op == O_constant | |
4467 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4468 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4469 | goto do_true; |
4470 | if (imm_expr.X_op != O_constant) | |
4471 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4472 | ++imm_expr.X_add_number; |
252b5132 RH |
4473 | /* FALLTHROUGH */ |
4474 | case M_BLT_I: | |
4475 | case M_BLTL_I: | |
4476 | if (mask == M_BLTL_I) | |
4477 | likely = 1; | |
4478 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4479 | { | |
67c0d1eb | 4480 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4481 | return; |
4482 | } | |
4483 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4484 | { | |
67c0d1eb | 4485 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4486 | return; |
4487 | } | |
67c0d1eb RS |
4488 | set_at (sreg, 0); |
4489 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4490 | break; |
4491 | ||
4492 | case M_BLEUL: | |
4493 | likely = 1; | |
4494 | case M_BLEU: | |
4495 | if (treg == 0) | |
4496 | { | |
67c0d1eb | 4497 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4498 | "s,t,p", sreg, 0); |
252b5132 RH |
4499 | return; |
4500 | } | |
4501 | if (sreg == 0) | |
4502 | goto do_true; | |
67c0d1eb RS |
4503 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4504 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4505 | break; |
4506 | ||
4507 | case M_BLEUL_I: | |
4508 | likely = 1; | |
4509 | case M_BLEU_I: | |
4510 | if (sreg == 0 | |
ca4e0257 | 4511 | || (HAVE_32BIT_GPRS |
252b5132 | 4512 | && imm_expr.X_op == O_constant |
956cd1d6 | 4513 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4514 | goto do_true; |
4515 | if (imm_expr.X_op != O_constant) | |
4516 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4517 | ++imm_expr.X_add_number; |
252b5132 RH |
4518 | /* FALLTHROUGH */ |
4519 | case M_BLTU_I: | |
4520 | case M_BLTUL_I: | |
4521 | if (mask == M_BLTUL_I) | |
4522 | likely = 1; | |
4523 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4524 | goto do_false; | |
4525 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4526 | { | |
67c0d1eb | 4527 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4528 | "s,t,p", sreg, 0); |
4529 | return; | |
4530 | } | |
67c0d1eb RS |
4531 | set_at (sreg, 1); |
4532 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4533 | break; |
4534 | ||
4535 | case M_BLTL: | |
4536 | likely = 1; | |
4537 | case M_BLT: | |
4538 | if (treg == 0) | |
4539 | { | |
67c0d1eb | 4540 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4541 | return; |
4542 | } | |
4543 | if (sreg == 0) | |
4544 | { | |
67c0d1eb | 4545 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4546 | return; |
4547 | } | |
67c0d1eb RS |
4548 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4549 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4550 | break; |
4551 | ||
4552 | case M_BLTUL: | |
4553 | likely = 1; | |
4554 | case M_BLTU: | |
4555 | if (treg == 0) | |
4556 | goto do_false; | |
4557 | if (sreg == 0) | |
4558 | { | |
67c0d1eb | 4559 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4560 | "s,t,p", 0, treg); |
252b5132 RH |
4561 | return; |
4562 | } | |
67c0d1eb RS |
4563 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4564 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4565 | break; |
4566 | ||
5f74bc13 CD |
4567 | case M_DEXT: |
4568 | { | |
4569 | unsigned long pos; | |
4570 | unsigned long size; | |
4571 | ||
4572 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4573 | { | |
4574 | as_bad (_("Unsupported large constant")); | |
4575 | pos = size = 1; | |
4576 | } | |
4577 | else | |
4578 | { | |
4579 | pos = (unsigned long) imm_expr.X_add_number; | |
4580 | size = (unsigned long) imm2_expr.X_add_number; | |
4581 | } | |
4582 | ||
4583 | if (pos > 63) | |
4584 | { | |
4585 | as_bad (_("Improper position (%lu)"), pos); | |
4586 | pos = 1; | |
4587 | } | |
4588 | if (size == 0 || size > 64 | |
4589 | || (pos + size - 1) > 63) | |
4590 | { | |
4591 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4592 | size, pos); | |
4593 | size = 1; | |
4594 | } | |
4595 | ||
4596 | if (size <= 32 && pos < 32) | |
4597 | { | |
4598 | s = "dext"; | |
4599 | fmt = "t,r,+A,+C"; | |
4600 | } | |
4601 | else if (size <= 32) | |
4602 | { | |
4603 | s = "dextu"; | |
4604 | fmt = "t,r,+E,+H"; | |
4605 | } | |
4606 | else | |
4607 | { | |
4608 | s = "dextm"; | |
4609 | fmt = "t,r,+A,+G"; | |
4610 | } | |
67c0d1eb | 4611 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4612 | } |
4613 | return; | |
4614 | ||
4615 | case M_DINS: | |
4616 | { | |
4617 | unsigned long pos; | |
4618 | unsigned long size; | |
4619 | ||
4620 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4621 | { | |
4622 | as_bad (_("Unsupported large constant")); | |
4623 | pos = size = 1; | |
4624 | } | |
4625 | else | |
4626 | { | |
4627 | pos = (unsigned long) imm_expr.X_add_number; | |
4628 | size = (unsigned long) imm2_expr.X_add_number; | |
4629 | } | |
4630 | ||
4631 | if (pos > 63) | |
4632 | { | |
4633 | as_bad (_("Improper position (%lu)"), pos); | |
4634 | pos = 1; | |
4635 | } | |
4636 | if (size == 0 || size > 64 | |
4637 | || (pos + size - 1) > 63) | |
4638 | { | |
4639 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4640 | size, pos); | |
4641 | size = 1; | |
4642 | } | |
4643 | ||
4644 | if (pos < 32 && (pos + size - 1) < 32) | |
4645 | { | |
4646 | s = "dins"; | |
4647 | fmt = "t,r,+A,+B"; | |
4648 | } | |
4649 | else if (pos >= 32) | |
4650 | { | |
4651 | s = "dinsu"; | |
4652 | fmt = "t,r,+E,+F"; | |
4653 | } | |
4654 | else | |
4655 | { | |
4656 | s = "dinsm"; | |
4657 | fmt = "t,r,+A,+F"; | |
4658 | } | |
67c0d1eb RS |
4659 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4660 | pos + size - 1); | |
5f74bc13 CD |
4661 | } |
4662 | return; | |
4663 | ||
252b5132 RH |
4664 | case M_DDIV_3: |
4665 | dbl = 1; | |
4666 | case M_DIV_3: | |
4667 | s = "mflo"; | |
4668 | goto do_div3; | |
4669 | case M_DREM_3: | |
4670 | dbl = 1; | |
4671 | case M_REM_3: | |
4672 | s = "mfhi"; | |
4673 | do_div3: | |
4674 | if (treg == 0) | |
4675 | { | |
4676 | as_warn (_("Divide by zero.")); | |
4677 | if (mips_trap) | |
67c0d1eb | 4678 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4679 | else |
67c0d1eb | 4680 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4681 | return; |
4682 | } | |
4683 | ||
b34976b6 | 4684 | mips_emit_delays (TRUE); |
252b5132 RH |
4685 | ++mips_opts.noreorder; |
4686 | mips_any_noreorder = 1; | |
4687 | if (mips_trap) | |
4688 | { | |
67c0d1eb RS |
4689 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4690 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4691 | } |
4692 | else | |
4693 | { | |
4694 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4695 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4696 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4697 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4698 | } |
4699 | expr1.X_add_number = -1; | |
f6a22291 | 4700 | load_register (AT, &expr1, dbl); |
252b5132 | 4701 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4702 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4703 | if (dbl) |
4704 | { | |
4705 | expr1.X_add_number = 1; | |
f6a22291 | 4706 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4707 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4708 | } |
4709 | else | |
4710 | { | |
4711 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4712 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4713 | } |
4714 | if (mips_trap) | |
4715 | { | |
67c0d1eb | 4716 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4717 | /* We want to close the noreorder block as soon as possible, so |
4718 | that later insns are available for delay slot filling. */ | |
4719 | --mips_opts.noreorder; | |
4720 | } | |
4721 | else | |
4722 | { | |
4723 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4724 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4725 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4726 | |
4727 | /* We want to close the noreorder block as soon as possible, so | |
4728 | that later insns are available for delay slot filling. */ | |
4729 | --mips_opts.noreorder; | |
4730 | ||
67c0d1eb | 4731 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4732 | } |
67c0d1eb | 4733 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4734 | break; |
4735 | ||
4736 | case M_DIV_3I: | |
4737 | s = "div"; | |
4738 | s2 = "mflo"; | |
4739 | goto do_divi; | |
4740 | case M_DIVU_3I: | |
4741 | s = "divu"; | |
4742 | s2 = "mflo"; | |
4743 | goto do_divi; | |
4744 | case M_REM_3I: | |
4745 | s = "div"; | |
4746 | s2 = "mfhi"; | |
4747 | goto do_divi; | |
4748 | case M_REMU_3I: | |
4749 | s = "divu"; | |
4750 | s2 = "mfhi"; | |
4751 | goto do_divi; | |
4752 | case M_DDIV_3I: | |
4753 | dbl = 1; | |
4754 | s = "ddiv"; | |
4755 | s2 = "mflo"; | |
4756 | goto do_divi; | |
4757 | case M_DDIVU_3I: | |
4758 | dbl = 1; | |
4759 | s = "ddivu"; | |
4760 | s2 = "mflo"; | |
4761 | goto do_divi; | |
4762 | case M_DREM_3I: | |
4763 | dbl = 1; | |
4764 | s = "ddiv"; | |
4765 | s2 = "mfhi"; | |
4766 | goto do_divi; | |
4767 | case M_DREMU_3I: | |
4768 | dbl = 1; | |
4769 | s = "ddivu"; | |
4770 | s2 = "mfhi"; | |
4771 | do_divi: | |
4772 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4773 | { | |
4774 | as_warn (_("Divide by zero.")); | |
4775 | if (mips_trap) | |
67c0d1eb | 4776 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4777 | else |
67c0d1eb | 4778 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4779 | return; |
4780 | } | |
4781 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4782 | { | |
4783 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4784 | move_register (dreg, sreg); |
252b5132 | 4785 | else |
67c0d1eb | 4786 | move_register (dreg, 0); |
252b5132 RH |
4787 | return; |
4788 | } | |
4789 | if (imm_expr.X_op == O_constant | |
4790 | && imm_expr.X_add_number == -1 | |
4791 | && s[strlen (s) - 1] != 'u') | |
4792 | { | |
4793 | if (strcmp (s2, "mflo") == 0) | |
4794 | { | |
67c0d1eb | 4795 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4796 | } |
4797 | else | |
67c0d1eb | 4798 | move_register (dreg, 0); |
252b5132 RH |
4799 | return; |
4800 | } | |
4801 | ||
67c0d1eb RS |
4802 | load_register (AT, &imm_expr, dbl); |
4803 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4804 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4805 | break; |
4806 | ||
4807 | case M_DIVU_3: | |
4808 | s = "divu"; | |
4809 | s2 = "mflo"; | |
4810 | goto do_divu3; | |
4811 | case M_REMU_3: | |
4812 | s = "divu"; | |
4813 | s2 = "mfhi"; | |
4814 | goto do_divu3; | |
4815 | case M_DDIVU_3: | |
4816 | s = "ddivu"; | |
4817 | s2 = "mflo"; | |
4818 | goto do_divu3; | |
4819 | case M_DREMU_3: | |
4820 | s = "ddivu"; | |
4821 | s2 = "mfhi"; | |
4822 | do_divu3: | |
b34976b6 | 4823 | mips_emit_delays (TRUE); |
252b5132 RH |
4824 | ++mips_opts.noreorder; |
4825 | mips_any_noreorder = 1; | |
4826 | if (mips_trap) | |
4827 | { | |
67c0d1eb RS |
4828 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4829 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4830 | /* We want to close the noreorder block as soon as possible, so |
4831 | that later insns are available for delay slot filling. */ | |
4832 | --mips_opts.noreorder; | |
4833 | } | |
4834 | else | |
4835 | { | |
4836 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4837 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4838 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4839 | |
4840 | /* We want to close the noreorder block as soon as possible, so | |
4841 | that later insns are available for delay slot filling. */ | |
4842 | --mips_opts.noreorder; | |
67c0d1eb | 4843 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4844 | } |
67c0d1eb | 4845 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4846 | return; |
4847 | ||
1abe91b1 MR |
4848 | case M_DLCA_AB: |
4849 | dbl = 1; | |
4850 | case M_LCA_AB: | |
4851 | call = 1; | |
4852 | goto do_la; | |
252b5132 RH |
4853 | case M_DLA_AB: |
4854 | dbl = 1; | |
4855 | case M_LA_AB: | |
1abe91b1 | 4856 | do_la: |
252b5132 RH |
4857 | /* Load the address of a symbol into a register. If breg is not |
4858 | zero, we then add a base register to it. */ | |
4859 | ||
3bec30a8 TS |
4860 | if (dbl && HAVE_32BIT_GPRS) |
4861 | as_warn (_("dla used to load 32-bit register")); | |
4862 | ||
c90bbe5b | 4863 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4864 | as_warn (_("la used to load 64-bit address")); |
4865 | ||
0c11417f MR |
4866 | if (offset_expr.X_op == O_constant |
4867 | && offset_expr.X_add_number >= -0x8000 | |
4868 | && offset_expr.X_add_number < 0x8000) | |
4869 | { | |
67c0d1eb | 4870 | macro_build (&offset_expr, |
b7c7d6c1 | 4871 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4872 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4873 | return; |
4874 | } | |
4875 | ||
afdbd6d0 CD |
4876 | if (treg == breg) |
4877 | { | |
4878 | tempreg = AT; | |
4879 | used_at = 1; | |
4880 | } | |
4881 | else | |
4882 | { | |
4883 | tempreg = treg; | |
4884 | used_at = 0; | |
4885 | } | |
4886 | ||
252b5132 RH |
4887 | if (offset_expr.X_op != O_symbol |
4888 | && offset_expr.X_op != O_constant) | |
4889 | { | |
4890 | as_bad (_("expression too complex")); | |
4891 | offset_expr.X_op = O_constant; | |
4892 | } | |
4893 | ||
252b5132 | 4894 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4895 | load_register (tempreg, &offset_expr, |
3e722fb5 | 4896 | (mips_pic == NO_PIC |
4d34fb5f TS |
4897 | ? (dbl || HAVE_64BIT_ADDRESSES) |
4898 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4899 | else if (mips_pic == NO_PIC) |
4900 | { | |
d6bc6245 | 4901 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4902 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4903 | Otherwise we want |
4904 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4905 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4906 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4907 | so we may as well always use the latter form. |
76b3015f | 4908 | |
d6bc6245 TS |
4909 | With 64bit address space and a usable $at we want |
4910 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4911 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4912 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4913 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4914 | dsll32 $tempreg,0 | |
3a482fd5 | 4915 | daddu $tempreg,$tempreg,$at |
76b3015f | 4916 | |
c03099e6 | 4917 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4918 | on superscalar processors. |
4919 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4920 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4921 | dsll $tempreg,16 | |
4922 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4923 | dsll $tempreg,16 | |
4924 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4925 | */ | |
d6bc6245 | 4926 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4927 | { |
e864ceca RS |
4928 | /* ??? We don't provide a GP-relative alternative for |
4929 | these macros. It used not to be possible with the | |
4930 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4931 | |
460597ba | 4932 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f | 4933 | { |
67c0d1eb | 4934 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4935 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4936 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4937 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4938 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4939 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4940 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4941 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4942 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4943 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4944 | used_at = 1; |
4945 | } | |
4946 | else | |
4947 | { | |
67c0d1eb | 4948 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4949 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4950 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4951 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4952 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4953 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4954 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4955 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4956 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4957 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4958 | } |
4959 | } | |
4960 | else | |
4961 | { | |
4962 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4963 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4964 | { | |
4d7206a2 | 4965 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4966 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4967 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4968 | relax_switch (); |
98d3f06f | 4969 | } |
67c0d1eb RS |
4970 | macro_build_lui (&offset_expr, tempreg); |
4971 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4972 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4973 | if (mips_relax.sequence) |
4974 | relax_end (); | |
98d3f06f | 4975 | } |
252b5132 | 4976 | } |
f5040a92 | 4977 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4978 | { |
9117d219 NC |
4979 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4980 | ||
252b5132 RH |
4981 | /* If this is a reference to an external symbol, and there |
4982 | is no constant, we want | |
4983 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4984 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4985 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4986 | For a local symbol, we want |
4987 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4988 | nop | |
4989 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4990 | ||
4991 | If we have a small constant, and this is a reference to | |
4992 | an external symbol, we want | |
4993 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4994 | nop | |
4995 | addiu $tempreg,$tempreg,<constant> | |
4996 | For a local symbol, we want the same instruction | |
4997 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4998 | addiu instruction. | |
4999 | ||
5000 | If we have a large constant, and this is a reference to | |
5001 | an external symbol, we want | |
5002 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5003 | lui $at,<hiconstant> | |
5004 | addiu $at,$at,<loconstant> | |
5005 | addu $tempreg,$tempreg,$at | |
5006 | For a local symbol, we want the same instruction | |
5007 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5008 | addiu instruction. |
ed6fb7bd SC |
5009 | */ |
5010 | ||
4d7206a2 | 5011 | if (offset_expr.X_add_number == 0) |
252b5132 | 5012 | { |
4d7206a2 RS |
5013 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5014 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5015 | ||
5016 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5017 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5018 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5019 | if (breg != 0) |
252b5132 RH |
5020 | { |
5021 | /* We're going to put in an addu instruction using | |
5022 | tempreg, so we may as well insert the nop right | |
5023 | now. */ | |
269137b2 | 5024 | load_delay_nop (); |
252b5132 | 5025 | } |
4d7206a2 | 5026 | relax_switch (); |
67c0d1eb RS |
5027 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5028 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5029 | load_delay_nop (); |
67c0d1eb RS |
5030 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5031 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5032 | relax_end (); |
252b5132 RH |
5033 | /* FIXME: If breg == 0, and the next instruction uses |
5034 | $tempreg, then if this variant case is used an extra | |
5035 | nop will be generated. */ | |
5036 | } | |
4d7206a2 RS |
5037 | else if (offset_expr.X_add_number >= -0x8000 |
5038 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5039 | { |
67c0d1eb | 5040 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5041 | load_delay_nop (); |
67c0d1eb | 5042 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5043 | } |
5044 | else | |
5045 | { | |
4d7206a2 RS |
5046 | expr1.X_add_number = offset_expr.X_add_number; |
5047 | offset_expr.X_add_number = | |
5048 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5049 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5050 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5051 | /* If we are going to add in a base register, and the |
5052 | target register and the base register are the same, | |
5053 | then we are using AT as a temporary register. Since | |
5054 | we want to load the constant into AT, we add our | |
5055 | current AT (from the global offset table) and the | |
5056 | register into the register now, and pretend we were | |
5057 | not using a base register. */ | |
67c0d1eb | 5058 | if (breg == treg) |
252b5132 | 5059 | { |
269137b2 | 5060 | load_delay_nop (); |
67c0d1eb | 5061 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5062 | treg, AT, breg); |
252b5132 RH |
5063 | breg = 0; |
5064 | tempreg = treg; | |
252b5132 | 5065 | } |
f6a22291 | 5066 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5067 | used_at = 1; |
5068 | } | |
5069 | } | |
f5040a92 AO |
5070 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5071 | { | |
67c0d1eb | 5072 | int add_breg_early = 0; |
f5040a92 AO |
5073 | |
5074 | /* If this is a reference to an external, and there is no | |
5075 | constant, or local symbol (*), with or without a | |
5076 | constant, we want | |
5077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5078 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5079 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5080 | ||
5081 | If we have a small constant, and this is a reference to | |
5082 | an external symbol, we want | |
5083 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5084 | addiu $tempreg,$tempreg,<constant> | |
5085 | ||
5086 | If we have a large constant, and this is a reference to | |
5087 | an external symbol, we want | |
5088 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5089 | lui $at,<hiconstant> | |
5090 | addiu $at,$at,<loconstant> | |
5091 | addu $tempreg,$tempreg,$at | |
5092 | ||
5093 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5094 | local symbols, even though it introduces an additional | |
5095 | instruction. */ | |
5096 | ||
f5040a92 AO |
5097 | if (offset_expr.X_add_number) |
5098 | { | |
4d7206a2 | 5099 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5100 | offset_expr.X_add_number = 0; |
5101 | ||
4d7206a2 | 5102 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5103 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5104 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5105 | |
5106 | if (expr1.X_add_number >= -0x8000 | |
5107 | && expr1.X_add_number < 0x8000) | |
5108 | { | |
67c0d1eb RS |
5109 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5110 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5111 | } |
ecd13cd3 | 5112 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5113 | { |
5114 | int dreg; | |
5115 | ||
5116 | /* If we are going to add in a base register, and the | |
5117 | target register and the base register are the same, | |
5118 | then we are using AT as a temporary register. Since | |
5119 | we want to load the constant into AT, we add our | |
5120 | current AT (from the global offset table) and the | |
5121 | register into the register now, and pretend we were | |
5122 | not using a base register. */ | |
5123 | if (breg != treg) | |
5124 | dreg = tempreg; | |
5125 | else | |
5126 | { | |
5127 | assert (tempreg == AT); | |
67c0d1eb RS |
5128 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5129 | treg, AT, breg); | |
f5040a92 | 5130 | dreg = treg; |
67c0d1eb | 5131 | add_breg_early = 1; |
f5040a92 AO |
5132 | } |
5133 | ||
f6a22291 | 5134 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5135 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5136 | dreg, dreg, AT); |
f5040a92 | 5137 | |
f5040a92 AO |
5138 | used_at = 1; |
5139 | } | |
5140 | else | |
5141 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5142 | ||
4d7206a2 | 5143 | relax_switch (); |
f5040a92 AO |
5144 | offset_expr.X_add_number = expr1.X_add_number; |
5145 | ||
67c0d1eb RS |
5146 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5147 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5148 | if (add_breg_early) | |
f5040a92 | 5149 | { |
67c0d1eb | 5150 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5151 | treg, tempreg, breg); |
f5040a92 AO |
5152 | breg = 0; |
5153 | tempreg = treg; | |
5154 | } | |
4d7206a2 | 5155 | relax_end (); |
f5040a92 | 5156 | } |
4d7206a2 | 5157 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5158 | { |
4d7206a2 | 5159 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5160 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5161 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5162 | relax_switch (); |
67c0d1eb RS |
5163 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5164 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5165 | relax_end (); |
f5040a92 | 5166 | } |
4d7206a2 | 5167 | else |
f5040a92 | 5168 | { |
67c0d1eb RS |
5169 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5170 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5171 | } |
5172 | } | |
5173 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5174 | { |
67c0d1eb | 5175 | int gpdelay; |
9117d219 NC |
5176 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5177 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5178 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5179 | |
5180 | /* This is the large GOT case. If this is a reference to an | |
5181 | external symbol, and there is no constant, we want | |
5182 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5183 | addu $tempreg,$tempreg,$gp | |
5184 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5185 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5186 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5187 | addu $tempreg,$tempreg,$gp | |
5188 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5189 | For a local symbol, we want |
5190 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5191 | nop | |
5192 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5193 | ||
5194 | If we have a small constant, and this is a reference to | |
5195 | an external symbol, we want | |
5196 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5197 | addu $tempreg,$tempreg,$gp | |
5198 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5199 | nop | |
5200 | addiu $tempreg,$tempreg,<constant> | |
5201 | For a local symbol, we want | |
5202 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5203 | nop | |
5204 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5205 | ||
5206 | If we have a large constant, and this is a reference to | |
5207 | an external symbol, we want | |
5208 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5209 | addu $tempreg,$tempreg,$gp | |
5210 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5211 | lui $at,<hiconstant> | |
5212 | addiu $at,$at,<loconstant> | |
5213 | addu $tempreg,$tempreg,$at | |
5214 | For a local symbol, we want | |
5215 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5216 | lui $at,<hiconstant> | |
5217 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5218 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5219 | */ |
438c16b8 | 5220 | |
252b5132 RH |
5221 | expr1.X_add_number = offset_expr.X_add_number; |
5222 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5223 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5224 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5225 | if (expr1.X_add_number == 0 && breg == 0 |
5226 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5227 | { |
5228 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5229 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5230 | } | |
67c0d1eb RS |
5231 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5232 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5233 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5234 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5235 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5236 | if (expr1.X_add_number == 0) |
5237 | { | |
67c0d1eb | 5238 | if (breg != 0) |
252b5132 RH |
5239 | { |
5240 | /* We're going to put in an addu instruction using | |
5241 | tempreg, so we may as well insert the nop right | |
5242 | now. */ | |
269137b2 | 5243 | load_delay_nop (); |
252b5132 | 5244 | } |
252b5132 RH |
5245 | } |
5246 | else if (expr1.X_add_number >= -0x8000 | |
5247 | && expr1.X_add_number < 0x8000) | |
5248 | { | |
269137b2 | 5249 | load_delay_nop (); |
67c0d1eb | 5250 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5251 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5252 | } |
5253 | else | |
5254 | { | |
67c0d1eb | 5255 | int dreg; |
252b5132 RH |
5256 | |
5257 | /* If we are going to add in a base register, and the | |
5258 | target register and the base register are the same, | |
5259 | then we are using AT as a temporary register. Since | |
5260 | we want to load the constant into AT, we add our | |
5261 | current AT (from the global offset table) and the | |
5262 | register into the register now, and pretend we were | |
5263 | not using a base register. */ | |
5264 | if (breg != treg) | |
67c0d1eb | 5265 | dreg = tempreg; |
252b5132 RH |
5266 | else |
5267 | { | |
5268 | assert (tempreg == AT); | |
269137b2 | 5269 | load_delay_nop (); |
67c0d1eb | 5270 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5271 | treg, AT, breg); |
252b5132 | 5272 | dreg = treg; |
252b5132 RH |
5273 | } |
5274 | ||
f6a22291 | 5275 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5276 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5277 | |
252b5132 RH |
5278 | used_at = 1; |
5279 | } | |
4d7206a2 RS |
5280 | offset_expr.X_add_number = |
5281 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5282 | relax_switch (); | |
252b5132 | 5283 | |
67c0d1eb | 5284 | if (gpdelay) |
252b5132 RH |
5285 | { |
5286 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5287 | the first instruction on the main stream does not. */ |
67c0d1eb | 5288 | macro_build (NULL, "nop", ""); |
252b5132 | 5289 | } |
ed6fb7bd | 5290 | |
67c0d1eb RS |
5291 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5292 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5293 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5294 | && expr1.X_add_number < 0x8000) |
5295 | { | |
269137b2 | 5296 | load_delay_nop (); |
67c0d1eb RS |
5297 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5298 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5299 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5300 | register, the external symbol case ended with a load, |
5301 | so if the symbol turns out to not be external, and | |
5302 | the next instruction uses tempreg, an unnecessary nop | |
5303 | will be inserted. */ | |
252b5132 RH |
5304 | } |
5305 | else | |
5306 | { | |
5307 | if (breg == treg) | |
5308 | { | |
5309 | /* We must add in the base register now, as in the | |
f5040a92 | 5310 | external symbol case. */ |
252b5132 | 5311 | assert (tempreg == AT); |
269137b2 | 5312 | load_delay_nop (); |
67c0d1eb | 5313 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5314 | treg, AT, breg); |
252b5132 RH |
5315 | tempreg = treg; |
5316 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5317 | it in in both cases. */ |
252b5132 RH |
5318 | breg = 0; |
5319 | } | |
5320 | ||
67c0d1eb RS |
5321 | macro_build_lui (&expr1, AT); |
5322 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5323 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5324 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5325 | tempreg, tempreg, AT); |
252b5132 | 5326 | } |
4d7206a2 | 5327 | relax_end (); |
252b5132 | 5328 | } |
f5040a92 AO |
5329 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5330 | { | |
f5040a92 AO |
5331 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5332 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5333 | int add_breg_early = 0; |
f5040a92 AO |
5334 | |
5335 | /* This is the large GOT case. If this is a reference to an | |
5336 | external symbol, and there is no constant, we want | |
5337 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5338 | add $tempreg,$tempreg,$gp | |
5339 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5340 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5341 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5342 | add $tempreg,$tempreg,$gp | |
5343 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5344 | ||
5345 | If we have a small constant, and this is a reference to | |
5346 | an external symbol, we want | |
5347 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5348 | add $tempreg,$tempreg,$gp | |
5349 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5350 | addi $tempreg,$tempreg,<constant> | |
5351 | ||
5352 | If we have a large constant, and this is a reference to | |
5353 | an external symbol, we want | |
5354 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5355 | addu $tempreg,$tempreg,$gp | |
5356 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5357 | lui $at,<hiconstant> | |
5358 | addi $at,$at,<loconstant> | |
5359 | add $tempreg,$tempreg,$at | |
5360 | ||
5361 | If we have NewABI, and we know it's a local symbol, we want | |
5362 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5363 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5364 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5365 | ||
4d7206a2 | 5366 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5367 | |
4d7206a2 | 5368 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5369 | offset_expr.X_add_number = 0; |
5370 | ||
1abe91b1 MR |
5371 | if (expr1.X_add_number == 0 && breg == 0 |
5372 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5373 | { |
5374 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5375 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5376 | } | |
67c0d1eb RS |
5377 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5378 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5379 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5380 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5381 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5382 | |
5383 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5384 | ; |
f5040a92 AO |
5385 | else if (expr1.X_add_number >= -0x8000 |
5386 | && expr1.X_add_number < 0x8000) | |
5387 | { | |
67c0d1eb | 5388 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5389 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5390 | } |
ecd13cd3 | 5391 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5392 | { |
5393 | int dreg; | |
5394 | ||
5395 | /* If we are going to add in a base register, and the | |
5396 | target register and the base register are the same, | |
5397 | then we are using AT as a temporary register. Since | |
5398 | we want to load the constant into AT, we add our | |
5399 | current AT (from the global offset table) and the | |
5400 | register into the register now, and pretend we were | |
5401 | not using a base register. */ | |
5402 | if (breg != treg) | |
5403 | dreg = tempreg; | |
5404 | else | |
5405 | { | |
5406 | assert (tempreg == AT); | |
67c0d1eb | 5407 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5408 | treg, AT, breg); |
f5040a92 | 5409 | dreg = treg; |
67c0d1eb | 5410 | add_breg_early = 1; |
f5040a92 AO |
5411 | } |
5412 | ||
f6a22291 | 5413 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5414 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5415 | |
f5040a92 AO |
5416 | used_at = 1; |
5417 | } | |
5418 | else | |
5419 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5420 | ||
4d7206a2 | 5421 | relax_switch (); |
f5040a92 | 5422 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5423 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5424 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5425 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5426 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5427 | if (add_breg_early) | |
f5040a92 | 5428 | { |
67c0d1eb | 5429 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5430 | treg, tempreg, breg); |
f5040a92 AO |
5431 | breg = 0; |
5432 | tempreg = treg; | |
5433 | } | |
4d7206a2 | 5434 | relax_end (); |
f5040a92 | 5435 | } |
252b5132 RH |
5436 | else |
5437 | abort (); | |
5438 | ||
5439 | if (breg != 0) | |
4d34fb5f TS |
5440 | { |
5441 | char *s; | |
5442 | ||
3e722fb5 | 5443 | if (mips_pic == NO_PIC) |
b7c7d6c1 | 5444 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5445 | else |
f899b4b8 | 5446 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5447 | |
67c0d1eb | 5448 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5449 | } |
252b5132 RH |
5450 | |
5451 | if (! used_at) | |
5452 | return; | |
5453 | ||
5454 | break; | |
5455 | ||
5456 | case M_J_A: | |
5457 | /* The j instruction may not be used in PIC code, since it | |
5458 | requires an absolute address. We convert it to a b | |
5459 | instruction. */ | |
5460 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5461 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5462 | else |
67c0d1eb | 5463 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5464 | return; |
5465 | ||
5466 | /* The jal instructions must be handled as macros because when | |
5467 | generating PIC code they expand to multi-instruction | |
5468 | sequences. Normally they are simple instructions. */ | |
5469 | case M_JAL_1: | |
5470 | dreg = RA; | |
5471 | /* Fall through. */ | |
5472 | case M_JAL_2: | |
3e722fb5 | 5473 | if (mips_pic == NO_PIC) |
67c0d1eb | 5474 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5475 | else if (mips_pic == SVR4_PIC) |
5476 | { | |
5477 | if (sreg != PIC_CALL_REG) | |
5478 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5479 | |
67c0d1eb | 5480 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5481 | if (! HAVE_NEWABI) |
252b5132 | 5482 | { |
6478892d TS |
5483 | if (mips_cprestore_offset < 0) |
5484 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5485 | else | |
5486 | { | |
7a621144 DJ |
5487 | if (! mips_frame_reg_valid) |
5488 | { | |
5489 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5490 | /* Quiet this warning. */ | |
5491 | mips_frame_reg_valid = 1; | |
5492 | } | |
5493 | if (! mips_cprestore_valid) | |
5494 | { | |
5495 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5496 | /* Quiet this warning. */ | |
5497 | mips_cprestore_valid = 1; | |
5498 | } | |
6478892d | 5499 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5500 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5501 | mips_gp_register, |
256ab948 TS |
5502 | mips_frame_reg, |
5503 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5504 | } |
252b5132 RH |
5505 | } |
5506 | } | |
5507 | else | |
5508 | abort (); | |
5509 | ||
5510 | return; | |
5511 | ||
5512 | case M_JAL_A: | |
5513 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5514 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5515 | else if (mips_pic == SVR4_PIC) |
5516 | { | |
5517 | /* If this is a reference to an external symbol, and we are | |
5518 | using a small GOT, we want | |
5519 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5520 | nop | |
f9419b05 | 5521 | jalr $ra,$25 |
252b5132 RH |
5522 | nop |
5523 | lw $gp,cprestore($sp) | |
5524 | The cprestore value is set using the .cprestore | |
5525 | pseudo-op. If we are using a big GOT, we want | |
5526 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5527 | addu $25,$25,$gp | |
5528 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5529 | nop | |
f9419b05 | 5530 | jalr $ra,$25 |
252b5132 RH |
5531 | nop |
5532 | lw $gp,cprestore($sp) | |
5533 | If the symbol is not external, we want | |
5534 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5535 | nop | |
5536 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5537 | jalr $ra,$25 |
252b5132 | 5538 | nop |
438c16b8 | 5539 | lw $gp,cprestore($sp) |
f5040a92 AO |
5540 | |
5541 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5542 | sequences above, minus nops, unless the symbol is local, | |
5543 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5544 | GOT_DISP. */ | |
438c16b8 | 5545 | if (HAVE_NEWABI) |
252b5132 | 5546 | { |
f5040a92 AO |
5547 | if (! mips_big_got) |
5548 | { | |
4d7206a2 | 5549 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5550 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5551 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5552 | mips_gp_register); |
4d7206a2 | 5553 | relax_switch (); |
67c0d1eb RS |
5554 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5555 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5556 | mips_gp_register); |
5557 | relax_end (); | |
f5040a92 AO |
5558 | } |
5559 | else | |
5560 | { | |
4d7206a2 | 5561 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5562 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5563 | BFD_RELOC_MIPS_CALL_HI16); | |
5564 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5565 | PIC_CALL_REG, mips_gp_register); | |
5566 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5567 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5568 | PIC_CALL_REG); | |
4d7206a2 | 5569 | relax_switch (); |
67c0d1eb RS |
5570 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5571 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5572 | mips_gp_register); | |
5573 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5574 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5575 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5576 | relax_end (); |
f5040a92 | 5577 | } |
684022ea | 5578 | |
67c0d1eb | 5579 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5580 | } |
5581 | else | |
5582 | { | |
4d7206a2 | 5583 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5584 | if (! mips_big_got) |
5585 | { | |
67c0d1eb RS |
5586 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5587 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5588 | mips_gp_register); |
269137b2 | 5589 | load_delay_nop (); |
4d7206a2 | 5590 | relax_switch (); |
438c16b8 | 5591 | } |
252b5132 | 5592 | else |
252b5132 | 5593 | { |
67c0d1eb RS |
5594 | int gpdelay; |
5595 | ||
5596 | gpdelay = reg_needs_delay (mips_gp_register); | |
5597 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5598 | BFD_RELOC_MIPS_CALL_HI16); | |
5599 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5600 | PIC_CALL_REG, mips_gp_register); | |
5601 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5602 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5603 | PIC_CALL_REG); | |
269137b2 | 5604 | load_delay_nop (); |
4d7206a2 | 5605 | relax_switch (); |
67c0d1eb RS |
5606 | if (gpdelay) |
5607 | macro_build (NULL, "nop", ""); | |
252b5132 | 5608 | } |
67c0d1eb RS |
5609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5610 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5611 | mips_gp_register); |
269137b2 | 5612 | load_delay_nop (); |
67c0d1eb RS |
5613 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5614 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5615 | relax_end (); |
67c0d1eb | 5616 | macro_build_jalr (&offset_expr); |
438c16b8 | 5617 | |
6478892d TS |
5618 | if (mips_cprestore_offset < 0) |
5619 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5620 | else | |
5621 | { | |
7a621144 DJ |
5622 | if (! mips_frame_reg_valid) |
5623 | { | |
5624 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5625 | /* Quiet this warning. */ | |
5626 | mips_frame_reg_valid = 1; | |
5627 | } | |
5628 | if (! mips_cprestore_valid) | |
5629 | { | |
5630 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5631 | /* Quiet this warning. */ | |
5632 | mips_cprestore_valid = 1; | |
5633 | } | |
6478892d | 5634 | if (mips_opts.noreorder) |
67c0d1eb | 5635 | macro_build (NULL, "nop", ""); |
6478892d | 5636 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5637 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5638 | mips_gp_register, |
256ab948 TS |
5639 | mips_frame_reg, |
5640 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5641 | } |
252b5132 RH |
5642 | } |
5643 | } | |
252b5132 RH |
5644 | else |
5645 | abort (); | |
5646 | ||
5647 | return; | |
5648 | ||
5649 | case M_LB_AB: | |
5650 | s = "lb"; | |
5651 | goto ld; | |
5652 | case M_LBU_AB: | |
5653 | s = "lbu"; | |
5654 | goto ld; | |
5655 | case M_LH_AB: | |
5656 | s = "lh"; | |
5657 | goto ld; | |
5658 | case M_LHU_AB: | |
5659 | s = "lhu"; | |
5660 | goto ld; | |
5661 | case M_LW_AB: | |
5662 | s = "lw"; | |
5663 | goto ld; | |
5664 | case M_LWC0_AB: | |
5665 | s = "lwc0"; | |
bdaaa2e1 | 5666 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5667 | coproc = 1; |
5668 | goto ld; | |
5669 | case M_LWC1_AB: | |
5670 | s = "lwc1"; | |
bdaaa2e1 | 5671 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5672 | coproc = 1; |
5673 | goto ld; | |
5674 | case M_LWC2_AB: | |
5675 | s = "lwc2"; | |
bdaaa2e1 | 5676 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5677 | coproc = 1; |
5678 | goto ld; | |
5679 | case M_LWC3_AB: | |
5680 | s = "lwc3"; | |
bdaaa2e1 | 5681 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5682 | coproc = 1; |
5683 | goto ld; | |
5684 | case M_LWL_AB: | |
5685 | s = "lwl"; | |
5686 | lr = 1; | |
5687 | goto ld; | |
5688 | case M_LWR_AB: | |
5689 | s = "lwr"; | |
5690 | lr = 1; | |
5691 | goto ld; | |
5692 | case M_LDC1_AB: | |
fef14a42 | 5693 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5694 | { |
5695 | as_bad (_("opcode not supported on this processor")); | |
5696 | return; | |
5697 | } | |
5698 | s = "ldc1"; | |
bdaaa2e1 | 5699 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5700 | coproc = 1; |
5701 | goto ld; | |
5702 | case M_LDC2_AB: | |
5703 | s = "ldc2"; | |
bdaaa2e1 | 5704 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5705 | coproc = 1; |
5706 | goto ld; | |
5707 | case M_LDC3_AB: | |
5708 | s = "ldc3"; | |
bdaaa2e1 | 5709 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5710 | coproc = 1; |
5711 | goto ld; | |
5712 | case M_LDL_AB: | |
5713 | s = "ldl"; | |
5714 | lr = 1; | |
5715 | goto ld; | |
5716 | case M_LDR_AB: | |
5717 | s = "ldr"; | |
5718 | lr = 1; | |
5719 | goto ld; | |
5720 | case M_LL_AB: | |
5721 | s = "ll"; | |
5722 | goto ld; | |
5723 | case M_LLD_AB: | |
5724 | s = "lld"; | |
5725 | goto ld; | |
5726 | case M_LWU_AB: | |
5727 | s = "lwu"; | |
5728 | ld: | |
5729 | if (breg == treg || coproc || lr) | |
5730 | { | |
5731 | tempreg = AT; | |
5732 | used_at = 1; | |
5733 | } | |
5734 | else | |
5735 | { | |
5736 | tempreg = treg; | |
5737 | used_at = 0; | |
5738 | } | |
5739 | goto ld_st; | |
5740 | case M_SB_AB: | |
5741 | s = "sb"; | |
5742 | goto st; | |
5743 | case M_SH_AB: | |
5744 | s = "sh"; | |
5745 | goto st; | |
5746 | case M_SW_AB: | |
5747 | s = "sw"; | |
5748 | goto st; | |
5749 | case M_SWC0_AB: | |
5750 | s = "swc0"; | |
bdaaa2e1 | 5751 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5752 | coproc = 1; |
5753 | goto st; | |
5754 | case M_SWC1_AB: | |
5755 | s = "swc1"; | |
bdaaa2e1 | 5756 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5757 | coproc = 1; |
5758 | goto st; | |
5759 | case M_SWC2_AB: | |
5760 | s = "swc2"; | |
bdaaa2e1 | 5761 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5762 | coproc = 1; |
5763 | goto st; | |
5764 | case M_SWC3_AB: | |
5765 | s = "swc3"; | |
bdaaa2e1 | 5766 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5767 | coproc = 1; |
5768 | goto st; | |
5769 | case M_SWL_AB: | |
5770 | s = "swl"; | |
5771 | goto st; | |
5772 | case M_SWR_AB: | |
5773 | s = "swr"; | |
5774 | goto st; | |
5775 | case M_SC_AB: | |
5776 | s = "sc"; | |
5777 | goto st; | |
5778 | case M_SCD_AB: | |
5779 | s = "scd"; | |
5780 | goto st; | |
5781 | case M_SDC1_AB: | |
fef14a42 | 5782 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5783 | { |
5784 | as_bad (_("opcode not supported on this processor")); | |
5785 | return; | |
5786 | } | |
5787 | s = "sdc1"; | |
5788 | coproc = 1; | |
bdaaa2e1 | 5789 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5790 | goto st; |
5791 | case M_SDC2_AB: | |
5792 | s = "sdc2"; | |
bdaaa2e1 | 5793 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5794 | coproc = 1; |
5795 | goto st; | |
5796 | case M_SDC3_AB: | |
5797 | s = "sdc3"; | |
bdaaa2e1 | 5798 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5799 | coproc = 1; |
5800 | goto st; | |
5801 | case M_SDL_AB: | |
5802 | s = "sdl"; | |
5803 | goto st; | |
5804 | case M_SDR_AB: | |
5805 | s = "sdr"; | |
5806 | st: | |
5807 | tempreg = AT; | |
5808 | used_at = 1; | |
5809 | ld_st: | |
bdaaa2e1 | 5810 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5811 | if (mask == M_LWC1_AB |
5812 | || mask == M_SWC1_AB | |
5813 | || mask == M_LDC1_AB | |
5814 | || mask == M_SDC1_AB | |
5815 | || mask == M_L_DAB | |
5816 | || mask == M_S_DAB) | |
5817 | fmt = "T,o(b)"; | |
5818 | else if (coproc) | |
5819 | fmt = "E,o(b)"; | |
5820 | else | |
5821 | fmt = "t,o(b)"; | |
5822 | ||
256ab948 TS |
5823 | /* Sign-extending 32-bit constants makes their handling easier. |
5824 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5825 | described below. */ | |
5826 | if ((! HAVE_64BIT_ADDRESSES | |
5827 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5828 | && (offset_expr.X_op == O_constant) |
5829 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5830 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5831 | { |
d17e7bce | 5832 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5833 | as_bad (_("constant too large")); |
ae826530 | 5834 | |
1b8e29e5 TS |
5835 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5836 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5837 | } |
256ab948 | 5838 | |
252b5132 RH |
5839 | if (offset_expr.X_op != O_constant |
5840 | && offset_expr.X_op != O_symbol) | |
5841 | { | |
5842 | as_bad (_("expression too complex")); | |
5843 | offset_expr.X_op = O_constant; | |
5844 | } | |
5845 | ||
5846 | /* A constant expression in PIC code can be handled just as it | |
5847 | is in non PIC code. */ | |
5848 | if (mips_pic == NO_PIC | |
5849 | || offset_expr.X_op == O_constant) | |
5850 | { | |
5851 | /* If this is a reference to a GP relative symbol, and there | |
5852 | is no base register, we want | |
cdf6fd85 | 5853 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5854 | Otherwise, if there is no base register, we want |
5855 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5856 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5857 | If we have a constant, we need two instructions anyhow, | |
5858 | so we always use the latter form. | |
5859 | ||
5860 | If we have a base register, and this is a reference to a | |
5861 | GP relative symbol, we want | |
5862 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5863 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5864 | Otherwise we want |
5865 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5866 | addu $tempreg,$tempreg,$breg | |
5867 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5868 | With a constant we always use the latter case. |
76b3015f | 5869 | |
d6bc6245 TS |
5870 | With 64bit address space and no base register and $at usable, |
5871 | we want | |
5872 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5873 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5874 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5875 | dsll32 $tempreg,0 | |
5876 | daddu $tempreg,$at | |
5877 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5878 | If we have a base register, we want | |
5879 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5880 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5881 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5882 | daddu $at,$breg | |
5883 | dsll32 $tempreg,0 | |
5884 | daddu $tempreg,$at | |
5885 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5886 | ||
5887 | Without $at we can't generate the optimal path for superscalar | |
5888 | processors here since this would require two temporary registers. | |
5889 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5890 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5891 | dsll $tempreg,16 | |
5892 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5893 | dsll $tempreg,16 | |
5894 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5895 | If we have a base register, we want | |
5896 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5897 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5898 | dsll $tempreg,16 | |
5899 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5900 | dsll $tempreg,16 | |
5901 | daddu $tempreg,$tempreg,$breg | |
5902 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5903 | |
5904 | If we have 64-bit addresses, as an optimization, for | |
5905 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5906 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5907 | mechanism since it is more efficient. Note that due to |
5908 | the signed offset used by memory operations, the 32-bit | |
5909 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5910 | probably attempt to generate 64-bit constants more |
5911 | efficiently in general. | |
9214dd3b AO |
5912 | |
5913 | As an extension for architectures with 64-bit registers, | |
5914 | we don't truncate 64-bit addresses given as literal | |
5915 | constants down to 32 bits, to support existing practice | |
5916 | in the mips64 Linux (the kernel), that compiles source | |
5917 | files with -mabi=64, assembling them as o32 or n32 (with | |
5918 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5919 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 5920 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
5921 | wasteful to compute the upper 32 bits of every |
5922 | non-literal address, that takes more space and time. | |
5923 | Some day this should probably be implemented as an | |
5924 | assembler option, such that the kernel doesn't have to | |
5925 | use such ugly hacks, even though it will still have to | |
5926 | end up converting the binary to ELF32 for a number of | |
5927 | platforms whose boot loaders don't support ELF64 | |
5928 | binaries. */ | |
256ab948 TS |
5929 | if ((HAVE_64BIT_ADDRESSES |
5930 | && ! (offset_expr.X_op == O_constant | |
5931 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5932 | || (HAVE_64BIT_GPRS | |
5933 | && offset_expr.X_op == O_constant | |
5934 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 5935 | { |
e864ceca RS |
5936 | /* ??? We don't provide a GP-relative alternative for |
5937 | these macros. It used not to be possible with the | |
5938 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 5939 | |
460597ba | 5940 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 5941 | { |
67c0d1eb RS |
5942 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5943 | BFD_RELOC_MIPS_HIGHEST); | |
5944 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5945 | BFD_RELOC_HI16_S); | |
5946 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5947 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5948 | if (breg != 0) |
67c0d1eb RS |
5949 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5950 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5951 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5952 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5953 | tempreg); | |
d6bc6245 TS |
5954 | used_at = 1; |
5955 | } | |
5956 | else | |
5957 | { | |
67c0d1eb RS |
5958 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5959 | BFD_RELOC_MIPS_HIGHEST); | |
5960 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5961 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5962 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5963 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5964 | tempreg, BFD_RELOC_HI16_S); | |
5965 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5966 | if (breg != 0) |
67c0d1eb | 5967 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5968 | tempreg, tempreg, breg); |
67c0d1eb | 5969 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5970 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
5971 | } |
5972 | ||
5973 | return; | |
5974 | } | |
256ab948 TS |
5975 | |
5976 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 5977 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 5978 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 5979 | |
252b5132 RH |
5980 | if (breg == 0) |
5981 | { | |
67c0d1eb RS |
5982 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5983 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 5984 | { |
4d7206a2 | 5985 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5986 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5987 | mips_gp_register); | |
4d7206a2 | 5988 | relax_switch (); |
252b5132 RH |
5989 | used_at = 0; |
5990 | } | |
67c0d1eb RS |
5991 | macro_build_lui (&offset_expr, tempreg); |
5992 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5993 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5994 | if (mips_relax.sequence) |
5995 | relax_end (); | |
252b5132 RH |
5996 | } |
5997 | else | |
5998 | { | |
67c0d1eb RS |
5999 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6000 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6001 | { |
4d7206a2 | 6002 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6004 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6005 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6006 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6007 | relax_switch (); |
252b5132 | 6008 | } |
67c0d1eb RS |
6009 | macro_build_lui (&offset_expr, tempreg); |
6010 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6011 | tempreg, tempreg, breg); |
67c0d1eb | 6012 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6013 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6014 | if (mips_relax.sequence) |
6015 | relax_end (); | |
252b5132 RH |
6016 | } |
6017 | } | |
6018 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6019 | { | |
ed6fb7bd | 6020 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6021 | |
252b5132 RH |
6022 | /* If this is a reference to an external symbol, we want |
6023 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6024 | nop | |
6025 | <op> $treg,0($tempreg) | |
6026 | Otherwise we want | |
6027 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6028 | nop | |
6029 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6030 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6031 | |
6032 | For NewABI, we want | |
6033 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6034 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6035 | ||
252b5132 RH |
6036 | If there is a base register, we add it to $tempreg before |
6037 | the <op>. If there is a constant, we stick it in the | |
6038 | <op> instruction. We don't handle constants larger than | |
6039 | 16 bits, because we have no way to load the upper 16 bits | |
6040 | (actually, we could handle them for the subset of cases | |
6041 | in which we are not using $at). */ | |
6042 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6043 | if (HAVE_NEWABI) |
6044 | { | |
67c0d1eb RS |
6045 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6046 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6047 | if (breg != 0) |
67c0d1eb | 6048 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6049 | tempreg, tempreg, breg); |
67c0d1eb | 6050 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6051 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6052 | |
6053 | if (! used_at) | |
6054 | return; | |
6055 | ||
6056 | break; | |
6057 | } | |
252b5132 RH |
6058 | expr1.X_add_number = offset_expr.X_add_number; |
6059 | offset_expr.X_add_number = 0; | |
6060 | if (expr1.X_add_number < -0x8000 | |
6061 | || expr1.X_add_number >= 0x8000) | |
6062 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6063 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6064 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6065 | load_delay_nop (); |
4d7206a2 RS |
6066 | relax_start (offset_expr.X_add_symbol); |
6067 | relax_switch (); | |
67c0d1eb RS |
6068 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6069 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6070 | relax_end (); |
252b5132 | 6071 | if (breg != 0) |
67c0d1eb | 6072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6073 | tempreg, tempreg, breg); |
67c0d1eb | 6074 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6075 | } |
f5040a92 | 6076 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6077 | { |
67c0d1eb | 6078 | int gpdelay; |
252b5132 RH |
6079 | |
6080 | /* If this is a reference to an external symbol, we want | |
6081 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6082 | addu $tempreg,$tempreg,$gp | |
6083 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6084 | <op> $treg,0($tempreg) | |
6085 | Otherwise we want | |
6086 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6087 | nop | |
6088 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6089 | <op> $treg,0($tempreg) | |
6090 | If there is a base register, we add it to $tempreg before | |
6091 | the <op>. If there is a constant, we stick it in the | |
6092 | <op> instruction. We don't handle constants larger than | |
6093 | 16 bits, because we have no way to load the upper 16 bits | |
6094 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6095 | in which we are not using $at). */ |
252b5132 RH |
6096 | assert (offset_expr.X_op == O_symbol); |
6097 | expr1.X_add_number = offset_expr.X_add_number; | |
6098 | offset_expr.X_add_number = 0; | |
6099 | if (expr1.X_add_number < -0x8000 | |
6100 | || expr1.X_add_number >= 0x8000) | |
6101 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6102 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6103 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6104 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6105 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6106 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6107 | mips_gp_register); | |
6108 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6109 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6110 | relax_switch (); |
67c0d1eb RS |
6111 | if (gpdelay) |
6112 | macro_build (NULL, "nop", ""); | |
6113 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6114 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6115 | load_delay_nop (); |
67c0d1eb RS |
6116 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6117 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6118 | relax_end (); |
6119 | ||
252b5132 | 6120 | if (breg != 0) |
67c0d1eb | 6121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6122 | tempreg, tempreg, breg); |
67c0d1eb | 6123 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6124 | } |
f5040a92 AO |
6125 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6126 | { | |
f5040a92 AO |
6127 | /* If this is a reference to an external symbol, we want |
6128 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6129 | add $tempreg,$tempreg,$gp | |
6130 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6131 | <op> $treg,<ofst>($tempreg) | |
6132 | Otherwise, for local symbols, we want: | |
6133 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6134 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6135 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6136 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6137 | offset_expr.X_add_number = 0; |
6138 | if (expr1.X_add_number < -0x8000 | |
6139 | || expr1.X_add_number >= 0x8000) | |
6140 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6141 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6142 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6143 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6145 | mips_gp_register); | |
6146 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6147 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6148 | if (breg != 0) |
67c0d1eb | 6149 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6150 | tempreg, tempreg, breg); |
67c0d1eb | 6151 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6152 | |
4d7206a2 | 6153 | relax_switch (); |
f5040a92 | 6154 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6155 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6156 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6157 | if (breg != 0) |
67c0d1eb | 6158 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6159 | tempreg, tempreg, breg); |
67c0d1eb | 6160 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6161 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6162 | relax_end (); |
f5040a92 | 6163 | } |
252b5132 RH |
6164 | else |
6165 | abort (); | |
6166 | ||
6167 | if (! used_at) | |
6168 | return; | |
6169 | ||
6170 | break; | |
6171 | ||
6172 | case M_LI: | |
6173 | case M_LI_S: | |
67c0d1eb | 6174 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6175 | return; |
6176 | ||
6177 | case M_DLI: | |
67c0d1eb | 6178 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6179 | return; |
6180 | ||
6181 | case M_LI_SS: | |
6182 | if (imm_expr.X_op == O_constant) | |
6183 | { | |
67c0d1eb RS |
6184 | load_register (AT, &imm_expr, 0); |
6185 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6186 | break; |
6187 | } | |
6188 | else | |
6189 | { | |
6190 | assert (offset_expr.X_op == O_symbol | |
6191 | && strcmp (segment_name (S_GET_SEGMENT | |
6192 | (offset_expr.X_add_symbol)), | |
6193 | ".lit4") == 0 | |
6194 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6195 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6196 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6197 | return; |
6198 | } | |
6199 | ||
6200 | case M_LI_D: | |
ca4e0257 RS |
6201 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6202 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6203 | order 32 bits of the value and the low order 32 bits are either | |
6204 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6205 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6206 | { | |
ca4e0257 | 6207 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6208 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6209 | else |
6210 | { | |
6211 | int hreg, lreg; | |
6212 | ||
6213 | if (target_big_endian) | |
6214 | { | |
6215 | hreg = treg; | |
6216 | lreg = treg + 1; | |
6217 | } | |
6218 | else | |
6219 | { | |
6220 | hreg = treg + 1; | |
6221 | lreg = treg; | |
6222 | } | |
6223 | ||
6224 | if (hreg <= 31) | |
67c0d1eb | 6225 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6226 | if (lreg <= 31) |
6227 | { | |
6228 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6229 | move_register (lreg, 0); |
252b5132 RH |
6230 | else |
6231 | { | |
6232 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6233 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6234 | } |
6235 | } | |
6236 | } | |
6237 | return; | |
6238 | } | |
6239 | ||
6240 | /* We know that sym is in the .rdata section. First we get the | |
6241 | upper 16 bits of the address. */ | |
6242 | if (mips_pic == NO_PIC) | |
6243 | { | |
67c0d1eb | 6244 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6245 | } |
6246 | else if (mips_pic == SVR4_PIC) | |
6247 | { | |
67c0d1eb RS |
6248 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6249 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6250 | } |
252b5132 RH |
6251 | else |
6252 | abort (); | |
bdaaa2e1 | 6253 | |
252b5132 | 6254 | /* Now we load the register(s). */ |
ca4e0257 | 6255 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6256 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6257 | else |
6258 | { | |
67c0d1eb | 6259 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6260 | if (treg != RA) |
252b5132 RH |
6261 | { |
6262 | /* FIXME: How in the world do we deal with the possible | |
6263 | overflow here? */ | |
6264 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6265 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6266 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6267 | } |
6268 | } | |
252b5132 RH |
6269 | break; |
6270 | ||
6271 | case M_LI_DD: | |
ca4e0257 RS |
6272 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6273 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6274 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6275 | the value and the low order 32 bits are either zero or in | |
6276 | OFFSET_EXPR. */ | |
252b5132 RH |
6277 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6278 | { | |
67c0d1eb | 6279 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6280 | if (HAVE_64BIT_FPRS) |
6281 | { | |
6282 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6283 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6284 | } |
252b5132 RH |
6285 | else |
6286 | { | |
67c0d1eb | 6287 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6288 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6289 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6290 | else |
6291 | { | |
6292 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6293 | load_register (AT, &offset_expr, 0); |
6294 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6295 | } |
6296 | } | |
6297 | break; | |
6298 | } | |
6299 | ||
6300 | assert (offset_expr.X_op == O_symbol | |
6301 | && offset_expr.X_add_number == 0); | |
6302 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6303 | if (strcmp (s, ".lit8") == 0) | |
6304 | { | |
e7af610e | 6305 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6306 | { |
67c0d1eb | 6307 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6308 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6309 | return; |
6310 | } | |
c9914766 | 6311 | breg = mips_gp_register; |
252b5132 RH |
6312 | r = BFD_RELOC_MIPS_LITERAL; |
6313 | goto dob; | |
6314 | } | |
6315 | else | |
6316 | { | |
6317 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6318 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6319 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6320 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6321 | else |
6322 | { | |
6323 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6324 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6325 | } |
bdaaa2e1 | 6326 | |
e7af610e | 6327 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6328 | { |
67c0d1eb RS |
6329 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6330 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6331 | break; |
6332 | } | |
6333 | breg = AT; | |
6334 | r = BFD_RELOC_LO16; | |
6335 | goto dob; | |
6336 | } | |
6337 | ||
6338 | case M_L_DOB: | |
fef14a42 | 6339 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6340 | { |
6341 | as_bad (_("opcode not supported on this processor")); | |
6342 | return; | |
6343 | } | |
6344 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6345 | to adjust when loading from memory. */ | |
6346 | r = BFD_RELOC_LO16; | |
6347 | dob: | |
e7af610e | 6348 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6349 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6350 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6351 | /* FIXME: A possible overflow which I don't know how to deal |
6352 | with. */ | |
6353 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6354 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6355 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6356 | |
252b5132 RH |
6357 | if (breg != AT) |
6358 | return; | |
6359 | break; | |
6360 | ||
6361 | case M_L_DAB: | |
6362 | /* | |
6363 | * The MIPS assembler seems to check for X_add_number not | |
6364 | * being double aligned and generating: | |
6365 | * lui at,%hi(foo+1) | |
6366 | * addu at,at,v1 | |
6367 | * addiu at,at,%lo(foo+1) | |
6368 | * lwc1 f2,0(at) | |
6369 | * lwc1 f3,4(at) | |
6370 | * But, the resulting address is the same after relocation so why | |
6371 | * generate the extra instruction? | |
6372 | */ | |
fef14a42 | 6373 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6374 | { |
6375 | as_bad (_("opcode not supported on this processor")); | |
6376 | return; | |
6377 | } | |
bdaaa2e1 | 6378 | /* Itbl support may require additional care here. */ |
252b5132 | 6379 | coproc = 1; |
e7af610e | 6380 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6381 | { |
6382 | s = "ldc1"; | |
6383 | goto ld; | |
6384 | } | |
6385 | ||
6386 | s = "lwc1"; | |
6387 | fmt = "T,o(b)"; | |
6388 | goto ldd_std; | |
6389 | ||
6390 | case M_S_DAB: | |
fef14a42 | 6391 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6392 | { |
6393 | as_bad (_("opcode not supported on this processor")); | |
6394 | return; | |
6395 | } | |
6396 | ||
e7af610e | 6397 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6398 | { |
6399 | s = "sdc1"; | |
6400 | goto st; | |
6401 | } | |
6402 | ||
6403 | s = "swc1"; | |
6404 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6405 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6406 | coproc = 1; |
6407 | goto ldd_std; | |
6408 | ||
6409 | case M_LD_AB: | |
ca4e0257 | 6410 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6411 | { |
6412 | s = "ld"; | |
6413 | goto ld; | |
6414 | } | |
6415 | ||
6416 | s = "lw"; | |
6417 | fmt = "t,o(b)"; | |
6418 | goto ldd_std; | |
6419 | ||
6420 | case M_SD_AB: | |
ca4e0257 | 6421 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6422 | { |
6423 | s = "sd"; | |
6424 | goto st; | |
6425 | } | |
6426 | ||
6427 | s = "sw"; | |
6428 | fmt = "t,o(b)"; | |
6429 | ||
6430 | ldd_std: | |
6431 | if (offset_expr.X_op != O_symbol | |
6432 | && offset_expr.X_op != O_constant) | |
6433 | { | |
6434 | as_bad (_("expression too complex")); | |
6435 | offset_expr.X_op = O_constant; | |
6436 | } | |
6437 | ||
6438 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6439 | to adjust when loading from memory. We set coproc if we must | |
6440 | load $fn+1 first. */ | |
bdaaa2e1 | 6441 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6442 | if (! target_big_endian) |
6443 | coproc = 0; | |
6444 | ||
6445 | if (mips_pic == NO_PIC | |
6446 | || offset_expr.X_op == O_constant) | |
6447 | { | |
6448 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6449 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6450 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6451 | If we have a base register, we use this |
6452 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6453 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6454 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6455 | If this is not a GP relative symbol, we want |
6456 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6457 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6458 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6459 | If there is a base register, we add it to $at after the | |
6460 | lui instruction. If there is a constant, we always use | |
6461 | the last case. */ | |
e7d556df | 6462 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6463 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6464 | used_at = 1; |
252b5132 RH |
6465 | else |
6466 | { | |
4d7206a2 | 6467 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6468 | if (breg == 0) |
6469 | { | |
c9914766 | 6470 | tempreg = mips_gp_register; |
252b5132 RH |
6471 | used_at = 0; |
6472 | } | |
6473 | else | |
6474 | { | |
67c0d1eb | 6475 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6476 | AT, breg, mips_gp_register); |
252b5132 | 6477 | tempreg = AT; |
252b5132 RH |
6478 | used_at = 1; |
6479 | } | |
6480 | ||
beae10d5 | 6481 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6482 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6483 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6484 | offset_expr.X_add_number += 4; |
6485 | ||
6486 | /* Set mips_optimize to 2 to avoid inserting an | |
6487 | undesired nop. */ | |
6488 | hold_mips_optimize = mips_optimize; | |
6489 | mips_optimize = 2; | |
beae10d5 | 6490 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6491 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6492 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6493 | mips_optimize = hold_mips_optimize; |
6494 | ||
4d7206a2 | 6495 | relax_switch (); |
252b5132 RH |
6496 | |
6497 | /* We just generated two relocs. When tc_gen_reloc | |
6498 | handles this case, it will skip the first reloc and | |
6499 | handle the second. The second reloc already has an | |
6500 | extra addend of 4, which we added above. We must | |
6501 | subtract it out, and then subtract another 4 to make | |
6502 | the first reloc come out right. The second reloc | |
6503 | will come out right because we are going to add 4 to | |
6504 | offset_expr when we build its instruction below. | |
6505 | ||
6506 | If we have a symbol, then we don't want to include | |
6507 | the offset, because it will wind up being included | |
6508 | when we generate the reloc. */ | |
6509 | ||
6510 | if (offset_expr.X_op == O_constant) | |
6511 | offset_expr.X_add_number -= 8; | |
6512 | else | |
6513 | { | |
6514 | offset_expr.X_add_number = -4; | |
6515 | offset_expr.X_op = O_constant; | |
6516 | } | |
6517 | } | |
67c0d1eb | 6518 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6519 | if (breg != 0) |
67c0d1eb | 6520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6521 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6522 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6523 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6524 | /* FIXME: How do we handle overflow here? */ |
6525 | offset_expr.X_add_number += 4; | |
beae10d5 | 6526 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6527 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6528 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6529 | if (mips_relax.sequence) |
6530 | relax_end (); | |
bdaaa2e1 | 6531 | } |
252b5132 RH |
6532 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6533 | { | |
252b5132 RH |
6534 | /* If this is a reference to an external symbol, we want |
6535 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6536 | nop | |
6537 | <op> $treg,0($at) | |
6538 | <op> $treg+1,4($at) | |
6539 | Otherwise we want | |
6540 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6541 | nop | |
6542 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6543 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6544 | If there is a base register we add it to $at before the | |
6545 | lwc1 instructions. If there is a constant we include it | |
6546 | in the lwc1 instructions. */ | |
6547 | used_at = 1; | |
6548 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6549 | if (expr1.X_add_number < -0x8000 |
6550 | || expr1.X_add_number >= 0x8000 - 4) | |
6551 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6552 | load_got_offset (AT, &offset_expr); |
269137b2 | 6553 | load_delay_nop (); |
252b5132 | 6554 | if (breg != 0) |
67c0d1eb | 6555 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6556 | |
6557 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6558 | nop. */ | |
6559 | hold_mips_optimize = mips_optimize; | |
6560 | mips_optimize = 2; | |
4d7206a2 | 6561 | |
beae10d5 | 6562 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6563 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6564 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6565 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6566 | expr1.X_add_number += 4; |
67c0d1eb RS |
6567 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6568 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6569 | relax_switch (); |
67c0d1eb RS |
6570 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6571 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6572 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6573 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6574 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6575 | relax_end (); |
252b5132 | 6576 | |
4d7206a2 | 6577 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6578 | } |
6579 | else if (mips_pic == SVR4_PIC) | |
6580 | { | |
67c0d1eb | 6581 | int gpdelay; |
252b5132 RH |
6582 | |
6583 | /* If this is a reference to an external symbol, we want | |
6584 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6585 | addu $at,$at,$gp | |
6586 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6587 | nop | |
6588 | <op> $treg,0($at) | |
6589 | <op> $treg+1,4($at) | |
6590 | Otherwise we want | |
6591 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6592 | nop | |
6593 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6594 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6595 | If there is a base register we add it to $at before the | |
6596 | lwc1 instructions. If there is a constant we include it | |
6597 | in the lwc1 instructions. */ | |
6598 | used_at = 1; | |
6599 | expr1.X_add_number = offset_expr.X_add_number; | |
6600 | offset_expr.X_add_number = 0; | |
6601 | if (expr1.X_add_number < -0x8000 | |
6602 | || expr1.X_add_number >= 0x8000 - 4) | |
6603 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6604 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6605 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6606 | macro_build (&offset_expr, "lui", "t,u", |
6607 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6608 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6609 | AT, AT, mips_gp_register); |
67c0d1eb | 6610 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6611 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6612 | load_delay_nop (); |
252b5132 | 6613 | if (breg != 0) |
67c0d1eb | 6614 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6615 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6616 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6617 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6618 | expr1.X_add_number += 4; |
6619 | ||
6620 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6621 | nop. */ | |
6622 | hold_mips_optimize = mips_optimize; | |
6623 | mips_optimize = 2; | |
beae10d5 | 6624 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6625 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6626 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6627 | mips_optimize = hold_mips_optimize; |
6628 | expr1.X_add_number -= 4; | |
6629 | ||
4d7206a2 RS |
6630 | relax_switch (); |
6631 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6632 | if (gpdelay) |
6633 | macro_build (NULL, "nop", ""); | |
6634 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6635 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6636 | load_delay_nop (); |
252b5132 | 6637 | if (breg != 0) |
67c0d1eb | 6638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6639 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6640 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6641 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6642 | offset_expr.X_add_number += 4; |
252b5132 RH |
6643 | |
6644 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6645 | nop. */ | |
6646 | hold_mips_optimize = mips_optimize; | |
6647 | mips_optimize = 2; | |
beae10d5 | 6648 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6649 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6650 | BFD_RELOC_LO16, AT); | |
252b5132 | 6651 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6652 | relax_end (); |
252b5132 | 6653 | } |
252b5132 RH |
6654 | else |
6655 | abort (); | |
6656 | ||
6657 | if (! used_at) | |
6658 | return; | |
6659 | ||
6660 | break; | |
6661 | ||
6662 | case M_LD_OB: | |
6663 | s = "lw"; | |
6664 | goto sd_ob; | |
6665 | case M_SD_OB: | |
6666 | s = "sw"; | |
6667 | sd_ob: | |
ca4e0257 | 6668 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6669 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6670 | offset_expr.X_add_number += 4; |
67c0d1eb | 6671 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6672 | return; |
6673 | ||
6674 | /* New code added to support COPZ instructions. | |
6675 | This code builds table entries out of the macros in mip_opcodes. | |
6676 | R4000 uses interlocks to handle coproc delays. | |
6677 | Other chips (like the R3000) require nops to be inserted for delays. | |
6678 | ||
f72c8c98 | 6679 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6680 | In order to fill delay slots for non-interlocked chips, |
6681 | we must have a way to specify delays based on the coprocessor. | |
6682 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6683 | What are the side-effects of the cop instruction? | |
6684 | What cache support might we have and what are its effects? | |
6685 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6686 | What registers are read/set/modified? |
252b5132 RH |
6687 | |
6688 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6689 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6690 | |
6691 | case M_COP0: | |
6692 | s = "c0"; | |
6693 | goto copz; | |
6694 | case M_COP1: | |
6695 | s = "c1"; | |
6696 | goto copz; | |
6697 | case M_COP2: | |
6698 | s = "c2"; | |
6699 | goto copz; | |
6700 | case M_COP3: | |
6701 | s = "c3"; | |
6702 | copz: | |
6703 | /* For now we just do C (same as Cz). The parameter will be | |
6704 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6705 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6706 | return; |
6707 | ||
ea1fb5dc | 6708 | case M_MOVE: |
67c0d1eb | 6709 | move_register (dreg, sreg); |
ea1fb5dc RS |
6710 | return; |
6711 | ||
252b5132 RH |
6712 | #ifdef LOSING_COMPILER |
6713 | default: | |
6714 | /* Try and see if this is a new itbl instruction. | |
6715 | This code builds table entries out of the macros in mip_opcodes. | |
6716 | FIXME: For now we just assemble the expression and pass it's | |
6717 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6718 | We may want to have the assembler assemble this value, |
252b5132 RH |
6719 | so that we gain the assembler's knowledge of delay slots, |
6720 | symbols, etc. | |
6721 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6722 | if (itbl_have_entries |
252b5132 | 6723 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6724 | { |
252b5132 RH |
6725 | s = ip->insn_mo->name; |
6726 | s2 = "cop3"; | |
6727 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6728 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6729 | return; |
beae10d5 | 6730 | } |
252b5132 RH |
6731 | macro2 (ip); |
6732 | return; | |
6733 | } | |
6734 | if (mips_opts.noat) | |
6735 | as_warn (_("Macro used $at after \".set noat\"")); | |
6736 | } | |
bdaaa2e1 | 6737 | |
252b5132 | 6738 | static void |
17a2f251 | 6739 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6740 | { |
6741 | register int treg, sreg, dreg, breg; | |
6742 | int tempreg; | |
6743 | int mask; | |
252b5132 RH |
6744 | int used_at; |
6745 | expressionS expr1; | |
6746 | const char *s; | |
6747 | const char *s2; | |
6748 | const char *fmt; | |
6749 | int likely = 0; | |
6750 | int dbl = 0; | |
6751 | int coproc = 0; | |
6752 | int lr = 0; | |
6753 | int imm = 0; | |
6754 | int off; | |
6755 | offsetT maxnum; | |
6756 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6757 | |
252b5132 RH |
6758 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6759 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6760 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6761 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6762 | |
252b5132 RH |
6763 | expr1.X_op = O_constant; |
6764 | expr1.X_op_symbol = NULL; | |
6765 | expr1.X_add_symbol = NULL; | |
6766 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6767 | |
252b5132 RH |
6768 | switch (mask) |
6769 | { | |
6770 | #endif /* LOSING_COMPILER */ | |
6771 | ||
6772 | case M_DMUL: | |
6773 | dbl = 1; | |
6774 | case M_MUL: | |
67c0d1eb RS |
6775 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6776 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6777 | return; |
6778 | ||
6779 | case M_DMUL_I: | |
6780 | dbl = 1; | |
6781 | case M_MUL_I: | |
6782 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6783 | not trying to be that fancy. GCC should do this for us | |
6784 | anyway. */ | |
67c0d1eb RS |
6785 | load_register (AT, &imm_expr, dbl); |
6786 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6787 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6788 | break; |
6789 | ||
6790 | case M_DMULO_I: | |
6791 | dbl = 1; | |
6792 | case M_MULO_I: | |
6793 | imm = 1; | |
6794 | goto do_mulo; | |
6795 | ||
6796 | case M_DMULO: | |
6797 | dbl = 1; | |
6798 | case M_MULO: | |
6799 | do_mulo: | |
b34976b6 | 6800 | mips_emit_delays (TRUE); |
252b5132 RH |
6801 | ++mips_opts.noreorder; |
6802 | mips_any_noreorder = 1; | |
6803 | if (imm) | |
67c0d1eb RS |
6804 | load_register (AT, &imm_expr, dbl); |
6805 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6806 | macro_build (NULL, "mflo", "d", dreg); | |
6807 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6808 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6809 | if (mips_trap) |
67c0d1eb | 6810 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6811 | else |
6812 | { | |
6813 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6814 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6815 | macro_build (NULL, "nop", "", 0); | |
6816 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6817 | } |
6818 | --mips_opts.noreorder; | |
67c0d1eb | 6819 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6820 | break; |
6821 | ||
6822 | case M_DMULOU_I: | |
6823 | dbl = 1; | |
6824 | case M_MULOU_I: | |
6825 | imm = 1; | |
6826 | goto do_mulou; | |
6827 | ||
6828 | case M_DMULOU: | |
6829 | dbl = 1; | |
6830 | case M_MULOU: | |
6831 | do_mulou: | |
b34976b6 | 6832 | mips_emit_delays (TRUE); |
252b5132 RH |
6833 | ++mips_opts.noreorder; |
6834 | mips_any_noreorder = 1; | |
6835 | if (imm) | |
67c0d1eb RS |
6836 | load_register (AT, &imm_expr, dbl); |
6837 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6838 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6839 | macro_build (NULL, "mfhi", "d", AT); |
6840 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6841 | if (mips_trap) |
67c0d1eb | 6842 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6843 | else |
6844 | { | |
6845 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6846 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6847 | macro_build (NULL, "nop", "", 0); | |
6848 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6849 | } |
6850 | --mips_opts.noreorder; | |
6851 | break; | |
6852 | ||
771c7ce4 | 6853 | case M_DROL: |
fef14a42 | 6854 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6855 | { |
6856 | if (dreg == sreg) | |
6857 | { | |
6858 | tempreg = AT; | |
6859 | used_at = 1; | |
6860 | } | |
6861 | else | |
6862 | { | |
6863 | tempreg = dreg; | |
6864 | used_at = 0; | |
6865 | } | |
67c0d1eb RS |
6866 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6867 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6868 | if (used_at) |
6869 | break; | |
6870 | return; | |
6871 | } | |
67c0d1eb RS |
6872 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6873 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6874 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6875 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6876 | break; |
6877 | ||
252b5132 | 6878 | case M_ROL: |
fef14a42 | 6879 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6880 | { |
6881 | if (dreg == sreg) | |
6882 | { | |
6883 | tempreg = AT; | |
6884 | used_at = 1; | |
6885 | } | |
6886 | else | |
6887 | { | |
6888 | tempreg = dreg; | |
6889 | used_at = 0; | |
6890 | } | |
67c0d1eb RS |
6891 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6892 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
6893 | if (used_at) |
6894 | break; | |
6895 | return; | |
6896 | } | |
67c0d1eb RS |
6897 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6898 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6899 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6900 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6901 | break; |
6902 | ||
771c7ce4 TS |
6903 | case M_DROL_I: |
6904 | { | |
6905 | unsigned int rot; | |
82dd0097 | 6906 | char *l, *r; |
771c7ce4 TS |
6907 | |
6908 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6909 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6910 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6911 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6912 | { |
6913 | rot = (64 - rot) & 0x3f; | |
6914 | if (rot >= 32) | |
67c0d1eb | 6915 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6916 | else |
67c0d1eb | 6917 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 6918 | return; |
60b63b72 | 6919 | } |
483fc7cd | 6920 | if (rot == 0) |
483fc7cd | 6921 | { |
67c0d1eb | 6922 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6923 | return; |
483fc7cd | 6924 | } |
82dd0097 CD |
6925 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6926 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6927 | rot &= 0x1f; | |
67c0d1eb RS |
6928 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6929 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6930 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6931 | } |
6932 | break; | |
6933 | ||
252b5132 | 6934 | case M_ROL_I: |
771c7ce4 TS |
6935 | { |
6936 | unsigned int rot; | |
6937 | ||
6938 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6939 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6940 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6941 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6942 | { |
67c0d1eb | 6943 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 6944 | return; |
60b63b72 | 6945 | } |
483fc7cd | 6946 | if (rot == 0) |
483fc7cd | 6947 | { |
67c0d1eb | 6948 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 6949 | return; |
483fc7cd | 6950 | } |
67c0d1eb RS |
6951 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6952 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6953 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6954 | } |
6955 | break; | |
6956 | ||
6957 | case M_DROR: | |
fef14a42 | 6958 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6959 | { |
67c0d1eb | 6960 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6961 | return; |
6962 | } | |
67c0d1eb RS |
6963 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6964 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6965 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6966 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6967 | break; |
6968 | ||
6969 | case M_ROR: | |
fef14a42 | 6970 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6971 | { |
67c0d1eb | 6972 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
6973 | return; |
6974 | } | |
67c0d1eb RS |
6975 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6976 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6977 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6978 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6979 | break; |
6980 | ||
771c7ce4 TS |
6981 | case M_DROR_I: |
6982 | { | |
6983 | unsigned int rot; | |
82dd0097 | 6984 | char *l, *r; |
771c7ce4 TS |
6985 | |
6986 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6987 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6988 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6989 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6990 | { |
6991 | if (rot >= 32) | |
67c0d1eb | 6992 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6993 | else |
67c0d1eb | 6994 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
6995 | return; |
6996 | } | |
483fc7cd | 6997 | if (rot == 0) |
483fc7cd | 6998 | { |
67c0d1eb | 6999 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7000 | return; |
483fc7cd | 7001 | } |
82dd0097 CD |
7002 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7003 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7004 | rot &= 0x1f; | |
67c0d1eb RS |
7005 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7006 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7007 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7008 | } |
7009 | break; | |
7010 | ||
252b5132 | 7011 | case M_ROR_I: |
771c7ce4 TS |
7012 | { |
7013 | unsigned int rot; | |
7014 | ||
7015 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7016 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7017 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7018 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7019 | { |
67c0d1eb | 7020 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7021 | return; |
7022 | } | |
483fc7cd | 7023 | if (rot == 0) |
483fc7cd | 7024 | { |
67c0d1eb | 7025 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7026 | return; |
483fc7cd | 7027 | } |
67c0d1eb RS |
7028 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7029 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7030 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7031 | } |
252b5132 RH |
7032 | break; |
7033 | ||
7034 | case M_S_DOB: | |
fef14a42 | 7035 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7036 | { |
7037 | as_bad (_("opcode not supported on this processor")); | |
7038 | return; | |
7039 | } | |
e7af610e | 7040 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7041 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7042 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7043 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7044 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7045 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7046 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7047 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7048 | return; |
7049 | ||
7050 | case M_SEQ: | |
7051 | if (sreg == 0) | |
67c0d1eb | 7052 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7053 | else if (treg == 0) |
67c0d1eb | 7054 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7055 | else |
7056 | { | |
67c0d1eb RS |
7057 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7058 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7059 | } |
7060 | return; | |
7061 | ||
7062 | case M_SEQ_I: | |
7063 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7064 | { | |
67c0d1eb | 7065 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7066 | return; |
7067 | } | |
7068 | if (sreg == 0) | |
7069 | { | |
7070 | as_warn (_("Instruction %s: result is always false"), | |
7071 | ip->insn_mo->name); | |
67c0d1eb | 7072 | move_register (dreg, 0); |
252b5132 RH |
7073 | return; |
7074 | } | |
7075 | if (imm_expr.X_op == O_constant | |
7076 | && imm_expr.X_add_number >= 0 | |
7077 | && imm_expr.X_add_number < 0x10000) | |
7078 | { | |
67c0d1eb | 7079 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7080 | used_at = 0; |
7081 | } | |
7082 | else if (imm_expr.X_op == O_constant | |
7083 | && imm_expr.X_add_number > -0x8000 | |
7084 | && imm_expr.X_add_number < 0) | |
7085 | { | |
7086 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7087 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7088 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7089 | used_at = 0; |
7090 | } | |
7091 | else | |
7092 | { | |
67c0d1eb RS |
7093 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7094 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7095 | used_at = 1; |
7096 | } | |
67c0d1eb | 7097 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7098 | if (used_at) |
7099 | break; | |
7100 | return; | |
7101 | ||
7102 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7103 | s = "slt"; | |
7104 | goto sge; | |
7105 | case M_SGEU: | |
7106 | s = "sltu"; | |
7107 | sge: | |
67c0d1eb RS |
7108 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7109 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7110 | return; |
7111 | ||
7112 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7113 | case M_SGEU_I: | |
7114 | if (imm_expr.X_op == O_constant | |
7115 | && imm_expr.X_add_number >= -0x8000 | |
7116 | && imm_expr.X_add_number < 0x8000) | |
7117 | { | |
67c0d1eb RS |
7118 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7119 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7120 | used_at = 0; |
7121 | } | |
7122 | else | |
7123 | { | |
67c0d1eb RS |
7124 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7125 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7126 | dreg, sreg, AT); | |
252b5132 RH |
7127 | used_at = 1; |
7128 | } | |
67c0d1eb | 7129 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7130 | if (used_at) |
7131 | break; | |
7132 | return; | |
7133 | ||
7134 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7135 | s = "slt"; | |
7136 | goto sgt; | |
7137 | case M_SGTU: | |
7138 | s = "sltu"; | |
7139 | sgt: | |
67c0d1eb | 7140 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7141 | return; |
7142 | ||
7143 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7144 | s = "slt"; | |
7145 | goto sgti; | |
7146 | case M_SGTU_I: | |
7147 | s = "sltu"; | |
7148 | sgti: | |
67c0d1eb RS |
7149 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7150 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7151 | break; |
7152 | ||
2396cfb9 | 7153 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7154 | s = "slt"; |
7155 | goto sle; | |
7156 | case M_SLEU: | |
7157 | s = "sltu"; | |
7158 | sle: | |
67c0d1eb RS |
7159 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7160 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7161 | return; |
7162 | ||
2396cfb9 | 7163 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7164 | s = "slt"; |
7165 | goto slei; | |
7166 | case M_SLEU_I: | |
7167 | s = "sltu"; | |
7168 | slei: | |
67c0d1eb RS |
7169 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7170 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7171 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7172 | break; |
7173 | ||
7174 | case M_SLT_I: | |
7175 | if (imm_expr.X_op == O_constant | |
7176 | && imm_expr.X_add_number >= -0x8000 | |
7177 | && imm_expr.X_add_number < 0x8000) | |
7178 | { | |
67c0d1eb | 7179 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7180 | return; |
7181 | } | |
67c0d1eb RS |
7182 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7183 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7184 | break; |
7185 | ||
7186 | case M_SLTU_I: | |
7187 | if (imm_expr.X_op == O_constant | |
7188 | && imm_expr.X_add_number >= -0x8000 | |
7189 | && imm_expr.X_add_number < 0x8000) | |
7190 | { | |
67c0d1eb | 7191 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7192 | BFD_RELOC_LO16); |
252b5132 RH |
7193 | return; |
7194 | } | |
67c0d1eb RS |
7195 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7196 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7197 | break; |
7198 | ||
7199 | case M_SNE: | |
7200 | if (sreg == 0) | |
67c0d1eb | 7201 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7202 | else if (treg == 0) |
67c0d1eb | 7203 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7204 | else |
7205 | { | |
67c0d1eb RS |
7206 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7207 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7208 | } |
7209 | return; | |
7210 | ||
7211 | case M_SNE_I: | |
7212 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7213 | { | |
67c0d1eb | 7214 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7215 | return; |
7216 | } | |
7217 | if (sreg == 0) | |
7218 | { | |
7219 | as_warn (_("Instruction %s: result is always true"), | |
7220 | ip->insn_mo->name); | |
67c0d1eb RS |
7221 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7222 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7223 | return; |
7224 | } | |
7225 | if (imm_expr.X_op == O_constant | |
7226 | && imm_expr.X_add_number >= 0 | |
7227 | && imm_expr.X_add_number < 0x10000) | |
7228 | { | |
67c0d1eb | 7229 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7230 | used_at = 0; |
7231 | } | |
7232 | else if (imm_expr.X_op == O_constant | |
7233 | && imm_expr.X_add_number > -0x8000 | |
7234 | && imm_expr.X_add_number < 0) | |
7235 | { | |
7236 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7237 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7238 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7239 | used_at = 0; |
7240 | } | |
7241 | else | |
7242 | { | |
67c0d1eb RS |
7243 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7244 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7245 | used_at = 1; |
7246 | } | |
67c0d1eb | 7247 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7248 | if (used_at) |
7249 | break; | |
7250 | return; | |
7251 | ||
7252 | case M_DSUB_I: | |
7253 | dbl = 1; | |
7254 | case M_SUB_I: | |
7255 | if (imm_expr.X_op == O_constant | |
7256 | && imm_expr.X_add_number > -0x8000 | |
7257 | && imm_expr.X_add_number <= 0x8000) | |
7258 | { | |
7259 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7260 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7261 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7262 | return; |
7263 | } | |
67c0d1eb RS |
7264 | load_register (AT, &imm_expr, dbl); |
7265 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7266 | break; |
7267 | ||
7268 | case M_DSUBU_I: | |
7269 | dbl = 1; | |
7270 | case M_SUBU_I: | |
7271 | if (imm_expr.X_op == O_constant | |
7272 | && imm_expr.X_add_number > -0x8000 | |
7273 | && imm_expr.X_add_number <= 0x8000) | |
7274 | { | |
7275 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7276 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7277 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7278 | return; |
7279 | } | |
67c0d1eb RS |
7280 | load_register (AT, &imm_expr, dbl); |
7281 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7282 | break; |
7283 | ||
7284 | case M_TEQ_I: | |
7285 | s = "teq"; | |
7286 | goto trap; | |
7287 | case M_TGE_I: | |
7288 | s = "tge"; | |
7289 | goto trap; | |
7290 | case M_TGEU_I: | |
7291 | s = "tgeu"; | |
7292 | goto trap; | |
7293 | case M_TLT_I: | |
7294 | s = "tlt"; | |
7295 | goto trap; | |
7296 | case M_TLTU_I: | |
7297 | s = "tltu"; | |
7298 | goto trap; | |
7299 | case M_TNE_I: | |
7300 | s = "tne"; | |
7301 | trap: | |
67c0d1eb RS |
7302 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7303 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7304 | break; |
7305 | ||
252b5132 | 7306 | case M_TRUNCWS: |
43841e91 | 7307 | case M_TRUNCWD: |
e7af610e | 7308 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7309 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7310 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7311 | ||
7312 | /* | |
7313 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7314 | * or is there a reason for it? | |
7315 | */ | |
b34976b6 | 7316 | mips_emit_delays (TRUE); |
252b5132 RH |
7317 | ++mips_opts.noreorder; |
7318 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7319 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7320 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7321 | macro_build (NULL, "nop", ""); | |
252b5132 | 7322 | expr1.X_add_number = 3; |
67c0d1eb | 7323 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7324 | expr1.X_add_number = 2; |
67c0d1eb RS |
7325 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7326 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7327 | macro_build (NULL, "nop", ""); | |
7328 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7329 | dreg, sreg); | |
7330 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7331 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7332 | --mips_opts.noreorder; |
7333 | break; | |
7334 | ||
7335 | case M_ULH: | |
7336 | s = "lb"; | |
7337 | goto ulh; | |
7338 | case M_ULHU: | |
7339 | s = "lbu"; | |
7340 | ulh: | |
7341 | if (offset_expr.X_add_number >= 0x7fff) | |
7342 | as_bad (_("operand overflow")); | |
252b5132 | 7343 | if (! target_big_endian) |
f9419b05 | 7344 | ++offset_expr.X_add_number; |
67c0d1eb | 7345 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7346 | if (! target_big_endian) |
f9419b05 | 7347 | --offset_expr.X_add_number; |
252b5132 | 7348 | else |
f9419b05 | 7349 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7350 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7351 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7352 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7353 | break; |
7354 | ||
7355 | case M_ULD: | |
7356 | s = "ldl"; | |
7357 | s2 = "ldr"; | |
7358 | off = 7; | |
7359 | goto ulw; | |
7360 | case M_ULW: | |
7361 | s = "lwl"; | |
7362 | s2 = "lwr"; | |
7363 | off = 3; | |
7364 | ulw: | |
7365 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7366 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7367 | if (treg != breg) |
7368 | tempreg = treg; | |
7369 | else | |
7370 | tempreg = AT; | |
252b5132 RH |
7371 | if (! target_big_endian) |
7372 | offset_expr.X_add_number += off; | |
67c0d1eb | 7373 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7374 | if (! target_big_endian) |
7375 | offset_expr.X_add_number -= off; | |
7376 | else | |
7377 | offset_expr.X_add_number += off; | |
67c0d1eb | 7378 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7379 | |
7380 | /* If necessary, move the result in tempreg the final destination. */ | |
7381 | if (treg == tempreg) | |
7382 | return; | |
7383 | /* Protect second load's delay slot. */ | |
017315e4 | 7384 | load_delay_nop (); |
67c0d1eb | 7385 | move_register (treg, tempreg); |
af22f5b2 | 7386 | break; |
252b5132 RH |
7387 | |
7388 | case M_ULD_A: | |
7389 | s = "ldl"; | |
7390 | s2 = "ldr"; | |
7391 | off = 7; | |
7392 | goto ulwa; | |
7393 | case M_ULW_A: | |
7394 | s = "lwl"; | |
7395 | s2 = "lwr"; | |
7396 | off = 3; | |
7397 | ulwa: | |
d6bc6245 | 7398 | used_at = 1; |
67c0d1eb | 7399 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7400 | if (breg != 0) |
67c0d1eb | 7401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7402 | if (! target_big_endian) |
7403 | expr1.X_add_number = off; | |
7404 | else | |
7405 | expr1.X_add_number = 0; | |
67c0d1eb | 7406 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7407 | if (! target_big_endian) |
7408 | expr1.X_add_number = 0; | |
7409 | else | |
7410 | expr1.X_add_number = off; | |
67c0d1eb | 7411 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7412 | break; |
7413 | ||
7414 | case M_ULH_A: | |
7415 | case M_ULHU_A: | |
d6bc6245 | 7416 | used_at = 1; |
67c0d1eb | 7417 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7418 | if (breg != 0) |
67c0d1eb | 7419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7420 | if (target_big_endian) |
7421 | expr1.X_add_number = 0; | |
67c0d1eb | 7422 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7423 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7424 | if (target_big_endian) |
7425 | expr1.X_add_number = 1; | |
7426 | else | |
7427 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7428 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7429 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7430 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7431 | break; |
7432 | ||
7433 | case M_USH: | |
7434 | if (offset_expr.X_add_number >= 0x7fff) | |
7435 | as_bad (_("operand overflow")); | |
7436 | if (target_big_endian) | |
f9419b05 | 7437 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7438 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7439 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7440 | if (target_big_endian) |
f9419b05 | 7441 | --offset_expr.X_add_number; |
252b5132 | 7442 | else |
f9419b05 | 7443 | ++offset_expr.X_add_number; |
67c0d1eb | 7444 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7445 | break; |
7446 | ||
7447 | case M_USD: | |
7448 | s = "sdl"; | |
7449 | s2 = "sdr"; | |
7450 | off = 7; | |
7451 | goto usw; | |
7452 | case M_USW: | |
7453 | s = "swl"; | |
7454 | s2 = "swr"; | |
7455 | off = 3; | |
7456 | usw: | |
7457 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7458 | as_bad (_("operand overflow")); | |
7459 | if (! target_big_endian) | |
7460 | offset_expr.X_add_number += off; | |
67c0d1eb | 7461 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7462 | if (! target_big_endian) |
7463 | offset_expr.X_add_number -= off; | |
7464 | else | |
7465 | offset_expr.X_add_number += off; | |
67c0d1eb | 7466 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7467 | return; |
7468 | ||
7469 | case M_USD_A: | |
7470 | s = "sdl"; | |
7471 | s2 = "sdr"; | |
7472 | off = 7; | |
7473 | goto uswa; | |
7474 | case M_USW_A: | |
7475 | s = "swl"; | |
7476 | s2 = "swr"; | |
7477 | off = 3; | |
7478 | uswa: | |
d6bc6245 | 7479 | used_at = 1; |
67c0d1eb | 7480 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7481 | if (breg != 0) |
67c0d1eb | 7482 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7483 | if (! target_big_endian) |
7484 | expr1.X_add_number = off; | |
7485 | else | |
7486 | expr1.X_add_number = 0; | |
67c0d1eb | 7487 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7488 | if (! target_big_endian) |
7489 | expr1.X_add_number = 0; | |
7490 | else | |
7491 | expr1.X_add_number = off; | |
67c0d1eb | 7492 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7493 | break; |
7494 | ||
7495 | case M_USH_A: | |
d6bc6245 | 7496 | used_at = 1; |
67c0d1eb | 7497 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7498 | if (breg != 0) |
67c0d1eb | 7499 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7500 | if (! target_big_endian) |
7501 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7502 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7503 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7504 | if (! target_big_endian) |
7505 | expr1.X_add_number = 1; | |
7506 | else | |
7507 | expr1.X_add_number = 0; | |
67c0d1eb | 7508 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7509 | if (! target_big_endian) |
7510 | expr1.X_add_number = 0; | |
7511 | else | |
7512 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7513 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7514 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7515 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7516 | break; |
7517 | ||
7518 | default: | |
7519 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7520 | are added dynamically. */ |
252b5132 RH |
7521 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7522 | break; | |
7523 | } | |
7524 | if (mips_opts.noat) | |
7525 | as_warn (_("Macro used $at after \".set noat\"")); | |
7526 | } | |
7527 | ||
7528 | /* Implement macros in mips16 mode. */ | |
7529 | ||
7530 | static void | |
17a2f251 | 7531 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7532 | { |
7533 | int mask; | |
7534 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7535 | expressionS expr1; |
7536 | int dbl; | |
7537 | const char *s, *s2, *s3; | |
7538 | ||
7539 | mask = ip->insn_mo->mask; | |
7540 | ||
7541 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7542 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7543 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7544 | ||
252b5132 RH |
7545 | expr1.X_op = O_constant; |
7546 | expr1.X_op_symbol = NULL; | |
7547 | expr1.X_add_symbol = NULL; | |
7548 | expr1.X_add_number = 1; | |
7549 | ||
7550 | dbl = 0; | |
7551 | ||
7552 | switch (mask) | |
7553 | { | |
7554 | default: | |
7555 | internalError (); | |
7556 | ||
7557 | case M_DDIV_3: | |
7558 | dbl = 1; | |
7559 | case M_DIV_3: | |
7560 | s = "mflo"; | |
7561 | goto do_div3; | |
7562 | case M_DREM_3: | |
7563 | dbl = 1; | |
7564 | case M_REM_3: | |
7565 | s = "mfhi"; | |
7566 | do_div3: | |
b34976b6 | 7567 | mips_emit_delays (TRUE); |
252b5132 RH |
7568 | ++mips_opts.noreorder; |
7569 | mips_any_noreorder = 1; | |
67c0d1eb | 7570 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7571 | expr1.X_add_number = 2; |
67c0d1eb RS |
7572 | macro_build (&expr1, "bnez", "x,p", yreg); |
7573 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7574 | |
252b5132 RH |
7575 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7576 | since that causes an overflow. We should do that as well, | |
7577 | but I don't see how to do the comparisons without a temporary | |
7578 | register. */ | |
7579 | --mips_opts.noreorder; | |
67c0d1eb | 7580 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7581 | break; |
7582 | ||
7583 | case M_DIVU_3: | |
7584 | s = "divu"; | |
7585 | s2 = "mflo"; | |
7586 | goto do_divu3; | |
7587 | case M_REMU_3: | |
7588 | s = "divu"; | |
7589 | s2 = "mfhi"; | |
7590 | goto do_divu3; | |
7591 | case M_DDIVU_3: | |
7592 | s = "ddivu"; | |
7593 | s2 = "mflo"; | |
7594 | goto do_divu3; | |
7595 | case M_DREMU_3: | |
7596 | s = "ddivu"; | |
7597 | s2 = "mfhi"; | |
7598 | do_divu3: | |
b34976b6 | 7599 | mips_emit_delays (TRUE); |
252b5132 RH |
7600 | ++mips_opts.noreorder; |
7601 | mips_any_noreorder = 1; | |
67c0d1eb | 7602 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7603 | expr1.X_add_number = 2; |
67c0d1eb RS |
7604 | macro_build (&expr1, "bnez", "x,p", yreg); |
7605 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7606 | --mips_opts.noreorder; |
67c0d1eb | 7607 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7608 | break; |
7609 | ||
7610 | case M_DMUL: | |
7611 | dbl = 1; | |
7612 | case M_MUL: | |
67c0d1eb RS |
7613 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7614 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7615 | return; |
7616 | ||
7617 | case M_DSUBU_I: | |
7618 | dbl = 1; | |
7619 | goto do_subu; | |
7620 | case M_SUBU_I: | |
7621 | do_subu: | |
7622 | if (imm_expr.X_op != O_constant) | |
7623 | as_bad (_("Unsupported large constant")); | |
7624 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7625 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7626 | break; |
7627 | ||
7628 | case M_SUBU_I_2: | |
7629 | if (imm_expr.X_op != O_constant) | |
7630 | as_bad (_("Unsupported large constant")); | |
7631 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7632 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7633 | break; |
7634 | ||
7635 | case M_DSUBU_I_2: | |
7636 | if (imm_expr.X_op != O_constant) | |
7637 | as_bad (_("Unsupported large constant")); | |
7638 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7639 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7640 | break; |
7641 | ||
7642 | case M_BEQ: | |
7643 | s = "cmp"; | |
7644 | s2 = "bteqz"; | |
7645 | goto do_branch; | |
7646 | case M_BNE: | |
7647 | s = "cmp"; | |
7648 | s2 = "btnez"; | |
7649 | goto do_branch; | |
7650 | case M_BLT: | |
7651 | s = "slt"; | |
7652 | s2 = "btnez"; | |
7653 | goto do_branch; | |
7654 | case M_BLTU: | |
7655 | s = "sltu"; | |
7656 | s2 = "btnez"; | |
7657 | goto do_branch; | |
7658 | case M_BLE: | |
7659 | s = "slt"; | |
7660 | s2 = "bteqz"; | |
7661 | goto do_reverse_branch; | |
7662 | case M_BLEU: | |
7663 | s = "sltu"; | |
7664 | s2 = "bteqz"; | |
7665 | goto do_reverse_branch; | |
7666 | case M_BGE: | |
7667 | s = "slt"; | |
7668 | s2 = "bteqz"; | |
7669 | goto do_branch; | |
7670 | case M_BGEU: | |
7671 | s = "sltu"; | |
7672 | s2 = "bteqz"; | |
7673 | goto do_branch; | |
7674 | case M_BGT: | |
7675 | s = "slt"; | |
7676 | s2 = "btnez"; | |
7677 | goto do_reverse_branch; | |
7678 | case M_BGTU: | |
7679 | s = "sltu"; | |
7680 | s2 = "btnez"; | |
7681 | ||
7682 | do_reverse_branch: | |
7683 | tmp = xreg; | |
7684 | xreg = yreg; | |
7685 | yreg = tmp; | |
7686 | ||
7687 | do_branch: | |
67c0d1eb RS |
7688 | macro_build (NULL, s, "x,y", xreg, yreg); |
7689 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7690 | break; |
7691 | ||
7692 | case M_BEQ_I: | |
7693 | s = "cmpi"; | |
7694 | s2 = "bteqz"; | |
7695 | s3 = "x,U"; | |
7696 | goto do_branch_i; | |
7697 | case M_BNE_I: | |
7698 | s = "cmpi"; | |
7699 | s2 = "btnez"; | |
7700 | s3 = "x,U"; | |
7701 | goto do_branch_i; | |
7702 | case M_BLT_I: | |
7703 | s = "slti"; | |
7704 | s2 = "btnez"; | |
7705 | s3 = "x,8"; | |
7706 | goto do_branch_i; | |
7707 | case M_BLTU_I: | |
7708 | s = "sltiu"; | |
7709 | s2 = "btnez"; | |
7710 | s3 = "x,8"; | |
7711 | goto do_branch_i; | |
7712 | case M_BLE_I: | |
7713 | s = "slti"; | |
7714 | s2 = "btnez"; | |
7715 | s3 = "x,8"; | |
7716 | goto do_addone_branch_i; | |
7717 | case M_BLEU_I: | |
7718 | s = "sltiu"; | |
7719 | s2 = "btnez"; | |
7720 | s3 = "x,8"; | |
7721 | goto do_addone_branch_i; | |
7722 | case M_BGE_I: | |
7723 | s = "slti"; | |
7724 | s2 = "bteqz"; | |
7725 | s3 = "x,8"; | |
7726 | goto do_branch_i; | |
7727 | case M_BGEU_I: | |
7728 | s = "sltiu"; | |
7729 | s2 = "bteqz"; | |
7730 | s3 = "x,8"; | |
7731 | goto do_branch_i; | |
7732 | case M_BGT_I: | |
7733 | s = "slti"; | |
7734 | s2 = "bteqz"; | |
7735 | s3 = "x,8"; | |
7736 | goto do_addone_branch_i; | |
7737 | case M_BGTU_I: | |
7738 | s = "sltiu"; | |
7739 | s2 = "bteqz"; | |
7740 | s3 = "x,8"; | |
7741 | ||
7742 | do_addone_branch_i: | |
7743 | if (imm_expr.X_op != O_constant) | |
7744 | as_bad (_("Unsupported large constant")); | |
7745 | ++imm_expr.X_add_number; | |
7746 | ||
7747 | do_branch_i: | |
67c0d1eb RS |
7748 | macro_build (&imm_expr, s, s3, xreg); |
7749 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7750 | break; |
7751 | ||
7752 | case M_ABS: | |
7753 | expr1.X_add_number = 0; | |
67c0d1eb | 7754 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7755 | if (xreg != yreg) |
67c0d1eb | 7756 | move_register (xreg, yreg); |
252b5132 | 7757 | expr1.X_add_number = 2; |
67c0d1eb RS |
7758 | macro_build (&expr1, "bteqz", "p"); |
7759 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7760 | } |
7761 | } | |
7762 | ||
7763 | /* For consistency checking, verify that all bits are specified either | |
7764 | by the match/mask part of the instruction definition, or by the | |
7765 | operand list. */ | |
7766 | static int | |
17a2f251 | 7767 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7768 | { |
7769 | const char *p = opc->args; | |
7770 | char c; | |
7771 | unsigned long used_bits = opc->mask; | |
7772 | ||
7773 | if ((used_bits & opc->match) != opc->match) | |
7774 | { | |
7775 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7776 | opc->name, opc->args); | |
7777 | return 0; | |
7778 | } | |
7779 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7780 | while (*p) | |
7781 | switch (c = *p++) | |
7782 | { | |
7783 | case ',': break; | |
7784 | case '(': break; | |
7785 | case ')': break; | |
af7ee8bf CD |
7786 | case '+': |
7787 | switch (c = *p++) | |
7788 | { | |
7789 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7790 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7791 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7792 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7793 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7794 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7795 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7796 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7797 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7798 | case 'I': break; | |
af7ee8bf CD |
7799 | default: |
7800 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7801 | c, opc->name, opc->args); | |
7802 | return 0; | |
7803 | } | |
7804 | break; | |
252b5132 RH |
7805 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7806 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7807 | case 'A': break; | |
4372b673 | 7808 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7809 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7810 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7811 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7812 | case 'F': break; | |
7813 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7814 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7815 | case 'I': break; |
e972090a | 7816 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7817 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7818 | case 'L': break; |
7819 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7820 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7821 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7822 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7823 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7824 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7825 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7826 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7827 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7828 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7829 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7830 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7831 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7832 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7833 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7834 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7835 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7836 | case 'f': break; | |
7837 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7838 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7839 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7840 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7841 | case 'l': break; | |
7842 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7843 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7844 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7845 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7846 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7847 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7848 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7849 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7850 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7851 | case 'x': break; | |
7852 | case 'z': break; | |
7853 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7854 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7855 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7856 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7857 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7858 | case '[': break; | |
7859 | case ']': break; | |
252b5132 RH |
7860 | default: |
7861 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7862 | c, opc->name, opc->args); | |
7863 | return 0; | |
7864 | } | |
7865 | #undef USE_BITS | |
7866 | if (used_bits != 0xffffffff) | |
7867 | { | |
7868 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7869 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7870 | return 0; | |
7871 | } | |
7872 | return 1; | |
7873 | } | |
7874 | ||
7875 | /* This routine assembles an instruction into its binary format. As a | |
7876 | side effect, it sets one of the global variables imm_reloc or | |
7877 | offset_reloc to the type of relocation to do if one of the operands | |
7878 | is an address expression. */ | |
7879 | ||
7880 | static void | |
17a2f251 | 7881 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7882 | { |
7883 | char *s; | |
7884 | const char *args; | |
43841e91 | 7885 | char c = 0; |
252b5132 RH |
7886 | struct mips_opcode *insn; |
7887 | char *argsStart; | |
7888 | unsigned int regno; | |
7889 | unsigned int lastregno = 0; | |
af7ee8bf | 7890 | unsigned int lastpos = 0; |
071742cf | 7891 | unsigned int limlo, limhi; |
252b5132 RH |
7892 | char *s_reset; |
7893 | char save_c = 0; | |
252b5132 RH |
7894 | |
7895 | insn_error = NULL; | |
7896 | ||
7897 | /* If the instruction contains a '.', we first try to match an instruction | |
7898 | including the '.'. Then we try again without the '.'. */ | |
7899 | insn = NULL; | |
3882b010 | 7900 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7901 | continue; |
7902 | ||
7903 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7904 | the call to hash_find. Save the character we replaced just in case we | |
7905 | have to re-parse the instruction. */ | |
3882b010 | 7906 | if (ISSPACE (*s)) |
252b5132 RH |
7907 | { |
7908 | save_c = *s; | |
7909 | *s++ = '\0'; | |
7910 | } | |
bdaaa2e1 | 7911 | |
252b5132 RH |
7912 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7913 | ||
7914 | /* If we didn't find the instruction in the opcode table, try again, but | |
7915 | this time with just the instruction up to, but not including the | |
7916 | first '.'. */ | |
7917 | if (insn == NULL) | |
7918 | { | |
bdaaa2e1 | 7919 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7920 | if (save_c) |
7921 | *(--s) = save_c; | |
7922 | ||
7923 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7924 | for (s = str; |
7925 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7926 | ++s) | |
252b5132 RH |
7927 | continue; |
7928 | ||
7929 | /* If we did not find a '.', then we can quit now. */ | |
7930 | if (*s != '.') | |
7931 | { | |
7932 | insn_error = "unrecognized opcode"; | |
7933 | return; | |
7934 | } | |
7935 | ||
7936 | /* Lookup the instruction in the hash table. */ | |
7937 | *s++ = '\0'; | |
7938 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7939 | { | |
7940 | insn_error = "unrecognized opcode"; | |
7941 | return; | |
7942 | } | |
252b5132 RH |
7943 | } |
7944 | ||
7945 | argsStart = s; | |
7946 | for (;;) | |
7947 | { | |
b34976b6 | 7948 | bfd_boolean ok; |
252b5132 RH |
7949 | |
7950 | assert (strcmp (insn->name, str) == 0); | |
7951 | ||
1f25f5d3 CD |
7952 | if (OPCODE_IS_MEMBER (insn, |
7953 | (mips_opts.isa | |
3396de36 | 7954 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7955 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7956 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7957 | mips_opts.arch)) |
b34976b6 | 7958 | ok = TRUE; |
bdaaa2e1 | 7959 | else |
b34976b6 | 7960 | ok = FALSE; |
bdaaa2e1 | 7961 | |
252b5132 RH |
7962 | if (insn->pinfo != INSN_MACRO) |
7963 | { | |
fef14a42 | 7964 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7965 | ok = FALSE; |
252b5132 RH |
7966 | } |
7967 | ||
7968 | if (! ok) | |
7969 | { | |
7970 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7971 | && strcmp (insn->name, insn[1].name) == 0) | |
7972 | { | |
7973 | ++insn; | |
7974 | continue; | |
7975 | } | |
252b5132 | 7976 | else |
beae10d5 | 7977 | { |
268f6bed L |
7978 | if (!insn_error) |
7979 | { | |
7980 | static char buf[100]; | |
fef14a42 TS |
7981 | sprintf (buf, |
7982 | _("opcode not supported on this processor: %s (%s)"), | |
7983 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7984 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7985 | insn_error = buf; |
7986 | } | |
7987 | if (save_c) | |
7988 | *(--s) = save_c; | |
2bd7f1f3 | 7989 | return; |
252b5132 | 7990 | } |
252b5132 RH |
7991 | } |
7992 | ||
7993 | ip->insn_mo = insn; | |
7994 | ip->insn_opcode = insn->match; | |
268f6bed | 7995 | insn_error = NULL; |
252b5132 RH |
7996 | for (args = insn->args;; ++args) |
7997 | { | |
deec1734 CD |
7998 | int is_mdmx; |
7999 | ||
ad8d3bb3 | 8000 | s += strspn (s, " \t"); |
deec1734 | 8001 | is_mdmx = 0; |
252b5132 RH |
8002 | switch (*args) |
8003 | { | |
8004 | case '\0': /* end of args */ | |
8005 | if (*s == '\0') | |
8006 | return; | |
8007 | break; | |
8008 | ||
8009 | case ',': | |
8010 | if (*s++ == *args) | |
8011 | continue; | |
8012 | s--; | |
8013 | switch (*++args) | |
8014 | { | |
8015 | case 'r': | |
8016 | case 'v': | |
38487616 | 8017 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8018 | continue; |
8019 | ||
8020 | case 'w': | |
38487616 TS |
8021 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8022 | continue; | |
8023 | ||
252b5132 | 8024 | case 'W': |
38487616 | 8025 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8026 | continue; |
8027 | ||
8028 | case 'V': | |
38487616 | 8029 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8030 | continue; |
8031 | } | |
8032 | break; | |
8033 | ||
8034 | case '(': | |
8035 | /* Handle optional base register. | |
8036 | Either the base register is omitted or | |
bdaaa2e1 | 8037 | we must have a left paren. */ |
252b5132 RH |
8038 | /* This is dependent on the next operand specifier |
8039 | is a base register specification. */ | |
8040 | assert (args[1] == 'b' || args[1] == '5' | |
8041 | || args[1] == '-' || args[1] == '4'); | |
8042 | if (*s == '\0') | |
8043 | return; | |
8044 | ||
8045 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8046 | case '[': |
8047 | case ']': | |
252b5132 RH |
8048 | if (*s++ == *args) |
8049 | continue; | |
8050 | break; | |
8051 | ||
af7ee8bf CD |
8052 | case '+': /* Opcode extension character. */ |
8053 | switch (*++args) | |
8054 | { | |
071742cf CD |
8055 | case 'A': /* ins/ext position, becomes LSB. */ |
8056 | limlo = 0; | |
8057 | limhi = 31; | |
5f74bc13 CD |
8058 | goto do_lsb; |
8059 | case 'E': | |
8060 | limlo = 32; | |
8061 | limhi = 63; | |
8062 | goto do_lsb; | |
8063 | do_lsb: | |
071742cf CD |
8064 | my_getExpression (&imm_expr, s); |
8065 | check_absolute_expr (ip, &imm_expr); | |
8066 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8067 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8068 | { | |
8069 | as_bad (_("Improper position (%lu)"), | |
8070 | (unsigned long) imm_expr.X_add_number); | |
8071 | imm_expr.X_add_number = limlo; | |
8072 | } | |
8073 | lastpos = imm_expr.X_add_number; | |
8074 | ip->insn_opcode |= (imm_expr.X_add_number | |
8075 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8076 | imm_expr.X_op = O_absent; | |
8077 | s = expr_end; | |
8078 | continue; | |
8079 | ||
8080 | case 'B': /* ins size, becomes MSB. */ | |
8081 | limlo = 1; | |
8082 | limhi = 32; | |
5f74bc13 CD |
8083 | goto do_msb; |
8084 | case 'F': | |
8085 | limlo = 33; | |
8086 | limhi = 64; | |
8087 | goto do_msb; | |
8088 | do_msb: | |
071742cf CD |
8089 | my_getExpression (&imm_expr, s); |
8090 | check_absolute_expr (ip, &imm_expr); | |
8091 | /* Check for negative input so that small negative numbers | |
8092 | will not succeed incorrectly. The checks against | |
8093 | (pos+size) transitively check "size" itself, | |
8094 | assuming that "pos" is reasonable. */ | |
8095 | if ((long) imm_expr.X_add_number < 0 | |
8096 | || ((unsigned long) imm_expr.X_add_number | |
8097 | + lastpos) < limlo | |
8098 | || ((unsigned long) imm_expr.X_add_number | |
8099 | + lastpos) > limhi) | |
8100 | { | |
8101 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8102 | (unsigned long) imm_expr.X_add_number, | |
8103 | (unsigned long) lastpos); | |
8104 | imm_expr.X_add_number = limlo - lastpos; | |
8105 | } | |
8106 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8107 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8108 | imm_expr.X_op = O_absent; | |
8109 | s = expr_end; | |
8110 | continue; | |
8111 | ||
8112 | case 'C': /* ext size, becomes MSBD. */ | |
8113 | limlo = 1; | |
8114 | limhi = 32; | |
5f74bc13 CD |
8115 | goto do_msbd; |
8116 | case 'G': | |
8117 | limlo = 33; | |
8118 | limhi = 64; | |
8119 | goto do_msbd; | |
8120 | case 'H': | |
8121 | limlo = 33; | |
8122 | limhi = 64; | |
8123 | goto do_msbd; | |
8124 | do_msbd: | |
071742cf CD |
8125 | my_getExpression (&imm_expr, s); |
8126 | check_absolute_expr (ip, &imm_expr); | |
8127 | /* Check for negative input so that small negative numbers | |
8128 | will not succeed incorrectly. The checks against | |
8129 | (pos+size) transitively check "size" itself, | |
8130 | assuming that "pos" is reasonable. */ | |
8131 | if ((long) imm_expr.X_add_number < 0 | |
8132 | || ((unsigned long) imm_expr.X_add_number | |
8133 | + lastpos) < limlo | |
8134 | || ((unsigned long) imm_expr.X_add_number | |
8135 | + lastpos) > limhi) | |
8136 | { | |
8137 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8138 | (unsigned long) imm_expr.X_add_number, | |
8139 | (unsigned long) lastpos); | |
8140 | imm_expr.X_add_number = limlo - lastpos; | |
8141 | } | |
8142 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8143 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8144 | imm_expr.X_op = O_absent; | |
8145 | s = expr_end; | |
8146 | continue; | |
af7ee8bf | 8147 | |
bbcc0807 CD |
8148 | case 'D': |
8149 | /* +D is for disassembly only; never match. */ | |
8150 | break; | |
8151 | ||
5f74bc13 CD |
8152 | case 'I': |
8153 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8154 | my_getExpression (&imm2_expr, s); | |
8155 | if (imm2_expr.X_op != O_big | |
8156 | && imm2_expr.X_op != O_constant) | |
8157 | insn_error = _("absolute expression required"); | |
13757d0c | 8158 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8159 | s = expr_end; |
8160 | continue; | |
8161 | ||
af7ee8bf CD |
8162 | default: |
8163 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8164 | *args, insn->name, insn->args); | |
8165 | /* Further processing is fruitless. */ | |
8166 | return; | |
8167 | } | |
8168 | break; | |
8169 | ||
252b5132 RH |
8170 | case '<': /* must be at least one digit */ |
8171 | /* | |
8172 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8173 | * than 31 or less than 0, then the shift amount should be |
8174 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8175 | * We issue a warning and mask out all but the low 5 bits. |
8176 | */ | |
8177 | my_getExpression (&imm_expr, s); | |
8178 | check_absolute_expr (ip, &imm_expr); | |
8179 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8180 | { | |
793b27f4 TS |
8181 | as_warn (_("Improper shift amount (%lu)"), |
8182 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8183 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8184 | } |
38487616 | 8185 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8186 | imm_expr.X_op = O_absent; |
8187 | s = expr_end; | |
8188 | continue; | |
8189 | ||
8190 | case '>': /* shift amount minus 32 */ | |
8191 | my_getExpression (&imm_expr, s); | |
8192 | check_absolute_expr (ip, &imm_expr); | |
8193 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8194 | || (unsigned long) imm_expr.X_add_number > 63) | |
8195 | break; | |
38487616 | 8196 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8197 | imm_expr.X_op = O_absent; |
8198 | s = expr_end; | |
8199 | continue; | |
8200 | ||
252b5132 RH |
8201 | case 'k': /* cache code */ |
8202 | case 'h': /* prefx code */ | |
8203 | my_getExpression (&imm_expr, s); | |
8204 | check_absolute_expr (ip, &imm_expr); | |
8205 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8206 | { | |
8207 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8208 | ip->insn_mo->name, | |
8209 | (unsigned long) imm_expr.X_add_number); | |
8210 | imm_expr.X_add_number &= 0x1f; | |
8211 | } | |
8212 | if (*args == 'k') | |
8213 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8214 | else | |
8215 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8216 | imm_expr.X_op = O_absent; | |
8217 | s = expr_end; | |
8218 | continue; | |
8219 | ||
8220 | case 'c': /* break code */ | |
8221 | my_getExpression (&imm_expr, s); | |
8222 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8223 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8224 | { |
793b27f4 TS |
8225 | as_warn (_("Illegal break code (%lu)"), |
8226 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8227 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8228 | } |
38487616 | 8229 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8230 | imm_expr.X_op = O_absent; |
8231 | s = expr_end; | |
8232 | continue; | |
8233 | ||
8234 | case 'q': /* lower break code */ | |
8235 | my_getExpression (&imm_expr, s); | |
8236 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8237 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8238 | { |
793b27f4 TS |
8239 | as_warn (_("Illegal lower break code (%lu)"), |
8240 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8241 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8242 | } |
38487616 | 8243 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8244 | imm_expr.X_op = O_absent; |
8245 | s = expr_end; | |
8246 | continue; | |
8247 | ||
4372b673 | 8248 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8249 | my_getExpression (&imm_expr, s); |
156c2f8b | 8250 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8251 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8252 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8253 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8254 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8255 | imm_expr.X_op = O_absent; |
8256 | s = expr_end; | |
8257 | continue; | |
8258 | ||
98d3f06f | 8259 | case 'C': /* Coprocessor code */ |
beae10d5 | 8260 | my_getExpression (&imm_expr, s); |
252b5132 | 8261 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8262 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8263 | { |
793b27f4 TS |
8264 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8265 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8266 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8267 | } |
beae10d5 KH |
8268 | ip->insn_opcode |= imm_expr.X_add_number; |
8269 | imm_expr.X_op = O_absent; | |
8270 | s = expr_end; | |
8271 | continue; | |
252b5132 | 8272 | |
4372b673 NC |
8273 | case 'J': /* 19-bit wait code. */ |
8274 | my_getExpression (&imm_expr, s); | |
8275 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8276 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8277 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8278 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8279 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8280 | imm_expr.X_op = O_absent; |
8281 | s = expr_end; | |
8282 | continue; | |
8283 | ||
252b5132 | 8284 | case 'P': /* Performance register */ |
beae10d5 | 8285 | my_getExpression (&imm_expr, s); |
252b5132 | 8286 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8287 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8288 | { |
793b27f4 TS |
8289 | as_warn (_("Invalid performance register (%lu)"), |
8290 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8291 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8292 | } |
38487616 | 8293 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8294 | imm_expr.X_op = O_absent; |
8295 | s = expr_end; | |
8296 | continue; | |
252b5132 RH |
8297 | |
8298 | case 'b': /* base register */ | |
8299 | case 'd': /* destination register */ | |
8300 | case 's': /* source register */ | |
8301 | case 't': /* target register */ | |
8302 | case 'r': /* both target and source */ | |
8303 | case 'v': /* both dest and source */ | |
8304 | case 'w': /* both dest and target */ | |
8305 | case 'E': /* coprocessor target register */ | |
8306 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8307 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8308 | case 'x': /* ignore register name */ |
8309 | case 'z': /* must be zero register */ | |
4372b673 | 8310 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8311 | s_reset = s; |
8312 | if (s[0] == '$') | |
8313 | { | |
8314 | ||
3882b010 | 8315 | if (ISDIGIT (s[1])) |
252b5132 RH |
8316 | { |
8317 | ++s; | |
8318 | regno = 0; | |
8319 | do | |
8320 | { | |
8321 | regno *= 10; | |
8322 | regno += *s - '0'; | |
8323 | ++s; | |
8324 | } | |
3882b010 | 8325 | while (ISDIGIT (*s)); |
252b5132 RH |
8326 | if (regno > 31) |
8327 | as_bad (_("Invalid register number (%d)"), regno); | |
8328 | } | |
af7ee8bf | 8329 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8330 | goto notreg; |
8331 | else | |
8332 | { | |
76db943d TS |
8333 | if (s[1] == 'r' && s[2] == 'a') |
8334 | { | |
8335 | s += 3; | |
8336 | regno = RA; | |
8337 | } | |
8338 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8339 | { |
8340 | s += 3; | |
8341 | regno = FP; | |
8342 | } | |
8343 | else if (s[1] == 's' && s[2] == 'p') | |
8344 | { | |
8345 | s += 3; | |
8346 | regno = SP; | |
8347 | } | |
8348 | else if (s[1] == 'g' && s[2] == 'p') | |
8349 | { | |
8350 | s += 3; | |
8351 | regno = GP; | |
8352 | } | |
8353 | else if (s[1] == 'a' && s[2] == 't') | |
8354 | { | |
8355 | s += 3; | |
8356 | regno = AT; | |
8357 | } | |
8358 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8359 | { | |
8360 | s += 4; | |
8361 | regno = KT0; | |
8362 | } | |
8363 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8364 | { | |
8365 | s += 4; | |
8366 | regno = KT1; | |
8367 | } | |
85b51719 TS |
8368 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8369 | { | |
8370 | s += 5; | |
8371 | regno = ZERO; | |
8372 | } | |
252b5132 RH |
8373 | else if (itbl_have_entries) |
8374 | { | |
8375 | char *p, *n; | |
d7ba4a77 | 8376 | unsigned long r; |
252b5132 | 8377 | |
d7ba4a77 | 8378 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8379 | n = itbl_get_field (&p); /* n is name */ |
8380 | ||
d7ba4a77 ILT |
8381 | /* See if this is a register defined in an |
8382 | itbl entry. */ | |
8383 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8384 | { |
8385 | /* Get_field advances to the start of | |
8386 | the next field, so we need to back | |
d7ba4a77 | 8387 | rack to the end of the last field. */ |
bdaaa2e1 | 8388 | if (p) |
252b5132 | 8389 | s = p - 1; |
bdaaa2e1 | 8390 | else |
d7ba4a77 | 8391 | s = strchr (s, '\0'); |
252b5132 RH |
8392 | regno = r; |
8393 | } | |
8394 | else | |
8395 | goto notreg; | |
beae10d5 | 8396 | } |
252b5132 RH |
8397 | else |
8398 | goto notreg; | |
8399 | } | |
8400 | if (regno == AT | |
8401 | && ! mips_opts.noat | |
8402 | && *args != 'E' | |
af7ee8bf CD |
8403 | && *args != 'G' |
8404 | && *args != 'K') | |
252b5132 RH |
8405 | as_warn (_("Used $at without \".set noat\"")); |
8406 | c = *args; | |
8407 | if (*s == ' ') | |
f9419b05 | 8408 | ++s; |
252b5132 RH |
8409 | if (args[1] != *s) |
8410 | { | |
8411 | if (c == 'r' || c == 'v' || c == 'w') | |
8412 | { | |
8413 | regno = lastregno; | |
8414 | s = s_reset; | |
f9419b05 | 8415 | ++args; |
252b5132 RH |
8416 | } |
8417 | } | |
8418 | /* 'z' only matches $0. */ | |
8419 | if (c == 'z' && regno != 0) | |
8420 | break; | |
8421 | ||
bdaaa2e1 KH |
8422 | /* Now that we have assembled one operand, we use the args string |
8423 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8424 | switch (c) |
8425 | { | |
8426 | case 'r': | |
8427 | case 's': | |
8428 | case 'v': | |
8429 | case 'b': | |
38487616 | 8430 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8431 | break; |
8432 | case 'd': | |
8433 | case 'G': | |
af7ee8bf | 8434 | case 'K': |
38487616 | 8435 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8436 | break; |
4372b673 | 8437 | case 'U': |
38487616 TS |
8438 | ip->insn_opcode |= regno << OP_SH_RD; |
8439 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8440 | break; |
252b5132 RH |
8441 | case 'w': |
8442 | case 't': | |
8443 | case 'E': | |
38487616 | 8444 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8445 | break; |
8446 | case 'x': | |
8447 | /* This case exists because on the r3000 trunc | |
8448 | expands into a macro which requires a gp | |
8449 | register. On the r6000 or r4000 it is | |
8450 | assembled into a single instruction which | |
8451 | ignores the register. Thus the insn version | |
8452 | is MIPS_ISA2 and uses 'x', and the macro | |
8453 | version is MIPS_ISA1 and uses 't'. */ | |
8454 | break; | |
8455 | case 'z': | |
8456 | /* This case is for the div instruction, which | |
8457 | acts differently if the destination argument | |
8458 | is $0. This only matches $0, and is checked | |
8459 | outside the switch. */ | |
8460 | break; | |
8461 | case 'D': | |
8462 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8463 | break; | |
8464 | /* What about all other operands like 'i', which | |
8465 | can be specified in the opcode table? */ | |
8466 | } | |
8467 | lastregno = regno; | |
8468 | continue; | |
8469 | } | |
8470 | notreg: | |
8471 | switch (*args++) | |
8472 | { | |
8473 | case 'r': | |
8474 | case 'v': | |
38487616 | 8475 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8476 | continue; |
8477 | case 'w': | |
38487616 | 8478 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8479 | continue; |
8480 | } | |
8481 | break; | |
8482 | ||
deec1734 CD |
8483 | case 'O': /* MDMX alignment immediate constant. */ |
8484 | my_getExpression (&imm_expr, s); | |
8485 | check_absolute_expr (ip, &imm_expr); | |
8486 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8487 | { | |
8488 | as_warn ("Improper align amount (%ld), using low bits", | |
8489 | (long) imm_expr.X_add_number); | |
8490 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8491 | } | |
8492 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8493 | imm_expr.X_op = O_absent; | |
8494 | s = expr_end; | |
8495 | continue; | |
8496 | ||
8497 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8498 | if (s[0] != '$') | |
8499 | { | |
8500 | /* MDMX Immediate. */ | |
8501 | my_getExpression (&imm_expr, s); | |
8502 | check_absolute_expr (ip, &imm_expr); | |
8503 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8504 | { | |
8505 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8506 | (long) imm_expr.X_add_number); | |
8507 | imm_expr.X_add_number &= OP_MASK_FT; | |
8508 | } | |
8509 | imm_expr.X_add_number &= OP_MASK_FT; | |
8510 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8511 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8512 | else | |
8513 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8514 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8515 | imm_expr.X_op = O_absent; | |
8516 | s = expr_end; | |
8517 | continue; | |
8518 | } | |
8519 | /* Not MDMX Immediate. Fall through. */ | |
8520 | case 'X': /* MDMX destination register. */ | |
8521 | case 'Y': /* MDMX source register. */ | |
8522 | case 'Z': /* MDMX target register. */ | |
8523 | is_mdmx = 1; | |
252b5132 RH |
8524 | case 'D': /* floating point destination register */ |
8525 | case 'S': /* floating point source register */ | |
8526 | case 'T': /* floating point target register */ | |
8527 | case 'R': /* floating point source register */ | |
8528 | case 'V': | |
8529 | case 'W': | |
8530 | s_reset = s; | |
deec1734 CD |
8531 | /* Accept $fN for FP and MDMX register numbers, and in |
8532 | addition accept $vN for MDMX register numbers. */ | |
8533 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8534 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8535 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8536 | { |
8537 | s += 2; | |
8538 | regno = 0; | |
8539 | do | |
8540 | { | |
8541 | regno *= 10; | |
8542 | regno += *s - '0'; | |
8543 | ++s; | |
8544 | } | |
3882b010 | 8545 | while (ISDIGIT (*s)); |
252b5132 RH |
8546 | |
8547 | if (regno > 31) | |
8548 | as_bad (_("Invalid float register number (%d)"), regno); | |
8549 | ||
8550 | if ((regno & 1) != 0 | |
ca4e0257 | 8551 | && HAVE_32BIT_FPRS |
252b5132 RH |
8552 | && ! (strcmp (str, "mtc1") == 0 |
8553 | || strcmp (str, "mfc1") == 0 | |
8554 | || strcmp (str, "lwc1") == 0 | |
8555 | || strcmp (str, "swc1") == 0 | |
8556 | || strcmp (str, "l.s") == 0 | |
8557 | || strcmp (str, "s.s") == 0)) | |
8558 | as_warn (_("Float register should be even, was %d"), | |
8559 | regno); | |
8560 | ||
8561 | c = *args; | |
8562 | if (*s == ' ') | |
f9419b05 | 8563 | ++s; |
252b5132 RH |
8564 | if (args[1] != *s) |
8565 | { | |
8566 | if (c == 'V' || c == 'W') | |
8567 | { | |
8568 | regno = lastregno; | |
8569 | s = s_reset; | |
f9419b05 | 8570 | ++args; |
252b5132 RH |
8571 | } |
8572 | } | |
8573 | switch (c) | |
8574 | { | |
8575 | case 'D': | |
deec1734 | 8576 | case 'X': |
38487616 | 8577 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8578 | break; |
8579 | case 'V': | |
8580 | case 'S': | |
deec1734 | 8581 | case 'Y': |
38487616 | 8582 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8583 | break; |
deec1734 CD |
8584 | case 'Q': |
8585 | /* This is like 'Z', but also needs to fix the MDMX | |
8586 | vector/scalar select bits. Note that the | |
8587 | scalar immediate case is handled above. */ | |
8588 | if (*s == '[') | |
8589 | { | |
8590 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8591 | int max_el = (is_qh ? 3 : 7); | |
8592 | s++; | |
8593 | my_getExpression(&imm_expr, s); | |
8594 | check_absolute_expr (ip, &imm_expr); | |
8595 | s = expr_end; | |
8596 | if (imm_expr.X_add_number > max_el) | |
8597 | as_bad(_("Bad element selector %ld"), | |
8598 | (long) imm_expr.X_add_number); | |
8599 | imm_expr.X_add_number &= max_el; | |
8600 | ip->insn_opcode |= (imm_expr.X_add_number | |
8601 | << (OP_SH_VSEL + | |
8602 | (is_qh ? 2 : 1))); | |
8603 | if (*s != ']') | |
8604 | as_warn(_("Expecting ']' found '%s'"), s); | |
8605 | else | |
8606 | s++; | |
8607 | } | |
8608 | else | |
8609 | { | |
8610 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8611 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8612 | << OP_SH_VSEL); | |
8613 | else | |
8614 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8615 | OP_SH_VSEL); | |
8616 | } | |
8617 | /* Fall through */ | |
252b5132 RH |
8618 | case 'W': |
8619 | case 'T': | |
deec1734 | 8620 | case 'Z': |
38487616 | 8621 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8622 | break; |
8623 | case 'R': | |
38487616 | 8624 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8625 | break; |
8626 | } | |
8627 | lastregno = regno; | |
8628 | continue; | |
8629 | } | |
8630 | ||
252b5132 RH |
8631 | switch (*args++) |
8632 | { | |
8633 | case 'V': | |
38487616 | 8634 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8635 | continue; |
8636 | case 'W': | |
38487616 | 8637 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8638 | continue; |
8639 | } | |
8640 | break; | |
8641 | ||
8642 | case 'I': | |
8643 | my_getExpression (&imm_expr, s); | |
8644 | if (imm_expr.X_op != O_big | |
8645 | && imm_expr.X_op != O_constant) | |
8646 | insn_error = _("absolute expression required"); | |
13757d0c | 8647 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8648 | s = expr_end; |
8649 | continue; | |
8650 | ||
8651 | case 'A': | |
8652 | my_getExpression (&offset_expr, s); | |
f6688943 | 8653 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8654 | s = expr_end; |
8655 | continue; | |
8656 | ||
8657 | case 'F': | |
8658 | case 'L': | |
8659 | case 'f': | |
8660 | case 'l': | |
8661 | { | |
8662 | int f64; | |
ca4e0257 | 8663 | int using_gprs; |
252b5132 RH |
8664 | char *save_in; |
8665 | char *err; | |
8666 | unsigned char temp[8]; | |
8667 | int len; | |
8668 | unsigned int length; | |
8669 | segT seg; | |
8670 | subsegT subseg; | |
8671 | char *p; | |
8672 | ||
8673 | /* These only appear as the last operand in an | |
8674 | instruction, and every instruction that accepts | |
8675 | them in any variant accepts them in all variants. | |
8676 | This means we don't have to worry about backing out | |
8677 | any changes if the instruction does not match. | |
8678 | ||
8679 | The difference between them is the size of the | |
8680 | floating point constant and where it goes. For 'F' | |
8681 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8682 | is 32 bits. Where the constant is placed is based | |
8683 | on how the MIPS assembler does things: | |
8684 | F -- .rdata | |
8685 | L -- .lit8 | |
8686 | f -- immediate value | |
8687 | l -- .lit4 | |
8688 | ||
8689 | The .lit4 and .lit8 sections are only used if | |
8690 | permitted by the -G argument. | |
8691 | ||
ca4e0257 RS |
8692 | The code below needs to know whether the target register |
8693 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8694 | 'F' are used with GPR-based instructions and 'l' and | |
8695 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8696 | |
8697 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8698 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8699 | |
8700 | save_in = input_line_pointer; | |
8701 | input_line_pointer = s; | |
8702 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8703 | length = len; | |
8704 | s = input_line_pointer; | |
8705 | input_line_pointer = save_in; | |
8706 | if (err != NULL && *err != '\0') | |
8707 | { | |
8708 | as_bad (_("Bad floating point constant: %s"), err); | |
8709 | memset (temp, '\0', sizeof temp); | |
8710 | length = f64 ? 8 : 4; | |
8711 | } | |
8712 | ||
156c2f8b | 8713 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8714 | |
8715 | if (*args == 'f' | |
8716 | || (*args == 'l' | |
3e722fb5 | 8717 | && (g_switch_value < 4 |
252b5132 RH |
8718 | || (temp[0] == 0 && temp[1] == 0) |
8719 | || (temp[2] == 0 && temp[3] == 0)))) | |
8720 | { | |
8721 | imm_expr.X_op = O_constant; | |
8722 | if (! target_big_endian) | |
8723 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8724 | else | |
8725 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8726 | } | |
8727 | else if (length > 4 | |
119d663a | 8728 | && ! mips_disable_float_construction |
ca4e0257 RS |
8729 | /* Constants can only be constructed in GPRs and |
8730 | copied to FPRs if the GPRs are at least as wide | |
8731 | as the FPRs. Force the constant into memory if | |
8732 | we are using 64-bit FPRs but the GPRs are only | |
8733 | 32 bits wide. */ | |
8734 | && (using_gprs | |
8735 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8736 | && ((temp[0] == 0 && temp[1] == 0) |
8737 | || (temp[2] == 0 && temp[3] == 0)) | |
8738 | && ((temp[4] == 0 && temp[5] == 0) | |
8739 | || (temp[6] == 0 && temp[7] == 0))) | |
8740 | { | |
ca4e0257 RS |
8741 | /* The value is simple enough to load with a couple of |
8742 | instructions. If using 32-bit registers, set | |
8743 | imm_expr to the high order 32 bits and offset_expr to | |
8744 | the low order 32 bits. Otherwise, set imm_expr to | |
8745 | the entire 64 bit constant. */ | |
8746 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8747 | { |
8748 | imm_expr.X_op = O_constant; | |
8749 | offset_expr.X_op = O_constant; | |
8750 | if (! target_big_endian) | |
8751 | { | |
8752 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8753 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8754 | } | |
8755 | else | |
8756 | { | |
8757 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8758 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8759 | } | |
8760 | if (offset_expr.X_add_number == 0) | |
8761 | offset_expr.X_op = O_absent; | |
8762 | } | |
8763 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8764 | { | |
8765 | imm_expr.X_op = O_constant; | |
8766 | if (! target_big_endian) | |
8767 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8768 | else | |
8769 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8770 | } | |
8771 | else | |
8772 | { | |
8773 | imm_expr.X_op = O_big; | |
8774 | imm_expr.X_add_number = 4; | |
8775 | if (! target_big_endian) | |
8776 | { | |
8777 | generic_bignum[0] = bfd_getl16 (temp); | |
8778 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8779 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8780 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8781 | } | |
8782 | else | |
8783 | { | |
8784 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8785 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8786 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8787 | generic_bignum[3] = bfd_getb16 (temp); | |
8788 | } | |
8789 | } | |
8790 | } | |
8791 | else | |
8792 | { | |
8793 | const char *newname; | |
8794 | segT new_seg; | |
8795 | ||
8796 | /* Switch to the right section. */ | |
8797 | seg = now_seg; | |
8798 | subseg = now_subseg; | |
8799 | switch (*args) | |
8800 | { | |
8801 | default: /* unused default case avoids warnings. */ | |
8802 | case 'L': | |
8803 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8804 | if (g_switch_value >= 8) |
252b5132 RH |
8805 | newname = ".lit8"; |
8806 | break; | |
8807 | case 'F': | |
3e722fb5 | 8808 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8809 | break; |
8810 | case 'l': | |
4d0d148d | 8811 | assert (g_switch_value >= 4); |
252b5132 RH |
8812 | newname = ".lit4"; |
8813 | break; | |
8814 | } | |
8815 | new_seg = subseg_new (newname, (subsegT) 0); | |
8816 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8817 | bfd_set_section_flags (stdoutput, new_seg, | |
8818 | (SEC_ALLOC | |
8819 | | SEC_LOAD | |
8820 | | SEC_READONLY | |
8821 | | SEC_DATA)); | |
8822 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8823 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8824 | && strcmp (TARGET_OS, "elf") != 0) | |
8825 | record_alignment (new_seg, 4); | |
8826 | else | |
8827 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8828 | if (seg == now_seg) | |
8829 | as_bad (_("Can't use floating point insn in this section")); | |
8830 | ||
8831 | /* Set the argument to the current address in the | |
8832 | section. */ | |
8833 | offset_expr.X_op = O_symbol; | |
8834 | offset_expr.X_add_symbol = | |
8835 | symbol_new ("L0\001", now_seg, | |
8836 | (valueT) frag_now_fix (), frag_now); | |
8837 | offset_expr.X_add_number = 0; | |
8838 | ||
8839 | /* Put the floating point number into the section. */ | |
8840 | p = frag_more ((int) length); | |
8841 | memcpy (p, temp, length); | |
8842 | ||
8843 | /* Switch back to the original section. */ | |
8844 | subseg_set (seg, subseg); | |
8845 | } | |
8846 | } | |
8847 | continue; | |
8848 | ||
8849 | case 'i': /* 16 bit unsigned immediate */ | |
8850 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8851 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8852 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8853 | { |
8854 | int more; | |
5e0116d5 RS |
8855 | offsetT minval, maxval; |
8856 | ||
8857 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8858 | && strcmp (insn->name, insn[1].name) == 0); | |
8859 | ||
8860 | /* If the expression was written as an unsigned number, | |
8861 | only treat it as signed if there are no more | |
8862 | alternatives. */ | |
8863 | if (more | |
8864 | && *args == 'j' | |
8865 | && sizeof (imm_expr.X_add_number) <= 4 | |
8866 | && imm_expr.X_op == O_constant | |
8867 | && imm_expr.X_add_number < 0 | |
8868 | && imm_expr.X_unsigned | |
8869 | && HAVE_64BIT_GPRS) | |
8870 | break; | |
8871 | ||
8872 | /* For compatibility with older assemblers, we accept | |
8873 | 0x8000-0xffff as signed 16-bit numbers when only | |
8874 | signed numbers are allowed. */ | |
8875 | if (*args == 'i') | |
8876 | minval = 0, maxval = 0xffff; | |
8877 | else if (more) | |
8878 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8879 | else |
5e0116d5 RS |
8880 | minval = -0x8000, maxval = 0xffff; |
8881 | ||
8882 | if (imm_expr.X_op != O_constant | |
8883 | || imm_expr.X_add_number < minval | |
8884 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8885 | { |
8886 | if (more) | |
8887 | break; | |
2ae7e77b AH |
8888 | if (imm_expr.X_op == O_constant |
8889 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8890 | as_bad (_("expression out of range")); |
252b5132 RH |
8891 | } |
8892 | } | |
8893 | s = expr_end; | |
8894 | continue; | |
8895 | ||
8896 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8897 | /* Check whether there is only a single bracketed expression |
8898 | left. If so, it must be the base register and the | |
8899 | constant must be zero. */ | |
8900 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8901 | { | |
8902 | offset_expr.X_op = O_constant; | |
8903 | offset_expr.X_add_number = 0; | |
8904 | continue; | |
8905 | } | |
252b5132 RH |
8906 | |
8907 | /* If this value won't fit into a 16 bit offset, then go | |
8908 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8909 | code pattern. */ |
5e0116d5 | 8910 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8911 | && (offset_expr.X_op != O_constant |
8912 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8913 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8914 | break; |
8915 | ||
252b5132 RH |
8916 | s = expr_end; |
8917 | continue; | |
8918 | ||
8919 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8920 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8921 | my_getExpression (&offset_expr, s); |
8922 | s = expr_end; | |
8923 | continue; | |
8924 | ||
8925 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8926 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8927 | && imm_expr.X_op == O_constant | |
8928 | && (imm_expr.X_add_number < 0 | |
8929 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8930 | as_bad (_("lui expression not in range 0..65535")); |
8931 | s = expr_end; | |
8932 | continue; | |
8933 | ||
8934 | case 'a': /* 26 bit address */ | |
8935 | my_getExpression (&offset_expr, s); | |
8936 | s = expr_end; | |
f6688943 | 8937 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8938 | continue; |
8939 | ||
8940 | case 'N': /* 3 bit branch condition code */ | |
8941 | case 'M': /* 3 bit compare condition code */ | |
8942 | if (strncmp (s, "$fcc", 4) != 0) | |
8943 | break; | |
8944 | s += 4; | |
8945 | regno = 0; | |
8946 | do | |
8947 | { | |
8948 | regno *= 10; | |
8949 | regno += *s - '0'; | |
8950 | ++s; | |
8951 | } | |
3882b010 | 8952 | while (ISDIGIT (*s)); |
252b5132 | 8953 | if (regno > 7) |
30c378fd CD |
8954 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8955 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8956 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8957 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8958 | && (regno & 1) != 0) | |
8959 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8960 | str, regno); | |
8961 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8962 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8963 | && (regno & 3) != 0) | |
8964 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8965 | str, regno); | |
252b5132 RH |
8966 | if (*args == 'N') |
8967 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8968 | else | |
8969 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8970 | continue; |
252b5132 | 8971 | |
156c2f8b NC |
8972 | case 'H': |
8973 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8974 | s += 2; | |
3882b010 | 8975 | if (ISDIGIT (*s)) |
156c2f8b NC |
8976 | { |
8977 | c = 0; | |
8978 | do | |
8979 | { | |
8980 | c *= 10; | |
8981 | c += *s - '0'; | |
8982 | ++s; | |
8983 | } | |
3882b010 | 8984 | while (ISDIGIT (*s)); |
156c2f8b NC |
8985 | } |
8986 | else | |
8987 | c = 8; /* Invalid sel value. */ | |
8988 | ||
8989 | if (c > 7) | |
8990 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8991 | ip->insn_opcode |= c; | |
8992 | continue; | |
8993 | ||
60b63b72 RS |
8994 | case 'e': |
8995 | /* Must be at least one digit. */ | |
8996 | my_getExpression (&imm_expr, s); | |
8997 | check_absolute_expr (ip, &imm_expr); | |
8998 | ||
8999 | if ((unsigned long) imm_expr.X_add_number | |
9000 | > (unsigned long) OP_MASK_VECBYTE) | |
9001 | { | |
9002 | as_bad (_("bad byte vector index (%ld)"), | |
9003 | (long) imm_expr.X_add_number); | |
9004 | imm_expr.X_add_number = 0; | |
9005 | } | |
9006 | ||
9007 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9008 | imm_expr.X_op = O_absent; | |
9009 | s = expr_end; | |
9010 | continue; | |
9011 | ||
9012 | case '%': | |
9013 | my_getExpression (&imm_expr, s); | |
9014 | check_absolute_expr (ip, &imm_expr); | |
9015 | ||
9016 | if ((unsigned long) imm_expr.X_add_number | |
9017 | > (unsigned long) OP_MASK_VECALIGN) | |
9018 | { | |
9019 | as_bad (_("bad byte vector index (%ld)"), | |
9020 | (long) imm_expr.X_add_number); | |
9021 | imm_expr.X_add_number = 0; | |
9022 | } | |
9023 | ||
9024 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9025 | imm_expr.X_op = O_absent; | |
9026 | s = expr_end; | |
9027 | continue; | |
9028 | ||
252b5132 RH |
9029 | default: |
9030 | as_bad (_("bad char = '%c'\n"), *args); | |
9031 | internalError (); | |
9032 | } | |
9033 | break; | |
9034 | } | |
9035 | /* Args don't match. */ | |
9036 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9037 | !strcmp (insn->name, insn[1].name)) | |
9038 | { | |
9039 | ++insn; | |
9040 | s = argsStart; | |
268f6bed | 9041 | insn_error = _("illegal operands"); |
252b5132 RH |
9042 | continue; |
9043 | } | |
268f6bed L |
9044 | if (save_c) |
9045 | *(--s) = save_c; | |
252b5132 RH |
9046 | insn_error = _("illegal operands"); |
9047 | return; | |
9048 | } | |
9049 | } | |
9050 | ||
9051 | /* This routine assembles an instruction into its binary format when | |
9052 | assembling for the mips16. As a side effect, it sets one of the | |
9053 | global variables imm_reloc or offset_reloc to the type of | |
9054 | relocation to do if one of the operands is an address expression. | |
9055 | It also sets mips16_small and mips16_ext if the user explicitly | |
9056 | requested a small or extended instruction. */ | |
9057 | ||
9058 | static void | |
17a2f251 | 9059 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9060 | { |
9061 | char *s; | |
9062 | const char *args; | |
9063 | struct mips_opcode *insn; | |
9064 | char *argsstart; | |
9065 | unsigned int regno; | |
9066 | unsigned int lastregno = 0; | |
9067 | char *s_reset; | |
9068 | ||
9069 | insn_error = NULL; | |
9070 | ||
b34976b6 AM |
9071 | mips16_small = FALSE; |
9072 | mips16_ext = FALSE; | |
252b5132 | 9073 | |
3882b010 | 9074 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9075 | ; |
9076 | switch (*s) | |
9077 | { | |
9078 | case '\0': | |
9079 | break; | |
9080 | ||
9081 | case ' ': | |
9082 | *s++ = '\0'; | |
9083 | break; | |
9084 | ||
9085 | case '.': | |
9086 | if (s[1] == 't' && s[2] == ' ') | |
9087 | { | |
9088 | *s = '\0'; | |
b34976b6 | 9089 | mips16_small = TRUE; |
252b5132 RH |
9090 | s += 3; |
9091 | break; | |
9092 | } | |
9093 | else if (s[1] == 'e' && s[2] == ' ') | |
9094 | { | |
9095 | *s = '\0'; | |
b34976b6 | 9096 | mips16_ext = TRUE; |
252b5132 RH |
9097 | s += 3; |
9098 | break; | |
9099 | } | |
9100 | /* Fall through. */ | |
9101 | default: | |
9102 | insn_error = _("unknown opcode"); | |
9103 | return; | |
9104 | } | |
9105 | ||
9106 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9107 | mips16_small = TRUE; |
252b5132 RH |
9108 | |
9109 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9110 | { | |
9111 | insn_error = _("unrecognized opcode"); | |
9112 | return; | |
9113 | } | |
9114 | ||
9115 | argsstart = s; | |
9116 | for (;;) | |
9117 | { | |
9118 | assert (strcmp (insn->name, str) == 0); | |
9119 | ||
9120 | ip->insn_mo = insn; | |
9121 | ip->insn_opcode = insn->match; | |
b34976b6 | 9122 | ip->use_extend = FALSE; |
252b5132 | 9123 | imm_expr.X_op = O_absent; |
f6688943 TS |
9124 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9125 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9126 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9127 | imm2_expr.X_op = O_absent; |
252b5132 | 9128 | offset_expr.X_op = O_absent; |
f6688943 TS |
9129 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9130 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9131 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9132 | for (args = insn->args; 1; ++args) |
9133 | { | |
9134 | int c; | |
9135 | ||
9136 | if (*s == ' ') | |
9137 | ++s; | |
9138 | ||
9139 | /* In this switch statement we call break if we did not find | |
9140 | a match, continue if we did find a match, or return if we | |
9141 | are done. */ | |
9142 | ||
9143 | c = *args; | |
9144 | switch (c) | |
9145 | { | |
9146 | case '\0': | |
9147 | if (*s == '\0') | |
9148 | { | |
9149 | /* Stuff the immediate value in now, if we can. */ | |
9150 | if (imm_expr.X_op == O_constant | |
f6688943 | 9151 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9152 | && insn->pinfo != INSN_MACRO) |
9153 | { | |
c4e7957c | 9154 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9155 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9156 | mips16_ext, &ip->insn_opcode, |
9157 | &ip->use_extend, &ip->extend); | |
9158 | imm_expr.X_op = O_absent; | |
f6688943 | 9159 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9160 | } |
9161 | ||
9162 | return; | |
9163 | } | |
9164 | break; | |
9165 | ||
9166 | case ',': | |
9167 | if (*s++ == c) | |
9168 | continue; | |
9169 | s--; | |
9170 | switch (*++args) | |
9171 | { | |
9172 | case 'v': | |
9173 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9174 | continue; | |
9175 | case 'w': | |
9176 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9177 | continue; | |
9178 | } | |
9179 | break; | |
9180 | ||
9181 | case '(': | |
9182 | case ')': | |
9183 | if (*s++ == c) | |
9184 | continue; | |
9185 | break; | |
9186 | ||
9187 | case 'v': | |
9188 | case 'w': | |
9189 | if (s[0] != '$') | |
9190 | { | |
9191 | if (c == 'v') | |
9192 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9193 | else | |
9194 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9195 | ++args; | |
9196 | continue; | |
9197 | } | |
9198 | /* Fall through. */ | |
9199 | case 'x': | |
9200 | case 'y': | |
9201 | case 'z': | |
9202 | case 'Z': | |
9203 | case '0': | |
9204 | case 'S': | |
9205 | case 'R': | |
9206 | case 'X': | |
9207 | case 'Y': | |
9208 | if (s[0] != '$') | |
9209 | break; | |
9210 | s_reset = s; | |
3882b010 | 9211 | if (ISDIGIT (s[1])) |
252b5132 RH |
9212 | { |
9213 | ++s; | |
9214 | regno = 0; | |
9215 | do | |
9216 | { | |
9217 | regno *= 10; | |
9218 | regno += *s - '0'; | |
9219 | ++s; | |
9220 | } | |
3882b010 | 9221 | while (ISDIGIT (*s)); |
252b5132 RH |
9222 | if (regno > 31) |
9223 | { | |
9224 | as_bad (_("invalid register number (%d)"), regno); | |
9225 | regno = 2; | |
9226 | } | |
9227 | } | |
9228 | else | |
9229 | { | |
76db943d TS |
9230 | if (s[1] == 'r' && s[2] == 'a') |
9231 | { | |
9232 | s += 3; | |
9233 | regno = RA; | |
9234 | } | |
9235 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9236 | { |
9237 | s += 3; | |
9238 | regno = FP; | |
9239 | } | |
9240 | else if (s[1] == 's' && s[2] == 'p') | |
9241 | { | |
9242 | s += 3; | |
9243 | regno = SP; | |
9244 | } | |
9245 | else if (s[1] == 'g' && s[2] == 'p') | |
9246 | { | |
9247 | s += 3; | |
9248 | regno = GP; | |
9249 | } | |
9250 | else if (s[1] == 'a' && s[2] == 't') | |
9251 | { | |
9252 | s += 3; | |
9253 | regno = AT; | |
9254 | } | |
9255 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9256 | { | |
9257 | s += 4; | |
9258 | regno = KT0; | |
9259 | } | |
9260 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9261 | { | |
9262 | s += 4; | |
9263 | regno = KT1; | |
9264 | } | |
85b51719 TS |
9265 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9266 | { | |
9267 | s += 5; | |
9268 | regno = ZERO; | |
9269 | } | |
252b5132 RH |
9270 | else |
9271 | break; | |
9272 | } | |
9273 | ||
9274 | if (*s == ' ') | |
9275 | ++s; | |
9276 | if (args[1] != *s) | |
9277 | { | |
9278 | if (c == 'v' || c == 'w') | |
9279 | { | |
9280 | regno = mips16_to_32_reg_map[lastregno]; | |
9281 | s = s_reset; | |
f9419b05 | 9282 | ++args; |
252b5132 RH |
9283 | } |
9284 | } | |
9285 | ||
9286 | switch (c) | |
9287 | { | |
9288 | case 'x': | |
9289 | case 'y': | |
9290 | case 'z': | |
9291 | case 'v': | |
9292 | case 'w': | |
9293 | case 'Z': | |
9294 | regno = mips32_to_16_reg_map[regno]; | |
9295 | break; | |
9296 | ||
9297 | case '0': | |
9298 | if (regno != 0) | |
9299 | regno = ILLEGAL_REG; | |
9300 | break; | |
9301 | ||
9302 | case 'S': | |
9303 | if (regno != SP) | |
9304 | regno = ILLEGAL_REG; | |
9305 | break; | |
9306 | ||
9307 | case 'R': | |
9308 | if (regno != RA) | |
9309 | regno = ILLEGAL_REG; | |
9310 | break; | |
9311 | ||
9312 | case 'X': | |
9313 | case 'Y': | |
9314 | if (regno == AT && ! mips_opts.noat) | |
9315 | as_warn (_("used $at without \".set noat\"")); | |
9316 | break; | |
9317 | ||
9318 | default: | |
9319 | internalError (); | |
9320 | } | |
9321 | ||
9322 | if (regno == ILLEGAL_REG) | |
9323 | break; | |
9324 | ||
9325 | switch (c) | |
9326 | { | |
9327 | case 'x': | |
9328 | case 'v': | |
9329 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9330 | break; | |
9331 | case 'y': | |
9332 | case 'w': | |
9333 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9334 | break; | |
9335 | case 'z': | |
9336 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9337 | break; | |
9338 | case 'Z': | |
9339 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9340 | case '0': | |
9341 | case 'S': | |
9342 | case 'R': | |
9343 | break; | |
9344 | case 'X': | |
9345 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9346 | break; | |
9347 | case 'Y': | |
9348 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9349 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9350 | break; | |
9351 | default: | |
9352 | internalError (); | |
9353 | } | |
9354 | ||
9355 | lastregno = regno; | |
9356 | continue; | |
9357 | ||
9358 | case 'P': | |
9359 | if (strncmp (s, "$pc", 3) == 0) | |
9360 | { | |
9361 | s += 3; | |
9362 | continue; | |
9363 | } | |
9364 | break; | |
9365 | ||
9366 | case '<': | |
9367 | case '>': | |
9368 | case '[': | |
9369 | case ']': | |
9370 | case '4': | |
9371 | case '5': | |
9372 | case 'H': | |
9373 | case 'W': | |
9374 | case 'D': | |
9375 | case 'j': | |
9376 | case '8': | |
9377 | case 'V': | |
9378 | case 'C': | |
9379 | case 'U': | |
9380 | case 'k': | |
9381 | case 'K': | |
9382 | if (s[0] == '%' | |
9383 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9384 | { | |
9385 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9386 | and generate the appropriate reloc. If the text | |
9387 | inside %gprel is not a symbol name with an | |
9388 | optional offset, then we generate a normal reloc | |
9389 | and will probably fail later. */ | |
9390 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9391 | if (imm_expr.X_op == O_symbol) | |
9392 | { | |
b34976b6 | 9393 | mips16_ext = TRUE; |
f6688943 | 9394 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9395 | s = expr_end; |
b34976b6 | 9396 | ip->use_extend = TRUE; |
252b5132 RH |
9397 | ip->extend = 0; |
9398 | continue; | |
9399 | } | |
9400 | } | |
9401 | else | |
9402 | { | |
9403 | /* Just pick up a normal expression. */ | |
9404 | my_getExpression (&imm_expr, s); | |
9405 | } | |
9406 | ||
9407 | if (imm_expr.X_op == O_register) | |
9408 | { | |
9409 | /* What we thought was an expression turned out to | |
9410 | be a register. */ | |
9411 | ||
9412 | if (s[0] == '(' && args[1] == '(') | |
9413 | { | |
9414 | /* It looks like the expression was omitted | |
9415 | before a register indirection, which means | |
9416 | that the expression is implicitly zero. We | |
9417 | still set up imm_expr, so that we handle | |
9418 | explicit extensions correctly. */ | |
9419 | imm_expr.X_op = O_constant; | |
9420 | imm_expr.X_add_number = 0; | |
f6688943 | 9421 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9422 | continue; |
9423 | } | |
9424 | ||
9425 | break; | |
9426 | } | |
9427 | ||
9428 | /* We need to relax this instruction. */ | |
f6688943 | 9429 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9430 | s = expr_end; |
9431 | continue; | |
9432 | ||
9433 | case 'p': | |
9434 | case 'q': | |
9435 | case 'A': | |
9436 | case 'B': | |
9437 | case 'E': | |
9438 | /* We use offset_reloc rather than imm_reloc for the PC | |
9439 | relative operands. This lets macros with both | |
9440 | immediate and address operands work correctly. */ | |
9441 | my_getExpression (&offset_expr, s); | |
9442 | ||
9443 | if (offset_expr.X_op == O_register) | |
9444 | break; | |
9445 | ||
9446 | /* We need to relax this instruction. */ | |
f6688943 | 9447 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9448 | s = expr_end; |
9449 | continue; | |
9450 | ||
9451 | case '6': /* break code */ | |
9452 | my_getExpression (&imm_expr, s); | |
9453 | check_absolute_expr (ip, &imm_expr); | |
9454 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9455 | { | |
9456 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9457 | ip->insn_mo->name, | |
9458 | (unsigned long) imm_expr.X_add_number); | |
9459 | imm_expr.X_add_number &= 0x3f; | |
9460 | } | |
9461 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9462 | imm_expr.X_op = O_absent; | |
9463 | s = expr_end; | |
9464 | continue; | |
9465 | ||
9466 | case 'a': /* 26 bit address */ | |
9467 | my_getExpression (&offset_expr, s); | |
9468 | s = expr_end; | |
f6688943 | 9469 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9470 | ip->insn_opcode <<= 16; |
9471 | continue; | |
9472 | ||
9473 | case 'l': /* register list for entry macro */ | |
9474 | case 'L': /* register list for exit macro */ | |
9475 | { | |
9476 | int mask; | |
9477 | ||
9478 | if (c == 'l') | |
9479 | mask = 0; | |
9480 | else | |
9481 | mask = 7 << 3; | |
9482 | while (*s != '\0') | |
9483 | { | |
9484 | int freg, reg1, reg2; | |
9485 | ||
9486 | while (*s == ' ' || *s == ',') | |
9487 | ++s; | |
9488 | if (*s != '$') | |
9489 | { | |
9490 | as_bad (_("can't parse register list")); | |
9491 | break; | |
9492 | } | |
9493 | ++s; | |
9494 | if (*s != 'f') | |
9495 | freg = 0; | |
9496 | else | |
9497 | { | |
9498 | freg = 1; | |
9499 | ++s; | |
9500 | } | |
9501 | reg1 = 0; | |
3882b010 | 9502 | while (ISDIGIT (*s)) |
252b5132 RH |
9503 | { |
9504 | reg1 *= 10; | |
9505 | reg1 += *s - '0'; | |
9506 | ++s; | |
9507 | } | |
9508 | if (*s == ' ') | |
9509 | ++s; | |
9510 | if (*s != '-') | |
9511 | reg2 = reg1; | |
9512 | else | |
9513 | { | |
9514 | ++s; | |
9515 | if (*s != '$') | |
9516 | break; | |
9517 | ++s; | |
9518 | if (freg) | |
9519 | { | |
9520 | if (*s == 'f') | |
9521 | ++s; | |
9522 | else | |
9523 | { | |
9524 | as_bad (_("invalid register list")); | |
9525 | break; | |
9526 | } | |
9527 | } | |
9528 | reg2 = 0; | |
3882b010 | 9529 | while (ISDIGIT (*s)) |
252b5132 RH |
9530 | { |
9531 | reg2 *= 10; | |
9532 | reg2 += *s - '0'; | |
9533 | ++s; | |
9534 | } | |
9535 | } | |
9536 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9537 | { | |
9538 | mask &= ~ (7 << 3); | |
9539 | mask |= 5 << 3; | |
9540 | } | |
9541 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9542 | { | |
9543 | mask &= ~ (7 << 3); | |
9544 | mask |= 6 << 3; | |
9545 | } | |
9546 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9547 | mask |= (reg2 - 3) << 3; | |
9548 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9549 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9550 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9551 | mask |= 1; |
9552 | else | |
9553 | { | |
9554 | as_bad (_("invalid register list")); | |
9555 | break; | |
9556 | } | |
9557 | } | |
9558 | /* The mask is filled in in the opcode table for the | |
9559 | benefit of the disassembler. We remove it before | |
9560 | applying the actual mask. */ | |
9561 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9562 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9563 | } | |
9564 | continue; | |
9565 | ||
9566 | case 'e': /* extend code */ | |
9567 | my_getExpression (&imm_expr, s); | |
9568 | check_absolute_expr (ip, &imm_expr); | |
9569 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9570 | { | |
9571 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9572 | ip->insn_mo->name, | |
9573 | (unsigned long) imm_expr.X_add_number); | |
9574 | imm_expr.X_add_number &= 0x7ff; | |
9575 | } | |
9576 | ip->insn_opcode |= imm_expr.X_add_number; | |
9577 | imm_expr.X_op = O_absent; | |
9578 | s = expr_end; | |
9579 | continue; | |
9580 | ||
9581 | default: | |
9582 | internalError (); | |
9583 | } | |
9584 | break; | |
9585 | } | |
9586 | ||
9587 | /* Args don't match. */ | |
9588 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9589 | strcmp (insn->name, insn[1].name) == 0) | |
9590 | { | |
9591 | ++insn; | |
9592 | s = argsstart; | |
9593 | continue; | |
9594 | } | |
9595 | ||
9596 | insn_error = _("illegal operands"); | |
9597 | ||
9598 | return; | |
9599 | } | |
9600 | } | |
9601 | ||
9602 | /* This structure holds information we know about a mips16 immediate | |
9603 | argument type. */ | |
9604 | ||
e972090a NC |
9605 | struct mips16_immed_operand |
9606 | { | |
252b5132 RH |
9607 | /* The type code used in the argument string in the opcode table. */ |
9608 | int type; | |
9609 | /* The number of bits in the short form of the opcode. */ | |
9610 | int nbits; | |
9611 | /* The number of bits in the extended form of the opcode. */ | |
9612 | int extbits; | |
9613 | /* The amount by which the short form is shifted when it is used; | |
9614 | for example, the sw instruction has a shift count of 2. */ | |
9615 | int shift; | |
9616 | /* The amount by which the short form is shifted when it is stored | |
9617 | into the instruction code. */ | |
9618 | int op_shift; | |
9619 | /* Non-zero if the short form is unsigned. */ | |
9620 | int unsp; | |
9621 | /* Non-zero if the extended form is unsigned. */ | |
9622 | int extu; | |
9623 | /* Non-zero if the value is PC relative. */ | |
9624 | int pcrel; | |
9625 | }; | |
9626 | ||
9627 | /* The mips16 immediate operand types. */ | |
9628 | ||
9629 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9630 | { | |
9631 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9632 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9633 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9634 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9635 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9636 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9637 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9638 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9639 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9640 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9641 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9642 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9643 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9644 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9645 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9646 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9647 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9648 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9649 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9650 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9651 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9652 | }; | |
9653 | ||
9654 | #define MIPS16_NUM_IMMED \ | |
9655 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9656 | ||
9657 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9658 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9659 | whether an extended value is needed; if one is needed, it sets | |
9660 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9661 | If SMALL is true, an unextended opcode was explicitly requested. | |
9662 | If EXT is true, an extended opcode was explicitly requested. If | |
9663 | WARN is true, warn if EXT does not match reality. */ | |
9664 | ||
9665 | static void | |
17a2f251 TS |
9666 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9667 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9668 | unsigned long *insn, bfd_boolean *use_extend, | |
9669 | unsigned short *extend) | |
252b5132 RH |
9670 | { |
9671 | register const struct mips16_immed_operand *op; | |
9672 | int mintiny, maxtiny; | |
b34976b6 | 9673 | bfd_boolean needext; |
252b5132 RH |
9674 | |
9675 | op = mips16_immed_operands; | |
9676 | while (op->type != type) | |
9677 | { | |
9678 | ++op; | |
9679 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9680 | } | |
9681 | ||
9682 | if (op->unsp) | |
9683 | { | |
9684 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9685 | { | |
9686 | mintiny = 1; | |
9687 | maxtiny = 1 << op->nbits; | |
9688 | } | |
9689 | else | |
9690 | { | |
9691 | mintiny = 0; | |
9692 | maxtiny = (1 << op->nbits) - 1; | |
9693 | } | |
9694 | } | |
9695 | else | |
9696 | { | |
9697 | mintiny = - (1 << (op->nbits - 1)); | |
9698 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9699 | } | |
9700 | ||
9701 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9702 | if (type == 'p' || type == 'q') | |
9703 | val /= 2; | |
9704 | ||
9705 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9706 | || val < (mintiny << op->shift) | |
9707 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9708 | needext = TRUE; |
252b5132 | 9709 | else |
b34976b6 | 9710 | needext = FALSE; |
252b5132 RH |
9711 | |
9712 | if (warn && ext && ! needext) | |
beae10d5 KH |
9713 | as_warn_where (file, line, |
9714 | _("extended operand requested but not required")); | |
252b5132 RH |
9715 | if (small && needext) |
9716 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9717 | ||
9718 | if (small || (! ext && ! needext)) | |
9719 | { | |
9720 | int insnval; | |
9721 | ||
b34976b6 | 9722 | *use_extend = FALSE; |
252b5132 RH |
9723 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9724 | insnval <<= op->op_shift; | |
9725 | *insn |= insnval; | |
9726 | } | |
9727 | else | |
9728 | { | |
9729 | long minext, maxext; | |
9730 | int extval; | |
9731 | ||
9732 | if (op->extu) | |
9733 | { | |
9734 | minext = 0; | |
9735 | maxext = (1 << op->extbits) - 1; | |
9736 | } | |
9737 | else | |
9738 | { | |
9739 | minext = - (1 << (op->extbits - 1)); | |
9740 | maxext = (1 << (op->extbits - 1)) - 1; | |
9741 | } | |
9742 | if (val < minext || val > maxext) | |
9743 | as_bad_where (file, line, | |
9744 | _("operand value out of range for instruction")); | |
9745 | ||
b34976b6 | 9746 | *use_extend = TRUE; |
252b5132 RH |
9747 | if (op->extbits == 16) |
9748 | { | |
9749 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9750 | val &= 0x1f; | |
9751 | } | |
9752 | else if (op->extbits == 15) | |
9753 | { | |
9754 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9755 | val &= 0xf; | |
9756 | } | |
9757 | else | |
9758 | { | |
9759 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9760 | val = 0; | |
9761 | } | |
9762 | ||
9763 | *extend = (unsigned short) extval; | |
9764 | *insn |= val; | |
9765 | } | |
9766 | } | |
9767 | \f | |
5e0116d5 | 9768 | static const struct percent_op_match |
ad8d3bb3 | 9769 | { |
5e0116d5 RS |
9770 | const char *str; |
9771 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9772 | } percent_op[] = |
9773 | { | |
5e0116d5 | 9774 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9775 | #ifdef OBJ_ELF |
5e0116d5 RS |
9776 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9777 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9778 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9779 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9780 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9781 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9782 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9783 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9784 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9785 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9786 | {"%half", BFD_RELOC_16}, | |
9787 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9788 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9789 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9790 | #endif |
5e0116d5 | 9791 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9792 | }; |
9793 | ||
252b5132 | 9794 | |
5e0116d5 RS |
9795 | /* Return true if *STR points to a relocation operator. When returning true, |
9796 | move *STR over the operator and store its relocation code in *RELOC. | |
9797 | Leave both *STR and *RELOC alone when returning false. */ | |
9798 | ||
9799 | static bfd_boolean | |
17a2f251 | 9800 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9801 | { |
5e0116d5 | 9802 | size_t i; |
76b3015f | 9803 | |
5e0116d5 RS |
9804 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
9805 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 9806 | { |
5e0116d5 RS |
9807 | *str += strlen (percent_op[i].str); |
9808 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9809 | |
5e0116d5 RS |
9810 | /* Check whether the output BFD supports this relocation. |
9811 | If not, issue an error and fall back on something safe. */ | |
9812 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9813 | { |
5e0116d5 RS |
9814 | as_bad ("relocation %s isn't supported by the current ABI", |
9815 | percent_op[i].str); | |
9816 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 9817 | } |
5e0116d5 | 9818 | return TRUE; |
394f9b3a | 9819 | } |
5e0116d5 | 9820 | return FALSE; |
394f9b3a | 9821 | } |
ad8d3bb3 | 9822 | |
ad8d3bb3 | 9823 | |
5e0116d5 RS |
9824 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9825 | expression in *EP and the relocations in the array starting | |
9826 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9827 | |
5e0116d5 RS |
9828 | On exit, EXPR_END points to the first character after the expression. |
9829 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 9830 | |
5e0116d5 | 9831 | static size_t |
17a2f251 TS |
9832 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9833 | char *str) | |
ad8d3bb3 | 9834 | { |
5e0116d5 RS |
9835 | bfd_reloc_code_real_type reversed_reloc[3]; |
9836 | size_t reloc_index, i; | |
09b8f35a RS |
9837 | int crux_depth, str_depth; |
9838 | char *crux; | |
5e0116d5 RS |
9839 | |
9840 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9841 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9842 | of the main expression and with CRUX_DEPTH containing the number | |
9843 | of open brackets at that point. */ | |
9844 | reloc_index = -1; | |
9845 | str_depth = 0; | |
9846 | do | |
fb1b3232 | 9847 | { |
09b8f35a RS |
9848 | reloc_index++; |
9849 | crux = str; | |
9850 | crux_depth = str_depth; | |
9851 | ||
9852 | /* Skip over whitespace and brackets, keeping count of the number | |
9853 | of brackets. */ | |
9854 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9855 | if (*str++ == '(') | |
9856 | str_depth++; | |
5e0116d5 | 9857 | } |
09b8f35a RS |
9858 | while (*str == '%' |
9859 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9860 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9861 | |
09b8f35a | 9862 | my_getExpression (ep, crux); |
5e0116d5 | 9863 | str = expr_end; |
394f9b3a | 9864 | |
5e0116d5 | 9865 | /* Match every open bracket. */ |
09b8f35a | 9866 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9867 | if (*str++ == ')') |
09b8f35a | 9868 | crux_depth--; |
394f9b3a | 9869 | |
09b8f35a | 9870 | if (crux_depth > 0) |
5e0116d5 | 9871 | as_bad ("unclosed '('"); |
394f9b3a | 9872 | |
5e0116d5 | 9873 | expr_end = str; |
252b5132 | 9874 | |
64bdfcaf RS |
9875 | if (reloc_index == 0) |
9876 | reloc[0] = BFD_RELOC_LO16; | |
9877 | else | |
9878 | { | |
9879 | prev_reloc_op_frag = frag_now; | |
9880 | for (i = 0; i < reloc_index; i++) | |
9881 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9882 | } | |
fb1b3232 | 9883 | |
5e0116d5 | 9884 | return reloc_index; |
252b5132 RH |
9885 | } |
9886 | ||
9887 | static void | |
17a2f251 | 9888 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9889 | { |
9890 | char *save_in; | |
98aa84af | 9891 | valueT val; |
252b5132 RH |
9892 | |
9893 | save_in = input_line_pointer; | |
9894 | input_line_pointer = str; | |
9895 | expression (ep); | |
9896 | expr_end = input_line_pointer; | |
9897 | input_line_pointer = save_in; | |
9898 | ||
9899 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9900 | then we bump the value of the symbol by 1 since that is how other | |
9901 | text symbols are handled. We don't bother to handle complex | |
9902 | expressions, just `.' plus or minus a constant. */ | |
9903 | if (mips_opts.mips16 | |
9904 | && ep->X_op == O_symbol | |
9905 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9906 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9907 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9908 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9909 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9910 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9911 | } |
9912 | ||
9913 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9914 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9915 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9916 | returned, or NULL on OK. */ |
9917 | ||
9918 | char * | |
17a2f251 | 9919 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9920 | { |
9921 | int prec; | |
9922 | LITTLENUM_TYPE words[4]; | |
9923 | char *t; | |
9924 | int i; | |
9925 | ||
9926 | switch (type) | |
9927 | { | |
9928 | case 'f': | |
9929 | prec = 2; | |
9930 | break; | |
9931 | ||
9932 | case 'd': | |
9933 | prec = 4; | |
9934 | break; | |
9935 | ||
9936 | default: | |
9937 | *sizeP = 0; | |
9938 | return _("bad call to md_atof"); | |
9939 | } | |
9940 | ||
9941 | t = atof_ieee (input_line_pointer, type, words); | |
9942 | if (t) | |
9943 | input_line_pointer = t; | |
9944 | ||
9945 | *sizeP = prec * 2; | |
9946 | ||
9947 | if (! target_big_endian) | |
9948 | { | |
9949 | for (i = prec - 1; i >= 0; i--) | |
9950 | { | |
17a2f251 | 9951 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9952 | litP += 2; |
9953 | } | |
9954 | } | |
9955 | else | |
9956 | { | |
9957 | for (i = 0; i < prec; i++) | |
9958 | { | |
17a2f251 | 9959 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9960 | litP += 2; |
9961 | } | |
9962 | } | |
bdaaa2e1 | 9963 | |
252b5132 RH |
9964 | return NULL; |
9965 | } | |
9966 | ||
9967 | void | |
17a2f251 | 9968 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9969 | { |
9970 | if (target_big_endian) | |
9971 | number_to_chars_bigendian (buf, val, n); | |
9972 | else | |
9973 | number_to_chars_littleendian (buf, val, n); | |
9974 | } | |
9975 | \f | |
ae948b86 | 9976 | #ifdef OBJ_ELF |
e013f690 TS |
9977 | static int support_64bit_objects(void) |
9978 | { | |
9979 | const char **list, **l; | |
aa3d8fdf | 9980 | int yes; |
e013f690 TS |
9981 | |
9982 | list = bfd_target_list (); | |
9983 | for (l = list; *l != NULL; l++) | |
9984 | #ifdef TE_TMIPS | |
9985 | /* This is traditional mips */ | |
9986 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9987 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9988 | #else | |
9989 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9990 | || strcmp (*l, "elf64-littlemips") == 0) | |
9991 | #endif | |
9992 | break; | |
aa3d8fdf | 9993 | yes = (*l != NULL); |
e013f690 | 9994 | free (list); |
aa3d8fdf | 9995 | return yes; |
e013f690 | 9996 | } |
ae948b86 | 9997 | #endif /* OBJ_ELF */ |
e013f690 | 9998 | |
78849248 | 9999 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10000 | |
e972090a NC |
10001 | struct option md_longopts[] = |
10002 | { | |
f9b4148d CD |
10003 | /* Options which specify architecture. */ |
10004 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10005 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10006 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10007 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10008 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10009 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10010 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10011 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10012 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10013 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10014 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10015 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10016 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10017 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10018 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10019 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10020 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10021 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10022 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10023 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10024 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10025 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10026 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10027 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10028 | |
10029 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10030 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10031 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10032 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10033 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10034 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10035 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10036 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10037 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10038 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10039 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10040 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10041 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10042 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10043 | ||
10044 | /* Old-style architecture options. Don't add more of these. */ | |
10045 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10046 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10047 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10048 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10049 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10050 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10051 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10052 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10053 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10054 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10055 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10056 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10057 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10058 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10059 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10060 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10061 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10062 | ||
10063 | /* Options which enable bug fixes. */ | |
10064 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10065 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10066 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10067 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10068 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10069 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10070 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10071 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10072 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10073 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10074 | |
10075 | /* Miscellaneous options. */ | |
10076 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10077 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10078 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10079 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10080 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10081 | {"break", no_argument, NULL, OPTION_BREAK}, |
10082 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10083 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10084 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10085 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10086 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10087 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10088 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10089 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10090 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10091 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10092 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10093 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10094 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10095 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10096 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10097 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10098 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10099 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10100 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10101 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10102 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10103 | |
10104 | /* ELF-specific options. */ | |
156c2f8b | 10105 | #ifdef OBJ_ELF |
1ffcab4b | 10106 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12) |
156c2f8b | 10107 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10108 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10109 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10110 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10111 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10112 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10113 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10114 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10115 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10116 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10117 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10118 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10119 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10120 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10121 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10122 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10123 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10124 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10125 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10126 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10127 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10128 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10129 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10130 | #endif /* OBJ_ELF */ |
f9b4148d | 10131 | |
252b5132 RH |
10132 | {NULL, no_argument, NULL, 0} |
10133 | }; | |
156c2f8b | 10134 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10135 | |
316f5878 RS |
10136 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10137 | NEW_VALUE. Warn if another value was already specified. Note: | |
10138 | we have to defer parsing the -march and -mtune arguments in order | |
10139 | to handle 'from-abi' correctly, since the ABI might be specified | |
10140 | in a later argument. */ | |
10141 | ||
10142 | static void | |
17a2f251 | 10143 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10144 | { |
10145 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10146 | as_warn (_("A different %s was already specified, is now %s"), | |
10147 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10148 | new_value); | |
10149 | ||
10150 | *string_ptr = new_value; | |
10151 | } | |
10152 | ||
252b5132 | 10153 | int |
17a2f251 | 10154 | md_parse_option (int c, char *arg) |
252b5132 RH |
10155 | { |
10156 | switch (c) | |
10157 | { | |
119d663a NC |
10158 | case OPTION_CONSTRUCT_FLOATS: |
10159 | mips_disable_float_construction = 0; | |
10160 | break; | |
bdaaa2e1 | 10161 | |
119d663a NC |
10162 | case OPTION_NO_CONSTRUCT_FLOATS: |
10163 | mips_disable_float_construction = 1; | |
10164 | break; | |
bdaaa2e1 | 10165 | |
252b5132 RH |
10166 | case OPTION_TRAP: |
10167 | mips_trap = 1; | |
10168 | break; | |
10169 | ||
10170 | case OPTION_BREAK: | |
10171 | mips_trap = 0; | |
10172 | break; | |
10173 | ||
10174 | case OPTION_EB: | |
10175 | target_big_endian = 1; | |
10176 | break; | |
10177 | ||
10178 | case OPTION_EL: | |
10179 | target_big_endian = 0; | |
10180 | break; | |
10181 | ||
10182 | case 'O': | |
10183 | if (arg && arg[1] == '0') | |
10184 | mips_optimize = 1; | |
10185 | else | |
10186 | mips_optimize = 2; | |
10187 | break; | |
10188 | ||
10189 | case 'g': | |
10190 | if (arg == NULL) | |
10191 | mips_debug = 2; | |
10192 | else | |
10193 | mips_debug = atoi (arg); | |
10194 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10195 | optimizations which limit full symbolic debugging. We take | |
10196 | that to be equivalent to -O0. */ | |
10197 | if (mips_debug == 2) | |
10198 | mips_optimize = 1; | |
10199 | break; | |
10200 | ||
10201 | case OPTION_MIPS1: | |
316f5878 | 10202 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10203 | break; |
10204 | ||
10205 | case OPTION_MIPS2: | |
316f5878 | 10206 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10207 | break; |
10208 | ||
10209 | case OPTION_MIPS3: | |
316f5878 | 10210 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10211 | break; |
10212 | ||
10213 | case OPTION_MIPS4: | |
316f5878 | 10214 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10215 | break; |
10216 | ||
84ea6cf2 | 10217 | case OPTION_MIPS5: |
316f5878 | 10218 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10219 | break; |
10220 | ||
e7af610e | 10221 | case OPTION_MIPS32: |
316f5878 | 10222 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10223 | break; |
10224 | ||
af7ee8bf CD |
10225 | case OPTION_MIPS32R2: |
10226 | file_mips_isa = ISA_MIPS32R2; | |
10227 | break; | |
10228 | ||
5f74bc13 CD |
10229 | case OPTION_MIPS64R2: |
10230 | file_mips_isa = ISA_MIPS64R2; | |
10231 | break; | |
10232 | ||
84ea6cf2 | 10233 | case OPTION_MIPS64: |
316f5878 | 10234 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10235 | break; |
10236 | ||
ec68c924 | 10237 | case OPTION_MTUNE: |
316f5878 RS |
10238 | mips_set_option_string (&mips_tune_string, arg); |
10239 | break; | |
ec68c924 | 10240 | |
316f5878 RS |
10241 | case OPTION_MARCH: |
10242 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10243 | break; |
10244 | ||
10245 | case OPTION_M4650: | |
316f5878 RS |
10246 | mips_set_option_string (&mips_arch_string, "4650"); |
10247 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10248 | break; |
10249 | ||
10250 | case OPTION_NO_M4650: | |
10251 | break; | |
10252 | ||
10253 | case OPTION_M4010: | |
316f5878 RS |
10254 | mips_set_option_string (&mips_arch_string, "4010"); |
10255 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10256 | break; |
10257 | ||
10258 | case OPTION_NO_M4010: | |
10259 | break; | |
10260 | ||
10261 | case OPTION_M4100: | |
316f5878 RS |
10262 | mips_set_option_string (&mips_arch_string, "4100"); |
10263 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10264 | break; |
10265 | ||
10266 | case OPTION_NO_M4100: | |
10267 | break; | |
10268 | ||
252b5132 | 10269 | case OPTION_M3900: |
316f5878 RS |
10270 | mips_set_option_string (&mips_arch_string, "3900"); |
10271 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10272 | break; |
bdaaa2e1 | 10273 | |
252b5132 RH |
10274 | case OPTION_NO_M3900: |
10275 | break; | |
10276 | ||
deec1734 CD |
10277 | case OPTION_MDMX: |
10278 | mips_opts.ase_mdmx = 1; | |
10279 | break; | |
10280 | ||
10281 | case OPTION_NO_MDMX: | |
10282 | mips_opts.ase_mdmx = 0; | |
10283 | break; | |
10284 | ||
252b5132 RH |
10285 | case OPTION_MIPS16: |
10286 | mips_opts.mips16 = 1; | |
b34976b6 | 10287 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10288 | break; |
10289 | ||
10290 | case OPTION_NO_MIPS16: | |
10291 | mips_opts.mips16 = 0; | |
b34976b6 | 10292 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10293 | break; |
10294 | ||
1f25f5d3 CD |
10295 | case OPTION_MIPS3D: |
10296 | mips_opts.ase_mips3d = 1; | |
10297 | break; | |
10298 | ||
10299 | case OPTION_NO_MIPS3D: | |
10300 | mips_opts.ase_mips3d = 0; | |
10301 | break; | |
10302 | ||
d766e8ec RS |
10303 | case OPTION_FIX_VR4120: |
10304 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10305 | break; |
10306 | ||
d766e8ec RS |
10307 | case OPTION_NO_FIX_VR4120: |
10308 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10309 | break; |
10310 | ||
4a6a3df4 AO |
10311 | case OPTION_RELAX_BRANCH: |
10312 | mips_relax_branch = 1; | |
10313 | break; | |
10314 | ||
10315 | case OPTION_NO_RELAX_BRANCH: | |
10316 | mips_relax_branch = 0; | |
10317 | break; | |
10318 | ||
0f074f60 | 10319 | #ifdef OBJ_ELF |
252b5132 RH |
10320 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10321 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10322 | intended to be compatible with Irix 5. */ | |
10323 | case OPTION_CALL_SHARED: | |
10324 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10325 | { | |
10326 | as_bad (_("-call_shared is supported only for ELF format")); | |
10327 | return 0; | |
10328 | } | |
10329 | mips_pic = SVR4_PIC; | |
143d77c5 | 10330 | mips_abicalls = TRUE; |
252b5132 RH |
10331 | if (g_switch_seen && g_switch_value != 0) |
10332 | { | |
10333 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10334 | return 0; | |
10335 | } | |
10336 | g_switch_value = 0; | |
10337 | break; | |
10338 | ||
10339 | case OPTION_NON_SHARED: | |
10340 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10341 | { | |
10342 | as_bad (_("-non_shared is supported only for ELF format")); | |
10343 | return 0; | |
10344 | } | |
10345 | mips_pic = NO_PIC; | |
143d77c5 | 10346 | mips_abicalls = FALSE; |
252b5132 RH |
10347 | break; |
10348 | ||
10349 | /* The -xgot option tells the assembler to use 32 offsets when | |
10350 | accessing the got in SVR4_PIC mode. It is for Irix | |
10351 | compatibility. */ | |
10352 | case OPTION_XGOT: | |
10353 | mips_big_got = 1; | |
10354 | break; | |
0f074f60 | 10355 | #endif /* OBJ_ELF */ |
252b5132 RH |
10356 | |
10357 | case 'G': | |
3e722fb5 | 10358 | if (mips_pic == SVR4_PIC) |
252b5132 | 10359 | { |
3e722fb5 | 10360 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10361 | return 0; |
10362 | } | |
10363 | else | |
10364 | g_switch_value = atoi (arg); | |
10365 | g_switch_seen = 1; | |
10366 | break; | |
10367 | ||
0f074f60 | 10368 | #ifdef OBJ_ELF |
34ba82a8 TS |
10369 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10370 | and -mabi=64. */ | |
252b5132 | 10371 | case OPTION_32: |
34ba82a8 TS |
10372 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10373 | { | |
10374 | as_bad (_("-32 is supported for ELF format only")); | |
10375 | return 0; | |
10376 | } | |
316f5878 | 10377 | mips_abi = O32_ABI; |
252b5132 RH |
10378 | break; |
10379 | ||
e013f690 | 10380 | case OPTION_N32: |
34ba82a8 TS |
10381 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10382 | { | |
10383 | as_bad (_("-n32 is supported for ELF format only")); | |
10384 | return 0; | |
10385 | } | |
316f5878 | 10386 | mips_abi = N32_ABI; |
e013f690 | 10387 | break; |
252b5132 | 10388 | |
e013f690 | 10389 | case OPTION_64: |
34ba82a8 TS |
10390 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10391 | { | |
10392 | as_bad (_("-64 is supported for ELF format only")); | |
10393 | return 0; | |
10394 | } | |
316f5878 | 10395 | mips_abi = N64_ABI; |
e013f690 TS |
10396 | if (! support_64bit_objects()) |
10397 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10398 | break; |
ae948b86 | 10399 | #endif /* OBJ_ELF */ |
252b5132 | 10400 | |
c97ef257 | 10401 | case OPTION_GP32: |
a325df1d | 10402 | file_mips_gp32 = 1; |
c97ef257 AH |
10403 | break; |
10404 | ||
10405 | case OPTION_GP64: | |
a325df1d | 10406 | file_mips_gp32 = 0; |
c97ef257 | 10407 | break; |
252b5132 | 10408 | |
ca4e0257 | 10409 | case OPTION_FP32: |
a325df1d | 10410 | file_mips_fp32 = 1; |
316f5878 RS |
10411 | break; |
10412 | ||
10413 | case OPTION_FP64: | |
10414 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10415 | break; |
10416 | ||
ae948b86 | 10417 | #ifdef OBJ_ELF |
252b5132 | 10418 | case OPTION_MABI: |
34ba82a8 TS |
10419 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10420 | { | |
10421 | as_bad (_("-mabi is supported for ELF format only")); | |
10422 | return 0; | |
10423 | } | |
e013f690 | 10424 | if (strcmp (arg, "32") == 0) |
316f5878 | 10425 | mips_abi = O32_ABI; |
e013f690 | 10426 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10427 | mips_abi = O64_ABI; |
e013f690 | 10428 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10429 | mips_abi = N32_ABI; |
e013f690 TS |
10430 | else if (strcmp (arg, "64") == 0) |
10431 | { | |
316f5878 | 10432 | mips_abi = N64_ABI; |
e013f690 TS |
10433 | if (! support_64bit_objects()) |
10434 | as_fatal (_("No compiled in support for 64 bit object file " | |
10435 | "format")); | |
10436 | } | |
10437 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10438 | mips_abi = EABI_ABI; |
e013f690 | 10439 | else |
da0e507f TS |
10440 | { |
10441 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10442 | return 0; | |
10443 | } | |
252b5132 | 10444 | break; |
e013f690 | 10445 | #endif /* OBJ_ELF */ |
252b5132 | 10446 | |
6b76fefe | 10447 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10448 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10449 | break; |
10450 | ||
9ee72ff1 | 10451 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10452 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10453 | break; |
10454 | ||
ecb4347a DJ |
10455 | #ifdef OBJ_ELF |
10456 | case OPTION_MDEBUG: | |
b34976b6 | 10457 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10458 | break; |
10459 | ||
10460 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10461 | mips_flag_mdebug = FALSE; |
ecb4347a | 10462 | break; |
dcd410fe RO |
10463 | |
10464 | case OPTION_PDR: | |
10465 | mips_flag_pdr = TRUE; | |
10466 | break; | |
10467 | ||
10468 | case OPTION_NO_PDR: | |
10469 | mips_flag_pdr = FALSE; | |
10470 | break; | |
ecb4347a DJ |
10471 | #endif /* OBJ_ELF */ |
10472 | ||
252b5132 RH |
10473 | default: |
10474 | return 0; | |
10475 | } | |
10476 | ||
10477 | return 1; | |
10478 | } | |
316f5878 RS |
10479 | \f |
10480 | /* Set up globals to generate code for the ISA or processor | |
10481 | described by INFO. */ | |
252b5132 | 10482 | |
252b5132 | 10483 | static void |
17a2f251 | 10484 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10485 | { |
316f5878 | 10486 | if (info != 0) |
252b5132 | 10487 | { |
fef14a42 TS |
10488 | file_mips_arch = info->cpu; |
10489 | mips_opts.arch = info->cpu; | |
316f5878 | 10490 | mips_opts.isa = info->isa; |
252b5132 | 10491 | } |
252b5132 RH |
10492 | } |
10493 | ||
252b5132 | 10494 | |
316f5878 | 10495 | /* Likewise for tuning. */ |
252b5132 | 10496 | |
316f5878 | 10497 | static void |
17a2f251 | 10498 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10499 | { |
10500 | if (info != 0) | |
fef14a42 | 10501 | mips_tune = info->cpu; |
316f5878 | 10502 | } |
80cc45a5 | 10503 | |
34ba82a8 | 10504 | |
252b5132 | 10505 | void |
17a2f251 | 10506 | mips_after_parse_args (void) |
e9670677 | 10507 | { |
fef14a42 TS |
10508 | const struct mips_cpu_info *arch_info = 0; |
10509 | const struct mips_cpu_info *tune_info = 0; | |
10510 | ||
e9670677 MR |
10511 | /* GP relative stuff not working for PE */ |
10512 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10513 | && g_switch_value != 0) | |
10514 | { | |
10515 | if (g_switch_seen) | |
10516 | as_bad (_("-G not supported in this configuration.")); | |
10517 | g_switch_value = 0; | |
10518 | } | |
10519 | ||
cac012d6 AO |
10520 | if (mips_abi == NO_ABI) |
10521 | mips_abi = MIPS_DEFAULT_ABI; | |
10522 | ||
22923709 RS |
10523 | /* The following code determines the architecture and register size. |
10524 | Similar code was added to GCC 3.3 (see override_options() in | |
10525 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10526 | as much as possible. */ | |
e9670677 | 10527 | |
316f5878 | 10528 | if (mips_arch_string != 0) |
fef14a42 | 10529 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10530 | |
316f5878 | 10531 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10532 | { |
316f5878 | 10533 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10534 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10535 | the -march selection (if any). */ |
fef14a42 | 10536 | if (arch_info != 0) |
e9670677 | 10537 | { |
316f5878 RS |
10538 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10539 | There's no harm in specifying both as long as the ISA levels | |
10540 | are the same. */ | |
fef14a42 | 10541 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10542 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10543 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10544 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10545 | } |
316f5878 | 10546 | else |
fef14a42 | 10547 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10548 | } |
10549 | ||
fef14a42 TS |
10550 | if (arch_info == 0) |
10551 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10552 | |
fef14a42 | 10553 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10554 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10555 | arch_info->name); |
10556 | ||
10557 | mips_set_architecture (arch_info); | |
10558 | ||
10559 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10560 | if (mips_tune_string != 0) | |
10561 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10562 | |
fef14a42 TS |
10563 | if (tune_info == 0) |
10564 | mips_set_tune (arch_info); | |
10565 | else | |
10566 | mips_set_tune (tune_info); | |
e9670677 | 10567 | |
316f5878 | 10568 | if (file_mips_gp32 >= 0) |
e9670677 | 10569 | { |
316f5878 RS |
10570 | /* The user specified the size of the integer registers. Make sure |
10571 | it agrees with the ABI and ISA. */ | |
10572 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10573 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10574 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10575 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10576 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10577 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10578 | } |
10579 | else | |
10580 | { | |
316f5878 RS |
10581 | /* Infer the integer register size from the ABI and processor. |
10582 | Restrict ourselves to 32-bit registers if that's all the | |
10583 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10584 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10585 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10586 | } |
10587 | ||
316f5878 RS |
10588 | /* ??? GAS treats single-float processors as though they had 64-bit |
10589 | float registers (although it complains when double-precision | |
10590 | instructions are used). As things stand, saying they have 32-bit | |
10591 | registers would lead to spurious "register must be even" messages. | |
10592 | So here we assume float registers are always the same size as | |
10593 | integer ones, unless the user says otherwise. */ | |
10594 | if (file_mips_fp32 < 0) | |
10595 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10596 | |
316f5878 | 10597 | /* End of GCC-shared inference code. */ |
e9670677 | 10598 | |
17a2f251 TS |
10599 | /* This flag is set when we have a 64-bit capable CPU but use only |
10600 | 32-bit wide registers. Note that EABI does not use it. */ | |
10601 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10602 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10603 | || mips_abi == O32_ABI)) | |
316f5878 | 10604 | mips_32bitmode = 1; |
e9670677 MR |
10605 | |
10606 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10607 | as_bad (_("trap exception not supported at ISA 1")); | |
10608 | ||
e9670677 MR |
10609 | /* If the selected architecture includes support for ASEs, enable |
10610 | generation of code for them. */ | |
a4672219 | 10611 | if (mips_opts.mips16 == -1) |
fef14a42 | 10612 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10613 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10614 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10615 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10616 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10617 | |
e9670677 | 10618 | file_mips_isa = mips_opts.isa; |
a4672219 | 10619 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10620 | file_ase_mips3d = mips_opts.ase_mips3d; |
10621 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10622 | mips_opts.gp32 = file_mips_gp32; | |
10623 | mips_opts.fp32 = file_mips_fp32; | |
10624 | ||
ecb4347a DJ |
10625 | if (mips_flag_mdebug < 0) |
10626 | { | |
10627 | #ifdef OBJ_MAYBE_ECOFF | |
10628 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10629 | mips_flag_mdebug = 1; | |
10630 | else | |
10631 | #endif /* OBJ_MAYBE_ECOFF */ | |
10632 | mips_flag_mdebug = 0; | |
10633 | } | |
e9670677 MR |
10634 | } |
10635 | \f | |
10636 | void | |
17a2f251 | 10637 | mips_init_after_args (void) |
252b5132 RH |
10638 | { |
10639 | /* initialize opcodes */ | |
10640 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10641 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10642 | } |
10643 | ||
10644 | long | |
17a2f251 | 10645 | md_pcrel_from (fixS *fixP) |
252b5132 | 10646 | { |
a7ebbfdf TS |
10647 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10648 | switch (fixP->fx_r_type) | |
10649 | { | |
10650 | case BFD_RELOC_16_PCREL_S2: | |
10651 | case BFD_RELOC_MIPS_JMP: | |
10652 | /* Return the address of the delay slot. */ | |
10653 | return addr + 4; | |
10654 | default: | |
10655 | return addr; | |
10656 | } | |
252b5132 RH |
10657 | } |
10658 | ||
252b5132 RH |
10659 | /* This is called before the symbol table is processed. In order to |
10660 | work with gcc when using mips-tfile, we must keep all local labels. | |
10661 | However, in other cases, we want to discard them. If we were | |
10662 | called with -g, but we didn't see any debugging information, it may | |
10663 | mean that gcc is smuggling debugging information through to | |
10664 | mips-tfile, in which case we must generate all local labels. */ | |
10665 | ||
10666 | void | |
17a2f251 | 10667 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10668 | { |
10669 | #ifndef NO_ECOFF_DEBUGGING | |
10670 | if (ECOFF_DEBUGGING | |
10671 | && mips_debug != 0 | |
10672 | && ! ecoff_debugging_seen) | |
10673 | flag_keep_locals = 1; | |
10674 | #endif | |
10675 | } | |
10676 | ||
3b91255e RS |
10677 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10678 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10679 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10680 | relocation operators. | |
10681 | ||
10682 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10683 | expression if: | |
10684 | ||
10685 | (a) it refers to the same symbol; and | |
10686 | (b) the offset applied in the %lo() expression is no lower than | |
10687 | the offset applied in the %got() or %hi(). | |
10688 | ||
10689 | (b) allows us to cope with code like: | |
10690 | ||
10691 | lui $4,%hi(foo) | |
10692 | lh $4,%lo(foo+2)($4) | |
10693 | ||
10694 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10695 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10696 | the high 16 bits. | |
10697 | ||
10698 | When several %lo()s match a particular %got() or %hi(), we use the | |
10699 | following rules to distinguish them: | |
10700 | ||
10701 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10702 | higher offsets. | |
10703 | ||
10704 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10705 | that already have a matching %got() or %hi(). | |
10706 | ||
10707 | (3) later %lo()s are better than earlier %lo()s. | |
10708 | ||
10709 | These rules are applied in order. | |
10710 | ||
10711 | (1) means, among other things, that %lo()s with identical offsets are | |
10712 | chosen if they exist. | |
10713 | ||
10714 | (2) means that we won't associate several high-part relocations with | |
10715 | the same low-part relocation unless there's no alternative. Having | |
10716 | several high parts for the same low part is a GNU extension; this rule | |
10717 | allows careful users to avoid it. | |
10718 | ||
10719 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10720 | with the last high-part relocation being at the front of the list. | |
10721 | It therefore makes sense to choose the last matching low-part | |
10722 | relocation, all other things being equal. It's also easier | |
10723 | to code that way. */ | |
252b5132 RH |
10724 | |
10725 | void | |
17a2f251 | 10726 | mips_frob_file (void) |
252b5132 RH |
10727 | { |
10728 | struct mips_hi_fixup *l; | |
10729 | ||
10730 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10731 | { | |
10732 | segment_info_type *seginfo; | |
3b91255e RS |
10733 | bfd_boolean matched_lo_p; |
10734 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10735 | |
5919d012 | 10736 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10737 | |
5919d012 RS |
10738 | /* If a GOT16 relocation turns out to be against a global symbol, |
10739 | there isn't supposed to be a matching LO. */ | |
10740 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10741 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10742 | continue; | |
10743 | ||
10744 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10745 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10746 | continue; |
10747 | ||
252b5132 | 10748 | seginfo = seg_info (l->seg); |
252b5132 | 10749 | |
3b91255e RS |
10750 | /* Set HI_POS to the position of this relocation in the chain. |
10751 | Set LO_POS to the position of the chosen low-part relocation. | |
10752 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10753 | relocation that matches an immediately-preceding high-part | |
10754 | relocation. */ | |
10755 | hi_pos = NULL; | |
10756 | lo_pos = NULL; | |
10757 | matched_lo_p = FALSE; | |
10758 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10759 | { | |
10760 | if (*pos == l->fixp) | |
10761 | hi_pos = pos; | |
10762 | ||
10763 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10764 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10765 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10766 | && (lo_pos == NULL | |
10767 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10768 | || (!matched_lo_p | |
10769 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10770 | lo_pos = pos; | |
10771 | ||
10772 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10773 | && fixup_has_matching_lo_p (*pos)); | |
10774 | } | |
10775 | ||
10776 | /* If we found a match, remove the high-part relocation from its | |
10777 | current position and insert it before the low-part relocation. | |
10778 | Make the offsets match so that fixup_has_matching_lo_p() | |
10779 | will return true. | |
10780 | ||
10781 | We don't warn about unmatched high-part relocations since some | |
10782 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10783 | instructions. */ | |
10784 | if (lo_pos != NULL) | |
10785 | { | |
10786 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10787 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10788 | { |
3b91255e RS |
10789 | *hi_pos = l->fixp->fx_next; |
10790 | l->fixp->fx_next = *lo_pos; | |
10791 | *lo_pos = l->fixp; | |
252b5132 | 10792 | } |
252b5132 RH |
10793 | } |
10794 | } | |
10795 | } | |
10796 | ||
3e722fb5 | 10797 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10798 | We have to prevent gas from dropping them. */ |
252b5132 | 10799 | |
252b5132 | 10800 | int |
17a2f251 | 10801 | mips_force_relocation (fixS *fixp) |
252b5132 | 10802 | { |
ae6063d4 | 10803 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10804 | return 1; |
10805 | ||
f6688943 TS |
10806 | if (HAVE_NEWABI |
10807 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10808 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10809 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10810 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10811 | return 1; | |
10812 | ||
3e722fb5 | 10813 | return 0; |
252b5132 RH |
10814 | } |
10815 | ||
45f8dfe8 AO |
10816 | /* This hook is called before a fix is simplified. We don't really |
10817 | decide whether to skip a fix here. Rather, we turn global symbols | |
10818 | used as branch targets into local symbols, such that they undergo | |
10819 | simplification. We can only do this if the symbol is defined and | |
10820 | it is in the same section as the branch. If this doesn't hold, we | |
10821 | emit a better error message than just saying the relocation is not | |
10822 | valid for the selected object format. | |
10823 | ||
10824 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10825 | segment in which the fix up occurs. The return value should be | |
10826 | non-zero to indicate the fix-up is valid for further | |
10827 | simplifications. */ | |
10828 | ||
10829 | int | |
17a2f251 | 10830 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10831 | { |
10832 | /* There's a lot of discussion on whether it should be possible to | |
10833 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10834 | seems to be that it can, but gas/bfd are very broken in creating | |
10835 | RELA relocations for this, so for now we only accept branches to | |
10836 | symbols in the same section. Anything else is of dubious value, | |
10837 | since there's no guarantee that at link time the symbol would be | |
10838 | in range. Even for branches to local symbols this is arguably | |
10839 | wrong, since it we assume the symbol is not going to be | |
10840 | overridden, which should be possible per ELF library semantics, | |
10841 | but then, there isn't a dynamic relocation that could be used to | |
10842 | this effect, and the target would likely be out of range as well. | |
10843 | ||
10844 | Unfortunately, it seems that there is too much code out there | |
10845 | that relies on branches to symbols that are global to be resolved | |
10846 | as if they were local, like the IRIX tools do, so we do it as | |
10847 | well, but with a warning so that people are reminded to fix their | |
10848 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10849 | targets, this entire block should go away (and probably the | |
10850 | whole function). */ | |
10851 | ||
10852 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10853 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10854 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10855 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10856 | && fixP->fx_addsy) | |
10857 | { | |
10858 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10859 | { | |
10860 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10861 | _("Cannot branch to undefined symbol.")); | |
10862 | /* Avoid any further errors about this fixup. */ | |
10863 | fixP->fx_done = 1; | |
10864 | } | |
10865 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10866 | { | |
10867 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10868 | _("Cannot branch to symbol in another section.")); | |
10869 | fixP->fx_done = 1; | |
10870 | } | |
10871 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10872 | { | |
10873 | symbolS *sym = fixP->fx_addsy; | |
10874 | ||
115695a8 CD |
10875 | if (mips_pic == SVR4_PIC) |
10876 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10877 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10878 | |
10879 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10880 | S_GET_SEGMENT (sym), | |
10881 | S_GET_VALUE (sym), | |
10882 | symbol_get_frag (sym)); | |
10883 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10884 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10885 | assert (symbol_resolved_p (sym)); | |
10886 | symbol_mark_resolved (fixP->fx_addsy); | |
10887 | } | |
10888 | } | |
10889 | ||
10890 | return 1; | |
10891 | } | |
10892 | ||
252b5132 RH |
10893 | /* Apply a fixup to the object file. */ |
10894 | ||
94f592af | 10895 | void |
17a2f251 | 10896 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10897 | { |
874e8986 | 10898 | bfd_byte *buf; |
98aa84af | 10899 | long insn; |
ed6fb7bd | 10900 | static int previous_fx_r_type = 0; |
a7ebbfdf | 10901 | reloc_howto_type *howto; |
252b5132 | 10902 | |
a7ebbfdf TS |
10903 | /* We ignore generic BFD relocations we don't know about. */ |
10904 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10905 | if (! howto) | |
10906 | return; | |
65551fa4 | 10907 | |
252b5132 RH |
10908 | assert (fixP->fx_size == 4 |
10909 | || fixP->fx_r_type == BFD_RELOC_16 | |
10910 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10911 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10912 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10913 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10914 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10915 | |
a7ebbfdf | 10916 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10917 | |
ed6fb7bd | 10918 | /* We are not done if this is a composite relocation to set up gp. */ |
3e722fb5 CD |
10919 | assert (! fixP->fx_pcrel); |
10920 | if (fixP->fx_addsy == NULL | |
ed6fb7bd | 10921 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB |
10181a0d AO |
10922 | || (fixP->fx_r_type == BFD_RELOC_64 |
10923 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
10924 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
10925 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
10926 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
10927 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 10928 | fixP->fx_done = 1; |
ed6fb7bd | 10929 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
10930 | |
10931 | switch (fixP->fx_r_type) | |
10932 | { | |
10933 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10934 | case BFD_RELOC_MIPS_SHIFT5: |
10935 | case BFD_RELOC_MIPS_SHIFT6: | |
10936 | case BFD_RELOC_MIPS_GOT_DISP: | |
10937 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10938 | case BFD_RELOC_MIPS_GOT_OFST: | |
10939 | case BFD_RELOC_MIPS_SUB: | |
10940 | case BFD_RELOC_MIPS_INSERT_A: | |
10941 | case BFD_RELOC_MIPS_INSERT_B: | |
10942 | case BFD_RELOC_MIPS_DELETE: | |
10943 | case BFD_RELOC_MIPS_HIGHEST: | |
10944 | case BFD_RELOC_MIPS_HIGHER: | |
10945 | case BFD_RELOC_MIPS_SCN_DISP: | |
10946 | case BFD_RELOC_MIPS_REL16: | |
10947 | case BFD_RELOC_MIPS_RELGOT: | |
10948 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10949 | case BFD_RELOC_HI16: |
10950 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10951 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10952 | case BFD_RELOC_MIPS_LITERAL: |
10953 | case BFD_RELOC_MIPS_CALL16: | |
10954 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10955 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10956 | case BFD_RELOC_MIPS_GOT_HI16: |
10957 | case BFD_RELOC_MIPS_GOT_LO16: | |
10958 | case BFD_RELOC_MIPS_CALL_HI16: | |
10959 | case BFD_RELOC_MIPS_CALL_LO16: | |
10960 | case BFD_RELOC_MIPS16_GPREL: | |
3e722fb5 | 10961 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10962 | /* Nothing needed to do. The value comes from the reloc entry */ |
10963 | break; | |
10964 | ||
10965 | case BFD_RELOC_MIPS16_JMP: | |
10966 | /* We currently always generate a reloc against a symbol, which | |
10967 | means that we don't want an addend even if the symbol is | |
10968 | defined. */ | |
a7ebbfdf | 10969 | *valP = 0; |
252b5132 RH |
10970 | break; |
10971 | ||
252b5132 RH |
10972 | case BFD_RELOC_64: |
10973 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10974 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10975 | if (fixP->fx_done) |
252b5132 RH |
10976 | { |
10977 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 10978 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
10979 | else |
10980 | { | |
a7ebbfdf | 10981 | valueT hiv; |
252b5132 | 10982 | |
a7ebbfdf | 10983 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
10984 | hiv = 0xffffffff; |
10985 | else | |
10986 | hiv = 0; | |
a7ebbfdf TS |
10987 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
10988 | *valP, 4); | |
10989 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
10990 | hiv, 4); | |
252b5132 RH |
10991 | } |
10992 | } | |
10993 | break; | |
10994 | ||
056350c6 | 10995 | case BFD_RELOC_RVA: |
252b5132 RH |
10996 | case BFD_RELOC_32: |
10997 | /* If we are deleting this reloc entry, we must fill in the | |
10998 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
10999 | resolved when it appears but is later defined. */ |
11000 | if (fixP->fx_done) | |
a7ebbfdf | 11001 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11002 | break; |
11003 | ||
11004 | case BFD_RELOC_16: | |
11005 | /* If we are deleting this reloc entry, we must fill in the | |
11006 | value now. */ | |
11007 | assert (fixP->fx_size == 2); | |
11008 | if (fixP->fx_done) | |
a7ebbfdf | 11009 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11010 | break; |
11011 | ||
11012 | case BFD_RELOC_LO16: | |
3e722fb5 CD |
11013 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11014 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11015 | /* When handling an embedded PIC switch statement, we can wind |
11016 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11017 | if (fixP->fx_done) | |
11018 | { | |
a7ebbfdf | 11019 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11020 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11021 | _("relocation overflow")); | |
252b5132 RH |
11022 | if (target_big_endian) |
11023 | buf += 2; | |
17a2f251 | 11024 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11025 | } |
11026 | break; | |
11027 | ||
11028 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11029 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11030 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11031 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11032 | |
252b5132 RH |
11033 | /* |
11034 | * We need to save the bits in the instruction since fixup_segment() | |
11035 | * might be deleting the relocation entry (i.e., a branch within | |
11036 | * the current segment). | |
11037 | */ | |
a7ebbfdf | 11038 | if (! fixP->fx_done) |
bb2d6cd7 | 11039 | break; |
252b5132 RH |
11040 | |
11041 | /* update old instruction data */ | |
252b5132 RH |
11042 | if (target_big_endian) |
11043 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11044 | else | |
11045 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11046 | ||
a7ebbfdf TS |
11047 | if (*valP + 0x20000 <= 0x3ffff) |
11048 | { | |
11049 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11050 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11051 | } |
11052 | else if (mips_pic == NO_PIC | |
11053 | && fixP->fx_done | |
11054 | && fixP->fx_frag->fr_address >= text_section->vma | |
11055 | && (fixP->fx_frag->fr_address | |
587aac4e | 11056 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11057 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11058 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11059 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11060 | { |
11061 | /* The branch offset is too large. If this is an | |
11062 | unconditional branch, and we are not generating PIC code, | |
11063 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11064 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11065 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11066 | else |
a7ebbfdf TS |
11067 | insn = 0x08000000; /* j */ |
11068 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11069 | fixP->fx_done = 0; | |
11070 | fixP->fx_addsy = section_symbol (text_section); | |
11071 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11072 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11073 | } |
11074 | else | |
11075 | { | |
11076 | /* If we got here, we have branch-relaxation disabled, | |
11077 | and there's nothing we can do to fix this instruction | |
11078 | without turning it into a longer sequence. */ | |
11079 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11080 | _("Branch out of range")); | |
252b5132 | 11081 | } |
252b5132 RH |
11082 | break; |
11083 | ||
11084 | case BFD_RELOC_VTABLE_INHERIT: | |
11085 | fixP->fx_done = 0; | |
11086 | if (fixP->fx_addsy | |
11087 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11088 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11089 | S_SET_WEAK (fixP->fx_addsy); | |
11090 | break; | |
11091 | ||
11092 | case BFD_RELOC_VTABLE_ENTRY: | |
11093 | fixP->fx_done = 0; | |
11094 | break; | |
11095 | ||
11096 | default: | |
11097 | internalError (); | |
11098 | } | |
a7ebbfdf TS |
11099 | |
11100 | /* Remember value for tc_gen_reloc. */ | |
11101 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11102 | } |
11103 | ||
11104 | #if 0 | |
11105 | void | |
17a2f251 | 11106 | printInsn (unsigned long oc) |
252b5132 RH |
11107 | { |
11108 | const struct mips_opcode *p; | |
11109 | int treg, sreg, dreg, shamt; | |
11110 | short imm; | |
11111 | const char *args; | |
11112 | int i; | |
11113 | ||
11114 | for (i = 0; i < NUMOPCODES; ++i) | |
11115 | { | |
11116 | p = &mips_opcodes[i]; | |
11117 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11118 | { | |
11119 | printf ("%08lx %s\t", oc, p->name); | |
11120 | treg = (oc >> 16) & 0x1f; | |
11121 | sreg = (oc >> 21) & 0x1f; | |
11122 | dreg = (oc >> 11) & 0x1f; | |
11123 | shamt = (oc >> 6) & 0x1f; | |
11124 | imm = oc; | |
11125 | for (args = p->args;; ++args) | |
11126 | { | |
11127 | switch (*args) | |
11128 | { | |
11129 | case '\0': | |
11130 | printf ("\n"); | |
11131 | break; | |
11132 | ||
11133 | case ',': | |
11134 | case '(': | |
11135 | case ')': | |
11136 | printf ("%c", *args); | |
11137 | continue; | |
11138 | ||
11139 | case 'r': | |
11140 | assert (treg == sreg); | |
11141 | printf ("$%d,$%d", treg, sreg); | |
11142 | continue; | |
11143 | ||
11144 | case 'd': | |
11145 | case 'G': | |
11146 | printf ("$%d", dreg); | |
11147 | continue; | |
11148 | ||
11149 | case 't': | |
11150 | case 'E': | |
11151 | printf ("$%d", treg); | |
11152 | continue; | |
11153 | ||
11154 | case 'k': | |
11155 | printf ("0x%x", treg); | |
11156 | continue; | |
11157 | ||
11158 | case 'b': | |
11159 | case 's': | |
11160 | printf ("$%d", sreg); | |
11161 | continue; | |
11162 | ||
11163 | case 'a': | |
11164 | printf ("0x%08lx", oc & 0x1ffffff); | |
11165 | continue; | |
11166 | ||
11167 | case 'i': | |
11168 | case 'j': | |
11169 | case 'o': | |
11170 | case 'u': | |
11171 | printf ("%d", imm); | |
11172 | continue; | |
11173 | ||
11174 | case '<': | |
11175 | case '>': | |
11176 | printf ("$%d", shamt); | |
11177 | continue; | |
11178 | ||
11179 | default: | |
11180 | internalError (); | |
11181 | } | |
11182 | break; | |
11183 | } | |
11184 | return; | |
11185 | } | |
11186 | } | |
11187 | printf (_("%08lx UNDEFINED\n"), oc); | |
11188 | } | |
11189 | #endif | |
11190 | ||
11191 | static symbolS * | |
17a2f251 | 11192 | get_symbol (void) |
252b5132 RH |
11193 | { |
11194 | int c; | |
11195 | char *name; | |
11196 | symbolS *p; | |
11197 | ||
11198 | name = input_line_pointer; | |
11199 | c = get_symbol_end (); | |
11200 | p = (symbolS *) symbol_find_or_make (name); | |
11201 | *input_line_pointer = c; | |
11202 | return p; | |
11203 | } | |
11204 | ||
11205 | /* Align the current frag to a given power of two. The MIPS assembler | |
11206 | also automatically adjusts any preceding label. */ | |
11207 | ||
11208 | static void | |
17a2f251 | 11209 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11210 | { |
b34976b6 | 11211 | mips_emit_delays (FALSE); |
252b5132 RH |
11212 | frag_align (to, fill, 0); |
11213 | record_alignment (now_seg, to); | |
11214 | if (label != NULL) | |
11215 | { | |
11216 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11217 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11218 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11219 | } | |
11220 | } | |
11221 | ||
11222 | /* Align to a given power of two. .align 0 turns off the automatic | |
11223 | alignment used by the data creating pseudo-ops. */ | |
11224 | ||
11225 | static void | |
17a2f251 | 11226 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11227 | { |
11228 | register int temp; | |
11229 | register long temp_fill; | |
11230 | long max_alignment = 15; | |
11231 | ||
11232 | /* | |
11233 | ||
67c1ffbe | 11234 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11235 | to the aligned address. |
11236 | o It's not documented but auto alignment is reinstated by | |
11237 | a .align pseudo instruction. | |
11238 | o Note also that after auto alignment is turned off the mips assembler | |
11239 | issues an error on attempt to assemble an improperly aligned data item. | |
11240 | We don't. | |
11241 | ||
11242 | */ | |
11243 | ||
11244 | temp = get_absolute_expression (); | |
11245 | if (temp > max_alignment) | |
11246 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11247 | else if (temp < 0) | |
11248 | { | |
11249 | as_warn (_("Alignment negative: 0 assumed.")); | |
11250 | temp = 0; | |
11251 | } | |
11252 | if (*input_line_pointer == ',') | |
11253 | { | |
f9419b05 | 11254 | ++input_line_pointer; |
252b5132 RH |
11255 | temp_fill = get_absolute_expression (); |
11256 | } | |
11257 | else | |
11258 | temp_fill = 0; | |
11259 | if (temp) | |
11260 | { | |
11261 | auto_align = 1; | |
11262 | mips_align (temp, (int) temp_fill, | |
11263 | insn_labels != NULL ? insn_labels->label : NULL); | |
11264 | } | |
11265 | else | |
11266 | { | |
11267 | auto_align = 0; | |
11268 | } | |
11269 | ||
11270 | demand_empty_rest_of_line (); | |
11271 | } | |
11272 | ||
11273 | void | |
17a2f251 | 11274 | mips_flush_pending_output (void) |
252b5132 | 11275 | { |
b34976b6 | 11276 | mips_emit_delays (FALSE); |
252b5132 RH |
11277 | mips_clear_insn_labels (); |
11278 | } | |
11279 | ||
11280 | static void | |
17a2f251 | 11281 | s_change_sec (int sec) |
252b5132 RH |
11282 | { |
11283 | segT seg; | |
11284 | ||
252b5132 RH |
11285 | #ifdef OBJ_ELF |
11286 | /* The ELF backend needs to know that we are changing sections, so | |
11287 | that .previous works correctly. We could do something like check | |
b6ff326e | 11288 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11289 | as it would not be appropriate to use it in the section changing |
11290 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11291 | This should be cleaner, somehow. */ | |
11292 | obj_elf_section_change_hook (); | |
11293 | #endif | |
11294 | ||
b34976b6 | 11295 | mips_emit_delays (FALSE); |
252b5132 RH |
11296 | switch (sec) |
11297 | { | |
11298 | case 't': | |
11299 | s_text (0); | |
11300 | break; | |
11301 | case 'd': | |
11302 | s_data (0); | |
11303 | break; | |
11304 | case 'b': | |
11305 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11306 | demand_empty_rest_of_line (); | |
11307 | break; | |
11308 | ||
11309 | case 'r': | |
4d0d148d TS |
11310 | seg = subseg_new (RDATA_SECTION_NAME, |
11311 | (subsegT) get_absolute_expression ()); | |
11312 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11313 | { |
4d0d148d TS |
11314 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11315 | | SEC_READONLY | SEC_RELOC | |
11316 | | SEC_DATA)); | |
11317 | if (strcmp (TARGET_OS, "elf") != 0) | |
11318 | record_alignment (seg, 4); | |
252b5132 | 11319 | } |
4d0d148d | 11320 | demand_empty_rest_of_line (); |
252b5132 RH |
11321 | break; |
11322 | ||
11323 | case 's': | |
4d0d148d TS |
11324 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11325 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11326 | { |
4d0d148d TS |
11327 | bfd_set_section_flags (stdoutput, seg, |
11328 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11329 | if (strcmp (TARGET_OS, "elf") != 0) | |
11330 | record_alignment (seg, 4); | |
252b5132 | 11331 | } |
4d0d148d TS |
11332 | demand_empty_rest_of_line (); |
11333 | break; | |
252b5132 RH |
11334 | } |
11335 | ||
11336 | auto_align = 1; | |
11337 | } | |
b34976b6 | 11338 | |
cca86cc8 | 11339 | void |
17a2f251 | 11340 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11341 | { |
7ed4a06a | 11342 | #ifdef OBJ_ELF |
cca86cc8 SC |
11343 | char *section_name; |
11344 | char c; | |
684022ea | 11345 | char next_c = 0; |
cca86cc8 SC |
11346 | int section_type; |
11347 | int section_flag; | |
11348 | int section_entry_size; | |
11349 | int section_alignment; | |
b34976b6 | 11350 | |
7ed4a06a TS |
11351 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11352 | return; | |
11353 | ||
cca86cc8 SC |
11354 | section_name = input_line_pointer; |
11355 | c = get_symbol_end (); | |
a816d1ed AO |
11356 | if (c) |
11357 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11358 | |
4cf0dd0d TS |
11359 | /* Do we have .section Name<,"flags">? */ |
11360 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11361 | { |
4cf0dd0d TS |
11362 | /* just after name is now '\0'. */ |
11363 | *input_line_pointer = c; | |
cca86cc8 SC |
11364 | input_line_pointer = section_name; |
11365 | obj_elf_section (ignore); | |
11366 | return; | |
11367 | } | |
11368 | input_line_pointer++; | |
11369 | ||
11370 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11371 | if (c == ',') | |
11372 | section_type = get_absolute_expression (); | |
11373 | else | |
11374 | section_type = 0; | |
11375 | if (*input_line_pointer++ == ',') | |
11376 | section_flag = get_absolute_expression (); | |
11377 | else | |
11378 | section_flag = 0; | |
11379 | if (*input_line_pointer++ == ',') | |
11380 | section_entry_size = get_absolute_expression (); | |
11381 | else | |
11382 | section_entry_size = 0; | |
11383 | if (*input_line_pointer++ == ',') | |
11384 | section_alignment = get_absolute_expression (); | |
11385 | else | |
11386 | section_alignment = 0; | |
11387 | ||
a816d1ed AO |
11388 | section_name = xstrdup (section_name); |
11389 | ||
8ab8a5c8 RS |
11390 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11391 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11392 | traditionally had to fall back on the more common @progbits instead. | |
11393 | ||
11394 | There's nothing really harmful in this, since bfd will correct | |
11395 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11396 | means that, for backwards compatibiltiy, the special_section entries | |
11397 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11398 | ||
11399 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11400 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11401 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11402 | generic type-checking code. */ | |
11403 | if (section_type == SHT_MIPS_DWARF) | |
11404 | section_type = SHT_PROGBITS; | |
11405 | ||
cca86cc8 SC |
11406 | obj_elf_change_section (section_name, section_type, section_flag, |
11407 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11408 | |
11409 | if (now_seg->name != section_name) | |
11410 | free (section_name); | |
7ed4a06a | 11411 | #endif /* OBJ_ELF */ |
cca86cc8 | 11412 | } |
252b5132 RH |
11413 | |
11414 | void | |
17a2f251 | 11415 | mips_enable_auto_align (void) |
252b5132 RH |
11416 | { |
11417 | auto_align = 1; | |
11418 | } | |
11419 | ||
11420 | static void | |
17a2f251 | 11421 | s_cons (int log_size) |
252b5132 RH |
11422 | { |
11423 | symbolS *label; | |
11424 | ||
11425 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11426 | mips_emit_delays (FALSE); |
252b5132 RH |
11427 | if (log_size > 0 && auto_align) |
11428 | mips_align (log_size, 0, label); | |
11429 | mips_clear_insn_labels (); | |
11430 | cons (1 << log_size); | |
11431 | } | |
11432 | ||
11433 | static void | |
17a2f251 | 11434 | s_float_cons (int type) |
252b5132 RH |
11435 | { |
11436 | symbolS *label; | |
11437 | ||
11438 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11439 | ||
b34976b6 | 11440 | mips_emit_delays (FALSE); |
252b5132 RH |
11441 | |
11442 | if (auto_align) | |
49309057 ILT |
11443 | { |
11444 | if (type == 'd') | |
11445 | mips_align (3, 0, label); | |
11446 | else | |
11447 | mips_align (2, 0, label); | |
11448 | } | |
252b5132 RH |
11449 | |
11450 | mips_clear_insn_labels (); | |
11451 | ||
11452 | float_cons (type); | |
11453 | } | |
11454 | ||
11455 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11456 | permitted to say | |
11457 | .globl foo .text | |
11458 | where foo is an undefined symbol, to mean that foo should be | |
11459 | considered to be the address of a function. */ | |
11460 | ||
11461 | static void | |
17a2f251 | 11462 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11463 | { |
11464 | char *name; | |
11465 | int c; | |
11466 | symbolS *symbolP; | |
11467 | flagword flag; | |
11468 | ||
11469 | name = input_line_pointer; | |
11470 | c = get_symbol_end (); | |
11471 | symbolP = symbol_find_or_make (name); | |
11472 | *input_line_pointer = c; | |
11473 | SKIP_WHITESPACE (); | |
11474 | ||
11475 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11476 | being a function is apparently labelled as being an object. */ | |
11477 | flag = BSF_OBJECT; | |
11478 | ||
11479 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11480 | { | |
11481 | char *secname; | |
11482 | asection *sec; | |
11483 | ||
11484 | secname = input_line_pointer; | |
11485 | c = get_symbol_end (); | |
11486 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11487 | if (sec == NULL) | |
11488 | as_bad (_("%s: no such section"), secname); | |
11489 | *input_line_pointer = c; | |
11490 | ||
11491 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11492 | flag = BSF_FUNCTION; | |
11493 | } | |
11494 | ||
49309057 | 11495 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11496 | |
11497 | S_SET_EXTERNAL (symbolP); | |
11498 | demand_empty_rest_of_line (); | |
11499 | } | |
11500 | ||
11501 | static void | |
17a2f251 | 11502 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11503 | { |
11504 | char *opt; | |
11505 | char c; | |
11506 | ||
11507 | opt = input_line_pointer; | |
11508 | c = get_symbol_end (); | |
11509 | ||
11510 | if (*opt == 'O') | |
11511 | { | |
11512 | /* FIXME: What does this mean? */ | |
11513 | } | |
11514 | else if (strncmp (opt, "pic", 3) == 0) | |
11515 | { | |
11516 | int i; | |
11517 | ||
11518 | i = atoi (opt + 3); | |
11519 | if (i == 0) | |
11520 | mips_pic = NO_PIC; | |
11521 | else if (i == 2) | |
143d77c5 | 11522 | { |
252b5132 | 11523 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11524 | mips_abicalls = TRUE; |
11525 | } | |
252b5132 RH |
11526 | else |
11527 | as_bad (_(".option pic%d not supported"), i); | |
11528 | ||
4d0d148d | 11529 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11530 | { |
11531 | if (g_switch_seen && g_switch_value != 0) | |
11532 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11533 | g_switch_value = 0; | |
11534 | bfd_set_gp_size (stdoutput, 0); | |
11535 | } | |
11536 | } | |
11537 | else | |
11538 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11539 | ||
11540 | *input_line_pointer = c; | |
11541 | demand_empty_rest_of_line (); | |
11542 | } | |
11543 | ||
11544 | /* This structure is used to hold a stack of .set values. */ | |
11545 | ||
e972090a NC |
11546 | struct mips_option_stack |
11547 | { | |
252b5132 RH |
11548 | struct mips_option_stack *next; |
11549 | struct mips_set_options options; | |
11550 | }; | |
11551 | ||
11552 | static struct mips_option_stack *mips_opts_stack; | |
11553 | ||
11554 | /* Handle the .set pseudo-op. */ | |
11555 | ||
11556 | static void | |
17a2f251 | 11557 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11558 | { |
11559 | char *name = input_line_pointer, ch; | |
11560 | ||
11561 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11562 | ++input_line_pointer; |
252b5132 RH |
11563 | ch = *input_line_pointer; |
11564 | *input_line_pointer = '\0'; | |
11565 | ||
11566 | if (strcmp (name, "reorder") == 0) | |
11567 | { | |
11568 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11569 | { | |
11570 | /* If we still have pending nops, we can discard them. The | |
11571 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11572 | needed. */ |
252b5132 RH |
11573 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11574 | * (mips_opts.mips16 ? 2 : 4)); | |
11575 | prev_nop_frag = NULL; | |
11576 | } | |
11577 | mips_opts.noreorder = 0; | |
11578 | } | |
11579 | else if (strcmp (name, "noreorder") == 0) | |
11580 | { | |
b34976b6 | 11581 | mips_emit_delays (TRUE); |
252b5132 RH |
11582 | mips_opts.noreorder = 1; |
11583 | mips_any_noreorder = 1; | |
11584 | } | |
11585 | else if (strcmp (name, "at") == 0) | |
11586 | { | |
11587 | mips_opts.noat = 0; | |
11588 | } | |
11589 | else if (strcmp (name, "noat") == 0) | |
11590 | { | |
11591 | mips_opts.noat = 1; | |
11592 | } | |
11593 | else if (strcmp (name, "macro") == 0) | |
11594 | { | |
11595 | mips_opts.warn_about_macros = 0; | |
11596 | } | |
11597 | else if (strcmp (name, "nomacro") == 0) | |
11598 | { | |
11599 | if (mips_opts.noreorder == 0) | |
11600 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11601 | mips_opts.warn_about_macros = 1; | |
11602 | } | |
11603 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11604 | { | |
11605 | mips_opts.nomove = 0; | |
11606 | } | |
11607 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11608 | { | |
11609 | mips_opts.nomove = 1; | |
11610 | } | |
11611 | else if (strcmp (name, "bopt") == 0) | |
11612 | { | |
11613 | mips_opts.nobopt = 0; | |
11614 | } | |
11615 | else if (strcmp (name, "nobopt") == 0) | |
11616 | { | |
11617 | mips_opts.nobopt = 1; | |
11618 | } | |
11619 | else if (strcmp (name, "mips16") == 0 | |
11620 | || strcmp (name, "MIPS-16") == 0) | |
11621 | mips_opts.mips16 = 1; | |
11622 | else if (strcmp (name, "nomips16") == 0 | |
11623 | || strcmp (name, "noMIPS-16") == 0) | |
11624 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11625 | else if (strcmp (name, "mips3d") == 0) |
11626 | mips_opts.ase_mips3d = 1; | |
11627 | else if (strcmp (name, "nomips3d") == 0) | |
11628 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11629 | else if (strcmp (name, "mdmx") == 0) |
11630 | mips_opts.ase_mdmx = 1; | |
11631 | else if (strcmp (name, "nomdmx") == 0) | |
11632 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11633 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11634 | { |
af7ee8bf | 11635 | int reset = 0; |
252b5132 | 11636 | |
1a2c1fad CD |
11637 | /* Permit the user to change the ISA and architecture on the fly. |
11638 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11639 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11640 | { |
11641 | reset = 1; | |
11642 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11643 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11644 | } |
11645 | else if (strncmp (name, "arch=", 5) == 0) | |
11646 | { | |
11647 | const struct mips_cpu_info *p; | |
11648 | ||
11649 | p = mips_parse_cpu("internal use", name + 5); | |
11650 | if (!p) | |
11651 | as_bad (_("unknown architecture %s"), name + 5); | |
11652 | else | |
11653 | { | |
11654 | mips_opts.arch = p->cpu; | |
11655 | mips_opts.isa = p->isa; | |
11656 | } | |
11657 | } | |
81a21e38 TS |
11658 | else if (strncmp (name, "mips", 4) == 0) |
11659 | { | |
11660 | const struct mips_cpu_info *p; | |
11661 | ||
11662 | p = mips_parse_cpu("internal use", name); | |
11663 | if (!p) | |
11664 | as_bad (_("unknown ISA level %s"), name + 4); | |
11665 | else | |
11666 | { | |
11667 | mips_opts.arch = p->cpu; | |
11668 | mips_opts.isa = p->isa; | |
11669 | } | |
11670 | } | |
af7ee8bf | 11671 | else |
81a21e38 | 11672 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11673 | |
11674 | switch (mips_opts.isa) | |
98d3f06f KH |
11675 | { |
11676 | case 0: | |
98d3f06f | 11677 | break; |
af7ee8bf CD |
11678 | case ISA_MIPS1: |
11679 | case ISA_MIPS2: | |
11680 | case ISA_MIPS32: | |
11681 | case ISA_MIPS32R2: | |
98d3f06f KH |
11682 | mips_opts.gp32 = 1; |
11683 | mips_opts.fp32 = 1; | |
11684 | break; | |
af7ee8bf CD |
11685 | case ISA_MIPS3: |
11686 | case ISA_MIPS4: | |
11687 | case ISA_MIPS5: | |
11688 | case ISA_MIPS64: | |
5f74bc13 | 11689 | case ISA_MIPS64R2: |
98d3f06f KH |
11690 | mips_opts.gp32 = 0; |
11691 | mips_opts.fp32 = 0; | |
11692 | break; | |
11693 | default: | |
11694 | as_bad (_("unknown ISA level %s"), name + 4); | |
11695 | break; | |
11696 | } | |
af7ee8bf | 11697 | if (reset) |
98d3f06f | 11698 | { |
af7ee8bf CD |
11699 | mips_opts.gp32 = file_mips_gp32; |
11700 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11701 | } |
252b5132 RH |
11702 | } |
11703 | else if (strcmp (name, "autoextend") == 0) | |
11704 | mips_opts.noautoextend = 0; | |
11705 | else if (strcmp (name, "noautoextend") == 0) | |
11706 | mips_opts.noautoextend = 1; | |
11707 | else if (strcmp (name, "push") == 0) | |
11708 | { | |
11709 | struct mips_option_stack *s; | |
11710 | ||
11711 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11712 | s->next = mips_opts_stack; | |
11713 | s->options = mips_opts; | |
11714 | mips_opts_stack = s; | |
11715 | } | |
11716 | else if (strcmp (name, "pop") == 0) | |
11717 | { | |
11718 | struct mips_option_stack *s; | |
11719 | ||
11720 | s = mips_opts_stack; | |
11721 | if (s == NULL) | |
11722 | as_bad (_(".set pop with no .set push")); | |
11723 | else | |
11724 | { | |
11725 | /* If we're changing the reorder mode we need to handle | |
11726 | delay slots correctly. */ | |
11727 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11728 | mips_emit_delays (TRUE); |
252b5132 RH |
11729 | else if (! s->options.noreorder && mips_opts.noreorder) |
11730 | { | |
11731 | if (prev_nop_frag != NULL) | |
11732 | { | |
11733 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11734 | * (mips_opts.mips16 ? 2 : 4)); | |
11735 | prev_nop_frag = NULL; | |
11736 | } | |
11737 | } | |
11738 | ||
11739 | mips_opts = s->options; | |
11740 | mips_opts_stack = s->next; | |
11741 | free (s); | |
11742 | } | |
11743 | } | |
11744 | else | |
11745 | { | |
11746 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11747 | } | |
11748 | *input_line_pointer = ch; | |
11749 | demand_empty_rest_of_line (); | |
11750 | } | |
11751 | ||
11752 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11753 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11754 | ||
11755 | static void | |
17a2f251 | 11756 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11757 | { |
11758 | mips_pic = SVR4_PIC; | |
143d77c5 | 11759 | mips_abicalls = TRUE; |
4d0d148d TS |
11760 | |
11761 | if (g_switch_seen && g_switch_value != 0) | |
11762 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11763 | g_switch_value = 0; | |
11764 | ||
252b5132 RH |
11765 | bfd_set_gp_size (stdoutput, 0); |
11766 | demand_empty_rest_of_line (); | |
11767 | } | |
11768 | ||
11769 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11770 | PIC code. It sets the $gp register for the function based on the | |
11771 | function address, which is in the register named in the argument. | |
11772 | This uses a relocation against _gp_disp, which is handled specially | |
11773 | by the linker. The result is: | |
11774 | lui $gp,%hi(_gp_disp) | |
11775 | addiu $gp,$gp,%lo(_gp_disp) | |
11776 | addu $gp,$gp,.cpload argument | |
11777 | The .cpload argument is normally $25 == $t9. */ | |
11778 | ||
11779 | static void | |
17a2f251 | 11780 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11781 | { |
11782 | expressionS ex; | |
252b5132 | 11783 | |
6478892d TS |
11784 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11785 | .cpload is ignored. */ | |
11786 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11787 | { |
11788 | s_ignore (0); | |
11789 | return; | |
11790 | } | |
11791 | ||
d3ecfc59 | 11792 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11793 | if (mips_opts.noreorder == 0) |
11794 | as_warn (_(".cpload not in noreorder section")); | |
11795 | ||
11796 | ex.X_op = O_symbol; | |
11797 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11798 | ex.X_op_symbol = NULL; | |
11799 | ex.X_add_number = 0; | |
11800 | ||
11801 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11802 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11803 | |
584892a6 | 11804 | macro_start (); |
67c0d1eb RS |
11805 | macro_build_lui (&ex, mips_gp_register); |
11806 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11807 | mips_gp_register, BFD_RELOC_LO16); |
67c0d1eb | 11808 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
17a2f251 | 11809 | mips_gp_register, tc_get_register (0)); |
584892a6 | 11810 | macro_end (); |
252b5132 RH |
11811 | |
11812 | demand_empty_rest_of_line (); | |
11813 | } | |
11814 | ||
6478892d TS |
11815 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11816 | .cpsetup $reg1, offset|$reg2, label | |
11817 | ||
11818 | If offset is given, this results in: | |
11819 | sd $gp, offset($sp) | |
956cd1d6 | 11820 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11821 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11822 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11823 | |
11824 | If $reg2 is given, this results in: | |
11825 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11826 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11827 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11828 | daddu $gp, $gp, $reg1 | |
11829 | $reg1 is normally $25 == $t9. */ | |
6478892d | 11830 | static void |
17a2f251 | 11831 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11832 | { |
11833 | expressionS ex_off; | |
11834 | expressionS ex_sym; | |
11835 | int reg1; | |
f21f8242 | 11836 | char *f; |
6478892d | 11837 | |
8586fc66 | 11838 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11839 | We also need NewABI support. */ |
11840 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11841 | { | |
11842 | s_ignore (0); | |
11843 | return; | |
11844 | } | |
11845 | ||
11846 | reg1 = tc_get_register (0); | |
11847 | SKIP_WHITESPACE (); | |
11848 | if (*input_line_pointer != ',') | |
11849 | { | |
11850 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11851 | return; | |
11852 | } | |
11853 | else | |
80245285 | 11854 | ++input_line_pointer; |
6478892d TS |
11855 | SKIP_WHITESPACE (); |
11856 | if (*input_line_pointer == '$') | |
80245285 TS |
11857 | { |
11858 | mips_cpreturn_register = tc_get_register (0); | |
11859 | mips_cpreturn_offset = -1; | |
11860 | } | |
6478892d | 11861 | else |
80245285 TS |
11862 | { |
11863 | mips_cpreturn_offset = get_absolute_expression (); | |
11864 | mips_cpreturn_register = -1; | |
11865 | } | |
6478892d TS |
11866 | SKIP_WHITESPACE (); |
11867 | if (*input_line_pointer != ',') | |
11868 | { | |
11869 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11870 | return; | |
11871 | } | |
11872 | else | |
f9419b05 | 11873 | ++input_line_pointer; |
6478892d | 11874 | SKIP_WHITESPACE (); |
f21f8242 | 11875 | expression (&ex_sym); |
6478892d | 11876 | |
584892a6 | 11877 | macro_start (); |
6478892d TS |
11878 | if (mips_cpreturn_register == -1) |
11879 | { | |
11880 | ex_off.X_op = O_constant; | |
11881 | ex_off.X_add_symbol = NULL; | |
11882 | ex_off.X_op_symbol = NULL; | |
11883 | ex_off.X_add_number = mips_cpreturn_offset; | |
11884 | ||
67c0d1eb | 11885 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11886 | BFD_RELOC_LO16, SP); |
6478892d TS |
11887 | } |
11888 | else | |
67c0d1eb | 11889 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11890 | mips_gp_register, 0); |
6478892d | 11891 | |
f21f8242 AO |
11892 | /* Ensure there's room for the next two instructions, so that `f' |
11893 | doesn't end up with an address in the wrong frag. */ | |
11894 | frag_grow (8); | |
11895 | f = frag_more (0); | |
67c0d1eb | 11896 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 11897 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11898 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 11899 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11900 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
11901 | |
11902 | f = frag_more (0); | |
67c0d1eb | 11903 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
17a2f251 | 11904 | mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 11905 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11906 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 11907 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 11908 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 11909 | |
67c0d1eb | 11910 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
17a2f251 | 11911 | mips_gp_register, reg1); |
584892a6 | 11912 | macro_end (); |
6478892d TS |
11913 | |
11914 | demand_empty_rest_of_line (); | |
11915 | } | |
11916 | ||
11917 | static void | |
17a2f251 | 11918 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11919 | { |
11920 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11921 | .cplocal is ignored. */ | |
11922 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11923 | { | |
11924 | s_ignore (0); | |
11925 | return; | |
11926 | } | |
11927 | ||
11928 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11929 | demand_empty_rest_of_line (); |
6478892d TS |
11930 | } |
11931 | ||
252b5132 RH |
11932 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11933 | offset from $sp. The offset is remembered, and after making a PIC | |
11934 | call $gp is restored from that location. */ | |
11935 | ||
11936 | static void | |
17a2f251 | 11937 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11938 | { |
11939 | expressionS ex; | |
252b5132 | 11940 | |
6478892d | 11941 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11942 | .cprestore is ignored. */ |
6478892d | 11943 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11944 | { |
11945 | s_ignore (0); | |
11946 | return; | |
11947 | } | |
11948 | ||
11949 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11950 | mips_cprestore_valid = 1; |
252b5132 RH |
11951 | |
11952 | ex.X_op = O_constant; | |
11953 | ex.X_add_symbol = NULL; | |
11954 | ex.X_op_symbol = NULL; | |
11955 | ex.X_add_number = mips_cprestore_offset; | |
11956 | ||
584892a6 | 11957 | macro_start (); |
67c0d1eb RS |
11958 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11959 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11960 | macro_end (); |
252b5132 RH |
11961 | |
11962 | demand_empty_rest_of_line (); | |
11963 | } | |
11964 | ||
6478892d | 11965 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11966 | was given in the preceding .cpsetup, it results in: |
6478892d | 11967 | ld $gp, offset($sp) |
76b3015f | 11968 | |
6478892d | 11969 | If a register $reg2 was given there, it results in: |
609f23f4 | 11970 | daddu $gp, $reg2, $0 |
6478892d TS |
11971 | */ |
11972 | static void | |
17a2f251 | 11973 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11974 | { |
11975 | expressionS ex; | |
6478892d TS |
11976 | |
11977 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11978 | We also need NewABI support. */ | |
11979 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11980 | { | |
11981 | s_ignore (0); | |
11982 | return; | |
11983 | } | |
11984 | ||
584892a6 | 11985 | macro_start (); |
6478892d TS |
11986 | if (mips_cpreturn_register == -1) |
11987 | { | |
11988 | ex.X_op = O_constant; | |
11989 | ex.X_add_symbol = NULL; | |
11990 | ex.X_op_symbol = NULL; | |
11991 | ex.X_add_number = mips_cpreturn_offset; | |
11992 | ||
67c0d1eb | 11993 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11994 | } |
11995 | else | |
67c0d1eb | 11996 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11997 | mips_cpreturn_register, 0); |
584892a6 | 11998 | macro_end (); |
6478892d TS |
11999 | |
12000 | demand_empty_rest_of_line (); | |
12001 | } | |
12002 | ||
12003 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12004 | code. It sets the offset to use in gp_rel relocations. */ | |
12005 | ||
12006 | static void | |
17a2f251 | 12007 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12008 | { |
12009 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12010 | We also need NewABI support. */ | |
12011 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12012 | { | |
12013 | s_ignore (0); | |
12014 | return; | |
12015 | } | |
12016 | ||
def2e0dd | 12017 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12018 | |
12019 | demand_empty_rest_of_line (); | |
12020 | } | |
12021 | ||
252b5132 RH |
12022 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12023 | code. It generates a 32 bit GP relative reloc. */ | |
12024 | ||
12025 | static void | |
17a2f251 | 12026 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12027 | { |
12028 | symbolS *label; | |
12029 | expressionS ex; | |
12030 | char *p; | |
12031 | ||
12032 | /* When not generating PIC code, this is treated as .word. */ | |
12033 | if (mips_pic != SVR4_PIC) | |
12034 | { | |
12035 | s_cons (2); | |
12036 | return; | |
12037 | } | |
12038 | ||
12039 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12040 | mips_emit_delays (TRUE); |
252b5132 RH |
12041 | if (auto_align) |
12042 | mips_align (2, 0, label); | |
12043 | mips_clear_insn_labels (); | |
12044 | ||
12045 | expression (&ex); | |
12046 | ||
12047 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12048 | { | |
12049 | as_bad (_("Unsupported use of .gpword")); | |
12050 | ignore_rest_of_line (); | |
12051 | } | |
12052 | ||
12053 | p = frag_more (4); | |
17a2f251 | 12054 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12055 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12056 | BFD_RELOC_GPREL32); |
252b5132 RH |
12057 | |
12058 | demand_empty_rest_of_line (); | |
12059 | } | |
12060 | ||
10181a0d | 12061 | static void |
17a2f251 | 12062 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12063 | { |
12064 | symbolS *label; | |
12065 | expressionS ex; | |
12066 | char *p; | |
12067 | ||
12068 | /* When not generating PIC code, this is treated as .dword. */ | |
12069 | if (mips_pic != SVR4_PIC) | |
12070 | { | |
12071 | s_cons (3); | |
12072 | return; | |
12073 | } | |
12074 | ||
12075 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12076 | mips_emit_delays (TRUE); |
10181a0d AO |
12077 | if (auto_align) |
12078 | mips_align (3, 0, label); | |
12079 | mips_clear_insn_labels (); | |
12080 | ||
12081 | expression (&ex); | |
12082 | ||
12083 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12084 | { | |
12085 | as_bad (_("Unsupported use of .gpdword")); | |
12086 | ignore_rest_of_line (); | |
12087 | } | |
12088 | ||
12089 | p = frag_more (8); | |
17a2f251 | 12090 | md_number_to_chars (p, 0, 8); |
a105a300 | 12091 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12092 | BFD_RELOC_GPREL32); |
12093 | ||
12094 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12095 | ex.X_op = O_absent; | |
12096 | ex.X_add_symbol = 0; | |
12097 | ex.X_add_number = 0; | |
b34976b6 | 12098 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12099 | BFD_RELOC_64); |
12100 | ||
12101 | demand_empty_rest_of_line (); | |
12102 | } | |
12103 | ||
252b5132 RH |
12104 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12105 | tables in SVR4 PIC code. */ | |
12106 | ||
12107 | static void | |
17a2f251 | 12108 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12109 | { |
252b5132 RH |
12110 | int reg; |
12111 | ||
10181a0d AO |
12112 | /* This is ignored when not generating SVR4 PIC code. */ |
12113 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12114 | { |
12115 | s_ignore (0); | |
12116 | return; | |
12117 | } | |
12118 | ||
12119 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12120 | macro_start (); |
252b5132 | 12121 | reg = tc_get_register (0); |
67c0d1eb | 12122 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12123 | macro_end (); |
252b5132 | 12124 | |
bdaaa2e1 | 12125 | demand_empty_rest_of_line (); |
252b5132 RH |
12126 | } |
12127 | ||
12128 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12129 | mips16 mode. This permits the linker to handle them specially, | |
12130 | such as generating jalx instructions when needed. We also make | |
12131 | them odd for the duration of the assembly, in order to generate the | |
12132 | right sort of code. We will make them even in the adjust_symtab | |
12133 | routine, while leaving them marked. This is convenient for the | |
12134 | debugger and the disassembler. The linker knows to make them odd | |
12135 | again. */ | |
12136 | ||
12137 | static void | |
17a2f251 | 12138 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12139 | { |
f9419b05 | 12140 | mips16_mark_labels (); |
252b5132 RH |
12141 | |
12142 | demand_empty_rest_of_line (); | |
12143 | } | |
12144 | ||
12145 | /* Handle a .stabn directive. We need these in order to mark a label | |
12146 | as being a mips16 text label correctly. Sometimes the compiler | |
12147 | will emit a label, followed by a .stabn, and then switch sections. | |
12148 | If the label and .stabn are in mips16 mode, then the label is | |
12149 | really a mips16 text label. */ | |
12150 | ||
12151 | static void | |
17a2f251 | 12152 | s_mips_stab (int type) |
252b5132 | 12153 | { |
f9419b05 | 12154 | if (type == 'n') |
252b5132 RH |
12155 | mips16_mark_labels (); |
12156 | ||
12157 | s_stab (type); | |
12158 | } | |
12159 | ||
12160 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12161 | */ | |
12162 | ||
12163 | static void | |
17a2f251 | 12164 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12165 | { |
12166 | char *name; | |
12167 | int c; | |
12168 | symbolS *symbolP; | |
12169 | expressionS exp; | |
12170 | ||
12171 | name = input_line_pointer; | |
12172 | c = get_symbol_end (); | |
12173 | symbolP = symbol_find_or_make (name); | |
12174 | S_SET_WEAK (symbolP); | |
12175 | *input_line_pointer = c; | |
12176 | ||
12177 | SKIP_WHITESPACE (); | |
12178 | ||
12179 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12180 | { | |
12181 | if (S_IS_DEFINED (symbolP)) | |
12182 | { | |
956cd1d6 | 12183 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12184 | S_GET_NAME (symbolP)); |
12185 | ignore_rest_of_line (); | |
12186 | return; | |
12187 | } | |
bdaaa2e1 | 12188 | |
252b5132 RH |
12189 | if (*input_line_pointer == ',') |
12190 | { | |
12191 | ++input_line_pointer; | |
12192 | SKIP_WHITESPACE (); | |
12193 | } | |
bdaaa2e1 | 12194 | |
252b5132 RH |
12195 | expression (&exp); |
12196 | if (exp.X_op != O_symbol) | |
12197 | { | |
12198 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12199 | ignore_rest_of_line (); |
252b5132 RH |
12200 | return; |
12201 | } | |
49309057 | 12202 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12203 | } |
12204 | ||
12205 | demand_empty_rest_of_line (); | |
12206 | } | |
12207 | ||
12208 | /* Parse a register string into a number. Called from the ECOFF code | |
12209 | to parse .frame. The argument is non-zero if this is the frame | |
12210 | register, so that we can record it in mips_frame_reg. */ | |
12211 | ||
12212 | int | |
17a2f251 | 12213 | tc_get_register (int frame) |
252b5132 RH |
12214 | { |
12215 | int reg; | |
12216 | ||
12217 | SKIP_WHITESPACE (); | |
12218 | if (*input_line_pointer++ != '$') | |
12219 | { | |
12220 | as_warn (_("expected `$'")); | |
85b51719 | 12221 | reg = ZERO; |
252b5132 | 12222 | } |
3882b010 | 12223 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12224 | { |
12225 | reg = get_absolute_expression (); | |
12226 | if (reg < 0 || reg >= 32) | |
12227 | { | |
12228 | as_warn (_("Bad register number")); | |
85b51719 | 12229 | reg = ZERO; |
252b5132 RH |
12230 | } |
12231 | } | |
12232 | else | |
12233 | { | |
76db943d | 12234 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12235 | { |
12236 | reg = RA; | |
12237 | input_line_pointer += 2; | |
12238 | } | |
76db943d | 12239 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12240 | { |
12241 | reg = FP; | |
12242 | input_line_pointer += 2; | |
12243 | } | |
252b5132 | 12244 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12245 | { |
12246 | reg = SP; | |
12247 | input_line_pointer += 2; | |
12248 | } | |
252b5132 | 12249 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12250 | { |
12251 | reg = GP; | |
12252 | input_line_pointer += 2; | |
12253 | } | |
252b5132 | 12254 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12255 | { |
12256 | reg = AT; | |
12257 | input_line_pointer += 2; | |
12258 | } | |
12259 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12260 | { | |
12261 | reg = KT0; | |
12262 | input_line_pointer += 3; | |
12263 | } | |
12264 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12265 | { | |
12266 | reg = KT1; | |
12267 | input_line_pointer += 3; | |
12268 | } | |
12269 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12270 | { | |
12271 | reg = ZERO; | |
12272 | input_line_pointer += 4; | |
12273 | } | |
252b5132 RH |
12274 | else |
12275 | { | |
12276 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12277 | reg = ZERO; |
12278 | while (ISALNUM(*input_line_pointer)) | |
12279 | input_line_pointer++; | |
252b5132 | 12280 | } |
252b5132 RH |
12281 | } |
12282 | if (frame) | |
7a621144 DJ |
12283 | { |
12284 | mips_frame_reg = reg != 0 ? reg : SP; | |
12285 | mips_frame_reg_valid = 1; | |
12286 | mips_cprestore_valid = 0; | |
12287 | } | |
252b5132 RH |
12288 | return reg; |
12289 | } | |
12290 | ||
12291 | valueT | |
17a2f251 | 12292 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12293 | { |
12294 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12295 | ||
12296 | #ifdef OBJ_ELF | |
12297 | /* We don't need to align ELF sections to the full alignment. | |
12298 | However, Irix 5 may prefer that we align them at least to a 16 | |
12299 | byte boundary. We don't bother to align the sections if we are | |
12300 | targeted for an embedded system. */ | |
12301 | if (strcmp (TARGET_OS, "elf") == 0) | |
12302 | return addr; | |
12303 | if (align > 4) | |
12304 | align = 4; | |
12305 | #endif | |
12306 | ||
12307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12308 | } | |
12309 | ||
12310 | /* Utility routine, called from above as well. If called while the | |
12311 | input file is still being read, it's only an approximation. (For | |
12312 | example, a symbol may later become defined which appeared to be | |
12313 | undefined earlier.) */ | |
12314 | ||
12315 | static int | |
17a2f251 | 12316 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12317 | { |
12318 | if (sym == 0) | |
12319 | return 0; | |
12320 | ||
4d0d148d | 12321 | if (g_switch_value > 0) |
252b5132 RH |
12322 | { |
12323 | const char *symname; | |
12324 | int change; | |
12325 | ||
c9914766 | 12326 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12327 | register. It can be if it is smaller than the -G size or if |
12328 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12329 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12330 | they can. */ |
12331 | symname = S_GET_NAME (sym); | |
12332 | if (symname != (const char *) NULL | |
12333 | && (strcmp (symname, "eprol") == 0 | |
12334 | || strcmp (symname, "etext") == 0 | |
12335 | || strcmp (symname, "_gp") == 0 | |
12336 | || strcmp (symname, "edata") == 0 | |
12337 | || strcmp (symname, "_fbss") == 0 | |
12338 | || strcmp (symname, "_fdata") == 0 | |
12339 | || strcmp (symname, "_ftext") == 0 | |
12340 | || strcmp (symname, "end") == 0 | |
12341 | || strcmp (symname, "_gp_disp") == 0)) | |
12342 | change = 1; | |
12343 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12344 | && (0 | |
12345 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12346 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12347 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12348 | <= g_switch_value)) | |
252b5132 RH |
12349 | #endif |
12350 | /* We must defer this decision until after the whole | |
12351 | file has been read, since there might be a .extern | |
12352 | after the first use of this symbol. */ | |
12353 | || (before_relaxing | |
12354 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12355 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12356 | #endif |
12357 | && S_GET_VALUE (sym) == 0) | |
12358 | || (S_GET_VALUE (sym) != 0 | |
12359 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12360 | change = 0; | |
12361 | else | |
12362 | { | |
12363 | const char *segname; | |
12364 | ||
12365 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12366 | assert (strcmp (segname, ".lit8") != 0 | |
12367 | && strcmp (segname, ".lit4") != 0); | |
12368 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12369 | && strcmp (segname, ".sbss") != 0 |
12370 | && strncmp (segname, ".sdata.", 7) != 0 | |
12371 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12372 | } |
12373 | return change; | |
12374 | } | |
12375 | else | |
c9914766 | 12376 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12377 | return 1; |
12378 | } | |
12379 | ||
5919d012 RS |
12380 | |
12381 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12382 | ||
12383 | static bfd_boolean | |
17a2f251 | 12384 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12385 | { |
12386 | asection *symsec; | |
12387 | bfd_boolean linkonce; | |
12388 | ||
12389 | /* Handle the case of a symbol equated to another symbol. */ | |
12390 | while (symbol_equated_reloc_p (sym)) | |
12391 | { | |
12392 | symbolS *n; | |
12393 | ||
12394 | /* It's possible to get a loop here in a badly written | |
12395 | program. */ | |
12396 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12397 | if (n == sym) | |
12398 | break; | |
12399 | sym = n; | |
12400 | } | |
12401 | ||
12402 | symsec = S_GET_SEGMENT (sym); | |
12403 | ||
12404 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12405 | linkonce = FALSE; | |
12406 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12407 | { | |
12408 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12409 | != 0) | |
12410 | linkonce = TRUE; | |
12411 | ||
12412 | /* The GNU toolchain uses an extension for ELF: a section | |
12413 | beginning with the magic string .gnu.linkonce is a linkonce | |
12414 | section. */ | |
12415 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12416 | sizeof ".gnu.linkonce" - 1) == 0) | |
12417 | linkonce = TRUE; | |
12418 | } | |
12419 | ||
12420 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12421 | return (symsec != &bfd_und_section | |
12422 | && symsec != &bfd_abs_section | |
12423 | && ! bfd_is_com_section (symsec) | |
12424 | && !linkonce | |
12425 | #ifdef OBJ_ELF | |
12426 | /* A global or weak symbol is treated as external. */ | |
12427 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12428 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12429 | #endif |
12430 | ); | |
12431 | } | |
12432 | ||
12433 | ||
252b5132 RH |
12434 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12435 | extended opcode. SEC is the section the frag is in. */ | |
12436 | ||
12437 | static int | |
17a2f251 | 12438 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12439 | { |
12440 | int type; | |
12441 | register const struct mips16_immed_operand *op; | |
12442 | offsetT val; | |
12443 | int mintiny, maxtiny; | |
12444 | segT symsec; | |
98aa84af | 12445 | fragS *sym_frag; |
252b5132 RH |
12446 | |
12447 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12448 | return 0; | |
12449 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12450 | return 1; | |
12451 | ||
12452 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12453 | op = mips16_immed_operands; | |
12454 | while (op->type != type) | |
12455 | { | |
12456 | ++op; | |
12457 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12458 | } | |
12459 | ||
12460 | if (op->unsp) | |
12461 | { | |
12462 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12463 | { | |
12464 | mintiny = 1; | |
12465 | maxtiny = 1 << op->nbits; | |
12466 | } | |
12467 | else | |
12468 | { | |
12469 | mintiny = 0; | |
12470 | maxtiny = (1 << op->nbits) - 1; | |
12471 | } | |
12472 | } | |
12473 | else | |
12474 | { | |
12475 | mintiny = - (1 << (op->nbits - 1)); | |
12476 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12477 | } | |
12478 | ||
98aa84af | 12479 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12480 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12481 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12482 | |
12483 | if (op->pcrel) | |
12484 | { | |
12485 | addressT addr; | |
12486 | ||
12487 | /* We won't have the section when we are called from | |
12488 | mips_relax_frag. However, we will always have been called | |
12489 | from md_estimate_size_before_relax first. If this is a | |
12490 | branch to a different section, we mark it as such. If SEC is | |
12491 | NULL, and the frag is not marked, then it must be a branch to | |
12492 | the same section. */ | |
12493 | if (sec == NULL) | |
12494 | { | |
12495 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12496 | return 1; | |
12497 | } | |
12498 | else | |
12499 | { | |
98aa84af | 12500 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12501 | if (symsec != sec) |
12502 | { | |
12503 | fragp->fr_subtype = | |
12504 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12505 | ||
12506 | /* FIXME: We should support this, and let the linker | |
12507 | catch branches and loads that are out of range. */ | |
12508 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12509 | _("unsupported PC relative reference to different section")); | |
12510 | ||
12511 | return 1; | |
12512 | } | |
98aa84af AM |
12513 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12514 | /* Assume non-extended on the first relaxation pass. | |
12515 | The address we have calculated will be bogus if this is | |
12516 | a forward branch to another frag, as the forward frag | |
12517 | will have fr_address == 0. */ | |
12518 | return 0; | |
252b5132 RH |
12519 | } |
12520 | ||
12521 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12522 | the same section. If the relax_marker of the symbol fragment |
12523 | differs from the relax_marker of this fragment, we have not | |
12524 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12525 | in STRETCH in order to get a better estimate of the address. |
12526 | This particularly matters because of the shift bits. */ | |
12527 | if (stretch != 0 | |
98aa84af | 12528 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12529 | { |
12530 | fragS *f; | |
12531 | ||
12532 | /* Adjust stretch for any alignment frag. Note that if have | |
12533 | been expanding the earlier code, the symbol may be | |
12534 | defined in what appears to be an earlier frag. FIXME: | |
12535 | This doesn't handle the fr_subtype field, which specifies | |
12536 | a maximum number of bytes to skip when doing an | |
12537 | alignment. */ | |
98aa84af | 12538 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12539 | { |
12540 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12541 | { | |
12542 | if (stretch < 0) | |
12543 | stretch = - ((- stretch) | |
12544 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12545 | else | |
12546 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12547 | if (stretch == 0) | |
12548 | break; | |
12549 | } | |
12550 | } | |
12551 | if (f != NULL) | |
12552 | val += stretch; | |
12553 | } | |
12554 | ||
12555 | addr = fragp->fr_address + fragp->fr_fix; | |
12556 | ||
12557 | /* The base address rules are complicated. The base address of | |
12558 | a branch is the following instruction. The base address of a | |
12559 | PC relative load or add is the instruction itself, but if it | |
12560 | is in a delay slot (in which case it can not be extended) use | |
12561 | the address of the instruction whose delay slot it is in. */ | |
12562 | if (type == 'p' || type == 'q') | |
12563 | { | |
12564 | addr += 2; | |
12565 | ||
12566 | /* If we are currently assuming that this frag should be | |
12567 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12568 | higher. */ |
252b5132 RH |
12569 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12570 | addr += 2; | |
12571 | ||
12572 | /* Ignore the low bit in the target, since it will be set | |
12573 | for a text label. */ | |
12574 | if ((val & 1) != 0) | |
12575 | --val; | |
12576 | } | |
12577 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12578 | addr -= 4; | |
12579 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12580 | addr -= 2; | |
12581 | ||
12582 | val -= addr & ~ ((1 << op->shift) - 1); | |
12583 | ||
12584 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12585 | if (type == 'p' || type == 'q') | |
12586 | val /= 2; | |
12587 | ||
12588 | /* If any of the shifted bits are set, we must use an extended | |
12589 | opcode. If the address depends on the size of this | |
12590 | instruction, this can lead to a loop, so we arrange to always | |
12591 | use an extended opcode. We only check this when we are in | |
12592 | the main relaxation loop, when SEC is NULL. */ | |
12593 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12594 | { | |
12595 | fragp->fr_subtype = | |
12596 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12597 | return 1; | |
12598 | } | |
12599 | ||
12600 | /* If we are about to mark a frag as extended because the value | |
12601 | is precisely maxtiny + 1, then there is a chance of an | |
12602 | infinite loop as in the following code: | |
12603 | la $4,foo | |
12604 | .skip 1020 | |
12605 | .align 2 | |
12606 | foo: | |
12607 | In this case when the la is extended, foo is 0x3fc bytes | |
12608 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12609 | the la must be extended. To avoid this loop, we mark the | |
12610 | frag as extended if it was small, and is about to become | |
12611 | extended with a value of maxtiny + 1. */ | |
12612 | if (val == ((maxtiny + 1) << op->shift) | |
12613 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12614 | && sec == NULL) | |
12615 | { | |
12616 | fragp->fr_subtype = | |
12617 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12618 | return 1; | |
12619 | } | |
12620 | } | |
12621 | else if (symsec != absolute_section && sec != NULL) | |
12622 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12623 | ||
12624 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12625 | || val < (mintiny << op->shift) | |
12626 | || val > (maxtiny << op->shift)) | |
12627 | return 1; | |
12628 | else | |
12629 | return 0; | |
12630 | } | |
12631 | ||
4a6a3df4 AO |
12632 | /* Compute the length of a branch sequence, and adjust the |
12633 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12634 | worst-case length is computed, with UPDATE being used to indicate | |
12635 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12636 | branch is to be computed. */ | |
12637 | static int | |
17a2f251 | 12638 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12639 | { |
b34976b6 | 12640 | bfd_boolean toofar; |
4a6a3df4 AO |
12641 | int length; |
12642 | ||
12643 | if (fragp | |
12644 | && S_IS_DEFINED (fragp->fr_symbol) | |
12645 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12646 | { | |
12647 | addressT addr; | |
12648 | offsetT val; | |
12649 | ||
12650 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12651 | ||
12652 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12653 | ||
12654 | val -= addr; | |
12655 | ||
12656 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12657 | } | |
12658 | else if (fragp) | |
12659 | /* If the symbol is not defined or it's in a different segment, | |
12660 | assume the user knows what's going on and emit a short | |
12661 | branch. */ | |
b34976b6 | 12662 | toofar = FALSE; |
4a6a3df4 | 12663 | else |
b34976b6 | 12664 | toofar = TRUE; |
4a6a3df4 AO |
12665 | |
12666 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12667 | fragp->fr_subtype | |
af6ae2ad | 12668 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12669 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12670 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12671 | toofar); | |
12672 | ||
12673 | length = 4; | |
12674 | if (toofar) | |
12675 | { | |
12676 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12677 | length += 8; | |
12678 | ||
12679 | if (mips_pic != NO_PIC) | |
12680 | { | |
12681 | /* Additional space for PIC loading of target address. */ | |
12682 | length += 8; | |
12683 | if (mips_opts.isa == ISA_MIPS1) | |
12684 | /* Additional space for $at-stabilizing nop. */ | |
12685 | length += 4; | |
12686 | } | |
12687 | ||
12688 | /* If branch is conditional. */ | |
12689 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12690 | length += 8; | |
12691 | } | |
b34976b6 | 12692 | |
4a6a3df4 AO |
12693 | return length; |
12694 | } | |
12695 | ||
252b5132 RH |
12696 | /* Estimate the size of a frag before relaxing. Unless this is the |
12697 | mips16, we are not really relaxing here, and the final size is | |
12698 | encoded in the subtype information. For the mips16, we have to | |
12699 | decide whether we are using an extended opcode or not. */ | |
12700 | ||
252b5132 | 12701 | int |
17a2f251 | 12702 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12703 | { |
5919d012 | 12704 | int change; |
252b5132 | 12705 | |
4a6a3df4 AO |
12706 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12707 | { | |
12708 | ||
b34976b6 AM |
12709 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12710 | ||
4a6a3df4 AO |
12711 | return fragp->fr_var; |
12712 | } | |
12713 | ||
252b5132 | 12714 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12715 | /* We don't want to modify the EXTENDED bit here; it might get us |
12716 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12717 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12718 | |
12719 | if (mips_pic == NO_PIC) | |
5919d012 | 12720 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12721 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12722 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12723 | else |
12724 | abort (); | |
12725 | ||
12726 | if (change) | |
12727 | { | |
4d7206a2 | 12728 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12729 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12730 | } |
4d7206a2 RS |
12731 | else |
12732 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12733 | } |
12734 | ||
12735 | /* This is called to see whether a reloc against a defined symbol | |
12736 | should be converted into a reloc against a section. Don't adjust | |
12737 | MIPS16 jump relocations, so we don't have to worry about the format | |
12738 | of the offset in the .o file. Don't adjust relocations against | |
12739 | mips16 symbols, so that the linker can find them if it needs to set | |
12740 | up a stub. */ | |
12741 | ||
12742 | int | |
17a2f251 | 12743 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
12744 | { |
12745 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
12746 | return 0; | |
a161fe53 | 12747 | |
252b5132 RH |
12748 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12749 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12750 | return 0; | |
a161fe53 | 12751 | |
252b5132 RH |
12752 | if (fixp->fx_addsy == NULL) |
12753 | return 1; | |
a161fe53 | 12754 | |
252b5132 RH |
12755 | #ifdef OBJ_ELF |
12756 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12757 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12758 | && fixp->fx_subsy == NULL) | |
12759 | return 0; | |
12760 | #endif | |
a161fe53 | 12761 | |
252b5132 RH |
12762 | return 1; |
12763 | } | |
12764 | ||
12765 | /* Translate internal representation of relocation info to BFD target | |
12766 | format. */ | |
12767 | ||
12768 | arelent ** | |
17a2f251 | 12769 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12770 | { |
12771 | static arelent *retval[4]; | |
12772 | arelent *reloc; | |
12773 | bfd_reloc_code_real_type code; | |
12774 | ||
4b0cff4e TS |
12775 | memset (retval, 0, sizeof(retval)); |
12776 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12777 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12778 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12779 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12780 | ||
3e722fb5 CD |
12781 | assert (! fixp->fx_pcrel); |
12782 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12783 | |
438c16b8 TS |
12784 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12785 | entry to be used in the relocation's section offset. */ | |
12786 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12787 | { |
12788 | reloc->address = reloc->addend; | |
12789 | reloc->addend = 0; | |
12790 | } | |
12791 | ||
252b5132 | 12792 | code = fixp->fx_r_type; |
252b5132 | 12793 | |
3e722fb5 CD |
12794 | /* To support a PC relative reloc, we used a Cygnus extension. |
12795 | We check for that here to make sure that we don't let such a | |
12796 | reloc escape normally. (FIXME: This was formerly used by | |
12797 | embedded-PIC support, but is now used by branch handling in | |
12798 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12799 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12800 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12801 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12802 | reloc->howto = NULL; |
12803 | else | |
12804 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12805 | ||
252b5132 RH |
12806 | if (reloc->howto == NULL) |
12807 | { | |
12808 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12809 | _("Can not represent %s relocation in this object file format"), | |
12810 | bfd_get_reloc_code_name (code)); | |
12811 | retval[0] = NULL; | |
12812 | } | |
12813 | ||
12814 | return retval; | |
12815 | } | |
12816 | ||
12817 | /* Relax a machine dependent frag. This returns the amount by which | |
12818 | the current size of the frag should change. */ | |
12819 | ||
12820 | int | |
17a2f251 | 12821 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12822 | { |
4a6a3df4 AO |
12823 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12824 | { | |
12825 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12826 | |
12827 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12828 | |
12829 | return fragp->fr_var - old_var; | |
12830 | } | |
12831 | ||
252b5132 RH |
12832 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12833 | return 0; | |
12834 | ||
c4e7957c | 12835 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12836 | { |
12837 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12838 | return 0; | |
12839 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12840 | return 2; | |
12841 | } | |
12842 | else | |
12843 | { | |
12844 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12845 | return 0; | |
12846 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12847 | return -2; | |
12848 | } | |
12849 | ||
12850 | return 0; | |
12851 | } | |
12852 | ||
12853 | /* Convert a machine dependent frag. */ | |
12854 | ||
12855 | void | |
17a2f251 | 12856 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12857 | { |
4a6a3df4 AO |
12858 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12859 | { | |
12860 | bfd_byte *buf; | |
12861 | unsigned long insn; | |
12862 | expressionS exp; | |
12863 | fixS *fixp; | |
b34976b6 | 12864 | |
4a6a3df4 AO |
12865 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12866 | ||
12867 | if (target_big_endian) | |
12868 | insn = bfd_getb32 (buf); | |
12869 | else | |
12870 | insn = bfd_getl32 (buf); | |
b34976b6 | 12871 | |
4a6a3df4 AO |
12872 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12873 | { | |
12874 | /* We generate a fixup instead of applying it right now | |
12875 | because, if there are linker relaxations, we're going to | |
12876 | need the relocations. */ | |
12877 | exp.X_op = O_symbol; | |
12878 | exp.X_add_symbol = fragp->fr_symbol; | |
12879 | exp.X_add_number = fragp->fr_offset; | |
12880 | ||
12881 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12882 | 4, &exp, 1, |
12883 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12884 | fixp->fx_file = fragp->fr_file; |
12885 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12886 | |
17a2f251 | 12887 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12888 | buf += 4; |
12889 | } | |
12890 | else | |
12891 | { | |
12892 | int i; | |
12893 | ||
12894 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12895 | _("relaxed out-of-range branch into a jump")); | |
12896 | ||
12897 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12898 | goto uncond; | |
12899 | ||
12900 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12901 | { | |
12902 | /* Reverse the branch. */ | |
12903 | switch ((insn >> 28) & 0xf) | |
12904 | { | |
12905 | case 4: | |
12906 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12907 | have the condition reversed by tweaking a single | |
12908 | bit, and their opcodes all have 0x4???????. */ | |
12909 | assert ((insn & 0xf1000000) == 0x41000000); | |
12910 | insn ^= 0x00010000; | |
12911 | break; | |
12912 | ||
12913 | case 0: | |
12914 | /* bltz 0x04000000 bgez 0x04010000 | |
12915 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12916 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12917 | insn ^= 0x00010000; | |
12918 | break; | |
b34976b6 | 12919 | |
4a6a3df4 AO |
12920 | case 1: |
12921 | /* beq 0x10000000 bne 0x14000000 | |
12922 | blez 0x18000000 bgtz 0x1c000000 */ | |
12923 | insn ^= 0x04000000; | |
12924 | break; | |
12925 | ||
12926 | default: | |
12927 | abort (); | |
12928 | } | |
12929 | } | |
12930 | ||
12931 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12932 | { | |
12933 | /* Clear the and-link bit. */ | |
12934 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12935 | ||
12936 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12937 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12938 | insn &= ~0x00100000; | |
12939 | } | |
12940 | ||
12941 | /* Branch over the branch (if the branch was likely) or the | |
12942 | full jump (not likely case). Compute the offset from the | |
12943 | current instruction to branch to. */ | |
12944 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12945 | i = 16; | |
12946 | else | |
12947 | { | |
12948 | /* How many bytes in instructions we've already emitted? */ | |
12949 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12950 | /* How many bytes in instructions from here to the end? */ | |
12951 | i = fragp->fr_var - i; | |
12952 | } | |
12953 | /* Convert to instruction count. */ | |
12954 | i >>= 2; | |
12955 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12956 | i--; |
4a6a3df4 AO |
12957 | insn |= i; |
12958 | /* Branch over the jump. */ | |
17a2f251 | 12959 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12960 | buf += 4; |
12961 | ||
12962 | /* Nop */ | |
17a2f251 | 12963 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12964 | buf += 4; |
12965 | ||
12966 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12967 | { | |
12968 | /* beql $0, $0, 2f */ | |
12969 | insn = 0x50000000; | |
12970 | /* Compute the PC offset from the current instruction to | |
12971 | the end of the variable frag. */ | |
12972 | /* How many bytes in instructions we've already emitted? */ | |
12973 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12974 | /* How many bytes in instructions from here to the end? */ | |
12975 | i = fragp->fr_var - i; | |
12976 | /* Convert to instruction count. */ | |
12977 | i >>= 2; | |
12978 | /* Don't decrement i, because we want to branch over the | |
12979 | delay slot. */ | |
12980 | ||
12981 | insn |= i; | |
17a2f251 | 12982 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
12983 | buf += 4; |
12984 | ||
17a2f251 | 12985 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
12986 | buf += 4; |
12987 | } | |
12988 | ||
12989 | uncond: | |
12990 | if (mips_pic == NO_PIC) | |
12991 | { | |
12992 | /* j or jal. */ | |
12993 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12994 | ? 0x0c000000 : 0x08000000); | |
12995 | exp.X_op = O_symbol; | |
12996 | exp.X_add_symbol = fragp->fr_symbol; | |
12997 | exp.X_add_number = fragp->fr_offset; | |
12998 | ||
12999 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13000 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13001 | fixp->fx_file = fragp->fr_file; | |
13002 | fixp->fx_line = fragp->fr_line; | |
13003 | ||
17a2f251 | 13004 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13005 | buf += 4; |
13006 | } | |
13007 | else | |
13008 | { | |
13009 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13010 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13011 | exp.X_op = O_symbol; | |
13012 | exp.X_add_symbol = fragp->fr_symbol; | |
13013 | exp.X_add_number = fragp->fr_offset; | |
13014 | ||
13015 | if (fragp->fr_offset) | |
13016 | { | |
13017 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13018 | exp.X_add_number = 0; | |
13019 | } | |
13020 | ||
13021 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13022 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13023 | fixp->fx_file = fragp->fr_file; | |
13024 | fixp->fx_line = fragp->fr_line; | |
13025 | ||
17a2f251 | 13026 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13027 | buf += 4; |
b34976b6 | 13028 | |
4a6a3df4 AO |
13029 | if (mips_opts.isa == ISA_MIPS1) |
13030 | { | |
13031 | /* nop */ | |
17a2f251 | 13032 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13033 | buf += 4; |
13034 | } | |
13035 | ||
13036 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13037 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13038 | ||
13039 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13040 | 4, &exp, 0, BFD_RELOC_LO16); | |
13041 | fixp->fx_file = fragp->fr_file; | |
13042 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13043 | |
17a2f251 | 13044 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13045 | buf += 4; |
13046 | ||
13047 | /* j(al)r $at. */ | |
13048 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13049 | insn = 0x0020f809; | |
13050 | else | |
13051 | insn = 0x00200008; | |
13052 | ||
17a2f251 | 13053 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13054 | buf += 4; |
13055 | } | |
13056 | } | |
13057 | ||
13058 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13059 | + fragp->fr_fix + fragp->fr_var); | |
13060 | ||
13061 | fragp->fr_fix += fragp->fr_var; | |
13062 | ||
13063 | return; | |
13064 | } | |
13065 | ||
252b5132 RH |
13066 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13067 | { | |
13068 | int type; | |
13069 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13070 | bfd_boolean small, ext; |
252b5132 RH |
13071 | offsetT val; |
13072 | bfd_byte *buf; | |
13073 | unsigned long insn; | |
b34976b6 | 13074 | bfd_boolean use_extend; |
252b5132 RH |
13075 | unsigned short extend; |
13076 | ||
13077 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13078 | op = mips16_immed_operands; | |
13079 | while (op->type != type) | |
13080 | ++op; | |
13081 | ||
13082 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13083 | { | |
b34976b6 AM |
13084 | small = FALSE; |
13085 | ext = TRUE; | |
252b5132 RH |
13086 | } |
13087 | else | |
13088 | { | |
b34976b6 AM |
13089 | small = TRUE; |
13090 | ext = FALSE; | |
252b5132 RH |
13091 | } |
13092 | ||
6386f3a7 | 13093 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13094 | val = S_GET_VALUE (fragp->fr_symbol); |
13095 | if (op->pcrel) | |
13096 | { | |
13097 | addressT addr; | |
13098 | ||
13099 | addr = fragp->fr_address + fragp->fr_fix; | |
13100 | ||
13101 | /* The rules for the base address of a PC relative reloc are | |
13102 | complicated; see mips16_extended_frag. */ | |
13103 | if (type == 'p' || type == 'q') | |
13104 | { | |
13105 | addr += 2; | |
13106 | if (ext) | |
13107 | addr += 2; | |
13108 | /* Ignore the low bit in the target, since it will be | |
13109 | set for a text label. */ | |
13110 | if ((val & 1) != 0) | |
13111 | --val; | |
13112 | } | |
13113 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13114 | addr -= 4; | |
13115 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13116 | addr -= 2; | |
13117 | ||
13118 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13119 | val -= addr; | |
13120 | ||
13121 | /* Make sure the section winds up with the alignment we have | |
13122 | assumed. */ | |
13123 | if (op->shift > 0) | |
13124 | record_alignment (asec, op->shift); | |
13125 | } | |
13126 | ||
13127 | if (ext | |
13128 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13129 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13130 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13131 | _("extended instruction in delay slot")); | |
13132 | ||
13133 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13134 | ||
13135 | if (target_big_endian) | |
13136 | insn = bfd_getb16 (buf); | |
13137 | else | |
13138 | insn = bfd_getl16 (buf); | |
13139 | ||
13140 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13141 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13142 | small, ext, &insn, &use_extend, &extend); | |
13143 | ||
13144 | if (use_extend) | |
13145 | { | |
17a2f251 | 13146 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13147 | fragp->fr_fix += 2; |
13148 | buf += 2; | |
13149 | } | |
13150 | ||
17a2f251 | 13151 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13152 | fragp->fr_fix += 2; |
13153 | buf += 2; | |
13154 | } | |
13155 | else | |
13156 | { | |
4d7206a2 RS |
13157 | int first, second; |
13158 | fixS *fixp; | |
252b5132 | 13159 | |
4d7206a2 RS |
13160 | first = RELAX_FIRST (fragp->fr_subtype); |
13161 | second = RELAX_SECOND (fragp->fr_subtype); | |
13162 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13163 | |
584892a6 RS |
13164 | /* Possibly emit a warning if we've chosen the longer option. */ |
13165 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13166 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13167 | { | |
13168 | const char *msg = macro_warning (fragp->fr_subtype); | |
13169 | if (msg != 0) | |
13170 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13171 | } | |
13172 | ||
4d7206a2 RS |
13173 | /* Go through all the fixups for the first sequence. Disable them |
13174 | (by marking them as done) if we're going to use the second | |
13175 | sequence instead. */ | |
13176 | while (fixp | |
13177 | && fixp->fx_frag == fragp | |
13178 | && fixp->fx_where < fragp->fr_fix - second) | |
13179 | { | |
13180 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13181 | fixp->fx_done = 1; | |
13182 | fixp = fixp->fx_next; | |
13183 | } | |
252b5132 | 13184 | |
4d7206a2 RS |
13185 | /* Go through the fixups for the second sequence. Disable them if |
13186 | we're going to use the first sequence, otherwise adjust their | |
13187 | addresses to account for the relaxation. */ | |
13188 | while (fixp && fixp->fx_frag == fragp) | |
13189 | { | |
13190 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13191 | fixp->fx_where -= first; | |
13192 | else | |
13193 | fixp->fx_done = 1; | |
13194 | fixp = fixp->fx_next; | |
13195 | } | |
13196 | ||
13197 | /* Now modify the frag contents. */ | |
13198 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13199 | { | |
13200 | char *start; | |
13201 | ||
13202 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13203 | memmove (start, start + first, second); | |
13204 | fragp->fr_fix -= first; | |
13205 | } | |
13206 | else | |
13207 | fragp->fr_fix -= second; | |
252b5132 RH |
13208 | } |
13209 | } | |
13210 | ||
13211 | #ifdef OBJ_ELF | |
13212 | ||
13213 | /* This function is called after the relocs have been generated. | |
13214 | We've been storing mips16 text labels as odd. Here we convert them | |
13215 | back to even for the convenience of the debugger. */ | |
13216 | ||
13217 | void | |
17a2f251 | 13218 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13219 | { |
13220 | asymbol **syms; | |
13221 | unsigned int count, i; | |
13222 | ||
13223 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13224 | return; | |
13225 | ||
13226 | syms = bfd_get_outsymbols (stdoutput); | |
13227 | count = bfd_get_symcount (stdoutput); | |
13228 | for (i = 0; i < count; i++, syms++) | |
13229 | { | |
13230 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13231 | && ((*syms)->value & 1) != 0) | |
13232 | { | |
13233 | (*syms)->value &= ~1; | |
13234 | /* If the symbol has an odd size, it was probably computed | |
13235 | incorrectly, so adjust that as well. */ | |
13236 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13237 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13238 | } | |
13239 | } | |
13240 | } | |
13241 | ||
13242 | #endif | |
13243 | ||
13244 | /* This function is called whenever a label is defined. It is used | |
13245 | when handling branch delays; if a branch has a label, we assume we | |
13246 | can not move it. */ | |
13247 | ||
13248 | void | |
17a2f251 | 13249 | mips_define_label (symbolS *sym) |
252b5132 RH |
13250 | { |
13251 | struct insn_label_list *l; | |
13252 | ||
13253 | if (free_insn_labels == NULL) | |
13254 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13255 | else | |
13256 | { | |
13257 | l = free_insn_labels; | |
13258 | free_insn_labels = l->next; | |
13259 | } | |
13260 | ||
13261 | l->label = sym; | |
13262 | l->next = insn_labels; | |
13263 | insn_labels = l; | |
13264 | } | |
13265 | \f | |
13266 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13267 | ||
13268 | /* Some special processing for a MIPS ELF file. */ | |
13269 | ||
13270 | void | |
17a2f251 | 13271 | mips_elf_final_processing (void) |
252b5132 RH |
13272 | { |
13273 | /* Write out the register information. */ | |
316f5878 | 13274 | if (mips_abi != N64_ABI) |
252b5132 RH |
13275 | { |
13276 | Elf32_RegInfo s; | |
13277 | ||
13278 | s.ri_gprmask = mips_gprmask; | |
13279 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13280 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13281 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13282 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13283 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13284 | ||
13285 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13286 | ((Elf32_External_RegInfo *) | |
13287 | mips_regmask_frag)); | |
13288 | } | |
13289 | else | |
13290 | { | |
13291 | Elf64_Internal_RegInfo s; | |
13292 | ||
13293 | s.ri_gprmask = mips_gprmask; | |
13294 | s.ri_pad = 0; | |
13295 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13296 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13297 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13298 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13299 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13300 | ||
13301 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13302 | ((Elf64_External_RegInfo *) | |
13303 | mips_regmask_frag)); | |
13304 | } | |
13305 | ||
13306 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13307 | sort of BFD interface for this. */ | |
13308 | if (mips_any_noreorder) | |
13309 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13310 | if (mips_pic != NO_PIC) | |
143d77c5 | 13311 | { |
252b5132 | 13312 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13313 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13314 | } | |
13315 | if (mips_abicalls) | |
13316 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13317 | |
98d3f06f | 13318 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13319 | if (file_ase_mips16) |
13320 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13321 | #if 0 /* XXX FIXME */ |
13322 | if (file_ase_mips3d) | |
13323 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13324 | #endif | |
deec1734 CD |
13325 | if (file_ase_mdmx) |
13326 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13327 | |
bdaaa2e1 | 13328 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13329 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13330 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13331 | else if (mips_abi == O64_ABI) |
252b5132 | 13332 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13333 | else if (mips_abi == EABI_ABI) |
252b5132 | 13334 | { |
316f5878 | 13335 | if (!file_mips_gp32) |
252b5132 RH |
13336 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13337 | else | |
13338 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13339 | } | |
316f5878 | 13340 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13341 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13342 | ||
c9914766 | 13343 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13344 | |
13345 | if (mips_32bitmode) | |
13346 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13347 | } | |
13348 | ||
13349 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13350 | \f | |
beae10d5 KH |
13351 | typedef struct proc { |
13352 | symbolS *isym; | |
13353 | unsigned long reg_mask; | |
13354 | unsigned long reg_offset; | |
13355 | unsigned long fpreg_mask; | |
13356 | unsigned long fpreg_offset; | |
13357 | unsigned long frame_offset; | |
13358 | unsigned long frame_reg; | |
13359 | unsigned long pc_reg; | |
13360 | } procS; | |
252b5132 RH |
13361 | |
13362 | static procS cur_proc; | |
13363 | static procS *cur_proc_ptr; | |
13364 | static int numprocs; | |
13365 | ||
0a9ef439 | 13366 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13367 | |
0a9ef439 | 13368 | void |
17a2f251 | 13369 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13370 | { |
0a9ef439 RH |
13371 | if (fragp->fr_type != rs_align_code) |
13372 | return; | |
13373 | ||
13374 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13375 | { |
13376 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13377 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13378 | ||
0a9ef439 RH |
13379 | int bytes; |
13380 | char *p; | |
a19d8eb0 | 13381 | |
0a9ef439 RH |
13382 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13383 | p = fragp->fr_literal + fragp->fr_fix; | |
13384 | ||
13385 | if (bytes & 1) | |
13386 | { | |
13387 | *p++ = 0; | |
f9419b05 | 13388 | fragp->fr_fix++; |
0a9ef439 RH |
13389 | } |
13390 | ||
13391 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13392 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13393 | } |
13394 | ||
0a9ef439 | 13395 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13396 | } |
13397 | ||
252b5132 | 13398 | static void |
17a2f251 | 13399 | md_obj_begin (void) |
252b5132 RH |
13400 | { |
13401 | } | |
13402 | ||
13403 | static void | |
17a2f251 | 13404 | md_obj_end (void) |
252b5132 RH |
13405 | { |
13406 | /* check for premature end, nesting errors, etc */ | |
13407 | if (cur_proc_ptr) | |
9a41af64 | 13408 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13409 | } |
13410 | ||
13411 | static long | |
17a2f251 | 13412 | get_number (void) |
252b5132 RH |
13413 | { |
13414 | int negative = 0; | |
13415 | long val = 0; | |
13416 | ||
13417 | if (*input_line_pointer == '-') | |
13418 | { | |
13419 | ++input_line_pointer; | |
13420 | negative = 1; | |
13421 | } | |
3882b010 | 13422 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13423 | as_bad (_("expected simple number")); |
252b5132 RH |
13424 | if (input_line_pointer[0] == '0') |
13425 | { | |
13426 | if (input_line_pointer[1] == 'x') | |
13427 | { | |
13428 | input_line_pointer += 2; | |
3882b010 | 13429 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13430 | { |
13431 | val <<= 4; | |
13432 | val |= hex_value (*input_line_pointer++); | |
13433 | } | |
13434 | return negative ? -val : val; | |
13435 | } | |
13436 | else | |
13437 | { | |
13438 | ++input_line_pointer; | |
3882b010 | 13439 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13440 | { |
13441 | val <<= 3; | |
13442 | val |= *input_line_pointer++ - '0'; | |
13443 | } | |
13444 | return negative ? -val : val; | |
13445 | } | |
13446 | } | |
3882b010 | 13447 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13448 | { |
13449 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13450 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13451 | as_warn (_("invalid number")); |
252b5132 RH |
13452 | return -1; |
13453 | } | |
3882b010 | 13454 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13455 | { |
13456 | val *= 10; | |
13457 | val += *input_line_pointer++ - '0'; | |
13458 | } | |
13459 | return negative ? -val : val; | |
13460 | } | |
13461 | ||
13462 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13463 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13464 | case .file implies DWARF-2. */ | |
13465 | ||
13466 | static void | |
17a2f251 | 13467 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13468 | { |
ecb4347a DJ |
13469 | static int first_file_directive = 0; |
13470 | ||
c5dd6aab DJ |
13471 | if (ECOFF_DEBUGGING) |
13472 | { | |
13473 | get_number (); | |
13474 | s_app_file (0); | |
13475 | } | |
13476 | else | |
ecb4347a DJ |
13477 | { |
13478 | char *filename; | |
13479 | ||
13480 | filename = dwarf2_directive_file (0); | |
13481 | ||
13482 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13483 | directive even for stabs output. Make sure that this | |
13484 | ".file" is handled. Note that you need a version of GCC | |
13485 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13486 | if (filename != NULL && ! first_file_directive) | |
13487 | { | |
13488 | (void) new_logical_line (filename, -1); | |
13489 | s_app_file_string (filename); | |
13490 | } | |
13491 | first_file_directive = 1; | |
13492 | } | |
c5dd6aab DJ |
13493 | } |
13494 | ||
13495 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13496 | |
13497 | static void | |
17a2f251 | 13498 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13499 | { |
c5dd6aab DJ |
13500 | if (!ECOFF_DEBUGGING) |
13501 | dwarf2_directive_loc (0); | |
252b5132 RH |
13502 | } |
13503 | ||
252b5132 RH |
13504 | /* The .end directive. */ |
13505 | ||
13506 | static void | |
17a2f251 | 13507 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13508 | { |
13509 | symbolS *p; | |
252b5132 | 13510 | |
7a621144 DJ |
13511 | /* Following functions need their own .frame and .cprestore directives. */ |
13512 | mips_frame_reg_valid = 0; | |
13513 | mips_cprestore_valid = 0; | |
13514 | ||
252b5132 RH |
13515 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13516 | { | |
13517 | p = get_symbol (); | |
13518 | demand_empty_rest_of_line (); | |
13519 | } | |
13520 | else | |
13521 | p = NULL; | |
13522 | ||
14949570 | 13523 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13524 | as_warn (_(".end not in text section")); |
13525 | ||
13526 | if (!cur_proc_ptr) | |
13527 | { | |
13528 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13529 | demand_empty_rest_of_line (); | |
13530 | return; | |
13531 | } | |
13532 | ||
13533 | if (p != NULL) | |
13534 | { | |
13535 | assert (S_GET_NAME (p)); | |
13536 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13537 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13538 | |
13539 | if (debug_type == DEBUG_STABS) | |
13540 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13541 | S_GET_NAME (p)); | |
252b5132 RH |
13542 | } |
13543 | else | |
13544 | as_warn (_(".end directive missing or unknown symbol")); | |
13545 | ||
ecb4347a DJ |
13546 | #ifdef OBJ_ELF |
13547 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13548 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13549 | && mips_flag_pdr) | |
ecb4347a DJ |
13550 | { |
13551 | segT saved_seg = now_seg; | |
13552 | subsegT saved_subseg = now_subseg; | |
13553 | valueT dot; | |
13554 | expressionS exp; | |
13555 | char *fragp; | |
252b5132 | 13556 | |
ecb4347a | 13557 | dot = frag_now_fix (); |
252b5132 RH |
13558 | |
13559 | #ifdef md_flush_pending_output | |
ecb4347a | 13560 | md_flush_pending_output (); |
252b5132 RH |
13561 | #endif |
13562 | ||
ecb4347a DJ |
13563 | assert (pdr_seg); |
13564 | subseg_set (pdr_seg, 0); | |
252b5132 | 13565 | |
ecb4347a DJ |
13566 | /* Write the symbol. */ |
13567 | exp.X_op = O_symbol; | |
13568 | exp.X_add_symbol = p; | |
13569 | exp.X_add_number = 0; | |
13570 | emit_expr (&exp, 4); | |
252b5132 | 13571 | |
ecb4347a | 13572 | fragp = frag_more (7 * 4); |
252b5132 | 13573 | |
17a2f251 TS |
13574 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13575 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13576 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13577 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13578 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13579 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13580 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13581 | |
ecb4347a DJ |
13582 | subseg_set (saved_seg, saved_subseg); |
13583 | } | |
13584 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13585 | |
13586 | cur_proc_ptr = NULL; | |
13587 | } | |
13588 | ||
13589 | /* The .aent and .ent directives. */ | |
13590 | ||
13591 | static void | |
17a2f251 | 13592 | s_mips_ent (int aent) |
252b5132 | 13593 | { |
252b5132 | 13594 | symbolS *symbolP; |
252b5132 RH |
13595 | |
13596 | symbolP = get_symbol (); | |
13597 | if (*input_line_pointer == ',') | |
f9419b05 | 13598 | ++input_line_pointer; |
252b5132 | 13599 | SKIP_WHITESPACE (); |
3882b010 | 13600 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13601 | || *input_line_pointer == '-') |
874e8986 | 13602 | get_number (); |
252b5132 | 13603 | |
14949570 | 13604 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13605 | as_warn (_(".ent or .aent not in text section.")); |
13606 | ||
13607 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13608 | as_warn (_("missing .end")); |
252b5132 RH |
13609 | |
13610 | if (!aent) | |
13611 | { | |
7a621144 DJ |
13612 | /* This function needs its own .frame and .cprestore directives. */ |
13613 | mips_frame_reg_valid = 0; | |
13614 | mips_cprestore_valid = 0; | |
13615 | ||
252b5132 RH |
13616 | cur_proc_ptr = &cur_proc; |
13617 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13618 | ||
13619 | cur_proc_ptr->isym = symbolP; | |
13620 | ||
49309057 | 13621 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13622 | |
f9419b05 | 13623 | ++numprocs; |
ecb4347a DJ |
13624 | |
13625 | if (debug_type == DEBUG_STABS) | |
13626 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13627 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13628 | } |
13629 | ||
13630 | demand_empty_rest_of_line (); | |
13631 | } | |
13632 | ||
13633 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13634 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13635 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13636 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13637 | symbol table (in the mdebug section). */ |
13638 | ||
13639 | static void | |
17a2f251 | 13640 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13641 | { |
ecb4347a DJ |
13642 | #ifdef OBJ_ELF |
13643 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13644 | { | |
13645 | long val; | |
252b5132 | 13646 | |
ecb4347a DJ |
13647 | if (cur_proc_ptr == (procS *) NULL) |
13648 | { | |
13649 | as_warn (_(".frame outside of .ent")); | |
13650 | demand_empty_rest_of_line (); | |
13651 | return; | |
13652 | } | |
252b5132 | 13653 | |
ecb4347a DJ |
13654 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13655 | ||
13656 | SKIP_WHITESPACE (); | |
13657 | if (*input_line_pointer++ != ',' | |
13658 | || get_absolute_expression_and_terminator (&val) != ',') | |
13659 | { | |
13660 | as_warn (_("Bad .frame directive")); | |
13661 | --input_line_pointer; | |
13662 | demand_empty_rest_of_line (); | |
13663 | return; | |
13664 | } | |
252b5132 | 13665 | |
ecb4347a DJ |
13666 | cur_proc_ptr->frame_offset = val; |
13667 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13668 | |
252b5132 | 13669 | demand_empty_rest_of_line (); |
252b5132 | 13670 | } |
ecb4347a DJ |
13671 | else |
13672 | #endif /* OBJ_ELF */ | |
13673 | s_ignore (ignore); | |
252b5132 RH |
13674 | } |
13675 | ||
bdaaa2e1 KH |
13676 | /* The .fmask and .mask directives. If the mdebug section is present |
13677 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13678 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13679 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13680 | make reference to the ecoff symbol table (in the mdebug section). */ |
13681 | ||
13682 | static void | |
17a2f251 | 13683 | s_mips_mask (int reg_type) |
252b5132 | 13684 | { |
ecb4347a DJ |
13685 | #ifdef OBJ_ELF |
13686 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13687 | { |
ecb4347a | 13688 | long mask, off; |
252b5132 | 13689 | |
ecb4347a DJ |
13690 | if (cur_proc_ptr == (procS *) NULL) |
13691 | { | |
13692 | as_warn (_(".mask/.fmask outside of .ent")); | |
13693 | demand_empty_rest_of_line (); | |
13694 | return; | |
13695 | } | |
252b5132 | 13696 | |
ecb4347a DJ |
13697 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13698 | { | |
13699 | as_warn (_("Bad .mask/.fmask directive")); | |
13700 | --input_line_pointer; | |
13701 | demand_empty_rest_of_line (); | |
13702 | return; | |
13703 | } | |
252b5132 | 13704 | |
ecb4347a DJ |
13705 | off = get_absolute_expression (); |
13706 | ||
13707 | if (reg_type == 'F') | |
13708 | { | |
13709 | cur_proc_ptr->fpreg_mask = mask; | |
13710 | cur_proc_ptr->fpreg_offset = off; | |
13711 | } | |
13712 | else | |
13713 | { | |
13714 | cur_proc_ptr->reg_mask = mask; | |
13715 | cur_proc_ptr->reg_offset = off; | |
13716 | } | |
13717 | ||
13718 | demand_empty_rest_of_line (); | |
252b5132 RH |
13719 | } |
13720 | else | |
ecb4347a DJ |
13721 | #endif /* OBJ_ELF */ |
13722 | s_ignore (reg_type); | |
252b5132 RH |
13723 | } |
13724 | ||
13725 | /* The .loc directive. */ | |
13726 | ||
13727 | #if 0 | |
13728 | static void | |
17a2f251 | 13729 | s_loc (int x) |
252b5132 RH |
13730 | { |
13731 | symbolS *symbolP; | |
13732 | int lineno; | |
13733 | int addroff; | |
13734 | ||
13735 | assert (now_seg == text_section); | |
13736 | ||
13737 | lineno = get_number (); | |
13738 | addroff = frag_now_fix (); | |
13739 | ||
13740 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13741 | S_SET_TYPE (symbolP, N_SLINE); | |
13742 | S_SET_OTHER (symbolP, 0); | |
13743 | S_SET_DESC (symbolP, lineno); | |
13744 | symbolP->sy_segment = now_seg; | |
13745 | } | |
13746 | #endif | |
e7af610e | 13747 | |
316f5878 RS |
13748 | /* A table describing all the processors gas knows about. Names are |
13749 | matched in the order listed. | |
e7af610e | 13750 | |
316f5878 RS |
13751 | To ease comparison, please keep this table in the same order as |
13752 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13753 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13754 | { | |
316f5878 RS |
13755 | /* Entries for generic ISAs */ |
13756 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13757 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13758 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13759 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13760 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13761 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13762 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13763 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13764 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13765 | |
13766 | /* MIPS I */ | |
13767 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13768 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13769 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13770 | ||
13771 | /* MIPS II */ | |
13772 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13773 | ||
13774 | /* MIPS III */ | |
13775 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13776 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13777 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13778 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13779 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13780 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13781 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13782 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13783 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13784 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13785 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13786 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13787 | ||
13788 | /* MIPS IV */ | |
13789 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13790 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13791 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13792 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13793 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13794 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13795 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13796 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13797 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13798 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13799 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
13800 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
13801 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
13802 | |
13803 | /* MIPS 32 */ | |
fef14a42 | 13804 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13805 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13806 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13807 | |
316f5878 RS |
13808 | /* MIPS 64 */ |
13809 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13810 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13811 | |
c7a23324 | 13812 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13813 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13814 | |
316f5878 RS |
13815 | /* End marker */ |
13816 | { NULL, 0, 0, 0 } | |
13817 | }; | |
e7af610e | 13818 | |
84ea6cf2 | 13819 | |
316f5878 RS |
13820 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13821 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13822 | |
316f5878 | 13823 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13824 | |
b34976b6 | 13825 | static bfd_boolean |
17a2f251 | 13826 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13827 | { |
13828 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13829 | given++, canonical++; | |
13830 | ||
13831 | return ((*given == 0 && *canonical == 0) | |
13832 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13833 | } | |
13834 | ||
13835 | ||
13836 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13837 | CPU name. We've traditionally allowed a lot of variation here. | |
13838 | ||
13839 | Note: this function is shared between GCC and GAS. */ | |
13840 | ||
b34976b6 | 13841 | static bfd_boolean |
17a2f251 | 13842 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13843 | { |
13844 | /* First see if the name matches exactly, or with a final "000" | |
13845 | turned into "k". */ | |
13846 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13847 | return TRUE; |
316f5878 RS |
13848 | |
13849 | /* If not, try comparing based on numerical designation alone. | |
13850 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13851 | if (TOLOWER (*given) == 'r') | |
13852 | given++; | |
13853 | if (!ISDIGIT (*given)) | |
b34976b6 | 13854 | return FALSE; |
316f5878 RS |
13855 | |
13856 | /* Skip over some well-known prefixes in the canonical name, | |
13857 | hoping to find a number there too. */ | |
13858 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13859 | canonical += 2; | |
13860 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13861 | canonical += 2; | |
13862 | else if (TOLOWER (canonical[0]) == 'r') | |
13863 | canonical += 1; | |
13864 | ||
13865 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13866 | } | |
13867 | ||
13868 | ||
13869 | /* Parse an option that takes the name of a processor as its argument. | |
13870 | OPTION is the name of the option and CPU_STRING is the argument. | |
13871 | Return the corresponding processor enumeration if the CPU_STRING is | |
13872 | recognized, otherwise report an error and return null. | |
13873 | ||
13874 | A similar function exists in GCC. */ | |
e7af610e NC |
13875 | |
13876 | static const struct mips_cpu_info * | |
17a2f251 | 13877 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13878 | { |
316f5878 | 13879 | const struct mips_cpu_info *p; |
e7af610e | 13880 | |
316f5878 RS |
13881 | /* 'from-abi' selects the most compatible architecture for the given |
13882 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13883 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13884 | version. Look first at the -mgp options, if given, otherwise base | |
13885 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13886 | |
316f5878 RS |
13887 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13888 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13889 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13890 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13891 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13892 | { | |
13893 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13894 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13895 | ||
13896 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13897 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13898 | ||
13899 | if (file_mips_gp32 >= 0) | |
13900 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13901 | ||
13902 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13903 | ? ISA_MIPS3 | |
13904 | : ISA_MIPS1); | |
13905 | } | |
13906 | ||
13907 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13908 | if (strcasecmp (cpu_string, "default") == 0) | |
13909 | return 0; | |
13910 | ||
13911 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13912 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13913 | return p; | |
13914 | ||
13915 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13916 | return 0; | |
e7af610e NC |
13917 | } |
13918 | ||
316f5878 RS |
13919 | /* Return the canonical processor information for ISA (a member of the |
13920 | ISA_MIPS* enumeration). */ | |
13921 | ||
e7af610e | 13922 | static const struct mips_cpu_info * |
17a2f251 | 13923 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13924 | { |
13925 | int i; | |
13926 | ||
13927 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13928 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13929 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13930 | return (&mips_cpu_info_table[i]); |
13931 | ||
e972090a | 13932 | return NULL; |
e7af610e | 13933 | } |
fef14a42 TS |
13934 | |
13935 | static const struct mips_cpu_info * | |
17a2f251 | 13936 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13937 | { |
13938 | int i; | |
13939 | ||
13940 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13941 | if (arch == mips_cpu_info_table[i].cpu) | |
13942 | return (&mips_cpu_info_table[i]); | |
13943 | ||
13944 | return NULL; | |
13945 | } | |
316f5878 RS |
13946 | \f |
13947 | static void | |
17a2f251 | 13948 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13949 | { |
13950 | if (*first_p) | |
13951 | { | |
13952 | fprintf (stream, "%24s", ""); | |
13953 | *col_p = 24; | |
13954 | } | |
13955 | else | |
13956 | { | |
13957 | fprintf (stream, ", "); | |
13958 | *col_p += 2; | |
13959 | } | |
e7af610e | 13960 | |
316f5878 RS |
13961 | if (*col_p + strlen (string) > 72) |
13962 | { | |
13963 | fprintf (stream, "\n%24s", ""); | |
13964 | *col_p = 24; | |
13965 | } | |
13966 | ||
13967 | fprintf (stream, "%s", string); | |
13968 | *col_p += strlen (string); | |
13969 | ||
13970 | *first_p = 0; | |
13971 | } | |
13972 | ||
13973 | void | |
17a2f251 | 13974 | md_show_usage (FILE *stream) |
e7af610e | 13975 | { |
316f5878 RS |
13976 | int column, first; |
13977 | size_t i; | |
13978 | ||
13979 | fprintf (stream, _("\ | |
13980 | MIPS options:\n\ | |
316f5878 RS |
13981 | -EB generate big endian output\n\ |
13982 | -EL generate little endian output\n\ | |
13983 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13984 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13985 | implicitly with the gp register [default 8]\n")); | |
13986 | fprintf (stream, _("\ | |
13987 | -mips1 generate MIPS ISA I instructions\n\ | |
13988 | -mips2 generate MIPS ISA II instructions\n\ | |
13989 | -mips3 generate MIPS ISA III instructions\n\ | |
13990 | -mips4 generate MIPS ISA IV instructions\n\ | |
13991 | -mips5 generate MIPS ISA V instructions\n\ | |
13992 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13993 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13994 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13995 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13996 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13997 | ||
13998 | first = 1; | |
e7af610e NC |
13999 | |
14000 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14001 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14002 | show (stream, "from-abi", &column, &first); | |
14003 | fputc ('\n', stream); | |
e7af610e | 14004 | |
316f5878 RS |
14005 | fprintf (stream, _("\ |
14006 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14007 | -no-mCPU don't generate code specific to CPU.\n\ | |
14008 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14009 | ||
14010 | first = 1; | |
14011 | ||
14012 | show (stream, "3900", &column, &first); | |
14013 | show (stream, "4010", &column, &first); | |
14014 | show (stream, "4100", &column, &first); | |
14015 | show (stream, "4650", &column, &first); | |
14016 | fputc ('\n', stream); | |
14017 | ||
14018 | fprintf (stream, _("\ | |
14019 | -mips16 generate mips16 instructions\n\ | |
14020 | -no-mips16 do not generate mips16 instructions\n")); | |
14021 | fprintf (stream, _("\ | |
d766e8ec | 14022 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14023 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14024 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14025 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14026 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14027 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14028 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14029 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14030 | #ifdef OBJ_ELF | |
14031 | fprintf (stream, _("\ | |
14032 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14033 | -non_shared do not generate position independent code\n\ | |
14034 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14035 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14036 | -mabi=ABI create ABI conformant object file for:\n")); |
14037 | ||
14038 | first = 1; | |
14039 | ||
14040 | show (stream, "32", &column, &first); | |
14041 | show (stream, "o64", &column, &first); | |
14042 | show (stream, "n32", &column, &first); | |
14043 | show (stream, "64", &column, &first); | |
14044 | show (stream, "eabi", &column, &first); | |
14045 | ||
14046 | fputc ('\n', stream); | |
14047 | ||
14048 | fprintf (stream, _("\ | |
14049 | -32 create o32 ABI object file (default)\n\ | |
14050 | -n32 create n32 ABI object file\n\ | |
14051 | -64 create 64 ABI object file\n")); | |
14052 | #endif | |
e7af610e | 14053 | } |
14e777e0 KB |
14054 | |
14055 | enum dwarf2_format | |
17a2f251 | 14056 | mips_dwarf2_format (void) |
14e777e0 KB |
14057 | { |
14058 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14059 | { |
14060 | #ifdef TE_IRIX | |
14061 | return dwarf2_format_64bit_irix; | |
14062 | #else | |
14063 | return dwarf2_format_64bit; | |
14064 | #endif | |
14065 | } | |
14e777e0 KB |
14066 | else |
14067 | return dwarf2_format_32bit; | |
14068 | } | |
73369e65 EC |
14069 | |
14070 | int | |
14071 | mips_dwarf2_addr_size (void) | |
14072 | { | |
14073 | if (mips_abi == N64_ABI) | |
14074 | return 8; | |
73369e65 EC |
14075 | else |
14076 | return 4; | |
14077 | } |