Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d RS |
152 | |
153 | /* True if this instruction occured in a .set noreorder block. */ | |
154 | unsigned int noreorder_p : 1; | |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
252b5132 RH |
196 | /* Whether we are assembling for the mips16 processor. 0 if we are |
197 | not, 1 if we are, and -1 if the value has not been initialized. | |
198 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
199 | -nomips16 command line options, and the default CPU. */ | |
200 | int mips16; | |
201 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
202 | reorder' and `.set noreorder'. */ | |
203 | int noreorder; | |
204 | /* Non-zero if we should not permit the $at ($1) register to be used | |
205 | in instructions. Changed by `.set at' and `.set noat'. */ | |
206 | int noat; | |
207 | /* Non-zero if we should warn when a macro instruction expands into | |
208 | more than one machine instruction. Changed by `.set nomacro' and | |
209 | `.set macro'. */ | |
210 | int warn_about_macros; | |
211 | /* Non-zero if we should not move instructions. Changed by `.set | |
212 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
213 | int nomove; | |
214 | /* Non-zero if we should not optimize branches by moving the target | |
215 | of the branch into the delay slot. Actually, we don't perform | |
216 | this optimization anyhow. Changed by `.set bopt' and `.set | |
217 | nobopt'. */ | |
218 | int nobopt; | |
219 | /* Non-zero if we should not autoextend mips16 instructions. | |
220 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
221 | int noautoextend; | |
a325df1d TS |
222 | /* Restrict general purpose registers and floating point registers |
223 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
224 | is passed but can changed if the assembler code uses .set mipsN. */ | |
225 | int gp32; | |
226 | int fp32; | |
fef14a42 TS |
227 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
228 | command line option, and the default CPU. */ | |
229 | int arch; | |
aed1a261 RS |
230 | /* True if ".set sym32" is in effect. */ |
231 | bfd_boolean sym32; | |
252b5132 RH |
232 | }; |
233 | ||
a325df1d | 234 | /* True if -mgp32 was passed. */ |
a8e8e863 | 235 | static int file_mips_gp32 = -1; |
a325df1d TS |
236 | |
237 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 238 | static int file_mips_fp32 = -1; |
a325df1d | 239 | |
252b5132 | 240 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 241 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 242 | -1 to indicate that they have not been initialized. */ |
252b5132 | 243 | |
e972090a NC |
244 | static struct mips_set_options mips_opts = |
245 | { | |
aed1a261 | 246 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 247 | }; |
252b5132 RH |
248 | |
249 | /* These variables are filled in with the masks of registers used. | |
250 | The object format code reads them and puts them in the appropriate | |
251 | place. */ | |
252 | unsigned long mips_gprmask; | |
253 | unsigned long mips_cprmask[4]; | |
254 | ||
255 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 256 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 257 | |
a4672219 TS |
258 | /* True if -mips16 was passed or implied by arguments passed on the |
259 | command line (e.g., by -march). */ | |
260 | static int file_ase_mips16; | |
261 | ||
1f25f5d3 CD |
262 | /* True if -mips3d was passed or implied by arguments passed on the |
263 | command line (e.g., by -march). */ | |
264 | static int file_ase_mips3d; | |
265 | ||
deec1734 CD |
266 | /* True if -mdmx was passed or implied by arguments passed on the |
267 | command line (e.g., by -march). */ | |
268 | static int file_ase_mdmx; | |
269 | ||
ec68c924 | 270 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 271 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 272 | static const char *mips_arch_string; |
ec68c924 EC |
273 | |
274 | /* The argument of the -mtune= flag. The architecture for which we | |
275 | are optimizing. */ | |
276 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 277 | static const char *mips_tune_string; |
ec68c924 | 278 | |
316f5878 | 279 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
280 | static int mips_32bitmode = 0; |
281 | ||
316f5878 RS |
282 | /* True if the given ABI requires 32-bit registers. */ |
283 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
284 | ||
285 | /* Likewise 64-bit registers. */ | |
286 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
287 | ((ABI) == N32_ABI \ | |
288 | || (ABI) == N64_ABI \ | |
289 | || (ABI) == O64_ABI) | |
290 | ||
bdaaa2e1 | 291 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 292 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
293 | (ISA) == ISA_MIPS3 \ |
294 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 295 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 296 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 297 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
298 | ) |
299 | ||
af7ee8bf CD |
300 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
301 | instructions. */ | |
302 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 303 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
304 | ) |
305 | ||
306 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
307 | instructions. */ | |
308 | #define ISA_HAS_ROR(ISA) ( \ | |
309 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 310 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
311 | ) |
312 | ||
e013f690 | 313 | #define HAVE_32BIT_GPRS \ |
316f5878 | 314 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 315 | |
e013f690 | 316 | #define HAVE_32BIT_FPRS \ |
316f5878 | 317 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
318 | |
319 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
320 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
321 | ||
316f5878 | 322 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 323 | |
316f5878 | 324 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 325 | |
3b91255e RS |
326 | /* True if relocations are stored in-place. */ |
327 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
328 | ||
aed1a261 RS |
329 | /* The ABI-derived address size. */ |
330 | #define HAVE_64BIT_ADDRESSES \ | |
331 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
332 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 333 | |
aed1a261 RS |
334 | /* The size of symbolic constants (i.e., expressions of the form |
335 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
336 | #define HAVE_32BIT_SYMBOLS \ | |
337 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
338 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 339 | |
b7c7d6c1 TS |
340 | /* Addresses are loaded in different ways, depending on the address size |
341 | in use. The n32 ABI Documentation also mandates the use of additions | |
342 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 343 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 344 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
345 | |
346 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 347 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
348 | |
349 | #define ADDRESS_LOAD_INSN \ | |
350 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
351 | ||
352 | #define ADDRESS_STORE_INSN \ | |
353 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
354 | ||
a4672219 | 355 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
356 | #define CPU_HAS_MIPS16(cpu) \ |
357 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
358 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 359 | |
1f25f5d3 CD |
360 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
361 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
362 | ) | |
363 | ||
deec1734 | 364 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 365 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
366 | ) |
367 | ||
60b63b72 RS |
368 | /* True if CPU has a dror instruction. */ |
369 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
370 | ||
371 | /* True if CPU has a ror instruction. */ | |
372 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
373 | ||
c8978940 CD |
374 | /* True if mflo and mfhi can be immediately followed by instructions |
375 | which write to the HI and LO registers. | |
376 | ||
377 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
378 | (at least) two instructions between the reads of HI/LO and | |
379 | instructions which write them, and later ISAs do not. Contradicting | |
380 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
381 | the UM for the NEC Vr5000) document needing the instructions between | |
382 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
383 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
384 | earlier-ISA CPUs for which CPU documentation declares that the | |
385 | instructions are really interlocked. */ | |
386 | #define hilo_interlocks \ | |
387 | (mips_opts.isa == ISA_MIPS32 \ | |
388 | || mips_opts.isa == ISA_MIPS32R2 \ | |
389 | || mips_opts.isa == ISA_MIPS64 \ | |
390 | || mips_opts.isa == ISA_MIPS64R2 \ | |
391 | || mips_opts.arch == CPU_R4010 \ | |
392 | || mips_opts.arch == CPU_R10000 \ | |
393 | || mips_opts.arch == CPU_R12000 \ | |
394 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
395 | || mips_opts.arch == CPU_VR5500 \ |
396 | ) | |
252b5132 RH |
397 | |
398 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
399 | from the GPRs after they are loaded from memory, and thus does not |
400 | require nops to be inserted. This applies to instructions marked | |
401 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
402 | level I. */ | |
252b5132 | 403 | #define gpr_interlocks \ |
e7af610e | 404 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 405 | || mips_opts.arch == CPU_R3900) |
252b5132 | 406 | |
81912461 ILT |
407 | /* Whether the processor uses hardware interlocks to avoid delays |
408 | required by coprocessor instructions, and thus does not require | |
409 | nops to be inserted. This applies to instructions marked | |
410 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
411 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
412 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
413 | levels I, II, and III. */ | |
bdaaa2e1 | 414 | /* Itbl support may require additional care here. */ |
81912461 ILT |
415 | #define cop_interlocks \ |
416 | ((mips_opts.isa != ISA_MIPS1 \ | |
417 | && mips_opts.isa != ISA_MIPS2 \ | |
418 | && mips_opts.isa != ISA_MIPS3) \ | |
419 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
420 | ) |
421 | ||
422 | /* Whether the processor uses hardware interlocks to protect reads | |
423 | from coprocessor registers after they are loaded from memory, and | |
424 | thus does not require nops to be inserted. This applies to | |
425 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
426 | requires at MIPS ISA level I. */ | |
427 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 428 | |
6b76fefe CM |
429 | /* Is this a mfhi or mflo instruction? */ |
430 | #define MF_HILO_INSN(PINFO) \ | |
431 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
432 | ||
252b5132 RH |
433 | /* MIPS PIC level. */ |
434 | ||
a161fe53 | 435 | enum mips_pic_level mips_pic; |
252b5132 | 436 | |
c9914766 | 437 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 438 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 439 | static int mips_big_got = 0; |
252b5132 RH |
440 | |
441 | /* 1 if trap instructions should used for overflow rather than break | |
442 | instructions. */ | |
c9914766 | 443 | static int mips_trap = 0; |
252b5132 | 444 | |
119d663a | 445 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 446 | by assembling two single width halves into two single width floating |
119d663a NC |
447 | point registers which just happen to alias the double width destination |
448 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 449 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
450 | automatically at assemble time. */ |
451 | static int mips_disable_float_construction; | |
452 | ||
252b5132 RH |
453 | /* Non-zero if any .set noreorder directives were used. */ |
454 | ||
455 | static int mips_any_noreorder; | |
456 | ||
6b76fefe CM |
457 | /* Non-zero if nops should be inserted when the register referenced in |
458 | an mfhi/mflo instruction is read in the next two instructions. */ | |
459 | static int mips_7000_hilo_fix; | |
460 | ||
252b5132 | 461 | /* The size of the small data section. */ |
156c2f8b | 462 | static unsigned int g_switch_value = 8; |
252b5132 RH |
463 | /* Whether the -G option was used. */ |
464 | static int g_switch_seen = 0; | |
465 | ||
466 | #define N_RMASK 0xc4 | |
467 | #define N_VFP 0xd4 | |
468 | ||
469 | /* If we can determine in advance that GP optimization won't be | |
470 | possible, we can skip the relaxation stuff that tries to produce | |
471 | GP-relative references. This makes delay slot optimization work | |
472 | better. | |
473 | ||
474 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
475 | gcc output. It needs to guess right for gcc, otherwise gcc |
476 | will put what it thinks is a GP-relative instruction in a branch | |
477 | delay slot. | |
252b5132 RH |
478 | |
479 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
480 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 481 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
482 | |
483 | /* handle of the OPCODE hash table */ | |
484 | static struct hash_control *op_hash = NULL; | |
485 | ||
486 | /* The opcode hash table we use for the mips16. */ | |
487 | static struct hash_control *mips16_op_hash = NULL; | |
488 | ||
489 | /* This array holds the chars that always start a comment. If the | |
490 | pre-processor is disabled, these aren't very useful */ | |
491 | const char comment_chars[] = "#"; | |
492 | ||
493 | /* This array holds the chars that only start a comment at the beginning of | |
494 | a line. If the line seems to have the form '# 123 filename' | |
495 | .line and .file directives will appear in the pre-processed output */ | |
496 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
497 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 498 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
499 | /* Also note that C style comments are always supported. */ |
500 | const char line_comment_chars[] = "#"; | |
501 | ||
bdaaa2e1 | 502 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 RH |
504 | |
505 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
506 | const char EXP_CHARS[] = "eE"; | |
507 | ||
508 | /* Chars that mean this number is a floating point constant */ | |
509 | /* As in 0f12.456 */ | |
510 | /* or 0d1.2345e12 */ | |
511 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
512 | ||
513 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
514 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
515 | but nothing is ideal around here. | |
516 | */ | |
517 | ||
518 | static char *insn_error; | |
519 | ||
520 | static int auto_align = 1; | |
521 | ||
522 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
523 | offset in the stack frame from which to restore the $gp register. | |
524 | This is set by the .cprestore pseudo-op, and saved in this | |
525 | variable. */ | |
526 | static offsetT mips_cprestore_offset = -1; | |
527 | ||
67c1ffbe | 528 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 529 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 530 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
531 | static offsetT mips_cpreturn_offset = -1; |
532 | static int mips_cpreturn_register = -1; | |
533 | static int mips_gp_register = GP; | |
def2e0dd | 534 | static int mips_gprel_offset = 0; |
6478892d | 535 | |
7a621144 DJ |
536 | /* Whether mips_cprestore_offset has been set in the current function |
537 | (or whether it has already been warned about, if not). */ | |
538 | static int mips_cprestore_valid = 0; | |
539 | ||
252b5132 RH |
540 | /* This is the register which holds the stack frame, as set by the |
541 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
542 | static int mips_frame_reg = SP; | |
543 | ||
7a621144 DJ |
544 | /* Whether mips_frame_reg has been set in the current function |
545 | (or whether it has already been warned about, if not). */ | |
546 | static int mips_frame_reg_valid = 0; | |
547 | ||
252b5132 RH |
548 | /* To output NOP instructions correctly, we need to keep information |
549 | about the previous two instructions. */ | |
550 | ||
551 | /* Whether we are optimizing. The default value of 2 means to remove | |
552 | unneeded NOPs and swap branch instructions when possible. A value | |
553 | of 1 means to not swap branches. A value of 0 means to always | |
554 | insert NOPs. */ | |
555 | static int mips_optimize = 2; | |
556 | ||
557 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
558 | equivalent to seeing no -g option at all. */ | |
559 | static int mips_debug = 0; | |
560 | ||
7d8e00cf RS |
561 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
562 | #define MAX_VR4130_NOPS 4 | |
563 | ||
564 | /* The maximum number of NOPs needed to fill delay slots. */ | |
565 | #define MAX_DELAY_NOPS 2 | |
566 | ||
567 | /* The maximum number of NOPs needed for any purpose. */ | |
568 | #define MAX_NOPS 4 | |
71400594 RS |
569 | |
570 | /* A list of previous instructions, with index 0 being the most recent. | |
571 | We need to look back MAX_NOPS instructions when filling delay slots | |
572 | or working around processor errata. We need to look back one | |
573 | instruction further if we're thinking about using history[0] to | |
574 | fill a branch delay slot. */ | |
575 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 576 | |
1e915849 RS |
577 | /* Nop instructions used by emit_nop. */ |
578 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
579 | ||
580 | /* The appropriate nop for the current mode. */ | |
581 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 582 | |
252b5132 RH |
583 | /* If this is set, it points to a frag holding nop instructions which |
584 | were inserted before the start of a noreorder section. If those | |
585 | nops turn out to be unnecessary, the size of the frag can be | |
586 | decreased. */ | |
587 | static fragS *prev_nop_frag; | |
588 | ||
589 | /* The number of nop instructions we created in prev_nop_frag. */ | |
590 | static int prev_nop_frag_holds; | |
591 | ||
592 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 593 | prev_nop_frag. */ |
252b5132 RH |
594 | static int prev_nop_frag_required; |
595 | ||
596 | /* The number of instructions we've seen since prev_nop_frag. */ | |
597 | static int prev_nop_frag_since; | |
598 | ||
599 | /* For ECOFF and ELF, relocations against symbols are done in two | |
600 | parts, with a HI relocation and a LO relocation. Each relocation | |
601 | has only 16 bits of space to store an addend. This means that in | |
602 | order for the linker to handle carries correctly, it must be able | |
603 | to locate both the HI and the LO relocation. This means that the | |
604 | relocations must appear in order in the relocation table. | |
605 | ||
606 | In order to implement this, we keep track of each unmatched HI | |
607 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 608 | corresponding LO relocation. */ |
252b5132 | 609 | |
e972090a NC |
610 | struct mips_hi_fixup |
611 | { | |
252b5132 RH |
612 | /* Next HI fixup. */ |
613 | struct mips_hi_fixup *next; | |
614 | /* This fixup. */ | |
615 | fixS *fixp; | |
616 | /* The section this fixup is in. */ | |
617 | segT seg; | |
618 | }; | |
619 | ||
620 | /* The list of unmatched HI relocs. */ | |
621 | ||
622 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
623 | ||
64bdfcaf RS |
624 | /* The frag containing the last explicit relocation operator. |
625 | Null if explicit relocations have not been used. */ | |
626 | ||
627 | static fragS *prev_reloc_op_frag; | |
628 | ||
252b5132 RH |
629 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
630 | ||
631 | #define X ILLEGAL_REG | |
e972090a NC |
632 | static const int mips32_to_16_reg_map[] = |
633 | { | |
252b5132 RH |
634 | X, X, 2, 3, 4, 5, 6, 7, |
635 | X, X, X, X, X, X, X, X, | |
636 | 0, 1, X, X, X, X, X, X, | |
637 | X, X, X, X, X, X, X, X | |
638 | }; | |
639 | #undef X | |
640 | ||
641 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
642 | ||
e972090a NC |
643 | static const unsigned int mips16_to_32_reg_map[] = |
644 | { | |
252b5132 RH |
645 | 16, 17, 2, 3, 4, 5, 6, 7 |
646 | }; | |
60b63b72 | 647 | |
71400594 RS |
648 | /* Classifies the kind of instructions we're interested in when |
649 | implementing -mfix-vr4120. */ | |
650 | enum fix_vr4120_class { | |
651 | FIX_VR4120_MACC, | |
652 | FIX_VR4120_DMACC, | |
653 | FIX_VR4120_MULT, | |
654 | FIX_VR4120_DMULT, | |
655 | FIX_VR4120_DIV, | |
656 | FIX_VR4120_MTHILO, | |
657 | NUM_FIX_VR4120_CLASSES | |
658 | }; | |
659 | ||
660 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
661 | there must be at least one other instruction between an instruction | |
662 | of type X and an instruction of type Y. */ | |
663 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
664 | ||
665 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 666 | static int mips_fix_vr4120; |
4a6a3df4 | 667 | |
7d8e00cf RS |
668 | /* ...likewise -mfix-vr4130. */ |
669 | static int mips_fix_vr4130; | |
670 | ||
4a6a3df4 AO |
671 | /* We don't relax branches by default, since this causes us to expand |
672 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
673 | fail to compute the offset before expanding the macro to the most | |
674 | efficient expansion. */ | |
675 | ||
676 | static int mips_relax_branch; | |
252b5132 | 677 | \f |
4d7206a2 RS |
678 | /* The expansion of many macros depends on the type of symbol that |
679 | they refer to. For example, when generating position-dependent code, | |
680 | a macro that refers to a symbol may have two different expansions, | |
681 | one which uses GP-relative addresses and one which uses absolute | |
682 | addresses. When generating SVR4-style PIC, a macro may have | |
683 | different expansions for local and global symbols. | |
684 | ||
685 | We handle these situations by generating both sequences and putting | |
686 | them in variant frags. In position-dependent code, the first sequence | |
687 | will be the GP-relative one and the second sequence will be the | |
688 | absolute one. In SVR4 PIC, the first sequence will be for global | |
689 | symbols and the second will be for local symbols. | |
690 | ||
584892a6 RS |
691 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
692 | SECOND are the lengths of the two sequences in bytes. These fields | |
693 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
694 | the subtype has the following flags: | |
4d7206a2 | 695 | |
584892a6 RS |
696 | RELAX_USE_SECOND |
697 | Set if it has been decided that we should use the second | |
698 | sequence instead of the first. | |
699 | ||
700 | RELAX_SECOND_LONGER | |
701 | Set in the first variant frag if the macro's second implementation | |
702 | is longer than its first. This refers to the macro as a whole, | |
703 | not an individual relaxation. | |
704 | ||
705 | RELAX_NOMACRO | |
706 | Set in the first variant frag if the macro appeared in a .set nomacro | |
707 | block and if one alternative requires a warning but the other does not. | |
708 | ||
709 | RELAX_DELAY_SLOT | |
710 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
711 | delay slot. | |
4d7206a2 RS |
712 | |
713 | The frag's "opcode" points to the first fixup for relaxable code. | |
714 | ||
715 | Relaxable macros are generated using a sequence such as: | |
716 | ||
717 | relax_start (SYMBOL); | |
718 | ... generate first expansion ... | |
719 | relax_switch (); | |
720 | ... generate second expansion ... | |
721 | relax_end (); | |
722 | ||
723 | The code and fixups for the unwanted alternative are discarded | |
724 | by md_convert_frag. */ | |
584892a6 | 725 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 726 | |
584892a6 RS |
727 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
728 | #define RELAX_SECOND(X) ((X) & 0xff) | |
729 | #define RELAX_USE_SECOND 0x10000 | |
730 | #define RELAX_SECOND_LONGER 0x20000 | |
731 | #define RELAX_NOMACRO 0x40000 | |
732 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 733 | |
4a6a3df4 AO |
734 | /* Branch without likely bit. If label is out of range, we turn: |
735 | ||
736 | beq reg1, reg2, label | |
737 | delay slot | |
738 | ||
739 | into | |
740 | ||
741 | bne reg1, reg2, 0f | |
742 | nop | |
743 | j label | |
744 | 0: delay slot | |
745 | ||
746 | with the following opcode replacements: | |
747 | ||
748 | beq <-> bne | |
749 | blez <-> bgtz | |
750 | bltz <-> bgez | |
751 | bc1f <-> bc1t | |
752 | ||
753 | bltzal <-> bgezal (with jal label instead of j label) | |
754 | ||
755 | Even though keeping the delay slot instruction in the delay slot of | |
756 | the branch would be more efficient, it would be very tricky to do | |
757 | correctly, because we'd have to introduce a variable frag *after* | |
758 | the delay slot instruction, and expand that instead. Let's do it | |
759 | the easy way for now, even if the branch-not-taken case now costs | |
760 | one additional instruction. Out-of-range branches are not supposed | |
761 | to be common, anyway. | |
762 | ||
763 | Branch likely. If label is out of range, we turn: | |
764 | ||
765 | beql reg1, reg2, label | |
766 | delay slot (annulled if branch not taken) | |
767 | ||
768 | into | |
769 | ||
770 | beql reg1, reg2, 1f | |
771 | nop | |
772 | beql $0, $0, 2f | |
773 | nop | |
774 | 1: j[al] label | |
775 | delay slot (executed only if branch taken) | |
776 | 2: | |
777 | ||
778 | It would be possible to generate a shorter sequence by losing the | |
779 | likely bit, generating something like: | |
b34976b6 | 780 | |
4a6a3df4 AO |
781 | bne reg1, reg2, 0f |
782 | nop | |
783 | j[al] label | |
784 | delay slot (executed only if branch taken) | |
785 | 0: | |
786 | ||
787 | beql -> bne | |
788 | bnel -> beq | |
789 | blezl -> bgtz | |
790 | bgtzl -> blez | |
791 | bltzl -> bgez | |
792 | bgezl -> bltz | |
793 | bc1fl -> bc1t | |
794 | bc1tl -> bc1f | |
795 | ||
796 | bltzall -> bgezal (with jal label instead of j label) | |
797 | bgezall -> bltzal (ditto) | |
798 | ||
799 | ||
800 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 801 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
802 | ((relax_substateT) \ |
803 | (0xc0000000 \ | |
804 | | ((toofar) ? 1 : 0) \ | |
805 | | ((link) ? 2 : 0) \ | |
806 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 807 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 808 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
809 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
810 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
811 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 812 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 813 | |
252b5132 RH |
814 | /* For mips16 code, we use an entirely different form of relaxation. |
815 | mips16 supports two versions of most instructions which take | |
816 | immediate values: a small one which takes some small value, and a | |
817 | larger one which takes a 16 bit value. Since branches also follow | |
818 | this pattern, relaxing these values is required. | |
819 | ||
820 | We can assemble both mips16 and normal MIPS code in a single | |
821 | object. Therefore, we need to support this type of relaxation at | |
822 | the same time that we support the relaxation described above. We | |
823 | use the high bit of the subtype field to distinguish these cases. | |
824 | ||
825 | The information we store for this type of relaxation is the | |
826 | argument code found in the opcode file for this relocation, whether | |
827 | the user explicitly requested a small or extended form, and whether | |
828 | the relocation is in a jump or jal delay slot. That tells us the | |
829 | size of the value, and how it should be stored. We also store | |
830 | whether the fragment is considered to be extended or not. We also | |
831 | store whether this is known to be a branch to a different section, | |
832 | whether we have tried to relax this frag yet, and whether we have | |
833 | ever extended a PC relative fragment because of a shift count. */ | |
834 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
835 | (0x80000000 \ | |
836 | | ((type) & 0xff) \ | |
837 | | ((small) ? 0x100 : 0) \ | |
838 | | ((ext) ? 0x200 : 0) \ | |
839 | | ((dslot) ? 0x400 : 0) \ | |
840 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 841 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
842 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
843 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
844 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
845 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
846 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
847 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
848 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
849 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
850 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
851 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
852 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
853 | |
854 | /* Is the given value a sign-extended 32-bit value? */ | |
855 | #define IS_SEXT_32BIT_NUM(x) \ | |
856 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
857 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
858 | ||
859 | /* Is the given value a sign-extended 16-bit value? */ | |
860 | #define IS_SEXT_16BIT_NUM(x) \ | |
861 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
862 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
863 | ||
2051e8c4 MR |
864 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
865 | #define IS_ZEXT_32BIT_NUM(x) \ | |
866 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
867 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
868 | ||
bf12938e RS |
869 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
870 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
871 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
872 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
873 | | (((VALUE) & (MASK)) << (SHIFT))) | |
874 | ||
875 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
876 | SHIFT places. */ | |
877 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
878 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
879 | ||
880 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
881 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
882 | ||
883 | include/opcode/mips.h specifies operand fields using the macros | |
884 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
885 | with "MIPS16OP" instead of "OP". */ | |
886 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
887 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
888 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
889 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
890 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
891 | ||
892 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
893 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
894 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
895 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
896 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
897 | MIPS16OP_MASK_##FIELD, \ | |
898 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
899 | \f |
900 | /* Global variables used when generating relaxable macros. See the | |
901 | comment above RELAX_ENCODE for more details about how relaxation | |
902 | is used. */ | |
903 | static struct { | |
904 | /* 0 if we're not emitting a relaxable macro. | |
905 | 1 if we're emitting the first of the two relaxation alternatives. | |
906 | 2 if we're emitting the second alternative. */ | |
907 | int sequence; | |
908 | ||
909 | /* The first relaxable fixup in the current frag. (In other words, | |
910 | the first fixup that refers to relaxable code.) */ | |
911 | fixS *first_fixup; | |
912 | ||
913 | /* sizes[0] says how many bytes of the first alternative are stored in | |
914 | the current frag. Likewise sizes[1] for the second alternative. */ | |
915 | unsigned int sizes[2]; | |
916 | ||
917 | /* The symbol on which the choice of sequence depends. */ | |
918 | symbolS *symbol; | |
919 | } mips_relax; | |
252b5132 | 920 | \f |
584892a6 RS |
921 | /* Global variables used to decide whether a macro needs a warning. */ |
922 | static struct { | |
923 | /* True if the macro is in a branch delay slot. */ | |
924 | bfd_boolean delay_slot_p; | |
925 | ||
926 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
927 | in bytes and sizes[1] is the length of the second alternative. | |
928 | For non-relaxable macros, both elements give the length of the | |
929 | macro in bytes. */ | |
930 | unsigned int sizes[2]; | |
931 | ||
932 | /* The first variant frag for this macro. */ | |
933 | fragS *first_frag; | |
934 | } mips_macro_warning; | |
935 | \f | |
252b5132 RH |
936 | /* Prototypes for static functions. */ |
937 | ||
17a2f251 | 938 | #define internalError() \ |
252b5132 | 939 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
940 | |
941 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
942 | ||
b34976b6 | 943 | static void append_insn |
4d7206a2 | 944 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 945 | static void mips_no_prev_insn (void); |
b34976b6 | 946 | static void mips16_macro_build |
67c0d1eb RS |
947 | (expressionS *, const char *, const char *, va_list); |
948 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
949 | static void macro_start (void); |
950 | static void macro_end (void); | |
17a2f251 TS |
951 | static void macro (struct mips_cl_insn * ip); |
952 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 953 | #ifdef LOSING_COMPILER |
17a2f251 | 954 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 955 | #endif |
17a2f251 TS |
956 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
957 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 958 | static void mips16_immed |
17a2f251 TS |
959 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
960 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 961 | static size_t my_getSmallExpression |
17a2f251 TS |
962 | (expressionS *, bfd_reloc_code_real_type *, char *); |
963 | static void my_getExpression (expressionS *, char *); | |
964 | static void s_align (int); | |
965 | static void s_change_sec (int); | |
966 | static void s_change_section (int); | |
967 | static void s_cons (int); | |
968 | static void s_float_cons (int); | |
969 | static void s_mips_globl (int); | |
970 | static void s_option (int); | |
971 | static void s_mipsset (int); | |
972 | static void s_abicalls (int); | |
973 | static void s_cpload (int); | |
974 | static void s_cpsetup (int); | |
975 | static void s_cplocal (int); | |
976 | static void s_cprestore (int); | |
977 | static void s_cpreturn (int); | |
978 | static void s_gpvalue (int); | |
979 | static void s_gpword (int); | |
980 | static void s_gpdword (int); | |
981 | static void s_cpadd (int); | |
982 | static void s_insn (int); | |
983 | static void md_obj_begin (void); | |
984 | static void md_obj_end (void); | |
985 | static void s_mips_ent (int); | |
986 | static void s_mips_end (int); | |
987 | static void s_mips_frame (int); | |
988 | static void s_mips_mask (int reg_type); | |
989 | static void s_mips_stab (int); | |
990 | static void s_mips_weakext (int); | |
991 | static void s_mips_file (int); | |
992 | static void s_mips_loc (int); | |
993 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 994 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 995 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
996 | |
997 | /* Table and functions used to map between CPU/ISA names, and | |
998 | ISA levels, and CPU numbers. */ | |
999 | ||
e972090a NC |
1000 | struct mips_cpu_info |
1001 | { | |
e7af610e NC |
1002 | const char *name; /* CPU or ISA name. */ |
1003 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
1004 | int isa; /* ISA level. */ | |
1005 | int cpu; /* CPU number (default CPU if ISA). */ | |
1006 | }; | |
1007 | ||
17a2f251 TS |
1008 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1009 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1010 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1011 | \f |
1012 | /* Pseudo-op table. | |
1013 | ||
1014 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1015 | should be defined here, but are currently unsupported: .alias, | |
1016 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1017 | ||
1018 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1019 | specific to the type of debugging information being generated, and | |
1020 | should be defined by the object format: .aent, .begin, .bend, | |
1021 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1022 | .vreg. | |
1023 | ||
1024 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1025 | not MIPS CPU specific, but are also not specific to the object file | |
1026 | format. This file is probably the best place to define them, but | |
1027 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1028 | .struct. */ | |
1029 | ||
e972090a NC |
1030 | static const pseudo_typeS mips_pseudo_table[] = |
1031 | { | |
beae10d5 | 1032 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1033 | {"option", s_option, 0}, |
1034 | {"set", s_mipsset, 0}, | |
1035 | {"rdata", s_change_sec, 'r'}, | |
1036 | {"sdata", s_change_sec, 's'}, | |
1037 | {"livereg", s_ignore, 0}, | |
1038 | {"abicalls", s_abicalls, 0}, | |
1039 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1040 | {"cpsetup", s_cpsetup, 0}, |
1041 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1042 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1043 | {"cpreturn", s_cpreturn, 0}, |
1044 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1045 | {"gpword", s_gpword, 0}, |
10181a0d | 1046 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1047 | {"cpadd", s_cpadd, 0}, |
1048 | {"insn", s_insn, 0}, | |
1049 | ||
beae10d5 | 1050 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1051 | chips. */ |
1052 | {"asciiz", stringer, 1}, | |
1053 | {"bss", s_change_sec, 'b'}, | |
1054 | {"err", s_err, 0}, | |
1055 | {"half", s_cons, 1}, | |
1056 | {"dword", s_cons, 3}, | |
1057 | {"weakext", s_mips_weakext, 0}, | |
1058 | ||
beae10d5 | 1059 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1060 | here for one reason or another. */ |
1061 | {"align", s_align, 0}, | |
1062 | {"byte", s_cons, 0}, | |
1063 | {"data", s_change_sec, 'd'}, | |
1064 | {"double", s_float_cons, 'd'}, | |
1065 | {"float", s_float_cons, 'f'}, | |
1066 | {"globl", s_mips_globl, 0}, | |
1067 | {"global", s_mips_globl, 0}, | |
1068 | {"hword", s_cons, 1}, | |
1069 | {"int", s_cons, 2}, | |
1070 | {"long", s_cons, 2}, | |
1071 | {"octa", s_cons, 4}, | |
1072 | {"quad", s_cons, 3}, | |
cca86cc8 | 1073 | {"section", s_change_section, 0}, |
252b5132 RH |
1074 | {"short", s_cons, 1}, |
1075 | {"single", s_float_cons, 'f'}, | |
1076 | {"stabn", s_mips_stab, 'n'}, | |
1077 | {"text", s_change_sec, 't'}, | |
1078 | {"word", s_cons, 2}, | |
add56521 | 1079 | |
add56521 | 1080 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1081 | |
43841e91 | 1082 | { NULL, NULL, 0 }, |
252b5132 RH |
1083 | }; |
1084 | ||
e972090a NC |
1085 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1086 | { | |
beae10d5 KH |
1087 | /* These pseudo-ops should be defined by the object file format. |
1088 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1089 | {"aent", s_mips_ent, 1}, |
1090 | {"bgnb", s_ignore, 0}, | |
1091 | {"end", s_mips_end, 0}, | |
1092 | {"endb", s_ignore, 0}, | |
1093 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1094 | {"file", s_mips_file, 0}, |
252b5132 RH |
1095 | {"fmask", s_mips_mask, 'F'}, |
1096 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1097 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1098 | {"mask", s_mips_mask, 'R'}, |
1099 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1100 | { NULL, NULL, 0 }, |
252b5132 RH |
1101 | }; |
1102 | ||
17a2f251 | 1103 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1104 | |
1105 | void | |
17a2f251 | 1106 | mips_pop_insert (void) |
252b5132 RH |
1107 | { |
1108 | pop_insert (mips_pseudo_table); | |
1109 | if (! ECOFF_DEBUGGING) | |
1110 | pop_insert (mips_nonecoff_pseudo_table); | |
1111 | } | |
1112 | \f | |
1113 | /* Symbols labelling the current insn. */ | |
1114 | ||
e972090a NC |
1115 | struct insn_label_list |
1116 | { | |
252b5132 RH |
1117 | struct insn_label_list *next; |
1118 | symbolS *label; | |
1119 | }; | |
1120 | ||
1121 | static struct insn_label_list *insn_labels; | |
1122 | static struct insn_label_list *free_insn_labels; | |
1123 | ||
17a2f251 | 1124 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1125 | |
1126 | static inline void | |
17a2f251 | 1127 | mips_clear_insn_labels (void) |
252b5132 RH |
1128 | { |
1129 | register struct insn_label_list **pl; | |
1130 | ||
1131 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1132 | ; | |
1133 | *pl = insn_labels; | |
1134 | insn_labels = NULL; | |
1135 | } | |
1136 | \f | |
1137 | static char *expr_end; | |
1138 | ||
1139 | /* Expressions which appear in instructions. These are set by | |
1140 | mips_ip. */ | |
1141 | ||
1142 | static expressionS imm_expr; | |
5f74bc13 | 1143 | static expressionS imm2_expr; |
252b5132 RH |
1144 | static expressionS offset_expr; |
1145 | ||
1146 | /* Relocs associated with imm_expr and offset_expr. */ | |
1147 | ||
f6688943 TS |
1148 | static bfd_reloc_code_real_type imm_reloc[3] |
1149 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1150 | static bfd_reloc_code_real_type offset_reloc[3] | |
1151 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1152 | |
252b5132 RH |
1153 | /* These are set by mips16_ip if an explicit extension is used. */ |
1154 | ||
b34976b6 | 1155 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1156 | |
7ed4a06a | 1157 | #ifdef OBJ_ELF |
ecb4347a DJ |
1158 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1159 | ECOFF debugging. */ | |
252b5132 RH |
1160 | |
1161 | static segT pdr_seg; | |
7ed4a06a | 1162 | #endif |
252b5132 | 1163 | |
e013f690 TS |
1164 | /* The default target format to use. */ |
1165 | ||
1166 | const char * | |
17a2f251 | 1167 | mips_target_format (void) |
e013f690 TS |
1168 | { |
1169 | switch (OUTPUT_FLAVOR) | |
1170 | { | |
e013f690 TS |
1171 | case bfd_target_ecoff_flavour: |
1172 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1173 | case bfd_target_coff_flavour: | |
1174 | return "pe-mips"; | |
1175 | case bfd_target_elf_flavour: | |
1176 | #ifdef TE_TMIPS | |
cfe86eaa | 1177 | /* This is traditional mips. */ |
e013f690 | 1178 | return (target_big_endian |
cfe86eaa TS |
1179 | ? (HAVE_64BIT_OBJECTS |
1180 | ? "elf64-tradbigmips" | |
1181 | : (HAVE_NEWABI | |
1182 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1183 | : (HAVE_64BIT_OBJECTS | |
1184 | ? "elf64-tradlittlemips" | |
1185 | : (HAVE_NEWABI | |
1186 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1187 | #else |
1188 | return (target_big_endian | |
cfe86eaa TS |
1189 | ? (HAVE_64BIT_OBJECTS |
1190 | ? "elf64-bigmips" | |
1191 | : (HAVE_NEWABI | |
1192 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1193 | : (HAVE_64BIT_OBJECTS | |
1194 | ? "elf64-littlemips" | |
1195 | : (HAVE_NEWABI | |
1196 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1197 | #endif |
1198 | default: | |
1199 | abort (); | |
1200 | return NULL; | |
1201 | } | |
1202 | } | |
1203 | ||
1e915849 RS |
1204 | /* Return the length of instruction INSN. */ |
1205 | ||
1206 | static inline unsigned int | |
1207 | insn_length (const struct mips_cl_insn *insn) | |
1208 | { | |
1209 | if (!mips_opts.mips16) | |
1210 | return 4; | |
1211 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1212 | } | |
1213 | ||
1214 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1215 | ||
1216 | static void | |
1217 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1218 | { | |
1219 | size_t i; | |
1220 | ||
1221 | insn->insn_mo = mo; | |
1222 | insn->use_extend = FALSE; | |
1223 | insn->extend = 0; | |
1224 | insn->insn_opcode = mo->match; | |
1225 | insn->frag = NULL; | |
1226 | insn->where = 0; | |
1227 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1228 | insn->fixp[i] = NULL; | |
1229 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1230 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1231 | insn->mips16_absolute_jump_p = 0; | |
1232 | } | |
1233 | ||
1234 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1235 | ||
1236 | static void | |
1237 | install_insn (const struct mips_cl_insn *insn) | |
1238 | { | |
1239 | char *f = insn->frag->fr_literal + insn->where; | |
1240 | if (!mips_opts.mips16) | |
1241 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1242 | else if (insn->mips16_absolute_jump_p) | |
1243 | { | |
1244 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1245 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1246 | } | |
1247 | else | |
1248 | { | |
1249 | if (insn->use_extend) | |
1250 | { | |
1251 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1252 | f += 2; | |
1253 | } | |
1254 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1259 | and install the opcode in the new location. */ | |
1260 | ||
1261 | static void | |
1262 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1263 | { | |
1264 | size_t i; | |
1265 | ||
1266 | insn->frag = frag; | |
1267 | insn->where = where; | |
1268 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1269 | if (insn->fixp[i] != NULL) | |
1270 | { | |
1271 | insn->fixp[i]->fx_frag = frag; | |
1272 | insn->fixp[i]->fx_where = where; | |
1273 | } | |
1274 | install_insn (insn); | |
1275 | } | |
1276 | ||
1277 | /* Add INSN to the end of the output. */ | |
1278 | ||
1279 | static void | |
1280 | add_fixed_insn (struct mips_cl_insn *insn) | |
1281 | { | |
1282 | char *f = frag_more (insn_length (insn)); | |
1283 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1284 | } | |
1285 | ||
1286 | /* Start a variant frag and move INSN to the start of the variant part, | |
1287 | marking it as fixed. The other arguments are as for frag_var. */ | |
1288 | ||
1289 | static void | |
1290 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1291 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1292 | { | |
1293 | frag_grow (max_chars); | |
1294 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1295 | insn->fixed_p = 1; | |
1296 | frag_var (rs_machine_dependent, max_chars, var, | |
1297 | subtype, symbol, offset, NULL); | |
1298 | } | |
1299 | ||
1300 | /* Insert N copies of INSN into the history buffer, starting at | |
1301 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1302 | ||
1303 | static void | |
1304 | insert_into_history (unsigned int first, unsigned int n, | |
1305 | const struct mips_cl_insn *insn) | |
1306 | { | |
1307 | if (mips_relax.sequence != 2) | |
1308 | { | |
1309 | unsigned int i; | |
1310 | ||
1311 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1312 | if (i >= first + n) | |
1313 | history[i] = history[i - n]; | |
1314 | else | |
1315 | history[i] = *insn; | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1320 | ||
1321 | static void | |
1322 | emit_nop (void) | |
1323 | { | |
1324 | add_fixed_insn (NOP_INSN); | |
1325 | insert_into_history (0, 1, NOP_INSN); | |
1326 | } | |
1327 | ||
71400594 RS |
1328 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1329 | the idea is to make it obvious at a glance that each errata is | |
1330 | included. */ | |
1331 | ||
1332 | static void | |
1333 | init_vr4120_conflicts (void) | |
1334 | { | |
1335 | #define CONFLICT(FIRST, SECOND) \ | |
1336 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1337 | ||
1338 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1339 | CONFLICT (MACC, DIV); | |
1340 | CONFLICT (DMACC, DIV); | |
1341 | ||
1342 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1343 | CONFLICT (DMULT, DMULT); | |
1344 | CONFLICT (DMULT, DMACC); | |
1345 | CONFLICT (DMACC, DMULT); | |
1346 | CONFLICT (DMACC, DMACC); | |
1347 | ||
1348 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1349 | CONFLICT (MACC, MTHILO); | |
1350 | CONFLICT (DMACC, MTHILO); | |
1351 | ||
1352 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1353 | instruction is executed immediately after a MACC or DMACC | |
1354 | instruction, the result of [either instruction] is incorrect." */ | |
1355 | CONFLICT (MACC, MULT); | |
1356 | CONFLICT (MACC, DMULT); | |
1357 | CONFLICT (DMACC, MULT); | |
1358 | CONFLICT (DMACC, DMULT); | |
1359 | ||
1360 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1361 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1362 | DDIV or DDIVU instruction, the result of the MACC or | |
1363 | DMACC instruction is incorrect.". */ | |
1364 | CONFLICT (DMULT, MACC); | |
1365 | CONFLICT (DMULT, DMACC); | |
1366 | CONFLICT (DIV, MACC); | |
1367 | CONFLICT (DIV, DMACC); | |
1368 | ||
1369 | #undef CONFLICT | |
1370 | } | |
1371 | ||
156c2f8b NC |
1372 | /* This function is called once, at assembler startup time. It should |
1373 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1374 | ||
252b5132 | 1375 | void |
17a2f251 | 1376 | md_begin (void) |
252b5132 | 1377 | { |
252b5132 | 1378 | register const char *retval = NULL; |
156c2f8b | 1379 | int i = 0; |
252b5132 | 1380 | int broken = 0; |
1f25f5d3 | 1381 | |
fef14a42 | 1382 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1383 | as_warn (_("Could not set architecture and machine")); |
1384 | ||
252b5132 RH |
1385 | op_hash = hash_new (); |
1386 | ||
1387 | for (i = 0; i < NUMOPCODES;) | |
1388 | { | |
1389 | const char *name = mips_opcodes[i].name; | |
1390 | ||
17a2f251 | 1391 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1392 | if (retval != NULL) |
1393 | { | |
1394 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1395 | mips_opcodes[i].name, retval); | |
1396 | /* Probably a memory allocation problem? Give up now. */ | |
1397 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1398 | } | |
1399 | do | |
1400 | { | |
1401 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1402 | { | |
1403 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1404 | broken = 1; | |
1e915849 RS |
1405 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1406 | { | |
1407 | create_insn (&nop_insn, mips_opcodes + i); | |
1408 | nop_insn.fixed_p = 1; | |
1409 | } | |
252b5132 RH |
1410 | } |
1411 | ++i; | |
1412 | } | |
1413 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1414 | } | |
1415 | ||
1416 | mips16_op_hash = hash_new (); | |
1417 | ||
1418 | i = 0; | |
1419 | while (i < bfd_mips16_num_opcodes) | |
1420 | { | |
1421 | const char *name = mips16_opcodes[i].name; | |
1422 | ||
17a2f251 | 1423 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1424 | if (retval != NULL) |
1425 | as_fatal (_("internal: can't hash `%s': %s"), | |
1426 | mips16_opcodes[i].name, retval); | |
1427 | do | |
1428 | { | |
1429 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1430 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1431 | != mips16_opcodes[i].match)) | |
1432 | { | |
1433 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1434 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1435 | broken = 1; | |
1436 | } | |
1e915849 RS |
1437 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1438 | { | |
1439 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1440 | mips16_nop_insn.fixed_p = 1; | |
1441 | } | |
252b5132 RH |
1442 | ++i; |
1443 | } | |
1444 | while (i < bfd_mips16_num_opcodes | |
1445 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1446 | } | |
1447 | ||
1448 | if (broken) | |
1449 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1450 | ||
1451 | /* We add all the general register names to the symbol table. This | |
1452 | helps us detect invalid uses of them. */ | |
1453 | for (i = 0; i < 32; i++) | |
1454 | { | |
1455 | char buf[5]; | |
1456 | ||
1457 | sprintf (buf, "$%d", i); | |
1458 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1459 | &zero_address_frag)); | |
1460 | } | |
76db943d TS |
1461 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1462 | &zero_address_frag)); | |
252b5132 RH |
1463 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1464 | &zero_address_frag)); | |
1465 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1466 | &zero_address_frag)); | |
1467 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1468 | &zero_address_frag)); | |
1469 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1470 | &zero_address_frag)); | |
1471 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1472 | &zero_address_frag)); | |
1473 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1474 | &zero_address_frag)); | |
85b51719 TS |
1475 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1476 | &zero_address_frag)); | |
252b5132 RH |
1477 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1478 | &zero_address_frag)); | |
1479 | ||
6047c971 AO |
1480 | /* If we don't add these register names to the symbol table, they |
1481 | may end up being added as regular symbols by operand(), and then | |
1482 | make it to the object file as undefined in case they're not | |
1483 | regarded as local symbols. They're local in o32, since `$' is a | |
1484 | local symbol prefix, but not in n32 or n64. */ | |
1485 | for (i = 0; i < 8; i++) | |
1486 | { | |
1487 | char buf[6]; | |
1488 | ||
1489 | sprintf (buf, "$fcc%i", i); | |
1490 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1491 | &zero_address_frag)); | |
1492 | } | |
1493 | ||
7d10b47d | 1494 | mips_no_prev_insn (); |
252b5132 RH |
1495 | |
1496 | mips_gprmask = 0; | |
1497 | mips_cprmask[0] = 0; | |
1498 | mips_cprmask[1] = 0; | |
1499 | mips_cprmask[2] = 0; | |
1500 | mips_cprmask[3] = 0; | |
1501 | ||
1502 | /* set the default alignment for the text section (2**2) */ | |
1503 | record_alignment (text_section, 2); | |
1504 | ||
4d0d148d | 1505 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1506 | |
1507 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1508 | { | |
1509 | /* On a native system, sections must be aligned to 16 byte | |
1510 | boundaries. When configured for an embedded ELF target, we | |
1511 | don't bother. */ | |
1512 | if (strcmp (TARGET_OS, "elf") != 0) | |
1513 | { | |
1514 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1515 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1516 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1517 | } | |
1518 | ||
1519 | /* Create a .reginfo section for register masks and a .mdebug | |
1520 | section for debugging information. */ | |
1521 | { | |
1522 | segT seg; | |
1523 | subsegT subseg; | |
1524 | flagword flags; | |
1525 | segT sec; | |
1526 | ||
1527 | seg = now_seg; | |
1528 | subseg = now_subseg; | |
1529 | ||
1530 | /* The ABI says this section should be loaded so that the | |
1531 | running program can access it. However, we don't load it | |
1532 | if we are configured for an embedded target */ | |
1533 | flags = SEC_READONLY | SEC_DATA; | |
1534 | if (strcmp (TARGET_OS, "elf") != 0) | |
1535 | flags |= SEC_ALLOC | SEC_LOAD; | |
1536 | ||
316f5878 | 1537 | if (mips_abi != N64_ABI) |
252b5132 RH |
1538 | { |
1539 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1540 | ||
195325d2 TS |
1541 | bfd_set_section_flags (stdoutput, sec, flags); |
1542 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1543 | |
252b5132 RH |
1544 | #ifdef OBJ_ELF |
1545 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1546 | #endif | |
1547 | } | |
1548 | else | |
1549 | { | |
1550 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1551 | .reginfo section. */ | |
1552 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1553 | bfd_set_section_flags (stdoutput, sec, flags); |
1554 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1555 | |
1556 | #ifdef OBJ_ELF | |
1557 | /* Set up the option header. */ | |
1558 | { | |
1559 | Elf_Internal_Options opthdr; | |
1560 | char *f; | |
1561 | ||
1562 | opthdr.kind = ODK_REGINFO; | |
1563 | opthdr.size = (sizeof (Elf_External_Options) | |
1564 | + sizeof (Elf64_External_RegInfo)); | |
1565 | opthdr.section = 0; | |
1566 | opthdr.info = 0; | |
1567 | f = frag_more (sizeof (Elf_External_Options)); | |
1568 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1569 | (Elf_External_Options *) f); | |
1570 | ||
1571 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1572 | } | |
1573 | #endif | |
1574 | } | |
1575 | ||
1576 | if (ECOFF_DEBUGGING) | |
1577 | { | |
1578 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1579 | (void) bfd_set_section_flags (stdoutput, sec, | |
1580 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1581 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1582 | } | |
ecb4347a | 1583 | #ifdef OBJ_ELF |
dcd410fe | 1584 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1585 | { |
1586 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1587 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1588 | SEC_READONLY | SEC_RELOC | |
1589 | | SEC_DEBUGGING); | |
1590 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1591 | } | |
252b5132 RH |
1592 | #endif |
1593 | ||
1594 | subseg_set (seg, subseg); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | if (! ECOFF_DEBUGGING) | |
1599 | md_obj_begin (); | |
71400594 RS |
1600 | |
1601 | if (mips_fix_vr4120) | |
1602 | init_vr4120_conflicts (); | |
252b5132 RH |
1603 | } |
1604 | ||
1605 | void | |
17a2f251 | 1606 | md_mips_end (void) |
252b5132 RH |
1607 | { |
1608 | if (! ECOFF_DEBUGGING) | |
1609 | md_obj_end (); | |
1610 | } | |
1611 | ||
1612 | void | |
17a2f251 | 1613 | md_assemble (char *str) |
252b5132 RH |
1614 | { |
1615 | struct mips_cl_insn insn; | |
f6688943 TS |
1616 | bfd_reloc_code_real_type unused_reloc[3] |
1617 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1618 | |
1619 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1620 | imm2_expr.X_op = O_absent; |
252b5132 | 1621 | offset_expr.X_op = O_absent; |
f6688943 TS |
1622 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1623 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1624 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1625 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1626 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1627 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1628 | |
1629 | if (mips_opts.mips16) | |
1630 | mips16_ip (str, &insn); | |
1631 | else | |
1632 | { | |
1633 | mips_ip (str, &insn); | |
beae10d5 KH |
1634 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1635 | str, insn.insn_opcode)); | |
252b5132 RH |
1636 | } |
1637 | ||
1638 | if (insn_error) | |
1639 | { | |
1640 | as_bad ("%s `%s'", insn_error, str); | |
1641 | return; | |
1642 | } | |
1643 | ||
1644 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1645 | { | |
584892a6 | 1646 | macro_start (); |
252b5132 RH |
1647 | if (mips_opts.mips16) |
1648 | mips16_macro (&insn); | |
1649 | else | |
1650 | macro (&insn); | |
584892a6 | 1651 | macro_end (); |
252b5132 RH |
1652 | } |
1653 | else | |
1654 | { | |
1655 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1656 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1657 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1658 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1659 | else |
4d7206a2 | 1660 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1661 | } |
1662 | } | |
1663 | ||
5919d012 RS |
1664 | /* Return true if the given relocation might need a matching %lo(). |
1665 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1666 | applied to local symbols. */ | |
1667 | ||
1668 | static inline bfd_boolean | |
17a2f251 | 1669 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1670 | { |
3b91255e RS |
1671 | return (HAVE_IN_PLACE_ADDENDS |
1672 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1673 | || reloc == BFD_RELOC_MIPS_GOT16 |
1674 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1675 | } |
1676 | ||
1677 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1678 | relocation. */ | |
1679 | ||
1680 | static inline bfd_boolean | |
17a2f251 | 1681 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1682 | { |
1683 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1684 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1685 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1686 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1687 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1688 | } | |
1689 | ||
252b5132 RH |
1690 | /* See whether instruction IP reads register REG. CLASS is the type |
1691 | of register. */ | |
1692 | ||
1693 | static int | |
71400594 | 1694 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1695 | enum mips_regclass class) |
252b5132 RH |
1696 | { |
1697 | if (class == MIPS16_REG) | |
1698 | { | |
1699 | assert (mips_opts.mips16); | |
1700 | reg = mips16_to_32_reg_map[reg]; | |
1701 | class = MIPS_GR_REG; | |
1702 | } | |
1703 | ||
85b51719 TS |
1704 | /* Don't report on general register ZERO, since it never changes. */ |
1705 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1706 | return 0; |
1707 | ||
1708 | if (class == MIPS_FP_REG) | |
1709 | { | |
1710 | assert (! mips_opts.mips16); | |
1711 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1712 | This is not optimal, because it will introduce an unnecessary | |
1713 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1714 | need to distinguish reading both $f0 and $f1 or just one of | |
1715 | them. Note that we don't have to check the other way, | |
1716 | because there is no instruction that sets both $f0 and $f1 | |
1717 | and requires a delay. */ | |
1718 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1719 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1720 | == (reg &~ (unsigned) 1))) |
1721 | return 1; | |
1722 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1723 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1724 | == (reg &~ (unsigned) 1))) |
1725 | return 1; | |
1726 | } | |
1727 | else if (! mips_opts.mips16) | |
1728 | { | |
1729 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1730 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1731 | return 1; |
1732 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1733 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1734 | return 1; |
1735 | } | |
1736 | else | |
1737 | { | |
1738 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1739 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1740 | return 1; |
1741 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1742 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1743 | return 1; |
1744 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1745 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1746 | == reg)) |
1747 | return 1; | |
1748 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1749 | return 1; | |
1750 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1751 | return 1; | |
1752 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1753 | return 1; | |
1754 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1755 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1756 | return 1; |
1757 | } | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | /* This function returns true if modifying a register requires a | |
1763 | delay. */ | |
1764 | ||
1765 | static int | |
17a2f251 | 1766 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1767 | { |
1768 | unsigned long prev_pinfo; | |
1769 | ||
47e39b9d | 1770 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1771 | if (! mips_opts.noreorder |
81912461 ILT |
1772 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1773 | && ! gpr_interlocks) | |
1774 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1775 | && ! cop_interlocks))) | |
252b5132 | 1776 | { |
81912461 ILT |
1777 | /* A load from a coprocessor or from memory. All load delays |
1778 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1779 | /* Itbl support may require additional care here. */ |
252b5132 | 1780 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1781 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1782 | return 1; |
1783 | } | |
1784 | ||
1785 | return 0; | |
1786 | } | |
1787 | ||
404a8071 RS |
1788 | /* Move all labels in insn_labels to the current insertion point. */ |
1789 | ||
1790 | static void | |
1791 | mips_move_labels (void) | |
1792 | { | |
1793 | struct insn_label_list *l; | |
1794 | valueT val; | |
1795 | ||
1796 | for (l = insn_labels; l != NULL; l = l->next) | |
1797 | { | |
1798 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
1799 | symbol_set_frag (l->label, frag_now); | |
1800 | val = (valueT) frag_now_fix (); | |
1801 | /* mips16 text labels are stored as odd. */ | |
1802 | if (mips_opts.mips16) | |
1803 | ++val; | |
1804 | S_SET_VALUE (l->label, val); | |
1805 | } | |
1806 | } | |
1807 | ||
252b5132 RH |
1808 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1809 | handle them specially, such as generating jalx instructions when | |
1810 | needed. We also make them odd for the duration of the assembly, in | |
1811 | order to generate the right sort of code. We will make them even | |
1812 | in the adjust_symtab routine, while leaving them marked. This is | |
1813 | convenient for the debugger and the disassembler. The linker knows | |
1814 | to make them odd again. */ | |
1815 | ||
1816 | static void | |
17a2f251 | 1817 | mips16_mark_labels (void) |
252b5132 RH |
1818 | { |
1819 | if (mips_opts.mips16) | |
1820 | { | |
1821 | struct insn_label_list *l; | |
98aa84af | 1822 | valueT val; |
252b5132 RH |
1823 | |
1824 | for (l = insn_labels; l != NULL; l = l->next) | |
1825 | { | |
1826 | #ifdef OBJ_ELF | |
1827 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1828 | S_SET_OTHER (l->label, STO_MIPS16); | |
1829 | #endif | |
98aa84af AM |
1830 | val = S_GET_VALUE (l->label); |
1831 | if ((val & 1) == 0) | |
1832 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1833 | } |
1834 | } | |
1835 | } | |
1836 | ||
4d7206a2 RS |
1837 | /* End the current frag. Make it a variant frag and record the |
1838 | relaxation info. */ | |
1839 | ||
1840 | static void | |
1841 | relax_close_frag (void) | |
1842 | { | |
584892a6 | 1843 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1844 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1845 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1846 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1847 | ||
1848 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1849 | mips_relax.first_fixup = 0; | |
1850 | } | |
1851 | ||
1852 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1853 | See the comment above RELAX_ENCODE for more details. */ | |
1854 | ||
1855 | static void | |
1856 | relax_start (symbolS *symbol) | |
1857 | { | |
1858 | assert (mips_relax.sequence == 0); | |
1859 | mips_relax.sequence = 1; | |
1860 | mips_relax.symbol = symbol; | |
1861 | } | |
1862 | ||
1863 | /* Start generating the second version of a relaxable sequence. | |
1864 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1865 | |
1866 | static void | |
4d7206a2 RS |
1867 | relax_switch (void) |
1868 | { | |
1869 | assert (mips_relax.sequence == 1); | |
1870 | mips_relax.sequence = 2; | |
1871 | } | |
1872 | ||
1873 | /* End the current relaxable sequence. */ | |
1874 | ||
1875 | static void | |
1876 | relax_end (void) | |
1877 | { | |
1878 | assert (mips_relax.sequence == 2); | |
1879 | relax_close_frag (); | |
1880 | mips_relax.sequence = 0; | |
1881 | } | |
1882 | ||
71400594 RS |
1883 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1884 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1885 | by VR4120 errata. */ | |
4d7206a2 | 1886 | |
71400594 RS |
1887 | static unsigned int |
1888 | classify_vr4120_insn (const char *name) | |
252b5132 | 1889 | { |
71400594 RS |
1890 | if (strncmp (name, "macc", 4) == 0) |
1891 | return FIX_VR4120_MACC; | |
1892 | if (strncmp (name, "dmacc", 5) == 0) | |
1893 | return FIX_VR4120_DMACC; | |
1894 | if (strncmp (name, "mult", 4) == 0) | |
1895 | return FIX_VR4120_MULT; | |
1896 | if (strncmp (name, "dmult", 5) == 0) | |
1897 | return FIX_VR4120_DMULT; | |
1898 | if (strstr (name, "div")) | |
1899 | return FIX_VR4120_DIV; | |
1900 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1901 | return FIX_VR4120_MTHILO; | |
1902 | return NUM_FIX_VR4120_CLASSES; | |
1903 | } | |
252b5132 | 1904 | |
71400594 RS |
1905 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1906 | where INSN1 is the earlier instruction. Return the worst-case value | |
1907 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1908 | |
71400594 RS |
1909 | static unsigned int |
1910 | insns_between (const struct mips_cl_insn *insn1, | |
1911 | const struct mips_cl_insn *insn2) | |
1912 | { | |
1913 | unsigned long pinfo1, pinfo2; | |
1914 | ||
1915 | /* This function needs to know which pinfo flags are set for INSN2 | |
1916 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1917 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1918 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1919 | pinfo1 = insn1->insn_mo->pinfo; | |
1920 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1921 | |
71400594 RS |
1922 | #define INSN2_USES_REG(REG, CLASS) \ |
1923 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1924 | ||
1925 | /* For most targets, write-after-read dependencies on the HI and LO | |
1926 | registers must be separated by at least two instructions. */ | |
1927 | if (!hilo_interlocks) | |
252b5132 | 1928 | { |
71400594 RS |
1929 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1930 | return 2; | |
1931 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1932 | return 2; | |
1933 | } | |
1934 | ||
1935 | /* If we're working around r7000 errata, there must be two instructions | |
1936 | between an mfhi or mflo and any instruction that uses the result. */ | |
1937 | if (mips_7000_hilo_fix | |
1938 | && MF_HILO_INSN (pinfo1) | |
1939 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1940 | return 2; | |
1941 | ||
1942 | /* If working around VR4120 errata, check for combinations that need | |
1943 | a single intervening instruction. */ | |
1944 | if (mips_fix_vr4120) | |
1945 | { | |
1946 | unsigned int class1, class2; | |
252b5132 | 1947 | |
71400594 RS |
1948 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1949 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1950 | { |
71400594 RS |
1951 | if (insn2 == NULL) |
1952 | return 1; | |
1953 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1954 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1955 | return 1; | |
252b5132 | 1956 | } |
71400594 RS |
1957 | } |
1958 | ||
1959 | if (!mips_opts.mips16) | |
1960 | { | |
1961 | /* Check for GPR or coprocessor load delays. All such delays | |
1962 | are on the RT register. */ | |
1963 | /* Itbl support may require additional care here. */ | |
1964 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
1965 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 1966 | { |
71400594 RS |
1967 | know (pinfo1 & INSN_WRITE_GPR_T); |
1968 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
1969 | return 1; | |
1970 | } | |
1971 | ||
1972 | /* Check for generic coprocessor hazards. | |
1973 | ||
1974 | This case is not handled very well. There is no special | |
1975 | knowledge of CP0 handling, and the coprocessors other than | |
1976 | the floating point unit are not distinguished at all. */ | |
1977 | /* Itbl support may require additional care here. FIXME! | |
1978 | Need to modify this to include knowledge about | |
1979 | user specified delays! */ | |
1980 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
1981 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
1982 | { | |
1983 | /* Handle cases where INSN1 writes to a known general coprocessor | |
1984 | register. There must be a one instruction delay before INSN2 | |
1985 | if INSN2 reads that register, otherwise no delay is needed. */ | |
1986 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 1987 | { |
71400594 RS |
1988 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
1989 | return 1; | |
252b5132 | 1990 | } |
71400594 | 1991 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 1992 | { |
71400594 RS |
1993 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
1994 | return 1; | |
252b5132 RH |
1995 | } |
1996 | else | |
1997 | { | |
71400594 RS |
1998 | /* Read-after-write dependencies on the control registers |
1999 | require a two-instruction gap. */ | |
2000 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2001 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2002 | return 2; | |
2003 | ||
2004 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2005 | also a coprocessor instruction, assume there must be | |
2006 | a one instruction gap. */ | |
2007 | if (pinfo2 & INSN_COP) | |
2008 | return 1; | |
252b5132 RH |
2009 | } |
2010 | } | |
6b76fefe | 2011 | |
71400594 RS |
2012 | /* Check for read-after-write dependencies on the coprocessor |
2013 | control registers in cases where INSN1 does not need a general | |
2014 | coprocessor delay. This means that INSN1 is a floating point | |
2015 | comparison instruction. */ | |
2016 | /* Itbl support may require additional care here. */ | |
2017 | else if (!cop_interlocks | |
2018 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2019 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2020 | return 1; | |
2021 | } | |
6b76fefe | 2022 | |
71400594 | 2023 | #undef INSN2_USES_REG |
6b76fefe | 2024 | |
71400594 RS |
2025 | return 0; |
2026 | } | |
6b76fefe | 2027 | |
7d8e00cf RS |
2028 | /* Return the number of nops that would be needed to work around the |
2029 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2030 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2031 | ||
2032 | static int | |
2033 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2034 | const struct mips_cl_insn *insn) | |
2035 | { | |
2036 | int i, j, reg; | |
2037 | ||
2038 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2039 | are not affected by the errata. */ | |
2040 | if (insn != 0 | |
2041 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2042 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2043 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2044 | return 0; | |
2045 | ||
2046 | /* Search for the first MFLO or MFHI. */ | |
2047 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2048 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2049 | { | |
2050 | /* Extract the destination register. */ | |
2051 | if (mips_opts.mips16) | |
2052 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2053 | else | |
2054 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2055 | ||
2056 | /* No nops are needed if INSN reads that register. */ | |
2057 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2058 | return 0; | |
2059 | ||
2060 | /* ...or if any of the intervening instructions do. */ | |
2061 | for (j = 0; j < i; j++) | |
2062 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2063 | return 0; | |
2064 | ||
2065 | return MAX_VR4130_NOPS - i; | |
2066 | } | |
2067 | return 0; | |
2068 | } | |
2069 | ||
71400594 RS |
2070 | /* Return the number of nops that would be needed if instruction INSN |
2071 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2072 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2073 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2074 | |
71400594 RS |
2075 | static int |
2076 | nops_for_insn (const struct mips_cl_insn *history, | |
2077 | const struct mips_cl_insn *insn) | |
2078 | { | |
2079 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2080 | |
71400594 | 2081 | nops = 0; |
7d8e00cf | 2082 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2083 | if (!history[i].noreorder_p) |
2084 | { | |
2085 | tmp_nops = insns_between (history + i, insn) - i; | |
2086 | if (tmp_nops > nops) | |
2087 | nops = tmp_nops; | |
2088 | } | |
7d8e00cf RS |
2089 | |
2090 | if (mips_fix_vr4130) | |
2091 | { | |
2092 | tmp_nops = nops_for_vr4130 (history, insn); | |
2093 | if (tmp_nops > nops) | |
2094 | nops = tmp_nops; | |
2095 | } | |
2096 | ||
71400594 RS |
2097 | return nops; |
2098 | } | |
252b5132 | 2099 | |
71400594 RS |
2100 | /* The variable arguments provide NUM_INSNS extra instructions that |
2101 | might be added to HISTORY. Return the largest number of nops that | |
2102 | would be needed after the extended sequence. */ | |
252b5132 | 2103 | |
71400594 RS |
2104 | static int |
2105 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2106 | { | |
2107 | va_list args; | |
2108 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2109 | struct mips_cl_insn *cursor; | |
2110 | int nops; | |
2111 | ||
2112 | va_start (args, history); | |
2113 | cursor = buffer + num_insns; | |
2114 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2115 | while (cursor > buffer) | |
2116 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2117 | ||
2118 | nops = nops_for_insn (buffer, NULL); | |
2119 | va_end (args); | |
2120 | return nops; | |
2121 | } | |
252b5132 | 2122 | |
71400594 RS |
2123 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2124 | worst-case delay for the branch target. */ | |
252b5132 | 2125 | |
71400594 RS |
2126 | static int |
2127 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2128 | const struct mips_cl_insn *insn) | |
2129 | { | |
2130 | int nops, tmp_nops; | |
60b63b72 | 2131 | |
71400594 RS |
2132 | nops = nops_for_insn (history, insn); |
2133 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2134 | | INSN_COND_BRANCH_DELAY | |
2135 | | INSN_COND_BRANCH_LIKELY)) | |
2136 | { | |
2137 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2138 | if (tmp_nops > nops) | |
2139 | nops = tmp_nops; | |
2140 | } | |
2141 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2142 | { | |
2143 | tmp_nops = nops_for_sequence (1, history, insn); | |
2144 | if (tmp_nops > nops) | |
2145 | nops = tmp_nops; | |
2146 | } | |
2147 | return nops; | |
2148 | } | |
2149 | ||
2150 | /* Output an instruction. IP is the instruction information. | |
2151 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2152 | RELOC_TYPE. */ | |
2153 | ||
2154 | static void | |
2155 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2156 | bfd_reloc_code_real_type *reloc_type) | |
2157 | { | |
2158 | register unsigned long prev_pinfo, pinfo; | |
2159 | relax_stateT prev_insn_frag_type = 0; | |
2160 | bfd_boolean relaxed_branch = FALSE; | |
2161 | ||
2162 | /* Mark instruction labels in mips16 mode. */ | |
2163 | mips16_mark_labels (); | |
2164 | ||
2165 | prev_pinfo = history[0].insn_mo->pinfo; | |
2166 | pinfo = ip->insn_mo->pinfo; | |
2167 | ||
2168 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2169 | { | |
2170 | /* There are a lot of optimizations we could do that we don't. | |
2171 | In particular, we do not, in general, reorder instructions. | |
2172 | If you use gcc with optimization, it will reorder | |
2173 | instructions and generally do much more optimization then we | |
2174 | do here; repeating all that work in the assembler would only | |
2175 | benefit hand written assembly code, and does not seem worth | |
2176 | it. */ | |
2177 | int nops = (mips_optimize == 0 | |
2178 | ? nops_for_insn (history, NULL) | |
2179 | : nops_for_insn_or_target (history, ip)); | |
2180 | if (nops > 0) | |
252b5132 RH |
2181 | { |
2182 | fragS *old_frag; | |
2183 | unsigned long old_frag_offset; | |
2184 | int i; | |
252b5132 RH |
2185 | |
2186 | old_frag = frag_now; | |
2187 | old_frag_offset = frag_now_fix (); | |
2188 | ||
2189 | for (i = 0; i < nops; i++) | |
2190 | emit_nop (); | |
2191 | ||
2192 | if (listing) | |
2193 | { | |
2194 | listing_prev_line (); | |
2195 | /* We may be at the start of a variant frag. In case we | |
2196 | are, make sure there is enough space for the frag | |
2197 | after the frags created by listing_prev_line. The | |
2198 | argument to frag_grow here must be at least as large | |
2199 | as the argument to all other calls to frag_grow in | |
2200 | this file. We don't have to worry about being in the | |
2201 | middle of a variant frag, because the variants insert | |
2202 | all needed nop instructions themselves. */ | |
2203 | frag_grow (40); | |
2204 | } | |
2205 | ||
404a8071 | 2206 | mips_move_labels (); |
252b5132 RH |
2207 | |
2208 | #ifndef NO_ECOFF_DEBUGGING | |
2209 | if (ECOFF_DEBUGGING) | |
2210 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2211 | #endif | |
2212 | } | |
71400594 RS |
2213 | } |
2214 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2215 | { | |
2216 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2217 | int nops = nops_for_insn_or_target (history, ip); | |
2218 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2219 | |
71400594 RS |
2220 | /* Enforce NOPS as a minimum. */ |
2221 | if (nops > prev_nop_frag_required) | |
2222 | prev_nop_frag_required = nops; | |
252b5132 | 2223 | |
71400594 RS |
2224 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2225 | { | |
2226 | /* Settle for the current number of nops. Update the history | |
2227 | accordingly (for the benefit of any future .set reorder code). */ | |
2228 | prev_nop_frag = NULL; | |
2229 | insert_into_history (prev_nop_frag_since, | |
2230 | prev_nop_frag_holds, NOP_INSN); | |
2231 | } | |
2232 | else | |
2233 | { | |
2234 | /* Allow this instruction to replace one of the nops that was | |
2235 | tentatively added to prev_nop_frag. */ | |
2236 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2237 | prev_nop_frag_holds--; | |
2238 | prev_nop_frag_since++; | |
252b5132 RH |
2239 | } |
2240 | } | |
2241 | ||
58e2ea4d MR |
2242 | #ifdef OBJ_ELF |
2243 | /* The value passed to dwarf2_emit_insn is the distance between | |
2244 | the beginning of the current instruction and the address that | |
2245 | should be recorded in the debug tables. For MIPS16 debug info | |
2246 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2247 | address higher by one than the current. */ | |
2248 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2249 | #endif | |
2250 | ||
895921c9 | 2251 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2252 | if (history[0].frag) |
2253 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2254 | |
4d7206a2 | 2255 | if (address_expr |
0b25d3e6 | 2256 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2257 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2258 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2259 | && mips_relax_branch | |
2260 | /* Don't try branch relaxation within .set nomacro, or within | |
2261 | .set noat if we use $at for PIC computations. If it turns | |
2262 | out that the branch was out-of-range, we'll get an error. */ | |
2263 | && !mips_opts.warn_about_macros | |
2264 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2265 | && !mips_opts.mips16) | |
2266 | { | |
895921c9 | 2267 | relaxed_branch = TRUE; |
1e915849 RS |
2268 | add_relaxed_insn (ip, (relaxed_branch_length |
2269 | (NULL, NULL, | |
2270 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2271 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2272 | : 0)), 4, | |
2273 | RELAX_BRANCH_ENCODE | |
2274 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2275 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2276 | pinfo & INSN_WRITE_GPR_31, | |
2277 | 0), | |
2278 | address_expr->X_add_symbol, | |
2279 | address_expr->X_add_number); | |
4a6a3df4 AO |
2280 | *reloc_type = BFD_RELOC_UNUSED; |
2281 | } | |
2282 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2283 | { |
2284 | /* We need to set up a variant frag. */ | |
2285 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2286 | add_relaxed_insn (ip, 4, 0, |
2287 | RELAX_MIPS16_ENCODE | |
2288 | (*reloc_type - BFD_RELOC_UNUSED, | |
2289 | mips16_small, mips16_ext, | |
2290 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2291 | history[0].mips16_absolute_jump_p), | |
2292 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2293 | } |
252b5132 RH |
2294 | else if (mips_opts.mips16 |
2295 | && ! ip->use_extend | |
f6688943 | 2296 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2297 | { |
2298 | /* Make sure there is enough room to swap this instruction with | |
2299 | a following jump instruction. */ | |
2300 | frag_grow (6); | |
1e915849 | 2301 | add_fixed_insn (ip); |
252b5132 RH |
2302 | } |
2303 | else | |
2304 | { | |
2305 | if (mips_opts.mips16 | |
2306 | && mips_opts.noreorder | |
2307 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2308 | as_warn (_("extended instruction in delay slot")); | |
2309 | ||
4d7206a2 RS |
2310 | if (mips_relax.sequence) |
2311 | { | |
2312 | /* If we've reached the end of this frag, turn it into a variant | |
2313 | frag and record the information for the instructions we've | |
2314 | written so far. */ | |
2315 | if (frag_room () < 4) | |
2316 | relax_close_frag (); | |
2317 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2318 | } | |
2319 | ||
584892a6 RS |
2320 | if (mips_relax.sequence != 2) |
2321 | mips_macro_warning.sizes[0] += 4; | |
2322 | if (mips_relax.sequence != 1) | |
2323 | mips_macro_warning.sizes[1] += 4; | |
2324 | ||
1e915849 RS |
2325 | if (mips_opts.mips16) |
2326 | { | |
2327 | ip->fixed_p = 1; | |
2328 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2329 | } | |
2330 | add_fixed_insn (ip); | |
252b5132 RH |
2331 | } |
2332 | ||
01a3f561 | 2333 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2334 | { |
2335 | if (address_expr->X_op == O_constant) | |
2336 | { | |
f17c130b | 2337 | unsigned int tmp; |
f6688943 TS |
2338 | |
2339 | switch (*reloc_type) | |
252b5132 RH |
2340 | { |
2341 | case BFD_RELOC_32: | |
2342 | ip->insn_opcode |= address_expr->X_add_number; | |
2343 | break; | |
2344 | ||
f6688943 | 2345 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2346 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2347 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2348 | break; |
2349 | ||
2350 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2351 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2352 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2353 | break; |
2354 | ||
2355 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2356 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2357 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2358 | break; |
2359 | ||
2360 | case BFD_RELOC_HI16: | |
2361 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2362 | break; | |
2363 | ||
01a3f561 | 2364 | case BFD_RELOC_UNUSED: |
252b5132 | 2365 | case BFD_RELOC_LO16: |
ed6fb7bd | 2366 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2367 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2368 | break; | |
2369 | ||
2370 | case BFD_RELOC_MIPS_JMP: | |
2371 | if ((address_expr->X_add_number & 3) != 0) | |
2372 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2373 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2374 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2375 | as_bad (_("jump address range overflow (0x%lx)"), |
2376 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2377 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2378 | break; | |
2379 | ||
2380 | case BFD_RELOC_MIPS16_JMP: | |
2381 | if ((address_expr->X_add_number & 3) != 0) | |
2382 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2383 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2384 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2385 | as_bad (_("jump address range overflow (0x%lx)"), |
2386 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2387 | ip->insn_opcode |= |
2388 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2389 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2390 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2391 | break; | |
2392 | ||
252b5132 RH |
2393 | case BFD_RELOC_16_PCREL_S2: |
2394 | goto need_reloc; | |
2395 | ||
2396 | default: | |
2397 | internalError (); | |
2398 | } | |
2399 | } | |
01a3f561 | 2400 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2401 | need_reloc: |
4d7206a2 RS |
2402 | { |
2403 | reloc_howto_type *howto; | |
2404 | int i; | |
34ce925e | 2405 | |
4d7206a2 RS |
2406 | /* In a compound relocation, it is the final (outermost) |
2407 | operator that determines the relocated field. */ | |
2408 | for (i = 1; i < 3; i++) | |
2409 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2410 | break; | |
34ce925e | 2411 | |
4d7206a2 | 2412 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2413 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2414 | bfd_get_reloc_size (howto), | |
2415 | address_expr, | |
2416 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2417 | reloc_type[0]); | |
4d7206a2 RS |
2418 | |
2419 | /* These relocations can have an addend that won't fit in | |
2420 | 4 octets for 64bit assembly. */ | |
2421 | if (HAVE_64BIT_GPRS | |
2422 | && ! howto->partial_inplace | |
2423 | && (reloc_type[0] == BFD_RELOC_16 | |
2424 | || reloc_type[0] == BFD_RELOC_32 | |
2425 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2426 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2427 | || reloc_type[0] == BFD_RELOC_LO16 | |
2428 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2429 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2430 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2431 | || reloc_type[0] == BFD_RELOC_64 | |
2432 | || reloc_type[0] == BFD_RELOC_CTOR | |
2433 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2434 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2435 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2436 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2437 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2438 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2439 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2440 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2441 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2442 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2443 | |
2444 | if (mips_relax.sequence) | |
2445 | { | |
2446 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2447 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2448 | } |
2449 | else if (reloc_needs_lo_p (*reloc_type)) | |
2450 | { | |
2451 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2452 | |
4d7206a2 RS |
2453 | /* Reuse the last entry if it already has a matching %lo. */ |
2454 | hi_fixup = mips_hi_fixup_list; | |
2455 | if (hi_fixup == 0 | |
2456 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2457 | { | |
2458 | hi_fixup = ((struct mips_hi_fixup *) | |
2459 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2460 | hi_fixup->next = mips_hi_fixup_list; | |
2461 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2462 | } |
1e915849 | 2463 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2464 | hi_fixup->seg = now_seg; |
2465 | } | |
f6688943 | 2466 | |
4d7206a2 RS |
2467 | /* Add fixups for the second and third relocations, if given. |
2468 | Note that the ABI allows the second relocation to be | |
2469 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2470 | moment we only use RSS_UNDEF, but we could add support | |
2471 | for the others if it ever becomes necessary. */ | |
2472 | for (i = 1; i < 3; i++) | |
2473 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2474 | { | |
1e915849 RS |
2475 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2476 | ip->fixp[0]->fx_size, NULL, 0, | |
2477 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2478 | |
2479 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2480 | ip->fixp[0]->fx_tcbit = 1; |
2481 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2482 | } |
252b5132 RH |
2483 | } |
2484 | } | |
1e915849 | 2485 | install_insn (ip); |
252b5132 RH |
2486 | |
2487 | /* Update the register mask information. */ | |
2488 | if (! mips_opts.mips16) | |
2489 | { | |
2490 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2491 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2492 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2493 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2494 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2495 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2496 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2497 | mips_gprmask |= 1 << RA; |
252b5132 | 2498 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2499 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2500 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2501 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2502 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2503 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2504 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2505 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2506 | if (pinfo & INSN_COP) |
2507 | { | |
bdaaa2e1 KH |
2508 | /* We don't keep enough information to sort these cases out. |
2509 | The itbl support does keep this information however, although | |
2510 | we currently don't support itbl fprmats as part of the cop | |
2511 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2512 | } |
2513 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2514 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2515 | } |
2516 | else | |
2517 | { | |
2518 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2519 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2520 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2521 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2522 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2523 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2524 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2525 | mips_gprmask |= 1 << TREG; | |
2526 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2527 | mips_gprmask |= 1 << SP; | |
2528 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2529 | mips_gprmask |= 1 << RA; | |
2530 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2531 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2532 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2533 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2534 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2535 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2536 | } |
2537 | ||
4d7206a2 | 2538 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2539 | { |
2540 | /* Filling the branch delay slot is more complex. We try to | |
2541 | switch the branch with the previous instruction, which we can | |
2542 | do if the previous instruction does not set up a condition | |
2543 | that the branch tests and if the branch is not itself the | |
2544 | target of any branch. */ | |
2545 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2546 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2547 | { | |
2548 | if (mips_optimize < 2 | |
2549 | /* If we have seen .set volatile or .set nomove, don't | |
2550 | optimize. */ | |
2551 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2552 | /* We can't swap if the previous instruction's position |
2553 | is fixed. */ | |
2554 | || history[0].fixed_p | |
252b5132 RH |
2555 | /* If the previous previous insn was in a .set |
2556 | noreorder, we can't swap. Actually, the MIPS | |
2557 | assembler will swap in this situation. However, gcc | |
2558 | configured -with-gnu-as will generate code like | |
2559 | .set noreorder | |
2560 | lw $4,XXX | |
2561 | .set reorder | |
2562 | INSN | |
2563 | bne $4,$0,foo | |
2564 | in which we can not swap the bne and INSN. If gcc is | |
2565 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2566 | .set pseudo-ops. */ |
47e39b9d | 2567 | || history[1].noreorder_p |
252b5132 RH |
2568 | /* If the branch is itself the target of a branch, we |
2569 | can not swap. We cheat on this; all we check for is | |
2570 | whether there is a label on this instruction. If | |
2571 | there are any branches to anything other than a | |
2572 | label, users must use .set noreorder. */ | |
2573 | || insn_labels != NULL | |
895921c9 MR |
2574 | /* If the previous instruction is in a variant frag |
2575 | other than this branch's one, we cannot do the swap. | |
2576 | This does not apply to the mips16, which uses variant | |
2577 | frags for different purposes. */ | |
252b5132 | 2578 | || (! mips_opts.mips16 |
895921c9 | 2579 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2580 | /* Check for conflicts between the branch and the instructions |
2581 | before the candidate delay slot. */ | |
2582 | || nops_for_insn (history + 1, ip) > 0 | |
2583 | /* Check for conflicts between the swapped sequence and the | |
2584 | target of the branch. */ | |
2585 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2586 | /* We do not swap with a trap instruction, since it |
2587 | complicates trap handlers to have the trap | |
2588 | instruction be in a delay slot. */ | |
2589 | || (prev_pinfo & INSN_TRAP) | |
2590 | /* If the branch reads a register that the previous | |
2591 | instruction sets, we can not swap. */ | |
2592 | || (! mips_opts.mips16 | |
2593 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2594 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2595 | MIPS_GR_REG)) |
2596 | || (! mips_opts.mips16 | |
2597 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2598 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2599 | MIPS_GR_REG)) |
2600 | || (mips_opts.mips16 | |
2601 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2602 | && (insn_uses_reg |
2603 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2604 | MIPS16_REG))) | |
252b5132 | 2605 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2606 | && (insn_uses_reg |
2607 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2608 | MIPS16_REG))) | |
252b5132 | 2609 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2610 | && (insn_uses_reg |
2611 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2612 | MIPS16_REG))) | |
252b5132 RH |
2613 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2614 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2615 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2616 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2617 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2618 | && insn_uses_reg (ip, | |
47e39b9d RS |
2619 | MIPS16OP_EXTRACT_REG32R |
2620 | (history[0].insn_opcode), | |
252b5132 RH |
2621 | MIPS_GR_REG)))) |
2622 | /* If the branch writes a register that the previous | |
2623 | instruction sets, we can not swap (we know that | |
2624 | branches write only to RD or to $31). */ | |
2625 | || (! mips_opts.mips16 | |
2626 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2627 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2628 | && (EXTRACT_OPERAND (RT, history[0]) |
2629 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2630 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2631 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2632 | || (! mips_opts.mips16 |
2633 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2634 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2635 | && (EXTRACT_OPERAND (RD, history[0]) |
2636 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2637 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2638 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2639 | || (mips_opts.mips16 |
2640 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2641 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2642 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2643 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2644 | == RA)))) |
2645 | /* If the branch writes a register that the previous | |
2646 | instruction reads, we can not swap (we know that | |
2647 | branches only write to RD or to $31). */ | |
2648 | || (! mips_opts.mips16 | |
2649 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2650 | && insn_uses_reg (&history[0], |
bf12938e | 2651 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2652 | MIPS_GR_REG)) |
2653 | || (! mips_opts.mips16 | |
2654 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2655 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2656 | || (mips_opts.mips16 |
2657 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2658 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2659 | /* If one instruction sets a condition code and the |
2660 | other one uses a condition code, we can not swap. */ | |
2661 | || ((pinfo & INSN_READ_COND_CODE) | |
2662 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2663 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2664 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2665 | /* If the previous instruction uses the PC, we can not | |
2666 | swap. */ | |
2667 | || (mips_opts.mips16 | |
2668 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2669 | /* If the previous instruction had a fixup in mips16 |
2670 | mode, we can not swap. This normally means that the | |
2671 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2672 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2673 | /* If the previous instruction is a sync, sync.l, or |
2674 | sync.p, we can not swap. */ | |
f173e82e | 2675 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2676 | { |
2677 | /* We could do even better for unconditional branches to | |
2678 | portions of this object file; we could pick up the | |
2679 | instruction at the destination, put it in the delay | |
2680 | slot, and bump the destination address. */ | |
1e915849 | 2681 | insert_into_history (0, 1, ip); |
252b5132 | 2682 | emit_nop (); |
dd22970f ILT |
2683 | if (mips_relax.sequence) |
2684 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2685 | } |
2686 | else | |
2687 | { | |
2688 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2689 | struct mips_cl_insn delay = history[0]; |
2690 | if (mips_opts.mips16) | |
252b5132 | 2691 | { |
1e915849 RS |
2692 | know (delay.frag == ip->frag); |
2693 | move_insn (ip, delay.frag, delay.where); | |
2694 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
2695 | } | |
2696 | else if (relaxed_branch) | |
2697 | { | |
2698 | /* Add the delay slot instruction to the end of the | |
2699 | current frag and shrink the fixed part of the | |
2700 | original frag. If the branch occupies the tail of | |
2701 | the latter, move it backwards to cover the gap. */ | |
2702 | delay.frag->fr_fix -= 4; | |
2703 | if (delay.frag == ip->frag) | |
2704 | move_insn (ip, ip->frag, ip->where - 4); | |
2705 | add_fixed_insn (&delay); | |
252b5132 RH |
2706 | } |
2707 | else | |
2708 | { | |
1e915849 RS |
2709 | move_insn (&delay, ip->frag, ip->where); |
2710 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2711 | } |
1e915849 RS |
2712 | history[0] = *ip; |
2713 | delay.fixed_p = 1; | |
2714 | insert_into_history (0, 1, &delay); | |
252b5132 | 2715 | } |
252b5132 RH |
2716 | |
2717 | /* If that was an unconditional branch, forget the previous | |
2718 | insn information. */ | |
2719 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 2720 | mips_no_prev_insn (); |
252b5132 RH |
2721 | } |
2722 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2723 | { | |
2724 | /* We don't yet optimize a branch likely. What we should do | |
2725 | is look at the target, copy the instruction found there | |
2726 | into the delay slot, and increment the branch to jump to | |
2727 | the next instruction. */ | |
1e915849 | 2728 | insert_into_history (0, 1, ip); |
252b5132 | 2729 | emit_nop (); |
252b5132 RH |
2730 | } |
2731 | else | |
1e915849 | 2732 | insert_into_history (0, 1, ip); |
252b5132 | 2733 | } |
1e915849 RS |
2734 | else |
2735 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2736 | |
2737 | /* We just output an insn, so the next one doesn't have a label. */ | |
2738 | mips_clear_insn_labels (); | |
252b5132 RH |
2739 | } |
2740 | ||
7d10b47d | 2741 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
2742 | |
2743 | static void | |
7d10b47d | 2744 | mips_no_prev_insn (void) |
252b5132 | 2745 | { |
7d10b47d RS |
2746 | prev_nop_frag = NULL; |
2747 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
2748 | mips_clear_insn_labels (); |
2749 | } | |
2750 | ||
7d10b47d RS |
2751 | /* This function must be called before we emit something other than |
2752 | instructions. It is like mips_no_prev_insn except that it inserts | |
2753 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 2754 | |
7d10b47d RS |
2755 | void |
2756 | mips_emit_delays (void) | |
252b5132 RH |
2757 | { |
2758 | if (! mips_opts.noreorder) | |
2759 | { | |
71400594 | 2760 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2761 | if (nops > 0) |
2762 | { | |
7d10b47d RS |
2763 | while (nops-- > 0) |
2764 | add_fixed_insn (NOP_INSN); | |
2765 | mips_move_labels (); | |
2766 | } | |
2767 | } | |
2768 | mips_no_prev_insn (); | |
2769 | } | |
2770 | ||
2771 | /* Start a (possibly nested) noreorder block. */ | |
2772 | ||
2773 | static void | |
2774 | start_noreorder (void) | |
2775 | { | |
2776 | if (mips_opts.noreorder == 0) | |
2777 | { | |
2778 | unsigned int i; | |
2779 | int nops; | |
2780 | ||
2781 | /* None of the instructions before the .set noreorder can be moved. */ | |
2782 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2783 | history[i].fixed_p = 1; | |
2784 | ||
2785 | /* Insert any nops that might be needed between the .set noreorder | |
2786 | block and the previous instructions. We will later remove any | |
2787 | nops that turn out not to be needed. */ | |
2788 | nops = nops_for_insn (history, NULL); | |
2789 | if (nops > 0) | |
2790 | { | |
2791 | if (mips_optimize != 0) | |
252b5132 RH |
2792 | { |
2793 | /* Record the frag which holds the nop instructions, so | |
2794 | that we can remove them if we don't need them. */ | |
2795 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2796 | prev_nop_frag = frag_now; | |
2797 | prev_nop_frag_holds = nops; | |
2798 | prev_nop_frag_required = 0; | |
2799 | prev_nop_frag_since = 0; | |
2800 | } | |
2801 | ||
2802 | for (; nops > 0; --nops) | |
1e915849 | 2803 | add_fixed_insn (NOP_INSN); |
252b5132 | 2804 | |
7d10b47d RS |
2805 | /* Move on to a new frag, so that it is safe to simply |
2806 | decrease the size of prev_nop_frag. */ | |
2807 | frag_wane (frag_now); | |
2808 | frag_new (0); | |
404a8071 | 2809 | mips_move_labels (); |
252b5132 | 2810 | } |
7d10b47d RS |
2811 | mips16_mark_labels (); |
2812 | mips_clear_insn_labels (); | |
252b5132 | 2813 | } |
7d10b47d RS |
2814 | mips_opts.noreorder++; |
2815 | mips_any_noreorder = 1; | |
2816 | } | |
252b5132 | 2817 | |
7d10b47d | 2818 | /* End a nested noreorder block. */ |
252b5132 | 2819 | |
7d10b47d RS |
2820 | static void |
2821 | end_noreorder (void) | |
2822 | { | |
2823 | mips_opts.noreorder--; | |
2824 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
2825 | { | |
2826 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
2827 | handling nop insertion the .set reorder way. */ | |
2828 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
2829 | * (mips_opts.mips16 ? 2 : 4)); | |
2830 | insert_into_history (prev_nop_frag_since, | |
2831 | prev_nop_frag_required, NOP_INSN); | |
2832 | prev_nop_frag = NULL; | |
2833 | } | |
252b5132 RH |
2834 | } |
2835 | ||
584892a6 RS |
2836 | /* Set up global variables for the start of a new macro. */ |
2837 | ||
2838 | static void | |
2839 | macro_start (void) | |
2840 | { | |
2841 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2842 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2843 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2844 | & (INSN_UNCOND_BRANCH_DELAY |
2845 | | INSN_COND_BRANCH_DELAY | |
2846 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2847 | } | |
2848 | ||
2849 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2850 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2851 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2852 | ||
2853 | static const char * | |
2854 | macro_warning (relax_substateT subtype) | |
2855 | { | |
2856 | if (subtype & RELAX_DELAY_SLOT) | |
2857 | return _("Macro instruction expanded into multiple instructions" | |
2858 | " in a branch delay slot"); | |
2859 | else if (subtype & RELAX_NOMACRO) | |
2860 | return _("Macro instruction expanded into multiple instructions"); | |
2861 | else | |
2862 | return 0; | |
2863 | } | |
2864 | ||
2865 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2866 | ||
2867 | static void | |
2868 | macro_end (void) | |
2869 | { | |
2870 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2871 | { | |
2872 | relax_substateT subtype; | |
2873 | ||
2874 | /* Set up the relaxation warning flags. */ | |
2875 | subtype = 0; | |
2876 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2877 | subtype |= RELAX_SECOND_LONGER; | |
2878 | if (mips_opts.warn_about_macros) | |
2879 | subtype |= RELAX_NOMACRO; | |
2880 | if (mips_macro_warning.delay_slot_p) | |
2881 | subtype |= RELAX_DELAY_SLOT; | |
2882 | ||
2883 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2884 | { | |
2885 | /* Either the macro has a single implementation or both | |
2886 | implementations are longer than 4 bytes. Emit the | |
2887 | warning now. */ | |
2888 | const char *msg = macro_warning (subtype); | |
2889 | if (msg != 0) | |
2890 | as_warn (msg); | |
2891 | } | |
2892 | else | |
2893 | { | |
2894 | /* One implementation might need a warning but the other | |
2895 | definitely doesn't. */ | |
2896 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2897 | } | |
2898 | } | |
2899 | } | |
2900 | ||
6e1304d8 RS |
2901 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2902 | The first argument in *ARGS will be either the code for a single | |
2903 | relocation or -1 followed by the three codes that make up a | |
2904 | composite relocation. */ | |
2905 | ||
2906 | static void | |
2907 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2908 | { | |
2909 | int i, next; | |
2910 | ||
2911 | next = va_arg (*args, int); | |
2912 | if (next >= 0) | |
2913 | r[0] = (bfd_reloc_code_real_type) next; | |
2914 | else | |
2915 | for (i = 0; i < 3; i++) | |
2916 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2917 | } | |
2918 | ||
252b5132 RH |
2919 | /* Build an instruction created by a macro expansion. This is passed |
2920 | a pointer to the count of instructions created so far, an | |
2921 | expression, the name of the instruction to build, an operand format | |
2922 | string, and corresponding arguments. */ | |
2923 | ||
252b5132 | 2924 | static void |
67c0d1eb | 2925 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2926 | { |
1e915849 | 2927 | const struct mips_opcode *mo; |
252b5132 | 2928 | struct mips_cl_insn insn; |
f6688943 | 2929 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2930 | va_list args; |
252b5132 | 2931 | |
252b5132 | 2932 | va_start (args, fmt); |
252b5132 | 2933 | |
252b5132 RH |
2934 | if (mips_opts.mips16) |
2935 | { | |
67c0d1eb | 2936 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2937 | va_end (args); |
2938 | return; | |
2939 | } | |
2940 | ||
f6688943 TS |
2941 | r[0] = BFD_RELOC_UNUSED; |
2942 | r[1] = BFD_RELOC_UNUSED; | |
2943 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2944 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2945 | assert (mo); | |
2946 | assert (strcmp (name, mo->name) == 0); | |
2947 | ||
2948 | /* Search until we get a match for NAME. It is assumed here that | |
2949 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2950 | while (strcmp (fmt, mo->args) != 0 | |
2951 | || mo->pinfo == INSN_MACRO | |
2952 | || !OPCODE_IS_MEMBER (mo, | |
2953 | (mips_opts.isa | |
2954 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2955 | mips_opts.arch) |
1e915849 RS |
2956 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2957 | { | |
2958 | ++mo; | |
2959 | assert (mo->name); | |
2960 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2961 | } |
2962 | ||
1e915849 | 2963 | create_insn (&insn, mo); |
252b5132 RH |
2964 | for (;;) |
2965 | { | |
2966 | switch (*fmt++) | |
2967 | { | |
2968 | case '\0': | |
2969 | break; | |
2970 | ||
2971 | case ',': | |
2972 | case '(': | |
2973 | case ')': | |
2974 | continue; | |
2975 | ||
5f74bc13 CD |
2976 | case '+': |
2977 | switch (*fmt++) | |
2978 | { | |
2979 | case 'A': | |
2980 | case 'E': | |
bf12938e | 2981 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
2982 | continue; |
2983 | ||
2984 | case 'B': | |
2985 | case 'F': | |
2986 | /* Note that in the macro case, these arguments are already | |
2987 | in MSB form. (When handling the instruction in the | |
2988 | non-macro case, these arguments are sizes from which | |
2989 | MSB values must be calculated.) */ | |
bf12938e | 2990 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
2991 | continue; |
2992 | ||
2993 | case 'C': | |
2994 | case 'G': | |
2995 | case 'H': | |
2996 | /* Note that in the macro case, these arguments are already | |
2997 | in MSBD form. (When handling the instruction in the | |
2998 | non-macro case, these arguments are sizes from which | |
2999 | MSBD values must be calculated.) */ | |
bf12938e | 3000 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3001 | continue; |
3002 | ||
3003 | default: | |
3004 | internalError (); | |
3005 | } | |
3006 | continue; | |
3007 | ||
252b5132 RH |
3008 | case 't': |
3009 | case 'w': | |
3010 | case 'E': | |
bf12938e | 3011 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3012 | continue; |
3013 | ||
3014 | case 'c': | |
bf12938e | 3015 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3016 | continue; |
3017 | ||
252b5132 RH |
3018 | case 'T': |
3019 | case 'W': | |
bf12938e | 3020 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3021 | continue; |
3022 | ||
3023 | case 'd': | |
3024 | case 'G': | |
af7ee8bf | 3025 | case 'K': |
bf12938e | 3026 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3027 | continue; |
3028 | ||
4372b673 NC |
3029 | case 'U': |
3030 | { | |
3031 | int tmp = va_arg (args, int); | |
3032 | ||
bf12938e RS |
3033 | INSERT_OPERAND (RT, insn, tmp); |
3034 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3035 | continue; |
4372b673 NC |
3036 | } |
3037 | ||
252b5132 RH |
3038 | case 'V': |
3039 | case 'S': | |
bf12938e | 3040 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3041 | continue; |
3042 | ||
3043 | case 'z': | |
3044 | continue; | |
3045 | ||
3046 | case '<': | |
bf12938e | 3047 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3048 | continue; |
3049 | ||
3050 | case 'D': | |
bf12938e | 3051 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3052 | continue; |
3053 | ||
3054 | case 'B': | |
bf12938e | 3055 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3056 | continue; |
3057 | ||
4372b673 | 3058 | case 'J': |
bf12938e | 3059 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3060 | continue; |
3061 | ||
252b5132 | 3062 | case 'q': |
bf12938e | 3063 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3064 | continue; |
3065 | ||
3066 | case 'b': | |
3067 | case 's': | |
3068 | case 'r': | |
3069 | case 'v': | |
bf12938e | 3070 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3071 | continue; |
3072 | ||
3073 | case 'i': | |
3074 | case 'j': | |
3075 | case 'o': | |
6e1304d8 | 3076 | macro_read_relocs (&args, r); |
cdf6fd85 | 3077 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3078 | || *r == BFD_RELOC_MIPS_LITERAL |
3079 | || *r == BFD_RELOC_MIPS_HIGHER | |
3080 | || *r == BFD_RELOC_HI16_S | |
3081 | || *r == BFD_RELOC_LO16 | |
3082 | || *r == BFD_RELOC_MIPS_GOT16 | |
3083 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3084 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3085 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3086 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3087 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3088 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3089 | continue; |
3090 | ||
3091 | case 'u': | |
6e1304d8 | 3092 | macro_read_relocs (&args, r); |
252b5132 RH |
3093 | assert (ep != NULL |
3094 | && (ep->X_op == O_constant | |
3095 | || (ep->X_op == O_symbol | |
f6688943 TS |
3096 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3097 | || *r == BFD_RELOC_HI16_S | |
3098 | || *r == BFD_RELOC_HI16 | |
3099 | || *r == BFD_RELOC_GPREL16 | |
3100 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3101 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3102 | continue; |
3103 | ||
3104 | case 'p': | |
3105 | assert (ep != NULL); | |
3106 | /* | |
3107 | * This allows macro() to pass an immediate expression for | |
3108 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3109 | * Note that the expression still might come from the assembly |
3110 | * input, in which case the value is not checked for range nor | |
3111 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3112 | */ |
3113 | if (ep->X_op == O_constant) | |
3114 | { | |
3115 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3116 | ep = NULL; | |
3117 | } | |
3118 | else | |
0b25d3e6 | 3119 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3120 | continue; |
3121 | ||
3122 | case 'a': | |
3123 | assert (ep != NULL); | |
f6688943 | 3124 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3125 | continue; |
3126 | ||
3127 | case 'C': | |
3128 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3129 | continue; | |
3130 | ||
3131 | default: | |
3132 | internalError (); | |
3133 | } | |
3134 | break; | |
3135 | } | |
3136 | va_end (args); | |
f6688943 | 3137 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3138 | |
4d7206a2 | 3139 | append_insn (&insn, ep, r); |
252b5132 RH |
3140 | } |
3141 | ||
3142 | static void | |
67c0d1eb | 3143 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3144 | va_list args) |
252b5132 | 3145 | { |
1e915849 | 3146 | struct mips_opcode *mo; |
252b5132 | 3147 | struct mips_cl_insn insn; |
f6688943 TS |
3148 | bfd_reloc_code_real_type r[3] |
3149 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3150 | |
1e915849 RS |
3151 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3152 | assert (mo); | |
3153 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3154 | |
1e915849 | 3155 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3156 | { |
1e915849 RS |
3157 | ++mo; |
3158 | assert (mo->name); | |
3159 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3160 | } |
3161 | ||
1e915849 | 3162 | create_insn (&insn, mo); |
252b5132 RH |
3163 | for (;;) |
3164 | { | |
3165 | int c; | |
3166 | ||
3167 | c = *fmt++; | |
3168 | switch (c) | |
3169 | { | |
3170 | case '\0': | |
3171 | break; | |
3172 | ||
3173 | case ',': | |
3174 | case '(': | |
3175 | case ')': | |
3176 | continue; | |
3177 | ||
3178 | case 'y': | |
3179 | case 'w': | |
bf12938e | 3180 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3181 | continue; |
3182 | ||
3183 | case 'x': | |
3184 | case 'v': | |
bf12938e | 3185 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3186 | continue; |
3187 | ||
3188 | case 'z': | |
bf12938e | 3189 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3190 | continue; |
3191 | ||
3192 | case 'Z': | |
bf12938e | 3193 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3194 | continue; |
3195 | ||
3196 | case '0': | |
3197 | case 'S': | |
3198 | case 'P': | |
3199 | case 'R': | |
3200 | continue; | |
3201 | ||
3202 | case 'X': | |
bf12938e | 3203 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3204 | continue; |
3205 | ||
3206 | case 'Y': | |
3207 | { | |
3208 | int regno; | |
3209 | ||
3210 | regno = va_arg (args, int); | |
3211 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3212 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3213 | } | |
3214 | continue; | |
3215 | ||
3216 | case '<': | |
3217 | case '>': | |
3218 | case '4': | |
3219 | case '5': | |
3220 | case 'H': | |
3221 | case 'W': | |
3222 | case 'D': | |
3223 | case 'j': | |
3224 | case '8': | |
3225 | case 'V': | |
3226 | case 'C': | |
3227 | case 'U': | |
3228 | case 'k': | |
3229 | case 'K': | |
3230 | case 'p': | |
3231 | case 'q': | |
3232 | { | |
3233 | assert (ep != NULL); | |
3234 | ||
3235 | if (ep->X_op != O_constant) | |
874e8986 | 3236 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3237 | else |
3238 | { | |
b34976b6 AM |
3239 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3240 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3241 | &insn.extend); |
252b5132 | 3242 | ep = NULL; |
f6688943 | 3243 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3244 | } |
3245 | } | |
3246 | continue; | |
3247 | ||
3248 | case '6': | |
bf12938e | 3249 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3250 | continue; |
3251 | } | |
3252 | ||
3253 | break; | |
3254 | } | |
3255 | ||
f6688943 | 3256 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3257 | |
4d7206a2 | 3258 | append_insn (&insn, ep, r); |
252b5132 RH |
3259 | } |
3260 | ||
2051e8c4 MR |
3261 | /* |
3262 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3263 | * higher bits unset. | |
3264 | */ | |
9f872bbe | 3265 | static void |
2051e8c4 MR |
3266 | normalize_constant_expr (expressionS *ex) |
3267 | { | |
9ee2a2d4 | 3268 | if (ex->X_op == O_constant |
2051e8c4 MR |
3269 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3270 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3271 | - 0x80000000); | |
3272 | } | |
3273 | ||
3274 | /* | |
3275 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3276 | * all higher bits unset. | |
3277 | */ | |
3278 | static void | |
3279 | normalize_address_expr (expressionS *ex) | |
3280 | { | |
3281 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3282 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3283 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3284 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3285 | - 0x80000000); | |
3286 | } | |
3287 | ||
438c16b8 TS |
3288 | /* |
3289 | * Generate a "jalr" instruction with a relocation hint to the called | |
3290 | * function. This occurs in NewABI PIC code. | |
3291 | */ | |
3292 | static void | |
67c0d1eb | 3293 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3294 | { |
685736be | 3295 | char *f = NULL; |
b34976b6 | 3296 | |
438c16b8 | 3297 | if (HAVE_NEWABI) |
f21f8242 | 3298 | { |
cc3d92a5 | 3299 | frag_grow (8); |
f21f8242 AO |
3300 | f = frag_more (0); |
3301 | } | |
67c0d1eb | 3302 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3303 | if (HAVE_NEWABI) |
f21f8242 | 3304 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3305 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3306 | } |
3307 | ||
252b5132 RH |
3308 | /* |
3309 | * Generate a "lui" instruction. | |
3310 | */ | |
3311 | static void | |
67c0d1eb | 3312 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3313 | { |
3314 | expressionS high_expr; | |
1e915849 | 3315 | const struct mips_opcode *mo; |
252b5132 | 3316 | struct mips_cl_insn insn; |
f6688943 TS |
3317 | bfd_reloc_code_real_type r[3] |
3318 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3319 | const char *name = "lui"; |
3320 | const char *fmt = "t,u"; | |
252b5132 RH |
3321 | |
3322 | assert (! mips_opts.mips16); | |
3323 | ||
4d7206a2 | 3324 | high_expr = *ep; |
252b5132 RH |
3325 | |
3326 | if (high_expr.X_op == O_constant) | |
3327 | { | |
3328 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3329 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3330 | >> 16) & 0xffff; | |
f6688943 | 3331 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3332 | } |
78e1bb40 | 3333 | else |
252b5132 RH |
3334 | { |
3335 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3336 | /* _gp_disp is a special case, used from s_cpload. |
3337 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3338 | assert (mips_pic == NO_PIC |
78e1bb40 | 3339 | || (! HAVE_NEWABI |
aa6975fb ILT |
3340 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3341 | || (! mips_in_shared | |
bbe506e8 TS |
3342 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3343 | "__gnu_local_gp") == 0)); | |
f6688943 | 3344 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3345 | } |
3346 | ||
1e915849 RS |
3347 | mo = hash_find (op_hash, name); |
3348 | assert (strcmp (name, mo->name) == 0); | |
3349 | assert (strcmp (fmt, mo->args) == 0); | |
3350 | create_insn (&insn, mo); | |
252b5132 | 3351 | |
bf12938e RS |
3352 | insn.insn_opcode = insn.insn_mo->match; |
3353 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3354 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3355 | { |
3356 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3357 | append_insn (&insn, NULL, r); |
252b5132 RH |
3358 | } |
3359 | else | |
4d7206a2 | 3360 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3361 | } |
3362 | ||
885add95 CD |
3363 | /* Generate a sequence of instructions to do a load or store from a constant |
3364 | offset off of a base register (breg) into/from a target register (treg), | |
3365 | using AT if necessary. */ | |
3366 | static void | |
67c0d1eb RS |
3367 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3368 | int treg, int breg, int dbl) | |
885add95 CD |
3369 | { |
3370 | assert (ep->X_op == O_constant); | |
3371 | ||
256ab948 | 3372 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3373 | if (!dbl) |
3374 | normalize_constant_expr (ep); | |
256ab948 | 3375 | |
67c1ffbe | 3376 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3377 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3378 | as_warn (_("operand overflow")); |
3379 | ||
3380 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3381 | { | |
3382 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3383 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3384 | } |
3385 | else | |
3386 | { | |
3387 | /* 32-bit offset, need multiple instructions and AT, like: | |
3388 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3389 | addu $tempreg,$tempreg,$breg | |
3390 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3391 | to handle the complete offset. */ | |
67c0d1eb RS |
3392 | macro_build_lui (ep, AT); |
3393 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3394 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3395 | |
3396 | if (mips_opts.noat) | |
8fc2e39e | 3397 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3398 | } |
3399 | } | |
3400 | ||
252b5132 RH |
3401 | /* set_at() |
3402 | * Generates code to set the $at register to true (one) | |
3403 | * if reg is less than the immediate expression. | |
3404 | */ | |
3405 | static void | |
67c0d1eb | 3406 | set_at (int reg, int unsignedp) |
252b5132 RH |
3407 | { |
3408 | if (imm_expr.X_op == O_constant | |
3409 | && imm_expr.X_add_number >= -0x8000 | |
3410 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3411 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3412 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3413 | else |
3414 | { | |
67c0d1eb RS |
3415 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3416 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3417 | } |
3418 | } | |
3419 | ||
3420 | /* Warn if an expression is not a constant. */ | |
3421 | ||
3422 | static void | |
17a2f251 | 3423 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3424 | { |
3425 | if (ex->X_op == O_big) | |
3426 | as_bad (_("unsupported large constant")); | |
3427 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3428 | as_bad (_("Instruction %s requires absolute expression"), |
3429 | ip->insn_mo->name); | |
13757d0c | 3430 | |
9ee2a2d4 MR |
3431 | if (HAVE_32BIT_GPRS) |
3432 | normalize_constant_expr (ex); | |
252b5132 RH |
3433 | } |
3434 | ||
3435 | /* Count the leading zeroes by performing a binary chop. This is a | |
3436 | bulky bit of source, but performance is a LOT better for the | |
3437 | majority of values than a simple loop to count the bits: | |
3438 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3439 | if ((v) & (1 << (31 - lcnt))) | |
3440 | break; | |
3441 | However it is not code size friendly, and the gain will drop a bit | |
3442 | on certain cached systems. | |
3443 | */ | |
3444 | #define COUNT_TOP_ZEROES(v) \ | |
3445 | (((v) & ~0xffff) == 0 \ | |
3446 | ? ((v) & ~0xff) == 0 \ | |
3447 | ? ((v) & ~0xf) == 0 \ | |
3448 | ? ((v) & ~0x3) == 0 \ | |
3449 | ? ((v) & ~0x1) == 0 \ | |
3450 | ? !(v) \ | |
3451 | ? 32 \ | |
3452 | : 31 \ | |
3453 | : 30 \ | |
3454 | : ((v) & ~0x7) == 0 \ | |
3455 | ? 29 \ | |
3456 | : 28 \ | |
3457 | : ((v) & ~0x3f) == 0 \ | |
3458 | ? ((v) & ~0x1f) == 0 \ | |
3459 | ? 27 \ | |
3460 | : 26 \ | |
3461 | : ((v) & ~0x7f) == 0 \ | |
3462 | ? 25 \ | |
3463 | : 24 \ | |
3464 | : ((v) & ~0xfff) == 0 \ | |
3465 | ? ((v) & ~0x3ff) == 0 \ | |
3466 | ? ((v) & ~0x1ff) == 0 \ | |
3467 | ? 23 \ | |
3468 | : 22 \ | |
3469 | : ((v) & ~0x7ff) == 0 \ | |
3470 | ? 21 \ | |
3471 | : 20 \ | |
3472 | : ((v) & ~0x3fff) == 0 \ | |
3473 | ? ((v) & ~0x1fff) == 0 \ | |
3474 | ? 19 \ | |
3475 | : 18 \ | |
3476 | : ((v) & ~0x7fff) == 0 \ | |
3477 | ? 17 \ | |
3478 | : 16 \ | |
3479 | : ((v) & ~0xffffff) == 0 \ | |
3480 | ? ((v) & ~0xfffff) == 0 \ | |
3481 | ? ((v) & ~0x3ffff) == 0 \ | |
3482 | ? ((v) & ~0x1ffff) == 0 \ | |
3483 | ? 15 \ | |
3484 | : 14 \ | |
3485 | : ((v) & ~0x7ffff) == 0 \ | |
3486 | ? 13 \ | |
3487 | : 12 \ | |
3488 | : ((v) & ~0x3fffff) == 0 \ | |
3489 | ? ((v) & ~0x1fffff) == 0 \ | |
3490 | ? 11 \ | |
3491 | : 10 \ | |
3492 | : ((v) & ~0x7fffff) == 0 \ | |
3493 | ? 9 \ | |
3494 | : 8 \ | |
3495 | : ((v) & ~0xfffffff) == 0 \ | |
3496 | ? ((v) & ~0x3ffffff) == 0 \ | |
3497 | ? ((v) & ~0x1ffffff) == 0 \ | |
3498 | ? 7 \ | |
3499 | : 6 \ | |
3500 | : ((v) & ~0x7ffffff) == 0 \ | |
3501 | ? 5 \ | |
3502 | : 4 \ | |
3503 | : ((v) & ~0x3fffffff) == 0 \ | |
3504 | ? ((v) & ~0x1fffffff) == 0 \ | |
3505 | ? 3 \ | |
3506 | : 2 \ | |
3507 | : ((v) & ~0x7fffffff) == 0 \ | |
3508 | ? 1 \ | |
3509 | : 0) | |
3510 | ||
3511 | /* load_register() | |
67c1ffbe | 3512 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3513 | * an absolute expression value into a register. |
3514 | */ | |
3515 | static void | |
67c0d1eb | 3516 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3517 | { |
3518 | int freg; | |
3519 | expressionS hi32, lo32; | |
3520 | ||
3521 | if (ep->X_op != O_big) | |
3522 | { | |
3523 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3524 | |
3525 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3526 | if (!dbl) |
3527 | normalize_constant_expr (ep); | |
256ab948 TS |
3528 | |
3529 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3530 | { |
3531 | /* We can handle 16 bit signed values with an addiu to | |
3532 | $zero. No need to ever use daddiu here, since $zero and | |
3533 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3534 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3535 | return; |
3536 | } | |
3537 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3538 | { | |
3539 | /* We can handle 16 bit unsigned values with an ori to | |
3540 | $zero. */ | |
67c0d1eb | 3541 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3542 | return; |
3543 | } | |
256ab948 | 3544 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3545 | { |
3546 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3547 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3548 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3549 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3550 | return; |
3551 | } | |
3552 | } | |
3553 | ||
3554 | /* The value is larger than 32 bits. */ | |
3555 | ||
2051e8c4 | 3556 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3557 | { |
2051e8c4 MR |
3558 | as_bad (_("Number (0x%lx%08lx) larger than 32 bits"), |
3559 | (unsigned long) (ep->X_add_number >> 32), | |
3560 | (unsigned long) (ep->X_add_number & 0xffffffff)); | |
67c0d1eb | 3561 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3562 | return; |
3563 | } | |
3564 | ||
3565 | if (ep->X_op != O_big) | |
3566 | { | |
3567 | hi32 = *ep; | |
3568 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3569 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3570 | hi32.X_add_number &= 0xffffffff; | |
3571 | lo32 = *ep; | |
3572 | lo32.X_add_number &= 0xffffffff; | |
3573 | } | |
3574 | else | |
3575 | { | |
3576 | assert (ep->X_add_number > 2); | |
3577 | if (ep->X_add_number == 3) | |
3578 | generic_bignum[3] = 0; | |
3579 | else if (ep->X_add_number > 4) | |
3580 | as_bad (_("Number larger than 64 bits")); | |
3581 | lo32.X_op = O_constant; | |
3582 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3583 | hi32.X_op = O_constant; | |
3584 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3585 | } | |
3586 | ||
3587 | if (hi32.X_add_number == 0) | |
3588 | freg = 0; | |
3589 | else | |
3590 | { | |
3591 | int shift, bit; | |
3592 | unsigned long hi, lo; | |
3593 | ||
956cd1d6 | 3594 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3595 | { |
3596 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3597 | { | |
67c0d1eb | 3598 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3599 | return; |
3600 | } | |
3601 | if (lo32.X_add_number & 0x80000000) | |
3602 | { | |
67c0d1eb | 3603 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3604 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3605 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3606 | return; |
3607 | } | |
3608 | } | |
252b5132 RH |
3609 | |
3610 | /* Check for 16bit shifted constant. We know that hi32 is | |
3611 | non-zero, so start the mask on the first bit of the hi32 | |
3612 | value. */ | |
3613 | shift = 17; | |
3614 | do | |
beae10d5 KH |
3615 | { |
3616 | unsigned long himask, lomask; | |
3617 | ||
3618 | if (shift < 32) | |
3619 | { | |
3620 | himask = 0xffff >> (32 - shift); | |
3621 | lomask = (0xffff << shift) & 0xffffffff; | |
3622 | } | |
3623 | else | |
3624 | { | |
3625 | himask = 0xffff << (shift - 32); | |
3626 | lomask = 0; | |
3627 | } | |
3628 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3629 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3630 | { | |
3631 | expressionS tmp; | |
3632 | ||
3633 | tmp.X_op = O_constant; | |
3634 | if (shift < 32) | |
3635 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3636 | | (lo32.X_add_number >> shift)); | |
3637 | else | |
3638 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3639 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3640 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3641 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3642 | return; |
3643 | } | |
f9419b05 | 3644 | ++shift; |
beae10d5 KH |
3645 | } |
3646 | while (shift <= (64 - 16)); | |
252b5132 RH |
3647 | |
3648 | /* Find the bit number of the lowest one bit, and store the | |
3649 | shifted value in hi/lo. */ | |
3650 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3651 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3652 | if (lo != 0) | |
3653 | { | |
3654 | bit = 0; | |
3655 | while ((lo & 1) == 0) | |
3656 | { | |
3657 | lo >>= 1; | |
3658 | ++bit; | |
3659 | } | |
3660 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3661 | hi >>= bit; | |
3662 | } | |
3663 | else | |
3664 | { | |
3665 | bit = 32; | |
3666 | while ((hi & 1) == 0) | |
3667 | { | |
3668 | hi >>= 1; | |
3669 | ++bit; | |
3670 | } | |
3671 | lo = hi; | |
3672 | hi = 0; | |
3673 | } | |
3674 | ||
3675 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3676 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3677 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3678 | { |
3679 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3680 | if (shift != 0) |
beae10d5 | 3681 | { |
252b5132 RH |
3682 | expressionS tmp; |
3683 | ||
3684 | /* This instruction will set the register to be all | |
3685 | ones. */ | |
beae10d5 KH |
3686 | tmp.X_op = O_constant; |
3687 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3688 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3689 | if (bit != 0) |
3690 | { | |
3691 | bit += shift; | |
67c0d1eb RS |
3692 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3693 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3694 | } |
67c0d1eb RS |
3695 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3696 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3697 | return; |
3698 | } | |
3699 | } | |
252b5132 RH |
3700 | |
3701 | /* Sign extend hi32 before calling load_register, because we can | |
3702 | generally get better code when we load a sign extended value. */ | |
3703 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3704 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3705 | load_register (reg, &hi32, 0); |
252b5132 RH |
3706 | freg = reg; |
3707 | } | |
3708 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3709 | { | |
3710 | if (freg != 0) | |
3711 | { | |
67c0d1eb | 3712 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3713 | freg = reg; |
3714 | } | |
3715 | } | |
3716 | else | |
3717 | { | |
3718 | expressionS mid16; | |
3719 | ||
956cd1d6 | 3720 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3721 | { |
67c0d1eb RS |
3722 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3723 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3724 | return; |
3725 | } | |
252b5132 RH |
3726 | |
3727 | if (freg != 0) | |
3728 | { | |
67c0d1eb | 3729 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3730 | freg = reg; |
3731 | } | |
3732 | mid16 = lo32; | |
3733 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3734 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3735 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3736 | freg = reg; |
3737 | } | |
3738 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3739 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3740 | } |
3741 | ||
269137b2 TS |
3742 | static inline void |
3743 | load_delay_nop (void) | |
3744 | { | |
3745 | if (!gpr_interlocks) | |
3746 | macro_build (NULL, "nop", ""); | |
3747 | } | |
3748 | ||
252b5132 RH |
3749 | /* Load an address into a register. */ |
3750 | ||
3751 | static void | |
67c0d1eb | 3752 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3753 | { |
252b5132 RH |
3754 | if (ep->X_op != O_constant |
3755 | && ep->X_op != O_symbol) | |
3756 | { | |
3757 | as_bad (_("expression too complex")); | |
3758 | ep->X_op = O_constant; | |
3759 | } | |
3760 | ||
3761 | if (ep->X_op == O_constant) | |
3762 | { | |
67c0d1eb | 3763 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3764 | return; |
3765 | } | |
3766 | ||
3767 | if (mips_pic == NO_PIC) | |
3768 | { | |
3769 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3770 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3771 | Otherwise we want |
3772 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3773 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3774 | If we have an addend, we always use the latter form. |
76b3015f | 3775 | |
d6bc6245 TS |
3776 | With 64bit address space and a usable $at we want |
3777 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3778 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3779 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3780 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3781 | dsll32 $reg,0 | |
3a482fd5 | 3782 | daddu $reg,$reg,$at |
76b3015f | 3783 | |
c03099e6 | 3784 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3785 | on superscalar processors. |
3786 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3787 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3788 | dsll $reg,16 | |
3789 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3790 | dsll $reg,16 | |
3791 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3792 | |
3793 | For GP relative symbols in 64bit address space we can use | |
3794 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3795 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3796 | { |
6caf9ef4 TS |
3797 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3798 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3799 | { | |
3800 | relax_start (ep->X_add_symbol); | |
3801 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3802 | mips_gp_register, BFD_RELOC_GPREL16); | |
3803 | relax_switch (); | |
3804 | } | |
d6bc6245 | 3805 | |
b8285c27 | 3806 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3807 | { |
67c0d1eb RS |
3808 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3809 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3810 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3811 | BFD_RELOC_MIPS_HIGHER); | |
3812 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3813 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3814 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3815 | *used_at = 1; |
3816 | } | |
3817 | else | |
3818 | { | |
67c0d1eb RS |
3819 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3820 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3821 | BFD_RELOC_MIPS_HIGHER); | |
3822 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3823 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3824 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3825 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3826 | } |
6caf9ef4 TS |
3827 | |
3828 | if (mips_relax.sequence) | |
3829 | relax_end (); | |
d6bc6245 | 3830 | } |
252b5132 RH |
3831 | else |
3832 | { | |
d6bc6245 | 3833 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3834 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3835 | { |
4d7206a2 | 3836 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3837 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3838 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3839 | relax_switch (); |
d6bc6245 | 3840 | } |
67c0d1eb RS |
3841 | macro_build_lui (ep, reg); |
3842 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3843 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3844 | if (mips_relax.sequence) |
3845 | relax_end (); | |
d6bc6245 | 3846 | } |
252b5132 RH |
3847 | } |
3848 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3849 | { | |
3850 | expressionS ex; | |
3851 | ||
3852 | /* If this is a reference to an external symbol, we want | |
3853 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3854 | Otherwise we want | |
3855 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3856 | nop | |
3857 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3858 | If there is a constant, it must be added in after. |
3859 | ||
ed6fb7bd | 3860 | If we have NewABI, we want |
f5040a92 AO |
3861 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3862 | unless we're referencing a global symbol with a non-zero | |
3863 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3864 | if (HAVE_NEWABI) |
3865 | { | |
f5040a92 AO |
3866 | if (ep->X_add_number) |
3867 | { | |
4d7206a2 | 3868 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3869 | ep->X_add_number = 0; |
4d7206a2 | 3870 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3871 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3872 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3873 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3874 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3875 | ex.X_op = O_constant; | |
67c0d1eb | 3876 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3877 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3878 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3879 | relax_switch (); |
f5040a92 | 3880 | } |
67c0d1eb | 3881 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3882 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3883 | if (mips_relax.sequence) |
3884 | relax_end (); | |
ed6fb7bd SC |
3885 | } |
3886 | else | |
3887 | { | |
f5040a92 AO |
3888 | ex.X_add_number = ep->X_add_number; |
3889 | ep->X_add_number = 0; | |
67c0d1eb RS |
3890 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3891 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3892 | load_delay_nop (); |
4d7206a2 RS |
3893 | relax_start (ep->X_add_symbol); |
3894 | relax_switch (); | |
67c0d1eb | 3895 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3896 | BFD_RELOC_LO16); |
4d7206a2 | 3897 | relax_end (); |
ed6fb7bd | 3898 | |
f5040a92 AO |
3899 | if (ex.X_add_number != 0) |
3900 | { | |
3901 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3902 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3903 | ex.X_op = O_constant; | |
67c0d1eb | 3904 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3905 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3906 | } |
252b5132 RH |
3907 | } |
3908 | } | |
3909 | else if (mips_pic == SVR4_PIC) | |
3910 | { | |
3911 | expressionS ex; | |
252b5132 RH |
3912 | |
3913 | /* This is the large GOT case. If this is a reference to an | |
3914 | external symbol, we want | |
3915 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3916 | addu $reg,$reg,$gp | |
3917 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3918 | |
3919 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3920 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3921 | nop | |
3922 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3923 | If there is a constant, it must be added in after. |
f5040a92 AO |
3924 | |
3925 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3926 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3927 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3928 | */ |
438c16b8 TS |
3929 | if (HAVE_NEWABI) |
3930 | { | |
4d7206a2 | 3931 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3932 | ep->X_add_number = 0; |
4d7206a2 | 3933 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3934 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3935 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3936 | reg, reg, mips_gp_register); | |
3937 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3938 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3939 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3940 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3941 | else if (ex.X_add_number) | |
3942 | { | |
3943 | ex.X_op = O_constant; | |
67c0d1eb RS |
3944 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3945 | BFD_RELOC_LO16); | |
f5040a92 AO |
3946 | } |
3947 | ||
3948 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3949 | relax_switch (); |
67c0d1eb | 3950 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3951 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3952 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3953 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3954 | relax_end (); |
438c16b8 | 3955 | } |
252b5132 | 3956 | else |
438c16b8 | 3957 | { |
f5040a92 AO |
3958 | ex.X_add_number = ep->X_add_number; |
3959 | ep->X_add_number = 0; | |
4d7206a2 | 3960 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3961 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3962 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3963 | reg, reg, mips_gp_register); | |
3964 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3965 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3966 | relax_switch (); |
3967 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3968 | { |
3969 | /* We need a nop before loading from $gp. This special | |
3970 | check is required because the lui which starts the main | |
3971 | instruction stream does not refer to $gp, and so will not | |
3972 | insert the nop which may be required. */ | |
67c0d1eb | 3973 | macro_build (NULL, "nop", ""); |
438c16b8 | 3974 | } |
67c0d1eb | 3975 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3976 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3977 | load_delay_nop (); |
67c0d1eb | 3978 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3979 | BFD_RELOC_LO16); |
4d7206a2 | 3980 | relax_end (); |
438c16b8 | 3981 | |
f5040a92 AO |
3982 | if (ex.X_add_number != 0) |
3983 | { | |
3984 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3985 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3986 | ex.X_op = O_constant; | |
67c0d1eb RS |
3987 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3988 | BFD_RELOC_LO16); | |
f5040a92 | 3989 | } |
252b5132 RH |
3990 | } |
3991 | } | |
252b5132 RH |
3992 | else |
3993 | abort (); | |
8fc2e39e TS |
3994 | |
3995 | if (mips_opts.noat && *used_at == 1) | |
3996 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
3997 | } |
3998 | ||
ea1fb5dc RS |
3999 | /* Move the contents of register SOURCE into register DEST. */ |
4000 | ||
4001 | static void | |
67c0d1eb | 4002 | move_register (int dest, int source) |
ea1fb5dc | 4003 | { |
67c0d1eb RS |
4004 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4005 | dest, source, 0); | |
ea1fb5dc RS |
4006 | } |
4007 | ||
4d7206a2 | 4008 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4009 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4010 | The two alternatives are: | |
4d7206a2 RS |
4011 | |
4012 | Global symbol Local sybmol | |
4013 | ------------- ------------ | |
4014 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4015 | ... ... | |
4016 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4017 | ||
4018 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4019 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4020 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4021 | |
4022 | static void | |
67c0d1eb | 4023 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4024 | { |
4025 | expressionS global; | |
4026 | ||
4027 | global = *local; | |
4028 | global.X_add_number = 0; | |
4029 | ||
4030 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4031 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4032 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4033 | relax_switch (); |
67c0d1eb RS |
4034 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4035 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4036 | relax_end (); |
4037 | } | |
4038 | ||
4039 | static void | |
67c0d1eb | 4040 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4041 | { |
4042 | expressionS global; | |
4043 | ||
4044 | global.X_op = O_constant; | |
4045 | global.X_op_symbol = NULL; | |
4046 | global.X_add_symbol = NULL; | |
4047 | global.X_add_number = local->X_add_number; | |
4048 | ||
4049 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4050 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4051 | dest, dest, BFD_RELOC_LO16); |
4052 | relax_switch (); | |
67c0d1eb | 4053 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4054 | relax_end (); |
4055 | } | |
4056 | ||
f6a22291 MR |
4057 | static void |
4058 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4059 | { | |
4060 | expressionS global; | |
4061 | int hold_mips_optimize; | |
4062 | ||
4063 | global.X_op = O_constant; | |
4064 | global.X_op_symbol = NULL; | |
4065 | global.X_add_symbol = NULL; | |
4066 | global.X_add_number = local->X_add_number; | |
4067 | ||
4068 | relax_start (local->X_add_symbol); | |
4069 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4070 | relax_switch (); | |
4071 | /* Set mips_optimize around the lui instruction to avoid | |
4072 | inserting an unnecessary nop after the lw. */ | |
4073 | hold_mips_optimize = mips_optimize; | |
4074 | mips_optimize = 2; | |
4075 | macro_build_lui (&global, tmp); | |
4076 | mips_optimize = hold_mips_optimize; | |
4077 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4078 | relax_end (); | |
4079 | ||
4080 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4081 | } | |
4082 | ||
252b5132 RH |
4083 | /* |
4084 | * Build macros | |
4085 | * This routine implements the seemingly endless macro or synthesized | |
4086 | * instructions and addressing modes in the mips assembly language. Many | |
4087 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4088 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4089 | * this verbose method. Others are not simple macros but are more like |
4090 | * optimizing code generation. | |
4091 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4092 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4093 | * The ensuing load upper instructions are ommited. This implies some kind |
4094 | * of global optimization. We currently only optimize within a single macro. | |
4095 | * For many of the load and store macros if the address is specified as a | |
4096 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4097 | * first load register 'at' with zero and use it as the base register. The | |
4098 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4099 | * we're missing. | |
4100 | */ | |
4101 | static void | |
17a2f251 | 4102 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4103 | { |
4104 | register int treg, sreg, dreg, breg; | |
4105 | int tempreg; | |
4106 | int mask; | |
43841e91 | 4107 | int used_at = 0; |
252b5132 RH |
4108 | expressionS expr1; |
4109 | const char *s; | |
4110 | const char *s2; | |
4111 | const char *fmt; | |
4112 | int likely = 0; | |
4113 | int dbl = 0; | |
4114 | int coproc = 0; | |
4115 | int lr = 0; | |
4116 | int imm = 0; | |
1abe91b1 | 4117 | int call = 0; |
252b5132 | 4118 | int off; |
67c0d1eb | 4119 | offsetT maxnum; |
252b5132 | 4120 | bfd_reloc_code_real_type r; |
252b5132 RH |
4121 | int hold_mips_optimize; |
4122 | ||
4123 | assert (! mips_opts.mips16); | |
4124 | ||
4125 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4126 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4127 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4128 | mask = ip->insn_mo->mask; | |
4129 | ||
4130 | expr1.X_op = O_constant; | |
4131 | expr1.X_op_symbol = NULL; | |
4132 | expr1.X_add_symbol = NULL; | |
4133 | expr1.X_add_number = 1; | |
4134 | ||
4135 | switch (mask) | |
4136 | { | |
4137 | case M_DABS: | |
4138 | dbl = 1; | |
4139 | case M_ABS: | |
4140 | /* bgez $a0,.+12 | |
4141 | move v0,$a0 | |
4142 | sub v0,$zero,$a0 | |
4143 | */ | |
4144 | ||
7d10b47d | 4145 | start_noreorder (); |
252b5132 RH |
4146 | |
4147 | expr1.X_add_number = 8; | |
67c0d1eb | 4148 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4149 | if (dreg == sreg) |
67c0d1eb | 4150 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4151 | else |
67c0d1eb RS |
4152 | move_register (dreg, sreg); |
4153 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4154 | |
7d10b47d | 4155 | end_noreorder (); |
8fc2e39e | 4156 | break; |
252b5132 RH |
4157 | |
4158 | case M_ADD_I: | |
4159 | s = "addi"; | |
4160 | s2 = "add"; | |
4161 | goto do_addi; | |
4162 | case M_ADDU_I: | |
4163 | s = "addiu"; | |
4164 | s2 = "addu"; | |
4165 | goto do_addi; | |
4166 | case M_DADD_I: | |
4167 | dbl = 1; | |
4168 | s = "daddi"; | |
4169 | s2 = "dadd"; | |
4170 | goto do_addi; | |
4171 | case M_DADDU_I: | |
4172 | dbl = 1; | |
4173 | s = "daddiu"; | |
4174 | s2 = "daddu"; | |
4175 | do_addi: | |
4176 | if (imm_expr.X_op == O_constant | |
4177 | && imm_expr.X_add_number >= -0x8000 | |
4178 | && imm_expr.X_add_number < 0x8000) | |
4179 | { | |
67c0d1eb | 4180 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4181 | break; |
252b5132 | 4182 | } |
8fc2e39e | 4183 | used_at = 1; |
67c0d1eb RS |
4184 | load_register (AT, &imm_expr, dbl); |
4185 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4186 | break; |
4187 | ||
4188 | case M_AND_I: | |
4189 | s = "andi"; | |
4190 | s2 = "and"; | |
4191 | goto do_bit; | |
4192 | case M_OR_I: | |
4193 | s = "ori"; | |
4194 | s2 = "or"; | |
4195 | goto do_bit; | |
4196 | case M_NOR_I: | |
4197 | s = ""; | |
4198 | s2 = "nor"; | |
4199 | goto do_bit; | |
4200 | case M_XOR_I: | |
4201 | s = "xori"; | |
4202 | s2 = "xor"; | |
4203 | do_bit: | |
4204 | if (imm_expr.X_op == O_constant | |
4205 | && imm_expr.X_add_number >= 0 | |
4206 | && imm_expr.X_add_number < 0x10000) | |
4207 | { | |
4208 | if (mask != M_NOR_I) | |
67c0d1eb | 4209 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4210 | else |
4211 | { | |
67c0d1eb RS |
4212 | macro_build (&imm_expr, "ori", "t,r,i", |
4213 | treg, sreg, BFD_RELOC_LO16); | |
4214 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4215 | } |
8fc2e39e | 4216 | break; |
252b5132 RH |
4217 | } |
4218 | ||
8fc2e39e | 4219 | used_at = 1; |
67c0d1eb RS |
4220 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4221 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4222 | break; |
4223 | ||
4224 | case M_BEQ_I: | |
4225 | s = "beq"; | |
4226 | goto beq_i; | |
4227 | case M_BEQL_I: | |
4228 | s = "beql"; | |
4229 | likely = 1; | |
4230 | goto beq_i; | |
4231 | case M_BNE_I: | |
4232 | s = "bne"; | |
4233 | goto beq_i; | |
4234 | case M_BNEL_I: | |
4235 | s = "bnel"; | |
4236 | likely = 1; | |
4237 | beq_i: | |
4238 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4239 | { | |
67c0d1eb | 4240 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4241 | break; |
252b5132 | 4242 | } |
8fc2e39e | 4243 | used_at = 1; |
67c0d1eb RS |
4244 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4245 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4246 | break; |
4247 | ||
4248 | case M_BGEL: | |
4249 | likely = 1; | |
4250 | case M_BGE: | |
4251 | if (treg == 0) | |
4252 | { | |
67c0d1eb | 4253 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4254 | break; |
252b5132 RH |
4255 | } |
4256 | if (sreg == 0) | |
4257 | { | |
67c0d1eb | 4258 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4259 | break; |
252b5132 | 4260 | } |
8fc2e39e | 4261 | used_at = 1; |
67c0d1eb RS |
4262 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4263 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4264 | break; |
4265 | ||
4266 | case M_BGTL_I: | |
4267 | likely = 1; | |
4268 | case M_BGT_I: | |
4269 | /* check for > max integer */ | |
4270 | maxnum = 0x7fffffff; | |
ca4e0257 | 4271 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4272 | { |
4273 | maxnum <<= 16; | |
4274 | maxnum |= 0xffff; | |
4275 | maxnum <<= 16; | |
4276 | maxnum |= 0xffff; | |
4277 | } | |
4278 | if (imm_expr.X_op == O_constant | |
4279 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4280 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4281 | { |
4282 | do_false: | |
4283 | /* result is always false */ | |
4284 | if (! likely) | |
67c0d1eb | 4285 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4286 | else |
67c0d1eb | 4287 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4288 | break; |
252b5132 RH |
4289 | } |
4290 | if (imm_expr.X_op != O_constant) | |
4291 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4292 | ++imm_expr.X_add_number; |
252b5132 RH |
4293 | /* FALLTHROUGH */ |
4294 | case M_BGE_I: | |
4295 | case M_BGEL_I: | |
4296 | if (mask == M_BGEL_I) | |
4297 | likely = 1; | |
4298 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4299 | { | |
67c0d1eb | 4300 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4301 | break; |
252b5132 RH |
4302 | } |
4303 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4304 | { | |
67c0d1eb | 4305 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4306 | break; |
252b5132 RH |
4307 | } |
4308 | maxnum = 0x7fffffff; | |
ca4e0257 | 4309 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4310 | { |
4311 | maxnum <<= 16; | |
4312 | maxnum |= 0xffff; | |
4313 | maxnum <<= 16; | |
4314 | maxnum |= 0xffff; | |
4315 | } | |
4316 | maxnum = - maxnum - 1; | |
4317 | if (imm_expr.X_op == O_constant | |
4318 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4319 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4320 | { |
4321 | do_true: | |
4322 | /* result is always true */ | |
4323 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4324 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4325 | break; |
252b5132 | 4326 | } |
8fc2e39e | 4327 | used_at = 1; |
67c0d1eb RS |
4328 | set_at (sreg, 0); |
4329 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4330 | break; |
4331 | ||
4332 | case M_BGEUL: | |
4333 | likely = 1; | |
4334 | case M_BGEU: | |
4335 | if (treg == 0) | |
4336 | goto do_true; | |
4337 | if (sreg == 0) | |
4338 | { | |
67c0d1eb | 4339 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4340 | "s,t,p", 0, treg); |
8fc2e39e | 4341 | break; |
252b5132 | 4342 | } |
8fc2e39e | 4343 | used_at = 1; |
67c0d1eb RS |
4344 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4345 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4346 | break; |
4347 | ||
4348 | case M_BGTUL_I: | |
4349 | likely = 1; | |
4350 | case M_BGTU_I: | |
4351 | if (sreg == 0 | |
ca4e0257 | 4352 | || (HAVE_32BIT_GPRS |
252b5132 | 4353 | && imm_expr.X_op == O_constant |
956cd1d6 | 4354 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4355 | goto do_false; |
4356 | if (imm_expr.X_op != O_constant) | |
4357 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4358 | ++imm_expr.X_add_number; |
252b5132 RH |
4359 | /* FALLTHROUGH */ |
4360 | case M_BGEU_I: | |
4361 | case M_BGEUL_I: | |
4362 | if (mask == M_BGEUL_I) | |
4363 | likely = 1; | |
4364 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4365 | goto do_true; | |
4366 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4367 | { | |
67c0d1eb | 4368 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4369 | "s,t,p", sreg, 0); |
8fc2e39e | 4370 | break; |
252b5132 | 4371 | } |
8fc2e39e | 4372 | used_at = 1; |
67c0d1eb RS |
4373 | set_at (sreg, 1); |
4374 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4375 | break; |
4376 | ||
4377 | case M_BGTL: | |
4378 | likely = 1; | |
4379 | case M_BGT: | |
4380 | if (treg == 0) | |
4381 | { | |
67c0d1eb | 4382 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4383 | break; |
252b5132 RH |
4384 | } |
4385 | if (sreg == 0) | |
4386 | { | |
67c0d1eb | 4387 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4388 | break; |
252b5132 | 4389 | } |
8fc2e39e | 4390 | used_at = 1; |
67c0d1eb RS |
4391 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4392 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4393 | break; |
4394 | ||
4395 | case M_BGTUL: | |
4396 | likely = 1; | |
4397 | case M_BGTU: | |
4398 | if (treg == 0) | |
4399 | { | |
67c0d1eb | 4400 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4401 | "s,t,p", sreg, 0); |
8fc2e39e | 4402 | break; |
252b5132 RH |
4403 | } |
4404 | if (sreg == 0) | |
4405 | goto do_false; | |
8fc2e39e | 4406 | used_at = 1; |
67c0d1eb RS |
4407 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4408 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4409 | break; |
4410 | ||
4411 | case M_BLEL: | |
4412 | likely = 1; | |
4413 | case M_BLE: | |
4414 | if (treg == 0) | |
4415 | { | |
67c0d1eb | 4416 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4417 | break; |
252b5132 RH |
4418 | } |
4419 | if (sreg == 0) | |
4420 | { | |
67c0d1eb | 4421 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4422 | break; |
252b5132 | 4423 | } |
8fc2e39e | 4424 | used_at = 1; |
67c0d1eb RS |
4425 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4426 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4427 | break; |
4428 | ||
4429 | case M_BLEL_I: | |
4430 | likely = 1; | |
4431 | case M_BLE_I: | |
4432 | maxnum = 0x7fffffff; | |
ca4e0257 | 4433 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4434 | { |
4435 | maxnum <<= 16; | |
4436 | maxnum |= 0xffff; | |
4437 | maxnum <<= 16; | |
4438 | maxnum |= 0xffff; | |
4439 | } | |
4440 | if (imm_expr.X_op == O_constant | |
4441 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4442 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4443 | goto do_true; |
4444 | if (imm_expr.X_op != O_constant) | |
4445 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4446 | ++imm_expr.X_add_number; |
252b5132 RH |
4447 | /* FALLTHROUGH */ |
4448 | case M_BLT_I: | |
4449 | case M_BLTL_I: | |
4450 | if (mask == M_BLTL_I) | |
4451 | likely = 1; | |
4452 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4453 | { | |
67c0d1eb | 4454 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4455 | break; |
252b5132 RH |
4456 | } |
4457 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4458 | { | |
67c0d1eb | 4459 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4460 | break; |
252b5132 | 4461 | } |
8fc2e39e | 4462 | used_at = 1; |
67c0d1eb RS |
4463 | set_at (sreg, 0); |
4464 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4465 | break; |
4466 | ||
4467 | case M_BLEUL: | |
4468 | likely = 1; | |
4469 | case M_BLEU: | |
4470 | if (treg == 0) | |
4471 | { | |
67c0d1eb | 4472 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4473 | "s,t,p", sreg, 0); |
8fc2e39e | 4474 | break; |
252b5132 RH |
4475 | } |
4476 | if (sreg == 0) | |
4477 | goto do_true; | |
8fc2e39e | 4478 | used_at = 1; |
67c0d1eb RS |
4479 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4480 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4481 | break; |
4482 | ||
4483 | case M_BLEUL_I: | |
4484 | likely = 1; | |
4485 | case M_BLEU_I: | |
4486 | if (sreg == 0 | |
ca4e0257 | 4487 | || (HAVE_32BIT_GPRS |
252b5132 | 4488 | && imm_expr.X_op == O_constant |
956cd1d6 | 4489 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4490 | goto do_true; |
4491 | if (imm_expr.X_op != O_constant) | |
4492 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4493 | ++imm_expr.X_add_number; |
252b5132 RH |
4494 | /* FALLTHROUGH */ |
4495 | case M_BLTU_I: | |
4496 | case M_BLTUL_I: | |
4497 | if (mask == M_BLTUL_I) | |
4498 | likely = 1; | |
4499 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4500 | goto do_false; | |
4501 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4502 | { | |
67c0d1eb | 4503 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4504 | "s,t,p", sreg, 0); |
8fc2e39e | 4505 | break; |
252b5132 | 4506 | } |
8fc2e39e | 4507 | used_at = 1; |
67c0d1eb RS |
4508 | set_at (sreg, 1); |
4509 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4510 | break; |
4511 | ||
4512 | case M_BLTL: | |
4513 | likely = 1; | |
4514 | case M_BLT: | |
4515 | if (treg == 0) | |
4516 | { | |
67c0d1eb | 4517 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4518 | break; |
252b5132 RH |
4519 | } |
4520 | if (sreg == 0) | |
4521 | { | |
67c0d1eb | 4522 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4523 | break; |
252b5132 | 4524 | } |
8fc2e39e | 4525 | used_at = 1; |
67c0d1eb RS |
4526 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4527 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4528 | break; |
4529 | ||
4530 | case M_BLTUL: | |
4531 | likely = 1; | |
4532 | case M_BLTU: | |
4533 | if (treg == 0) | |
4534 | goto do_false; | |
4535 | if (sreg == 0) | |
4536 | { | |
67c0d1eb | 4537 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4538 | "s,t,p", 0, treg); |
8fc2e39e | 4539 | break; |
252b5132 | 4540 | } |
8fc2e39e | 4541 | used_at = 1; |
67c0d1eb RS |
4542 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4543 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4544 | break; |
4545 | ||
5f74bc13 CD |
4546 | case M_DEXT: |
4547 | { | |
4548 | unsigned long pos; | |
4549 | unsigned long size; | |
4550 | ||
4551 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4552 | { | |
4553 | as_bad (_("Unsupported large constant")); | |
4554 | pos = size = 1; | |
4555 | } | |
4556 | else | |
4557 | { | |
4558 | pos = (unsigned long) imm_expr.X_add_number; | |
4559 | size = (unsigned long) imm2_expr.X_add_number; | |
4560 | } | |
4561 | ||
4562 | if (pos > 63) | |
4563 | { | |
4564 | as_bad (_("Improper position (%lu)"), pos); | |
4565 | pos = 1; | |
4566 | } | |
4567 | if (size == 0 || size > 64 | |
4568 | || (pos + size - 1) > 63) | |
4569 | { | |
4570 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4571 | size, pos); | |
4572 | size = 1; | |
4573 | } | |
4574 | ||
4575 | if (size <= 32 && pos < 32) | |
4576 | { | |
4577 | s = "dext"; | |
4578 | fmt = "t,r,+A,+C"; | |
4579 | } | |
4580 | else if (size <= 32) | |
4581 | { | |
4582 | s = "dextu"; | |
4583 | fmt = "t,r,+E,+H"; | |
4584 | } | |
4585 | else | |
4586 | { | |
4587 | s = "dextm"; | |
4588 | fmt = "t,r,+A,+G"; | |
4589 | } | |
67c0d1eb | 4590 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4591 | } |
8fc2e39e | 4592 | break; |
5f74bc13 CD |
4593 | |
4594 | case M_DINS: | |
4595 | { | |
4596 | unsigned long pos; | |
4597 | unsigned long size; | |
4598 | ||
4599 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4600 | { | |
4601 | as_bad (_("Unsupported large constant")); | |
4602 | pos = size = 1; | |
4603 | } | |
4604 | else | |
4605 | { | |
4606 | pos = (unsigned long) imm_expr.X_add_number; | |
4607 | size = (unsigned long) imm2_expr.X_add_number; | |
4608 | } | |
4609 | ||
4610 | if (pos > 63) | |
4611 | { | |
4612 | as_bad (_("Improper position (%lu)"), pos); | |
4613 | pos = 1; | |
4614 | } | |
4615 | if (size == 0 || size > 64 | |
4616 | || (pos + size - 1) > 63) | |
4617 | { | |
4618 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4619 | size, pos); | |
4620 | size = 1; | |
4621 | } | |
4622 | ||
4623 | if (pos < 32 && (pos + size - 1) < 32) | |
4624 | { | |
4625 | s = "dins"; | |
4626 | fmt = "t,r,+A,+B"; | |
4627 | } | |
4628 | else if (pos >= 32) | |
4629 | { | |
4630 | s = "dinsu"; | |
4631 | fmt = "t,r,+E,+F"; | |
4632 | } | |
4633 | else | |
4634 | { | |
4635 | s = "dinsm"; | |
4636 | fmt = "t,r,+A,+F"; | |
4637 | } | |
67c0d1eb RS |
4638 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4639 | pos + size - 1); | |
5f74bc13 | 4640 | } |
8fc2e39e | 4641 | break; |
5f74bc13 | 4642 | |
252b5132 RH |
4643 | case M_DDIV_3: |
4644 | dbl = 1; | |
4645 | case M_DIV_3: | |
4646 | s = "mflo"; | |
4647 | goto do_div3; | |
4648 | case M_DREM_3: | |
4649 | dbl = 1; | |
4650 | case M_REM_3: | |
4651 | s = "mfhi"; | |
4652 | do_div3: | |
4653 | if (treg == 0) | |
4654 | { | |
4655 | as_warn (_("Divide by zero.")); | |
4656 | if (mips_trap) | |
67c0d1eb | 4657 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4658 | else |
67c0d1eb | 4659 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4660 | break; |
252b5132 RH |
4661 | } |
4662 | ||
7d10b47d | 4663 | start_noreorder (); |
252b5132 RH |
4664 | if (mips_trap) |
4665 | { | |
67c0d1eb RS |
4666 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4667 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4668 | } |
4669 | else | |
4670 | { | |
4671 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4672 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4673 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4674 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4675 | } |
4676 | expr1.X_add_number = -1; | |
8fc2e39e | 4677 | used_at = 1; |
f6a22291 | 4678 | load_register (AT, &expr1, dbl); |
252b5132 | 4679 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4680 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4681 | if (dbl) |
4682 | { | |
4683 | expr1.X_add_number = 1; | |
f6a22291 | 4684 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4685 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4686 | } |
4687 | else | |
4688 | { | |
4689 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4690 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4691 | } |
4692 | if (mips_trap) | |
4693 | { | |
67c0d1eb | 4694 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4695 | /* We want to close the noreorder block as soon as possible, so |
4696 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4697 | end_noreorder (); |
252b5132 RH |
4698 | } |
4699 | else | |
4700 | { | |
4701 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4702 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4703 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4704 | |
4705 | /* We want to close the noreorder block as soon as possible, so | |
4706 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4707 | end_noreorder (); |
252b5132 | 4708 | |
67c0d1eb | 4709 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4710 | } |
67c0d1eb | 4711 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4712 | break; |
4713 | ||
4714 | case M_DIV_3I: | |
4715 | s = "div"; | |
4716 | s2 = "mflo"; | |
4717 | goto do_divi; | |
4718 | case M_DIVU_3I: | |
4719 | s = "divu"; | |
4720 | s2 = "mflo"; | |
4721 | goto do_divi; | |
4722 | case M_REM_3I: | |
4723 | s = "div"; | |
4724 | s2 = "mfhi"; | |
4725 | goto do_divi; | |
4726 | case M_REMU_3I: | |
4727 | s = "divu"; | |
4728 | s2 = "mfhi"; | |
4729 | goto do_divi; | |
4730 | case M_DDIV_3I: | |
4731 | dbl = 1; | |
4732 | s = "ddiv"; | |
4733 | s2 = "mflo"; | |
4734 | goto do_divi; | |
4735 | case M_DDIVU_3I: | |
4736 | dbl = 1; | |
4737 | s = "ddivu"; | |
4738 | s2 = "mflo"; | |
4739 | goto do_divi; | |
4740 | case M_DREM_3I: | |
4741 | dbl = 1; | |
4742 | s = "ddiv"; | |
4743 | s2 = "mfhi"; | |
4744 | goto do_divi; | |
4745 | case M_DREMU_3I: | |
4746 | dbl = 1; | |
4747 | s = "ddivu"; | |
4748 | s2 = "mfhi"; | |
4749 | do_divi: | |
4750 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4751 | { | |
4752 | as_warn (_("Divide by zero.")); | |
4753 | if (mips_trap) | |
67c0d1eb | 4754 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4755 | else |
67c0d1eb | 4756 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4757 | break; |
252b5132 RH |
4758 | } |
4759 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4760 | { | |
4761 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4762 | move_register (dreg, sreg); |
252b5132 | 4763 | else |
67c0d1eb | 4764 | move_register (dreg, 0); |
8fc2e39e | 4765 | break; |
252b5132 RH |
4766 | } |
4767 | if (imm_expr.X_op == O_constant | |
4768 | && imm_expr.X_add_number == -1 | |
4769 | && s[strlen (s) - 1] != 'u') | |
4770 | { | |
4771 | if (strcmp (s2, "mflo") == 0) | |
4772 | { | |
67c0d1eb | 4773 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4774 | } |
4775 | else | |
67c0d1eb | 4776 | move_register (dreg, 0); |
8fc2e39e | 4777 | break; |
252b5132 RH |
4778 | } |
4779 | ||
8fc2e39e | 4780 | used_at = 1; |
67c0d1eb RS |
4781 | load_register (AT, &imm_expr, dbl); |
4782 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4783 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4784 | break; |
4785 | ||
4786 | case M_DIVU_3: | |
4787 | s = "divu"; | |
4788 | s2 = "mflo"; | |
4789 | goto do_divu3; | |
4790 | case M_REMU_3: | |
4791 | s = "divu"; | |
4792 | s2 = "mfhi"; | |
4793 | goto do_divu3; | |
4794 | case M_DDIVU_3: | |
4795 | s = "ddivu"; | |
4796 | s2 = "mflo"; | |
4797 | goto do_divu3; | |
4798 | case M_DREMU_3: | |
4799 | s = "ddivu"; | |
4800 | s2 = "mfhi"; | |
4801 | do_divu3: | |
7d10b47d | 4802 | start_noreorder (); |
252b5132 RH |
4803 | if (mips_trap) |
4804 | { | |
67c0d1eb RS |
4805 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4806 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4807 | /* We want to close the noreorder block as soon as possible, so |
4808 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4809 | end_noreorder (); |
252b5132 RH |
4810 | } |
4811 | else | |
4812 | { | |
4813 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4814 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4815 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4816 | |
4817 | /* We want to close the noreorder block as soon as possible, so | |
4818 | that later insns are available for delay slot filling. */ | |
7d10b47d | 4819 | end_noreorder (); |
67c0d1eb | 4820 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4821 | } |
67c0d1eb | 4822 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4823 | break; |
252b5132 | 4824 | |
1abe91b1 MR |
4825 | case M_DLCA_AB: |
4826 | dbl = 1; | |
4827 | case M_LCA_AB: | |
4828 | call = 1; | |
4829 | goto do_la; | |
252b5132 RH |
4830 | case M_DLA_AB: |
4831 | dbl = 1; | |
4832 | case M_LA_AB: | |
1abe91b1 | 4833 | do_la: |
252b5132 RH |
4834 | /* Load the address of a symbol into a register. If breg is not |
4835 | zero, we then add a base register to it. */ | |
4836 | ||
3bec30a8 TS |
4837 | if (dbl && HAVE_32BIT_GPRS) |
4838 | as_warn (_("dla used to load 32-bit register")); | |
4839 | ||
c90bbe5b | 4840 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4841 | as_warn (_("la used to load 64-bit address")); |
4842 | ||
0c11417f MR |
4843 | if (offset_expr.X_op == O_constant |
4844 | && offset_expr.X_add_number >= -0x8000 | |
4845 | && offset_expr.X_add_number < 0x8000) | |
4846 | { | |
aed1a261 | 4847 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4848 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4849 | break; |
0c11417f MR |
4850 | } |
4851 | ||
b8285c27 | 4852 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4853 | { |
4854 | tempreg = AT; | |
4855 | used_at = 1; | |
4856 | } | |
4857 | else | |
4858 | { | |
4859 | tempreg = treg; | |
afdbd6d0 CD |
4860 | } |
4861 | ||
252b5132 RH |
4862 | if (offset_expr.X_op != O_symbol |
4863 | && offset_expr.X_op != O_constant) | |
4864 | { | |
4865 | as_bad (_("expression too complex")); | |
4866 | offset_expr.X_op = O_constant; | |
4867 | } | |
4868 | ||
252b5132 | 4869 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4870 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4871 | else if (mips_pic == NO_PIC) |
4872 | { | |
d6bc6245 | 4873 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4874 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4875 | Otherwise we want |
4876 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4877 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4878 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4879 | so we may as well always use the latter form. |
76b3015f | 4880 | |
6caf9ef4 TS |
4881 | With 64bit address space and a usable $at we want |
4882 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4883 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4884 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4885 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4886 | dsll32 $tempreg,0 | |
4887 | daddu $tempreg,$tempreg,$at | |
4888 | ||
4889 | If $at is already in use, we use a path which is suboptimal | |
4890 | on superscalar processors. | |
4891 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4892 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4893 | dsll $tempreg,16 | |
4894 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4895 | dsll $tempreg,16 | |
4896 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4897 | ||
4898 | For GP relative symbols in 64bit address space we can use | |
4899 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4900 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4901 | { |
6caf9ef4 TS |
4902 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4903 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4904 | { | |
4905 | relax_start (offset_expr.X_add_symbol); | |
4906 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4907 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4908 | relax_switch (); | |
4909 | } | |
d6bc6245 | 4910 | |
b8285c27 | 4911 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4912 | { |
67c0d1eb | 4913 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4914 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4915 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4916 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4917 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4918 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4919 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4920 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4921 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4922 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4923 | used_at = 1; |
4924 | } | |
4925 | else | |
4926 | { | |
67c0d1eb | 4927 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4928 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4929 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4930 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4931 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4932 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4933 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4934 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4935 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4936 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4937 | } |
6caf9ef4 TS |
4938 | |
4939 | if (mips_relax.sequence) | |
4940 | relax_end (); | |
98d3f06f KH |
4941 | } |
4942 | else | |
4943 | { | |
4944 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4945 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4946 | { |
4d7206a2 | 4947 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4948 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4949 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4950 | relax_switch (); |
98d3f06f | 4951 | } |
6943caf0 ILT |
4952 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4953 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4954 | macro_build_lui (&offset_expr, tempreg); |
4955 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4956 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4957 | if (mips_relax.sequence) |
4958 | relax_end (); | |
98d3f06f | 4959 | } |
252b5132 | 4960 | } |
f5040a92 | 4961 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4962 | { |
9117d219 NC |
4963 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4964 | ||
252b5132 RH |
4965 | /* If this is a reference to an external symbol, and there |
4966 | is no constant, we want | |
4967 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4968 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4969 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4970 | For a local symbol, we want |
4971 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4972 | nop | |
4973 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4974 | ||
4975 | If we have a small constant, and this is a reference to | |
4976 | an external symbol, we want | |
4977 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4978 | nop | |
4979 | addiu $tempreg,$tempreg,<constant> | |
4980 | For a local symbol, we want the same instruction | |
4981 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4982 | addiu instruction. | |
4983 | ||
4984 | If we have a large constant, and this is a reference to | |
4985 | an external symbol, we want | |
4986 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4987 | lui $at,<hiconstant> | |
4988 | addiu $at,$at,<loconstant> | |
4989 | addu $tempreg,$tempreg,$at | |
4990 | For a local symbol, we want the same instruction | |
4991 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4992 | addiu instruction. |
ed6fb7bd SC |
4993 | */ |
4994 | ||
4d7206a2 | 4995 | if (offset_expr.X_add_number == 0) |
252b5132 | 4996 | { |
4d7206a2 RS |
4997 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
4998 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4999 | ||
5000 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5001 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5002 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5003 | if (breg != 0) |
252b5132 RH |
5004 | { |
5005 | /* We're going to put in an addu instruction using | |
5006 | tempreg, so we may as well insert the nop right | |
5007 | now. */ | |
269137b2 | 5008 | load_delay_nop (); |
252b5132 | 5009 | } |
4d7206a2 | 5010 | relax_switch (); |
67c0d1eb RS |
5011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5012 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5013 | load_delay_nop (); |
67c0d1eb RS |
5014 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5015 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5016 | relax_end (); |
252b5132 RH |
5017 | /* FIXME: If breg == 0, and the next instruction uses |
5018 | $tempreg, then if this variant case is used an extra | |
5019 | nop will be generated. */ | |
5020 | } | |
4d7206a2 RS |
5021 | else if (offset_expr.X_add_number >= -0x8000 |
5022 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5023 | { |
67c0d1eb | 5024 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5025 | load_delay_nop (); |
67c0d1eb | 5026 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5027 | } |
5028 | else | |
5029 | { | |
4d7206a2 RS |
5030 | expr1.X_add_number = offset_expr.X_add_number; |
5031 | offset_expr.X_add_number = | |
5032 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5033 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5034 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5035 | /* If we are going to add in a base register, and the |
5036 | target register and the base register are the same, | |
5037 | then we are using AT as a temporary register. Since | |
5038 | we want to load the constant into AT, we add our | |
5039 | current AT (from the global offset table) and the | |
5040 | register into the register now, and pretend we were | |
5041 | not using a base register. */ | |
67c0d1eb | 5042 | if (breg == treg) |
252b5132 | 5043 | { |
269137b2 | 5044 | load_delay_nop (); |
67c0d1eb | 5045 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5046 | treg, AT, breg); |
252b5132 RH |
5047 | breg = 0; |
5048 | tempreg = treg; | |
252b5132 | 5049 | } |
f6a22291 | 5050 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5051 | used_at = 1; |
5052 | } | |
5053 | } | |
f5040a92 AO |
5054 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5055 | { | |
67c0d1eb | 5056 | int add_breg_early = 0; |
f5040a92 AO |
5057 | |
5058 | /* If this is a reference to an external, and there is no | |
5059 | constant, or local symbol (*), with or without a | |
5060 | constant, we want | |
5061 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5062 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5063 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5064 | ||
5065 | If we have a small constant, and this is a reference to | |
5066 | an external symbol, we want | |
5067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5068 | addiu $tempreg,$tempreg,<constant> | |
5069 | ||
5070 | If we have a large constant, and this is a reference to | |
5071 | an external symbol, we want | |
5072 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5073 | lui $at,<hiconstant> | |
5074 | addiu $at,$at,<loconstant> | |
5075 | addu $tempreg,$tempreg,$at | |
5076 | ||
5077 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5078 | local symbols, even though it introduces an additional | |
5079 | instruction. */ | |
5080 | ||
f5040a92 AO |
5081 | if (offset_expr.X_add_number) |
5082 | { | |
4d7206a2 | 5083 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5084 | offset_expr.X_add_number = 0; |
5085 | ||
4d7206a2 | 5086 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5087 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5088 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5089 | |
5090 | if (expr1.X_add_number >= -0x8000 | |
5091 | && expr1.X_add_number < 0x8000) | |
5092 | { | |
67c0d1eb RS |
5093 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5094 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5095 | } |
ecd13cd3 | 5096 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5097 | { |
5098 | int dreg; | |
5099 | ||
5100 | /* If we are going to add in a base register, and the | |
5101 | target register and the base register are the same, | |
5102 | then we are using AT as a temporary register. Since | |
5103 | we want to load the constant into AT, we add our | |
5104 | current AT (from the global offset table) and the | |
5105 | register into the register now, and pretend we were | |
5106 | not using a base register. */ | |
5107 | if (breg != treg) | |
5108 | dreg = tempreg; | |
5109 | else | |
5110 | { | |
5111 | assert (tempreg == AT); | |
67c0d1eb RS |
5112 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5113 | treg, AT, breg); | |
f5040a92 | 5114 | dreg = treg; |
67c0d1eb | 5115 | add_breg_early = 1; |
f5040a92 AO |
5116 | } |
5117 | ||
f6a22291 | 5118 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5119 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5120 | dreg, dreg, AT); |
f5040a92 | 5121 | |
f5040a92 AO |
5122 | used_at = 1; |
5123 | } | |
5124 | else | |
5125 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5126 | ||
4d7206a2 | 5127 | relax_switch (); |
f5040a92 AO |
5128 | offset_expr.X_add_number = expr1.X_add_number; |
5129 | ||
67c0d1eb RS |
5130 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5131 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5132 | if (add_breg_early) | |
f5040a92 | 5133 | { |
67c0d1eb | 5134 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5135 | treg, tempreg, breg); |
f5040a92 AO |
5136 | breg = 0; |
5137 | tempreg = treg; | |
5138 | } | |
4d7206a2 | 5139 | relax_end (); |
f5040a92 | 5140 | } |
4d7206a2 | 5141 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5142 | { |
4d7206a2 | 5143 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5144 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5145 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5146 | relax_switch (); |
67c0d1eb RS |
5147 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5148 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5149 | relax_end (); |
f5040a92 | 5150 | } |
4d7206a2 | 5151 | else |
f5040a92 | 5152 | { |
67c0d1eb RS |
5153 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5154 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5155 | } |
5156 | } | |
5157 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5158 | { |
67c0d1eb | 5159 | int gpdelay; |
9117d219 NC |
5160 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5161 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5162 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5163 | |
5164 | /* This is the large GOT case. If this is a reference to an | |
5165 | external symbol, and there is no constant, we want | |
5166 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5167 | addu $tempreg,$tempreg,$gp | |
5168 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5169 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5170 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5171 | addu $tempreg,$tempreg,$gp | |
5172 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5173 | For a local symbol, we want |
5174 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5175 | nop | |
5176 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5177 | ||
5178 | If we have a small constant, and this is a reference to | |
5179 | an external symbol, we want | |
5180 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5181 | addu $tempreg,$tempreg,$gp | |
5182 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5183 | nop | |
5184 | addiu $tempreg,$tempreg,<constant> | |
5185 | For a local symbol, we want | |
5186 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5187 | nop | |
5188 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5189 | ||
5190 | If we have a large constant, and this is a reference to | |
5191 | an external symbol, we want | |
5192 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5193 | addu $tempreg,$tempreg,$gp | |
5194 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5195 | lui $at,<hiconstant> | |
5196 | addiu $at,$at,<loconstant> | |
5197 | addu $tempreg,$tempreg,$at | |
5198 | For a local symbol, we want | |
5199 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5200 | lui $at,<hiconstant> | |
5201 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5202 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5203 | */ |
438c16b8 | 5204 | |
252b5132 RH |
5205 | expr1.X_add_number = offset_expr.X_add_number; |
5206 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5207 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5208 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5209 | if (expr1.X_add_number == 0 && breg == 0 |
5210 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5211 | { |
5212 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5213 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5214 | } | |
67c0d1eb RS |
5215 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5216 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5217 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5218 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5219 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5220 | if (expr1.X_add_number == 0) |
5221 | { | |
67c0d1eb | 5222 | if (breg != 0) |
252b5132 RH |
5223 | { |
5224 | /* We're going to put in an addu instruction using | |
5225 | tempreg, so we may as well insert the nop right | |
5226 | now. */ | |
269137b2 | 5227 | load_delay_nop (); |
252b5132 | 5228 | } |
252b5132 RH |
5229 | } |
5230 | else if (expr1.X_add_number >= -0x8000 | |
5231 | && expr1.X_add_number < 0x8000) | |
5232 | { | |
269137b2 | 5233 | load_delay_nop (); |
67c0d1eb | 5234 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5235 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5236 | } |
5237 | else | |
5238 | { | |
67c0d1eb | 5239 | int dreg; |
252b5132 RH |
5240 | |
5241 | /* If we are going to add in a base register, and the | |
5242 | target register and the base register are the same, | |
5243 | then we are using AT as a temporary register. Since | |
5244 | we want to load the constant into AT, we add our | |
5245 | current AT (from the global offset table) and the | |
5246 | register into the register now, and pretend we were | |
5247 | not using a base register. */ | |
5248 | if (breg != treg) | |
67c0d1eb | 5249 | dreg = tempreg; |
252b5132 RH |
5250 | else |
5251 | { | |
5252 | assert (tempreg == AT); | |
269137b2 | 5253 | load_delay_nop (); |
67c0d1eb | 5254 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5255 | treg, AT, breg); |
252b5132 | 5256 | dreg = treg; |
252b5132 RH |
5257 | } |
5258 | ||
f6a22291 | 5259 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5260 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5261 | |
252b5132 RH |
5262 | used_at = 1; |
5263 | } | |
4d7206a2 RS |
5264 | offset_expr.X_add_number = |
5265 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5266 | relax_switch (); | |
252b5132 | 5267 | |
67c0d1eb | 5268 | if (gpdelay) |
252b5132 RH |
5269 | { |
5270 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5271 | the first instruction on the main stream does not. */ |
67c0d1eb | 5272 | macro_build (NULL, "nop", ""); |
252b5132 | 5273 | } |
ed6fb7bd | 5274 | |
67c0d1eb RS |
5275 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5276 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5277 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5278 | && expr1.X_add_number < 0x8000) |
5279 | { | |
269137b2 | 5280 | load_delay_nop (); |
67c0d1eb RS |
5281 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5282 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5283 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5284 | register, the external symbol case ended with a load, |
5285 | so if the symbol turns out to not be external, and | |
5286 | the next instruction uses tempreg, an unnecessary nop | |
5287 | will be inserted. */ | |
252b5132 RH |
5288 | } |
5289 | else | |
5290 | { | |
5291 | if (breg == treg) | |
5292 | { | |
5293 | /* We must add in the base register now, as in the | |
f5040a92 | 5294 | external symbol case. */ |
252b5132 | 5295 | assert (tempreg == AT); |
269137b2 | 5296 | load_delay_nop (); |
67c0d1eb | 5297 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5298 | treg, AT, breg); |
252b5132 RH |
5299 | tempreg = treg; |
5300 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5301 | it in in both cases. */ |
252b5132 RH |
5302 | breg = 0; |
5303 | } | |
5304 | ||
67c0d1eb RS |
5305 | macro_build_lui (&expr1, AT); |
5306 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5307 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5308 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5309 | tempreg, tempreg, AT); |
8fc2e39e | 5310 | used_at = 1; |
252b5132 | 5311 | } |
4d7206a2 | 5312 | relax_end (); |
252b5132 | 5313 | } |
f5040a92 AO |
5314 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5315 | { | |
f5040a92 AO |
5316 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5317 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5318 | int add_breg_early = 0; |
f5040a92 AO |
5319 | |
5320 | /* This is the large GOT case. If this is a reference to an | |
5321 | external symbol, and there is no constant, we want | |
5322 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5323 | add $tempreg,$tempreg,$gp | |
5324 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5325 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5326 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5327 | add $tempreg,$tempreg,$gp | |
5328 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5329 | ||
5330 | If we have a small constant, and this is a reference to | |
5331 | an external symbol, we want | |
5332 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5333 | add $tempreg,$tempreg,$gp | |
5334 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5335 | addi $tempreg,$tempreg,<constant> | |
5336 | ||
5337 | If we have a large constant, and this is a reference to | |
5338 | an external symbol, we want | |
5339 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5340 | addu $tempreg,$tempreg,$gp | |
5341 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5342 | lui $at,<hiconstant> | |
5343 | addi $at,$at,<loconstant> | |
5344 | add $tempreg,$tempreg,$at | |
5345 | ||
5346 | If we have NewABI, and we know it's a local symbol, we want | |
5347 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5348 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5349 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5350 | ||
4d7206a2 | 5351 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5352 | |
4d7206a2 | 5353 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5354 | offset_expr.X_add_number = 0; |
5355 | ||
1abe91b1 MR |
5356 | if (expr1.X_add_number == 0 && breg == 0 |
5357 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5358 | { |
5359 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5360 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5361 | } | |
67c0d1eb RS |
5362 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5364 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5365 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5366 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5367 | |
5368 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5369 | ; |
f5040a92 AO |
5370 | else if (expr1.X_add_number >= -0x8000 |
5371 | && expr1.X_add_number < 0x8000) | |
5372 | { | |
67c0d1eb | 5373 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5374 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5375 | } |
ecd13cd3 | 5376 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5377 | { |
5378 | int dreg; | |
5379 | ||
5380 | /* If we are going to add in a base register, and the | |
5381 | target register and the base register are the same, | |
5382 | then we are using AT as a temporary register. Since | |
5383 | we want to load the constant into AT, we add our | |
5384 | current AT (from the global offset table) and the | |
5385 | register into the register now, and pretend we were | |
5386 | not using a base register. */ | |
5387 | if (breg != treg) | |
5388 | dreg = tempreg; | |
5389 | else | |
5390 | { | |
5391 | assert (tempreg == AT); | |
67c0d1eb | 5392 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5393 | treg, AT, breg); |
f5040a92 | 5394 | dreg = treg; |
67c0d1eb | 5395 | add_breg_early = 1; |
f5040a92 AO |
5396 | } |
5397 | ||
f6a22291 | 5398 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5399 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5400 | |
f5040a92 AO |
5401 | used_at = 1; |
5402 | } | |
5403 | else | |
5404 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5405 | ||
4d7206a2 | 5406 | relax_switch (); |
f5040a92 | 5407 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5408 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5409 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5410 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5411 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5412 | if (add_breg_early) | |
f5040a92 | 5413 | { |
67c0d1eb | 5414 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5415 | treg, tempreg, breg); |
f5040a92 AO |
5416 | breg = 0; |
5417 | tempreg = treg; | |
5418 | } | |
4d7206a2 | 5419 | relax_end (); |
f5040a92 | 5420 | } |
252b5132 RH |
5421 | else |
5422 | abort (); | |
5423 | ||
5424 | if (breg != 0) | |
aed1a261 | 5425 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5426 | break; |
5427 | ||
5428 | case M_J_A: | |
5429 | /* The j instruction may not be used in PIC code, since it | |
5430 | requires an absolute address. We convert it to a b | |
5431 | instruction. */ | |
5432 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5433 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5434 | else |
67c0d1eb | 5435 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5436 | break; |
252b5132 RH |
5437 | |
5438 | /* The jal instructions must be handled as macros because when | |
5439 | generating PIC code they expand to multi-instruction | |
5440 | sequences. Normally they are simple instructions. */ | |
5441 | case M_JAL_1: | |
5442 | dreg = RA; | |
5443 | /* Fall through. */ | |
5444 | case M_JAL_2: | |
3e722fb5 | 5445 | if (mips_pic == NO_PIC) |
67c0d1eb | 5446 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5447 | else if (mips_pic == SVR4_PIC) |
5448 | { | |
5449 | if (sreg != PIC_CALL_REG) | |
5450 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5451 | |
67c0d1eb | 5452 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5453 | if (! HAVE_NEWABI) |
252b5132 | 5454 | { |
6478892d TS |
5455 | if (mips_cprestore_offset < 0) |
5456 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5457 | else | |
5458 | { | |
7a621144 DJ |
5459 | if (! mips_frame_reg_valid) |
5460 | { | |
5461 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5462 | /* Quiet this warning. */ | |
5463 | mips_frame_reg_valid = 1; | |
5464 | } | |
5465 | if (! mips_cprestore_valid) | |
5466 | { | |
5467 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5468 | /* Quiet this warning. */ | |
5469 | mips_cprestore_valid = 1; | |
5470 | } | |
6478892d | 5471 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5472 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5473 | mips_gp_register, |
256ab948 TS |
5474 | mips_frame_reg, |
5475 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5476 | } |
252b5132 RH |
5477 | } |
5478 | } | |
5479 | else | |
5480 | abort (); | |
5481 | ||
8fc2e39e | 5482 | break; |
252b5132 RH |
5483 | |
5484 | case M_JAL_A: | |
5485 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5486 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5487 | else if (mips_pic == SVR4_PIC) |
5488 | { | |
5489 | /* If this is a reference to an external symbol, and we are | |
5490 | using a small GOT, we want | |
5491 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5492 | nop | |
f9419b05 | 5493 | jalr $ra,$25 |
252b5132 RH |
5494 | nop |
5495 | lw $gp,cprestore($sp) | |
5496 | The cprestore value is set using the .cprestore | |
5497 | pseudo-op. If we are using a big GOT, we want | |
5498 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5499 | addu $25,$25,$gp | |
5500 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5501 | nop | |
f9419b05 | 5502 | jalr $ra,$25 |
252b5132 RH |
5503 | nop |
5504 | lw $gp,cprestore($sp) | |
5505 | If the symbol is not external, we want | |
5506 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5507 | nop | |
5508 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5509 | jalr $ra,$25 |
252b5132 | 5510 | nop |
438c16b8 | 5511 | lw $gp,cprestore($sp) |
f5040a92 AO |
5512 | |
5513 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5514 | sequences above, minus nops, unless the symbol is local, | |
5515 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5516 | GOT_DISP. */ | |
438c16b8 | 5517 | if (HAVE_NEWABI) |
252b5132 | 5518 | { |
f5040a92 AO |
5519 | if (! mips_big_got) |
5520 | { | |
4d7206a2 | 5521 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5522 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5523 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5524 | mips_gp_register); |
4d7206a2 | 5525 | relax_switch (); |
67c0d1eb RS |
5526 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5527 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5528 | mips_gp_register); |
5529 | relax_end (); | |
f5040a92 AO |
5530 | } |
5531 | else | |
5532 | { | |
4d7206a2 | 5533 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5534 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5535 | BFD_RELOC_MIPS_CALL_HI16); | |
5536 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5537 | PIC_CALL_REG, mips_gp_register); | |
5538 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5539 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5540 | PIC_CALL_REG); | |
4d7206a2 | 5541 | relax_switch (); |
67c0d1eb RS |
5542 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5543 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5544 | mips_gp_register); | |
5545 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5546 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5547 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5548 | relax_end (); |
f5040a92 | 5549 | } |
684022ea | 5550 | |
67c0d1eb | 5551 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5552 | } |
5553 | else | |
5554 | { | |
4d7206a2 | 5555 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5556 | if (! mips_big_got) |
5557 | { | |
67c0d1eb RS |
5558 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5559 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5560 | mips_gp_register); |
269137b2 | 5561 | load_delay_nop (); |
4d7206a2 | 5562 | relax_switch (); |
438c16b8 | 5563 | } |
252b5132 | 5564 | else |
252b5132 | 5565 | { |
67c0d1eb RS |
5566 | int gpdelay; |
5567 | ||
5568 | gpdelay = reg_needs_delay (mips_gp_register); | |
5569 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5570 | BFD_RELOC_MIPS_CALL_HI16); | |
5571 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5572 | PIC_CALL_REG, mips_gp_register); | |
5573 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5574 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5575 | PIC_CALL_REG); | |
269137b2 | 5576 | load_delay_nop (); |
4d7206a2 | 5577 | relax_switch (); |
67c0d1eb RS |
5578 | if (gpdelay) |
5579 | macro_build (NULL, "nop", ""); | |
252b5132 | 5580 | } |
67c0d1eb RS |
5581 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5582 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5583 | mips_gp_register); |
269137b2 | 5584 | load_delay_nop (); |
67c0d1eb RS |
5585 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5586 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5587 | relax_end (); |
67c0d1eb | 5588 | macro_build_jalr (&offset_expr); |
438c16b8 | 5589 | |
6478892d TS |
5590 | if (mips_cprestore_offset < 0) |
5591 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5592 | else | |
5593 | { | |
7a621144 DJ |
5594 | if (! mips_frame_reg_valid) |
5595 | { | |
5596 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5597 | /* Quiet this warning. */ | |
5598 | mips_frame_reg_valid = 1; | |
5599 | } | |
5600 | if (! mips_cprestore_valid) | |
5601 | { | |
5602 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5603 | /* Quiet this warning. */ | |
5604 | mips_cprestore_valid = 1; | |
5605 | } | |
6478892d | 5606 | if (mips_opts.noreorder) |
67c0d1eb | 5607 | macro_build (NULL, "nop", ""); |
6478892d | 5608 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5609 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5610 | mips_gp_register, |
256ab948 TS |
5611 | mips_frame_reg, |
5612 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5613 | } |
252b5132 RH |
5614 | } |
5615 | } | |
252b5132 RH |
5616 | else |
5617 | abort (); | |
5618 | ||
8fc2e39e | 5619 | break; |
252b5132 RH |
5620 | |
5621 | case M_LB_AB: | |
5622 | s = "lb"; | |
5623 | goto ld; | |
5624 | case M_LBU_AB: | |
5625 | s = "lbu"; | |
5626 | goto ld; | |
5627 | case M_LH_AB: | |
5628 | s = "lh"; | |
5629 | goto ld; | |
5630 | case M_LHU_AB: | |
5631 | s = "lhu"; | |
5632 | goto ld; | |
5633 | case M_LW_AB: | |
5634 | s = "lw"; | |
5635 | goto ld; | |
5636 | case M_LWC0_AB: | |
5637 | s = "lwc0"; | |
bdaaa2e1 | 5638 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5639 | coproc = 1; |
5640 | goto ld; | |
5641 | case M_LWC1_AB: | |
5642 | s = "lwc1"; | |
bdaaa2e1 | 5643 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5644 | coproc = 1; |
5645 | goto ld; | |
5646 | case M_LWC2_AB: | |
5647 | s = "lwc2"; | |
bdaaa2e1 | 5648 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5649 | coproc = 1; |
5650 | goto ld; | |
5651 | case M_LWC3_AB: | |
5652 | s = "lwc3"; | |
bdaaa2e1 | 5653 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5654 | coproc = 1; |
5655 | goto ld; | |
5656 | case M_LWL_AB: | |
5657 | s = "lwl"; | |
5658 | lr = 1; | |
5659 | goto ld; | |
5660 | case M_LWR_AB: | |
5661 | s = "lwr"; | |
5662 | lr = 1; | |
5663 | goto ld; | |
5664 | case M_LDC1_AB: | |
fef14a42 | 5665 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5666 | { |
5667 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5668 | break; |
252b5132 RH |
5669 | } |
5670 | s = "ldc1"; | |
bdaaa2e1 | 5671 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5672 | coproc = 1; |
5673 | goto ld; | |
5674 | case M_LDC2_AB: | |
5675 | s = "ldc2"; | |
bdaaa2e1 | 5676 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5677 | coproc = 1; |
5678 | goto ld; | |
5679 | case M_LDC3_AB: | |
5680 | s = "ldc3"; | |
bdaaa2e1 | 5681 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5682 | coproc = 1; |
5683 | goto ld; | |
5684 | case M_LDL_AB: | |
5685 | s = "ldl"; | |
5686 | lr = 1; | |
5687 | goto ld; | |
5688 | case M_LDR_AB: | |
5689 | s = "ldr"; | |
5690 | lr = 1; | |
5691 | goto ld; | |
5692 | case M_LL_AB: | |
5693 | s = "ll"; | |
5694 | goto ld; | |
5695 | case M_LLD_AB: | |
5696 | s = "lld"; | |
5697 | goto ld; | |
5698 | case M_LWU_AB: | |
5699 | s = "lwu"; | |
5700 | ld: | |
8fc2e39e | 5701 | if (breg == treg || coproc || lr) |
252b5132 RH |
5702 | { |
5703 | tempreg = AT; | |
5704 | used_at = 1; | |
5705 | } | |
5706 | else | |
5707 | { | |
5708 | tempreg = treg; | |
252b5132 RH |
5709 | } |
5710 | goto ld_st; | |
5711 | case M_SB_AB: | |
5712 | s = "sb"; | |
5713 | goto st; | |
5714 | case M_SH_AB: | |
5715 | s = "sh"; | |
5716 | goto st; | |
5717 | case M_SW_AB: | |
5718 | s = "sw"; | |
5719 | goto st; | |
5720 | case M_SWC0_AB: | |
5721 | s = "swc0"; | |
bdaaa2e1 | 5722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5723 | coproc = 1; |
5724 | goto st; | |
5725 | case M_SWC1_AB: | |
5726 | s = "swc1"; | |
bdaaa2e1 | 5727 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5728 | coproc = 1; |
5729 | goto st; | |
5730 | case M_SWC2_AB: | |
5731 | s = "swc2"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto st; | |
5735 | case M_SWC3_AB: | |
5736 | s = "swc3"; | |
bdaaa2e1 | 5737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5738 | coproc = 1; |
5739 | goto st; | |
5740 | case M_SWL_AB: | |
5741 | s = "swl"; | |
5742 | goto st; | |
5743 | case M_SWR_AB: | |
5744 | s = "swr"; | |
5745 | goto st; | |
5746 | case M_SC_AB: | |
5747 | s = "sc"; | |
5748 | goto st; | |
5749 | case M_SCD_AB: | |
5750 | s = "scd"; | |
5751 | goto st; | |
5752 | case M_SDC1_AB: | |
fef14a42 | 5753 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5754 | { |
5755 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5756 | break; |
252b5132 RH |
5757 | } |
5758 | s = "sdc1"; | |
5759 | coproc = 1; | |
bdaaa2e1 | 5760 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5761 | goto st; |
5762 | case M_SDC2_AB: | |
5763 | s = "sdc2"; | |
bdaaa2e1 | 5764 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5765 | coproc = 1; |
5766 | goto st; | |
5767 | case M_SDC3_AB: | |
5768 | s = "sdc3"; | |
bdaaa2e1 | 5769 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5770 | coproc = 1; |
5771 | goto st; | |
5772 | case M_SDL_AB: | |
5773 | s = "sdl"; | |
5774 | goto st; | |
5775 | case M_SDR_AB: | |
5776 | s = "sdr"; | |
5777 | st: | |
8fc2e39e TS |
5778 | tempreg = AT; |
5779 | used_at = 1; | |
252b5132 | 5780 | ld_st: |
bdaaa2e1 | 5781 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5782 | if (mask == M_LWC1_AB |
5783 | || mask == M_SWC1_AB | |
5784 | || mask == M_LDC1_AB | |
5785 | || mask == M_SDC1_AB | |
5786 | || mask == M_L_DAB | |
5787 | || mask == M_S_DAB) | |
5788 | fmt = "T,o(b)"; | |
5789 | else if (coproc) | |
5790 | fmt = "E,o(b)"; | |
5791 | else | |
5792 | fmt = "t,o(b)"; | |
5793 | ||
5794 | if (offset_expr.X_op != O_constant | |
5795 | && offset_expr.X_op != O_symbol) | |
5796 | { | |
5797 | as_bad (_("expression too complex")); | |
5798 | offset_expr.X_op = O_constant; | |
5799 | } | |
5800 | ||
2051e8c4 MR |
5801 | if (HAVE_32BIT_ADDRESSES |
5802 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5803 | as_bad (_("Number (0x%lx%08lx) larger than 32 bits"), | |
5804 | (unsigned long) (offset_expr.X_add_number >> 32), | |
5805 | (unsigned long) (offset_expr.X_add_number & 0xffffffff)); | |
5806 | ||
252b5132 RH |
5807 | /* A constant expression in PIC code can be handled just as it |
5808 | is in non PIC code. */ | |
aed1a261 RS |
5809 | if (offset_expr.X_op == O_constant) |
5810 | { | |
aed1a261 RS |
5811 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
5812 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 5813 | normalize_address_expr (&expr1); |
aed1a261 RS |
5814 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
5815 | if (breg != 0) | |
5816 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5817 | tempreg, tempreg, breg); | |
5818 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5819 | } | |
5820 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5821 | { |
5822 | /* If this is a reference to a GP relative symbol, and there | |
5823 | is no base register, we want | |
cdf6fd85 | 5824 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5825 | Otherwise, if there is no base register, we want |
5826 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5827 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5828 | If we have a constant, we need two instructions anyhow, | |
5829 | so we always use the latter form. | |
5830 | ||
5831 | If we have a base register, and this is a reference to a | |
5832 | GP relative symbol, we want | |
5833 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5834 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5835 | Otherwise we want |
5836 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5837 | addu $tempreg,$tempreg,$breg | |
5838 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5839 | With a constant we always use the latter case. |
76b3015f | 5840 | |
d6bc6245 TS |
5841 | With 64bit address space and no base register and $at usable, |
5842 | we want | |
5843 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5844 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5845 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5846 | dsll32 $tempreg,0 | |
5847 | daddu $tempreg,$at | |
5848 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5849 | If we have a base register, we want | |
5850 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5851 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5852 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5853 | daddu $at,$breg | |
5854 | dsll32 $tempreg,0 | |
5855 | daddu $tempreg,$at | |
5856 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5857 | ||
5858 | Without $at we can't generate the optimal path for superscalar | |
5859 | processors here since this would require two temporary registers. | |
5860 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5861 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5862 | dsll $tempreg,16 | |
5863 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5864 | dsll $tempreg,16 | |
5865 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5866 | If we have a base register, we want | |
5867 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5868 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5869 | dsll $tempreg,16 | |
5870 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5871 | dsll $tempreg,16 | |
5872 | daddu $tempreg,$tempreg,$breg | |
5873 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5874 | |
6caf9ef4 | 5875 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5876 | the same sequence as in 32bit address space. */ |
5877 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5878 | { |
aed1a261 | 5879 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5880 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5881 | { | |
5882 | relax_start (offset_expr.X_add_symbol); | |
5883 | if (breg == 0) | |
5884 | { | |
5885 | macro_build (&offset_expr, s, fmt, treg, | |
5886 | BFD_RELOC_GPREL16, mips_gp_register); | |
5887 | } | |
5888 | else | |
5889 | { | |
5890 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5891 | tempreg, breg, mips_gp_register); | |
5892 | macro_build (&offset_expr, s, fmt, treg, | |
5893 | BFD_RELOC_GPREL16, tempreg); | |
5894 | } | |
5895 | relax_switch (); | |
5896 | } | |
d6bc6245 | 5897 | |
b8285c27 | 5898 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5899 | { |
67c0d1eb RS |
5900 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5901 | BFD_RELOC_MIPS_HIGHEST); | |
5902 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5903 | BFD_RELOC_HI16_S); | |
5904 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5905 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5906 | if (breg != 0) |
67c0d1eb RS |
5907 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5908 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5909 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5910 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5911 | tempreg); | |
d6bc6245 TS |
5912 | used_at = 1; |
5913 | } | |
5914 | else | |
5915 | { | |
67c0d1eb RS |
5916 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5917 | BFD_RELOC_MIPS_HIGHEST); | |
5918 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5919 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5920 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5921 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5922 | tempreg, BFD_RELOC_HI16_S); | |
5923 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5924 | if (breg != 0) |
67c0d1eb | 5925 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5926 | tempreg, tempreg, breg); |
67c0d1eb | 5927 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5928 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5929 | } |
6caf9ef4 TS |
5930 | |
5931 | if (mips_relax.sequence) | |
5932 | relax_end (); | |
8fc2e39e | 5933 | break; |
d6bc6245 | 5934 | } |
256ab948 | 5935 | |
252b5132 RH |
5936 | if (breg == 0) |
5937 | { | |
67c0d1eb | 5938 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5939 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5940 | { |
4d7206a2 | 5941 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5942 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5943 | mips_gp_register); | |
4d7206a2 | 5944 | relax_switch (); |
252b5132 | 5945 | } |
67c0d1eb RS |
5946 | macro_build_lui (&offset_expr, tempreg); |
5947 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5948 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5949 | if (mips_relax.sequence) |
5950 | relax_end (); | |
252b5132 RH |
5951 | } |
5952 | else | |
5953 | { | |
67c0d1eb | 5954 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5955 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5956 | { |
4d7206a2 | 5957 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5958 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5959 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5960 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5961 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5962 | relax_switch (); |
252b5132 | 5963 | } |
67c0d1eb RS |
5964 | macro_build_lui (&offset_expr, tempreg); |
5965 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5966 | tempreg, tempreg, breg); |
67c0d1eb | 5967 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5968 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5969 | if (mips_relax.sequence) |
5970 | relax_end (); | |
252b5132 RH |
5971 | } |
5972 | } | |
5973 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5974 | { | |
ed6fb7bd | 5975 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5976 | |
252b5132 RH |
5977 | /* If this is a reference to an external symbol, we want |
5978 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5979 | nop | |
5980 | <op> $treg,0($tempreg) | |
5981 | Otherwise we want | |
5982 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5983 | nop | |
5984 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5985 | <op> $treg,0($tempreg) | |
f5040a92 AO |
5986 | |
5987 | For NewABI, we want | |
5988 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5989 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
5990 | ||
252b5132 RH |
5991 | If there is a base register, we add it to $tempreg before |
5992 | the <op>. If there is a constant, we stick it in the | |
5993 | <op> instruction. We don't handle constants larger than | |
5994 | 16 bits, because we have no way to load the upper 16 bits | |
5995 | (actually, we could handle them for the subset of cases | |
5996 | in which we are not using $at). */ | |
5997 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
5998 | if (HAVE_NEWABI) |
5999 | { | |
67c0d1eb RS |
6000 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6001 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6002 | if (breg != 0) |
67c0d1eb | 6003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6004 | tempreg, tempreg, breg); |
67c0d1eb | 6005 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6006 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6007 | break; |
6008 | } | |
252b5132 RH |
6009 | expr1.X_add_number = offset_expr.X_add_number; |
6010 | offset_expr.X_add_number = 0; | |
6011 | if (expr1.X_add_number < -0x8000 | |
6012 | || expr1.X_add_number >= 0x8000) | |
6013 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6014 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6015 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6016 | load_delay_nop (); |
4d7206a2 RS |
6017 | relax_start (offset_expr.X_add_symbol); |
6018 | relax_switch (); | |
67c0d1eb RS |
6019 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6020 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6021 | relax_end (); |
252b5132 | 6022 | if (breg != 0) |
67c0d1eb | 6023 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6024 | tempreg, tempreg, breg); |
67c0d1eb | 6025 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6026 | } |
f5040a92 | 6027 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6028 | { |
67c0d1eb | 6029 | int gpdelay; |
252b5132 RH |
6030 | |
6031 | /* If this is a reference to an external symbol, we want | |
6032 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6033 | addu $tempreg,$tempreg,$gp | |
6034 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6035 | <op> $treg,0($tempreg) | |
6036 | Otherwise we want | |
6037 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6038 | nop | |
6039 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6040 | <op> $treg,0($tempreg) | |
6041 | If there is a base register, we add it to $tempreg before | |
6042 | the <op>. If there is a constant, we stick it in the | |
6043 | <op> instruction. We don't handle constants larger than | |
6044 | 16 bits, because we have no way to load the upper 16 bits | |
6045 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6046 | in which we are not using $at). */ |
252b5132 RH |
6047 | assert (offset_expr.X_op == O_symbol); |
6048 | expr1.X_add_number = offset_expr.X_add_number; | |
6049 | offset_expr.X_add_number = 0; | |
6050 | if (expr1.X_add_number < -0x8000 | |
6051 | || expr1.X_add_number >= 0x8000) | |
6052 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6053 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6054 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6055 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6056 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6058 | mips_gp_register); | |
6059 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6060 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6061 | relax_switch (); |
67c0d1eb RS |
6062 | if (gpdelay) |
6063 | macro_build (NULL, "nop", ""); | |
6064 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6065 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6066 | load_delay_nop (); |
67c0d1eb RS |
6067 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6068 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6069 | relax_end (); |
6070 | ||
252b5132 | 6071 | if (breg != 0) |
67c0d1eb | 6072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6073 | tempreg, tempreg, breg); |
67c0d1eb | 6074 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6075 | } |
f5040a92 AO |
6076 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6077 | { | |
f5040a92 AO |
6078 | /* If this is a reference to an external symbol, we want |
6079 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6080 | add $tempreg,$tempreg,$gp | |
6081 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6082 | <op> $treg,<ofst>($tempreg) | |
6083 | Otherwise, for local symbols, we want: | |
6084 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6085 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6086 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6087 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6088 | offset_expr.X_add_number = 0; |
6089 | if (expr1.X_add_number < -0x8000 | |
6090 | || expr1.X_add_number >= 0x8000) | |
6091 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6092 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6093 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6094 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6095 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6096 | mips_gp_register); | |
6097 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6098 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6099 | if (breg != 0) |
67c0d1eb | 6100 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6101 | tempreg, tempreg, breg); |
67c0d1eb | 6102 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6103 | |
4d7206a2 | 6104 | relax_switch (); |
f5040a92 | 6105 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6106 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6107 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6108 | if (breg != 0) |
67c0d1eb | 6109 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6110 | tempreg, tempreg, breg); |
67c0d1eb | 6111 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6112 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6113 | relax_end (); |
f5040a92 | 6114 | } |
252b5132 RH |
6115 | else |
6116 | abort (); | |
6117 | ||
252b5132 RH |
6118 | break; |
6119 | ||
6120 | case M_LI: | |
6121 | case M_LI_S: | |
67c0d1eb | 6122 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6123 | break; |
252b5132 RH |
6124 | |
6125 | case M_DLI: | |
67c0d1eb | 6126 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6127 | break; |
252b5132 RH |
6128 | |
6129 | case M_LI_SS: | |
6130 | if (imm_expr.X_op == O_constant) | |
6131 | { | |
8fc2e39e | 6132 | used_at = 1; |
67c0d1eb RS |
6133 | load_register (AT, &imm_expr, 0); |
6134 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6135 | break; |
6136 | } | |
6137 | else | |
6138 | { | |
6139 | assert (offset_expr.X_op == O_symbol | |
6140 | && strcmp (segment_name (S_GET_SEGMENT | |
6141 | (offset_expr.X_add_symbol)), | |
6142 | ".lit4") == 0 | |
6143 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6144 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6145 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6146 | break; |
252b5132 RH |
6147 | } |
6148 | ||
6149 | case M_LI_D: | |
ca4e0257 RS |
6150 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6151 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6152 | order 32 bits of the value and the low order 32 bits are either | |
6153 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6154 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6155 | { | |
ca4e0257 | 6156 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6157 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6158 | else |
6159 | { | |
6160 | int hreg, lreg; | |
6161 | ||
6162 | if (target_big_endian) | |
6163 | { | |
6164 | hreg = treg; | |
6165 | lreg = treg + 1; | |
6166 | } | |
6167 | else | |
6168 | { | |
6169 | hreg = treg + 1; | |
6170 | lreg = treg; | |
6171 | } | |
6172 | ||
6173 | if (hreg <= 31) | |
67c0d1eb | 6174 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6175 | if (lreg <= 31) |
6176 | { | |
6177 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6178 | move_register (lreg, 0); |
252b5132 RH |
6179 | else |
6180 | { | |
6181 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6182 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6183 | } |
6184 | } | |
6185 | } | |
8fc2e39e | 6186 | break; |
252b5132 RH |
6187 | } |
6188 | ||
6189 | /* We know that sym is in the .rdata section. First we get the | |
6190 | upper 16 bits of the address. */ | |
6191 | if (mips_pic == NO_PIC) | |
6192 | { | |
67c0d1eb | 6193 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6194 | used_at = 1; |
252b5132 RH |
6195 | } |
6196 | else if (mips_pic == SVR4_PIC) | |
6197 | { | |
67c0d1eb RS |
6198 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6199 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6200 | used_at = 1; |
252b5132 | 6201 | } |
252b5132 RH |
6202 | else |
6203 | abort (); | |
bdaaa2e1 | 6204 | |
252b5132 | 6205 | /* Now we load the register(s). */ |
ca4e0257 | 6206 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6207 | { |
6208 | used_at = 1; | |
6209 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6210 | } | |
252b5132 RH |
6211 | else |
6212 | { | |
8fc2e39e | 6213 | used_at = 1; |
67c0d1eb | 6214 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6215 | if (treg != RA) |
252b5132 RH |
6216 | { |
6217 | /* FIXME: How in the world do we deal with the possible | |
6218 | overflow here? */ | |
6219 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6220 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6221 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6222 | } |
6223 | } | |
252b5132 RH |
6224 | break; |
6225 | ||
6226 | case M_LI_DD: | |
ca4e0257 RS |
6227 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6228 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6229 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6230 | the value and the low order 32 bits are either zero or in | |
6231 | OFFSET_EXPR. */ | |
252b5132 RH |
6232 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6233 | { | |
8fc2e39e | 6234 | used_at = 1; |
67c0d1eb | 6235 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6236 | if (HAVE_64BIT_FPRS) |
6237 | { | |
6238 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6239 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6240 | } |
252b5132 RH |
6241 | else |
6242 | { | |
67c0d1eb | 6243 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6244 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6245 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6246 | else |
6247 | { | |
6248 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6249 | load_register (AT, &offset_expr, 0); |
6250 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6251 | } |
6252 | } | |
6253 | break; | |
6254 | } | |
6255 | ||
6256 | assert (offset_expr.X_op == O_symbol | |
6257 | && offset_expr.X_add_number == 0); | |
6258 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6259 | if (strcmp (s, ".lit8") == 0) | |
6260 | { | |
e7af610e | 6261 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6262 | { |
67c0d1eb | 6263 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6264 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6265 | break; |
252b5132 | 6266 | } |
c9914766 | 6267 | breg = mips_gp_register; |
252b5132 RH |
6268 | r = BFD_RELOC_MIPS_LITERAL; |
6269 | goto dob; | |
6270 | } | |
6271 | else | |
6272 | { | |
6273 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6274 | used_at = 1; |
252b5132 | 6275 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6276 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6277 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6278 | else |
6279 | { | |
6280 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6281 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6282 | } |
bdaaa2e1 | 6283 | |
e7af610e | 6284 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6285 | { |
67c0d1eb RS |
6286 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6287 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6288 | break; |
6289 | } | |
6290 | breg = AT; | |
6291 | r = BFD_RELOC_LO16; | |
6292 | goto dob; | |
6293 | } | |
6294 | ||
6295 | case M_L_DOB: | |
fef14a42 | 6296 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6297 | { |
6298 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6299 | break; |
252b5132 RH |
6300 | } |
6301 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6302 | to adjust when loading from memory. */ | |
6303 | r = BFD_RELOC_LO16; | |
6304 | dob: | |
e7af610e | 6305 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6306 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6307 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6308 | /* FIXME: A possible overflow which I don't know how to deal |
6309 | with. */ | |
6310 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6311 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6312 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6313 | break; |
6314 | ||
6315 | case M_L_DAB: | |
6316 | /* | |
6317 | * The MIPS assembler seems to check for X_add_number not | |
6318 | * being double aligned and generating: | |
6319 | * lui at,%hi(foo+1) | |
6320 | * addu at,at,v1 | |
6321 | * addiu at,at,%lo(foo+1) | |
6322 | * lwc1 f2,0(at) | |
6323 | * lwc1 f3,4(at) | |
6324 | * But, the resulting address is the same after relocation so why | |
6325 | * generate the extra instruction? | |
6326 | */ | |
fef14a42 | 6327 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6328 | { |
6329 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6330 | break; |
252b5132 | 6331 | } |
bdaaa2e1 | 6332 | /* Itbl support may require additional care here. */ |
252b5132 | 6333 | coproc = 1; |
e7af610e | 6334 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6335 | { |
6336 | s = "ldc1"; | |
6337 | goto ld; | |
6338 | } | |
6339 | ||
6340 | s = "lwc1"; | |
6341 | fmt = "T,o(b)"; | |
6342 | goto ldd_std; | |
6343 | ||
6344 | case M_S_DAB: | |
fef14a42 | 6345 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6346 | { |
6347 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6348 | break; |
252b5132 RH |
6349 | } |
6350 | ||
e7af610e | 6351 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6352 | { |
6353 | s = "sdc1"; | |
6354 | goto st; | |
6355 | } | |
6356 | ||
6357 | s = "swc1"; | |
6358 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6359 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6360 | coproc = 1; |
6361 | goto ldd_std; | |
6362 | ||
6363 | case M_LD_AB: | |
ca4e0257 | 6364 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6365 | { |
6366 | s = "ld"; | |
6367 | goto ld; | |
6368 | } | |
6369 | ||
6370 | s = "lw"; | |
6371 | fmt = "t,o(b)"; | |
6372 | goto ldd_std; | |
6373 | ||
6374 | case M_SD_AB: | |
ca4e0257 | 6375 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6376 | { |
6377 | s = "sd"; | |
6378 | goto st; | |
6379 | } | |
6380 | ||
6381 | s = "sw"; | |
6382 | fmt = "t,o(b)"; | |
6383 | ||
6384 | ldd_std: | |
6385 | if (offset_expr.X_op != O_symbol | |
6386 | && offset_expr.X_op != O_constant) | |
6387 | { | |
6388 | as_bad (_("expression too complex")); | |
6389 | offset_expr.X_op = O_constant; | |
6390 | } | |
6391 | ||
2051e8c4 MR |
6392 | if (HAVE_32BIT_ADDRESSES |
6393 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
6394 | as_bad (_("Number (0x%lx%08lx) larger than 32 bits"), | |
6395 | (unsigned long) (offset_expr.X_add_number >> 32), | |
6396 | (unsigned long) (offset_expr.X_add_number & 0xffffffff)); | |
6397 | ||
252b5132 RH |
6398 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6399 | to adjust when loading from memory. We set coproc if we must | |
6400 | load $fn+1 first. */ | |
bdaaa2e1 | 6401 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6402 | if (! target_big_endian) |
6403 | coproc = 0; | |
6404 | ||
6405 | if (mips_pic == NO_PIC | |
6406 | || offset_expr.X_op == O_constant) | |
6407 | { | |
6408 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6409 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6410 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6411 | If we have a base register, we use this |
6412 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6413 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6414 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6415 | If this is not a GP relative symbol, we want |
6416 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6417 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6418 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6419 | If there is a base register, we add it to $at after the | |
6420 | lui instruction. If there is a constant, we always use | |
6421 | the last case. */ | |
39a59cf8 MR |
6422 | if (offset_expr.X_op == O_symbol |
6423 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6424 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6425 | { |
4d7206a2 | 6426 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6427 | if (breg == 0) |
6428 | { | |
c9914766 | 6429 | tempreg = mips_gp_register; |
252b5132 RH |
6430 | } |
6431 | else | |
6432 | { | |
67c0d1eb | 6433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6434 | AT, breg, mips_gp_register); |
252b5132 | 6435 | tempreg = AT; |
252b5132 RH |
6436 | used_at = 1; |
6437 | } | |
6438 | ||
beae10d5 | 6439 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6440 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6441 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6442 | offset_expr.X_add_number += 4; |
6443 | ||
6444 | /* Set mips_optimize to 2 to avoid inserting an | |
6445 | undesired nop. */ | |
6446 | hold_mips_optimize = mips_optimize; | |
6447 | mips_optimize = 2; | |
beae10d5 | 6448 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6449 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6450 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6451 | mips_optimize = hold_mips_optimize; |
6452 | ||
4d7206a2 | 6453 | relax_switch (); |
252b5132 RH |
6454 | |
6455 | /* We just generated two relocs. When tc_gen_reloc | |
6456 | handles this case, it will skip the first reloc and | |
6457 | handle the second. The second reloc already has an | |
6458 | extra addend of 4, which we added above. We must | |
6459 | subtract it out, and then subtract another 4 to make | |
6460 | the first reloc come out right. The second reloc | |
6461 | will come out right because we are going to add 4 to | |
6462 | offset_expr when we build its instruction below. | |
6463 | ||
6464 | If we have a symbol, then we don't want to include | |
6465 | the offset, because it will wind up being included | |
6466 | when we generate the reloc. */ | |
6467 | ||
6468 | if (offset_expr.X_op == O_constant) | |
6469 | offset_expr.X_add_number -= 8; | |
6470 | else | |
6471 | { | |
6472 | offset_expr.X_add_number = -4; | |
6473 | offset_expr.X_op = O_constant; | |
6474 | } | |
6475 | } | |
8fc2e39e | 6476 | used_at = 1; |
67c0d1eb | 6477 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6478 | if (breg != 0) |
67c0d1eb | 6479 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6480 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6481 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6482 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6483 | /* FIXME: How do we handle overflow here? */ |
6484 | offset_expr.X_add_number += 4; | |
beae10d5 | 6485 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6486 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6487 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6488 | if (mips_relax.sequence) |
6489 | relax_end (); | |
bdaaa2e1 | 6490 | } |
252b5132 RH |
6491 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6492 | { | |
252b5132 RH |
6493 | /* If this is a reference to an external symbol, we want |
6494 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6495 | nop | |
6496 | <op> $treg,0($at) | |
6497 | <op> $treg+1,4($at) | |
6498 | Otherwise we want | |
6499 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6500 | nop | |
6501 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6502 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6503 | If there is a base register we add it to $at before the | |
6504 | lwc1 instructions. If there is a constant we include it | |
6505 | in the lwc1 instructions. */ | |
6506 | used_at = 1; | |
6507 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6508 | if (expr1.X_add_number < -0x8000 |
6509 | || expr1.X_add_number >= 0x8000 - 4) | |
6510 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6511 | load_got_offset (AT, &offset_expr); |
269137b2 | 6512 | load_delay_nop (); |
252b5132 | 6513 | if (breg != 0) |
67c0d1eb | 6514 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6515 | |
6516 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6517 | nop. */ | |
6518 | hold_mips_optimize = mips_optimize; | |
6519 | mips_optimize = 2; | |
4d7206a2 | 6520 | |
beae10d5 | 6521 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6522 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6523 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6524 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6525 | expr1.X_add_number += 4; |
67c0d1eb RS |
6526 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6527 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6528 | relax_switch (); |
67c0d1eb RS |
6529 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6530 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6531 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6532 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6533 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6534 | relax_end (); |
252b5132 | 6535 | |
4d7206a2 | 6536 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6537 | } |
6538 | else if (mips_pic == SVR4_PIC) | |
6539 | { | |
67c0d1eb | 6540 | int gpdelay; |
252b5132 RH |
6541 | |
6542 | /* If this is a reference to an external symbol, we want | |
6543 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6544 | addu $at,$at,$gp | |
6545 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6546 | nop | |
6547 | <op> $treg,0($at) | |
6548 | <op> $treg+1,4($at) | |
6549 | Otherwise we want | |
6550 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6551 | nop | |
6552 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6553 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6554 | If there is a base register we add it to $at before the | |
6555 | lwc1 instructions. If there is a constant we include it | |
6556 | in the lwc1 instructions. */ | |
6557 | used_at = 1; | |
6558 | expr1.X_add_number = offset_expr.X_add_number; | |
6559 | offset_expr.X_add_number = 0; | |
6560 | if (expr1.X_add_number < -0x8000 | |
6561 | || expr1.X_add_number >= 0x8000 - 4) | |
6562 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6563 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6564 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6565 | macro_build (&offset_expr, "lui", "t,u", |
6566 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6567 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6568 | AT, AT, mips_gp_register); |
67c0d1eb | 6569 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6570 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6571 | load_delay_nop (); |
252b5132 | 6572 | if (breg != 0) |
67c0d1eb | 6573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6574 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6575 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6576 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6577 | expr1.X_add_number += 4; |
6578 | ||
6579 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6580 | nop. */ | |
6581 | hold_mips_optimize = mips_optimize; | |
6582 | mips_optimize = 2; | |
beae10d5 | 6583 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6584 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6585 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6586 | mips_optimize = hold_mips_optimize; |
6587 | expr1.X_add_number -= 4; | |
6588 | ||
4d7206a2 RS |
6589 | relax_switch (); |
6590 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6591 | if (gpdelay) |
6592 | macro_build (NULL, "nop", ""); | |
6593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6594 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6595 | load_delay_nop (); |
252b5132 | 6596 | if (breg != 0) |
67c0d1eb | 6597 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6598 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6599 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6600 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6601 | offset_expr.X_add_number += 4; |
252b5132 RH |
6602 | |
6603 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6604 | nop. */ | |
6605 | hold_mips_optimize = mips_optimize; | |
6606 | mips_optimize = 2; | |
beae10d5 | 6607 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6608 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6609 | BFD_RELOC_LO16, AT); | |
252b5132 | 6610 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6611 | relax_end (); |
252b5132 | 6612 | } |
252b5132 RH |
6613 | else |
6614 | abort (); | |
6615 | ||
252b5132 RH |
6616 | break; |
6617 | ||
6618 | case M_LD_OB: | |
6619 | s = "lw"; | |
6620 | goto sd_ob; | |
6621 | case M_SD_OB: | |
6622 | s = "sw"; | |
6623 | sd_ob: | |
ca4e0257 | 6624 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6625 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6626 | offset_expr.X_add_number += 4; |
67c0d1eb | 6627 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6628 | break; |
252b5132 RH |
6629 | |
6630 | /* New code added to support COPZ instructions. | |
6631 | This code builds table entries out of the macros in mip_opcodes. | |
6632 | R4000 uses interlocks to handle coproc delays. | |
6633 | Other chips (like the R3000) require nops to be inserted for delays. | |
6634 | ||
f72c8c98 | 6635 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6636 | In order to fill delay slots for non-interlocked chips, |
6637 | we must have a way to specify delays based on the coprocessor. | |
6638 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6639 | What are the side-effects of the cop instruction? | |
6640 | What cache support might we have and what are its effects? | |
6641 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6642 | What registers are read/set/modified? |
252b5132 RH |
6643 | |
6644 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6645 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6646 | |
6647 | case M_COP0: | |
6648 | s = "c0"; | |
6649 | goto copz; | |
6650 | case M_COP1: | |
6651 | s = "c1"; | |
6652 | goto copz; | |
6653 | case M_COP2: | |
6654 | s = "c2"; | |
6655 | goto copz; | |
6656 | case M_COP3: | |
6657 | s = "c3"; | |
6658 | copz: | |
6659 | /* For now we just do C (same as Cz). The parameter will be | |
6660 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6661 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6662 | break; |
252b5132 | 6663 | |
ea1fb5dc | 6664 | case M_MOVE: |
67c0d1eb | 6665 | move_register (dreg, sreg); |
8fc2e39e | 6666 | break; |
ea1fb5dc | 6667 | |
252b5132 RH |
6668 | #ifdef LOSING_COMPILER |
6669 | default: | |
6670 | /* Try and see if this is a new itbl instruction. | |
6671 | This code builds table entries out of the macros in mip_opcodes. | |
6672 | FIXME: For now we just assemble the expression and pass it's | |
6673 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6674 | We may want to have the assembler assemble this value, |
252b5132 RH |
6675 | so that we gain the assembler's knowledge of delay slots, |
6676 | symbols, etc. | |
6677 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6678 | if (itbl_have_entries |
252b5132 | 6679 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6680 | { |
252b5132 RH |
6681 | s = ip->insn_mo->name; |
6682 | s2 = "cop3"; | |
6683 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6684 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6685 | break; |
beae10d5 | 6686 | } |
252b5132 | 6687 | macro2 (ip); |
8fc2e39e | 6688 | break; |
252b5132 | 6689 | } |
8fc2e39e TS |
6690 | if (mips_opts.noat && used_at) |
6691 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6692 | } |
bdaaa2e1 | 6693 | |
252b5132 | 6694 | static void |
17a2f251 | 6695 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6696 | { |
6697 | register int treg, sreg, dreg, breg; | |
6698 | int tempreg; | |
6699 | int mask; | |
252b5132 RH |
6700 | int used_at; |
6701 | expressionS expr1; | |
6702 | const char *s; | |
6703 | const char *s2; | |
6704 | const char *fmt; | |
6705 | int likely = 0; | |
6706 | int dbl = 0; | |
6707 | int coproc = 0; | |
6708 | int lr = 0; | |
6709 | int imm = 0; | |
6710 | int off; | |
6711 | offsetT maxnum; | |
6712 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6713 | |
252b5132 RH |
6714 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6715 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6716 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6717 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6718 | |
252b5132 RH |
6719 | expr1.X_op = O_constant; |
6720 | expr1.X_op_symbol = NULL; | |
6721 | expr1.X_add_symbol = NULL; | |
6722 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6723 | |
252b5132 RH |
6724 | switch (mask) |
6725 | { | |
6726 | #endif /* LOSING_COMPILER */ | |
6727 | ||
6728 | case M_DMUL: | |
6729 | dbl = 1; | |
6730 | case M_MUL: | |
67c0d1eb RS |
6731 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6732 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6733 | break; |
252b5132 RH |
6734 | |
6735 | case M_DMUL_I: | |
6736 | dbl = 1; | |
6737 | case M_MUL_I: | |
6738 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6739 | not trying to be that fancy. GCC should do this for us | |
6740 | anyway. */ | |
8fc2e39e | 6741 | used_at = 1; |
67c0d1eb RS |
6742 | load_register (AT, &imm_expr, dbl); |
6743 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6744 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6745 | break; |
6746 | ||
6747 | case M_DMULO_I: | |
6748 | dbl = 1; | |
6749 | case M_MULO_I: | |
6750 | imm = 1; | |
6751 | goto do_mulo; | |
6752 | ||
6753 | case M_DMULO: | |
6754 | dbl = 1; | |
6755 | case M_MULO: | |
6756 | do_mulo: | |
7d10b47d | 6757 | start_noreorder (); |
8fc2e39e | 6758 | used_at = 1; |
252b5132 | 6759 | if (imm) |
67c0d1eb RS |
6760 | load_register (AT, &imm_expr, dbl); |
6761 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6762 | macro_build (NULL, "mflo", "d", dreg); | |
6763 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6764 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6765 | if (mips_trap) |
67c0d1eb | 6766 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6767 | else |
6768 | { | |
6769 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6770 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6771 | macro_build (NULL, "nop", "", 0); | |
6772 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6773 | } |
7d10b47d | 6774 | end_noreorder (); |
67c0d1eb | 6775 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6776 | break; |
6777 | ||
6778 | case M_DMULOU_I: | |
6779 | dbl = 1; | |
6780 | case M_MULOU_I: | |
6781 | imm = 1; | |
6782 | goto do_mulou; | |
6783 | ||
6784 | case M_DMULOU: | |
6785 | dbl = 1; | |
6786 | case M_MULOU: | |
6787 | do_mulou: | |
7d10b47d | 6788 | start_noreorder (); |
8fc2e39e | 6789 | used_at = 1; |
252b5132 | 6790 | if (imm) |
67c0d1eb RS |
6791 | load_register (AT, &imm_expr, dbl); |
6792 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6793 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6794 | macro_build (NULL, "mfhi", "d", AT); |
6795 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6796 | if (mips_trap) |
67c0d1eb | 6797 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6798 | else |
6799 | { | |
6800 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6801 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6802 | macro_build (NULL, "nop", "", 0); | |
6803 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 6804 | } |
7d10b47d | 6805 | end_noreorder (); |
252b5132 RH |
6806 | break; |
6807 | ||
771c7ce4 | 6808 | case M_DROL: |
fef14a42 | 6809 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6810 | { |
6811 | if (dreg == sreg) | |
6812 | { | |
6813 | tempreg = AT; | |
6814 | used_at = 1; | |
6815 | } | |
6816 | else | |
6817 | { | |
6818 | tempreg = dreg; | |
82dd0097 | 6819 | } |
67c0d1eb RS |
6820 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6821 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6822 | break; |
82dd0097 | 6823 | } |
8fc2e39e | 6824 | used_at = 1; |
67c0d1eb RS |
6825 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6826 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6827 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6828 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6829 | break; |
6830 | ||
252b5132 | 6831 | case M_ROL: |
fef14a42 | 6832 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6833 | { |
6834 | if (dreg == sreg) | |
6835 | { | |
6836 | tempreg = AT; | |
6837 | used_at = 1; | |
6838 | } | |
6839 | else | |
6840 | { | |
6841 | tempreg = dreg; | |
82dd0097 | 6842 | } |
67c0d1eb RS |
6843 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6844 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6845 | break; |
82dd0097 | 6846 | } |
8fc2e39e | 6847 | used_at = 1; |
67c0d1eb RS |
6848 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6849 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6850 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6851 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6852 | break; |
6853 | ||
771c7ce4 TS |
6854 | case M_DROL_I: |
6855 | { | |
6856 | unsigned int rot; | |
82dd0097 | 6857 | char *l, *r; |
771c7ce4 TS |
6858 | |
6859 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6860 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6861 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6862 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6863 | { |
6864 | rot = (64 - rot) & 0x3f; | |
6865 | if (rot >= 32) | |
67c0d1eb | 6866 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6867 | else |
67c0d1eb | 6868 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6869 | break; |
60b63b72 | 6870 | } |
483fc7cd | 6871 | if (rot == 0) |
483fc7cd | 6872 | { |
67c0d1eb | 6873 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6874 | break; |
483fc7cd | 6875 | } |
82dd0097 CD |
6876 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6877 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6878 | rot &= 0x1f; | |
8fc2e39e | 6879 | used_at = 1; |
67c0d1eb RS |
6880 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6881 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6882 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6883 | } |
6884 | break; | |
6885 | ||
252b5132 | 6886 | case M_ROL_I: |
771c7ce4 TS |
6887 | { |
6888 | unsigned int rot; | |
6889 | ||
6890 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6891 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6892 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6893 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6894 | { |
67c0d1eb | 6895 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6896 | break; |
60b63b72 | 6897 | } |
483fc7cd | 6898 | if (rot == 0) |
483fc7cd | 6899 | { |
67c0d1eb | 6900 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6901 | break; |
483fc7cd | 6902 | } |
8fc2e39e | 6903 | used_at = 1; |
67c0d1eb RS |
6904 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6905 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6906 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6907 | } |
6908 | break; | |
6909 | ||
6910 | case M_DROR: | |
fef14a42 | 6911 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6912 | { |
67c0d1eb | 6913 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6914 | break; |
82dd0097 | 6915 | } |
8fc2e39e | 6916 | used_at = 1; |
67c0d1eb RS |
6917 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6918 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6919 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6920 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6921 | break; |
6922 | ||
6923 | case M_ROR: | |
fef14a42 | 6924 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6925 | { |
67c0d1eb | 6926 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6927 | break; |
82dd0097 | 6928 | } |
8fc2e39e | 6929 | used_at = 1; |
67c0d1eb RS |
6930 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6931 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6932 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6933 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6934 | break; |
6935 | ||
771c7ce4 TS |
6936 | case M_DROR_I: |
6937 | { | |
6938 | unsigned int rot; | |
82dd0097 | 6939 | char *l, *r; |
771c7ce4 TS |
6940 | |
6941 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6942 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6943 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6944 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6945 | { |
6946 | if (rot >= 32) | |
67c0d1eb | 6947 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6948 | else |
67c0d1eb | 6949 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6950 | break; |
82dd0097 | 6951 | } |
483fc7cd | 6952 | if (rot == 0) |
483fc7cd | 6953 | { |
67c0d1eb | 6954 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6955 | break; |
483fc7cd | 6956 | } |
82dd0097 CD |
6957 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6958 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6959 | rot &= 0x1f; | |
8fc2e39e | 6960 | used_at = 1; |
67c0d1eb RS |
6961 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6962 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6963 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6964 | } |
6965 | break; | |
6966 | ||
252b5132 | 6967 | case M_ROR_I: |
771c7ce4 TS |
6968 | { |
6969 | unsigned int rot; | |
6970 | ||
6971 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6972 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6973 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6974 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6975 | { |
67c0d1eb | 6976 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6977 | break; |
82dd0097 | 6978 | } |
483fc7cd | 6979 | if (rot == 0) |
483fc7cd | 6980 | { |
67c0d1eb | 6981 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6982 | break; |
483fc7cd | 6983 | } |
8fc2e39e | 6984 | used_at = 1; |
67c0d1eb RS |
6985 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
6986 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6987 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 6988 | } |
252b5132 RH |
6989 | break; |
6990 | ||
6991 | case M_S_DOB: | |
fef14a42 | 6992 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6993 | { |
6994 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6995 | break; |
252b5132 | 6996 | } |
e7af610e | 6997 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6998 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6999 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7000 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7001 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7002 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7003 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7004 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7005 | break; |
252b5132 RH |
7006 | |
7007 | case M_SEQ: | |
7008 | if (sreg == 0) | |
67c0d1eb | 7009 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7010 | else if (treg == 0) |
67c0d1eb | 7011 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7012 | else |
7013 | { | |
67c0d1eb RS |
7014 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7015 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7016 | } |
8fc2e39e | 7017 | break; |
252b5132 RH |
7018 | |
7019 | case M_SEQ_I: | |
7020 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7021 | { | |
67c0d1eb | 7022 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7023 | break; |
252b5132 RH |
7024 | } |
7025 | if (sreg == 0) | |
7026 | { | |
7027 | as_warn (_("Instruction %s: result is always false"), | |
7028 | ip->insn_mo->name); | |
67c0d1eb | 7029 | move_register (dreg, 0); |
8fc2e39e | 7030 | break; |
252b5132 RH |
7031 | } |
7032 | if (imm_expr.X_op == O_constant | |
7033 | && imm_expr.X_add_number >= 0 | |
7034 | && imm_expr.X_add_number < 0x10000) | |
7035 | { | |
67c0d1eb | 7036 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7037 | } |
7038 | else if (imm_expr.X_op == O_constant | |
7039 | && imm_expr.X_add_number > -0x8000 | |
7040 | && imm_expr.X_add_number < 0) | |
7041 | { | |
7042 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7043 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7044 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7045 | } |
7046 | else | |
7047 | { | |
67c0d1eb RS |
7048 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7049 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7050 | used_at = 1; |
7051 | } | |
67c0d1eb | 7052 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7053 | break; |
252b5132 RH |
7054 | |
7055 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7056 | s = "slt"; | |
7057 | goto sge; | |
7058 | case M_SGEU: | |
7059 | s = "sltu"; | |
7060 | sge: | |
67c0d1eb RS |
7061 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7062 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7063 | break; |
252b5132 RH |
7064 | |
7065 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7066 | case M_SGEU_I: | |
7067 | if (imm_expr.X_op == O_constant | |
7068 | && imm_expr.X_add_number >= -0x8000 | |
7069 | && imm_expr.X_add_number < 0x8000) | |
7070 | { | |
67c0d1eb RS |
7071 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7072 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7073 | } |
7074 | else | |
7075 | { | |
67c0d1eb RS |
7076 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7077 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7078 | dreg, sreg, AT); | |
252b5132 RH |
7079 | used_at = 1; |
7080 | } | |
67c0d1eb | 7081 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7082 | break; |
252b5132 RH |
7083 | |
7084 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7085 | s = "slt"; | |
7086 | goto sgt; | |
7087 | case M_SGTU: | |
7088 | s = "sltu"; | |
7089 | sgt: | |
67c0d1eb | 7090 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7091 | break; |
252b5132 RH |
7092 | |
7093 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7094 | s = "slt"; | |
7095 | goto sgti; | |
7096 | case M_SGTU_I: | |
7097 | s = "sltu"; | |
7098 | sgti: | |
8fc2e39e | 7099 | used_at = 1; |
67c0d1eb RS |
7100 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7101 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7102 | break; |
7103 | ||
2396cfb9 | 7104 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7105 | s = "slt"; |
7106 | goto sle; | |
7107 | case M_SLEU: | |
7108 | s = "sltu"; | |
7109 | sle: | |
67c0d1eb RS |
7110 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7111 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7112 | break; |
252b5132 | 7113 | |
2396cfb9 | 7114 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7115 | s = "slt"; |
7116 | goto slei; | |
7117 | case M_SLEU_I: | |
7118 | s = "sltu"; | |
7119 | slei: | |
8fc2e39e | 7120 | used_at = 1; |
67c0d1eb RS |
7121 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7122 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7123 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7124 | break; |
7125 | ||
7126 | case M_SLT_I: | |
7127 | if (imm_expr.X_op == O_constant | |
7128 | && imm_expr.X_add_number >= -0x8000 | |
7129 | && imm_expr.X_add_number < 0x8000) | |
7130 | { | |
67c0d1eb | 7131 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7132 | break; |
252b5132 | 7133 | } |
8fc2e39e | 7134 | used_at = 1; |
67c0d1eb RS |
7135 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7136 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7137 | break; |
7138 | ||
7139 | case M_SLTU_I: | |
7140 | if (imm_expr.X_op == O_constant | |
7141 | && imm_expr.X_add_number >= -0x8000 | |
7142 | && imm_expr.X_add_number < 0x8000) | |
7143 | { | |
67c0d1eb | 7144 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7145 | BFD_RELOC_LO16); |
8fc2e39e | 7146 | break; |
252b5132 | 7147 | } |
8fc2e39e | 7148 | used_at = 1; |
67c0d1eb RS |
7149 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7150 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7151 | break; |
7152 | ||
7153 | case M_SNE: | |
7154 | if (sreg == 0) | |
67c0d1eb | 7155 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7156 | else if (treg == 0) |
67c0d1eb | 7157 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7158 | else |
7159 | { | |
67c0d1eb RS |
7160 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7161 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7162 | } |
8fc2e39e | 7163 | break; |
252b5132 RH |
7164 | |
7165 | case M_SNE_I: | |
7166 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7167 | { | |
67c0d1eb | 7168 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7169 | break; |
252b5132 RH |
7170 | } |
7171 | if (sreg == 0) | |
7172 | { | |
7173 | as_warn (_("Instruction %s: result is always true"), | |
7174 | ip->insn_mo->name); | |
67c0d1eb RS |
7175 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7176 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7177 | break; |
252b5132 RH |
7178 | } |
7179 | if (imm_expr.X_op == O_constant | |
7180 | && imm_expr.X_add_number >= 0 | |
7181 | && imm_expr.X_add_number < 0x10000) | |
7182 | { | |
67c0d1eb | 7183 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7184 | } |
7185 | else if (imm_expr.X_op == O_constant | |
7186 | && imm_expr.X_add_number > -0x8000 | |
7187 | && imm_expr.X_add_number < 0) | |
7188 | { | |
7189 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7190 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7191 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7192 | } |
7193 | else | |
7194 | { | |
67c0d1eb RS |
7195 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7196 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7197 | used_at = 1; |
7198 | } | |
67c0d1eb | 7199 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7200 | break; |
252b5132 RH |
7201 | |
7202 | case M_DSUB_I: | |
7203 | dbl = 1; | |
7204 | case M_SUB_I: | |
7205 | if (imm_expr.X_op == O_constant | |
7206 | && imm_expr.X_add_number > -0x8000 | |
7207 | && imm_expr.X_add_number <= 0x8000) | |
7208 | { | |
7209 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7210 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7211 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7212 | break; |
252b5132 | 7213 | } |
8fc2e39e | 7214 | used_at = 1; |
67c0d1eb RS |
7215 | load_register (AT, &imm_expr, dbl); |
7216 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7217 | break; |
7218 | ||
7219 | case M_DSUBU_I: | |
7220 | dbl = 1; | |
7221 | case M_SUBU_I: | |
7222 | if (imm_expr.X_op == O_constant | |
7223 | && imm_expr.X_add_number > -0x8000 | |
7224 | && imm_expr.X_add_number <= 0x8000) | |
7225 | { | |
7226 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7227 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7228 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7229 | break; |
252b5132 | 7230 | } |
8fc2e39e | 7231 | used_at = 1; |
67c0d1eb RS |
7232 | load_register (AT, &imm_expr, dbl); |
7233 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7234 | break; |
7235 | ||
7236 | case M_TEQ_I: | |
7237 | s = "teq"; | |
7238 | goto trap; | |
7239 | case M_TGE_I: | |
7240 | s = "tge"; | |
7241 | goto trap; | |
7242 | case M_TGEU_I: | |
7243 | s = "tgeu"; | |
7244 | goto trap; | |
7245 | case M_TLT_I: | |
7246 | s = "tlt"; | |
7247 | goto trap; | |
7248 | case M_TLTU_I: | |
7249 | s = "tltu"; | |
7250 | goto trap; | |
7251 | case M_TNE_I: | |
7252 | s = "tne"; | |
7253 | trap: | |
8fc2e39e | 7254 | used_at = 1; |
67c0d1eb RS |
7255 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7256 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7257 | break; |
7258 | ||
252b5132 | 7259 | case M_TRUNCWS: |
43841e91 | 7260 | case M_TRUNCWD: |
e7af610e | 7261 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7262 | used_at = 1; |
252b5132 RH |
7263 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7264 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7265 | ||
7266 | /* | |
7267 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7268 | * or is there a reason for it? | |
7269 | */ | |
7d10b47d | 7270 | start_noreorder (); |
67c0d1eb RS |
7271 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7272 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7273 | macro_build (NULL, "nop", ""); | |
252b5132 | 7274 | expr1.X_add_number = 3; |
67c0d1eb | 7275 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7276 | expr1.X_add_number = 2; |
67c0d1eb RS |
7277 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7278 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7279 | macro_build (NULL, "nop", ""); | |
7280 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7281 | dreg, sreg); | |
7282 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7283 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7284 | end_noreorder (); |
252b5132 RH |
7285 | break; |
7286 | ||
7287 | case M_ULH: | |
7288 | s = "lb"; | |
7289 | goto ulh; | |
7290 | case M_ULHU: | |
7291 | s = "lbu"; | |
7292 | ulh: | |
8fc2e39e | 7293 | used_at = 1; |
252b5132 RH |
7294 | if (offset_expr.X_add_number >= 0x7fff) |
7295 | as_bad (_("operand overflow")); | |
252b5132 | 7296 | if (! target_big_endian) |
f9419b05 | 7297 | ++offset_expr.X_add_number; |
67c0d1eb | 7298 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7299 | if (! target_big_endian) |
f9419b05 | 7300 | --offset_expr.X_add_number; |
252b5132 | 7301 | else |
f9419b05 | 7302 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7303 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7304 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7305 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7306 | break; |
7307 | ||
7308 | case M_ULD: | |
7309 | s = "ldl"; | |
7310 | s2 = "ldr"; | |
7311 | off = 7; | |
7312 | goto ulw; | |
7313 | case M_ULW: | |
7314 | s = "lwl"; | |
7315 | s2 = "lwr"; | |
7316 | off = 3; | |
7317 | ulw: | |
7318 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7319 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7320 | if (treg != breg) |
7321 | tempreg = treg; | |
7322 | else | |
8fc2e39e TS |
7323 | { |
7324 | used_at = 1; | |
7325 | tempreg = AT; | |
7326 | } | |
252b5132 RH |
7327 | if (! target_big_endian) |
7328 | offset_expr.X_add_number += off; | |
67c0d1eb | 7329 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7330 | if (! target_big_endian) |
7331 | offset_expr.X_add_number -= off; | |
7332 | else | |
7333 | offset_expr.X_add_number += off; | |
67c0d1eb | 7334 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7335 | |
7336 | /* If necessary, move the result in tempreg the final destination. */ | |
7337 | if (treg == tempreg) | |
8fc2e39e | 7338 | break; |
af22f5b2 | 7339 | /* Protect second load's delay slot. */ |
017315e4 | 7340 | load_delay_nop (); |
67c0d1eb | 7341 | move_register (treg, tempreg); |
af22f5b2 | 7342 | break; |
252b5132 RH |
7343 | |
7344 | case M_ULD_A: | |
7345 | s = "ldl"; | |
7346 | s2 = "ldr"; | |
7347 | off = 7; | |
7348 | goto ulwa; | |
7349 | case M_ULW_A: | |
7350 | s = "lwl"; | |
7351 | s2 = "lwr"; | |
7352 | off = 3; | |
7353 | ulwa: | |
d6bc6245 | 7354 | used_at = 1; |
67c0d1eb | 7355 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7356 | if (breg != 0) |
67c0d1eb | 7357 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7358 | if (! target_big_endian) |
7359 | expr1.X_add_number = off; | |
7360 | else | |
7361 | expr1.X_add_number = 0; | |
67c0d1eb | 7362 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7363 | if (! target_big_endian) |
7364 | expr1.X_add_number = 0; | |
7365 | else | |
7366 | expr1.X_add_number = off; | |
67c0d1eb | 7367 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7368 | break; |
7369 | ||
7370 | case M_ULH_A: | |
7371 | case M_ULHU_A: | |
d6bc6245 | 7372 | used_at = 1; |
67c0d1eb | 7373 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7374 | if (breg != 0) |
67c0d1eb | 7375 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7376 | if (target_big_endian) |
7377 | expr1.X_add_number = 0; | |
67c0d1eb | 7378 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7379 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7380 | if (target_big_endian) |
7381 | expr1.X_add_number = 1; | |
7382 | else | |
7383 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7384 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7385 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7386 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7387 | break; |
7388 | ||
7389 | case M_USH: | |
8fc2e39e | 7390 | used_at = 1; |
252b5132 RH |
7391 | if (offset_expr.X_add_number >= 0x7fff) |
7392 | as_bad (_("operand overflow")); | |
7393 | if (target_big_endian) | |
f9419b05 | 7394 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7395 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7396 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7397 | if (target_big_endian) |
f9419b05 | 7398 | --offset_expr.X_add_number; |
252b5132 | 7399 | else |
f9419b05 | 7400 | ++offset_expr.X_add_number; |
67c0d1eb | 7401 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7402 | break; |
7403 | ||
7404 | case M_USD: | |
7405 | s = "sdl"; | |
7406 | s2 = "sdr"; | |
7407 | off = 7; | |
7408 | goto usw; | |
7409 | case M_USW: | |
7410 | s = "swl"; | |
7411 | s2 = "swr"; | |
7412 | off = 3; | |
7413 | usw: | |
7414 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7415 | as_bad (_("operand overflow")); | |
7416 | if (! target_big_endian) | |
7417 | offset_expr.X_add_number += off; | |
67c0d1eb | 7418 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7419 | if (! target_big_endian) |
7420 | offset_expr.X_add_number -= off; | |
7421 | else | |
7422 | offset_expr.X_add_number += off; | |
67c0d1eb | 7423 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7424 | break; |
252b5132 RH |
7425 | |
7426 | case M_USD_A: | |
7427 | s = "sdl"; | |
7428 | s2 = "sdr"; | |
7429 | off = 7; | |
7430 | goto uswa; | |
7431 | case M_USW_A: | |
7432 | s = "swl"; | |
7433 | s2 = "swr"; | |
7434 | off = 3; | |
7435 | uswa: | |
d6bc6245 | 7436 | used_at = 1; |
67c0d1eb | 7437 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7438 | if (breg != 0) |
67c0d1eb | 7439 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7440 | if (! target_big_endian) |
7441 | expr1.X_add_number = off; | |
7442 | else | |
7443 | expr1.X_add_number = 0; | |
67c0d1eb | 7444 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7445 | if (! target_big_endian) |
7446 | expr1.X_add_number = 0; | |
7447 | else | |
7448 | expr1.X_add_number = off; | |
67c0d1eb | 7449 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7450 | break; |
7451 | ||
7452 | case M_USH_A: | |
d6bc6245 | 7453 | used_at = 1; |
67c0d1eb | 7454 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7455 | if (breg != 0) |
67c0d1eb | 7456 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7457 | if (! target_big_endian) |
7458 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7459 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7460 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7461 | if (! target_big_endian) |
7462 | expr1.X_add_number = 1; | |
7463 | else | |
7464 | expr1.X_add_number = 0; | |
67c0d1eb | 7465 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7466 | if (! target_big_endian) |
7467 | expr1.X_add_number = 0; | |
7468 | else | |
7469 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7470 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7471 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7472 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7473 | break; |
7474 | ||
7475 | default: | |
7476 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7477 | are added dynamically. */ |
252b5132 RH |
7478 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7479 | break; | |
7480 | } | |
8fc2e39e TS |
7481 | if (mips_opts.noat && used_at) |
7482 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7483 | } |
7484 | ||
7485 | /* Implement macros in mips16 mode. */ | |
7486 | ||
7487 | static void | |
17a2f251 | 7488 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7489 | { |
7490 | int mask; | |
7491 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7492 | expressionS expr1; |
7493 | int dbl; | |
7494 | const char *s, *s2, *s3; | |
7495 | ||
7496 | mask = ip->insn_mo->mask; | |
7497 | ||
bf12938e RS |
7498 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7499 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7500 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7501 | |
252b5132 RH |
7502 | expr1.X_op = O_constant; |
7503 | expr1.X_op_symbol = NULL; | |
7504 | expr1.X_add_symbol = NULL; | |
7505 | expr1.X_add_number = 1; | |
7506 | ||
7507 | dbl = 0; | |
7508 | ||
7509 | switch (mask) | |
7510 | { | |
7511 | default: | |
7512 | internalError (); | |
7513 | ||
7514 | case M_DDIV_3: | |
7515 | dbl = 1; | |
7516 | case M_DIV_3: | |
7517 | s = "mflo"; | |
7518 | goto do_div3; | |
7519 | case M_DREM_3: | |
7520 | dbl = 1; | |
7521 | case M_REM_3: | |
7522 | s = "mfhi"; | |
7523 | do_div3: | |
7d10b47d | 7524 | start_noreorder (); |
67c0d1eb | 7525 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7526 | expr1.X_add_number = 2; |
67c0d1eb RS |
7527 | macro_build (&expr1, "bnez", "x,p", yreg); |
7528 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7529 | |
252b5132 RH |
7530 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7531 | since that causes an overflow. We should do that as well, | |
7532 | but I don't see how to do the comparisons without a temporary | |
7533 | register. */ | |
7d10b47d | 7534 | end_noreorder (); |
67c0d1eb | 7535 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7536 | break; |
7537 | ||
7538 | case M_DIVU_3: | |
7539 | s = "divu"; | |
7540 | s2 = "mflo"; | |
7541 | goto do_divu3; | |
7542 | case M_REMU_3: | |
7543 | s = "divu"; | |
7544 | s2 = "mfhi"; | |
7545 | goto do_divu3; | |
7546 | case M_DDIVU_3: | |
7547 | s = "ddivu"; | |
7548 | s2 = "mflo"; | |
7549 | goto do_divu3; | |
7550 | case M_DREMU_3: | |
7551 | s = "ddivu"; | |
7552 | s2 = "mfhi"; | |
7553 | do_divu3: | |
7d10b47d | 7554 | start_noreorder (); |
67c0d1eb | 7555 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7556 | expr1.X_add_number = 2; |
67c0d1eb RS |
7557 | macro_build (&expr1, "bnez", "x,p", yreg); |
7558 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7559 | end_noreorder (); |
67c0d1eb | 7560 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7561 | break; |
7562 | ||
7563 | case M_DMUL: | |
7564 | dbl = 1; | |
7565 | case M_MUL: | |
67c0d1eb RS |
7566 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7567 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7568 | break; |
252b5132 RH |
7569 | |
7570 | case M_DSUBU_I: | |
7571 | dbl = 1; | |
7572 | goto do_subu; | |
7573 | case M_SUBU_I: | |
7574 | do_subu: | |
7575 | if (imm_expr.X_op != O_constant) | |
7576 | as_bad (_("Unsupported large constant")); | |
7577 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7578 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7579 | break; |
7580 | ||
7581 | case M_SUBU_I_2: | |
7582 | if (imm_expr.X_op != O_constant) | |
7583 | as_bad (_("Unsupported large constant")); | |
7584 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7585 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7586 | break; |
7587 | ||
7588 | case M_DSUBU_I_2: | |
7589 | if (imm_expr.X_op != O_constant) | |
7590 | as_bad (_("Unsupported large constant")); | |
7591 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7592 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7593 | break; |
7594 | ||
7595 | case M_BEQ: | |
7596 | s = "cmp"; | |
7597 | s2 = "bteqz"; | |
7598 | goto do_branch; | |
7599 | case M_BNE: | |
7600 | s = "cmp"; | |
7601 | s2 = "btnez"; | |
7602 | goto do_branch; | |
7603 | case M_BLT: | |
7604 | s = "slt"; | |
7605 | s2 = "btnez"; | |
7606 | goto do_branch; | |
7607 | case M_BLTU: | |
7608 | s = "sltu"; | |
7609 | s2 = "btnez"; | |
7610 | goto do_branch; | |
7611 | case M_BLE: | |
7612 | s = "slt"; | |
7613 | s2 = "bteqz"; | |
7614 | goto do_reverse_branch; | |
7615 | case M_BLEU: | |
7616 | s = "sltu"; | |
7617 | s2 = "bteqz"; | |
7618 | goto do_reverse_branch; | |
7619 | case M_BGE: | |
7620 | s = "slt"; | |
7621 | s2 = "bteqz"; | |
7622 | goto do_branch; | |
7623 | case M_BGEU: | |
7624 | s = "sltu"; | |
7625 | s2 = "bteqz"; | |
7626 | goto do_branch; | |
7627 | case M_BGT: | |
7628 | s = "slt"; | |
7629 | s2 = "btnez"; | |
7630 | goto do_reverse_branch; | |
7631 | case M_BGTU: | |
7632 | s = "sltu"; | |
7633 | s2 = "btnez"; | |
7634 | ||
7635 | do_reverse_branch: | |
7636 | tmp = xreg; | |
7637 | xreg = yreg; | |
7638 | yreg = tmp; | |
7639 | ||
7640 | do_branch: | |
67c0d1eb RS |
7641 | macro_build (NULL, s, "x,y", xreg, yreg); |
7642 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7643 | break; |
7644 | ||
7645 | case M_BEQ_I: | |
7646 | s = "cmpi"; | |
7647 | s2 = "bteqz"; | |
7648 | s3 = "x,U"; | |
7649 | goto do_branch_i; | |
7650 | case M_BNE_I: | |
7651 | s = "cmpi"; | |
7652 | s2 = "btnez"; | |
7653 | s3 = "x,U"; | |
7654 | goto do_branch_i; | |
7655 | case M_BLT_I: | |
7656 | s = "slti"; | |
7657 | s2 = "btnez"; | |
7658 | s3 = "x,8"; | |
7659 | goto do_branch_i; | |
7660 | case M_BLTU_I: | |
7661 | s = "sltiu"; | |
7662 | s2 = "btnez"; | |
7663 | s3 = "x,8"; | |
7664 | goto do_branch_i; | |
7665 | case M_BLE_I: | |
7666 | s = "slti"; | |
7667 | s2 = "btnez"; | |
7668 | s3 = "x,8"; | |
7669 | goto do_addone_branch_i; | |
7670 | case M_BLEU_I: | |
7671 | s = "sltiu"; | |
7672 | s2 = "btnez"; | |
7673 | s3 = "x,8"; | |
7674 | goto do_addone_branch_i; | |
7675 | case M_BGE_I: | |
7676 | s = "slti"; | |
7677 | s2 = "bteqz"; | |
7678 | s3 = "x,8"; | |
7679 | goto do_branch_i; | |
7680 | case M_BGEU_I: | |
7681 | s = "sltiu"; | |
7682 | s2 = "bteqz"; | |
7683 | s3 = "x,8"; | |
7684 | goto do_branch_i; | |
7685 | case M_BGT_I: | |
7686 | s = "slti"; | |
7687 | s2 = "bteqz"; | |
7688 | s3 = "x,8"; | |
7689 | goto do_addone_branch_i; | |
7690 | case M_BGTU_I: | |
7691 | s = "sltiu"; | |
7692 | s2 = "bteqz"; | |
7693 | s3 = "x,8"; | |
7694 | ||
7695 | do_addone_branch_i: | |
7696 | if (imm_expr.X_op != O_constant) | |
7697 | as_bad (_("Unsupported large constant")); | |
7698 | ++imm_expr.X_add_number; | |
7699 | ||
7700 | do_branch_i: | |
67c0d1eb RS |
7701 | macro_build (&imm_expr, s, s3, xreg); |
7702 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7703 | break; |
7704 | ||
7705 | case M_ABS: | |
7706 | expr1.X_add_number = 0; | |
67c0d1eb | 7707 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7708 | if (xreg != yreg) |
67c0d1eb | 7709 | move_register (xreg, yreg); |
252b5132 | 7710 | expr1.X_add_number = 2; |
67c0d1eb RS |
7711 | macro_build (&expr1, "bteqz", "p"); |
7712 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7713 | } |
7714 | } | |
7715 | ||
7716 | /* For consistency checking, verify that all bits are specified either | |
7717 | by the match/mask part of the instruction definition, or by the | |
7718 | operand list. */ | |
7719 | static int | |
17a2f251 | 7720 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7721 | { |
7722 | const char *p = opc->args; | |
7723 | char c; | |
7724 | unsigned long used_bits = opc->mask; | |
7725 | ||
7726 | if ((used_bits & opc->match) != opc->match) | |
7727 | { | |
7728 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7729 | opc->name, opc->args); | |
7730 | return 0; | |
7731 | } | |
7732 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7733 | while (*p) | |
7734 | switch (c = *p++) | |
7735 | { | |
7736 | case ',': break; | |
7737 | case '(': break; | |
7738 | case ')': break; | |
af7ee8bf CD |
7739 | case '+': |
7740 | switch (c = *p++) | |
7741 | { | |
7742 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7743 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7744 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7745 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7746 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7747 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7748 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7749 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7750 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7751 | case 'I': break; | |
af7ee8bf CD |
7752 | default: |
7753 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7754 | c, opc->name, opc->args); | |
7755 | return 0; | |
7756 | } | |
7757 | break; | |
252b5132 RH |
7758 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7759 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7760 | case 'A': break; | |
4372b673 | 7761 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7762 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7763 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7764 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7765 | case 'F': break; | |
7766 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7767 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7768 | case 'I': break; |
e972090a | 7769 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7770 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7771 | case 'L': break; |
7772 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7773 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7774 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7775 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7776 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7777 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7778 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7779 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7780 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7781 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7782 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7783 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7784 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7785 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7786 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7787 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7788 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7789 | case 'f': break; | |
7790 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7791 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7792 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7793 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7794 | case 'l': break; | |
7795 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7796 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7797 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7798 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7799 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7800 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7801 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7802 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7803 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7804 | case 'x': break; | |
7805 | case 'z': break; | |
7806 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7807 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7808 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7809 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7810 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7811 | case '[': break; | |
7812 | case ']': break; | |
252b5132 RH |
7813 | default: |
7814 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7815 | c, opc->name, opc->args); | |
7816 | return 0; | |
7817 | } | |
7818 | #undef USE_BITS | |
7819 | if (used_bits != 0xffffffff) | |
7820 | { | |
7821 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7822 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7823 | return 0; | |
7824 | } | |
7825 | return 1; | |
7826 | } | |
7827 | ||
7828 | /* This routine assembles an instruction into its binary format. As a | |
7829 | side effect, it sets one of the global variables imm_reloc or | |
7830 | offset_reloc to the type of relocation to do if one of the operands | |
7831 | is an address expression. */ | |
7832 | ||
7833 | static void | |
17a2f251 | 7834 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7835 | { |
7836 | char *s; | |
7837 | const char *args; | |
43841e91 | 7838 | char c = 0; |
252b5132 RH |
7839 | struct mips_opcode *insn; |
7840 | char *argsStart; | |
7841 | unsigned int regno; | |
7842 | unsigned int lastregno = 0; | |
af7ee8bf | 7843 | unsigned int lastpos = 0; |
071742cf | 7844 | unsigned int limlo, limhi; |
252b5132 RH |
7845 | char *s_reset; |
7846 | char save_c = 0; | |
252b5132 RH |
7847 | |
7848 | insn_error = NULL; | |
7849 | ||
7850 | /* If the instruction contains a '.', we first try to match an instruction | |
7851 | including the '.'. Then we try again without the '.'. */ | |
7852 | insn = NULL; | |
3882b010 | 7853 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7854 | continue; |
7855 | ||
7856 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7857 | the call to hash_find. Save the character we replaced just in case we | |
7858 | have to re-parse the instruction. */ | |
3882b010 | 7859 | if (ISSPACE (*s)) |
252b5132 RH |
7860 | { |
7861 | save_c = *s; | |
7862 | *s++ = '\0'; | |
7863 | } | |
bdaaa2e1 | 7864 | |
252b5132 RH |
7865 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7866 | ||
7867 | /* If we didn't find the instruction in the opcode table, try again, but | |
7868 | this time with just the instruction up to, but not including the | |
7869 | first '.'. */ | |
7870 | if (insn == NULL) | |
7871 | { | |
bdaaa2e1 | 7872 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7873 | if (save_c) |
7874 | *(--s) = save_c; | |
7875 | ||
7876 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7877 | for (s = str; |
7878 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7879 | ++s) | |
252b5132 RH |
7880 | continue; |
7881 | ||
7882 | /* If we did not find a '.', then we can quit now. */ | |
7883 | if (*s != '.') | |
7884 | { | |
7885 | insn_error = "unrecognized opcode"; | |
7886 | return; | |
7887 | } | |
7888 | ||
7889 | /* Lookup the instruction in the hash table. */ | |
7890 | *s++ = '\0'; | |
7891 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7892 | { | |
7893 | insn_error = "unrecognized opcode"; | |
7894 | return; | |
7895 | } | |
252b5132 RH |
7896 | } |
7897 | ||
7898 | argsStart = s; | |
7899 | for (;;) | |
7900 | { | |
b34976b6 | 7901 | bfd_boolean ok; |
252b5132 RH |
7902 | |
7903 | assert (strcmp (insn->name, str) == 0); | |
7904 | ||
1f25f5d3 CD |
7905 | if (OPCODE_IS_MEMBER (insn, |
7906 | (mips_opts.isa | |
3396de36 | 7907 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7908 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7909 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7910 | mips_opts.arch)) |
b34976b6 | 7911 | ok = TRUE; |
bdaaa2e1 | 7912 | else |
b34976b6 | 7913 | ok = FALSE; |
bdaaa2e1 | 7914 | |
252b5132 RH |
7915 | if (insn->pinfo != INSN_MACRO) |
7916 | { | |
fef14a42 | 7917 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7918 | ok = FALSE; |
252b5132 RH |
7919 | } |
7920 | ||
7921 | if (! ok) | |
7922 | { | |
7923 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7924 | && strcmp (insn->name, insn[1].name) == 0) | |
7925 | { | |
7926 | ++insn; | |
7927 | continue; | |
7928 | } | |
252b5132 | 7929 | else |
beae10d5 | 7930 | { |
268f6bed L |
7931 | if (!insn_error) |
7932 | { | |
7933 | static char buf[100]; | |
fef14a42 TS |
7934 | sprintf (buf, |
7935 | _("opcode not supported on this processor: %s (%s)"), | |
7936 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7937 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7938 | insn_error = buf; |
7939 | } | |
7940 | if (save_c) | |
7941 | *(--s) = save_c; | |
2bd7f1f3 | 7942 | return; |
252b5132 | 7943 | } |
252b5132 RH |
7944 | } |
7945 | ||
1e915849 | 7946 | create_insn (ip, insn); |
268f6bed | 7947 | insn_error = NULL; |
252b5132 RH |
7948 | for (args = insn->args;; ++args) |
7949 | { | |
deec1734 CD |
7950 | int is_mdmx; |
7951 | ||
ad8d3bb3 | 7952 | s += strspn (s, " \t"); |
deec1734 | 7953 | is_mdmx = 0; |
252b5132 RH |
7954 | switch (*args) |
7955 | { | |
7956 | case '\0': /* end of args */ | |
7957 | if (*s == '\0') | |
7958 | return; | |
7959 | break; | |
7960 | ||
7961 | case ',': | |
7962 | if (*s++ == *args) | |
7963 | continue; | |
7964 | s--; | |
7965 | switch (*++args) | |
7966 | { | |
7967 | case 'r': | |
7968 | case 'v': | |
bf12938e | 7969 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
7970 | continue; |
7971 | ||
7972 | case 'w': | |
bf12938e | 7973 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
7974 | continue; |
7975 | ||
252b5132 | 7976 | case 'W': |
bf12938e | 7977 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
7978 | continue; |
7979 | ||
7980 | case 'V': | |
bf12938e | 7981 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
7982 | continue; |
7983 | } | |
7984 | break; | |
7985 | ||
7986 | case '(': | |
7987 | /* Handle optional base register. | |
7988 | Either the base register is omitted or | |
bdaaa2e1 | 7989 | we must have a left paren. */ |
252b5132 RH |
7990 | /* This is dependent on the next operand specifier |
7991 | is a base register specification. */ | |
7992 | assert (args[1] == 'b' || args[1] == '5' | |
7993 | || args[1] == '-' || args[1] == '4'); | |
7994 | if (*s == '\0') | |
7995 | return; | |
7996 | ||
7997 | case ')': /* these must match exactly */ | |
60b63b72 RS |
7998 | case '[': |
7999 | case ']': | |
252b5132 RH |
8000 | if (*s++ == *args) |
8001 | continue; | |
8002 | break; | |
8003 | ||
af7ee8bf CD |
8004 | case '+': /* Opcode extension character. */ |
8005 | switch (*++args) | |
8006 | { | |
071742cf CD |
8007 | case 'A': /* ins/ext position, becomes LSB. */ |
8008 | limlo = 0; | |
8009 | limhi = 31; | |
5f74bc13 CD |
8010 | goto do_lsb; |
8011 | case 'E': | |
8012 | limlo = 32; | |
8013 | limhi = 63; | |
8014 | goto do_lsb; | |
8015 | do_lsb: | |
071742cf CD |
8016 | my_getExpression (&imm_expr, s); |
8017 | check_absolute_expr (ip, &imm_expr); | |
8018 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8019 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8020 | { | |
8021 | as_bad (_("Improper position (%lu)"), | |
8022 | (unsigned long) imm_expr.X_add_number); | |
8023 | imm_expr.X_add_number = limlo; | |
8024 | } | |
8025 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8026 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8027 | imm_expr.X_op = O_absent; |
8028 | s = expr_end; | |
8029 | continue; | |
8030 | ||
8031 | case 'B': /* ins size, becomes MSB. */ | |
8032 | limlo = 1; | |
8033 | limhi = 32; | |
5f74bc13 CD |
8034 | goto do_msb; |
8035 | case 'F': | |
8036 | limlo = 33; | |
8037 | limhi = 64; | |
8038 | goto do_msb; | |
8039 | do_msb: | |
071742cf CD |
8040 | my_getExpression (&imm_expr, s); |
8041 | check_absolute_expr (ip, &imm_expr); | |
8042 | /* Check for negative input so that small negative numbers | |
8043 | will not succeed incorrectly. The checks against | |
8044 | (pos+size) transitively check "size" itself, | |
8045 | assuming that "pos" is reasonable. */ | |
8046 | if ((long) imm_expr.X_add_number < 0 | |
8047 | || ((unsigned long) imm_expr.X_add_number | |
8048 | + lastpos) < limlo | |
8049 | || ((unsigned long) imm_expr.X_add_number | |
8050 | + lastpos) > limhi) | |
8051 | { | |
8052 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8053 | (unsigned long) imm_expr.X_add_number, | |
8054 | (unsigned long) lastpos); | |
8055 | imm_expr.X_add_number = limlo - lastpos; | |
8056 | } | |
bf12938e RS |
8057 | INSERT_OPERAND (INSMSB, *ip, |
8058 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8059 | imm_expr.X_op = O_absent; |
8060 | s = expr_end; | |
8061 | continue; | |
8062 | ||
8063 | case 'C': /* ext size, becomes MSBD. */ | |
8064 | limlo = 1; | |
8065 | limhi = 32; | |
5f74bc13 CD |
8066 | goto do_msbd; |
8067 | case 'G': | |
8068 | limlo = 33; | |
8069 | limhi = 64; | |
8070 | goto do_msbd; | |
8071 | case 'H': | |
8072 | limlo = 33; | |
8073 | limhi = 64; | |
8074 | goto do_msbd; | |
8075 | do_msbd: | |
071742cf CD |
8076 | my_getExpression (&imm_expr, s); |
8077 | check_absolute_expr (ip, &imm_expr); | |
8078 | /* Check for negative input so that small negative numbers | |
8079 | will not succeed incorrectly. The checks against | |
8080 | (pos+size) transitively check "size" itself, | |
8081 | assuming that "pos" is reasonable. */ | |
8082 | if ((long) imm_expr.X_add_number < 0 | |
8083 | || ((unsigned long) imm_expr.X_add_number | |
8084 | + lastpos) < limlo | |
8085 | || ((unsigned long) imm_expr.X_add_number | |
8086 | + lastpos) > limhi) | |
8087 | { | |
8088 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8089 | (unsigned long) imm_expr.X_add_number, | |
8090 | (unsigned long) lastpos); | |
8091 | imm_expr.X_add_number = limlo - lastpos; | |
8092 | } | |
bf12938e | 8093 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8094 | imm_expr.X_op = O_absent; |
8095 | s = expr_end; | |
8096 | continue; | |
af7ee8bf | 8097 | |
bbcc0807 CD |
8098 | case 'D': |
8099 | /* +D is for disassembly only; never match. */ | |
8100 | break; | |
8101 | ||
5f74bc13 CD |
8102 | case 'I': |
8103 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8104 | my_getExpression (&imm2_expr, s); | |
8105 | if (imm2_expr.X_op != O_big | |
8106 | && imm2_expr.X_op != O_constant) | |
8107 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8108 | if (HAVE_32BIT_GPRS) |
8109 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8110 | s = expr_end; |
8111 | continue; | |
8112 | ||
af7ee8bf CD |
8113 | default: |
8114 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8115 | *args, insn->name, insn->args); | |
8116 | /* Further processing is fruitless. */ | |
8117 | return; | |
8118 | } | |
8119 | break; | |
8120 | ||
252b5132 RH |
8121 | case '<': /* must be at least one digit */ |
8122 | /* | |
8123 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8124 | * than 31 or less than 0, then the shift amount should be |
8125 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8126 | * We issue a warning and mask out all but the low 5 bits. |
8127 | */ | |
8128 | my_getExpression (&imm_expr, s); | |
8129 | check_absolute_expr (ip, &imm_expr); | |
8130 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8131 | as_warn (_("Improper shift amount (%lu)"), |
8132 | (unsigned long) imm_expr.X_add_number); | |
8133 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8134 | imm_expr.X_op = O_absent; |
8135 | s = expr_end; | |
8136 | continue; | |
8137 | ||
8138 | case '>': /* shift amount minus 32 */ | |
8139 | my_getExpression (&imm_expr, s); | |
8140 | check_absolute_expr (ip, &imm_expr); | |
8141 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8142 | || (unsigned long) imm_expr.X_add_number > 63) | |
8143 | break; | |
bf12938e | 8144 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8145 | imm_expr.X_op = O_absent; |
8146 | s = expr_end; | |
8147 | continue; | |
8148 | ||
252b5132 RH |
8149 | case 'k': /* cache code */ |
8150 | case 'h': /* prefx code */ | |
8151 | my_getExpression (&imm_expr, s); | |
8152 | check_absolute_expr (ip, &imm_expr); | |
8153 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8154 | as_warn (_("Invalid value for `%s' (%lu)"), |
8155 | ip->insn_mo->name, | |
8156 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8157 | if (*args == 'k') |
bf12938e | 8158 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8159 | else |
bf12938e | 8160 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8161 | imm_expr.X_op = O_absent; |
8162 | s = expr_end; | |
8163 | continue; | |
8164 | ||
8165 | case 'c': /* break code */ | |
8166 | my_getExpression (&imm_expr, s); | |
8167 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8168 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8169 | as_warn (_("Illegal break code (%lu)"), |
8170 | (unsigned long) imm_expr.X_add_number); | |
8171 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8172 | imm_expr.X_op = O_absent; |
8173 | s = expr_end; | |
8174 | continue; | |
8175 | ||
8176 | case 'q': /* lower break code */ | |
8177 | my_getExpression (&imm_expr, s); | |
8178 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8179 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8180 | as_warn (_("Illegal lower break code (%lu)"), |
8181 | (unsigned long) imm_expr.X_add_number); | |
8182 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8183 | imm_expr.X_op = O_absent; |
8184 | s = expr_end; | |
8185 | continue; | |
8186 | ||
4372b673 | 8187 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8188 | my_getExpression (&imm_expr, s); |
156c2f8b | 8189 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8190 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8191 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8192 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8193 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8194 | imm_expr.X_op = O_absent; |
8195 | s = expr_end; | |
8196 | continue; | |
8197 | ||
98d3f06f | 8198 | case 'C': /* Coprocessor code */ |
beae10d5 | 8199 | my_getExpression (&imm_expr, s); |
252b5132 | 8200 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8201 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8202 | { |
793b27f4 TS |
8203 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8204 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8205 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8206 | } |
beae10d5 KH |
8207 | ip->insn_opcode |= imm_expr.X_add_number; |
8208 | imm_expr.X_op = O_absent; | |
8209 | s = expr_end; | |
8210 | continue; | |
252b5132 | 8211 | |
4372b673 NC |
8212 | case 'J': /* 19-bit wait code. */ |
8213 | my_getExpression (&imm_expr, s); | |
8214 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8215 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8216 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8217 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8218 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8219 | imm_expr.X_op = O_absent; |
8220 | s = expr_end; | |
8221 | continue; | |
8222 | ||
252b5132 | 8223 | case 'P': /* Performance register */ |
beae10d5 | 8224 | my_getExpression (&imm_expr, s); |
252b5132 | 8225 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8226 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8227 | as_warn (_("Invalid performance register (%lu)"), |
8228 | (unsigned long) imm_expr.X_add_number); | |
8229 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8230 | imm_expr.X_op = O_absent; |
8231 | s = expr_end; | |
8232 | continue; | |
252b5132 RH |
8233 | |
8234 | case 'b': /* base register */ | |
8235 | case 'd': /* destination register */ | |
8236 | case 's': /* source register */ | |
8237 | case 't': /* target register */ | |
8238 | case 'r': /* both target and source */ | |
8239 | case 'v': /* both dest and source */ | |
8240 | case 'w': /* both dest and target */ | |
8241 | case 'E': /* coprocessor target register */ | |
8242 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8243 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8244 | case 'x': /* ignore register name */ |
8245 | case 'z': /* must be zero register */ | |
4372b673 | 8246 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8247 | s_reset = s; |
8248 | if (s[0] == '$') | |
8249 | { | |
8250 | ||
3882b010 | 8251 | if (ISDIGIT (s[1])) |
252b5132 RH |
8252 | { |
8253 | ++s; | |
8254 | regno = 0; | |
8255 | do | |
8256 | { | |
8257 | regno *= 10; | |
8258 | regno += *s - '0'; | |
8259 | ++s; | |
8260 | } | |
3882b010 | 8261 | while (ISDIGIT (*s)); |
252b5132 RH |
8262 | if (regno > 31) |
8263 | as_bad (_("Invalid register number (%d)"), regno); | |
8264 | } | |
af7ee8bf | 8265 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8266 | goto notreg; |
8267 | else | |
8268 | { | |
76db943d TS |
8269 | if (s[1] == 'r' && s[2] == 'a') |
8270 | { | |
8271 | s += 3; | |
8272 | regno = RA; | |
8273 | } | |
8274 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8275 | { |
8276 | s += 3; | |
8277 | regno = FP; | |
8278 | } | |
8279 | else if (s[1] == 's' && s[2] == 'p') | |
8280 | { | |
8281 | s += 3; | |
8282 | regno = SP; | |
8283 | } | |
8284 | else if (s[1] == 'g' && s[2] == 'p') | |
8285 | { | |
8286 | s += 3; | |
8287 | regno = GP; | |
8288 | } | |
8289 | else if (s[1] == 'a' && s[2] == 't') | |
8290 | { | |
8291 | s += 3; | |
8292 | regno = AT; | |
8293 | } | |
8294 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8295 | { | |
8296 | s += 4; | |
8297 | regno = KT0; | |
8298 | } | |
8299 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8300 | { | |
8301 | s += 4; | |
8302 | regno = KT1; | |
8303 | } | |
85b51719 TS |
8304 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8305 | { | |
8306 | s += 5; | |
8307 | regno = ZERO; | |
8308 | } | |
252b5132 RH |
8309 | else if (itbl_have_entries) |
8310 | { | |
8311 | char *p, *n; | |
d7ba4a77 | 8312 | unsigned long r; |
252b5132 | 8313 | |
d7ba4a77 | 8314 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8315 | n = itbl_get_field (&p); /* n is name */ |
8316 | ||
d7ba4a77 ILT |
8317 | /* See if this is a register defined in an |
8318 | itbl entry. */ | |
8319 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8320 | { |
8321 | /* Get_field advances to the start of | |
8322 | the next field, so we need to back | |
d7ba4a77 | 8323 | rack to the end of the last field. */ |
bdaaa2e1 | 8324 | if (p) |
252b5132 | 8325 | s = p - 1; |
bdaaa2e1 | 8326 | else |
d7ba4a77 | 8327 | s = strchr (s, '\0'); |
252b5132 RH |
8328 | regno = r; |
8329 | } | |
8330 | else | |
8331 | goto notreg; | |
beae10d5 | 8332 | } |
252b5132 RH |
8333 | else |
8334 | goto notreg; | |
8335 | } | |
8336 | if (regno == AT | |
8337 | && ! mips_opts.noat | |
8338 | && *args != 'E' | |
af7ee8bf CD |
8339 | && *args != 'G' |
8340 | && *args != 'K') | |
252b5132 RH |
8341 | as_warn (_("Used $at without \".set noat\"")); |
8342 | c = *args; | |
8343 | if (*s == ' ') | |
f9419b05 | 8344 | ++s; |
252b5132 RH |
8345 | if (args[1] != *s) |
8346 | { | |
8347 | if (c == 'r' || c == 'v' || c == 'w') | |
8348 | { | |
8349 | regno = lastregno; | |
8350 | s = s_reset; | |
f9419b05 | 8351 | ++args; |
252b5132 RH |
8352 | } |
8353 | } | |
8354 | /* 'z' only matches $0. */ | |
8355 | if (c == 'z' && regno != 0) | |
8356 | break; | |
8357 | ||
bdaaa2e1 KH |
8358 | /* Now that we have assembled one operand, we use the args string |
8359 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8360 | switch (c) |
8361 | { | |
8362 | case 'r': | |
8363 | case 's': | |
8364 | case 'v': | |
8365 | case 'b': | |
bf12938e | 8366 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8367 | break; |
8368 | case 'd': | |
8369 | case 'G': | |
af7ee8bf | 8370 | case 'K': |
bf12938e | 8371 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8372 | break; |
4372b673 | 8373 | case 'U': |
bf12938e RS |
8374 | INSERT_OPERAND (RD, *ip, regno); |
8375 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8376 | break; |
252b5132 RH |
8377 | case 'w': |
8378 | case 't': | |
8379 | case 'E': | |
bf12938e | 8380 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8381 | break; |
8382 | case 'x': | |
8383 | /* This case exists because on the r3000 trunc | |
8384 | expands into a macro which requires a gp | |
8385 | register. On the r6000 or r4000 it is | |
8386 | assembled into a single instruction which | |
8387 | ignores the register. Thus the insn version | |
8388 | is MIPS_ISA2 and uses 'x', and the macro | |
8389 | version is MIPS_ISA1 and uses 't'. */ | |
8390 | break; | |
8391 | case 'z': | |
8392 | /* This case is for the div instruction, which | |
8393 | acts differently if the destination argument | |
8394 | is $0. This only matches $0, and is checked | |
8395 | outside the switch. */ | |
8396 | break; | |
8397 | case 'D': | |
8398 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8399 | break; | |
8400 | /* What about all other operands like 'i', which | |
8401 | can be specified in the opcode table? */ | |
8402 | } | |
8403 | lastregno = regno; | |
8404 | continue; | |
8405 | } | |
8406 | notreg: | |
8407 | switch (*args++) | |
8408 | { | |
8409 | case 'r': | |
8410 | case 'v': | |
bf12938e | 8411 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8412 | continue; |
8413 | case 'w': | |
bf12938e | 8414 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8415 | continue; |
8416 | } | |
8417 | break; | |
8418 | ||
deec1734 CD |
8419 | case 'O': /* MDMX alignment immediate constant. */ |
8420 | my_getExpression (&imm_expr, s); | |
8421 | check_absolute_expr (ip, &imm_expr); | |
8422 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8423 | as_warn ("Improper align amount (%ld), using low bits", |
8424 | (long) imm_expr.X_add_number); | |
8425 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8426 | imm_expr.X_op = O_absent; |
8427 | s = expr_end; | |
8428 | continue; | |
8429 | ||
8430 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8431 | if (s[0] != '$') | |
8432 | { | |
8433 | /* MDMX Immediate. */ | |
8434 | my_getExpression (&imm_expr, s); | |
8435 | check_absolute_expr (ip, &imm_expr); | |
8436 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8437 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8438 | (long) imm_expr.X_add_number); | |
8439 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8440 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8441 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8442 | else | |
8443 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8444 | imm_expr.X_op = O_absent; |
8445 | s = expr_end; | |
8446 | continue; | |
8447 | } | |
8448 | /* Not MDMX Immediate. Fall through. */ | |
8449 | case 'X': /* MDMX destination register. */ | |
8450 | case 'Y': /* MDMX source register. */ | |
8451 | case 'Z': /* MDMX target register. */ | |
8452 | is_mdmx = 1; | |
252b5132 RH |
8453 | case 'D': /* floating point destination register */ |
8454 | case 'S': /* floating point source register */ | |
8455 | case 'T': /* floating point target register */ | |
8456 | case 'R': /* floating point source register */ | |
8457 | case 'V': | |
8458 | case 'W': | |
8459 | s_reset = s; | |
deec1734 CD |
8460 | /* Accept $fN for FP and MDMX register numbers, and in |
8461 | addition accept $vN for MDMX register numbers. */ | |
8462 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8463 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8464 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8465 | { |
8466 | s += 2; | |
8467 | regno = 0; | |
8468 | do | |
8469 | { | |
8470 | regno *= 10; | |
8471 | regno += *s - '0'; | |
8472 | ++s; | |
8473 | } | |
3882b010 | 8474 | while (ISDIGIT (*s)); |
252b5132 RH |
8475 | |
8476 | if (regno > 31) | |
8477 | as_bad (_("Invalid float register number (%d)"), regno); | |
8478 | ||
8479 | if ((regno & 1) != 0 | |
ca4e0257 | 8480 | && HAVE_32BIT_FPRS |
252b5132 RH |
8481 | && ! (strcmp (str, "mtc1") == 0 |
8482 | || strcmp (str, "mfc1") == 0 | |
8483 | || strcmp (str, "lwc1") == 0 | |
8484 | || strcmp (str, "swc1") == 0 | |
8485 | || strcmp (str, "l.s") == 0 | |
8486 | || strcmp (str, "s.s") == 0)) | |
8487 | as_warn (_("Float register should be even, was %d"), | |
8488 | regno); | |
8489 | ||
8490 | c = *args; | |
8491 | if (*s == ' ') | |
f9419b05 | 8492 | ++s; |
252b5132 RH |
8493 | if (args[1] != *s) |
8494 | { | |
8495 | if (c == 'V' || c == 'W') | |
8496 | { | |
8497 | regno = lastregno; | |
8498 | s = s_reset; | |
f9419b05 | 8499 | ++args; |
252b5132 RH |
8500 | } |
8501 | } | |
8502 | switch (c) | |
8503 | { | |
8504 | case 'D': | |
deec1734 | 8505 | case 'X': |
bf12938e | 8506 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8507 | break; |
8508 | case 'V': | |
8509 | case 'S': | |
deec1734 | 8510 | case 'Y': |
bf12938e | 8511 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8512 | break; |
deec1734 CD |
8513 | case 'Q': |
8514 | /* This is like 'Z', but also needs to fix the MDMX | |
8515 | vector/scalar select bits. Note that the | |
8516 | scalar immediate case is handled above. */ | |
8517 | if (*s == '[') | |
8518 | { | |
8519 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8520 | int max_el = (is_qh ? 3 : 7); | |
8521 | s++; | |
8522 | my_getExpression(&imm_expr, s); | |
8523 | check_absolute_expr (ip, &imm_expr); | |
8524 | s = expr_end; | |
8525 | if (imm_expr.X_add_number > max_el) | |
8526 | as_bad(_("Bad element selector %ld"), | |
8527 | (long) imm_expr.X_add_number); | |
8528 | imm_expr.X_add_number &= max_el; | |
8529 | ip->insn_opcode |= (imm_expr.X_add_number | |
8530 | << (OP_SH_VSEL + | |
8531 | (is_qh ? 2 : 1))); | |
01a3f561 | 8532 | imm_expr.X_op = O_absent; |
deec1734 CD |
8533 | if (*s != ']') |
8534 | as_warn(_("Expecting ']' found '%s'"), s); | |
8535 | else | |
8536 | s++; | |
8537 | } | |
8538 | else | |
8539 | { | |
8540 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8541 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8542 | << OP_SH_VSEL); | |
8543 | else | |
8544 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8545 | OP_SH_VSEL); | |
8546 | } | |
8547 | /* Fall through */ | |
252b5132 RH |
8548 | case 'W': |
8549 | case 'T': | |
deec1734 | 8550 | case 'Z': |
bf12938e | 8551 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8552 | break; |
8553 | case 'R': | |
bf12938e | 8554 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8555 | break; |
8556 | } | |
8557 | lastregno = regno; | |
8558 | continue; | |
8559 | } | |
8560 | ||
252b5132 RH |
8561 | switch (*args++) |
8562 | { | |
8563 | case 'V': | |
bf12938e | 8564 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8565 | continue; |
8566 | case 'W': | |
bf12938e | 8567 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8568 | continue; |
8569 | } | |
8570 | break; | |
8571 | ||
8572 | case 'I': | |
8573 | my_getExpression (&imm_expr, s); | |
8574 | if (imm_expr.X_op != O_big | |
8575 | && imm_expr.X_op != O_constant) | |
8576 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8577 | if (HAVE_32BIT_GPRS) |
8578 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
8579 | s = expr_end; |
8580 | continue; | |
8581 | ||
8582 | case 'A': | |
8583 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 8584 | normalize_address_expr (&offset_expr); |
f6688943 | 8585 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8586 | s = expr_end; |
8587 | continue; | |
8588 | ||
8589 | case 'F': | |
8590 | case 'L': | |
8591 | case 'f': | |
8592 | case 'l': | |
8593 | { | |
8594 | int f64; | |
ca4e0257 | 8595 | int using_gprs; |
252b5132 RH |
8596 | char *save_in; |
8597 | char *err; | |
8598 | unsigned char temp[8]; | |
8599 | int len; | |
8600 | unsigned int length; | |
8601 | segT seg; | |
8602 | subsegT subseg; | |
8603 | char *p; | |
8604 | ||
8605 | /* These only appear as the last operand in an | |
8606 | instruction, and every instruction that accepts | |
8607 | them in any variant accepts them in all variants. | |
8608 | This means we don't have to worry about backing out | |
8609 | any changes if the instruction does not match. | |
8610 | ||
8611 | The difference between them is the size of the | |
8612 | floating point constant and where it goes. For 'F' | |
8613 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8614 | is 32 bits. Where the constant is placed is based | |
8615 | on how the MIPS assembler does things: | |
8616 | F -- .rdata | |
8617 | L -- .lit8 | |
8618 | f -- immediate value | |
8619 | l -- .lit4 | |
8620 | ||
8621 | The .lit4 and .lit8 sections are only used if | |
8622 | permitted by the -G argument. | |
8623 | ||
ca4e0257 RS |
8624 | The code below needs to know whether the target register |
8625 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8626 | 'F' are used with GPR-based instructions and 'l' and | |
8627 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8628 | |
8629 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8630 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8631 | |
8632 | save_in = input_line_pointer; | |
8633 | input_line_pointer = s; | |
8634 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8635 | length = len; | |
8636 | s = input_line_pointer; | |
8637 | input_line_pointer = save_in; | |
8638 | if (err != NULL && *err != '\0') | |
8639 | { | |
8640 | as_bad (_("Bad floating point constant: %s"), err); | |
8641 | memset (temp, '\0', sizeof temp); | |
8642 | length = f64 ? 8 : 4; | |
8643 | } | |
8644 | ||
156c2f8b | 8645 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8646 | |
8647 | if (*args == 'f' | |
8648 | || (*args == 'l' | |
3e722fb5 | 8649 | && (g_switch_value < 4 |
252b5132 RH |
8650 | || (temp[0] == 0 && temp[1] == 0) |
8651 | || (temp[2] == 0 && temp[3] == 0)))) | |
8652 | { | |
8653 | imm_expr.X_op = O_constant; | |
8654 | if (! target_big_endian) | |
8655 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8656 | else | |
8657 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8658 | } | |
8659 | else if (length > 4 | |
119d663a | 8660 | && ! mips_disable_float_construction |
ca4e0257 RS |
8661 | /* Constants can only be constructed in GPRs and |
8662 | copied to FPRs if the GPRs are at least as wide | |
8663 | as the FPRs. Force the constant into memory if | |
8664 | we are using 64-bit FPRs but the GPRs are only | |
8665 | 32 bits wide. */ | |
8666 | && (using_gprs | |
8667 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8668 | && ((temp[0] == 0 && temp[1] == 0) |
8669 | || (temp[2] == 0 && temp[3] == 0)) | |
8670 | && ((temp[4] == 0 && temp[5] == 0) | |
8671 | || (temp[6] == 0 && temp[7] == 0))) | |
8672 | { | |
ca4e0257 RS |
8673 | /* The value is simple enough to load with a couple of |
8674 | instructions. If using 32-bit registers, set | |
8675 | imm_expr to the high order 32 bits and offset_expr to | |
8676 | the low order 32 bits. Otherwise, set imm_expr to | |
8677 | the entire 64 bit constant. */ | |
8678 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8679 | { |
8680 | imm_expr.X_op = O_constant; | |
8681 | offset_expr.X_op = O_constant; | |
8682 | if (! target_big_endian) | |
8683 | { | |
8684 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8685 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8686 | } | |
8687 | else | |
8688 | { | |
8689 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8690 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8691 | } | |
8692 | if (offset_expr.X_add_number == 0) | |
8693 | offset_expr.X_op = O_absent; | |
8694 | } | |
8695 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8696 | { | |
8697 | imm_expr.X_op = O_constant; | |
8698 | if (! target_big_endian) | |
8699 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8700 | else | |
8701 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8702 | } | |
8703 | else | |
8704 | { | |
8705 | imm_expr.X_op = O_big; | |
8706 | imm_expr.X_add_number = 4; | |
8707 | if (! target_big_endian) | |
8708 | { | |
8709 | generic_bignum[0] = bfd_getl16 (temp); | |
8710 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8711 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8712 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8713 | } | |
8714 | else | |
8715 | { | |
8716 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8717 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8718 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8719 | generic_bignum[3] = bfd_getb16 (temp); | |
8720 | } | |
8721 | } | |
8722 | } | |
8723 | else | |
8724 | { | |
8725 | const char *newname; | |
8726 | segT new_seg; | |
8727 | ||
8728 | /* Switch to the right section. */ | |
8729 | seg = now_seg; | |
8730 | subseg = now_subseg; | |
8731 | switch (*args) | |
8732 | { | |
8733 | default: /* unused default case avoids warnings. */ | |
8734 | case 'L': | |
8735 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8736 | if (g_switch_value >= 8) |
252b5132 RH |
8737 | newname = ".lit8"; |
8738 | break; | |
8739 | case 'F': | |
3e722fb5 | 8740 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8741 | break; |
8742 | case 'l': | |
4d0d148d | 8743 | assert (g_switch_value >= 4); |
252b5132 RH |
8744 | newname = ".lit4"; |
8745 | break; | |
8746 | } | |
8747 | new_seg = subseg_new (newname, (subsegT) 0); | |
8748 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8749 | bfd_set_section_flags (stdoutput, new_seg, | |
8750 | (SEC_ALLOC | |
8751 | | SEC_LOAD | |
8752 | | SEC_READONLY | |
8753 | | SEC_DATA)); | |
8754 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8755 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8756 | && strcmp (TARGET_OS, "elf") != 0) | |
8757 | record_alignment (new_seg, 4); | |
8758 | else | |
8759 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8760 | if (seg == now_seg) | |
8761 | as_bad (_("Can't use floating point insn in this section")); | |
8762 | ||
8763 | /* Set the argument to the current address in the | |
8764 | section. */ | |
8765 | offset_expr.X_op = O_symbol; | |
8766 | offset_expr.X_add_symbol = | |
8767 | symbol_new ("L0\001", now_seg, | |
8768 | (valueT) frag_now_fix (), frag_now); | |
8769 | offset_expr.X_add_number = 0; | |
8770 | ||
8771 | /* Put the floating point number into the section. */ | |
8772 | p = frag_more ((int) length); | |
8773 | memcpy (p, temp, length); | |
8774 | ||
8775 | /* Switch back to the original section. */ | |
8776 | subseg_set (seg, subseg); | |
8777 | } | |
8778 | } | |
8779 | continue; | |
8780 | ||
8781 | case 'i': /* 16 bit unsigned immediate */ | |
8782 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8783 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8784 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8785 | { |
8786 | int more; | |
5e0116d5 RS |
8787 | offsetT minval, maxval; |
8788 | ||
8789 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8790 | && strcmp (insn->name, insn[1].name) == 0); | |
8791 | ||
8792 | /* If the expression was written as an unsigned number, | |
8793 | only treat it as signed if there are no more | |
8794 | alternatives. */ | |
8795 | if (more | |
8796 | && *args == 'j' | |
8797 | && sizeof (imm_expr.X_add_number) <= 4 | |
8798 | && imm_expr.X_op == O_constant | |
8799 | && imm_expr.X_add_number < 0 | |
8800 | && imm_expr.X_unsigned | |
8801 | && HAVE_64BIT_GPRS) | |
8802 | break; | |
8803 | ||
8804 | /* For compatibility with older assemblers, we accept | |
8805 | 0x8000-0xffff as signed 16-bit numbers when only | |
8806 | signed numbers are allowed. */ | |
8807 | if (*args == 'i') | |
8808 | minval = 0, maxval = 0xffff; | |
8809 | else if (more) | |
8810 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8811 | else |
5e0116d5 RS |
8812 | minval = -0x8000, maxval = 0xffff; |
8813 | ||
8814 | if (imm_expr.X_op != O_constant | |
8815 | || imm_expr.X_add_number < minval | |
8816 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8817 | { |
8818 | if (more) | |
8819 | break; | |
2ae7e77b AH |
8820 | if (imm_expr.X_op == O_constant |
8821 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8822 | as_bad (_("expression out of range")); |
252b5132 RH |
8823 | } |
8824 | } | |
8825 | s = expr_end; | |
8826 | continue; | |
8827 | ||
8828 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8829 | /* Check whether there is only a single bracketed expression |
8830 | left. If so, it must be the base register and the | |
8831 | constant must be zero. */ | |
8832 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8833 | { | |
8834 | offset_expr.X_op = O_constant; | |
8835 | offset_expr.X_add_number = 0; | |
8836 | continue; | |
8837 | } | |
252b5132 RH |
8838 | |
8839 | /* If this value won't fit into a 16 bit offset, then go | |
8840 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8841 | code pattern. */ |
5e0116d5 | 8842 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8843 | && (offset_expr.X_op != O_constant |
8844 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8845 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8846 | break; |
8847 | ||
252b5132 RH |
8848 | s = expr_end; |
8849 | continue; | |
8850 | ||
8851 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8852 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8853 | my_getExpression (&offset_expr, s); |
8854 | s = expr_end; | |
8855 | continue; | |
8856 | ||
8857 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8858 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8859 | && imm_expr.X_op == O_constant | |
8860 | && (imm_expr.X_add_number < 0 | |
8861 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8862 | as_bad (_("lui expression not in range 0..65535")); |
8863 | s = expr_end; | |
8864 | continue; | |
8865 | ||
8866 | case 'a': /* 26 bit address */ | |
8867 | my_getExpression (&offset_expr, s); | |
8868 | s = expr_end; | |
f6688943 | 8869 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8870 | continue; |
8871 | ||
8872 | case 'N': /* 3 bit branch condition code */ | |
8873 | case 'M': /* 3 bit compare condition code */ | |
8874 | if (strncmp (s, "$fcc", 4) != 0) | |
8875 | break; | |
8876 | s += 4; | |
8877 | regno = 0; | |
8878 | do | |
8879 | { | |
8880 | regno *= 10; | |
8881 | regno += *s - '0'; | |
8882 | ++s; | |
8883 | } | |
3882b010 | 8884 | while (ISDIGIT (*s)); |
252b5132 | 8885 | if (regno > 7) |
30c378fd CD |
8886 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8887 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8888 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8889 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8890 | && (regno & 1) != 0) | |
8891 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8892 | str, regno); | |
8893 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8894 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8895 | && (regno & 3) != 0) | |
8896 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8897 | str, regno); | |
252b5132 | 8898 | if (*args == 'N') |
bf12938e | 8899 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 8900 | else |
bf12938e | 8901 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 8902 | continue; |
252b5132 | 8903 | |
156c2f8b NC |
8904 | case 'H': |
8905 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8906 | s += 2; | |
3882b010 | 8907 | if (ISDIGIT (*s)) |
156c2f8b NC |
8908 | { |
8909 | c = 0; | |
8910 | do | |
8911 | { | |
8912 | c *= 10; | |
8913 | c += *s - '0'; | |
8914 | ++s; | |
8915 | } | |
3882b010 | 8916 | while (ISDIGIT (*s)); |
156c2f8b NC |
8917 | } |
8918 | else | |
8919 | c = 8; /* Invalid sel value. */ | |
8920 | ||
8921 | if (c > 7) | |
8922 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8923 | ip->insn_opcode |= c; | |
8924 | continue; | |
8925 | ||
60b63b72 RS |
8926 | case 'e': |
8927 | /* Must be at least one digit. */ | |
8928 | my_getExpression (&imm_expr, s); | |
8929 | check_absolute_expr (ip, &imm_expr); | |
8930 | ||
8931 | if ((unsigned long) imm_expr.X_add_number | |
8932 | > (unsigned long) OP_MASK_VECBYTE) | |
8933 | { | |
8934 | as_bad (_("bad byte vector index (%ld)"), | |
8935 | (long) imm_expr.X_add_number); | |
8936 | imm_expr.X_add_number = 0; | |
8937 | } | |
8938 | ||
bf12938e | 8939 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8940 | imm_expr.X_op = O_absent; |
8941 | s = expr_end; | |
8942 | continue; | |
8943 | ||
8944 | case '%': | |
8945 | my_getExpression (&imm_expr, s); | |
8946 | check_absolute_expr (ip, &imm_expr); | |
8947 | ||
8948 | if ((unsigned long) imm_expr.X_add_number | |
8949 | > (unsigned long) OP_MASK_VECALIGN) | |
8950 | { | |
8951 | as_bad (_("bad byte vector index (%ld)"), | |
8952 | (long) imm_expr.X_add_number); | |
8953 | imm_expr.X_add_number = 0; | |
8954 | } | |
8955 | ||
bf12938e | 8956 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8957 | imm_expr.X_op = O_absent; |
8958 | s = expr_end; | |
8959 | continue; | |
8960 | ||
252b5132 RH |
8961 | default: |
8962 | as_bad (_("bad char = '%c'\n"), *args); | |
8963 | internalError (); | |
8964 | } | |
8965 | break; | |
8966 | } | |
8967 | /* Args don't match. */ | |
8968 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8969 | !strcmp (insn->name, insn[1].name)) | |
8970 | { | |
8971 | ++insn; | |
8972 | s = argsStart; | |
268f6bed | 8973 | insn_error = _("illegal operands"); |
252b5132 RH |
8974 | continue; |
8975 | } | |
268f6bed L |
8976 | if (save_c) |
8977 | *(--s) = save_c; | |
252b5132 RH |
8978 | insn_error = _("illegal operands"); |
8979 | return; | |
8980 | } | |
8981 | } | |
8982 | ||
8983 | /* This routine assembles an instruction into its binary format when | |
8984 | assembling for the mips16. As a side effect, it sets one of the | |
8985 | global variables imm_reloc or offset_reloc to the type of | |
8986 | relocation to do if one of the operands is an address expression. | |
8987 | It also sets mips16_small and mips16_ext if the user explicitly | |
8988 | requested a small or extended instruction. */ | |
8989 | ||
8990 | static void | |
17a2f251 | 8991 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8992 | { |
8993 | char *s; | |
8994 | const char *args; | |
8995 | struct mips_opcode *insn; | |
8996 | char *argsstart; | |
8997 | unsigned int regno; | |
8998 | unsigned int lastregno = 0; | |
8999 | char *s_reset; | |
d6f16593 | 9000 | size_t i; |
252b5132 RH |
9001 | |
9002 | insn_error = NULL; | |
9003 | ||
b34976b6 AM |
9004 | mips16_small = FALSE; |
9005 | mips16_ext = FALSE; | |
252b5132 | 9006 | |
3882b010 | 9007 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9008 | ; |
9009 | switch (*s) | |
9010 | { | |
9011 | case '\0': | |
9012 | break; | |
9013 | ||
9014 | case ' ': | |
9015 | *s++ = '\0'; | |
9016 | break; | |
9017 | ||
9018 | case '.': | |
9019 | if (s[1] == 't' && s[2] == ' ') | |
9020 | { | |
9021 | *s = '\0'; | |
b34976b6 | 9022 | mips16_small = TRUE; |
252b5132 RH |
9023 | s += 3; |
9024 | break; | |
9025 | } | |
9026 | else if (s[1] == 'e' && s[2] == ' ') | |
9027 | { | |
9028 | *s = '\0'; | |
b34976b6 | 9029 | mips16_ext = TRUE; |
252b5132 RH |
9030 | s += 3; |
9031 | break; | |
9032 | } | |
9033 | /* Fall through. */ | |
9034 | default: | |
9035 | insn_error = _("unknown opcode"); | |
9036 | return; | |
9037 | } | |
9038 | ||
9039 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9040 | mips16_small = TRUE; |
252b5132 RH |
9041 | |
9042 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9043 | { | |
9044 | insn_error = _("unrecognized opcode"); | |
9045 | return; | |
9046 | } | |
9047 | ||
9048 | argsstart = s; | |
9049 | for (;;) | |
9050 | { | |
9051 | assert (strcmp (insn->name, str) == 0); | |
9052 | ||
1e915849 | 9053 | create_insn (ip, insn); |
252b5132 | 9054 | imm_expr.X_op = O_absent; |
f6688943 TS |
9055 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9056 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9057 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9058 | imm2_expr.X_op = O_absent; |
252b5132 | 9059 | offset_expr.X_op = O_absent; |
f6688943 TS |
9060 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9061 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9062 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9063 | for (args = insn->args; 1; ++args) |
9064 | { | |
9065 | int c; | |
9066 | ||
9067 | if (*s == ' ') | |
9068 | ++s; | |
9069 | ||
9070 | /* In this switch statement we call break if we did not find | |
9071 | a match, continue if we did find a match, or return if we | |
9072 | are done. */ | |
9073 | ||
9074 | c = *args; | |
9075 | switch (c) | |
9076 | { | |
9077 | case '\0': | |
9078 | if (*s == '\0') | |
9079 | { | |
9080 | /* Stuff the immediate value in now, if we can. */ | |
9081 | if (imm_expr.X_op == O_constant | |
f6688943 | 9082 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9083 | && insn->pinfo != INSN_MACRO) |
9084 | { | |
d6f16593 MR |
9085 | valueT tmp; |
9086 | ||
9087 | switch (*offset_reloc) | |
9088 | { | |
9089 | case BFD_RELOC_MIPS16_HI16_S: | |
9090 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9091 | break; | |
9092 | ||
9093 | case BFD_RELOC_MIPS16_HI16: | |
9094 | tmp = imm_expr.X_add_number >> 16; | |
9095 | break; | |
9096 | ||
9097 | case BFD_RELOC_MIPS16_LO16: | |
9098 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9099 | - 0x8000; | |
9100 | break; | |
9101 | ||
9102 | case BFD_RELOC_UNUSED: | |
9103 | tmp = imm_expr.X_add_number; | |
9104 | break; | |
9105 | ||
9106 | default: | |
9107 | internalError (); | |
9108 | } | |
9109 | *offset_reloc = BFD_RELOC_UNUSED; | |
9110 | ||
c4e7957c | 9111 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9112 | tmp, TRUE, mips16_small, |
252b5132 RH |
9113 | mips16_ext, &ip->insn_opcode, |
9114 | &ip->use_extend, &ip->extend); | |
9115 | imm_expr.X_op = O_absent; | |
f6688943 | 9116 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9117 | } |
9118 | ||
9119 | return; | |
9120 | } | |
9121 | break; | |
9122 | ||
9123 | case ',': | |
9124 | if (*s++ == c) | |
9125 | continue; | |
9126 | s--; | |
9127 | switch (*++args) | |
9128 | { | |
9129 | case 'v': | |
bf12938e | 9130 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9131 | continue; |
9132 | case 'w': | |
bf12938e | 9133 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9134 | continue; |
9135 | } | |
9136 | break; | |
9137 | ||
9138 | case '(': | |
9139 | case ')': | |
9140 | if (*s++ == c) | |
9141 | continue; | |
9142 | break; | |
9143 | ||
9144 | case 'v': | |
9145 | case 'w': | |
9146 | if (s[0] != '$') | |
9147 | { | |
9148 | if (c == 'v') | |
bf12938e | 9149 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9150 | else |
bf12938e | 9151 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9152 | ++args; |
9153 | continue; | |
9154 | } | |
9155 | /* Fall through. */ | |
9156 | case 'x': | |
9157 | case 'y': | |
9158 | case 'z': | |
9159 | case 'Z': | |
9160 | case '0': | |
9161 | case 'S': | |
9162 | case 'R': | |
9163 | case 'X': | |
9164 | case 'Y': | |
9165 | if (s[0] != '$') | |
9166 | break; | |
9167 | s_reset = s; | |
3882b010 | 9168 | if (ISDIGIT (s[1])) |
252b5132 RH |
9169 | { |
9170 | ++s; | |
9171 | regno = 0; | |
9172 | do | |
9173 | { | |
9174 | regno *= 10; | |
9175 | regno += *s - '0'; | |
9176 | ++s; | |
9177 | } | |
3882b010 | 9178 | while (ISDIGIT (*s)); |
252b5132 RH |
9179 | if (regno > 31) |
9180 | { | |
9181 | as_bad (_("invalid register number (%d)"), regno); | |
9182 | regno = 2; | |
9183 | } | |
9184 | } | |
9185 | else | |
9186 | { | |
76db943d TS |
9187 | if (s[1] == 'r' && s[2] == 'a') |
9188 | { | |
9189 | s += 3; | |
9190 | regno = RA; | |
9191 | } | |
9192 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9193 | { |
9194 | s += 3; | |
9195 | regno = FP; | |
9196 | } | |
9197 | else if (s[1] == 's' && s[2] == 'p') | |
9198 | { | |
9199 | s += 3; | |
9200 | regno = SP; | |
9201 | } | |
9202 | else if (s[1] == 'g' && s[2] == 'p') | |
9203 | { | |
9204 | s += 3; | |
9205 | regno = GP; | |
9206 | } | |
9207 | else if (s[1] == 'a' && s[2] == 't') | |
9208 | { | |
9209 | s += 3; | |
9210 | regno = AT; | |
9211 | } | |
9212 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9213 | { | |
9214 | s += 4; | |
9215 | regno = KT0; | |
9216 | } | |
9217 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9218 | { | |
9219 | s += 4; | |
9220 | regno = KT1; | |
9221 | } | |
85b51719 TS |
9222 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9223 | { | |
9224 | s += 5; | |
9225 | regno = ZERO; | |
9226 | } | |
252b5132 RH |
9227 | else |
9228 | break; | |
9229 | } | |
9230 | ||
9231 | if (*s == ' ') | |
9232 | ++s; | |
9233 | if (args[1] != *s) | |
9234 | { | |
9235 | if (c == 'v' || c == 'w') | |
9236 | { | |
9237 | regno = mips16_to_32_reg_map[lastregno]; | |
9238 | s = s_reset; | |
f9419b05 | 9239 | ++args; |
252b5132 RH |
9240 | } |
9241 | } | |
9242 | ||
9243 | switch (c) | |
9244 | { | |
9245 | case 'x': | |
9246 | case 'y': | |
9247 | case 'z': | |
9248 | case 'v': | |
9249 | case 'w': | |
9250 | case 'Z': | |
9251 | regno = mips32_to_16_reg_map[regno]; | |
9252 | break; | |
9253 | ||
9254 | case '0': | |
9255 | if (regno != 0) | |
9256 | regno = ILLEGAL_REG; | |
9257 | break; | |
9258 | ||
9259 | case 'S': | |
9260 | if (regno != SP) | |
9261 | regno = ILLEGAL_REG; | |
9262 | break; | |
9263 | ||
9264 | case 'R': | |
9265 | if (regno != RA) | |
9266 | regno = ILLEGAL_REG; | |
9267 | break; | |
9268 | ||
9269 | case 'X': | |
9270 | case 'Y': | |
9271 | if (regno == AT && ! mips_opts.noat) | |
9272 | as_warn (_("used $at without \".set noat\"")); | |
9273 | break; | |
9274 | ||
9275 | default: | |
9276 | internalError (); | |
9277 | } | |
9278 | ||
9279 | if (regno == ILLEGAL_REG) | |
9280 | break; | |
9281 | ||
9282 | switch (c) | |
9283 | { | |
9284 | case 'x': | |
9285 | case 'v': | |
bf12938e | 9286 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9287 | break; |
9288 | case 'y': | |
9289 | case 'w': | |
bf12938e | 9290 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9291 | break; |
9292 | case 'z': | |
bf12938e | 9293 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9294 | break; |
9295 | case 'Z': | |
bf12938e | 9296 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9297 | case '0': |
9298 | case 'S': | |
9299 | case 'R': | |
9300 | break; | |
9301 | case 'X': | |
bf12938e | 9302 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9303 | break; |
9304 | case 'Y': | |
9305 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9306 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9307 | break; |
9308 | default: | |
9309 | internalError (); | |
9310 | } | |
9311 | ||
9312 | lastregno = regno; | |
9313 | continue; | |
9314 | ||
9315 | case 'P': | |
9316 | if (strncmp (s, "$pc", 3) == 0) | |
9317 | { | |
9318 | s += 3; | |
9319 | continue; | |
9320 | } | |
9321 | break; | |
9322 | ||
252b5132 RH |
9323 | case '5': |
9324 | case 'H': | |
9325 | case 'W': | |
9326 | case 'D': | |
9327 | case 'j': | |
252b5132 RH |
9328 | case 'V': |
9329 | case 'C': | |
9330 | case 'U': | |
9331 | case 'k': | |
9332 | case 'K': | |
d6f16593 MR |
9333 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9334 | if (i > 0) | |
252b5132 | 9335 | { |
d6f16593 | 9336 | if (imm_expr.X_op != O_constant) |
252b5132 | 9337 | { |
b34976b6 | 9338 | mips16_ext = TRUE; |
b34976b6 | 9339 | ip->use_extend = TRUE; |
252b5132 | 9340 | ip->extend = 0; |
252b5132 | 9341 | } |
d6f16593 MR |
9342 | else |
9343 | { | |
9344 | /* We need to relax this instruction. */ | |
9345 | *offset_reloc = *imm_reloc; | |
9346 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9347 | } | |
9348 | s = expr_end; | |
9349 | continue; | |
252b5132 | 9350 | } |
d6f16593 MR |
9351 | *imm_reloc = BFD_RELOC_UNUSED; |
9352 | /* Fall through. */ | |
9353 | case '<': | |
9354 | case '>': | |
9355 | case '[': | |
9356 | case ']': | |
9357 | case '4': | |
9358 | case '8': | |
9359 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9360 | if (imm_expr.X_op == O_register) |
9361 | { | |
9362 | /* What we thought was an expression turned out to | |
9363 | be a register. */ | |
9364 | ||
9365 | if (s[0] == '(' && args[1] == '(') | |
9366 | { | |
9367 | /* It looks like the expression was omitted | |
9368 | before a register indirection, which means | |
9369 | that the expression is implicitly zero. We | |
9370 | still set up imm_expr, so that we handle | |
9371 | explicit extensions correctly. */ | |
9372 | imm_expr.X_op = O_constant; | |
9373 | imm_expr.X_add_number = 0; | |
f6688943 | 9374 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9375 | continue; |
9376 | } | |
9377 | ||
9378 | break; | |
9379 | } | |
9380 | ||
9381 | /* We need to relax this instruction. */ | |
f6688943 | 9382 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9383 | s = expr_end; |
9384 | continue; | |
9385 | ||
9386 | case 'p': | |
9387 | case 'q': | |
9388 | case 'A': | |
9389 | case 'B': | |
9390 | case 'E': | |
9391 | /* We use offset_reloc rather than imm_reloc for the PC | |
9392 | relative operands. This lets macros with both | |
9393 | immediate and address operands work correctly. */ | |
9394 | my_getExpression (&offset_expr, s); | |
9395 | ||
9396 | if (offset_expr.X_op == O_register) | |
9397 | break; | |
9398 | ||
9399 | /* We need to relax this instruction. */ | |
f6688943 | 9400 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9401 | s = expr_end; |
9402 | continue; | |
9403 | ||
9404 | case '6': /* break code */ | |
9405 | my_getExpression (&imm_expr, s); | |
9406 | check_absolute_expr (ip, &imm_expr); | |
9407 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9408 | as_warn (_("Invalid value for `%s' (%lu)"), |
9409 | ip->insn_mo->name, | |
9410 | (unsigned long) imm_expr.X_add_number); | |
9411 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9412 | imm_expr.X_op = O_absent; |
9413 | s = expr_end; | |
9414 | continue; | |
9415 | ||
9416 | case 'a': /* 26 bit address */ | |
9417 | my_getExpression (&offset_expr, s); | |
9418 | s = expr_end; | |
f6688943 | 9419 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9420 | ip->insn_opcode <<= 16; |
9421 | continue; | |
9422 | ||
9423 | case 'l': /* register list for entry macro */ | |
9424 | case 'L': /* register list for exit macro */ | |
9425 | { | |
9426 | int mask; | |
9427 | ||
9428 | if (c == 'l') | |
9429 | mask = 0; | |
9430 | else | |
9431 | mask = 7 << 3; | |
9432 | while (*s != '\0') | |
9433 | { | |
9434 | int freg, reg1, reg2; | |
9435 | ||
9436 | while (*s == ' ' || *s == ',') | |
9437 | ++s; | |
9438 | if (*s != '$') | |
9439 | { | |
9440 | as_bad (_("can't parse register list")); | |
9441 | break; | |
9442 | } | |
9443 | ++s; | |
9444 | if (*s != 'f') | |
9445 | freg = 0; | |
9446 | else | |
9447 | { | |
9448 | freg = 1; | |
9449 | ++s; | |
9450 | } | |
9451 | reg1 = 0; | |
3882b010 | 9452 | while (ISDIGIT (*s)) |
252b5132 RH |
9453 | { |
9454 | reg1 *= 10; | |
9455 | reg1 += *s - '0'; | |
9456 | ++s; | |
9457 | } | |
9458 | if (*s == ' ') | |
9459 | ++s; | |
9460 | if (*s != '-') | |
9461 | reg2 = reg1; | |
9462 | else | |
9463 | { | |
9464 | ++s; | |
9465 | if (*s != '$') | |
9466 | break; | |
9467 | ++s; | |
9468 | if (freg) | |
9469 | { | |
9470 | if (*s == 'f') | |
9471 | ++s; | |
9472 | else | |
9473 | { | |
9474 | as_bad (_("invalid register list")); | |
9475 | break; | |
9476 | } | |
9477 | } | |
9478 | reg2 = 0; | |
3882b010 | 9479 | while (ISDIGIT (*s)) |
252b5132 RH |
9480 | { |
9481 | reg2 *= 10; | |
9482 | reg2 += *s - '0'; | |
9483 | ++s; | |
9484 | } | |
9485 | } | |
9486 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9487 | { | |
9488 | mask &= ~ (7 << 3); | |
9489 | mask |= 5 << 3; | |
9490 | } | |
9491 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9492 | { | |
9493 | mask &= ~ (7 << 3); | |
9494 | mask |= 6 << 3; | |
9495 | } | |
9496 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9497 | mask |= (reg2 - 3) << 3; | |
9498 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9499 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9500 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9501 | mask |= 1; |
9502 | else | |
9503 | { | |
9504 | as_bad (_("invalid register list")); | |
9505 | break; | |
9506 | } | |
9507 | } | |
9508 | /* The mask is filled in in the opcode table for the | |
9509 | benefit of the disassembler. We remove it before | |
9510 | applying the actual mask. */ | |
9511 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9512 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9513 | } | |
9514 | continue; | |
9515 | ||
9516 | case 'e': /* extend code */ | |
9517 | my_getExpression (&imm_expr, s); | |
9518 | check_absolute_expr (ip, &imm_expr); | |
9519 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9520 | { | |
9521 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9522 | ip->insn_mo->name, | |
9523 | (unsigned long) imm_expr.X_add_number); | |
9524 | imm_expr.X_add_number &= 0x7ff; | |
9525 | } | |
9526 | ip->insn_opcode |= imm_expr.X_add_number; | |
9527 | imm_expr.X_op = O_absent; | |
9528 | s = expr_end; | |
9529 | continue; | |
9530 | ||
9531 | default: | |
9532 | internalError (); | |
9533 | } | |
9534 | break; | |
9535 | } | |
9536 | ||
9537 | /* Args don't match. */ | |
9538 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9539 | strcmp (insn->name, insn[1].name) == 0) | |
9540 | { | |
9541 | ++insn; | |
9542 | s = argsstart; | |
9543 | continue; | |
9544 | } | |
9545 | ||
9546 | insn_error = _("illegal operands"); | |
9547 | ||
9548 | return; | |
9549 | } | |
9550 | } | |
9551 | ||
9552 | /* This structure holds information we know about a mips16 immediate | |
9553 | argument type. */ | |
9554 | ||
e972090a NC |
9555 | struct mips16_immed_operand |
9556 | { | |
252b5132 RH |
9557 | /* The type code used in the argument string in the opcode table. */ |
9558 | int type; | |
9559 | /* The number of bits in the short form of the opcode. */ | |
9560 | int nbits; | |
9561 | /* The number of bits in the extended form of the opcode. */ | |
9562 | int extbits; | |
9563 | /* The amount by which the short form is shifted when it is used; | |
9564 | for example, the sw instruction has a shift count of 2. */ | |
9565 | int shift; | |
9566 | /* The amount by which the short form is shifted when it is stored | |
9567 | into the instruction code. */ | |
9568 | int op_shift; | |
9569 | /* Non-zero if the short form is unsigned. */ | |
9570 | int unsp; | |
9571 | /* Non-zero if the extended form is unsigned. */ | |
9572 | int extu; | |
9573 | /* Non-zero if the value is PC relative. */ | |
9574 | int pcrel; | |
9575 | }; | |
9576 | ||
9577 | /* The mips16 immediate operand types. */ | |
9578 | ||
9579 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9580 | { | |
9581 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9582 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9583 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9584 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9585 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9586 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9587 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9588 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9589 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9590 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9591 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9592 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9593 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9594 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9595 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9596 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9597 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9598 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9599 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9600 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9601 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9602 | }; | |
9603 | ||
9604 | #define MIPS16_NUM_IMMED \ | |
9605 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9606 | ||
9607 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9608 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9609 | whether an extended value is needed; if one is needed, it sets | |
9610 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9611 | If SMALL is true, an unextended opcode was explicitly requested. | |
9612 | If EXT is true, an extended opcode was explicitly requested. If | |
9613 | WARN is true, warn if EXT does not match reality. */ | |
9614 | ||
9615 | static void | |
17a2f251 TS |
9616 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9617 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9618 | unsigned long *insn, bfd_boolean *use_extend, | |
9619 | unsigned short *extend) | |
252b5132 RH |
9620 | { |
9621 | register const struct mips16_immed_operand *op; | |
9622 | int mintiny, maxtiny; | |
b34976b6 | 9623 | bfd_boolean needext; |
252b5132 RH |
9624 | |
9625 | op = mips16_immed_operands; | |
9626 | while (op->type != type) | |
9627 | { | |
9628 | ++op; | |
9629 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9630 | } | |
9631 | ||
9632 | if (op->unsp) | |
9633 | { | |
9634 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9635 | { | |
9636 | mintiny = 1; | |
9637 | maxtiny = 1 << op->nbits; | |
9638 | } | |
9639 | else | |
9640 | { | |
9641 | mintiny = 0; | |
9642 | maxtiny = (1 << op->nbits) - 1; | |
9643 | } | |
9644 | } | |
9645 | else | |
9646 | { | |
9647 | mintiny = - (1 << (op->nbits - 1)); | |
9648 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9649 | } | |
9650 | ||
9651 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9652 | if (type == 'p' || type == 'q') | |
9653 | val /= 2; | |
9654 | ||
9655 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9656 | || val < (mintiny << op->shift) | |
9657 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9658 | needext = TRUE; |
252b5132 | 9659 | else |
b34976b6 | 9660 | needext = FALSE; |
252b5132 RH |
9661 | |
9662 | if (warn && ext && ! needext) | |
beae10d5 KH |
9663 | as_warn_where (file, line, |
9664 | _("extended operand requested but not required")); | |
252b5132 RH |
9665 | if (small && needext) |
9666 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9667 | ||
9668 | if (small || (! ext && ! needext)) | |
9669 | { | |
9670 | int insnval; | |
9671 | ||
b34976b6 | 9672 | *use_extend = FALSE; |
252b5132 RH |
9673 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9674 | insnval <<= op->op_shift; | |
9675 | *insn |= insnval; | |
9676 | } | |
9677 | else | |
9678 | { | |
9679 | long minext, maxext; | |
9680 | int extval; | |
9681 | ||
9682 | if (op->extu) | |
9683 | { | |
9684 | minext = 0; | |
9685 | maxext = (1 << op->extbits) - 1; | |
9686 | } | |
9687 | else | |
9688 | { | |
9689 | minext = - (1 << (op->extbits - 1)); | |
9690 | maxext = (1 << (op->extbits - 1)) - 1; | |
9691 | } | |
9692 | if (val < minext || val > maxext) | |
9693 | as_bad_where (file, line, | |
9694 | _("operand value out of range for instruction")); | |
9695 | ||
b34976b6 | 9696 | *use_extend = TRUE; |
252b5132 RH |
9697 | if (op->extbits == 16) |
9698 | { | |
9699 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9700 | val &= 0x1f; | |
9701 | } | |
9702 | else if (op->extbits == 15) | |
9703 | { | |
9704 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9705 | val &= 0xf; | |
9706 | } | |
9707 | else | |
9708 | { | |
9709 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9710 | val = 0; | |
9711 | } | |
9712 | ||
9713 | *extend = (unsigned short) extval; | |
9714 | *insn |= val; | |
9715 | } | |
9716 | } | |
9717 | \f | |
d6f16593 | 9718 | struct percent_op_match |
ad8d3bb3 | 9719 | { |
5e0116d5 RS |
9720 | const char *str; |
9721 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9722 | }; |
9723 | ||
9724 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9725 | { |
5e0116d5 | 9726 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9727 | #ifdef OBJ_ELF |
5e0116d5 RS |
9728 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9729 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9730 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9731 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9732 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9733 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9734 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9735 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9736 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9737 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9738 | {"%half", BFD_RELOC_16}, | |
9739 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9740 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9741 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9742 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9743 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9744 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9745 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9746 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9747 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9748 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9749 | #endif |
5e0116d5 | 9750 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9751 | }; |
9752 | ||
d6f16593 MR |
9753 | static const struct percent_op_match mips16_percent_op[] = |
9754 | { | |
9755 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9756 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9757 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9758 | }; | |
9759 | ||
252b5132 | 9760 | |
5e0116d5 RS |
9761 | /* Return true if *STR points to a relocation operator. When returning true, |
9762 | move *STR over the operator and store its relocation code in *RELOC. | |
9763 | Leave both *STR and *RELOC alone when returning false. */ | |
9764 | ||
9765 | static bfd_boolean | |
17a2f251 | 9766 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9767 | { |
d6f16593 MR |
9768 | const struct percent_op_match *percent_op; |
9769 | size_t limit, i; | |
9770 | ||
9771 | if (mips_opts.mips16) | |
9772 | { | |
9773 | percent_op = mips16_percent_op; | |
9774 | limit = ARRAY_SIZE (mips16_percent_op); | |
9775 | } | |
9776 | else | |
9777 | { | |
9778 | percent_op = mips_percent_op; | |
9779 | limit = ARRAY_SIZE (mips_percent_op); | |
9780 | } | |
76b3015f | 9781 | |
d6f16593 | 9782 | for (i = 0; i < limit; i++) |
5e0116d5 | 9783 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9784 | { |
3f98094e DJ |
9785 | int len = strlen (percent_op[i].str); |
9786 | ||
9787 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9788 | continue; | |
9789 | ||
5e0116d5 RS |
9790 | *str += strlen (percent_op[i].str); |
9791 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9792 | |
5e0116d5 RS |
9793 | /* Check whether the output BFD supports this relocation. |
9794 | If not, issue an error and fall back on something safe. */ | |
9795 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9796 | { |
5e0116d5 RS |
9797 | as_bad ("relocation %s isn't supported by the current ABI", |
9798 | percent_op[i].str); | |
01a3f561 | 9799 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9800 | } |
5e0116d5 | 9801 | return TRUE; |
394f9b3a | 9802 | } |
5e0116d5 | 9803 | return FALSE; |
394f9b3a | 9804 | } |
ad8d3bb3 | 9805 | |
ad8d3bb3 | 9806 | |
5e0116d5 RS |
9807 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9808 | expression in *EP and the relocations in the array starting | |
9809 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9810 | |
01a3f561 | 9811 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9812 | |
5e0116d5 | 9813 | static size_t |
17a2f251 TS |
9814 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9815 | char *str) | |
ad8d3bb3 | 9816 | { |
5e0116d5 RS |
9817 | bfd_reloc_code_real_type reversed_reloc[3]; |
9818 | size_t reloc_index, i; | |
09b8f35a RS |
9819 | int crux_depth, str_depth; |
9820 | char *crux; | |
5e0116d5 RS |
9821 | |
9822 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9823 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9824 | of the main expression and with CRUX_DEPTH containing the number | |
9825 | of open brackets at that point. */ | |
9826 | reloc_index = -1; | |
9827 | str_depth = 0; | |
9828 | do | |
fb1b3232 | 9829 | { |
09b8f35a RS |
9830 | reloc_index++; |
9831 | crux = str; | |
9832 | crux_depth = str_depth; | |
9833 | ||
9834 | /* Skip over whitespace and brackets, keeping count of the number | |
9835 | of brackets. */ | |
9836 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9837 | if (*str++ == '(') | |
9838 | str_depth++; | |
5e0116d5 | 9839 | } |
09b8f35a RS |
9840 | while (*str == '%' |
9841 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9842 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9843 | |
09b8f35a | 9844 | my_getExpression (ep, crux); |
5e0116d5 | 9845 | str = expr_end; |
394f9b3a | 9846 | |
5e0116d5 | 9847 | /* Match every open bracket. */ |
09b8f35a | 9848 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9849 | if (*str++ == ')') |
09b8f35a | 9850 | crux_depth--; |
394f9b3a | 9851 | |
09b8f35a | 9852 | if (crux_depth > 0) |
5e0116d5 | 9853 | as_bad ("unclosed '('"); |
394f9b3a | 9854 | |
5e0116d5 | 9855 | expr_end = str; |
252b5132 | 9856 | |
01a3f561 | 9857 | if (reloc_index != 0) |
64bdfcaf RS |
9858 | { |
9859 | prev_reloc_op_frag = frag_now; | |
9860 | for (i = 0; i < reloc_index; i++) | |
9861 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9862 | } | |
fb1b3232 | 9863 | |
5e0116d5 | 9864 | return reloc_index; |
252b5132 RH |
9865 | } |
9866 | ||
9867 | static void | |
17a2f251 | 9868 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9869 | { |
9870 | char *save_in; | |
98aa84af | 9871 | valueT val; |
252b5132 RH |
9872 | |
9873 | save_in = input_line_pointer; | |
9874 | input_line_pointer = str; | |
9875 | expression (ep); | |
9876 | expr_end = input_line_pointer; | |
9877 | input_line_pointer = save_in; | |
9878 | ||
9879 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9880 | then we bump the value of the symbol by 1 since that is how other | |
9881 | text symbols are handled. We don't bother to handle complex | |
9882 | expressions, just `.' plus or minus a constant. */ | |
9883 | if (mips_opts.mips16 | |
9884 | && ep->X_op == O_symbol | |
9885 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9886 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9887 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9888 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9889 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9890 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9891 | } |
9892 | ||
9893 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9894 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9895 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9896 | returned, or NULL on OK. */ |
9897 | ||
9898 | char * | |
17a2f251 | 9899 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9900 | { |
9901 | int prec; | |
9902 | LITTLENUM_TYPE words[4]; | |
9903 | char *t; | |
9904 | int i; | |
9905 | ||
9906 | switch (type) | |
9907 | { | |
9908 | case 'f': | |
9909 | prec = 2; | |
9910 | break; | |
9911 | ||
9912 | case 'd': | |
9913 | prec = 4; | |
9914 | break; | |
9915 | ||
9916 | default: | |
9917 | *sizeP = 0; | |
9918 | return _("bad call to md_atof"); | |
9919 | } | |
9920 | ||
9921 | t = atof_ieee (input_line_pointer, type, words); | |
9922 | if (t) | |
9923 | input_line_pointer = t; | |
9924 | ||
9925 | *sizeP = prec * 2; | |
9926 | ||
9927 | if (! target_big_endian) | |
9928 | { | |
9929 | for (i = prec - 1; i >= 0; i--) | |
9930 | { | |
17a2f251 | 9931 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9932 | litP += 2; |
9933 | } | |
9934 | } | |
9935 | else | |
9936 | { | |
9937 | for (i = 0; i < prec; i++) | |
9938 | { | |
17a2f251 | 9939 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9940 | litP += 2; |
9941 | } | |
9942 | } | |
bdaaa2e1 | 9943 | |
252b5132 RH |
9944 | return NULL; |
9945 | } | |
9946 | ||
9947 | void | |
17a2f251 | 9948 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9949 | { |
9950 | if (target_big_endian) | |
9951 | number_to_chars_bigendian (buf, val, n); | |
9952 | else | |
9953 | number_to_chars_littleendian (buf, val, n); | |
9954 | } | |
9955 | \f | |
ae948b86 | 9956 | #ifdef OBJ_ELF |
e013f690 TS |
9957 | static int support_64bit_objects(void) |
9958 | { | |
9959 | const char **list, **l; | |
aa3d8fdf | 9960 | int yes; |
e013f690 TS |
9961 | |
9962 | list = bfd_target_list (); | |
9963 | for (l = list; *l != NULL; l++) | |
9964 | #ifdef TE_TMIPS | |
9965 | /* This is traditional mips */ | |
9966 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9967 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9968 | #else | |
9969 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9970 | || strcmp (*l, "elf64-littlemips") == 0) | |
9971 | #endif | |
9972 | break; | |
aa3d8fdf | 9973 | yes = (*l != NULL); |
e013f690 | 9974 | free (list); |
aa3d8fdf | 9975 | return yes; |
e013f690 | 9976 | } |
ae948b86 | 9977 | #endif /* OBJ_ELF */ |
e013f690 | 9978 | |
78849248 | 9979 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 9980 | |
e972090a NC |
9981 | struct option md_longopts[] = |
9982 | { | |
f9b4148d CD |
9983 | /* Options which specify architecture. */ |
9984 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
9985 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
9986 | {"march", required_argument, NULL, OPTION_MARCH}, | |
9987 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
9988 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
9989 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
9990 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
9991 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 9992 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 9993 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 9994 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 9995 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 9996 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 9997 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 9998 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 9999 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10000 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10001 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10002 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10003 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10004 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10005 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10006 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10007 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10008 | |
10009 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10010 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10011 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10012 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10013 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10014 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10015 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10016 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10017 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10018 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10019 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10020 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10021 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10022 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10023 | ||
10024 | /* Old-style architecture options. Don't add more of these. */ | |
10025 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10026 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10027 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10028 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10029 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10030 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10031 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10032 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10033 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10034 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10035 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10036 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10037 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10038 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10039 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10040 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10041 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10042 | ||
10043 | /* Options which enable bug fixes. */ | |
10044 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10045 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10046 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10047 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10048 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10049 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10050 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10051 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10052 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10053 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10054 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10055 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10056 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10057 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10058 | |
10059 | /* Miscellaneous options. */ | |
7d8e00cf | 10060 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10061 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10062 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10063 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10064 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10065 | {"break", no_argument, NULL, OPTION_BREAK}, |
10066 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10067 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10068 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10069 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10070 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10071 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10072 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10073 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10074 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10075 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10076 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10077 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10078 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10079 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10080 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10081 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10082 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10083 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10084 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10085 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10086 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10087 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10088 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10089 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10090 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10091 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10092 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10093 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10094 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10095 | |
10096 | /* ELF-specific options. */ | |
156c2f8b | 10097 | #ifdef OBJ_ELF |
aed1a261 | 10098 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10099 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10100 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10101 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10102 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10103 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10104 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10105 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10106 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10107 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10108 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10109 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10110 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10111 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10112 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10113 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10114 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10115 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10116 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10117 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10118 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10119 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10120 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10121 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10122 | #endif /* OBJ_ELF */ |
f9b4148d | 10123 | |
252b5132 RH |
10124 | {NULL, no_argument, NULL, 0} |
10125 | }; | |
156c2f8b | 10126 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10127 | |
316f5878 RS |
10128 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10129 | NEW_VALUE. Warn if another value was already specified. Note: | |
10130 | we have to defer parsing the -march and -mtune arguments in order | |
10131 | to handle 'from-abi' correctly, since the ABI might be specified | |
10132 | in a later argument. */ | |
10133 | ||
10134 | static void | |
17a2f251 | 10135 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10136 | { |
10137 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10138 | as_warn (_("A different %s was already specified, is now %s"), | |
10139 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10140 | new_value); | |
10141 | ||
10142 | *string_ptr = new_value; | |
10143 | } | |
10144 | ||
252b5132 | 10145 | int |
17a2f251 | 10146 | md_parse_option (int c, char *arg) |
252b5132 RH |
10147 | { |
10148 | switch (c) | |
10149 | { | |
119d663a NC |
10150 | case OPTION_CONSTRUCT_FLOATS: |
10151 | mips_disable_float_construction = 0; | |
10152 | break; | |
bdaaa2e1 | 10153 | |
119d663a NC |
10154 | case OPTION_NO_CONSTRUCT_FLOATS: |
10155 | mips_disable_float_construction = 1; | |
10156 | break; | |
bdaaa2e1 | 10157 | |
252b5132 RH |
10158 | case OPTION_TRAP: |
10159 | mips_trap = 1; | |
10160 | break; | |
10161 | ||
10162 | case OPTION_BREAK: | |
10163 | mips_trap = 0; | |
10164 | break; | |
10165 | ||
10166 | case OPTION_EB: | |
10167 | target_big_endian = 1; | |
10168 | break; | |
10169 | ||
10170 | case OPTION_EL: | |
10171 | target_big_endian = 0; | |
10172 | break; | |
10173 | ||
10174 | case 'O': | |
10175 | if (arg && arg[1] == '0') | |
10176 | mips_optimize = 1; | |
10177 | else | |
10178 | mips_optimize = 2; | |
10179 | break; | |
10180 | ||
10181 | case 'g': | |
10182 | if (arg == NULL) | |
10183 | mips_debug = 2; | |
10184 | else | |
10185 | mips_debug = atoi (arg); | |
10186 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10187 | optimizations which limit full symbolic debugging. We take | |
10188 | that to be equivalent to -O0. */ | |
10189 | if (mips_debug == 2) | |
10190 | mips_optimize = 1; | |
10191 | break; | |
10192 | ||
10193 | case OPTION_MIPS1: | |
316f5878 | 10194 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10195 | break; |
10196 | ||
10197 | case OPTION_MIPS2: | |
316f5878 | 10198 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10199 | break; |
10200 | ||
10201 | case OPTION_MIPS3: | |
316f5878 | 10202 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10203 | break; |
10204 | ||
10205 | case OPTION_MIPS4: | |
316f5878 | 10206 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10207 | break; |
10208 | ||
84ea6cf2 | 10209 | case OPTION_MIPS5: |
316f5878 | 10210 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10211 | break; |
10212 | ||
e7af610e | 10213 | case OPTION_MIPS32: |
316f5878 | 10214 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10215 | break; |
10216 | ||
af7ee8bf CD |
10217 | case OPTION_MIPS32R2: |
10218 | file_mips_isa = ISA_MIPS32R2; | |
10219 | break; | |
10220 | ||
5f74bc13 CD |
10221 | case OPTION_MIPS64R2: |
10222 | file_mips_isa = ISA_MIPS64R2; | |
10223 | break; | |
10224 | ||
84ea6cf2 | 10225 | case OPTION_MIPS64: |
316f5878 | 10226 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10227 | break; |
10228 | ||
ec68c924 | 10229 | case OPTION_MTUNE: |
316f5878 RS |
10230 | mips_set_option_string (&mips_tune_string, arg); |
10231 | break; | |
ec68c924 | 10232 | |
316f5878 RS |
10233 | case OPTION_MARCH: |
10234 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10235 | break; |
10236 | ||
10237 | case OPTION_M4650: | |
316f5878 RS |
10238 | mips_set_option_string (&mips_arch_string, "4650"); |
10239 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10240 | break; |
10241 | ||
10242 | case OPTION_NO_M4650: | |
10243 | break; | |
10244 | ||
10245 | case OPTION_M4010: | |
316f5878 RS |
10246 | mips_set_option_string (&mips_arch_string, "4010"); |
10247 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10248 | break; |
10249 | ||
10250 | case OPTION_NO_M4010: | |
10251 | break; | |
10252 | ||
10253 | case OPTION_M4100: | |
316f5878 RS |
10254 | mips_set_option_string (&mips_arch_string, "4100"); |
10255 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10256 | break; |
10257 | ||
10258 | case OPTION_NO_M4100: | |
10259 | break; | |
10260 | ||
252b5132 | 10261 | case OPTION_M3900: |
316f5878 RS |
10262 | mips_set_option_string (&mips_arch_string, "3900"); |
10263 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10264 | break; |
bdaaa2e1 | 10265 | |
252b5132 RH |
10266 | case OPTION_NO_M3900: |
10267 | break; | |
10268 | ||
deec1734 CD |
10269 | case OPTION_MDMX: |
10270 | mips_opts.ase_mdmx = 1; | |
10271 | break; | |
10272 | ||
10273 | case OPTION_NO_MDMX: | |
10274 | mips_opts.ase_mdmx = 0; | |
10275 | break; | |
10276 | ||
252b5132 RH |
10277 | case OPTION_MIPS16: |
10278 | mips_opts.mips16 = 1; | |
7d10b47d | 10279 | mips_no_prev_insn (); |
252b5132 RH |
10280 | break; |
10281 | ||
10282 | case OPTION_NO_MIPS16: | |
10283 | mips_opts.mips16 = 0; | |
7d10b47d | 10284 | mips_no_prev_insn (); |
252b5132 RH |
10285 | break; |
10286 | ||
1f25f5d3 CD |
10287 | case OPTION_MIPS3D: |
10288 | mips_opts.ase_mips3d = 1; | |
10289 | break; | |
10290 | ||
10291 | case OPTION_NO_MIPS3D: | |
10292 | mips_opts.ase_mips3d = 0; | |
10293 | break; | |
10294 | ||
d766e8ec RS |
10295 | case OPTION_FIX_VR4120: |
10296 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10297 | break; |
10298 | ||
d766e8ec RS |
10299 | case OPTION_NO_FIX_VR4120: |
10300 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10301 | break; |
10302 | ||
7d8e00cf RS |
10303 | case OPTION_FIX_VR4130: |
10304 | mips_fix_vr4130 = 1; | |
10305 | break; | |
10306 | ||
10307 | case OPTION_NO_FIX_VR4130: | |
10308 | mips_fix_vr4130 = 0; | |
10309 | break; | |
10310 | ||
4a6a3df4 AO |
10311 | case OPTION_RELAX_BRANCH: |
10312 | mips_relax_branch = 1; | |
10313 | break; | |
10314 | ||
10315 | case OPTION_NO_RELAX_BRANCH: | |
10316 | mips_relax_branch = 0; | |
10317 | break; | |
10318 | ||
aa6975fb ILT |
10319 | case OPTION_MSHARED: |
10320 | mips_in_shared = TRUE; | |
10321 | break; | |
10322 | ||
10323 | case OPTION_MNO_SHARED: | |
10324 | mips_in_shared = FALSE; | |
10325 | break; | |
10326 | ||
aed1a261 RS |
10327 | case OPTION_MSYM32: |
10328 | mips_opts.sym32 = TRUE; | |
10329 | break; | |
10330 | ||
10331 | case OPTION_MNO_SYM32: | |
10332 | mips_opts.sym32 = FALSE; | |
10333 | break; | |
10334 | ||
0f074f60 | 10335 | #ifdef OBJ_ELF |
252b5132 RH |
10336 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10337 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10338 | intended to be compatible with Irix 5. */ | |
10339 | case OPTION_CALL_SHARED: | |
10340 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10341 | { | |
10342 | as_bad (_("-call_shared is supported only for ELF format")); | |
10343 | return 0; | |
10344 | } | |
10345 | mips_pic = SVR4_PIC; | |
143d77c5 | 10346 | mips_abicalls = TRUE; |
252b5132 RH |
10347 | if (g_switch_seen && g_switch_value != 0) |
10348 | { | |
10349 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10350 | return 0; | |
10351 | } | |
10352 | g_switch_value = 0; | |
10353 | break; | |
10354 | ||
10355 | case OPTION_NON_SHARED: | |
10356 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10357 | { | |
10358 | as_bad (_("-non_shared is supported only for ELF format")); | |
10359 | return 0; | |
10360 | } | |
10361 | mips_pic = NO_PIC; | |
143d77c5 | 10362 | mips_abicalls = FALSE; |
252b5132 RH |
10363 | break; |
10364 | ||
10365 | /* The -xgot option tells the assembler to use 32 offsets when | |
10366 | accessing the got in SVR4_PIC mode. It is for Irix | |
10367 | compatibility. */ | |
10368 | case OPTION_XGOT: | |
10369 | mips_big_got = 1; | |
10370 | break; | |
0f074f60 | 10371 | #endif /* OBJ_ELF */ |
252b5132 RH |
10372 | |
10373 | case 'G': | |
6caf9ef4 TS |
10374 | g_switch_value = atoi (arg); |
10375 | g_switch_seen = 1; | |
10376 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10377 | { |
3e722fb5 | 10378 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10379 | return 0; |
10380 | } | |
252b5132 RH |
10381 | break; |
10382 | ||
0f074f60 | 10383 | #ifdef OBJ_ELF |
34ba82a8 TS |
10384 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10385 | and -mabi=64. */ | |
252b5132 | 10386 | case OPTION_32: |
34ba82a8 TS |
10387 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10388 | { | |
10389 | as_bad (_("-32 is supported for ELF format only")); | |
10390 | return 0; | |
10391 | } | |
316f5878 | 10392 | mips_abi = O32_ABI; |
252b5132 RH |
10393 | break; |
10394 | ||
e013f690 | 10395 | case OPTION_N32: |
34ba82a8 TS |
10396 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10397 | { | |
10398 | as_bad (_("-n32 is supported for ELF format only")); | |
10399 | return 0; | |
10400 | } | |
316f5878 | 10401 | mips_abi = N32_ABI; |
e013f690 | 10402 | break; |
252b5132 | 10403 | |
e013f690 | 10404 | case OPTION_64: |
34ba82a8 TS |
10405 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10406 | { | |
10407 | as_bad (_("-64 is supported for ELF format only")); | |
10408 | return 0; | |
10409 | } | |
316f5878 | 10410 | mips_abi = N64_ABI; |
e013f690 TS |
10411 | if (! support_64bit_objects()) |
10412 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10413 | break; |
ae948b86 | 10414 | #endif /* OBJ_ELF */ |
252b5132 | 10415 | |
c97ef257 | 10416 | case OPTION_GP32: |
a325df1d | 10417 | file_mips_gp32 = 1; |
c97ef257 AH |
10418 | break; |
10419 | ||
10420 | case OPTION_GP64: | |
a325df1d | 10421 | file_mips_gp32 = 0; |
c97ef257 | 10422 | break; |
252b5132 | 10423 | |
ca4e0257 | 10424 | case OPTION_FP32: |
a325df1d | 10425 | file_mips_fp32 = 1; |
316f5878 RS |
10426 | break; |
10427 | ||
10428 | case OPTION_FP64: | |
10429 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10430 | break; |
10431 | ||
ae948b86 | 10432 | #ifdef OBJ_ELF |
252b5132 | 10433 | case OPTION_MABI: |
34ba82a8 TS |
10434 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10435 | { | |
10436 | as_bad (_("-mabi is supported for ELF format only")); | |
10437 | return 0; | |
10438 | } | |
e013f690 | 10439 | if (strcmp (arg, "32") == 0) |
316f5878 | 10440 | mips_abi = O32_ABI; |
e013f690 | 10441 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10442 | mips_abi = O64_ABI; |
e013f690 | 10443 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10444 | mips_abi = N32_ABI; |
e013f690 TS |
10445 | else if (strcmp (arg, "64") == 0) |
10446 | { | |
316f5878 | 10447 | mips_abi = N64_ABI; |
e013f690 TS |
10448 | if (! support_64bit_objects()) |
10449 | as_fatal (_("No compiled in support for 64 bit object file " | |
10450 | "format")); | |
10451 | } | |
10452 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10453 | mips_abi = EABI_ABI; |
e013f690 | 10454 | else |
da0e507f TS |
10455 | { |
10456 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10457 | return 0; | |
10458 | } | |
252b5132 | 10459 | break; |
e013f690 | 10460 | #endif /* OBJ_ELF */ |
252b5132 | 10461 | |
6b76fefe | 10462 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10463 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10464 | break; |
10465 | ||
9ee72ff1 | 10466 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10467 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10468 | break; |
10469 | ||
ecb4347a DJ |
10470 | #ifdef OBJ_ELF |
10471 | case OPTION_MDEBUG: | |
b34976b6 | 10472 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10473 | break; |
10474 | ||
10475 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10476 | mips_flag_mdebug = FALSE; |
ecb4347a | 10477 | break; |
dcd410fe RO |
10478 | |
10479 | case OPTION_PDR: | |
10480 | mips_flag_pdr = TRUE; | |
10481 | break; | |
10482 | ||
10483 | case OPTION_NO_PDR: | |
10484 | mips_flag_pdr = FALSE; | |
10485 | break; | |
ecb4347a DJ |
10486 | #endif /* OBJ_ELF */ |
10487 | ||
252b5132 RH |
10488 | default: |
10489 | return 0; | |
10490 | } | |
10491 | ||
10492 | return 1; | |
10493 | } | |
316f5878 RS |
10494 | \f |
10495 | /* Set up globals to generate code for the ISA or processor | |
10496 | described by INFO. */ | |
252b5132 | 10497 | |
252b5132 | 10498 | static void |
17a2f251 | 10499 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10500 | { |
316f5878 | 10501 | if (info != 0) |
252b5132 | 10502 | { |
fef14a42 TS |
10503 | file_mips_arch = info->cpu; |
10504 | mips_opts.arch = info->cpu; | |
316f5878 | 10505 | mips_opts.isa = info->isa; |
252b5132 | 10506 | } |
252b5132 RH |
10507 | } |
10508 | ||
252b5132 | 10509 | |
316f5878 | 10510 | /* Likewise for tuning. */ |
252b5132 | 10511 | |
316f5878 | 10512 | static void |
17a2f251 | 10513 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10514 | { |
10515 | if (info != 0) | |
fef14a42 | 10516 | mips_tune = info->cpu; |
316f5878 | 10517 | } |
80cc45a5 | 10518 | |
34ba82a8 | 10519 | |
252b5132 | 10520 | void |
17a2f251 | 10521 | mips_after_parse_args (void) |
e9670677 | 10522 | { |
fef14a42 TS |
10523 | const struct mips_cpu_info *arch_info = 0; |
10524 | const struct mips_cpu_info *tune_info = 0; | |
10525 | ||
e9670677 | 10526 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10527 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10528 | { |
6caf9ef4 | 10529 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10530 | as_bad (_("-G not supported in this configuration.")); |
10531 | g_switch_value = 0; | |
10532 | } | |
10533 | ||
cac012d6 AO |
10534 | if (mips_abi == NO_ABI) |
10535 | mips_abi = MIPS_DEFAULT_ABI; | |
10536 | ||
22923709 RS |
10537 | /* The following code determines the architecture and register size. |
10538 | Similar code was added to GCC 3.3 (see override_options() in | |
10539 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10540 | as much as possible. */ | |
e9670677 | 10541 | |
316f5878 | 10542 | if (mips_arch_string != 0) |
fef14a42 | 10543 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10544 | |
316f5878 | 10545 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10546 | { |
316f5878 | 10547 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10548 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10549 | the -march selection (if any). */ |
fef14a42 | 10550 | if (arch_info != 0) |
e9670677 | 10551 | { |
316f5878 RS |
10552 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10553 | There's no harm in specifying both as long as the ISA levels | |
10554 | are the same. */ | |
fef14a42 | 10555 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10556 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10557 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10558 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10559 | } |
316f5878 | 10560 | else |
fef14a42 | 10561 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10562 | } |
10563 | ||
fef14a42 TS |
10564 | if (arch_info == 0) |
10565 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10566 | |
fef14a42 | 10567 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10568 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10569 | arch_info->name); |
10570 | ||
10571 | mips_set_architecture (arch_info); | |
10572 | ||
10573 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10574 | if (mips_tune_string != 0) | |
10575 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10576 | |
fef14a42 TS |
10577 | if (tune_info == 0) |
10578 | mips_set_tune (arch_info); | |
10579 | else | |
10580 | mips_set_tune (tune_info); | |
e9670677 | 10581 | |
316f5878 | 10582 | if (file_mips_gp32 >= 0) |
e9670677 | 10583 | { |
316f5878 RS |
10584 | /* The user specified the size of the integer registers. Make sure |
10585 | it agrees with the ABI and ISA. */ | |
10586 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10587 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10588 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10589 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10590 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10591 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10592 | } |
10593 | else | |
10594 | { | |
316f5878 RS |
10595 | /* Infer the integer register size from the ABI and processor. |
10596 | Restrict ourselves to 32-bit registers if that's all the | |
10597 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10598 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10599 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10600 | } |
10601 | ||
316f5878 RS |
10602 | /* ??? GAS treats single-float processors as though they had 64-bit |
10603 | float registers (although it complains when double-precision | |
10604 | instructions are used). As things stand, saying they have 32-bit | |
10605 | registers would lead to spurious "register must be even" messages. | |
10606 | So here we assume float registers are always the same size as | |
10607 | integer ones, unless the user says otherwise. */ | |
10608 | if (file_mips_fp32 < 0) | |
10609 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10610 | |
316f5878 | 10611 | /* End of GCC-shared inference code. */ |
e9670677 | 10612 | |
17a2f251 TS |
10613 | /* This flag is set when we have a 64-bit capable CPU but use only |
10614 | 32-bit wide registers. Note that EABI does not use it. */ | |
10615 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10616 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10617 | || mips_abi == O32_ABI)) | |
316f5878 | 10618 | mips_32bitmode = 1; |
e9670677 MR |
10619 | |
10620 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10621 | as_bad (_("trap exception not supported at ISA 1")); | |
10622 | ||
e9670677 MR |
10623 | /* If the selected architecture includes support for ASEs, enable |
10624 | generation of code for them. */ | |
a4672219 | 10625 | if (mips_opts.mips16 == -1) |
fef14a42 | 10626 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10627 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10628 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10629 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10630 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10631 | |
e9670677 | 10632 | file_mips_isa = mips_opts.isa; |
a4672219 | 10633 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10634 | file_ase_mips3d = mips_opts.ase_mips3d; |
10635 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10636 | mips_opts.gp32 = file_mips_gp32; | |
10637 | mips_opts.fp32 = file_mips_fp32; | |
10638 | ||
ecb4347a DJ |
10639 | if (mips_flag_mdebug < 0) |
10640 | { | |
10641 | #ifdef OBJ_MAYBE_ECOFF | |
10642 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10643 | mips_flag_mdebug = 1; | |
10644 | else | |
10645 | #endif /* OBJ_MAYBE_ECOFF */ | |
10646 | mips_flag_mdebug = 0; | |
10647 | } | |
e9670677 MR |
10648 | } |
10649 | \f | |
10650 | void | |
17a2f251 | 10651 | mips_init_after_args (void) |
252b5132 RH |
10652 | { |
10653 | /* initialize opcodes */ | |
10654 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10655 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10656 | } |
10657 | ||
10658 | long | |
17a2f251 | 10659 | md_pcrel_from (fixS *fixP) |
252b5132 | 10660 | { |
a7ebbfdf TS |
10661 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10662 | switch (fixP->fx_r_type) | |
10663 | { | |
10664 | case BFD_RELOC_16_PCREL_S2: | |
10665 | case BFD_RELOC_MIPS_JMP: | |
10666 | /* Return the address of the delay slot. */ | |
10667 | return addr + 4; | |
10668 | default: | |
10669 | return addr; | |
10670 | } | |
252b5132 RH |
10671 | } |
10672 | ||
252b5132 RH |
10673 | /* This is called before the symbol table is processed. In order to |
10674 | work with gcc when using mips-tfile, we must keep all local labels. | |
10675 | However, in other cases, we want to discard them. If we were | |
10676 | called with -g, but we didn't see any debugging information, it may | |
10677 | mean that gcc is smuggling debugging information through to | |
10678 | mips-tfile, in which case we must generate all local labels. */ | |
10679 | ||
10680 | void | |
17a2f251 | 10681 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10682 | { |
10683 | #ifndef NO_ECOFF_DEBUGGING | |
10684 | if (ECOFF_DEBUGGING | |
10685 | && mips_debug != 0 | |
10686 | && ! ecoff_debugging_seen) | |
10687 | flag_keep_locals = 1; | |
10688 | #endif | |
10689 | } | |
10690 | ||
3b91255e RS |
10691 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10692 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10693 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10694 | relocation operators. | |
10695 | ||
10696 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10697 | expression if: | |
10698 | ||
10699 | (a) it refers to the same symbol; and | |
10700 | (b) the offset applied in the %lo() expression is no lower than | |
10701 | the offset applied in the %got() or %hi(). | |
10702 | ||
10703 | (b) allows us to cope with code like: | |
10704 | ||
10705 | lui $4,%hi(foo) | |
10706 | lh $4,%lo(foo+2)($4) | |
10707 | ||
10708 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10709 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10710 | the high 16 bits. | |
10711 | ||
10712 | When several %lo()s match a particular %got() or %hi(), we use the | |
10713 | following rules to distinguish them: | |
10714 | ||
10715 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10716 | higher offsets. | |
10717 | ||
10718 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10719 | that already have a matching %got() or %hi(). | |
10720 | ||
10721 | (3) later %lo()s are better than earlier %lo()s. | |
10722 | ||
10723 | These rules are applied in order. | |
10724 | ||
10725 | (1) means, among other things, that %lo()s with identical offsets are | |
10726 | chosen if they exist. | |
10727 | ||
10728 | (2) means that we won't associate several high-part relocations with | |
10729 | the same low-part relocation unless there's no alternative. Having | |
10730 | several high parts for the same low part is a GNU extension; this rule | |
10731 | allows careful users to avoid it. | |
10732 | ||
10733 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10734 | with the last high-part relocation being at the front of the list. | |
10735 | It therefore makes sense to choose the last matching low-part | |
10736 | relocation, all other things being equal. It's also easier | |
10737 | to code that way. */ | |
252b5132 RH |
10738 | |
10739 | void | |
17a2f251 | 10740 | mips_frob_file (void) |
252b5132 RH |
10741 | { |
10742 | struct mips_hi_fixup *l; | |
10743 | ||
10744 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10745 | { | |
10746 | segment_info_type *seginfo; | |
3b91255e RS |
10747 | bfd_boolean matched_lo_p; |
10748 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10749 | |
5919d012 | 10750 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10751 | |
5919d012 RS |
10752 | /* If a GOT16 relocation turns out to be against a global symbol, |
10753 | there isn't supposed to be a matching LO. */ | |
10754 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10755 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10756 | continue; | |
10757 | ||
10758 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10759 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10760 | continue; |
10761 | ||
252b5132 | 10762 | seginfo = seg_info (l->seg); |
252b5132 | 10763 | |
3b91255e RS |
10764 | /* Set HI_POS to the position of this relocation in the chain. |
10765 | Set LO_POS to the position of the chosen low-part relocation. | |
10766 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10767 | relocation that matches an immediately-preceding high-part | |
10768 | relocation. */ | |
10769 | hi_pos = NULL; | |
10770 | lo_pos = NULL; | |
10771 | matched_lo_p = FALSE; | |
10772 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10773 | { | |
10774 | if (*pos == l->fixp) | |
10775 | hi_pos = pos; | |
10776 | ||
704803a9 MR |
10777 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
10778 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
10779 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
10780 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10781 | && (lo_pos == NULL | |
10782 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10783 | || (!matched_lo_p | |
10784 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10785 | lo_pos = pos; | |
10786 | ||
10787 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10788 | && fixup_has_matching_lo_p (*pos)); | |
10789 | } | |
10790 | ||
10791 | /* If we found a match, remove the high-part relocation from its | |
10792 | current position and insert it before the low-part relocation. | |
10793 | Make the offsets match so that fixup_has_matching_lo_p() | |
10794 | will return true. | |
10795 | ||
10796 | We don't warn about unmatched high-part relocations since some | |
10797 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10798 | instructions. */ | |
10799 | if (lo_pos != NULL) | |
10800 | { | |
10801 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10802 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10803 | { |
3b91255e RS |
10804 | *hi_pos = l->fixp->fx_next; |
10805 | l->fixp->fx_next = *lo_pos; | |
10806 | *lo_pos = l->fixp; | |
252b5132 | 10807 | } |
252b5132 RH |
10808 | } |
10809 | } | |
10810 | } | |
10811 | ||
3e722fb5 | 10812 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10813 | We have to prevent gas from dropping them. */ |
252b5132 | 10814 | |
252b5132 | 10815 | int |
17a2f251 | 10816 | mips_force_relocation (fixS *fixp) |
252b5132 | 10817 | { |
ae6063d4 | 10818 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10819 | return 1; |
10820 | ||
f6688943 TS |
10821 | if (HAVE_NEWABI |
10822 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10823 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10824 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10825 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10826 | return 1; | |
10827 | ||
3e722fb5 | 10828 | return 0; |
252b5132 RH |
10829 | } |
10830 | ||
45f8dfe8 AO |
10831 | /* This hook is called before a fix is simplified. We don't really |
10832 | decide whether to skip a fix here. Rather, we turn global symbols | |
10833 | used as branch targets into local symbols, such that they undergo | |
10834 | simplification. We can only do this if the symbol is defined and | |
10835 | it is in the same section as the branch. If this doesn't hold, we | |
10836 | emit a better error message than just saying the relocation is not | |
10837 | valid for the selected object format. | |
10838 | ||
10839 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10840 | segment in which the fix up occurs. The return value should be | |
10841 | non-zero to indicate the fix-up is valid for further | |
10842 | simplifications. */ | |
10843 | ||
10844 | int | |
17a2f251 | 10845 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10846 | { |
10847 | /* There's a lot of discussion on whether it should be possible to | |
10848 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10849 | seems to be that it can, but gas/bfd are very broken in creating | |
10850 | RELA relocations for this, so for now we only accept branches to | |
10851 | symbols in the same section. Anything else is of dubious value, | |
10852 | since there's no guarantee that at link time the symbol would be | |
10853 | in range. Even for branches to local symbols this is arguably | |
10854 | wrong, since it we assume the symbol is not going to be | |
10855 | overridden, which should be possible per ELF library semantics, | |
10856 | but then, there isn't a dynamic relocation that could be used to | |
10857 | this effect, and the target would likely be out of range as well. | |
10858 | ||
10859 | Unfortunately, it seems that there is too much code out there | |
10860 | that relies on branches to symbols that are global to be resolved | |
10861 | as if they were local, like the IRIX tools do, so we do it as | |
10862 | well, but with a warning so that people are reminded to fix their | |
10863 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10864 | targets, this entire block should go away (and probably the | |
10865 | whole function). */ | |
10866 | ||
10867 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10868 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10869 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10870 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10871 | && fixP->fx_addsy) | |
10872 | { | |
10873 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10874 | { | |
10875 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10876 | _("Cannot branch to undefined symbol.")); | |
10877 | /* Avoid any further errors about this fixup. */ | |
10878 | fixP->fx_done = 1; | |
10879 | } | |
10880 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10881 | { | |
10882 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10883 | _("Cannot branch to symbol in another section.")); | |
10884 | fixP->fx_done = 1; | |
10885 | } | |
10886 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10887 | { | |
10888 | symbolS *sym = fixP->fx_addsy; | |
10889 | ||
115695a8 CD |
10890 | if (mips_pic == SVR4_PIC) |
10891 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10892 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10893 | |
10894 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10895 | S_GET_SEGMENT (sym), | |
10896 | S_GET_VALUE (sym), | |
10897 | symbol_get_frag (sym)); | |
10898 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10899 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10900 | assert (symbol_resolved_p (sym)); | |
10901 | symbol_mark_resolved (fixP->fx_addsy); | |
10902 | } | |
10903 | } | |
10904 | ||
10905 | return 1; | |
10906 | } | |
10907 | ||
252b5132 RH |
10908 | /* Apply a fixup to the object file. */ |
10909 | ||
94f592af | 10910 | void |
17a2f251 | 10911 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10912 | { |
874e8986 | 10913 | bfd_byte *buf; |
98aa84af | 10914 | long insn; |
a7ebbfdf | 10915 | reloc_howto_type *howto; |
252b5132 | 10916 | |
a7ebbfdf TS |
10917 | /* We ignore generic BFD relocations we don't know about. */ |
10918 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10919 | if (! howto) | |
10920 | return; | |
65551fa4 | 10921 | |
252b5132 RH |
10922 | assert (fixP->fx_size == 4 |
10923 | || fixP->fx_r_type == BFD_RELOC_16 | |
10924 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10925 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10926 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10927 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10928 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10929 | |
a7ebbfdf | 10930 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10931 | |
3e722fb5 | 10932 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10933 | |
10934 | /* Don't treat parts of a composite relocation as done. There are two | |
10935 | reasons for this: | |
10936 | ||
10937 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
10938 | should nevertheless be emitted if the first part is. | |
10939 | ||
10940 | (2) In normal usage, composite relocations are never assembly-time | |
10941 | constants. The easiest way of dealing with the pathological | |
10942 | exceptions is to generate a relocation against STN_UNDEF and | |
10943 | leave everything up to the linker. */ | |
10944 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
10945 | fixP->fx_done = 1; |
10946 | ||
10947 | switch (fixP->fx_r_type) | |
10948 | { | |
3f98094e DJ |
10949 | case BFD_RELOC_MIPS_TLS_GD: |
10950 | case BFD_RELOC_MIPS_TLS_LDM: | |
10951 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
10952 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
10953 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
10954 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
10955 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
10956 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10957 | /* fall through */ | |
10958 | ||
252b5132 | 10959 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
10960 | case BFD_RELOC_MIPS_SHIFT5: |
10961 | case BFD_RELOC_MIPS_SHIFT6: | |
10962 | case BFD_RELOC_MIPS_GOT_DISP: | |
10963 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10964 | case BFD_RELOC_MIPS_GOT_OFST: | |
10965 | case BFD_RELOC_MIPS_SUB: | |
10966 | case BFD_RELOC_MIPS_INSERT_A: | |
10967 | case BFD_RELOC_MIPS_INSERT_B: | |
10968 | case BFD_RELOC_MIPS_DELETE: | |
10969 | case BFD_RELOC_MIPS_HIGHEST: | |
10970 | case BFD_RELOC_MIPS_HIGHER: | |
10971 | case BFD_RELOC_MIPS_SCN_DISP: | |
10972 | case BFD_RELOC_MIPS_REL16: | |
10973 | case BFD_RELOC_MIPS_RELGOT: | |
10974 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10975 | case BFD_RELOC_HI16: |
10976 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10977 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10978 | case BFD_RELOC_MIPS_LITERAL: |
10979 | case BFD_RELOC_MIPS_CALL16: | |
10980 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10981 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10982 | case BFD_RELOC_MIPS_GOT_HI16: |
10983 | case BFD_RELOC_MIPS_GOT_LO16: | |
10984 | case BFD_RELOC_MIPS_CALL_HI16: | |
10985 | case BFD_RELOC_MIPS_CALL_LO16: | |
10986 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
10987 | case BFD_RELOC_MIPS16_HI16: |
10988 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 10989 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10990 | /* Nothing needed to do. The value comes from the reloc entry */ |
10991 | break; | |
10992 | ||
10993 | case BFD_RELOC_MIPS16_JMP: | |
10994 | /* We currently always generate a reloc against a symbol, which | |
10995 | means that we don't want an addend even if the symbol is | |
10996 | defined. */ | |
a7ebbfdf | 10997 | *valP = 0; |
252b5132 RH |
10998 | break; |
10999 | ||
252b5132 RH |
11000 | case BFD_RELOC_64: |
11001 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11002 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11003 | if (fixP->fx_done) |
252b5132 RH |
11004 | { |
11005 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11006 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11007 | else |
11008 | { | |
a7ebbfdf | 11009 | valueT hiv; |
252b5132 | 11010 | |
a7ebbfdf | 11011 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11012 | hiv = 0xffffffff; |
11013 | else | |
11014 | hiv = 0; | |
b215186b | 11015 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11016 | *valP, 4); |
b215186b | 11017 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11018 | hiv, 4); |
252b5132 RH |
11019 | } |
11020 | } | |
11021 | break; | |
11022 | ||
056350c6 | 11023 | case BFD_RELOC_RVA: |
252b5132 RH |
11024 | case BFD_RELOC_32: |
11025 | /* If we are deleting this reloc entry, we must fill in the | |
11026 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11027 | resolved when it appears but is later defined. */ |
11028 | if (fixP->fx_done) | |
2132e3a3 | 11029 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11030 | break; |
11031 | ||
11032 | case BFD_RELOC_16: | |
11033 | /* If we are deleting this reloc entry, we must fill in the | |
11034 | value now. */ | |
252b5132 | 11035 | if (fixP->fx_done) |
2132e3a3 | 11036 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11037 | break; |
11038 | ||
11039 | case BFD_RELOC_LO16: | |
d6f16593 | 11040 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11041 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11042 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11043 | /* When handling an embedded PIC switch statement, we can wind |
11044 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11045 | if (fixP->fx_done) | |
11046 | { | |
a7ebbfdf | 11047 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11048 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11049 | _("relocation overflow")); | |
252b5132 RH |
11050 | if (target_big_endian) |
11051 | buf += 2; | |
2132e3a3 | 11052 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11053 | } |
11054 | break; | |
11055 | ||
11056 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11057 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11058 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11059 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11060 | |
252b5132 RH |
11061 | /* |
11062 | * We need to save the bits in the instruction since fixup_segment() | |
11063 | * might be deleting the relocation entry (i.e., a branch within | |
11064 | * the current segment). | |
11065 | */ | |
a7ebbfdf | 11066 | if (! fixP->fx_done) |
bb2d6cd7 | 11067 | break; |
252b5132 RH |
11068 | |
11069 | /* update old instruction data */ | |
252b5132 RH |
11070 | if (target_big_endian) |
11071 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11072 | else | |
11073 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11074 | ||
a7ebbfdf TS |
11075 | if (*valP + 0x20000 <= 0x3ffff) |
11076 | { | |
11077 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11078 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11079 | } |
11080 | else if (mips_pic == NO_PIC | |
11081 | && fixP->fx_done | |
11082 | && fixP->fx_frag->fr_address >= text_section->vma | |
11083 | && (fixP->fx_frag->fr_address | |
587aac4e | 11084 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11085 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11086 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11087 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11088 | { |
11089 | /* The branch offset is too large. If this is an | |
11090 | unconditional branch, and we are not generating PIC code, | |
11091 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11092 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11093 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11094 | else |
a7ebbfdf TS |
11095 | insn = 0x08000000; /* j */ |
11096 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11097 | fixP->fx_done = 0; | |
11098 | fixP->fx_addsy = section_symbol (text_section); | |
11099 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11100 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11101 | } |
11102 | else | |
11103 | { | |
11104 | /* If we got here, we have branch-relaxation disabled, | |
11105 | and there's nothing we can do to fix this instruction | |
11106 | without turning it into a longer sequence. */ | |
11107 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11108 | _("Branch out of range")); | |
252b5132 | 11109 | } |
252b5132 RH |
11110 | break; |
11111 | ||
11112 | case BFD_RELOC_VTABLE_INHERIT: | |
11113 | fixP->fx_done = 0; | |
11114 | if (fixP->fx_addsy | |
11115 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11116 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11117 | S_SET_WEAK (fixP->fx_addsy); | |
11118 | break; | |
11119 | ||
11120 | case BFD_RELOC_VTABLE_ENTRY: | |
11121 | fixP->fx_done = 0; | |
11122 | break; | |
11123 | ||
11124 | default: | |
11125 | internalError (); | |
11126 | } | |
a7ebbfdf TS |
11127 | |
11128 | /* Remember value for tc_gen_reloc. */ | |
11129 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11130 | } |
11131 | ||
252b5132 | 11132 | static symbolS * |
17a2f251 | 11133 | get_symbol (void) |
252b5132 RH |
11134 | { |
11135 | int c; | |
11136 | char *name; | |
11137 | symbolS *p; | |
11138 | ||
11139 | name = input_line_pointer; | |
11140 | c = get_symbol_end (); | |
11141 | p = (symbolS *) symbol_find_or_make (name); | |
11142 | *input_line_pointer = c; | |
11143 | return p; | |
11144 | } | |
11145 | ||
11146 | /* Align the current frag to a given power of two. The MIPS assembler | |
11147 | also automatically adjusts any preceding label. */ | |
11148 | ||
11149 | static void | |
17a2f251 | 11150 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11151 | { |
7d10b47d | 11152 | mips_emit_delays (); |
252b5132 RH |
11153 | frag_align (to, fill, 0); |
11154 | record_alignment (now_seg, to); | |
11155 | if (label != NULL) | |
11156 | { | |
11157 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11158 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11159 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11160 | } | |
11161 | } | |
11162 | ||
11163 | /* Align to a given power of two. .align 0 turns off the automatic | |
11164 | alignment used by the data creating pseudo-ops. */ | |
11165 | ||
11166 | static void | |
17a2f251 | 11167 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11168 | { |
11169 | register int temp; | |
11170 | register long temp_fill; | |
11171 | long max_alignment = 15; | |
11172 | ||
11173 | /* | |
11174 | ||
67c1ffbe | 11175 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11176 | to the aligned address. |
11177 | o It's not documented but auto alignment is reinstated by | |
11178 | a .align pseudo instruction. | |
11179 | o Note also that after auto alignment is turned off the mips assembler | |
11180 | issues an error on attempt to assemble an improperly aligned data item. | |
11181 | We don't. | |
11182 | ||
11183 | */ | |
11184 | ||
11185 | temp = get_absolute_expression (); | |
11186 | if (temp > max_alignment) | |
11187 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11188 | else if (temp < 0) | |
11189 | { | |
11190 | as_warn (_("Alignment negative: 0 assumed.")); | |
11191 | temp = 0; | |
11192 | } | |
11193 | if (*input_line_pointer == ',') | |
11194 | { | |
f9419b05 | 11195 | ++input_line_pointer; |
252b5132 RH |
11196 | temp_fill = get_absolute_expression (); |
11197 | } | |
11198 | else | |
11199 | temp_fill = 0; | |
11200 | if (temp) | |
11201 | { | |
11202 | auto_align = 1; | |
11203 | mips_align (temp, (int) temp_fill, | |
11204 | insn_labels != NULL ? insn_labels->label : NULL); | |
11205 | } | |
11206 | else | |
11207 | { | |
11208 | auto_align = 0; | |
11209 | } | |
11210 | ||
11211 | demand_empty_rest_of_line (); | |
11212 | } | |
11213 | ||
252b5132 | 11214 | static void |
17a2f251 | 11215 | s_change_sec (int sec) |
252b5132 RH |
11216 | { |
11217 | segT seg; | |
11218 | ||
252b5132 RH |
11219 | #ifdef OBJ_ELF |
11220 | /* The ELF backend needs to know that we are changing sections, so | |
11221 | that .previous works correctly. We could do something like check | |
b6ff326e | 11222 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11223 | as it would not be appropriate to use it in the section changing |
11224 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11225 | This should be cleaner, somehow. */ | |
11226 | obj_elf_section_change_hook (); | |
11227 | #endif | |
11228 | ||
7d10b47d | 11229 | mips_emit_delays (); |
252b5132 RH |
11230 | switch (sec) |
11231 | { | |
11232 | case 't': | |
11233 | s_text (0); | |
11234 | break; | |
11235 | case 'd': | |
11236 | s_data (0); | |
11237 | break; | |
11238 | case 'b': | |
11239 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11240 | demand_empty_rest_of_line (); | |
11241 | break; | |
11242 | ||
11243 | case 'r': | |
4d0d148d TS |
11244 | seg = subseg_new (RDATA_SECTION_NAME, |
11245 | (subsegT) get_absolute_expression ()); | |
11246 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11247 | { |
4d0d148d TS |
11248 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11249 | | SEC_READONLY | SEC_RELOC | |
11250 | | SEC_DATA)); | |
11251 | if (strcmp (TARGET_OS, "elf") != 0) | |
11252 | record_alignment (seg, 4); | |
252b5132 | 11253 | } |
4d0d148d | 11254 | demand_empty_rest_of_line (); |
252b5132 RH |
11255 | break; |
11256 | ||
11257 | case 's': | |
4d0d148d TS |
11258 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11259 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11260 | { |
4d0d148d TS |
11261 | bfd_set_section_flags (stdoutput, seg, |
11262 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11263 | if (strcmp (TARGET_OS, "elf") != 0) | |
11264 | record_alignment (seg, 4); | |
252b5132 | 11265 | } |
4d0d148d TS |
11266 | demand_empty_rest_of_line (); |
11267 | break; | |
252b5132 RH |
11268 | } |
11269 | ||
11270 | auto_align = 1; | |
11271 | } | |
b34976b6 | 11272 | |
cca86cc8 | 11273 | void |
17a2f251 | 11274 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11275 | { |
7ed4a06a | 11276 | #ifdef OBJ_ELF |
cca86cc8 SC |
11277 | char *section_name; |
11278 | char c; | |
684022ea | 11279 | char next_c = 0; |
cca86cc8 SC |
11280 | int section_type; |
11281 | int section_flag; | |
11282 | int section_entry_size; | |
11283 | int section_alignment; | |
b34976b6 | 11284 | |
7ed4a06a TS |
11285 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11286 | return; | |
11287 | ||
cca86cc8 SC |
11288 | section_name = input_line_pointer; |
11289 | c = get_symbol_end (); | |
a816d1ed AO |
11290 | if (c) |
11291 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11292 | |
4cf0dd0d TS |
11293 | /* Do we have .section Name<,"flags">? */ |
11294 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11295 | { |
4cf0dd0d TS |
11296 | /* just after name is now '\0'. */ |
11297 | *input_line_pointer = c; | |
cca86cc8 SC |
11298 | input_line_pointer = section_name; |
11299 | obj_elf_section (ignore); | |
11300 | return; | |
11301 | } | |
11302 | input_line_pointer++; | |
11303 | ||
11304 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11305 | if (c == ',') | |
11306 | section_type = get_absolute_expression (); | |
11307 | else | |
11308 | section_type = 0; | |
11309 | if (*input_line_pointer++ == ',') | |
11310 | section_flag = get_absolute_expression (); | |
11311 | else | |
11312 | section_flag = 0; | |
11313 | if (*input_line_pointer++ == ',') | |
11314 | section_entry_size = get_absolute_expression (); | |
11315 | else | |
11316 | section_entry_size = 0; | |
11317 | if (*input_line_pointer++ == ',') | |
11318 | section_alignment = get_absolute_expression (); | |
11319 | else | |
11320 | section_alignment = 0; | |
11321 | ||
a816d1ed AO |
11322 | section_name = xstrdup (section_name); |
11323 | ||
8ab8a5c8 RS |
11324 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11325 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11326 | traditionally had to fall back on the more common @progbits instead. | |
11327 | ||
11328 | There's nothing really harmful in this, since bfd will correct | |
11329 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11330 | means that, for backwards compatibiltiy, the special_section entries | |
11331 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11332 | ||
11333 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11334 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11335 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11336 | generic type-checking code. */ | |
11337 | if (section_type == SHT_MIPS_DWARF) | |
11338 | section_type = SHT_PROGBITS; | |
11339 | ||
cca86cc8 SC |
11340 | obj_elf_change_section (section_name, section_type, section_flag, |
11341 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11342 | |
11343 | if (now_seg->name != section_name) | |
11344 | free (section_name); | |
7ed4a06a | 11345 | #endif /* OBJ_ELF */ |
cca86cc8 | 11346 | } |
252b5132 RH |
11347 | |
11348 | void | |
17a2f251 | 11349 | mips_enable_auto_align (void) |
252b5132 RH |
11350 | { |
11351 | auto_align = 1; | |
11352 | } | |
11353 | ||
11354 | static void | |
17a2f251 | 11355 | s_cons (int log_size) |
252b5132 RH |
11356 | { |
11357 | symbolS *label; | |
11358 | ||
11359 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11360 | mips_emit_delays (); |
252b5132 RH |
11361 | if (log_size > 0 && auto_align) |
11362 | mips_align (log_size, 0, label); | |
11363 | mips_clear_insn_labels (); | |
11364 | cons (1 << log_size); | |
11365 | } | |
11366 | ||
11367 | static void | |
17a2f251 | 11368 | s_float_cons (int type) |
252b5132 RH |
11369 | { |
11370 | symbolS *label; | |
11371 | ||
11372 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11373 | ||
7d10b47d | 11374 | mips_emit_delays (); |
252b5132 RH |
11375 | |
11376 | if (auto_align) | |
49309057 ILT |
11377 | { |
11378 | if (type == 'd') | |
11379 | mips_align (3, 0, label); | |
11380 | else | |
11381 | mips_align (2, 0, label); | |
11382 | } | |
252b5132 RH |
11383 | |
11384 | mips_clear_insn_labels (); | |
11385 | ||
11386 | float_cons (type); | |
11387 | } | |
11388 | ||
11389 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11390 | permitted to say | |
11391 | .globl foo .text | |
11392 | where foo is an undefined symbol, to mean that foo should be | |
11393 | considered to be the address of a function. */ | |
11394 | ||
11395 | static void | |
17a2f251 | 11396 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11397 | { |
11398 | char *name; | |
11399 | int c; | |
11400 | symbolS *symbolP; | |
11401 | flagword flag; | |
11402 | ||
11403 | name = input_line_pointer; | |
11404 | c = get_symbol_end (); | |
11405 | symbolP = symbol_find_or_make (name); | |
11406 | *input_line_pointer = c; | |
11407 | SKIP_WHITESPACE (); | |
11408 | ||
11409 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11410 | being a function is apparently labelled as being an object. */ | |
11411 | flag = BSF_OBJECT; | |
11412 | ||
11413 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11414 | { | |
11415 | char *secname; | |
11416 | asection *sec; | |
11417 | ||
11418 | secname = input_line_pointer; | |
11419 | c = get_symbol_end (); | |
11420 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11421 | if (sec == NULL) | |
11422 | as_bad (_("%s: no such section"), secname); | |
11423 | *input_line_pointer = c; | |
11424 | ||
11425 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11426 | flag = BSF_FUNCTION; | |
11427 | } | |
11428 | ||
49309057 | 11429 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11430 | |
11431 | S_SET_EXTERNAL (symbolP); | |
11432 | demand_empty_rest_of_line (); | |
11433 | } | |
11434 | ||
11435 | static void | |
17a2f251 | 11436 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11437 | { |
11438 | char *opt; | |
11439 | char c; | |
11440 | ||
11441 | opt = input_line_pointer; | |
11442 | c = get_symbol_end (); | |
11443 | ||
11444 | if (*opt == 'O') | |
11445 | { | |
11446 | /* FIXME: What does this mean? */ | |
11447 | } | |
11448 | else if (strncmp (opt, "pic", 3) == 0) | |
11449 | { | |
11450 | int i; | |
11451 | ||
11452 | i = atoi (opt + 3); | |
11453 | if (i == 0) | |
11454 | mips_pic = NO_PIC; | |
11455 | else if (i == 2) | |
143d77c5 | 11456 | { |
252b5132 | 11457 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11458 | mips_abicalls = TRUE; |
11459 | } | |
252b5132 RH |
11460 | else |
11461 | as_bad (_(".option pic%d not supported"), i); | |
11462 | ||
4d0d148d | 11463 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11464 | { |
11465 | if (g_switch_seen && g_switch_value != 0) | |
11466 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11467 | g_switch_value = 0; | |
11468 | bfd_set_gp_size (stdoutput, 0); | |
11469 | } | |
11470 | } | |
11471 | else | |
11472 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11473 | ||
11474 | *input_line_pointer = c; | |
11475 | demand_empty_rest_of_line (); | |
11476 | } | |
11477 | ||
11478 | /* This structure is used to hold a stack of .set values. */ | |
11479 | ||
e972090a NC |
11480 | struct mips_option_stack |
11481 | { | |
252b5132 RH |
11482 | struct mips_option_stack *next; |
11483 | struct mips_set_options options; | |
11484 | }; | |
11485 | ||
11486 | static struct mips_option_stack *mips_opts_stack; | |
11487 | ||
11488 | /* Handle the .set pseudo-op. */ | |
11489 | ||
11490 | static void | |
17a2f251 | 11491 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11492 | { |
11493 | char *name = input_line_pointer, ch; | |
11494 | ||
11495 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11496 | ++input_line_pointer; |
252b5132 RH |
11497 | ch = *input_line_pointer; |
11498 | *input_line_pointer = '\0'; | |
11499 | ||
11500 | if (strcmp (name, "reorder") == 0) | |
11501 | { | |
7d10b47d RS |
11502 | if (mips_opts.noreorder) |
11503 | end_noreorder (); | |
252b5132 RH |
11504 | } |
11505 | else if (strcmp (name, "noreorder") == 0) | |
11506 | { | |
7d10b47d RS |
11507 | if (!mips_opts.noreorder) |
11508 | start_noreorder (); | |
252b5132 RH |
11509 | } |
11510 | else if (strcmp (name, "at") == 0) | |
11511 | { | |
11512 | mips_opts.noat = 0; | |
11513 | } | |
11514 | else if (strcmp (name, "noat") == 0) | |
11515 | { | |
11516 | mips_opts.noat = 1; | |
11517 | } | |
11518 | else if (strcmp (name, "macro") == 0) | |
11519 | { | |
11520 | mips_opts.warn_about_macros = 0; | |
11521 | } | |
11522 | else if (strcmp (name, "nomacro") == 0) | |
11523 | { | |
11524 | if (mips_opts.noreorder == 0) | |
11525 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11526 | mips_opts.warn_about_macros = 1; | |
11527 | } | |
11528 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11529 | { | |
11530 | mips_opts.nomove = 0; | |
11531 | } | |
11532 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11533 | { | |
11534 | mips_opts.nomove = 1; | |
11535 | } | |
11536 | else if (strcmp (name, "bopt") == 0) | |
11537 | { | |
11538 | mips_opts.nobopt = 0; | |
11539 | } | |
11540 | else if (strcmp (name, "nobopt") == 0) | |
11541 | { | |
11542 | mips_opts.nobopt = 1; | |
11543 | } | |
11544 | else if (strcmp (name, "mips16") == 0 | |
11545 | || strcmp (name, "MIPS-16") == 0) | |
11546 | mips_opts.mips16 = 1; | |
11547 | else if (strcmp (name, "nomips16") == 0 | |
11548 | || strcmp (name, "noMIPS-16") == 0) | |
11549 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11550 | else if (strcmp (name, "mips3d") == 0) |
11551 | mips_opts.ase_mips3d = 1; | |
11552 | else if (strcmp (name, "nomips3d") == 0) | |
11553 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11554 | else if (strcmp (name, "mdmx") == 0) |
11555 | mips_opts.ase_mdmx = 1; | |
11556 | else if (strcmp (name, "nomdmx") == 0) | |
11557 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11558 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11559 | { |
af7ee8bf | 11560 | int reset = 0; |
252b5132 | 11561 | |
1a2c1fad CD |
11562 | /* Permit the user to change the ISA and architecture on the fly. |
11563 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11564 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11565 | { |
11566 | reset = 1; | |
11567 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11568 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11569 | } |
11570 | else if (strncmp (name, "arch=", 5) == 0) | |
11571 | { | |
11572 | const struct mips_cpu_info *p; | |
11573 | ||
11574 | p = mips_parse_cpu("internal use", name + 5); | |
11575 | if (!p) | |
11576 | as_bad (_("unknown architecture %s"), name + 5); | |
11577 | else | |
11578 | { | |
11579 | mips_opts.arch = p->cpu; | |
11580 | mips_opts.isa = p->isa; | |
11581 | } | |
11582 | } | |
81a21e38 TS |
11583 | else if (strncmp (name, "mips", 4) == 0) |
11584 | { | |
11585 | const struct mips_cpu_info *p; | |
11586 | ||
11587 | p = mips_parse_cpu("internal use", name); | |
11588 | if (!p) | |
11589 | as_bad (_("unknown ISA level %s"), name + 4); | |
11590 | else | |
11591 | { | |
11592 | mips_opts.arch = p->cpu; | |
11593 | mips_opts.isa = p->isa; | |
11594 | } | |
11595 | } | |
af7ee8bf | 11596 | else |
81a21e38 | 11597 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11598 | |
11599 | switch (mips_opts.isa) | |
98d3f06f KH |
11600 | { |
11601 | case 0: | |
98d3f06f | 11602 | break; |
af7ee8bf CD |
11603 | case ISA_MIPS1: |
11604 | case ISA_MIPS2: | |
11605 | case ISA_MIPS32: | |
11606 | case ISA_MIPS32R2: | |
98d3f06f KH |
11607 | mips_opts.gp32 = 1; |
11608 | mips_opts.fp32 = 1; | |
11609 | break; | |
af7ee8bf CD |
11610 | case ISA_MIPS3: |
11611 | case ISA_MIPS4: | |
11612 | case ISA_MIPS5: | |
11613 | case ISA_MIPS64: | |
5f74bc13 | 11614 | case ISA_MIPS64R2: |
98d3f06f KH |
11615 | mips_opts.gp32 = 0; |
11616 | mips_opts.fp32 = 0; | |
11617 | break; | |
11618 | default: | |
11619 | as_bad (_("unknown ISA level %s"), name + 4); | |
11620 | break; | |
11621 | } | |
af7ee8bf | 11622 | if (reset) |
98d3f06f | 11623 | { |
af7ee8bf CD |
11624 | mips_opts.gp32 = file_mips_gp32; |
11625 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11626 | } |
252b5132 RH |
11627 | } |
11628 | else if (strcmp (name, "autoextend") == 0) | |
11629 | mips_opts.noautoextend = 0; | |
11630 | else if (strcmp (name, "noautoextend") == 0) | |
11631 | mips_opts.noautoextend = 1; | |
11632 | else if (strcmp (name, "push") == 0) | |
11633 | { | |
11634 | struct mips_option_stack *s; | |
11635 | ||
11636 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11637 | s->next = mips_opts_stack; | |
11638 | s->options = mips_opts; | |
11639 | mips_opts_stack = s; | |
11640 | } | |
11641 | else if (strcmp (name, "pop") == 0) | |
11642 | { | |
11643 | struct mips_option_stack *s; | |
11644 | ||
11645 | s = mips_opts_stack; | |
11646 | if (s == NULL) | |
11647 | as_bad (_(".set pop with no .set push")); | |
11648 | else | |
11649 | { | |
11650 | /* If we're changing the reorder mode we need to handle | |
11651 | delay slots correctly. */ | |
11652 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 11653 | start_noreorder (); |
252b5132 | 11654 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 11655 | end_noreorder (); |
252b5132 RH |
11656 | |
11657 | mips_opts = s->options; | |
11658 | mips_opts_stack = s->next; | |
11659 | free (s); | |
11660 | } | |
11661 | } | |
aed1a261 RS |
11662 | else if (strcmp (name, "sym32") == 0) |
11663 | mips_opts.sym32 = TRUE; | |
11664 | else if (strcmp (name, "nosym32") == 0) | |
11665 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11666 | else |
11667 | { | |
11668 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11669 | } | |
11670 | *input_line_pointer = ch; | |
11671 | demand_empty_rest_of_line (); | |
11672 | } | |
11673 | ||
11674 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11675 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11676 | ||
11677 | static void | |
17a2f251 | 11678 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11679 | { |
11680 | mips_pic = SVR4_PIC; | |
143d77c5 | 11681 | mips_abicalls = TRUE; |
4d0d148d TS |
11682 | |
11683 | if (g_switch_seen && g_switch_value != 0) | |
11684 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11685 | g_switch_value = 0; | |
11686 | ||
252b5132 RH |
11687 | bfd_set_gp_size (stdoutput, 0); |
11688 | demand_empty_rest_of_line (); | |
11689 | } | |
11690 | ||
11691 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11692 | PIC code. It sets the $gp register for the function based on the | |
11693 | function address, which is in the register named in the argument. | |
11694 | This uses a relocation against _gp_disp, which is handled specially | |
11695 | by the linker. The result is: | |
11696 | lui $gp,%hi(_gp_disp) | |
11697 | addiu $gp,$gp,%lo(_gp_disp) | |
11698 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11699 | The .cpload argument is normally $25 == $t9. |
11700 | ||
11701 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11702 | lui $gp,%hi(__gnu_local_gp) |
11703 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11704 | and the argument is ignored. This saves an instruction, but the |
11705 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11706 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11707 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11708 | |
11709 | static void | |
17a2f251 | 11710 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11711 | { |
11712 | expressionS ex; | |
aa6975fb ILT |
11713 | int reg; |
11714 | int in_shared; | |
252b5132 | 11715 | |
6478892d TS |
11716 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11717 | .cpload is ignored. */ | |
11718 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11719 | { |
11720 | s_ignore (0); | |
11721 | return; | |
11722 | } | |
11723 | ||
d3ecfc59 | 11724 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11725 | if (mips_opts.noreorder == 0) |
11726 | as_warn (_(".cpload not in noreorder section")); | |
11727 | ||
aa6975fb ILT |
11728 | reg = tc_get_register (0); |
11729 | ||
11730 | /* If we need to produce a 64-bit address, we are better off using | |
11731 | the default instruction sequence. */ | |
aed1a261 | 11732 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11733 | |
252b5132 | 11734 | ex.X_op = O_symbol; |
bbe506e8 TS |
11735 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11736 | "__gnu_local_gp"); | |
252b5132 RH |
11737 | ex.X_op_symbol = NULL; |
11738 | ex.X_add_number = 0; | |
11739 | ||
11740 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11741 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11742 | |
584892a6 | 11743 | macro_start (); |
67c0d1eb RS |
11744 | macro_build_lui (&ex, mips_gp_register); |
11745 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11746 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11747 | if (in_shared) |
11748 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11749 | mips_gp_register, reg); | |
584892a6 | 11750 | macro_end (); |
252b5132 RH |
11751 | |
11752 | demand_empty_rest_of_line (); | |
11753 | } | |
11754 | ||
6478892d TS |
11755 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11756 | .cpsetup $reg1, offset|$reg2, label | |
11757 | ||
11758 | If offset is given, this results in: | |
11759 | sd $gp, offset($sp) | |
956cd1d6 | 11760 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11761 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11762 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11763 | |
11764 | If $reg2 is given, this results in: | |
11765 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11766 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11767 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11768 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11769 | $reg1 is normally $25 == $t9. |
11770 | ||
11771 | The -mno-shared option replaces the last three instructions with | |
11772 | lui $gp,%hi(_gp) | |
11773 | addiu $gp,$gp,%lo(_gp) | |
11774 | */ | |
11775 | ||
6478892d | 11776 | static void |
17a2f251 | 11777 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11778 | { |
11779 | expressionS ex_off; | |
11780 | expressionS ex_sym; | |
11781 | int reg1; | |
6478892d | 11782 | |
8586fc66 | 11783 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11784 | We also need NewABI support. */ |
11785 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11786 | { | |
11787 | s_ignore (0); | |
11788 | return; | |
11789 | } | |
11790 | ||
11791 | reg1 = tc_get_register (0); | |
11792 | SKIP_WHITESPACE (); | |
11793 | if (*input_line_pointer != ',') | |
11794 | { | |
11795 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11796 | return; | |
11797 | } | |
11798 | else | |
80245285 | 11799 | ++input_line_pointer; |
6478892d TS |
11800 | SKIP_WHITESPACE (); |
11801 | if (*input_line_pointer == '$') | |
80245285 TS |
11802 | { |
11803 | mips_cpreturn_register = tc_get_register (0); | |
11804 | mips_cpreturn_offset = -1; | |
11805 | } | |
6478892d | 11806 | else |
80245285 TS |
11807 | { |
11808 | mips_cpreturn_offset = get_absolute_expression (); | |
11809 | mips_cpreturn_register = -1; | |
11810 | } | |
6478892d TS |
11811 | SKIP_WHITESPACE (); |
11812 | if (*input_line_pointer != ',') | |
11813 | { | |
11814 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11815 | return; | |
11816 | } | |
11817 | else | |
f9419b05 | 11818 | ++input_line_pointer; |
6478892d | 11819 | SKIP_WHITESPACE (); |
f21f8242 | 11820 | expression (&ex_sym); |
6478892d | 11821 | |
584892a6 | 11822 | macro_start (); |
6478892d TS |
11823 | if (mips_cpreturn_register == -1) |
11824 | { | |
11825 | ex_off.X_op = O_constant; | |
11826 | ex_off.X_add_symbol = NULL; | |
11827 | ex_off.X_op_symbol = NULL; | |
11828 | ex_off.X_add_number = mips_cpreturn_offset; | |
11829 | ||
67c0d1eb | 11830 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11831 | BFD_RELOC_LO16, SP); |
6478892d TS |
11832 | } |
11833 | else | |
67c0d1eb | 11834 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11835 | mips_gp_register, 0); |
6478892d | 11836 | |
aed1a261 | 11837 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
11838 | { |
11839 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11840 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11841 | BFD_RELOC_HI16_S); | |
11842 | ||
11843 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11844 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11845 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11846 | ||
11847 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11848 | mips_gp_register, reg1); | |
11849 | } | |
11850 | else | |
11851 | { | |
11852 | expressionS ex; | |
11853 | ||
11854 | ex.X_op = O_symbol; | |
4184909a | 11855 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
11856 | ex.X_op_symbol = NULL; |
11857 | ex.X_add_number = 0; | |
6e1304d8 | 11858 | |
aa6975fb ILT |
11859 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11860 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11861 | ||
11862 | macro_build_lui (&ex, mips_gp_register); | |
11863 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11864 | mips_gp_register, BFD_RELOC_LO16); | |
11865 | } | |
f21f8242 | 11866 | |
584892a6 | 11867 | macro_end (); |
6478892d TS |
11868 | |
11869 | demand_empty_rest_of_line (); | |
11870 | } | |
11871 | ||
11872 | static void | |
17a2f251 | 11873 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11874 | { |
11875 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11876 | .cplocal is ignored. */ | |
11877 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11878 | { | |
11879 | s_ignore (0); | |
11880 | return; | |
11881 | } | |
11882 | ||
11883 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11884 | demand_empty_rest_of_line (); |
6478892d TS |
11885 | } |
11886 | ||
252b5132 RH |
11887 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11888 | offset from $sp. The offset is remembered, and after making a PIC | |
11889 | call $gp is restored from that location. */ | |
11890 | ||
11891 | static void | |
17a2f251 | 11892 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11893 | { |
11894 | expressionS ex; | |
252b5132 | 11895 | |
6478892d | 11896 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11897 | .cprestore is ignored. */ |
6478892d | 11898 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11899 | { |
11900 | s_ignore (0); | |
11901 | return; | |
11902 | } | |
11903 | ||
11904 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11905 | mips_cprestore_valid = 1; |
252b5132 RH |
11906 | |
11907 | ex.X_op = O_constant; | |
11908 | ex.X_add_symbol = NULL; | |
11909 | ex.X_op_symbol = NULL; | |
11910 | ex.X_add_number = mips_cprestore_offset; | |
11911 | ||
584892a6 | 11912 | macro_start (); |
67c0d1eb RS |
11913 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11914 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11915 | macro_end (); |
252b5132 RH |
11916 | |
11917 | demand_empty_rest_of_line (); | |
11918 | } | |
11919 | ||
6478892d | 11920 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11921 | was given in the preceding .cpsetup, it results in: |
6478892d | 11922 | ld $gp, offset($sp) |
76b3015f | 11923 | |
6478892d | 11924 | If a register $reg2 was given there, it results in: |
609f23f4 | 11925 | daddu $gp, $reg2, $0 |
6478892d TS |
11926 | */ |
11927 | static void | |
17a2f251 | 11928 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11929 | { |
11930 | expressionS ex; | |
6478892d TS |
11931 | |
11932 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11933 | We also need NewABI support. */ | |
11934 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11935 | { | |
11936 | s_ignore (0); | |
11937 | return; | |
11938 | } | |
11939 | ||
584892a6 | 11940 | macro_start (); |
6478892d TS |
11941 | if (mips_cpreturn_register == -1) |
11942 | { | |
11943 | ex.X_op = O_constant; | |
11944 | ex.X_add_symbol = NULL; | |
11945 | ex.X_op_symbol = NULL; | |
11946 | ex.X_add_number = mips_cpreturn_offset; | |
11947 | ||
67c0d1eb | 11948 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11949 | } |
11950 | else | |
67c0d1eb | 11951 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11952 | mips_cpreturn_register, 0); |
584892a6 | 11953 | macro_end (); |
6478892d TS |
11954 | |
11955 | demand_empty_rest_of_line (); | |
11956 | } | |
11957 | ||
11958 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11959 | code. It sets the offset to use in gp_rel relocations. */ | |
11960 | ||
11961 | static void | |
17a2f251 | 11962 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11963 | { |
11964 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11965 | We also need NewABI support. */ | |
11966 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11967 | { | |
11968 | s_ignore (0); | |
11969 | return; | |
11970 | } | |
11971 | ||
def2e0dd | 11972 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11973 | |
11974 | demand_empty_rest_of_line (); | |
11975 | } | |
11976 | ||
252b5132 RH |
11977 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11978 | code. It generates a 32 bit GP relative reloc. */ | |
11979 | ||
11980 | static void | |
17a2f251 | 11981 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11982 | { |
11983 | symbolS *label; | |
11984 | expressionS ex; | |
11985 | char *p; | |
11986 | ||
11987 | /* When not generating PIC code, this is treated as .word. */ | |
11988 | if (mips_pic != SVR4_PIC) | |
11989 | { | |
11990 | s_cons (2); | |
11991 | return; | |
11992 | } | |
11993 | ||
11994 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 11995 | mips_emit_delays (); |
252b5132 RH |
11996 | if (auto_align) |
11997 | mips_align (2, 0, label); | |
11998 | mips_clear_insn_labels (); | |
11999 | ||
12000 | expression (&ex); | |
12001 | ||
12002 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12003 | { | |
12004 | as_bad (_("Unsupported use of .gpword")); | |
12005 | ignore_rest_of_line (); | |
12006 | } | |
12007 | ||
12008 | p = frag_more (4); | |
17a2f251 | 12009 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12010 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12011 | BFD_RELOC_GPREL32); |
252b5132 RH |
12012 | |
12013 | demand_empty_rest_of_line (); | |
12014 | } | |
12015 | ||
10181a0d | 12016 | static void |
17a2f251 | 12017 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12018 | { |
12019 | symbolS *label; | |
12020 | expressionS ex; | |
12021 | char *p; | |
12022 | ||
12023 | /* When not generating PIC code, this is treated as .dword. */ | |
12024 | if (mips_pic != SVR4_PIC) | |
12025 | { | |
12026 | s_cons (3); | |
12027 | return; | |
12028 | } | |
12029 | ||
12030 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12031 | mips_emit_delays (); |
10181a0d AO |
12032 | if (auto_align) |
12033 | mips_align (3, 0, label); | |
12034 | mips_clear_insn_labels (); | |
12035 | ||
12036 | expression (&ex); | |
12037 | ||
12038 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12039 | { | |
12040 | as_bad (_("Unsupported use of .gpdword")); | |
12041 | ignore_rest_of_line (); | |
12042 | } | |
12043 | ||
12044 | p = frag_more (8); | |
17a2f251 | 12045 | md_number_to_chars (p, 0, 8); |
a105a300 | 12046 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12047 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12048 | |
12049 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12050 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12051 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12052 | |
12053 | demand_empty_rest_of_line (); | |
12054 | } | |
12055 | ||
252b5132 RH |
12056 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12057 | tables in SVR4 PIC code. */ | |
12058 | ||
12059 | static void | |
17a2f251 | 12060 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12061 | { |
252b5132 RH |
12062 | int reg; |
12063 | ||
10181a0d AO |
12064 | /* This is ignored when not generating SVR4 PIC code. */ |
12065 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12066 | { |
12067 | s_ignore (0); | |
12068 | return; | |
12069 | } | |
12070 | ||
12071 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12072 | macro_start (); |
252b5132 | 12073 | reg = tc_get_register (0); |
67c0d1eb | 12074 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12075 | macro_end (); |
252b5132 | 12076 | |
bdaaa2e1 | 12077 | demand_empty_rest_of_line (); |
252b5132 RH |
12078 | } |
12079 | ||
12080 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12081 | mips16 mode. This permits the linker to handle them specially, | |
12082 | such as generating jalx instructions when needed. We also make | |
12083 | them odd for the duration of the assembly, in order to generate the | |
12084 | right sort of code. We will make them even in the adjust_symtab | |
12085 | routine, while leaving them marked. This is convenient for the | |
12086 | debugger and the disassembler. The linker knows to make them odd | |
12087 | again. */ | |
12088 | ||
12089 | static void | |
17a2f251 | 12090 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12091 | { |
f9419b05 | 12092 | mips16_mark_labels (); |
252b5132 RH |
12093 | |
12094 | demand_empty_rest_of_line (); | |
12095 | } | |
12096 | ||
12097 | /* Handle a .stabn directive. We need these in order to mark a label | |
12098 | as being a mips16 text label correctly. Sometimes the compiler | |
12099 | will emit a label, followed by a .stabn, and then switch sections. | |
12100 | If the label and .stabn are in mips16 mode, then the label is | |
12101 | really a mips16 text label. */ | |
12102 | ||
12103 | static void | |
17a2f251 | 12104 | s_mips_stab (int type) |
252b5132 | 12105 | { |
f9419b05 | 12106 | if (type == 'n') |
252b5132 RH |
12107 | mips16_mark_labels (); |
12108 | ||
12109 | s_stab (type); | |
12110 | } | |
12111 | ||
12112 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12113 | */ | |
12114 | ||
12115 | static void | |
17a2f251 | 12116 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12117 | { |
12118 | char *name; | |
12119 | int c; | |
12120 | symbolS *symbolP; | |
12121 | expressionS exp; | |
12122 | ||
12123 | name = input_line_pointer; | |
12124 | c = get_symbol_end (); | |
12125 | symbolP = symbol_find_or_make (name); | |
12126 | S_SET_WEAK (symbolP); | |
12127 | *input_line_pointer = c; | |
12128 | ||
12129 | SKIP_WHITESPACE (); | |
12130 | ||
12131 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12132 | { | |
12133 | if (S_IS_DEFINED (symbolP)) | |
12134 | { | |
956cd1d6 | 12135 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12136 | S_GET_NAME (symbolP)); |
12137 | ignore_rest_of_line (); | |
12138 | return; | |
12139 | } | |
bdaaa2e1 | 12140 | |
252b5132 RH |
12141 | if (*input_line_pointer == ',') |
12142 | { | |
12143 | ++input_line_pointer; | |
12144 | SKIP_WHITESPACE (); | |
12145 | } | |
bdaaa2e1 | 12146 | |
252b5132 RH |
12147 | expression (&exp); |
12148 | if (exp.X_op != O_symbol) | |
12149 | { | |
12150 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12151 | ignore_rest_of_line (); |
252b5132 RH |
12152 | return; |
12153 | } | |
49309057 | 12154 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12155 | } |
12156 | ||
12157 | demand_empty_rest_of_line (); | |
12158 | } | |
12159 | ||
12160 | /* Parse a register string into a number. Called from the ECOFF code | |
12161 | to parse .frame. The argument is non-zero if this is the frame | |
12162 | register, so that we can record it in mips_frame_reg. */ | |
12163 | ||
12164 | int | |
17a2f251 | 12165 | tc_get_register (int frame) |
252b5132 RH |
12166 | { |
12167 | int reg; | |
12168 | ||
12169 | SKIP_WHITESPACE (); | |
12170 | if (*input_line_pointer++ != '$') | |
12171 | { | |
12172 | as_warn (_("expected `$'")); | |
85b51719 | 12173 | reg = ZERO; |
252b5132 | 12174 | } |
3882b010 | 12175 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12176 | { |
12177 | reg = get_absolute_expression (); | |
12178 | if (reg < 0 || reg >= 32) | |
12179 | { | |
12180 | as_warn (_("Bad register number")); | |
85b51719 | 12181 | reg = ZERO; |
252b5132 RH |
12182 | } |
12183 | } | |
12184 | else | |
12185 | { | |
76db943d | 12186 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12187 | { |
12188 | reg = RA; | |
12189 | input_line_pointer += 2; | |
12190 | } | |
76db943d | 12191 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12192 | { |
12193 | reg = FP; | |
12194 | input_line_pointer += 2; | |
12195 | } | |
252b5132 | 12196 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12197 | { |
12198 | reg = SP; | |
12199 | input_line_pointer += 2; | |
12200 | } | |
252b5132 | 12201 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12202 | { |
12203 | reg = GP; | |
12204 | input_line_pointer += 2; | |
12205 | } | |
252b5132 | 12206 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12207 | { |
12208 | reg = AT; | |
12209 | input_line_pointer += 2; | |
12210 | } | |
12211 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12212 | { | |
12213 | reg = KT0; | |
12214 | input_line_pointer += 3; | |
12215 | } | |
12216 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12217 | { | |
12218 | reg = KT1; | |
12219 | input_line_pointer += 3; | |
12220 | } | |
12221 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12222 | { | |
12223 | reg = ZERO; | |
12224 | input_line_pointer += 4; | |
12225 | } | |
252b5132 RH |
12226 | else |
12227 | { | |
12228 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12229 | reg = ZERO; |
12230 | while (ISALNUM(*input_line_pointer)) | |
12231 | input_line_pointer++; | |
252b5132 | 12232 | } |
252b5132 RH |
12233 | } |
12234 | if (frame) | |
7a621144 DJ |
12235 | { |
12236 | mips_frame_reg = reg != 0 ? reg : SP; | |
12237 | mips_frame_reg_valid = 1; | |
12238 | mips_cprestore_valid = 0; | |
12239 | } | |
252b5132 RH |
12240 | return reg; |
12241 | } | |
12242 | ||
12243 | valueT | |
17a2f251 | 12244 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12245 | { |
12246 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12247 | ||
12248 | #ifdef OBJ_ELF | |
12249 | /* We don't need to align ELF sections to the full alignment. | |
12250 | However, Irix 5 may prefer that we align them at least to a 16 | |
12251 | byte boundary. We don't bother to align the sections if we are | |
12252 | targeted for an embedded system. */ | |
12253 | if (strcmp (TARGET_OS, "elf") == 0) | |
12254 | return addr; | |
12255 | if (align > 4) | |
12256 | align = 4; | |
12257 | #endif | |
12258 | ||
12259 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12260 | } | |
12261 | ||
12262 | /* Utility routine, called from above as well. If called while the | |
12263 | input file is still being read, it's only an approximation. (For | |
12264 | example, a symbol may later become defined which appeared to be | |
12265 | undefined earlier.) */ | |
12266 | ||
12267 | static int | |
17a2f251 | 12268 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12269 | { |
12270 | if (sym == 0) | |
12271 | return 0; | |
12272 | ||
4d0d148d | 12273 | if (g_switch_value > 0) |
252b5132 RH |
12274 | { |
12275 | const char *symname; | |
12276 | int change; | |
12277 | ||
c9914766 | 12278 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12279 | register. It can be if it is smaller than the -G size or if |
12280 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12281 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12282 | they can. */ |
12283 | symname = S_GET_NAME (sym); | |
12284 | if (symname != (const char *) NULL | |
12285 | && (strcmp (symname, "eprol") == 0 | |
12286 | || strcmp (symname, "etext") == 0 | |
12287 | || strcmp (symname, "_gp") == 0 | |
12288 | || strcmp (symname, "edata") == 0 | |
12289 | || strcmp (symname, "_fbss") == 0 | |
12290 | || strcmp (symname, "_fdata") == 0 | |
12291 | || strcmp (symname, "_ftext") == 0 | |
12292 | || strcmp (symname, "end") == 0 | |
12293 | || strcmp (symname, "_gp_disp") == 0)) | |
12294 | change = 1; | |
12295 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12296 | && (0 | |
12297 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12298 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12299 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12300 | <= g_switch_value)) | |
252b5132 RH |
12301 | #endif |
12302 | /* We must defer this decision until after the whole | |
12303 | file has been read, since there might be a .extern | |
12304 | after the first use of this symbol. */ | |
12305 | || (before_relaxing | |
12306 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12307 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12308 | #endif |
12309 | && S_GET_VALUE (sym) == 0) | |
12310 | || (S_GET_VALUE (sym) != 0 | |
12311 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12312 | change = 0; | |
12313 | else | |
12314 | { | |
12315 | const char *segname; | |
12316 | ||
12317 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12318 | assert (strcmp (segname, ".lit8") != 0 | |
12319 | && strcmp (segname, ".lit4") != 0); | |
12320 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12321 | && strcmp (segname, ".sbss") != 0 |
12322 | && strncmp (segname, ".sdata.", 7) != 0 | |
12323 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12324 | } |
12325 | return change; | |
12326 | } | |
12327 | else | |
c9914766 | 12328 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12329 | return 1; |
12330 | } | |
12331 | ||
5919d012 RS |
12332 | |
12333 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12334 | ||
12335 | static bfd_boolean | |
17a2f251 | 12336 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12337 | { |
12338 | asection *symsec; | |
12339 | bfd_boolean linkonce; | |
12340 | ||
12341 | /* Handle the case of a symbol equated to another symbol. */ | |
12342 | while (symbol_equated_reloc_p (sym)) | |
12343 | { | |
12344 | symbolS *n; | |
12345 | ||
12346 | /* It's possible to get a loop here in a badly written | |
12347 | program. */ | |
12348 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12349 | if (n == sym) | |
12350 | break; | |
12351 | sym = n; | |
12352 | } | |
12353 | ||
12354 | symsec = S_GET_SEGMENT (sym); | |
12355 | ||
12356 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12357 | linkonce = FALSE; | |
12358 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12359 | { | |
12360 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12361 | != 0) | |
12362 | linkonce = TRUE; | |
12363 | ||
12364 | /* The GNU toolchain uses an extension for ELF: a section | |
12365 | beginning with the magic string .gnu.linkonce is a linkonce | |
12366 | section. */ | |
12367 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12368 | sizeof ".gnu.linkonce" - 1) == 0) | |
12369 | linkonce = TRUE; | |
12370 | } | |
12371 | ||
12372 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12373 | return (symsec != &bfd_und_section | |
12374 | && symsec != &bfd_abs_section | |
12375 | && ! bfd_is_com_section (symsec) | |
12376 | && !linkonce | |
12377 | #ifdef OBJ_ELF | |
12378 | /* A global or weak symbol is treated as external. */ | |
12379 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12380 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12381 | #endif |
12382 | ); | |
12383 | } | |
12384 | ||
12385 | ||
252b5132 RH |
12386 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12387 | extended opcode. SEC is the section the frag is in. */ | |
12388 | ||
12389 | static int | |
17a2f251 | 12390 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12391 | { |
12392 | int type; | |
12393 | register const struct mips16_immed_operand *op; | |
12394 | offsetT val; | |
12395 | int mintiny, maxtiny; | |
12396 | segT symsec; | |
98aa84af | 12397 | fragS *sym_frag; |
252b5132 RH |
12398 | |
12399 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12400 | return 0; | |
12401 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12402 | return 1; | |
12403 | ||
12404 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12405 | op = mips16_immed_operands; | |
12406 | while (op->type != type) | |
12407 | { | |
12408 | ++op; | |
12409 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12410 | } | |
12411 | ||
12412 | if (op->unsp) | |
12413 | { | |
12414 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12415 | { | |
12416 | mintiny = 1; | |
12417 | maxtiny = 1 << op->nbits; | |
12418 | } | |
12419 | else | |
12420 | { | |
12421 | mintiny = 0; | |
12422 | maxtiny = (1 << op->nbits) - 1; | |
12423 | } | |
12424 | } | |
12425 | else | |
12426 | { | |
12427 | mintiny = - (1 << (op->nbits - 1)); | |
12428 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12429 | } | |
12430 | ||
98aa84af | 12431 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12432 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12433 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12434 | |
12435 | if (op->pcrel) | |
12436 | { | |
12437 | addressT addr; | |
12438 | ||
12439 | /* We won't have the section when we are called from | |
12440 | mips_relax_frag. However, we will always have been called | |
12441 | from md_estimate_size_before_relax first. If this is a | |
12442 | branch to a different section, we mark it as such. If SEC is | |
12443 | NULL, and the frag is not marked, then it must be a branch to | |
12444 | the same section. */ | |
12445 | if (sec == NULL) | |
12446 | { | |
12447 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12448 | return 1; | |
12449 | } | |
12450 | else | |
12451 | { | |
98aa84af | 12452 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12453 | if (symsec != sec) |
12454 | { | |
12455 | fragp->fr_subtype = | |
12456 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12457 | ||
12458 | /* FIXME: We should support this, and let the linker | |
12459 | catch branches and loads that are out of range. */ | |
12460 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12461 | _("unsupported PC relative reference to different section")); | |
12462 | ||
12463 | return 1; | |
12464 | } | |
98aa84af AM |
12465 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12466 | /* Assume non-extended on the first relaxation pass. | |
12467 | The address we have calculated will be bogus if this is | |
12468 | a forward branch to another frag, as the forward frag | |
12469 | will have fr_address == 0. */ | |
12470 | return 0; | |
252b5132 RH |
12471 | } |
12472 | ||
12473 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12474 | the same section. If the relax_marker of the symbol fragment |
12475 | differs from the relax_marker of this fragment, we have not | |
12476 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12477 | in STRETCH in order to get a better estimate of the address. |
12478 | This particularly matters because of the shift bits. */ | |
12479 | if (stretch != 0 | |
98aa84af | 12480 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12481 | { |
12482 | fragS *f; | |
12483 | ||
12484 | /* Adjust stretch for any alignment frag. Note that if have | |
12485 | been expanding the earlier code, the symbol may be | |
12486 | defined in what appears to be an earlier frag. FIXME: | |
12487 | This doesn't handle the fr_subtype field, which specifies | |
12488 | a maximum number of bytes to skip when doing an | |
12489 | alignment. */ | |
98aa84af | 12490 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12491 | { |
12492 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12493 | { | |
12494 | if (stretch < 0) | |
12495 | stretch = - ((- stretch) | |
12496 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12497 | else | |
12498 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12499 | if (stretch == 0) | |
12500 | break; | |
12501 | } | |
12502 | } | |
12503 | if (f != NULL) | |
12504 | val += stretch; | |
12505 | } | |
12506 | ||
12507 | addr = fragp->fr_address + fragp->fr_fix; | |
12508 | ||
12509 | /* The base address rules are complicated. The base address of | |
12510 | a branch is the following instruction. The base address of a | |
12511 | PC relative load or add is the instruction itself, but if it | |
12512 | is in a delay slot (in which case it can not be extended) use | |
12513 | the address of the instruction whose delay slot it is in. */ | |
12514 | if (type == 'p' || type == 'q') | |
12515 | { | |
12516 | addr += 2; | |
12517 | ||
12518 | /* If we are currently assuming that this frag should be | |
12519 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12520 | higher. */ |
252b5132 RH |
12521 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12522 | addr += 2; | |
12523 | ||
12524 | /* Ignore the low bit in the target, since it will be set | |
12525 | for a text label. */ | |
12526 | if ((val & 1) != 0) | |
12527 | --val; | |
12528 | } | |
12529 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12530 | addr -= 4; | |
12531 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12532 | addr -= 2; | |
12533 | ||
12534 | val -= addr & ~ ((1 << op->shift) - 1); | |
12535 | ||
12536 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12537 | if (type == 'p' || type == 'q') | |
12538 | val /= 2; | |
12539 | ||
12540 | /* If any of the shifted bits are set, we must use an extended | |
12541 | opcode. If the address depends on the size of this | |
12542 | instruction, this can lead to a loop, so we arrange to always | |
12543 | use an extended opcode. We only check this when we are in | |
12544 | the main relaxation loop, when SEC is NULL. */ | |
12545 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12546 | { | |
12547 | fragp->fr_subtype = | |
12548 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12549 | return 1; | |
12550 | } | |
12551 | ||
12552 | /* If we are about to mark a frag as extended because the value | |
12553 | is precisely maxtiny + 1, then there is a chance of an | |
12554 | infinite loop as in the following code: | |
12555 | la $4,foo | |
12556 | .skip 1020 | |
12557 | .align 2 | |
12558 | foo: | |
12559 | In this case when the la is extended, foo is 0x3fc bytes | |
12560 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12561 | the la must be extended. To avoid this loop, we mark the | |
12562 | frag as extended if it was small, and is about to become | |
12563 | extended with a value of maxtiny + 1. */ | |
12564 | if (val == ((maxtiny + 1) << op->shift) | |
12565 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12566 | && sec == NULL) | |
12567 | { | |
12568 | fragp->fr_subtype = | |
12569 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12570 | return 1; | |
12571 | } | |
12572 | } | |
12573 | else if (symsec != absolute_section && sec != NULL) | |
12574 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12575 | ||
12576 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12577 | || val < (mintiny << op->shift) | |
12578 | || val > (maxtiny << op->shift)) | |
12579 | return 1; | |
12580 | else | |
12581 | return 0; | |
12582 | } | |
12583 | ||
4a6a3df4 AO |
12584 | /* Compute the length of a branch sequence, and adjust the |
12585 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12586 | worst-case length is computed, with UPDATE being used to indicate | |
12587 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12588 | branch is to be computed. */ | |
12589 | static int | |
17a2f251 | 12590 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12591 | { |
b34976b6 | 12592 | bfd_boolean toofar; |
4a6a3df4 AO |
12593 | int length; |
12594 | ||
12595 | if (fragp | |
12596 | && S_IS_DEFINED (fragp->fr_symbol) | |
12597 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12598 | { | |
12599 | addressT addr; | |
12600 | offsetT val; | |
12601 | ||
12602 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12603 | ||
12604 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12605 | ||
12606 | val -= addr; | |
12607 | ||
12608 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12609 | } | |
12610 | else if (fragp) | |
12611 | /* If the symbol is not defined or it's in a different segment, | |
12612 | assume the user knows what's going on and emit a short | |
12613 | branch. */ | |
b34976b6 | 12614 | toofar = FALSE; |
4a6a3df4 | 12615 | else |
b34976b6 | 12616 | toofar = TRUE; |
4a6a3df4 AO |
12617 | |
12618 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12619 | fragp->fr_subtype | |
af6ae2ad | 12620 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12621 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12622 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12623 | toofar); | |
12624 | ||
12625 | length = 4; | |
12626 | if (toofar) | |
12627 | { | |
12628 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12629 | length += 8; | |
12630 | ||
12631 | if (mips_pic != NO_PIC) | |
12632 | { | |
12633 | /* Additional space for PIC loading of target address. */ | |
12634 | length += 8; | |
12635 | if (mips_opts.isa == ISA_MIPS1) | |
12636 | /* Additional space for $at-stabilizing nop. */ | |
12637 | length += 4; | |
12638 | } | |
12639 | ||
12640 | /* If branch is conditional. */ | |
12641 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12642 | length += 8; | |
12643 | } | |
b34976b6 | 12644 | |
4a6a3df4 AO |
12645 | return length; |
12646 | } | |
12647 | ||
252b5132 RH |
12648 | /* Estimate the size of a frag before relaxing. Unless this is the |
12649 | mips16, we are not really relaxing here, and the final size is | |
12650 | encoded in the subtype information. For the mips16, we have to | |
12651 | decide whether we are using an extended opcode or not. */ | |
12652 | ||
252b5132 | 12653 | int |
17a2f251 | 12654 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12655 | { |
5919d012 | 12656 | int change; |
252b5132 | 12657 | |
4a6a3df4 AO |
12658 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12659 | { | |
12660 | ||
b34976b6 AM |
12661 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12662 | ||
4a6a3df4 AO |
12663 | return fragp->fr_var; |
12664 | } | |
12665 | ||
252b5132 | 12666 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12667 | /* We don't want to modify the EXTENDED bit here; it might get us |
12668 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12669 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12670 | |
12671 | if (mips_pic == NO_PIC) | |
5919d012 | 12672 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12673 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12674 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12675 | else |
12676 | abort (); | |
12677 | ||
12678 | if (change) | |
12679 | { | |
4d7206a2 | 12680 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12681 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12682 | } |
4d7206a2 RS |
12683 | else |
12684 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12685 | } |
12686 | ||
12687 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12688 | should be converted into a reloc against a section. */ |
252b5132 RH |
12689 | |
12690 | int | |
17a2f251 | 12691 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12692 | { |
de7e6852 RS |
12693 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12694 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12695 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12696 | return 0; | |
a161fe53 | 12697 | |
252b5132 RH |
12698 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12699 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12700 | return 0; | |
a161fe53 | 12701 | |
252b5132 RH |
12702 | if (fixp->fx_addsy == NULL) |
12703 | return 1; | |
a161fe53 | 12704 | |
de7e6852 RS |
12705 | /* If symbol SYM is in a mergeable section, relocations of the form |
12706 | SYM + 0 can usually be made section-relative. The mergeable data | |
12707 | is then identified by the section offset rather than by the symbol. | |
12708 | ||
12709 | However, if we're generating REL LO16 relocations, the offset is split | |
12710 | between the LO16 and parterning high part relocation. The linker will | |
12711 | need to recalculate the complete offset in order to correctly identify | |
12712 | the merge data. | |
12713 | ||
12714 | The linker has traditionally not looked for the parterning high part | |
12715 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12716 | placed anywhere. Rather than break backwards compatibility by changing | |
12717 | this, it seems better not to force the issue, and instead keep the | |
12718 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
12719 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
12720 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
12721 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
12722 | && HAVE_IN_PLACE_ADDENDS |
12723 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12724 | return 0; | |
12725 | ||
252b5132 | 12726 | #ifdef OBJ_ELF |
de7e6852 RS |
12727 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12728 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12729 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12730 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12731 | && fixp->fx_subsy == NULL) | |
12732 | return 0; | |
12733 | #endif | |
a161fe53 | 12734 | |
252b5132 RH |
12735 | return 1; |
12736 | } | |
12737 | ||
12738 | /* Translate internal representation of relocation info to BFD target | |
12739 | format. */ | |
12740 | ||
12741 | arelent ** | |
17a2f251 | 12742 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12743 | { |
12744 | static arelent *retval[4]; | |
12745 | arelent *reloc; | |
12746 | bfd_reloc_code_real_type code; | |
12747 | ||
4b0cff4e TS |
12748 | memset (retval, 0, sizeof(retval)); |
12749 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12750 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12751 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12752 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12753 | ||
3e722fb5 CD |
12754 | assert (! fixp->fx_pcrel); |
12755 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12756 | |
438c16b8 TS |
12757 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12758 | entry to be used in the relocation's section offset. */ | |
12759 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12760 | { |
12761 | reloc->address = reloc->addend; | |
12762 | reloc->addend = 0; | |
12763 | } | |
12764 | ||
252b5132 | 12765 | code = fixp->fx_r_type; |
252b5132 | 12766 | |
3e722fb5 CD |
12767 | /* To support a PC relative reloc, we used a Cygnus extension. |
12768 | We check for that here to make sure that we don't let such a | |
12769 | reloc escape normally. (FIXME: This was formerly used by | |
12770 | embedded-PIC support, but is now used by branch handling in | |
12771 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12772 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12773 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12774 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12775 | reloc->howto = NULL; |
12776 | else | |
12777 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12778 | ||
252b5132 RH |
12779 | if (reloc->howto == NULL) |
12780 | { | |
12781 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12782 | _("Can not represent %s relocation in this object file format"), | |
12783 | bfd_get_reloc_code_name (code)); | |
12784 | retval[0] = NULL; | |
12785 | } | |
12786 | ||
12787 | return retval; | |
12788 | } | |
12789 | ||
12790 | /* Relax a machine dependent frag. This returns the amount by which | |
12791 | the current size of the frag should change. */ | |
12792 | ||
12793 | int | |
17a2f251 | 12794 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12795 | { |
4a6a3df4 AO |
12796 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12797 | { | |
12798 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12799 | |
12800 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12801 | |
12802 | return fragp->fr_var - old_var; | |
12803 | } | |
12804 | ||
252b5132 RH |
12805 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12806 | return 0; | |
12807 | ||
c4e7957c | 12808 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12809 | { |
12810 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12811 | return 0; | |
12812 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12813 | return 2; | |
12814 | } | |
12815 | else | |
12816 | { | |
12817 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12818 | return 0; | |
12819 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12820 | return -2; | |
12821 | } | |
12822 | ||
12823 | return 0; | |
12824 | } | |
12825 | ||
12826 | /* Convert a machine dependent frag. */ | |
12827 | ||
12828 | void | |
17a2f251 | 12829 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12830 | { |
4a6a3df4 AO |
12831 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12832 | { | |
12833 | bfd_byte *buf; | |
12834 | unsigned long insn; | |
12835 | expressionS exp; | |
12836 | fixS *fixp; | |
b34976b6 | 12837 | |
4a6a3df4 AO |
12838 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12839 | ||
12840 | if (target_big_endian) | |
12841 | insn = bfd_getb32 (buf); | |
12842 | else | |
12843 | insn = bfd_getl32 (buf); | |
b34976b6 | 12844 | |
4a6a3df4 AO |
12845 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12846 | { | |
12847 | /* We generate a fixup instead of applying it right now | |
12848 | because, if there are linker relaxations, we're going to | |
12849 | need the relocations. */ | |
12850 | exp.X_op = O_symbol; | |
12851 | exp.X_add_symbol = fragp->fr_symbol; | |
12852 | exp.X_add_number = fragp->fr_offset; | |
12853 | ||
12854 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12855 | 4, &exp, 1, |
12856 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12857 | fixp->fx_file = fragp->fr_file; |
12858 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12859 | |
2132e3a3 | 12860 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12861 | buf += 4; |
12862 | } | |
12863 | else | |
12864 | { | |
12865 | int i; | |
12866 | ||
12867 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12868 | _("relaxed out-of-range branch into a jump")); | |
12869 | ||
12870 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12871 | goto uncond; | |
12872 | ||
12873 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12874 | { | |
12875 | /* Reverse the branch. */ | |
12876 | switch ((insn >> 28) & 0xf) | |
12877 | { | |
12878 | case 4: | |
12879 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12880 | have the condition reversed by tweaking a single | |
12881 | bit, and their opcodes all have 0x4???????. */ | |
12882 | assert ((insn & 0xf1000000) == 0x41000000); | |
12883 | insn ^= 0x00010000; | |
12884 | break; | |
12885 | ||
12886 | case 0: | |
12887 | /* bltz 0x04000000 bgez 0x04010000 | |
12888 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12889 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12890 | insn ^= 0x00010000; | |
12891 | break; | |
b34976b6 | 12892 | |
4a6a3df4 AO |
12893 | case 1: |
12894 | /* beq 0x10000000 bne 0x14000000 | |
12895 | blez 0x18000000 bgtz 0x1c000000 */ | |
12896 | insn ^= 0x04000000; | |
12897 | break; | |
12898 | ||
12899 | default: | |
12900 | abort (); | |
12901 | } | |
12902 | } | |
12903 | ||
12904 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12905 | { | |
12906 | /* Clear the and-link bit. */ | |
12907 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12908 | ||
12909 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12910 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12911 | insn &= ~0x00100000; | |
12912 | } | |
12913 | ||
12914 | /* Branch over the branch (if the branch was likely) or the | |
12915 | full jump (not likely case). Compute the offset from the | |
12916 | current instruction to branch to. */ | |
12917 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12918 | i = 16; | |
12919 | else | |
12920 | { | |
12921 | /* How many bytes in instructions we've already emitted? */ | |
12922 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12923 | /* How many bytes in instructions from here to the end? */ | |
12924 | i = fragp->fr_var - i; | |
12925 | } | |
12926 | /* Convert to instruction count. */ | |
12927 | i >>= 2; | |
12928 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12929 | i--; |
4a6a3df4 AO |
12930 | insn |= i; |
12931 | /* Branch over the jump. */ | |
2132e3a3 | 12932 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12933 | buf += 4; |
12934 | ||
12935 | /* Nop */ | |
2132e3a3 | 12936 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12937 | buf += 4; |
12938 | ||
12939 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12940 | { | |
12941 | /* beql $0, $0, 2f */ | |
12942 | insn = 0x50000000; | |
12943 | /* Compute the PC offset from the current instruction to | |
12944 | the end of the variable frag. */ | |
12945 | /* How many bytes in instructions we've already emitted? */ | |
12946 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12947 | /* How many bytes in instructions from here to the end? */ | |
12948 | i = fragp->fr_var - i; | |
12949 | /* Convert to instruction count. */ | |
12950 | i >>= 2; | |
12951 | /* Don't decrement i, because we want to branch over the | |
12952 | delay slot. */ | |
12953 | ||
12954 | insn |= i; | |
2132e3a3 | 12955 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12956 | buf += 4; |
12957 | ||
2132e3a3 | 12958 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12959 | buf += 4; |
12960 | } | |
12961 | ||
12962 | uncond: | |
12963 | if (mips_pic == NO_PIC) | |
12964 | { | |
12965 | /* j or jal. */ | |
12966 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12967 | ? 0x0c000000 : 0x08000000); | |
12968 | exp.X_op = O_symbol; | |
12969 | exp.X_add_symbol = fragp->fr_symbol; | |
12970 | exp.X_add_number = fragp->fr_offset; | |
12971 | ||
12972 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12973 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
12974 | fixp->fx_file = fragp->fr_file; | |
12975 | fixp->fx_line = fragp->fr_line; | |
12976 | ||
2132e3a3 | 12977 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12978 | buf += 4; |
12979 | } | |
12980 | else | |
12981 | { | |
12982 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
12983 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
12984 | exp.X_op = O_symbol; | |
12985 | exp.X_add_symbol = fragp->fr_symbol; | |
12986 | exp.X_add_number = fragp->fr_offset; | |
12987 | ||
12988 | if (fragp->fr_offset) | |
12989 | { | |
12990 | exp.X_add_symbol = make_expr_symbol (&exp); | |
12991 | exp.X_add_number = 0; | |
12992 | } | |
12993 | ||
12994 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12995 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
12996 | fixp->fx_file = fragp->fr_file; | |
12997 | fixp->fx_line = fragp->fr_line; | |
12998 | ||
2132e3a3 | 12999 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13000 | buf += 4; |
b34976b6 | 13001 | |
4a6a3df4 AO |
13002 | if (mips_opts.isa == ISA_MIPS1) |
13003 | { | |
13004 | /* nop */ | |
2132e3a3 | 13005 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13006 | buf += 4; |
13007 | } | |
13008 | ||
13009 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13010 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13011 | ||
13012 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13013 | 4, &exp, 0, BFD_RELOC_LO16); | |
13014 | fixp->fx_file = fragp->fr_file; | |
13015 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13016 | |
2132e3a3 | 13017 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13018 | buf += 4; |
13019 | ||
13020 | /* j(al)r $at. */ | |
13021 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13022 | insn = 0x0020f809; | |
13023 | else | |
13024 | insn = 0x00200008; | |
13025 | ||
2132e3a3 | 13026 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13027 | buf += 4; |
13028 | } | |
13029 | } | |
13030 | ||
13031 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13032 | + fragp->fr_fix + fragp->fr_var); | |
13033 | ||
13034 | fragp->fr_fix += fragp->fr_var; | |
13035 | ||
13036 | return; | |
13037 | } | |
13038 | ||
252b5132 RH |
13039 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13040 | { | |
13041 | int type; | |
13042 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13043 | bfd_boolean small, ext; |
252b5132 RH |
13044 | offsetT val; |
13045 | bfd_byte *buf; | |
13046 | unsigned long insn; | |
b34976b6 | 13047 | bfd_boolean use_extend; |
252b5132 RH |
13048 | unsigned short extend; |
13049 | ||
13050 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13051 | op = mips16_immed_operands; | |
13052 | while (op->type != type) | |
13053 | ++op; | |
13054 | ||
13055 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13056 | { | |
b34976b6 AM |
13057 | small = FALSE; |
13058 | ext = TRUE; | |
252b5132 RH |
13059 | } |
13060 | else | |
13061 | { | |
b34976b6 AM |
13062 | small = TRUE; |
13063 | ext = FALSE; | |
252b5132 RH |
13064 | } |
13065 | ||
6386f3a7 | 13066 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13067 | val = S_GET_VALUE (fragp->fr_symbol); |
13068 | if (op->pcrel) | |
13069 | { | |
13070 | addressT addr; | |
13071 | ||
13072 | addr = fragp->fr_address + fragp->fr_fix; | |
13073 | ||
13074 | /* The rules for the base address of a PC relative reloc are | |
13075 | complicated; see mips16_extended_frag. */ | |
13076 | if (type == 'p' || type == 'q') | |
13077 | { | |
13078 | addr += 2; | |
13079 | if (ext) | |
13080 | addr += 2; | |
13081 | /* Ignore the low bit in the target, since it will be | |
13082 | set for a text label. */ | |
13083 | if ((val & 1) != 0) | |
13084 | --val; | |
13085 | } | |
13086 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13087 | addr -= 4; | |
13088 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13089 | addr -= 2; | |
13090 | ||
13091 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13092 | val -= addr; | |
13093 | ||
13094 | /* Make sure the section winds up with the alignment we have | |
13095 | assumed. */ | |
13096 | if (op->shift > 0) | |
13097 | record_alignment (asec, op->shift); | |
13098 | } | |
13099 | ||
13100 | if (ext | |
13101 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13102 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13103 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13104 | _("extended instruction in delay slot")); | |
13105 | ||
13106 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13107 | ||
13108 | if (target_big_endian) | |
13109 | insn = bfd_getb16 (buf); | |
13110 | else | |
13111 | insn = bfd_getl16 (buf); | |
13112 | ||
13113 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13114 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13115 | small, ext, &insn, &use_extend, &extend); | |
13116 | ||
13117 | if (use_extend) | |
13118 | { | |
2132e3a3 | 13119 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13120 | fragp->fr_fix += 2; |
13121 | buf += 2; | |
13122 | } | |
13123 | ||
2132e3a3 | 13124 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13125 | fragp->fr_fix += 2; |
13126 | buf += 2; | |
13127 | } | |
13128 | else | |
13129 | { | |
4d7206a2 RS |
13130 | int first, second; |
13131 | fixS *fixp; | |
252b5132 | 13132 | |
4d7206a2 RS |
13133 | first = RELAX_FIRST (fragp->fr_subtype); |
13134 | second = RELAX_SECOND (fragp->fr_subtype); | |
13135 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13136 | |
584892a6 RS |
13137 | /* Possibly emit a warning if we've chosen the longer option. */ |
13138 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13139 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13140 | { | |
13141 | const char *msg = macro_warning (fragp->fr_subtype); | |
13142 | if (msg != 0) | |
13143 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13144 | } | |
13145 | ||
4d7206a2 RS |
13146 | /* Go through all the fixups for the first sequence. Disable them |
13147 | (by marking them as done) if we're going to use the second | |
13148 | sequence instead. */ | |
13149 | while (fixp | |
13150 | && fixp->fx_frag == fragp | |
13151 | && fixp->fx_where < fragp->fr_fix - second) | |
13152 | { | |
13153 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13154 | fixp->fx_done = 1; | |
13155 | fixp = fixp->fx_next; | |
13156 | } | |
252b5132 | 13157 | |
4d7206a2 RS |
13158 | /* Go through the fixups for the second sequence. Disable them if |
13159 | we're going to use the first sequence, otherwise adjust their | |
13160 | addresses to account for the relaxation. */ | |
13161 | while (fixp && fixp->fx_frag == fragp) | |
13162 | { | |
13163 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13164 | fixp->fx_where -= first; | |
13165 | else | |
13166 | fixp->fx_done = 1; | |
13167 | fixp = fixp->fx_next; | |
13168 | } | |
13169 | ||
13170 | /* Now modify the frag contents. */ | |
13171 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13172 | { | |
13173 | char *start; | |
13174 | ||
13175 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13176 | memmove (start, start + first, second); | |
13177 | fragp->fr_fix -= first; | |
13178 | } | |
13179 | else | |
13180 | fragp->fr_fix -= second; | |
252b5132 RH |
13181 | } |
13182 | } | |
13183 | ||
13184 | #ifdef OBJ_ELF | |
13185 | ||
13186 | /* This function is called after the relocs have been generated. | |
13187 | We've been storing mips16 text labels as odd. Here we convert them | |
13188 | back to even for the convenience of the debugger. */ | |
13189 | ||
13190 | void | |
17a2f251 | 13191 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13192 | { |
13193 | asymbol **syms; | |
13194 | unsigned int count, i; | |
13195 | ||
13196 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13197 | return; | |
13198 | ||
13199 | syms = bfd_get_outsymbols (stdoutput); | |
13200 | count = bfd_get_symcount (stdoutput); | |
13201 | for (i = 0; i < count; i++, syms++) | |
13202 | { | |
13203 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13204 | && ((*syms)->value & 1) != 0) | |
13205 | { | |
13206 | (*syms)->value &= ~1; | |
13207 | /* If the symbol has an odd size, it was probably computed | |
13208 | incorrectly, so adjust that as well. */ | |
13209 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13210 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13211 | } | |
13212 | } | |
13213 | } | |
13214 | ||
13215 | #endif | |
13216 | ||
13217 | /* This function is called whenever a label is defined. It is used | |
13218 | when handling branch delays; if a branch has a label, we assume we | |
13219 | can not move it. */ | |
13220 | ||
13221 | void | |
17a2f251 | 13222 | mips_define_label (symbolS *sym) |
252b5132 RH |
13223 | { |
13224 | struct insn_label_list *l; | |
13225 | ||
13226 | if (free_insn_labels == NULL) | |
13227 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13228 | else | |
13229 | { | |
13230 | l = free_insn_labels; | |
13231 | free_insn_labels = l->next; | |
13232 | } | |
13233 | ||
13234 | l->label = sym; | |
13235 | l->next = insn_labels; | |
13236 | insn_labels = l; | |
13237 | } | |
13238 | \f | |
13239 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13240 | ||
13241 | /* Some special processing for a MIPS ELF file. */ | |
13242 | ||
13243 | void | |
17a2f251 | 13244 | mips_elf_final_processing (void) |
252b5132 RH |
13245 | { |
13246 | /* Write out the register information. */ | |
316f5878 | 13247 | if (mips_abi != N64_ABI) |
252b5132 RH |
13248 | { |
13249 | Elf32_RegInfo s; | |
13250 | ||
13251 | s.ri_gprmask = mips_gprmask; | |
13252 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13253 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13254 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13255 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13256 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13257 | ||
13258 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13259 | ((Elf32_External_RegInfo *) | |
13260 | mips_regmask_frag)); | |
13261 | } | |
13262 | else | |
13263 | { | |
13264 | Elf64_Internal_RegInfo s; | |
13265 | ||
13266 | s.ri_gprmask = mips_gprmask; | |
13267 | s.ri_pad = 0; | |
13268 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13269 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13270 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13271 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13272 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13273 | ||
13274 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13275 | ((Elf64_External_RegInfo *) | |
13276 | mips_regmask_frag)); | |
13277 | } | |
13278 | ||
13279 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13280 | sort of BFD interface for this. */ | |
13281 | if (mips_any_noreorder) | |
13282 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13283 | if (mips_pic != NO_PIC) | |
143d77c5 | 13284 | { |
252b5132 | 13285 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13286 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13287 | } | |
13288 | if (mips_abicalls) | |
13289 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13290 | |
98d3f06f | 13291 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13292 | if (file_ase_mips16) |
13293 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13294 | #if 0 /* XXX FIXME */ |
13295 | if (file_ase_mips3d) | |
13296 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13297 | #endif | |
deec1734 CD |
13298 | if (file_ase_mdmx) |
13299 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13300 | |
bdaaa2e1 | 13301 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13302 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13303 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13304 | else if (mips_abi == O64_ABI) |
252b5132 | 13305 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13306 | else if (mips_abi == EABI_ABI) |
252b5132 | 13307 | { |
316f5878 | 13308 | if (!file_mips_gp32) |
252b5132 RH |
13309 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13310 | else | |
13311 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13312 | } | |
316f5878 | 13313 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13314 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13315 | ||
c9914766 | 13316 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13317 | |
13318 | if (mips_32bitmode) | |
13319 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13320 | } | |
13321 | ||
13322 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13323 | \f | |
beae10d5 | 13324 | typedef struct proc { |
9b2f1d35 EC |
13325 | symbolS *func_sym; |
13326 | symbolS *func_end_sym; | |
beae10d5 KH |
13327 | unsigned long reg_mask; |
13328 | unsigned long reg_offset; | |
13329 | unsigned long fpreg_mask; | |
13330 | unsigned long fpreg_offset; | |
13331 | unsigned long frame_offset; | |
13332 | unsigned long frame_reg; | |
13333 | unsigned long pc_reg; | |
13334 | } procS; | |
252b5132 RH |
13335 | |
13336 | static procS cur_proc; | |
13337 | static procS *cur_proc_ptr; | |
13338 | static int numprocs; | |
13339 | ||
0a9ef439 | 13340 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13341 | |
0a9ef439 | 13342 | void |
17a2f251 | 13343 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13344 | { |
0a9ef439 RH |
13345 | if (fragp->fr_type != rs_align_code) |
13346 | return; | |
13347 | ||
13348 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13349 | { |
13350 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13351 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13352 | ||
0a9ef439 RH |
13353 | int bytes; |
13354 | char *p; | |
a19d8eb0 | 13355 | |
0a9ef439 RH |
13356 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13357 | p = fragp->fr_literal + fragp->fr_fix; | |
13358 | ||
13359 | if (bytes & 1) | |
13360 | { | |
13361 | *p++ = 0; | |
f9419b05 | 13362 | fragp->fr_fix++; |
0a9ef439 RH |
13363 | } |
13364 | ||
13365 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13366 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13367 | } |
13368 | ||
0a9ef439 | 13369 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13370 | } |
13371 | ||
252b5132 | 13372 | static void |
17a2f251 | 13373 | md_obj_begin (void) |
252b5132 RH |
13374 | { |
13375 | } | |
13376 | ||
13377 | static void | |
17a2f251 | 13378 | md_obj_end (void) |
252b5132 RH |
13379 | { |
13380 | /* check for premature end, nesting errors, etc */ | |
13381 | if (cur_proc_ptr) | |
9a41af64 | 13382 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13383 | } |
13384 | ||
13385 | static long | |
17a2f251 | 13386 | get_number (void) |
252b5132 RH |
13387 | { |
13388 | int negative = 0; | |
13389 | long val = 0; | |
13390 | ||
13391 | if (*input_line_pointer == '-') | |
13392 | { | |
13393 | ++input_line_pointer; | |
13394 | negative = 1; | |
13395 | } | |
3882b010 | 13396 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13397 | as_bad (_("expected simple number")); |
252b5132 RH |
13398 | if (input_line_pointer[0] == '0') |
13399 | { | |
13400 | if (input_line_pointer[1] == 'x') | |
13401 | { | |
13402 | input_line_pointer += 2; | |
3882b010 | 13403 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13404 | { |
13405 | val <<= 4; | |
13406 | val |= hex_value (*input_line_pointer++); | |
13407 | } | |
13408 | return negative ? -val : val; | |
13409 | } | |
13410 | else | |
13411 | { | |
13412 | ++input_line_pointer; | |
3882b010 | 13413 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13414 | { |
13415 | val <<= 3; | |
13416 | val |= *input_line_pointer++ - '0'; | |
13417 | } | |
13418 | return negative ? -val : val; | |
13419 | } | |
13420 | } | |
3882b010 | 13421 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13422 | { |
13423 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13424 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13425 | as_warn (_("invalid number")); |
252b5132 RH |
13426 | return -1; |
13427 | } | |
3882b010 | 13428 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13429 | { |
13430 | val *= 10; | |
13431 | val += *input_line_pointer++ - '0'; | |
13432 | } | |
13433 | return negative ? -val : val; | |
13434 | } | |
13435 | ||
13436 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13437 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13438 | case .file implies DWARF-2. */ | |
13439 | ||
13440 | static void | |
17a2f251 | 13441 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13442 | { |
ecb4347a DJ |
13443 | static int first_file_directive = 0; |
13444 | ||
c5dd6aab DJ |
13445 | if (ECOFF_DEBUGGING) |
13446 | { | |
13447 | get_number (); | |
13448 | s_app_file (0); | |
13449 | } | |
13450 | else | |
ecb4347a DJ |
13451 | { |
13452 | char *filename; | |
13453 | ||
13454 | filename = dwarf2_directive_file (0); | |
13455 | ||
13456 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13457 | directive even for stabs output. Make sure that this | |
13458 | ".file" is handled. Note that you need a version of GCC | |
13459 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13460 | if (filename != NULL && ! first_file_directive) | |
13461 | { | |
13462 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13463 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13464 | } |
13465 | first_file_directive = 1; | |
13466 | } | |
c5dd6aab DJ |
13467 | } |
13468 | ||
13469 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13470 | |
13471 | static void | |
17a2f251 | 13472 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13473 | { |
c5dd6aab DJ |
13474 | if (!ECOFF_DEBUGGING) |
13475 | dwarf2_directive_loc (0); | |
252b5132 RH |
13476 | } |
13477 | ||
252b5132 RH |
13478 | /* The .end directive. */ |
13479 | ||
13480 | static void | |
17a2f251 | 13481 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13482 | { |
13483 | symbolS *p; | |
252b5132 | 13484 | |
7a621144 DJ |
13485 | /* Following functions need their own .frame and .cprestore directives. */ |
13486 | mips_frame_reg_valid = 0; | |
13487 | mips_cprestore_valid = 0; | |
13488 | ||
252b5132 RH |
13489 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13490 | { | |
13491 | p = get_symbol (); | |
13492 | demand_empty_rest_of_line (); | |
13493 | } | |
13494 | else | |
13495 | p = NULL; | |
13496 | ||
14949570 | 13497 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13498 | as_warn (_(".end not in text section")); |
13499 | ||
13500 | if (!cur_proc_ptr) | |
13501 | { | |
13502 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13503 | demand_empty_rest_of_line (); | |
13504 | return; | |
13505 | } | |
13506 | ||
13507 | if (p != NULL) | |
13508 | { | |
13509 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13510 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13511 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13512 | |
13513 | if (debug_type == DEBUG_STABS) | |
13514 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13515 | S_GET_NAME (p)); | |
252b5132 RH |
13516 | } |
13517 | else | |
13518 | as_warn (_(".end directive missing or unknown symbol")); | |
13519 | ||
2132e3a3 | 13520 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13521 | /* Create an expression to calculate the size of the function. */ |
13522 | if (p && cur_proc_ptr) | |
13523 | { | |
13524 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13525 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13526 | ||
13527 | obj->size = exp; | |
13528 | exp->X_op = O_subtract; | |
13529 | exp->X_add_symbol = symbol_temp_new_now (); | |
13530 | exp->X_op_symbol = p; | |
13531 | exp->X_add_number = 0; | |
13532 | ||
13533 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13534 | } | |
13535 | ||
ecb4347a | 13536 | /* Generate a .pdr section. */ |
dcd410fe RO |
13537 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13538 | && mips_flag_pdr) | |
ecb4347a DJ |
13539 | { |
13540 | segT saved_seg = now_seg; | |
13541 | subsegT saved_subseg = now_subseg; | |
13542 | valueT dot; | |
13543 | expressionS exp; | |
13544 | char *fragp; | |
252b5132 | 13545 | |
ecb4347a | 13546 | dot = frag_now_fix (); |
252b5132 RH |
13547 | |
13548 | #ifdef md_flush_pending_output | |
ecb4347a | 13549 | md_flush_pending_output (); |
252b5132 RH |
13550 | #endif |
13551 | ||
ecb4347a DJ |
13552 | assert (pdr_seg); |
13553 | subseg_set (pdr_seg, 0); | |
252b5132 | 13554 | |
ecb4347a DJ |
13555 | /* Write the symbol. */ |
13556 | exp.X_op = O_symbol; | |
13557 | exp.X_add_symbol = p; | |
13558 | exp.X_add_number = 0; | |
13559 | emit_expr (&exp, 4); | |
252b5132 | 13560 | |
ecb4347a | 13561 | fragp = frag_more (7 * 4); |
252b5132 | 13562 | |
17a2f251 TS |
13563 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13564 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13565 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13566 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13567 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13568 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13569 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13570 | |
ecb4347a DJ |
13571 | subseg_set (saved_seg, saved_subseg); |
13572 | } | |
13573 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13574 | |
13575 | cur_proc_ptr = NULL; | |
13576 | } | |
13577 | ||
13578 | /* The .aent and .ent directives. */ | |
13579 | ||
13580 | static void | |
17a2f251 | 13581 | s_mips_ent (int aent) |
252b5132 | 13582 | { |
252b5132 | 13583 | symbolS *symbolP; |
252b5132 RH |
13584 | |
13585 | symbolP = get_symbol (); | |
13586 | if (*input_line_pointer == ',') | |
f9419b05 | 13587 | ++input_line_pointer; |
252b5132 | 13588 | SKIP_WHITESPACE (); |
3882b010 | 13589 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13590 | || *input_line_pointer == '-') |
874e8986 | 13591 | get_number (); |
252b5132 | 13592 | |
14949570 | 13593 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13594 | as_warn (_(".ent or .aent not in text section.")); |
13595 | ||
13596 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13597 | as_warn (_("missing .end")); |
252b5132 RH |
13598 | |
13599 | if (!aent) | |
13600 | { | |
7a621144 DJ |
13601 | /* This function needs its own .frame and .cprestore directives. */ |
13602 | mips_frame_reg_valid = 0; | |
13603 | mips_cprestore_valid = 0; | |
13604 | ||
252b5132 RH |
13605 | cur_proc_ptr = &cur_proc; |
13606 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13607 | ||
9b2f1d35 | 13608 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13609 | |
49309057 | 13610 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13611 | |
f9419b05 | 13612 | ++numprocs; |
ecb4347a DJ |
13613 | |
13614 | if (debug_type == DEBUG_STABS) | |
13615 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13616 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13617 | } |
13618 | ||
13619 | demand_empty_rest_of_line (); | |
13620 | } | |
13621 | ||
13622 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13623 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13624 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13625 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13626 | symbol table (in the mdebug section). */ |
13627 | ||
13628 | static void | |
17a2f251 | 13629 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13630 | { |
ecb4347a DJ |
13631 | #ifdef OBJ_ELF |
13632 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13633 | { | |
13634 | long val; | |
252b5132 | 13635 | |
ecb4347a DJ |
13636 | if (cur_proc_ptr == (procS *) NULL) |
13637 | { | |
13638 | as_warn (_(".frame outside of .ent")); | |
13639 | demand_empty_rest_of_line (); | |
13640 | return; | |
13641 | } | |
252b5132 | 13642 | |
ecb4347a DJ |
13643 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13644 | ||
13645 | SKIP_WHITESPACE (); | |
13646 | if (*input_line_pointer++ != ',' | |
13647 | || get_absolute_expression_and_terminator (&val) != ',') | |
13648 | { | |
13649 | as_warn (_("Bad .frame directive")); | |
13650 | --input_line_pointer; | |
13651 | demand_empty_rest_of_line (); | |
13652 | return; | |
13653 | } | |
252b5132 | 13654 | |
ecb4347a DJ |
13655 | cur_proc_ptr->frame_offset = val; |
13656 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13657 | |
252b5132 | 13658 | demand_empty_rest_of_line (); |
252b5132 | 13659 | } |
ecb4347a DJ |
13660 | else |
13661 | #endif /* OBJ_ELF */ | |
13662 | s_ignore (ignore); | |
252b5132 RH |
13663 | } |
13664 | ||
bdaaa2e1 KH |
13665 | /* The .fmask and .mask directives. If the mdebug section is present |
13666 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13667 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13668 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13669 | make reference to the ecoff symbol table (in the mdebug section). */ |
13670 | ||
13671 | static void | |
17a2f251 | 13672 | s_mips_mask (int reg_type) |
252b5132 | 13673 | { |
ecb4347a DJ |
13674 | #ifdef OBJ_ELF |
13675 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13676 | { |
ecb4347a | 13677 | long mask, off; |
252b5132 | 13678 | |
ecb4347a DJ |
13679 | if (cur_proc_ptr == (procS *) NULL) |
13680 | { | |
13681 | as_warn (_(".mask/.fmask outside of .ent")); | |
13682 | demand_empty_rest_of_line (); | |
13683 | return; | |
13684 | } | |
252b5132 | 13685 | |
ecb4347a DJ |
13686 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13687 | { | |
13688 | as_warn (_("Bad .mask/.fmask directive")); | |
13689 | --input_line_pointer; | |
13690 | demand_empty_rest_of_line (); | |
13691 | return; | |
13692 | } | |
252b5132 | 13693 | |
ecb4347a DJ |
13694 | off = get_absolute_expression (); |
13695 | ||
13696 | if (reg_type == 'F') | |
13697 | { | |
13698 | cur_proc_ptr->fpreg_mask = mask; | |
13699 | cur_proc_ptr->fpreg_offset = off; | |
13700 | } | |
13701 | else | |
13702 | { | |
13703 | cur_proc_ptr->reg_mask = mask; | |
13704 | cur_proc_ptr->reg_offset = off; | |
13705 | } | |
13706 | ||
13707 | demand_empty_rest_of_line (); | |
252b5132 RH |
13708 | } |
13709 | else | |
ecb4347a DJ |
13710 | #endif /* OBJ_ELF */ |
13711 | s_ignore (reg_type); | |
252b5132 RH |
13712 | } |
13713 | ||
316f5878 RS |
13714 | /* A table describing all the processors gas knows about. Names are |
13715 | matched in the order listed. | |
e7af610e | 13716 | |
316f5878 RS |
13717 | To ease comparison, please keep this table in the same order as |
13718 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13719 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13720 | { | |
316f5878 RS |
13721 | /* Entries for generic ISAs */ |
13722 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13723 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13724 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13725 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13726 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13727 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13728 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13729 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13730 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13731 | |
13732 | /* MIPS I */ | |
13733 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13734 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13735 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13736 | ||
13737 | /* MIPS II */ | |
13738 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13739 | ||
13740 | /* MIPS III */ | |
13741 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13742 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13743 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13744 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13745 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13746 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13747 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13748 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13749 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13750 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13751 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13752 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13753 | ||
13754 | /* MIPS IV */ | |
13755 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13756 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13757 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13758 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13759 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13760 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13761 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13762 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13763 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13764 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13765 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13766 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13767 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13768 | |
13769 | /* MIPS 32 */ | |
fef14a42 | 13770 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13771 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13772 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13773 | |
316f5878 RS |
13774 | /* MIPS 64 */ |
13775 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13776 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13777 | |
c7a23324 | 13778 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13779 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13780 | |
316f5878 RS |
13781 | /* End marker */ |
13782 | { NULL, 0, 0, 0 } | |
13783 | }; | |
e7af610e | 13784 | |
84ea6cf2 | 13785 | |
316f5878 RS |
13786 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13787 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13788 | |
316f5878 | 13789 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13790 | |
b34976b6 | 13791 | static bfd_boolean |
17a2f251 | 13792 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13793 | { |
13794 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13795 | given++, canonical++; | |
13796 | ||
13797 | return ((*given == 0 && *canonical == 0) | |
13798 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13799 | } | |
13800 | ||
13801 | ||
13802 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13803 | CPU name. We've traditionally allowed a lot of variation here. | |
13804 | ||
13805 | Note: this function is shared between GCC and GAS. */ | |
13806 | ||
b34976b6 | 13807 | static bfd_boolean |
17a2f251 | 13808 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13809 | { |
13810 | /* First see if the name matches exactly, or with a final "000" | |
13811 | turned into "k". */ | |
13812 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13813 | return TRUE; |
316f5878 RS |
13814 | |
13815 | /* If not, try comparing based on numerical designation alone. | |
13816 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13817 | if (TOLOWER (*given) == 'r') | |
13818 | given++; | |
13819 | if (!ISDIGIT (*given)) | |
b34976b6 | 13820 | return FALSE; |
316f5878 RS |
13821 | |
13822 | /* Skip over some well-known prefixes in the canonical name, | |
13823 | hoping to find a number there too. */ | |
13824 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13825 | canonical += 2; | |
13826 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13827 | canonical += 2; | |
13828 | else if (TOLOWER (canonical[0]) == 'r') | |
13829 | canonical += 1; | |
13830 | ||
13831 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13832 | } | |
13833 | ||
13834 | ||
13835 | /* Parse an option that takes the name of a processor as its argument. | |
13836 | OPTION is the name of the option and CPU_STRING is the argument. | |
13837 | Return the corresponding processor enumeration if the CPU_STRING is | |
13838 | recognized, otherwise report an error and return null. | |
13839 | ||
13840 | A similar function exists in GCC. */ | |
e7af610e NC |
13841 | |
13842 | static const struct mips_cpu_info * | |
17a2f251 | 13843 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13844 | { |
316f5878 | 13845 | const struct mips_cpu_info *p; |
e7af610e | 13846 | |
316f5878 RS |
13847 | /* 'from-abi' selects the most compatible architecture for the given |
13848 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13849 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13850 | version. Look first at the -mgp options, if given, otherwise base | |
13851 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13852 | |
316f5878 RS |
13853 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13854 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13855 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13856 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13857 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13858 | { | |
13859 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13860 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13861 | ||
13862 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13863 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13864 | ||
13865 | if (file_mips_gp32 >= 0) | |
13866 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13867 | ||
13868 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13869 | ? ISA_MIPS3 | |
13870 | : ISA_MIPS1); | |
13871 | } | |
13872 | ||
13873 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13874 | if (strcasecmp (cpu_string, "default") == 0) | |
13875 | return 0; | |
13876 | ||
13877 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13878 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13879 | return p; | |
13880 | ||
13881 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13882 | return 0; | |
e7af610e NC |
13883 | } |
13884 | ||
316f5878 RS |
13885 | /* Return the canonical processor information for ISA (a member of the |
13886 | ISA_MIPS* enumeration). */ | |
13887 | ||
e7af610e | 13888 | static const struct mips_cpu_info * |
17a2f251 | 13889 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13890 | { |
13891 | int i; | |
13892 | ||
13893 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13894 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13895 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13896 | return (&mips_cpu_info_table[i]); |
13897 | ||
e972090a | 13898 | return NULL; |
e7af610e | 13899 | } |
fef14a42 TS |
13900 | |
13901 | static const struct mips_cpu_info * | |
17a2f251 | 13902 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13903 | { |
13904 | int i; | |
13905 | ||
13906 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13907 | if (arch == mips_cpu_info_table[i].cpu) | |
13908 | return (&mips_cpu_info_table[i]); | |
13909 | ||
13910 | return NULL; | |
13911 | } | |
316f5878 RS |
13912 | \f |
13913 | static void | |
17a2f251 | 13914 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13915 | { |
13916 | if (*first_p) | |
13917 | { | |
13918 | fprintf (stream, "%24s", ""); | |
13919 | *col_p = 24; | |
13920 | } | |
13921 | else | |
13922 | { | |
13923 | fprintf (stream, ", "); | |
13924 | *col_p += 2; | |
13925 | } | |
e7af610e | 13926 | |
316f5878 RS |
13927 | if (*col_p + strlen (string) > 72) |
13928 | { | |
13929 | fprintf (stream, "\n%24s", ""); | |
13930 | *col_p = 24; | |
13931 | } | |
13932 | ||
13933 | fprintf (stream, "%s", string); | |
13934 | *col_p += strlen (string); | |
13935 | ||
13936 | *first_p = 0; | |
13937 | } | |
13938 | ||
13939 | void | |
17a2f251 | 13940 | md_show_usage (FILE *stream) |
e7af610e | 13941 | { |
316f5878 RS |
13942 | int column, first; |
13943 | size_t i; | |
13944 | ||
13945 | fprintf (stream, _("\ | |
13946 | MIPS options:\n\ | |
316f5878 RS |
13947 | -EB generate big endian output\n\ |
13948 | -EL generate little endian output\n\ | |
13949 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13950 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13951 | implicitly with the gp register [default 8]\n")); | |
13952 | fprintf (stream, _("\ | |
13953 | -mips1 generate MIPS ISA I instructions\n\ | |
13954 | -mips2 generate MIPS ISA II instructions\n\ | |
13955 | -mips3 generate MIPS ISA III instructions\n\ | |
13956 | -mips4 generate MIPS ISA IV instructions\n\ | |
13957 | -mips5 generate MIPS ISA V instructions\n\ | |
13958 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13959 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13960 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13961 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13962 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13963 | ||
13964 | first = 1; | |
e7af610e NC |
13965 | |
13966 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13967 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13968 | show (stream, "from-abi", &column, &first); | |
13969 | fputc ('\n', stream); | |
e7af610e | 13970 | |
316f5878 RS |
13971 | fprintf (stream, _("\ |
13972 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13973 | -no-mCPU don't generate code specific to CPU.\n\ | |
13974 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13975 | ||
13976 | first = 1; | |
13977 | ||
13978 | show (stream, "3900", &column, &first); | |
13979 | show (stream, "4010", &column, &first); | |
13980 | show (stream, "4100", &column, &first); | |
13981 | show (stream, "4650", &column, &first); | |
13982 | fputc ('\n', stream); | |
13983 | ||
13984 | fprintf (stream, _("\ | |
13985 | -mips16 generate mips16 instructions\n\ | |
13986 | -no-mips16 do not generate mips16 instructions\n")); | |
13987 | fprintf (stream, _("\ | |
d766e8ec | 13988 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 13989 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
13990 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
13991 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
13992 | -mno-shared optimize output for executables\n\ |
13993 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
13994 | -O0 remove unneeded NOPs, do not swap branches\n\ |
13995 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
13996 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
13997 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
13998 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
13999 | #ifdef OBJ_ELF | |
14000 | fprintf (stream, _("\ | |
14001 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14002 | -non_shared do not generate position independent code\n\ | |
14003 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14004 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14005 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14006 | non-shared code\n\ | |
316f5878 RS |
14007 | -mabi=ABI create ABI conformant object file for:\n")); |
14008 | ||
14009 | first = 1; | |
14010 | ||
14011 | show (stream, "32", &column, &first); | |
14012 | show (stream, "o64", &column, &first); | |
14013 | show (stream, "n32", &column, &first); | |
14014 | show (stream, "64", &column, &first); | |
14015 | show (stream, "eabi", &column, &first); | |
14016 | ||
14017 | fputc ('\n', stream); | |
14018 | ||
14019 | fprintf (stream, _("\ | |
14020 | -32 create o32 ABI object file (default)\n\ | |
14021 | -n32 create n32 ABI object file\n\ | |
14022 | -64 create 64 ABI object file\n")); | |
14023 | #endif | |
e7af610e | 14024 | } |
14e777e0 KB |
14025 | |
14026 | enum dwarf2_format | |
17a2f251 | 14027 | mips_dwarf2_format (void) |
14e777e0 KB |
14028 | { |
14029 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14030 | { |
14031 | #ifdef TE_IRIX | |
14032 | return dwarf2_format_64bit_irix; | |
14033 | #else | |
14034 | return dwarf2_format_64bit; | |
14035 | #endif | |
14036 | } | |
14e777e0 KB |
14037 | else |
14038 | return dwarf2_format_32bit; | |
14039 | } | |
73369e65 EC |
14040 | |
14041 | int | |
14042 | mips_dwarf2_addr_size (void) | |
14043 | { | |
14044 | if (mips_abi == N64_ABI) | |
14045 | return 8; | |
73369e65 EC |
14046 | else |
14047 | return 4; | |
14048 | } | |
5862107c EC |
14049 | |
14050 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14051 | void | |
14052 | mips_cfi_frame_initial_instructions (void) | |
14053 | { | |
14054 | cfi_add_CFA_def_cfa_register (SP); | |
14055 | } | |
14056 |