Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
50 | #undef OBJ_PROCESS_STAB | |
51 | #undef OUTPUT_FLAVOR | |
52 | #undef S_GET_ALIGN | |
53 | #undef S_GET_SIZE | |
54 | #undef S_SET_ALIGN | |
55 | #undef S_SET_SIZE | |
56 | #undef TARGET_SYMBOL_FIELDS | |
57 | #undef obj_frob_file | |
cc5703cd | 58 | #undef obj_frob_file_after_relocs |
739708fa KR |
59 | #undef obj_frob_symbol |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | ||
63 | #include "obj-elf.h" | |
64 | /* Fix any of them that we actually care about. */ | |
65 | #undef OUTPUT_FLAVOR | |
66 | #define OUTPUT_FLAVOR mips_output_flavor() | |
67 | #endif | |
68 | ||
69 | #if defined (OBJ_ELF) | |
f2a663d3 | 70 | #include "elf/mips.h" |
1dc1e798 | 71 | #endif |
f2a663d3 | 72 | |
739708fa | 73 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 74 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
75 | #define ECOFF_DEBUGGING 0 |
76 | #endif | |
77 | ||
22ba90ce ILT |
78 | #include "ecoff.h" |
79 | ||
a8aed9dd | 80 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 81 | static char *mips_regmask_frag; |
a8aed9dd | 82 | #endif |
f2a663d3 | 83 | |
3d3c5039 | 84 | #define AT 1 |
cc5703cd | 85 | #define TREG 24 |
9226253a | 86 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
87 | #define KT0 26 |
88 | #define KT1 27 | |
670a50eb | 89 | #define GP 28 |
9226253a ILT |
90 | #define SP 29 |
91 | #define FP 30 | |
3d3c5039 ILT |
92 | #define RA 31 |
93 | ||
cc5703cd ILT |
94 | #define ILLEGAL_REG (32) |
95 | ||
af942793 SS |
96 | /* Allow override of standard little-endian ECOFF format. */ |
97 | ||
98 | #ifndef ECOFF_LITTLE_FORMAT | |
99 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
100 | #endif | |
101 | ||
1dc1e798 | 102 | extern int target_big_endian; |
88225433 | 103 | |
7f9880e5 ILT |
104 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
105 | 32 bit ABI. This has no meaning for ECOFF. */ | |
106 | static int mips_64; | |
107 | ||
04cb3372 | 108 | /* The default target format to use. */ |
1dc1e798 KR |
109 | const char * |
110 | mips_target_format () | |
111 | { | |
112 | switch (OUTPUT_FLAVOR) | |
113 | { | |
114 | case bfd_target_aout_flavour: | |
115 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
116 | case bfd_target_ecoff_flavour: | |
af942793 | 117 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 118 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
119 | return (target_big_endian |
120 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
121 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
122 | default: |
123 | abort (); | |
124 | } | |
125 | } | |
04cb3372 | 126 | |
d2c71068 | 127 | /* The name of the readonly data section. */ |
1dc1e798 KR |
128 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
129 | ? ".data" \ | |
130 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
131 | ? ".rdata" \ | |
132 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
133 | ? ".rodata" \ | |
134 | : (abort (), "")) | |
d2c71068 | 135 | |
1aa6938e ILT |
136 | /* These variables are filled in with the masks of registers used. |
137 | The object format code reads them and puts them in the appropriate | |
138 | place. */ | |
139 | unsigned long mips_gprmask; | |
140 | unsigned long mips_cprmask[4]; | |
141 | ||
1051c97f ILT |
142 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
143 | temporarily using .set mipsN). */ | |
8358c818 ILT |
144 | static int mips_isa = -1; |
145 | ||
1051c97f ILT |
146 | /* MIPS ISA we are using for this output file. */ |
147 | static int file_mips_isa; | |
148 | ||
cc5703cd ILT |
149 | /* Whether we are assembling for the mips16 processor. */ |
150 | static int mips16 = -1; | |
151 | ||
8c63448a | 152 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 153 | static int mips_cpu = -1; |
8c63448a | 154 | |
b2b8c24e ILT |
155 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
156 | static int mips_4650 = -1; | |
157 | ||
e532b44c ILT |
158 | /* Whether the 4010 instructions are permitted. */ |
159 | static int mips_4010 = -1; | |
160 | ||
c625fc23 JSC |
161 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
162 | static int mips_4100 = -1; | |
163 | ||
276c2d7d GRK |
164 | /* start-sanitize-r5900 */ |
165 | /* Whether Toshiba r5900 instructions are permitted. */ | |
166 | static int mips_5900 = -1; | |
167 | /* end-sanitize-r5900 */ | |
168 | ||
e532b44c ILT |
169 | /* Whether the processor uses hardware interlocks, and thus does not |
170 | require nops to be inserted. */ | |
171 | static int interlocks = -1; | |
172 | ||
344a8d61 JSC |
173 | /* As with "interlocks" this is used by hardware that has FP |
174 | (co-processor) interlocks. */ | |
efec4a28 | 175 | /* Itbl support may require additional care here. */ |
344a8d61 JSC |
176 | static int cop_interlocks = -1; |
177 | ||
d9aba805 ILT |
178 | /* MIPS PIC level. */ |
179 | ||
180 | enum mips_pic_level | |
181 | { | |
182 | /* Do not generate PIC code. */ | |
183 | NO_PIC, | |
184 | ||
185 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
186 | not sure what it is supposed to do. */ | |
187 | IRIX4_PIC, | |
188 | ||
189 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
190 | SVR4_PIC, | |
191 | ||
192 | /* Generate PIC code without using a global offset table: the data | |
193 | segment has a maximum size of 64K, all data references are off | |
194 | the $gp register, and all text references are PC relative. This | |
195 | is used on some embedded systems. */ | |
196 | EMBEDDED_PIC | |
197 | }; | |
198 | ||
199 | static enum mips_pic_level mips_pic; | |
9226253a | 200 | |
fb251650 ILT |
201 | /* 1 if we should generate 32 bit offsets from the GP register in |
202 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
203 | static int mips_big_got; | |
204 | ||
8ea7f4e8 ILT |
205 | /* 1 if trap instructions should used for overflow rather than break |
206 | instructions. */ | |
207 | static int mips_trap; | |
208 | ||
cc5703cd ILT |
209 | /* 1 if we should autoextend mips16 instructions. */ |
210 | static int mips16_autoextend = 1; | |
211 | ||
3d3c5039 ILT |
212 | static int mips_warn_about_macros; |
213 | static int mips_noreorder; | |
0dd2d296 | 214 | static int mips_any_noreorder; |
3d3c5039 ILT |
215 | static int mips_nomove; |
216 | static int mips_noat; | |
217 | static int mips_nobopt; | |
218 | ||
670a50eb ILT |
219 | /* The size of the small data section. */ |
220 | static int g_switch_value = 8; | |
42562568 ILT |
221 | /* Whether the -G option was used. */ |
222 | static int g_switch_seen = 0; | |
670a50eb | 223 | |
3d3c5039 ILT |
224 | #define N_RMASK 0xc4 |
225 | #define N_VFP 0xd4 | |
226 | ||
d8a1c247 KR |
227 | /* If we can determine in advance that GP optimization won't be |
228 | possible, we can skip the relaxation stuff that tries to produce | |
229 | GP-relative references. This makes delay slot optimization work | |
230 | better. | |
231 | ||
232 | This function can only provide a guess, but it seems to work for | |
233 | gcc output. If it guesses wrong, the only loss should be in | |
234 | efficiency; it shouldn't introduce any bugs. | |
235 | ||
236 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
237 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
238 | static int nopic_need_relax PARAMS ((symbolS *)); | |
239 | ||
3d3c5039 ILT |
240 | /* handle of the OPCODE hash table */ |
241 | static struct hash_control *op_hash = NULL; | |
242 | ||
cc5703cd ILT |
243 | /* The opcode hash table we use for the mips16. */ |
244 | static struct hash_control *mips16_op_hash = NULL; | |
245 | ||
3d3c5039 ILT |
246 | /* This array holds the chars that always start a comment. If the |
247 | pre-processor is disabled, these aren't very useful */ | |
248 | const char comment_chars[] = "#"; | |
249 | ||
250 | /* This array holds the chars that only start a comment at the beginning of | |
251 | a line. If the line seems to have the form '# 123 filename' | |
252 | .line and .file directives will appear in the pre-processed output */ | |
253 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
254 | first line of the input file. This is because the compiler outputs | |
255 | #NO_APP at the beginning of its output. */ | |
256 | /* Also note that C style comments are always supported. */ | |
257 | const char line_comment_chars[] = "#"; | |
258 | ||
259 | /* This array holds machine specific line separator characters. */ | |
260 | const char line_separator_chars[] = ""; | |
261 | ||
262 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
263 | const char EXP_CHARS[] = "eE"; | |
264 | ||
265 | /* Chars that mean this number is a floating point constant */ | |
266 | /* As in 0f12.456 */ | |
267 | /* or 0d1.2345e12 */ | |
268 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
269 | ||
270 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
271 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
272 | but nothing is ideal around here. | |
273 | */ | |
274 | ||
670a50eb | 275 | static char *insn_error; |
3d3c5039 | 276 | |
3d3c5039 | 277 | static int auto_align = 1; |
becfe05e | 278 | |
9226253a ILT |
279 | /* When outputting SVR4 PIC code, the assembler needs to know the |
280 | offset in the stack frame from which to restore the $gp register. | |
281 | This is set by the .cprestore pseudo-op, and saved in this | |
282 | variable. */ | |
0dd2d296 ILT |
283 | static offsetT mips_cprestore_offset = -1; |
284 | ||
285 | /* This is the register which holds the stack frame, as set by the | |
286 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
287 | static int mips_frame_reg = SP; | |
9226253a | 288 | |
becfe05e ILT |
289 | /* To output NOP instructions correctly, we need to keep information |
290 | about the previous two instructions. */ | |
291 | ||
0aa07269 ILT |
292 | /* Whether we are optimizing. The default value of 2 means to remove |
293 | unneeded NOPs and swap branch instructions when possible. A value | |
294 | of 1 means to not swap branches. A value of 0 means to always | |
295 | insert NOPs. */ | |
296 | static int mips_optimize = 2; | |
4e95866e | 297 | |
22ba90ce ILT |
298 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
299 | equivalent to seeing no -g option at all. */ | |
300 | static int mips_debug = 0; | |
301 | ||
becfe05e ILT |
302 | /* The previous instruction. */ |
303 | static struct mips_cl_insn prev_insn; | |
304 | ||
305 | /* The instruction before prev_insn. */ | |
306 | static struct mips_cl_insn prev_prev_insn; | |
307 | ||
308 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
309 | point the insn_mo field at this dummy integer. */ | |
310 | static const struct mips_opcode dummy_opcode = { 0 }; | |
311 | ||
312 | /* Non-zero if prev_insn is valid. */ | |
313 | static int prev_insn_valid; | |
314 | ||
315 | /* The frag for the previous instruction. */ | |
316 | static struct frag *prev_insn_frag; | |
317 | ||
318 | /* The offset into prev_insn_frag for the previous instruction. */ | |
319 | static long prev_insn_where; | |
320 | ||
a677feeb ILT |
321 | /* The reloc type for the previous instruction, if any. */ |
322 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
323 | ||
becfe05e ILT |
324 | /* The reloc for the previous instruction, if any. */ |
325 | static fixS *prev_insn_fixp; | |
326 | ||
327 | /* Non-zero if the previous instruction was in a delay slot. */ | |
328 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
329 | |
330 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
331 | static int prev_insn_unreordered; | |
332 | ||
cc5703cd ILT |
333 | /* Non-zero if the previous instruction uses an extend opcode (if |
334 | mips16). */ | |
335 | static int prev_insn_extended; | |
336 | ||
4e95866e ILT |
337 | /* Non-zero if the previous previous instruction was in a .set |
338 | noreorder. */ | |
339 | static int prev_prev_insn_unreordered; | |
867a58b3 | 340 | |
4a1cb507 ILT |
341 | /* If this is set, it points to a frag holding nop instructions which |
342 | were inserted before the start of a noreorder section. If those | |
343 | nops turn out to be unnecessary, the size of the frag can be | |
344 | decreased. */ | |
345 | static fragS *prev_nop_frag; | |
346 | ||
347 | /* The number of nop instructions we created in prev_nop_frag. */ | |
348 | static int prev_nop_frag_holds; | |
349 | ||
350 | /* The number of nop instructions that we know we need in | |
351 | prev_nop_frag. */ | |
352 | static int prev_nop_frag_required; | |
353 | ||
354 | /* The number of instructions we've seen since prev_nop_frag. */ | |
355 | static int prev_nop_frag_since; | |
356 | ||
867a58b3 ILT |
357 | /* For ECOFF and ELF, relocations against symbols are done in two |
358 | parts, with a HI relocation and a LO relocation. Each relocation | |
359 | has only 16 bits of space to store an addend. This means that in | |
360 | order for the linker to handle carries correctly, it must be able | |
361 | to locate both the HI and the LO relocation. This means that the | |
362 | relocations must appear in order in the relocation table. | |
363 | ||
364 | In order to implement this, we keep track of each unmatched HI | |
365 | relocation. We then sort them so that they immediately precede the | |
366 | corresponding LO relocation. */ | |
367 | ||
368 | struct mips_hi_fixup | |
369 | { | |
370 | /* Next HI fixup. */ | |
371 | struct mips_hi_fixup *next; | |
372 | /* This fixup. */ | |
373 | fixS *fixp; | |
374 | /* The section this fixup is in. */ | |
375 | segT seg; | |
376 | }; | |
377 | ||
378 | /* The list of unmatched HI relocs. */ | |
379 | ||
380 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
381 | |
382 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
383 | ||
384 | #define X ILLEGAL_REG | |
385 | static const int mips32_to_16_reg_map[] = | |
386 | { | |
387 | X, X, 2, 3, 4, 5, 6, 7, | |
388 | X, X, X, X, X, X, X, X, | |
389 | 0, 1, X, X, X, X, X, X, | |
390 | X, X, X, X, X, X, X, X | |
391 | }; | |
392 | #undef X | |
393 | ||
394 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
395 | ||
396 | static const int mips16_to_32_reg_map[] = | |
397 | { | |
398 | 16, 17, 2, 3, 4, 5, 6, 7 | |
399 | }; | |
3d3c5039 | 400 | \f |
0dd2d296 ILT |
401 | /* Since the MIPS does not have multiple forms of PC relative |
402 | instructions, we do not have to do relaxing as is done on other | |
403 | platforms. However, we do have to handle GP relative addressing | |
404 | correctly, which turns out to be a similar problem. | |
405 | ||
406 | Every macro that refers to a symbol can occur in (at least) two | |
407 | forms, one with GP relative addressing and one without. For | |
408 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 409 | a macro instruction like this: |
0dd2d296 ILT |
410 | lw $4,i |
411 | If i can be addressed off the GP register (this is true if it is in | |
412 | the .sbss or .sdata section, or if it is known to be smaller than | |
413 | the -G argument) this will generate the following instruction: | |
414 | lw $4,i($gp) | |
415 | This instruction will use a GPREL reloc. If i can not be addressed | |
416 | off the GP register, the following instruction sequence will be used: | |
417 | lui $at,i | |
418 | lw $4,i($at) | |
419 | In this case the first instruction will have a HI16 reloc, and the | |
420 | second reloc will have a LO16 reloc. Both relocs will be against | |
421 | the symbol i. | |
422 | ||
423 | The issue here is that we may not know whether i is GP addressable | |
424 | until after we see the instruction that uses it. Therefore, we | |
425 | want to be able to choose the final instruction sequence only at | |
426 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 427 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
428 | end of assembly. |
429 | ||
430 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
431 | addressing in quite the same way, but the issue still arises as |
432 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
433 | |
434 | We handle these issues by actually generating both possible | |
435 | instruction sequences. The longer one is put in a frag_var with | |
436 | type rs_machine_dependent. We encode what to do with the frag in | |
437 | the subtype field. We encode (1) the number of existing bytes to | |
438 | replace, (2) the number of new bytes to use, (3) the offset from | |
439 | the start of the existing bytes to the first reloc we must generate | |
440 | (that is, the offset is applied from the start of the existing | |
441 | bytes after they are replaced by the new bytes, if any), (4) the | |
442 | offset from the start of the existing bytes to the second reloc, | |
443 | (5) whether a third reloc is needed (the third reloc is always four | |
444 | bytes after the second reloc), and (6) whether to warn if this | |
445 | variant is used (this is sometimes needed if .set nomacro or .set | |
446 | noat is in effect). All these numbers are reasonably small. | |
447 | ||
448 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
449 | ensure that delay slots are handled correctly. Fortunately, there |
450 | are a limited number of cases. When the second instruction | |
451 | sequence is generated, append_insn is directed to maintain the | |
452 | existing delay slot information, so it continues to apply to any | |
453 | code after the second instruction sequence. This means that the | |
454 | second instruction sequence must not impose any requirements not | |
455 | required by the first instruction sequence. | |
0dd2d296 ILT |
456 | |
457 | These variant frags are then handled in functions called by the | |
458 | machine independent code. md_estimate_size_before_relax returns | |
459 | the final size of the frag. md_convert_frag sets up the final form | |
460 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
461 | one if needed. */ | |
462 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
463 | ((relax_substateT) \ | |
cc5703cd | 464 | (((old) << 23) \ |
0dd2d296 ILT |
465 | | ((new) << 16) \ |
466 | | (((reloc1) + 64) << 9) \ | |
467 | | (((reloc2) + 64) << 2) \ | |
468 | | ((reloc3) ? (1 << 1) : 0) \ | |
469 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
470 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
471 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
472 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
473 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
474 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
475 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
476 | |
477 | /* For mips16 code, we use an entirely different form of relaxation. | |
478 | mips16 supports two versions of most instructions which take | |
479 | immediate values: a small one which takes some small value, and a | |
480 | larger one which takes a 16 bit value. Since branches also follow | |
481 | this pattern, relaxing these values is required. | |
482 | ||
483 | We can assemble both mips16 and normal MIPS code in a single | |
484 | object. Therefore, we need to support this type of relaxation at | |
485 | the same time that we support the relaxation described above. We | |
486 | use the high bit of the subtype field to distinguish these cases. | |
487 | ||
a677feeb ILT |
488 | The information we store for this type of relaxation is the |
489 | argument code found in the opcode file for this relocation, whether | |
490 | the user explicitly requested a small or extended form, and whether | |
491 | the relocation is in a jump or jal delay slot. That tells us the | |
492 | size of the value, and how it should be stored. We also store | |
493 | whether the fragment is considered to be extended or not. We also | |
494 | store whether this is known to be a branch to a different section, | |
495 | whether we have tried to relax this frag yet, and whether we have | |
496 | ever extended a PC relative fragment because of a shift count. */ | |
497 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
498 | (0x80000000 \ | |
499 | | ((type) & 0xff) \ | |
500 | | ((small) ? 0x100 : 0) \ | |
501 | | ((ext) ? 0x200 : 0) \ | |
502 | | ((dslot) ? 0x400 : 0) \ | |
503 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
504 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
505 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
506 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
507 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
508 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
509 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
510 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
511 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
512 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
513 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
514 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
515 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 516 | \f |
3d3c5039 ILT |
517 | /* Prototypes for static functions. */ |
518 | ||
519 | #ifdef __STDC__ | |
520 | #define internalError() \ | |
521 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
522 | #else | |
523 | #define internalError() as_fatal ("MIPS internal Error"); | |
524 | #endif | |
525 | ||
cc5703cd ILT |
526 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
527 | ||
becfe05e | 528 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 529 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 530 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
531 | static void append_insn PARAMS ((char *place, |
532 | struct mips_cl_insn * ip, | |
670a50eb | 533 | expressionS * p, |
867a58b3 ILT |
534 | bfd_reloc_code_real_type r, |
535 | boolean)); | |
4a1cb507 | 536 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 537 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 538 | #ifdef USE_STDARG |
0dd2d296 | 539 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
540 | const char *name, const char *fmt, |
541 | ...)); | |
c625fc23 JSC |
542 | #else |
543 | static void macro_build (); | |
544 | #endif | |
cc5703cd ILT |
545 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
546 | const char *, const char *, | |
547 | va_list)); | |
0dd2d296 ILT |
548 | static void macro_build_lui PARAMS ((char *place, int *counter, |
549 | expressionS * ep, int regnum)); | |
6e8dda9c | 550 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 551 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 552 | expressionS *)); |
d8a1c247 | 553 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 554 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 555 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 556 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
557 | #ifdef LOSING_COMPILER |
558 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
559 | #endif | |
670a50eb | 560 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 561 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
562 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
563 | boolean, boolean, unsigned long *, | |
564 | boolean *, unsigned short *)); | |
670a50eb ILT |
565 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
566 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 567 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 568 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
569 | static void s_align PARAMS ((int)); |
570 | static void s_change_sec PARAMS ((int)); | |
571 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 572 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 573 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
574 | static void s_option PARAMS ((int)); |
575 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
576 | static void s_abicalls PARAMS ((int)); |
577 | static void s_cpload PARAMS ((int)); | |
578 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
579 | static void s_gpword PARAMS ((int)); |
580 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 581 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
582 | static void md_obj_begin PARAMS ((void)); |
583 | static void md_obj_end PARAMS ((void)); | |
584 | static long get_number PARAMS ((void)); | |
585 | static void s_ent PARAMS ((int)); | |
586 | static void s_mipsend PARAMS ((int)); | |
587 | static void s_file PARAMS ((int)); | |
cc5703cd | 588 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
589 | \f |
590 | /* Pseudo-op table. | |
591 | ||
592 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
593 | should be defined here, but are currently unsupported: .alias, | |
594 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
595 | ||
596 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
597 | specific to the type of debugging information being generated, and | |
598 | should be defined by the object format: .aent, .begin, .bend, | |
599 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
600 | .vreg. | |
601 | ||
602 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
603 | not MIPS CPU specific, but are also not specific to the object file | |
604 | format. This file is probably the best place to define them, but | |
605 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
606 | .struct, .weakext. */ | |
607 | ||
739708fa | 608 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 609 | { |
670a50eb ILT |
610 | /* MIPS specific pseudo-ops. */ |
611 | {"option", s_option, 0}, | |
612 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
613 | {"rdata", s_change_sec, 'r'}, |
614 | {"sdata", s_change_sec, 's'}, | |
615 | {"livereg", s_ignore, 0}, | |
739708fa KR |
616 | {"abicalls", s_abicalls, 0}, |
617 | {"cpload", s_cpload, 0}, | |
618 | {"cprestore", s_cprestore, 0}, | |
619 | {"gpword", s_gpword, 0}, | |
620 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 621 | {"insn", s_insn, 0}, |
3d3c5039 | 622 | |
670a50eb | 623 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 624 | chips. */ |
739708fa | 625 | {"asciiz", stringer, 1}, |
670a50eb ILT |
626 | {"bss", s_change_sec, 'b'}, |
627 | {"err", s_err, 0}, | |
628 | {"half", s_cons, 1}, | |
52aa70b5 | 629 | {"dword", s_cons, 3}, |
3d3c5039 | 630 | |
670a50eb | 631 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 632 | here for one reason or another. */ |
670a50eb ILT |
633 | {"align", s_align, 0}, |
634 | {"byte", s_cons, 0}, | |
635 | {"data", s_change_sec, 'd'}, | |
becfe05e | 636 | {"double", s_float_cons, 'd'}, |
becfe05e | 637 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
638 | {"globl", s_mips_globl, 0}, |
639 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
640 | {"hword", s_cons, 1}, |
641 | {"int", s_cons, 2}, | |
642 | {"long", s_cons, 2}, | |
643 | {"octa", s_cons, 4}, | |
644 | {"quad", s_cons, 3}, | |
645 | {"short", s_cons, 1}, | |
646 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
647 | {"text", s_change_sec, 't'}, |
648 | {"word", s_cons, 2}, | |
739708fa KR |
649 | { 0 }, |
650 | }; | |
3d3c5039 | 651 | |
739708fa | 652 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 653 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 654 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 655 | {"aent", s_ent, 1}, |
9226253a | 656 | {"bgnb", s_ignore, 0}, |
670a50eb | 657 | {"end", s_mipsend, 0}, |
9226253a | 658 | {"endb", s_ignore, 0}, |
670a50eb ILT |
659 | {"ent", s_ent, 0}, |
660 | {"file", s_file, 0}, | |
661 | {"fmask", s_ignore, 'F'}, | |
662 | {"frame", s_ignore, 0}, | |
663 | {"loc", s_ignore, 0}, | |
664 | {"mask", s_ignore, 'R'}, | |
665 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
666 | { 0 }, |
667 | }; | |
61420a20 | 668 | |
739708fa KR |
669 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
670 | ||
671 | void | |
672 | mips_pop_insert () | |
673 | { | |
674 | pop_insert (mips_pseudo_table); | |
675 | if (! ECOFF_DEBUGGING) | |
676 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 677 | } |
3d3c5039 | 678 | \f |
fbcfacb7 ILT |
679 | /* Symbols labelling the current insn. */ |
680 | ||
681 | struct insn_label_list | |
682 | { | |
683 | struct insn_label_list *next; | |
684 | symbolS *label; | |
685 | }; | |
686 | ||
687 | static struct insn_label_list *insn_labels; | |
688 | static struct insn_label_list *free_insn_labels; | |
689 | ||
690 | static void mips_clear_insn_labels PARAMS ((void)); | |
691 | ||
692 | static inline void | |
693 | mips_clear_insn_labels () | |
694 | { | |
695 | register struct insn_label_list **pl; | |
696 | ||
697 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
698 | ; | |
699 | *pl = insn_labels; | |
700 | insn_labels = NULL; | |
701 | } | |
702 | \f | |
3d3c5039 ILT |
703 | static char *expr_end; |
704 | ||
867a58b3 ILT |
705 | /* Expressions which appear in instructions. These are set by |
706 | mips_ip. */ | |
707 | ||
3d3c5039 ILT |
708 | static expressionS imm_expr; |
709 | static expressionS offset_expr; | |
867a58b3 ILT |
710 | |
711 | /* Relocs associated with imm_expr and offset_expr. */ | |
712 | ||
3d3c5039 ILT |
713 | static bfd_reloc_code_real_type imm_reloc; |
714 | static bfd_reloc_code_real_type offset_reloc; | |
715 | ||
867a58b3 ILT |
716 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
717 | ||
718 | static boolean imm_unmatched_hi; | |
719 | ||
8728fa92 ILT |
720 | /* These are set by mips16_ip if an explicit extension is used. */ |
721 | ||
722 | static boolean mips16_small, mips16_ext; | |
723 | ||
3d3c5039 ILT |
724 | /* |
725 | * This function is called once, at assembler startup time. It should | |
726 | * set up all the tables, etc. that the MD part of the assembler will need. | |
727 | */ | |
728 | void | |
670a50eb | 729 | md_begin () |
3d3c5039 | 730 | { |
0dd2d296 | 731 | boolean ok = false; |
604633ae | 732 | register const char *retval = NULL; |
670a50eb | 733 | register unsigned int i = 0; |
3d3c5039 | 734 | |
8358c818 ILT |
735 | if (mips_isa == -1) |
736 | { | |
8c63448a ILT |
737 | const char *cpu; |
738 | char *a = NULL; | |
739 | ||
740 | cpu = TARGET_CPU; | |
741 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
742 | { | |
743 | a = xmalloc (sizeof TARGET_CPU); | |
744 | strcpy (a, TARGET_CPU); | |
745 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
746 | cpu = a; | |
747 | } | |
748 | ||
749 | if (strcmp (cpu, "mips") == 0) | |
750 | { | |
751 | mips_isa = 1; | |
4bb0cc41 ILT |
752 | if (mips_cpu == -1) |
753 | mips_cpu = 3000; | |
8c63448a ILT |
754 | } |
755 | else if (strcmp (cpu, "r6000") == 0 | |
756 | || strcmp (cpu, "mips2") == 0) | |
757 | { | |
758 | mips_isa = 2; | |
4bb0cc41 ILT |
759 | if (mips_cpu == -1) |
760 | mips_cpu = 6000; | |
8c63448a ILT |
761 | } |
762 | else if (strcmp (cpu, "mips64") == 0 | |
763 | || strcmp (cpu, "r4000") == 0 | |
764 | || strcmp (cpu, "mips3") == 0) | |
765 | { | |
766 | mips_isa = 3; | |
4bb0cc41 ILT |
767 | if (mips_cpu == -1) |
768 | mips_cpu = 4000; | |
8c63448a ILT |
769 | } |
770 | else if (strcmp (cpu, "r4400") == 0) | |
771 | { | |
772 | mips_isa = 3; | |
4bb0cc41 ILT |
773 | if (mips_cpu == -1) |
774 | mips_cpu = 4400; | |
8c63448a ILT |
775 | } |
776 | else if (strcmp (cpu, "mips64orion") == 0 | |
777 | || strcmp (cpu, "r4600") == 0) | |
778 | { | |
779 | mips_isa = 3; | |
4bb0cc41 ILT |
780 | if (mips_cpu == -1) |
781 | mips_cpu = 4600; | |
8c63448a | 782 | } |
b2b8c24e ILT |
783 | else if (strcmp (cpu, "r4650") == 0) |
784 | { | |
785 | mips_isa = 3; | |
786 | if (mips_cpu == -1) | |
787 | mips_cpu = 4650; | |
788 | if (mips_4650 == -1) | |
789 | mips_4650 = 1; | |
790 | } | |
c625fc23 JSC |
791 | else if (strcmp (cpu, "mips64vr4300") == 0) |
792 | { | |
793 | mips_isa = 3; | |
794 | if (mips_cpu == -1) | |
795 | mips_cpu = 4300; | |
796 | } | |
797 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
798 | { | |
799 | mips_isa = 3; | |
800 | if (mips_cpu == -1) | |
801 | mips_cpu = 4100; | |
802 | if (mips_4100 == -1) | |
803 | mips_4100 = 1; | |
804 | } | |
e532b44c ILT |
805 | else if (strcmp (cpu, "r4010") == 0) |
806 | { | |
807 | mips_isa = 2; | |
808 | if (mips_cpu == -1) | |
809 | mips_cpu = 4010; | |
810 | if (mips_4010 == -1) | |
811 | mips_4010 = 1; | |
812 | } | |
517078c1 ILT |
813 | else if (strcmp (cpu, "r5000") == 0 |
814 | || strcmp (cpu, "mips64vr5000") == 0) | |
815 | { | |
816 | mips_isa = 4; | |
817 | if (mips_cpu == -1) | |
818 | mips_cpu = 5000; | |
819 | } | |
276c2d7d GRK |
820 | /* start-sanitize-r5900 */ |
821 | else if (strcmp (cpu, "r5900") == 0 | |
822 | || strcmp (cpu, "mips64vr5900") == 0 | |
823 | || strcmp (cpu, "mips64vr5900el") == 0) | |
824 | { | |
825 | mips_isa = 3; | |
826 | if (mips_cpu == -1) | |
827 | mips_cpu = 5900; | |
16262668 | 828 | if (mips_5900 == -1) |
276c2d7d GRK |
829 | mips_5900 = 1; |
830 | } | |
831 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
832 | else if (strcmp (cpu, "r8000") == 0 |
833 | || strcmp (cpu, "mips4") == 0) | |
834 | { | |
835 | mips_isa = 4; | |
836 | if (mips_cpu == -1) | |
837 | mips_cpu = 8000; | |
838 | } | |
839 | else if (strcmp (cpu, "r10000") == 0) | |
840 | { | |
841 | mips_isa = 4; | |
842 | if (mips_cpu == -1) | |
843 | mips_cpu = 10000; | |
844 | } | |
cc5703cd ILT |
845 | else if (strcmp (cpu, "mips16") == 0) |
846 | { | |
847 | mips_isa = 3; | |
848 | if (mips_cpu == -1) | |
849 | mips_cpu = 0; /* FIXME */ | |
850 | } | |
8358c818 | 851 | else |
8c63448a ILT |
852 | { |
853 | mips_isa = 1; | |
4bb0cc41 ILT |
854 | if (mips_cpu == -1) |
855 | mips_cpu = 3000; | |
8c63448a ILT |
856 | } |
857 | ||
858 | if (a != NULL) | |
859 | free (a); | |
8358c818 ILT |
860 | } |
861 | ||
cc5703cd ILT |
862 | if (mips16 < 0) |
863 | { | |
864 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
865 | mips16 = 1; | |
866 | else | |
867 | mips16 = 0; | |
868 | } | |
869 | ||
b2b8c24e ILT |
870 | if (mips_4650 < 0) |
871 | mips_4650 = 0; | |
872 | ||
e532b44c ILT |
873 | if (mips_4010 < 0) |
874 | mips_4010 = 0; | |
875 | ||
c625fc23 JSC |
876 | if (mips_4100 < 0) |
877 | mips_4100 = 0; | |
878 | ||
276c2d7d GRK |
879 | /* start-sanitize-r5900 */ |
880 | if (mips_5900 < 0) | |
881 | mips_5900 = 0; | |
882 | /* end-sanitize-r5900 */ | |
883 | ||
c36a90ef | 884 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
885 | interlocks = 1; |
886 | else | |
887 | interlocks = 0; | |
888 | ||
efec4a28 | 889 | /* Itbl support may require additional care here. */ |
ca296aab | 890 | if (mips_cpu == 4300) |
344a8d61 JSC |
891 | cop_interlocks = 1; |
892 | else | |
893 | cop_interlocks = 0; | |
894 | ||
8ea7f4e8 ILT |
895 | if (mips_isa < 2 && mips_trap) |
896 | as_bad ("trap exception not supported at ISA 1"); | |
897 | ||
97f99d11 ILT |
898 | switch (mips_isa) |
899 | { | |
900 | case 1: | |
901 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
902 | break; | |
903 | case 2: | |
904 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
905 | break; | |
906 | case 3: | |
907 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
908 | break; | |
d8a1c247 KR |
909 | case 4: |
910 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
911 | break; | |
97f99d11 ILT |
912 | } |
913 | if (! ok) | |
914 | as_warn ("Could not set architecture and machine"); | |
915 | ||
1051c97f ILT |
916 | file_mips_isa = mips_isa; |
917 | ||
13fe1379 ILT |
918 | op_hash = hash_new (); |
919 | ||
670a50eb ILT |
920 | for (i = 0; i < NUMOPCODES;) |
921 | { | |
922 | const char *name = mips_opcodes[i].name; | |
923 | ||
604633ae | 924 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 925 | if (retval != NULL) |
670a50eb ILT |
926 | { |
927 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
928 | mips_opcodes[i].name, retval); | |
929 | as_fatal ("Broken assembler. No assembly attempted."); | |
930 | } | |
931 | do | |
932 | { | |
8358c818 ILT |
933 | if (mips_opcodes[i].pinfo != INSN_MACRO |
934 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
935 | != mips_opcodes[i].match)) | |
670a50eb ILT |
936 | { |
937 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
938 | mips_opcodes[i].name, mips_opcodes[i].args); | |
939 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 940 | } |
670a50eb ILT |
941 | ++i; |
942 | } | |
943 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
944 | } |
945 | ||
cc5703cd ILT |
946 | mips16_op_hash = hash_new (); |
947 | ||
948 | i = 0; | |
949 | while (i < bfd_mips16_num_opcodes) | |
950 | { | |
951 | const char *name = mips16_opcodes[i].name; | |
952 | ||
953 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
954 | if (retval != NULL) | |
955 | as_fatal ("internal error: can't hash `%s': %s\n", | |
956 | mips16_opcodes[i].name, retval); | |
957 | do | |
958 | { | |
959 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
960 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
961 | != mips16_opcodes[i].match)) | |
962 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
963 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
964 | ++i; | |
965 | } | |
966 | while (i < bfd_mips16_num_opcodes | |
967 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
968 | } | |
969 | ||
ebf28372 ILT |
970 | /* We add all the general register names to the symbol table. This |
971 | helps us detect invalid uses of them. */ | |
972 | for (i = 0; i < 32; i++) | |
973 | { | |
974 | char buf[5]; | |
975 | ||
976 | sprintf (buf, "$%d", i); | |
977 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
978 | &zero_address_frag)); | |
979 | } | |
980 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
981 | &zero_address_frag)); | |
982 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
983 | &zero_address_frag)); | |
984 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
985 | &zero_address_frag)); | |
986 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
987 | &zero_address_frag)); | |
988 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
989 | &zero_address_frag)); | |
990 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
991 | &zero_address_frag)); | |
992 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
993 | &zero_address_frag)); | |
994 | ||
4a1cb507 | 995 | mips_no_prev_insn (false); |
becfe05e | 996 | |
1aa6938e ILT |
997 | mips_gprmask = 0; |
998 | mips_cprmask[0] = 0; | |
999 | mips_cprmask[1] = 0; | |
1000 | mips_cprmask[2] = 0; | |
1001 | mips_cprmask[3] = 0; | |
1002 | ||
8358c818 | 1003 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1004 | record_alignment (text_section, 2); |
8358c818 | 1005 | |
1dc1e798 KR |
1006 | if (USE_GLOBAL_POINTER_OPT) |
1007 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1008 | |
1dc1e798 KR |
1009 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1010 | { | |
08e17202 ILT |
1011 | /* On a native system, sections must be aligned to 16 byte |
1012 | boundaries. When configured for an embedded ELF target, we | |
1013 | don't bother. */ | |
1014 | if (strcmp (TARGET_OS, "elf") != 0) | |
1015 | { | |
1016 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1017 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1018 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1019 | } | |
1dc1e798 KR |
1020 | |
1021 | /* Create a .reginfo section for register masks and a .mdebug | |
1022 | section for debugging information. */ | |
1023 | { | |
1024 | segT seg; | |
1025 | subsegT subseg; | |
b3a64736 | 1026 | flagword flags; |
1dc1e798 KR |
1027 | segT sec; |
1028 | ||
1029 | seg = now_seg; | |
1030 | subseg = now_subseg; | |
1dc1e798 | 1031 | |
b3a64736 ILT |
1032 | /* The ABI says this section should be loaded so that the |
1033 | running program can access it. However, we don't load it | |
1034 | if we are configured for an embedded target */ | |
1035 | flags = SEC_READONLY | SEC_DATA; | |
1036 | if (strcmp (TARGET_OS, "elf") != 0) | |
1037 | flags |= SEC_ALLOC | SEC_LOAD; | |
1038 | ||
87178180 ILT |
1039 | if (! mips_64) |
1040 | { | |
1041 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1042 | |
b3a64736 ILT |
1043 | |
1044 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1045 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1046 | ||
f2a663d3 | 1047 | #ifdef OBJ_ELF |
87178180 | 1048 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1049 | #endif |
87178180 ILT |
1050 | } |
1051 | else | |
1052 | { | |
1053 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1054 | .reginfo section. */ | |
1055 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1056 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1057 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1058 | ||
1059 | #ifdef OBJ_ELF | |
1060 | /* Set up the option header. */ | |
1061 | { | |
1062 | Elf_Internal_Options opthdr; | |
1063 | char *f; | |
1064 | ||
1065 | opthdr.kind = ODK_REGINFO; | |
1066 | opthdr.size = (sizeof (Elf_External_Options) | |
1067 | + sizeof (Elf64_External_RegInfo)); | |
1068 | opthdr.section = 0; | |
1069 | opthdr.info = 0; | |
1070 | f = frag_more (sizeof (Elf_External_Options)); | |
1071 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1072 | (Elf_External_Options *) f); | |
1073 | ||
1074 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1075 | } | |
1076 | #endif | |
1077 | } | |
f2a663d3 | 1078 | |
739708fa KR |
1079 | if (ECOFF_DEBUGGING) |
1080 | { | |
1081 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1082 | (void) bfd_set_section_flags (stdoutput, sec, | |
1083 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1084 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1085 | } | |
0dd2d296 | 1086 | |
1dc1e798 KR |
1087 | subseg_set (seg, subseg); |
1088 | } | |
1089 | } | |
f2a663d3 | 1090 | |
739708fa KR |
1091 | if (! ECOFF_DEBUGGING) |
1092 | md_obj_begin (); | |
3d3c5039 ILT |
1093 | } |
1094 | ||
1095 | void | |
13fe1379 | 1096 | md_mips_end () |
3d3c5039 | 1097 | { |
739708fa KR |
1098 | if (! ECOFF_DEBUGGING) |
1099 | md_obj_end (); | |
3d3c5039 ILT |
1100 | } |
1101 | ||
1102 | void | |
670a50eb ILT |
1103 | md_assemble (str) |
1104 | char *str; | |
3d3c5039 | 1105 | { |
670a50eb | 1106 | struct mips_cl_insn insn; |
3d3c5039 | 1107 | |
5ac34ac3 | 1108 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1109 | imm_reloc = BFD_RELOC_UNUSED; |
1110 | imm_unmatched_hi = false; | |
5ac34ac3 | 1111 | offset_expr.X_op = O_absent; |
867a58b3 | 1112 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1113 | |
cc5703cd ILT |
1114 | if (mips16) |
1115 | mips16_ip (str, &insn); | |
1116 | else | |
efec4a28 | 1117 | { |
9218cee0 | 1118 | mips_ip (str, &insn); |
efec4a28 DP |
1119 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1120 | str, insn.insn_opcode)); | |
1121 | } | |
cc5703cd | 1122 | |
670a50eb ILT |
1123 | if (insn_error) |
1124 | { | |
1125 | as_bad ("%s `%s'", insn_error, str); | |
1126 | return; | |
1127 | } | |
cc5703cd | 1128 | |
670a50eb ILT |
1129 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1130 | { | |
cc5703cd ILT |
1131 | if (mips16) |
1132 | mips16_macro (&insn); | |
1133 | else | |
1134 | macro (&insn); | |
3d3c5039 | 1135 | } |
670a50eb ILT |
1136 | else |
1137 | { | |
5ac34ac3 | 1138 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1139 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1140 | imm_unmatched_hi); | |
5ac34ac3 | 1141 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1142 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1143 | else |
867a58b3 | 1144 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1145 | } |
1146 | } | |
1147 | ||
cc5703cd ILT |
1148 | /* See whether instruction IP reads register REG. CLASS is the type |
1149 | of register. */ | |
becfe05e ILT |
1150 | |
1151 | static int | |
cc5703cd | 1152 | insn_uses_reg (ip, reg, class) |
becfe05e | 1153 | struct mips_cl_insn *ip; |
604633ae | 1154 | unsigned int reg; |
cc5703cd | 1155 | enum mips_regclass class; |
becfe05e | 1156 | { |
cc5703cd ILT |
1157 | if (class == MIPS16_REG) |
1158 | { | |
1159 | assert (mips16); | |
1160 | reg = mips16_to_32_reg_map[reg]; | |
1161 | class = MIPS_GR_REG; | |
1162 | } | |
1163 | ||
becfe05e | 1164 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1165 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1166 | return 0; |
1167 | ||
cc5703cd | 1168 | if (class == MIPS_FP_REG) |
becfe05e | 1169 | { |
cc5703cd | 1170 | assert (! mips16); |
becfe05e ILT |
1171 | /* If we are called with either $f0 or $f1, we must check $f0. |
1172 | This is not optimal, because it will introduce an unnecessary | |
1173 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1174 | need to distinguish reading both $f0 and $f1 or just one of | |
1175 | them. Note that we don't have to check the other way, | |
1176 | because there is no instruction that sets both $f0 and $f1 | |
1177 | and requires a delay. */ | |
1178 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1179 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1180 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1181 | return 1; |
1182 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1183 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1184 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1185 | return 1; |
1186 | } | |
cc5703cd | 1187 | else if (! mips16) |
becfe05e ILT |
1188 | { |
1189 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1190 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1191 | return 1; | |
1192 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1193 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1194 | return 1; | |
1195 | } | |
cc5703cd ILT |
1196 | else |
1197 | { | |
1198 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1199 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1200 | return 1; | |
1201 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1202 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1203 | return 1; | |
1204 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1205 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1206 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1207 | return 1; | |
1208 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1209 | return 1; | |
1210 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1211 | return 1; | |
1212 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1213 | return 1; | |
1214 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1215 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1216 | & MIPS16OP_MASK_REGR32) == reg) | |
1217 | return 1; | |
1218 | } | |
becfe05e ILT |
1219 | |
1220 | return 0; | |
1221 | } | |
1222 | ||
fb251650 ILT |
1223 | /* This function returns true if modifying a register requires a |
1224 | delay. */ | |
1225 | ||
1226 | static int | |
1227 | reg_needs_delay (reg) | |
1228 | int reg; | |
1229 | { | |
1230 | unsigned long prev_pinfo; | |
1231 | ||
1232 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1233 | if (! mips_noreorder | |
1234 | && mips_isa < 4 | |
1235 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1236 | || (mips_isa < 2 | |
1237 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1238 | { | |
1239 | /* A load from a coprocessor or from memory. All load | |
1240 | delays delay the use of general register rt for one | |
1241 | instruction on the r3000. The r6000 and r4000 use | |
1242 | interlocks. */ | |
efec4a28 | 1243 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1244 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1245 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1246 | return 1; | |
1247 | } | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
0dd2d296 ILT |
1252 | /* Output an instruction. PLACE is where to put the instruction; if |
1253 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1254 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1255 | used with RELOC_TYPE. */ | |
3d3c5039 | 1256 | |
3d3c5039 | 1257 | static void |
867a58b3 | 1258 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1259 | char *place; |
670a50eb ILT |
1260 | struct mips_cl_insn *ip; |
1261 | expressionS *address_expr; | |
1262 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1263 | boolean unmatched_hi; |
3d3c5039 | 1264 | { |
1aa6938e | 1265 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1266 | char *f; |
becfe05e ILT |
1267 | fixS *fixp; |
1268 | int nops = 0; | |
3d3c5039 | 1269 | |
fbcfacb7 ILT |
1270 | /* Mark instruction labels in mips16 mode. This permits the linker |
1271 | to handle them specially, such as generating jalx instructions | |
1272 | when needed. We also make them odd for the duration of the | |
1273 | assembly, in order to generate the right sort of code. We will | |
1274 | make them even in the adjust_symtab routine, while leaving them | |
1275 | marked. This is convenient for the debugger and the | |
1276 | disassembler. The linker knows to make them odd again. */ | |
1277 | if (mips16) | |
1278 | { | |
1279 | struct insn_label_list *l; | |
1280 | ||
1281 | for (l = insn_labels; l != NULL; l = l->next) | |
1282 | { | |
1283 | #ifdef S_SET_OTHER | |
1284 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1285 | S_SET_OTHER (l->label, STO_MIPS16); | |
1286 | #endif | |
1287 | ++l->label->sy_value.X_add_number; | |
1288 | } | |
1289 | } | |
1290 | ||
1aa6938e ILT |
1291 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1292 | pinfo = ip->insn_mo->pinfo; | |
1293 | ||
4a1cb507 | 1294 | if (place == NULL && (! mips_noreorder || prev_nop_frag != NULL)) |
becfe05e | 1295 | { |
4a1cb507 ILT |
1296 | int prev_prev_nop; |
1297 | ||
becfe05e | 1298 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1299 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1300 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1301 | (1) a load from memory delay |
1302 | (2) a load from a coprocessor delay | |
1303 | (3) an unconditional branch delay | |
1304 | (4) a conditional branch delay | |
1305 | (5) a move to coprocessor register delay | |
1306 | (6) a load coprocessor register from memory delay | |
1307 | (7) a coprocessor condition code delay | |
1308 | (8) a HI/LO special register delay | |
becfe05e ILT |
1309 | |
1310 | There are a lot of optimizations we could do that we don't. | |
1311 | In particular, we do not, in general, reorder instructions. | |
1312 | If you use gcc with optimization, it will reorder | |
1313 | instructions and generally do much more optimization then we | |
1314 | do here; repeating all that work in the assembler would only | |
1315 | benefit hand written assembly code, and does not seem worth | |
1316 | it. */ | |
1317 | ||
1318 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1319 | #define emit_nop() \ |
1320 | (mips16 \ | |
1321 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1322 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1323 | |
1324 | /* The previous insn might require a delay slot, depending upon | |
1325 | the contents of the current insn. */ | |
cc5703cd ILT |
1326 | if (! mips16 |
1327 | && mips_isa < 4 | |
5af96dce ILT |
1328 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1329 | && ! cop_interlocks) | |
d8a1c247 KR |
1330 | || (mips_isa < 2 |
1331 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1332 | { |
1333 | /* A load from a coprocessor or from memory. All load | |
1334 | delays delay the use of general register rt for one | |
1335 | instruction on the r3000. The r6000 and r4000 use | |
1336 | interlocks. */ | |
efec4a28 | 1337 | /* Itbl support may require additional care here. */ |
1aa6938e | 1338 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1339 | if (mips_optimize == 0 |
1340 | || insn_uses_reg (ip, | |
1341 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1342 | & OP_MASK_RT), | |
cc5703cd | 1343 | MIPS_GR_REG)) |
becfe05e ILT |
1344 | ++nops; |
1345 | } | |
cc5703cd ILT |
1346 | else if (! mips16 |
1347 | && mips_isa < 4 | |
5af96dce ILT |
1348 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1349 | && ! cop_interlocks) | |
d8a1c247 KR |
1350 | || (mips_isa < 2 |
1351 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1352 | { |
1353 | /* A generic coprocessor delay. The previous instruction | |
1354 | modified a coprocessor general or control register. If | |
1355 | it modified a control register, we need to avoid any | |
1356 | coprocessor instruction (this is probably not always | |
1357 | required, but it sometimes is). If it modified a general | |
1358 | register, we avoid using that register. | |
1359 | ||
8358c818 ILT |
1360 | On the r6000 and r4000 loading a coprocessor register |
1361 | from memory is interlocked, and does not require a delay. | |
1362 | ||
becfe05e ILT |
1363 | This case is not handled very well. There is no special |
1364 | knowledge of CP0 handling, and the coprocessors other | |
1365 | than the floating point unit are not distinguished at | |
1366 | all. */ | |
efec4a28 DP |
1367 | /* Itbl support may require additional care here. FIXME! |
1368 | Need to modify this to include knowledge about | |
1369 | user specified delays! */ | |
1aa6938e | 1370 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1371 | { |
0aa07269 ILT |
1372 | if (mips_optimize == 0 |
1373 | || insn_uses_reg (ip, | |
8358c818 ILT |
1374 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1375 | & OP_MASK_FT), | |
cc5703cd | 1376 | MIPS_FP_REG)) |
becfe05e ILT |
1377 | ++nops; |
1378 | } | |
1aa6938e | 1379 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1380 | { |
0aa07269 ILT |
1381 | if (mips_optimize == 0 |
1382 | || insn_uses_reg (ip, | |
8358c818 ILT |
1383 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1384 | & OP_MASK_FS), | |
cc5703cd | 1385 | MIPS_FP_REG)) |
becfe05e ILT |
1386 | ++nops; |
1387 | } | |
1388 | else | |
1389 | { | |
1390 | /* We don't know exactly what the previous instruction | |
1391 | does. If the current instruction uses a coprocessor | |
1392 | register, we must insert a NOP. If previous | |
1393 | instruction may set the condition codes, and the | |
1394 | current instruction uses them, we must insert two | |
1395 | NOPS. */ | |
efec4a28 | 1396 | /* Itbl support may require additional care here. */ |
0aa07269 | 1397 | if (mips_optimize == 0 |
1aa6938e ILT |
1398 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1399 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1400 | nops += 2; |
1aa6938e | 1401 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1402 | ++nops; |
1403 | } | |
1404 | } | |
cc5703cd ILT |
1405 | else if (! mips16 |
1406 | && mips_isa < 4 | |
344a8d61 JSC |
1407 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1408 | && ! cop_interlocks) | |
becfe05e ILT |
1409 | { |
1410 | /* The previous instruction sets the coprocessor condition | |
1411 | codes, but does not require a general coprocessor delay | |
1412 | (this means it is a floating point comparison | |
1413 | instruction). If this instruction uses the condition | |
1414 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1415 | /* Itbl support may require additional care here. */ |
0aa07269 | 1416 | if (mips_optimize == 0 |
1aa6938e | 1417 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1418 | ++nops; |
1419 | } | |
1aa6938e | 1420 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1421 | { |
1422 | /* The previous instruction reads the LO register; if the | |
1423 | current instruction writes to the LO register, we must | |
517078c1 | 1424 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1425 | if (! interlocks |
b2b8c24e ILT |
1426 | && (mips_optimize == 0 |
1427 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1428 | nops += 2; |
1429 | } | |
1430 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1431 | { | |
1432 | /* The previous instruction reads the HI register; if the | |
1433 | current instruction writes to the HI register, we must | |
517078c1 | 1434 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1435 | if (! interlocks |
b2b8c24e ILT |
1436 | && (mips_optimize == 0 |
1437 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1438 | nops += 2; |
1439 | } | |
1440 | ||
4a1cb507 ILT |
1441 | /* If the previous instruction was in a noreorder section, then |
1442 | we don't want to insert the nop after all. */ | |
efec4a28 | 1443 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1444 | if (prev_insn_unreordered) |
1445 | nops = 0; | |
1446 | ||
becfe05e ILT |
1447 | /* There are two cases which require two intervening |
1448 | instructions: 1) setting the condition codes using a move to | |
1449 | coprocessor instruction which requires a general coprocessor | |
1450 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1451 | or LO register and then writing to it (except on processors |
1452 | which have interlocks). If we are not already emitting a NOP | |
1453 | instruction, we must check for these cases compared to the | |
1454 | instruction previous to the previous instruction. */ | |
4a1cb507 ILT |
1455 | if ((! mips16 |
1456 | && mips_isa < 4 | |
1457 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) | |
1458 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1459 | && (pinfo & INSN_READ_COND_CODE) | |
1460 | && ! cop_interlocks) | |
1461 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1462 | && (pinfo & INSN_WRITE_LO) | |
1463 | && ! interlocks) | |
1464 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1465 | && (pinfo & INSN_WRITE_HI) | |
1466 | && ! interlocks)) | |
1467 | prev_prev_nop = 1; | |
1468 | else | |
1469 | prev_prev_nop = 0; | |
1470 | ||
1471 | if (prev_prev_insn_unreordered) | |
1472 | prev_prev_nop = 0; | |
1473 | ||
1474 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1475 | ++nops; |
1476 | ||
0dd2d296 ILT |
1477 | /* If we are being given a nop instruction, don't bother with |
1478 | one of the nops we would otherwise output. This will only | |
1479 | happen when a nop instruction is used with mips_optimize set | |
1480 | to 0. */ | |
4a1cb507 ILT |
1481 | if (nops > 0 |
1482 | && ! mips_noreorder | |
1483 | && ip->insn_opcode == (mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1484 | --nops; |
1485 | ||
becfe05e | 1486 | /* Now emit the right number of NOP instructions. */ |
4a1cb507 | 1487 | if (nops > 0 && ! mips_noreorder) |
becfe05e | 1488 | { |
5af96dce ILT |
1489 | fragS *old_frag; |
1490 | unsigned long old_frag_offset; | |
8c63448a | 1491 | int i; |
fbcfacb7 | 1492 | struct insn_label_list *l; |
8c63448a | 1493 | |
5af96dce ILT |
1494 | old_frag = frag_now; |
1495 | old_frag_offset = frag_now_fix (); | |
1496 | ||
8c63448a | 1497 | for (i = 0; i < nops; i++) |
becfe05e | 1498 | emit_nop (); |
5af96dce | 1499 | |
af255ca0 | 1500 | if (listing) |
546f5536 ILT |
1501 | { |
1502 | listing_prev_line (); | |
1503 | /* We may be at the start of a variant frag. In case we | |
1504 | are, make sure there is enough space for the frag | |
1505 | after the frags created by listing_prev_line. The | |
1506 | argument to frag_grow here must be at least as large | |
1507 | as the argument to all other calls to frag_grow in | |
1508 | this file. We don't have to worry about being in the | |
1509 | middle of a variant frag, because the variants insert | |
1510 | all needed nop instructions themselves. */ | |
1511 | frag_grow (40); | |
1512 | } | |
5af96dce | 1513 | |
fbcfacb7 | 1514 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1515 | { |
fbcfacb7 ILT |
1516 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1517 | l->label->sy_frag = frag_now; | |
1518 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1519 | /* mips16 text labels are stored as odd. */ | |
1520 | if (mips16) | |
1521 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1522 | } |
5af96dce ILT |
1523 | |
1524 | #ifndef NO_ECOFF_DEBUGGING | |
1525 | if (ECOFF_DEBUGGING) | |
1526 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1527 | #endif | |
becfe05e | 1528 | } |
4a1cb507 ILT |
1529 | else if (prev_nop_frag != NULL) |
1530 | { | |
1531 | /* We have a frag holding nops we may be able to remove. If | |
1532 | we don't need any nops, we can decrease the size of | |
1533 | prev_nop_frag by the size of one instruction. If we do | |
1534 | need some nops, we count them in prev_nops_required. */ | |
1535 | if (prev_nop_frag_since == 0) | |
1536 | { | |
1537 | if (nops == 0) | |
1538 | { | |
1539 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1540 | --prev_nop_frag_holds; | |
1541 | } | |
1542 | else | |
1543 | prev_nop_frag_required += nops; | |
1544 | } | |
1545 | else | |
1546 | { | |
1547 | if (prev_prev_nop == 0) | |
1548 | { | |
1549 | prev_nop_frag->fr_fix -= mips16 ? 2 : 4; | |
1550 | --prev_nop_frag_holds; | |
1551 | } | |
1552 | else | |
1553 | ++prev_nop_frag_required; | |
1554 | } | |
1555 | ||
1556 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1557 | prev_nop_frag = NULL; | |
1558 | ||
1559 | ++prev_nop_frag_since; | |
1560 | ||
1561 | /* Sanity check: by the time we reach the second instruction | |
1562 | after prev_nop_frag, we should have used up all the nops | |
1563 | one way or another. */ | |
1564 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1565 | } | |
becfe05e | 1566 | } |
4a1cb507 | 1567 | |
cc5703cd ILT |
1568 | if (reloc_type > BFD_RELOC_UNUSED) |
1569 | { | |
1570 | /* We need to set up a variant frag. */ | |
1571 | assert (mips16 && address_expr != NULL); | |
1572 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1573 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1574 | mips16_small, mips16_ext, |
1575 | (prev_pinfo | |
1576 | & INSN_UNCOND_BRANCH_DELAY), | |
1577 | (prev_insn_reloc_type | |
1578 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1579 | make_expr_symbol (address_expr), (long) 0, |
1580 | (char *) NULL); | |
1581 | } | |
1582 | else if (place != NULL) | |
0dd2d296 | 1583 | f = place; |
cc5703cd | 1584 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1585 | { |
1586 | /* Make sure there is enough room to swap this instruction with | |
1587 | a following jump instruction. */ | |
1588 | frag_grow (6); | |
1589 | f = frag_more (2); | |
1590 | } | |
cc5703cd | 1591 | else |
035936da ILT |
1592 | { |
1593 | if (mips16 | |
1594 | && mips_noreorder | |
1595 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1596 | as_warn ("extended instruction in delay slot"); | |
1597 | ||
1598 | f = frag_more (4); | |
1599 | } | |
1600 | ||
becfe05e | 1601 | fixp = NULL; |
cc5703cd | 1602 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1603 | { |
5ac34ac3 | 1604 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1605 | { |
1606 | switch (reloc_type) | |
1607 | { | |
3d3c5039 | 1608 | case BFD_RELOC_32: |
670a50eb ILT |
1609 | ip->insn_opcode |= address_expr->X_add_number; |
1610 | break; | |
3d3c5039 ILT |
1611 | |
1612 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1613 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1614 | break; | |
3d3c5039 ILT |
1615 | |
1616 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1617 | if ((address_expr->X_add_number & 3) != 0) |
1618 | as_bad ("jump to misaligned address (0x%lx)", | |
1619 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1620 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1621 | break; | |
1622 | ||
cc5703cd | 1623 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1624 | if ((address_expr->X_add_number & 3) != 0) |
1625 | as_bad ("jump to misaligned address (0x%lx)", | |
1626 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1627 | ip->insn_opcode |= |
1628 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1629 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1630 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1631 | break; | |
1632 | ||
3d3c5039 | 1633 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1634 | goto need_reloc; |
3d3c5039 ILT |
1635 | |
1636 | default: | |
670a50eb | 1637 | internalError (); |
3d3c5039 | 1638 | } |
670a50eb ILT |
1639 | } |
1640 | else | |
1641 | { | |
3d3c5039 | 1642 | need_reloc: |
0dd2d296 ILT |
1643 | /* Don't generate a reloc if we are writing into a variant |
1644 | frag. */ | |
1645 | if (place == NULL) | |
867a58b3 ILT |
1646 | { |
1647 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1648 | address_expr, | |
1649 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1650 | reloc_type); | |
1651 | if (unmatched_hi) | |
1652 | { | |
1653 | struct mips_hi_fixup *hi_fixup; | |
1654 | ||
1655 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1656 | hi_fixup = ((struct mips_hi_fixup *) | |
1657 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1658 | hi_fixup->fixp = fixp; | |
1659 | hi_fixup->seg = now_seg; | |
1660 | hi_fixup->next = mips_hi_fixup_list; | |
1661 | mips_hi_fixup_list = hi_fixup; | |
1662 | } | |
1663 | } | |
3d3c5039 ILT |
1664 | } |
1665 | } | |
becfe05e | 1666 | |
16262668 | 1667 | if (! mips16) |
cc5703cd | 1668 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1669 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1670 | { | |
1671 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1672 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1673 | } | |
cc5703cd ILT |
1674 | else |
1675 | { | |
1676 | if (ip->use_extend) | |
1677 | { | |
1678 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1679 | f += 2; | |
1680 | } | |
1681 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1682 | } | |
670a50eb | 1683 | |
1aa6938e | 1684 | /* Update the register mask information. */ |
cc5703cd ILT |
1685 | if (! mips16) |
1686 | { | |
1687 | if (pinfo & INSN_WRITE_GPR_D) | |
1688 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1689 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1690 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1691 | if (pinfo & INSN_READ_GPR_S) | |
1692 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1693 | if (pinfo & INSN_WRITE_GPR_31) | |
1694 | mips_gprmask |= 1 << 31; | |
1695 | if (pinfo & INSN_WRITE_FPR_D) | |
1696 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1697 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1698 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1699 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1700 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1701 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1702 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1703 | if (pinfo & INSN_COP) | |
1704 | { | |
efec4a28 DP |
1705 | /* We don't keep enough information to sort these cases out. |
1706 | The itbl support does keep this information however, although | |
1707 | we currently don't support itbl fprmats as part of the cop | |
1708 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1709 | } |
1710 | /* Never set the bit for $0, which is always zero. */ | |
1711 | mips_gprmask &=~ 1 << 0; | |
1712 | } | |
1713 | else | |
1aa6938e | 1714 | { |
cc5703cd ILT |
1715 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1716 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1717 | & MIPS16OP_MASK_RX); | |
1718 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1719 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1720 | & MIPS16OP_MASK_RY); | |
1721 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1722 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1723 | & MIPS16OP_MASK_RZ); | |
1724 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1725 | mips_gprmask |= 1 << TREG; | |
1726 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1727 | mips_gprmask |= 1 << SP; | |
1728 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1729 | mips_gprmask |= 1 << RA; | |
1730 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1731 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1732 | if (pinfo & MIPS16_INSN_READ_Z) | |
1733 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1734 | & MIPS16OP_MASK_MOVE32Z); | |
1735 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1736 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1737 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1738 | } |
1aa6938e | 1739 | |
0dd2d296 | 1740 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1741 | { |
becfe05e ILT |
1742 | /* Filling the branch delay slot is more complex. We try to |
1743 | switch the branch with the previous instruction, which we can | |
1744 | do if the previous instruction does not set up a condition | |
1745 | that the branch tests and if the branch is not itself the | |
1746 | target of any branch. */ | |
1aa6938e ILT |
1747 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1748 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1749 | { |
0aa07269 | 1750 | if (mips_optimize < 2 |
19ed8960 ILT |
1751 | /* If we have seen .set volatile or .set nomove, don't |
1752 | optimize. */ | |
1753 | || mips_nomove != 0 | |
4e95866e ILT |
1754 | /* If we had to emit any NOP instructions, then we |
1755 | already know we can not swap. */ | |
1756 | || nops != 0 | |
becfe05e ILT |
1757 | /* If we don't even know the previous insn, we can not |
1758 | swap. */ | |
1759 | || ! prev_insn_valid | |
1760 | /* If the previous insn is already in a branch delay | |
1761 | slot, then we can not swap. */ | |
1762 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1763 | /* If the previous previous insn was in a .set |
1764 | noreorder, we can't swap. Actually, the MIPS | |
1765 | assembler will swap in this situation. However, gcc | |
1766 | configured -with-gnu-as will generate code like | |
1767 | .set noreorder | |
1768 | lw $4,XXX | |
1769 | .set reorder | |
1770 | INSN | |
1771 | bne $4,$0,foo | |
1772 | in which we can not swap the bne and INSN. If gcc is | |
1773 | not configured -with-gnu-as, it does not output the | |
1774 | .set pseudo-ops. We don't have to check | |
1775 | prev_insn_unreordered, because prev_insn_valid will | |
1776 | be 0 in that case. We don't want to use | |
1777 | prev_prev_insn_valid, because we do want to be able | |
1778 | to swap at the start of a function. */ | |
1779 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1780 | /* If the branch is itself the target of a branch, we |
1781 | can not swap. We cheat on this; all we check for is | |
1782 | whether there is a label on this instruction. If | |
1783 | there are any branches to anything other than a | |
1784 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1785 | || insn_labels != NULL |
777ad64d | 1786 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1787 | can not do the swap. This does not apply to the |
1788 | mips16, which uses variant frags for different | |
1789 | purposes. */ | |
1790 | || (! mips16 | |
1791 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1792 | /* If the branch reads the condition codes, we don't |
1793 | even try to swap, because in the sequence | |
1794 | ctc1 $X,$31 | |
1795 | INSN | |
1796 | INSN | |
1797 | bc1t LABEL | |
1798 | we can not swap, and I don't feel like handling that | |
1799 | case. */ | |
cc5703cd ILT |
1800 | || (! mips16 |
1801 | && mips_isa < 4 | |
d8a1c247 | 1802 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1803 | /* We can not swap with an instruction that requires a |
1804 | delay slot, becase the target of the branch might | |
1805 | interfere with that instruction. */ | |
cc5703cd ILT |
1806 | || (! mips16 |
1807 | && mips_isa < 4 | |
d8a1c247 | 1808 | && (prev_pinfo |
efec4a28 | 1809 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1810 | & (INSN_LOAD_COPROC_DELAY |
1811 | | INSN_COPROC_MOVE_DELAY | |
1812 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1813 | || (! interlocks |
b2b8c24e ILT |
1814 | && (prev_pinfo |
1815 | & (INSN_READ_LO | |
1816 | | INSN_READ_HI))) | |
cc5703cd ILT |
1817 | || (! mips16 |
1818 | && mips_isa < 2 | |
1aa6938e | 1819 | && (prev_pinfo |
8358c818 | 1820 | & (INSN_LOAD_MEMORY_DELAY |
efec4a28 | 1821 | /* Itbl support may require additional care here. */ |
8358c818 | 1822 | | INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 1823 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1824 | || (prev_pinfo |
6e8dda9c ILT |
1825 | & (INSN_UNCOND_BRANCH_DELAY |
1826 | | INSN_COND_BRANCH_DELAY | |
1827 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1828 | /* We do not swap with a trap instruction, since it |
1829 | complicates trap handlers to have the trap | |
1830 | instruction be in a delay slot. */ | |
1aa6938e | 1831 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1832 | /* If the branch reads a register that the previous |
1833 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1834 | || (! mips16 |
1835 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1836 | && insn_uses_reg (ip, |
1837 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1838 | & OP_MASK_RT), | |
cc5703cd ILT |
1839 | MIPS_GR_REG)) |
1840 | || (! mips16 | |
1841 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1842 | && insn_uses_reg (ip, |
1843 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1844 | & OP_MASK_RD), | |
cc5703cd ILT |
1845 | MIPS_GR_REG)) |
1846 | || (mips16 | |
1847 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1848 | && insn_uses_reg (ip, | |
1849 | ((prev_insn.insn_opcode | |
1850 | >> MIPS16OP_SH_RX) | |
1851 | & MIPS16OP_MASK_RX), | |
1852 | MIPS16_REG)) | |
1853 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1854 | && insn_uses_reg (ip, | |
1855 | ((prev_insn.insn_opcode | |
1856 | >> MIPS16OP_SH_RY) | |
1857 | & MIPS16OP_MASK_RY), | |
1858 | MIPS16_REG)) | |
1859 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1860 | && insn_uses_reg (ip, | |
1861 | ((prev_insn.insn_opcode | |
1862 | >> MIPS16OP_SH_RZ) | |
1863 | & MIPS16OP_MASK_RZ), | |
1864 | MIPS16_REG)) | |
1865 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1866 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1867 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1868 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1869 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1870 | && insn_uses_reg (ip, | |
1871 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1872 | insn_opcode), | |
1873 | MIPS_GR_REG)))) | |
1849d646 ILT |
1874 | /* If the branch writes a register that the previous |
1875 | instruction sets, we can not swap (we know that | |
1876 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1877 | || (! mips16 |
1878 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1879 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1880 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1881 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1882 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1883 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1884 | & OP_MASK_RT) | |
1885 | == 31)))) | |
cc5703cd ILT |
1886 | || (! mips16 |
1887 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1888 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1889 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1890 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1891 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1892 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1893 | & OP_MASK_RD) | |
1894 | == 31)))) | |
cc5703cd ILT |
1895 | || (mips16 |
1896 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1897 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1898 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1899 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1900 | == RA)))) | |
becfe05e ILT |
1901 | /* If the branch writes a register that the previous |
1902 | instruction reads, we can not swap (we know that | |
1903 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1904 | || (! mips16 |
1905 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1906 | && insn_uses_reg (&prev_insn, |
1907 | ((ip->insn_opcode >> OP_SH_RD) | |
1908 | & OP_MASK_RD), | |
cc5703cd ILT |
1909 | MIPS_GR_REG)) |
1910 | || (! mips16 | |
1911 | && (pinfo & INSN_WRITE_GPR_31) | |
1912 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1913 | || (mips16 | |
1914 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1915 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1916 | /* If we are generating embedded PIC code, the branch |
1917 | might be expanded into a sequence which uses $at, so | |
1918 | we can't swap with an instruction which reads it. */ | |
1919 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1920 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1921 | /* If the previous previous instruction has a load |
1922 | delay, and sets a register that the branch reads, we | |
1923 | can not swap. */ | |
cc5703cd ILT |
1924 | || (! mips16 |
1925 | && mips_isa < 4 | |
efec4a28 | 1926 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1927 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1928 | || (mips_isa < 2 | |
1929 | && (prev_prev_insn.insn_mo->pinfo | |
1930 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1931 | && insn_uses_reg (ip, |
1932 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1933 | & OP_MASK_RT), | |
cc5703cd | 1934 | MIPS_GR_REG)) |
d31a3f5e ILT |
1935 | /* If one instruction sets a condition code and the |
1936 | other one uses a condition code, we can not swap. */ | |
1937 | || ((pinfo & INSN_READ_COND_CODE) | |
1938 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1939 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1940 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1941 | /* If the previous instruction uses the PC, we can not | |
1942 | swap. */ | |
1943 | || (mips16 | |
1944 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1945 | /* If the previous instruction was extended, we can not | |
1946 | swap. */ | |
1947 | || (mips16 && prev_insn_extended) | |
1948 | /* If the previous instruction had a fixup in mips16 | |
1949 | mode, we can not swap. This normally means that the | |
1950 | previous instruction was a 4 byte branch anyhow. */ | |
1951 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1952 | { |
1953 | /* We could do even better for unconditional branches to | |
1954 | portions of this object file; we could pick up the | |
1955 | instruction at the destination, put it in the delay | |
1956 | slot, and bump the destination address. */ | |
1957 | emit_nop (); | |
1958 | /* Update the previous insn information. */ | |
1959 | prev_prev_insn = *ip; | |
1960 | prev_insn.insn_mo = &dummy_opcode; | |
1961 | } | |
1962 | else | |
1963 | { | |
becfe05e | 1964 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1965 | if (! mips16) |
1966 | { | |
1967 | char *prev_f; | |
1968 | char temp[4]; | |
1969 | ||
1970 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1971 | memcpy (temp, prev_f, 4); | |
1972 | memcpy (prev_f, f, 4); | |
1973 | memcpy (f, temp, 4); | |
1974 | if (prev_insn_fixp) | |
1975 | { | |
1976 | prev_insn_fixp->fx_frag = frag_now; | |
1977 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1978 | } | |
1979 | if (fixp) | |
1980 | { | |
1981 | fixp->fx_frag = prev_insn_frag; | |
1982 | fixp->fx_where = prev_insn_where; | |
1983 | } | |
1984 | } | |
cc5703cd | 1985 | else |
becfe05e | 1986 | { |
cc5703cd ILT |
1987 | char *prev_f; |
1988 | char temp[2]; | |
1989 | ||
1990 | assert (prev_insn_fixp == NULL); | |
1991 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1992 | memcpy (temp, prev_f, 2); | |
1993 | memcpy (prev_f, f, 2); | |
1994 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
1995 | { |
1996 | assert (reloc_type == BFD_RELOC_UNUSED); | |
1997 | memcpy (f, temp, 2); | |
1998 | } | |
cc5703cd ILT |
1999 | else |
2000 | { | |
2001 | memcpy (f, f + 2, 2); | |
2002 | memcpy (f + 2, temp, 2); | |
2003 | } | |
2004 | if (fixp) | |
2005 | { | |
2006 | fixp->fx_frag = prev_insn_frag; | |
2007 | fixp->fx_where = prev_insn_where; | |
2008 | } | |
becfe05e | 2009 | } |
cc5703cd | 2010 | |
becfe05e ILT |
2011 | /* Update the previous insn information; leave prev_insn |
2012 | unchanged. */ | |
2013 | prev_prev_insn = *ip; | |
2014 | } | |
2015 | prev_insn_is_delay_slot = 1; | |
2016 | ||
2017 | /* If that was an unconditional branch, forget the previous | |
2018 | insn information. */ | |
1aa6938e | 2019 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2020 | { |
2021 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2022 | prev_insn.insn_mo = &dummy_opcode; | |
2023 | } | |
a677feeb ILT |
2024 | |
2025 | prev_insn_fixp = NULL; | |
2026 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2027 | prev_insn_extended = 0; | |
becfe05e | 2028 | } |
1aa6938e | 2029 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2030 | { |
2031 | /* We don't yet optimize a branch likely. What we should do | |
2032 | is look at the target, copy the instruction found there | |
2033 | into the delay slot, and increment the branch to jump to | |
2034 | the next instruction. */ | |
2035 | emit_nop (); | |
2036 | /* Update the previous insn information. */ | |
2037 | prev_prev_insn = *ip; | |
2038 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2039 | prev_insn_fixp = NULL; |
2040 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2041 | prev_insn_extended = 0; | |
8358c818 | 2042 | } |
becfe05e | 2043 | else |
670a50eb | 2044 | { |
becfe05e ILT |
2045 | /* Update the previous insn information. */ |
2046 | if (nops > 0) | |
2047 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2048 | else | |
2049 | prev_prev_insn = prev_insn; | |
2050 | prev_insn = *ip; | |
2051 | ||
2052 | /* Any time we see a branch, we always fill the delay slot | |
2053 | immediately; since this insn is not a branch, we know it | |
2054 | is not in a delay slot. */ | |
2055 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2056 | |
2057 | prev_insn_fixp = fixp; | |
2058 | prev_insn_reloc_type = reloc_type; | |
2059 | if (mips16) | |
2060 | prev_insn_extended = (ip->use_extend | |
2061 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2062 | } |
2063 | ||
4e95866e ILT |
2064 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2065 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2066 | prev_insn_frag = frag_now; |
2067 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2068 | prev_insn_valid = 1; |
2069 | } | |
fbcfacb7 | 2070 | else if (place == NULL) |
a677feeb | 2071 | { |
fbcfacb7 | 2072 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2073 | reordering, in order to determine the base address for mips16 |
2074 | PC relative relocs. */ | |
4a1cb507 | 2075 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2076 | prev_insn = *ip; |
2077 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2078 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2079 | prev_insn_unreordered = 1; | |
a677feeb | 2080 | } |
3d3c5039 | 2081 | |
becfe05e | 2082 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2083 | mips_clear_insn_labels (); |
becfe05e ILT |
2084 | } |
2085 | ||
2086 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2087 | label. If PRESERVE is non-zero, it remembers enough information to |
2088 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2089 | |
2090 | static void | |
4a1cb507 ILT |
2091 | mips_no_prev_insn (preserve) |
2092 | int preserve; | |
becfe05e | 2093 | { |
4a1cb507 ILT |
2094 | if (! preserve) |
2095 | { | |
2096 | prev_insn.insn_mo = &dummy_opcode; | |
2097 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2098 | prev_nop_frag = NULL; | |
2099 | prev_nop_frag_holds = 0; | |
2100 | prev_nop_frag_required = 0; | |
2101 | prev_nop_frag_since = 0; | |
2102 | } | |
becfe05e ILT |
2103 | prev_insn_valid = 0; |
2104 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2105 | prev_insn_unreordered = 0; |
cc5703cd | 2106 | prev_insn_extended = 0; |
a677feeb | 2107 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2108 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2109 | mips_clear_insn_labels (); |
becfe05e ILT |
2110 | } |
2111 | ||
2112 | /* This function must be called whenever we turn on noreorder or emit | |
2113 | something other than instructions. It inserts any NOPS which might | |
2114 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2115 | kept for the previous instructions. The INSNS parameter is true if |
2116 | instructions are to follow. */ | |
becfe05e ILT |
2117 | |
2118 | static void | |
fbcfacb7 ILT |
2119 | mips_emit_delays (insns) |
2120 | boolean insns; | |
becfe05e ILT |
2121 | { |
2122 | if (! mips_noreorder) | |
2123 | { | |
4a1cb507 | 2124 | int nops; |
becfe05e | 2125 | |
4a1cb507 | 2126 | nops = 0; |
cc5703cd ILT |
2127 | if ((! mips16 |
2128 | && mips_isa < 4 | |
344a8d61 JSC |
2129 | && (! cop_interlocks |
2130 | && (prev_insn.insn_mo->pinfo | |
2131 | & (INSN_LOAD_COPROC_DELAY | |
2132 | | INSN_COPROC_MOVE_DELAY | |
2133 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 2134 | || (! interlocks |
b2b8c24e ILT |
2135 | && (prev_insn.insn_mo->pinfo |
2136 | & (INSN_READ_LO | |
2137 | | INSN_READ_HI))) | |
cc5703cd ILT |
2138 | || (! mips16 |
2139 | && mips_isa < 2 | |
8358c818 ILT |
2140 | && (prev_insn.insn_mo->pinfo |
2141 | & (INSN_LOAD_MEMORY_DELAY | |
2142 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e | 2143 | { |
efec4a28 | 2144 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2145 | ++nops; |
cc5703cd ILT |
2146 | if ((! mips16 |
2147 | && mips_isa < 4 | |
344a8d61 JSC |
2148 | && (! cop_interlocks |
2149 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2150 | || (! interlocks |
b2b8c24e ILT |
2151 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2152 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2153 | ++nops; |
2154 | ||
2155 | if (prev_insn_unreordered) | |
2156 | nops = 0; | |
becfe05e | 2157 | } |
cc5703cd ILT |
2158 | else if ((! mips16 |
2159 | && mips_isa < 4 | |
344a8d61 JSC |
2160 | && (! cop_interlocks |
2161 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2162 | || (! interlocks |
b2b8c24e ILT |
2163 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2164 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2165 | { |
efec4a28 | 2166 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2167 | if (! prev_prev_insn_unreordered) |
2168 | ++nops; | |
2169 | } | |
2170 | ||
2171 | if (nops > 0) | |
670a50eb | 2172 | { |
fbcfacb7 ILT |
2173 | struct insn_label_list *l; |
2174 | ||
4a1cb507 ILT |
2175 | if (insns) |
2176 | { | |
2177 | /* Record the frag which holds the nop instructions, so | |
2178 | that we can remove them if we don't need them. */ | |
2179 | frag_grow (mips16 ? nops * 2 : nops * 4); | |
2180 | prev_nop_frag = frag_now; | |
2181 | prev_nop_frag_holds = nops; | |
2182 | prev_nop_frag_required = 0; | |
2183 | prev_nop_frag_since = 0; | |
2184 | } | |
2185 | ||
2186 | for (; nops > 0; --nops) | |
2187 | emit_nop (); | |
2188 | ||
2189 | if (insns) | |
2190 | { | |
2191 | /* Move on to a new frag, so that it is safe to simply | |
2192 | decrease the size of prev_nop_frag. */ | |
2193 | frag_wane (frag_now); | |
2194 | frag_new (0); | |
2195 | } | |
2196 | ||
fbcfacb7 | 2197 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2198 | { |
fbcfacb7 ILT |
2199 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2200 | l->label->sy_frag = frag_now; | |
2201 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2202 | /* mips16 text labels are stored as odd. */ | |
2203 | if (mips16) | |
2204 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2205 | } |
3d3c5039 ILT |
2206 | } |
2207 | } | |
0221ddf7 | 2208 | |
fbcfacb7 ILT |
2209 | /* Mark instruction labels in mips16 mode. This permits the linker |
2210 | to handle them specially, such as generating jalx instructions | |
2211 | when needed. We also make them odd for the duration of the | |
2212 | assembly, in order to generate the right sort of code. We will | |
2213 | make them even in the adjust_symtab routine, while leaving them | |
2214 | marked. This is convenient for the debugger and the | |
2215 | disassembler. The linker knows to make them odd again. */ | |
2216 | if (mips16 && insns) | |
2217 | { | |
2218 | struct insn_label_list *l; | |
2219 | ||
2220 | for (l = insn_labels; l != NULL; l = l->next) | |
2221 | { | |
2222 | #ifdef S_SET_OTHER | |
2223 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2224 | S_SET_OTHER (l->label, STO_MIPS16); | |
2225 | #endif | |
2226 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2227 | ++l->label->sy_value.X_add_number; | |
2228 | } | |
2229 | } | |
2230 | ||
4a1cb507 | 2231 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2232 | } |
2233 | ||
670a50eb ILT |
2234 | /* Build an instruction created by a macro expansion. This is passed |
2235 | a pointer to the count of instructions created so far, an | |
2236 | expression, the name of the instruction to build, an operand format | |
2237 | string, and corresponding arguments. */ | |
2238 | ||
1dc1e798 | 2239 | #ifdef USE_STDARG |
3d3c5039 | 2240 | static void |
0dd2d296 ILT |
2241 | macro_build (char *place, |
2242 | int *counter, | |
670a50eb | 2243 | expressionS * ep, |
3d3c5039 ILT |
2244 | const char *name, |
2245 | const char *fmt, | |
2246 | ...) | |
1dc1e798 | 2247 | #else |
3d3c5039 | 2248 | static void |
0dd2d296 ILT |
2249 | macro_build (place, counter, ep, name, fmt, va_alist) |
2250 | char *place; | |
3d3c5039 ILT |
2251 | int *counter; |
2252 | expressionS *ep; | |
2253 | const char *name; | |
2254 | const char *fmt; | |
2255 | va_dcl | |
1dc1e798 | 2256 | #endif |
3d3c5039 | 2257 | { |
670a50eb ILT |
2258 | struct mips_cl_insn insn; |
2259 | bfd_reloc_code_real_type r; | |
2260 | va_list args; | |
3d3c5039 | 2261 | |
1dc1e798 | 2262 | #ifdef USE_STDARG |
670a50eb | 2263 | va_start (args, fmt); |
3d3c5039 | 2264 | #else |
670a50eb | 2265 | va_start (args); |
3d3c5039 ILT |
2266 | #endif |
2267 | ||
670a50eb ILT |
2268 | /* |
2269 | * If the macro is about to expand into a second instruction, | |
2270 | * print a warning if needed. We need to pass ip as a parameter | |
2271 | * to generate a better warning message here... | |
2272 | */ | |
0dd2d296 | 2273 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2274 | as_warn ("Macro instruction expanded into multiple instructions"); |
2275 | ||
0dd2d296 ILT |
2276 | if (place == NULL) |
2277 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2278 | |
cc5703cd ILT |
2279 | if (mips16) |
2280 | { | |
2281 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2282 | va_end (args); | |
2283 | return; | |
2284 | } | |
2285 | ||
670a50eb ILT |
2286 | r = BFD_RELOC_UNUSED; |
2287 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2288 | assert (insn.insn_mo); | |
2289 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2290 | ||
9226253a | 2291 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2292 | || insn.insn_mo->pinfo == INSN_MACRO |
2293 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2294 | && mips_isa < 2) | |
2295 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2296 | && mips_isa < 3) | |
2297 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2298 | && mips_isa < 4) | |
2299 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2300 | && ! mips_4650) | |
2301 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2302 | && ! mips_4010) | |
2303 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2304 | && ! mips_4100) |
2305 | /* start-sanitize-r5900 */ | |
2306 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2307 | && ! mips_5900) | |
2308 | /* end-sanitize-r5900 */ | |
2309 | ) | |
670a50eb ILT |
2310 | { |
2311 | ++insn.insn_mo; | |
2312 | assert (insn.insn_mo->name); | |
2313 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2314 | } |
670a50eb ILT |
2315 | insn.insn_opcode = insn.insn_mo->match; |
2316 | for (;;) | |
2317 | { | |
2318 | switch (*fmt++) | |
2319 | { | |
3d3c5039 | 2320 | case '\0': |
670a50eb | 2321 | break; |
3d3c5039 ILT |
2322 | |
2323 | case ',': | |
2324 | case '(': | |
2325 | case ')': | |
670a50eb | 2326 | continue; |
3d3c5039 ILT |
2327 | |
2328 | case 't': | |
2329 | case 'w': | |
918692a5 | 2330 | case 'E': |
670a50eb ILT |
2331 | insn.insn_opcode |= va_arg (args, int) << 16; |
2332 | continue; | |
3d3c5039 ILT |
2333 | |
2334 | case 'c': | |
2335 | case 'T': | |
2336 | case 'W': | |
670a50eb ILT |
2337 | insn.insn_opcode |= va_arg (args, int) << 16; |
2338 | continue; | |
3d3c5039 ILT |
2339 | |
2340 | case 'd': | |
918692a5 | 2341 | case 'G': |
670a50eb ILT |
2342 | insn.insn_opcode |= va_arg (args, int) << 11; |
2343 | continue; | |
3d3c5039 ILT |
2344 | |
2345 | case 'V': | |
2346 | case 'S': | |
670a50eb ILT |
2347 | insn.insn_opcode |= va_arg (args, int) << 11; |
2348 | continue; | |
3d3c5039 | 2349 | |
ff3a5c18 ILT |
2350 | case 'z': |
2351 | continue; | |
2352 | ||
3d3c5039 | 2353 | case '<': |
670a50eb ILT |
2354 | insn.insn_opcode |= va_arg (args, int) << 6; |
2355 | continue; | |
3d3c5039 ILT |
2356 | |
2357 | case 'D': | |
670a50eb ILT |
2358 | insn.insn_opcode |= va_arg (args, int) << 6; |
2359 | continue; | |
3d3c5039 | 2360 | |
918692a5 ILT |
2361 | case 'B': |
2362 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2363 | continue; | |
2364 | ||
3d3c5039 ILT |
2365 | case 'b': |
2366 | case 's': | |
2367 | case 'r': | |
2368 | case 'v': | |
670a50eb ILT |
2369 | insn.insn_opcode |= va_arg (args, int) << 21; |
2370 | continue; | |
3d3c5039 ILT |
2371 | |
2372 | case 'i': | |
2373 | case 'j': | |
2374 | case 'o': | |
9226253a | 2375 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2376 | assert (r == BFD_RELOC_MIPS_GPREL |
2377 | || r == BFD_RELOC_MIPS_LITERAL | |
2378 | || r == BFD_RELOC_LO16 | |
2379 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2380 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2381 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2382 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2383 | || (ep->X_op == O_subtract |
2384 | && now_seg == text_section | |
ecd4ca1c | 2385 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2386 | continue; |
3d3c5039 | 2387 | |
6e8dda9c | 2388 | case 'u': |
ecd4ca1c ILT |
2389 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2390 | assert (ep != NULL | |
2391 | && (ep->X_op == O_constant | |
2392 | || (ep->X_op == O_symbol | |
2393 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2394 | || r == BFD_RELOC_HI16 |
2395 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2396 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2397 | || (ep->X_op == O_subtract |
2398 | && now_seg == text_section | |
ecd4ca1c ILT |
2399 | && r == BFD_RELOC_PCREL_HI16_S))); |
2400 | if (ep->X_op == O_constant) | |
2401 | { | |
2402 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2403 | ep = NULL; | |
2404 | r = BFD_RELOC_UNUSED; | |
2405 | } | |
6e8dda9c ILT |
2406 | continue; |
2407 | ||
3d3c5039 | 2408 | case 'p': |
670a50eb ILT |
2409 | assert (ep != NULL); |
2410 | /* | |
2411 | * This allows macro() to pass an immediate expression for | |
2412 | * creating short branches without creating a symbol. | |
2413 | * Note that the expression still might come from the assembly | |
2414 | * input, in which case the value is not checked for range nor | |
2415 | * is a relocation entry generated (yuck). | |
2416 | */ | |
5ac34ac3 | 2417 | if (ep->X_op == O_constant) |
670a50eb ILT |
2418 | { |
2419 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2420 | ep = NULL; | |
2421 | } | |
2422 | else | |
2423 | r = BFD_RELOC_16_PCREL_S2; | |
2424 | continue; | |
3d3c5039 | 2425 | |
9226253a ILT |
2426 | case 'a': |
2427 | assert (ep != NULL); | |
2428 | r = BFD_RELOC_MIPS_JMP; | |
2429 | continue; | |
2430 | ||
3d3c5039 | 2431 | default: |
670a50eb | 2432 | internalError (); |
3d3c5039 | 2433 | } |
670a50eb | 2434 | break; |
3d3c5039 | 2435 | } |
670a50eb ILT |
2436 | va_end (args); |
2437 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2438 | ||
867a58b3 | 2439 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2440 | } |
2441 | ||
cc5703cd ILT |
2442 | static void |
2443 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2444 | char *place; | |
2445 | int *counter; | |
2446 | expressionS *ep; | |
2447 | const char *name; | |
2448 | const char *fmt; | |
2449 | va_list args; | |
2450 | { | |
2451 | struct mips_cl_insn insn; | |
2452 | bfd_reloc_code_real_type r; | |
2453 | ||
2454 | r = BFD_RELOC_UNUSED; | |
2455 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2456 | assert (insn.insn_mo); | |
2457 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2458 | ||
2459 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2460 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2461 | { | |
2462 | ++insn.insn_mo; | |
2463 | assert (insn.insn_mo->name); | |
2464 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2465 | } | |
2466 | ||
2467 | insn.insn_opcode = insn.insn_mo->match; | |
2468 | insn.use_extend = false; | |
2469 | ||
2470 | for (;;) | |
2471 | { | |
2472 | int c; | |
2473 | ||
2474 | c = *fmt++; | |
2475 | switch (c) | |
2476 | { | |
2477 | case '\0': | |
2478 | break; | |
2479 | ||
2480 | case ',': | |
2481 | case '(': | |
2482 | case ')': | |
2483 | continue; | |
2484 | ||
2485 | case 'y': | |
2486 | case 'w': | |
2487 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2488 | continue; | |
2489 | ||
2490 | case 'x': | |
2491 | case 'v': | |
2492 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2493 | continue; | |
2494 | ||
2495 | case 'z': | |
2496 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2497 | continue; | |
2498 | ||
2499 | case 'Z': | |
2500 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2501 | continue; | |
2502 | ||
2503 | case '0': | |
2504 | case 'S': | |
2505 | case 'P': | |
2506 | case 'R': | |
2507 | continue; | |
2508 | ||
2509 | case 'X': | |
2510 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2511 | continue; | |
2512 | ||
2513 | case 'Y': | |
2514 | { | |
2515 | int regno; | |
2516 | ||
2517 | regno = va_arg (args, int); | |
2518 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2519 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2520 | } | |
2521 | continue; | |
2522 | ||
2523 | case '<': | |
2524 | case '>': | |
2525 | case '4': | |
2526 | case '5': | |
2527 | case 'H': | |
2528 | case 'W': | |
2529 | case 'D': | |
2530 | case 'j': | |
2531 | case '8': | |
2532 | case 'V': | |
2533 | case 'C': | |
2534 | case 'U': | |
2535 | case 'k': | |
2536 | case 'K': | |
2537 | case 'p': | |
2538 | case 'q': | |
2539 | { | |
2540 | assert (ep != NULL); | |
2541 | ||
2542 | if (ep->X_op != O_constant) | |
2543 | r = BFD_RELOC_UNUSED + c; | |
2544 | else | |
2545 | { | |
15e69f98 ILT |
2546 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2547 | false, false, &insn.insn_opcode, | |
2548 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2549 | ep = NULL; |
2550 | r = BFD_RELOC_UNUSED; | |
2551 | } | |
2552 | } | |
2553 | continue; | |
2554 | ||
2555 | case '6': | |
2556 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2557 | continue; | |
2558 | } | |
2559 | ||
2560 | break; | |
2561 | } | |
2562 | ||
2563 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2564 | ||
2565 | append_insn (place, &insn, ep, r, false); | |
2566 | } | |
2567 | ||
3d3c5039 ILT |
2568 | /* |
2569 | * Generate a "lui" instruction. | |
2570 | */ | |
2571 | static void | |
0dd2d296 ILT |
2572 | macro_build_lui (place, counter, ep, regnum) |
2573 | char *place; | |
3d3c5039 ILT |
2574 | int *counter; |
2575 | expressionS *ep; | |
2576 | int regnum; | |
2577 | { | |
670a50eb ILT |
2578 | expressionS high_expr; |
2579 | struct mips_cl_insn insn; | |
2580 | bfd_reloc_code_real_type r; | |
2581 | CONST char *name = "lui"; | |
2582 | CONST char *fmt = "t,u"; | |
2583 | ||
cc5703cd ILT |
2584 | assert (! mips16); |
2585 | ||
0dd2d296 ILT |
2586 | if (place == NULL) |
2587 | high_expr = *ep; | |
2588 | else | |
2589 | { | |
2590 | high_expr.X_op = O_constant; | |
fb251650 | 2591 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2592 | } |
670a50eb | 2593 | |
5ac34ac3 | 2594 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2595 | { |
2596 | /* we can compute the instruction now without a relocation entry */ | |
2597 | if (high_expr.X_add_number & 0x8000) | |
2598 | high_expr.X_add_number += 0x10000; | |
2599 | high_expr.X_add_number = | |
2600 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2601 | r = BFD_RELOC_UNUSED; | |
2602 | } | |
2603 | else | |
0dd2d296 ILT |
2604 | { |
2605 | assert (ep->X_op == O_symbol); | |
2606 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2607 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2608 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2609 | r = BFD_RELOC_HI16_S; | |
2610 | } | |
670a50eb ILT |
2611 | |
2612 | /* | |
2613 | * If the macro is about to expand into a second instruction, | |
2614 | * print a warning if needed. We need to pass ip as a parameter | |
2615 | * to generate a better warning message here... | |
2616 | */ | |
0dd2d296 | 2617 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2618 | as_warn ("Macro instruction expanded into multiple instructions"); |
2619 | ||
0dd2d296 ILT |
2620 | if (place == NULL) |
2621 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2622 | |
2623 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2624 | assert (insn.insn_mo); | |
2625 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2626 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2627 | ||
0dd2d296 | 2628 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2629 | if (r == BFD_RELOC_UNUSED) |
2630 | { | |
2631 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2632 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2633 | } |
2634 | else | |
867a58b3 | 2635 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2636 | } |
2637 | ||
2638 | /* set_at() | |
2639 | * Generates code to set the $at register to true (one) | |
2640 | * if reg is less than the immediate expression. | |
2641 | */ | |
2642 | static void | |
6e8dda9c | 2643 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2644 | int *counter; |
2645 | int reg; | |
6e8dda9c | 2646 | int unsignedp; |
3d3c5039 | 2647 | { |
6e8dda9c | 2648 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2649 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2650 | unsignedp ? "sltiu" : "slti", |
9226253a | 2651 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2652 | else |
670a50eb | 2653 | { |
d8a1c247 | 2654 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2655 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2656 | unsignedp ? "sltu" : "slt", |
2657 | "d,v,t", AT, reg, AT); | |
670a50eb | 2658 | } |
3d3c5039 ILT |
2659 | } |
2660 | ||
6e8dda9c | 2661 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2662 | |
2663 | static void | |
19ed8960 | 2664 | check_absolute_expr (ip, ex) |
3d3c5039 | 2665 | struct mips_cl_insn *ip; |
19ed8960 | 2666 | expressionS *ex; |
3d3c5039 | 2667 | { |
19ed8960 | 2668 | if (ex->X_op != O_constant) |
670a50eb | 2669 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2670 | } |
2671 | ||
ff8716f5 JSC |
2672 | /* Count the leading zeroes by performing a binary chop. This is a |
2673 | bulky bit of source, but performance is a LOT better for the | |
2674 | majority of values than a simple loop to count the bits: | |
2675 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2676 | if ((v) & (1 << (31 - lcnt))) | |
2677 | break; | |
2678 | However it is not code size friendly, and the gain will drop a bit | |
2679 | on certain cached systems. | |
2680 | */ | |
2681 | #define COUNT_TOP_ZEROES(v) \ | |
2682 | (((v) & ~0xffff) == 0 \ | |
2683 | ? ((v) & ~0xff) == 0 \ | |
2684 | ? ((v) & ~0xf) == 0 \ | |
2685 | ? ((v) & ~0x3) == 0 \ | |
2686 | ? ((v) & ~0x1) == 0 \ | |
2687 | ? !(v) \ | |
2688 | ? 32 \ | |
2689 | : 31 \ | |
2690 | : 30 \ | |
2691 | : ((v) & ~0x7) == 0 \ | |
2692 | ? 29 \ | |
2693 | : 28 \ | |
2694 | : ((v) & ~0x3f) == 0 \ | |
2695 | ? ((v) & ~0x1f) == 0 \ | |
2696 | ? 27 \ | |
2697 | : 26 \ | |
2698 | : ((v) & ~0x7f) == 0 \ | |
2699 | ? 25 \ | |
2700 | : 24 \ | |
2701 | : ((v) & ~0xfff) == 0 \ | |
2702 | ? ((v) & ~0x3ff) == 0 \ | |
2703 | ? ((v) & ~0x1ff) == 0 \ | |
2704 | ? 23 \ | |
2705 | : 22 \ | |
2706 | : ((v) & ~0x7ff) == 0 \ | |
2707 | ? 21 \ | |
2708 | : 20 \ | |
2709 | : ((v) & ~0x3fff) == 0 \ | |
2710 | ? ((v) & ~0x1fff) == 0 \ | |
2711 | ? 19 \ | |
2712 | : 18 \ | |
2713 | : ((v) & ~0x7fff) == 0 \ | |
2714 | ? 17 \ | |
2715 | : 16 \ | |
2716 | : ((v) & ~0xffffff) == 0 \ | |
2717 | ? ((v) & ~0xfffff) == 0 \ | |
2718 | ? ((v) & ~0x3ffff) == 0 \ | |
2719 | ? ((v) & ~0x1ffff) == 0 \ | |
2720 | ? 15 \ | |
2721 | : 14 \ | |
2722 | : ((v) & ~0x7ffff) == 0 \ | |
2723 | ? 13 \ | |
2724 | : 12 \ | |
2725 | : ((v) & ~0x3fffff) == 0 \ | |
2726 | ? ((v) & ~0x1fffff) == 0 \ | |
2727 | ? 11 \ | |
2728 | : 10 \ | |
2729 | : ((v) & ~0x7fffff) == 0 \ | |
2730 | ? 9 \ | |
2731 | : 8 \ | |
2732 | : ((v) & ~0xfffffff) == 0 \ | |
2733 | ? ((v) & ~0x3ffffff) == 0 \ | |
2734 | ? ((v) & ~0x1ffffff) == 0 \ | |
2735 | ? 7 \ | |
2736 | : 6 \ | |
2737 | : ((v) & ~0x7ffffff) == 0 \ | |
2738 | ? 5 \ | |
2739 | : 4 \ | |
2740 | : ((v) & ~0x3fffffff) == 0 \ | |
2741 | ? ((v) & ~0x1fffffff) == 0 \ | |
2742 | ? 3 \ | |
2743 | : 2 \ | |
2744 | : ((v) & ~0x7fffffff) == 0 \ | |
2745 | ? 1 \ | |
2746 | : 0) | |
2747 | ||
3d3c5039 ILT |
2748 | /* load_register() |
2749 | * This routine generates the least number of instructions neccessary to load | |
2750 | * an absolute expression value into a register. | |
2751 | */ | |
2752 | static void | |
d8a1c247 | 2753 | load_register (counter, reg, ep, dbl) |
670a50eb | 2754 | int *counter; |
670a50eb ILT |
2755 | int reg; |
2756 | expressionS *ep; | |
d8a1c247 | 2757 | int dbl; |
3d3c5039 | 2758 | { |
c36a90ef ILT |
2759 | int freg; |
2760 | expressionS hi32, lo32; | |
847a01cd ILT |
2761 | |
2762 | if (ep->X_op != O_big) | |
6e8dda9c | 2763 | { |
847a01cd | 2764 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2765 | if (ep->X_add_number < 0x8000 |
2766 | && (ep->X_add_number >= 0 | |
2767 | || (ep->X_add_number >= -0x8000 | |
2768 | && (! dbl | |
2769 | || ! ep->X_unsigned | |
2770 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2771 | { |
2772 | /* We can handle 16 bit signed values with an addiu to | |
2773 | $zero. No need to ever use daddiu here, since $zero and | |
2774 | the result are always correct in 32 bit mode. */ | |
2775 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2776 | (int) BFD_RELOC_LO16); | |
2777 | return; | |
2778 | } | |
2779 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2780 | { | |
2781 | /* We can handle 16 bit unsigned values with an ori to | |
2782 | $zero. */ | |
2783 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2784 | (int) BFD_RELOC_LO16); | |
2785 | return; | |
2786 | } | |
98bfd087 ILT |
2787 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2788 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2789 | == ~ (offsetT) 0x7fffffff)) | |
2790 | && (! dbl | |
2791 | || ! ep->X_unsigned | |
2792 | || sizeof (ep->X_add_number) > 4 | |
2793 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2794 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2795 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2796 | { |
2797 | /* 32 bit values require an lui. */ | |
2798 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2799 | (int) BFD_RELOC_HI16); | |
2800 | if ((ep->X_add_number & 0xffff) != 0) | |
2801 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2802 | (int) BFD_RELOC_LO16); | |
2803 | return; | |
2804 | } | |
6e8dda9c | 2805 | } |
847a01cd ILT |
2806 | |
2807 | /* The value is larger than 32 bits. */ | |
2808 | ||
2809 | if (mips_isa < 3) | |
670a50eb | 2810 | { |
6e8dda9c | 2811 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2812 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2813 | (int) BFD_RELOC_LO16); |
847a01cd | 2814 | return; |
6e8dda9c | 2815 | } |
6e8dda9c | 2816 | |
847a01cd ILT |
2817 | if (ep->X_op != O_big) |
2818 | { | |
6e8dda9c | 2819 | hi32 = *ep; |
c36a90ef ILT |
2820 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2821 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2822 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2823 | lo32 = *ep; |
2824 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2825 | } |
847a01cd ILT |
2826 | else |
2827 | { | |
2828 | assert (ep->X_add_number > 2); | |
2829 | if (ep->X_add_number == 3) | |
2830 | generic_bignum[3] = 0; | |
2831 | else if (ep->X_add_number > 4) | |
2832 | as_bad ("Number larger than 64 bits"); | |
2833 | lo32.X_op = O_constant; | |
2834 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2835 | hi32.X_op = O_constant; | |
2836 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2837 | } | |
2838 | ||
d8a1c247 KR |
2839 | if (hi32.X_add_number == 0) |
2840 | freg = 0; | |
2841 | else | |
2842 | { | |
c36a90ef ILT |
2843 | int shift, bit; |
2844 | unsigned long hi, lo; | |
2845 | ||
fb251650 ILT |
2846 | if (hi32.X_add_number == 0xffffffff) |
2847 | { | |
2848 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2849 | { | |
c36a90ef ILT |
2850 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2851 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2852 | return; |
2853 | } | |
2854 | if (lo32.X_add_number & 0x80000000) | |
2855 | { | |
2856 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2857 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2858 | if (lo32.X_add_number & 0xffff) |
2859 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2860 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2861 | return; |
2862 | } | |
2863 | } | |
ff8716f5 | 2864 | |
c36a90ef ILT |
2865 | /* Check for 16bit shifted constant. We know that hi32 is |
2866 | non-zero, so start the mask on the first bit of the hi32 | |
2867 | value. */ | |
ff8716f5 JSC |
2868 | shift = 17; |
2869 | do | |
2870 | { | |
c36a90ef ILT |
2871 | unsigned long himask, lomask; |
2872 | ||
2873 | if (shift < 32) | |
2874 | { | |
2875 | himask = 0xffff >> (32 - shift); | |
2876 | lomask = (0xffff << shift) & 0xffffffff; | |
2877 | } | |
2878 | else | |
2879 | { | |
2880 | himask = 0xffff << (shift - 32); | |
2881 | lomask = 0; | |
2882 | } | |
2883 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2884 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2885 | { | |
2886 | expressionS tmp; | |
2887 | ||
2888 | tmp.X_op = O_constant; | |
2889 | if (shift < 32) | |
2890 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2891 | | (lo32.X_add_number >> shift)); | |
2892 | else | |
2893 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2894 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2895 | (int) BFD_RELOC_LO16); | |
2896 | macro_build ((char *) NULL, counter, NULL, | |
2897 | (shift >= 32) ? "dsll32" : "dsll", | |
2898 | "d,w,<", reg, reg, | |
2899 | (shift >= 32) ? shift - 32 : shift); | |
2900 | return; | |
2901 | } | |
ff8716f5 JSC |
2902 | shift++; |
2903 | } while (shift <= (64 - 16)); | |
2904 | ||
c36a90ef ILT |
2905 | /* Find the bit number of the lowest one bit, and store the |
2906 | shifted value in hi/lo. */ | |
2907 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2908 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2909 | if (lo != 0) | |
2910 | { | |
2911 | bit = 0; | |
2912 | while ((lo & 1) == 0) | |
2913 | { | |
2914 | lo >>= 1; | |
2915 | ++bit; | |
2916 | } | |
2917 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2918 | hi >>= bit; | |
2919 | } | |
2920 | else | |
2921 | { | |
2922 | bit = 32; | |
2923 | while ((hi & 1) == 0) | |
2924 | { | |
2925 | hi >>= 1; | |
2926 | ++bit; | |
2927 | } | |
2928 | lo = hi; | |
2929 | hi = 0; | |
2930 | } | |
2931 | ||
2932 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2933 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2934 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2935 | { |
c36a90ef | 2936 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2937 | if (shift != 0) |
2938 | { | |
c36a90ef ILT |
2939 | expressionS tmp; |
2940 | ||
2941 | /* This instruction will set the register to be all | |
2942 | ones. */ | |
ff8716f5 | 2943 | tmp.X_op = O_constant; |
c36a90ef ILT |
2944 | tmp.X_add_number = (offsetT) -1; |
2945 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2946 | reg, 0, (int) BFD_RELOC_LO16); | |
2947 | if (bit != 0) | |
ff8716f5 | 2948 | { |
c36a90ef | 2949 | bit += shift; |
ff8716f5 | 2950 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2951 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2952 | "d,w,<", reg, reg, |
c36a90ef | 2953 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2954 | } |
c36a90ef ILT |
2955 | macro_build ((char *) NULL, counter, NULL, |
2956 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2957 | "d,w,<", reg, reg, | |
2958 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2959 | return; |
2960 | } | |
2961 | } | |
c36a90ef ILT |
2962 | |
2963 | /* Sign extend hi32 before calling load_register, because we can | |
2964 | generally get better code when we load a sign extended value. */ | |
2965 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2966 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2967 | load_register (counter, reg, &hi32, 0); |
2968 | freg = reg; | |
2969 | } | |
847a01cd | 2970 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2971 | { |
2972 | if (freg != 0) | |
2973 | { | |
2974 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2975 | freg, 0); | |
2976 | freg = reg; | |
2977 | } | |
2978 | } | |
847a01cd ILT |
2979 | else |
2980 | { | |
2981 | expressionS mid16; | |
2982 | ||
fb251650 ILT |
2983 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2984 | { | |
2985 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2986 | (int) BFD_RELOC_HI16); | |
2987 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2988 | reg, 0); |
fb251650 ILT |
2989 | return; |
2990 | } | |
2991 | ||
d8a1c247 KR |
2992 | if (freg != 0) |
2993 | { | |
2994 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2995 | freg, 16); | |
2996 | freg = reg; | |
2997 | } | |
847a01cd ILT |
2998 | mid16 = lo32; |
2999 | mid16.X_add_number >>= 16; | |
3000 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3001 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3002 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3003 | reg, 16); | |
d8a1c247 | 3004 | freg = reg; |
847a01cd ILT |
3005 | } |
3006 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3007 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3008 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3009 | } |
3010 | ||
0dd2d296 ILT |
3011 | /* Load an address into a register. */ |
3012 | ||
3013 | static void | |
3014 | load_address (counter, reg, ep) | |
3015 | int *counter; | |
3016 | int reg; | |
3017 | expressionS *ep; | |
3018 | { | |
3019 | char *p; | |
3020 | ||
3021 | if (ep->X_op != O_constant | |
3022 | && ep->X_op != O_symbol) | |
3023 | { | |
3024 | as_bad ("expression too complex"); | |
3025 | ep->X_op = O_constant; | |
3026 | } | |
3027 | ||
3028 | if (ep->X_op == O_constant) | |
d9aba805 | 3029 | { |
d8a1c247 | 3030 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3031 | return; |
3032 | } | |
3033 | ||
3034 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3035 | { |
3036 | /* If this is a reference to a GP relative symbol, we want | |
3037 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3038 | Otherwise we want | |
04cb3372 | 3039 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3040 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3041 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
3042 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
3043 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
3044 | p = NULL; |
3045 | else | |
3046 | { | |
8ea7f4e8 | 3047 | frag_grow (20); |
0dd2d296 ILT |
3048 | macro_build ((char *) NULL, counter, ep, |
3049 | mips_isa < 3 ? "addiu" : "daddiu", | |
3050 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3051 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 3052 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
3053 | ep->X_add_symbol, (long) 0, (char *) NULL); |
3054 | } | |
3055 | macro_build_lui (p, counter, ep, reg); | |
3056 | if (p != NULL) | |
3057 | p += 4; | |
3058 | macro_build (p, counter, ep, | |
3059 | mips_isa < 3 ? "addiu" : "daddiu", | |
3060 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3061 | } | |
fb251650 | 3062 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3063 | { |
3064 | expressionS ex; | |
3065 | ||
3066 | /* If this is a reference to an external symbol, we want | |
3067 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3068 | Otherwise we want | |
3069 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3070 | nop | |
3071 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3072 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3073 | ex.X_add_number = ep->X_add_number; |
3074 | ep->X_add_number = 0; | |
8ea7f4e8 | 3075 | frag_grow (20); |
0dd2d296 ILT |
3076 | macro_build ((char *) NULL, counter, ep, |
3077 | mips_isa < 3 ? "lw" : "ld", | |
3078 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3079 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3080 | p = frag_var (rs_machine_dependent, 4, 0, | |
3081 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
3082 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
3083 | macro_build (p, counter, ep, | |
3084 | mips_isa < 3 ? "addiu" : "daddiu", | |
3085 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3086 | if (ex.X_add_number != 0) | |
3087 | { | |
3088 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3089 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3090 | ex.X_op = O_constant; | |
fb251650 ILT |
3091 | macro_build ((char *) NULL, counter, &ex, |
3092 | mips_isa < 3 ? "addiu" : "daddiu", | |
3093 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3094 | } | |
3095 | } | |
3096 | else if (mips_pic == SVR4_PIC) | |
3097 | { | |
3098 | expressionS ex; | |
3099 | int off; | |
3100 | ||
3101 | /* This is the large GOT case. If this is a reference to an | |
3102 | external symbol, we want | |
3103 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3104 | addu $reg,$reg,$gp | |
3105 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3106 | Otherwise, for a reference to a local symbol, we want | |
3107 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3108 | nop | |
3109 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3110 | If there is a constant, it must be added in after. */ | |
3111 | ex.X_add_number = ep->X_add_number; | |
3112 | ep->X_add_number = 0; | |
3113 | if (reg_needs_delay (GP)) | |
3114 | off = 4; | |
3115 | else | |
3116 | off = 0; | |
3117 | frag_grow (32); | |
3118 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3119 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3120 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3121 | mips_isa < 3 ? "addu" : "daddu", | |
3122 | "d,v,t", reg, reg, GP); | |
3123 | macro_build ((char *) NULL, counter, ep, | |
3124 | mips_isa < 3 ? "lw" : "ld", | |
3125 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3126 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3127 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3128 | mips_warn_about_macros), | |
3129 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
3130 | if (off > 0) | |
3131 | { | |
3132 | /* We need a nop before loading from $gp. This special | |
3133 | check is required because the lui which starts the main | |
3134 | instruction stream does not refer to $gp, and so will not | |
3135 | insert the nop which may be required. */ | |
3136 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3137 | p += 4; | |
3138 | } | |
3139 | macro_build (p, counter, ep, | |
3140 | mips_isa < 3 ? "lw" : "ld", | |
3141 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3142 | p += 4; | |
3143 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3144 | p += 4; | |
3145 | macro_build (p, counter, ep, | |
3146 | mips_isa < 3 ? "addiu" : "daddiu", | |
3147 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3148 | if (ex.X_add_number != 0) | |
3149 | { | |
3150 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3151 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3152 | ex.X_op = O_constant; | |
3153 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
3154 | mips_isa < 3 ? "addiu" : "daddiu", |
3155 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3156 | } | |
d9aba805 ILT |
3157 | } |
3158 | else if (mips_pic == EMBEDDED_PIC) | |
3159 | { | |
3160 | /* We always do | |
3161 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3162 | */ | |
3163 | macro_build ((char *) NULL, counter, ep, | |
3164 | mips_isa < 3 ? "addiu" : "daddiu", | |
3165 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3166 | } | |
3167 | else | |
3168 | abort (); | |
0dd2d296 ILT |
3169 | } |
3170 | ||
3d3c5039 ILT |
3171 | /* |
3172 | * Build macros | |
3173 | * This routine implements the seemingly endless macro or synthesized | |
3174 | * instructions and addressing modes in the mips assembly language. Many | |
3175 | * of these macros are simple and are similar to each other. These could | |
3176 | * probably be handled by some kind of table or grammer aproach instead of | |
3177 | * this verbose method. Others are not simple macros but are more like | |
3178 | * optimizing code generation. | |
3179 | * One interesting optimization is when several store macros appear | |
3180 | * consecutivly that would load AT with the upper half of the same address. | |
3181 | * The ensuing load upper instructions are ommited. This implies some kind | |
3182 | * of global optimization. We currently only optimize within a single macro. | |
3183 | * For many of the load and store macros if the address is specified as a | |
3184 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3185 | * first load register 'at' with zero and use it as the base register. The | |
3186 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3187 | * we're missing. | |
3188 | */ | |
3189 | static void | |
3190 | macro (ip) | |
3191 | struct mips_cl_insn *ip; | |
3192 | { | |
670a50eb ILT |
3193 | register int treg, sreg, dreg, breg; |
3194 | int tempreg; | |
3195 | int mask; | |
3196 | int icnt = 0; | |
3197 | int used_at; | |
670a50eb ILT |
3198 | expressionS expr1; |
3199 | const char *s; | |
8358c818 | 3200 | const char *s2; |
670a50eb | 3201 | const char *fmt; |
8358c818 ILT |
3202 | int likely = 0; |
3203 | int dbl = 0; | |
3204 | int coproc = 0; | |
b2b8c24e | 3205 | int lr = 0; |
6e8dda9c | 3206 | offsetT maxnum; |
adcf2b9d | 3207 | int off; |
9226253a | 3208 | bfd_reloc_code_real_type r; |
0dd2d296 | 3209 | char *p; |
55933a58 | 3210 | int hold_mips_optimize; |
670a50eb | 3211 | |
cc5703cd ILT |
3212 | assert (! mips16); |
3213 | ||
670a50eb ILT |
3214 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3215 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3216 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3217 | mask = ip->insn_mo->mask; | |
3218 | ||
5ac34ac3 ILT |
3219 | expr1.X_op = O_constant; |
3220 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3221 | expr1.X_add_symbol = NULL; |
3222 | expr1.X_add_number = 1; | |
3223 | ||
3224 | switch (mask) | |
3225 | { | |
6e8dda9c ILT |
3226 | case M_DABS: |
3227 | dbl = 1; | |
3d3c5039 | 3228 | case M_ABS: |
6e8dda9c ILT |
3229 | /* bgez $a0,.+12 |
3230 | move v0,$a0 | |
3231 | sub v0,$zero,$a0 | |
3232 | */ | |
3d3c5039 | 3233 | |
fbcfacb7 | 3234 | mips_emit_delays (true); |
becfe05e | 3235 | ++mips_noreorder; |
0dd2d296 | 3236 | mips_any_noreorder = 1; |
3d3c5039 | 3237 | |
670a50eb | 3238 | expr1.X_add_number = 8; |
0dd2d296 | 3239 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3240 | if (dreg == sreg) |
0dd2d296 | 3241 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3242 | else |
0dd2d296 ILT |
3243 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3244 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3245 | dbl ? "dsub" : "sub", |
3246 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3247 | |
becfe05e | 3248 | --mips_noreorder; |
670a50eb | 3249 | return; |
3d3c5039 ILT |
3250 | |
3251 | case M_ADD_I: | |
8358c818 ILT |
3252 | s = "addi"; |
3253 | s2 = "add"; | |
3254 | goto do_addi; | |
3d3c5039 | 3255 | case M_ADDU_I: |
8358c818 ILT |
3256 | s = "addiu"; |
3257 | s2 = "addu"; | |
3258 | goto do_addi; | |
3259 | case M_DADD_I: | |
6e8dda9c | 3260 | dbl = 1; |
8358c818 ILT |
3261 | s = "daddi"; |
3262 | s2 = "dadd"; | |
3263 | goto do_addi; | |
3264 | case M_DADDU_I: | |
6e8dda9c | 3265 | dbl = 1; |
8358c818 ILT |
3266 | s = "daddiu"; |
3267 | s2 = "daddu"; | |
3268 | do_addi: | |
6e8dda9c | 3269 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3270 | { |
0dd2d296 | 3271 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3272 | (int) BFD_RELOC_LO16); |
670a50eb | 3273 | return; |
3d3c5039 | 3274 | } |
d8a1c247 | 3275 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3276 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3277 | break; |
3d3c5039 ILT |
3278 | |
3279 | case M_AND_I: | |
6e8dda9c ILT |
3280 | s = "andi"; |
3281 | s2 = "and"; | |
3282 | goto do_bit; | |
3d3c5039 | 3283 | case M_OR_I: |
6e8dda9c ILT |
3284 | s = "ori"; |
3285 | s2 = "or"; | |
3286 | goto do_bit; | |
3d3c5039 | 3287 | case M_NOR_I: |
6e8dda9c ILT |
3288 | s = ""; |
3289 | s2 = "nor"; | |
3290 | goto do_bit; | |
3d3c5039 | 3291 | case M_XOR_I: |
6e8dda9c ILT |
3292 | s = "xori"; |
3293 | s2 = "xor"; | |
3294 | do_bit: | |
3295 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3296 | { |
6e8dda9c | 3297 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3298 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3299 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3300 | else |
670a50eb | 3301 | { |
0dd2d296 ILT |
3302 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3303 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3304 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3305 | treg, treg, 0); |
3d3c5039 | 3306 | } |
6e8dda9c | 3307 | return; |
3d3c5039 | 3308 | } |
6e8dda9c | 3309 | |
d8a1c247 | 3310 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3311 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3312 | break; |
3d3c5039 ILT |
3313 | |
3314 | case M_BEQ_I: | |
8358c818 ILT |
3315 | s = "beq"; |
3316 | goto beq_i; | |
3317 | case M_BEQL_I: | |
3318 | s = "beql"; | |
3319 | likely = 1; | |
3320 | goto beq_i; | |
3d3c5039 | 3321 | case M_BNE_I: |
8358c818 ILT |
3322 | s = "bne"; |
3323 | goto beq_i; | |
3324 | case M_BNEL_I: | |
3325 | s = "bnel"; | |
3326 | likely = 1; | |
3327 | beq_i: | |
670a50eb ILT |
3328 | if (imm_expr.X_add_number == 0) |
3329 | { | |
0dd2d296 ILT |
3330 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3331 | 0); | |
670a50eb ILT |
3332 | return; |
3333 | } | |
d8a1c247 | 3334 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3335 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3336 | break; |
3d3c5039 | 3337 | |
8358c818 ILT |
3338 | case M_BGEL: |
3339 | likely = 1; | |
3d3c5039 | 3340 | case M_BGE: |
670a50eb ILT |
3341 | if (treg == 0) |
3342 | { | |
0dd2d296 | 3343 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3344 | likely ? "bgezl" : "bgez", |
3345 | "s,p", sreg); | |
670a50eb | 3346 | return; |
3d3c5039 | 3347 | } |
9a7d824a ILT |
3348 | if (sreg == 0) |
3349 | { | |
0dd2d296 | 3350 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3351 | likely ? "blezl" : "blez", |
3352 | "s,p", treg); | |
9a7d824a ILT |
3353 | return; |
3354 | } | |
0dd2d296 ILT |
3355 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3356 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3357 | likely ? "beql" : "beq", |
3358 | "s,t,p", AT, 0); | |
670a50eb | 3359 | break; |
3d3c5039 | 3360 | |
8358c818 ILT |
3361 | case M_BGTL_I: |
3362 | likely = 1; | |
3d3c5039 | 3363 | case M_BGT_I: |
9a7d824a | 3364 | /* check for > max integer */ |
6e8dda9c ILT |
3365 | maxnum = 0x7fffffff; |
3366 | if (mips_isa >= 3) | |
3367 | { | |
3368 | maxnum <<= 16; | |
3369 | maxnum |= 0xffff; | |
3370 | maxnum <<= 16; | |
3371 | maxnum |= 0xffff; | |
3372 | } | |
7b777690 ILT |
3373 | if (imm_expr.X_add_number >= maxnum |
3374 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3375 | { |
3376 | do_false: | |
3377 | /* result is always false */ | |
8358c818 ILT |
3378 | if (! likely) |
3379 | { | |
3380 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3381 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3382 | } |
3383 | else | |
3384 | { | |
3385 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3386 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3387 | "s,t,p", 0, 0); | |
8358c818 | 3388 | } |
9a7d824a ILT |
3389 | return; |
3390 | } | |
670a50eb ILT |
3391 | imm_expr.X_add_number++; |
3392 | /* FALLTHROUGH */ | |
3d3c5039 | 3393 | case M_BGE_I: |
8358c818 ILT |
3394 | case M_BGEL_I: |
3395 | if (mask == M_BGEL_I) | |
3396 | likely = 1; | |
670a50eb ILT |
3397 | if (imm_expr.X_add_number == 0) |
3398 | { | |
0dd2d296 | 3399 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3400 | likely ? "bgezl" : "bgez", |
3401 | "s,p", sreg); | |
670a50eb | 3402 | return; |
3d3c5039 | 3403 | } |
670a50eb ILT |
3404 | if (imm_expr.X_add_number == 1) |
3405 | { | |
0dd2d296 | 3406 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3407 | likely ? "bgtzl" : "bgtz", |
3408 | "s,p", sreg); | |
670a50eb | 3409 | return; |
3d3c5039 | 3410 | } |
6e8dda9c ILT |
3411 | maxnum = 0x7fffffff; |
3412 | if (mips_isa >= 3) | |
3413 | { | |
3414 | maxnum <<= 16; | |
3415 | maxnum |= 0xffff; | |
3416 | maxnum <<= 16; | |
3417 | maxnum |= 0xffff; | |
3418 | } | |
3419 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3420 | if (imm_expr.X_add_number <= maxnum |
3421 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3422 | { |
3423 | do_true: | |
3424 | /* result is always true */ | |
3425 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3426 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3427 | return; |
3428 | } | |
6e8dda9c | 3429 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3430 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3431 | likely ? "beql" : "beq", |
3432 | "s,t,p", AT, 0); | |
670a50eb | 3433 | break; |
3d3c5039 | 3434 | |
8358c818 ILT |
3435 | case M_BGEUL: |
3436 | likely = 1; | |
3d3c5039 | 3437 | case M_BGEU: |
670a50eb | 3438 | if (treg == 0) |
9a7d824a ILT |
3439 | goto do_true; |
3440 | if (sreg == 0) | |
670a50eb | 3441 | { |
0dd2d296 | 3442 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3443 | likely ? "beql" : "beq", |
3444 | "s,t,p", 0, treg); | |
670a50eb | 3445 | return; |
3d3c5039 | 3446 | } |
0dd2d296 ILT |
3447 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3448 | treg); | |
3449 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3450 | likely ? "beql" : "beq", |
3451 | "s,t,p", AT, 0); | |
670a50eb | 3452 | break; |
3d3c5039 | 3453 | |
8358c818 ILT |
3454 | case M_BGTUL_I: |
3455 | likely = 1; | |
9a7d824a | 3456 | case M_BGTU_I: |
6e8dda9c | 3457 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3458 | goto do_false; |
3459 | imm_expr.X_add_number++; | |
3460 | /* FALLTHROUGH */ | |
3d3c5039 | 3461 | case M_BGEU_I: |
8358c818 ILT |
3462 | case M_BGEUL_I: |
3463 | if (mask == M_BGEUL_I) | |
3464 | likely = 1; | |
670a50eb | 3465 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3466 | goto do_true; |
670a50eb ILT |
3467 | if (imm_expr.X_add_number == 1) |
3468 | { | |
0dd2d296 | 3469 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3470 | likely ? "bnel" : "bne", |
3471 | "s,t,p", sreg, 0); | |
670a50eb | 3472 | return; |
3d3c5039 | 3473 | } |
6e8dda9c | 3474 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3475 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3476 | likely ? "beql" : "beq", |
3477 | "s,t,p", AT, 0); | |
670a50eb | 3478 | break; |
3d3c5039 | 3479 | |
8358c818 ILT |
3480 | case M_BGTL: |
3481 | likely = 1; | |
3d3c5039 | 3482 | case M_BGT: |
670a50eb ILT |
3483 | if (treg == 0) |
3484 | { | |
0dd2d296 | 3485 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3486 | likely ? "bgtzl" : "bgtz", |
3487 | "s,p", sreg); | |
670a50eb | 3488 | return; |
3d3c5039 | 3489 | } |
9a7d824a ILT |
3490 | if (sreg == 0) |
3491 | { | |
0dd2d296 | 3492 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3493 | likely ? "bltzl" : "bltz", |
3494 | "s,p", treg); | |
9a7d824a ILT |
3495 | return; |
3496 | } | |
0dd2d296 ILT |
3497 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3498 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3499 | likely ? "bnel" : "bne", |
3500 | "s,t,p", AT, 0); | |
670a50eb | 3501 | break; |
3d3c5039 | 3502 | |
8358c818 ILT |
3503 | case M_BGTUL: |
3504 | likely = 1; | |
3d3c5039 | 3505 | case M_BGTU: |
670a50eb ILT |
3506 | if (treg == 0) |
3507 | { | |
0dd2d296 | 3508 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3509 | likely ? "bnel" : "bne", |
3510 | "s,t,p", sreg, 0); | |
670a50eb | 3511 | return; |
3d3c5039 | 3512 | } |
9a7d824a ILT |
3513 | if (sreg == 0) |
3514 | goto do_false; | |
0dd2d296 ILT |
3515 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3516 | sreg); | |
3517 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3518 | likely ? "bnel" : "bne", |
3519 | "s,t,p", AT, 0); | |
670a50eb | 3520 | break; |
3d3c5039 | 3521 | |
8358c818 ILT |
3522 | case M_BLEL: |
3523 | likely = 1; | |
3d3c5039 | 3524 | case M_BLE: |
670a50eb ILT |
3525 | if (treg == 0) |
3526 | { | |
0dd2d296 | 3527 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3528 | likely ? "blezl" : "blez", |
3529 | "s,p", sreg); | |
670a50eb ILT |
3530 | return; |
3531 | } | |
9a7d824a ILT |
3532 | if (sreg == 0) |
3533 | { | |
0dd2d296 | 3534 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3535 | likely ? "bgezl" : "bgez", |
3536 | "s,p", treg); | |
9a7d824a ILT |
3537 | return; |
3538 | } | |
0dd2d296 ILT |
3539 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3540 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3541 | likely ? "beql" : "beq", |
3542 | "s,t,p", AT, 0); | |
670a50eb | 3543 | break; |
3d3c5039 | 3544 | |
8358c818 ILT |
3545 | case M_BLEL_I: |
3546 | likely = 1; | |
3d3c5039 | 3547 | case M_BLE_I: |
6e8dda9c ILT |
3548 | maxnum = 0x7fffffff; |
3549 | if (mips_isa >= 3) | |
3550 | { | |
3551 | maxnum <<= 16; | |
3552 | maxnum |= 0xffff; | |
3553 | maxnum <<= 16; | |
3554 | maxnum |= 0xffff; | |
3555 | } | |
7b777690 ILT |
3556 | if (imm_expr.X_add_number >= maxnum |
3557 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3558 | goto do_true; |
3559 | imm_expr.X_add_number++; | |
3560 | /* FALLTHROUGH */ | |
9a7d824a | 3561 | case M_BLT_I: |
8358c818 ILT |
3562 | case M_BLTL_I: |
3563 | if (mask == M_BLTL_I) | |
3564 | likely = 1; | |
670a50eb ILT |
3565 | if (imm_expr.X_add_number == 0) |
3566 | { | |
0dd2d296 | 3567 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3568 | likely ? "bltzl" : "bltz", |
3569 | "s,p", sreg); | |
670a50eb ILT |
3570 | return; |
3571 | } | |
9a7d824a | 3572 | if (imm_expr.X_add_number == 1) |
670a50eb | 3573 | { |
0dd2d296 | 3574 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3575 | likely ? "blezl" : "blez", |
3576 | "s,p", sreg); | |
670a50eb ILT |
3577 | return; |
3578 | } | |
6e8dda9c | 3579 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3580 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3581 | likely ? "bnel" : "bne", |
3582 | "s,t,p", AT, 0); | |
670a50eb | 3583 | break; |
3d3c5039 | 3584 | |
8358c818 ILT |
3585 | case M_BLEUL: |
3586 | likely = 1; | |
3d3c5039 | 3587 | case M_BLEU: |
670a50eb ILT |
3588 | if (treg == 0) |
3589 | { | |
0dd2d296 | 3590 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3591 | likely ? "beql" : "beq", |
3592 | "s,t,p", sreg, 0); | |
670a50eb | 3593 | return; |
3d3c5039 | 3594 | } |
9a7d824a ILT |
3595 | if (sreg == 0) |
3596 | goto do_true; | |
0dd2d296 ILT |
3597 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3598 | sreg); | |
3599 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3600 | likely ? "beql" : "beq", |
3601 | "s,t,p", AT, 0); | |
670a50eb | 3602 | break; |
3d3c5039 | 3603 | |
8358c818 ILT |
3604 | case M_BLEUL_I: |
3605 | likely = 1; | |
3d3c5039 | 3606 | case M_BLEU_I: |
6e8dda9c | 3607 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3608 | goto do_true; |
3609 | imm_expr.X_add_number++; | |
3610 | /* FALLTHROUGH */ | |
9a7d824a | 3611 | case M_BLTU_I: |
8358c818 ILT |
3612 | case M_BLTUL_I: |
3613 | if (mask == M_BLTUL_I) | |
3614 | likely = 1; | |
670a50eb | 3615 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3616 | goto do_false; |
3617 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3618 | { |
0dd2d296 | 3619 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3620 | likely ? "beql" : "beq", |
3621 | "s,t,p", sreg, 0); | |
670a50eb | 3622 | return; |
3d3c5039 | 3623 | } |
6e8dda9c | 3624 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3625 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3626 | likely ? "bnel" : "bne", |
3627 | "s,t,p", AT, 0); | |
670a50eb | 3628 | break; |
3d3c5039 | 3629 | |
8358c818 ILT |
3630 | case M_BLTL: |
3631 | likely = 1; | |
3d3c5039 | 3632 | case M_BLT: |
670a50eb ILT |
3633 | if (treg == 0) |
3634 | { | |
0dd2d296 | 3635 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3636 | likely ? "bltzl" : "bltz", |
3637 | "s,p", sreg); | |
670a50eb | 3638 | return; |
3d3c5039 | 3639 | } |
9a7d824a | 3640 | if (sreg == 0) |
670a50eb | 3641 | { |
0dd2d296 | 3642 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3643 | likely ? "bgtzl" : "bgtz", |
3644 | "s,p", treg); | |
670a50eb | 3645 | return; |
3d3c5039 | 3646 | } |
0dd2d296 ILT |
3647 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3648 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3649 | likely ? "bnel" : "bne", |
3650 | "s,t,p", AT, 0); | |
670a50eb | 3651 | break; |
3d3c5039 | 3652 | |
8358c818 ILT |
3653 | case M_BLTUL: |
3654 | likely = 1; | |
3d3c5039 | 3655 | case M_BLTU: |
670a50eb | 3656 | if (treg == 0) |
9a7d824a ILT |
3657 | goto do_false; |
3658 | if (sreg == 0) | |
670a50eb | 3659 | { |
0dd2d296 | 3660 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3661 | likely ? "bnel" : "bne", |
3662 | "s,t,p", 0, treg); | |
670a50eb ILT |
3663 | return; |
3664 | } | |
0dd2d296 ILT |
3665 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3666 | treg); | |
3667 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3668 | likely ? "bnel" : "bne", |
3669 | "s,t,p", AT, 0); | |
670a50eb | 3670 | break; |
3d3c5039 | 3671 | |
8358c818 ILT |
3672 | case M_DDIV_3: |
3673 | dbl = 1; | |
3d3c5039 | 3674 | case M_DIV_3: |
8358c818 ILT |
3675 | s = "mflo"; |
3676 | goto do_div3; | |
3677 | case M_DREM_3: | |
3678 | dbl = 1; | |
3d3c5039 | 3679 | case M_REM_3: |
8358c818 ILT |
3680 | s = "mfhi"; |
3681 | do_div3: | |
670a50eb ILT |
3682 | if (treg == 0) |
3683 | { | |
3684 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3685 | if (mips_trap) |
3686 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3687 | else | |
3688 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3689 | return; |
3690 | } | |
3691 | ||
fbcfacb7 | 3692 | mips_emit_delays (true); |
becfe05e | 3693 | ++mips_noreorder; |
0dd2d296 ILT |
3694 | mips_any_noreorder = 1; |
3695 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3696 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3697 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3698 | if (mips_trap) |
3699 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3700 | else | |
3701 | { | |
3702 | expr1.X_add_number = 8; | |
3703 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3704 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3705 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3706 | } | |
670a50eb | 3707 | expr1.X_add_number = -1; |
0dd2d296 | 3708 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3709 | dbl ? "daddiu" : "addiu", |
9226253a | 3710 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3711 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3712 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3713 | if (dbl) |
3714 | { | |
3715 | expr1.X_add_number = 1; | |
0dd2d296 | 3716 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3717 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3718 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3719 | 31); | |
8358c818 ILT |
3720 | } |
3721 | else | |
3722 | { | |
3723 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3724 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3725 | (int) BFD_RELOC_HI16); | |
8358c818 | 3726 | } |
8ea7f4e8 ILT |
3727 | if (mips_trap) |
3728 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3729 | else | |
3730 | { | |
3731 | expr1.X_add_number = 8; | |
3732 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3733 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3734 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3735 | } | |
becfe05e | 3736 | --mips_noreorder; |
0dd2d296 | 3737 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3738 | break; |
3d3c5039 ILT |
3739 | |
3740 | case M_DIV_3I: | |
8358c818 ILT |
3741 | s = "div"; |
3742 | s2 = "mflo"; | |
3743 | goto do_divi; | |
3d3c5039 | 3744 | case M_DIVU_3I: |
8358c818 ILT |
3745 | s = "divu"; |
3746 | s2 = "mflo"; | |
3747 | goto do_divi; | |
3d3c5039 | 3748 | case M_REM_3I: |
8358c818 ILT |
3749 | s = "div"; |
3750 | s2 = "mfhi"; | |
3751 | goto do_divi; | |
3d3c5039 | 3752 | case M_REMU_3I: |
8358c818 ILT |
3753 | s = "divu"; |
3754 | s2 = "mfhi"; | |
3755 | goto do_divi; | |
3756 | case M_DDIV_3I: | |
3757 | dbl = 1; | |
3758 | s = "ddiv"; | |
3759 | s2 = "mflo"; | |
3760 | goto do_divi; | |
3761 | case M_DDIVU_3I: | |
3762 | dbl = 1; | |
3763 | s = "ddivu"; | |
3764 | s2 = "mflo"; | |
3765 | goto do_divi; | |
3766 | case M_DREM_3I: | |
3767 | dbl = 1; | |
3768 | s = "ddiv"; | |
3769 | s2 = "mfhi"; | |
3770 | goto do_divi; | |
3771 | case M_DREMU_3I: | |
3772 | dbl = 1; | |
3773 | s = "ddivu"; | |
3774 | s2 = "mfhi"; | |
3775 | do_divi: | |
670a50eb ILT |
3776 | if (imm_expr.X_add_number == 0) |
3777 | { | |
3778 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3779 | if (mips_trap) |
3780 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3781 | else | |
3782 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3783 | return; |
3784 | } | |
3785 | if (imm_expr.X_add_number == 1) | |
3786 | { | |
8358c818 | 3787 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3788 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3789 | sreg); | |
3d3c5039 | 3790 | else |
0dd2d296 | 3791 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3792 | return; |
3793 | } | |
8358c818 ILT |
3794 | if (imm_expr.X_add_number == -1 |
3795 | && s[strlen (s) - 1] != 'u') | |
3796 | { | |
3797 | if (strcmp (s2, "mflo") == 0) | |
3798 | { | |
3799 | if (dbl) | |
0dd2d296 ILT |
3800 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3801 | sreg); | |
8358c818 | 3802 | else |
0dd2d296 ILT |
3803 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3804 | sreg); | |
8358c818 ILT |
3805 | } |
3806 | else | |
0dd2d296 | 3807 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3808 | return; |
3809 | } | |
3d3c5039 | 3810 | |
d8a1c247 | 3811 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3812 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3813 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3814 | break; |
3815 | ||
3816 | case M_DIVU_3: | |
8358c818 ILT |
3817 | s = "divu"; |
3818 | s2 = "mflo"; | |
3819 | goto do_divu3; | |
670a50eb | 3820 | case M_REMU_3: |
8358c818 ILT |
3821 | s = "divu"; |
3822 | s2 = "mfhi"; | |
3823 | goto do_divu3; | |
3824 | case M_DDIVU_3: | |
3825 | s = "ddivu"; | |
3826 | s2 = "mflo"; | |
3827 | goto do_divu3; | |
3828 | case M_DREMU_3: | |
3829 | s = "ddivu"; | |
3830 | s2 = "mfhi"; | |
3831 | do_divu3: | |
fbcfacb7 | 3832 | mips_emit_delays (true); |
becfe05e | 3833 | ++mips_noreorder; |
0dd2d296 ILT |
3834 | mips_any_noreorder = 1; |
3835 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3836 | if (mips_trap) |
3837 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3838 | else | |
3839 | { | |
3840 | expr1.X_add_number = 8; | |
3841 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3842 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3843 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3844 | } | |
becfe05e | 3845 | --mips_noreorder; |
0dd2d296 | 3846 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3847 | return; |
3d3c5039 | 3848 | |
d8a1c247 KR |
3849 | case M_DLA_AB: |
3850 | dbl = 1; | |
0dd2d296 | 3851 | case M_LA_AB: |
d9aba805 ILT |
3852 | /* Load the address of a symbol into a register. If breg is not |
3853 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3854 | |
3855 | /* When generating embedded PIC code, we permit expressions of | |
3856 | the form | |
3857 | la $4,foo-bar | |
3858 | where bar is an address in the .text section. These are used | |
3859 | when getting the addresses of functions. We don't permit | |
3860 | X_add_number to be non-zero, because if the symbol is | |
3861 | external the relaxing code needs to know that any addend is | |
3862 | purely the offset to X_op_symbol. */ | |
3863 | if (mips_pic == EMBEDDED_PIC | |
3864 | && offset_expr.X_op == O_subtract | |
3865 | && now_seg == text_section | |
847a01cd ILT |
3866 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3867 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3868 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3869 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3870 | ->sy_value.X_add_symbol) | |
3871 | == text_section))) | |
ecd4ca1c ILT |
3872 | && breg == 0 |
3873 | && offset_expr.X_add_number == 0) | |
3874 | { | |
3875 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3876 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3877 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3878 | mips_isa < 3 ? "addiu" : "daddiu", | |
3879 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3880 | return; | |
3881 | } | |
3882 | ||
0dd2d296 ILT |
3883 | if (offset_expr.X_op != O_symbol |
3884 | && offset_expr.X_op != O_constant) | |
670a50eb | 3885 | { |
0dd2d296 ILT |
3886 | as_bad ("expression too complex"); |
3887 | offset_expr.X_op = O_constant; | |
3888 | } | |
3889 | ||
3890 | if (treg == breg) | |
3891 | { | |
3892 | tempreg = AT; | |
3893 | used_at = 1; | |
3d3c5039 | 3894 | } |
670a50eb ILT |
3895 | else |
3896 | { | |
0dd2d296 ILT |
3897 | tempreg = treg; |
3898 | used_at = 0; | |
670a50eb | 3899 | } |
3d3c5039 | 3900 | |
5ac34ac3 | 3901 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3902 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3903 | else if (mips_pic == NO_PIC) |
670a50eb | 3904 | { |
0dd2d296 ILT |
3905 | /* If this is a reference to an GP relative symbol, we want |
3906 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3907 | Otherwise we want | |
3908 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3909 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3910 | If we have a constant, we need two instructions anyhow, | |
3911 | so we may as well always use the latter form. */ | |
7a15a226 | 3912 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3913 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3914 | p = NULL; |
3915 | else | |
3916 | { | |
8ea7f4e8 | 3917 | frag_grow (20); |
0dd2d296 ILT |
3918 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3919 | mips_isa < 3 ? "addiu" : "daddiu", | |
3920 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3921 | p = frag_var (rs_machine_dependent, 8, 0, | |
3922 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3923 | mips_warn_about_macros), | |
3924 | offset_expr.X_add_symbol, (long) 0, | |
3925 | (char *) NULL); | |
3926 | } | |
3927 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3928 | if (p != NULL) | |
3929 | p += 4; | |
3930 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3931 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3932 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3933 | } | |
fb251650 | 3934 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3935 | { |
3936 | /* If this is a reference to an external symbol, and there | |
3937 | is no constant, we want | |
3938 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3939 | For a local symbol, we want | |
3940 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3941 | nop | |
3942 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3943 | ||
3944 | If we have a small constant, and this is a reference to | |
3945 | an external symbol, we want | |
3946 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3947 | nop | |
3948 | addiu $tempreg,$tempreg,<constant> | |
3949 | For a local symbol, we want the same instruction | |
3950 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3951 | addiu instruction. | |
3952 | ||
3953 | If we have a large constant, and this is a reference to | |
3954 | an external symbol, we want | |
3955 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3956 | lui $at,<hiconstant> | |
3957 | addiu $at,$at,<loconstant> | |
3958 | addu $tempreg,$tempreg,$at | |
3959 | For a local symbol, we want the same instruction | |
3960 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3961 | addiu instruction. */ | |
3962 | expr1.X_add_number = offset_expr.X_add_number; | |
3963 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3964 | frag_grow (32); |
0dd2d296 | 3965 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3966 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3967 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3968 | if (expr1.X_add_number == 0) | |
3969 | { | |
3970 | int off; | |
3971 | ||
3972 | if (breg == 0) | |
3973 | off = 0; | |
3974 | else | |
3975 | { | |
3976 | /* We're going to put in an addu instruction using | |
3977 | tempreg, so we may as well insert the nop right | |
3978 | now. */ | |
3979 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3980 | "nop", ""); | |
3981 | off = 4; | |
3982 | } | |
3983 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3984 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3985 | (breg == 0 | |
3986 | ? mips_warn_about_macros | |
3987 | : 0)), | |
3988 | offset_expr.X_add_symbol, (long) 0, | |
3989 | (char *) NULL); | |
3990 | if (breg == 0) | |
3991 | { | |
3992 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3993 | p += 4; | |
3994 | } | |
3995 | macro_build (p, &icnt, &expr1, | |
3996 | mips_isa < 3 ? "addiu" : "daddiu", | |
3997 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3998 | /* FIXME: If breg == 0, and the next instruction uses | |
3999 | $tempreg, then if this variant case is used an extra | |
4000 | nop will be generated. */ | |
4001 | } | |
4002 | else if (expr1.X_add_number >= -0x8000 | |
4003 | && expr1.X_add_number < 0x8000) | |
4004 | { | |
4005 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4006 | "nop", ""); | |
4007 | macro_build ((char *) NULL, &icnt, &expr1, | |
4008 | mips_isa < 3 ? "addiu" : "daddiu", | |
4009 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4010 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4011 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4012 | offset_expr.X_add_symbol, (long) 0, | |
4013 | (char *) NULL); | |
4014 | } | |
4015 | else | |
4016 | { | |
4017 | int off1; | |
4018 | ||
4019 | /* If we are going to add in a base register, and the | |
4020 | target register and the base register are the same, | |
4021 | then we are using AT as a temporary register. Since | |
4022 | we want to load the constant into AT, we add our | |
4023 | current AT (from the global offset table) and the | |
4024 | register into the register now, and pretend we were | |
4025 | not using a base register. */ | |
4026 | if (breg != treg) | |
4027 | off1 = 0; | |
4028 | else | |
4029 | { | |
4030 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4031 | "nop", ""); | |
4032 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4033 | mips_isa < 3 ? "addu" : "daddu", | |
4034 | "d,v,t", treg, AT, breg); | |
4035 | breg = 0; | |
4036 | tempreg = treg; | |
4037 | off1 = -8; | |
4038 | } | |
4039 | ||
55933a58 ILT |
4040 | /* Set mips_optimize around the lui instruction to avoid |
4041 | inserting an unnecessary nop after the lw. */ | |
4042 | hold_mips_optimize = mips_optimize; | |
4043 | mips_optimize = 2; | |
0dd2d296 | 4044 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4045 | mips_optimize = hold_mips_optimize; |
4046 | ||
0dd2d296 ILT |
4047 | macro_build ((char *) NULL, &icnt, &expr1, |
4048 | mips_isa < 3 ? "addiu" : "daddiu", | |
4049 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4050 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4051 | mips_isa < 3 ? "addu" : "daddu", | |
4052 | "d,v,t", tempreg, tempreg, AT); | |
4053 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4054 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4055 | offset_expr.X_add_symbol, (long) 0, | |
4056 | (char *) NULL); | |
4057 | used_at = 1; | |
4058 | } | |
670a50eb | 4059 | } |
fb251650 ILT |
4060 | else if (mips_pic == SVR4_PIC) |
4061 | { | |
4062 | int gpdel; | |
4063 | ||
4064 | /* This is the large GOT case. If this is a reference to an | |
4065 | external symbol, and there is no constant, we want | |
4066 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4067 | addu $tempreg,$tempreg,$gp | |
4068 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4069 | For a local symbol, we want | |
4070 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4071 | nop | |
4072 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4073 | ||
4074 | If we have a small constant, and this is a reference to | |
4075 | an external symbol, we want | |
4076 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4077 | addu $tempreg,$tempreg,$gp | |
4078 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4079 | nop | |
4080 | addiu $tempreg,$tempreg,<constant> | |
4081 | For a local symbol, we want | |
4082 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4083 | nop | |
4084 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4085 | ||
4086 | If we have a large constant, and this is a reference to | |
4087 | an external symbol, we want | |
4088 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4089 | addu $tempreg,$tempreg,$gp | |
4090 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4091 | lui $at,<hiconstant> | |
4092 | addiu $at,$at,<loconstant> | |
4093 | addu $tempreg,$tempreg,$at | |
4094 | For a local symbol, we want | |
4095 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4096 | lui $at,<hiconstant> | |
4097 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4098 | addu $tempreg,$tempreg,$at | |
4099 | */ | |
4100 | expr1.X_add_number = offset_expr.X_add_number; | |
4101 | offset_expr.X_add_number = 0; | |
4102 | frag_grow (52); | |
4103 | if (reg_needs_delay (GP)) | |
4104 | gpdel = 4; | |
4105 | else | |
4106 | gpdel = 0; | |
4107 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4108 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4109 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4110 | mips_isa < 3 ? "addu" : "daddu", | |
4111 | "d,v,t", tempreg, tempreg, GP); | |
4112 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4113 | dbl ? "ld" : "lw", | |
4114 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4115 | tempreg); | |
4116 | if (expr1.X_add_number == 0) | |
4117 | { | |
4118 | int off; | |
4119 | ||
4120 | if (breg == 0) | |
4121 | off = 0; | |
4122 | else | |
4123 | { | |
4124 | /* We're going to put in an addu instruction using | |
4125 | tempreg, so we may as well insert the nop right | |
4126 | now. */ | |
4127 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4128 | "nop", ""); | |
4129 | off = 4; | |
4130 | } | |
4131 | ||
4132 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4133 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4134 | 8 + gpdel, 0, | |
4135 | (breg == 0 | |
4136 | ? mips_warn_about_macros | |
4137 | : 0)), | |
4138 | offset_expr.X_add_symbol, (long) 0, | |
4139 | (char *) NULL); | |
4140 | } | |
4141 | else if (expr1.X_add_number >= -0x8000 | |
4142 | && expr1.X_add_number < 0x8000) | |
4143 | { | |
4144 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4145 | "nop", ""); | |
4146 | macro_build ((char *) NULL, &icnt, &expr1, | |
4147 | mips_isa < 3 ? "addiu" : "daddiu", | |
4148 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4149 | ||
4150 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4151 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4152 | (breg == 0 | |
4153 | ? mips_warn_about_macros | |
4154 | : 0)), | |
4155 | offset_expr.X_add_symbol, (long) 0, | |
4156 | (char *) NULL); | |
4157 | } | |
4158 | else | |
4159 | { | |
4160 | int adj, dreg; | |
4161 | ||
4162 | /* If we are going to add in a base register, and the | |
4163 | target register and the base register are the same, | |
4164 | then we are using AT as a temporary register. Since | |
4165 | we want to load the constant into AT, we add our | |
4166 | current AT (from the global offset table) and the | |
4167 | register into the register now, and pretend we were | |
4168 | not using a base register. */ | |
4169 | if (breg != treg) | |
4170 | { | |
4171 | adj = 0; | |
4172 | dreg = tempreg; | |
4173 | } | |
4174 | else | |
4175 | { | |
4176 | assert (tempreg == AT); | |
4177 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4178 | "nop", ""); | |
4179 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4180 | mips_isa < 3 ? "addu" : "daddu", | |
4181 | "d,v,t", treg, AT, breg); | |
4182 | dreg = treg; | |
4183 | adj = 8; | |
4184 | } | |
4185 | ||
4186 | /* Set mips_optimize around the lui instruction to avoid | |
4187 | inserting an unnecessary nop after the lw. */ | |
4188 | hold_mips_optimize = mips_optimize; | |
4189 | mips_optimize = 2; | |
4190 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4191 | mips_optimize = hold_mips_optimize; | |
4192 | ||
4193 | macro_build ((char *) NULL, &icnt, &expr1, | |
4194 | mips_isa < 3 ? "addiu" : "daddiu", | |
4195 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4197 | mips_isa < 3 ? "addu" : "daddu", | |
4198 | "d,v,t", dreg, dreg, AT); | |
4199 | ||
4200 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4201 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4202 | 8 + gpdel, 0, | |
4203 | (breg == 0 | |
4204 | ? mips_warn_about_macros | |
4205 | : 0)), | |
4206 | offset_expr.X_add_symbol, (long) 0, | |
4207 | (char *) NULL); | |
4208 | ||
4209 | used_at = 1; | |
4210 | } | |
4211 | ||
4212 | if (gpdel > 0) | |
4213 | { | |
4214 | /* This is needed because this instruction uses $gp, but | |
4215 | the first instruction on the main stream does not. */ | |
4216 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4217 | p += 4; | |
4218 | } | |
4219 | macro_build (p, &icnt, &offset_expr, | |
4220 | dbl ? "ld" : "lw", | |
4221 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4222 | p += 4; | |
4223 | if (expr1.X_add_number >= -0x8000 | |
4224 | && expr1.X_add_number < 0x8000) | |
4225 | { | |
4226 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4227 | p += 4; | |
4228 | macro_build (p, &icnt, &expr1, | |
4229 | mips_isa < 3 ? "addiu" : "daddiu", | |
4230 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4231 | /* FIXME: If add_number is 0, and there was no base | |
4232 | register, the external symbol case ended with a load, | |
4233 | so if the symbol turns out to not be external, and | |
4234 | the next instruction uses tempreg, an unnecessary nop | |
4235 | will be inserted. */ | |
4236 | } | |
4237 | else | |
4238 | { | |
4239 | if (breg == treg) | |
4240 | { | |
4241 | /* We must add in the base register now, as in the | |
4242 | external symbol case. */ | |
4243 | assert (tempreg == AT); | |
4244 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4245 | p += 4; | |
4246 | macro_build (p, &icnt, (expressionS *) NULL, | |
4247 | mips_isa < 3 ? "addu" : "daddu", | |
4248 | "d,v,t", treg, AT, breg); | |
4249 | p += 4; | |
4250 | tempreg = treg; | |
4251 | /* We set breg to 0 because we have arranged to add | |
4252 | it in in both cases. */ | |
4253 | breg = 0; | |
4254 | } | |
4255 | ||
4256 | macro_build_lui (p, &icnt, &expr1, AT); | |
4257 | p += 4; | |
4258 | macro_build (p, &icnt, &expr1, | |
4259 | mips_isa < 3 ? "addiu" : "daddiu", | |
4260 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4261 | p += 4; | |
4262 | macro_build (p, &icnt, (expressionS *) NULL, | |
4263 | mips_isa < 3 ? "addu" : "daddu", | |
4264 | "d,v,t", tempreg, tempreg, AT); | |
4265 | p += 4; | |
4266 | } | |
4267 | } | |
d9aba805 ILT |
4268 | else if (mips_pic == EMBEDDED_PIC) |
4269 | { | |
4270 | /* We use | |
4271 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4272 | */ | |
4273 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4274 | mips_isa < 3 ? "addiu" : "daddiu", | |
4275 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4276 | } | |
4277 | else | |
4278 | abort (); | |
0dd2d296 | 4279 | |
670a50eb | 4280 | if (breg != 0) |
0dd2d296 ILT |
4281 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4282 | mips_isa < 3 ? "addu" : "daddu", | |
4283 | "d,v,t", treg, tempreg, breg); | |
4284 | ||
4285 | if (! used_at) | |
4286 | return; | |
4287 | ||
4288 | break; | |
4289 | ||
4290 | case M_J_A: | |
4291 | /* The j instruction may not be used in PIC code, since it | |
4292 | requires an absolute address. We convert it to a b | |
4293 | instruction. */ | |
d9aba805 | 4294 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4295 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4296 | else | |
4297 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4298 | return; |
3d3c5039 | 4299 | |
9226253a ILT |
4300 | /* The jal instructions must be handled as macros because when |
4301 | generating PIC code they expand to multi-instruction | |
4302 | sequences. Normally they are simple instructions. */ | |
4303 | case M_JAL_1: | |
4304 | dreg = RA; | |
4305 | /* Fall through. */ | |
4306 | case M_JAL_2: | |
d9aba805 ILT |
4307 | if (mips_pic == NO_PIC |
4308 | || mips_pic == EMBEDDED_PIC) | |
4309 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4310 | "d,s", dreg, sreg); | |
4311 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4312 | { |
d9aba805 ILT |
4313 | if (sreg != PIC_CALL_REG) |
4314 | as_warn ("MIPS PIC call to register other than $25"); | |
4315 | ||
0dd2d296 ILT |
4316 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4317 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4318 | if (mips_cprestore_offset < 0) |
4319 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4320 | else | |
4321 | { | |
4322 | expr1.X_add_number = mips_cprestore_offset; | |
4323 | macro_build ((char *) NULL, &icnt, &expr1, | |
4324 | mips_isa < 3 ? "lw" : "ld", | |
4325 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4326 | } | |
9226253a | 4327 | } |
0dd2d296 | 4328 | else |
d9aba805 ILT |
4329 | abort (); |
4330 | ||
9226253a ILT |
4331 | return; |
4332 | ||
4333 | case M_JAL_A: | |
d9aba805 ILT |
4334 | if (mips_pic == NO_PIC) |
4335 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4336 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4337 | { |
fb251650 ILT |
4338 | /* If this is a reference to an external symbol, and we are |
4339 | using a small GOT, we want | |
d9aba805 ILT |
4340 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4341 | nop | |
4342 | jalr $25 | |
4343 | nop | |
4344 | lw $gp,cprestore($sp) | |
4345 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4346 | pseudo-op. If we are using a big GOT, we want |
4347 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4348 | addu $25,$25,$gp | |
4349 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4350 | nop | |
4351 | jalr $25 | |
4352 | nop | |
4353 | lw $gp,cprestore($sp) | |
4354 | If the symbol is not external, we want | |
d9aba805 ILT |
4355 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4356 | nop | |
4357 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4358 | jalr $25 | |
4359 | nop | |
fb251650 ILT |
4360 | lw $gp,cprestore($sp) */ |
4361 | frag_grow (40); | |
4362 | if (! mips_big_got) | |
4363 | { | |
4364 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4365 | mips_isa < 3 ? "lw" : "ld", | |
4366 | "t,o(b)", PIC_CALL_REG, | |
4367 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4368 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4369 | "nop", ""); | |
4370 | p = frag_var (rs_machine_dependent, 4, 0, | |
4371 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4372 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4373 | } | |
4374 | else | |
4375 | { | |
4376 | int gpdel; | |
4377 | ||
4378 | if (reg_needs_delay (GP)) | |
4379 | gpdel = 4; | |
4380 | else | |
4381 | gpdel = 0; | |
4382 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4383 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4384 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4385 | mips_isa < 3 ? "addu" : "daddu", | |
4386 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4387 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4388 | mips_isa < 3 ? "lw" : "ld", | |
4389 | "t,o(b)", PIC_CALL_REG, | |
4390 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4391 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4392 | "nop", ""); | |
4393 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4394 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4395 | 0, 0), | |
4396 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4397 | if (gpdel > 0) | |
4398 | { | |
4399 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4400 | p += 4; | |
4401 | } | |
4402 | macro_build (p, &icnt, &offset_expr, | |
4403 | mips_isa < 3 ? "lw" : "ld", | |
4404 | "t,o(b)", PIC_CALL_REG, | |
4405 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4406 | p += 4; | |
4407 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4408 | p += 4; | |
4409 | } | |
d9aba805 ILT |
4410 | macro_build (p, &icnt, &offset_expr, |
4411 | mips_isa < 3 ? "addiu" : "daddiu", | |
4412 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4413 | (int) BFD_RELOC_LO16); | |
4414 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4415 | "jalr", "s", PIC_CALL_REG); | |
4416 | if (mips_cprestore_offset < 0) | |
4417 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4418 | else | |
4419 | { | |
4420 | if (mips_noreorder) | |
4421 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4422 | "nop", ""); | |
4423 | expr1.X_add_number = mips_cprestore_offset; | |
4424 | macro_build ((char *) NULL, &icnt, &expr1, | |
4425 | mips_isa < 3 ? "lw" : "ld", | |
4426 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4427 | mips_frame_reg); | |
4428 | } | |
0dd2d296 | 4429 | } |
d9aba805 | 4430 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4431 | { |
4432 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4433 | /* The linker may expand the call to a longer sequence which | |
4434 | uses $at, so we must break rather than return. */ | |
4435 | break; | |
4436 | } | |
d9aba805 ILT |
4437 | else |
4438 | abort (); | |
4439 | ||
9226253a ILT |
4440 | return; |
4441 | ||
3d3c5039 | 4442 | case M_LB_AB: |
670a50eb ILT |
4443 | s = "lb"; |
4444 | goto ld; | |
3d3c5039 | 4445 | case M_LBU_AB: |
670a50eb ILT |
4446 | s = "lbu"; |
4447 | goto ld; | |
3d3c5039 | 4448 | case M_LH_AB: |
670a50eb ILT |
4449 | s = "lh"; |
4450 | goto ld; | |
3d3c5039 | 4451 | case M_LHU_AB: |
670a50eb ILT |
4452 | s = "lhu"; |
4453 | goto ld; | |
3d3c5039 | 4454 | case M_LW_AB: |
670a50eb ILT |
4455 | s = "lw"; |
4456 | goto ld; | |
3d3c5039 | 4457 | case M_LWC0_AB: |
670a50eb | 4458 | s = "lwc0"; |
efec4a28 | 4459 | /* Itbl support may require additional care here. */ |
8358c818 | 4460 | coproc = 1; |
670a50eb | 4461 | goto ld; |
3d3c5039 | 4462 | case M_LWC1_AB: |
670a50eb | 4463 | s = "lwc1"; |
efec4a28 | 4464 | /* Itbl support may require additional care here. */ |
8358c818 | 4465 | coproc = 1; |
670a50eb | 4466 | goto ld; |
3d3c5039 | 4467 | case M_LWC2_AB: |
670a50eb | 4468 | s = "lwc2"; |
efec4a28 | 4469 | /* Itbl support may require additional care here. */ |
8358c818 | 4470 | coproc = 1; |
670a50eb | 4471 | goto ld; |
3d3c5039 | 4472 | case M_LWC3_AB: |
670a50eb | 4473 | s = "lwc3"; |
efec4a28 | 4474 | /* Itbl support may require additional care here. */ |
8358c818 | 4475 | coproc = 1; |
670a50eb | 4476 | goto ld; |
3d3c5039 | 4477 | case M_LWL_AB: |
670a50eb | 4478 | s = "lwl"; |
b2b8c24e | 4479 | lr = 1; |
670a50eb | 4480 | goto ld; |
3d3c5039 | 4481 | case M_LWR_AB: |
670a50eb | 4482 | s = "lwr"; |
b2b8c24e | 4483 | lr = 1; |
8358c818 ILT |
4484 | goto ld; |
4485 | case M_LDC1_AB: | |
4486 | s = "ldc1"; | |
efec4a28 | 4487 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4488 | coproc = 1; |
4489 | goto ld; | |
4490 | case M_LDC2_AB: | |
4491 | s = "ldc2"; | |
efec4a28 | 4492 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4493 | coproc = 1; |
4494 | goto ld; | |
4495 | case M_LDC3_AB: | |
4496 | s = "ldc3"; | |
efec4a28 | 4497 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4498 | coproc = 1; |
4499 | goto ld; | |
4500 | case M_LDL_AB: | |
4501 | s = "ldl"; | |
b2b8c24e | 4502 | lr = 1; |
8358c818 ILT |
4503 | goto ld; |
4504 | case M_LDR_AB: | |
4505 | s = "ldr"; | |
b2b8c24e | 4506 | lr = 1; |
8358c818 ILT |
4507 | goto ld; |
4508 | case M_LL_AB: | |
4509 | s = "ll"; | |
4510 | goto ld; | |
4511 | case M_LLD_AB: | |
4512 | s = "lld"; | |
4513 | goto ld; | |
4514 | case M_LWU_AB: | |
4515 | s = "lwu"; | |
3d3c5039 | 4516 | ld: |
b2b8c24e | 4517 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4518 | { |
4519 | tempreg = AT; | |
4520 | used_at = 1; | |
4521 | } | |
4522 | else | |
4523 | { | |
4524 | tempreg = treg; | |
4525 | used_at = 0; | |
4526 | } | |
4527 | goto ld_st; | |
3d3c5039 | 4528 | case M_SB_AB: |
670a50eb ILT |
4529 | s = "sb"; |
4530 | goto st; | |
3d3c5039 | 4531 | case M_SH_AB: |
670a50eb ILT |
4532 | s = "sh"; |
4533 | goto st; | |
3d3c5039 | 4534 | case M_SW_AB: |
670a50eb ILT |
4535 | s = "sw"; |
4536 | goto st; | |
3d3c5039 | 4537 | case M_SWC0_AB: |
670a50eb | 4538 | s = "swc0"; |
efec4a28 | 4539 | /* Itbl support may require additional care here. */ |
8358c818 | 4540 | coproc = 1; |
670a50eb | 4541 | goto st; |
3d3c5039 | 4542 | case M_SWC1_AB: |
670a50eb | 4543 | s = "swc1"; |
efec4a28 | 4544 | /* Itbl support may require additional care here. */ |
8358c818 | 4545 | coproc = 1; |
670a50eb | 4546 | goto st; |
3d3c5039 | 4547 | case M_SWC2_AB: |
670a50eb | 4548 | s = "swc2"; |
efec4a28 | 4549 | /* Itbl support may require additional care here. */ |
8358c818 | 4550 | coproc = 1; |
670a50eb | 4551 | goto st; |
3d3c5039 | 4552 | case M_SWC3_AB: |
670a50eb | 4553 | s = "swc3"; |
efec4a28 | 4554 | /* Itbl support may require additional care here. */ |
8358c818 | 4555 | coproc = 1; |
670a50eb | 4556 | goto st; |
3d3c5039 | 4557 | case M_SWL_AB: |
670a50eb ILT |
4558 | s = "swl"; |
4559 | goto st; | |
3d3c5039 | 4560 | case M_SWR_AB: |
670a50eb | 4561 | s = "swr"; |
8358c818 ILT |
4562 | goto st; |
4563 | case M_SC_AB: | |
4564 | s = "sc"; | |
4565 | goto st; | |
4566 | case M_SCD_AB: | |
4567 | s = "scd"; | |
4568 | goto st; | |
4569 | case M_SDC1_AB: | |
4570 | s = "sdc1"; | |
4571 | coproc = 1; | |
efec4a28 | 4572 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4573 | goto st; |
4574 | case M_SDC2_AB: | |
4575 | s = "sdc2"; | |
efec4a28 | 4576 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4577 | coproc = 1; |
4578 | goto st; | |
4579 | case M_SDC3_AB: | |
4580 | s = "sdc3"; | |
efec4a28 | 4581 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4582 | coproc = 1; |
4583 | goto st; | |
4584 | case M_SDL_AB: | |
4585 | s = "sdl"; | |
4586 | goto st; | |
4587 | case M_SDR_AB: | |
4588 | s = "sdr"; | |
3d3c5039 | 4589 | st: |
670a50eb ILT |
4590 | tempreg = AT; |
4591 | used_at = 1; | |
3d3c5039 | 4592 | ld_st: |
efec4a28 | 4593 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4594 | if (mask == M_LWC1_AB |
4595 | || mask == M_SWC1_AB | |
8358c818 | 4596 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4597 | || mask == M_SDC1_AB |
4598 | || mask == M_L_DAB | |
4599 | || mask == M_S_DAB) | |
670a50eb | 4600 | fmt = "T,o(b)"; |
8358c818 | 4601 | else if (coproc) |
19ed8960 | 4602 | fmt = "E,o(b)"; |
670a50eb ILT |
4603 | else |
4604 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4605 | |
4606 | if (offset_expr.X_op != O_constant | |
4607 | && offset_expr.X_op != O_symbol) | |
4608 | { | |
4609 | as_bad ("expression too complex"); | |
4610 | offset_expr.X_op = O_constant; | |
4611 | } | |
4612 | ||
4613 | /* A constant expression in PIC code can be handled just as it | |
4614 | is in non PIC code. */ | |
d9aba805 | 4615 | if (mips_pic == NO_PIC |
0dd2d296 | 4616 | || offset_expr.X_op == O_constant) |
670a50eb | 4617 | { |
0dd2d296 ILT |
4618 | /* If this is a reference to a GP relative symbol, and there |
4619 | is no base register, we want | |
4620 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4621 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4622 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4623 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4624 | If we have a constant, we need two instructions anyhow, | |
4625 | so we always use the latter form. | |
4626 | ||
4627 | If we have a base register, and this is a reference to a | |
4628 | GP relative symbol, we want | |
4629 | addu $tempreg,$breg,$gp | |
4630 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4631 | Otherwise we want | |
4632 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4633 | addu $tempreg,$tempreg,$breg | |
4634 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4635 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4636 | if (breg == 0) |
4637 | { | |
7a15a226 | 4638 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4639 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4640 | p = NULL; |
4641 | else | |
4642 | { | |
8ea7f4e8 | 4643 | frag_grow (20); |
0dd2d296 ILT |
4644 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4645 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4646 | p = frag_var (rs_machine_dependent, 8, 0, | |
4647 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4648 | (mips_warn_about_macros |
4649 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4650 | offset_expr.X_add_symbol, (long) 0, |
4651 | (char *) NULL); | |
8197b589 | 4652 | used_at = 0; |
0dd2d296 ILT |
4653 | } |
4654 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4655 | if (p != NULL) | |
4656 | p += 4; | |
4657 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4658 | (int) BFD_RELOC_LO16, tempreg); | |
4659 | } | |
4660 | else | |
4661 | { | |
7a15a226 | 4662 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4663 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4664 | p = NULL; |
4665 | else | |
4666 | { | |
8ea7f4e8 | 4667 | frag_grow (28); |
0dd2d296 ILT |
4668 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4669 | mips_isa < 3 ? "addu" : "daddu", | |
4670 | "d,v,t", tempreg, breg, GP); | |
4671 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4672 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4673 | p = frag_var (rs_machine_dependent, 12, 0, | |
4674 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4675 | offset_expr.X_add_symbol, (long) 0, | |
4676 | (char *) NULL); | |
4677 | } | |
4678 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4679 | if (p != NULL) | |
4680 | p += 4; | |
4681 | macro_build (p, &icnt, (expressionS *) NULL, | |
4682 | mips_isa < 3 ? "addu" : "daddu", | |
4683 | "d,v,t", tempreg, tempreg, breg); | |
4684 | if (p != NULL) | |
4685 | p += 4; | |
4686 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4687 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4688 | } |
670a50eb | 4689 | } |
fb251650 | 4690 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4691 | { |
0dd2d296 ILT |
4692 | /* If this is a reference to an external symbol, we want |
4693 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4694 | nop | |
4695 | <op> $treg,0($tempreg) | |
4696 | Otherwise we want | |
4697 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4698 | nop | |
4699 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4700 | <op> $treg,0($tempreg) | |
4701 | If there is a base register, we add it to $tempreg before | |
4702 | the <op>. If there is a constant, we stick it in the | |
4703 | <op> instruction. We don't handle constants larger than | |
4704 | 16 bits, because we have no way to load the upper 16 bits | |
4705 | (actually, we could handle them for the subset of cases | |
4706 | in which we are not using $at). */ | |
4707 | assert (offset_expr.X_op == O_symbol); | |
4708 | expr1.X_add_number = offset_expr.X_add_number; | |
4709 | offset_expr.X_add_number = 0; | |
4710 | if (expr1.X_add_number < -0x8000 | |
4711 | || expr1.X_add_number >= 0x8000) | |
4712 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4713 | frag_grow (20); |
0dd2d296 ILT |
4714 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4715 | mips_isa < 3 ? "lw" : "ld", | |
4716 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4718 | p = frag_var (rs_machine_dependent, 4, 0, | |
4719 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4720 | offset_expr.X_add_symbol, (long) 0, | |
4721 | (char *) NULL); | |
4722 | macro_build (p, &icnt, &offset_expr, | |
4723 | mips_isa < 3 ? "addiu" : "daddiu", | |
4724 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4725 | if (breg != 0) |
0dd2d296 | 4726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4727 | mips_isa < 3 ? "addu" : "daddu", |
4728 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4729 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4730 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4731 | } |
fb251650 ILT |
4732 | else if (mips_pic == SVR4_PIC) |
4733 | { | |
4734 | int gpdel; | |
4735 | ||
4736 | /* If this is a reference to an external symbol, we want | |
4737 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4738 | addu $tempreg,$tempreg,$gp | |
4739 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4740 | <op> $treg,0($tempreg) | |
4741 | Otherwise we want | |
4742 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4743 | nop | |
4744 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4745 | <op> $treg,0($tempreg) | |
4746 | If there is a base register, we add it to $tempreg before | |
4747 | the <op>. If there is a constant, we stick it in the | |
4748 | <op> instruction. We don't handle constants larger than | |
4749 | 16 bits, because we have no way to load the upper 16 bits | |
4750 | (actually, we could handle them for the subset of cases | |
4751 | in which we are not using $at). */ | |
4752 | assert (offset_expr.X_op == O_symbol); | |
4753 | expr1.X_add_number = offset_expr.X_add_number; | |
4754 | offset_expr.X_add_number = 0; | |
4755 | if (expr1.X_add_number < -0x8000 | |
4756 | || expr1.X_add_number >= 0x8000) | |
4757 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4758 | if (reg_needs_delay (GP)) | |
4759 | gpdel = 4; | |
4760 | else | |
4761 | gpdel = 0; | |
4762 | frag_grow (36); | |
4763 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4764 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4765 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4766 | mips_isa < 3 ? "addu" : "daddu", | |
4767 | "d,v,t", tempreg, tempreg, GP); | |
4768 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4769 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4770 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4771 | tempreg); | |
fb251650 ILT |
4772 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4773 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4774 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4775 | if (gpdel > 0) | |
4776 | { | |
4777 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4778 | p += 4; | |
4779 | } | |
4780 | macro_build (p, &icnt, &offset_expr, | |
4781 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4782 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4783 | p += 4; |
4784 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4785 | p += 4; | |
4786 | macro_build (p, &icnt, &offset_expr, | |
4787 | mips_isa < 3 ? "addiu" : "daddiu", | |
4788 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4789 | if (breg != 0) | |
4790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4791 | mips_isa < 3 ? "addu" : "daddu", | |
4792 | "d,v,t", tempreg, tempreg, breg); | |
4793 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4794 | (int) BFD_RELOC_LO16, tempreg); | |
4795 | } | |
d9aba805 ILT |
4796 | else if (mips_pic == EMBEDDED_PIC) |
4797 | { | |
4798 | /* If there is no base register, we want | |
4799 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4800 | If there is a base register, we want | |
4801 | addu $tempreg,$breg,$gp | |
4802 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4803 | */ | |
4804 | assert (offset_expr.X_op == O_symbol); | |
4805 | if (breg == 0) | |
4806 | { | |
4807 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4808 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4809 | used_at = 0; | |
4810 | } | |
4811 | else | |
4812 | { | |
4813 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4814 | mips_isa < 3 ? "addu" : "daddu", | |
4815 | "d,v,t", tempreg, breg, GP); | |
4816 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4817 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4818 | } | |
4819 | } | |
4820 | else | |
4821 | abort (); | |
0dd2d296 ILT |
4822 | |
4823 | if (! used_at) | |
4824 | return; | |
4825 | ||
4826 | break; | |
3d3c5039 ILT |
4827 | |
4828 | case M_LI: | |
19ed8960 | 4829 | case M_LI_S: |
d8a1c247 KR |
4830 | load_register (&icnt, treg, &imm_expr, 0); |
4831 | return; | |
4832 | ||
4833 | case M_DLI: | |
4834 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4835 | return; |
3d3c5039 | 4836 | |
0dd2d296 | 4837 | case M_LI_SS: |
55933a58 | 4838 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4839 | { |
d8a1c247 | 4840 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4842 | "mtc1", "t,G", AT, treg); | |
4843 | break; | |
0dd2d296 | 4844 | } |
d9aba805 | 4845 | else |
d2c71068 | 4846 | { |
55933a58 ILT |
4847 | assert (offset_expr.X_op == O_symbol |
4848 | && strcmp (segment_name (S_GET_SEGMENT | |
4849 | (offset_expr.X_add_symbol)), | |
4850 | ".lit4") == 0 | |
4851 | && offset_expr.X_add_number == 0); | |
4852 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4853 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4854 | return; |
4855 | } | |
0dd2d296 | 4856 | |
3d3c5039 | 4857 | case M_LI_D: |
d9aba805 ILT |
4858 | /* We know that sym is in the .rdata section. First we get the |
4859 | upper 16 bits of the address. */ | |
4860 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4861 | { |
4862 | /* FIXME: This won't work for a 64 bit address. */ | |
4863 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4864 | } | |
d9aba805 | 4865 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4866 | { |
4867 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4868 | mips_isa < 3 ? "lw" : "ld", | |
4869 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4870 | } | |
d9aba805 ILT |
4871 | else if (mips_pic == EMBEDDED_PIC) |
4872 | { | |
4873 | /* For embedded PIC we pick up the entire address off $gp in | |
4874 | a single instruction. */ | |
4875 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4876 | mips_isa < 3 ? "addiu" : "daddiu", | |
4877 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4878 | offset_expr.X_op = O_constant; | |
4879 | offset_expr.X_add_number = 0; | |
4880 | } | |
4881 | else | |
4882 | abort (); | |
4883 | ||
0dd2d296 | 4884 | /* Now we load the register(s). */ |
8358c818 | 4885 | if (mips_isa >= 3) |
0dd2d296 ILT |
4886 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4887 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4888 | else |
4889 | { | |
0dd2d296 ILT |
4890 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4891 | treg, (int) BFD_RELOC_LO16, AT); | |
4892 | if (treg != 31) | |
4893 | { | |
4894 | /* FIXME: How in the world do we deal with the possible | |
4895 | overflow here? */ | |
4896 | offset_expr.X_add_number += 4; | |
4897 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4898 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4899 | } | |
8358c818 | 4900 | } |
d2c71068 ILT |
4901 | |
4902 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4903 | does not become a variant frag. */ | |
4904 | frag_wane (frag_now); | |
4905 | frag_new (0); | |
4906 | ||
670a50eb | 4907 | break; |
3d3c5039 ILT |
4908 | |
4909 | case M_LI_DD: | |
55933a58 ILT |
4910 | assert (offset_expr.X_op == O_symbol |
4911 | && offset_expr.X_add_number == 0); | |
4912 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4913 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4914 | { |
0dd2d296 ILT |
4915 | if (mips_isa >= 2) |
4916 | { | |
4917 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4918 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4919 | return; | |
4920 | } | |
4921 | breg = GP; | |
4922 | r = BFD_RELOC_MIPS_LITERAL; | |
4923 | goto dob; | |
4924 | } | |
55933a58 | 4925 | else |
0dd2d296 | 4926 | { |
55933a58 ILT |
4927 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4928 | if (mips_pic == SVR4_PIC) | |
4929 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4930 | mips_isa < 3 ? "lw" : "ld", | |
4931 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4932 | else | |
4933 | { | |
4934 | /* FIXME: This won't work for a 64 bit address. */ | |
4935 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4936 | } | |
4937 | ||
0dd2d296 ILT |
4938 | if (mips_isa >= 2) |
4939 | { | |
4940 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4941 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4942 | |
4943 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4944 | that this does not become a variant frag. */ | |
4945 | frag_wane (frag_now); | |
4946 | frag_new (0); | |
4947 | ||
0dd2d296 ILT |
4948 | break; |
4949 | } | |
4950 | breg = AT; | |
4951 | r = BFD_RELOC_LO16; | |
4952 | goto dob; | |
8358c818 | 4953 | } |
9226253a | 4954 | |
3d3c5039 | 4955 | case M_L_DOB: |
9a7d824a ILT |
4956 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4957 | to adjust when loading from memory. */ | |
9226253a ILT |
4958 | r = BFD_RELOC_LO16; |
4959 | dob: | |
8358c818 | 4960 | assert (mips_isa < 2); |
0dd2d296 | 4961 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4962 | target_big_endian ? treg + 1 : treg, |
9226253a | 4963 | (int) r, breg); |
0dd2d296 ILT |
4964 | /* FIXME: A possible overflow which I don't know how to deal |
4965 | with. */ | |
670a50eb | 4966 | offset_expr.X_add_number += 4; |
0dd2d296 | 4967 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4968 | target_big_endian ? treg : treg + 1, |
9226253a | 4969 | (int) r, breg); |
d2c71068 ILT |
4970 | |
4971 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4972 | does not become a variant frag. */ | |
4973 | frag_wane (frag_now); | |
4974 | frag_new (0); | |
4975 | ||
0dd2d296 ILT |
4976 | if (breg != AT) |
4977 | return; | |
4978 | break; | |
3d3c5039 ILT |
4979 | |
4980 | case M_L_DAB: | |
670a50eb ILT |
4981 | /* |
4982 | * The MIPS assembler seems to check for X_add_number not | |
4983 | * being double aligned and generating: | |
4984 | * lui at,%hi(foo+1) | |
4985 | * addu at,at,v1 | |
4986 | * addiu at,at,%lo(foo+1) | |
4987 | * lwc1 f2,0(at) | |
4988 | * lwc1 f3,4(at) | |
4989 | * But, the resulting address is the same after relocation so why | |
4990 | * generate the extra instruction? | |
4991 | */ | |
efec4a28 | 4992 | /* Itbl support may require additional care here. */ |
4032d3f0 | 4993 | coproc = 1; |
0dd2d296 | 4994 | if (mips_isa >= 2) |
670a50eb | 4995 | { |
0dd2d296 ILT |
4996 | s = "ldc1"; |
4997 | goto ld; | |
670a50eb | 4998 | } |
0dd2d296 ILT |
4999 | |
5000 | s = "lwc1"; | |
5001 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5002 | goto ldd_std; |
5003 | ||
5004 | case M_S_DAB: | |
8358c818 | 5005 | if (mips_isa >= 2) |
8358c818 | 5006 | { |
0dd2d296 ILT |
5007 | s = "sdc1"; |
5008 | goto st; | |
8358c818 | 5009 | } |
3d3c5039 | 5010 | |
0dd2d296 ILT |
5011 | s = "swc1"; |
5012 | fmt = "T,o(b)"; | |
efec4a28 | 5013 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5014 | coproc = 1; |
5015 | goto ldd_std; | |
3d3c5039 ILT |
5016 | |
5017 | case M_LD_AB: | |
0dd2d296 | 5018 | if (mips_isa >= 3) |
670a50eb | 5019 | { |
0dd2d296 ILT |
5020 | s = "ld"; |
5021 | goto ld; | |
670a50eb | 5022 | } |
0dd2d296 ILT |
5023 | |
5024 | s = "lw"; | |
5025 | fmt = "t,o(b)"; | |
5026 | goto ldd_std; | |
5027 | ||
5028 | case M_SD_AB: | |
5029 | if (mips_isa >= 3) | |
670a50eb | 5030 | { |
0dd2d296 ILT |
5031 | s = "sd"; |
5032 | goto st; | |
670a50eb | 5033 | } |
0dd2d296 | 5034 | |
670a50eb | 5035 | s = "sw"; |
0dd2d296 ILT |
5036 | fmt = "t,o(b)"; |
5037 | ||
5038 | ldd_std: | |
5039 | if (offset_expr.X_op != O_symbol | |
5040 | && offset_expr.X_op != O_constant) | |
670a50eb | 5041 | { |
0dd2d296 ILT |
5042 | as_bad ("expression too complex"); |
5043 | offset_expr.X_op = O_constant; | |
5044 | } | |
5045 | ||
5046 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5047 | to adjust when loading from memory. We set coproc if we must | |
5048 | load $fn+1 first. */ | |
efec4a28 | 5049 | /* Itbl support may require additional care here. */ |
b9129c6f | 5050 | if (! target_big_endian) |
0dd2d296 ILT |
5051 | coproc = 0; |
5052 | ||
d9aba805 | 5053 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5054 | || offset_expr.X_op == O_constant) |
5055 | { | |
5056 | /* If this is a reference to a GP relative symbol, we want | |
5057 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5058 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5059 | If we have a base register, we use this | |
5060 | addu $at,$breg,$gp | |
5061 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5062 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5063 | If this is not a GP relative symbol, we want | |
5064 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5065 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5066 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5067 | If there is a base register, we add it to $at after the | |
5068 | lui instruction. If there is a constant, we always use | |
5069 | the last case. */ | |
7a15a226 | 5070 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 5071 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 5072 | { |
0dd2d296 ILT |
5073 | p = NULL; |
5074 | used_at = 1; | |
670a50eb ILT |
5075 | } |
5076 | else | |
0dd2d296 ILT |
5077 | { |
5078 | int off; | |
5079 | ||
5080 | if (breg == 0) | |
5081 | { | |
8ea7f4e8 | 5082 | frag_grow (28); |
0dd2d296 ILT |
5083 | tempreg = GP; |
5084 | off = 0; | |
5085 | used_at = 0; | |
5086 | } | |
5087 | else | |
5088 | { | |
8ea7f4e8 | 5089 | frag_grow (36); |
0dd2d296 ILT |
5090 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5091 | mips_isa < 3 ? "addu" : "daddu", | |
5092 | "d,v,t", AT, breg, GP); | |
5093 | tempreg = AT; | |
5094 | off = 4; | |
5095 | used_at = 1; | |
5096 | } | |
5097 | ||
efec4a28 | 5098 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5099 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5100 | coproc ? treg + 1 : treg, | |
5101 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5102 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5103 | |
5104 | /* Set mips_optimize to 2 to avoid inserting an | |
5105 | undesired nop. */ | |
5106 | hold_mips_optimize = mips_optimize; | |
5107 | mips_optimize = 2; | |
efec4a28 | 5108 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5109 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5110 | coproc ? treg : treg + 1, | |
5111 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5112 | mips_optimize = hold_mips_optimize; |
5113 | ||
0dd2d296 ILT |
5114 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5115 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 5116 | used_at && mips_noat), |
0dd2d296 ILT |
5117 | offset_expr.X_add_symbol, (long) 0, |
5118 | (char *) NULL); | |
777ad64d ILT |
5119 | |
5120 | /* We just generated two relocs. When tc_gen_reloc | |
5121 | handles this case, it will skip the first reloc and | |
5122 | handle the second. The second reloc already has an | |
5123 | extra addend of 4, which we added above. We must | |
5124 | subtract it out, and then subtract another 4 to make | |
5125 | the first reloc come out right. The second reloc | |
5126 | will come out right because we are going to add 4 to | |
5127 | offset_expr when we build its instruction below. */ | |
5128 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
5129 | offset_expr.X_op = O_constant; |
5130 | } | |
5131 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5132 | if (p != NULL) | |
5133 | p += 4; | |
5134 | if (breg != 0) | |
5135 | { | |
5136 | macro_build (p, &icnt, (expressionS *) NULL, | |
5137 | mips_isa < 3 ? "addu" : "daddu", | |
5138 | "d,v,t", AT, breg, AT); | |
5139 | if (p != NULL) | |
5140 | p += 4; | |
5141 | } | |
efec4a28 | 5142 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5143 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5144 | coproc ? treg + 1 : treg, | |
5145 | (int) BFD_RELOC_LO16, AT); | |
5146 | if (p != NULL) | |
5147 | p += 4; | |
5148 | /* FIXME: How do we handle overflow here? */ | |
5149 | offset_expr.X_add_number += 4; | |
efec4a28 | 5150 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5151 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5152 | coproc ? treg : treg + 1, | |
5153 | (int) BFD_RELOC_LO16, AT); | |
5154 | } | |
fb251650 | 5155 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5156 | { |
0dd2d296 ILT |
5157 | int off; |
5158 | ||
5159 | /* If this is a reference to an external symbol, we want | |
5160 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5161 | nop | |
5162 | <op> $treg,0($at) | |
5163 | <op> $treg+1,4($at) | |
5164 | Otherwise we want | |
5165 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5166 | nop | |
5167 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5168 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5169 | If there is a base register we add it to $at before the | |
5170 | lwc1 instructions. If there is a constant we include it | |
5171 | in the lwc1 instructions. */ | |
5172 | used_at = 1; | |
5173 | expr1.X_add_number = offset_expr.X_add_number; | |
5174 | offset_expr.X_add_number = 0; | |
5175 | if (expr1.X_add_number < -0x8000 | |
5176 | || expr1.X_add_number >= 0x8000 - 4) | |
5177 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5178 | if (breg == 0) | |
5179 | off = 0; | |
5180 | else | |
5181 | off = 4; | |
8ea7f4e8 | 5182 | frag_grow (24 + off); |
0dd2d296 ILT |
5183 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5184 | mips_isa < 3 ? "lw" : "ld", | |
5185 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5186 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5187 | if (breg != 0) |
0dd2d296 | 5188 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 5189 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5190 | "d,v,t", AT, breg, AT); |
efec4a28 | 5191 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5192 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5193 | coproc ? treg + 1 : treg, | |
5194 | (int) BFD_RELOC_LO16, AT); | |
5195 | expr1.X_add_number += 4; | |
55933a58 ILT |
5196 | |
5197 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5198 | nop. */ | |
5199 | hold_mips_optimize = mips_optimize; | |
5200 | mips_optimize = 2; | |
efec4a28 | 5201 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5202 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5203 | coproc ? treg : treg + 1, | |
5204 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5205 | mips_optimize = hold_mips_optimize; |
5206 | ||
0dd2d296 ILT |
5207 | (void) frag_var (rs_machine_dependent, 0, 0, |
5208 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5209 | offset_expr.X_add_symbol, (long) 0, | |
5210 | (char *) NULL); | |
8358c818 | 5211 | } |
fb251650 ILT |
5212 | else if (mips_pic == SVR4_PIC) |
5213 | { | |
5214 | int gpdel, off; | |
5215 | ||
5216 | /* If this is a reference to an external symbol, we want | |
5217 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5218 | addu $at,$at,$gp | |
5219 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5220 | nop | |
5221 | <op> $treg,0($at) | |
5222 | <op> $treg+1,4($at) | |
5223 | Otherwise we want | |
5224 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5225 | nop | |
5226 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5227 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5228 | If there is a base register we add it to $at before the | |
5229 | lwc1 instructions. If there is a constant we include it | |
5230 | in the lwc1 instructions. */ | |
5231 | used_at = 1; | |
5232 | expr1.X_add_number = offset_expr.X_add_number; | |
5233 | offset_expr.X_add_number = 0; | |
5234 | if (expr1.X_add_number < -0x8000 | |
5235 | || expr1.X_add_number >= 0x8000 - 4) | |
5236 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5237 | if (reg_needs_delay (GP)) | |
5238 | gpdel = 4; | |
5239 | else | |
5240 | gpdel = 0; | |
5241 | if (breg == 0) | |
5242 | off = 0; | |
5243 | else | |
5244 | off = 4; | |
5245 | frag_grow (56); | |
5246 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5247 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5248 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5249 | mips_isa < 3 ? "addu" : "daddu", | |
5250 | "d,v,t", AT, AT, GP); | |
5251 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5252 | mips_isa < 3 ? "lw" : "ld", | |
5253 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5254 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5255 | if (breg != 0) | |
5256 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5257 | mips_isa < 3 ? "addu" : "daddu", | |
5258 | "d,v,t", AT, breg, AT); | |
efec4a28 | 5259 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5260 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5261 | coproc ? treg + 1 : treg, | |
5262 | (int) BFD_RELOC_LO16, AT); | |
5263 | expr1.X_add_number += 4; | |
5264 | ||
5265 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5266 | nop. */ | |
5267 | hold_mips_optimize = mips_optimize; | |
5268 | mips_optimize = 2; | |
efec4a28 | 5269 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5270 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5271 | coproc ? treg : treg + 1, | |
5272 | (int) BFD_RELOC_LO16, AT); | |
5273 | mips_optimize = hold_mips_optimize; | |
5274 | expr1.X_add_number -= 4; | |
5275 | ||
5276 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5277 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5278 | 8 + gpdel + off, 1, 0), | |
5279 | offset_expr.X_add_symbol, (long) 0, | |
5280 | (char *) NULL); | |
5281 | if (gpdel > 0) | |
5282 | { | |
5283 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5284 | p += 4; | |
5285 | } | |
5286 | macro_build (p, &icnt, &offset_expr, | |
5287 | mips_isa < 3 ? "lw" : "ld", | |
5288 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5289 | p += 4; | |
5290 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5291 | p += 4; | |
5292 | if (breg != 0) | |
5293 | { | |
5294 | macro_build (p, &icnt, (expressionS *) NULL, | |
5295 | mips_isa < 3 ? "addu" : "daddu", | |
5296 | "d,v,t", AT, breg, AT); | |
5297 | p += 4; | |
5298 | } | |
efec4a28 | 5299 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5300 | macro_build (p, &icnt, &expr1, s, fmt, |
5301 | coproc ? treg + 1 : treg, | |
5302 | (int) BFD_RELOC_LO16, AT); | |
5303 | p += 4; | |
5304 | expr1.X_add_number += 4; | |
5305 | ||
5306 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5307 | nop. */ | |
5308 | hold_mips_optimize = mips_optimize; | |
5309 | mips_optimize = 2; | |
efec4a28 | 5310 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5311 | macro_build (p, &icnt, &expr1, s, fmt, |
5312 | coproc ? treg : treg + 1, | |
5313 | (int) BFD_RELOC_LO16, AT); | |
5314 | mips_optimize = hold_mips_optimize; | |
5315 | } | |
d9aba805 ILT |
5316 | else if (mips_pic == EMBEDDED_PIC) |
5317 | { | |
5318 | /* If there is no base register, we use | |
5319 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5320 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5321 | If we have a base register, we use | |
5322 | addu $at,$breg,$gp | |
5323 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5324 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5325 | */ | |
5326 | if (breg == 0) | |
5327 | { | |
5328 | tempreg = GP; | |
5329 | used_at = 0; | |
5330 | } | |
5331 | else | |
5332 | { | |
5333 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5334 | mips_isa < 3 ? "addu" : "daddu", | |
5335 | "d,v,t", AT, breg, GP); | |
5336 | tempreg = AT; | |
5337 | used_at = 1; | |
5338 | } | |
5339 | ||
efec4a28 | 5340 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5341 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5342 | coproc ? treg + 1 : treg, | |
5343 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5344 | offset_expr.X_add_number += 4; | |
efec4a28 | 5345 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5346 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5347 | coproc ? treg : treg + 1, | |
5348 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5349 | } | |
5350 | else | |
5351 | abort (); | |
0dd2d296 ILT |
5352 | |
5353 | if (! used_at) | |
5354 | return; | |
5355 | ||
5356 | break; | |
5357 | ||
5358 | case M_LD_OB: | |
5359 | s = "lw"; | |
5360 | goto sd_ob; | |
5361 | case M_SD_OB: | |
5362 | s = "sw"; | |
5363 | sd_ob: | |
5364 | assert (mips_isa < 3); | |
5365 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5366 | (int) BFD_RELOC_LO16, breg); | |
5367 | offset_expr.X_add_number += 4; | |
5368 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5369 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5370 | return; |
efec4a28 DP |
5371 | |
5372 | /* New code added to support COPZ instructions. | |
5373 | This code builds table entries out of the macros in mip_opcodes. | |
5374 | R4000 uses interlocks to handle coproc delays. | |
5375 | Other chips (like the R3000) require nops to be inserted for delays. | |
5376 | ||
5377 | FIXME: Currently, we require that the user handle delays. | |
5378 | In order to fill delay slots for non-interlocked chips, | |
5379 | we must have a way to specify delays based on the coprocessor. | |
5380 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5381 | What are the side-effects of the cop instruction? | |
5382 | What cache support might we have and what are its effects? | |
5383 | Both coprocessor & memory require delays. how long??? | |
5384 | What registers are read/set/modified? | |
5385 | ||
5386 | If an itbl is provided to interpret cop instructions, | |
5387 | this knowledge can be encoded in the itbl spec. */ | |
5388 | ||
5389 | case M_COP0: | |
5390 | s = "cop0"; | |
5391 | goto copz; | |
5392 | case M_COP1: | |
5393 | s = "cop1"; | |
5394 | goto copz; | |
5395 | case M_COP2: | |
5396 | s = "cop2"; | |
5397 | goto copz; | |
5398 | case M_COP3: | |
5399 | s = "cop3"; | |
5400 | copz: | |
5401 | /* For now we just do C (same as Cz). */ | |
9218cee0 | 5402 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); |
efec4a28 DP |
5403 | return; |
5404 | ||
917fae09 SS |
5405 | #ifdef LOSING_COMPILER |
5406 | default: | |
efec4a28 DP |
5407 | /* Try and see if this is a new itbl instruction. |
5408 | This code builds table entries out of the macros in mip_opcodes. | |
5409 | FIXME: For now we just assemble the expression and pass it's | |
5410 | value along as a 32-bit immediate. | |
5411 | We may want to have the assembler assemble this value, | |
5412 | so that we gain the assembler's knowledge of delay slots, | |
5413 | symbols, etc. | |
5414 | Would it be more efficient to use mask (id) here? */ | |
5415 | if (itbl_have_entries | |
9218cee0 | 5416 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5417 | { |
5418 | s = ip->insn_mo->name; | |
5419 | s2 = "cop3"; | |
9218cee0 | 5420 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5421 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5422 | return; | |
5423 | } | |
917fae09 SS |
5424 | macro2 (ip); |
5425 | return; | |
5426 | } | |
5427 | if (mips_noat) | |
5428 | as_warn ("Macro used $at after \".set noat\""); | |
5429 | } | |
5430 | ||
5431 | static void | |
5432 | macro2 (ip) | |
5433 | struct mips_cl_insn *ip; | |
5434 | { | |
5435 | register int treg, sreg, dreg, breg; | |
5436 | int tempreg; | |
5437 | int mask; | |
5438 | int icnt = 0; | |
5439 | int used_at; | |
5440 | expressionS expr1; | |
5441 | const char *s; | |
5442 | const char *s2; | |
5443 | const char *fmt; | |
5444 | int likely = 0; | |
5445 | int dbl = 0; | |
5446 | int coproc = 0; | |
adcf2b9d ILT |
5447 | int lr = 0; |
5448 | int off; | |
917fae09 SS |
5449 | offsetT maxnum; |
5450 | bfd_reloc_code_real_type r; | |
5451 | char *p; | |
5452 | ||
5453 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5454 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5455 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5456 | mask = ip->insn_mo->mask; | |
5457 | ||
5458 | expr1.X_op = O_constant; | |
5459 | expr1.X_op_symbol = NULL; | |
5460 | expr1.X_add_symbol = NULL; | |
5461 | expr1.X_add_number = 1; | |
5462 | ||
5463 | switch (mask) | |
5464 | { | |
5465 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5466 | |
8358c818 ILT |
5467 | case M_DMUL: |
5468 | dbl = 1; | |
3d3c5039 | 5469 | case M_MUL: |
0dd2d296 | 5470 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5471 | dbl ? "dmultu" : "multu", |
5472 | "s,t", sreg, treg); | |
0dd2d296 | 5473 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5474 | return; |
3d3c5039 | 5475 | |
8358c818 ILT |
5476 | case M_DMUL_I: |
5477 | dbl = 1; | |
3d3c5039 | 5478 | case M_MUL_I: |
8358c818 ILT |
5479 | /* The MIPS assembler some times generates shifts and adds. I'm |
5480 | not trying to be that fancy. GCC should do this for us | |
5481 | anyway. */ | |
d8a1c247 | 5482 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5483 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5484 | dbl ? "dmult" : "mult", |
5485 | "s,t", sreg, AT); | |
0dd2d296 | 5486 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5487 | break; |
3d3c5039 | 5488 | |
8358c818 ILT |
5489 | case M_DMULO: |
5490 | dbl = 1; | |
5491 | case M_MULO: | |
fbcfacb7 | 5492 | mips_emit_delays (true); |
8358c818 | 5493 | ++mips_noreorder; |
0dd2d296 ILT |
5494 | mips_any_noreorder = 1; |
5495 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5496 | dbl ? "dmult" : "mult", |
5497 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5498 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5499 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5500 | dbl ? "dsra32" : "sra", |
5501 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5502 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5503 | if (mips_trap) |
5504 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5505 | else | |
5506 | { | |
5507 | expr1.X_add_number = 8; | |
5508 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5509 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5510 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5511 | } | |
8358c818 | 5512 | --mips_noreorder; |
0dd2d296 | 5513 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5514 | break; |
5515 | ||
5516 | case M_DMULOU: | |
5517 | dbl = 1; | |
5518 | case M_MULOU: | |
fbcfacb7 | 5519 | mips_emit_delays (true); |
8358c818 | 5520 | ++mips_noreorder; |
0dd2d296 ILT |
5521 | mips_any_noreorder = 1; |
5522 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5523 | dbl ? "dmultu" : "multu", |
5524 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5525 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5526 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5527 | if (mips_trap) |
5528 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5529 | else | |
5530 | { | |
5531 | expr1.X_add_number = 8; | |
5532 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5533 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5534 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5535 | } | |
8358c818 ILT |
5536 | --mips_noreorder; |
5537 | break; | |
5538 | ||
3d3c5039 | 5539 | case M_ROL: |
0dd2d296 ILT |
5540 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5541 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5542 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5543 | treg); | |
5544 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5545 | break; |
3d3c5039 ILT |
5546 | |
5547 | case M_ROL_I: | |
0dd2d296 | 5548 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5549 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5550 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5551 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5552 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5553 | break; |
3d3c5039 ILT |
5554 | |
5555 | case M_ROR: | |
0dd2d296 ILT |
5556 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5557 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5558 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5559 | treg); | |
5560 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5561 | break; |
3d3c5039 ILT |
5562 | |
5563 | case M_ROR_I: | |
0dd2d296 | 5564 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5565 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5566 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5567 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5568 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5569 | break; |
3d3c5039 ILT |
5570 | |
5571 | case M_S_DOB: | |
8358c818 | 5572 | assert (mips_isa < 2); |
9a7d824a ILT |
5573 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5574 | to adjust when storing to memory. */ | |
0dd2d296 | 5575 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5576 | target_big_endian ? treg + 1 : treg, |
9226253a | 5577 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5578 | offset_expr.X_add_number += 4; |
0dd2d296 | 5579 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5580 | target_big_endian ? treg : treg + 1, |
9226253a | 5581 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5582 | return; |
3d3c5039 | 5583 | |
3d3c5039 | 5584 | case M_SEQ: |
670a50eb | 5585 | if (sreg == 0) |
0dd2d296 ILT |
5586 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5587 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5588 | else if (treg == 0) |
0dd2d296 ILT |
5589 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5590 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5591 | else |
5592 | { | |
0dd2d296 ILT |
5593 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5594 | sreg, treg); | |
5595 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5596 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5597 | } |
670a50eb | 5598 | return; |
3d3c5039 ILT |
5599 | |
5600 | case M_SEQ_I: | |
670a50eb ILT |
5601 | if (imm_expr.X_add_number == 0) |
5602 | { | |
0dd2d296 ILT |
5603 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5604 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5605 | return; |
3d3c5039 | 5606 | } |
670a50eb ILT |
5607 | if (sreg == 0) |
5608 | { | |
9a7d824a | 5609 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5610 | ip->insn_mo->name); |
0dd2d296 | 5611 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5612 | return; |
3d3c5039 | 5613 | } |
6e8dda9c | 5614 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5615 | { |
0dd2d296 ILT |
5616 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5617 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5618 | used_at = 0; |
6e8dda9c ILT |
5619 | } |
5620 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5621 | { | |
5622 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5623 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5624 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5625 | "t,r,j", dreg, sreg, |
5626 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5627 | used_at = 0; |
5628 | } | |
5629 | else | |
5630 | { | |
d8a1c247 | 5631 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5632 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5633 | sreg, AT); | |
670a50eb ILT |
5634 | used_at = 1; |
5635 | } | |
0dd2d296 | 5636 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5637 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5638 | if (used_at) |
5639 | break; | |
5640 | return; | |
3d3c5039 ILT |
5641 | |
5642 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5643 | s = "slt"; |
5644 | goto sge; | |
3d3c5039 | 5645 | case M_SGEU: |
670a50eb | 5646 | s = "sltu"; |
3d3c5039 | 5647 | sge: |
0dd2d296 ILT |
5648 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5649 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5650 | (int) BFD_RELOC_LO16); |
670a50eb | 5651 | return; |
3d3c5039 | 5652 | |
670a50eb | 5653 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5654 | case M_SGEU_I: |
6e8dda9c | 5655 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5656 | { |
0dd2d296 | 5657 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5658 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5659 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5660 | used_at = 0; |
5661 | } | |
5662 | else | |
5663 | { | |
d8a1c247 | 5664 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5665 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5666 | mask == M_SGE_I ? "slt" : "sltu", |
5667 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5668 | used_at = 1; |
5669 | } | |
0dd2d296 | 5670 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5671 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5672 | if (used_at) |
5673 | break; | |
5674 | return; | |
3d3c5039 ILT |
5675 | |
5676 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5677 | s = "slt"; |
5678 | goto sgt; | |
3d3c5039 | 5679 | case M_SGTU: |
670a50eb | 5680 | s = "sltu"; |
3d3c5039 | 5681 | sgt: |
0dd2d296 | 5682 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5683 | return; |
3d3c5039 | 5684 | |
670a50eb ILT |
5685 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5686 | s = "slt"; | |
5687 | goto sgti; | |
3d3c5039 | 5688 | case M_SGTU_I: |
670a50eb | 5689 | s = "sltu"; |
3d3c5039 | 5690 | sgti: |
d8a1c247 | 5691 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5692 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5693 | break; |
3d3c5039 | 5694 | |
670a50eb ILT |
5695 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5696 | s = "slt"; | |
5697 | goto sle; | |
3d3c5039 | 5698 | case M_SLEU: |
670a50eb | 5699 | s = "sltu"; |
3d3c5039 | 5700 | sle: |
0dd2d296 ILT |
5701 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5702 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5703 | (int) BFD_RELOC_LO16); |
670a50eb | 5704 | return; |
3d3c5039 | 5705 | |
670a50eb ILT |
5706 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5707 | s = "slt"; | |
5708 | goto slei; | |
3d3c5039 | 5709 | case M_SLEU_I: |
670a50eb | 5710 | s = "sltu"; |
3d3c5039 | 5711 | slei: |
d8a1c247 | 5712 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5713 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5714 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5715 | (int) BFD_RELOC_LO16); |
670a50eb | 5716 | break; |
3d3c5039 ILT |
5717 | |
5718 | case M_SLT_I: | |
6e8dda9c | 5719 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5720 | { |
0dd2d296 ILT |
5721 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5722 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5723 | return; |
3d3c5039 | 5724 | } |
d8a1c247 | 5725 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5726 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5727 | break; |
3d3c5039 ILT |
5728 | |
5729 | case M_SLTU_I: | |
6e8dda9c | 5730 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5731 | { |
0dd2d296 ILT |
5732 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5733 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5734 | return; |
3d3c5039 | 5735 | } |
d8a1c247 | 5736 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5737 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5738 | AT); | |
670a50eb | 5739 | break; |
3d3c5039 ILT |
5740 | |
5741 | case M_SNE: | |
670a50eb | 5742 | if (sreg == 0) |
0dd2d296 ILT |
5743 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5744 | treg); | |
670a50eb | 5745 | else if (treg == 0) |
0dd2d296 ILT |
5746 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5747 | sreg); | |
670a50eb ILT |
5748 | else |
5749 | { | |
0dd2d296 ILT |
5750 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5751 | sreg, treg); | |
5752 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5753 | dreg); | |
3d3c5039 | 5754 | } |
670a50eb | 5755 | return; |
3d3c5039 ILT |
5756 | |
5757 | case M_SNE_I: | |
670a50eb ILT |
5758 | if (imm_expr.X_add_number == 0) |
5759 | { | |
0dd2d296 ILT |
5760 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5761 | sreg); | |
670a50eb | 5762 | return; |
3d3c5039 | 5763 | } |
670a50eb ILT |
5764 | if (sreg == 0) |
5765 | { | |
9a7d824a | 5766 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5767 | ip->insn_mo->name); |
0dd2d296 | 5768 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5769 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5770 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5771 | return; |
3d3c5039 | 5772 | } |
6e8dda9c | 5773 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5774 | { |
0dd2d296 ILT |
5775 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5776 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5777 | used_at = 0; |
6e8dda9c ILT |
5778 | } |
5779 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5780 | { | |
5781 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5782 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5783 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5784 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5785 | used_at = 0; |
5786 | } | |
5787 | else | |
5788 | { | |
d8a1c247 | 5789 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5790 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5791 | sreg, AT); | |
670a50eb ILT |
5792 | used_at = 1; |
5793 | } | |
0dd2d296 | 5794 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5795 | if (used_at) |
5796 | break; | |
5797 | return; | |
3d3c5039 | 5798 | |
8358c818 ILT |
5799 | case M_DSUB_I: |
5800 | dbl = 1; | |
3d3c5039 | 5801 | case M_SUB_I: |
6e8dda9c | 5802 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5803 | { |
5804 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5805 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5806 | dbl ? "daddi" : "addi", |
9226253a | 5807 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5808 | return; |
3d3c5039 | 5809 | } |
d8a1c247 | 5810 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5811 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5812 | dbl ? "dsub" : "sub", |
5813 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5814 | break; |
3d3c5039 | 5815 | |
8358c818 ILT |
5816 | case M_DSUBU_I: |
5817 | dbl = 1; | |
3d3c5039 | 5818 | case M_SUBU_I: |
6e8dda9c | 5819 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5820 | { |
5821 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5822 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5823 | dbl ? "daddiu" : "addiu", |
9226253a | 5824 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5825 | return; |
3d3c5039 | 5826 | } |
d8a1c247 | 5827 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5828 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5829 | dbl ? "dsubu" : "subu", |
5830 | "d,v,t", dreg, sreg, AT); | |
5831 | break; | |
5832 | ||
5833 | case M_TEQ_I: | |
5834 | s = "teq"; | |
5835 | goto trap; | |
5836 | case M_TGE_I: | |
5837 | s = "tge"; | |
5838 | goto trap; | |
5839 | case M_TGEU_I: | |
5840 | s = "tgeu"; | |
5841 | goto trap; | |
5842 | case M_TLT_I: | |
5843 | s = "tlt"; | |
5844 | goto trap; | |
5845 | case M_TLTU_I: | |
5846 | s = "tltu"; | |
5847 | goto trap; | |
5848 | case M_TNE_I: | |
5849 | s = "tne"; | |
5850 | trap: | |
d8a1c247 | 5851 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5852 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5853 | break; |
3d3c5039 ILT |
5854 | |
5855 | case M_TRUNCWD: | |
5856 | case M_TRUNCWS: | |
8358c818 | 5857 | assert (mips_isa < 2); |
670a50eb ILT |
5858 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5859 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5860 | ||
5861 | /* | |
5862 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5863 | * or is there a reason for it? | |
5864 | */ | |
fbcfacb7 | 5865 | mips_emit_delays (true); |
becfe05e | 5866 | ++mips_noreorder; |
0dd2d296 ILT |
5867 | mips_any_noreorder = 1; |
5868 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5869 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5870 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5871 | expr1.X_add_number = 3; |
0dd2d296 | 5872 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5873 | (int) BFD_RELOC_LO16); |
670a50eb | 5874 | expr1.X_add_number = 2; |
0dd2d296 | 5875 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5876 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5877 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5878 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5879 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5880 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5881 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5882 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5883 | --mips_noreorder; |
670a50eb | 5884 | break; |
3d3c5039 ILT |
5885 | |
5886 | case M_ULH: | |
670a50eb ILT |
5887 | s = "lb"; |
5888 | goto ulh; | |
3d3c5039 | 5889 | case M_ULHU: |
670a50eb | 5890 | s = "lbu"; |
3d3c5039 | 5891 | ulh: |
8ea7f4e8 ILT |
5892 | if (offset_expr.X_add_number >= 0x7fff) |
5893 | as_bad ("operand overflow"); | |
670a50eb | 5894 | /* avoid load delay */ |
b9129c6f | 5895 | if (! target_big_endian) |
8ea7f4e8 | 5896 | offset_expr.X_add_number += 1; |
0dd2d296 | 5897 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5898 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5899 | if (! target_big_endian) |
8ea7f4e8 ILT |
5900 | offset_expr.X_add_number -= 1; |
5901 | else | |
5902 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5903 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5904 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5905 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5906 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5907 | break; |
3d3c5039 | 5908 | |
adcf2b9d ILT |
5909 | case M_ULD: |
5910 | s = "ldl"; | |
5911 | s2 = "ldr"; | |
5912 | off = 7; | |
5913 | goto ulw; | |
3d3c5039 | 5914 | case M_ULW: |
adcf2b9d ILT |
5915 | s = "lwl"; |
5916 | s2 = "lwr"; | |
5917 | off = 3; | |
5918 | ulw: | |
5919 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5920 | as_bad ("operand overflow"); |
b9129c6f | 5921 | if (! target_big_endian) |
adcf2b9d ILT |
5922 | offset_expr.X_add_number += off; |
5923 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5924 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5925 | if (! target_big_endian) |
adcf2b9d | 5926 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5927 | else |
adcf2b9d ILT |
5928 | offset_expr.X_add_number += off; |
5929 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5930 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5931 | return; |
3d3c5039 | 5932 | |
adcf2b9d ILT |
5933 | case M_ULD_A: |
5934 | s = "ldl"; | |
5935 | s2 = "ldr"; | |
5936 | off = 7; | |
5937 | goto ulwa; | |
5938 | case M_ULW_A: | |
5939 | s = "lwl"; | |
5940 | s2 = "lwr"; | |
5941 | off = 3; | |
5942 | ulwa: | |
5943 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5944 | if (breg != 0) |
5945 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5946 | mips_isa < 3 ? "addu" : "daddu", | |
5947 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5948 | if (! target_big_endian) |
adcf2b9d ILT |
5949 | expr1.X_add_number = off; |
5950 | else | |
5951 | expr1.X_add_number = 0; | |
5952 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5953 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5954 | if (! target_big_endian) |
adcf2b9d ILT |
5955 | expr1.X_add_number = 0; |
5956 | else | |
5957 | expr1.X_add_number = off; | |
5958 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5959 | (int) BFD_RELOC_LO16, AT); | |
5960 | break; | |
5961 | ||
3d3c5039 ILT |
5962 | case M_ULH_A: |
5963 | case M_ULHU_A: | |
0dd2d296 | 5964 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5965 | if (breg != 0) |
5966 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5967 | mips_isa < 3 ? "addu" : "daddu", | |
5968 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5969 | if (target_big_endian) |
adcf2b9d ILT |
5970 | expr1.X_add_number = 0; |
5971 | macro_build ((char *) NULL, &icnt, &expr1, | |
5972 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5973 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5974 | if (target_big_endian) |
adcf2b9d | 5975 | expr1.X_add_number = 1; |
670a50eb | 5976 | else |
adcf2b9d ILT |
5977 | expr1.X_add_number = 0; |
5978 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5979 | (int) BFD_RELOC_LO16, AT); | |
5980 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5981 | treg, 8); | |
5982 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5983 | treg, AT); | |
670a50eb | 5984 | break; |
3d3c5039 ILT |
5985 | |
5986 | case M_USH: | |
8ea7f4e8 ILT |
5987 | if (offset_expr.X_add_number >= 0x7fff) |
5988 | as_bad ("operand overflow"); | |
b9129c6f | 5989 | if (target_big_endian) |
8ea7f4e8 | 5990 | offset_expr.X_add_number += 1; |
0dd2d296 | 5991 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5992 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5993 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5994 | if (target_big_endian) |
8ea7f4e8 ILT |
5995 | offset_expr.X_add_number -= 1; |
5996 | else | |
5997 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5998 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5999 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6000 | break; |
3d3c5039 | 6001 | |
adcf2b9d ILT |
6002 | case M_USD: |
6003 | s = "sdl"; | |
6004 | s2 = "sdr"; | |
6005 | off = 7; | |
6006 | goto usw; | |
3d3c5039 | 6007 | case M_USW: |
adcf2b9d ILT |
6008 | s = "swl"; |
6009 | s2 = "swr"; | |
6010 | off = 3; | |
6011 | usw: | |
6012 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6013 | as_bad ("operand overflow"); |
b9129c6f | 6014 | if (! target_big_endian) |
adcf2b9d ILT |
6015 | offset_expr.X_add_number += off; |
6016 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6017 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6018 | if (! target_big_endian) |
adcf2b9d | 6019 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6020 | else |
adcf2b9d ILT |
6021 | offset_expr.X_add_number += off; |
6022 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6023 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6024 | return; |
3d3c5039 | 6025 | |
adcf2b9d ILT |
6026 | case M_USD_A: |
6027 | s = "sdl"; | |
6028 | s2 = "sdr"; | |
6029 | off = 7; | |
6030 | goto uswa; | |
3d3c5039 | 6031 | case M_USW_A: |
adcf2b9d ILT |
6032 | s = "swl"; |
6033 | s2 = "swr"; | |
6034 | off = 3; | |
6035 | uswa: | |
0dd2d296 | 6036 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6037 | if (breg != 0) |
6038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6039 | mips_isa < 3 ? "addu" : "daddu", | |
6040 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6041 | if (! target_big_endian) |
adcf2b9d | 6042 | expr1.X_add_number = off; |
670a50eb | 6043 | else |
adcf2b9d ILT |
6044 | expr1.X_add_number = 0; |
6045 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6046 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6047 | if (! target_big_endian) |
adcf2b9d ILT |
6048 | expr1.X_add_number = 0; |
6049 | else | |
6050 | expr1.X_add_number = off; | |
6051 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6052 | (int) BFD_RELOC_LO16, AT); | |
6053 | break; | |
6054 | ||
6055 | case M_USH_A: | |
6056 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6057 | if (breg != 0) |
6058 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6059 | mips_isa < 3 ? "addu" : "daddu", | |
6060 | "d,v,t", AT, AT, breg); | |
b9129c6f | 6061 | if (! target_big_endian) |
adcf2b9d ILT |
6062 | expr1.X_add_number = 0; |
6063 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6064 | (int) BFD_RELOC_LO16, AT); | |
6065 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6066 | treg, 8); | |
b9129c6f | 6067 | if (! target_big_endian) |
adcf2b9d ILT |
6068 | expr1.X_add_number = 1; |
6069 | else | |
6070 | expr1.X_add_number = 0; | |
6071 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6072 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6073 | if (! target_big_endian) |
adcf2b9d ILT |
6074 | expr1.X_add_number = 0; |
6075 | else | |
6076 | expr1.X_add_number = 1; | |
6077 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6078 | (int) BFD_RELOC_LO16, AT); | |
6079 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6080 | treg, 8); | |
6081 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6082 | treg, AT); | |
670a50eb | 6083 | break; |
3d3c5039 ILT |
6084 | |
6085 | default: | |
9218cee0 ILT |
6086 | /* FIXME: Check if this is one of the itbl macros, since they |
6087 | are added dynamically. */ | |
670a50eb | 6088 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6089 | break; |
3d3c5039 | 6090 | } |
670a50eb ILT |
6091 | if (mips_noat) |
6092 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
6093 | } |
6094 | ||
cc5703cd | 6095 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6096 | |
3d3c5039 | 6097 | static void |
cc5703cd | 6098 | mips16_macro (ip) |
3d3c5039 ILT |
6099 | struct mips_cl_insn *ip; |
6100 | { | |
cc5703cd ILT |
6101 | int mask; |
6102 | int xreg, yreg, zreg, tmp; | |
6103 | int icnt; | |
6104 | expressionS expr1; | |
6105 | int dbl; | |
6106 | const char *s, *s2, *s3; | |
3d3c5039 | 6107 | |
cc5703cd | 6108 | mask = ip->insn_mo->mask; |
3d3c5039 | 6109 | |
cc5703cd ILT |
6110 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6111 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6112 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6113 | |
cc5703cd | 6114 | icnt = 0; |
8358c818 | 6115 | |
cc5703cd ILT |
6116 | expr1.X_op = O_constant; |
6117 | expr1.X_op_symbol = NULL; | |
6118 | expr1.X_add_symbol = NULL; | |
6119 | expr1.X_add_number = 1; | |
8358c818 | 6120 | |
cc5703cd | 6121 | dbl = 0; |
517078c1 | 6122 | |
cc5703cd ILT |
6123 | switch (mask) |
6124 | { | |
6125 | default: | |
6126 | internalError (); | |
6127 | ||
6128 | case M_DDIV_3: | |
6129 | dbl = 1; | |
6130 | case M_DIV_3: | |
6131 | s = "mflo"; | |
6132 | goto do_div3; | |
6133 | case M_DREM_3: | |
6134 | dbl = 1; | |
6135 | case M_REM_3: | |
6136 | s = "mfhi"; | |
6137 | do_div3: | |
fbcfacb7 | 6138 | mips_emit_delays (true); |
cc5703cd ILT |
6139 | ++mips_noreorder; |
6140 | mips_any_noreorder = 1; | |
6141 | macro_build ((char *) NULL, &icnt, NULL, | |
6142 | dbl ? "ddiv" : "div", | |
6143 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6144 | expr1.X_add_number = 2; |
cc5703cd | 6145 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6146 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6147 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6148 | since that causes an overflow. We should do that as well, | |
6149 | but I don't see how to do the comparisons without a temporary | |
6150 | register. */ | |
6151 | --mips_noreorder; | |
6152 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6153 | break; | |
6154 | ||
6155 | case M_DIVU_3: | |
6156 | s = "divu"; | |
6157 | s2 = "mflo"; | |
6158 | goto do_divu3; | |
6159 | case M_REMU_3: | |
6160 | s = "divu"; | |
6161 | s2 = "mfhi"; | |
6162 | goto do_divu3; | |
6163 | case M_DDIVU_3: | |
6164 | s = "ddivu"; | |
6165 | s2 = "mflo"; | |
6166 | goto do_divu3; | |
6167 | case M_DREMU_3: | |
6168 | s = "ddivu"; | |
6169 | s2 = "mfhi"; | |
6170 | do_divu3: | |
fbcfacb7 | 6171 | mips_emit_delays (true); |
cc5703cd ILT |
6172 | ++mips_noreorder; |
6173 | mips_any_noreorder = 1; | |
6174 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6175 | expr1.X_add_number = 2; |
cc5703cd | 6176 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6177 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6178 | --mips_noreorder; | |
6179 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6180 | break; | |
6181 | ||
6182 | case M_DSUBU_I: | |
6183 | dbl = 1; | |
6184 | goto do_subu; | |
6185 | case M_SUBU_I: | |
6186 | do_subu: | |
6187 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6188 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6189 | dbl ? "daddiu" : "addiu", | |
6190 | "y,x,4", yreg, xreg); | |
6191 | break; | |
6192 | ||
6193 | case M_SUBU_I_2: | |
6194 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6195 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6196 | "x,k", xreg); | |
6197 | break; | |
6198 | ||
6199 | case M_DSUBU_I_2: | |
6200 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6201 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6202 | "y,j", yreg); | |
6203 | break; | |
6204 | ||
6205 | case M_BEQ: | |
6206 | s = "cmp"; | |
6207 | s2 = "bteqz"; | |
6208 | goto do_branch; | |
6209 | case M_BNE: | |
6210 | s = "cmp"; | |
6211 | s2 = "btnez"; | |
6212 | goto do_branch; | |
6213 | case M_BLT: | |
6214 | s = "slt"; | |
6215 | s2 = "btnez"; | |
6216 | goto do_branch; | |
6217 | case M_BLTU: | |
6218 | s = "sltu"; | |
6219 | s2 = "btnez"; | |
6220 | goto do_branch; | |
6221 | case M_BLE: | |
6222 | s = "slt"; | |
6223 | s2 = "bteqz"; | |
6224 | goto do_reverse_branch; | |
6225 | case M_BLEU: | |
6226 | s = "sltu"; | |
6227 | s2 = "bteqz"; | |
6228 | goto do_reverse_branch; | |
6229 | case M_BGE: | |
6230 | s = "slt"; | |
6231 | s2 = "bteqz"; | |
6232 | goto do_branch; | |
6233 | case M_BGEU: | |
6234 | s = "sltu"; | |
6235 | s2 = "bteqz"; | |
6236 | goto do_branch; | |
6237 | case M_BGT: | |
6238 | s = "slt"; | |
6239 | s2 = "btnez"; | |
6240 | goto do_reverse_branch; | |
6241 | case M_BGTU: | |
6242 | s = "sltu"; | |
6243 | s2 = "btnez"; | |
6244 | ||
6245 | do_reverse_branch: | |
6246 | tmp = xreg; | |
6247 | xreg = yreg; | |
6248 | yreg = tmp; | |
6249 | ||
6250 | do_branch: | |
6251 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6252 | xreg, yreg); | |
6253 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6254 | break; | |
6255 | ||
6256 | case M_BEQ_I: | |
6257 | s = "cmpi"; | |
6258 | s2 = "bteqz"; | |
6259 | s3 = "x,U"; | |
6260 | goto do_branch_i; | |
6261 | case M_BNE_I: | |
6262 | s = "cmpi"; | |
6263 | s2 = "btnez"; | |
6264 | s3 = "x,U"; | |
6265 | goto do_branch_i; | |
6266 | case M_BLT_I: | |
6267 | s = "slti"; | |
6268 | s2 = "btnez"; | |
6269 | s3 = "x,8"; | |
6270 | goto do_branch_i; | |
6271 | case M_BLTU_I: | |
6272 | s = "sltiu"; | |
6273 | s2 = "btnez"; | |
6274 | s3 = "x,8"; | |
6275 | goto do_branch_i; | |
6276 | case M_BLE_I: | |
6277 | s = "slti"; | |
6278 | s2 = "btnez"; | |
6279 | s3 = "x,8"; | |
6280 | goto do_addone_branch_i; | |
6281 | case M_BLEU_I: | |
6282 | s = "sltiu"; | |
6283 | s2 = "btnez"; | |
6284 | s3 = "x,8"; | |
6285 | goto do_addone_branch_i; | |
6286 | case M_BGE_I: | |
6287 | s = "slti"; | |
6288 | s2 = "bteqz"; | |
6289 | s3 = "x,8"; | |
6290 | goto do_branch_i; | |
6291 | case M_BGEU_I: | |
6292 | s = "sltiu"; | |
6293 | s2 = "bteqz"; | |
6294 | s3 = "x,8"; | |
6295 | goto do_branch_i; | |
6296 | case M_BGT_I: | |
6297 | s = "slti"; | |
6298 | s2 = "bteqz"; | |
6299 | s3 = "x,8"; | |
6300 | goto do_addone_branch_i; | |
6301 | case M_BGTU_I: | |
6302 | s = "sltiu"; | |
6303 | s2 = "bteqz"; | |
6304 | s3 = "x,8"; | |
6305 | ||
6306 | do_addone_branch_i: | |
6307 | ++imm_expr.X_add_number; | |
6308 | ||
6309 | do_branch_i: | |
6310 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6311 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6312 | break; | |
18e0764d ILT |
6313 | |
6314 | case M_ABS: | |
6315 | expr1.X_add_number = 0; | |
6316 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6317 | if (xreg != yreg) | |
6318 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6319 | "move", "y,X", xreg, yreg); | |
6320 | expr1.X_add_number = 2; | |
6321 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6322 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6323 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6324 | } |
6325 | } | |
6326 | ||
6327 | /* This routine assembles an instruction into its binary format. As a | |
6328 | side effect, it sets one of the global variables imm_reloc or | |
6329 | offset_reloc to the type of relocation to do if one of the operands | |
6330 | is an address expression. */ | |
6331 | ||
6332 | static void | |
6333 | mips_ip (str, ip) | |
6334 | char *str; | |
6335 | struct mips_cl_insn *ip; | |
6336 | { | |
6337 | char *s; | |
6338 | const char *args; | |
6339 | char c; | |
6340 | struct mips_opcode *insn; | |
6341 | char *argsStart; | |
6342 | unsigned int regno; | |
6343 | unsigned int lastregno = 0; | |
6344 | char *s_reset; | |
6345 | ||
6346 | insn_error = NULL; | |
6347 | ||
e2e5acfa | 6348 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6349 | continue; |
1857d1e6 | 6350 | if (isspace (*s)) |
e2e5acfa | 6351 | *s++ = '\0'; |
1857d1e6 | 6352 | |
cc5703cd ILT |
6353 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6354 | { | |
6355 | insn_error = "unrecognized opcode"; | |
6356 | return; | |
6357 | } | |
6358 | argsStart = s; | |
6359 | for (;;) | |
6360 | { | |
6361 | int insn_isa; | |
6362 | ||
6363 | assert (strcmp (insn->name, str) == 0); | |
6364 | ||
6365 | if (insn->pinfo == INSN_MACRO) | |
6366 | insn_isa = insn->match; | |
6367 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6368 | insn_isa = 2; | |
6369 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6370 | insn_isa = 3; | |
6371 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6372 | insn_isa = 4; | |
6373 | else | |
6374 | insn_isa = 1; | |
6375 | ||
6376 | if (insn_isa > mips_isa | |
16262668 ILT |
6377 | || (insn->pinfo != INSN_MACRO |
6378 | && (((insn->pinfo & INSN_ISA) == INSN_4650 | |
6379 | && ! mips_4650) | |
6380 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6381 | && ! mips_4010) | |
6382 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6383 | && ! mips_4100) | |
6384 | /* start-sanitize-r5900 */ | |
6385 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6386 | && ! mips_5900) | |
6387 | /* end-sanitize-r5900 */ | |
6388 | ))) | |
cc5703cd ILT |
6389 | { |
6390 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6391 | && strcmp (insn->name, insn[1].name) == 0) | |
6392 | { | |
6393 | ++insn; | |
6394 | continue; | |
6395 | } | |
6396 | if (insn_isa <= mips_isa) | |
6397 | insn_error = "opcode not supported on this processor"; | |
6398 | else | |
6399 | { | |
6400 | static char buf[100]; | |
6401 | ||
6402 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6403 | insn_error = buf; | |
6404 | } | |
6405 | return; | |
6406 | } | |
8358c818 | 6407 | |
670a50eb ILT |
6408 | ip->insn_mo = insn; |
6409 | ip->insn_opcode = insn->match; | |
6410 | for (args = insn->args;; ++args) | |
6411 | { | |
6412 | if (*s == ' ') | |
6413 | ++s; | |
6414 | switch (*args) | |
6415 | { | |
6416 | case '\0': /* end of args */ | |
6417 | if (*s == '\0') | |
6418 | return; | |
6419 | break; | |
3d3c5039 ILT |
6420 | |
6421 | case ',': | |
670a50eb ILT |
6422 | if (*s++ == *args) |
6423 | continue; | |
6424 | s--; | |
6425 | switch (*++args) | |
6426 | { | |
3d3c5039 ILT |
6427 | case 'r': |
6428 | case 'v': | |
670a50eb ILT |
6429 | ip->insn_opcode |= lastregno << 21; |
6430 | continue; | |
3d3c5039 ILT |
6431 | |
6432 | case 'w': | |
6433 | case 'W': | |
670a50eb ILT |
6434 | ip->insn_opcode |= lastregno << 16; |
6435 | continue; | |
3d3c5039 ILT |
6436 | |
6437 | case 'V': | |
670a50eb ILT |
6438 | ip->insn_opcode |= lastregno << 11; |
6439 | continue; | |
3d3c5039 | 6440 | } |
670a50eb | 6441 | break; |
3d3c5039 ILT |
6442 | |
6443 | case '(': | |
670a50eb ILT |
6444 | /* handle optional base register. |
6445 | Either the base register is omitted or | |
6446 | we must have a left paren. */ | |
6447 | /* this is dependent on the next operand specifier | |
6448 | is a 'b' for base register */ | |
6449 | assert (args[1] == 'b'); | |
6450 | if (*s == '\0') | |
6451 | return; | |
3d3c5039 | 6452 | |
670a50eb ILT |
6453 | case ')': /* these must match exactly */ |
6454 | if (*s++ == *args) | |
3d3c5039 | 6455 | continue; |
670a50eb ILT |
6456 | break; |
6457 | ||
6458 | case '<': /* must be at least one digit */ | |
6459 | /* | |
6460 | * According to the manual, if the shift amount is greater | |
6461 | * than 31 or less than 0 the the shift amount should be | |
6462 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6463 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6464 | */ |
6465 | my_getExpression (&imm_expr, s); | |
6466 | check_absolute_expr (ip, &imm_expr); | |
6467 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6468 | { | |
58d4951d ILT |
6469 | as_warn ("Improper shift amount (%ld)", |
6470 | (long) imm_expr.X_add_number); | |
9226253a | 6471 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6472 | } |
6473 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6474 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6475 | s = expr_end; |
6476 | continue; | |
6477 | ||
56c96faa ILT |
6478 | case '>': /* shift amount minus 32 */ |
6479 | my_getExpression (&imm_expr, s); | |
6480 | check_absolute_expr (ip, &imm_expr); | |
6481 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6482 | || (unsigned long) imm_expr.X_add_number > 63) | |
6483 | break; | |
6484 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6485 | imm_expr.X_op = O_absent; | |
6486 | s = expr_end; | |
6487 | continue; | |
6488 | ||
9226253a | 6489 | case 'k': /* cache code */ |
d8a1c247 | 6490 | case 'h': /* prefx code */ |
9226253a ILT |
6491 | my_getExpression (&imm_expr, s); |
6492 | check_absolute_expr (ip, &imm_expr); | |
6493 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6494 | { | |
d8a1c247 KR |
6495 | as_warn ("Invalid value for `%s' (%lu)", |
6496 | ip->insn_mo->name, | |
9226253a ILT |
6497 | (unsigned long) imm_expr.X_add_number); |
6498 | imm_expr.X_add_number &= 0x1f; | |
6499 | } | |
d8a1c247 KR |
6500 | if (*args == 'k') |
6501 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6502 | else | |
6503 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6504 | imm_expr.X_op = O_absent; |
6505 | s = expr_end; | |
6506 | continue; | |
6507 | ||
670a50eb ILT |
6508 | case 'c': /* break code */ |
6509 | my_getExpression (&imm_expr, s); | |
6510 | check_absolute_expr (ip, &imm_expr); | |
6511 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6512 | as_warn ("Illegal break code (%ld)", |
6513 | (long) imm_expr.X_add_number); | |
670a50eb | 6514 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6515 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6516 | s = expr_end; |
6517 | continue; | |
6518 | ||
918692a5 ILT |
6519 | case 'B': /* syscall code */ |
6520 | my_getExpression (&imm_expr, s); | |
6521 | check_absolute_expr (ip, &imm_expr); | |
6522 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6523 | as_warn ("Illegal syscall code (%ld)", |
6524 | (long) imm_expr.X_add_number); | |
918692a5 | 6525 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6526 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6527 | s = expr_end; |
6528 | continue; | |
6529 | ||
0aa07269 ILT |
6530 | case 'C': /* Coprocessor code */ |
6531 | my_getExpression (&imm_expr, s); | |
6532 | check_absolute_expr (ip, &imm_expr); | |
6533 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6534 | { | |
58d4951d ILT |
6535 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6536 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6537 | imm_expr.X_add_number &= ((1<<25) - 1); |
6538 | } | |
6539 | ip->insn_opcode |= imm_expr.X_add_number; | |
6540 | imm_expr.X_op = O_absent; | |
6541 | s = expr_end; | |
6542 | continue; | |
6543 | ||
670a50eb ILT |
6544 | case 'b': /* base register */ |
6545 | case 'd': /* destination register */ | |
6546 | case 's': /* source register */ | |
6547 | case 't': /* target register */ | |
6548 | case 'r': /* both target and source */ | |
6549 | case 'v': /* both dest and source */ | |
6550 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6551 | case 'E': /* coprocessor target register */ |
6552 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6553 | case 'x': /* ignore register name */ |
ff3a5c18 | 6554 | case 'z': /* must be zero register */ |
670a50eb ILT |
6555 | s_reset = s; |
6556 | if (s[0] == '$') | |
6557 | { | |
6558 | if (isdigit (s[1])) | |
6559 | { | |
6560 | ++s; | |
6561 | regno = 0; | |
6562 | do | |
6563 | { | |
6564 | regno *= 10; | |
6565 | regno += *s - '0'; | |
6566 | ++s; | |
6567 | } | |
6568 | while (isdigit (*s)); | |
0aa07269 ILT |
6569 | if (regno > 31) |
6570 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6571 | } |
0dd2d296 ILT |
6572 | else if (*args == 'E' || *args == 'G') |
6573 | goto notreg; | |
6574 | else | |
670a50eb | 6575 | { |
0aa07269 ILT |
6576 | if (s[1] == 'f' && s[2] == 'p') |
6577 | { | |
6578 | s += 3; | |
9226253a | 6579 | regno = FP; |
0aa07269 ILT |
6580 | } |
6581 | else if (s[1] == 's' && s[2] == 'p') | |
6582 | { | |
6583 | s += 3; | |
9226253a | 6584 | regno = SP; |
0aa07269 ILT |
6585 | } |
6586 | else if (s[1] == 'g' && s[2] == 'p') | |
6587 | { | |
6588 | s += 3; | |
9226253a | 6589 | regno = GP; |
0aa07269 ILT |
6590 | } |
6591 | else if (s[1] == 'a' && s[2] == 't') | |
6592 | { | |
6593 | s += 3; | |
9226253a | 6594 | regno = AT; |
0aa07269 | 6595 | } |
b2b8c24e ILT |
6596 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6597 | { | |
6598 | s += 4; | |
6599 | regno = KT0; | |
6600 | } | |
6601 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6602 | { | |
6603 | s += 4; | |
6604 | regno = KT1; | |
6605 | } | |
efec4a28 DP |
6606 | else if (itbl_have_entries) |
6607 | { | |
6608 | char *p, *n; | |
6609 | int r; | |
6610 | ||
6611 | p = s+1; /* advance past '$' */ | |
9218cee0 | 6612 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
6613 | |
6614 | /* See if this is a register defined in an | |
6615 | itbl entry */ | |
9218cee0 ILT |
6616 | r = itbl_get_reg_val (n); |
6617 | if (r) | |
efec4a28 | 6618 | { |
9218cee0 ILT |
6619 | /* Get_field advances to the start of |
6620 | the next field, so we need to back | |
6621 | rack to the end of the last field. */ | |
efec4a28 | 6622 | if (p) |
9218cee0 | 6623 | s = p - 1; |
efec4a28 | 6624 | else |
9218cee0 | 6625 | s = strchr (s,'\0'); |
efec4a28 DP |
6626 | regno = r; |
6627 | } | |
6628 | else | |
6629 | goto notreg; | |
6630 | } | |
0aa07269 ILT |
6631 | else |
6632 | goto notreg; | |
670a50eb | 6633 | } |
9753202d ILT |
6634 | if (regno == AT |
6635 | && ! mips_noat | |
6636 | && *args != 'E' | |
6637 | && *args != 'G') | |
13fe1379 | 6638 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6639 | c = *args; |
6640 | if (*s == ' ') | |
6641 | s++; | |
6642 | if (args[1] != *s) | |
6643 | { | |
6644 | if (c == 'r' || c == 'v' || c == 'w') | |
6645 | { | |
6646 | regno = lastregno; | |
6647 | s = s_reset; | |
6648 | args++; | |
6649 | } | |
6650 | } | |
ff3a5c18 ILT |
6651 | /* 'z' only matches $0. */ |
6652 | if (c == 'z' && regno != 0) | |
6653 | break; | |
efec4a28 DP |
6654 | |
6655 | /* Now that we have assembled one operand, we use the args string | |
6656 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
6657 | switch (c) |
6658 | { | |
3d3c5039 ILT |
6659 | case 'r': |
6660 | case 's': | |
6661 | case 'v': | |
6662 | case 'b': | |
670a50eb ILT |
6663 | ip->insn_opcode |= regno << 21; |
6664 | break; | |
3d3c5039 | 6665 | case 'd': |
918692a5 | 6666 | case 'G': |
670a50eb ILT |
6667 | ip->insn_opcode |= regno << 11; |
6668 | break; | |
3d3c5039 ILT |
6669 | case 'w': |
6670 | case 't': | |
918692a5 | 6671 | case 'E': |
670a50eb | 6672 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6673 | break; |
6674 | case 'x': | |
6675 | /* This case exists because on the r3000 trunc | |
6676 | expands into a macro which requires a gp | |
6677 | register. On the r6000 or r4000 it is | |
6678 | assembled into a single instruction which | |
6679 | ignores the register. Thus the insn version | |
6680 | is MIPS_ISA2 and uses 'x', and the macro | |
6681 | version is MIPS_ISA1 and uses 't'. */ | |
6682 | break; | |
ff3a5c18 ILT |
6683 | case 'z': |
6684 | /* This case is for the div instruction, which | |
6685 | acts differently if the destination argument | |
6686 | is $0. This only matches $0, and is checked | |
6687 | outside the switch. */ | |
6688 | break; | |
efec4a28 DP |
6689 | case 'D': |
6690 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
6691 | break; | |
9218cee0 ILT |
6692 | /* What about all other operands like 'i', which |
6693 | can be specified in the opcode table? */ | |
3d3c5039 | 6694 | } |
670a50eb ILT |
6695 | lastregno = regno; |
6696 | continue; | |
3d3c5039 ILT |
6697 | } |
6698 | notreg: | |
670a50eb ILT |
6699 | switch (*args++) |
6700 | { | |
3d3c5039 ILT |
6701 | case 'r': |
6702 | case 'v': | |
670a50eb ILT |
6703 | ip->insn_opcode |= lastregno << 21; |
6704 | continue; | |
3d3c5039 | 6705 | case 'w': |
670a50eb ILT |
6706 | ip->insn_opcode |= lastregno << 16; |
6707 | continue; | |
3d3c5039 | 6708 | } |
670a50eb | 6709 | break; |
3d3c5039 | 6710 | |
670a50eb ILT |
6711 | case 'D': /* floating point destination register */ |
6712 | case 'S': /* floating point source register */ | |
6713 | case 'T': /* floating point target register */ | |
d8a1c247 | 6714 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6715 | case 'V': |
6716 | case 'W': | |
670a50eb ILT |
6717 | s_reset = s; |
6718 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6719 | { | |
6720 | s += 2; | |
6721 | regno = 0; | |
6722 | do | |
6723 | { | |
6724 | regno *= 10; | |
6725 | regno += *s - '0'; | |
6726 | ++s; | |
6727 | } | |
6728 | while (isdigit (*s)); | |
6729 | ||
6730 | if (regno > 31) | |
6731 | as_bad ("Invalid float register number (%d)", regno); | |
6732 | ||
9226253a ILT |
6733 | if ((regno & 1) != 0 |
6734 | && mips_isa < 3 | |
538034cf ILT |
6735 | && ! (strcmp (str, "mtc1") == 0 |
6736 | || strcmp (str, "mfc1") == 0 | |
6737 | || strcmp (str, "lwc1") == 0 | |
6738 | || strcmp (str, "swc1") == 0 | |
6739 | || strcmp (str, "l.s") == 0 | |
6740 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6741 | as_warn ("Float register should be even, was %d", |
6742 | regno); | |
6743 | ||
6744 | c = *args; | |
6745 | if (*s == ' ') | |
6746 | s++; | |
6747 | if (args[1] != *s) | |
6748 | { | |
6749 | if (c == 'V' || c == 'W') | |
6750 | { | |
6751 | regno = lastregno; | |
6752 | s = s_reset; | |
6753 | args++; | |
3d3c5039 ILT |
6754 | } |
6755 | } | |
670a50eb ILT |
6756 | switch (c) |
6757 | { | |
3d3c5039 | 6758 | case 'D': |
670a50eb ILT |
6759 | ip->insn_opcode |= regno << 6; |
6760 | break; | |
3d3c5039 ILT |
6761 | case 'V': |
6762 | case 'S': | |
670a50eb ILT |
6763 | ip->insn_opcode |= regno << 11; |
6764 | break; | |
3d3c5039 ILT |
6765 | case 'W': |
6766 | case 'T': | |
670a50eb | 6767 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6768 | break; |
6769 | case 'R': | |
6770 | ip->insn_opcode |= regno << 21; | |
6771 | break; | |
3d3c5039 | 6772 | } |
670a50eb ILT |
6773 | lastregno = regno; |
6774 | continue; | |
3d3c5039 | 6775 | } |
670a50eb ILT |
6776 | switch (*args++) |
6777 | { | |
3d3c5039 | 6778 | case 'V': |
670a50eb ILT |
6779 | ip->insn_opcode |= lastregno << 11; |
6780 | continue; | |
3d3c5039 | 6781 | case 'W': |
670a50eb ILT |
6782 | ip->insn_opcode |= lastregno << 16; |
6783 | continue; | |
3d3c5039 | 6784 | } |
670a50eb | 6785 | break; |
3d3c5039 ILT |
6786 | |
6787 | case 'I': | |
670a50eb | 6788 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6789 | if (imm_expr.X_op != O_big |
6790 | && imm_expr.X_op != O_constant) | |
6791 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6792 | s = expr_end; |
6793 | continue; | |
3d3c5039 ILT |
6794 | |
6795 | case 'A': | |
670a50eb ILT |
6796 | my_getExpression (&offset_expr, s); |
6797 | imm_reloc = BFD_RELOC_32; | |
6798 | s = expr_end; | |
6799 | continue; | |
3d3c5039 ILT |
6800 | |
6801 | case 'F': | |
19ed8960 ILT |
6802 | case 'L': |
6803 | case 'f': | |
6804 | case 'l': | |
6805 | { | |
6806 | int f64; | |
6807 | char *save_in; | |
6808 | char *err; | |
6809 | unsigned char temp[8]; | |
604633ae ILT |
6810 | int len; |
6811 | unsigned int length; | |
19ed8960 ILT |
6812 | segT seg; |
6813 | subsegT subseg; | |
6814 | char *p; | |
6815 | ||
6816 | /* These only appear as the last operand in an | |
6817 | instruction, and every instruction that accepts | |
6818 | them in any variant accepts them in all variants. | |
6819 | This means we don't have to worry about backing out | |
6820 | any changes if the instruction does not match. | |
6821 | ||
6822 | The difference between them is the size of the | |
6823 | floating point constant and where it goes. For 'F' | |
6824 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6825 | is 32 bits. Where the constant is placed is based | |
6826 | on how the MIPS assembler does things: | |
6827 | F -- .rdata | |
6828 | L -- .lit8 | |
6829 | f -- immediate value | |
6830 | l -- .lit4 | |
0dd2d296 | 6831 | |
55933a58 ILT |
6832 | The .lit4 and .lit8 sections are only used if |
6833 | permitted by the -G argument. | |
6834 | ||
6835 | When generating embedded PIC code, we use the | |
6836 | .lit8 section but not the .lit4 section (we can do | |
6837 | .lit4 inline easily; we need to put .lit8 | |
6838 | somewhere in the data segment, and using .lit8 | |
6839 | permits the linker to eventually combine identical | |
6840 | .lit8 entries). */ | |
19ed8960 ILT |
6841 | |
6842 | f64 = *args == 'F' || *args == 'L'; | |
6843 | ||
6844 | save_in = input_line_pointer; | |
6845 | input_line_pointer = s; | |
604633ae ILT |
6846 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6847 | length = len; | |
19ed8960 ILT |
6848 | s = input_line_pointer; |
6849 | input_line_pointer = save_in; | |
6850 | if (err != NULL && *err != '\0') | |
6851 | { | |
6852 | as_bad ("Bad floating point constant: %s", err); | |
6853 | memset (temp, '\0', sizeof temp); | |
6854 | length = f64 ? 8 : 4; | |
6855 | } | |
6856 | ||
6857 | assert (length == (f64 ? 8 : 4)); | |
6858 | ||
0dd2d296 | 6859 | if (*args == 'f' |
55933a58 | 6860 | || (*args == 'l' |
1dc1e798 KR |
6861 | && (! USE_GLOBAL_POINTER_OPT |
6862 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6863 | || g_switch_value < 4) |
1113140a | 6864 | )) |
19ed8960 ILT |
6865 | { |
6866 | imm_expr.X_op = O_constant; | |
b9129c6f | 6867 | if (! target_big_endian) |
19ed8960 ILT |
6868 | imm_expr.X_add_number = |
6869 | (((((((int) temp[3] << 8) | |
6870 | | temp[2]) << 8) | |
6871 | | temp[1]) << 8) | |
6872 | | temp[0]); | |
6873 | else | |
6874 | imm_expr.X_add_number = | |
6875 | (((((((int) temp[0] << 8) | |
6876 | | temp[1]) << 8) | |
6877 | | temp[2]) << 8) | |
6878 | | temp[3]); | |
6879 | } | |
6880 | else | |
6881 | { | |
0dd2d296 ILT |
6882 | const char *newname; |
6883 | segT new_seg; | |
6884 | ||
19ed8960 ILT |
6885 | /* Switch to the right section. */ |
6886 | seg = now_seg; | |
6887 | subseg = now_subseg; | |
6888 | switch (*args) | |
6889 | { | |
0dd2d296 | 6890 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6891 | case 'L': |
1113140a | 6892 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6893 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6894 | newname = ".lit8"; |
0dd2d296 ILT |
6895 | break; |
6896 | case 'F': | |
d2c71068 | 6897 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6898 | break; |
6899 | case 'l': | |
1dc1e798 KR |
6900 | assert (!USE_GLOBAL_POINTER_OPT |
6901 | || g_switch_value >= 4); | |
0dd2d296 | 6902 | newname = ".lit4"; |
19ed8960 ILT |
6903 | break; |
6904 | } | |
0dd2d296 | 6905 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6906 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6907 | bfd_set_section_flags (stdoutput, new_seg, | |
6908 | (SEC_ALLOC | |
6909 | | SEC_LOAD | |
6910 | | SEC_READONLY | |
6911 | | SEC_DATA)); | |
e2e5acfa JW |
6912 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
6913 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
6914 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
6915 | record_alignment (new_seg, 4); |
6916 | else | |
6917 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6918 | if (seg == now_seg) |
6919 | as_bad ("Can't use floating point insn in this section"); | |
6920 | ||
6921 | /* Set the argument to the current address in the | |
6e8dda9c | 6922 | section. */ |
19ed8960 ILT |
6923 | offset_expr.X_op = O_symbol; |
6924 | offset_expr.X_add_symbol = | |
6925 | symbol_new ("L0\001", now_seg, | |
6926 | (valueT) frag_now_fix (), frag_now); | |
6927 | offset_expr.X_add_number = 0; | |
6928 | ||
6929 | /* Put the floating point number into the section. */ | |
604633ae | 6930 | p = frag_more ((int) length); |
19ed8960 ILT |
6931 | memcpy (p, temp, length); |
6932 | ||
6933 | /* Switch back to the original section. */ | |
6934 | subseg_set (seg, subseg); | |
6935 | } | |
6936 | } | |
670a50eb ILT |
6937 | continue; |
6938 | ||
6939 | case 'i': /* 16 bit unsigned immediate */ | |
6940 | case 'j': /* 16 bit signed immediate */ | |
6941 | imm_reloc = BFD_RELOC_LO16; | |
6942 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6943 | if (c != '\0') |
670a50eb ILT |
6944 | { |
6945 | if (c != 'l') | |
6946 | { | |
5ac34ac3 | 6947 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6948 | imm_expr.X_add_number = |
6949 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6950 | else if (c == 'h') | |
867a58b3 ILT |
6951 | { |
6952 | imm_reloc = BFD_RELOC_HI16_S; | |
6953 | imm_unmatched_hi = true; | |
6954 | } | |
670a50eb ILT |
6955 | else |
6956 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6957 | } |
670a50eb | 6958 | } |
670a50eb ILT |
6959 | if (*args == 'i') |
6960 | { | |
344a8d61 | 6961 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6962 | || ((imm_expr.X_add_number < 0 |
6963 | || imm_expr.X_add_number >= 0x10000) | |
6964 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6965 | { |
6966 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6967 | !strcmp (insn->name, insn[1].name)) | |
6968 | break; | |
9753202d ILT |
6969 | if (imm_expr.X_op != O_constant |
6970 | && imm_expr.X_op != O_big) | |
6971 | insn_error = "absolute expression required"; | |
6972 | else | |
6973 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6974 | } |
670a50eb ILT |
6975 | } |
6976 | else | |
6977 | { | |
d9aba805 ILT |
6978 | int more; |
6979 | offsetT max; | |
6980 | ||
be22008b ILT |
6981 | /* The upper bound should be 0x8000, but |
6982 | unfortunately the MIPS assembler accepts numbers | |
6983 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6984 | we want to be compatible. We only permit this |
6985 | extended range for an instruction which does not | |
6986 | provide any further alternates, since those | |
6987 | alternates may handle other cases. People should | |
6988 | use the numbers they mean, rather than relying on | |
6989 | a mysterious sign extension. */ | |
6990 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6991 | strcmp (insn->name, insn[1].name) == 0); | |
6992 | if (more) | |
6993 | max = 0x8000; | |
6994 | else | |
6995 | max = 0x10000; | |
344a8d61 | 6996 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6997 | || ((imm_expr.X_add_number < -0x8000 |
6998 | || imm_expr.X_add_number >= max) | |
6999 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7000 | || (more |
7001 | && imm_expr.X_add_number < 0 | |
7002 | && mips_isa >= 3 | |
7003 | && imm_expr.X_unsigned | |
7004 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7005 | { |
d9aba805 | 7006 | if (more) |
99c24539 | 7007 | break; |
9753202d ILT |
7008 | if (imm_expr.X_op != O_constant |
7009 | && imm_expr.X_op != O_big) | |
7010 | insn_error = "absolute expression required"; | |
7011 | else | |
7012 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7013 | } |
3d3c5039 | 7014 | } |
670a50eb ILT |
7015 | s = expr_end; |
7016 | continue; | |
7017 | ||
7018 | case 'o': /* 16 bit offset */ | |
7019 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7020 | |
7021 | /* If this value won't fit into a 16 bit offset, then go | |
7022 | find a macro that will generate the 32 bit offset | |
7023 | code pattern. As a special hack, we accept the | |
7024 | difference of two local symbols as a constant. This | |
7025 | is required to suppose embedded PIC switches, which | |
7026 | use an instruction which looks like | |
7027 | lw $4,$L12-$LS12($4) | |
7028 | The problem with handling this in a more general | |
7029 | fashion is that the macro function doesn't expect to | |
7030 | see anything which can be handled in a single | |
7031 | constant instruction. */ | |
6f0b87c3 SS |
7032 | if (c == 0 |
7033 | && (offset_expr.X_op != O_constant | |
7034 | || offset_expr.X_add_number >= 0x8000 | |
7035 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7036 | && (mips_pic != EMBEDDED_PIC |
7037 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7038 | || now_seg != text_section |
7039 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7040 | != text_section))) | |
670a50eb | 7041 | break; |
3d3c5039 | 7042 | |
670a50eb ILT |
7043 | offset_reloc = BFD_RELOC_LO16; |
7044 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7045 | { |
7046 | assert (offset_expr.X_op == O_constant); | |
7047 | offset_expr.X_add_number = | |
7048 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7049 | } | |
cc5703cd ILT |
7050 | s = expr_end; |
7051 | continue; | |
7052 | ||
7053 | case 'p': /* pc relative offset */ | |
7054 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7055 | my_getExpression (&offset_expr, s); | |
7056 | s = expr_end; | |
7057 | continue; | |
7058 | ||
7059 | case 'u': /* upper 16 bits */ | |
7060 | c = my_getSmallExpression (&imm_expr, s); | |
7061 | if (imm_expr.X_op == O_constant | |
7062 | && (imm_expr.X_add_number < 0 | |
7063 | || imm_expr.X_add_number >= 0x10000)) | |
7064 | as_bad ("lui expression not in range 0..65535"); | |
7065 | imm_reloc = BFD_RELOC_LO16; | |
7066 | if (c) | |
7067 | { | |
7068 | if (c != 'l') | |
7069 | { | |
7070 | if (imm_expr.X_op == O_constant) | |
7071 | imm_expr.X_add_number = | |
7072 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7073 | else if (c == 'h') | |
7074 | { | |
7075 | imm_reloc = BFD_RELOC_HI16_S; | |
7076 | imm_unmatched_hi = true; | |
7077 | } | |
7078 | else | |
7079 | imm_reloc = BFD_RELOC_HI16; | |
7080 | } | |
7081 | } | |
7082 | s = expr_end; | |
7083 | continue; | |
7084 | ||
7085 | case 'a': /* 26 bit address */ | |
7086 | my_getExpression (&offset_expr, s); | |
7087 | s = expr_end; | |
7088 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7089 | continue; | |
7090 | ||
7091 | case 'N': /* 3 bit branch condition code */ | |
7092 | case 'M': /* 3 bit compare condition code */ | |
7093 | if (strncmp (s, "$fcc", 4) != 0) | |
7094 | break; | |
7095 | s += 4; | |
7096 | regno = 0; | |
7097 | do | |
7098 | { | |
7099 | regno *= 10; | |
7100 | regno += *s - '0'; | |
7101 | ++s; | |
7102 | } | |
7103 | while (isdigit (*s)); | |
7104 | if (regno > 7) | |
7105 | as_bad ("invalid condition code register $fcc%d", regno); | |
7106 | if (*args == 'N') | |
7107 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7108 | else | |
7109 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7110 | continue; | |
7111 | ||
7112 | default: | |
7113 | fprintf (stderr, "bad char = '%c'\n", *args); | |
7114 | internalError (); | |
7115 | } | |
7116 | break; | |
7117 | } | |
7118 | /* Args don't match. */ | |
7119 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7120 | !strcmp (insn->name, insn[1].name)) | |
7121 | { | |
7122 | ++insn; | |
7123 | s = argsStart; | |
7124 | continue; | |
7125 | } | |
7126 | insn_error = "illegal operands"; | |
7127 | return; | |
7128 | } | |
7129 | } | |
7130 | ||
7131 | /* This routine assembles an instruction into its binary format when | |
7132 | assembling for the mips16. As a side effect, it sets one of the | |
7133 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7134 | relocation to do if one of the operands is an address expression. |
7135 | It also sets mips16_small and mips16_ext if the user explicitly | |
7136 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7137 | |
7138 | static void | |
7139 | mips16_ip (str, ip) | |
7140 | char *str; | |
7141 | struct mips_cl_insn *ip; | |
7142 | { | |
7143 | char *s; | |
cc5703cd ILT |
7144 | const char *args; |
7145 | struct mips_opcode *insn; | |
7146 | char *argsstart; | |
7147 | unsigned int regno; | |
7148 | unsigned int lastregno = 0; | |
7149 | char *s_reset; | |
7150 | ||
7151 | insn_error = NULL; | |
7152 | ||
8728fa92 ILT |
7153 | mips16_small = false; |
7154 | mips16_ext = false; | |
cc5703cd ILT |
7155 | |
7156 | for (s = str; islower (*s); ++s) | |
7157 | ; | |
7158 | switch (*s) | |
7159 | { | |
7160 | case '\0': | |
7161 | break; | |
7162 | ||
7163 | case ' ': | |
7164 | *s++ = '\0'; | |
7165 | break; | |
7166 | ||
7167 | case '.': | |
7168 | if (s[1] == 't' && s[2] == ' ') | |
7169 | { | |
7170 | *s = '\0'; | |
8728fa92 | 7171 | mips16_small = true; |
cc5703cd ILT |
7172 | s += 3; |
7173 | break; | |
7174 | } | |
7175 | else if (s[1] == 'e' && s[2] == ' ') | |
7176 | { | |
7177 | *s = '\0'; | |
8728fa92 | 7178 | mips16_ext = true; |
cc5703cd ILT |
7179 | s += 3; |
7180 | break; | |
7181 | } | |
7182 | /* Fall through. */ | |
7183 | default: | |
7184 | insn_error = "unknown opcode"; | |
7185 | return; | |
7186 | } | |
7187 | ||
8728fa92 ILT |
7188 | if (! mips16_autoextend && ! mips16_ext) |
7189 | mips16_small = true; | |
7190 | ||
cc5703cd ILT |
7191 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7192 | { | |
7193 | insn_error = "unrecognized opcode"; | |
7194 | return; | |
7195 | } | |
7196 | ||
7197 | argsstart = s; | |
7198 | for (;;) | |
7199 | { | |
7200 | assert (strcmp (insn->name, str) == 0); | |
7201 | ||
7202 | ip->insn_mo = insn; | |
7203 | ip->insn_opcode = insn->match; | |
7204 | ip->use_extend = false; | |
7205 | imm_expr.X_op = O_absent; | |
7206 | imm_reloc = BFD_RELOC_UNUSED; | |
7207 | offset_expr.X_op = O_absent; | |
7208 | offset_reloc = BFD_RELOC_UNUSED; | |
7209 | for (args = insn->args; 1; ++args) | |
7210 | { | |
7211 | int c; | |
7212 | ||
7213 | if (*s == ' ') | |
7214 | ++s; | |
7215 | ||
7216 | /* In this switch statement we call break if we did not find | |
7217 | a match, continue if we did find a match, or return if we | |
7218 | are done. */ | |
7219 | ||
7220 | c = *args; | |
7221 | switch (c) | |
7222 | { | |
7223 | case '\0': | |
7224 | if (*s == '\0') | |
7225 | { | |
7226 | /* Stuff the immediate value in now, if we can. */ | |
7227 | if (imm_expr.X_op == O_constant | |
7228 | && imm_reloc > BFD_RELOC_UNUSED | |
7229 | && insn->pinfo != INSN_MACRO) | |
7230 | { | |
15e69f98 ILT |
7231 | mips16_immed ((char *) NULL, 0, |
7232 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7233 | imm_expr.X_add_number, true, mips16_small, |
7234 | mips16_ext, &ip->insn_opcode, | |
7235 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7236 | imm_expr.X_op = O_absent; |
7237 | imm_reloc = BFD_RELOC_UNUSED; | |
7238 | } | |
7239 | ||
7240 | return; | |
7241 | } | |
7242 | break; | |
7243 | ||
7244 | case ',': | |
7245 | if (*s++ == c) | |
7246 | continue; | |
7247 | s--; | |
7248 | switch (*++args) | |
7249 | { | |
7250 | case 'v': | |
7251 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7252 | continue; | |
7253 | case 'w': | |
7254 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7255 | continue; | |
7256 | } | |
7257 | break; | |
7258 | ||
7259 | case '(': | |
7260 | case ')': | |
7261 | if (*s++ == c) | |
7262 | continue; | |
7263 | break; | |
7264 | ||
7265 | case 'v': | |
7266 | case 'w': | |
7267 | if (s[0] != '$') | |
7268 | { | |
7269 | if (c == 'v') | |
7270 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7271 | else | |
7272 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7273 | ++args; | |
7274 | continue; | |
7275 | } | |
7276 | /* Fall through. */ | |
7277 | case 'x': | |
7278 | case 'y': | |
7279 | case 'z': | |
7280 | case 'Z': | |
7281 | case '0': | |
7282 | case 'S': | |
7283 | case 'R': | |
7284 | case 'X': | |
7285 | case 'Y': | |
7286 | if (s[0] != '$') | |
7287 | break; | |
7288 | s_reset = s; | |
7289 | if (isdigit (s[1])) | |
7290 | { | |
7291 | ++s; | |
7292 | regno = 0; | |
7293 | do | |
7294 | { | |
7295 | regno *= 10; | |
7296 | regno += *s - '0'; | |
7297 | ++s; | |
7298 | } | |
7299 | while (isdigit (*s)); | |
7300 | if (regno > 31) | |
7301 | { | |
7302 | as_bad ("invalid register number (%d)", regno); | |
7303 | regno = 2; | |
7304 | } | |
7305 | } | |
7306 | else | |
7307 | { | |
7308 | if (s[1] == 'f' && s[2] == 'p') | |
7309 | { | |
7310 | s += 3; | |
7311 | regno = FP; | |
7312 | } | |
7313 | else if (s[1] == 's' && s[2] == 'p') | |
7314 | { | |
7315 | s += 3; | |
7316 | regno = SP; | |
7317 | } | |
7318 | else if (s[1] == 'g' && s[2] == 'p') | |
7319 | { | |
7320 | s += 3; | |
7321 | regno = GP; | |
7322 | } | |
7323 | else if (s[1] == 'a' && s[2] == 't') | |
7324 | { | |
7325 | s += 3; | |
7326 | regno = AT; | |
7327 | } | |
7328 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7329 | { | |
7330 | s += 4; | |
7331 | regno = KT0; | |
7332 | } | |
7333 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7334 | { | |
7335 | s += 4; | |
7336 | regno = KT1; | |
7337 | } | |
7338 | else | |
7339 | break; | |
7340 | } | |
7341 | ||
7342 | if (*s == ' ') | |
7343 | ++s; | |
7344 | if (args[1] != *s) | |
7345 | { | |
7346 | if (c == 'v' || c == 'w') | |
7347 | { | |
7348 | regno = mips16_to_32_reg_map[lastregno]; | |
7349 | s = s_reset; | |
7350 | args++; | |
7351 | } | |
7352 | } | |
7353 | ||
7354 | switch (c) | |
7355 | { | |
7356 | case 'x': | |
7357 | case 'y': | |
7358 | case 'z': | |
7359 | case 'v': | |
7360 | case 'w': | |
7361 | case 'Z': | |
7362 | regno = mips32_to_16_reg_map[regno]; | |
7363 | break; | |
7364 | ||
7365 | case '0': | |
7366 | if (regno != 0) | |
7367 | regno = ILLEGAL_REG; | |
7368 | break; | |
7369 | ||
7370 | case 'S': | |
7371 | if (regno != SP) | |
7372 | regno = ILLEGAL_REG; | |
7373 | break; | |
7374 | ||
7375 | case 'R': | |
7376 | if (regno != RA) | |
7377 | regno = ILLEGAL_REG; | |
7378 | break; | |
7379 | ||
7380 | case 'X': | |
7381 | case 'Y': | |
7382 | if (regno == AT && ! mips_noat) | |
7383 | as_warn ("used $at without \".set noat\""); | |
7384 | break; | |
7385 | ||
7386 | default: | |
7387 | internalError (); | |
7388 | } | |
7389 | ||
7390 | if (regno == ILLEGAL_REG) | |
7391 | break; | |
7392 | ||
7393 | switch (c) | |
7394 | { | |
7395 | case 'x': | |
7396 | case 'v': | |
7397 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7398 | break; | |
7399 | case 'y': | |
7400 | case 'w': | |
7401 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7402 | break; | |
7403 | case 'z': | |
7404 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7405 | break; | |
7406 | case 'Z': | |
7407 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7408 | case '0': | |
7409 | case 'S': | |
7410 | case 'R': | |
7411 | break; | |
7412 | case 'X': | |
7413 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7414 | break; | |
7415 | case 'Y': | |
7416 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7417 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7418 | break; | |
7419 | default: | |
7420 | internalError (); | |
7421 | } | |
7422 | ||
7423 | lastregno = regno; | |
7424 | continue; | |
7425 | ||
7426 | case 'P': | |
7427 | if (strncmp (s, "$pc", 3) == 0) | |
7428 | { | |
7429 | s += 3; | |
7430 | continue; | |
7431 | } | |
7432 | break; | |
7433 | ||
7434 | case '<': | |
7435 | case '>': | |
7436 | case '[': | |
7437 | case ']': | |
7438 | case '4': | |
7439 | case '5': | |
7440 | case 'H': | |
7441 | case 'W': | |
7442 | case 'D': | |
7443 | case 'j': | |
7444 | case '8': | |
7445 | case 'V': | |
7446 | case 'C': | |
7447 | case 'U': | |
7448 | case 'k': | |
7449 | case 'K': | |
16262668 ILT |
7450 | if (s[0] == '%' |
7451 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7452 | { | |
7453 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7454 | and generate the appropriate reloc. If the text | |
7455 | inside %gprel is not a symbol name with an | |
7456 | optional offset, then we generate a normal reloc | |
7457 | and will probably fail later. */ | |
7458 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7459 | if (imm_expr.X_op == O_symbol) | |
7460 | { | |
7461 | mips16_ext = true; | |
7462 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7463 | s = expr_end; | |
7464 | ip->use_extend = true; | |
7465 | ip->extend = 0; | |
7466 | continue; | |
7467 | } | |
7468 | } | |
7469 | else | |
7470 | { | |
7471 | /* Just pick up a normal expression. */ | |
7472 | my_getExpression (&imm_expr, s); | |
7473 | } | |
7474 | ||
ebf28372 ILT |
7475 | if (imm_expr.X_op == O_register) |
7476 | { | |
7477 | /* What we thought was an expression turned out to | |
7478 | be a register. */ | |
7479 | ||
7480 | if (s[0] == '(' && args[1] == '(') | |
7481 | { | |
7482 | /* It looks like the expression was omitted | |
7483 | before a register indirection, which means | |
7484 | that the expression is implicitly zero. We | |
7485 | still set up imm_expr, so that we handle | |
7486 | explicit extensions correctly. */ | |
7487 | imm_expr.X_op = O_constant; | |
7488 | imm_expr.X_add_number = 0; | |
7489 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7490 | continue; | |
7491 | } | |
7492 | ||
7493 | break; | |
7494 | } | |
7495 | ||
cc5703cd ILT |
7496 | /* We need to relax this instruction. */ |
7497 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7498 | s = expr_end; | |
7499 | continue; | |
7500 | ||
7501 | case 'p': | |
7502 | case 'q': | |
7503 | case 'A': | |
7504 | case 'B': | |
7505 | case 'E': | |
7506 | /* We use offset_reloc rather than imm_reloc for the PC | |
7507 | relative operands. This lets macros with both | |
7508 | immediate and address operands work correctly. */ | |
670a50eb | 7509 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7510 | |
7511 | if (offset_expr.X_op == O_register) | |
7512 | break; | |
7513 | ||
cc5703cd ILT |
7514 | /* We need to relax this instruction. */ |
7515 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7516 | s = expr_end; |
7517 | continue; | |
7518 | ||
cc5703cd ILT |
7519 | case '6': /* break code */ |
7520 | my_getExpression (&imm_expr, s); | |
7521 | check_absolute_expr (ip, &imm_expr); | |
7522 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7523 | { |
cc5703cd ILT |
7524 | as_warn ("Invalid value for `%s' (%lu)", |
7525 | ip->insn_mo->name, | |
7526 | (unsigned long) imm_expr.X_add_number); | |
7527 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7528 | } |
cc5703cd ILT |
7529 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7530 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7531 | s = expr_end; |
7532 | continue; | |
3d3c5039 | 7533 | |
670a50eb ILT |
7534 | case 'a': /* 26 bit address */ |
7535 | my_getExpression (&offset_expr, s); | |
7536 | s = expr_end; | |
cc5703cd ILT |
7537 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7538 | ip->insn_opcode <<= 16; | |
670a50eb | 7539 | continue; |
3d3c5039 | 7540 | |
cc5703cd ILT |
7541 | case 'l': /* register list for entry macro */ |
7542 | case 'L': /* register list for exit macro */ | |
7543 | { | |
7544 | int mask; | |
7545 | ||
7546 | if (c == 'l') | |
7547 | mask = 0; | |
7548 | else | |
7549 | mask = 7 << 3; | |
7550 | while (*s != '\0') | |
7551 | { | |
c9167640 | 7552 | int freg, reg1, reg2; |
cc5703cd ILT |
7553 | |
7554 | while (*s == ' ' || *s == ',') | |
7555 | ++s; | |
7556 | if (*s != '$') | |
7557 | { | |
7558 | as_bad ("can't parse register list"); | |
7559 | break; | |
7560 | } | |
7561 | ++s; | |
c9167640 ILT |
7562 | if (*s != 'f') |
7563 | freg = 0; | |
7564 | else | |
7565 | { | |
7566 | freg = 1; | |
7567 | ++s; | |
7568 | } | |
cc5703cd ILT |
7569 | reg1 = 0; |
7570 | while (isdigit (*s)) | |
7571 | { | |
7572 | reg1 *= 10; | |
7573 | reg1 += *s - '0'; | |
7574 | ++s; | |
7575 | } | |
7576 | if (*s == ' ') | |
7577 | ++s; | |
7578 | if (*s != '-') | |
7579 | reg2 = reg1; | |
7580 | else | |
7581 | { | |
7582 | ++s; | |
7583 | if (*s != '$') | |
7584 | break; | |
7585 | ++s; | |
c9167640 ILT |
7586 | if (freg) |
7587 | { | |
7588 | if (*s == 'f') | |
7589 | ++s; | |
7590 | else | |
7591 | { | |
7592 | as_bad ("invalid register list"); | |
7593 | break; | |
7594 | } | |
7595 | } | |
cc5703cd ILT |
7596 | reg2 = 0; |
7597 | while (isdigit (*s)) | |
7598 | { | |
7599 | reg2 *= 10; | |
7600 | reg2 += *s - '0'; | |
7601 | ++s; | |
7602 | } | |
7603 | } | |
c9167640 ILT |
7604 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7605 | { | |
7606 | mask &= ~ (7 << 3); | |
7607 | mask |= 5 << 3; | |
7608 | } | |
7609 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7610 | { | |
7611 | mask &= ~ (7 << 3); | |
7612 | mask |= 6 << 3; | |
7613 | } | |
7614 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7615 | mask |= (reg2 - 3) << 3; |
7616 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7617 | mask |= (reg2 - 15) << 1; | |
7618 | else if (reg1 == 31 && reg2 == 31) | |
7619 | mask |= 1; | |
7620 | else | |
c9167640 ILT |
7621 | { |
7622 | as_bad ("invalid register list"); | |
7623 | break; | |
7624 | } | |
cc5703cd | 7625 | } |
c9167640 ILT |
7626 | /* The mask is filled in in the opcode table for the |
7627 | benefit of the disassembler. We remove it before | |
7628 | applying the actual mask. */ | |
7629 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7630 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7631 | } | |
7632 | continue; | |
d8a1c247 | 7633 | |
56bb6eee ILT |
7634 | case 'e': /* extend code */ |
7635 | my_getExpression (&imm_expr, s); | |
7636 | check_absolute_expr (ip, &imm_expr); | |
7637 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
7638 | { | |
7639 | as_warn ("Invalid value for `%s' (%lu)", | |
7640 | ip->insn_mo->name, | |
7641 | (unsigned long) imm_expr.X_add_number); | |
7642 | imm_expr.X_add_number &= 0x7ff; | |
7643 | } | |
7644 | ip->insn_opcode |= imm_expr.X_add_number; | |
7645 | imm_expr.X_op = O_absent; | |
7646 | s = expr_end; | |
7647 | continue; | |
7648 | ||
3d3c5039 | 7649 | default: |
670a50eb | 7650 | internalError (); |
3d3c5039 | 7651 | } |
670a50eb | 7652 | break; |
3d3c5039 | 7653 | } |
cc5703cd | 7654 | |
670a50eb | 7655 | /* Args don't match. */ |
cc5703cd ILT |
7656 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7657 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7658 | { |
7659 | ++insn; | |
cc5703cd | 7660 | s = argsstart; |
670a50eb | 7661 | continue; |
3d3c5039 | 7662 | } |
cc5703cd | 7663 | |
9753202d | 7664 | insn_error = "illegal operands"; |
cc5703cd | 7665 | |
670a50eb | 7666 | return; |
3d3c5039 ILT |
7667 | } |
7668 | } | |
7669 | ||
cc5703cd ILT |
7670 | /* This structure holds information we know about a mips16 immediate |
7671 | argument type. */ | |
7672 | ||
7673 | struct mips16_immed_operand | |
7674 | { | |
7675 | /* The type code used in the argument string in the opcode table. */ | |
7676 | int type; | |
7677 | /* The number of bits in the short form of the opcode. */ | |
7678 | int nbits; | |
7679 | /* The number of bits in the extended form of the opcode. */ | |
7680 | int extbits; | |
7681 | /* The amount by which the short form is shifted when it is used; | |
7682 | for example, the sw instruction has a shift count of 2. */ | |
7683 | int shift; | |
7684 | /* The amount by which the short form is shifted when it is stored | |
7685 | into the instruction code. */ | |
7686 | int op_shift; | |
7687 | /* Non-zero if the short form is unsigned. */ | |
7688 | int unsp; | |
7689 | /* Non-zero if the extended form is unsigned. */ | |
7690 | int extu; | |
7691 | /* Non-zero if the value is PC relative. */ | |
7692 | int pcrel; | |
7693 | }; | |
7694 | ||
7695 | /* The mips16 immediate operand types. */ | |
7696 | ||
7697 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7698 | { | |
7699 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7700 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7701 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7702 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7703 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7704 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7705 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7706 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7707 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7708 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7709 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7710 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7711 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7712 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7713 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7714 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7715 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7716 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7717 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7718 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7719 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7720 | }; | |
7721 | ||
7722 | #define MIPS16_NUM_IMMED \ | |
7723 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7724 | ||
7725 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7726 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7727 | whether an extended value is needed; if one is needed, it sets | |
7728 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7729 | If SMALL is true, an unextended opcode was explicitly requested. | |
7730 | If EXT is true, an extended opcode was explicitly requested. If | |
7731 | WARN is true, warn if EXT does not match reality. */ | |
7732 | ||
7733 | static void | |
15e69f98 ILT |
7734 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7735 | extend) | |
7736 | char *file; | |
7737 | unsigned int line; | |
cc5703cd ILT |
7738 | int type; |
7739 | offsetT val; | |
7740 | boolean warn; | |
7741 | boolean small; | |
7742 | boolean ext; | |
7743 | unsigned long *insn; | |
7744 | boolean *use_extend; | |
7745 | unsigned short *extend; | |
7746 | { | |
7747 | register const struct mips16_immed_operand *op; | |
7748 | int mintiny, maxtiny; | |
7749 | boolean needext; | |
7750 | ||
7751 | op = mips16_immed_operands; | |
7752 | while (op->type != type) | |
7753 | { | |
7754 | ++op; | |
7755 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7756 | } | |
7757 | ||
7758 | if (op->unsp) | |
7759 | { | |
7760 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7761 | { | |
7762 | mintiny = 1; | |
7763 | maxtiny = 1 << op->nbits; | |
7764 | } | |
7765 | else | |
7766 | { | |
7767 | mintiny = 0; | |
7768 | maxtiny = (1 << op->nbits) - 1; | |
7769 | } | |
7770 | } | |
7771 | else | |
7772 | { | |
7773 | mintiny = - (1 << (op->nbits - 1)); | |
7774 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7775 | } | |
7776 | ||
7777 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7778 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7779 | val /= 2; |
cc5703cd ILT |
7780 | |
7781 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7782 | || val < (mintiny << op->shift) | |
7783 | || val > (maxtiny << op->shift)) | |
7784 | needext = true; | |
7785 | else | |
7786 | needext = false; | |
7787 | ||
7788 | if (warn && ext && ! needext) | |
15e69f98 | 7789 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7790 | if (small && needext) |
15e69f98 | 7791 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7792 | |
7793 | if (small || (! ext && ! needext)) | |
7794 | { | |
7795 | int insnval; | |
7796 | ||
7797 | *use_extend = false; | |
7798 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7799 | insnval <<= op->op_shift; | |
7800 | *insn |= insnval; | |
7801 | } | |
7802 | else | |
7803 | { | |
7804 | long minext, maxext; | |
7805 | int extval; | |
7806 | ||
7807 | if (op->extu) | |
7808 | { | |
7809 | minext = 0; | |
7810 | maxext = (1 << op->extbits) - 1; | |
7811 | } | |
7812 | else | |
7813 | { | |
7814 | minext = - (1 << (op->extbits - 1)); | |
7815 | maxext = (1 << (op->extbits - 1)) - 1; | |
7816 | } | |
7817 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7818 | as_bad_where (file, line, |
7819 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7820 | |
7821 | *use_extend = true; | |
7822 | if (op->extbits == 16) | |
7823 | { | |
7824 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7825 | val &= 0x1f; | |
7826 | } | |
7827 | else if (op->extbits == 15) | |
7828 | { | |
7829 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7830 | val &= 0xf; | |
7831 | } | |
7832 | else | |
7833 | { | |
7834 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7835 | val = 0; | |
7836 | } | |
7837 | ||
7838 | *extend = (unsigned short) extval; | |
7839 | *insn |= val; | |
7840 | } | |
7841 | } | |
7842 | \f | |
3d3c5039 ILT |
7843 | #define LP '(' |
7844 | #define RP ')' | |
7845 | ||
7846 | static int | |
7847 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7848 | expressionS *ep; |
7849 | char *str; | |
3d3c5039 | 7850 | { |
670a50eb ILT |
7851 | char *sp; |
7852 | int c = 0; | |
7853 | ||
7854 | if (*str == ' ') | |
7855 | str++; | |
7856 | if (*str == LP | |
7857 | || (*str == '%' && | |
7858 | ((str[1] == 'h' && str[2] == 'i') | |
7859 | || (str[1] == 'H' && str[2] == 'I') | |
7860 | || (str[1] == 'l' && str[2] == 'o')) | |
7861 | && str[3] == LP)) | |
7862 | { | |
7863 | if (*str == LP) | |
7864 | c = 0; | |
7865 | else | |
7866 | { | |
7867 | c = str[1]; | |
7868 | str += 3; | |
7869 | } | |
7870 | ||
7871 | /* | |
7872 | * A small expression may be followed by a base register. | |
7873 | * Scan to the end of this operand, and then back over a possible | |
7874 | * base register. Then scan the small expression up to that | |
7875 | * point. (Based on code in sparc.c...) | |
7876 | */ | |
7877 | for (sp = str; *sp && *sp != ','; sp++) | |
7878 | ; | |
7879 | if (sp - 4 >= str && sp[-1] == RP) | |
7880 | { | |
7881 | if (isdigit (sp[-2])) | |
7882 | { | |
7883 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7884 | ; | |
7885 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7886 | { | |
7887 | sp--; | |
7888 | goto do_it; | |
3d3c5039 | 7889 | } |
670a50eb ILT |
7890 | } |
7891 | else if (sp - 5 >= str | |
7892 | && sp[-5] == LP | |
7893 | && sp[-4] == '$' | |
7894 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7895 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7896 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7897 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7898 | { | |
7899 | sp -= 5; | |
3d3c5039 | 7900 | do_it: |
670a50eb ILT |
7901 | if (sp == str) |
7902 | { | |
7903 | /* no expression means zero offset */ | |
7904 | if (c) | |
7905 | { | |
7906 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7907 | ep->X_op = O_absent; |
670a50eb | 7908 | expr_end = str - 3; |
3d3c5039 | 7909 | } |
670a50eb ILT |
7910 | else |
7911 | { | |
52aa70b5 | 7912 | ep->X_op = O_constant; |
670a50eb ILT |
7913 | expr_end = sp; |
7914 | } | |
7915 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7916 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7917 | ep->X_add_number = 0; |
7918 | } | |
7919 | else | |
7920 | { | |
7921 | *sp = '\0'; | |
7922 | my_getExpression (ep, str); | |
7923 | *sp = LP; | |
3d3c5039 | 7924 | } |
670a50eb | 7925 | return c; |
3d3c5039 ILT |
7926 | } |
7927 | } | |
7928 | } | |
670a50eb ILT |
7929 | my_getExpression (ep, str); |
7930 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7931 | } |
7932 | ||
7933 | static void | |
7934 | my_getExpression (ep, str) | |
670a50eb ILT |
7935 | expressionS *ep; |
7936 | char *str; | |
3d3c5039 | 7937 | { |
670a50eb | 7938 | char *save_in; |
670a50eb ILT |
7939 | |
7940 | save_in = input_line_pointer; | |
7941 | input_line_pointer = str; | |
5ac34ac3 | 7942 | expression (ep); |
670a50eb ILT |
7943 | expr_end = input_line_pointer; |
7944 | input_line_pointer = save_in; | |
eb17f56c ILT |
7945 | |
7946 | /* If we are in mips16 mode, and this is an expression based on `.', | |
7947 | then we bump the value of the symbol by 1 since that is how other | |
7948 | text symbols are handled. We don't bother to handle complex | |
7949 | expressions, just `.' plus or minus a constant. */ | |
7950 | if (mips16 | |
7951 | && ep->X_op == O_symbol | |
7952 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
7953 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
7954 | && ep->X_add_symbol->sy_frag == frag_now | |
7955 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
7956 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
7957 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
7958 | } |
7959 | ||
becfe05e ILT |
7960 | /* Turn a string in input_line_pointer into a floating point constant |
7961 | of type type, and store the appropriate bytes in *litP. The number | |
7962 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7963 | returned, or NULL on OK. */ | |
7964 | ||
3d3c5039 | 7965 | char * |
670a50eb | 7966 | md_atof (type, litP, sizeP) |
becfe05e | 7967 | int type; |
3d3c5039 ILT |
7968 | char *litP; |
7969 | int *sizeP; | |
7970 | { | |
becfe05e ILT |
7971 | int prec; |
7972 | LITTLENUM_TYPE words[4]; | |
7973 | char *t; | |
7974 | int i; | |
7975 | ||
7976 | switch (type) | |
7977 | { | |
7978 | case 'f': | |
7979 | prec = 2; | |
7980 | break; | |
7981 | ||
7982 | case 'd': | |
7983 | prec = 4; | |
7984 | break; | |
7985 | ||
7986 | default: | |
7987 | *sizeP = 0; | |
7988 | return "bad call to md_atof"; | |
7989 | } | |
7990 | ||
7991 | t = atof_ieee (input_line_pointer, type, words); | |
7992 | if (t) | |
7993 | input_line_pointer = t; | |
7994 | ||
7995 | *sizeP = prec * 2; | |
7996 | ||
b9129c6f | 7997 | if (! target_big_endian) |
becfe05e ILT |
7998 | { |
7999 | for (i = prec - 1; i >= 0; i--) | |
8000 | { | |
8001 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8002 | litP += 2; | |
8003 | } | |
8004 | } | |
8005 | else | |
8006 | { | |
8007 | for (i = 0; i < prec; i++) | |
8008 | { | |
8009 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8010 | litP += 2; | |
8011 | } | |
8012 | } | |
8013 | ||
670a50eb | 8014 | return NULL; |
3d3c5039 ILT |
8015 | } |
8016 | ||
8017 | void | |
8018 | md_number_to_chars (buf, val, n) | |
8019 | char *buf; | |
918692a5 | 8020 | valueT val; |
3d3c5039 ILT |
8021 | int n; |
8022 | { | |
b9129c6f ILT |
8023 | if (target_big_endian) |
8024 | number_to_chars_bigendian (buf, val, n); | |
8025 | else | |
8026 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8027 | } |
f3d817d8 | 8028 | \f |
e8d4d475 | 8029 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8030 | |
f3d817d8 DM |
8031 | struct option md_longopts[] = { |
8032 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8033 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8034 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8035 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8036 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8037 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8038 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8039 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8040 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8041 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8042 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8043 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8044 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8045 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8046 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8047 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8048 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8049 | {"break", no_argument, NULL, OPTION_BREAK}, |
8050 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8051 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8052 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8053 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8054 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8055 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8056 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8057 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8058 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8059 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8060 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8061 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8062 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8063 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8064 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8065 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8066 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8067 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8068 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8069 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8070 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
276c2d7d GRK |
8071 | /* start-sanitize-5900 */ |
8072 | #define OPTION_M5900 (OPTION_MD_BASE + 24) | |
8073 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8074 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8075 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
8076 | /* end-sanitize-5900 */ | |
f3d817d8 | 8077 | |
d8a1c247 | 8078 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8079 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8080 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8081 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8082 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8083 | #ifdef OBJ_ELF |
f3d817d8 | 8084 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8085 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8086 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8087 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8088 | {"32", no_argument, NULL, OPTION_32}, |
8089 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8090 | #endif |
8091 | ||
8092 | {NULL, no_argument, NULL, 0} | |
8093 | }; | |
8094 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8095 | |
8096 | int | |
f3d817d8 DM |
8097 | md_parse_option (c, arg) |
8098 | int c; | |
8099 | char *arg; | |
3d3c5039 | 8100 | { |
f3d817d8 | 8101 | switch (c) |
670a50eb | 8102 | { |
f3d817d8 DM |
8103 | case OPTION_TRAP: |
8104 | mips_trap = 1; | |
8105 | break; | |
670a50eb | 8106 | |
f3d817d8 DM |
8107 | case OPTION_BREAK: |
8108 | mips_trap = 0; | |
8109 | break; | |
8110 | ||
e8d4d475 | 8111 | case OPTION_EB: |
1dc1e798 | 8112 | target_big_endian = 1; |
e8d4d475 | 8113 | break; |
04cb3372 | 8114 | |
e8d4d475 | 8115 | case OPTION_EL: |
1dc1e798 | 8116 | target_big_endian = 0; |
f3d817d8 | 8117 | break; |
670a50eb | 8118 | |
f3d817d8 DM |
8119 | case 'O': |
8120 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8121 | mips_optimize = 1; |
8122 | else | |
8123 | mips_optimize = 2; | |
f3d817d8 | 8124 | break; |
0aa07269 | 8125 | |
f3d817d8 | 8126 | case 'g': |
22ba90ce ILT |
8127 | if (arg == NULL) |
8128 | mips_debug = 2; | |
8129 | else | |
8130 | mips_debug = atoi (arg); | |
8131 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8132 | optimizations which limit full symbolic debugging. We take | |
8133 | that to be equivalent to -O0. */ | |
8134 | if (mips_debug == 2) | |
05874c2e | 8135 | mips_optimize = 1; |
f3d817d8 | 8136 | break; |
4e95866e | 8137 | |
f3d817d8 DM |
8138 | case OPTION_MIPS1: |
8139 | mips_isa = 1; | |
4bb0cc41 ILT |
8140 | if (mips_cpu == -1) |
8141 | mips_cpu = 3000; | |
f3d817d8 | 8142 | break; |
8358c818 | 8143 | |
f3d817d8 DM |
8144 | case OPTION_MIPS2: |
8145 | mips_isa = 2; | |
4bb0cc41 ILT |
8146 | if (mips_cpu == -1) |
8147 | mips_cpu = 6000; | |
f3d817d8 | 8148 | break; |
8358c818 | 8149 | |
f3d817d8 DM |
8150 | case OPTION_MIPS3: |
8151 | mips_isa = 3; | |
4bb0cc41 ILT |
8152 | if (mips_cpu == -1) |
8153 | mips_cpu = 4000; | |
f3d817d8 | 8154 | break; |
8358c818 | 8155 | |
d8a1c247 KR |
8156 | case OPTION_MIPS4: |
8157 | mips_isa = 4; | |
8158 | if (mips_cpu == -1) | |
8159 | mips_cpu = 8000; | |
8160 | break; | |
8161 | ||
f3d817d8 DM |
8162 | case OPTION_MCPU: |
8163 | { | |
8164 | char *p; | |
8165 | ||
8166 | /* Identify the processor type */ | |
8167 | p = arg; | |
8168 | if (strcmp (p, "default") == 0 | |
8169 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8170 | mips_cpu = -1; |
f3d817d8 DM |
8171 | else |
8172 | { | |
c625fc23 JSC |
8173 | int sv = 0; |
8174 | ||
8175 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8176 | processor. */ | |
8177 | if (*p == 'v' || *p == 'V') | |
8178 | { | |
8179 | sv = 1; | |
8180 | p++; | |
8181 | } | |
8182 | ||
f3d817d8 DM |
8183 | if (*p == 'r' || *p == 'R') |
8184 | p++; | |
8358c818 | 8185 | |
4bb0cc41 | 8186 | mips_cpu = -1; |
f3d817d8 DM |
8187 | switch (*p) |
8188 | { | |
d8a1c247 KR |
8189 | case '1': |
8190 | if (strcmp (p, "10000") == 0 | |
8191 | || strcmp (p, "10k") == 0 | |
8192 | || strcmp (p, "10K") == 0) | |
8193 | mips_cpu = 10000; | |
8194 | break; | |
8195 | ||
f3d817d8 DM |
8196 | case '2': |
8197 | if (strcmp (p, "2000") == 0 | |
8198 | || strcmp (p, "2k") == 0 | |
8199 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8200 | mips_cpu = 2000; |
f3d817d8 | 8201 | break; |
8358c818 | 8202 | |
f3d817d8 DM |
8203 | case '3': |
8204 | if (strcmp (p, "3000") == 0 | |
8205 | || strcmp (p, "3k") == 0 | |
8206 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8207 | mips_cpu = 3000; |
f3d817d8 | 8208 | break; |
8358c818 | 8209 | |
f3d817d8 DM |
8210 | case '4': |
8211 | if (strcmp (p, "4000") == 0 | |
8212 | || strcmp (p, "4k") == 0 | |
8c63448a | 8213 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8214 | mips_cpu = 4000; |
c625fc23 JSC |
8215 | else if (strcmp (p, "4100") == 0) |
8216 | { | |
8217 | mips_cpu = 4100; | |
8218 | if (mips_4100 < 0) | |
8219 | mips_4100 = 1; | |
8220 | } | |
8221 | else if (strcmp (p, "4300") == 0) | |
8222 | mips_cpu = 4300; | |
8c63448a | 8223 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8224 | mips_cpu = 4400; |
8c63448a | 8225 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8226 | mips_cpu = 4600; |
b2b8c24e ILT |
8227 | else if (strcmp (p, "4650") == 0) |
8228 | { | |
8229 | mips_cpu = 4650; | |
8230 | if (mips_4650 < 0) | |
8231 | mips_4650 = 1; | |
8232 | } | |
e532b44c ILT |
8233 | else if (strcmp (p, "4010") == 0) |
8234 | { | |
8235 | mips_cpu = 4010; | |
8236 | if (mips_4010 < 0) | |
8237 | mips_4010 = 1; | |
8238 | } | |
f3d817d8 | 8239 | break; |
8358c818 | 8240 | |
517078c1 ILT |
8241 | case '5': |
8242 | if (strcmp (p, "5000") == 0 | |
8243 | || strcmp (p, "5k") == 0 | |
8244 | || strcmp (p, "5K") == 0) | |
8245 | mips_cpu = 5000; | |
276c2d7d GRK |
8246 | /* start-sanitize-r5900 */ |
8247 | else if (strcmp (p, "5900") == 0) | |
8248 | mips_cpu = 5900; | |
8249 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8250 | break; |
8251 | ||
f3d817d8 DM |
8252 | case '6': |
8253 | if (strcmp (p, "6000") == 0 | |
8254 | || strcmp (p, "6k") == 0 | |
8255 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8256 | mips_cpu = 6000; |
f3d817d8 | 8257 | break; |
55933a58 | 8258 | |
d8a1c247 KR |
8259 | case '8': |
8260 | if (strcmp (p, "8000") == 0 | |
8261 | || strcmp (p, "8k") == 0 | |
8262 | || strcmp (p, "8K") == 0) | |
8263 | mips_cpu = 8000; | |
8264 | break; | |
8265 | ||
55933a58 ILT |
8266 | case 'o': |
8267 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8268 | mips_cpu = 4600; |
55933a58 | 8269 | break; |
f3d817d8 | 8270 | } |
8358c818 | 8271 | |
517078c1 | 8272 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8273 | { |
8274 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8275 | return 0; | |
8276 | } | |
8277 | ||
4bb0cc41 | 8278 | if (mips_cpu == -1) |
f3d817d8 DM |
8279 | { |
8280 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8281 | return 0; | |
8282 | } | |
8283 | } | |
8284 | } | |
8285 | break; | |
8358c818 | 8286 | |
b2b8c24e ILT |
8287 | case OPTION_M4650: |
8288 | mips_4650 = 1; | |
8289 | break; | |
8290 | ||
8291 | case OPTION_NO_M4650: | |
8292 | mips_4650 = 0; | |
8293 | break; | |
8294 | ||
e532b44c ILT |
8295 | case OPTION_M4010: |
8296 | mips_4010 = 1; | |
8297 | break; | |
8298 | ||
8299 | case OPTION_NO_M4010: | |
8300 | mips_4010 = 0; | |
8301 | break; | |
8302 | ||
c625fc23 JSC |
8303 | case OPTION_M4100: |
8304 | mips_4100 = 1; | |
8305 | break; | |
8306 | ||
8307 | case OPTION_NO_M4100: | |
8308 | mips_4100 = 0; | |
8309 | break; | |
8310 | ||
276c2d7d GRK |
8311 | /* start-sanitize-r5900 */ |
8312 | case OPTION_M5900: | |
8313 | mips_5900 = 1; | |
8314 | break; | |
8315 | ||
8316 | case OPTION_NO_M5900: | |
8317 | mips_5900 = 0; | |
8318 | break; | |
8319 | /* end-sanitize-r5900 */ | |
8320 | ||
cc5703cd ILT |
8321 | case OPTION_MIPS16: |
8322 | mips16 = 1; | |
4a1cb507 | 8323 | mips_no_prev_insn (false); |
cc5703cd ILT |
8324 | break; |
8325 | ||
8326 | case OPTION_NO_MIPS16: | |
8327 | mips16 = 0; | |
4a1cb507 | 8328 | mips_no_prev_insn (false); |
cc5703cd ILT |
8329 | break; |
8330 | ||
f3d817d8 | 8331 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8332 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8333 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8334 | { |
8335 | as_bad ("-G may not be used with embedded PIC code"); | |
8336 | return 0; | |
8337 | } | |
5b63f465 | 8338 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8339 | break; |
d9aba805 | 8340 | |
fb251650 ILT |
8341 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8342 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8343 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8344 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8345 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8346 | { | |
8347 | as_bad ("-call_shared is supported only for ELF format"); | |
8348 | return 0; | |
8349 | } | |
d9aba805 ILT |
8350 | mips_pic = SVR4_PIC; |
8351 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8352 | { |
8353 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8354 | return 0; | |
8355 | } | |
d9aba805 | 8356 | g_switch_value = 0; |
f3d817d8 DM |
8357 | break; |
8358 | ||
8359 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8360 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8361 | { | |
8362 | as_bad ("-non_shared is supported only for ELF format"); | |
8363 | return 0; | |
8364 | } | |
d9aba805 | 8365 | mips_pic = NO_PIC; |
f3d817d8 | 8366 | break; |
8358c818 | 8367 | |
fb251650 ILT |
8368 | /* The -xgot option tells the assembler to use 32 offsets when |
8369 | accessing the got in SVR4_PIC mode. It is for Irix | |
8370 | compatibility. */ | |
8371 | case OPTION_XGOT: | |
8372 | mips_big_got = 1; | |
8373 | break; | |
8374 | ||
f3d817d8 | 8375 | case 'G': |
1dc1e798 KR |
8376 | if (! USE_GLOBAL_POINTER_OPT) |
8377 | { | |
8378 | as_bad ("-G is not supported for this configuration"); | |
8379 | return 0; | |
8380 | } | |
8381 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8382 | { |
f3d817d8 DM |
8383 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8384 | return 0; | |
670a50eb ILT |
8385 | } |
8386 | else | |
f3d817d8 | 8387 | g_switch_value = atoi (arg); |
42562568 | 8388 | g_switch_seen = 1; |
f3d817d8 | 8389 | break; |
4e95866e | 8390 | |
7f9880e5 ILT |
8391 | /* The -32 and -64 options tell the assembler to output the 32 |
8392 | bit or the 64 bit MIPS ELF format. */ | |
8393 | case OPTION_32: | |
8394 | mips_64 = 0; | |
8395 | break; | |
8396 | ||
8397 | case OPTION_64: | |
9c44af60 ILT |
8398 | { |
8399 | const char **list, **l; | |
8400 | ||
8401 | list = bfd_target_list (); | |
8402 | for (l = list; *l != NULL; l++) | |
8403 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8404 | || strcmp (*l, "elf64-littlemips") == 0) | |
8405 | break; | |
8406 | if (*l == NULL) | |
8407 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8408 | free (list); | |
8409 | mips_64 = 1; | |
8410 | } | |
7f9880e5 ILT |
8411 | break; |
8412 | ||
f3d817d8 DM |
8413 | default: |
8414 | return 0; | |
8ea7f4e8 ILT |
8415 | } |
8416 | ||
f3d817d8 | 8417 | return 1; |
8ea7f4e8 ILT |
8418 | } |
8419 | ||
f3d817d8 DM |
8420 | void |
8421 | md_show_usage (stream) | |
8422 | FILE *stream; | |
8423 | { | |
8424 | fprintf(stream, "\ | |
8425 | MIPS options:\n\ | |
8426 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8427 | -EB generate big endian output\n\ |
8428 | -EL generate little endian output\n\ | |
8429 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8430 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8431 | implicitly with the gp register [default 8]\n"); |
8432 | fprintf(stream, "\ | |
f3d817d8 DM |
8433 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8434 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8435 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8436 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8437 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8438 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8439 | -m4650 permit R4650 instructions\n\ |
8440 | -no-m4650 do not permit R4650 instructions\n\ | |
8441 | -m4010 permit R4010 instructions\n\ | |
8442 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8443 | -m4100 permit VR4100 instructions\n\ |
8444 | -no-m4100 do not permit VR4100 instructions\n"); | |
8445 | fprintf(stream, "\ | |
cc5703cd ILT |
8446 | -mips16 generate mips16 instructions\n\ |
8447 | -no-mips16 do not generate mips16 instructions\n"); | |
8448 | fprintf(stream, "\ | |
f3d817d8 DM |
8449 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8450 | -O remove unneeded NOPs and swap branches\n\ | |
8451 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8452 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8453 | #ifdef OBJ_ELF | |
8454 | fprintf(stream, "\ | |
8455 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8456 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8457 | -xgot assume a 32 bit GOT\n\ |
8458 | -32 create 32 bit object file (default)\n\ | |
8459 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8460 | #endif |
8461 | } | |
8462 | \f | |
efec4a28 DP |
8463 | void |
8464 | mips_init_after_args () | |
8465 | { | |
af942793 SS |
8466 | /* initialize opcodes */ |
8467 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
8468 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
8469 | } |
8470 | ||
3d3c5039 ILT |
8471 | long |
8472 | md_pcrel_from (fixP) | |
8473 | fixS *fixP; | |
8474 | { | |
1dc1e798 KR |
8475 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8476 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8477 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8478 | { | |
8479 | /* This makes a branch to an undefined symbol be a branch to the | |
8480 | current location. */ | |
8481 | return 4; | |
8482 | } | |
5b63f465 | 8483 | |
670a50eb ILT |
8484 | /* return the address of the delay slot */ |
8485 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8486 | } |
8487 | ||
abdad6bc ILT |
8488 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8489 | reloc for a cons. We could use the definition there, except that | |
8490 | we want to handle 64 bit relocs specially. */ | |
8491 | ||
8492 | void | |
8493 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8494 | fragS *frag; | |
8495 | int where; | |
8496 | unsigned int nbytes; | |
8497 | expressionS *exp; | |
8498 | { | |
bf39474f | 8499 | #ifndef OBJ_ELF |
abdad6bc | 8500 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8501 | 4 byte reloc. */ |
8502 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8503 | { |
b9129c6f | 8504 | if (target_big_endian) |
abdad6bc ILT |
8505 | where += 4; |
8506 | nbytes = 4; | |
8507 | } | |
bf39474f | 8508 | #endif |
abdad6bc | 8509 | |
7f9880e5 | 8510 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8511 | as_bad ("Unsupported reloc size %d", nbytes); |
8512 | ||
8513 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8514 | (nbytes == 2 |
8515 | ? BFD_RELOC_16 | |
8516 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8517 | } |
8518 | ||
23604921 ILT |
8519 | /* This is called before the symbol table is processed. In order to |
8520 | work with gcc when using mips-tfile, we must keep all local labels. | |
8521 | However, in other cases, we want to discard them. If we were | |
8522 | called with -g, but we didn't see any debugging information, it may | |
8523 | mean that gcc is smuggling debugging information through to | |
8524 | mips-tfile, in which case we must generate all local labels. */ | |
8525 | ||
8526 | void | |
8527 | mips_frob_file_before_adjust () | |
8528 | { | |
8529 | #ifndef NO_ECOFF_DEBUGGING | |
8530 | if (ECOFF_DEBUGGING | |
8531 | && mips_debug != 0 | |
8532 | && ! ecoff_debugging_seen) | |
8533 | flag_keep_locals = 1; | |
8534 | #endif | |
8535 | } | |
8536 | ||
867a58b3 ILT |
8537 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8538 | the corresponding LO reloc. This is called before md_apply_fix and | |
8539 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8540 | explicit use of the %hi modifier. */ | |
8541 | ||
8542 | void | |
8543 | mips_frob_file () | |
8544 | { | |
8545 | struct mips_hi_fixup *l; | |
8546 | ||
8547 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8548 | { | |
8549 | segment_info_type *seginfo; | |
9b61d62b | 8550 | int pass; |
867a58b3 ILT |
8551 | |
8552 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8553 | ||
8554 | /* Check quickly whether the next fixup happens to be a matching | |
8555 | %lo. */ | |
8556 | if (l->fixp->fx_next != NULL | |
8557 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8558 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8559 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8560 | continue; | |
8561 | ||
8562 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8563 | When we find one, move the %hi just in front of it. We do |
8564 | this in two passes. In the first pass, we try to find a | |
8565 | unique %lo. In the second pass, we permit multiple %hi | |
8566 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8567 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8568 | for (pass = 0; pass < 2; pass++) |
8569 | { | |
8570 | fixS *f, *prev; | |
8571 | ||
8572 | prev = NULL; | |
8573 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8574 | { |
9b61d62b ILT |
8575 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8576 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8577 | && f->fx_addsy == l->fixp->fx_addsy | |
8578 | && f->fx_offset == l->fixp->fx_offset | |
8579 | && (pass == 1 | |
8580 | || prev == NULL | |
8581 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8582 | || prev->fx_addsy != f->fx_addsy | |
8583 | || prev->fx_offset != f->fx_offset)) | |
8584 | { | |
8585 | fixS **pf; | |
867a58b3 | 8586 | |
9b61d62b ILT |
8587 | /* Move l->fixp before f. */ |
8588 | for (pf = &seginfo->fix_root; | |
8589 | *pf != l->fixp; | |
8590 | pf = &(*pf)->fx_next) | |
8591 | assert (*pf != NULL); | |
867a58b3 | 8592 | |
9b61d62b | 8593 | *pf = l->fixp->fx_next; |
867a58b3 | 8594 | |
9b61d62b ILT |
8595 | l->fixp->fx_next = f; |
8596 | if (prev == NULL) | |
8597 | seginfo->fix_root = l->fixp; | |
8598 | else | |
8599 | prev->fx_next = l->fixp; | |
867a58b3 | 8600 | |
9b61d62b ILT |
8601 | break; |
8602 | } | |
8603 | ||
8604 | prev = f; | |
867a58b3 ILT |
8605 | } |
8606 | ||
9b61d62b ILT |
8607 | if (f != NULL) |
8608 | break; | |
867a58b3 | 8609 | |
9b61d62b ILT |
8610 | if (pass == 1) |
8611 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8612 | "Unmatched %%hi reloc"); | |
8613 | } | |
867a58b3 ILT |
8614 | } |
8615 | } | |
8616 | ||
1c803e52 ILT |
8617 | /* When generating embedded PIC code we need to use a special |
8618 | relocation to represent the difference of two symbols in the .text | |
8619 | section (switch tables use a difference of this sort). See | |
8620 | include/coff/mips.h for details. This macro checks whether this | |
8621 | fixup requires the special reloc. */ | |
8622 | #define SWITCH_TABLE(fixp) \ | |
8623 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8624 | && (fixp)->fx_addsy != NULL \ | |
8625 | && (fixp)->fx_subsy != NULL \ | |
8626 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8627 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8628 | ||
5b63f465 | 8629 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8630 | relocations, in case the linker has to relax a call. We also need |
8631 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8632 | |
8633 | /*ARGSUSED*/ | |
8634 | int | |
8635 | mips_force_relocation (fixp) | |
8636 | fixS *fixp; | |
8637 | { | |
1c803e52 | 8638 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8639 | && (fixp->fx_pcrel |
8640 | || SWITCH_TABLE (fixp) | |
8641 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8642 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8643 | } |
8644 | ||
8645 | /* Apply a fixup to the object file. */ | |
8646 | ||
3d3c5039 ILT |
8647 | int |
8648 | md_apply_fix (fixP, valueP) | |
8649 | fixS *fixP; | |
918692a5 | 8650 | valueT *valueP; |
3d3c5039 | 8651 | { |
670a50eb ILT |
8652 | unsigned char *buf; |
8653 | long insn, value; | |
3d3c5039 | 8654 | |
bf39474f ILT |
8655 | assert (fixP->fx_size == 4 |
8656 | || fixP->fx_r_type == BFD_RELOC_16 | |
8657 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8658 | |
670a50eb | 8659 | value = *valueP; |
1748b9d8 ILT |
8660 | |
8661 | /* If we aren't adjusting this fixup to be against the section | |
8662 | symbol, we need to adjust the value. */ | |
8663 | #ifdef S_GET_OTHER | |
8664 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8665 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8666 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8667 | { | |
8668 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8669 | if (value != 0 && ! fixP->fx_pcrel) | |
8670 | { | |
8671 | /* In this case, the bfd_install_relocation routine will | |
8672 | incorrectly add the symbol value back in. We just want | |
8673 | the addend to appear in the object file. */ | |
8674 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8675 | } | |
8676 | } | |
8677 | #endif | |
8678 | ||
670a50eb | 8679 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8680 | |
5b63f465 ILT |
8681 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8682 | fixP->fx_done = 1; | |
8683 | ||
670a50eb ILT |
8684 | switch (fixP->fx_r_type) |
8685 | { | |
3d3c5039 ILT |
8686 | case BFD_RELOC_MIPS_JMP: |
8687 | case BFD_RELOC_HI16: | |
8688 | case BFD_RELOC_HI16_S: | |
670a50eb | 8689 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8690 | case BFD_RELOC_MIPS_LITERAL: |
8691 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8692 | case BFD_RELOC_MIPS_GOT16: |
8693 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8694 | case BFD_RELOC_MIPS_GOT_HI16: |
8695 | case BFD_RELOC_MIPS_GOT_LO16: | |
8696 | case BFD_RELOC_MIPS_CALL_HI16: | |
8697 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8698 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8699 | if (fixP->fx_pcrel) |
7b777690 ILT |
8700 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8701 | "Invalid PC relative reloc"); | |
670a50eb | 8702 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8703 | break; |
3d3c5039 | 8704 | |
cc5703cd ILT |
8705 | case BFD_RELOC_MIPS16_JMP: |
8706 | /* We currently always generate a reloc against a symbol, which | |
8707 | means that we don't want an addend even if the symbol is | |
8708 | defined. */ | |
8709 | fixP->fx_addnumber = 0; | |
8710 | break; | |
8711 | ||
ecd4ca1c ILT |
8712 | case BFD_RELOC_PCREL_HI16_S: |
8713 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8714 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8715 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8716 | { | |
8717 | /* For an external symbol adjust by the address to make it | |
8718 | pcrel_offset. We use the address of the RELLO reloc | |
8719 | which follows this one. */ | |
8720 | value += (fixP->fx_next->fx_frag->fr_address | |
8721 | + fixP->fx_next->fx_where); | |
8722 | } | |
8723 | if (value & 0x8000) | |
8724 | value += 0x10000; | |
8725 | value >>= 16; | |
0221ddf7 | 8726 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8727 | if (target_big_endian) |
ecd4ca1c ILT |
8728 | buf += 2; |
8729 | md_number_to_chars (buf, value, 2); | |
8730 | break; | |
8731 | ||
8732 | case BFD_RELOC_PCREL_LO16: | |
8733 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8734 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8735 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8736 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8737 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8738 | if (target_big_endian) |
ecd4ca1c ILT |
8739 | buf += 2; |
8740 | md_number_to_chars (buf, value, 2); | |
8741 | break; | |
8742 | ||
bf39474f ILT |
8743 | case BFD_RELOC_64: |
8744 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8745 | extended value if we are only 32 bits. */ | |
8746 | if (fixP->fx_done | |
8747 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8748 | { | |
8749 | if (8 <= sizeof (valueT)) | |
8750 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8751 | value, 8); | |
8752 | else | |
8753 | { | |
8754 | long w1, w2; | |
8755 | long hiv; | |
8756 | ||
8757 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8758 | if (target_big_endian) |
bf39474f ILT |
8759 | w1 += 4; |
8760 | else | |
8761 | w2 += 4; | |
8762 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8763 | if ((value & 0x80000000) != 0) | |
8764 | hiv = 0xffffffff; | |
8765 | else | |
8766 | hiv = 0; | |
8767 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8768 | } | |
8769 | } | |
8770 | break; | |
8771 | ||
f3645945 ILT |
8772 | case BFD_RELOC_32: |
8773 | /* If we are deleting this reloc entry, we must fill in the | |
8774 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8775 | resolved when it appears but is later defined. We also need |
8776 | to fill in the value if this is an embedded PIC switch table | |
8777 | entry. */ | |
8778 | if (fixP->fx_done | |
8779 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8780 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8781 | value, 4); | |
8782 | break; | |
8783 | ||
49ad0c4c ILT |
8784 | case BFD_RELOC_16: |
8785 | /* If we are deleting this reloc entry, we must fill in the | |
8786 | value now. */ | |
8787 | assert (fixP->fx_size == 2); | |
8788 | if (fixP->fx_done) | |
8789 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8790 | value, 2); | |
8791 | break; | |
8792 | ||
f3645945 ILT |
8793 | case BFD_RELOC_LO16: |
8794 | /* When handling an embedded PIC switch statement, we can wind | |
8795 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8796 | if (fixP->fx_done) | |
8797 | { | |
8798 | if (value < -0x8000 || value > 0x7fff) | |
8799 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8800 | "relocation overflow"); | |
0221ddf7 | 8801 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8802 | if (target_big_endian) |
f3645945 ILT |
8803 | buf += 2; |
8804 | md_number_to_chars (buf, value, 2); | |
8805 | } | |
8806 | break; | |
8807 | ||
3d3c5039 | 8808 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8809 | /* |
8810 | * We need to save the bits in the instruction since fixup_segment() | |
8811 | * might be deleting the relocation entry (i.e., a branch within | |
8812 | * the current segment). | |
8813 | */ | |
fbcfacb7 | 8814 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8815 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8816 | "Branch to odd address (%lx)", value); | |
670a50eb | 8817 | value >>= 2; |
670a50eb ILT |
8818 | |
8819 | /* update old instruction data */ | |
8820 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8821 | if (target_big_endian) |
8822 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8823 | else | |
8824 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8825 | |
8826 | if (value >= -0x8000 && value < 0x8000) | |
8827 | insn |= value & 0xffff; | |
8828 | else | |
8829 | { | |
8830 | /* The branch offset is too large. If this is an | |
8831 | unconditional branch, and we are not generating PIC code, | |
8832 | we can convert it to an absolute jump instruction. */ | |
8833 | if (mips_pic == NO_PIC | |
8834 | && fixP->fx_done | |
8835 | && fixP->fx_frag->fr_address >= text_section->vma | |
8836 | && (fixP->fx_frag->fr_address | |
8837 | < text_section->vma + text_section->_raw_size) | |
8838 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8839 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8840 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8841 | { | |
8842 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8843 | insn = 0x0c000000; /* jal */ | |
8844 | else | |
8845 | insn = 0x08000000; /* j */ | |
8846 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8847 | fixP->fx_done = 0; | |
8848 | fixP->fx_addsy = section_symbol (text_section); | |
8849 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8850 | } | |
8851 | else | |
8852 | { | |
8853 | /* FIXME. It would be possible in principle to handle | |
8854 | conditional branches which overflow. They could be | |
8855 | transformed into a branch around a jump. This would | |
8856 | require setting up variant frags for each different | |
8857 | branch type. The native MIPS assembler attempts to | |
8858 | handle these cases, but it appears to do it | |
8859 | incorrectly. */ | |
8860 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8861 | "Relocation overflow"); | |
8862 | } | |
8863 | } | |
8864 | ||
604633ae | 8865 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8866 | break; |
3d3c5039 ILT |
8867 | |
8868 | default: | |
670a50eb | 8869 | internalError (); |
3d3c5039 | 8870 | } |
5b63f465 | 8871 | |
670a50eb | 8872 | return 1; |
3d3c5039 ILT |
8873 | } |
8874 | ||
8875 | #if 0 | |
8876 | void | |
670a50eb ILT |
8877 | printInsn (oc) |
8878 | unsigned long oc; | |
3d3c5039 | 8879 | { |
670a50eb ILT |
8880 | const struct mips_opcode *p; |
8881 | int treg, sreg, dreg, shamt; | |
8882 | short imm; | |
8883 | const char *args; | |
8884 | int i; | |
3d3c5039 | 8885 | |
670a50eb ILT |
8886 | for (i = 0; i < NUMOPCODES; ++i) |
8887 | { | |
8888 | p = &mips_opcodes[i]; | |
8889 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8890 | { | |
8891 | printf ("%08lx %s\t", oc, p->name); | |
8892 | treg = (oc >> 16) & 0x1f; | |
8893 | sreg = (oc >> 21) & 0x1f; | |
8894 | dreg = (oc >> 11) & 0x1f; | |
8895 | shamt = (oc >> 6) & 0x1f; | |
8896 | imm = oc; | |
8897 | for (args = p->args;; ++args) | |
8898 | { | |
8899 | switch (*args) | |
8900 | { | |
3d3c5039 | 8901 | case '\0': |
670a50eb ILT |
8902 | printf ("\n"); |
8903 | break; | |
3d3c5039 ILT |
8904 | |
8905 | case ',': | |
8906 | case '(': | |
8907 | case ')': | |
670a50eb ILT |
8908 | printf ("%c", *args); |
8909 | continue; | |
3d3c5039 ILT |
8910 | |
8911 | case 'r': | |
670a50eb ILT |
8912 | assert (treg == sreg); |
8913 | printf ("$%d,$%d", treg, sreg); | |
8914 | continue; | |
3d3c5039 ILT |
8915 | |
8916 | case 'd': | |
918692a5 | 8917 | case 'G': |
670a50eb ILT |
8918 | printf ("$%d", dreg); |
8919 | continue; | |
3d3c5039 ILT |
8920 | |
8921 | case 't': | |
918692a5 | 8922 | case 'E': |
670a50eb ILT |
8923 | printf ("$%d", treg); |
8924 | continue; | |
3d3c5039 | 8925 | |
9226253a ILT |
8926 | case 'k': |
8927 | printf ("0x%x", treg); | |
8928 | continue; | |
8929 | ||
3d3c5039 ILT |
8930 | case 'b': |
8931 | case 's': | |
670a50eb ILT |
8932 | printf ("$%d", sreg); |
8933 | continue; | |
3d3c5039 ILT |
8934 | |
8935 | case 'a': | |
670a50eb ILT |
8936 | printf ("0x%08lx", oc & 0x1ffffff); |
8937 | continue; | |
3d3c5039 ILT |
8938 | |
8939 | case 'i': | |
8940 | case 'j': | |
8941 | case 'o': | |
8942 | case 'u': | |
670a50eb ILT |
8943 | printf ("%d", imm); |
8944 | continue; | |
3d3c5039 ILT |
8945 | |
8946 | case '<': | |
56c96faa | 8947 | case '>': |
670a50eb ILT |
8948 | printf ("$%d", shamt); |
8949 | continue; | |
3d3c5039 ILT |
8950 | |
8951 | default: | |
670a50eb | 8952 | internalError (); |
3d3c5039 | 8953 | } |
670a50eb | 8954 | break; |
3d3c5039 | 8955 | } |
670a50eb | 8956 | return; |
3d3c5039 ILT |
8957 | } |
8958 | } | |
670a50eb | 8959 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8960 | } |
8961 | #endif | |
8962 | ||
8963 | static symbolS * | |
8964 | get_symbol () | |
8965 | { | |
670a50eb ILT |
8966 | int c; |
8967 | char *name; | |
8968 | symbolS *p; | |
8969 | ||
8970 | name = input_line_pointer; | |
8971 | c = get_symbol_end (); | |
8972 | p = (symbolS *) symbol_find_or_make (name); | |
8973 | *input_line_pointer = c; | |
8974 | return p; | |
3d3c5039 ILT |
8975 | } |
8976 | ||
becfe05e ILT |
8977 | /* Align the current frag to a given power of two. The MIPS assembler |
8978 | also automatically adjusts any preceding label. */ | |
8979 | ||
8980 | static void | |
23dc1ae3 | 8981 | mips_align (to, fill, label) |
becfe05e ILT |
8982 | int to; |
8983 | int fill; | |
23dc1ae3 | 8984 | symbolS *label; |
becfe05e | 8985 | { |
fbcfacb7 | 8986 | mips_emit_delays (false); |
e2e5acfa | 8987 | frag_align (to, fill, 0); |
becfe05e | 8988 | record_alignment (now_seg, to); |
23dc1ae3 | 8989 | if (label != NULL) |
becfe05e | 8990 | { |
23dc1ae3 ILT |
8991 | assert (S_GET_SEGMENT (label) == now_seg); |
8992 | label->sy_frag = frag_now; | |
8993 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8994 | } |
8995 | } | |
8996 | ||
8997 | /* Align to a given power of two. .align 0 turns off the automatic | |
8998 | alignment used by the data creating pseudo-ops. */ | |
8999 | ||
3d3c5039 ILT |
9000 | static void |
9001 | s_align (x) | |
9002 | int x; | |
9003 | { | |
670a50eb ILT |
9004 | register int temp; |
9005 | register long temp_fill; | |
9006 | long max_alignment = 15; | |
3d3c5039 | 9007 | |
670a50eb | 9008 | /* |
3d3c5039 ILT |
9009 | |
9010 | o Note that the assembler pulls down any immediately preceeding label | |
9011 | to the aligned address. | |
9012 | o It's not documented but auto alignment is reinstated by | |
9013 | a .align pseudo instruction. | |
9014 | o Note also that after auto alignment is turned off the mips assembler | |
9015 | issues an error on attempt to assemble an improperly aligned data item. | |
9016 | We don't. | |
9017 | ||
9018 | */ | |
9019 | ||
670a50eb ILT |
9020 | temp = get_absolute_expression (); |
9021 | if (temp > max_alignment) | |
9022 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9023 | else if (temp < 0) | |
9024 | { | |
9025 | as_warn ("Alignment negative: 0 assumed."); | |
9026 | temp = 0; | |
9027 | } | |
9028 | if (*input_line_pointer == ',') | |
9029 | { | |
9030 | input_line_pointer++; | |
9031 | temp_fill = get_absolute_expression (); | |
9032 | } | |
9033 | else | |
9034 | temp_fill = 0; | |
9035 | if (temp) | |
9036 | { | |
9037 | auto_align = 1; | |
fbcfacb7 ILT |
9038 | mips_align (temp, (int) temp_fill, |
9039 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9040 | } |
670a50eb ILT |
9041 | else |
9042 | { | |
9043 | auto_align = 0; | |
3d3c5039 ILT |
9044 | } |
9045 | ||
670a50eb | 9046 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9047 | } |
9048 | ||
739708fa KR |
9049 | void |
9050 | mips_flush_pending_output () | |
becfe05e | 9051 | { |
fbcfacb7 ILT |
9052 | mips_emit_delays (false); |
9053 | mips_clear_insn_labels (); | |
becfe05e ILT |
9054 | } |
9055 | ||
3d3c5039 ILT |
9056 | static void |
9057 | s_change_sec (sec) | |
9058 | int sec; | |
9059 | { | |
88225433 | 9060 | segT seg; |
becfe05e | 9061 | |
5b63f465 ILT |
9062 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9063 | .sdata and .sbss sections. We change the .data and .rdata | |
9064 | pseudo-ops to use .sdata. */ | |
9065 | if (mips_pic == EMBEDDED_PIC | |
9066 | && (sec == 'd' || sec == 'r')) | |
9067 | sec = 's'; | |
9068 | ||
fbcfacb7 | 9069 | mips_emit_delays (false); |
670a50eb ILT |
9070 | switch (sec) |
9071 | { | |
3d3c5039 | 9072 | case 't': |
604633ae | 9073 | s_text (0); |
670a50eb | 9074 | break; |
3d3c5039 | 9075 | case 'd': |
604633ae | 9076 | s_data (0); |
670a50eb | 9077 | break; |
3d3c5039 | 9078 | case 'b': |
670a50eb | 9079 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9080 | demand_empty_rest_of_line (); |
9081 | break; | |
88225433 ILT |
9082 | |
9083 | case 'r': | |
1dc1e798 KR |
9084 | if (USE_GLOBAL_POINTER_OPT) |
9085 | { | |
9086 | seg = subseg_new (RDATA_SECTION_NAME, | |
9087 | (subsegT) get_absolute_expression ()); | |
9088 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9089 | { | |
9090 | bfd_set_section_flags (stdoutput, seg, | |
9091 | (SEC_ALLOC | |
9092 | | SEC_LOAD | |
9093 | | SEC_READONLY | |
9094 | | SEC_RELOC | |
9095 | | SEC_DATA)); | |
08e17202 ILT |
9096 | if (strcmp (TARGET_OS, "elf") != 0) |
9097 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9098 | } |
9099 | demand_empty_rest_of_line (); | |
9100 | } | |
9101 | else | |
9102 | { | |
9103 | as_bad ("No read only data section in this object file format"); | |
9104 | demand_empty_rest_of_line (); | |
9105 | return; | |
9106 | } | |
88225433 | 9107 | break; |
88225433 ILT |
9108 | |
9109 | case 's': | |
1dc1e798 KR |
9110 | if (USE_GLOBAL_POINTER_OPT) |
9111 | { | |
9112 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9113 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9114 | { | |
9115 | bfd_set_section_flags (stdoutput, seg, | |
9116 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9117 | | SEC_DATA); | |
08e17202 ILT |
9118 | if (strcmp (TARGET_OS, "elf") != 0) |
9119 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9120 | } |
9121 | demand_empty_rest_of_line (); | |
9122 | break; | |
9123 | } | |
9124 | else | |
9125 | { | |
9126 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9127 | demand_empty_rest_of_line (); | |
9128 | return; | |
9129 | } | |
3d3c5039 | 9130 | } |
88225433 | 9131 | |
670a50eb | 9132 | auto_align = 1; |
3d3c5039 ILT |
9133 | } |
9134 | ||
739708fa KR |
9135 | void |
9136 | mips_enable_auto_align () | |
9da4c5d1 | 9137 | { |
9da4c5d1 ILT |
9138 | auto_align = 1; |
9139 | } | |
9140 | ||
3d3c5039 ILT |
9141 | static void |
9142 | s_cons (log_size) | |
9143 | int log_size; | |
9144 | { | |
23dc1ae3 ILT |
9145 | symbolS *label; |
9146 | ||
fbcfacb7 ILT |
9147 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9148 | mips_emit_delays (false); | |
670a50eb | 9149 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9150 | mips_align (log_size, 0, label); |
fbcfacb7 | 9151 | mips_clear_insn_labels (); |
670a50eb | 9152 | cons (1 << log_size); |
3d3c5039 ILT |
9153 | } |
9154 | ||
3d3c5039 | 9155 | static void |
becfe05e ILT |
9156 | s_float_cons (type) |
9157 | int type; | |
3d3c5039 | 9158 | { |
23dc1ae3 ILT |
9159 | symbolS *label; |
9160 | ||
fbcfacb7 | 9161 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9162 | |
fbcfacb7 | 9163 | mips_emit_delays (false); |
670a50eb ILT |
9164 | |
9165 | if (auto_align) | |
becfe05e | 9166 | if (type == 'd') |
23dc1ae3 | 9167 | mips_align (3, 0, label); |
670a50eb | 9168 | else |
23dc1ae3 | 9169 | mips_align (2, 0, label); |
670a50eb | 9170 | |
fbcfacb7 | 9171 | mips_clear_insn_labels (); |
1849d646 | 9172 | |
becfe05e | 9173 | float_cons (type); |
3d3c5039 ILT |
9174 | } |
9175 | ||
c1444ec4 ILT |
9176 | /* Handle .globl. We need to override it because on Irix 5 you are |
9177 | permitted to say | |
9178 | .globl foo .text | |
9179 | where foo is an undefined symbol, to mean that foo should be | |
9180 | considered to be the address of a function. */ | |
9181 | ||
9182 | static void | |
9183 | s_mips_globl (x) | |
9184 | int x; | |
9185 | { | |
9186 | char *name; | |
9187 | int c; | |
9188 | symbolS *symbolP; | |
fb251650 | 9189 | flagword flag; |
c1444ec4 ILT |
9190 | |
9191 | name = input_line_pointer; | |
9192 | c = get_symbol_end (); | |
9193 | symbolP = symbol_find_or_make (name); | |
9194 | *input_line_pointer = c; | |
9195 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9196 | |
9197 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9198 | being a function is apparently labelled as being an object. */ | |
9199 | flag = BSF_OBJECT; | |
9200 | ||
c1444ec4 ILT |
9201 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9202 | { | |
9203 | char *secname; | |
9204 | asection *sec; | |
9205 | ||
9206 | secname = input_line_pointer; | |
9207 | c = get_symbol_end (); | |
9208 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9209 | if (sec == NULL) | |
9210 | as_bad ("%s: no such section", secname); | |
9211 | *input_line_pointer = c; | |
9212 | ||
9213 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9214 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9215 | } |
9216 | ||
fb251650 ILT |
9217 | symbolP->bsym->flags |= flag; |
9218 | ||
c1444ec4 ILT |
9219 | S_SET_EXTERNAL (symbolP); |
9220 | demand_empty_rest_of_line (); | |
9221 | } | |
9222 | ||
3d3c5039 ILT |
9223 | static void |
9224 | s_option (x) | |
9225 | int x; | |
9226 | { | |
dd3f1f76 ILT |
9227 | char *opt; |
9228 | char c; | |
9229 | ||
9230 | opt = input_line_pointer; | |
9231 | c = get_symbol_end (); | |
9232 | ||
dd3f1f76 | 9233 | if (*opt == 'O') |
9226253a ILT |
9234 | { |
9235 | /* FIXME: What does this mean? */ | |
9236 | } | |
dd3f1f76 | 9237 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9238 | { |
d9aba805 | 9239 | int i; |
42562568 | 9240 | |
d9aba805 ILT |
9241 | i = atoi (opt + 3); |
9242 | if (i == 0) | |
9243 | mips_pic = NO_PIC; | |
9244 | else if (i == 2) | |
9245 | mips_pic = SVR4_PIC; | |
9246 | else | |
9247 | as_bad (".option pic%d not supported", i); | |
9248 | ||
1dc1e798 | 9249 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9250 | { |
9251 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9252 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9253 | g_switch_value = 0; |
9254 | bfd_set_gp_size (stdoutput, 0); | |
9255 | } | |
9226253a | 9256 | } |
dd3f1f76 ILT |
9257 | else |
9258 | as_warn ("Unrecognized option \"%s\"", opt); | |
9259 | ||
9260 | *input_line_pointer = c; | |
670a50eb | 9261 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9262 | } |
9263 | ||
9264 | static void | |
9265 | s_mipsset (x) | |
9266 | int x; | |
9267 | { | |
670a50eb ILT |
9268 | char *name = input_line_pointer, ch; |
9269 | ||
9270 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9271 | input_line_pointer++; | |
9272 | ch = *input_line_pointer; | |
9273 | *input_line_pointer = '\0'; | |
9274 | ||
9275 | if (strcmp (name, "reorder") == 0) | |
9276 | { | |
4a1cb507 | 9277 | if (mips_noreorder && prev_nop_frag != NULL) |
4e95866e | 9278 | { |
4a1cb507 ILT |
9279 | /* If we still have pending nops, we can discard them. The |
9280 | usual nop handling will insert any that are still | |
9281 | needed. */ | |
9282 | prev_nop_frag->fr_fix -= prev_nop_frag_holds * (mips16 ? 2 : 4); | |
9283 | prev_nop_frag = NULL; | |
4e95866e | 9284 | } |
670a50eb ILT |
9285 | mips_noreorder = 0; |
9286 | } | |
9287 | else if (strcmp (name, "noreorder") == 0) | |
9288 | { | |
fbcfacb7 | 9289 | mips_emit_delays (true); |
670a50eb | 9290 | mips_noreorder = 1; |
0dd2d296 | 9291 | mips_any_noreorder = 1; |
670a50eb ILT |
9292 | } |
9293 | else if (strcmp (name, "at") == 0) | |
9294 | { | |
9295 | mips_noat = 0; | |
9296 | } | |
9297 | else if (strcmp (name, "noat") == 0) | |
9298 | { | |
9299 | mips_noat = 1; | |
3d3c5039 | 9300 | } |
670a50eb ILT |
9301 | else if (strcmp (name, "macro") == 0) |
9302 | { | |
9303 | mips_warn_about_macros = 0; | |
9304 | } | |
9305 | else if (strcmp (name, "nomacro") == 0) | |
9306 | { | |
9307 | if (mips_noreorder == 0) | |
9308 | as_bad ("`noreorder' must be set before `nomacro'"); | |
9309 | mips_warn_about_macros = 1; | |
9310 | } | |
9311 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9312 | { | |
9313 | mips_nomove = 0; | |
9314 | } | |
9315 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9316 | { | |
9317 | mips_nomove = 1; | |
9318 | } | |
9319 | else if (strcmp (name, "bopt") == 0) | |
9320 | { | |
9321 | mips_nobopt = 0; | |
9322 | } | |
9323 | else if (strcmp (name, "nobopt") == 0) | |
9324 | { | |
9325 | mips_nobopt = 1; | |
9326 | } | |
943321c0 ILT |
9327 | else if (strcmp (name, "mips16") == 0 |
9328 | || strcmp (name, "MIPS-16") == 0) | |
9329 | mips16 = 1; | |
9330 | else if (strcmp (name, "nomips16") == 0 | |
9331 | || strcmp (name, "noMIPS-16") == 0) | |
9332 | mips16 = 0; | |
1051c97f ILT |
9333 | else if (strncmp (name, "mips", 4) == 0) |
9334 | { | |
9335 | int isa; | |
9336 | ||
9337 | /* Permit the user to change the ISA on the fly. Needless to | |
9338 | say, misuse can cause serious problems. */ | |
9339 | isa = atoi (name + 4); | |
9340 | if (isa == 0) | |
9341 | mips_isa = file_mips_isa; | |
d8a1c247 | 9342 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9343 | as_bad ("unknown ISA level"); |
9344 | else | |
9345 | mips_isa = isa; | |
9346 | } | |
cc5703cd ILT |
9347 | else if (strcmp (name, "autoextend") == 0) |
9348 | mips16_autoextend = 1; | |
9349 | else if (strcmp (name, "noautoextend") == 0) | |
9350 | mips16_autoextend = 0; | |
670a50eb ILT |
9351 | else |
9352 | { | |
9353 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9354 | } | |
9355 | *input_line_pointer = ch; | |
9356 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9357 | } |
9358 | ||
9226253a ILT |
9359 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9360 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9361 | ||
9362 | static void | |
9363 | s_abicalls (ignore) | |
9364 | int ignore; | |
9365 | { | |
d9aba805 | 9366 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9367 | if (USE_GLOBAL_POINTER_OPT) |
9368 | { | |
9369 | if (g_switch_seen && g_switch_value != 0) | |
9370 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9371 | g_switch_value = 0; | |
9372 | } | |
d9aba805 | 9373 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9374 | demand_empty_rest_of_line (); |
9375 | } | |
9376 | ||
9377 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9378 | PIC code. It sets the $gp register for the function based on the | |
9379 | function address, which is in the register named in the argument. | |
9380 | This uses a relocation against _gp_disp, which is handled specially | |
9381 | by the linker. The result is: | |
9382 | lui $gp,%hi(_gp_disp) | |
9383 | addiu $gp,$gp,%lo(_gp_disp) | |
9384 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9385 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9386 | |
9387 | static void | |
9388 | s_cpload (ignore) | |
9389 | int ignore; | |
9390 | { | |
9391 | expressionS ex; | |
9392 | int icnt = 0; | |
9393 | ||
d9aba805 ILT |
9394 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9395 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9396 | { |
9397 | s_ignore (0); | |
9398 | return; | |
9399 | } | |
9400 | ||
9401 | /* .cpload should be a in .set noreorder section. */ | |
9402 | if (mips_noreorder == 0) | |
9403 | as_warn (".cpload not in noreorder section"); | |
9404 | ||
9226253a ILT |
9405 | ex.X_op = O_symbol; |
9406 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9407 | ex.X_op_symbol = NULL; | |
9408 | ex.X_add_number = 0; | |
9409 | ||
fb251650 ILT |
9410 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9411 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9412 | ||
0dd2d296 ILT |
9413 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9414 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9415 | (int) BFD_RELOC_LO16); |
9416 | ||
0dd2d296 ILT |
9417 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9418 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9419 | |
9420 | demand_empty_rest_of_line (); | |
9421 | } | |
9422 | ||
9423 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9424 | offset from $sp. The offset is remembered, and after making a PIC | |
9425 | call $gp is restored from that location. */ | |
9426 | ||
9427 | static void | |
9428 | s_cprestore (ignore) | |
9429 | int ignore; | |
9430 | { | |
9431 | expressionS ex; | |
9432 | int icnt = 0; | |
9433 | ||
d9aba805 ILT |
9434 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9435 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9436 | { |
9437 | s_ignore (0); | |
9438 | return; | |
9439 | } | |
9440 | ||
9226253a ILT |
9441 | mips_cprestore_offset = get_absolute_expression (); |
9442 | ||
9443 | ex.X_op = O_constant; | |
9444 | ex.X_add_symbol = NULL; | |
9445 | ex.X_op_symbol = NULL; | |
9446 | ex.X_add_number = mips_cprestore_offset; | |
9447 | ||
0dd2d296 | 9448 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9449 | mips_isa < 3 ? "sw" : "sd", |
9450 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9451 | ||
9452 | demand_empty_rest_of_line (); | |
9453 | } | |
9454 | ||
0dd2d296 ILT |
9455 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9456 | code. It generates a 32 bit GP relative reloc. */ | |
9457 | ||
9458 | static void | |
9459 | s_gpword (ignore) | |
9460 | int ignore; | |
9461 | { | |
23dc1ae3 | 9462 | symbolS *label; |
0dd2d296 ILT |
9463 | expressionS ex; |
9464 | char *p; | |
9465 | ||
9466 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9467 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9468 | { |
9469 | s_cons (2); | |
9470 | return; | |
9471 | } | |
9472 | ||
fbcfacb7 ILT |
9473 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9474 | mips_emit_delays (true); | |
0dd2d296 | 9475 | if (auto_align) |
23dc1ae3 | 9476 | mips_align (2, 0, label); |
fbcfacb7 | 9477 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9478 | |
9479 | expression (&ex); | |
9480 | ||
9481 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9482 | { | |
9483 | as_bad ("Unsupported use of .gpword"); | |
9484 | ignore_rest_of_line (); | |
9485 | } | |
9486 | ||
9487 | p = frag_more (4); | |
9488 | md_number_to_chars (p, (valueT) 0, 4); | |
9489 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9490 | BFD_RELOC_MIPS_GPREL32); | |
9491 | ||
9492 | demand_empty_rest_of_line (); | |
9493 | } | |
9494 | ||
9495 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9496 | tables in SVR4 PIC code. */ | |
9497 | ||
9498 | static void | |
9499 | s_cpadd (ignore) | |
9500 | int ignore; | |
9501 | { | |
9502 | int icnt = 0; | |
9503 | int reg; | |
9504 | ||
9505 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9506 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9507 | { |
9508 | s_ignore (0); | |
9509 | return; | |
9510 | } | |
9511 | ||
9512 | /* Add $gp to the register named as an argument. */ | |
9513 | reg = tc_get_register (0); | |
9514 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9515 | mips_isa < 3 ? "addu" : "daddu", | |
9516 | "d,v,t", reg, reg, GP); | |
9517 | ||
9518 | demand_empty_rest_of_line (); | |
9519 | } | |
9520 | ||
ed3eb786 ILT |
9521 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9522 | mips16 mode. This permits the linker to handle them specially, | |
9523 | such as generating jalx instructions when needed. We also make | |
9524 | them odd for the duration of the assembly, in order to generate the | |
9525 | right sort of code. We will make them even in the adjust_symtab | |
9526 | routine, while leaving them marked. This is convenient for the | |
9527 | debugger and the disassembler. The linker knows to make them odd | |
9528 | again. */ | |
9529 | ||
9530 | static void | |
9531 | s_insn (ignore) | |
9532 | int ignore; | |
9533 | { | |
9534 | if (mips16) | |
9535 | { | |
9536 | struct insn_label_list *l; | |
9537 | ||
9538 | for (l = insn_labels; l != NULL; l = l->next) | |
9539 | { | |
9540 | #ifdef S_SET_OTHER | |
9541 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9542 | S_SET_OTHER (l->label, STO_MIPS16); | |
9543 | #endif | |
9544 | ++l->label->sy_value.X_add_number; | |
9545 | } | |
9546 | ||
9547 | mips_clear_insn_labels (); | |
9548 | } | |
9549 | ||
9550 | demand_empty_rest_of_line (); | |
9551 | } | |
9552 | ||
9226253a | 9553 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9554 | to parse .frame. The argument is non-zero if this is the frame |
9555 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9556 | |
3d3c5039 | 9557 | int |
0dd2d296 ILT |
9558 | tc_get_register (frame) |
9559 | int frame; | |
3d3c5039 ILT |
9560 | { |
9561 | int reg; | |
9562 | ||
9563 | SKIP_WHITESPACE (); | |
9564 | if (*input_line_pointer++ != '$') | |
9565 | { | |
9566 | as_warn ("expected `$'"); | |
0dd2d296 | 9567 | reg = 0; |
3d3c5039 | 9568 | } |
0dd2d296 | 9569 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9570 | { |
9571 | reg = get_absolute_expression (); | |
9572 | if (reg < 0 || reg >= 32) | |
9573 | { | |
9574 | as_warn ("Bad register number"); | |
9575 | reg = 0; | |
9576 | } | |
9577 | } | |
9578 | else | |
9579 | { | |
9580 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9581 | reg = FP; |
3d3c5039 | 9582 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9583 | reg = SP; |
3d3c5039 | 9584 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9585 | reg = GP; |
3d3c5039 | 9586 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9587 | reg = AT; |
3d3c5039 ILT |
9588 | else |
9589 | { | |
9590 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9591 | reg = 0; |
3d3c5039 ILT |
9592 | } |
9593 | input_line_pointer += 2; | |
9594 | } | |
0dd2d296 ILT |
9595 | if (frame) |
9596 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9597 | return reg; |
9598 | } | |
9599 | ||
0dd2d296 ILT |
9600 | valueT |
9601 | md_section_align (seg, addr) | |
9602 | asection *seg; | |
9603 | valueT addr; | |
9604 | { | |
9605 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9606 | ||
cf32394d ILT |
9607 | #ifdef OBJ_ELF |
9608 | /* We don't need to align ELF sections to the full alignment. | |
9609 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9610 | byte boundary. We don't bother to align the sections if we are |
9611 | targeted for an embedded system. */ | |
9612 | if (strcmp (TARGET_OS, "elf") == 0) | |
9613 | return addr; | |
943321c0 ILT |
9614 | if (align > 4) |
9615 | align = 4; | |
10a14e36 | 9616 | #endif |
cf32394d ILT |
9617 | |
9618 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9619 | } |
9620 | ||
d8a1c247 KR |
9621 | /* Utility routine, called from above as well. If called while the |
9622 | input file is still being read, it's only an approximation. (For | |
9623 | example, a symbol may later become defined which appeared to be | |
9624 | undefined earlier.) */ | |
22ba90ce ILT |
9625 | |
9626 | static int | |
9627 | nopic_need_relax (sym) | |
d8a1c247 KR |
9628 | symbolS *sym; |
9629 | { | |
9630 | if (sym == 0) | |
9631 | return 0; | |
9632 | ||
1dc1e798 KR |
9633 | if (USE_GLOBAL_POINTER_OPT) |
9634 | { | |
9635 | const char *symname; | |
9636 | int change; | |
9637 | ||
9638 | /* Find out whether this symbol can be referenced off the GP | |
9639 | register. It can be if it is smaller than the -G size or if | |
9640 | it is in the .sdata or .sbss section. Certain symbols can | |
9641 | not be referenced off the GP, although it appears as though | |
9642 | they can. */ | |
9643 | symname = S_GET_NAME (sym); | |
9644 | if (symname != (const char *) NULL | |
9645 | && (strcmp (symname, "eprol") == 0 | |
9646 | || strcmp (symname, "etext") == 0 | |
9647 | || strcmp (symname, "_gp") == 0 | |
9648 | || strcmp (symname, "edata") == 0 | |
9649 | || strcmp (symname, "_fbss") == 0 | |
9650 | || strcmp (symname, "_fdata") == 0 | |
9651 | || strcmp (symname, "_ftext") == 0 | |
9652 | || strcmp (symname, "end") == 0 | |
9653 | || strcmp (symname, "_gp_disp") == 0)) | |
9654 | change = 1; | |
9655 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9656 | && (0 |
9657 | #ifndef NO_ECOFF_DEBUGGING | |
9658 | || (sym->ecoff_extern_size != 0 | |
9659 | && sym->ecoff_extern_size <= g_switch_value) | |
9660 | #endif | |
1dc1e798 KR |
9661 | || (S_GET_VALUE (sym) != 0 |
9662 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9663 | change = 0; | |
9664 | else | |
9665 | { | |
9666 | const char *segname; | |
d8a1c247 | 9667 | |
1dc1e798 KR |
9668 | segname = segment_name (S_GET_SEGMENT (sym)); |
9669 | assert (strcmp (segname, ".lit8") != 0 | |
9670 | && strcmp (segname, ".lit4") != 0); | |
9671 | change = (strcmp (segname, ".sdata") != 0 | |
9672 | && strcmp (segname, ".sbss") != 0); | |
9673 | } | |
9674 | return change; | |
9675 | } | |
9676 | else | |
9677 | /* We are not optimizing for the GP register. */ | |
9678 | return 1; | |
d8a1c247 KR |
9679 | } |
9680 | ||
cc5703cd ILT |
9681 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9682 | extended opcode. SEC is the section the frag is in. */ | |
9683 | ||
9684 | static int | |
9685 | mips16_extended_frag (fragp, sec, stretch) | |
9686 | fragS *fragp; | |
9687 | asection *sec; | |
9688 | long stretch; | |
9689 | { | |
9690 | int type; | |
9691 | register const struct mips16_immed_operand *op; | |
9692 | offsetT val; | |
9693 | int mintiny, maxtiny; | |
f74ba7a3 | 9694 | segT symsec; |
cc5703cd | 9695 | |
8728fa92 ILT |
9696 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9697 | return 0; | |
9698 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9699 | return 1; | |
9700 | ||
cc5703cd ILT |
9701 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9702 | op = mips16_immed_operands; | |
9703 | while (op->type != type) | |
9704 | { | |
9705 | ++op; | |
9706 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9707 | } | |
9708 | ||
9709 | if (op->unsp) | |
9710 | { | |
9711 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9712 | { | |
9713 | mintiny = 1; | |
9714 | maxtiny = 1 << op->nbits; | |
9715 | } | |
9716 | else | |
9717 | { | |
9718 | mintiny = 0; | |
9719 | maxtiny = (1 << op->nbits) - 1; | |
9720 | } | |
9721 | } | |
9722 | else | |
9723 | { | |
9724 | mintiny = - (1 << (op->nbits - 1)); | |
9725 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9726 | } | |
9727 | ||
f74ba7a3 ILT |
9728 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9729 | a particular frag address. */ | |
9730 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9731 | { | |
9732 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9733 | + fragp->fr_symbol->sy_frag->fr_address); | |
9734 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9735 | } | |
9736 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9737 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9738 | == O_constant)) | |
9739 | { | |
9740 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9741 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9742 | + fragp->fr_symbol->sy_value.X_add_number | |
9743 | + fragp->fr_symbol->sy_frag->fr_address); | |
9744 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9745 | } | |
9746 | else | |
9747 | return 1; | |
cc5703cd ILT |
9748 | |
9749 | if (op->pcrel) | |
9750 | { | |
9751 | addressT addr; | |
9752 | ||
9753 | /* We won't have the section when we are called from | |
9754 | mips_relax_frag. However, we will always have been called | |
9755 | from md_estimate_size_before_relax first. If this is a | |
9756 | branch to a different section, we mark it as such. If SEC is | |
9757 | NULL, and the frag is not marked, then it must be a branch to | |
9758 | the same section. */ | |
9759 | if (sec == NULL) | |
9760 | { | |
9761 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9762 | return 1; | |
9763 | } | |
9764 | else | |
9765 | { | |
f74ba7a3 | 9766 | if (symsec != sec) |
cc5703cd ILT |
9767 | { |
9768 | fragp->fr_subtype = | |
9769 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9770 | ||
9771 | /* FIXME: We should support this, and let the linker | |
9772 | catch branches and loads that are out of range. */ | |
9773 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9774 | "unsupported PC relative reference to different section"); | |
9775 | ||
9776 | return 1; | |
9777 | } | |
9778 | } | |
9779 | ||
9780 | /* In this case, we know for sure that the symbol fragment is in | |
9781 | the same section. If the fr_address of the symbol fragment | |
9782 | is greater then the address of this fragment we want to add | |
9783 | in STRETCH in order to get a better estimate of the address. | |
9784 | This particularly matters because of the shift bits. */ | |
9785 | if (stretch != 0 | |
9786 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9787 | { | |
9788 | fragS *f; | |
9789 | ||
e2e5acfa JW |
9790 | /* Adjust stretch for any alignment frag. FIXME: This |
9791 | doesn't handle the fr_subtype field, which specifies a | |
9792 | maximum number of bytes to skip when doing an alignment. */ | |
cc5703cd ILT |
9793 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) |
9794 | { | |
9795 | assert (f != NULL); | |
9796 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9797 | { | |
9798 | if (stretch < 0) | |
9799 | stretch = - ((- stretch) | |
9800 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9801 | else | |
9802 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9803 | if (stretch == 0) | |
9804 | break; | |
9805 | } | |
9806 | } | |
9807 | val += stretch; | |
9808 | } | |
9809 | ||
a677feeb ILT |
9810 | addr = fragp->fr_address + fragp->fr_fix; |
9811 | ||
9812 | /* The base address rules are complicated. The base address of | |
9813 | a branch is the following instruction. The base address of a | |
9814 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
9815 | is in a delay slot (in which case it can not be extended) use |
9816 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 9817 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
9818 | { |
9819 | addr += 2; | |
319305a7 ILT |
9820 | |
9821 | /* If we are currently assuming that this frag should be | |
9822 | extended, then, the current address is two bytes | |
9823 | higher. */ | |
9824 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9825 | addr += 2; | |
9826 | ||
fbcfacb7 ILT |
9827 | /* Ignore the low bit in the target, since it will be set |
9828 | for a text label. */ | |
9829 | if ((val & 1) != 0) | |
9830 | --val; | |
9831 | } | |
a677feeb ILT |
9832 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9833 | addr -= 4; | |
9834 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9835 | addr -= 2; | |
cc5703cd | 9836 | |
cc5703cd ILT |
9837 | val -= addr & ~ ((1 << op->shift) - 1); |
9838 | ||
9839 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9840 | if (type == 'p' || type == 'q') | |
9841 | val /= 2; | |
9842 | ||
9843 | /* If any of the shifted bits are set, we must use an extended | |
9844 | opcode. If the address depends on the size of this | |
9845 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9846 | use an extended opcode. We only check this when we are in |
9847 | the main relaxation loop, when SEC is NULL. */ | |
9848 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9849 | { | |
9850 | fragp->fr_subtype = | |
9851 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9852 | return 1; | |
9853 | } | |
9854 | ||
9855 | /* If we are about to mark a frag as extended because the value | |
9856 | is precisely maxtiny + 1, then there is a chance of an | |
9857 | infinite loop as in the following code: | |
9858 | la $4,foo | |
9859 | .skip 1020 | |
9860 | .align 2 | |
9861 | foo: | |
9862 | In this case when the la is extended, foo is 0x3fc bytes | |
9863 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9864 | the la must be extended. To avoid this loop, we mark the | |
9865 | frag as extended if it was small, and is about to become | |
9866 | extended with a value of maxtiny + 1. */ | |
9867 | if (val == ((maxtiny + 1) << op->shift) | |
9868 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9869 | && sec == NULL) | |
cc5703cd ILT |
9870 | { |
9871 | fragp->fr_subtype = | |
9872 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9873 | return 1; | |
9874 | } | |
9875 | } | |
41a0ed22 ILT |
9876 | else if (symsec != absolute_section && sec != NULL) |
9877 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9878 | |
9879 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9880 | || val < (mintiny << op->shift) | |
9881 | || val > (maxtiny << op->shift)) | |
9882 | return 1; | |
9883 | else | |
9884 | return 0; | |
9885 | } | |
9886 | ||
9887 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9888 | mips16, we are not really relaxing here, and the final size is | |
9889 | encoded in the subtype information. For the mips16, we have to | |
9890 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9891 | |
0dd2d296 ILT |
9892 | /*ARGSUSED*/ |
9893 | int | |
9894 | md_estimate_size_before_relax (fragp, segtype) | |
9895 | fragS *fragp; | |
9896 | asection *segtype; | |
9897 | { | |
9898 | int change; | |
9899 | ||
cc5703cd ILT |
9900 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9901 | { | |
9902 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9903 | { | |
9904 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9905 | return 4; | |
9906 | } | |
9907 | else | |
9908 | { | |
9909 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9910 | return 2; | |
9911 | } | |
9912 | } | |
9913 | ||
d9aba805 | 9914 | if (mips_pic == NO_PIC) |
0dd2d296 | 9915 | { |
d8a1c247 | 9916 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9917 | } |
d9aba805 | 9918 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9919 | { |
9920 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9921 | ||
9922 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9923 | change = (symsec != &bfd_und_section | |
9924 | && symsec != &bfd_abs_section | |
9925 | && ! bfd_is_com_section (symsec)); | |
9926 | } | |
d9aba805 ILT |
9927 | else |
9928 | abort (); | |
0dd2d296 ILT |
9929 | |
9930 | if (change) | |
9931 | { | |
9932 | /* Record the offset to the first reloc in the fr_opcode field. | |
9933 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9934 | must be expanded. */ | |
9935 | fragp->fr_opcode = (fragp->fr_literal | |
9936 | + fragp->fr_fix | |
9937 | - RELAX_OLD (fragp->fr_subtype) | |
9938 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9939 | /* FIXME: This really needs as_warn_where. */ | |
9940 | if (RELAX_WARN (fragp->fr_subtype)) | |
9941 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9942 | } | |
9943 | ||
9944 | if (! change) | |
9945 | return 0; | |
9946 | else | |
9947 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9948 | } | |
9949 | ||
0d7f9025 ILT |
9950 | /* This is called to see whether a reloc against a defined symbol |
9951 | should be converted into a reloc against a section. Don't adjust | |
9952 | MIPS16 jump relocations, so we don't have to worry about the format | |
9953 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
9954 | mips16 symbols, so that the linker can find them if it needs to set |
9955 | up a stub. */ | |
0d7f9025 ILT |
9956 | |
9957 | int | |
9958 | mips_fix_adjustable (fixp) | |
9959 | fixS *fixp; | |
9960 | { | |
9961 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
9962 | return 0; | |
9963 | if (fixp->fx_addsy == NULL) | |
9964 | return 1; | |
0d7f9025 ILT |
9965 | #ifdef S_GET_OTHER |
9966 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9967 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16) | |
9968 | return 0; | |
9969 | #endif | |
9970 | return 1; | |
9971 | } | |
9972 | ||
0dd2d296 ILT |
9973 | /* Translate internal representation of relocation info to BFD target |
9974 | format. */ | |
9975 | ||
9976 | arelent ** | |
3d3c5039 ILT |
9977 | tc_gen_reloc (section, fixp) |
9978 | asection *section; | |
9979 | fixS *fixp; | |
9980 | { | |
0dd2d296 | 9981 | static arelent *retval[4]; |
3d3c5039 | 9982 | arelent *reloc; |
a8aed9dd | 9983 | bfd_reloc_code_real_type code; |
3d3c5039 | 9984 | |
0dd2d296 ILT |
9985 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9986 | retval[1] = NULL; | |
3d3c5039 ILT |
9987 | |
9988 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9989 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9990 | |
9991 | if (mips_pic == EMBEDDED_PIC | |
9992 | && SWITCH_TABLE (fixp)) | |
9993 | { | |
9994 | /* For a switch table entry we use a special reloc. The addend | |
9995 | is actually the difference between the reloc address and the | |
9996 | subtrahend. */ | |
9997 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9998 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9999 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10000 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10001 | } | |
ecd4ca1c ILT |
10002 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10003 | { | |
10004 | /* We use a special addend for an internal RELLO reloc. */ | |
10005 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10006 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10007 | else | |
10008 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10009 | } | |
10010 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10011 | { | |
10012 | assert (fixp->fx_next != NULL | |
10013 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10014 | /* We use a special addend for an internal RELHI reloc. The | |
10015 | reloc is relative to the RELLO; adjust the addend | |
10016 | accordingly. */ | |
10017 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10018 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10019 | + fixp->fx_next->fx_where | |
10020 | - S_GET_VALUE (fixp->fx_subsy)); | |
10021 | else | |
10022 | reloc->addend = (fixp->fx_addnumber | |
10023 | + fixp->fx_next->fx_frag->fr_address | |
10024 | + fixp->fx_next->fx_where); | |
10025 | } | |
1c803e52 | 10026 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10027 | reloc->addend = fixp->fx_addnumber; |
10028 | else | |
5b63f465 | 10029 | { |
1dc1e798 KR |
10030 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10031 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10032 | handling. */ | |
10033 | reloc->addend = reloc->address; | |
10034 | else | |
10035 | reloc->addend = -reloc->address; | |
5b63f465 | 10036 | } |
0dd2d296 ILT |
10037 | |
10038 | /* If this is a variant frag, we may need to adjust the existing | |
10039 | reloc and generate a new one. */ | |
10040 | if (fixp->fx_frag->fr_opcode != NULL | |
10041 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10042 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10043 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10044 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10045 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10046 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10047 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10048 | { |
10049 | arelent *reloc2; | |
10050 | ||
cc5703cd ILT |
10051 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10052 | ||
0dd2d296 | 10053 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10054 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10055 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10056 | the second one handle all of them. */ | |
0dd2d296 ILT |
10057 | if (fixp->fx_next != NULL |
10058 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10059 | { | |
fb251650 ILT |
10060 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10061 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10062 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10063 | && (fixp->fx_next->fx_r_type | |
10064 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10065 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10066 | && (fixp->fx_next->fx_r_type | |
10067 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10068 | retval[0] = NULL; |
10069 | return retval; | |
10070 | } | |
10071 | ||
10072 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10073 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10074 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10075 | retval[2] = NULL; | |
10076 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10077 | reloc2->address = (reloc->address | |
10078 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10079 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10080 | reloc2->addend = fixp->fx_addnumber; | |
10081 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10082 | assert (reloc2->howto != NULL); | |
10083 | ||
10084 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10085 | { | |
10086 | arelent *reloc3; | |
10087 | ||
10088 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10089 | retval[3] = NULL; | |
10090 | *reloc3 = *reloc2; | |
10091 | reloc3->address += 4; | |
10092 | } | |
10093 | ||
d9aba805 | 10094 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10095 | { |
10096 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10097 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10098 | } | |
d9aba805 | 10099 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10100 | { |
fb251650 | 10101 | switch (fixp->fx_r_type) |
0dd2d296 | 10102 | { |
fb251650 ILT |
10103 | default: |
10104 | abort (); | |
10105 | case BFD_RELOC_MIPS_GOT16: | |
10106 | break; | |
10107 | case BFD_RELOC_MIPS_CALL16: | |
10108 | case BFD_RELOC_MIPS_GOT_LO16: | |
10109 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10110 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10111 | break; |
0dd2d296 ILT |
10112 | } |
10113 | } | |
d9aba805 ILT |
10114 | else |
10115 | abort (); | |
0dd2d296 ILT |
10116 | } |
10117 | ||
a8aed9dd ILT |
10118 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10119 | fixup_segment converted a non-PC relative reloc into a PC | |
10120 | relative reloc. In such a case, we need to convert the reloc | |
10121 | code. */ | |
10122 | code = fixp->fx_r_type; | |
10123 | if (fixp->fx_pcrel) | |
10124 | { | |
10125 | switch (code) | |
10126 | { | |
10127 | case BFD_RELOC_8: | |
10128 | code = BFD_RELOC_8_PCREL; | |
10129 | break; | |
10130 | case BFD_RELOC_16: | |
10131 | code = BFD_RELOC_16_PCREL; | |
10132 | break; | |
10133 | case BFD_RELOC_32: | |
10134 | code = BFD_RELOC_32_PCREL; | |
10135 | break; | |
bf39474f ILT |
10136 | case BFD_RELOC_64: |
10137 | code = BFD_RELOC_64_PCREL; | |
10138 | break; | |
a8aed9dd ILT |
10139 | case BFD_RELOC_8_PCREL: |
10140 | case BFD_RELOC_16_PCREL: | |
10141 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10142 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10143 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10144 | case BFD_RELOC_PCREL_HI16_S: |
10145 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10146 | break; |
10147 | default: | |
10148 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10149 | "Cannot make %s relocation PC relative", | |
10150 | bfd_get_reloc_code_name (code)); | |
10151 | } | |
10152 | } | |
10153 | ||
d9aba805 ILT |
10154 | /* To support a PC relative reloc when generating embedded PIC code |
10155 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10156 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10157 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10158 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10159 | && mips_pic != EMBEDDED_PIC) |
10160 | reloc->howto = NULL; | |
10161 | else | |
a8aed9dd | 10162 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10163 | |
52aa70b5 JW |
10164 | if (reloc->howto == NULL) |
10165 | { | |
10166 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10167 | "Can not represent %s relocation in this object file format", |
10168 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10169 | retval[0] = NULL; |
52aa70b5 | 10170 | } |
3d3c5039 | 10171 | |
0dd2d296 | 10172 | return retval; |
3d3c5039 ILT |
10173 | } |
10174 | ||
cc5703cd ILT |
10175 | /* Relax a machine dependent frag. This returns the amount by which |
10176 | the current size of the frag should change. */ | |
10177 | ||
10178 | int | |
10179 | mips_relax_frag (fragp, stretch) | |
10180 | fragS *fragp; | |
10181 | long stretch; | |
10182 | { | |
10183 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10184 | return 0; | |
10185 | ||
10186 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10187 | { | |
10188 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10189 | return 0; | |
10190 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10191 | return 2; | |
10192 | } | |
10193 | else | |
10194 | { | |
10195 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10196 | return 0; | |
10197 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10198 | return -2; | |
10199 | } | |
10200 | ||
10201 | return 0; | |
10202 | } | |
10203 | ||
0dd2d296 ILT |
10204 | /* Convert a machine dependent frag. */ |
10205 | ||
10206 | void | |
10207 | md_convert_frag (abfd, asec, fragp) | |
10208 | bfd *abfd; | |
10209 | segT asec; | |
10210 | fragS *fragp; | |
3d3c5039 | 10211 | { |
0dd2d296 ILT |
10212 | int old, new; |
10213 | char *fixptr; | |
3d3c5039 | 10214 | |
cc5703cd ILT |
10215 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10216 | { | |
10217 | int type; | |
10218 | register const struct mips16_immed_operand *op; | |
10219 | boolean small, ext; | |
10220 | offsetT val; | |
10221 | bfd_byte *buf; | |
10222 | unsigned long insn; | |
10223 | boolean use_extend; | |
10224 | unsigned short extend; | |
10225 | ||
10226 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10227 | op = mips16_immed_operands; | |
10228 | while (op->type != type) | |
10229 | ++op; | |
10230 | ||
10231 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10232 | { | |
10233 | small = false; | |
10234 | ext = true; | |
10235 | } | |
10236 | else | |
10237 | { | |
10238 | small = true; | |
10239 | ext = false; | |
10240 | } | |
10241 | ||
f74ba7a3 | 10242 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 10243 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10244 | if (op->pcrel) |
10245 | { | |
10246 | addressT addr; | |
10247 | ||
a677feeb ILT |
10248 | addr = fragp->fr_address + fragp->fr_fix; |
10249 | ||
10250 | /* The rules for the base address of a PC relative reloc are | |
10251 | complicated; see mips16_extended_frag. */ | |
10252 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10253 | { |
10254 | addr += 2; | |
319305a7 ILT |
10255 | if (ext) |
10256 | addr += 2; | |
fbcfacb7 ILT |
10257 | /* Ignore the low bit in the target, since it will be |
10258 | set for a text label. */ | |
10259 | if ((val & 1) != 0) | |
10260 | --val; | |
10261 | } | |
a677feeb ILT |
10262 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10263 | addr -= 4; | |
10264 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10265 | addr -= 2; | |
10266 | ||
cc5703cd ILT |
10267 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10268 | val -= addr; | |
a677feeb ILT |
10269 | |
10270 | /* Make sure the section winds up with the alignment we have | |
10271 | assumed. */ | |
10272 | if (op->shift > 0) | |
10273 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10274 | } |
10275 | ||
035936da ILT |
10276 | if (ext |
10277 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10278 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10279 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10280 | "extended instruction in delay slot"); | |
10281 | ||
cc5703cd ILT |
10282 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10283 | ||
b9129c6f ILT |
10284 | if (target_big_endian) |
10285 | insn = bfd_getb16 (buf); | |
10286 | else | |
10287 | insn = bfd_getl16 (buf); | |
cc5703cd | 10288 | |
31a2c6ff ILT |
10289 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10290 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10291 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10292 | |
10293 | if (use_extend) | |
10294 | { | |
10295 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10296 | fragp->fr_fix += 2; | |
10297 | buf += 2; | |
10298 | } | |
3d3c5039 | 10299 | |
cc5703cd ILT |
10300 | md_number_to_chars (buf, insn, 2); |
10301 | fragp->fr_fix += 2; | |
10302 | buf += 2; | |
10303 | } | |
10304 | else | |
10305 | { | |
10306 | if (fragp->fr_opcode == NULL) | |
10307 | return; | |
0dd2d296 | 10308 | |
cc5703cd ILT |
10309 | old = RELAX_OLD (fragp->fr_subtype); |
10310 | new = RELAX_NEW (fragp->fr_subtype); | |
10311 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10312 | |
cc5703cd ILT |
10313 | if (new > 0) |
10314 | memcpy (fixptr - old, fixptr, new); | |
10315 | ||
10316 | fragp->fr_fix += new - old; | |
10317 | } | |
0dd2d296 | 10318 | } |
becfe05e | 10319 | |
fbcfacb7 ILT |
10320 | #ifdef OBJ_ELF |
10321 | ||
10322 | /* This function is called after the relocs have been generated. | |
10323 | We've been storing mips16 text labels as odd. Here we convert them | |
10324 | back to even for the convenience of the debugger. */ | |
10325 | ||
10326 | void | |
10327 | mips_frob_file_after_relocs () | |
10328 | { | |
10329 | asymbol **syms; | |
10330 | unsigned int count, i; | |
10331 | ||
10332 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10333 | return; | |
10334 | ||
10335 | syms = bfd_get_outsymbols (stdoutput); | |
10336 | count = bfd_get_symcount (stdoutput); | |
10337 | for (i = 0; i < count; i++, syms++) | |
10338 | { | |
10339 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10340 | && ((*syms)->value & 1) != 0) | |
10341 | { | |
10342 | (*syms)->value &= ~1; | |
10343 | /* If the symbol has an odd size, it was probably computed | |
10344 | incorrectly, so adjust that as well. */ | |
10345 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10346 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10347 | } | |
10348 | } | |
10349 | } | |
10350 | ||
10351 | #endif | |
10352 | ||
becfe05e ILT |
10353 | /* This function is called whenever a label is defined. It is used |
10354 | when handling branch delays; if a branch has a label, we assume we | |
10355 | can not move it. */ | |
10356 | ||
10357 | void | |
10358 | mips_define_label (sym) | |
10359 | symbolS *sym; | |
10360 | { | |
fbcfacb7 ILT |
10361 | struct insn_label_list *l; |
10362 | ||
10363 | if (free_insn_labels == NULL) | |
10364 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10365 | else | |
10366 | { | |
10367 | l = free_insn_labels; | |
10368 | free_insn_labels = l->next; | |
10369 | } | |
10370 | ||
10371 | l->label = sym; | |
10372 | l->next = insn_labels; | |
10373 | insn_labels = l; | |
becfe05e | 10374 | } |
3d3c5039 | 10375 | \f |
739708fa | 10376 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10377 | |
0dd2d296 | 10378 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10379 | |
10380 | void | |
10381 | mips_elf_final_processing () | |
10382 | { | |
87178180 ILT |
10383 | /* Write out the register information. */ |
10384 | if (! mips_64) | |
10385 | { | |
10386 | Elf32_RegInfo s; | |
10387 | ||
10388 | s.ri_gprmask = mips_gprmask; | |
10389 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10390 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10391 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10392 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10393 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10394 | ||
10395 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10396 | ((Elf32_External_RegInfo *) | |
10397 | mips_regmask_frag)); | |
10398 | } | |
10399 | else | |
10400 | { | |
10401 | Elf64_Internal_RegInfo s; | |
10402 | ||
10403 | s.ri_gprmask = mips_gprmask; | |
10404 | s.ri_pad = 0; | |
10405 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10406 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10407 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10408 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10409 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10410 | ||
10411 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10412 | ((Elf64_External_RegInfo *) | |
10413 | mips_regmask_frag)); | |
10414 | } | |
0dd2d296 ILT |
10415 | |
10416 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10417 | sort of BFD interface for this. */ | |
10418 | if (mips_any_noreorder) | |
10419 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10420 | if (mips_pic != NO_PIC) |
0dd2d296 | 10421 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10422 | } |
10423 | ||
739708fa | 10424 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10425 | \f |
3d3c5039 ILT |
10426 | /* These functions should really be defined by the object file format, |
10427 | since they are related to debugging information. However, this | |
10428 | code has to work for the a.out format, which does not define them, | |
10429 | so we provide simple versions here. These don't actually generate | |
10430 | any debugging information, but they do simple checking and someday | |
10431 | somebody may make them useful. */ | |
10432 | ||
670a50eb ILT |
10433 | typedef struct loc |
10434 | { | |
10435 | struct loc *loc_next; | |
10436 | unsigned long loc_fileno; | |
10437 | unsigned long loc_lineno; | |
10438 | unsigned long loc_offset; | |
10439 | unsigned short loc_delta; | |
10440 | unsigned short loc_count; | |
3d3c5039 | 10441 | #if 0 |
670a50eb | 10442 | fragS *loc_frag; |
3d3c5039 | 10443 | #endif |
670a50eb ILT |
10444 | } |
10445 | locS; | |
3d3c5039 | 10446 | |
670a50eb ILT |
10447 | typedef struct proc |
10448 | { | |
3d3c5039 ILT |
10449 | struct proc *proc_next; |
10450 | struct symbol *proc_isym; | |
10451 | struct symbol *proc_end; | |
10452 | unsigned long proc_reg_mask; | |
10453 | unsigned long proc_reg_offset; | |
10454 | unsigned long proc_fpreg_mask; | |
10455 | unsigned long proc_fpreg_offset; | |
10456 | unsigned long proc_frameoffset; | |
10457 | unsigned long proc_framereg; | |
10458 | unsigned long proc_pcreg; | |
10459 | locS *proc_iline; | |
10460 | struct file *proc_file; | |
10461 | int proc_index; | |
670a50eb ILT |
10462 | } |
10463 | procS; | |
3d3c5039 | 10464 | |
670a50eb ILT |
10465 | typedef struct file |
10466 | { | |
3d3c5039 ILT |
10467 | struct file *file_next; |
10468 | unsigned long file_fileno; | |
10469 | struct symbol *file_symbol; | |
10470 | struct symbol *file_end; | |
10471 | struct proc *file_proc; | |
10472 | int file_numprocs; | |
670a50eb ILT |
10473 | } |
10474 | fileS; | |
3d3c5039 ILT |
10475 | |
10476 | static struct obstack proc_frags; | |
10477 | static procS *proc_lastP; | |
10478 | static procS *proc_rootP; | |
10479 | static int numprocs; | |
10480 | ||
10481 | static void | |
10482 | md_obj_begin () | |
10483 | { | |
670a50eb | 10484 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10485 | } |
10486 | ||
10487 | static void | |
10488 | md_obj_end () | |
10489 | { | |
10490 | /* check for premature end, nesting errors, etc */ | |
10491 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10492 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10493 | } |
10494 | ||
3d3c5039 ILT |
10495 | static long |
10496 | get_number () | |
10497 | { | |
670a50eb ILT |
10498 | int negative = 0; |
10499 | long val = 0; | |
3d3c5039 | 10500 | |
670a50eb ILT |
10501 | if (*input_line_pointer == '-') |
10502 | { | |
10503 | ++input_line_pointer; | |
10504 | negative = 1; | |
3d3c5039 | 10505 | } |
670a50eb ILT |
10506 | if (!isdigit (*input_line_pointer)) |
10507 | as_bad ("Expected simple number."); | |
10508 | if (input_line_pointer[0] == '0') | |
10509 | { | |
10510 | if (input_line_pointer[1] == 'x') | |
10511 | { | |
10512 | input_line_pointer += 2; | |
10513 | while (isxdigit (*input_line_pointer)) | |
10514 | { | |
10515 | val <<= 4; | |
3a762a0b | 10516 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10517 | } |
670a50eb ILT |
10518 | return negative ? -val : val; |
10519 | } | |
10520 | else | |
10521 | { | |
10522 | ++input_line_pointer; | |
10523 | while (isdigit (*input_line_pointer)) | |
10524 | { | |
10525 | val <<= 3; | |
10526 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10527 | } |
670a50eb | 10528 | return negative ? -val : val; |
3d3c5039 ILT |
10529 | } |
10530 | } | |
670a50eb ILT |
10531 | if (!isdigit (*input_line_pointer)) |
10532 | { | |
10533 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10534 | *input_line_pointer, *input_line_pointer); | |
10535 | as_warn ("Invalid number"); | |
10536 | return -1; | |
3d3c5039 | 10537 | } |
670a50eb ILT |
10538 | while (isdigit (*input_line_pointer)) |
10539 | { | |
10540 | val *= 10; | |
10541 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10542 | } |
670a50eb | 10543 | return negative ? -val : val; |
3d3c5039 ILT |
10544 | } |
10545 | ||
10546 | /* The .file directive; just like the usual .file directive, but there | |
10547 | is an initial number which is the ECOFF file index. */ | |
10548 | ||
10549 | static void | |
10550 | s_file (x) | |
10551 | int x; | |
10552 | { | |
670a50eb | 10553 | int line; |
3d3c5039 | 10554 | |
670a50eb | 10555 | line = get_number (); |
9a7d824a | 10556 | s_app_file (0); |
3d3c5039 ILT |
10557 | } |
10558 | ||
10559 | ||
10560 | /* The .end directive. */ | |
10561 | ||
10562 | static void | |
10563 | s_mipsend (x) | |
10564 | int x; | |
10565 | { | |
670a50eb ILT |
10566 | symbolS *p; |
10567 | ||
10568 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10569 | { | |
10570 | p = get_symbol (); | |
10571 | demand_empty_rest_of_line (); | |
10572 | } | |
10573 | else | |
10574 | p = NULL; | |
10575 | if (now_seg != text_section) | |
10576 | as_warn (".end not in text section"); | |
10577 | if (!proc_lastP) | |
10578 | { | |
10579 | as_warn (".end and no .ent seen yet."); | |
10580 | return; | |
3d3c5039 ILT |
10581 | } |
10582 | ||
670a50eb ILT |
10583 | if (p != NULL) |
10584 | { | |
10585 | assert (S_GET_NAME (p)); | |
10586 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10587 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10588 | } |
10589 | ||
670a50eb | 10590 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10591 | } |
10592 | ||
10593 | /* The .aent and .ent directives. */ | |
10594 | ||
10595 | static void | |
10596 | s_ent (aent) | |
10597 | int aent; | |
10598 | { | |
670a50eb ILT |
10599 | int number = 0; |
10600 | procS *procP; | |
10601 | symbolS *symbolP; | |
10602 | ||
10603 | symbolP = get_symbol (); | |
10604 | if (*input_line_pointer == ',') | |
10605 | input_line_pointer++; | |
dd3f1f76 | 10606 | SKIP_WHITESPACE (); |
670a50eb ILT |
10607 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10608 | number = get_number (); | |
10609 | if (now_seg != text_section) | |
10610 | as_warn (".ent or .aent not in text section."); | |
10611 | ||
10612 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10613 | as_warn ("missing `.end'"); | |
10614 | ||
10615 | if (!aent) | |
10616 | { | |
10617 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10618 | procP->proc_isym = symbolP; | |
10619 | procP->proc_reg_mask = 0; | |
10620 | procP->proc_reg_offset = 0; | |
10621 | procP->proc_fpreg_mask = 0; | |
10622 | procP->proc_fpreg_offset = 0; | |
10623 | procP->proc_frameoffset = 0; | |
10624 | procP->proc_framereg = 0; | |
10625 | procP->proc_pcreg = 0; | |
10626 | procP->proc_end = NULL; | |
10627 | procP->proc_next = NULL; | |
10628 | if (proc_lastP) | |
10629 | proc_lastP->proc_next = procP; | |
10630 | else | |
10631 | proc_rootP = procP; | |
10632 | proc_lastP = procP; | |
10633 | numprocs++; | |
3d3c5039 | 10634 | } |
670a50eb | 10635 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10636 | } |
10637 | ||
10638 | /* The .frame directive. */ | |
10639 | ||
88225433 | 10640 | #if 0 |
3d3c5039 ILT |
10641 | static void |
10642 | s_frame (x) | |
670a50eb | 10643 | int x; |
3d3c5039 | 10644 | { |
670a50eb ILT |
10645 | char str[100]; |
10646 | symbolS *symP; | |
10647 | int frame_reg; | |
10648 | int frame_off; | |
10649 | int pcreg; | |
10650 | ||
0dd2d296 | 10651 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10652 | if (*input_line_pointer == ',') |
10653 | input_line_pointer++; | |
5ac34ac3 | 10654 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10655 | if (*input_line_pointer == ',') |
10656 | input_line_pointer++; | |
0dd2d296 | 10657 | pcreg = tc_get_register (0); |
670a50eb ILT |
10658 | |
10659 | /* bob third eye */ | |
10660 | assert (proc_rootP); | |
10661 | proc_rootP->proc_framereg = frame_reg; | |
10662 | proc_rootP->proc_frameoffset = frame_off; | |
10663 | proc_rootP->proc_pcreg = pcreg; | |
10664 | /* bob macho .frame */ | |
10665 | ||
10666 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10667 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10668 | { |
10669 | if (!proc_lastP) | |
10670 | as_warn ("No .ent for .frame to use."); | |
10671 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10672 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10673 | S_SET_TYPE (symP, N_RMASK); | |
10674 | S_SET_OTHER (symP, 0); | |
10675 | S_SET_DESC (symP, 0); | |
10676 | symP->sy_forward = proc_lastP->proc_isym; | |
10677 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10678 | } |
670a50eb | 10679 | demand_empty_rest_of_line (); |
3d3c5039 | 10680 | } |
88225433 | 10681 | #endif |
3d3c5039 ILT |
10682 | |
10683 | /* The .fmask and .mask directives. */ | |
10684 | ||
88225433 | 10685 | #if 0 |
3d3c5039 ILT |
10686 | static void |
10687 | s_mask (reg_type) | |
10688 | char reg_type; | |
10689 | { | |
670a50eb ILT |
10690 | char str[100], *strP; |
10691 | symbolS *symP; | |
10692 | int i; | |
10693 | unsigned int mask; | |
10694 | int off; | |
10695 | ||
10696 | mask = get_number (); | |
10697 | if (*input_line_pointer == ',') | |
10698 | input_line_pointer++; | |
10699 | off = get_absolute_expression (); | |
10700 | ||
10701 | /* bob only for coff */ | |
10702 | assert (proc_rootP); | |
10703 | if (reg_type == 'F') | |
10704 | { | |
10705 | proc_rootP->proc_fpreg_mask = mask; | |
10706 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10707 | } |
670a50eb ILT |
10708 | else |
10709 | { | |
10710 | proc_rootP->proc_reg_mask = mask; | |
10711 | proc_rootP->proc_reg_offset = off; | |
10712 | } | |
10713 | ||
10714 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10715 | |
670a50eb ILT |
10716 | /* We don't have to write out a mask stab if no saved regs. */ |
10717 | if (!(mask == 0)) | |
10718 | { | |
10719 | if (!proc_lastP) | |
10720 | as_warn ("No .ent for .mask to use."); | |
10721 | strP = str; | |
10722 | for (i = 0; i < 32; i++) | |
10723 | { | |
10724 | if (mask % 2) | |
10725 | { | |
10726 | sprintf (strP, "%c%d,", reg_type, i); | |
10727 | strP += strlen (strP); | |
10728 | } | |
3d3c5039 | 10729 | mask /= 2; |
670a50eb ILT |
10730 | } |
10731 | sprintf (strP, ";%d,", off); | |
10732 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10733 | S_SET_TYPE (symP, N_RMASK); | |
10734 | S_SET_OTHER (symP, 0); | |
10735 | S_SET_DESC (symP, 0); | |
10736 | symP->sy_forward = proc_lastP->proc_isym; | |
10737 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10738 | } |
3d3c5039 | 10739 | } |
88225433 | 10740 | #endif |
3d3c5039 ILT |
10741 | |
10742 | /* The .loc directive. */ | |
10743 | ||
88225433 | 10744 | #if 0 |
3d3c5039 ILT |
10745 | static void |
10746 | s_loc (x) | |
10747 | int x; | |
10748 | { | |
670a50eb ILT |
10749 | symbolS *symbolP; |
10750 | int lineno; | |
10751 | int addroff; | |
3d3c5039 | 10752 | |
670a50eb | 10753 | assert (now_seg == text_section); |
3d3c5039 | 10754 | |
670a50eb | 10755 | lineno = get_number (); |
87e48495 | 10756 | addroff = frag_now_fix (); |
3d3c5039 | 10757 | |
670a50eb ILT |
10758 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10759 | S_SET_TYPE (symbolP, N_SLINE); | |
10760 | S_SET_OTHER (symbolP, 0); | |
10761 | S_SET_DESC (symbolP, lineno); | |
10762 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10763 | } |
88225433 | 10764 | #endif |