Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
071742cf | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 RH |
113 | /* The name of the readonly data section. */ |
114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
115 | ? ".data" \ | |
116 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
117 | ? ".rdata" \ | |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a325df1d TS |
124 | /* The ABI to use. */ |
125 | enum mips_abi_level | |
126 | { | |
127 | NO_ABI = 0, | |
128 | O32_ABI, | |
129 | O64_ABI, | |
130 | N32_ABI, | |
131 | N64_ABI, | |
132 | EABI_ABI | |
133 | }; | |
134 | ||
135 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 136 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 137 | |
143d77c5 EC |
138 | /* Whether or not we have code that can call pic code. */ |
139 | int mips_abicalls = FALSE; | |
140 | ||
252b5132 RH |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
e972090a NC |
145 | struct mips_set_options |
146 | { | |
252b5132 RH |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
1f25f5d3 CD |
151 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
152 | if they have not been initialized. Changed by `.set <asename>', by | |
153 | command line options, and based on the default architecture. */ | |
154 | int ase_mips3d; | |
deec1734 | 155 | int ase_mdmx; |
252b5132 RH |
156 | /* Whether we are assembling for the mips16 processor. 0 if we are |
157 | not, 1 if we are, and -1 if the value has not been initialized. | |
158 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
159 | -nomips16 command line options, and the default CPU. */ | |
160 | int mips16; | |
161 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
162 | reorder' and `.set noreorder'. */ | |
163 | int noreorder; | |
164 | /* Non-zero if we should not permit the $at ($1) register to be used | |
165 | in instructions. Changed by `.set at' and `.set noat'. */ | |
166 | int noat; | |
167 | /* Non-zero if we should warn when a macro instruction expands into | |
168 | more than one machine instruction. Changed by `.set nomacro' and | |
169 | `.set macro'. */ | |
170 | int warn_about_macros; | |
171 | /* Non-zero if we should not move instructions. Changed by `.set | |
172 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
173 | int nomove; | |
174 | /* Non-zero if we should not optimize branches by moving the target | |
175 | of the branch into the delay slot. Actually, we don't perform | |
176 | this optimization anyhow. Changed by `.set bopt' and `.set | |
177 | nobopt'. */ | |
178 | int nobopt; | |
179 | /* Non-zero if we should not autoextend mips16 instructions. | |
180 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
181 | int noautoextend; | |
a325df1d TS |
182 | /* Restrict general purpose registers and floating point registers |
183 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
184 | is passed but can changed if the assembler code uses .set mipsN. */ | |
185 | int gp32; | |
186 | int fp32; | |
fef14a42 TS |
187 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
188 | command line option, and the default CPU. */ | |
189 | int arch; | |
252b5132 RH |
190 | }; |
191 | ||
a325df1d | 192 | /* True if -mgp32 was passed. */ |
a8e8e863 | 193 | static int file_mips_gp32 = -1; |
a325df1d TS |
194 | |
195 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 196 | static int file_mips_fp32 = -1; |
a325df1d | 197 | |
252b5132 | 198 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 199 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 200 | -1 to indicate that they have not been initialized. */ |
252b5132 | 201 | |
e972090a NC |
202 | static struct mips_set_options mips_opts = |
203 | { | |
fef14a42 | 204 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 205 | }; |
252b5132 RH |
206 | |
207 | /* These variables are filled in with the masks of registers used. | |
208 | The object format code reads them and puts them in the appropriate | |
209 | place. */ | |
210 | unsigned long mips_gprmask; | |
211 | unsigned long mips_cprmask[4]; | |
212 | ||
213 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 214 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 215 | |
a4672219 TS |
216 | /* True if -mips16 was passed or implied by arguments passed on the |
217 | command line (e.g., by -march). */ | |
218 | static int file_ase_mips16; | |
219 | ||
1f25f5d3 CD |
220 | /* True if -mips3d was passed or implied by arguments passed on the |
221 | command line (e.g., by -march). */ | |
222 | static int file_ase_mips3d; | |
223 | ||
deec1734 CD |
224 | /* True if -mdmx was passed or implied by arguments passed on the |
225 | command line (e.g., by -march). */ | |
226 | static int file_ase_mdmx; | |
227 | ||
ec68c924 | 228 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 229 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 230 | static const char *mips_arch_string; |
ec68c924 EC |
231 | |
232 | /* The argument of the -mtune= flag. The architecture for which we | |
233 | are optimizing. */ | |
234 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 235 | static const char *mips_tune_string; |
ec68c924 | 236 | |
316f5878 | 237 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
238 | static int mips_32bitmode = 0; |
239 | ||
9ce8a5dd GRK |
240 | /* Some ISA's have delay slots for instructions which read or write |
241 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 242 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
243 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
244 | delay slot in this ISA. The uses of this macro assume that any | |
245 | ISA that has delay slots for one of these, has them for all. They | |
246 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 247 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 248 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
249 | (ISA) == ISA_MIPS1 \ |
250 | || (ISA) == ISA_MIPS2 \ | |
251 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
252 | ) |
253 | ||
316f5878 RS |
254 | /* True if the given ABI requires 32-bit registers. */ |
255 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
256 | ||
257 | /* Likewise 64-bit registers. */ | |
258 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
259 | ((ABI) == N32_ABI \ | |
260 | || (ABI) == N64_ABI \ | |
261 | || (ABI) == O64_ABI) | |
262 | ||
bdaaa2e1 | 263 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 264 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
265 | (ISA) == ISA_MIPS3 \ |
266 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 267 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 268 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
269 | ) |
270 | ||
af7ee8bf CD |
271 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
272 | instructions. */ | |
273 | #define ISA_HAS_DROR(ISA) ( \ | |
274 | 0 \ | |
275 | ) | |
276 | ||
277 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
278 | instructions. */ | |
279 | #define ISA_HAS_ROR(ISA) ( \ | |
280 | (ISA) == ISA_MIPS32R2 \ | |
281 | ) | |
282 | ||
e013f690 | 283 | #define HAVE_32BIT_GPRS \ |
316f5878 | 284 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 285 | |
e013f690 | 286 | #define HAVE_32BIT_FPRS \ |
316f5878 | 287 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
288 | |
289 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
290 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
291 | ||
316f5878 | 292 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 293 | |
316f5878 | 294 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
295 | |
296 | /* We can only have 64bit addresses if the object file format | |
297 | supports it. */ | |
afdbd6d0 CD |
298 | #define HAVE_32BIT_ADDRESSES \ |
299 | (HAVE_32BIT_GPRS \ | |
300 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
301 | || ! HAVE_64BIT_OBJECTS) \ | |
302 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
303 | |
304 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
5a7a0b7b AO |
305 | #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \ |
306 | || HAVE_64BIT_GPRS) | |
ca4e0257 | 307 | |
b7c7d6c1 TS |
308 | /* Addresses are loaded in different ways, depending on the address size |
309 | in use. The n32 ABI Documentation also mandates the use of additions | |
310 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 311 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 312 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
313 | |
314 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 315 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
316 | |
317 | #define ADDRESS_LOAD_INSN \ | |
318 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
319 | ||
320 | #define ADDRESS_STORE_INSN \ | |
321 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
322 | ||
a4672219 | 323 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
324 | #define CPU_HAS_MIPS16(cpu) \ |
325 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
326 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 327 | |
1f25f5d3 CD |
328 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
329 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
330 | ) | |
331 | ||
deec1734 | 332 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 333 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
334 | ) |
335 | ||
60b63b72 RS |
336 | /* True if CPU has a dror instruction. */ |
337 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
338 | ||
339 | /* True if CPU has a ror instruction. */ | |
340 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
341 | ||
bdaaa2e1 | 342 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 343 | reads from the HI and LO registers, and thus does not |
ec68c924 | 344 | require nops to be inserted. */ |
252b5132 | 345 | |
fef14a42 TS |
346 | #define hilo_interlocks (mips_opts.arch == CPU_R4010 \ |
347 | || mips_opts.arch == CPU_VR5500 \ | |
5a7ea749 | 348 | || mips_opts.arch == CPU_RM7000 \ |
fef14a42 | 349 | || mips_opts.arch == CPU_SB1 \ |
252b5132 RH |
350 | ) |
351 | ||
352 | /* Whether the processor uses hardware interlocks to protect reads | |
353 | from the GPRs, and thus does not require nops to be inserted. */ | |
354 | #define gpr_interlocks \ | |
e7af610e | 355 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 TS |
356 | || mips_opts.arch == CPU_VR5400 \ |
357 | || mips_opts.arch == CPU_VR5500 \ | |
358 | || mips_opts.arch == CPU_R3900) | |
252b5132 RH |
359 | |
360 | /* As with other "interlocks" this is used by hardware that has FP | |
361 | (co-processor) interlocks. */ | |
bdaaa2e1 | 362 | /* Itbl support may require additional care here. */ |
fef14a42 TS |
363 | #define cop_interlocks (mips_opts.arch == CPU_R4300 \ |
364 | || mips_opts.arch == CPU_VR5400 \ | |
365 | || mips_opts.arch == CPU_VR5500 \ | |
366 | || mips_opts.arch == CPU_SB1 \ | |
252b5132 RH |
367 | ) |
368 | ||
6b76fefe CM |
369 | /* Is this a mfhi or mflo instruction? */ |
370 | #define MF_HILO_INSN(PINFO) \ | |
371 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
372 | ||
252b5132 RH |
373 | /* MIPS PIC level. */ |
374 | ||
a161fe53 | 375 | enum mips_pic_level mips_pic; |
252b5132 | 376 | |
39c0a331 L |
377 | /* Warn about all NOPS that the assembler generates. */ |
378 | static int warn_nops = 0; | |
379 | ||
c9914766 | 380 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 381 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 382 | static int mips_big_got = 0; |
252b5132 RH |
383 | |
384 | /* 1 if trap instructions should used for overflow rather than break | |
385 | instructions. */ | |
c9914766 | 386 | static int mips_trap = 0; |
252b5132 | 387 | |
119d663a | 388 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 389 | by assembling two single width halves into two single width floating |
119d663a NC |
390 | point registers which just happen to alias the double width destination |
391 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 392 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
393 | automatically at assemble time. */ |
394 | static int mips_disable_float_construction; | |
395 | ||
252b5132 RH |
396 | /* Non-zero if any .set noreorder directives were used. */ |
397 | ||
398 | static int mips_any_noreorder; | |
399 | ||
6b76fefe CM |
400 | /* Non-zero if nops should be inserted when the register referenced in |
401 | an mfhi/mflo instruction is read in the next two instructions. */ | |
402 | static int mips_7000_hilo_fix; | |
403 | ||
252b5132 | 404 | /* The size of the small data section. */ |
156c2f8b | 405 | static unsigned int g_switch_value = 8; |
252b5132 RH |
406 | /* Whether the -G option was used. */ |
407 | static int g_switch_seen = 0; | |
408 | ||
409 | #define N_RMASK 0xc4 | |
410 | #define N_VFP 0xd4 | |
411 | ||
412 | /* If we can determine in advance that GP optimization won't be | |
413 | possible, we can skip the relaxation stuff that tries to produce | |
414 | GP-relative references. This makes delay slot optimization work | |
415 | better. | |
416 | ||
417 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
418 | gcc output. It needs to guess right for gcc, otherwise gcc |
419 | will put what it thinks is a GP-relative instruction in a branch | |
420 | delay slot. | |
252b5132 RH |
421 | |
422 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
423 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 424 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
425 | |
426 | /* handle of the OPCODE hash table */ | |
427 | static struct hash_control *op_hash = NULL; | |
428 | ||
429 | /* The opcode hash table we use for the mips16. */ | |
430 | static struct hash_control *mips16_op_hash = NULL; | |
431 | ||
432 | /* This array holds the chars that always start a comment. If the | |
433 | pre-processor is disabled, these aren't very useful */ | |
434 | const char comment_chars[] = "#"; | |
435 | ||
436 | /* This array holds the chars that only start a comment at the beginning of | |
437 | a line. If the line seems to have the form '# 123 filename' | |
438 | .line and .file directives will appear in the pre-processed output */ | |
439 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
440 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 441 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
442 | /* Also note that C style comments are always supported. */ |
443 | const char line_comment_chars[] = "#"; | |
444 | ||
bdaaa2e1 | 445 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 446 | const char line_separator_chars[] = ";"; |
252b5132 RH |
447 | |
448 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
449 | const char EXP_CHARS[] = "eE"; | |
450 | ||
451 | /* Chars that mean this number is a floating point constant */ | |
452 | /* As in 0f12.456 */ | |
453 | /* or 0d1.2345e12 */ | |
454 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
455 | ||
456 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
457 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
458 | but nothing is ideal around here. | |
459 | */ | |
460 | ||
461 | static char *insn_error; | |
462 | ||
463 | static int auto_align = 1; | |
464 | ||
465 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
466 | offset in the stack frame from which to restore the $gp register. | |
467 | This is set by the .cprestore pseudo-op, and saved in this | |
468 | variable. */ | |
469 | static offsetT mips_cprestore_offset = -1; | |
470 | ||
6478892d TS |
471 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
472 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 473 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
474 | static offsetT mips_cpreturn_offset = -1; |
475 | static int mips_cpreturn_register = -1; | |
476 | static int mips_gp_register = GP; | |
def2e0dd | 477 | static int mips_gprel_offset = 0; |
6478892d | 478 | |
7a621144 DJ |
479 | /* Whether mips_cprestore_offset has been set in the current function |
480 | (or whether it has already been warned about, if not). */ | |
481 | static int mips_cprestore_valid = 0; | |
482 | ||
252b5132 RH |
483 | /* This is the register which holds the stack frame, as set by the |
484 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
485 | static int mips_frame_reg = SP; | |
486 | ||
7a621144 DJ |
487 | /* Whether mips_frame_reg has been set in the current function |
488 | (or whether it has already been warned about, if not). */ | |
489 | static int mips_frame_reg_valid = 0; | |
490 | ||
252b5132 RH |
491 | /* To output NOP instructions correctly, we need to keep information |
492 | about the previous two instructions. */ | |
493 | ||
494 | /* Whether we are optimizing. The default value of 2 means to remove | |
495 | unneeded NOPs and swap branch instructions when possible. A value | |
496 | of 1 means to not swap branches. A value of 0 means to always | |
497 | insert NOPs. */ | |
498 | static int mips_optimize = 2; | |
499 | ||
500 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
501 | equivalent to seeing no -g option at all. */ | |
502 | static int mips_debug = 0; | |
503 | ||
504 | /* The previous instruction. */ | |
505 | static struct mips_cl_insn prev_insn; | |
506 | ||
507 | /* The instruction before prev_insn. */ | |
508 | static struct mips_cl_insn prev_prev_insn; | |
509 | ||
510 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
511 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 512 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
513 | |
514 | /* Non-zero if prev_insn is valid. */ | |
515 | static int prev_insn_valid; | |
516 | ||
517 | /* The frag for the previous instruction. */ | |
518 | static struct frag *prev_insn_frag; | |
519 | ||
520 | /* The offset into prev_insn_frag for the previous instruction. */ | |
521 | static long prev_insn_where; | |
522 | ||
523 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 524 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
525 | |
526 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 527 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
528 | |
529 | /* Non-zero if the previous instruction was in a delay slot. */ | |
530 | static int prev_insn_is_delay_slot; | |
531 | ||
532 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
533 | static int prev_insn_unreordered; | |
534 | ||
535 | /* Non-zero if the previous instruction uses an extend opcode (if | |
536 | mips16). */ | |
537 | static int prev_insn_extended; | |
538 | ||
539 | /* Non-zero if the previous previous instruction was in a .set | |
540 | noreorder. */ | |
541 | static int prev_prev_insn_unreordered; | |
542 | ||
543 | /* If this is set, it points to a frag holding nop instructions which | |
544 | were inserted before the start of a noreorder section. If those | |
545 | nops turn out to be unnecessary, the size of the frag can be | |
546 | decreased. */ | |
547 | static fragS *prev_nop_frag; | |
548 | ||
549 | /* The number of nop instructions we created in prev_nop_frag. */ | |
550 | static int prev_nop_frag_holds; | |
551 | ||
552 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 553 | prev_nop_frag. */ |
252b5132 RH |
554 | static int prev_nop_frag_required; |
555 | ||
556 | /* The number of instructions we've seen since prev_nop_frag. */ | |
557 | static int prev_nop_frag_since; | |
558 | ||
559 | /* For ECOFF and ELF, relocations against symbols are done in two | |
560 | parts, with a HI relocation and a LO relocation. Each relocation | |
561 | has only 16 bits of space to store an addend. This means that in | |
562 | order for the linker to handle carries correctly, it must be able | |
563 | to locate both the HI and the LO relocation. This means that the | |
564 | relocations must appear in order in the relocation table. | |
565 | ||
566 | In order to implement this, we keep track of each unmatched HI | |
567 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 568 | corresponding LO relocation. */ |
252b5132 | 569 | |
e972090a NC |
570 | struct mips_hi_fixup |
571 | { | |
252b5132 RH |
572 | /* Next HI fixup. */ |
573 | struct mips_hi_fixup *next; | |
574 | /* This fixup. */ | |
575 | fixS *fixp; | |
576 | /* The section this fixup is in. */ | |
577 | segT seg; | |
578 | }; | |
579 | ||
580 | /* The list of unmatched HI relocs. */ | |
581 | ||
582 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
583 | ||
64bdfcaf RS |
584 | /* The frag containing the last explicit relocation operator. |
585 | Null if explicit relocations have not been used. */ | |
586 | ||
587 | static fragS *prev_reloc_op_frag; | |
588 | ||
252b5132 RH |
589 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
590 | ||
591 | #define X ILLEGAL_REG | |
e972090a NC |
592 | static const int mips32_to_16_reg_map[] = |
593 | { | |
252b5132 RH |
594 | X, X, 2, 3, 4, 5, 6, 7, |
595 | X, X, X, X, X, X, X, X, | |
596 | 0, 1, X, X, X, X, X, X, | |
597 | X, X, X, X, X, X, X, X | |
598 | }; | |
599 | #undef X | |
600 | ||
601 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
602 | ||
e972090a NC |
603 | static const unsigned int mips16_to_32_reg_map[] = |
604 | { | |
252b5132 RH |
605 | 16, 17, 2, 3, 4, 5, 6, 7 |
606 | }; | |
60b63b72 RS |
607 | |
608 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
609 | |
610 | /* We don't relax branches by default, since this causes us to expand | |
611 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
612 | fail to compute the offset before expanding the macro to the most | |
613 | efficient expansion. */ | |
614 | ||
615 | static int mips_relax_branch; | |
252b5132 RH |
616 | \f |
617 | /* Since the MIPS does not have multiple forms of PC relative | |
618 | instructions, we do not have to do relaxing as is done on other | |
619 | platforms. However, we do have to handle GP relative addressing | |
620 | correctly, which turns out to be a similar problem. | |
621 | ||
622 | Every macro that refers to a symbol can occur in (at least) two | |
623 | forms, one with GP relative addressing and one without. For | |
624 | example, loading a global variable into a register generally uses | |
625 | a macro instruction like this: | |
626 | lw $4,i | |
627 | If i can be addressed off the GP register (this is true if it is in | |
628 | the .sbss or .sdata section, or if it is known to be smaller than | |
629 | the -G argument) this will generate the following instruction: | |
630 | lw $4,i($gp) | |
631 | This instruction will use a GPREL reloc. If i can not be addressed | |
632 | off the GP register, the following instruction sequence will be used: | |
633 | lui $at,i | |
634 | lw $4,i($at) | |
635 | In this case the first instruction will have a HI16 reloc, and the | |
636 | second reloc will have a LO16 reloc. Both relocs will be against | |
637 | the symbol i. | |
638 | ||
639 | The issue here is that we may not know whether i is GP addressable | |
640 | until after we see the instruction that uses it. Therefore, we | |
641 | want to be able to choose the final instruction sequence only at | |
642 | the end of the assembly. This is similar to the way other | |
643 | platforms choose the size of a PC relative instruction only at the | |
644 | end of assembly. | |
645 | ||
646 | When generating position independent code we do not use GP | |
647 | addressing in quite the same way, but the issue still arises as | |
648 | external symbols and local symbols must be handled differently. | |
649 | ||
650 | We handle these issues by actually generating both possible | |
651 | instruction sequences. The longer one is put in a frag_var with | |
652 | type rs_machine_dependent. We encode what to do with the frag in | |
653 | the subtype field. We encode (1) the number of existing bytes to | |
654 | replace, (2) the number of new bytes to use, (3) the offset from | |
655 | the start of the existing bytes to the first reloc we must generate | |
656 | (that is, the offset is applied from the start of the existing | |
657 | bytes after they are replaced by the new bytes, if any), (4) the | |
658 | offset from the start of the existing bytes to the second reloc, | |
659 | (5) whether a third reloc is needed (the third reloc is always four | |
660 | bytes after the second reloc), and (6) whether to warn if this | |
661 | variant is used (this is sometimes needed if .set nomacro or .set | |
662 | noat is in effect). All these numbers are reasonably small. | |
663 | ||
664 | Generating two instruction sequences must be handled carefully to | |
665 | ensure that delay slots are handled correctly. Fortunately, there | |
666 | are a limited number of cases. When the second instruction | |
667 | sequence is generated, append_insn is directed to maintain the | |
668 | existing delay slot information, so it continues to apply to any | |
669 | code after the second instruction sequence. This means that the | |
670 | second instruction sequence must not impose any requirements not | |
671 | required by the first instruction sequence. | |
672 | ||
673 | These variant frags are then handled in functions called by the | |
674 | machine independent code. md_estimate_size_before_relax returns | |
675 | the final size of the frag. md_convert_frag sets up the final form | |
676 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
677 | one if needed. */ | |
678 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
679 | ((relax_substateT) \ | |
680 | (((old) << 23) \ | |
681 | | ((new) << 16) \ | |
682 | | (((reloc1) + 64) << 9) \ | |
683 | | (((reloc2) + 64) << 2) \ | |
684 | | ((reloc3) ? (1 << 1) : 0) \ | |
685 | | ((warn) ? 1 : 0))) | |
686 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
687 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
688 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
689 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
690 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
691 | #define RELAX_WARN(i) ((i) & 1) | |
692 | ||
4a6a3df4 AO |
693 | /* Branch without likely bit. If label is out of range, we turn: |
694 | ||
695 | beq reg1, reg2, label | |
696 | delay slot | |
697 | ||
698 | into | |
699 | ||
700 | bne reg1, reg2, 0f | |
701 | nop | |
702 | j label | |
703 | 0: delay slot | |
704 | ||
705 | with the following opcode replacements: | |
706 | ||
707 | beq <-> bne | |
708 | blez <-> bgtz | |
709 | bltz <-> bgez | |
710 | bc1f <-> bc1t | |
711 | ||
712 | bltzal <-> bgezal (with jal label instead of j label) | |
713 | ||
714 | Even though keeping the delay slot instruction in the delay slot of | |
715 | the branch would be more efficient, it would be very tricky to do | |
716 | correctly, because we'd have to introduce a variable frag *after* | |
717 | the delay slot instruction, and expand that instead. Let's do it | |
718 | the easy way for now, even if the branch-not-taken case now costs | |
719 | one additional instruction. Out-of-range branches are not supposed | |
720 | to be common, anyway. | |
721 | ||
722 | Branch likely. If label is out of range, we turn: | |
723 | ||
724 | beql reg1, reg2, label | |
725 | delay slot (annulled if branch not taken) | |
726 | ||
727 | into | |
728 | ||
729 | beql reg1, reg2, 1f | |
730 | nop | |
731 | beql $0, $0, 2f | |
732 | nop | |
733 | 1: j[al] label | |
734 | delay slot (executed only if branch taken) | |
735 | 2: | |
736 | ||
737 | It would be possible to generate a shorter sequence by losing the | |
738 | likely bit, generating something like: | |
b34976b6 | 739 | |
4a6a3df4 AO |
740 | bne reg1, reg2, 0f |
741 | nop | |
742 | j[al] label | |
743 | delay slot (executed only if branch taken) | |
744 | 0: | |
745 | ||
746 | beql -> bne | |
747 | bnel -> beq | |
748 | blezl -> bgtz | |
749 | bgtzl -> blez | |
750 | bltzl -> bgez | |
751 | bgezl -> bltz | |
752 | bc1fl -> bc1t | |
753 | bc1tl -> bc1f | |
754 | ||
755 | bltzall -> bgezal (with jal label instead of j label) | |
756 | bgezall -> bltzal (ditto) | |
757 | ||
758 | ||
759 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 760 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
761 | ((relax_substateT) \ |
762 | (0xc0000000 \ | |
763 | | ((toofar) ? 1 : 0) \ | |
764 | | ((link) ? 2 : 0) \ | |
765 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 766 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 767 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
768 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
769 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
770 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 771 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 772 | |
252b5132 RH |
773 | /* For mips16 code, we use an entirely different form of relaxation. |
774 | mips16 supports two versions of most instructions which take | |
775 | immediate values: a small one which takes some small value, and a | |
776 | larger one which takes a 16 bit value. Since branches also follow | |
777 | this pattern, relaxing these values is required. | |
778 | ||
779 | We can assemble both mips16 and normal MIPS code in a single | |
780 | object. Therefore, we need to support this type of relaxation at | |
781 | the same time that we support the relaxation described above. We | |
782 | use the high bit of the subtype field to distinguish these cases. | |
783 | ||
784 | The information we store for this type of relaxation is the | |
785 | argument code found in the opcode file for this relocation, whether | |
786 | the user explicitly requested a small or extended form, and whether | |
787 | the relocation is in a jump or jal delay slot. That tells us the | |
788 | size of the value, and how it should be stored. We also store | |
789 | whether the fragment is considered to be extended or not. We also | |
790 | store whether this is known to be a branch to a different section, | |
791 | whether we have tried to relax this frag yet, and whether we have | |
792 | ever extended a PC relative fragment because of a shift count. */ | |
793 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
794 | (0x80000000 \ | |
795 | | ((type) & 0xff) \ | |
796 | | ((small) ? 0x100 : 0) \ | |
797 | | ((ext) ? 0x200 : 0) \ | |
798 | | ((dslot) ? 0x400 : 0) \ | |
799 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 800 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
801 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
802 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
803 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
804 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
805 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
806 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
807 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
808 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
809 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
810 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
811 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
812 | |
813 | /* Is the given value a sign-extended 32-bit value? */ | |
814 | #define IS_SEXT_32BIT_NUM(x) \ | |
815 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
816 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
817 | ||
818 | /* Is the given value a sign-extended 16-bit value? */ | |
819 | #define IS_SEXT_16BIT_NUM(x) \ | |
820 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
821 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
822 | ||
252b5132 RH |
823 | \f |
824 | /* Prototypes for static functions. */ | |
825 | ||
17a2f251 | 826 | #define internalError() \ |
252b5132 | 827 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
828 | |
829 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
830 | ||
b34976b6 | 831 | static void append_insn |
17a2f251 TS |
832 | (char *place, struct mips_cl_insn *ip, expressionS *p, |
833 | bfd_reloc_code_real_type *r); | |
834 | static void mips_no_prev_insn (int); | |
b34976b6 | 835 | static void mips16_macro_build |
17a2f251 TS |
836 | (char *, int *, expressionS *, const char *, const char *, va_list); |
837 | static void load_register (int *, int, expressionS *, int); | |
838 | static void macro (struct mips_cl_insn * ip); | |
839 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 840 | #ifdef LOSING_COMPILER |
17a2f251 | 841 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 842 | #endif |
17a2f251 TS |
843 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
844 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 845 | static void mips16_immed |
17a2f251 TS |
846 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
847 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 848 | static size_t my_getSmallExpression |
17a2f251 TS |
849 | (expressionS *, bfd_reloc_code_real_type *, char *); |
850 | static void my_getExpression (expressionS *, char *); | |
851 | static void s_align (int); | |
852 | static void s_change_sec (int); | |
853 | static void s_change_section (int); | |
854 | static void s_cons (int); | |
855 | static void s_float_cons (int); | |
856 | static void s_mips_globl (int); | |
857 | static void s_option (int); | |
858 | static void s_mipsset (int); | |
859 | static void s_abicalls (int); | |
860 | static void s_cpload (int); | |
861 | static void s_cpsetup (int); | |
862 | static void s_cplocal (int); | |
863 | static void s_cprestore (int); | |
864 | static void s_cpreturn (int); | |
865 | static void s_gpvalue (int); | |
866 | static void s_gpword (int); | |
867 | static void s_gpdword (int); | |
868 | static void s_cpadd (int); | |
869 | static void s_insn (int); | |
870 | static void md_obj_begin (void); | |
871 | static void md_obj_end (void); | |
872 | static void s_mips_ent (int); | |
873 | static void s_mips_end (int); | |
874 | static void s_mips_frame (int); | |
875 | static void s_mips_mask (int reg_type); | |
876 | static void s_mips_stab (int); | |
877 | static void s_mips_weakext (int); | |
878 | static void s_mips_file (int); | |
879 | static void s_mips_loc (int); | |
880 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 881 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 882 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
883 | |
884 | /* Table and functions used to map between CPU/ISA names, and | |
885 | ISA levels, and CPU numbers. */ | |
886 | ||
e972090a NC |
887 | struct mips_cpu_info |
888 | { | |
e7af610e NC |
889 | const char *name; /* CPU or ISA name. */ |
890 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
891 | int isa; /* ISA level. */ | |
892 | int cpu; /* CPU number (default CPU if ISA). */ | |
893 | }; | |
894 | ||
17a2f251 TS |
895 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
896 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
897 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
898 | \f |
899 | /* Pseudo-op table. | |
900 | ||
901 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
902 | should be defined here, but are currently unsupported: .alias, | |
903 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
904 | ||
905 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
906 | specific to the type of debugging information being generated, and | |
907 | should be defined by the object format: .aent, .begin, .bend, | |
908 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
909 | .vreg. | |
910 | ||
911 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
912 | not MIPS CPU specific, but are also not specific to the object file | |
913 | format. This file is probably the best place to define them, but | |
914 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
915 | .struct. */ | |
916 | ||
e972090a NC |
917 | static const pseudo_typeS mips_pseudo_table[] = |
918 | { | |
beae10d5 | 919 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
920 | {"option", s_option, 0}, |
921 | {"set", s_mipsset, 0}, | |
922 | {"rdata", s_change_sec, 'r'}, | |
923 | {"sdata", s_change_sec, 's'}, | |
924 | {"livereg", s_ignore, 0}, | |
925 | {"abicalls", s_abicalls, 0}, | |
926 | {"cpload", s_cpload, 0}, | |
6478892d TS |
927 | {"cpsetup", s_cpsetup, 0}, |
928 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 929 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
930 | {"cpreturn", s_cpreturn, 0}, |
931 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 932 | {"gpword", s_gpword, 0}, |
10181a0d | 933 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
934 | {"cpadd", s_cpadd, 0}, |
935 | {"insn", s_insn, 0}, | |
936 | ||
beae10d5 | 937 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
938 | chips. */ |
939 | {"asciiz", stringer, 1}, | |
940 | {"bss", s_change_sec, 'b'}, | |
941 | {"err", s_err, 0}, | |
942 | {"half", s_cons, 1}, | |
943 | {"dword", s_cons, 3}, | |
944 | {"weakext", s_mips_weakext, 0}, | |
945 | ||
beae10d5 | 946 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
947 | here for one reason or another. */ |
948 | {"align", s_align, 0}, | |
949 | {"byte", s_cons, 0}, | |
950 | {"data", s_change_sec, 'd'}, | |
951 | {"double", s_float_cons, 'd'}, | |
952 | {"float", s_float_cons, 'f'}, | |
953 | {"globl", s_mips_globl, 0}, | |
954 | {"global", s_mips_globl, 0}, | |
955 | {"hword", s_cons, 1}, | |
956 | {"int", s_cons, 2}, | |
957 | {"long", s_cons, 2}, | |
958 | {"octa", s_cons, 4}, | |
959 | {"quad", s_cons, 3}, | |
cca86cc8 | 960 | {"section", s_change_section, 0}, |
252b5132 RH |
961 | {"short", s_cons, 1}, |
962 | {"single", s_float_cons, 'f'}, | |
963 | {"stabn", s_mips_stab, 'n'}, | |
964 | {"text", s_change_sec, 't'}, | |
965 | {"word", s_cons, 2}, | |
add56521 | 966 | |
add56521 | 967 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 968 | |
43841e91 | 969 | { NULL, NULL, 0 }, |
252b5132 RH |
970 | }; |
971 | ||
e972090a NC |
972 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
973 | { | |
beae10d5 KH |
974 | /* These pseudo-ops should be defined by the object file format. |
975 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
976 | {"aent", s_mips_ent, 1}, |
977 | {"bgnb", s_ignore, 0}, | |
978 | {"end", s_mips_end, 0}, | |
979 | {"endb", s_ignore, 0}, | |
980 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 981 | {"file", s_mips_file, 0}, |
252b5132 RH |
982 | {"fmask", s_mips_mask, 'F'}, |
983 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 984 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
985 | {"mask", s_mips_mask, 'R'}, |
986 | {"verstamp", s_ignore, 0}, | |
43841e91 | 987 | { NULL, NULL, 0 }, |
252b5132 RH |
988 | }; |
989 | ||
17a2f251 | 990 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
991 | |
992 | void | |
17a2f251 | 993 | mips_pop_insert (void) |
252b5132 RH |
994 | { |
995 | pop_insert (mips_pseudo_table); | |
996 | if (! ECOFF_DEBUGGING) | |
997 | pop_insert (mips_nonecoff_pseudo_table); | |
998 | } | |
999 | \f | |
1000 | /* Symbols labelling the current insn. */ | |
1001 | ||
e972090a NC |
1002 | struct insn_label_list |
1003 | { | |
252b5132 RH |
1004 | struct insn_label_list *next; |
1005 | symbolS *label; | |
1006 | }; | |
1007 | ||
1008 | static struct insn_label_list *insn_labels; | |
1009 | static struct insn_label_list *free_insn_labels; | |
1010 | ||
17a2f251 | 1011 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1012 | |
1013 | static inline void | |
17a2f251 | 1014 | mips_clear_insn_labels (void) |
252b5132 RH |
1015 | { |
1016 | register struct insn_label_list **pl; | |
1017 | ||
1018 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1019 | ; | |
1020 | *pl = insn_labels; | |
1021 | insn_labels = NULL; | |
1022 | } | |
1023 | \f | |
1024 | static char *expr_end; | |
1025 | ||
1026 | /* Expressions which appear in instructions. These are set by | |
1027 | mips_ip. */ | |
1028 | ||
1029 | static expressionS imm_expr; | |
1030 | static expressionS offset_expr; | |
1031 | ||
1032 | /* Relocs associated with imm_expr and offset_expr. */ | |
1033 | ||
f6688943 TS |
1034 | static bfd_reloc_code_real_type imm_reloc[3] |
1035 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1036 | static bfd_reloc_code_real_type offset_reloc[3] | |
1037 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1038 | |
252b5132 RH |
1039 | /* These are set by mips16_ip if an explicit extension is used. */ |
1040 | ||
b34976b6 | 1041 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1042 | |
7ed4a06a | 1043 | #ifdef OBJ_ELF |
ecb4347a DJ |
1044 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1045 | ECOFF debugging. */ | |
252b5132 RH |
1046 | |
1047 | static segT pdr_seg; | |
7ed4a06a | 1048 | #endif |
252b5132 | 1049 | |
e013f690 TS |
1050 | /* The default target format to use. */ |
1051 | ||
1052 | const char * | |
17a2f251 | 1053 | mips_target_format (void) |
e013f690 TS |
1054 | { |
1055 | switch (OUTPUT_FLAVOR) | |
1056 | { | |
1057 | case bfd_target_aout_flavour: | |
1058 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1059 | case bfd_target_ecoff_flavour: | |
1060 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1061 | case bfd_target_coff_flavour: | |
1062 | return "pe-mips"; | |
1063 | case bfd_target_elf_flavour: | |
1064 | #ifdef TE_TMIPS | |
cfe86eaa | 1065 | /* This is traditional mips. */ |
e013f690 | 1066 | return (target_big_endian |
cfe86eaa TS |
1067 | ? (HAVE_64BIT_OBJECTS |
1068 | ? "elf64-tradbigmips" | |
1069 | : (HAVE_NEWABI | |
1070 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1071 | : (HAVE_64BIT_OBJECTS | |
1072 | ? "elf64-tradlittlemips" | |
1073 | : (HAVE_NEWABI | |
1074 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1075 | #else |
1076 | return (target_big_endian | |
cfe86eaa TS |
1077 | ? (HAVE_64BIT_OBJECTS |
1078 | ? "elf64-bigmips" | |
1079 | : (HAVE_NEWABI | |
1080 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1081 | : (HAVE_64BIT_OBJECTS | |
1082 | ? "elf64-littlemips" | |
1083 | : (HAVE_NEWABI | |
1084 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1085 | #endif |
1086 | default: | |
1087 | abort (); | |
1088 | return NULL; | |
1089 | } | |
1090 | } | |
1091 | ||
156c2f8b NC |
1092 | /* This function is called once, at assembler startup time. It should |
1093 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1094 | ||
252b5132 | 1095 | void |
17a2f251 | 1096 | md_begin (void) |
252b5132 | 1097 | { |
252b5132 | 1098 | register const char *retval = NULL; |
156c2f8b | 1099 | int i = 0; |
252b5132 | 1100 | int broken = 0; |
1f25f5d3 | 1101 | |
fef14a42 | 1102 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1103 | as_warn (_("Could not set architecture and machine")); |
1104 | ||
252b5132 RH |
1105 | op_hash = hash_new (); |
1106 | ||
1107 | for (i = 0; i < NUMOPCODES;) | |
1108 | { | |
1109 | const char *name = mips_opcodes[i].name; | |
1110 | ||
17a2f251 | 1111 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1112 | if (retval != NULL) |
1113 | { | |
1114 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1115 | mips_opcodes[i].name, retval); | |
1116 | /* Probably a memory allocation problem? Give up now. */ | |
1117 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1118 | } | |
1119 | do | |
1120 | { | |
1121 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1122 | { | |
1123 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1124 | broken = 1; | |
1125 | } | |
1126 | ++i; | |
1127 | } | |
1128 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1129 | } | |
1130 | ||
1131 | mips16_op_hash = hash_new (); | |
1132 | ||
1133 | i = 0; | |
1134 | while (i < bfd_mips16_num_opcodes) | |
1135 | { | |
1136 | const char *name = mips16_opcodes[i].name; | |
1137 | ||
17a2f251 | 1138 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1139 | if (retval != NULL) |
1140 | as_fatal (_("internal: can't hash `%s': %s"), | |
1141 | mips16_opcodes[i].name, retval); | |
1142 | do | |
1143 | { | |
1144 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1145 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1146 | != mips16_opcodes[i].match)) | |
1147 | { | |
1148 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1149 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1150 | broken = 1; | |
1151 | } | |
1152 | ++i; | |
1153 | } | |
1154 | while (i < bfd_mips16_num_opcodes | |
1155 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1156 | } | |
1157 | ||
1158 | if (broken) | |
1159 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1160 | ||
1161 | /* We add all the general register names to the symbol table. This | |
1162 | helps us detect invalid uses of them. */ | |
1163 | for (i = 0; i < 32; i++) | |
1164 | { | |
1165 | char buf[5]; | |
1166 | ||
1167 | sprintf (buf, "$%d", i); | |
1168 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1169 | &zero_address_frag)); | |
1170 | } | |
76db943d TS |
1171 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1172 | &zero_address_frag)); | |
252b5132 RH |
1173 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1174 | &zero_address_frag)); | |
1175 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1176 | &zero_address_frag)); | |
1177 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1178 | &zero_address_frag)); | |
1179 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1180 | &zero_address_frag)); | |
1181 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1182 | &zero_address_frag)); | |
1183 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1184 | &zero_address_frag)); | |
85b51719 TS |
1185 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1186 | &zero_address_frag)); | |
252b5132 RH |
1187 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1188 | &zero_address_frag)); | |
1189 | ||
6047c971 AO |
1190 | /* If we don't add these register names to the symbol table, they |
1191 | may end up being added as regular symbols by operand(), and then | |
1192 | make it to the object file as undefined in case they're not | |
1193 | regarded as local symbols. They're local in o32, since `$' is a | |
1194 | local symbol prefix, but not in n32 or n64. */ | |
1195 | for (i = 0; i < 8; i++) | |
1196 | { | |
1197 | char buf[6]; | |
1198 | ||
1199 | sprintf (buf, "$fcc%i", i); | |
1200 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1201 | &zero_address_frag)); | |
1202 | } | |
1203 | ||
b34976b6 | 1204 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1205 | |
1206 | mips_gprmask = 0; | |
1207 | mips_cprmask[0] = 0; | |
1208 | mips_cprmask[1] = 0; | |
1209 | mips_cprmask[2] = 0; | |
1210 | mips_cprmask[3] = 0; | |
1211 | ||
1212 | /* set the default alignment for the text section (2**2) */ | |
1213 | record_alignment (text_section, 2); | |
1214 | ||
1215 | if (USE_GLOBAL_POINTER_OPT) | |
1216 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1217 | ||
1218 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1219 | { | |
1220 | /* On a native system, sections must be aligned to 16 byte | |
1221 | boundaries. When configured for an embedded ELF target, we | |
1222 | don't bother. */ | |
1223 | if (strcmp (TARGET_OS, "elf") != 0) | |
1224 | { | |
1225 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1226 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1227 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1228 | } | |
1229 | ||
1230 | /* Create a .reginfo section for register masks and a .mdebug | |
1231 | section for debugging information. */ | |
1232 | { | |
1233 | segT seg; | |
1234 | subsegT subseg; | |
1235 | flagword flags; | |
1236 | segT sec; | |
1237 | ||
1238 | seg = now_seg; | |
1239 | subseg = now_subseg; | |
1240 | ||
1241 | /* The ABI says this section should be loaded so that the | |
1242 | running program can access it. However, we don't load it | |
1243 | if we are configured for an embedded target */ | |
1244 | flags = SEC_READONLY | SEC_DATA; | |
1245 | if (strcmp (TARGET_OS, "elf") != 0) | |
1246 | flags |= SEC_ALLOC | SEC_LOAD; | |
1247 | ||
316f5878 | 1248 | if (mips_abi != N64_ABI) |
252b5132 RH |
1249 | { |
1250 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1251 | ||
195325d2 TS |
1252 | bfd_set_section_flags (stdoutput, sec, flags); |
1253 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1254 | |
252b5132 RH |
1255 | #ifdef OBJ_ELF |
1256 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1257 | #endif | |
1258 | } | |
1259 | else | |
1260 | { | |
1261 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1262 | .reginfo section. */ | |
1263 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1264 | bfd_set_section_flags (stdoutput, sec, flags); |
1265 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1266 | |
1267 | #ifdef OBJ_ELF | |
1268 | /* Set up the option header. */ | |
1269 | { | |
1270 | Elf_Internal_Options opthdr; | |
1271 | char *f; | |
1272 | ||
1273 | opthdr.kind = ODK_REGINFO; | |
1274 | opthdr.size = (sizeof (Elf_External_Options) | |
1275 | + sizeof (Elf64_External_RegInfo)); | |
1276 | opthdr.section = 0; | |
1277 | opthdr.info = 0; | |
1278 | f = frag_more (sizeof (Elf_External_Options)); | |
1279 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1280 | (Elf_External_Options *) f); | |
1281 | ||
1282 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1283 | } | |
1284 | #endif | |
1285 | } | |
1286 | ||
1287 | if (ECOFF_DEBUGGING) | |
1288 | { | |
1289 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1290 | (void) bfd_set_section_flags (stdoutput, sec, | |
1291 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1292 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1293 | } | |
ecb4347a | 1294 | #ifdef OBJ_ELF |
dcd410fe | 1295 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1296 | { |
1297 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1298 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1299 | SEC_READONLY | SEC_RELOC | |
1300 | | SEC_DEBUGGING); | |
1301 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1302 | } | |
252b5132 RH |
1303 | #endif |
1304 | ||
1305 | subseg_set (seg, subseg); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | if (! ECOFF_DEBUGGING) | |
1310 | md_obj_begin (); | |
1311 | } | |
1312 | ||
1313 | void | |
17a2f251 | 1314 | md_mips_end (void) |
252b5132 RH |
1315 | { |
1316 | if (! ECOFF_DEBUGGING) | |
1317 | md_obj_end (); | |
1318 | } | |
1319 | ||
1320 | void | |
17a2f251 | 1321 | md_assemble (char *str) |
252b5132 RH |
1322 | { |
1323 | struct mips_cl_insn insn; | |
f6688943 TS |
1324 | bfd_reloc_code_real_type unused_reloc[3] |
1325 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1326 | |
1327 | imm_expr.X_op = O_absent; | |
252b5132 | 1328 | offset_expr.X_op = O_absent; |
f6688943 TS |
1329 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1330 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1331 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1332 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1333 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1334 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1335 | |
1336 | if (mips_opts.mips16) | |
1337 | mips16_ip (str, &insn); | |
1338 | else | |
1339 | { | |
1340 | mips_ip (str, &insn); | |
beae10d5 KH |
1341 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1342 | str, insn.insn_opcode)); | |
252b5132 RH |
1343 | } |
1344 | ||
1345 | if (insn_error) | |
1346 | { | |
1347 | as_bad ("%s `%s'", insn_error, str); | |
1348 | return; | |
1349 | } | |
1350 | ||
1351 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1352 | { | |
1353 | if (mips_opts.mips16) | |
1354 | mips16_macro (&insn); | |
1355 | else | |
1356 | macro (&insn); | |
1357 | } | |
1358 | else | |
1359 | { | |
1360 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1361 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1362 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1363 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1364 | else |
5e0116d5 | 1365 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1366 | } |
1367 | } | |
1368 | ||
5919d012 RS |
1369 | /* Return true if the given relocation might need a matching %lo(). |
1370 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1371 | applied to local symbols. */ | |
1372 | ||
1373 | static inline bfd_boolean | |
17a2f251 | 1374 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1375 | { |
1376 | return (reloc == BFD_RELOC_HI16_S | |
1377 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1378 | } | |
1379 | ||
1380 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1381 | relocation. */ | |
1382 | ||
1383 | static inline bfd_boolean | |
17a2f251 | 1384 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1385 | { |
1386 | return (fixp->fx_next != NULL | |
1387 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1388 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1389 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1390 | } | |
1391 | ||
252b5132 RH |
1392 | /* See whether instruction IP reads register REG. CLASS is the type |
1393 | of register. */ | |
1394 | ||
1395 | static int | |
17a2f251 TS |
1396 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1397 | enum mips_regclass class) | |
252b5132 RH |
1398 | { |
1399 | if (class == MIPS16_REG) | |
1400 | { | |
1401 | assert (mips_opts.mips16); | |
1402 | reg = mips16_to_32_reg_map[reg]; | |
1403 | class = MIPS_GR_REG; | |
1404 | } | |
1405 | ||
85b51719 TS |
1406 | /* Don't report on general register ZERO, since it never changes. */ |
1407 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1408 | return 0; |
1409 | ||
1410 | if (class == MIPS_FP_REG) | |
1411 | { | |
1412 | assert (! mips_opts.mips16); | |
1413 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1414 | This is not optimal, because it will introduce an unnecessary | |
1415 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1416 | need to distinguish reading both $f0 and $f1 or just one of | |
1417 | them. Note that we don't have to check the other way, | |
1418 | because there is no instruction that sets both $f0 and $f1 | |
1419 | and requires a delay. */ | |
1420 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1421 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1422 | == (reg &~ (unsigned) 1))) | |
1423 | return 1; | |
1424 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1425 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1426 | == (reg &~ (unsigned) 1))) | |
1427 | return 1; | |
1428 | } | |
1429 | else if (! mips_opts.mips16) | |
1430 | { | |
1431 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1432 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1433 | return 1; | |
1434 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1435 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1436 | return 1; | |
1437 | } | |
1438 | else | |
1439 | { | |
1440 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1441 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1442 | & MIPS16OP_MASK_RX)] | |
1443 | == reg)) | |
1444 | return 1; | |
1445 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1446 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1447 | & MIPS16OP_MASK_RY)] | |
1448 | == reg)) | |
1449 | return 1; | |
1450 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1451 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1452 | & MIPS16OP_MASK_MOVE32Z)] | |
1453 | == reg)) | |
1454 | return 1; | |
1455 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1456 | return 1; | |
1457 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1460 | return 1; | |
1461 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1462 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1463 | & MIPS16OP_MASK_REGR32) == reg) | |
1464 | return 1; | |
1465 | } | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
1470 | /* This function returns true if modifying a register requires a | |
1471 | delay. */ | |
1472 | ||
1473 | static int | |
17a2f251 | 1474 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1475 | { |
1476 | unsigned long prev_pinfo; | |
1477 | ||
1478 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1479 | if (! mips_opts.noreorder | |
9ce8a5dd | 1480 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1481 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1482 | || (! gpr_interlocks | |
1483 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1484 | { | |
1485 | /* A load from a coprocessor or from memory. All load | |
1486 | delays delay the use of general register rt for one | |
1487 | instruction on the r3000. The r6000 and r4000 use | |
1488 | interlocks. */ | |
bdaaa2e1 | 1489 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1490 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1491 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1492 | return 1; | |
1493 | } | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1499 | handle them specially, such as generating jalx instructions when | |
1500 | needed. We also make them odd for the duration of the assembly, in | |
1501 | order to generate the right sort of code. We will make them even | |
1502 | in the adjust_symtab routine, while leaving them marked. This is | |
1503 | convenient for the debugger and the disassembler. The linker knows | |
1504 | to make them odd again. */ | |
1505 | ||
1506 | static void | |
17a2f251 | 1507 | mips16_mark_labels (void) |
252b5132 RH |
1508 | { |
1509 | if (mips_opts.mips16) | |
1510 | { | |
1511 | struct insn_label_list *l; | |
98aa84af | 1512 | valueT val; |
252b5132 RH |
1513 | |
1514 | for (l = insn_labels; l != NULL; l = l->next) | |
1515 | { | |
1516 | #ifdef OBJ_ELF | |
1517 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1518 | S_SET_OTHER (l->label, STO_MIPS16); | |
1519 | #endif | |
98aa84af AM |
1520 | val = S_GET_VALUE (l->label); |
1521 | if ((val & 1) == 0) | |
1522 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1523 | } |
1524 | } | |
1525 | } | |
1526 | ||
1527 | /* Output an instruction. PLACE is where to put the instruction; if | |
1528 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1529 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1530 | used with RELOC_TYPE. */ | |
1531 | ||
1532 | static void | |
17a2f251 TS |
1533 | append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr, |
1534 | bfd_reloc_code_real_type *reloc_type) | |
252b5132 RH |
1535 | { |
1536 | register unsigned long prev_pinfo, pinfo; | |
1537 | char *f; | |
f6688943 | 1538 | fixS *fixp[3]; |
252b5132 | 1539 | int nops = 0; |
f5040a92 | 1540 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1541 | |
1542 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1543 | mips16_mark_labels (); |
252b5132 RH |
1544 | |
1545 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1546 | pinfo = ip->insn_mo->pinfo; | |
1547 | ||
1548 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1549 | { | |
1550 | int prev_prev_nop; | |
1551 | ||
1552 | /* If the previous insn required any delay slots, see if we need | |
1553 | to insert a NOP or two. There are eight kinds of possible | |
1554 | hazards, of which an instruction can have at most one type. | |
1555 | (1) a load from memory delay | |
1556 | (2) a load from a coprocessor delay | |
1557 | (3) an unconditional branch delay | |
1558 | (4) a conditional branch delay | |
1559 | (5) a move to coprocessor register delay | |
1560 | (6) a load coprocessor register from memory delay | |
1561 | (7) a coprocessor condition code delay | |
1562 | (8) a HI/LO special register delay | |
1563 | ||
1564 | There are a lot of optimizations we could do that we don't. | |
1565 | In particular, we do not, in general, reorder instructions. | |
1566 | If you use gcc with optimization, it will reorder | |
1567 | instructions and generally do much more optimization then we | |
1568 | do here; repeating all that work in the assembler would only | |
1569 | benefit hand written assembly code, and does not seem worth | |
1570 | it. */ | |
1571 | ||
1572 | /* This is how a NOP is emitted. */ | |
1573 | #define emit_nop() \ | |
1574 | (mips_opts.mips16 \ | |
1575 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1576 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1577 | ||
1578 | /* The previous insn might require a delay slot, depending upon | |
1579 | the contents of the current insn. */ | |
1580 | if (! mips_opts.mips16 | |
9ce8a5dd | 1581 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1582 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1583 | && ! cop_interlocks) | |
1584 | || (! gpr_interlocks | |
1585 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1586 | { | |
1587 | /* A load from a coprocessor or from memory. All load | |
1588 | delays delay the use of general register rt for one | |
1589 | instruction on the r3000. The r6000 and r4000 use | |
1590 | interlocks. */ | |
beae10d5 | 1591 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1592 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1593 | if (mips_optimize == 0 | |
1594 | || insn_uses_reg (ip, | |
1595 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1596 | & OP_MASK_RT), | |
1597 | MIPS_GR_REG)) | |
1598 | ++nops; | |
1599 | } | |
1600 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1601 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1602 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1603 | && ! cop_interlocks) |
e7af610e | 1604 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1605 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1606 | { | |
1607 | /* A generic coprocessor delay. The previous instruction | |
1608 | modified a coprocessor general or control register. If | |
1609 | it modified a control register, we need to avoid any | |
1610 | coprocessor instruction (this is probably not always | |
1611 | required, but it sometimes is). If it modified a general | |
1612 | register, we avoid using that register. | |
1613 | ||
1614 | On the r6000 and r4000 loading a coprocessor register | |
1615 | from memory is interlocked, and does not require a delay. | |
1616 | ||
1617 | This case is not handled very well. There is no special | |
1618 | knowledge of CP0 handling, and the coprocessors other | |
1619 | than the floating point unit are not distinguished at | |
1620 | all. */ | |
1621 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1622 | Need to modify this to include knowledge about |
252b5132 RH |
1623 | user specified delays! */ |
1624 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1625 | { | |
1626 | if (mips_optimize == 0 | |
1627 | || insn_uses_reg (ip, | |
1628 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1629 | & OP_MASK_FT), | |
1630 | MIPS_FP_REG)) | |
1631 | ++nops; | |
1632 | } | |
1633 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1634 | { | |
1635 | if (mips_optimize == 0 | |
1636 | || insn_uses_reg (ip, | |
1637 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1638 | & OP_MASK_FS), | |
1639 | MIPS_FP_REG)) | |
1640 | ++nops; | |
1641 | } | |
1642 | else | |
1643 | { | |
1644 | /* We don't know exactly what the previous instruction | |
1645 | does. If the current instruction uses a coprocessor | |
1646 | register, we must insert a NOP. If previous | |
1647 | instruction may set the condition codes, and the | |
1648 | current instruction uses them, we must insert two | |
1649 | NOPS. */ | |
bdaaa2e1 | 1650 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1651 | if (mips_optimize == 0 |
1652 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1653 | && (pinfo & INSN_READ_COND_CODE))) | |
1654 | nops += 2; | |
1655 | else if (pinfo & INSN_COP) | |
1656 | ++nops; | |
1657 | } | |
1658 | } | |
1659 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1660 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1661 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1662 | && ! cop_interlocks) | |
1663 | { | |
1664 | /* The previous instruction sets the coprocessor condition | |
1665 | codes, but does not require a general coprocessor delay | |
1666 | (this means it is a floating point comparison | |
1667 | instruction). If this instruction uses the condition | |
1668 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1669 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1670 | if (mips_optimize == 0 |
1671 | || (pinfo & INSN_READ_COND_CODE)) | |
1672 | ++nops; | |
1673 | } | |
6b76fefe CM |
1674 | |
1675 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1676 | previous insn was an mfhi/mflo and the current insn | |
1677 | reads the register that the mfhi/mflo wrote to, then | |
1678 | insert two nops. */ | |
1679 | ||
1680 | else if (mips_7000_hilo_fix | |
1681 | && MF_HILO_INSN (prev_pinfo) | |
1682 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1683 | & OP_MASK_RD), |
1684 | MIPS_GR_REG)) | |
6b76fefe CM |
1685 | { |
1686 | nops += 2; | |
1687 | } | |
1688 | ||
1689 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1690 | 2nd previous insn was an mfhi/mflo and the current insn | |
1691 | reads the register that the mfhi/mflo wrote to, then | |
1692 | insert one nop. */ | |
1693 | ||
1694 | else if (mips_7000_hilo_fix | |
1695 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1696 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1697 | & OP_MASK_RD), | |
1698 | MIPS_GR_REG)) | |
bdaaa2e1 | 1699 | |
6b76fefe | 1700 | { |
f9419b05 | 1701 | ++nops; |
6b76fefe | 1702 | } |
bdaaa2e1 | 1703 | |
252b5132 RH |
1704 | else if (prev_pinfo & INSN_READ_LO) |
1705 | { | |
1706 | /* The previous instruction reads the LO register; if the | |
1707 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1708 | insert two NOPS. Some newer processors have interlocks. |
1709 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1710 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1711 | though the tx39's divide insns still do require the |
1712 | delay. */ | |
252b5132 | 1713 | if (! (hilo_interlocks |
ec68c924 | 1714 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1715 | && (mips_optimize == 0 |
1716 | || (pinfo & INSN_WRITE_LO))) | |
1717 | nops += 2; | |
1718 | /* Most mips16 branch insns don't have a delay slot. | |
1719 | If a read from LO is immediately followed by a branch | |
1720 | to a write to LO we have a read followed by a write | |
1721 | less than 2 insns away. We assume the target of | |
1722 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1723 | between a read and an immediately following branch. */ |
252b5132 RH |
1724 | else if (mips_opts.mips16 |
1725 | && (mips_optimize == 0 | |
1726 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1727 | ++nops; |
252b5132 RH |
1728 | } |
1729 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1730 | { | |
1731 | /* The previous instruction reads the HI register; if the | |
1732 | current instruction writes to the HI register, we must | |
1733 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1734 | Also the note tx39's multiply above. */ |
252b5132 | 1735 | if (! (hilo_interlocks |
ec68c924 | 1736 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1737 | && (mips_optimize == 0 |
1738 | || (pinfo & INSN_WRITE_HI))) | |
1739 | nops += 2; | |
1740 | /* Most mips16 branch insns don't have a delay slot. | |
1741 | If a read from HI is immediately followed by a branch | |
1742 | to a write to HI we have a read followed by a write | |
1743 | less than 2 insns away. We assume the target of | |
1744 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1745 | between a read and an immediately following branch. */ |
252b5132 RH |
1746 | else if (mips_opts.mips16 |
1747 | && (mips_optimize == 0 | |
1748 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1749 | ++nops; |
252b5132 RH |
1750 | } |
1751 | ||
1752 | /* If the previous instruction was in a noreorder section, then | |
1753 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1754 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1755 | if (prev_insn_unreordered) |
1756 | nops = 0; | |
1757 | ||
1758 | /* There are two cases which require two intervening | |
1759 | instructions: 1) setting the condition codes using a move to | |
1760 | coprocessor instruction which requires a general coprocessor | |
1761 | delay and then reading the condition codes 2) reading the HI | |
1762 | or LO register and then writing to it (except on processors | |
1763 | which have interlocks). If we are not already emitting a NOP | |
1764 | instruction, we must check for these cases compared to the | |
1765 | instruction previous to the previous instruction. */ | |
1766 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1767 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1768 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1769 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1770 | && (pinfo & INSN_READ_COND_CODE) | |
1771 | && ! cop_interlocks) | |
1772 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1773 | && (pinfo & INSN_WRITE_LO) | |
1774 | && ! (hilo_interlocks | |
ec68c924 | 1775 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1776 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1777 | && (pinfo & INSN_WRITE_HI) | |
1778 | && ! (hilo_interlocks | |
ec68c924 | 1779 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1780 | prev_prev_nop = 1; |
1781 | else | |
1782 | prev_prev_nop = 0; | |
1783 | ||
1784 | if (prev_prev_insn_unreordered) | |
1785 | prev_prev_nop = 0; | |
1786 | ||
1787 | if (prev_prev_nop && nops == 0) | |
1788 | ++nops; | |
1789 | ||
60b63b72 RS |
1790 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1791 | { | |
1792 | /* We're out of bits in pinfo, so we must resort to string | |
1793 | ops here. Shortcuts are selected based on opcodes being | |
1794 | limited to the VR4122 instruction set. */ | |
1795 | int min_nops = 0; | |
1796 | const char *pn = prev_insn.insn_mo->name; | |
1797 | const char *tn = ip->insn_mo->name; | |
1798 | if (strncmp(pn, "macc", 4) == 0 | |
1799 | || strncmp(pn, "dmacc", 5) == 0) | |
1800 | { | |
1801 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1802 | if (strstr (tn, "div")) | |
1803 | { | |
1804 | min_nops = 1; | |
1805 | } | |
1806 | ||
1807 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1808 | if (pn[0] == 'd' /* dmacc */ | |
1809 | && (strncmp(tn, "dmult", 5) == 0 | |
1810 | || strncmp(tn, "dmacc", 5) == 0)) | |
1811 | { | |
1812 | min_nops = 1; | |
1813 | } | |
1814 | ||
1815 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1816 | if (strcmp (tn, "mtlo") == 0 | |
1817 | || strcmp (tn, "mthi") == 0) | |
1818 | { | |
1819 | min_nops = 1; | |
1820 | } | |
1821 | ||
1822 | } | |
1823 | else if (strncmp(pn, "dmult", 5) == 0 | |
1824 | && (strncmp(tn, "dmult", 5) == 0 | |
1825 | || strncmp(tn, "dmacc", 5) == 0)) | |
1826 | { | |
1827 | /* Here is the rest of errata 23. */ | |
1828 | min_nops = 1; | |
1829 | } | |
1830 | if (nops < min_nops) | |
1831 | nops = min_nops; | |
1832 | } | |
1833 | ||
252b5132 RH |
1834 | /* If we are being given a nop instruction, don't bother with |
1835 | one of the nops we would otherwise output. This will only | |
1836 | happen when a nop instruction is used with mips_optimize set | |
1837 | to 0. */ | |
1838 | if (nops > 0 | |
1839 | && ! mips_opts.noreorder | |
156c2f8b | 1840 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1841 | --nops; |
1842 | ||
1843 | /* Now emit the right number of NOP instructions. */ | |
1844 | if (nops > 0 && ! mips_opts.noreorder) | |
1845 | { | |
1846 | fragS *old_frag; | |
1847 | unsigned long old_frag_offset; | |
1848 | int i; | |
1849 | struct insn_label_list *l; | |
1850 | ||
1851 | old_frag = frag_now; | |
1852 | old_frag_offset = frag_now_fix (); | |
1853 | ||
1854 | for (i = 0; i < nops; i++) | |
1855 | emit_nop (); | |
1856 | ||
1857 | if (listing) | |
1858 | { | |
1859 | listing_prev_line (); | |
1860 | /* We may be at the start of a variant frag. In case we | |
1861 | are, make sure there is enough space for the frag | |
1862 | after the frags created by listing_prev_line. The | |
1863 | argument to frag_grow here must be at least as large | |
1864 | as the argument to all other calls to frag_grow in | |
1865 | this file. We don't have to worry about being in the | |
1866 | middle of a variant frag, because the variants insert | |
1867 | all needed nop instructions themselves. */ | |
1868 | frag_grow (40); | |
1869 | } | |
1870 | ||
1871 | for (l = insn_labels; l != NULL; l = l->next) | |
1872 | { | |
98aa84af AM |
1873 | valueT val; |
1874 | ||
252b5132 | 1875 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1876 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1877 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1878 | /* mips16 text labels are stored as odd. */ |
1879 | if (mips_opts.mips16) | |
f9419b05 | 1880 | ++val; |
98aa84af | 1881 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1882 | } |
1883 | ||
1884 | #ifndef NO_ECOFF_DEBUGGING | |
1885 | if (ECOFF_DEBUGGING) | |
1886 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1887 | #endif | |
1888 | } | |
1889 | else if (prev_nop_frag != NULL) | |
1890 | { | |
1891 | /* We have a frag holding nops we may be able to remove. If | |
1892 | we don't need any nops, we can decrease the size of | |
1893 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1894 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1895 | if (prev_nop_frag_since == 0) |
1896 | { | |
1897 | if (nops == 0) | |
1898 | { | |
1899 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1900 | --prev_nop_frag_holds; | |
1901 | } | |
1902 | else | |
1903 | prev_nop_frag_required += nops; | |
1904 | } | |
1905 | else | |
1906 | { | |
1907 | if (prev_prev_nop == 0) | |
1908 | { | |
1909 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1910 | --prev_nop_frag_holds; | |
1911 | } | |
1912 | else | |
1913 | ++prev_nop_frag_required; | |
1914 | } | |
1915 | ||
1916 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1917 | prev_nop_frag = NULL; | |
1918 | ||
1919 | ++prev_nop_frag_since; | |
1920 | ||
1921 | /* Sanity check: by the time we reach the second instruction | |
1922 | after prev_nop_frag, we should have used up all the nops | |
1923 | one way or another. */ | |
1924 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1925 | } | |
1926 | } | |
1927 | ||
4a6a3df4 AO |
1928 | if (place == NULL |
1929 | && address_expr | |
0b25d3e6 | 1930 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
1931 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
1932 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
1933 | && mips_relax_branch | |
1934 | /* Don't try branch relaxation within .set nomacro, or within | |
1935 | .set noat if we use $at for PIC computations. If it turns | |
1936 | out that the branch was out-of-range, we'll get an error. */ | |
1937 | && !mips_opts.warn_about_macros | |
1938 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
1939 | && !mips_opts.mips16) | |
1940 | { | |
1941 | f = frag_var (rs_machine_dependent, | |
1942 | relaxed_branch_length | |
1943 | (NULL, NULL, | |
1944 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
1945 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
1946 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 1947 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
1948 | pinfo & INSN_COND_BRANCH_LIKELY, |
1949 | pinfo & INSN_WRITE_GPR_31, | |
1950 | 0), | |
1951 | address_expr->X_add_symbol, | |
1952 | address_expr->X_add_number, | |
1953 | 0); | |
1954 | *reloc_type = BFD_RELOC_UNUSED; | |
1955 | } | |
1956 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
1957 | { |
1958 | /* We need to set up a variant frag. */ | |
1959 | assert (mips_opts.mips16 && address_expr != NULL); | |
1960 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1961 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1962 | mips16_small, mips16_ext, |
1963 | (prev_pinfo | |
1964 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1965 | (*prev_insn_reloc_type |
252b5132 | 1966 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 1967 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
1968 | } |
1969 | else if (place != NULL) | |
1970 | f = place; | |
1971 | else if (mips_opts.mips16 | |
1972 | && ! ip->use_extend | |
f6688943 | 1973 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1974 | { |
1975 | /* Make sure there is enough room to swap this instruction with | |
1976 | a following jump instruction. */ | |
1977 | frag_grow (6); | |
1978 | f = frag_more (2); | |
1979 | } | |
1980 | else | |
1981 | { | |
1982 | if (mips_opts.mips16 | |
1983 | && mips_opts.noreorder | |
1984 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1985 | as_warn (_("extended instruction in delay slot")); | |
1986 | ||
1987 | f = frag_more (4); | |
1988 | } | |
1989 | ||
f6688943 TS |
1990 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1991 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1992 | { |
1993 | if (address_expr->X_op == O_constant) | |
1994 | { | |
4db1a35d | 1995 | valueT tmp; |
f6688943 TS |
1996 | |
1997 | switch (*reloc_type) | |
252b5132 RH |
1998 | { |
1999 | case BFD_RELOC_32: | |
2000 | ip->insn_opcode |= address_expr->X_add_number; | |
2001 | break; | |
2002 | ||
f6688943 | 2003 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2004 | tmp = (address_expr->X_add_number |
2005 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2006 | tmp >>= 16; |
2007 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2008 | break; | |
2009 | ||
2010 | case BFD_RELOC_MIPS_HIGHER: | |
2011 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2012 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2013 | break; | |
2014 | ||
2015 | case BFD_RELOC_HI16_S: | |
2016 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2017 | >> 16) & 0xffff; | |
2018 | break; | |
2019 | ||
2020 | case BFD_RELOC_HI16: | |
2021 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2022 | break; | |
2023 | ||
252b5132 | 2024 | case BFD_RELOC_LO16: |
ed6fb7bd | 2025 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2026 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2027 | break; | |
2028 | ||
2029 | case BFD_RELOC_MIPS_JMP: | |
2030 | if ((address_expr->X_add_number & 3) != 0) | |
2031 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2032 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2033 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2034 | as_bad (_("jump address range overflow (0x%lx)"), |
2035 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2036 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2037 | break; | |
2038 | ||
2039 | case BFD_RELOC_MIPS16_JMP: | |
2040 | if ((address_expr->X_add_number & 3) != 0) | |
2041 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2042 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2043 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2044 | as_bad (_("jump address range overflow (0x%lx)"), |
2045 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2046 | ip->insn_opcode |= |
2047 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2048 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2049 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2050 | break; | |
2051 | ||
252b5132 RH |
2052 | case BFD_RELOC_16_PCREL_S2: |
2053 | goto need_reloc; | |
2054 | ||
2055 | default: | |
2056 | internalError (); | |
2057 | } | |
2058 | } | |
2059 | else | |
2060 | { | |
2061 | need_reloc: | |
f6688943 | 2062 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2063 | if (place == NULL) |
2064 | { | |
34ce925e RS |
2065 | reloc_howto_type *howto; |
2066 | int i; | |
2067 | ||
2068 | /* In a compound relocation, it is the final (outermost) | |
2069 | operator that determines the relocated field. */ | |
2070 | for (i = 1; i < 3; i++) | |
2071 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2072 | break; | |
2073 | ||
2074 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); | |
a105a300 TS |
2075 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
2076 | bfd_get_reloc_size(howto), | |
f6688943 | 2077 | address_expr, |
a105a300 | 2078 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2079 | reloc_type[0]); |
2080 | ||
b6ff326e | 2081 | /* These relocations can have an addend that won't fit in |
f6688943 | 2082 | 4 octets for 64bit assembly. */ |
a105a300 TS |
2083 | if (HAVE_64BIT_GPRS |
2084 | && ! howto->partial_inplace | |
2085 | && (reloc_type[0] == BFD_RELOC_16 | |
2086 | || reloc_type[0] == BFD_RELOC_32 | |
2087 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2088 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2089 | || reloc_type[0] == BFD_RELOC_LO16 | |
2090 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2091 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2092 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2093 | || reloc_type[0] == BFD_RELOC_64 | |
2094 | || reloc_type[0] == BFD_RELOC_CTOR | |
2095 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2096 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2097 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2098 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2099 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2100 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2101 | fixp[0]->fx_no_overflow = 1; |
2102 | ||
5919d012 | 2103 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2104 | { |
2105 | struct mips_hi_fixup *hi_fixup; | |
2106 | ||
5919d012 RS |
2107 | /* Reuse the last entry if it already has a matching %lo. */ |
2108 | hi_fixup = mips_hi_fixup_list; | |
2109 | if (hi_fixup == 0 | |
2110 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2111 | { | |
2112 | hi_fixup = ((struct mips_hi_fixup *) | |
2113 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2114 | hi_fixup->next = mips_hi_fixup_list; | |
2115 | mips_hi_fixup_list = hi_fixup; | |
2116 | } | |
f6688943 | 2117 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2118 | hi_fixup->seg = now_seg; |
252b5132 | 2119 | } |
f6688943 | 2120 | |
34ce925e RS |
2121 | /* Add fixups for the second and third relocations, if given. |
2122 | Note that the ABI allows the second relocation to be | |
2123 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2124 | moment we only use RSS_UNDEF, but we could add support | |
2125 | for the others if it ever becomes necessary. */ | |
2126 | for (i = 1; i < 3; i++) | |
2127 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2128 | { | |
2129 | address_expr->X_op = O_absent; | |
2130 | address_expr->X_add_symbol = 0; | |
2131 | address_expr->X_add_number = 0; | |
2132 | ||
2133 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, | |
2134 | fixp[0]->fx_size, address_expr, | |
2135 | FALSE, reloc_type[i]); | |
2136 | } | |
252b5132 RH |
2137 | } |
2138 | } | |
2139 | } | |
2140 | ||
2141 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2142 | { |
2143 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2144 | #ifdef OBJ_ELF | |
2145 | dwarf2_emit_insn (4); | |
2146 | #endif | |
2147 | } | |
f6688943 | 2148 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2149 | { |
2150 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2151 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2152 | #ifdef OBJ_ELF |
2153 | dwarf2_emit_insn (4); | |
2154 | #endif | |
252b5132 RH |
2155 | } |
2156 | else | |
2157 | { | |
2158 | if (ip->use_extend) | |
2159 | { | |
2160 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2161 | f += 2; | |
2162 | } | |
2163 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2164 | #ifdef OBJ_ELF |
2165 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2166 | #endif | |
252b5132 RH |
2167 | } |
2168 | ||
2169 | /* Update the register mask information. */ | |
2170 | if (! mips_opts.mips16) | |
2171 | { | |
2172 | if (pinfo & INSN_WRITE_GPR_D) | |
2173 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2174 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2175 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2176 | if (pinfo & INSN_READ_GPR_S) | |
2177 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2178 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2179 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2180 | if (pinfo & INSN_WRITE_FPR_D) |
2181 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2182 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2183 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2184 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2185 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2186 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2187 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2188 | if (pinfo & INSN_COP) | |
2189 | { | |
bdaaa2e1 KH |
2190 | /* We don't keep enough information to sort these cases out. |
2191 | The itbl support does keep this information however, although | |
2192 | we currently don't support itbl fprmats as part of the cop | |
2193 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2194 | } |
2195 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2196 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2197 | } |
2198 | else | |
2199 | { | |
2200 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2201 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2202 | & MIPS16OP_MASK_RX); | |
2203 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2204 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2205 | & MIPS16OP_MASK_RY); | |
2206 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2207 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2208 | & MIPS16OP_MASK_RZ); | |
2209 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2210 | mips_gprmask |= 1 << TREG; | |
2211 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2212 | mips_gprmask |= 1 << SP; | |
2213 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2214 | mips_gprmask |= 1 << RA; | |
2215 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2216 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2217 | if (pinfo & MIPS16_INSN_READ_Z) | |
2218 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2219 | & MIPS16OP_MASK_MOVE32Z); | |
2220 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2221 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2222 | & MIPS16OP_MASK_REGR32); | |
2223 | } | |
2224 | ||
2225 | if (place == NULL && ! mips_opts.noreorder) | |
2226 | { | |
2227 | /* Filling the branch delay slot is more complex. We try to | |
2228 | switch the branch with the previous instruction, which we can | |
2229 | do if the previous instruction does not set up a condition | |
2230 | that the branch tests and if the branch is not itself the | |
2231 | target of any branch. */ | |
2232 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2233 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2234 | { | |
2235 | if (mips_optimize < 2 | |
2236 | /* If we have seen .set volatile or .set nomove, don't | |
2237 | optimize. */ | |
2238 | || mips_opts.nomove != 0 | |
2239 | /* If we had to emit any NOP instructions, then we | |
2240 | already know we can not swap. */ | |
2241 | || nops != 0 | |
2242 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2243 | swap. */ |
252b5132 RH |
2244 | || ! prev_insn_valid |
2245 | /* If the previous insn is already in a branch delay | |
2246 | slot, then we can not swap. */ | |
2247 | || prev_insn_is_delay_slot | |
2248 | /* If the previous previous insn was in a .set | |
2249 | noreorder, we can't swap. Actually, the MIPS | |
2250 | assembler will swap in this situation. However, gcc | |
2251 | configured -with-gnu-as will generate code like | |
2252 | .set noreorder | |
2253 | lw $4,XXX | |
2254 | .set reorder | |
2255 | INSN | |
2256 | bne $4,$0,foo | |
2257 | in which we can not swap the bne and INSN. If gcc is | |
2258 | not configured -with-gnu-as, it does not output the | |
2259 | .set pseudo-ops. We don't have to check | |
2260 | prev_insn_unreordered, because prev_insn_valid will | |
2261 | be 0 in that case. We don't want to use | |
2262 | prev_prev_insn_valid, because we do want to be able | |
2263 | to swap at the start of a function. */ | |
2264 | || prev_prev_insn_unreordered | |
2265 | /* If the branch is itself the target of a branch, we | |
2266 | can not swap. We cheat on this; all we check for is | |
2267 | whether there is a label on this instruction. If | |
2268 | there are any branches to anything other than a | |
2269 | label, users must use .set noreorder. */ | |
2270 | || insn_labels != NULL | |
2271 | /* If the previous instruction is in a variant frag, we | |
2272 | can not do the swap. This does not apply to the | |
2273 | mips16, which uses variant frags for different | |
2274 | purposes. */ | |
2275 | || (! mips_opts.mips16 | |
2276 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2277 | /* If the branch reads the condition codes, we don't | |
2278 | even try to swap, because in the sequence | |
2279 | ctc1 $X,$31 | |
2280 | INSN | |
2281 | INSN | |
2282 | bc1t LABEL | |
2283 | we can not swap, and I don't feel like handling that | |
2284 | case. */ | |
2285 | || (! mips_opts.mips16 | |
9ce8a5dd | 2286 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2287 | && (pinfo & INSN_READ_COND_CODE)) |
2288 | /* We can not swap with an instruction that requires a | |
2289 | delay slot, becase the target of the branch might | |
2290 | interfere with that instruction. */ | |
2291 | || (! mips_opts.mips16 | |
9ce8a5dd | 2292 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2293 | && (prev_pinfo |
bdaaa2e1 | 2294 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2295 | & (INSN_LOAD_COPROC_DELAY |
2296 | | INSN_COPROC_MOVE_DELAY | |
2297 | | INSN_WRITE_COND_CODE))) | |
2298 | || (! (hilo_interlocks | |
ec68c924 | 2299 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2300 | && (prev_pinfo |
2301 | & (INSN_READ_LO | |
2302 | | INSN_READ_HI))) | |
2303 | || (! mips_opts.mips16 | |
2304 | && ! gpr_interlocks | |
2305 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2306 | || (! mips_opts.mips16 | |
e7af610e | 2307 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2308 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2309 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2310 | /* We can not swap with a branch instruction. */ | |
2311 | || (prev_pinfo | |
2312 | & (INSN_UNCOND_BRANCH_DELAY | |
2313 | | INSN_COND_BRANCH_DELAY | |
2314 | | INSN_COND_BRANCH_LIKELY)) | |
2315 | /* We do not swap with a trap instruction, since it | |
2316 | complicates trap handlers to have the trap | |
2317 | instruction be in a delay slot. */ | |
2318 | || (prev_pinfo & INSN_TRAP) | |
2319 | /* If the branch reads a register that the previous | |
2320 | instruction sets, we can not swap. */ | |
2321 | || (! mips_opts.mips16 | |
2322 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2323 | && insn_uses_reg (ip, | |
2324 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2325 | & OP_MASK_RT), | |
2326 | MIPS_GR_REG)) | |
2327 | || (! mips_opts.mips16 | |
2328 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2329 | && insn_uses_reg (ip, | |
2330 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2331 | & OP_MASK_RD), | |
2332 | MIPS_GR_REG)) | |
2333 | || (mips_opts.mips16 | |
2334 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2335 | && insn_uses_reg (ip, | |
2336 | ((prev_insn.insn_opcode | |
2337 | >> MIPS16OP_SH_RX) | |
2338 | & MIPS16OP_MASK_RX), | |
2339 | MIPS16_REG)) | |
2340 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2341 | && insn_uses_reg (ip, | |
2342 | ((prev_insn.insn_opcode | |
2343 | >> MIPS16OP_SH_RY) | |
2344 | & MIPS16OP_MASK_RY), | |
2345 | MIPS16_REG)) | |
2346 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2347 | && insn_uses_reg (ip, | |
2348 | ((prev_insn.insn_opcode | |
2349 | >> MIPS16OP_SH_RZ) | |
2350 | & MIPS16OP_MASK_RZ), | |
2351 | MIPS16_REG)) | |
2352 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2353 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2354 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2355 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2356 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2357 | && insn_uses_reg (ip, | |
2358 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2359 | insn_opcode), | |
2360 | MIPS_GR_REG)))) | |
2361 | /* If the branch writes a register that the previous | |
2362 | instruction sets, we can not swap (we know that | |
2363 | branches write only to RD or to $31). */ | |
2364 | || (! mips_opts.mips16 | |
2365 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2366 | && (((pinfo & INSN_WRITE_GPR_D) | |
2367 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2368 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2369 | || ((pinfo & INSN_WRITE_GPR_31) | |
2370 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2371 | & OP_MASK_RT) | |
f9419b05 | 2372 | == RA)))) |
252b5132 RH |
2373 | || (! mips_opts.mips16 |
2374 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2375 | && (((pinfo & INSN_WRITE_GPR_D) | |
2376 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2377 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2378 | || ((pinfo & INSN_WRITE_GPR_31) | |
2379 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2380 | & OP_MASK_RD) | |
f9419b05 | 2381 | == RA)))) |
252b5132 RH |
2382 | || (mips_opts.mips16 |
2383 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2384 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2385 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2386 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2387 | == RA)))) | |
2388 | /* If the branch writes a register that the previous | |
2389 | instruction reads, we can not swap (we know that | |
2390 | branches only write to RD or to $31). */ | |
2391 | || (! mips_opts.mips16 | |
2392 | && (pinfo & INSN_WRITE_GPR_D) | |
2393 | && insn_uses_reg (&prev_insn, | |
2394 | ((ip->insn_opcode >> OP_SH_RD) | |
2395 | & OP_MASK_RD), | |
2396 | MIPS_GR_REG)) | |
2397 | || (! mips_opts.mips16 | |
2398 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2399 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2400 | || (mips_opts.mips16 |
2401 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2402 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2403 | /* If we are generating embedded PIC code, the branch | |
2404 | might be expanded into a sequence which uses $at, so | |
2405 | we can't swap with an instruction which reads it. */ | |
2406 | || (mips_pic == EMBEDDED_PIC | |
2407 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2408 | /* If the previous previous instruction has a load | |
2409 | delay, and sets a register that the branch reads, we | |
2410 | can not swap. */ | |
2411 | || (! mips_opts.mips16 | |
9ce8a5dd | 2412 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2413 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2414 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2415 | || (! gpr_interlocks | |
2416 | && (prev_prev_insn.insn_mo->pinfo | |
2417 | & INSN_LOAD_MEMORY_DELAY))) | |
2418 | && insn_uses_reg (ip, | |
2419 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2420 | & OP_MASK_RT), | |
2421 | MIPS_GR_REG)) | |
2422 | /* If one instruction sets a condition code and the | |
2423 | other one uses a condition code, we can not swap. */ | |
2424 | || ((pinfo & INSN_READ_COND_CODE) | |
2425 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2426 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2427 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2428 | /* If the previous instruction uses the PC, we can not | |
2429 | swap. */ | |
2430 | || (mips_opts.mips16 | |
2431 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2432 | /* If the previous instruction was extended, we can not | |
2433 | swap. */ | |
2434 | || (mips_opts.mips16 && prev_insn_extended) | |
2435 | /* If the previous instruction had a fixup in mips16 | |
2436 | mode, we can not swap. This normally means that the | |
2437 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2438 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2439 | /* If the previous instruction is a sync, sync.l, or |
2440 | sync.p, we can not swap. */ | |
f173e82e | 2441 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2442 | { |
2443 | /* We could do even better for unconditional branches to | |
2444 | portions of this object file; we could pick up the | |
2445 | instruction at the destination, put it in the delay | |
2446 | slot, and bump the destination address. */ | |
2447 | emit_nop (); | |
2448 | /* Update the previous insn information. */ | |
2449 | prev_prev_insn = *ip; | |
2450 | prev_insn.insn_mo = &dummy_opcode; | |
2451 | } | |
2452 | else | |
2453 | { | |
2454 | /* It looks like we can actually do the swap. */ | |
2455 | if (! mips_opts.mips16) | |
2456 | { | |
2457 | char *prev_f; | |
2458 | char temp[4]; | |
2459 | ||
2460 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2461 | memcpy (temp, prev_f, 4); | |
2462 | memcpy (prev_f, f, 4); | |
2463 | memcpy (f, temp, 4); | |
f6688943 TS |
2464 | if (prev_insn_fixp[0]) |
2465 | { | |
2466 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2467 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2468 | } | |
2469 | if (prev_insn_fixp[1]) | |
2470 | { | |
2471 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2472 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2473 | } | |
2474 | if (prev_insn_fixp[2]) | |
252b5132 | 2475 | { |
f6688943 TS |
2476 | prev_insn_fixp[2]->fx_frag = frag_now; |
2477 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2478 | } |
f5040a92 AO |
2479 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2480 | && prev_insn_frag != frag_now | |
2481 | && (prev_insn_fixp[0]->fx_r_type | |
2482 | == BFD_RELOC_MIPS_GOT_DISP | |
2483 | || (prev_insn_fixp[0]->fx_r_type | |
2484 | == BFD_RELOC_MIPS_CALL16))) | |
2485 | { | |
2486 | /* To avoid confusion in tc_gen_reloc, we must | |
2487 | ensure that this does not become a variant | |
2488 | frag. */ | |
2489 | force_new_frag = TRUE; | |
2490 | } | |
f6688943 | 2491 | if (fixp[0]) |
252b5132 | 2492 | { |
f6688943 TS |
2493 | fixp[0]->fx_frag = prev_insn_frag; |
2494 | fixp[0]->fx_where = prev_insn_where; | |
2495 | } | |
2496 | if (fixp[1]) | |
2497 | { | |
2498 | fixp[1]->fx_frag = prev_insn_frag; | |
2499 | fixp[1]->fx_where = prev_insn_where; | |
2500 | } | |
2501 | if (fixp[2]) | |
2502 | { | |
2503 | fixp[2]->fx_frag = prev_insn_frag; | |
2504 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2505 | } |
2506 | } | |
2507 | else | |
2508 | { | |
2509 | char *prev_f; | |
2510 | char temp[2]; | |
2511 | ||
f6688943 TS |
2512 | assert (prev_insn_fixp[0] == NULL); |
2513 | assert (prev_insn_fixp[1] == NULL); | |
2514 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2515 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2516 | memcpy (temp, prev_f, 2); | |
2517 | memcpy (prev_f, f, 2); | |
f6688943 | 2518 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2519 | { |
f6688943 | 2520 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2521 | memcpy (f, temp, 2); |
2522 | } | |
2523 | else | |
2524 | { | |
2525 | memcpy (f, f + 2, 2); | |
2526 | memcpy (f + 2, temp, 2); | |
2527 | } | |
f6688943 TS |
2528 | if (fixp[0]) |
2529 | { | |
2530 | fixp[0]->fx_frag = prev_insn_frag; | |
2531 | fixp[0]->fx_where = prev_insn_where; | |
2532 | } | |
2533 | if (fixp[1]) | |
2534 | { | |
2535 | fixp[1]->fx_frag = prev_insn_frag; | |
2536 | fixp[1]->fx_where = prev_insn_where; | |
2537 | } | |
2538 | if (fixp[2]) | |
252b5132 | 2539 | { |
f6688943 TS |
2540 | fixp[2]->fx_frag = prev_insn_frag; |
2541 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2542 | } |
2543 | } | |
2544 | ||
2545 | /* Update the previous insn information; leave prev_insn | |
2546 | unchanged. */ | |
2547 | prev_prev_insn = *ip; | |
2548 | } | |
2549 | prev_insn_is_delay_slot = 1; | |
2550 | ||
2551 | /* If that was an unconditional branch, forget the previous | |
2552 | insn information. */ | |
2553 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2554 | { | |
2555 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2556 | prev_insn.insn_mo = &dummy_opcode; | |
2557 | } | |
2558 | ||
f6688943 TS |
2559 | prev_insn_fixp[0] = NULL; |
2560 | prev_insn_fixp[1] = NULL; | |
2561 | prev_insn_fixp[2] = NULL; | |
2562 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2563 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2564 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2565 | prev_insn_extended = 0; |
2566 | } | |
2567 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2568 | { | |
2569 | /* We don't yet optimize a branch likely. What we should do | |
2570 | is look at the target, copy the instruction found there | |
2571 | into the delay slot, and increment the branch to jump to | |
2572 | the next instruction. */ | |
2573 | emit_nop (); | |
2574 | /* Update the previous insn information. */ | |
2575 | prev_prev_insn = *ip; | |
2576 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2577 | prev_insn_fixp[0] = NULL; |
2578 | prev_insn_fixp[1] = NULL; | |
2579 | prev_insn_fixp[2] = NULL; | |
2580 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2581 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2582 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2583 | prev_insn_extended = 0; |
2584 | } | |
2585 | else | |
2586 | { | |
2587 | /* Update the previous insn information. */ | |
2588 | if (nops > 0) | |
2589 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2590 | else | |
2591 | prev_prev_insn = prev_insn; | |
2592 | prev_insn = *ip; | |
2593 | ||
2594 | /* Any time we see a branch, we always fill the delay slot | |
2595 | immediately; since this insn is not a branch, we know it | |
2596 | is not in a delay slot. */ | |
2597 | prev_insn_is_delay_slot = 0; | |
2598 | ||
f6688943 TS |
2599 | prev_insn_fixp[0] = fixp[0]; |
2600 | prev_insn_fixp[1] = fixp[1]; | |
2601 | prev_insn_fixp[2] = fixp[2]; | |
2602 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2603 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2604 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2605 | if (mips_opts.mips16) |
2606 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2607 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2608 | } |
2609 | ||
2610 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2611 | prev_insn_unreordered = 0; | |
2612 | prev_insn_frag = frag_now; | |
2613 | prev_insn_where = f - frag_now->fr_literal; | |
2614 | prev_insn_valid = 1; | |
2615 | } | |
2616 | else if (place == NULL) | |
2617 | { | |
2618 | /* We need to record a bit of information even when we are not | |
2619 | reordering, in order to determine the base address for mips16 | |
2620 | PC relative relocs. */ | |
2621 | prev_prev_insn = prev_insn; | |
2622 | prev_insn = *ip; | |
f6688943 TS |
2623 | prev_insn_reloc_type[0] = reloc_type[0]; |
2624 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2625 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2626 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2627 | prev_insn_unreordered = 1; | |
2628 | } | |
2629 | ||
2630 | /* We just output an insn, so the next one doesn't have a label. */ | |
2631 | mips_clear_insn_labels (); | |
f5040a92 AO |
2632 | |
2633 | /* We must ensure that the frag to which an instruction that was | |
2634 | moved from a non-variant frag doesn't become a variant frag, | |
2635 | otherwise tc_gen_reloc may get confused. */ | |
2636 | if (force_new_frag) | |
2637 | { | |
2638 | frag_wane (frag_now); | |
2639 | frag_new (0); | |
2640 | } | |
252b5132 RH |
2641 | } |
2642 | ||
2643 | /* This function forgets that there was any previous instruction or | |
2644 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2645 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2646 | |
2647 | static void | |
17a2f251 | 2648 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2649 | { |
2650 | if (! preserve) | |
2651 | { | |
2652 | prev_insn.insn_mo = &dummy_opcode; | |
2653 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2654 | prev_nop_frag = NULL; | |
2655 | prev_nop_frag_holds = 0; | |
2656 | prev_nop_frag_required = 0; | |
2657 | prev_nop_frag_since = 0; | |
2658 | } | |
2659 | prev_insn_valid = 0; | |
2660 | prev_insn_is_delay_slot = 0; | |
2661 | prev_insn_unreordered = 0; | |
2662 | prev_insn_extended = 0; | |
f6688943 TS |
2663 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2664 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2665 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2666 | prev_prev_insn_unreordered = 0; |
2667 | mips_clear_insn_labels (); | |
2668 | } | |
2669 | ||
2670 | /* This function must be called whenever we turn on noreorder or emit | |
2671 | something other than instructions. It inserts any NOPS which might | |
2672 | be needed by the previous instruction, and clears the information | |
2673 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2674 | instructions are to follow. */ |
252b5132 RH |
2675 | |
2676 | static void | |
17a2f251 | 2677 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2678 | { |
2679 | if (! mips_opts.noreorder) | |
2680 | { | |
2681 | int nops; | |
2682 | ||
2683 | nops = 0; | |
2684 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2685 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2686 | && (! cop_interlocks |
2687 | && (prev_insn.insn_mo->pinfo | |
2688 | & (INSN_LOAD_COPROC_DELAY | |
2689 | | INSN_COPROC_MOVE_DELAY | |
2690 | | INSN_WRITE_COND_CODE)))) | |
2691 | || (! hilo_interlocks | |
2692 | && (prev_insn.insn_mo->pinfo | |
2693 | & (INSN_READ_LO | |
2694 | | INSN_READ_HI))) | |
2695 | || (! mips_opts.mips16 | |
2696 | && ! gpr_interlocks | |
bdaaa2e1 | 2697 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2698 | & INSN_LOAD_MEMORY_DELAY)) |
2699 | || (! mips_opts.mips16 | |
e7af610e | 2700 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2701 | && (prev_insn.insn_mo->pinfo |
2702 | & INSN_COPROC_MEMORY_DELAY))) | |
2703 | { | |
beae10d5 | 2704 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2705 | ++nops; |
2706 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2707 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2708 | && (! cop_interlocks |
2709 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2710 | || (! hilo_interlocks | |
2711 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2712 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2713 | ++nops; | |
2714 | ||
2715 | if (prev_insn_unreordered) | |
2716 | nops = 0; | |
2717 | } | |
2718 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2719 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2720 | && (! cop_interlocks |
2721 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2722 | || (! hilo_interlocks | |
2723 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2724 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2725 | { | |
beae10d5 | 2726 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2727 | if (! prev_prev_insn_unreordered) |
2728 | ++nops; | |
2729 | } | |
2730 | ||
60b63b72 RS |
2731 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2732 | { | |
2733 | int min_nops = 0; | |
2734 | const char *pn = prev_insn.insn_mo->name; | |
2735 | if (strncmp(pn, "macc", 4) == 0 | |
2736 | || strncmp(pn, "dmacc", 5) == 0 | |
2737 | || strncmp(pn, "dmult", 5) == 0) | |
2738 | { | |
2739 | min_nops = 1; | |
2740 | } | |
2741 | if (nops < min_nops) | |
2742 | nops = min_nops; | |
2743 | } | |
2744 | ||
252b5132 RH |
2745 | if (nops > 0) |
2746 | { | |
2747 | struct insn_label_list *l; | |
2748 | ||
2749 | if (insns) | |
2750 | { | |
2751 | /* Record the frag which holds the nop instructions, so | |
2752 | that we can remove them if we don't need them. */ | |
2753 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2754 | prev_nop_frag = frag_now; | |
2755 | prev_nop_frag_holds = nops; | |
2756 | prev_nop_frag_required = 0; | |
2757 | prev_nop_frag_since = 0; | |
2758 | } | |
2759 | ||
2760 | for (; nops > 0; --nops) | |
2761 | emit_nop (); | |
2762 | ||
2763 | if (insns) | |
2764 | { | |
2765 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2766 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2767 | frag_wane (frag_now); |
2768 | frag_new (0); | |
2769 | } | |
2770 | ||
2771 | for (l = insn_labels; l != NULL; l = l->next) | |
2772 | { | |
98aa84af AM |
2773 | valueT val; |
2774 | ||
252b5132 | 2775 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2776 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2777 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2778 | /* mips16 text labels are stored as odd. */ |
2779 | if (mips_opts.mips16) | |
f9419b05 | 2780 | ++val; |
98aa84af | 2781 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2782 | } |
2783 | } | |
2784 | } | |
2785 | ||
2786 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2787 | if (insns) |
252b5132 RH |
2788 | mips16_mark_labels (); |
2789 | ||
2790 | mips_no_prev_insn (insns); | |
2791 | } | |
2792 | ||
2793 | /* Build an instruction created by a macro expansion. This is passed | |
2794 | a pointer to the count of instructions created so far, an | |
2795 | expression, the name of the instruction to build, an operand format | |
2796 | string, and corresponding arguments. */ | |
2797 | ||
252b5132 | 2798 | static void |
17a2f251 TS |
2799 | macro_build (char *place, int *counter, expressionS *ep, const char *name, |
2800 | const char *fmt, ...) | |
252b5132 RH |
2801 | { |
2802 | struct mips_cl_insn insn; | |
f6688943 | 2803 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2804 | va_list args; |
252b5132 | 2805 | |
252b5132 | 2806 | va_start (args, fmt); |
252b5132 RH |
2807 | |
2808 | /* | |
2809 | * If the macro is about to expand into a second instruction, | |
2810 | * print a warning if needed. We need to pass ip as a parameter | |
2811 | * to generate a better warning message here... | |
2812 | */ | |
2813 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2814 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2815 | ||
80cc45a5 EC |
2816 | /* |
2817 | * If the macro is about to expand into a second instruction, | |
2818 | * and it is in a delay slot, print a warning. | |
2819 | */ | |
2820 | if (place == NULL | |
2821 | && *counter == 1 | |
2822 | && mips_opts.noreorder | |
2823 | && (prev_prev_insn.insn_mo->pinfo | |
2824 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2825 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2826 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2827 | ||
252b5132 | 2828 | if (place == NULL) |
f9419b05 | 2829 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2830 | |
2831 | if (mips_opts.mips16) | |
2832 | { | |
2833 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2834 | va_end (args); | |
2835 | return; | |
2836 | } | |
2837 | ||
f6688943 TS |
2838 | r[0] = BFD_RELOC_UNUSED; |
2839 | r[1] = BFD_RELOC_UNUSED; | |
2840 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2841 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2842 | assert (insn.insn_mo); | |
2843 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2844 | ||
2845 | /* Search until we get a match for NAME. */ | |
2846 | while (1) | |
2847 | { | |
b34976b6 | 2848 | /* It is assumed here that macros will never generate |
deec1734 | 2849 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2850 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2851 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2852 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2853 | (mips_opts.isa | |
3396de36 | 2854 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
2855 | mips_opts.arch) |
2856 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
2857 | break; |
2858 | ||
2859 | ++insn.insn_mo; | |
2860 | assert (insn.insn_mo->name); | |
2861 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2862 | } | |
2863 | ||
2864 | insn.insn_opcode = insn.insn_mo->match; | |
2865 | for (;;) | |
2866 | { | |
2867 | switch (*fmt++) | |
2868 | { | |
2869 | case '\0': | |
2870 | break; | |
2871 | ||
2872 | case ',': | |
2873 | case '(': | |
2874 | case ')': | |
2875 | continue; | |
2876 | ||
2877 | case 't': | |
2878 | case 'w': | |
2879 | case 'E': | |
38487616 | 2880 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2881 | continue; |
2882 | ||
2883 | case 'c': | |
38487616 TS |
2884 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2885 | continue; | |
2886 | ||
252b5132 RH |
2887 | case 'T': |
2888 | case 'W': | |
38487616 | 2889 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2890 | continue; |
2891 | ||
2892 | case 'd': | |
2893 | case 'G': | |
af7ee8bf | 2894 | case 'K': |
38487616 | 2895 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2896 | continue; |
2897 | ||
4372b673 NC |
2898 | case 'U': |
2899 | { | |
2900 | int tmp = va_arg (args, int); | |
2901 | ||
38487616 TS |
2902 | insn.insn_opcode |= tmp << OP_SH_RT; |
2903 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2904 | continue; |
4372b673 NC |
2905 | } |
2906 | ||
252b5132 RH |
2907 | case 'V': |
2908 | case 'S': | |
38487616 | 2909 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2910 | continue; |
2911 | ||
2912 | case 'z': | |
2913 | continue; | |
2914 | ||
2915 | case '<': | |
38487616 | 2916 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2917 | continue; |
2918 | ||
2919 | case 'D': | |
38487616 | 2920 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2921 | continue; |
2922 | ||
2923 | case 'B': | |
38487616 | 2924 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2925 | continue; |
2926 | ||
4372b673 | 2927 | case 'J': |
38487616 | 2928 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2929 | continue; |
2930 | ||
252b5132 | 2931 | case 'q': |
38487616 | 2932 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2933 | continue; |
2934 | ||
2935 | case 'b': | |
2936 | case 's': | |
2937 | case 'r': | |
2938 | case 'v': | |
38487616 | 2939 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2940 | continue; |
2941 | ||
2942 | case 'i': | |
2943 | case 'j': | |
2944 | case 'o': | |
f6688943 | 2945 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 2946 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
2947 | || *r == BFD_RELOC_MIPS_LITERAL |
2948 | || *r == BFD_RELOC_MIPS_HIGHER | |
2949 | || *r == BFD_RELOC_HI16_S | |
2950 | || *r == BFD_RELOC_LO16 | |
2951 | || *r == BFD_RELOC_MIPS_GOT16 | |
2952 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
2953 | || *r == BFD_RELOC_MIPS_GOT_DISP |
2954 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
2955 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
2956 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
2957 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2958 | || (ep->X_op == O_subtract |
f6688943 | 2959 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2960 | continue; |
2961 | ||
2962 | case 'u': | |
f6688943 | 2963 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2964 | assert (ep != NULL |
2965 | && (ep->X_op == O_constant | |
2966 | || (ep->X_op == O_symbol | |
f6688943 TS |
2967 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2968 | || *r == BFD_RELOC_HI16_S | |
2969 | || *r == BFD_RELOC_HI16 | |
2970 | || *r == BFD_RELOC_GPREL16 | |
2971 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2972 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2973 | || (ep->X_op == O_subtract |
f6688943 | 2974 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2975 | continue; |
2976 | ||
2977 | case 'p': | |
2978 | assert (ep != NULL); | |
2979 | /* | |
2980 | * This allows macro() to pass an immediate expression for | |
2981 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
2982 | * Note that the expression still might come from the assembly |
2983 | * input, in which case the value is not checked for range nor | |
2984 | * is a relocation entry generated (yuck). | |
252b5132 RH |
2985 | */ |
2986 | if (ep->X_op == O_constant) | |
2987 | { | |
2988 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2989 | ep = NULL; | |
2990 | } | |
2991 | else | |
0b25d3e6 | 2992 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
2993 | continue; |
2994 | ||
2995 | case 'a': | |
2996 | assert (ep != NULL); | |
f6688943 | 2997 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
2998 | continue; |
2999 | ||
3000 | case 'C': | |
3001 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3002 | continue; | |
3003 | ||
3004 | default: | |
3005 | internalError (); | |
3006 | } | |
3007 | break; | |
3008 | } | |
3009 | va_end (args); | |
f6688943 | 3010 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3011 | |
5e0116d5 | 3012 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3013 | } |
3014 | ||
3015 | static void | |
17a2f251 TS |
3016 | mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED, |
3017 | expressionS *ep, const char *name, const char *fmt, | |
3018 | va_list args) | |
252b5132 RH |
3019 | { |
3020 | struct mips_cl_insn insn; | |
f6688943 TS |
3021 | bfd_reloc_code_real_type r[3] |
3022 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3023 | |
252b5132 RH |
3024 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3025 | assert (insn.insn_mo); | |
3026 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3027 | ||
3028 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3029 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3030 | { | |
3031 | ++insn.insn_mo; | |
3032 | assert (insn.insn_mo->name); | |
3033 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3034 | } | |
3035 | ||
3036 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3037 | insn.use_extend = FALSE; |
252b5132 RH |
3038 | |
3039 | for (;;) | |
3040 | { | |
3041 | int c; | |
3042 | ||
3043 | c = *fmt++; | |
3044 | switch (c) | |
3045 | { | |
3046 | case '\0': | |
3047 | break; | |
3048 | ||
3049 | case ',': | |
3050 | case '(': | |
3051 | case ')': | |
3052 | continue; | |
3053 | ||
3054 | case 'y': | |
3055 | case 'w': | |
3056 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3057 | continue; | |
3058 | ||
3059 | case 'x': | |
3060 | case 'v': | |
3061 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3062 | continue; | |
3063 | ||
3064 | case 'z': | |
3065 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3066 | continue; | |
3067 | ||
3068 | case 'Z': | |
3069 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3070 | continue; | |
3071 | ||
3072 | case '0': | |
3073 | case 'S': | |
3074 | case 'P': | |
3075 | case 'R': | |
3076 | continue; | |
3077 | ||
3078 | case 'X': | |
3079 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3080 | continue; | |
3081 | ||
3082 | case 'Y': | |
3083 | { | |
3084 | int regno; | |
3085 | ||
3086 | regno = va_arg (args, int); | |
3087 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3088 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3089 | } | |
3090 | continue; | |
3091 | ||
3092 | case '<': | |
3093 | case '>': | |
3094 | case '4': | |
3095 | case '5': | |
3096 | case 'H': | |
3097 | case 'W': | |
3098 | case 'D': | |
3099 | case 'j': | |
3100 | case '8': | |
3101 | case 'V': | |
3102 | case 'C': | |
3103 | case 'U': | |
3104 | case 'k': | |
3105 | case 'K': | |
3106 | case 'p': | |
3107 | case 'q': | |
3108 | { | |
3109 | assert (ep != NULL); | |
3110 | ||
3111 | if (ep->X_op != O_constant) | |
874e8986 | 3112 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3113 | else |
3114 | { | |
b34976b6 AM |
3115 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3116 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3117 | &insn.extend); |
252b5132 | 3118 | ep = NULL; |
f6688943 | 3119 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3120 | } |
3121 | } | |
3122 | continue; | |
3123 | ||
3124 | case '6': | |
3125 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3126 | continue; | |
3127 | } | |
3128 | ||
3129 | break; | |
3130 | } | |
3131 | ||
f6688943 | 3132 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3133 | |
5e0116d5 | 3134 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3135 | } |
3136 | ||
438c16b8 TS |
3137 | /* |
3138 | * Generate a "jalr" instruction with a relocation hint to the called | |
3139 | * function. This occurs in NewABI PIC code. | |
3140 | */ | |
3141 | static void | |
17a2f251 | 3142 | macro_build_jalr (int icnt, expressionS *ep) |
438c16b8 | 3143 | { |
685736be | 3144 | char *f = NULL; |
b34976b6 | 3145 | |
438c16b8 | 3146 | if (HAVE_NEWABI) |
f21f8242 AO |
3147 | { |
3148 | frag_grow (4); | |
3149 | f = frag_more (0); | |
3150 | } | |
17a2f251 | 3151 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3152 | if (HAVE_NEWABI) |
f21f8242 | 3153 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3154 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3155 | } |
3156 | ||
252b5132 RH |
3157 | /* |
3158 | * Generate a "lui" instruction. | |
3159 | */ | |
3160 | static void | |
17a2f251 | 3161 | macro_build_lui (char *place, int *counter, expressionS *ep, int regnum) |
252b5132 RH |
3162 | { |
3163 | expressionS high_expr; | |
3164 | struct mips_cl_insn insn; | |
f6688943 TS |
3165 | bfd_reloc_code_real_type r[3] |
3166 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3167 | const char *name = "lui"; |
3168 | const char *fmt = "t,u"; | |
252b5132 RH |
3169 | |
3170 | assert (! mips_opts.mips16); | |
3171 | ||
3172 | if (place == NULL) | |
3173 | high_expr = *ep; | |
3174 | else | |
3175 | { | |
3176 | high_expr.X_op = O_constant; | |
3177 | high_expr.X_add_number = ep->X_add_number; | |
3178 | } | |
3179 | ||
3180 | if (high_expr.X_op == O_constant) | |
3181 | { | |
3182 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3183 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3184 | >> 16) & 0xffff; | |
f6688943 | 3185 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3186 | } |
78e1bb40 | 3187 | else |
252b5132 RH |
3188 | { |
3189 | assert (ep->X_op == O_symbol); | |
3190 | /* _gp_disp is a special case, used from s_cpload. */ | |
3191 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3192 | || (! HAVE_NEWABI |
3193 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3194 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3195 | } |
3196 | ||
3197 | /* | |
3198 | * If the macro is about to expand into a second instruction, | |
3199 | * print a warning if needed. We need to pass ip as a parameter | |
3200 | * to generate a better warning message here... | |
3201 | */ | |
3202 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3203 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3204 | ||
3205 | if (place == NULL) | |
f9419b05 | 3206 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3207 | |
3208 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3209 | assert (insn.insn_mo); | |
3210 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3211 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3212 | ||
3213 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3214 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3215 | { |
3216 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3217 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3218 | } |
3219 | else | |
5e0116d5 | 3220 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3221 | } |
3222 | ||
885add95 CD |
3223 | /* Generate a sequence of instructions to do a load or store from a constant |
3224 | offset off of a base register (breg) into/from a target register (treg), | |
3225 | using AT if necessary. */ | |
3226 | static void | |
17a2f251 TS |
3227 | macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep, |
3228 | const char *op, int treg, int breg) | |
885add95 CD |
3229 | { |
3230 | assert (ep->X_op == O_constant); | |
3231 | ||
3232 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3233 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3234 | as_warn (_("operand overflow")); | |
3235 | ||
3236 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3237 | { | |
3238 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
17a2f251 TS |
3239 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3240 | breg); | |
885add95 CD |
3241 | } |
3242 | else | |
3243 | { | |
3244 | /* 32-bit offset, need multiple instructions and AT, like: | |
3245 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3246 | addu $tempreg,$tempreg,$breg | |
3247 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3248 | to handle the complete offset. */ | |
3249 | macro_build_lui (place, counter, ep, AT); | |
3250 | if (place != NULL) | |
3251 | place += 4; | |
17a2f251 TS |
3252 | macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, |
3253 | breg); | |
885add95 CD |
3254 | if (place != NULL) |
3255 | place += 4; | |
17a2f251 TS |
3256 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3257 | AT); | |
885add95 CD |
3258 | |
3259 | if (mips_opts.noat) | |
3260 | as_warn (_("Macro used $at after \".set noat\"")); | |
3261 | } | |
3262 | } | |
3263 | ||
252b5132 RH |
3264 | /* set_at() |
3265 | * Generates code to set the $at register to true (one) | |
3266 | * if reg is less than the immediate expression. | |
3267 | */ | |
3268 | static void | |
17a2f251 | 3269 | set_at (int *counter, int reg, int unsignedp) |
252b5132 RH |
3270 | { |
3271 | if (imm_expr.X_op == O_constant | |
3272 | && imm_expr.X_add_number >= -0x8000 | |
3273 | && imm_expr.X_add_number < 0x8000) | |
17a2f251 TS |
3274 | macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti", |
3275 | "t,r,j", AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3276 | else |
3277 | { | |
4d34fb5f | 3278 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 3279 | macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt", |
252b5132 RH |
3280 | "d,v,t", AT, reg, AT); |
3281 | } | |
3282 | } | |
3283 | ||
3284 | /* Warn if an expression is not a constant. */ | |
3285 | ||
3286 | static void | |
17a2f251 | 3287 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3288 | { |
3289 | if (ex->X_op == O_big) | |
3290 | as_bad (_("unsupported large constant")); | |
3291 | else if (ex->X_op != O_constant) | |
3292 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3293 | } | |
3294 | ||
3295 | /* Count the leading zeroes by performing a binary chop. This is a | |
3296 | bulky bit of source, but performance is a LOT better for the | |
3297 | majority of values than a simple loop to count the bits: | |
3298 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3299 | if ((v) & (1 << (31 - lcnt))) | |
3300 | break; | |
3301 | However it is not code size friendly, and the gain will drop a bit | |
3302 | on certain cached systems. | |
3303 | */ | |
3304 | #define COUNT_TOP_ZEROES(v) \ | |
3305 | (((v) & ~0xffff) == 0 \ | |
3306 | ? ((v) & ~0xff) == 0 \ | |
3307 | ? ((v) & ~0xf) == 0 \ | |
3308 | ? ((v) & ~0x3) == 0 \ | |
3309 | ? ((v) & ~0x1) == 0 \ | |
3310 | ? !(v) \ | |
3311 | ? 32 \ | |
3312 | : 31 \ | |
3313 | : 30 \ | |
3314 | : ((v) & ~0x7) == 0 \ | |
3315 | ? 29 \ | |
3316 | : 28 \ | |
3317 | : ((v) & ~0x3f) == 0 \ | |
3318 | ? ((v) & ~0x1f) == 0 \ | |
3319 | ? 27 \ | |
3320 | : 26 \ | |
3321 | : ((v) & ~0x7f) == 0 \ | |
3322 | ? 25 \ | |
3323 | : 24 \ | |
3324 | : ((v) & ~0xfff) == 0 \ | |
3325 | ? ((v) & ~0x3ff) == 0 \ | |
3326 | ? ((v) & ~0x1ff) == 0 \ | |
3327 | ? 23 \ | |
3328 | : 22 \ | |
3329 | : ((v) & ~0x7ff) == 0 \ | |
3330 | ? 21 \ | |
3331 | : 20 \ | |
3332 | : ((v) & ~0x3fff) == 0 \ | |
3333 | ? ((v) & ~0x1fff) == 0 \ | |
3334 | ? 19 \ | |
3335 | : 18 \ | |
3336 | : ((v) & ~0x7fff) == 0 \ | |
3337 | ? 17 \ | |
3338 | : 16 \ | |
3339 | : ((v) & ~0xffffff) == 0 \ | |
3340 | ? ((v) & ~0xfffff) == 0 \ | |
3341 | ? ((v) & ~0x3ffff) == 0 \ | |
3342 | ? ((v) & ~0x1ffff) == 0 \ | |
3343 | ? 15 \ | |
3344 | : 14 \ | |
3345 | : ((v) & ~0x7ffff) == 0 \ | |
3346 | ? 13 \ | |
3347 | : 12 \ | |
3348 | : ((v) & ~0x3fffff) == 0 \ | |
3349 | ? ((v) & ~0x1fffff) == 0 \ | |
3350 | ? 11 \ | |
3351 | : 10 \ | |
3352 | : ((v) & ~0x7fffff) == 0 \ | |
3353 | ? 9 \ | |
3354 | : 8 \ | |
3355 | : ((v) & ~0xfffffff) == 0 \ | |
3356 | ? ((v) & ~0x3ffffff) == 0 \ | |
3357 | ? ((v) & ~0x1ffffff) == 0 \ | |
3358 | ? 7 \ | |
3359 | : 6 \ | |
3360 | : ((v) & ~0x7ffffff) == 0 \ | |
3361 | ? 5 \ | |
3362 | : 4 \ | |
3363 | : ((v) & ~0x3fffffff) == 0 \ | |
3364 | ? ((v) & ~0x1fffffff) == 0 \ | |
3365 | ? 3 \ | |
3366 | : 2 \ | |
3367 | : ((v) & ~0x7fffffff) == 0 \ | |
3368 | ? 1 \ | |
3369 | : 0) | |
3370 | ||
3371 | /* load_register() | |
3372 | * This routine generates the least number of instructions neccessary to load | |
3373 | * an absolute expression value into a register. | |
3374 | */ | |
3375 | static void | |
17a2f251 | 3376 | load_register (int *counter, int reg, expressionS *ep, int dbl) |
252b5132 RH |
3377 | { |
3378 | int freg; | |
3379 | expressionS hi32, lo32; | |
3380 | ||
3381 | if (ep->X_op != O_big) | |
3382 | { | |
3383 | assert (ep->X_op == O_constant); | |
3384 | if (ep->X_add_number < 0x8000 | |
3385 | && (ep->X_add_number >= 0 | |
3386 | || (ep->X_add_number >= -0x8000 | |
3387 | && (! dbl | |
3388 | || ! ep->X_unsigned | |
3389 | || sizeof (ep->X_add_number) > 4)))) | |
3390 | { | |
3391 | /* We can handle 16 bit signed values with an addiu to | |
3392 | $zero. No need to ever use daddiu here, since $zero and | |
3393 | the result are always correct in 32 bit mode. */ | |
17a2f251 TS |
3394 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3395 | BFD_RELOC_LO16); | |
252b5132 RH |
3396 | return; |
3397 | } | |
3398 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3399 | { | |
3400 | /* We can handle 16 bit unsigned values with an ori to | |
3401 | $zero. */ | |
17a2f251 TS |
3402 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0, |
3403 | BFD_RELOC_LO16); | |
252b5132 RH |
3404 | return; |
3405 | } | |
6373ee54 | 3406 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3407 | && (! dbl |
3408 | || ! ep->X_unsigned | |
3409 | || sizeof (ep->X_add_number) > 4 | |
3410 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3411 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3412 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3413 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3414 | && ! dbl |
3415 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3416 | == ~ (offsetT) 0xffffffff))) | |
3417 | { | |
3418 | /* 32 bit values require an lui. */ | |
17a2f251 | 3419 | macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3420 | if ((ep->X_add_number & 0xffff) != 0) |
17a2f251 TS |
3421 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg, |
3422 | BFD_RELOC_LO16); | |
252b5132 RH |
3423 | return; |
3424 | } | |
3425 | } | |
3426 | ||
3427 | /* The value is larger than 32 bits. */ | |
3428 | ||
ca4e0257 | 3429 | if (HAVE_32BIT_GPRS) |
252b5132 | 3430 | { |
956cd1d6 TS |
3431 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3432 | (unsigned long) ep->X_add_number); | |
17a2f251 TS |
3433 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3434 | BFD_RELOC_LO16); | |
252b5132 RH |
3435 | return; |
3436 | } | |
3437 | ||
3438 | if (ep->X_op != O_big) | |
3439 | { | |
3440 | hi32 = *ep; | |
3441 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3442 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3443 | hi32.X_add_number &= 0xffffffff; | |
3444 | lo32 = *ep; | |
3445 | lo32.X_add_number &= 0xffffffff; | |
3446 | } | |
3447 | else | |
3448 | { | |
3449 | assert (ep->X_add_number > 2); | |
3450 | if (ep->X_add_number == 3) | |
3451 | generic_bignum[3] = 0; | |
3452 | else if (ep->X_add_number > 4) | |
3453 | as_bad (_("Number larger than 64 bits")); | |
3454 | lo32.X_op = O_constant; | |
3455 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3456 | hi32.X_op = O_constant; | |
3457 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3458 | } | |
3459 | ||
3460 | if (hi32.X_add_number == 0) | |
3461 | freg = 0; | |
3462 | else | |
3463 | { | |
3464 | int shift, bit; | |
3465 | unsigned long hi, lo; | |
3466 | ||
956cd1d6 | 3467 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3468 | { |
3469 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3470 | { | |
17a2f251 TS |
3471 | macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, |
3472 | BFD_RELOC_LO16); | |
beae10d5 KH |
3473 | return; |
3474 | } | |
3475 | if (lo32.X_add_number & 0x80000000) | |
3476 | { | |
17a2f251 TS |
3477 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3478 | BFD_RELOC_HI16); | |
252b5132 | 3479 | if (lo32.X_add_number & 0xffff) |
17a2f251 TS |
3480 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
3481 | BFD_RELOC_LO16); | |
beae10d5 KH |
3482 | return; |
3483 | } | |
3484 | } | |
252b5132 RH |
3485 | |
3486 | /* Check for 16bit shifted constant. We know that hi32 is | |
3487 | non-zero, so start the mask on the first bit of the hi32 | |
3488 | value. */ | |
3489 | shift = 17; | |
3490 | do | |
beae10d5 KH |
3491 | { |
3492 | unsigned long himask, lomask; | |
3493 | ||
3494 | if (shift < 32) | |
3495 | { | |
3496 | himask = 0xffff >> (32 - shift); | |
3497 | lomask = (0xffff << shift) & 0xffffffff; | |
3498 | } | |
3499 | else | |
3500 | { | |
3501 | himask = 0xffff << (shift - 32); | |
3502 | lomask = 0; | |
3503 | } | |
3504 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3505 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3506 | { | |
3507 | expressionS tmp; | |
3508 | ||
3509 | tmp.X_op = O_constant; | |
3510 | if (shift < 32) | |
3511 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3512 | | (lo32.X_add_number >> shift)); | |
3513 | else | |
3514 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
17a2f251 TS |
3515 | macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0, |
3516 | BFD_RELOC_LO16); | |
3517 | macro_build (NULL, counter, NULL, | |
beae10d5 KH |
3518 | (shift >= 32) ? "dsll32" : "dsll", |
3519 | "d,w,<", reg, reg, | |
3520 | (shift >= 32) ? shift - 32 : shift); | |
3521 | return; | |
3522 | } | |
f9419b05 | 3523 | ++shift; |
beae10d5 KH |
3524 | } |
3525 | while (shift <= (64 - 16)); | |
252b5132 RH |
3526 | |
3527 | /* Find the bit number of the lowest one bit, and store the | |
3528 | shifted value in hi/lo. */ | |
3529 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3530 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3531 | if (lo != 0) | |
3532 | { | |
3533 | bit = 0; | |
3534 | while ((lo & 1) == 0) | |
3535 | { | |
3536 | lo >>= 1; | |
3537 | ++bit; | |
3538 | } | |
3539 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3540 | hi >>= bit; | |
3541 | } | |
3542 | else | |
3543 | { | |
3544 | bit = 32; | |
3545 | while ((hi & 1) == 0) | |
3546 | { | |
3547 | hi >>= 1; | |
3548 | ++bit; | |
3549 | } | |
3550 | lo = hi; | |
3551 | hi = 0; | |
3552 | } | |
3553 | ||
3554 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3555 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3556 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3557 | { |
3558 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3559 | if (shift != 0) |
beae10d5 | 3560 | { |
252b5132 RH |
3561 | expressionS tmp; |
3562 | ||
3563 | /* This instruction will set the register to be all | |
3564 | ones. */ | |
beae10d5 KH |
3565 | tmp.X_op = O_constant; |
3566 | tmp.X_add_number = (offsetT) -1; | |
17a2f251 TS |
3567 | macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, |
3568 | BFD_RELOC_LO16); | |
beae10d5 KH |
3569 | if (bit != 0) |
3570 | { | |
3571 | bit += shift; | |
17a2f251 | 3572 | macro_build (NULL, counter, NULL, |
beae10d5 KH |
3573 | (bit >= 32) ? "dsll32" : "dsll", |
3574 | "d,w,<", reg, reg, | |
3575 | (bit >= 32) ? bit - 32 : bit); | |
3576 | } | |
17a2f251 | 3577 | macro_build (NULL, counter, NULL, |
252b5132 | 3578 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3579 | "d,w,<", reg, reg, |
252b5132 | 3580 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3581 | return; |
3582 | } | |
3583 | } | |
252b5132 RH |
3584 | |
3585 | /* Sign extend hi32 before calling load_register, because we can | |
3586 | generally get better code when we load a sign extended value. */ | |
3587 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3588 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3589 | load_register (counter, reg, &hi32, 0); |
3590 | freg = reg; | |
3591 | } | |
3592 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3593 | { | |
3594 | if (freg != 0) | |
3595 | { | |
17a2f251 | 3596 | macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3597 | freg = reg; |
3598 | } | |
3599 | } | |
3600 | else | |
3601 | { | |
3602 | expressionS mid16; | |
3603 | ||
956cd1d6 | 3604 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3605 | { |
17a2f251 TS |
3606 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3607 | BFD_RELOC_HI16); | |
3608 | macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3609 | return; |
3610 | } | |
252b5132 RH |
3611 | |
3612 | if (freg != 0) | |
3613 | { | |
17a2f251 | 3614 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3615 | freg = reg; |
3616 | } | |
3617 | mid16 = lo32; | |
3618 | mid16.X_add_number >>= 16; | |
17a2f251 TS |
3619 | macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg, |
3620 | BFD_RELOC_LO16); | |
3621 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3622 | freg = reg; |
3623 | } | |
3624 | if ((lo32.X_add_number & 0xffff) != 0) | |
17a2f251 TS |
3625 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
3626 | BFD_RELOC_LO16); | |
252b5132 RH |
3627 | } |
3628 | ||
3629 | /* Load an address into a register. */ | |
3630 | ||
3631 | static void | |
17a2f251 | 3632 | load_address (int *counter, int reg, expressionS *ep, int *used_at) |
252b5132 | 3633 | { |
f9419b05 | 3634 | char *p = NULL; |
252b5132 RH |
3635 | |
3636 | if (ep->X_op != O_constant | |
3637 | && ep->X_op != O_symbol) | |
3638 | { | |
3639 | as_bad (_("expression too complex")); | |
3640 | ep->X_op = O_constant; | |
3641 | } | |
3642 | ||
3643 | if (ep->X_op == O_constant) | |
3644 | { | |
c9914766 | 3645 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3646 | return; |
3647 | } | |
3648 | ||
3649 | if (mips_pic == NO_PIC) | |
3650 | { | |
3651 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3652 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3653 | Otherwise we want |
3654 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3655 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3656 | If we have an addend, we always use the latter form. |
76b3015f | 3657 | |
d6bc6245 TS |
3658 | With 64bit address space and a usable $at we want |
3659 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3660 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3661 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3662 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3663 | dsll32 $reg,0 | |
3a482fd5 | 3664 | daddu $reg,$reg,$at |
76b3015f | 3665 | |
c03099e6 | 3666 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3667 | on superscalar processors. |
3668 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3669 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3670 | dsll $reg,16 | |
3671 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3672 | dsll $reg,16 | |
3673 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3674 | */ | |
c9914766 | 3675 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3676 | { |
d6bc6245 TS |
3677 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3678 | hold the data for such large chunks. */ | |
3679 | ||
460597ba | 3680 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3681 | { |
3682 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3683 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3684 | macro_build (p, counter, ep, "lui", "t,u", |
17a2f251 | 3685 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 3686 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3687 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 3688 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3689 | AT, AT, BFD_RELOC_LO16); |
3690 | macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3691 | macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3692 | *used_at = 1; |
3693 | } | |
3694 | else | |
3695 | { | |
3696 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3697 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3698 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3699 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
3700 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3701 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3702 | reg, reg, BFD_RELOC_HI16_S); |
3703 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3704 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3705 | reg, reg, BFD_RELOC_LO16); |
d6bc6245 TS |
3706 | } |
3707 | } | |
252b5132 RH |
3708 | else |
3709 | { | |
d6bc6245 TS |
3710 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3711 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3712 | { | |
3713 | frag_grow (20); | |
17a2f251 TS |
3714 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3715 | mips_gp_register, BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3716 | p = frag_var (rs_machine_dependent, 8, 0, |
3717 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3718 | mips_opts.warn_about_macros), | |
956cd1d6 | 3719 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3720 | } |
3721 | macro_build_lui (p, counter, ep, reg); | |
3722 | if (p != NULL) | |
3723 | p += 4; | |
17a2f251 TS |
3724 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3725 | BFD_RELOC_LO16); | |
d6bc6245 | 3726 | } |
252b5132 RH |
3727 | } |
3728 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3729 | { | |
3730 | expressionS ex; | |
3731 | ||
3732 | /* If this is a reference to an external symbol, we want | |
3733 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3734 | Otherwise we want | |
3735 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3736 | nop | |
3737 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3738 | If there is a constant, it must be added in after. |
3739 | ||
ed6fb7bd | 3740 | If we have NewABI, we want |
f5040a92 AO |
3741 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3742 | unless we're referencing a global symbol with a non-zero | |
3743 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3744 | if (HAVE_NEWABI) |
3745 | { | |
f5040a92 | 3746 | frag_grow (12); |
684022ea | 3747 | |
f5040a92 AO |
3748 | if (ep->X_add_number) |
3749 | { | |
3750 | frag_now->tc_frag_data.tc_fr_offset = | |
3751 | ex.X_add_number = ep->X_add_number; | |
3752 | ep->X_add_number = 0; | |
17a2f251 TS |
3753 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", |
3754 | reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3755 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3756 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3757 | ex.X_op = O_constant; | |
17a2f251 TS |
3758 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3759 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3760 | p = frag_var (rs_machine_dependent, 8, 0, |
3761 | RELAX_ENCODE (8, 4, 0, 0, 0, | |
3762 | mips_opts.warn_about_macros), | |
17a2f251 | 3763 | ep->X_add_symbol, 0, NULL); |
f5040a92 AO |
3764 | ep->X_add_number = ex.X_add_number; |
3765 | } | |
3766 | ||
f899b4b8 | 3767 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3768 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
f5040a92 AO |
3769 | |
3770 | if (! p) | |
3771 | { | |
3772 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3773 | that this does not become a variant frag. */ | |
3774 | frag_wane (frag_now); | |
3775 | frag_new (0); | |
3776 | } | |
ed6fb7bd SC |
3777 | } |
3778 | else | |
3779 | { | |
f5040a92 AO |
3780 | ex.X_add_number = ep->X_add_number; |
3781 | ep->X_add_number = 0; | |
3782 | frag_grow (20); | |
17a2f251 TS |
3783 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3784 | BFD_RELOC_MIPS_GOT16, | |
f899b4b8 | 3785 | mips_gp_register); |
17a2f251 | 3786 | macro_build (NULL, counter, NULL, "nop", ""); |
ed6fb7bd SC |
3787 | p = frag_var (rs_machine_dependent, 4, 0, |
3788 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
17a2f251 TS |
3789 | ep->X_add_symbol, 0, NULL); |
3790 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, | |
3791 | BFD_RELOC_LO16); | |
ed6fb7bd | 3792 | |
f5040a92 AO |
3793 | if (ex.X_add_number != 0) |
3794 | { | |
3795 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3796 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3797 | ex.X_op = O_constant; | |
17a2f251 TS |
3798 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3799 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3800 | } |
252b5132 RH |
3801 | } |
3802 | } | |
3803 | else if (mips_pic == SVR4_PIC) | |
3804 | { | |
3805 | expressionS ex; | |
3806 | int off; | |
3807 | ||
3808 | /* This is the large GOT case. If this is a reference to an | |
3809 | external symbol, we want | |
3810 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3811 | addu $reg,$reg,$gp | |
3812 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3813 | |
3814 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3815 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3816 | nop | |
3817 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3818 | If there is a constant, it must be added in after. |
f5040a92 AO |
3819 | |
3820 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3821 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3822 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3823 | */ |
438c16b8 TS |
3824 | if (HAVE_NEWABI) |
3825 | { | |
f5040a92 AO |
3826 | frag_grow (24); |
3827 | ||
3828 | frag_now->tc_frag_data.tc_fr_offset = | |
3829 | ex.X_add_number = ep->X_add_number; | |
3830 | ep->X_add_number = 0; | |
17a2f251 TS |
3831 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3832 | BFD_RELOC_MIPS_GOT_HI16); | |
3833 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3834 | reg, mips_gp_register); | |
3835 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3836 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3837 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3838 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3839 | else if (ex.X_add_number) | |
3840 | { | |
3841 | ex.X_op = O_constant; | |
17a2f251 TS |
3842 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3843 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3844 | } |
3845 | ||
3846 | ep->X_add_number = ex.X_add_number; | |
3847 | p = frag_var (rs_machine_dependent, 8, 0, | |
3848 | RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0, | |
3849 | mips_opts.warn_about_macros), | |
17a2f251 | 3850 | ep->X_add_symbol, 0, NULL); |
f899b4b8 | 3851 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 TS |
3852 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
3853 | macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3854 | reg, BFD_RELOC_MIPS_GOT_OFST); | |
438c16b8 | 3855 | } |
252b5132 | 3856 | else |
438c16b8 | 3857 | { |
f5040a92 AO |
3858 | ex.X_add_number = ep->X_add_number; |
3859 | ep->X_add_number = 0; | |
438c16b8 TS |
3860 | if (reg_needs_delay (mips_gp_register)) |
3861 | off = 4; | |
3862 | else | |
3863 | off = 0; | |
3864 | frag_grow (32); | |
17a2f251 TS |
3865 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3866 | BFD_RELOC_MIPS_GOT_HI16); | |
3867 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3868 | reg, mips_gp_register); | |
3869 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3870 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
438c16b8 TS |
3871 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3872 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3873 | mips_opts.warn_about_macros), | |
3874 | ep->X_add_symbol, 0, NULL); | |
3875 | if (off > 0) | |
3876 | { | |
3877 | /* We need a nop before loading from $gp. This special | |
3878 | check is required because the lui which starts the main | |
3879 | instruction stream does not refer to $gp, and so will not | |
3880 | insert the nop which may be required. */ | |
17a2f251 | 3881 | macro_build (p, counter, NULL, "nop", ""); |
438c16b8 TS |
3882 | p += 4; |
3883 | } | |
f899b4b8 | 3884 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3885 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
438c16b8 | 3886 | p += 4; |
17a2f251 | 3887 | macro_build (p, counter, NULL, "nop", ""); |
252b5132 | 3888 | p += 4; |
17a2f251 TS |
3889 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3890 | BFD_RELOC_LO16); | |
438c16b8 | 3891 | |
f5040a92 AO |
3892 | if (ex.X_add_number != 0) |
3893 | { | |
3894 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3895 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3896 | ex.X_op = O_constant; | |
17a2f251 TS |
3897 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3898 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3899 | } |
252b5132 RH |
3900 | } |
3901 | } | |
3902 | else if (mips_pic == EMBEDDED_PIC) | |
3903 | { | |
3904 | /* We always do | |
cdf6fd85 | 3905 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 3906 | */ |
17a2f251 TS |
3907 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3908 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
3909 | } |
3910 | else | |
3911 | abort (); | |
3912 | } | |
3913 | ||
ea1fb5dc RS |
3914 | /* Move the contents of register SOURCE into register DEST. */ |
3915 | ||
3916 | static void | |
17a2f251 | 3917 | move_register (int *counter, int dest, int source) |
ea1fb5dc | 3918 | { |
17a2f251 | 3919 | macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", |
ea1fb5dc RS |
3920 | "d,v,t", dest, source, 0); |
3921 | } | |
3922 | ||
252b5132 RH |
3923 | /* |
3924 | * Build macros | |
3925 | * This routine implements the seemingly endless macro or synthesized | |
3926 | * instructions and addressing modes in the mips assembly language. Many | |
3927 | * of these macros are simple and are similar to each other. These could | |
3928 | * probably be handled by some kind of table or grammer aproach instead of | |
3929 | * this verbose method. Others are not simple macros but are more like | |
3930 | * optimizing code generation. | |
3931 | * One interesting optimization is when several store macros appear | |
3932 | * consecutivly that would load AT with the upper half of the same address. | |
3933 | * The ensuing load upper instructions are ommited. This implies some kind | |
3934 | * of global optimization. We currently only optimize within a single macro. | |
3935 | * For many of the load and store macros if the address is specified as a | |
3936 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3937 | * first load register 'at' with zero and use it as the base register. The | |
3938 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3939 | * we're missing. | |
3940 | */ | |
3941 | static void | |
17a2f251 | 3942 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
3943 | { |
3944 | register int treg, sreg, dreg, breg; | |
3945 | int tempreg; | |
3946 | int mask; | |
3947 | int icnt = 0; | |
43841e91 | 3948 | int used_at = 0; |
252b5132 RH |
3949 | expressionS expr1; |
3950 | const char *s; | |
3951 | const char *s2; | |
3952 | const char *fmt; | |
3953 | int likely = 0; | |
3954 | int dbl = 0; | |
3955 | int coproc = 0; | |
3956 | int lr = 0; | |
3957 | int imm = 0; | |
3958 | offsetT maxnum; | |
3959 | int off; | |
3960 | bfd_reloc_code_real_type r; | |
252b5132 RH |
3961 | int hold_mips_optimize; |
3962 | ||
3963 | assert (! mips_opts.mips16); | |
3964 | ||
3965 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3966 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3967 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3968 | mask = ip->insn_mo->mask; | |
3969 | ||
3970 | expr1.X_op = O_constant; | |
3971 | expr1.X_op_symbol = NULL; | |
3972 | expr1.X_add_symbol = NULL; | |
3973 | expr1.X_add_number = 1; | |
3974 | ||
5919d012 RS |
3975 | /* Umatched fixups should not be put in the same frag as a relaxable |
3976 | macro. For example, suppose we have: | |
3977 | ||
3978 | lui $4,%hi(l1) # 1 | |
3979 | la $5,l2 # 2 | |
3980 | addiu $4,$4,%lo(l1) # 3 | |
3981 | ||
3982 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
3983 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
3984 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
3985 | for #2 to be the last for that frag. | |
3986 | ||
64bdfcaf RS |
3987 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
3988 | it assumes that they belong to a relaxable macro. We mustn't put | |
3989 | other uses of such relocations into a variant frag. | |
3990 | ||
3991 | To avoid both problems, finish the current frag it contains a | |
3992 | %reloc() operator. The macro then goes into a new frag. */ | |
3993 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
3994 | { |
3995 | frag_wane (frag_now); | |
3996 | frag_new (0); | |
3997 | } | |
3998 | ||
252b5132 RH |
3999 | switch (mask) |
4000 | { | |
4001 | case M_DABS: | |
4002 | dbl = 1; | |
4003 | case M_ABS: | |
4004 | /* bgez $a0,.+12 | |
4005 | move v0,$a0 | |
4006 | sub v0,$zero,$a0 | |
4007 | */ | |
4008 | ||
b34976b6 | 4009 | mips_emit_delays (TRUE); |
252b5132 RH |
4010 | ++mips_opts.noreorder; |
4011 | mips_any_noreorder = 1; | |
4012 | ||
4013 | expr1.X_add_number = 8; | |
17a2f251 | 4014 | macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
252b5132 | 4015 | if (dreg == sreg) |
17a2f251 | 4016 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 | 4017 | else |
ea1fb5dc | 4018 | move_register (&icnt, dreg, sreg); |
17a2f251 TS |
4019 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, |
4020 | sreg); | |
252b5132 RH |
4021 | |
4022 | --mips_opts.noreorder; | |
4023 | return; | |
4024 | ||
4025 | case M_ADD_I: | |
4026 | s = "addi"; | |
4027 | s2 = "add"; | |
4028 | goto do_addi; | |
4029 | case M_ADDU_I: | |
4030 | s = "addiu"; | |
4031 | s2 = "addu"; | |
4032 | goto do_addi; | |
4033 | case M_DADD_I: | |
4034 | dbl = 1; | |
4035 | s = "daddi"; | |
4036 | s2 = "dadd"; | |
4037 | goto do_addi; | |
4038 | case M_DADDU_I: | |
4039 | dbl = 1; | |
4040 | s = "daddiu"; | |
4041 | s2 = "daddu"; | |
4042 | do_addi: | |
4043 | if (imm_expr.X_op == O_constant | |
4044 | && imm_expr.X_add_number >= -0x8000 | |
4045 | && imm_expr.X_add_number < 0x8000) | |
4046 | { | |
17a2f251 TS |
4047 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
4048 | BFD_RELOC_LO16); | |
252b5132 RH |
4049 | return; |
4050 | } | |
4051 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 | 4052 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4053 | break; |
4054 | ||
4055 | case M_AND_I: | |
4056 | s = "andi"; | |
4057 | s2 = "and"; | |
4058 | goto do_bit; | |
4059 | case M_OR_I: | |
4060 | s = "ori"; | |
4061 | s2 = "or"; | |
4062 | goto do_bit; | |
4063 | case M_NOR_I: | |
4064 | s = ""; | |
4065 | s2 = "nor"; | |
4066 | goto do_bit; | |
4067 | case M_XOR_I: | |
4068 | s = "xori"; | |
4069 | s2 = "xor"; | |
4070 | do_bit: | |
4071 | if (imm_expr.X_op == O_constant | |
4072 | && imm_expr.X_add_number >= 0 | |
4073 | && imm_expr.X_add_number < 0x10000) | |
4074 | { | |
4075 | if (mask != M_NOR_I) | |
17a2f251 TS |
4076 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg, |
4077 | BFD_RELOC_LO16); | |
252b5132 RH |
4078 | else |
4079 | { | |
17a2f251 TS |
4080 | macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg, |
4081 | BFD_RELOC_LO16); | |
4082 | macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4083 | } |
4084 | return; | |
4085 | } | |
4086 | ||
d6bc6245 | 4087 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4088 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4089 | break; |
4090 | ||
4091 | case M_BEQ_I: | |
4092 | s = "beq"; | |
4093 | goto beq_i; | |
4094 | case M_BEQL_I: | |
4095 | s = "beql"; | |
4096 | likely = 1; | |
4097 | goto beq_i; | |
4098 | case M_BNE_I: | |
4099 | s = "bne"; | |
4100 | goto beq_i; | |
4101 | case M_BNEL_I: | |
4102 | s = "bnel"; | |
4103 | likely = 1; | |
4104 | beq_i: | |
4105 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4106 | { | |
17a2f251 | 4107 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4108 | return; |
4109 | } | |
4d34fb5f | 4110 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4111 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
252b5132 RH |
4112 | break; |
4113 | ||
4114 | case M_BGEL: | |
4115 | likely = 1; | |
4116 | case M_BGE: | |
4117 | if (treg == 0) | |
4118 | { | |
17a2f251 TS |
4119 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4120 | "s,p", sreg); | |
252b5132 RH |
4121 | return; |
4122 | } | |
4123 | if (sreg == 0) | |
4124 | { | |
17a2f251 TS |
4125 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4126 | "s,p", treg); | |
252b5132 RH |
4127 | return; |
4128 | } | |
17a2f251 TS |
4129 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4130 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4131 | "s,t,p", AT, 0); | |
252b5132 RH |
4132 | break; |
4133 | ||
4134 | case M_BGTL_I: | |
4135 | likely = 1; | |
4136 | case M_BGT_I: | |
4137 | /* check for > max integer */ | |
4138 | maxnum = 0x7fffffff; | |
ca4e0257 | 4139 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4140 | { |
4141 | maxnum <<= 16; | |
4142 | maxnum |= 0xffff; | |
4143 | maxnum <<= 16; | |
4144 | maxnum |= 0xffff; | |
4145 | } | |
4146 | if (imm_expr.X_op == O_constant | |
4147 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4148 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4149 | { |
4150 | do_false: | |
4151 | /* result is always false */ | |
4152 | if (! likely) | |
4153 | { | |
39c0a331 L |
4154 | if (warn_nops) |
4155 | as_warn (_("Branch %s is always false (nop)"), | |
4156 | ip->insn_mo->name); | |
17a2f251 | 4157 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 RH |
4158 | } |
4159 | else | |
4160 | { | |
39c0a331 L |
4161 | if (warn_nops) |
4162 | as_warn (_("Branch likely %s is always false"), | |
4163 | ip->insn_mo->name); | |
17a2f251 | 4164 | macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4165 | } |
4166 | return; | |
4167 | } | |
4168 | if (imm_expr.X_op != O_constant) | |
4169 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4170 | ++imm_expr.X_add_number; |
252b5132 RH |
4171 | /* FALLTHROUGH */ |
4172 | case M_BGE_I: | |
4173 | case M_BGEL_I: | |
4174 | if (mask == M_BGEL_I) | |
4175 | likely = 1; | |
4176 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4177 | { | |
17a2f251 TS |
4178 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4179 | "s,p", sreg); | |
252b5132 RH |
4180 | return; |
4181 | } | |
4182 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4183 | { | |
17a2f251 TS |
4184 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4185 | "s,p", sreg); | |
252b5132 RH |
4186 | return; |
4187 | } | |
4188 | maxnum = 0x7fffffff; | |
ca4e0257 | 4189 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4190 | { |
4191 | maxnum <<= 16; | |
4192 | maxnum |= 0xffff; | |
4193 | maxnum <<= 16; | |
4194 | maxnum |= 0xffff; | |
4195 | } | |
4196 | maxnum = - maxnum - 1; | |
4197 | if (imm_expr.X_op == O_constant | |
4198 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4199 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4200 | { |
4201 | do_true: | |
4202 | /* result is always true */ | |
4203 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
17a2f251 | 4204 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
4205 | return; |
4206 | } | |
4207 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4208 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4209 | "s,t,p", AT, 0); | |
252b5132 RH |
4210 | break; |
4211 | ||
4212 | case M_BGEUL: | |
4213 | likely = 1; | |
4214 | case M_BGEU: | |
4215 | if (treg == 0) | |
4216 | goto do_true; | |
4217 | if (sreg == 0) | |
4218 | { | |
17a2f251 TS |
4219 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4220 | "s,t,p", 0, treg); | |
252b5132 RH |
4221 | return; |
4222 | } | |
17a2f251 TS |
4223 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4224 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4225 | "s,t,p", AT, 0); | |
252b5132 RH |
4226 | break; |
4227 | ||
4228 | case M_BGTUL_I: | |
4229 | likely = 1; | |
4230 | case M_BGTU_I: | |
4231 | if (sreg == 0 | |
ca4e0257 | 4232 | || (HAVE_32BIT_GPRS |
252b5132 | 4233 | && imm_expr.X_op == O_constant |
956cd1d6 | 4234 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4235 | goto do_false; |
4236 | if (imm_expr.X_op != O_constant) | |
4237 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4238 | ++imm_expr.X_add_number; |
252b5132 RH |
4239 | /* FALLTHROUGH */ |
4240 | case M_BGEU_I: | |
4241 | case M_BGEUL_I: | |
4242 | if (mask == M_BGEUL_I) | |
4243 | likely = 1; | |
4244 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4245 | goto do_true; | |
4246 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4247 | { | |
17a2f251 TS |
4248 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4249 | "s,t,p", sreg, 0); | |
252b5132 RH |
4250 | return; |
4251 | } | |
4252 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4253 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4254 | "s,t,p", AT, 0); | |
252b5132 RH |
4255 | break; |
4256 | ||
4257 | case M_BGTL: | |
4258 | likely = 1; | |
4259 | case M_BGT: | |
4260 | if (treg == 0) | |
4261 | { | |
17a2f251 TS |
4262 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4263 | "s,p", sreg); | |
252b5132 RH |
4264 | return; |
4265 | } | |
4266 | if (sreg == 0) | |
4267 | { | |
17a2f251 TS |
4268 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4269 | "s,p", treg); | |
252b5132 RH |
4270 | return; |
4271 | } | |
17a2f251 TS |
4272 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4273 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4274 | "s,t,p", AT, 0); | |
252b5132 RH |
4275 | break; |
4276 | ||
4277 | case M_BGTUL: | |
4278 | likely = 1; | |
4279 | case M_BGTU: | |
4280 | if (treg == 0) | |
4281 | { | |
17a2f251 TS |
4282 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4283 | "s,t,p", sreg, 0); | |
252b5132 RH |
4284 | return; |
4285 | } | |
4286 | if (sreg == 0) | |
4287 | goto do_false; | |
17a2f251 TS |
4288 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4289 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4290 | "s,t,p", AT, 0); | |
252b5132 RH |
4291 | break; |
4292 | ||
4293 | case M_BLEL: | |
4294 | likely = 1; | |
4295 | case M_BLE: | |
4296 | if (treg == 0) | |
4297 | { | |
17a2f251 TS |
4298 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4299 | "s,p", sreg); | |
252b5132 RH |
4300 | return; |
4301 | } | |
4302 | if (sreg == 0) | |
4303 | { | |
17a2f251 TS |
4304 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4305 | "s,p", treg); | |
252b5132 RH |
4306 | return; |
4307 | } | |
17a2f251 TS |
4308 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4309 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4310 | "s,t,p", AT, 0); | |
252b5132 RH |
4311 | break; |
4312 | ||
4313 | case M_BLEL_I: | |
4314 | likely = 1; | |
4315 | case M_BLE_I: | |
4316 | maxnum = 0x7fffffff; | |
ca4e0257 | 4317 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4318 | { |
4319 | maxnum <<= 16; | |
4320 | maxnum |= 0xffff; | |
4321 | maxnum <<= 16; | |
4322 | maxnum |= 0xffff; | |
4323 | } | |
4324 | if (imm_expr.X_op == O_constant | |
4325 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4326 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4327 | goto do_true; |
4328 | if (imm_expr.X_op != O_constant) | |
4329 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4330 | ++imm_expr.X_add_number; |
252b5132 RH |
4331 | /* FALLTHROUGH */ |
4332 | case M_BLT_I: | |
4333 | case M_BLTL_I: | |
4334 | if (mask == M_BLTL_I) | |
4335 | likely = 1; | |
4336 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4337 | { | |
17a2f251 TS |
4338 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4339 | "s,p", sreg); | |
252b5132 RH |
4340 | return; |
4341 | } | |
4342 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4343 | { | |
17a2f251 TS |
4344 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4345 | "s,p", sreg); | |
252b5132 RH |
4346 | return; |
4347 | } | |
4348 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4349 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4350 | "s,t,p", AT, 0); | |
252b5132 RH |
4351 | break; |
4352 | ||
4353 | case M_BLEUL: | |
4354 | likely = 1; | |
4355 | case M_BLEU: | |
4356 | if (treg == 0) | |
4357 | { | |
17a2f251 TS |
4358 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4359 | "s,t,p", sreg, 0); | |
252b5132 RH |
4360 | return; |
4361 | } | |
4362 | if (sreg == 0) | |
4363 | goto do_true; | |
17a2f251 TS |
4364 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4365 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4366 | "s,t,p", AT, 0); | |
252b5132 RH |
4367 | break; |
4368 | ||
4369 | case M_BLEUL_I: | |
4370 | likely = 1; | |
4371 | case M_BLEU_I: | |
4372 | if (sreg == 0 | |
ca4e0257 | 4373 | || (HAVE_32BIT_GPRS |
252b5132 | 4374 | && imm_expr.X_op == O_constant |
956cd1d6 | 4375 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4376 | goto do_true; |
4377 | if (imm_expr.X_op != O_constant) | |
4378 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4379 | ++imm_expr.X_add_number; |
252b5132 RH |
4380 | /* FALLTHROUGH */ |
4381 | case M_BLTU_I: | |
4382 | case M_BLTUL_I: | |
4383 | if (mask == M_BLTUL_I) | |
4384 | likely = 1; | |
4385 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4386 | goto do_false; | |
4387 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4388 | { | |
17a2f251 | 4389 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4390 | "s,t,p", sreg, 0); |
4391 | return; | |
4392 | } | |
4393 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4394 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4395 | "s,t,p", AT, 0); | |
252b5132 RH |
4396 | break; |
4397 | ||
4398 | case M_BLTL: | |
4399 | likely = 1; | |
4400 | case M_BLT: | |
4401 | if (treg == 0) | |
4402 | { | |
17a2f251 TS |
4403 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4404 | "s,p", sreg); | |
252b5132 RH |
4405 | return; |
4406 | } | |
4407 | if (sreg == 0) | |
4408 | { | |
17a2f251 TS |
4409 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4410 | "s,p", treg); | |
252b5132 RH |
4411 | return; |
4412 | } | |
17a2f251 TS |
4413 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4414 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4415 | "s,t,p", AT, 0); | |
252b5132 RH |
4416 | break; |
4417 | ||
4418 | case M_BLTUL: | |
4419 | likely = 1; | |
4420 | case M_BLTU: | |
4421 | if (treg == 0) | |
4422 | goto do_false; | |
4423 | if (sreg == 0) | |
4424 | { | |
17a2f251 TS |
4425 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4426 | "s,t,p", 0, treg); | |
252b5132 RH |
4427 | return; |
4428 | } | |
17a2f251 TS |
4429 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4430 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4431 | "s,t,p", AT, 0); | |
252b5132 RH |
4432 | break; |
4433 | ||
4434 | case M_DDIV_3: | |
4435 | dbl = 1; | |
4436 | case M_DIV_3: | |
4437 | s = "mflo"; | |
4438 | goto do_div3; | |
4439 | case M_DREM_3: | |
4440 | dbl = 1; | |
4441 | case M_REM_3: | |
4442 | s = "mfhi"; | |
4443 | do_div3: | |
4444 | if (treg == 0) | |
4445 | { | |
4446 | as_warn (_("Divide by zero.")); | |
4447 | if (mips_trap) | |
17a2f251 | 4448 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4449 | else |
17a2f251 | 4450 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4451 | return; |
4452 | } | |
4453 | ||
b34976b6 | 4454 | mips_emit_delays (TRUE); |
252b5132 RH |
4455 | ++mips_opts.noreorder; |
4456 | mips_any_noreorder = 1; | |
4457 | if (mips_trap) | |
4458 | { | |
17a2f251 TS |
4459 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4460 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4461 | sreg, treg); | |
252b5132 RH |
4462 | } |
4463 | else | |
4464 | { | |
4465 | expr1.X_add_number = 8; | |
17a2f251 TS |
4466 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4467 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4468 | sreg, treg); | |
4469 | macro_build (NULL, &icnt,NULL, "break", "c", 7); | |
252b5132 RH |
4470 | } |
4471 | expr1.X_add_number = -1; | |
17a2f251 TS |
4472 | macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j", |
4473 | AT, 0, BFD_RELOC_LO16); | |
252b5132 | 4474 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
17a2f251 | 4475 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4476 | if (dbl) |
4477 | { | |
4478 | expr1.X_add_number = 1; | |
17a2f251 TS |
4479 | macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
4480 | BFD_RELOC_LO16); | |
4481 | macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31); | |
252b5132 RH |
4482 | } |
4483 | else | |
4484 | { | |
4485 | expr1.X_add_number = 0x80000000; | |
17a2f251 TS |
4486 | macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT, |
4487 | BFD_RELOC_HI16); | |
252b5132 RH |
4488 | } |
4489 | if (mips_trap) | |
4490 | { | |
17a2f251 | 4491 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4492 | /* We want to close the noreorder block as soon as possible, so |
4493 | that later insns are available for delay slot filling. */ | |
4494 | --mips_opts.noreorder; | |
4495 | } | |
4496 | else | |
4497 | { | |
4498 | expr1.X_add_number = 8; | |
17a2f251 TS |
4499 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); |
4500 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
252b5132 RH |
4501 | |
4502 | /* We want to close the noreorder block as soon as possible, so | |
4503 | that later insns are available for delay slot filling. */ | |
4504 | --mips_opts.noreorder; | |
4505 | ||
17a2f251 | 4506 | macro_build (NULL, &icnt, NULL, "break", "c", 6); |
252b5132 | 4507 | } |
17a2f251 | 4508 | macro_build (NULL, &icnt, NULL, s, "d", dreg); |
252b5132 RH |
4509 | break; |
4510 | ||
4511 | case M_DIV_3I: | |
4512 | s = "div"; | |
4513 | s2 = "mflo"; | |
4514 | goto do_divi; | |
4515 | case M_DIVU_3I: | |
4516 | s = "divu"; | |
4517 | s2 = "mflo"; | |
4518 | goto do_divi; | |
4519 | case M_REM_3I: | |
4520 | s = "div"; | |
4521 | s2 = "mfhi"; | |
4522 | goto do_divi; | |
4523 | case M_REMU_3I: | |
4524 | s = "divu"; | |
4525 | s2 = "mfhi"; | |
4526 | goto do_divi; | |
4527 | case M_DDIV_3I: | |
4528 | dbl = 1; | |
4529 | s = "ddiv"; | |
4530 | s2 = "mflo"; | |
4531 | goto do_divi; | |
4532 | case M_DDIVU_3I: | |
4533 | dbl = 1; | |
4534 | s = "ddivu"; | |
4535 | s2 = "mflo"; | |
4536 | goto do_divi; | |
4537 | case M_DREM_3I: | |
4538 | dbl = 1; | |
4539 | s = "ddiv"; | |
4540 | s2 = "mfhi"; | |
4541 | goto do_divi; | |
4542 | case M_DREMU_3I: | |
4543 | dbl = 1; | |
4544 | s = "ddivu"; | |
4545 | s2 = "mfhi"; | |
4546 | do_divi: | |
4547 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4548 | { | |
4549 | as_warn (_("Divide by zero.")); | |
4550 | if (mips_trap) | |
17a2f251 | 4551 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4552 | else |
17a2f251 | 4553 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4554 | return; |
4555 | } | |
4556 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4557 | { | |
4558 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4559 | move_register (&icnt, dreg, sreg); |
252b5132 | 4560 | else |
ea1fb5dc | 4561 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4562 | return; |
4563 | } | |
4564 | if (imm_expr.X_op == O_constant | |
4565 | && imm_expr.X_add_number == -1 | |
4566 | && s[strlen (s) - 1] != 'u') | |
4567 | { | |
4568 | if (strcmp (s2, "mflo") == 0) | |
4569 | { | |
17a2f251 TS |
4570 | macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w", |
4571 | dreg, sreg); | |
252b5132 RH |
4572 | } |
4573 | else | |
ea1fb5dc | 4574 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4575 | return; |
4576 | } | |
4577 | ||
4578 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
4579 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4580 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); | |
252b5132 RH |
4581 | break; |
4582 | ||
4583 | case M_DIVU_3: | |
4584 | s = "divu"; | |
4585 | s2 = "mflo"; | |
4586 | goto do_divu3; | |
4587 | case M_REMU_3: | |
4588 | s = "divu"; | |
4589 | s2 = "mfhi"; | |
4590 | goto do_divu3; | |
4591 | case M_DDIVU_3: | |
4592 | s = "ddivu"; | |
4593 | s2 = "mflo"; | |
4594 | goto do_divu3; | |
4595 | case M_DREMU_3: | |
4596 | s = "ddivu"; | |
4597 | s2 = "mfhi"; | |
4598 | do_divu3: | |
b34976b6 | 4599 | mips_emit_delays (TRUE); |
252b5132 RH |
4600 | ++mips_opts.noreorder; |
4601 | mips_any_noreorder = 1; | |
4602 | if (mips_trap) | |
4603 | { | |
17a2f251 TS |
4604 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4605 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4606 | /* We want to close the noreorder block as soon as possible, so |
4607 | that later insns are available for delay slot filling. */ | |
4608 | --mips_opts.noreorder; | |
4609 | } | |
4610 | else | |
4611 | { | |
4612 | expr1.X_add_number = 8; | |
17a2f251 TS |
4613 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4614 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4615 | |
4616 | /* We want to close the noreorder block as soon as possible, so | |
4617 | that later insns are available for delay slot filling. */ | |
4618 | --mips_opts.noreorder; | |
17a2f251 | 4619 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 | 4620 | } |
17a2f251 | 4621 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); |
252b5132 RH |
4622 | return; |
4623 | ||
4624 | case M_DLA_AB: | |
4625 | dbl = 1; | |
4626 | case M_LA_AB: | |
4627 | /* Load the address of a symbol into a register. If breg is not | |
4628 | zero, we then add a base register to it. */ | |
4629 | ||
3bec30a8 TS |
4630 | if (dbl && HAVE_32BIT_GPRS) |
4631 | as_warn (_("dla used to load 32-bit register")); | |
4632 | ||
c90bbe5b | 4633 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4634 | as_warn (_("la used to load 64-bit address")); |
4635 | ||
0c11417f MR |
4636 | if (offset_expr.X_op == O_constant |
4637 | && offset_expr.X_add_number >= -0x8000 | |
4638 | && offset_expr.X_add_number < 0x8000) | |
4639 | { | |
17a2f251 | 4640 | macro_build (NULL, &icnt, &offset_expr, |
b7c7d6c1 | 4641 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4642 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4643 | return; |
4644 | } | |
4645 | ||
afdbd6d0 CD |
4646 | if (treg == breg) |
4647 | { | |
4648 | tempreg = AT; | |
4649 | used_at = 1; | |
4650 | } | |
4651 | else | |
4652 | { | |
4653 | tempreg = treg; | |
4654 | used_at = 0; | |
4655 | } | |
4656 | ||
252b5132 RH |
4657 | /* When generating embedded PIC code, we permit expressions of |
4658 | the form | |
afdbd6d0 CD |
4659 | la $treg,foo-bar |
4660 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4661 | where bar is an address in the current section. These are used |
252b5132 RH |
4662 | when getting the addresses of functions. We don't permit |
4663 | X_add_number to be non-zero, because if the symbol is | |
4664 | external the relaxing code needs to know that any addend is | |
4665 | purely the offset to X_op_symbol. */ | |
4666 | if (mips_pic == EMBEDDED_PIC | |
4667 | && offset_expr.X_op == O_subtract | |
49309057 | 4668 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4669 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4670 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4671 | && (S_GET_SEGMENT | |
4672 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4673 | ->X_add_symbol) | |
bb2d6cd7 | 4674 | == now_seg))) |
bb2d6cd7 GK |
4675 | && (offset_expr.X_add_number == 0 |
4676 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4677 | { |
afdbd6d0 CD |
4678 | if (breg == 0) |
4679 | { | |
4680 | tempreg = treg; | |
4681 | used_at = 0; | |
17a2f251 TS |
4682 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4683 | BFD_RELOC_PCREL_HI16_S); | |
afdbd6d0 CD |
4684 | } |
4685 | else | |
4686 | { | |
17a2f251 TS |
4687 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4688 | BFD_RELOC_PCREL_HI16_S); | |
4689 | macro_build (NULL, &icnt, NULL, | |
4d34fb5f | 4690 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4691 | "d,v,t", tempreg, tempreg, breg); |
4692 | } | |
17a2f251 | 4693 | macro_build (NULL, &icnt, &offset_expr, |
4d34fb5f | 4694 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4695 | "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); |
afdbd6d0 CD |
4696 | if (! used_at) |
4697 | return; | |
4698 | break; | |
252b5132 RH |
4699 | } |
4700 | ||
4701 | if (offset_expr.X_op != O_symbol | |
4702 | && offset_expr.X_op != O_constant) | |
4703 | { | |
4704 | as_bad (_("expression too complex")); | |
4705 | offset_expr.X_op = O_constant; | |
4706 | } | |
4707 | ||
252b5132 | 4708 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4709 | load_register (&icnt, tempreg, &offset_expr, |
4710 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4711 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4712 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4713 | else if (mips_pic == NO_PIC) |
4714 | { | |
d6bc6245 | 4715 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4716 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4717 | Otherwise we want |
4718 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4719 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4720 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4721 | so we may as well always use the latter form. |
76b3015f | 4722 | |
d6bc6245 TS |
4723 | With 64bit address space and a usable $at we want |
4724 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4725 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4726 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4727 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4728 | dsll32 $tempreg,0 | |
3a482fd5 | 4729 | daddu $tempreg,$tempreg,$at |
76b3015f | 4730 | |
c03099e6 | 4731 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4732 | on superscalar processors. |
4733 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4734 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4735 | dsll $tempreg,16 | |
4736 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4737 | dsll $tempreg,16 | |
4738 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4739 | */ | |
f9419b05 | 4740 | char *p = NULL; |
d6bc6245 | 4741 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4742 | { |
d6bc6245 TS |
4743 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4744 | hold the data for such large chunks. */ | |
4745 | ||
460597ba | 4746 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4747 | { |
4748 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4749 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4750 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 4751 | AT, BFD_RELOC_HI16_S); |
98d3f06f | 4752 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4753 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
98d3f06f | 4754 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4755 | AT, AT, BFD_RELOC_LO16); |
4756 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
4757 | tempreg, tempreg, 0); | |
4758 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
4759 | tempreg, tempreg, AT); | |
98d3f06f KH |
4760 | used_at = 1; |
4761 | } | |
4762 | else | |
4763 | { | |
4764 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4765 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4766 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4767 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
4768 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4769 | tempreg, tempreg, 16); |
4770 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 TS |
4771 | tempreg, tempreg, BFD_RELOC_HI16_S); |
4772 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4773 | tempreg, tempreg, 16); |
4774 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4775 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4776 | } |
4777 | } | |
4778 | else | |
4779 | { | |
4780 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4781 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4782 | { | |
4783 | frag_grow (20); | |
17a2f251 TS |
4784 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
4785 | "t,r,j", tempreg, mips_gp_register, | |
4786 | BFD_RELOC_GPREL16); | |
98d3f06f KH |
4787 | p = frag_var (rs_machine_dependent, 8, 0, |
4788 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4789 | mips_opts.warn_about_macros), | |
4790 | offset_expr.X_add_symbol, 0, NULL); | |
4791 | } | |
4792 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4793 | if (p != NULL) | |
4794 | p += 4; | |
f899b4b8 | 4795 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4796 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4797 | } |
252b5132 | 4798 | } |
f5040a92 | 4799 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4800 | { |
9117d219 NC |
4801 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4802 | ||
252b5132 RH |
4803 | /* If this is a reference to an external symbol, and there |
4804 | is no constant, we want | |
4805 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4806 | or if tempreg is PIC_CALL_REG |
4807 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4808 | For a local symbol, we want |
4809 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4810 | nop | |
4811 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4812 | ||
4813 | If we have a small constant, and this is a reference to | |
4814 | an external symbol, we want | |
4815 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4816 | nop | |
4817 | addiu $tempreg,$tempreg,<constant> | |
4818 | For a local symbol, we want the same instruction | |
4819 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4820 | addiu instruction. | |
4821 | ||
4822 | If we have a large constant, and this is a reference to | |
4823 | an external symbol, we want | |
4824 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4825 | lui $at,<hiconstant> | |
4826 | addiu $at,$at,<loconstant> | |
4827 | addu $tempreg,$tempreg,$at | |
4828 | For a local symbol, we want the same instruction | |
4829 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4830 | addiu instruction. |
ed6fb7bd SC |
4831 | */ |
4832 | ||
252b5132 RH |
4833 | expr1.X_add_number = offset_expr.X_add_number; |
4834 | offset_expr.X_add_number = 0; | |
4835 | frag_grow (32); | |
9117d219 NC |
4836 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4837 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
17a2f251 TS |
4838 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
4839 | tempreg, lw_reloc_type, mips_gp_register); | |
252b5132 RH |
4840 | if (expr1.X_add_number == 0) |
4841 | { | |
4842 | int off; | |
f9419b05 | 4843 | char *p; |
252b5132 RH |
4844 | |
4845 | if (breg == 0) | |
4846 | off = 0; | |
4847 | else | |
4848 | { | |
4849 | /* We're going to put in an addu instruction using | |
4850 | tempreg, so we may as well insert the nop right | |
4851 | now. */ | |
17a2f251 | 4852 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
4853 | off = 4; |
4854 | } | |
4855 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4856 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4857 | (breg == 0 | |
4858 | ? mips_opts.warn_about_macros | |
4859 | : 0)), | |
c4e7957c | 4860 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4861 | if (breg == 0) |
4862 | { | |
17a2f251 | 4863 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
4864 | p += 4; |
4865 | } | |
f899b4b8 | 4866 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 4867 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
4868 | /* FIXME: If breg == 0, and the next instruction uses |
4869 | $tempreg, then if this variant case is used an extra | |
4870 | nop will be generated. */ | |
4871 | } | |
4872 | else if (expr1.X_add_number >= -0x8000 | |
4873 | && expr1.X_add_number < 0x8000) | |
4874 | { | |
17a2f251 TS |
4875 | macro_build (NULL, &icnt, NULL, "nop", ""); |
4876 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
4877 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
c4e7957c TS |
4878 | frag_var (rs_machine_dependent, 0, 0, |
4879 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4880 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4881 | } |
4882 | else | |
4883 | { | |
4884 | int off1; | |
4885 | ||
4886 | /* If we are going to add in a base register, and the | |
4887 | target register and the base register are the same, | |
4888 | then we are using AT as a temporary register. Since | |
4889 | we want to load the constant into AT, we add our | |
4890 | current AT (from the global offset table) and the | |
4891 | register into the register now, and pretend we were | |
4892 | not using a base register. */ | |
4893 | if (breg != treg) | |
4894 | off1 = 0; | |
4895 | else | |
4896 | { | |
17a2f251 TS |
4897 | macro_build (NULL, &icnt, NULL, "nop", ""); |
4898 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4899 | treg, AT, breg); | |
252b5132 RH |
4900 | breg = 0; |
4901 | tempreg = treg; | |
4902 | off1 = -8; | |
4903 | } | |
4904 | ||
4905 | /* Set mips_optimize around the lui instruction to avoid | |
4906 | inserting an unnecessary nop after the lw. */ | |
4907 | hold_mips_optimize = mips_optimize; | |
4908 | mips_optimize = 2; | |
c4e7957c | 4909 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4910 | mips_optimize = hold_mips_optimize; |
4911 | ||
17a2f251 TS |
4912 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
4913 | AT, AT, BFD_RELOC_LO16); | |
4914 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4915 | tempreg, tempreg, AT); | |
c4e7957c TS |
4916 | frag_var (rs_machine_dependent, 0, 0, |
4917 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4918 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4919 | used_at = 1; |
4920 | } | |
4921 | } | |
f5040a92 AO |
4922 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
4923 | { | |
4924 | char *p = NULL; | |
4925 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
4926 | int adj = 0; | |
4927 | ||
4928 | /* If this is a reference to an external, and there is no | |
4929 | constant, or local symbol (*), with or without a | |
4930 | constant, we want | |
4931 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4932 | or if tempreg is PIC_CALL_REG | |
4933 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4934 | ||
4935 | If we have a small constant, and this is a reference to | |
4936 | an external symbol, we want | |
4937 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4938 | addiu $tempreg,$tempreg,<constant> | |
4939 | ||
4940 | If we have a large constant, and this is a reference to | |
4941 | an external symbol, we want | |
4942 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4943 | lui $at,<hiconstant> | |
4944 | addiu $at,$at,<loconstant> | |
4945 | addu $tempreg,$tempreg,$at | |
4946 | ||
4947 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
4948 | local symbols, even though it introduces an additional | |
4949 | instruction. */ | |
4950 | ||
4951 | frag_grow (28); | |
4952 | if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
4953 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4954 | if (offset_expr.X_add_number) | |
4955 | { | |
4956 | frag_now->tc_frag_data.tc_fr_offset = | |
4957 | expr1.X_add_number = offset_expr.X_add_number; | |
4958 | offset_expr.X_add_number = 0; | |
4959 | ||
17a2f251 TS |
4960 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
4961 | "t,o(b)", tempreg, lw_reloc_type, | |
4962 | mips_gp_register); | |
f5040a92 AO |
4963 | |
4964 | if (expr1.X_add_number >= -0x8000 | |
4965 | && expr1.X_add_number < 0x8000) | |
4966 | { | |
17a2f251 TS |
4967 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
4968 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
4969 | p = frag_var (rs_machine_dependent, 4, 0, |
4970 | RELAX_ENCODE (8, 4, 0, 0, 0, 0), | |
4971 | offset_expr.X_add_symbol, 0, NULL); | |
4972 | } | |
4973 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
4974 | { | |
4975 | int dreg; | |
4976 | ||
4977 | /* If we are going to add in a base register, and the | |
4978 | target register and the base register are the same, | |
4979 | then we are using AT as a temporary register. Since | |
4980 | we want to load the constant into AT, we add our | |
4981 | current AT (from the global offset table) and the | |
4982 | register into the register now, and pretend we were | |
4983 | not using a base register. */ | |
4984 | if (breg != treg) | |
4985 | dreg = tempreg; | |
4986 | else | |
4987 | { | |
4988 | assert (tempreg == AT); | |
17a2f251 TS |
4989 | macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN, |
4990 | "d,v,t", treg, AT, breg); | |
f5040a92 AO |
4991 | dreg = treg; |
4992 | adj = 4; | |
4993 | } | |
4994 | ||
17a2f251 TS |
4995 | macro_build_lui (NULL, &icnt, &expr1, AT); |
4996 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
4997 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4998 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4999 | dreg, dreg, AT); | |
f5040a92 AO |
5000 | |
5001 | p = frag_var (rs_machine_dependent, 4 + adj, 0, | |
5002 | RELAX_ENCODE (16 + adj, 4 + adj, | |
5003 | 0, 0, 0, 0), | |
5004 | offset_expr.X_add_symbol, 0, NULL); | |
5005 | ||
5006 | used_at = 1; | |
5007 | } | |
5008 | else | |
5009 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5010 | ||
5011 | offset_expr.X_add_number = expr1.X_add_number; | |
5012 | ||
f899b4b8 | 5013 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 | 5014 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP, |
f5040a92 AO |
5015 | mips_gp_register); |
5016 | if (adj) | |
5017 | { | |
17a2f251 | 5018 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5019 | treg, tempreg, breg); |
f5040a92 AO |
5020 | breg = 0; |
5021 | tempreg = treg; | |
5022 | } | |
5023 | } | |
5024 | else | |
5025 | { | |
17a2f251 TS |
5026 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5027 | "t,o(b)", tempreg, lw_reloc_type, | |
5028 | mips_gp_register); | |
f5040a92 AO |
5029 | if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP) |
5030 | p = frag_var (rs_machine_dependent, 0, 0, | |
5031 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5032 | offset_expr.X_add_symbol, 0, NULL); | |
5033 | } | |
5034 | ||
5035 | if (! p) | |
5036 | { | |
5037 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5038 | that this does not become a variant frag. */ | |
5039 | frag_wane (frag_now); | |
5040 | frag_new (0); | |
5041 | } | |
5042 | } | |
5043 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 RH |
5044 | { |
5045 | int gpdel; | |
f9419b05 | 5046 | char *p; |
9117d219 NC |
5047 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5048 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5049 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5050 | |
5051 | /* This is the large GOT case. If this is a reference to an | |
5052 | external symbol, and there is no constant, we want | |
5053 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5054 | addu $tempreg,$tempreg,$gp | |
5055 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5056 | or if tempreg is PIC_CALL_REG |
5057 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5058 | addu $tempreg,$tempreg,$gp | |
5059 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5060 | For a local symbol, we want |
5061 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5062 | nop | |
5063 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5064 | ||
5065 | If we have a small constant, and this is a reference to | |
5066 | an external symbol, we want | |
5067 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5068 | addu $tempreg,$tempreg,$gp | |
5069 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5070 | nop | |
5071 | addiu $tempreg,$tempreg,<constant> | |
5072 | For a local symbol, we want | |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5074 | nop | |
5075 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5076 | ||
5077 | If we have a large constant, and this is a reference to | |
5078 | an external symbol, we want | |
5079 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5080 | addu $tempreg,$tempreg,$gp | |
5081 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5082 | lui $at,<hiconstant> | |
5083 | addiu $at,$at,<loconstant> | |
5084 | addu $tempreg,$tempreg,$at | |
5085 | For a local symbol, we want | |
5086 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5087 | lui $at,<hiconstant> | |
5088 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5089 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5090 | */ |
438c16b8 | 5091 | |
252b5132 RH |
5092 | expr1.X_add_number = offset_expr.X_add_number; |
5093 | offset_expr.X_add_number = 0; | |
5094 | frag_grow (52); | |
f7ea7ef2 | 5095 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5096 | gpdel = 4; |
5097 | else | |
5098 | gpdel = 0; | |
9117d219 NC |
5099 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5100 | { | |
5101 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5102 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5103 | } | |
17a2f251 | 5104 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5105 | tempreg, lui_reloc_type); |
17a2f251 TS |
5106 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5107 | tempreg, tempreg, mips_gp_register); | |
5108 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5109 | tempreg, lw_reloc_type, tempreg); | |
252b5132 RH |
5110 | if (expr1.X_add_number == 0) |
5111 | { | |
5112 | int off; | |
5113 | ||
5114 | if (breg == 0) | |
5115 | off = 0; | |
5116 | else | |
5117 | { | |
5118 | /* We're going to put in an addu instruction using | |
5119 | tempreg, so we may as well insert the nop right | |
5120 | now. */ | |
17a2f251 | 5121 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
5122 | off = 4; |
5123 | } | |
5124 | ||
5125 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5126 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5127 | 8 + gpdel, 0, | |
5128 | (breg == 0 | |
5129 | ? mips_opts.warn_about_macros | |
5130 | : 0)), | |
c4e7957c | 5131 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5132 | } |
5133 | else if (expr1.X_add_number >= -0x8000 | |
5134 | && expr1.X_add_number < 0x8000) | |
5135 | { | |
17a2f251 TS |
5136 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5137 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
5138 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 RH |
5139 | |
5140 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5141 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5142 | (breg == 0 | |
5143 | ? mips_opts.warn_about_macros | |
5144 | : 0)), | |
c4e7957c | 5145 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5146 | } |
5147 | else | |
5148 | { | |
5149 | int adj, dreg; | |
5150 | ||
5151 | /* If we are going to add in a base register, and the | |
5152 | target register and the base register are the same, | |
5153 | then we are using AT as a temporary register. Since | |
5154 | we want to load the constant into AT, we add our | |
5155 | current AT (from the global offset table) and the | |
5156 | register into the register now, and pretend we were | |
5157 | not using a base register. */ | |
5158 | if (breg != treg) | |
5159 | { | |
5160 | adj = 0; | |
5161 | dreg = tempreg; | |
5162 | } | |
5163 | else | |
5164 | { | |
5165 | assert (tempreg == AT); | |
17a2f251 TS |
5166 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5167 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5168 | treg, AT, breg); | |
252b5132 RH |
5169 | dreg = treg; |
5170 | adj = 8; | |
5171 | } | |
5172 | ||
5173 | /* Set mips_optimize around the lui instruction to avoid | |
5174 | inserting an unnecessary nop after the lw. */ | |
5175 | hold_mips_optimize = mips_optimize; | |
5176 | mips_optimize = 2; | |
c4e7957c | 5177 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5178 | mips_optimize = hold_mips_optimize; |
5179 | ||
17a2f251 TS |
5180 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5181 | AT, AT, BFD_RELOC_LO16); | |
5182 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5183 | dreg, dreg, AT); | |
252b5132 RH |
5184 | |
5185 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5186 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5187 | 8 + gpdel, 0, | |
5188 | (breg == 0 | |
5189 | ? mips_opts.warn_about_macros | |
5190 | : 0)), | |
c4e7957c | 5191 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5192 | |
5193 | used_at = 1; | |
5194 | } | |
5195 | ||
5196 | if (gpdel > 0) | |
5197 | { | |
5198 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5199 | the first instruction on the main stream does not. */ |
17a2f251 | 5200 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5201 | p += 4; |
5202 | } | |
ed6fb7bd | 5203 | |
f899b4b8 TS |
5204 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5205 | tempreg, local_reloc_type, mips_gp_register); | |
252b5132 | 5206 | p += 4; |
f5040a92 | 5207 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5208 | && expr1.X_add_number < 0x8000) |
5209 | { | |
17a2f251 | 5210 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5211 | p += 4; |
f899b4b8 | 5212 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 5213 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 5214 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5215 | register, the external symbol case ended with a load, |
5216 | so if the symbol turns out to not be external, and | |
5217 | the next instruction uses tempreg, an unnecessary nop | |
5218 | will be inserted. */ | |
252b5132 RH |
5219 | } |
5220 | else | |
5221 | { | |
5222 | if (breg == treg) | |
5223 | { | |
5224 | /* We must add in the base register now, as in the | |
f5040a92 | 5225 | external symbol case. */ |
252b5132 | 5226 | assert (tempreg == AT); |
17a2f251 | 5227 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5228 | p += 4; |
17a2f251 TS |
5229 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5230 | treg, AT, breg); | |
252b5132 RH |
5231 | p += 4; |
5232 | tempreg = treg; | |
5233 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5234 | it in in both cases. */ |
252b5132 RH |
5235 | breg = 0; |
5236 | } | |
5237 | ||
5238 | macro_build_lui (p, &icnt, &expr1, AT); | |
5239 | p += 4; | |
17a2f251 TS |
5240 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5241 | AT, AT, BFD_RELOC_LO16); | |
252b5132 | 5242 | p += 4; |
17a2f251 TS |
5243 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5244 | tempreg, tempreg, AT); | |
252b5132 RH |
5245 | p += 4; |
5246 | } | |
5247 | } | |
f5040a92 AO |
5248 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5249 | { | |
5250 | char *p = NULL; | |
5251 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; | |
5252 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
5253 | int adj = 0; | |
5254 | ||
5255 | /* This is the large GOT case. If this is a reference to an | |
5256 | external symbol, and there is no constant, we want | |
5257 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5258 | add $tempreg,$tempreg,$gp | |
5259 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5260 | or if tempreg is PIC_CALL_REG | |
5261 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5262 | add $tempreg,$tempreg,$gp | |
5263 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5264 | ||
5265 | If we have a small constant, and this is a reference to | |
5266 | an external symbol, we want | |
5267 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5268 | add $tempreg,$tempreg,$gp | |
5269 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5270 | addi $tempreg,$tempreg,<constant> | |
5271 | ||
5272 | If we have a large constant, and this is a reference to | |
5273 | an external symbol, we want | |
5274 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5275 | addu $tempreg,$tempreg,$gp | |
5276 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5277 | lui $at,<hiconstant> | |
5278 | addi $at,$at,<loconstant> | |
5279 | add $tempreg,$tempreg,$at | |
5280 | ||
5281 | If we have NewABI, and we know it's a local symbol, we want | |
5282 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5283 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5284 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5285 | ||
5286 | frag_grow (40); | |
5287 | ||
5288 | frag_now->tc_frag_data.tc_fr_offset = | |
5289 | expr1.X_add_number = offset_expr.X_add_number; | |
5290 | offset_expr.X_add_number = 0; | |
5291 | ||
5292 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5293 | { | |
5294 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5295 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5296 | } | |
17a2f251 | 5297 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
f5040a92 | 5298 | tempreg, lui_reloc_type); |
17a2f251 TS |
5299 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5300 | tempreg, tempreg, mips_gp_register); | |
5301 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
5302 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
5303 | ||
5304 | if (expr1.X_add_number == 0) | |
5305 | { | |
5306 | p = frag_var (rs_machine_dependent, 8, 0, | |
5307 | RELAX_ENCODE (12, 8, 0, 4, 0, | |
5308 | mips_opts.warn_about_macros), | |
5309 | offset_expr.X_add_symbol, 0, NULL); | |
684022ea | 5310 | } |
f5040a92 AO |
5311 | else if (expr1.X_add_number >= -0x8000 |
5312 | && expr1.X_add_number < 0x8000) | |
5313 | { | |
17a2f251 TS |
5314 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5315 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
5316 | p = frag_var (rs_machine_dependent, 8, 0, |
5317 | RELAX_ENCODE (16, 8, 0, 4, 0, | |
5318 | mips_opts.warn_about_macros), | |
5319 | offset_expr.X_add_symbol, 0, NULL); | |
5320 | } | |
5321 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5322 | { | |
5323 | int dreg; | |
5324 | ||
5325 | /* If we are going to add in a base register, and the | |
5326 | target register and the base register are the same, | |
5327 | then we are using AT as a temporary register. Since | |
5328 | we want to load the constant into AT, we add our | |
5329 | current AT (from the global offset table) and the | |
5330 | register into the register now, and pretend we were | |
5331 | not using a base register. */ | |
5332 | if (breg != treg) | |
5333 | dreg = tempreg; | |
5334 | else | |
5335 | { | |
5336 | assert (tempreg == AT); | |
17a2f251 TS |
5337 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5338 | treg, AT, breg); | |
f5040a92 AO |
5339 | dreg = treg; |
5340 | adj = 4; | |
5341 | } | |
5342 | ||
5343 | /* Set mips_optimize around the lui instruction to avoid | |
5344 | inserting an unnecessary nop after the lw. */ | |
17a2f251 TS |
5345 | macro_build_lui (NULL, &icnt, &expr1, AT); |
5346 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5347 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
5348 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5349 | dreg, dreg, AT); | |
f5040a92 AO |
5350 | |
5351 | p = frag_var (rs_machine_dependent, 8 + adj, 0, | |
5352 | RELAX_ENCODE (24 + adj, 8 + adj, | |
5353 | 0, 4, 0, | |
5354 | (breg == 0 | |
5355 | ? mips_opts.warn_about_macros | |
5356 | : 0)), | |
5357 | offset_expr.X_add_symbol, 0, NULL); | |
5358 | ||
5359 | used_at = 1; | |
5360 | } | |
5361 | else | |
5362 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5363 | ||
5364 | offset_expr.X_add_number = expr1.X_add_number; | |
f899b4b8 | 5365 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5366 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5367 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5368 | tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 AO |
5369 | if (adj) |
5370 | { | |
17a2f251 TS |
5371 | macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5372 | treg, tempreg, breg); | |
f5040a92 AO |
5373 | breg = 0; |
5374 | tempreg = treg; | |
5375 | } | |
5376 | } | |
252b5132 RH |
5377 | else if (mips_pic == EMBEDDED_PIC) |
5378 | { | |
5379 | /* We use | |
cdf6fd85 | 5380 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5381 | */ |
17a2f251 TS |
5382 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5383 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
5384 | } |
5385 | else | |
5386 | abort (); | |
5387 | ||
5388 | if (breg != 0) | |
4d34fb5f TS |
5389 | { |
5390 | char *s; | |
5391 | ||
5392 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5393 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5394 | else |
f899b4b8 | 5395 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5396 | |
17a2f251 | 5397 | macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5398 | } |
252b5132 RH |
5399 | |
5400 | if (! used_at) | |
5401 | return; | |
5402 | ||
5403 | break; | |
5404 | ||
5405 | case M_J_A: | |
5406 | /* The j instruction may not be used in PIC code, since it | |
5407 | requires an absolute address. We convert it to a b | |
5408 | instruction. */ | |
5409 | if (mips_pic == NO_PIC) | |
17a2f251 | 5410 | macro_build (NULL, &icnt, &offset_expr, "j", "a"); |
252b5132 | 5411 | else |
17a2f251 | 5412 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
5413 | return; |
5414 | ||
5415 | /* The jal instructions must be handled as macros because when | |
5416 | generating PIC code they expand to multi-instruction | |
5417 | sequences. Normally they are simple instructions. */ | |
5418 | case M_JAL_1: | |
5419 | dreg = RA; | |
5420 | /* Fall through. */ | |
5421 | case M_JAL_2: | |
5422 | if (mips_pic == NO_PIC | |
5423 | || mips_pic == EMBEDDED_PIC) | |
17a2f251 | 5424 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5425 | else if (mips_pic == SVR4_PIC) |
5426 | { | |
5427 | if (sreg != PIC_CALL_REG) | |
5428 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5429 | |
17a2f251 | 5430 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5431 | if (! HAVE_NEWABI) |
252b5132 | 5432 | { |
6478892d TS |
5433 | if (mips_cprestore_offset < 0) |
5434 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5435 | else | |
5436 | { | |
7a621144 DJ |
5437 | if (! mips_frame_reg_valid) |
5438 | { | |
5439 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5440 | /* Quiet this warning. */ | |
5441 | mips_frame_reg_valid = 1; | |
5442 | } | |
5443 | if (! mips_cprestore_valid) | |
5444 | { | |
5445 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5446 | /* Quiet this warning. */ | |
5447 | mips_cprestore_valid = 1; | |
5448 | } | |
6478892d | 5449 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5450 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5451 | ADDRESS_LOAD_INSN, |
5452 | mips_gp_register, | |
5453 | mips_frame_reg); | |
6478892d | 5454 | } |
252b5132 RH |
5455 | } |
5456 | } | |
5457 | else | |
5458 | abort (); | |
5459 | ||
5460 | return; | |
5461 | ||
5462 | case M_JAL_A: | |
5463 | if (mips_pic == NO_PIC) | |
17a2f251 | 5464 | macro_build (NULL, &icnt, &offset_expr, "jal", "a"); |
252b5132 RH |
5465 | else if (mips_pic == SVR4_PIC) |
5466 | { | |
f9419b05 TS |
5467 | char *p; |
5468 | ||
252b5132 RH |
5469 | /* If this is a reference to an external symbol, and we are |
5470 | using a small GOT, we want | |
5471 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5472 | nop | |
f9419b05 | 5473 | jalr $ra,$25 |
252b5132 RH |
5474 | nop |
5475 | lw $gp,cprestore($sp) | |
5476 | The cprestore value is set using the .cprestore | |
5477 | pseudo-op. If we are using a big GOT, we want | |
5478 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5479 | addu $25,$25,$gp | |
5480 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5481 | nop | |
f9419b05 | 5482 | jalr $ra,$25 |
252b5132 RH |
5483 | nop |
5484 | lw $gp,cprestore($sp) | |
5485 | If the symbol is not external, we want | |
5486 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5487 | nop | |
5488 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5489 | jalr $ra,$25 |
252b5132 | 5490 | nop |
438c16b8 | 5491 | lw $gp,cprestore($sp) |
f5040a92 AO |
5492 | |
5493 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5494 | sequences above, minus nops, unless the symbol is local, | |
5495 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5496 | GOT_DISP. */ | |
438c16b8 | 5497 | if (HAVE_NEWABI) |
252b5132 | 5498 | { |
f5040a92 AO |
5499 | if (! mips_big_got) |
5500 | { | |
5501 | frag_grow (4); | |
17a2f251 TS |
5502 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5503 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 AO |
5504 | mips_gp_register); |
5505 | frag_var (rs_machine_dependent, 0, 0, | |
5506 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5507 | offset_expr.X_add_symbol, 0, NULL); | |
5508 | } | |
5509 | else | |
5510 | { | |
5511 | frag_grow (20); | |
17a2f251 TS |
5512 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5513 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5514 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5515 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5516 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5517 | "t,o(b)", PIC_CALL_REG, | |
5518 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
f5040a92 AO |
5519 | p = frag_var (rs_machine_dependent, 8, 0, |
5520 | RELAX_ENCODE (12, 8, 0, 4, 0, 0), | |
5521 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
5522 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5523 | "t,o(b)", PIC_CALL_REG, | |
17a2f251 | 5524 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5525 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
dc9461f6 | 5526 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5527 | BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 | 5528 | } |
684022ea | 5529 | |
438c16b8 | 5530 | macro_build_jalr (icnt, &offset_expr); |
252b5132 RH |
5531 | } |
5532 | else | |
5533 | { | |
438c16b8 TS |
5534 | frag_grow (40); |
5535 | if (! mips_big_got) | |
5536 | { | |
17a2f251 TS |
5537 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5538 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
5539 | mips_gp_register); | |
5540 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5541 | p = frag_var (rs_machine_dependent, 4, 0, |
5542 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5543 | offset_expr.X_add_symbol, 0, NULL); | |
5544 | } | |
252b5132 | 5545 | else |
252b5132 | 5546 | { |
438c16b8 TS |
5547 | int gpdel; |
5548 | ||
5549 | if (reg_needs_delay (mips_gp_register)) | |
5550 | gpdel = 4; | |
5551 | else | |
5552 | gpdel = 0; | |
17a2f251 TS |
5553 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5554 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5555 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5556 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5557 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5558 | "t,o(b)", PIC_CALL_REG, | |
5559 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5560 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5561 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5562 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5563 | 8 + gpdel, 0, 0), | |
5564 | offset_expr.X_add_symbol, 0, NULL); | |
5565 | if (gpdel > 0) | |
5566 | { | |
17a2f251 | 5567 | macro_build (p, &icnt, NULL, "nop", ""); |
438c16b8 TS |
5568 | p += 4; |
5569 | } | |
f899b4b8 | 5570 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 TS |
5571 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, |
5572 | mips_gp_register); | |
438c16b8 | 5573 | p += 4; |
17a2f251 | 5574 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5575 | p += 4; |
5576 | } | |
f899b4b8 | 5577 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
438c16b8 | 5578 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5579 | BFD_RELOC_LO16); |
438c16b8 TS |
5580 | macro_build_jalr (icnt, &offset_expr); |
5581 | ||
6478892d TS |
5582 | if (mips_cprestore_offset < 0) |
5583 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5584 | else | |
5585 | { | |
7a621144 DJ |
5586 | if (! mips_frame_reg_valid) |
5587 | { | |
5588 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5589 | /* Quiet this warning. */ | |
5590 | mips_frame_reg_valid = 1; | |
5591 | } | |
5592 | if (! mips_cprestore_valid) | |
5593 | { | |
5594 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5595 | /* Quiet this warning. */ | |
5596 | mips_cprestore_valid = 1; | |
5597 | } | |
6478892d | 5598 | if (mips_opts.noreorder) |
17a2f251 | 5599 | macro_build (NULL, &icnt, NULL, "nop", ""); |
6478892d | 5600 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5601 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5602 | ADDRESS_LOAD_INSN, |
5603 | mips_gp_register, | |
5604 | mips_frame_reg); | |
6478892d | 5605 | } |
252b5132 RH |
5606 | } |
5607 | } | |
5608 | else if (mips_pic == EMBEDDED_PIC) | |
5609 | { | |
17a2f251 | 5610 | macro_build (NULL, &icnt, &offset_expr, "bal", "p"); |
252b5132 RH |
5611 | /* The linker may expand the call to a longer sequence which |
5612 | uses $at, so we must break rather than return. */ | |
5613 | break; | |
5614 | } | |
5615 | else | |
5616 | abort (); | |
5617 | ||
5618 | return; | |
5619 | ||
5620 | case M_LB_AB: | |
5621 | s = "lb"; | |
5622 | goto ld; | |
5623 | case M_LBU_AB: | |
5624 | s = "lbu"; | |
5625 | goto ld; | |
5626 | case M_LH_AB: | |
5627 | s = "lh"; | |
5628 | goto ld; | |
5629 | case M_LHU_AB: | |
5630 | s = "lhu"; | |
5631 | goto ld; | |
5632 | case M_LW_AB: | |
5633 | s = "lw"; | |
5634 | goto ld; | |
5635 | case M_LWC0_AB: | |
5636 | s = "lwc0"; | |
bdaaa2e1 | 5637 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5638 | coproc = 1; |
5639 | goto ld; | |
5640 | case M_LWC1_AB: | |
5641 | s = "lwc1"; | |
bdaaa2e1 | 5642 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5643 | coproc = 1; |
5644 | goto ld; | |
5645 | case M_LWC2_AB: | |
5646 | s = "lwc2"; | |
bdaaa2e1 | 5647 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5648 | coproc = 1; |
5649 | goto ld; | |
5650 | case M_LWC3_AB: | |
5651 | s = "lwc3"; | |
bdaaa2e1 | 5652 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5653 | coproc = 1; |
5654 | goto ld; | |
5655 | case M_LWL_AB: | |
5656 | s = "lwl"; | |
5657 | lr = 1; | |
5658 | goto ld; | |
5659 | case M_LWR_AB: | |
5660 | s = "lwr"; | |
5661 | lr = 1; | |
5662 | goto ld; | |
5663 | case M_LDC1_AB: | |
fef14a42 | 5664 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5665 | { |
5666 | as_bad (_("opcode not supported on this processor")); | |
5667 | return; | |
5668 | } | |
5669 | s = "ldc1"; | |
bdaaa2e1 | 5670 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5671 | coproc = 1; |
5672 | goto ld; | |
5673 | case M_LDC2_AB: | |
5674 | s = "ldc2"; | |
bdaaa2e1 | 5675 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5676 | coproc = 1; |
5677 | goto ld; | |
5678 | case M_LDC3_AB: | |
5679 | s = "ldc3"; | |
bdaaa2e1 | 5680 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5681 | coproc = 1; |
5682 | goto ld; | |
5683 | case M_LDL_AB: | |
5684 | s = "ldl"; | |
5685 | lr = 1; | |
5686 | goto ld; | |
5687 | case M_LDR_AB: | |
5688 | s = "ldr"; | |
5689 | lr = 1; | |
5690 | goto ld; | |
5691 | case M_LL_AB: | |
5692 | s = "ll"; | |
5693 | goto ld; | |
5694 | case M_LLD_AB: | |
5695 | s = "lld"; | |
5696 | goto ld; | |
5697 | case M_LWU_AB: | |
5698 | s = "lwu"; | |
5699 | ld: | |
5700 | if (breg == treg || coproc || lr) | |
5701 | { | |
5702 | tempreg = AT; | |
5703 | used_at = 1; | |
5704 | } | |
5705 | else | |
5706 | { | |
5707 | tempreg = treg; | |
5708 | used_at = 0; | |
5709 | } | |
5710 | goto ld_st; | |
5711 | case M_SB_AB: | |
5712 | s = "sb"; | |
5713 | goto st; | |
5714 | case M_SH_AB: | |
5715 | s = "sh"; | |
5716 | goto st; | |
5717 | case M_SW_AB: | |
5718 | s = "sw"; | |
5719 | goto st; | |
5720 | case M_SWC0_AB: | |
5721 | s = "swc0"; | |
bdaaa2e1 | 5722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5723 | coproc = 1; |
5724 | goto st; | |
5725 | case M_SWC1_AB: | |
5726 | s = "swc1"; | |
bdaaa2e1 | 5727 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5728 | coproc = 1; |
5729 | goto st; | |
5730 | case M_SWC2_AB: | |
5731 | s = "swc2"; | |
bdaaa2e1 | 5732 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5733 | coproc = 1; |
5734 | goto st; | |
5735 | case M_SWC3_AB: | |
5736 | s = "swc3"; | |
bdaaa2e1 | 5737 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5738 | coproc = 1; |
5739 | goto st; | |
5740 | case M_SWL_AB: | |
5741 | s = "swl"; | |
5742 | goto st; | |
5743 | case M_SWR_AB: | |
5744 | s = "swr"; | |
5745 | goto st; | |
5746 | case M_SC_AB: | |
5747 | s = "sc"; | |
5748 | goto st; | |
5749 | case M_SCD_AB: | |
5750 | s = "scd"; | |
5751 | goto st; | |
5752 | case M_SDC1_AB: | |
fef14a42 | 5753 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5754 | { |
5755 | as_bad (_("opcode not supported on this processor")); | |
5756 | return; | |
5757 | } | |
5758 | s = "sdc1"; | |
5759 | coproc = 1; | |
bdaaa2e1 | 5760 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5761 | goto st; |
5762 | case M_SDC2_AB: | |
5763 | s = "sdc2"; | |
bdaaa2e1 | 5764 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5765 | coproc = 1; |
5766 | goto st; | |
5767 | case M_SDC3_AB: | |
5768 | s = "sdc3"; | |
bdaaa2e1 | 5769 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5770 | coproc = 1; |
5771 | goto st; | |
5772 | case M_SDL_AB: | |
5773 | s = "sdl"; | |
5774 | goto st; | |
5775 | case M_SDR_AB: | |
5776 | s = "sdr"; | |
5777 | st: | |
5778 | tempreg = AT; | |
5779 | used_at = 1; | |
5780 | ld_st: | |
bdaaa2e1 | 5781 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5782 | if (mask == M_LWC1_AB |
5783 | || mask == M_SWC1_AB | |
5784 | || mask == M_LDC1_AB | |
5785 | || mask == M_SDC1_AB | |
5786 | || mask == M_L_DAB | |
5787 | || mask == M_S_DAB) | |
5788 | fmt = "T,o(b)"; | |
5789 | else if (coproc) | |
5790 | fmt = "E,o(b)"; | |
5791 | else | |
5792 | fmt = "t,o(b)"; | |
5793 | ||
afdbd6d0 CD |
5794 | /* For embedded PIC, we allow loads where the offset is calculated |
5795 | by subtracting a symbol in the current segment from an unknown | |
5796 | symbol, relative to a base register, e.g.: | |
5797 | <op> $treg, <sym>-<localsym>($breg) | |
5798 | This is used by the compiler for switch statements. */ | |
76b3015f | 5799 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5800 | && offset_expr.X_op == O_subtract |
5801 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5802 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5803 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5804 | && (S_GET_SEGMENT | |
5805 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5806 | ->X_add_symbol) | |
5807 | == now_seg))) | |
5808 | && breg != 0 | |
5809 | && (offset_expr.X_add_number == 0 | |
5810 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5811 | { | |
5812 | /* For this case, we output the instructions: | |
5813 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5814 | addiu $tempreg,$tempreg,$breg | |
5815 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5816 | If the relocation would fit entirely in 16 bits, it would be | |
5817 | nice to emit: | |
5818 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5819 | instead, but that seems quite difficult. */ | |
17a2f251 TS |
5820 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
5821 | BFD_RELOC_PCREL_HI16_S); | |
5822 | macro_build (NULL, &icnt, NULL, | |
afdbd6d0 CD |
5823 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5824 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
b7c7d6c1 | 5825 | ? "addu" : "daddu"), |
afdbd6d0 | 5826 | "d,v,t", tempreg, tempreg, breg); |
17a2f251 TS |
5827 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
5828 | BFD_RELOC_PCREL_LO16, tempreg); | |
afdbd6d0 CD |
5829 | if (! used_at) |
5830 | return; | |
5831 | break; | |
5832 | } | |
5833 | ||
252b5132 RH |
5834 | if (offset_expr.X_op != O_constant |
5835 | && offset_expr.X_op != O_symbol) | |
5836 | { | |
5837 | as_bad (_("expression too complex")); | |
5838 | offset_expr.X_op = O_constant; | |
5839 | } | |
5840 | ||
5841 | /* A constant expression in PIC code can be handled just as it | |
5842 | is in non PIC code. */ | |
5843 | if (mips_pic == NO_PIC | |
5844 | || offset_expr.X_op == O_constant) | |
5845 | { | |
f9419b05 TS |
5846 | char *p; |
5847 | ||
252b5132 RH |
5848 | /* If this is a reference to a GP relative symbol, and there |
5849 | is no base register, we want | |
cdf6fd85 | 5850 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5851 | Otherwise, if there is no base register, we want |
5852 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5853 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5854 | If we have a constant, we need two instructions anyhow, | |
5855 | so we always use the latter form. | |
5856 | ||
5857 | If we have a base register, and this is a reference to a | |
5858 | GP relative symbol, we want | |
5859 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5860 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5861 | Otherwise we want |
5862 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5863 | addu $tempreg,$tempreg,$breg | |
5864 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5865 | With a constant we always use the latter case. |
76b3015f | 5866 | |
d6bc6245 TS |
5867 | With 64bit address space and no base register and $at usable, |
5868 | we want | |
5869 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5870 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5871 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5872 | dsll32 $tempreg,0 | |
5873 | daddu $tempreg,$at | |
5874 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5875 | If we have a base register, we want | |
5876 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5877 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5878 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5879 | daddu $at,$breg | |
5880 | dsll32 $tempreg,0 | |
5881 | daddu $tempreg,$at | |
5882 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5883 | ||
5884 | Without $at we can't generate the optimal path for superscalar | |
5885 | processors here since this would require two temporary registers. | |
5886 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5887 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5888 | dsll $tempreg,16 | |
5889 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5890 | dsll $tempreg,16 | |
5891 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5892 | If we have a base register, we want | |
5893 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5894 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5895 | dsll $tempreg,16 | |
5896 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5897 | dsll $tempreg,16 | |
5898 | daddu $tempreg,$tempreg,$breg | |
5899 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5900 | |
5901 | If we have 64-bit addresses, as an optimization, for | |
5902 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5903 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5904 | mechanism since it is more efficient. Note that due to |
5905 | the signed offset used by memory operations, the 32-bit | |
5906 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5907 | probably attempt to generate 64-bit constants more |
5908 | efficiently in general. | |
9214dd3b AO |
5909 | |
5910 | As an extension for architectures with 64-bit registers, | |
5911 | we don't truncate 64-bit addresses given as literal | |
5912 | constants down to 32 bits, to support existing practice | |
5913 | in the mips64 Linux (the kernel), that compiles source | |
5914 | files with -mabi=64, assembling them as o32 or n32 (with | |
5915 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5916 | the whole kernel is loaded into a memory region that is | |
5917 | addressible with sign-extended 32-bit addresses, it is | |
5918 | wasteful to compute the upper 32 bits of every | |
5919 | non-literal address, that takes more space and time. | |
5920 | Some day this should probably be implemented as an | |
5921 | assembler option, such that the kernel doesn't have to | |
5922 | use such ugly hacks, even though it will still have to | |
5923 | end up converting the binary to ELF32 for a number of | |
5924 | platforms whose boot loaders don't support ELF64 | |
5925 | binaries. */ | |
5a7a0b7b AO |
5926 | if ((offset_expr.X_op != O_constant && HAVE_64BIT_ADDRESSES) |
5927 | || (offset_expr.X_op == O_constant | |
eb0a7d52 | 5928 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000) |
5a7a0b7b | 5929 | && HAVE_64BIT_ADDRESS_CONSTANTS)) |
d6bc6245 TS |
5930 | { |
5931 | p = NULL; | |
5932 | ||
5933 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5934 | hold the data for such large chunks. */ | |
5935 | ||
460597ba | 5936 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
5937 | { |
5938 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 5939 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 5940 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 5941 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 5942 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5943 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 5944 | if (breg != 0) |
17a2f251 TS |
5945 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
5946 | AT, AT, breg); | |
5947 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
5948 | tempreg, tempreg, 0); | |
5949 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
5950 | tempreg, tempreg, AT); | |
5951 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5952 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
5953 | used_at = 1; |
5954 | } | |
5955 | else | |
5956 | { | |
5957 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 5958 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 5959 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
5960 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
5961 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5962 | tempreg, tempreg, 16); | |
d6bc6245 | 5963 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
5964 | tempreg, tempreg, BFD_RELOC_HI16_S); |
5965 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5966 | tempreg, tempreg, 16); | |
d6bc6245 | 5967 | if (breg != 0) |
17a2f251 TS |
5968 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
5969 | tempreg, tempreg, breg); | |
5970 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5971 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
5972 | } |
5973 | ||
5974 | return; | |
5975 | } | |
5a7a0b7b | 5976 | else if (offset_expr.X_op == O_constant |
eb0a7d52 | 5977 | && !HAVE_64BIT_ADDRESS_CONSTANTS |
5a7a0b7b AO |
5978 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5979 | as_bad (_("load/store address overflow (max 32 bits)")); | |
76b3015f | 5980 | |
252b5132 RH |
5981 | if (breg == 0) |
5982 | { | |
e7d556df | 5983 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5984 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5985 | p = NULL; | |
5986 | else | |
5987 | { | |
5988 | frag_grow (20); | |
17a2f251 TS |
5989 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
5990 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
5991 | p = frag_var (rs_machine_dependent, 8, 0, |
5992 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5993 | (mips_opts.warn_about_macros | |
5994 | || (used_at | |
5995 | && mips_opts.noat))), | |
956cd1d6 | 5996 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5997 | used_at = 0; |
5998 | } | |
5999 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6000 | if (p != NULL) | |
6001 | p += 4; | |
6002 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6003 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6004 | } |
6005 | else | |
6006 | { | |
e7d556df | 6007 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6008 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6009 | p = NULL; | |
6010 | else | |
6011 | { | |
6012 | frag_grow (28); | |
17a2f251 TS |
6013 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6014 | tempreg, breg, mips_gp_register); | |
6015 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6016 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6017 | p = frag_var (rs_machine_dependent, 12, 0, |
6018 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 6019 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6020 | } |
6021 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6022 | if (p != NULL) | |
6023 | p += 4; | |
17a2f251 TS |
6024 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6025 | tempreg, tempreg, breg); | |
252b5132 RH |
6026 | if (p != NULL) |
6027 | p += 4; | |
6028 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6029 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6030 | } |
6031 | } | |
6032 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6033 | { | |
f9419b05 | 6034 | char *p; |
ed6fb7bd | 6035 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6036 | |
252b5132 RH |
6037 | /* If this is a reference to an external symbol, we want |
6038 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6039 | nop | |
6040 | <op> $treg,0($tempreg) | |
6041 | Otherwise we want | |
6042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6043 | nop | |
6044 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6045 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6046 | |
6047 | For NewABI, we want | |
6048 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6049 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6050 | ||
252b5132 RH |
6051 | If there is a base register, we add it to $tempreg before |
6052 | the <op>. If there is a constant, we stick it in the | |
6053 | <op> instruction. We don't handle constants larger than | |
6054 | 16 bits, because we have no way to load the upper 16 bits | |
6055 | (actually, we could handle them for the subset of cases | |
6056 | in which we are not using $at). */ | |
6057 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6058 | if (HAVE_NEWABI) |
6059 | { | |
17a2f251 TS |
6060 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6061 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
6062 | mips_gp_register); | |
f5040a92 | 6063 | if (breg != 0) |
17a2f251 TS |
6064 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6065 | tempreg, tempreg, breg); | |
6066 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6067 | BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
f5040a92 AO |
6068 | |
6069 | if (! used_at) | |
6070 | return; | |
6071 | ||
6072 | break; | |
6073 | } | |
252b5132 RH |
6074 | expr1.X_add_number = offset_expr.X_add_number; |
6075 | offset_expr.X_add_number = 0; | |
6076 | if (expr1.X_add_number < -0x8000 | |
6077 | || expr1.X_add_number >= 0x8000) | |
6078 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6079 | frag_grow (20); | |
17a2f251 TS |
6080 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6081 | tempreg, lw_reloc_type, mips_gp_register); | |
6082 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
bdaaa2e1 | 6083 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 6084 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 6085 | offset_expr.X_add_symbol, 0, NULL); |
f899b4b8 | 6086 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 6087 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 6088 | if (breg != 0) |
17a2f251 TS |
6089 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6090 | tempreg, tempreg, breg); | |
6091 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6092 | tempreg); | |
252b5132 | 6093 | } |
f5040a92 | 6094 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 RH |
6095 | { |
6096 | int gpdel; | |
f9419b05 | 6097 | char *p; |
252b5132 RH |
6098 | |
6099 | /* If this is a reference to an external symbol, we want | |
6100 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6101 | addu $tempreg,$tempreg,$gp | |
6102 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6103 | <op> $treg,0($tempreg) | |
6104 | Otherwise we want | |
6105 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6106 | nop | |
6107 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6108 | <op> $treg,0($tempreg) | |
6109 | If there is a base register, we add it to $tempreg before | |
6110 | the <op>. If there is a constant, we stick it in the | |
6111 | <op> instruction. We don't handle constants larger than | |
6112 | 16 bits, because we have no way to load the upper 16 bits | |
6113 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6114 | in which we are not using $at). */ |
252b5132 RH |
6115 | assert (offset_expr.X_op == O_symbol); |
6116 | expr1.X_add_number = offset_expr.X_add_number; | |
6117 | offset_expr.X_add_number = 0; | |
6118 | if (expr1.X_add_number < -0x8000 | |
6119 | || expr1.X_add_number >= 0x8000) | |
6120 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
f7ea7ef2 | 6121 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6122 | gpdel = 4; |
6123 | else | |
6124 | gpdel = 0; | |
6125 | frag_grow (36); | |
17a2f251 TS |
6126 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6127 | BFD_RELOC_MIPS_GOT_HI16); | |
6128 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6129 | tempreg, tempreg, mips_gp_register); | |
6130 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6131 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
252b5132 RH |
6132 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
6133 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6134 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6135 | if (gpdel > 0) |
6136 | { | |
17a2f251 | 6137 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6138 | p += 4; |
6139 | } | |
17a2f251 TS |
6140 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6141 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6142 | p += 4; |
17a2f251 | 6143 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 6144 | p += 4; |
17a2f251 TS |
6145 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6146 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6147 | if (breg != 0) |
17a2f251 TS |
6148 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6149 | tempreg, tempreg, breg); | |
6150 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6151 | tempreg); | |
252b5132 | 6152 | } |
f5040a92 AO |
6153 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6154 | { | |
6155 | char *p; | |
6156 | int bregsz = breg != 0 ? 4 : 0; | |
6157 | ||
6158 | /* If this is a reference to an external symbol, we want | |
6159 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6160 | add $tempreg,$tempreg,$gp | |
6161 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6162 | <op> $treg,<ofst>($tempreg) | |
6163 | Otherwise, for local symbols, we want: | |
6164 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6165 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6166 | assert (offset_expr.X_op == O_symbol); | |
6167 | frag_now->tc_frag_data.tc_fr_offset = | |
6168 | expr1.X_add_number = offset_expr.X_add_number; | |
6169 | offset_expr.X_add_number = 0; | |
6170 | if (expr1.X_add_number < -0x8000 | |
6171 | || expr1.X_add_number >= 0x8000) | |
6172 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6173 | frag_grow (36); | |
17a2f251 TS |
6174 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6175 | BFD_RELOC_MIPS_GOT_HI16); | |
6176 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6177 | tempreg, tempreg, mips_gp_register); | |
6178 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6179 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6180 | if (breg != 0) |
17a2f251 TS |
6181 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6182 | tempreg, tempreg, breg); | |
6183 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6184 | tempreg); | |
684022ea | 6185 | |
f5040a92 AO |
6186 | offset_expr.X_add_number = expr1.X_add_number; |
6187 | p = frag_var (rs_machine_dependent, 12 + bregsz, 0, | |
6188 | RELAX_ENCODE (16 + bregsz, 8 + bregsz, | |
6189 | 0, 4 + bregsz, 0, 0), | |
6190 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 | 6191 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6192 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f5040a92 | 6193 | if (breg != 0) |
17a2f251 TS |
6194 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6195 | tempreg, tempreg, breg); | |
f5040a92 | 6196 | macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg, |
17a2f251 | 6197 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 | 6198 | } |
252b5132 RH |
6199 | else if (mips_pic == EMBEDDED_PIC) |
6200 | { | |
6201 | /* If there is no base register, we want | |
cdf6fd85 | 6202 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6203 | If there is a base register, we want |
6204 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6205 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6206 | */ |
6207 | assert (offset_expr.X_op == O_symbol); | |
6208 | if (breg == 0) | |
6209 | { | |
17a2f251 TS |
6210 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
6211 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
6212 | used_at = 0; |
6213 | } | |
6214 | else | |
6215 | { | |
17a2f251 TS |
6216 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6217 | tempreg, breg, mips_gp_register); | |
6218 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6219 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6220 | } |
6221 | } | |
6222 | else | |
6223 | abort (); | |
6224 | ||
6225 | if (! used_at) | |
6226 | return; | |
6227 | ||
6228 | break; | |
6229 | ||
6230 | case M_LI: | |
6231 | case M_LI_S: | |
6232 | load_register (&icnt, treg, &imm_expr, 0); | |
6233 | return; | |
6234 | ||
6235 | case M_DLI: | |
6236 | load_register (&icnt, treg, &imm_expr, 1); | |
6237 | return; | |
6238 | ||
6239 | case M_LI_SS: | |
6240 | if (imm_expr.X_op == O_constant) | |
6241 | { | |
6242 | load_register (&icnt, AT, &imm_expr, 0); | |
17a2f251 | 6243 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6244 | break; |
6245 | } | |
6246 | else | |
6247 | { | |
6248 | assert (offset_expr.X_op == O_symbol | |
6249 | && strcmp (segment_name (S_GET_SEGMENT | |
6250 | (offset_expr.X_add_symbol)), | |
6251 | ".lit4") == 0 | |
6252 | && offset_expr.X_add_number == 0); | |
17a2f251 TS |
6253 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg, |
6254 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6255 | return; |
6256 | } | |
6257 | ||
6258 | case M_LI_D: | |
ca4e0257 RS |
6259 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6260 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6261 | order 32 bits of the value and the low order 32 bits are either | |
6262 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6263 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6264 | { | |
ca4e0257 | 6265 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6266 | load_register (&icnt, treg, &imm_expr, 1); |
6267 | else | |
6268 | { | |
6269 | int hreg, lreg; | |
6270 | ||
6271 | if (target_big_endian) | |
6272 | { | |
6273 | hreg = treg; | |
6274 | lreg = treg + 1; | |
6275 | } | |
6276 | else | |
6277 | { | |
6278 | hreg = treg + 1; | |
6279 | lreg = treg; | |
6280 | } | |
6281 | ||
6282 | if (hreg <= 31) | |
6283 | load_register (&icnt, hreg, &imm_expr, 0); | |
6284 | if (lreg <= 31) | |
6285 | { | |
6286 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6287 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6288 | else |
6289 | { | |
6290 | assert (offset_expr.X_op == O_constant); | |
6291 | load_register (&icnt, lreg, &offset_expr, 0); | |
6292 | } | |
6293 | } | |
6294 | } | |
6295 | return; | |
6296 | } | |
6297 | ||
6298 | /* We know that sym is in the .rdata section. First we get the | |
6299 | upper 16 bits of the address. */ | |
6300 | if (mips_pic == NO_PIC) | |
6301 | { | |
956cd1d6 | 6302 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6303 | } |
6304 | else if (mips_pic == SVR4_PIC) | |
6305 | { | |
17a2f251 TS |
6306 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6307 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6308 | } |
6309 | else if (mips_pic == EMBEDDED_PIC) | |
6310 | { | |
6311 | /* For embedded PIC we pick up the entire address off $gp in | |
6312 | a single instruction. */ | |
17a2f251 TS |
6313 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6314 | AT, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
6315 | offset_expr.X_op = O_constant; |
6316 | offset_expr.X_add_number = 0; | |
6317 | } | |
6318 | else | |
6319 | abort (); | |
bdaaa2e1 | 6320 | |
252b5132 | 6321 | /* Now we load the register(s). */ |
ca4e0257 | 6322 | if (HAVE_64BIT_GPRS) |
17a2f251 TS |
6323 | macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg, |
6324 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6325 | else |
6326 | { | |
17a2f251 TS |
6327 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg, |
6328 | BFD_RELOC_LO16, AT); | |
f9419b05 | 6329 | if (treg != RA) |
252b5132 RH |
6330 | { |
6331 | /* FIXME: How in the world do we deal with the possible | |
6332 | overflow here? */ | |
6333 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6334 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
6335 | treg + 1, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6336 | } |
6337 | } | |
6338 | ||
6339 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6340 | does not become a variant frag. */ | |
6341 | frag_wane (frag_now); | |
6342 | frag_new (0); | |
6343 | ||
6344 | break; | |
6345 | ||
6346 | case M_LI_DD: | |
ca4e0257 RS |
6347 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6348 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6349 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6350 | the value and the low order 32 bits are either zero or in | |
6351 | OFFSET_EXPR. */ | |
252b5132 RH |
6352 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6353 | { | |
ca4e0257 RS |
6354 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6355 | if (HAVE_64BIT_FPRS) | |
6356 | { | |
6357 | assert (HAVE_64BIT_GPRS); | |
17a2f251 | 6358 | macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6359 | } |
252b5132 RH |
6360 | else |
6361 | { | |
17a2f251 | 6362 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6363 | if (offset_expr.X_op == O_absent) |
17a2f251 | 6364 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6365 | else |
6366 | { | |
6367 | assert (offset_expr.X_op == O_constant); | |
6368 | load_register (&icnt, AT, &offset_expr, 0); | |
17a2f251 | 6369 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6370 | } |
6371 | } | |
6372 | break; | |
6373 | } | |
6374 | ||
6375 | assert (offset_expr.X_op == O_symbol | |
6376 | && offset_expr.X_add_number == 0); | |
6377 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6378 | if (strcmp (s, ".lit8") == 0) | |
6379 | { | |
e7af610e | 6380 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6381 | { |
17a2f251 TS |
6382 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6383 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6384 | return; |
6385 | } | |
c9914766 | 6386 | breg = mips_gp_register; |
252b5132 RH |
6387 | r = BFD_RELOC_MIPS_LITERAL; |
6388 | goto dob; | |
6389 | } | |
6390 | else | |
6391 | { | |
6392 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6393 | if (mips_pic == SVR4_PIC) | |
17a2f251 TS |
6394 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6395 | "t,o(b)", AT, BFD_RELOC_MIPS_GOT16, | |
6396 | mips_gp_register); | |
252b5132 RH |
6397 | else |
6398 | { | |
6399 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6400 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6401 | } |
bdaaa2e1 | 6402 | |
e7af610e | 6403 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6404 | { |
17a2f251 TS |
6405 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6406 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6407 | |
6408 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6409 | that this does not become a variant frag. */ | |
6410 | frag_wane (frag_now); | |
6411 | frag_new (0); | |
6412 | ||
6413 | break; | |
6414 | } | |
6415 | breg = AT; | |
6416 | r = BFD_RELOC_LO16; | |
6417 | goto dob; | |
6418 | } | |
6419 | ||
6420 | case M_L_DOB: | |
fef14a42 | 6421 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6422 | { |
6423 | as_bad (_("opcode not supported on this processor")); | |
6424 | return; | |
6425 | } | |
6426 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6427 | to adjust when loading from memory. */ | |
6428 | r = BFD_RELOC_LO16; | |
6429 | dob: | |
e7af610e | 6430 | assert (mips_opts.isa == ISA_MIPS1); |
17a2f251 TS |
6431 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6432 | target_big_endian ? treg + 1 : treg, r, breg); | |
252b5132 RH |
6433 | /* FIXME: A possible overflow which I don't know how to deal |
6434 | with. */ | |
6435 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6436 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6437 | target_big_endian ? treg : treg + 1, r, breg); | |
252b5132 RH |
6438 | |
6439 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6440 | does not become a variant frag. */ | |
6441 | frag_wane (frag_now); | |
6442 | frag_new (0); | |
6443 | ||
6444 | if (breg != AT) | |
6445 | return; | |
6446 | break; | |
6447 | ||
6448 | case M_L_DAB: | |
6449 | /* | |
6450 | * The MIPS assembler seems to check for X_add_number not | |
6451 | * being double aligned and generating: | |
6452 | * lui at,%hi(foo+1) | |
6453 | * addu at,at,v1 | |
6454 | * addiu at,at,%lo(foo+1) | |
6455 | * lwc1 f2,0(at) | |
6456 | * lwc1 f3,4(at) | |
6457 | * But, the resulting address is the same after relocation so why | |
6458 | * generate the extra instruction? | |
6459 | */ | |
fef14a42 | 6460 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6461 | { |
6462 | as_bad (_("opcode not supported on this processor")); | |
6463 | return; | |
6464 | } | |
bdaaa2e1 | 6465 | /* Itbl support may require additional care here. */ |
252b5132 | 6466 | coproc = 1; |
e7af610e | 6467 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6468 | { |
6469 | s = "ldc1"; | |
6470 | goto ld; | |
6471 | } | |
6472 | ||
6473 | s = "lwc1"; | |
6474 | fmt = "T,o(b)"; | |
6475 | goto ldd_std; | |
6476 | ||
6477 | case M_S_DAB: | |
fef14a42 | 6478 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6479 | { |
6480 | as_bad (_("opcode not supported on this processor")); | |
6481 | return; | |
6482 | } | |
6483 | ||
e7af610e | 6484 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6485 | { |
6486 | s = "sdc1"; | |
6487 | goto st; | |
6488 | } | |
6489 | ||
6490 | s = "swc1"; | |
6491 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6492 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6493 | coproc = 1; |
6494 | goto ldd_std; | |
6495 | ||
6496 | case M_LD_AB: | |
ca4e0257 | 6497 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6498 | { |
6499 | s = "ld"; | |
6500 | goto ld; | |
6501 | } | |
6502 | ||
6503 | s = "lw"; | |
6504 | fmt = "t,o(b)"; | |
6505 | goto ldd_std; | |
6506 | ||
6507 | case M_SD_AB: | |
ca4e0257 | 6508 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6509 | { |
6510 | s = "sd"; | |
6511 | goto st; | |
6512 | } | |
6513 | ||
6514 | s = "sw"; | |
6515 | fmt = "t,o(b)"; | |
6516 | ||
6517 | ldd_std: | |
afdbd6d0 CD |
6518 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6519 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6520 | This is not currently done by the compiler, and assembly coders | |
6521 | writing embedded-pic code can cope. */ | |
6522 | ||
252b5132 RH |
6523 | if (offset_expr.X_op != O_symbol |
6524 | && offset_expr.X_op != O_constant) | |
6525 | { | |
6526 | as_bad (_("expression too complex")); | |
6527 | offset_expr.X_op = O_constant; | |
6528 | } | |
6529 | ||
6530 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6531 | to adjust when loading from memory. We set coproc if we must | |
6532 | load $fn+1 first. */ | |
bdaaa2e1 | 6533 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6534 | if (! target_big_endian) |
6535 | coproc = 0; | |
6536 | ||
6537 | if (mips_pic == NO_PIC | |
6538 | || offset_expr.X_op == O_constant) | |
6539 | { | |
f9419b05 TS |
6540 | char *p; |
6541 | ||
252b5132 | 6542 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6543 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6544 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6545 | If we have a base register, we use this |
6546 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6547 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6548 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6549 | If this is not a GP relative symbol, we want |
6550 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6551 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6552 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6553 | If there is a base register, we add it to $at after the | |
6554 | lui instruction. If there is a constant, we always use | |
6555 | the last case. */ | |
e7d556df | 6556 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6557 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6558 | { | |
6559 | p = NULL; | |
6560 | used_at = 1; | |
6561 | } | |
6562 | else | |
6563 | { | |
6564 | int off; | |
6565 | ||
6566 | if (breg == 0) | |
6567 | { | |
6568 | frag_grow (28); | |
c9914766 | 6569 | tempreg = mips_gp_register; |
252b5132 RH |
6570 | off = 0; |
6571 | used_at = 0; | |
6572 | } | |
6573 | else | |
6574 | { | |
6575 | frag_grow (36); | |
17a2f251 TS |
6576 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6577 | AT, breg, mips_gp_register); | |
252b5132 RH |
6578 | tempreg = AT; |
6579 | off = 4; | |
6580 | used_at = 1; | |
6581 | } | |
6582 | ||
beae10d5 | 6583 | /* Itbl support may require additional care here. */ |
17a2f251 | 6584 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6585 | coproc ? treg + 1 : treg, |
17a2f251 | 6586 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6587 | offset_expr.X_add_number += 4; |
6588 | ||
6589 | /* Set mips_optimize to 2 to avoid inserting an | |
6590 | undesired nop. */ | |
6591 | hold_mips_optimize = mips_optimize; | |
6592 | mips_optimize = 2; | |
beae10d5 | 6593 | /* Itbl support may require additional care here. */ |
17a2f251 | 6594 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6595 | coproc ? treg : treg + 1, |
17a2f251 | 6596 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6597 | mips_optimize = hold_mips_optimize; |
6598 | ||
6599 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6600 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6601 | used_at && mips_opts.noat), | |
956cd1d6 | 6602 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6603 | |
6604 | /* We just generated two relocs. When tc_gen_reloc | |
6605 | handles this case, it will skip the first reloc and | |
6606 | handle the second. The second reloc already has an | |
6607 | extra addend of 4, which we added above. We must | |
6608 | subtract it out, and then subtract another 4 to make | |
6609 | the first reloc come out right. The second reloc | |
6610 | will come out right because we are going to add 4 to | |
6611 | offset_expr when we build its instruction below. | |
6612 | ||
6613 | If we have a symbol, then we don't want to include | |
6614 | the offset, because it will wind up being included | |
6615 | when we generate the reloc. */ | |
6616 | ||
6617 | if (offset_expr.X_op == O_constant) | |
6618 | offset_expr.X_add_number -= 8; | |
6619 | else | |
6620 | { | |
6621 | offset_expr.X_add_number = -4; | |
6622 | offset_expr.X_op = O_constant; | |
6623 | } | |
6624 | } | |
6625 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6626 | if (p != NULL) | |
6627 | p += 4; | |
6628 | if (breg != 0) | |
6629 | { | |
17a2f251 TS |
6630 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6631 | AT, breg, AT); | |
252b5132 RH |
6632 | if (p != NULL) |
6633 | p += 4; | |
6634 | } | |
beae10d5 | 6635 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6636 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6637 | coproc ? treg + 1 : treg, | |
17a2f251 | 6638 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6639 | if (p != NULL) |
6640 | p += 4; | |
6641 | /* FIXME: How do we handle overflow here? */ | |
6642 | offset_expr.X_add_number += 4; | |
beae10d5 | 6643 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6644 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6645 | coproc ? treg : treg + 1, | |
17a2f251 | 6646 | BFD_RELOC_LO16, AT); |
bdaaa2e1 | 6647 | } |
252b5132 RH |
6648 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6649 | { | |
6650 | int off; | |
6651 | ||
6652 | /* If this is a reference to an external symbol, we want | |
6653 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6654 | nop | |
6655 | <op> $treg,0($at) | |
6656 | <op> $treg+1,4($at) | |
6657 | Otherwise we want | |
6658 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6659 | nop | |
6660 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6661 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6662 | If there is a base register we add it to $at before the | |
6663 | lwc1 instructions. If there is a constant we include it | |
6664 | in the lwc1 instructions. */ | |
6665 | used_at = 1; | |
6666 | expr1.X_add_number = offset_expr.X_add_number; | |
6667 | offset_expr.X_add_number = 0; | |
6668 | if (expr1.X_add_number < -0x8000 | |
6669 | || expr1.X_add_number >= 0x8000 - 4) | |
6670 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6671 | if (breg == 0) | |
6672 | off = 0; | |
6673 | else | |
6674 | off = 4; | |
6675 | frag_grow (24 + off); | |
17a2f251 TS |
6676 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6677 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
6678 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6679 | if (breg != 0) |
17a2f251 TS |
6680 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6681 | AT, breg, AT); | |
beae10d5 | 6682 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6683 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6684 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6685 | expr1.X_add_number += 4; |
6686 | ||
6687 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6688 | nop. */ | |
6689 | hold_mips_optimize = mips_optimize; | |
6690 | mips_optimize = 2; | |
beae10d5 | 6691 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6692 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6693 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6694 | mips_optimize = hold_mips_optimize; |
6695 | ||
6696 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6697 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6698 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6699 | } |
6700 | else if (mips_pic == SVR4_PIC) | |
6701 | { | |
6702 | int gpdel, off; | |
f9419b05 | 6703 | char *p; |
252b5132 RH |
6704 | |
6705 | /* If this is a reference to an external symbol, we want | |
6706 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6707 | addu $at,$at,$gp | |
6708 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6709 | nop | |
6710 | <op> $treg,0($at) | |
6711 | <op> $treg+1,4($at) | |
6712 | Otherwise we want | |
6713 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6714 | nop | |
6715 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6716 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6717 | If there is a base register we add it to $at before the | |
6718 | lwc1 instructions. If there is a constant we include it | |
6719 | in the lwc1 instructions. */ | |
6720 | used_at = 1; | |
6721 | expr1.X_add_number = offset_expr.X_add_number; | |
6722 | offset_expr.X_add_number = 0; | |
6723 | if (expr1.X_add_number < -0x8000 | |
6724 | || expr1.X_add_number >= 0x8000 - 4) | |
6725 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6726 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6727 | gpdel = 4; |
6728 | else | |
6729 | gpdel = 0; | |
6730 | if (breg == 0) | |
6731 | off = 0; | |
6732 | else | |
6733 | off = 4; | |
6734 | frag_grow (56); | |
17a2f251 TS |
6735 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT, |
6736 | BFD_RELOC_MIPS_GOT_HI16); | |
6737 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6738 | AT, AT, mips_gp_register); | |
6739 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6740 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); | |
6741 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6742 | if (breg != 0) |
17a2f251 TS |
6743 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6744 | AT, breg, AT); | |
beae10d5 | 6745 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6746 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6747 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6748 | expr1.X_add_number += 4; |
6749 | ||
6750 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6751 | nop. */ | |
6752 | hold_mips_optimize = mips_optimize; | |
6753 | mips_optimize = 2; | |
beae10d5 | 6754 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6755 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6756 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6757 | mips_optimize = hold_mips_optimize; |
6758 | expr1.X_add_number -= 4; | |
6759 | ||
6760 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6761 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6762 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6763 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6764 | if (gpdel > 0) |
6765 | { | |
17a2f251 | 6766 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6767 | p += 4; |
6768 | } | |
17a2f251 TS |
6769 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6770 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6771 | p += 4; |
17a2f251 | 6772 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6773 | p += 4; |
6774 | if (breg != 0) | |
6775 | { | |
17a2f251 TS |
6776 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6777 | AT, breg, AT); | |
252b5132 RH |
6778 | p += 4; |
6779 | } | |
beae10d5 | 6780 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6781 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6782 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6783 | p += 4; |
6784 | expr1.X_add_number += 4; | |
6785 | ||
6786 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6787 | nop. */ | |
6788 | hold_mips_optimize = mips_optimize; | |
6789 | mips_optimize = 2; | |
beae10d5 | 6790 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6791 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6792 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6793 | mips_optimize = hold_mips_optimize; |
6794 | } | |
6795 | else if (mips_pic == EMBEDDED_PIC) | |
6796 | { | |
6797 | /* If there is no base register, we use | |
cdf6fd85 TS |
6798 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6799 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6800 | If we have a base register, we use |
6801 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6802 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6803 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6804 | */ |
6805 | if (breg == 0) | |
6806 | { | |
c9914766 | 6807 | tempreg = mips_gp_register; |
252b5132 RH |
6808 | used_at = 0; |
6809 | } | |
6810 | else | |
6811 | { | |
17a2f251 TS |
6812 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6813 | AT, breg, mips_gp_register); | |
252b5132 RH |
6814 | tempreg = AT; |
6815 | used_at = 1; | |
6816 | } | |
6817 | ||
beae10d5 | 6818 | /* Itbl support may require additional care here. */ |
17a2f251 | 6819 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6820 | coproc ? treg + 1 : treg, |
17a2f251 | 6821 | BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6822 | offset_expr.X_add_number += 4; |
beae10d5 | 6823 | /* Itbl support may require additional care here. */ |
17a2f251 | 6824 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6825 | coproc ? treg : treg + 1, |
17a2f251 | 6826 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6827 | } |
6828 | else | |
6829 | abort (); | |
6830 | ||
6831 | if (! used_at) | |
6832 | return; | |
6833 | ||
6834 | break; | |
6835 | ||
6836 | case M_LD_OB: | |
6837 | s = "lw"; | |
6838 | goto sd_ob; | |
6839 | case M_SD_OB: | |
6840 | s = "sw"; | |
6841 | sd_ob: | |
ca4e0257 | 6842 | assert (HAVE_32BIT_ADDRESSES); |
17a2f251 TS |
6843 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6844 | BFD_RELOC_LO16, breg); | |
252b5132 | 6845 | offset_expr.X_add_number += 4; |
17a2f251 TS |
6846 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, |
6847 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
6848 | return; |
6849 | ||
6850 | /* New code added to support COPZ instructions. | |
6851 | This code builds table entries out of the macros in mip_opcodes. | |
6852 | R4000 uses interlocks to handle coproc delays. | |
6853 | Other chips (like the R3000) require nops to be inserted for delays. | |
6854 | ||
f72c8c98 | 6855 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6856 | In order to fill delay slots for non-interlocked chips, |
6857 | we must have a way to specify delays based on the coprocessor. | |
6858 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6859 | What are the side-effects of the cop instruction? | |
6860 | What cache support might we have and what are its effects? | |
6861 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6862 | What registers are read/set/modified? |
252b5132 RH |
6863 | |
6864 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6865 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6866 | |
6867 | case M_COP0: | |
6868 | s = "c0"; | |
6869 | goto copz; | |
6870 | case M_COP1: | |
6871 | s = "c1"; | |
6872 | goto copz; | |
6873 | case M_COP2: | |
6874 | s = "c2"; | |
6875 | goto copz; | |
6876 | case M_COP3: | |
6877 | s = "c3"; | |
6878 | copz: | |
6879 | /* For now we just do C (same as Cz). The parameter will be | |
6880 | stored in insn_opcode by mips_ip. */ | |
17a2f251 | 6881 | macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6882 | return; |
6883 | ||
ea1fb5dc RS |
6884 | case M_MOVE: |
6885 | move_register (&icnt, dreg, sreg); | |
6886 | return; | |
6887 | ||
252b5132 RH |
6888 | #ifdef LOSING_COMPILER |
6889 | default: | |
6890 | /* Try and see if this is a new itbl instruction. | |
6891 | This code builds table entries out of the macros in mip_opcodes. | |
6892 | FIXME: For now we just assemble the expression and pass it's | |
6893 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6894 | We may want to have the assembler assemble this value, |
252b5132 RH |
6895 | so that we gain the assembler's knowledge of delay slots, |
6896 | symbols, etc. | |
6897 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6898 | if (itbl_have_entries |
252b5132 | 6899 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6900 | { |
252b5132 RH |
6901 | s = ip->insn_mo->name; |
6902 | s2 = "cop3"; | |
6903 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
17a2f251 | 6904 | macro_build (NULL, &icnt, &immed_expr, s, "C"); |
252b5132 | 6905 | return; |
beae10d5 | 6906 | } |
252b5132 RH |
6907 | macro2 (ip); |
6908 | return; | |
6909 | } | |
6910 | if (mips_opts.noat) | |
6911 | as_warn (_("Macro used $at after \".set noat\"")); | |
6912 | } | |
bdaaa2e1 | 6913 | |
252b5132 | 6914 | static void |
17a2f251 | 6915 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6916 | { |
6917 | register int treg, sreg, dreg, breg; | |
6918 | int tempreg; | |
6919 | int mask; | |
6920 | int icnt = 0; | |
6921 | int used_at; | |
6922 | expressionS expr1; | |
6923 | const char *s; | |
6924 | const char *s2; | |
6925 | const char *fmt; | |
6926 | int likely = 0; | |
6927 | int dbl = 0; | |
6928 | int coproc = 0; | |
6929 | int lr = 0; | |
6930 | int imm = 0; | |
6931 | int off; | |
6932 | offsetT maxnum; | |
6933 | bfd_reloc_code_real_type r; | |
6934 | char *p; | |
bdaaa2e1 | 6935 | |
252b5132 RH |
6936 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6937 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6938 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6939 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6940 | |
252b5132 RH |
6941 | expr1.X_op = O_constant; |
6942 | expr1.X_op_symbol = NULL; | |
6943 | expr1.X_add_symbol = NULL; | |
6944 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6945 | |
252b5132 RH |
6946 | switch (mask) |
6947 | { | |
6948 | #endif /* LOSING_COMPILER */ | |
6949 | ||
6950 | case M_DMUL: | |
6951 | dbl = 1; | |
6952 | case M_MUL: | |
17a2f251 TS |
6953 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
6954 | sreg, treg); | |
6955 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
6956 | return; |
6957 | ||
6958 | case M_DMUL_I: | |
6959 | dbl = 1; | |
6960 | case M_MUL_I: | |
6961 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6962 | not trying to be that fancy. GCC should do this for us | |
6963 | anyway. */ | |
6964 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
6965 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
6966 | sreg, AT); | |
6967 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
6968 | break; |
6969 | ||
6970 | case M_DMULO_I: | |
6971 | dbl = 1; | |
6972 | case M_MULO_I: | |
6973 | imm = 1; | |
6974 | goto do_mulo; | |
6975 | ||
6976 | case M_DMULO: | |
6977 | dbl = 1; | |
6978 | case M_MULO: | |
6979 | do_mulo: | |
b34976b6 | 6980 | mips_emit_delays (TRUE); |
252b5132 RH |
6981 | ++mips_opts.noreorder; |
6982 | mips_any_noreorder = 1; | |
6983 | if (imm) | |
6984 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
6985 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
6986 | sreg, imm ? AT : treg); | |
6987 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
6988 | macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<", | |
6989 | dreg, dreg, RA); | |
6990 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
252b5132 | 6991 | if (mips_trap) |
17a2f251 | 6992 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6993 | else |
6994 | { | |
6995 | expr1.X_add_number = 8; | |
17a2f251 TS |
6996 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); |
6997 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
6998 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
6999 | } |
7000 | --mips_opts.noreorder; | |
17a2f251 | 7001 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); |
252b5132 RH |
7002 | break; |
7003 | ||
7004 | case M_DMULOU_I: | |
7005 | dbl = 1; | |
7006 | case M_MULOU_I: | |
7007 | imm = 1; | |
7008 | goto do_mulou; | |
7009 | ||
7010 | case M_DMULOU: | |
7011 | dbl = 1; | |
7012 | case M_MULOU: | |
7013 | do_mulou: | |
b34976b6 | 7014 | mips_emit_delays (TRUE); |
252b5132 RH |
7015 | ++mips_opts.noreorder; |
7016 | mips_any_noreorder = 1; | |
7017 | if (imm) | |
7018 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7019 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
7020 | sreg, imm ? AT : treg); | |
7021 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
7022 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 | 7023 | if (mips_trap) |
17a2f251 | 7024 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7025 | else |
7026 | { | |
7027 | expr1.X_add_number = 8; | |
17a2f251 TS |
7028 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); |
7029 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
7030 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
7031 | } |
7032 | --mips_opts.noreorder; | |
7033 | break; | |
7034 | ||
771c7ce4 | 7035 | case M_DROL: |
fef14a42 | 7036 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7037 | { |
7038 | if (dreg == sreg) | |
7039 | { | |
7040 | tempreg = AT; | |
7041 | used_at = 1; | |
7042 | } | |
7043 | else | |
7044 | { | |
7045 | tempreg = dreg; | |
7046 | used_at = 0; | |
7047 | } | |
17a2f251 TS |
7048 | macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg); |
7049 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, | |
7050 | tempreg); | |
82dd0097 CD |
7051 | if (used_at) |
7052 | break; | |
7053 | return; | |
7054 | } | |
17a2f251 TS |
7055 | macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg); |
7056 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7057 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7058 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7059 | break; |
7060 | ||
252b5132 | 7061 | case M_ROL: |
fef14a42 | 7062 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7063 | { |
7064 | if (dreg == sreg) | |
7065 | { | |
7066 | tempreg = AT; | |
7067 | used_at = 1; | |
7068 | } | |
7069 | else | |
7070 | { | |
7071 | tempreg = dreg; | |
7072 | used_at = 0; | |
7073 | } | |
17a2f251 TS |
7074 | macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg); |
7075 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, | |
7076 | tempreg); | |
82dd0097 CD |
7077 | if (used_at) |
7078 | break; | |
7079 | return; | |
7080 | } | |
17a2f251 TS |
7081 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7082 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7083 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7084 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7085 | break; |
7086 | ||
771c7ce4 TS |
7087 | case M_DROL_I: |
7088 | { | |
7089 | unsigned int rot; | |
82dd0097 | 7090 | char *l, *r; |
771c7ce4 TS |
7091 | |
7092 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7093 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7094 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7095 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7096 | { |
7097 | rot = (64 - rot) & 0x3f; | |
7098 | if (rot >= 32) | |
17a2f251 TS |
7099 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7100 | dreg, sreg, rot - 32); | |
60b63b72 | 7101 | else |
17a2f251 TS |
7102 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7103 | dreg, sreg, rot); | |
82dd0097 | 7104 | return; |
60b63b72 | 7105 | } |
483fc7cd | 7106 | if (rot == 0) |
483fc7cd | 7107 | { |
17a2f251 | 7108 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7109 | return; |
483fc7cd | 7110 | } |
82dd0097 CD |
7111 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7112 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7113 | rot &= 0x1f; | |
17a2f251 TS |
7114 | macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot); |
7115 | macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg, | |
7116 | (0x20 - rot) & 0x1f); | |
7117 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7118 | } |
7119 | break; | |
7120 | ||
252b5132 | 7121 | case M_ROL_I: |
771c7ce4 TS |
7122 | { |
7123 | unsigned int rot; | |
7124 | ||
7125 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7126 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7127 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7128 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7129 | { |
17a2f251 TS |
7130 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, |
7131 | (32 - rot) & 0x1f); | |
82dd0097 | 7132 | return; |
60b63b72 | 7133 | } |
483fc7cd | 7134 | if (rot == 0) |
483fc7cd | 7135 | { |
17a2f251 | 7136 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7137 | return; |
483fc7cd | 7138 | } |
17a2f251 TS |
7139 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot); |
7140 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
7141 | (0x20 - rot) & 0x1f); | |
7142 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7143 | } |
7144 | break; | |
7145 | ||
7146 | case M_DROR: | |
fef14a42 | 7147 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7148 | { |
17a2f251 | 7149 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7150 | return; |
7151 | } | |
17a2f251 TS |
7152 | macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg); |
7153 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7154 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7155 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7156 | break; |
7157 | ||
7158 | case M_ROR: | |
fef14a42 | 7159 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7160 | { |
17a2f251 | 7161 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7162 | return; |
7163 | } | |
17a2f251 TS |
7164 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7165 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7166 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7167 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7168 | break; |
7169 | ||
771c7ce4 TS |
7170 | case M_DROR_I: |
7171 | { | |
7172 | unsigned int rot; | |
82dd0097 | 7173 | char *l, *r; |
771c7ce4 TS |
7174 | |
7175 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7176 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7177 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7178 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7179 | { |
7180 | if (rot >= 32) | |
17a2f251 TS |
7181 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7182 | dreg, sreg, rot - 32); | |
82dd0097 | 7183 | else |
17a2f251 TS |
7184 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7185 | dreg, sreg, rot); | |
82dd0097 CD |
7186 | return; |
7187 | } | |
483fc7cd | 7188 | if (rot == 0) |
483fc7cd | 7189 | { |
17a2f251 | 7190 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7191 | return; |
483fc7cd | 7192 | } |
82dd0097 CD |
7193 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7194 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7195 | rot &= 0x1f; | |
17a2f251 TS |
7196 | macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot); |
7197 | macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg, | |
7198 | (0x20 - rot) & 0x1f); | |
7199 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7200 | } |
7201 | break; | |
7202 | ||
252b5132 | 7203 | case M_ROR_I: |
771c7ce4 TS |
7204 | { |
7205 | unsigned int rot; | |
7206 | ||
7207 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7208 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7209 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7210 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7211 | { |
17a2f251 | 7212 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7213 | return; |
7214 | } | |
483fc7cd | 7215 | if (rot == 0) |
483fc7cd | 7216 | { |
17a2f251 | 7217 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7218 | return; |
483fc7cd | 7219 | } |
17a2f251 TS |
7220 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot); |
7221 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
7222 | (0x20 - rot) & 0x1f); | |
7223 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7224 | } |
252b5132 RH |
7225 | break; |
7226 | ||
7227 | case M_S_DOB: | |
fef14a42 | 7228 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7229 | { |
7230 | as_bad (_("opcode not supported on this processor")); | |
7231 | return; | |
7232 | } | |
e7af610e | 7233 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7234 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7235 | to adjust when storing to memory. */ | |
17a2f251 | 7236 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7237 | target_big_endian ? treg + 1 : treg, |
17a2f251 | 7238 | BFD_RELOC_LO16, breg); |
252b5132 | 7239 | offset_expr.X_add_number += 4; |
17a2f251 | 7240 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7241 | target_big_endian ? treg : treg + 1, |
17a2f251 | 7242 | BFD_RELOC_LO16, breg); |
252b5132 RH |
7243 | return; |
7244 | ||
7245 | case M_SEQ: | |
7246 | if (sreg == 0) | |
17a2f251 TS |
7247 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg, |
7248 | BFD_RELOC_LO16); | |
252b5132 | 7249 | else if (treg == 0) |
17a2f251 TS |
7250 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7251 | BFD_RELOC_LO16); | |
252b5132 RH |
7252 | else |
7253 | { | |
17a2f251 TS |
7254 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7255 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7256 | BFD_RELOC_LO16); | |
252b5132 RH |
7257 | } |
7258 | return; | |
7259 | ||
7260 | case M_SEQ_I: | |
7261 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7262 | { | |
17a2f251 TS |
7263 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7264 | BFD_RELOC_LO16); | |
252b5132 RH |
7265 | return; |
7266 | } | |
7267 | if (sreg == 0) | |
7268 | { | |
7269 | as_warn (_("Instruction %s: result is always false"), | |
7270 | ip->insn_mo->name); | |
ea1fb5dc | 7271 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7272 | return; |
7273 | } | |
7274 | if (imm_expr.X_op == O_constant | |
7275 | && imm_expr.X_add_number >= 0 | |
7276 | && imm_expr.X_add_number < 0x10000) | |
7277 | { | |
17a2f251 TS |
7278 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7279 | BFD_RELOC_LO16); | |
252b5132 RH |
7280 | used_at = 0; |
7281 | } | |
7282 | else if (imm_expr.X_op == O_constant | |
7283 | && imm_expr.X_add_number > -0x8000 | |
7284 | && imm_expr.X_add_number < 0) | |
7285 | { | |
7286 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7287 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7288 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7289 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7290 | used_at = 0; |
7291 | } | |
7292 | else | |
7293 | { | |
4d34fb5f | 7294 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7295 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7296 | used_at = 1; |
7297 | } | |
17a2f251 TS |
7298 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
7299 | BFD_RELOC_LO16); | |
252b5132 RH |
7300 | if (used_at) |
7301 | break; | |
7302 | return; | |
7303 | ||
7304 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7305 | s = "slt"; | |
7306 | goto sge; | |
7307 | case M_SGEU: | |
7308 | s = "sltu"; | |
7309 | sge: | |
17a2f251 TS |
7310 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
7311 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7312 | BFD_RELOC_LO16); | |
252b5132 RH |
7313 | return; |
7314 | ||
7315 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7316 | case M_SGEU_I: | |
7317 | if (imm_expr.X_op == O_constant | |
7318 | && imm_expr.X_add_number >= -0x8000 | |
7319 | && imm_expr.X_add_number < 0x8000) | |
7320 | { | |
17a2f251 | 7321 | macro_build (NULL, &icnt, &imm_expr, |
252b5132 | 7322 | mask == M_SGE_I ? "slti" : "sltiu", |
17a2f251 | 7323 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7324 | used_at = 0; |
7325 | } | |
7326 | else | |
7327 | { | |
4d34fb5f | 7328 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7329 | macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu", |
7330 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7331 | used_at = 1; |
7332 | } | |
17a2f251 TS |
7333 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7334 | BFD_RELOC_LO16); | |
252b5132 RH |
7335 | if (used_at) |
7336 | break; | |
7337 | return; | |
7338 | ||
7339 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7340 | s = "slt"; | |
7341 | goto sgt; | |
7342 | case M_SGTU: | |
7343 | s = "sltu"; | |
7344 | sgt: | |
17a2f251 | 7345 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7346 | return; |
7347 | ||
7348 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7349 | s = "slt"; | |
7350 | goto sgti; | |
7351 | case M_SGTU_I: | |
7352 | s = "sltu"; | |
7353 | sgti: | |
4d34fb5f | 7354 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7355 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
252b5132 RH |
7356 | break; |
7357 | ||
2396cfb9 | 7358 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7359 | s = "slt"; |
7360 | goto sle; | |
7361 | case M_SLEU: | |
7362 | s = "sltu"; | |
7363 | sle: | |
17a2f251 TS |
7364 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
7365 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7366 | BFD_RELOC_LO16); | |
252b5132 RH |
7367 | return; |
7368 | ||
2396cfb9 | 7369 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7370 | s = "slt"; |
7371 | goto slei; | |
7372 | case M_SLEU_I: | |
7373 | s = "sltu"; | |
7374 | slei: | |
4d34fb5f | 7375 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7376 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
7377 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7378 | BFD_RELOC_LO16); | |
252b5132 RH |
7379 | break; |
7380 | ||
7381 | case M_SLT_I: | |
7382 | if (imm_expr.X_op == O_constant | |
7383 | && imm_expr.X_add_number >= -0x8000 | |
7384 | && imm_expr.X_add_number < 0x8000) | |
7385 | { | |
17a2f251 TS |
7386 | macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg, |
7387 | BFD_RELOC_LO16); | |
252b5132 RH |
7388 | return; |
7389 | } | |
4d34fb5f | 7390 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7391 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7392 | break; |
7393 | ||
7394 | case M_SLTU_I: | |
7395 | if (imm_expr.X_op == O_constant | |
7396 | && imm_expr.X_add_number >= -0x8000 | |
7397 | && imm_expr.X_add_number < 0x8000) | |
7398 | { | |
17a2f251 TS |
7399 | macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg, |
7400 | BFD_RELOC_LO16); | |
252b5132 RH |
7401 | return; |
7402 | } | |
4d34fb5f | 7403 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7404 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7405 | break; |
7406 | ||
7407 | case M_SNE: | |
7408 | if (sreg == 0) | |
17a2f251 | 7409 | macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg); |
252b5132 | 7410 | else if (treg == 0) |
17a2f251 | 7411 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7412 | else |
7413 | { | |
17a2f251 TS |
7414 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7415 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7416 | } |
7417 | return; | |
7418 | ||
7419 | case M_SNE_I: | |
7420 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7421 | { | |
17a2f251 | 7422 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7423 | return; |
7424 | } | |
7425 | if (sreg == 0) | |
7426 | { | |
7427 | as_warn (_("Instruction %s: result is always true"), | |
7428 | ip->insn_mo->name); | |
17a2f251 | 7429 | macro_build (NULL, &icnt, &expr1, |
ca4e0257 | 7430 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7431 | "t,r,j", dreg, 0, BFD_RELOC_LO16); |
252b5132 RH |
7432 | return; |
7433 | } | |
7434 | if (imm_expr.X_op == O_constant | |
7435 | && imm_expr.X_add_number >= 0 | |
7436 | && imm_expr.X_add_number < 0x10000) | |
7437 | { | |
17a2f251 TS |
7438 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7439 | BFD_RELOC_LO16); | |
252b5132 RH |
7440 | used_at = 0; |
7441 | } | |
7442 | else if (imm_expr.X_op == O_constant | |
7443 | && imm_expr.X_add_number > -0x8000 | |
7444 | && imm_expr.X_add_number < 0) | |
7445 | { | |
7446 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7447 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7448 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7449 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7450 | used_at = 0; |
7451 | } | |
7452 | else | |
7453 | { | |
4d34fb5f | 7454 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7455 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7456 | used_at = 1; |
7457 | } | |
17a2f251 | 7458 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7459 | if (used_at) |
7460 | break; | |
7461 | return; | |
7462 | ||
7463 | case M_DSUB_I: | |
7464 | dbl = 1; | |
7465 | case M_SUB_I: | |
7466 | if (imm_expr.X_op == O_constant | |
7467 | && imm_expr.X_add_number > -0x8000 | |
7468 | && imm_expr.X_add_number <= 0x8000) | |
7469 | { | |
7470 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7471 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi", |
7472 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7473 | return; |
7474 | } | |
7475 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7476 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", |
7477 | dreg, sreg, AT); | |
252b5132 RH |
7478 | break; |
7479 | ||
7480 | case M_DSUBU_I: | |
7481 | dbl = 1; | |
7482 | case M_SUBU_I: | |
7483 | if (imm_expr.X_op == O_constant | |
7484 | && imm_expr.X_add_number > -0x8000 | |
7485 | && imm_expr.X_add_number <= 0x8000) | |
7486 | { | |
7487 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7488 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", |
7489 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7490 | return; |
7491 | } | |
7492 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7493 | macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t", |
7494 | dreg, sreg, AT); | |
252b5132 RH |
7495 | break; |
7496 | ||
7497 | case M_TEQ_I: | |
7498 | s = "teq"; | |
7499 | goto trap; | |
7500 | case M_TGE_I: | |
7501 | s = "tge"; | |
7502 | goto trap; | |
7503 | case M_TGEU_I: | |
7504 | s = "tgeu"; | |
7505 | goto trap; | |
7506 | case M_TLT_I: | |
7507 | s = "tlt"; | |
7508 | goto trap; | |
7509 | case M_TLTU_I: | |
7510 | s = "tltu"; | |
7511 | goto trap; | |
7512 | case M_TNE_I: | |
7513 | s = "tne"; | |
7514 | trap: | |
4d34fb5f | 7515 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7516 | macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT); |
252b5132 RH |
7517 | break; |
7518 | ||
252b5132 | 7519 | case M_TRUNCWS: |
43841e91 | 7520 | case M_TRUNCWD: |
e7af610e | 7521 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7522 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7523 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7524 | ||
7525 | /* | |
7526 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7527 | * or is there a reason for it? | |
7528 | */ | |
b34976b6 | 7529 | mips_emit_delays (TRUE); |
252b5132 RH |
7530 | ++mips_opts.noreorder; |
7531 | mips_any_noreorder = 1; | |
17a2f251 TS |
7532 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); |
7533 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); | |
7534 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 7535 | expr1.X_add_number = 3; |
17a2f251 TS |
7536 | macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
7537 | BFD_RELOC_LO16); | |
252b5132 | 7538 | expr1.X_add_number = 2; |
17a2f251 TS |
7539 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
7540 | BFD_RELOC_LO16); | |
7541 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA); | |
7542 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
7543 | macro_build (NULL, &icnt, NULL, | |
7544 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", | |
7545 | "D,S", dreg, sreg); | |
7546 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA); | |
7547 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 RH |
7548 | --mips_opts.noreorder; |
7549 | break; | |
7550 | ||
7551 | case M_ULH: | |
7552 | s = "lb"; | |
7553 | goto ulh; | |
7554 | case M_ULHU: | |
7555 | s = "lbu"; | |
7556 | ulh: | |
7557 | if (offset_expr.X_add_number >= 0x7fff) | |
7558 | as_bad (_("operand overflow")); | |
252b5132 | 7559 | if (! target_big_endian) |
f9419b05 | 7560 | ++offset_expr.X_add_number; |
17a2f251 TS |
7561 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT, |
7562 | BFD_RELOC_LO16, breg); | |
252b5132 | 7563 | if (! target_big_endian) |
f9419b05 | 7564 | --offset_expr.X_add_number; |
252b5132 | 7565 | else |
f9419b05 | 7566 | ++offset_expr.X_add_number; |
17a2f251 TS |
7567 | macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg, |
7568 | BFD_RELOC_LO16, breg); | |
7569 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8); | |
7570 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7571 | break; |
7572 | ||
7573 | case M_ULD: | |
7574 | s = "ldl"; | |
7575 | s2 = "ldr"; | |
7576 | off = 7; | |
7577 | goto ulw; | |
7578 | case M_ULW: | |
7579 | s = "lwl"; | |
7580 | s2 = "lwr"; | |
7581 | off = 3; | |
7582 | ulw: | |
7583 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7584 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7585 | if (treg != breg) |
7586 | tempreg = treg; | |
7587 | else | |
7588 | tempreg = AT; | |
252b5132 RH |
7589 | if (! target_big_endian) |
7590 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7591 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg, |
7592 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7593 | if (! target_big_endian) |
7594 | offset_expr.X_add_number -= off; | |
7595 | else | |
7596 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7597 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg, |
7598 | BFD_RELOC_LO16, breg); | |
af22f5b2 CD |
7599 | |
7600 | /* If necessary, move the result in tempreg the final destination. */ | |
7601 | if (treg == tempreg) | |
7602 | return; | |
7603 | /* Protect second load's delay slot. */ | |
7604 | if (!gpr_interlocks) | |
17a2f251 | 7605 | macro_build (NULL, &icnt, NULL, "nop", ""); |
af22f5b2 CD |
7606 | move_register (&icnt, treg, tempreg); |
7607 | break; | |
252b5132 RH |
7608 | |
7609 | case M_ULD_A: | |
7610 | s = "ldl"; | |
7611 | s2 = "ldr"; | |
7612 | off = 7; | |
7613 | goto ulwa; | |
7614 | case M_ULW_A: | |
7615 | s = "lwl"; | |
7616 | s2 = "lwr"; | |
7617 | off = 3; | |
7618 | ulwa: | |
d6bc6245 | 7619 | used_at = 1; |
c9914766 | 7620 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7621 | if (breg != 0) |
17a2f251 TS |
7622 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7623 | AT, AT, breg); | |
252b5132 RH |
7624 | if (! target_big_endian) |
7625 | expr1.X_add_number = off; | |
7626 | else | |
7627 | expr1.X_add_number = 0; | |
17a2f251 TS |
7628 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7629 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7630 | if (! target_big_endian) |
7631 | expr1.X_add_number = 0; | |
7632 | else | |
7633 | expr1.X_add_number = off; | |
17a2f251 TS |
7634 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7635 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7636 | break; |
7637 | ||
7638 | case M_ULH_A: | |
7639 | case M_ULHU_A: | |
d6bc6245 | 7640 | used_at = 1; |
c9914766 | 7641 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7642 | if (breg != 0) |
17a2f251 TS |
7643 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7644 | AT, AT, breg); | |
252b5132 RH |
7645 | if (target_big_endian) |
7646 | expr1.X_add_number = 0; | |
17a2f251 TS |
7647 | macro_build (NULL, &icnt, &expr1, |
7648 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", | |
7649 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7650 | if (target_big_endian) |
7651 | expr1.X_add_number = 1; | |
7652 | else | |
7653 | expr1.X_add_number = 0; | |
17a2f251 TS |
7654 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", |
7655 | AT, BFD_RELOC_LO16, AT); | |
7656 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7657 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7658 | break; |
7659 | ||
7660 | case M_USH: | |
7661 | if (offset_expr.X_add_number >= 0x7fff) | |
7662 | as_bad (_("operand overflow")); | |
7663 | if (target_big_endian) | |
f9419b05 | 7664 | ++offset_expr.X_add_number; |
17a2f251 TS |
7665 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7666 | BFD_RELOC_LO16, breg); | |
7667 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7668 | if (target_big_endian) |
f9419b05 | 7669 | --offset_expr.X_add_number; |
252b5132 | 7670 | else |
f9419b05 | 7671 | ++offset_expr.X_add_number; |
17a2f251 TS |
7672 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7673 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7674 | break; |
7675 | ||
7676 | case M_USD: | |
7677 | s = "sdl"; | |
7678 | s2 = "sdr"; | |
7679 | off = 7; | |
7680 | goto usw; | |
7681 | case M_USW: | |
7682 | s = "swl"; | |
7683 | s2 = "swr"; | |
7684 | off = 3; | |
7685 | usw: | |
7686 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7687 | as_bad (_("operand overflow")); | |
7688 | if (! target_big_endian) | |
7689 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7690 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7691 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7692 | if (! target_big_endian) |
7693 | offset_expr.X_add_number -= off; | |
7694 | else | |
7695 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7696 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
7697 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7698 | return; |
7699 | ||
7700 | case M_USD_A: | |
7701 | s = "sdl"; | |
7702 | s2 = "sdr"; | |
7703 | off = 7; | |
7704 | goto uswa; | |
7705 | case M_USW_A: | |
7706 | s = "swl"; | |
7707 | s2 = "swr"; | |
7708 | off = 3; | |
7709 | uswa: | |
d6bc6245 | 7710 | used_at = 1; |
c9914766 | 7711 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7712 | if (breg != 0) |
17a2f251 TS |
7713 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7714 | AT, AT, breg); | |
252b5132 RH |
7715 | if (! target_big_endian) |
7716 | expr1.X_add_number = off; | |
7717 | else | |
7718 | expr1.X_add_number = 0; | |
17a2f251 TS |
7719 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7720 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7721 | if (! target_big_endian) |
7722 | expr1.X_add_number = 0; | |
7723 | else | |
7724 | expr1.X_add_number = off; | |
17a2f251 TS |
7725 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7726 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7727 | break; |
7728 | ||
7729 | case M_USH_A: | |
d6bc6245 | 7730 | used_at = 1; |
c9914766 | 7731 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7732 | if (breg != 0) |
17a2f251 TS |
7733 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7734 | AT, AT, breg); | |
252b5132 RH |
7735 | if (! target_big_endian) |
7736 | expr1.X_add_number = 0; | |
17a2f251 TS |
7737 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7738 | BFD_RELOC_LO16, AT); | |
7739 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7740 | if (! target_big_endian) |
7741 | expr1.X_add_number = 1; | |
7742 | else | |
7743 | expr1.X_add_number = 0; | |
17a2f251 TS |
7744 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7745 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7746 | if (! target_big_endian) |
7747 | expr1.X_add_number = 0; | |
7748 | else | |
7749 | expr1.X_add_number = 1; | |
17a2f251 TS |
7750 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
7751 | BFD_RELOC_LO16, AT); | |
7752 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7753 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7754 | break; |
7755 | ||
7756 | default: | |
7757 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7758 | are added dynamically. */ |
252b5132 RH |
7759 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7760 | break; | |
7761 | } | |
7762 | if (mips_opts.noat) | |
7763 | as_warn (_("Macro used $at after \".set noat\"")); | |
7764 | } | |
7765 | ||
7766 | /* Implement macros in mips16 mode. */ | |
7767 | ||
7768 | static void | |
17a2f251 | 7769 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7770 | { |
7771 | int mask; | |
7772 | int xreg, yreg, zreg, tmp; | |
7773 | int icnt; | |
7774 | expressionS expr1; | |
7775 | int dbl; | |
7776 | const char *s, *s2, *s3; | |
7777 | ||
7778 | mask = ip->insn_mo->mask; | |
7779 | ||
7780 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7781 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7782 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7783 | ||
7784 | icnt = 0; | |
7785 | ||
7786 | expr1.X_op = O_constant; | |
7787 | expr1.X_op_symbol = NULL; | |
7788 | expr1.X_add_symbol = NULL; | |
7789 | expr1.X_add_number = 1; | |
7790 | ||
7791 | dbl = 0; | |
7792 | ||
7793 | switch (mask) | |
7794 | { | |
7795 | default: | |
7796 | internalError (); | |
7797 | ||
7798 | case M_DDIV_3: | |
7799 | dbl = 1; | |
7800 | case M_DIV_3: | |
7801 | s = "mflo"; | |
7802 | goto do_div3; | |
7803 | case M_DREM_3: | |
7804 | dbl = 1; | |
7805 | case M_REM_3: | |
7806 | s = "mfhi"; | |
7807 | do_div3: | |
b34976b6 | 7808 | mips_emit_delays (TRUE); |
252b5132 RH |
7809 | ++mips_opts.noreorder; |
7810 | mips_any_noreorder = 1; | |
17a2f251 TS |
7811 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y", |
7812 | xreg, yreg); | |
252b5132 | 7813 | expr1.X_add_number = 2; |
17a2f251 TS |
7814 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
7815 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
bdaaa2e1 | 7816 | |
252b5132 RH |
7817 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7818 | since that causes an overflow. We should do that as well, | |
7819 | but I don't see how to do the comparisons without a temporary | |
7820 | register. */ | |
7821 | --mips_opts.noreorder; | |
17a2f251 | 7822 | macro_build (NULL, &icnt, NULL, s, "x", zreg); |
252b5132 RH |
7823 | break; |
7824 | ||
7825 | case M_DIVU_3: | |
7826 | s = "divu"; | |
7827 | s2 = "mflo"; | |
7828 | goto do_divu3; | |
7829 | case M_REMU_3: | |
7830 | s = "divu"; | |
7831 | s2 = "mfhi"; | |
7832 | goto do_divu3; | |
7833 | case M_DDIVU_3: | |
7834 | s = "ddivu"; | |
7835 | s2 = "mflo"; | |
7836 | goto do_divu3; | |
7837 | case M_DREMU_3: | |
7838 | s = "ddivu"; | |
7839 | s2 = "mfhi"; | |
7840 | do_divu3: | |
b34976b6 | 7841 | mips_emit_delays (TRUE); |
252b5132 RH |
7842 | ++mips_opts.noreorder; |
7843 | mips_any_noreorder = 1; | |
17a2f251 | 7844 | macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7845 | expr1.X_add_number = 2; |
17a2f251 TS |
7846 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
7847 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
252b5132 | 7848 | --mips_opts.noreorder; |
17a2f251 | 7849 | macro_build (NULL, &icnt, NULL, s2, "x", zreg); |
252b5132 RH |
7850 | break; |
7851 | ||
7852 | case M_DMUL: | |
7853 | dbl = 1; | |
7854 | case M_MUL: | |
17a2f251 TS |
7855 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y", |
7856 | xreg, yreg); | |
7857 | macro_build (NULL, &icnt, NULL, "mflo", "x", zreg); | |
252b5132 RH |
7858 | return; |
7859 | ||
7860 | case M_DSUBU_I: | |
7861 | dbl = 1; | |
7862 | goto do_subu; | |
7863 | case M_SUBU_I: | |
7864 | do_subu: | |
7865 | if (imm_expr.X_op != O_constant) | |
7866 | as_bad (_("Unsupported large constant")); | |
7867 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7868 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", |
7869 | yreg, xreg); | |
252b5132 RH |
7870 | break; |
7871 | ||
7872 | case M_SUBU_I_2: | |
7873 | if (imm_expr.X_op != O_constant) | |
7874 | as_bad (_("Unsupported large constant")); | |
7875 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7876 | macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7877 | break; |
7878 | ||
7879 | case M_DSUBU_I_2: | |
7880 | if (imm_expr.X_op != O_constant) | |
7881 | as_bad (_("Unsupported large constant")); | |
7882 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7883 | macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7884 | break; |
7885 | ||
7886 | case M_BEQ: | |
7887 | s = "cmp"; | |
7888 | s2 = "bteqz"; | |
7889 | goto do_branch; | |
7890 | case M_BNE: | |
7891 | s = "cmp"; | |
7892 | s2 = "btnez"; | |
7893 | goto do_branch; | |
7894 | case M_BLT: | |
7895 | s = "slt"; | |
7896 | s2 = "btnez"; | |
7897 | goto do_branch; | |
7898 | case M_BLTU: | |
7899 | s = "sltu"; | |
7900 | s2 = "btnez"; | |
7901 | goto do_branch; | |
7902 | case M_BLE: | |
7903 | s = "slt"; | |
7904 | s2 = "bteqz"; | |
7905 | goto do_reverse_branch; | |
7906 | case M_BLEU: | |
7907 | s = "sltu"; | |
7908 | s2 = "bteqz"; | |
7909 | goto do_reverse_branch; | |
7910 | case M_BGE: | |
7911 | s = "slt"; | |
7912 | s2 = "bteqz"; | |
7913 | goto do_branch; | |
7914 | case M_BGEU: | |
7915 | s = "sltu"; | |
7916 | s2 = "bteqz"; | |
7917 | goto do_branch; | |
7918 | case M_BGT: | |
7919 | s = "slt"; | |
7920 | s2 = "btnez"; | |
7921 | goto do_reverse_branch; | |
7922 | case M_BGTU: | |
7923 | s = "sltu"; | |
7924 | s2 = "btnez"; | |
7925 | ||
7926 | do_reverse_branch: | |
7927 | tmp = xreg; | |
7928 | xreg = yreg; | |
7929 | yreg = tmp; | |
7930 | ||
7931 | do_branch: | |
17a2f251 TS |
7932 | macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg); |
7933 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
7934 | break; |
7935 | ||
7936 | case M_BEQ_I: | |
7937 | s = "cmpi"; | |
7938 | s2 = "bteqz"; | |
7939 | s3 = "x,U"; | |
7940 | goto do_branch_i; | |
7941 | case M_BNE_I: | |
7942 | s = "cmpi"; | |
7943 | s2 = "btnez"; | |
7944 | s3 = "x,U"; | |
7945 | goto do_branch_i; | |
7946 | case M_BLT_I: | |
7947 | s = "slti"; | |
7948 | s2 = "btnez"; | |
7949 | s3 = "x,8"; | |
7950 | goto do_branch_i; | |
7951 | case M_BLTU_I: | |
7952 | s = "sltiu"; | |
7953 | s2 = "btnez"; | |
7954 | s3 = "x,8"; | |
7955 | goto do_branch_i; | |
7956 | case M_BLE_I: | |
7957 | s = "slti"; | |
7958 | s2 = "btnez"; | |
7959 | s3 = "x,8"; | |
7960 | goto do_addone_branch_i; | |
7961 | case M_BLEU_I: | |
7962 | s = "sltiu"; | |
7963 | s2 = "btnez"; | |
7964 | s3 = "x,8"; | |
7965 | goto do_addone_branch_i; | |
7966 | case M_BGE_I: | |
7967 | s = "slti"; | |
7968 | s2 = "bteqz"; | |
7969 | s3 = "x,8"; | |
7970 | goto do_branch_i; | |
7971 | case M_BGEU_I: | |
7972 | s = "sltiu"; | |
7973 | s2 = "bteqz"; | |
7974 | s3 = "x,8"; | |
7975 | goto do_branch_i; | |
7976 | case M_BGT_I: | |
7977 | s = "slti"; | |
7978 | s2 = "bteqz"; | |
7979 | s3 = "x,8"; | |
7980 | goto do_addone_branch_i; | |
7981 | case M_BGTU_I: | |
7982 | s = "sltiu"; | |
7983 | s2 = "bteqz"; | |
7984 | s3 = "x,8"; | |
7985 | ||
7986 | do_addone_branch_i: | |
7987 | if (imm_expr.X_op != O_constant) | |
7988 | as_bad (_("Unsupported large constant")); | |
7989 | ++imm_expr.X_add_number; | |
7990 | ||
7991 | do_branch_i: | |
17a2f251 TS |
7992 | macro_build (NULL, &icnt, &imm_expr, s, s3, xreg); |
7993 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
7994 | break; |
7995 | ||
7996 | case M_ABS: | |
7997 | expr1.X_add_number = 0; | |
17a2f251 | 7998 | macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7999 | if (xreg != yreg) |
ea1fb5dc | 8000 | move_register (&icnt, xreg, yreg); |
252b5132 | 8001 | expr1.X_add_number = 2; |
17a2f251 TS |
8002 | macro_build (NULL, &icnt, &expr1, "bteqz", "p"); |
8003 | macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8004 | } |
8005 | } | |
8006 | ||
8007 | /* For consistency checking, verify that all bits are specified either | |
8008 | by the match/mask part of the instruction definition, or by the | |
8009 | operand list. */ | |
8010 | static int | |
17a2f251 | 8011 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8012 | { |
8013 | const char *p = opc->args; | |
8014 | char c; | |
8015 | unsigned long used_bits = opc->mask; | |
8016 | ||
8017 | if ((used_bits & opc->match) != opc->match) | |
8018 | { | |
8019 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8020 | opc->name, opc->args); | |
8021 | return 0; | |
8022 | } | |
8023 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8024 | while (*p) | |
8025 | switch (c = *p++) | |
8026 | { | |
8027 | case ',': break; | |
8028 | case '(': break; | |
8029 | case ')': break; | |
af7ee8bf CD |
8030 | case '+': |
8031 | switch (c = *p++) | |
8032 | { | |
8033 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8034 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8035 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8036 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8037 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8038 | default: |
8039 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8040 | c, opc->name, opc->args); | |
8041 | return 0; | |
8042 | } | |
8043 | break; | |
252b5132 RH |
8044 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8045 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8046 | case 'A': break; | |
4372b673 | 8047 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8048 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8049 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8050 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8051 | case 'F': break; | |
8052 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8053 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8054 | case 'I': break; |
e972090a | 8055 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8056 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8057 | case 'L': break; |
8058 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8059 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8060 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8061 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8062 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8063 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8064 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8065 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8066 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8067 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8068 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8069 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8070 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8071 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8072 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8073 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8074 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8075 | case 'f': break; | |
8076 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8077 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8078 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8079 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8080 | case 'l': break; | |
8081 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8082 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8083 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8084 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8085 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8086 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8087 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8088 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8089 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8090 | case 'x': break; | |
8091 | case 'z': break; | |
8092 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8093 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8094 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8095 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8096 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8097 | case '[': break; | |
8098 | case ']': break; | |
252b5132 RH |
8099 | default: |
8100 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8101 | c, opc->name, opc->args); | |
8102 | return 0; | |
8103 | } | |
8104 | #undef USE_BITS | |
8105 | if (used_bits != 0xffffffff) | |
8106 | { | |
8107 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8108 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8109 | return 0; | |
8110 | } | |
8111 | return 1; | |
8112 | } | |
8113 | ||
8114 | /* This routine assembles an instruction into its binary format. As a | |
8115 | side effect, it sets one of the global variables imm_reloc or | |
8116 | offset_reloc to the type of relocation to do if one of the operands | |
8117 | is an address expression. */ | |
8118 | ||
8119 | static void | |
17a2f251 | 8120 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8121 | { |
8122 | char *s; | |
8123 | const char *args; | |
43841e91 | 8124 | char c = 0; |
252b5132 RH |
8125 | struct mips_opcode *insn; |
8126 | char *argsStart; | |
8127 | unsigned int regno; | |
8128 | unsigned int lastregno = 0; | |
af7ee8bf | 8129 | unsigned int lastpos = 0; |
071742cf | 8130 | unsigned int limlo, limhi; |
252b5132 RH |
8131 | char *s_reset; |
8132 | char save_c = 0; | |
252b5132 RH |
8133 | |
8134 | insn_error = NULL; | |
8135 | ||
8136 | /* If the instruction contains a '.', we first try to match an instruction | |
8137 | including the '.'. Then we try again without the '.'. */ | |
8138 | insn = NULL; | |
3882b010 | 8139 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8140 | continue; |
8141 | ||
8142 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8143 | the call to hash_find. Save the character we replaced just in case we | |
8144 | have to re-parse the instruction. */ | |
3882b010 | 8145 | if (ISSPACE (*s)) |
252b5132 RH |
8146 | { |
8147 | save_c = *s; | |
8148 | *s++ = '\0'; | |
8149 | } | |
bdaaa2e1 | 8150 | |
252b5132 RH |
8151 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8152 | ||
8153 | /* If we didn't find the instruction in the opcode table, try again, but | |
8154 | this time with just the instruction up to, but not including the | |
8155 | first '.'. */ | |
8156 | if (insn == NULL) | |
8157 | { | |
bdaaa2e1 | 8158 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8159 | if (save_c) |
8160 | *(--s) = save_c; | |
8161 | ||
8162 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8163 | for (s = str; |
8164 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8165 | ++s) | |
252b5132 RH |
8166 | continue; |
8167 | ||
8168 | /* If we did not find a '.', then we can quit now. */ | |
8169 | if (*s != '.') | |
8170 | { | |
8171 | insn_error = "unrecognized opcode"; | |
8172 | return; | |
8173 | } | |
8174 | ||
8175 | /* Lookup the instruction in the hash table. */ | |
8176 | *s++ = '\0'; | |
8177 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8178 | { | |
8179 | insn_error = "unrecognized opcode"; | |
8180 | return; | |
8181 | } | |
252b5132 RH |
8182 | } |
8183 | ||
8184 | argsStart = s; | |
8185 | for (;;) | |
8186 | { | |
b34976b6 | 8187 | bfd_boolean ok; |
252b5132 RH |
8188 | |
8189 | assert (strcmp (insn->name, str) == 0); | |
8190 | ||
1f25f5d3 CD |
8191 | if (OPCODE_IS_MEMBER (insn, |
8192 | (mips_opts.isa | |
3396de36 | 8193 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8194 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8195 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8196 | mips_opts.arch)) |
b34976b6 | 8197 | ok = TRUE; |
bdaaa2e1 | 8198 | else |
b34976b6 | 8199 | ok = FALSE; |
bdaaa2e1 | 8200 | |
252b5132 RH |
8201 | if (insn->pinfo != INSN_MACRO) |
8202 | { | |
fef14a42 | 8203 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8204 | ok = FALSE; |
252b5132 RH |
8205 | } |
8206 | ||
8207 | if (! ok) | |
8208 | { | |
8209 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8210 | && strcmp (insn->name, insn[1].name) == 0) | |
8211 | { | |
8212 | ++insn; | |
8213 | continue; | |
8214 | } | |
252b5132 | 8215 | else |
beae10d5 | 8216 | { |
268f6bed L |
8217 | if (!insn_error) |
8218 | { | |
8219 | static char buf[100]; | |
fef14a42 TS |
8220 | sprintf (buf, |
8221 | _("opcode not supported on this processor: %s (%s)"), | |
8222 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8223 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8224 | insn_error = buf; |
8225 | } | |
8226 | if (save_c) | |
8227 | *(--s) = save_c; | |
2bd7f1f3 | 8228 | return; |
252b5132 | 8229 | } |
252b5132 RH |
8230 | } |
8231 | ||
8232 | ip->insn_mo = insn; | |
8233 | ip->insn_opcode = insn->match; | |
268f6bed | 8234 | insn_error = NULL; |
252b5132 RH |
8235 | for (args = insn->args;; ++args) |
8236 | { | |
deec1734 CD |
8237 | int is_mdmx; |
8238 | ||
ad8d3bb3 | 8239 | s += strspn (s, " \t"); |
deec1734 | 8240 | is_mdmx = 0; |
252b5132 RH |
8241 | switch (*args) |
8242 | { | |
8243 | case '\0': /* end of args */ | |
8244 | if (*s == '\0') | |
8245 | return; | |
8246 | break; | |
8247 | ||
8248 | case ',': | |
8249 | if (*s++ == *args) | |
8250 | continue; | |
8251 | s--; | |
8252 | switch (*++args) | |
8253 | { | |
8254 | case 'r': | |
8255 | case 'v': | |
38487616 | 8256 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8257 | continue; |
8258 | ||
8259 | case 'w': | |
38487616 TS |
8260 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8261 | continue; | |
8262 | ||
252b5132 | 8263 | case 'W': |
38487616 | 8264 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8265 | continue; |
8266 | ||
8267 | case 'V': | |
38487616 | 8268 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8269 | continue; |
8270 | } | |
8271 | break; | |
8272 | ||
8273 | case '(': | |
8274 | /* Handle optional base register. | |
8275 | Either the base register is omitted or | |
bdaaa2e1 | 8276 | we must have a left paren. */ |
252b5132 RH |
8277 | /* This is dependent on the next operand specifier |
8278 | is a base register specification. */ | |
8279 | assert (args[1] == 'b' || args[1] == '5' | |
8280 | || args[1] == '-' || args[1] == '4'); | |
8281 | if (*s == '\0') | |
8282 | return; | |
8283 | ||
8284 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8285 | case '[': |
8286 | case ']': | |
252b5132 RH |
8287 | if (*s++ == *args) |
8288 | continue; | |
8289 | break; | |
8290 | ||
af7ee8bf CD |
8291 | case '+': /* Opcode extension character. */ |
8292 | switch (*++args) | |
8293 | { | |
071742cf CD |
8294 | case 'A': /* ins/ext position, becomes LSB. */ |
8295 | limlo = 0; | |
8296 | limhi = 31; | |
8297 | my_getExpression (&imm_expr, s); | |
8298 | check_absolute_expr (ip, &imm_expr); | |
8299 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8300 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8301 | { | |
8302 | as_bad (_("Improper position (%lu)"), | |
8303 | (unsigned long) imm_expr.X_add_number); | |
8304 | imm_expr.X_add_number = limlo; | |
8305 | } | |
8306 | lastpos = imm_expr.X_add_number; | |
8307 | ip->insn_opcode |= (imm_expr.X_add_number | |
8308 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8309 | imm_expr.X_op = O_absent; | |
8310 | s = expr_end; | |
8311 | continue; | |
8312 | ||
8313 | case 'B': /* ins size, becomes MSB. */ | |
8314 | limlo = 1; | |
8315 | limhi = 32; | |
8316 | my_getExpression (&imm_expr, s); | |
8317 | check_absolute_expr (ip, &imm_expr); | |
8318 | /* Check for negative input so that small negative numbers | |
8319 | will not succeed incorrectly. The checks against | |
8320 | (pos+size) transitively check "size" itself, | |
8321 | assuming that "pos" is reasonable. */ | |
8322 | if ((long) imm_expr.X_add_number < 0 | |
8323 | || ((unsigned long) imm_expr.X_add_number | |
8324 | + lastpos) < limlo | |
8325 | || ((unsigned long) imm_expr.X_add_number | |
8326 | + lastpos) > limhi) | |
8327 | { | |
8328 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8329 | (unsigned long) imm_expr.X_add_number, | |
8330 | (unsigned long) lastpos); | |
8331 | imm_expr.X_add_number = limlo - lastpos; | |
8332 | } | |
8333 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8334 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8335 | imm_expr.X_op = O_absent; | |
8336 | s = expr_end; | |
8337 | continue; | |
8338 | ||
8339 | case 'C': /* ext size, becomes MSBD. */ | |
8340 | limlo = 1; | |
8341 | limhi = 32; | |
8342 | my_getExpression (&imm_expr, s); | |
8343 | check_absolute_expr (ip, &imm_expr); | |
8344 | /* Check for negative input so that small negative numbers | |
8345 | will not succeed incorrectly. The checks against | |
8346 | (pos+size) transitively check "size" itself, | |
8347 | assuming that "pos" is reasonable. */ | |
8348 | if ((long) imm_expr.X_add_number < 0 | |
8349 | || ((unsigned long) imm_expr.X_add_number | |
8350 | + lastpos) < limlo | |
8351 | || ((unsigned long) imm_expr.X_add_number | |
8352 | + lastpos) > limhi) | |
8353 | { | |
8354 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8355 | (unsigned long) imm_expr.X_add_number, | |
8356 | (unsigned long) lastpos); | |
8357 | imm_expr.X_add_number = limlo - lastpos; | |
8358 | } | |
8359 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8360 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8361 | imm_expr.X_op = O_absent; | |
8362 | s = expr_end; | |
8363 | continue; | |
af7ee8bf | 8364 | |
bbcc0807 CD |
8365 | case 'D': |
8366 | /* +D is for disassembly only; never match. */ | |
8367 | break; | |
8368 | ||
af7ee8bf CD |
8369 | default: |
8370 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8371 | *args, insn->name, insn->args); | |
8372 | /* Further processing is fruitless. */ | |
8373 | return; | |
8374 | } | |
8375 | break; | |
8376 | ||
252b5132 RH |
8377 | case '<': /* must be at least one digit */ |
8378 | /* | |
8379 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8380 | * than 31 or less than 0, then the shift amount should be |
8381 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8382 | * We issue a warning and mask out all but the low 5 bits. |
8383 | */ | |
8384 | my_getExpression (&imm_expr, s); | |
8385 | check_absolute_expr (ip, &imm_expr); | |
8386 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8387 | { | |
793b27f4 TS |
8388 | as_warn (_("Improper shift amount (%lu)"), |
8389 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8390 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8391 | } |
38487616 | 8392 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8393 | imm_expr.X_op = O_absent; |
8394 | s = expr_end; | |
8395 | continue; | |
8396 | ||
8397 | case '>': /* shift amount minus 32 */ | |
8398 | my_getExpression (&imm_expr, s); | |
8399 | check_absolute_expr (ip, &imm_expr); | |
8400 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8401 | || (unsigned long) imm_expr.X_add_number > 63) | |
8402 | break; | |
38487616 | 8403 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8404 | imm_expr.X_op = O_absent; |
8405 | s = expr_end; | |
8406 | continue; | |
8407 | ||
252b5132 RH |
8408 | case 'k': /* cache code */ |
8409 | case 'h': /* prefx code */ | |
8410 | my_getExpression (&imm_expr, s); | |
8411 | check_absolute_expr (ip, &imm_expr); | |
8412 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8413 | { | |
8414 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8415 | ip->insn_mo->name, | |
8416 | (unsigned long) imm_expr.X_add_number); | |
8417 | imm_expr.X_add_number &= 0x1f; | |
8418 | } | |
8419 | if (*args == 'k') | |
8420 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8421 | else | |
8422 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8423 | imm_expr.X_op = O_absent; | |
8424 | s = expr_end; | |
8425 | continue; | |
8426 | ||
8427 | case 'c': /* break code */ | |
8428 | my_getExpression (&imm_expr, s); | |
8429 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8430 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8431 | { |
793b27f4 TS |
8432 | as_warn (_("Illegal break code (%lu)"), |
8433 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8434 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8435 | } |
38487616 | 8436 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8437 | imm_expr.X_op = O_absent; |
8438 | s = expr_end; | |
8439 | continue; | |
8440 | ||
8441 | case 'q': /* lower break code */ | |
8442 | my_getExpression (&imm_expr, s); | |
8443 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8444 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8445 | { |
793b27f4 TS |
8446 | as_warn (_("Illegal lower break code (%lu)"), |
8447 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8448 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8449 | } |
38487616 | 8450 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8451 | imm_expr.X_op = O_absent; |
8452 | s = expr_end; | |
8453 | continue; | |
8454 | ||
4372b673 | 8455 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8456 | my_getExpression (&imm_expr, s); |
156c2f8b | 8457 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8458 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8459 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8460 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8461 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8462 | imm_expr.X_op = O_absent; |
8463 | s = expr_end; | |
8464 | continue; | |
8465 | ||
98d3f06f | 8466 | case 'C': /* Coprocessor code */ |
beae10d5 | 8467 | my_getExpression (&imm_expr, s); |
252b5132 | 8468 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8469 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8470 | { |
793b27f4 TS |
8471 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8472 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8473 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8474 | } |
beae10d5 KH |
8475 | ip->insn_opcode |= imm_expr.X_add_number; |
8476 | imm_expr.X_op = O_absent; | |
8477 | s = expr_end; | |
8478 | continue; | |
252b5132 | 8479 | |
4372b673 NC |
8480 | case 'J': /* 19-bit wait code. */ |
8481 | my_getExpression (&imm_expr, s); | |
8482 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8483 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8484 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8485 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8486 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8487 | imm_expr.X_op = O_absent; |
8488 | s = expr_end; | |
8489 | continue; | |
8490 | ||
252b5132 | 8491 | case 'P': /* Performance register */ |
beae10d5 | 8492 | my_getExpression (&imm_expr, s); |
252b5132 | 8493 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8494 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8495 | { |
793b27f4 TS |
8496 | as_warn (_("Invalid performance register (%lu)"), |
8497 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8498 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8499 | } |
38487616 | 8500 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8501 | imm_expr.X_op = O_absent; |
8502 | s = expr_end; | |
8503 | continue; | |
252b5132 RH |
8504 | |
8505 | case 'b': /* base register */ | |
8506 | case 'd': /* destination register */ | |
8507 | case 's': /* source register */ | |
8508 | case 't': /* target register */ | |
8509 | case 'r': /* both target and source */ | |
8510 | case 'v': /* both dest and source */ | |
8511 | case 'w': /* both dest and target */ | |
8512 | case 'E': /* coprocessor target register */ | |
8513 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8514 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8515 | case 'x': /* ignore register name */ |
8516 | case 'z': /* must be zero register */ | |
4372b673 | 8517 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8518 | s_reset = s; |
8519 | if (s[0] == '$') | |
8520 | { | |
8521 | ||
3882b010 | 8522 | if (ISDIGIT (s[1])) |
252b5132 RH |
8523 | { |
8524 | ++s; | |
8525 | regno = 0; | |
8526 | do | |
8527 | { | |
8528 | regno *= 10; | |
8529 | regno += *s - '0'; | |
8530 | ++s; | |
8531 | } | |
3882b010 | 8532 | while (ISDIGIT (*s)); |
252b5132 RH |
8533 | if (regno > 31) |
8534 | as_bad (_("Invalid register number (%d)"), regno); | |
8535 | } | |
af7ee8bf | 8536 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8537 | goto notreg; |
8538 | else | |
8539 | { | |
76db943d TS |
8540 | if (s[1] == 'r' && s[2] == 'a') |
8541 | { | |
8542 | s += 3; | |
8543 | regno = RA; | |
8544 | } | |
8545 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8546 | { |
8547 | s += 3; | |
8548 | regno = FP; | |
8549 | } | |
8550 | else if (s[1] == 's' && s[2] == 'p') | |
8551 | { | |
8552 | s += 3; | |
8553 | regno = SP; | |
8554 | } | |
8555 | else if (s[1] == 'g' && s[2] == 'p') | |
8556 | { | |
8557 | s += 3; | |
8558 | regno = GP; | |
8559 | } | |
8560 | else if (s[1] == 'a' && s[2] == 't') | |
8561 | { | |
8562 | s += 3; | |
8563 | regno = AT; | |
8564 | } | |
8565 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8566 | { | |
8567 | s += 4; | |
8568 | regno = KT0; | |
8569 | } | |
8570 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8571 | { | |
8572 | s += 4; | |
8573 | regno = KT1; | |
8574 | } | |
85b51719 TS |
8575 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8576 | { | |
8577 | s += 5; | |
8578 | regno = ZERO; | |
8579 | } | |
252b5132 RH |
8580 | else if (itbl_have_entries) |
8581 | { | |
8582 | char *p, *n; | |
d7ba4a77 | 8583 | unsigned long r; |
252b5132 | 8584 | |
d7ba4a77 | 8585 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8586 | n = itbl_get_field (&p); /* n is name */ |
8587 | ||
d7ba4a77 ILT |
8588 | /* See if this is a register defined in an |
8589 | itbl entry. */ | |
8590 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8591 | { |
8592 | /* Get_field advances to the start of | |
8593 | the next field, so we need to back | |
d7ba4a77 | 8594 | rack to the end of the last field. */ |
bdaaa2e1 | 8595 | if (p) |
252b5132 | 8596 | s = p - 1; |
bdaaa2e1 | 8597 | else |
d7ba4a77 | 8598 | s = strchr (s, '\0'); |
252b5132 RH |
8599 | regno = r; |
8600 | } | |
8601 | else | |
8602 | goto notreg; | |
beae10d5 | 8603 | } |
252b5132 RH |
8604 | else |
8605 | goto notreg; | |
8606 | } | |
8607 | if (regno == AT | |
8608 | && ! mips_opts.noat | |
8609 | && *args != 'E' | |
af7ee8bf CD |
8610 | && *args != 'G' |
8611 | && *args != 'K') | |
252b5132 RH |
8612 | as_warn (_("Used $at without \".set noat\"")); |
8613 | c = *args; | |
8614 | if (*s == ' ') | |
f9419b05 | 8615 | ++s; |
252b5132 RH |
8616 | if (args[1] != *s) |
8617 | { | |
8618 | if (c == 'r' || c == 'v' || c == 'w') | |
8619 | { | |
8620 | regno = lastregno; | |
8621 | s = s_reset; | |
f9419b05 | 8622 | ++args; |
252b5132 RH |
8623 | } |
8624 | } | |
8625 | /* 'z' only matches $0. */ | |
8626 | if (c == 'z' && regno != 0) | |
8627 | break; | |
8628 | ||
bdaaa2e1 KH |
8629 | /* Now that we have assembled one operand, we use the args string |
8630 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8631 | switch (c) |
8632 | { | |
8633 | case 'r': | |
8634 | case 's': | |
8635 | case 'v': | |
8636 | case 'b': | |
38487616 | 8637 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8638 | break; |
8639 | case 'd': | |
8640 | case 'G': | |
af7ee8bf | 8641 | case 'K': |
38487616 | 8642 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8643 | break; |
4372b673 | 8644 | case 'U': |
38487616 TS |
8645 | ip->insn_opcode |= regno << OP_SH_RD; |
8646 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8647 | break; |
252b5132 RH |
8648 | case 'w': |
8649 | case 't': | |
8650 | case 'E': | |
38487616 | 8651 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8652 | break; |
8653 | case 'x': | |
8654 | /* This case exists because on the r3000 trunc | |
8655 | expands into a macro which requires a gp | |
8656 | register. On the r6000 or r4000 it is | |
8657 | assembled into a single instruction which | |
8658 | ignores the register. Thus the insn version | |
8659 | is MIPS_ISA2 and uses 'x', and the macro | |
8660 | version is MIPS_ISA1 and uses 't'. */ | |
8661 | break; | |
8662 | case 'z': | |
8663 | /* This case is for the div instruction, which | |
8664 | acts differently if the destination argument | |
8665 | is $0. This only matches $0, and is checked | |
8666 | outside the switch. */ | |
8667 | break; | |
8668 | case 'D': | |
8669 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8670 | break; | |
8671 | /* What about all other operands like 'i', which | |
8672 | can be specified in the opcode table? */ | |
8673 | } | |
8674 | lastregno = regno; | |
8675 | continue; | |
8676 | } | |
8677 | notreg: | |
8678 | switch (*args++) | |
8679 | { | |
8680 | case 'r': | |
8681 | case 'v': | |
38487616 | 8682 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8683 | continue; |
8684 | case 'w': | |
38487616 | 8685 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8686 | continue; |
8687 | } | |
8688 | break; | |
8689 | ||
deec1734 CD |
8690 | case 'O': /* MDMX alignment immediate constant. */ |
8691 | my_getExpression (&imm_expr, s); | |
8692 | check_absolute_expr (ip, &imm_expr); | |
8693 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8694 | { | |
8695 | as_warn ("Improper align amount (%ld), using low bits", | |
8696 | (long) imm_expr.X_add_number); | |
8697 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8698 | } | |
8699 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8700 | imm_expr.X_op = O_absent; | |
8701 | s = expr_end; | |
8702 | continue; | |
8703 | ||
8704 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8705 | if (s[0] != '$') | |
8706 | { | |
8707 | /* MDMX Immediate. */ | |
8708 | my_getExpression (&imm_expr, s); | |
8709 | check_absolute_expr (ip, &imm_expr); | |
8710 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8711 | { | |
8712 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8713 | (long) imm_expr.X_add_number); | |
8714 | imm_expr.X_add_number &= OP_MASK_FT; | |
8715 | } | |
8716 | imm_expr.X_add_number &= OP_MASK_FT; | |
8717 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8718 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8719 | else | |
8720 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8721 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8722 | imm_expr.X_op = O_absent; | |
8723 | s = expr_end; | |
8724 | continue; | |
8725 | } | |
8726 | /* Not MDMX Immediate. Fall through. */ | |
8727 | case 'X': /* MDMX destination register. */ | |
8728 | case 'Y': /* MDMX source register. */ | |
8729 | case 'Z': /* MDMX target register. */ | |
8730 | is_mdmx = 1; | |
252b5132 RH |
8731 | case 'D': /* floating point destination register */ |
8732 | case 'S': /* floating point source register */ | |
8733 | case 'T': /* floating point target register */ | |
8734 | case 'R': /* floating point source register */ | |
8735 | case 'V': | |
8736 | case 'W': | |
8737 | s_reset = s; | |
deec1734 CD |
8738 | /* Accept $fN for FP and MDMX register numbers, and in |
8739 | addition accept $vN for MDMX register numbers. */ | |
8740 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8741 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8742 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8743 | { |
8744 | s += 2; | |
8745 | regno = 0; | |
8746 | do | |
8747 | { | |
8748 | regno *= 10; | |
8749 | regno += *s - '0'; | |
8750 | ++s; | |
8751 | } | |
3882b010 | 8752 | while (ISDIGIT (*s)); |
252b5132 RH |
8753 | |
8754 | if (regno > 31) | |
8755 | as_bad (_("Invalid float register number (%d)"), regno); | |
8756 | ||
8757 | if ((regno & 1) != 0 | |
ca4e0257 | 8758 | && HAVE_32BIT_FPRS |
252b5132 RH |
8759 | && ! (strcmp (str, "mtc1") == 0 |
8760 | || strcmp (str, "mfc1") == 0 | |
8761 | || strcmp (str, "lwc1") == 0 | |
8762 | || strcmp (str, "swc1") == 0 | |
8763 | || strcmp (str, "l.s") == 0 | |
8764 | || strcmp (str, "s.s") == 0)) | |
8765 | as_warn (_("Float register should be even, was %d"), | |
8766 | regno); | |
8767 | ||
8768 | c = *args; | |
8769 | if (*s == ' ') | |
f9419b05 | 8770 | ++s; |
252b5132 RH |
8771 | if (args[1] != *s) |
8772 | { | |
8773 | if (c == 'V' || c == 'W') | |
8774 | { | |
8775 | regno = lastregno; | |
8776 | s = s_reset; | |
f9419b05 | 8777 | ++args; |
252b5132 RH |
8778 | } |
8779 | } | |
8780 | switch (c) | |
8781 | { | |
8782 | case 'D': | |
deec1734 | 8783 | case 'X': |
38487616 | 8784 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8785 | break; |
8786 | case 'V': | |
8787 | case 'S': | |
deec1734 | 8788 | case 'Y': |
38487616 | 8789 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8790 | break; |
deec1734 CD |
8791 | case 'Q': |
8792 | /* This is like 'Z', but also needs to fix the MDMX | |
8793 | vector/scalar select bits. Note that the | |
8794 | scalar immediate case is handled above. */ | |
8795 | if (*s == '[') | |
8796 | { | |
8797 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8798 | int max_el = (is_qh ? 3 : 7); | |
8799 | s++; | |
8800 | my_getExpression(&imm_expr, s); | |
8801 | check_absolute_expr (ip, &imm_expr); | |
8802 | s = expr_end; | |
8803 | if (imm_expr.X_add_number > max_el) | |
8804 | as_bad(_("Bad element selector %ld"), | |
8805 | (long) imm_expr.X_add_number); | |
8806 | imm_expr.X_add_number &= max_el; | |
8807 | ip->insn_opcode |= (imm_expr.X_add_number | |
8808 | << (OP_SH_VSEL + | |
8809 | (is_qh ? 2 : 1))); | |
8810 | if (*s != ']') | |
8811 | as_warn(_("Expecting ']' found '%s'"), s); | |
8812 | else | |
8813 | s++; | |
8814 | } | |
8815 | else | |
8816 | { | |
8817 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8818 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8819 | << OP_SH_VSEL); | |
8820 | else | |
8821 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8822 | OP_SH_VSEL); | |
8823 | } | |
8824 | /* Fall through */ | |
252b5132 RH |
8825 | case 'W': |
8826 | case 'T': | |
deec1734 | 8827 | case 'Z': |
38487616 | 8828 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8829 | break; |
8830 | case 'R': | |
38487616 | 8831 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8832 | break; |
8833 | } | |
8834 | lastregno = regno; | |
8835 | continue; | |
8836 | } | |
8837 | ||
252b5132 RH |
8838 | switch (*args++) |
8839 | { | |
8840 | case 'V': | |
38487616 | 8841 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8842 | continue; |
8843 | case 'W': | |
38487616 | 8844 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8845 | continue; |
8846 | } | |
8847 | break; | |
8848 | ||
8849 | case 'I': | |
8850 | my_getExpression (&imm_expr, s); | |
8851 | if (imm_expr.X_op != O_big | |
8852 | && imm_expr.X_op != O_constant) | |
8853 | insn_error = _("absolute expression required"); | |
8854 | s = expr_end; | |
8855 | continue; | |
8856 | ||
8857 | case 'A': | |
8858 | my_getExpression (&offset_expr, s); | |
f6688943 | 8859 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8860 | s = expr_end; |
8861 | continue; | |
8862 | ||
8863 | case 'F': | |
8864 | case 'L': | |
8865 | case 'f': | |
8866 | case 'l': | |
8867 | { | |
8868 | int f64; | |
ca4e0257 | 8869 | int using_gprs; |
252b5132 RH |
8870 | char *save_in; |
8871 | char *err; | |
8872 | unsigned char temp[8]; | |
8873 | int len; | |
8874 | unsigned int length; | |
8875 | segT seg; | |
8876 | subsegT subseg; | |
8877 | char *p; | |
8878 | ||
8879 | /* These only appear as the last operand in an | |
8880 | instruction, and every instruction that accepts | |
8881 | them in any variant accepts them in all variants. | |
8882 | This means we don't have to worry about backing out | |
8883 | any changes if the instruction does not match. | |
8884 | ||
8885 | The difference between them is the size of the | |
8886 | floating point constant and where it goes. For 'F' | |
8887 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8888 | is 32 bits. Where the constant is placed is based | |
8889 | on how the MIPS assembler does things: | |
8890 | F -- .rdata | |
8891 | L -- .lit8 | |
8892 | f -- immediate value | |
8893 | l -- .lit4 | |
8894 | ||
8895 | The .lit4 and .lit8 sections are only used if | |
8896 | permitted by the -G argument. | |
8897 | ||
8898 | When generating embedded PIC code, we use the | |
8899 | .lit8 section but not the .lit4 section (we can do | |
8900 | .lit4 inline easily; we need to put .lit8 | |
8901 | somewhere in the data segment, and using .lit8 | |
8902 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8903 | .lit8 entries). |
8904 | ||
8905 | The code below needs to know whether the target register | |
8906 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8907 | 'F' are used with GPR-based instructions and 'l' and | |
8908 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8909 | |
8910 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8911 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8912 | |
8913 | save_in = input_line_pointer; | |
8914 | input_line_pointer = s; | |
8915 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8916 | length = len; | |
8917 | s = input_line_pointer; | |
8918 | input_line_pointer = save_in; | |
8919 | if (err != NULL && *err != '\0') | |
8920 | { | |
8921 | as_bad (_("Bad floating point constant: %s"), err); | |
8922 | memset (temp, '\0', sizeof temp); | |
8923 | length = f64 ? 8 : 4; | |
8924 | } | |
8925 | ||
156c2f8b | 8926 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8927 | |
8928 | if (*args == 'f' | |
8929 | || (*args == 'l' | |
8930 | && (! USE_GLOBAL_POINTER_OPT | |
8931 | || mips_pic == EMBEDDED_PIC | |
8932 | || g_switch_value < 4 | |
8933 | || (temp[0] == 0 && temp[1] == 0) | |
8934 | || (temp[2] == 0 && temp[3] == 0)))) | |
8935 | { | |
8936 | imm_expr.X_op = O_constant; | |
8937 | if (! target_big_endian) | |
8938 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8939 | else | |
8940 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8941 | } | |
8942 | else if (length > 4 | |
119d663a | 8943 | && ! mips_disable_float_construction |
ca4e0257 RS |
8944 | /* Constants can only be constructed in GPRs and |
8945 | copied to FPRs if the GPRs are at least as wide | |
8946 | as the FPRs. Force the constant into memory if | |
8947 | we are using 64-bit FPRs but the GPRs are only | |
8948 | 32 bits wide. */ | |
8949 | && (using_gprs | |
8950 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8951 | && ((temp[0] == 0 && temp[1] == 0) |
8952 | || (temp[2] == 0 && temp[3] == 0)) | |
8953 | && ((temp[4] == 0 && temp[5] == 0) | |
8954 | || (temp[6] == 0 && temp[7] == 0))) | |
8955 | { | |
ca4e0257 RS |
8956 | /* The value is simple enough to load with a couple of |
8957 | instructions. If using 32-bit registers, set | |
8958 | imm_expr to the high order 32 bits and offset_expr to | |
8959 | the low order 32 bits. Otherwise, set imm_expr to | |
8960 | the entire 64 bit constant. */ | |
8961 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8962 | { |
8963 | imm_expr.X_op = O_constant; | |
8964 | offset_expr.X_op = O_constant; | |
8965 | if (! target_big_endian) | |
8966 | { | |
8967 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8968 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8969 | } | |
8970 | else | |
8971 | { | |
8972 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8973 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8974 | } | |
8975 | if (offset_expr.X_add_number == 0) | |
8976 | offset_expr.X_op = O_absent; | |
8977 | } | |
8978 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8979 | { | |
8980 | imm_expr.X_op = O_constant; | |
8981 | if (! target_big_endian) | |
8982 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8983 | else | |
8984 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8985 | } | |
8986 | else | |
8987 | { | |
8988 | imm_expr.X_op = O_big; | |
8989 | imm_expr.X_add_number = 4; | |
8990 | if (! target_big_endian) | |
8991 | { | |
8992 | generic_bignum[0] = bfd_getl16 (temp); | |
8993 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8994 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8995 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8996 | } | |
8997 | else | |
8998 | { | |
8999 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9000 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9001 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9002 | generic_bignum[3] = bfd_getb16 (temp); | |
9003 | } | |
9004 | } | |
9005 | } | |
9006 | else | |
9007 | { | |
9008 | const char *newname; | |
9009 | segT new_seg; | |
9010 | ||
9011 | /* Switch to the right section. */ | |
9012 | seg = now_seg; | |
9013 | subseg = now_subseg; | |
9014 | switch (*args) | |
9015 | { | |
9016 | default: /* unused default case avoids warnings. */ | |
9017 | case 'L': | |
9018 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9019 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9020 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9021 | newname = ".lit8"; |
9022 | break; | |
9023 | case 'F': | |
bb2d6cd7 GK |
9024 | if (mips_pic == EMBEDDED_PIC) |
9025 | newname = ".lit8"; | |
9026 | else | |
9027 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9028 | break; |
9029 | case 'l': | |
9030 | assert (!USE_GLOBAL_POINTER_OPT | |
9031 | || g_switch_value >= 4); | |
9032 | newname = ".lit4"; | |
9033 | break; | |
9034 | } | |
9035 | new_seg = subseg_new (newname, (subsegT) 0); | |
9036 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9037 | bfd_set_section_flags (stdoutput, new_seg, | |
9038 | (SEC_ALLOC | |
9039 | | SEC_LOAD | |
9040 | | SEC_READONLY | |
9041 | | SEC_DATA)); | |
9042 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9043 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9044 | && strcmp (TARGET_OS, "elf") != 0) | |
9045 | record_alignment (new_seg, 4); | |
9046 | else | |
9047 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9048 | if (seg == now_seg) | |
9049 | as_bad (_("Can't use floating point insn in this section")); | |
9050 | ||
9051 | /* Set the argument to the current address in the | |
9052 | section. */ | |
9053 | offset_expr.X_op = O_symbol; | |
9054 | offset_expr.X_add_symbol = | |
9055 | symbol_new ("L0\001", now_seg, | |
9056 | (valueT) frag_now_fix (), frag_now); | |
9057 | offset_expr.X_add_number = 0; | |
9058 | ||
9059 | /* Put the floating point number into the section. */ | |
9060 | p = frag_more ((int) length); | |
9061 | memcpy (p, temp, length); | |
9062 | ||
9063 | /* Switch back to the original section. */ | |
9064 | subseg_set (seg, subseg); | |
9065 | } | |
9066 | } | |
9067 | continue; | |
9068 | ||
9069 | case 'i': /* 16 bit unsigned immediate */ | |
9070 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9071 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9072 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9073 | { |
9074 | int more; | |
5e0116d5 RS |
9075 | offsetT minval, maxval; |
9076 | ||
9077 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9078 | && strcmp (insn->name, insn[1].name) == 0); | |
9079 | ||
9080 | /* If the expression was written as an unsigned number, | |
9081 | only treat it as signed if there are no more | |
9082 | alternatives. */ | |
9083 | if (more | |
9084 | && *args == 'j' | |
9085 | && sizeof (imm_expr.X_add_number) <= 4 | |
9086 | && imm_expr.X_op == O_constant | |
9087 | && imm_expr.X_add_number < 0 | |
9088 | && imm_expr.X_unsigned | |
9089 | && HAVE_64BIT_GPRS) | |
9090 | break; | |
9091 | ||
9092 | /* For compatibility with older assemblers, we accept | |
9093 | 0x8000-0xffff as signed 16-bit numbers when only | |
9094 | signed numbers are allowed. */ | |
9095 | if (*args == 'i') | |
9096 | minval = 0, maxval = 0xffff; | |
9097 | else if (more) | |
9098 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9099 | else |
5e0116d5 RS |
9100 | minval = -0x8000, maxval = 0xffff; |
9101 | ||
9102 | if (imm_expr.X_op != O_constant | |
9103 | || imm_expr.X_add_number < minval | |
9104 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9105 | { |
9106 | if (more) | |
9107 | break; | |
2ae7e77b AH |
9108 | if (imm_expr.X_op == O_constant |
9109 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9110 | as_bad (_("expression out of range")); |
252b5132 RH |
9111 | } |
9112 | } | |
9113 | s = expr_end; | |
9114 | continue; | |
9115 | ||
9116 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9117 | /* Check whether there is only a single bracketed expression |
9118 | left. If so, it must be the base register and the | |
9119 | constant must be zero. */ | |
9120 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9121 | { | |
9122 | offset_expr.X_op = O_constant; | |
9123 | offset_expr.X_add_number = 0; | |
9124 | continue; | |
9125 | } | |
252b5132 RH |
9126 | |
9127 | /* If this value won't fit into a 16 bit offset, then go | |
9128 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9129 | code pattern. */ |
5e0116d5 | 9130 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9131 | && (offset_expr.X_op != O_constant |
9132 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9133 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9134 | break; |
9135 | ||
252b5132 RH |
9136 | s = expr_end; |
9137 | continue; | |
9138 | ||
9139 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9140 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9141 | my_getExpression (&offset_expr, s); |
9142 | s = expr_end; | |
9143 | continue; | |
9144 | ||
9145 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9146 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9147 | && imm_expr.X_op == O_constant | |
9148 | && (imm_expr.X_add_number < 0 | |
9149 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9150 | as_bad (_("lui expression not in range 0..65535")); |
9151 | s = expr_end; | |
9152 | continue; | |
9153 | ||
9154 | case 'a': /* 26 bit address */ | |
9155 | my_getExpression (&offset_expr, s); | |
9156 | s = expr_end; | |
f6688943 | 9157 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9158 | continue; |
9159 | ||
9160 | case 'N': /* 3 bit branch condition code */ | |
9161 | case 'M': /* 3 bit compare condition code */ | |
9162 | if (strncmp (s, "$fcc", 4) != 0) | |
9163 | break; | |
9164 | s += 4; | |
9165 | regno = 0; | |
9166 | do | |
9167 | { | |
9168 | regno *= 10; | |
9169 | regno += *s - '0'; | |
9170 | ++s; | |
9171 | } | |
3882b010 | 9172 | while (ISDIGIT (*s)); |
252b5132 RH |
9173 | if (regno > 7) |
9174 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9175 | if (*args == 'N') | |
9176 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9177 | else | |
9178 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9179 | continue; |
252b5132 | 9180 | |
156c2f8b NC |
9181 | case 'H': |
9182 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9183 | s += 2; | |
3882b010 | 9184 | if (ISDIGIT (*s)) |
156c2f8b NC |
9185 | { |
9186 | c = 0; | |
9187 | do | |
9188 | { | |
9189 | c *= 10; | |
9190 | c += *s - '0'; | |
9191 | ++s; | |
9192 | } | |
3882b010 | 9193 | while (ISDIGIT (*s)); |
156c2f8b NC |
9194 | } |
9195 | else | |
9196 | c = 8; /* Invalid sel value. */ | |
9197 | ||
9198 | if (c > 7) | |
9199 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9200 | ip->insn_opcode |= c; | |
9201 | continue; | |
9202 | ||
60b63b72 RS |
9203 | case 'e': |
9204 | /* Must be at least one digit. */ | |
9205 | my_getExpression (&imm_expr, s); | |
9206 | check_absolute_expr (ip, &imm_expr); | |
9207 | ||
9208 | if ((unsigned long) imm_expr.X_add_number | |
9209 | > (unsigned long) OP_MASK_VECBYTE) | |
9210 | { | |
9211 | as_bad (_("bad byte vector index (%ld)"), | |
9212 | (long) imm_expr.X_add_number); | |
9213 | imm_expr.X_add_number = 0; | |
9214 | } | |
9215 | ||
9216 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9217 | imm_expr.X_op = O_absent; | |
9218 | s = expr_end; | |
9219 | continue; | |
9220 | ||
9221 | case '%': | |
9222 | my_getExpression (&imm_expr, s); | |
9223 | check_absolute_expr (ip, &imm_expr); | |
9224 | ||
9225 | if ((unsigned long) imm_expr.X_add_number | |
9226 | > (unsigned long) OP_MASK_VECALIGN) | |
9227 | { | |
9228 | as_bad (_("bad byte vector index (%ld)"), | |
9229 | (long) imm_expr.X_add_number); | |
9230 | imm_expr.X_add_number = 0; | |
9231 | } | |
9232 | ||
9233 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9234 | imm_expr.X_op = O_absent; | |
9235 | s = expr_end; | |
9236 | continue; | |
9237 | ||
252b5132 RH |
9238 | default: |
9239 | as_bad (_("bad char = '%c'\n"), *args); | |
9240 | internalError (); | |
9241 | } | |
9242 | break; | |
9243 | } | |
9244 | /* Args don't match. */ | |
9245 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9246 | !strcmp (insn->name, insn[1].name)) | |
9247 | { | |
9248 | ++insn; | |
9249 | s = argsStart; | |
268f6bed | 9250 | insn_error = _("illegal operands"); |
252b5132 RH |
9251 | continue; |
9252 | } | |
268f6bed L |
9253 | if (save_c) |
9254 | *(--s) = save_c; | |
252b5132 RH |
9255 | insn_error = _("illegal operands"); |
9256 | return; | |
9257 | } | |
9258 | } | |
9259 | ||
9260 | /* This routine assembles an instruction into its binary format when | |
9261 | assembling for the mips16. As a side effect, it sets one of the | |
9262 | global variables imm_reloc or offset_reloc to the type of | |
9263 | relocation to do if one of the operands is an address expression. | |
9264 | It also sets mips16_small and mips16_ext if the user explicitly | |
9265 | requested a small or extended instruction. */ | |
9266 | ||
9267 | static void | |
17a2f251 | 9268 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9269 | { |
9270 | char *s; | |
9271 | const char *args; | |
9272 | struct mips_opcode *insn; | |
9273 | char *argsstart; | |
9274 | unsigned int regno; | |
9275 | unsigned int lastregno = 0; | |
9276 | char *s_reset; | |
9277 | ||
9278 | insn_error = NULL; | |
9279 | ||
b34976b6 AM |
9280 | mips16_small = FALSE; |
9281 | mips16_ext = FALSE; | |
252b5132 | 9282 | |
3882b010 | 9283 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9284 | ; |
9285 | switch (*s) | |
9286 | { | |
9287 | case '\0': | |
9288 | break; | |
9289 | ||
9290 | case ' ': | |
9291 | *s++ = '\0'; | |
9292 | break; | |
9293 | ||
9294 | case '.': | |
9295 | if (s[1] == 't' && s[2] == ' ') | |
9296 | { | |
9297 | *s = '\0'; | |
b34976b6 | 9298 | mips16_small = TRUE; |
252b5132 RH |
9299 | s += 3; |
9300 | break; | |
9301 | } | |
9302 | else if (s[1] == 'e' && s[2] == ' ') | |
9303 | { | |
9304 | *s = '\0'; | |
b34976b6 | 9305 | mips16_ext = TRUE; |
252b5132 RH |
9306 | s += 3; |
9307 | break; | |
9308 | } | |
9309 | /* Fall through. */ | |
9310 | default: | |
9311 | insn_error = _("unknown opcode"); | |
9312 | return; | |
9313 | } | |
9314 | ||
9315 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9316 | mips16_small = TRUE; |
252b5132 RH |
9317 | |
9318 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9319 | { | |
9320 | insn_error = _("unrecognized opcode"); | |
9321 | return; | |
9322 | } | |
9323 | ||
9324 | argsstart = s; | |
9325 | for (;;) | |
9326 | { | |
9327 | assert (strcmp (insn->name, str) == 0); | |
9328 | ||
9329 | ip->insn_mo = insn; | |
9330 | ip->insn_opcode = insn->match; | |
b34976b6 | 9331 | ip->use_extend = FALSE; |
252b5132 | 9332 | imm_expr.X_op = O_absent; |
f6688943 TS |
9333 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9334 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9335 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9336 | offset_expr.X_op = O_absent; |
f6688943 TS |
9337 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9338 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9339 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9340 | for (args = insn->args; 1; ++args) |
9341 | { | |
9342 | int c; | |
9343 | ||
9344 | if (*s == ' ') | |
9345 | ++s; | |
9346 | ||
9347 | /* In this switch statement we call break if we did not find | |
9348 | a match, continue if we did find a match, or return if we | |
9349 | are done. */ | |
9350 | ||
9351 | c = *args; | |
9352 | switch (c) | |
9353 | { | |
9354 | case '\0': | |
9355 | if (*s == '\0') | |
9356 | { | |
9357 | /* Stuff the immediate value in now, if we can. */ | |
9358 | if (imm_expr.X_op == O_constant | |
f6688943 | 9359 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9360 | && insn->pinfo != INSN_MACRO) |
9361 | { | |
c4e7957c | 9362 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9363 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9364 | mips16_ext, &ip->insn_opcode, |
9365 | &ip->use_extend, &ip->extend); | |
9366 | imm_expr.X_op = O_absent; | |
f6688943 | 9367 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9368 | } |
9369 | ||
9370 | return; | |
9371 | } | |
9372 | break; | |
9373 | ||
9374 | case ',': | |
9375 | if (*s++ == c) | |
9376 | continue; | |
9377 | s--; | |
9378 | switch (*++args) | |
9379 | { | |
9380 | case 'v': | |
9381 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9382 | continue; | |
9383 | case 'w': | |
9384 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9385 | continue; | |
9386 | } | |
9387 | break; | |
9388 | ||
9389 | case '(': | |
9390 | case ')': | |
9391 | if (*s++ == c) | |
9392 | continue; | |
9393 | break; | |
9394 | ||
9395 | case 'v': | |
9396 | case 'w': | |
9397 | if (s[0] != '$') | |
9398 | { | |
9399 | if (c == 'v') | |
9400 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9401 | else | |
9402 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9403 | ++args; | |
9404 | continue; | |
9405 | } | |
9406 | /* Fall through. */ | |
9407 | case 'x': | |
9408 | case 'y': | |
9409 | case 'z': | |
9410 | case 'Z': | |
9411 | case '0': | |
9412 | case 'S': | |
9413 | case 'R': | |
9414 | case 'X': | |
9415 | case 'Y': | |
9416 | if (s[0] != '$') | |
9417 | break; | |
9418 | s_reset = s; | |
3882b010 | 9419 | if (ISDIGIT (s[1])) |
252b5132 RH |
9420 | { |
9421 | ++s; | |
9422 | regno = 0; | |
9423 | do | |
9424 | { | |
9425 | regno *= 10; | |
9426 | regno += *s - '0'; | |
9427 | ++s; | |
9428 | } | |
3882b010 | 9429 | while (ISDIGIT (*s)); |
252b5132 RH |
9430 | if (regno > 31) |
9431 | { | |
9432 | as_bad (_("invalid register number (%d)"), regno); | |
9433 | regno = 2; | |
9434 | } | |
9435 | } | |
9436 | else | |
9437 | { | |
76db943d TS |
9438 | if (s[1] == 'r' && s[2] == 'a') |
9439 | { | |
9440 | s += 3; | |
9441 | regno = RA; | |
9442 | } | |
9443 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9444 | { |
9445 | s += 3; | |
9446 | regno = FP; | |
9447 | } | |
9448 | else if (s[1] == 's' && s[2] == 'p') | |
9449 | { | |
9450 | s += 3; | |
9451 | regno = SP; | |
9452 | } | |
9453 | else if (s[1] == 'g' && s[2] == 'p') | |
9454 | { | |
9455 | s += 3; | |
9456 | regno = GP; | |
9457 | } | |
9458 | else if (s[1] == 'a' && s[2] == 't') | |
9459 | { | |
9460 | s += 3; | |
9461 | regno = AT; | |
9462 | } | |
9463 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9464 | { | |
9465 | s += 4; | |
9466 | regno = KT0; | |
9467 | } | |
9468 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9469 | { | |
9470 | s += 4; | |
9471 | regno = KT1; | |
9472 | } | |
85b51719 TS |
9473 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9474 | { | |
9475 | s += 5; | |
9476 | regno = ZERO; | |
9477 | } | |
252b5132 RH |
9478 | else |
9479 | break; | |
9480 | } | |
9481 | ||
9482 | if (*s == ' ') | |
9483 | ++s; | |
9484 | if (args[1] != *s) | |
9485 | { | |
9486 | if (c == 'v' || c == 'w') | |
9487 | { | |
9488 | regno = mips16_to_32_reg_map[lastregno]; | |
9489 | s = s_reset; | |
f9419b05 | 9490 | ++args; |
252b5132 RH |
9491 | } |
9492 | } | |
9493 | ||
9494 | switch (c) | |
9495 | { | |
9496 | case 'x': | |
9497 | case 'y': | |
9498 | case 'z': | |
9499 | case 'v': | |
9500 | case 'w': | |
9501 | case 'Z': | |
9502 | regno = mips32_to_16_reg_map[regno]; | |
9503 | break; | |
9504 | ||
9505 | case '0': | |
9506 | if (regno != 0) | |
9507 | regno = ILLEGAL_REG; | |
9508 | break; | |
9509 | ||
9510 | case 'S': | |
9511 | if (regno != SP) | |
9512 | regno = ILLEGAL_REG; | |
9513 | break; | |
9514 | ||
9515 | case 'R': | |
9516 | if (regno != RA) | |
9517 | regno = ILLEGAL_REG; | |
9518 | break; | |
9519 | ||
9520 | case 'X': | |
9521 | case 'Y': | |
9522 | if (regno == AT && ! mips_opts.noat) | |
9523 | as_warn (_("used $at without \".set noat\"")); | |
9524 | break; | |
9525 | ||
9526 | default: | |
9527 | internalError (); | |
9528 | } | |
9529 | ||
9530 | if (regno == ILLEGAL_REG) | |
9531 | break; | |
9532 | ||
9533 | switch (c) | |
9534 | { | |
9535 | case 'x': | |
9536 | case 'v': | |
9537 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9538 | break; | |
9539 | case 'y': | |
9540 | case 'w': | |
9541 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9542 | break; | |
9543 | case 'z': | |
9544 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9545 | break; | |
9546 | case 'Z': | |
9547 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9548 | case '0': | |
9549 | case 'S': | |
9550 | case 'R': | |
9551 | break; | |
9552 | case 'X': | |
9553 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9554 | break; | |
9555 | case 'Y': | |
9556 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9557 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9558 | break; | |
9559 | default: | |
9560 | internalError (); | |
9561 | } | |
9562 | ||
9563 | lastregno = regno; | |
9564 | continue; | |
9565 | ||
9566 | case 'P': | |
9567 | if (strncmp (s, "$pc", 3) == 0) | |
9568 | { | |
9569 | s += 3; | |
9570 | continue; | |
9571 | } | |
9572 | break; | |
9573 | ||
9574 | case '<': | |
9575 | case '>': | |
9576 | case '[': | |
9577 | case ']': | |
9578 | case '4': | |
9579 | case '5': | |
9580 | case 'H': | |
9581 | case 'W': | |
9582 | case 'D': | |
9583 | case 'j': | |
9584 | case '8': | |
9585 | case 'V': | |
9586 | case 'C': | |
9587 | case 'U': | |
9588 | case 'k': | |
9589 | case 'K': | |
9590 | if (s[0] == '%' | |
9591 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9592 | { | |
9593 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9594 | and generate the appropriate reloc. If the text | |
9595 | inside %gprel is not a symbol name with an | |
9596 | optional offset, then we generate a normal reloc | |
9597 | and will probably fail later. */ | |
9598 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9599 | if (imm_expr.X_op == O_symbol) | |
9600 | { | |
b34976b6 | 9601 | mips16_ext = TRUE; |
f6688943 | 9602 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9603 | s = expr_end; |
b34976b6 | 9604 | ip->use_extend = TRUE; |
252b5132 RH |
9605 | ip->extend = 0; |
9606 | continue; | |
9607 | } | |
9608 | } | |
9609 | else | |
9610 | { | |
9611 | /* Just pick up a normal expression. */ | |
9612 | my_getExpression (&imm_expr, s); | |
9613 | } | |
9614 | ||
9615 | if (imm_expr.X_op == O_register) | |
9616 | { | |
9617 | /* What we thought was an expression turned out to | |
9618 | be a register. */ | |
9619 | ||
9620 | if (s[0] == '(' && args[1] == '(') | |
9621 | { | |
9622 | /* It looks like the expression was omitted | |
9623 | before a register indirection, which means | |
9624 | that the expression is implicitly zero. We | |
9625 | still set up imm_expr, so that we handle | |
9626 | explicit extensions correctly. */ | |
9627 | imm_expr.X_op = O_constant; | |
9628 | imm_expr.X_add_number = 0; | |
f6688943 | 9629 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9630 | continue; |
9631 | } | |
9632 | ||
9633 | break; | |
9634 | } | |
9635 | ||
9636 | /* We need to relax this instruction. */ | |
f6688943 | 9637 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9638 | s = expr_end; |
9639 | continue; | |
9640 | ||
9641 | case 'p': | |
9642 | case 'q': | |
9643 | case 'A': | |
9644 | case 'B': | |
9645 | case 'E': | |
9646 | /* We use offset_reloc rather than imm_reloc for the PC | |
9647 | relative operands. This lets macros with both | |
9648 | immediate and address operands work correctly. */ | |
9649 | my_getExpression (&offset_expr, s); | |
9650 | ||
9651 | if (offset_expr.X_op == O_register) | |
9652 | break; | |
9653 | ||
9654 | /* We need to relax this instruction. */ | |
f6688943 | 9655 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9656 | s = expr_end; |
9657 | continue; | |
9658 | ||
9659 | case '6': /* break code */ | |
9660 | my_getExpression (&imm_expr, s); | |
9661 | check_absolute_expr (ip, &imm_expr); | |
9662 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9663 | { | |
9664 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9665 | ip->insn_mo->name, | |
9666 | (unsigned long) imm_expr.X_add_number); | |
9667 | imm_expr.X_add_number &= 0x3f; | |
9668 | } | |
9669 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9670 | imm_expr.X_op = O_absent; | |
9671 | s = expr_end; | |
9672 | continue; | |
9673 | ||
9674 | case 'a': /* 26 bit address */ | |
9675 | my_getExpression (&offset_expr, s); | |
9676 | s = expr_end; | |
f6688943 | 9677 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9678 | ip->insn_opcode <<= 16; |
9679 | continue; | |
9680 | ||
9681 | case 'l': /* register list for entry macro */ | |
9682 | case 'L': /* register list for exit macro */ | |
9683 | { | |
9684 | int mask; | |
9685 | ||
9686 | if (c == 'l') | |
9687 | mask = 0; | |
9688 | else | |
9689 | mask = 7 << 3; | |
9690 | while (*s != '\0') | |
9691 | { | |
9692 | int freg, reg1, reg2; | |
9693 | ||
9694 | while (*s == ' ' || *s == ',') | |
9695 | ++s; | |
9696 | if (*s != '$') | |
9697 | { | |
9698 | as_bad (_("can't parse register list")); | |
9699 | break; | |
9700 | } | |
9701 | ++s; | |
9702 | if (*s != 'f') | |
9703 | freg = 0; | |
9704 | else | |
9705 | { | |
9706 | freg = 1; | |
9707 | ++s; | |
9708 | } | |
9709 | reg1 = 0; | |
3882b010 | 9710 | while (ISDIGIT (*s)) |
252b5132 RH |
9711 | { |
9712 | reg1 *= 10; | |
9713 | reg1 += *s - '0'; | |
9714 | ++s; | |
9715 | } | |
9716 | if (*s == ' ') | |
9717 | ++s; | |
9718 | if (*s != '-') | |
9719 | reg2 = reg1; | |
9720 | else | |
9721 | { | |
9722 | ++s; | |
9723 | if (*s != '$') | |
9724 | break; | |
9725 | ++s; | |
9726 | if (freg) | |
9727 | { | |
9728 | if (*s == 'f') | |
9729 | ++s; | |
9730 | else | |
9731 | { | |
9732 | as_bad (_("invalid register list")); | |
9733 | break; | |
9734 | } | |
9735 | } | |
9736 | reg2 = 0; | |
3882b010 | 9737 | while (ISDIGIT (*s)) |
252b5132 RH |
9738 | { |
9739 | reg2 *= 10; | |
9740 | reg2 += *s - '0'; | |
9741 | ++s; | |
9742 | } | |
9743 | } | |
9744 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9745 | { | |
9746 | mask &= ~ (7 << 3); | |
9747 | mask |= 5 << 3; | |
9748 | } | |
9749 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9750 | { | |
9751 | mask &= ~ (7 << 3); | |
9752 | mask |= 6 << 3; | |
9753 | } | |
9754 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9755 | mask |= (reg2 - 3) << 3; | |
9756 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9757 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9758 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9759 | mask |= 1; |
9760 | else | |
9761 | { | |
9762 | as_bad (_("invalid register list")); | |
9763 | break; | |
9764 | } | |
9765 | } | |
9766 | /* The mask is filled in in the opcode table for the | |
9767 | benefit of the disassembler. We remove it before | |
9768 | applying the actual mask. */ | |
9769 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9770 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9771 | } | |
9772 | continue; | |
9773 | ||
9774 | case 'e': /* extend code */ | |
9775 | my_getExpression (&imm_expr, s); | |
9776 | check_absolute_expr (ip, &imm_expr); | |
9777 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9778 | { | |
9779 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9780 | ip->insn_mo->name, | |
9781 | (unsigned long) imm_expr.X_add_number); | |
9782 | imm_expr.X_add_number &= 0x7ff; | |
9783 | } | |
9784 | ip->insn_opcode |= imm_expr.X_add_number; | |
9785 | imm_expr.X_op = O_absent; | |
9786 | s = expr_end; | |
9787 | continue; | |
9788 | ||
9789 | default: | |
9790 | internalError (); | |
9791 | } | |
9792 | break; | |
9793 | } | |
9794 | ||
9795 | /* Args don't match. */ | |
9796 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9797 | strcmp (insn->name, insn[1].name) == 0) | |
9798 | { | |
9799 | ++insn; | |
9800 | s = argsstart; | |
9801 | continue; | |
9802 | } | |
9803 | ||
9804 | insn_error = _("illegal operands"); | |
9805 | ||
9806 | return; | |
9807 | } | |
9808 | } | |
9809 | ||
9810 | /* This structure holds information we know about a mips16 immediate | |
9811 | argument type. */ | |
9812 | ||
e972090a NC |
9813 | struct mips16_immed_operand |
9814 | { | |
252b5132 RH |
9815 | /* The type code used in the argument string in the opcode table. */ |
9816 | int type; | |
9817 | /* The number of bits in the short form of the opcode. */ | |
9818 | int nbits; | |
9819 | /* The number of bits in the extended form of the opcode. */ | |
9820 | int extbits; | |
9821 | /* The amount by which the short form is shifted when it is used; | |
9822 | for example, the sw instruction has a shift count of 2. */ | |
9823 | int shift; | |
9824 | /* The amount by which the short form is shifted when it is stored | |
9825 | into the instruction code. */ | |
9826 | int op_shift; | |
9827 | /* Non-zero if the short form is unsigned. */ | |
9828 | int unsp; | |
9829 | /* Non-zero if the extended form is unsigned. */ | |
9830 | int extu; | |
9831 | /* Non-zero if the value is PC relative. */ | |
9832 | int pcrel; | |
9833 | }; | |
9834 | ||
9835 | /* The mips16 immediate operand types. */ | |
9836 | ||
9837 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9838 | { | |
9839 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9840 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9841 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9842 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9843 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9844 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9845 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9846 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9847 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9848 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9849 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9850 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9851 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9852 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9853 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9854 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9855 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9856 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9857 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9858 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9859 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9860 | }; | |
9861 | ||
9862 | #define MIPS16_NUM_IMMED \ | |
9863 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9864 | ||
9865 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9866 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9867 | whether an extended value is needed; if one is needed, it sets | |
9868 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9869 | If SMALL is true, an unextended opcode was explicitly requested. | |
9870 | If EXT is true, an extended opcode was explicitly requested. If | |
9871 | WARN is true, warn if EXT does not match reality. */ | |
9872 | ||
9873 | static void | |
17a2f251 TS |
9874 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9875 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9876 | unsigned long *insn, bfd_boolean *use_extend, | |
9877 | unsigned short *extend) | |
252b5132 RH |
9878 | { |
9879 | register const struct mips16_immed_operand *op; | |
9880 | int mintiny, maxtiny; | |
b34976b6 | 9881 | bfd_boolean needext; |
252b5132 RH |
9882 | |
9883 | op = mips16_immed_operands; | |
9884 | while (op->type != type) | |
9885 | { | |
9886 | ++op; | |
9887 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9888 | } | |
9889 | ||
9890 | if (op->unsp) | |
9891 | { | |
9892 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9893 | { | |
9894 | mintiny = 1; | |
9895 | maxtiny = 1 << op->nbits; | |
9896 | } | |
9897 | else | |
9898 | { | |
9899 | mintiny = 0; | |
9900 | maxtiny = (1 << op->nbits) - 1; | |
9901 | } | |
9902 | } | |
9903 | else | |
9904 | { | |
9905 | mintiny = - (1 << (op->nbits - 1)); | |
9906 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9907 | } | |
9908 | ||
9909 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9910 | if (type == 'p' || type == 'q') | |
9911 | val /= 2; | |
9912 | ||
9913 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9914 | || val < (mintiny << op->shift) | |
9915 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9916 | needext = TRUE; |
252b5132 | 9917 | else |
b34976b6 | 9918 | needext = FALSE; |
252b5132 RH |
9919 | |
9920 | if (warn && ext && ! needext) | |
beae10d5 KH |
9921 | as_warn_where (file, line, |
9922 | _("extended operand requested but not required")); | |
252b5132 RH |
9923 | if (small && needext) |
9924 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9925 | ||
9926 | if (small || (! ext && ! needext)) | |
9927 | { | |
9928 | int insnval; | |
9929 | ||
b34976b6 | 9930 | *use_extend = FALSE; |
252b5132 RH |
9931 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9932 | insnval <<= op->op_shift; | |
9933 | *insn |= insnval; | |
9934 | } | |
9935 | else | |
9936 | { | |
9937 | long minext, maxext; | |
9938 | int extval; | |
9939 | ||
9940 | if (op->extu) | |
9941 | { | |
9942 | minext = 0; | |
9943 | maxext = (1 << op->extbits) - 1; | |
9944 | } | |
9945 | else | |
9946 | { | |
9947 | minext = - (1 << (op->extbits - 1)); | |
9948 | maxext = (1 << (op->extbits - 1)) - 1; | |
9949 | } | |
9950 | if (val < minext || val > maxext) | |
9951 | as_bad_where (file, line, | |
9952 | _("operand value out of range for instruction")); | |
9953 | ||
b34976b6 | 9954 | *use_extend = TRUE; |
252b5132 RH |
9955 | if (op->extbits == 16) |
9956 | { | |
9957 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9958 | val &= 0x1f; | |
9959 | } | |
9960 | else if (op->extbits == 15) | |
9961 | { | |
9962 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9963 | val &= 0xf; | |
9964 | } | |
9965 | else | |
9966 | { | |
9967 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9968 | val = 0; | |
9969 | } | |
9970 | ||
9971 | *extend = (unsigned short) extval; | |
9972 | *insn |= val; | |
9973 | } | |
9974 | } | |
9975 | \f | |
5e0116d5 | 9976 | static const struct percent_op_match |
ad8d3bb3 | 9977 | { |
5e0116d5 RS |
9978 | const char *str; |
9979 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9980 | } percent_op[] = |
9981 | { | |
5e0116d5 | 9982 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9983 | #ifdef OBJ_ELF |
5e0116d5 RS |
9984 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9985 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9986 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9987 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9988 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9989 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9990 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9991 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9992 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9993 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9994 | {"%half", BFD_RELOC_16}, | |
9995 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9996 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9997 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9998 | #endif |
5e0116d5 | 9999 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10000 | }; |
10001 | ||
252b5132 | 10002 | |
5e0116d5 RS |
10003 | /* Return true if *STR points to a relocation operator. When returning true, |
10004 | move *STR over the operator and store its relocation code in *RELOC. | |
10005 | Leave both *STR and *RELOC alone when returning false. */ | |
10006 | ||
10007 | static bfd_boolean | |
17a2f251 | 10008 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10009 | { |
5e0116d5 | 10010 | size_t i; |
76b3015f | 10011 | |
5e0116d5 RS |
10012 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10013 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10014 | { |
5e0116d5 RS |
10015 | *str += strlen (percent_op[i].str); |
10016 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10017 | |
5e0116d5 RS |
10018 | /* Check whether the output BFD supports this relocation. |
10019 | If not, issue an error and fall back on something safe. */ | |
10020 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10021 | { |
5e0116d5 RS |
10022 | as_bad ("relocation %s isn't supported by the current ABI", |
10023 | percent_op[i].str); | |
10024 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10025 | } |
5e0116d5 | 10026 | return TRUE; |
394f9b3a | 10027 | } |
5e0116d5 | 10028 | return FALSE; |
394f9b3a | 10029 | } |
ad8d3bb3 | 10030 | |
ad8d3bb3 | 10031 | |
5e0116d5 RS |
10032 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10033 | expression in *EP and the relocations in the array starting | |
10034 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10035 | |
5e0116d5 RS |
10036 | On exit, EXPR_END points to the first character after the expression. |
10037 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10038 | |
5e0116d5 | 10039 | static size_t |
17a2f251 TS |
10040 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10041 | char *str) | |
ad8d3bb3 | 10042 | { |
5e0116d5 RS |
10043 | bfd_reloc_code_real_type reversed_reloc[3]; |
10044 | size_t reloc_index, i; | |
09b8f35a RS |
10045 | int crux_depth, str_depth; |
10046 | char *crux; | |
5e0116d5 RS |
10047 | |
10048 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10049 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10050 | of the main expression and with CRUX_DEPTH containing the number | |
10051 | of open brackets at that point. */ | |
10052 | reloc_index = -1; | |
10053 | str_depth = 0; | |
10054 | do | |
fb1b3232 | 10055 | { |
09b8f35a RS |
10056 | reloc_index++; |
10057 | crux = str; | |
10058 | crux_depth = str_depth; | |
10059 | ||
10060 | /* Skip over whitespace and brackets, keeping count of the number | |
10061 | of brackets. */ | |
10062 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10063 | if (*str++ == '(') | |
10064 | str_depth++; | |
5e0116d5 | 10065 | } |
09b8f35a RS |
10066 | while (*str == '%' |
10067 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10068 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10069 | |
09b8f35a | 10070 | my_getExpression (ep, crux); |
5e0116d5 | 10071 | str = expr_end; |
394f9b3a | 10072 | |
5e0116d5 | 10073 | /* Match every open bracket. */ |
09b8f35a | 10074 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10075 | if (*str++ == ')') |
09b8f35a | 10076 | crux_depth--; |
394f9b3a | 10077 | |
09b8f35a | 10078 | if (crux_depth > 0) |
5e0116d5 | 10079 | as_bad ("unclosed '('"); |
394f9b3a | 10080 | |
5e0116d5 | 10081 | expr_end = str; |
252b5132 | 10082 | |
64bdfcaf RS |
10083 | if (reloc_index == 0) |
10084 | reloc[0] = BFD_RELOC_LO16; | |
10085 | else | |
10086 | { | |
10087 | prev_reloc_op_frag = frag_now; | |
10088 | for (i = 0; i < reloc_index; i++) | |
10089 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10090 | } | |
fb1b3232 | 10091 | |
5e0116d5 | 10092 | return reloc_index; |
252b5132 RH |
10093 | } |
10094 | ||
10095 | static void | |
17a2f251 | 10096 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10097 | { |
10098 | char *save_in; | |
98aa84af | 10099 | valueT val; |
252b5132 RH |
10100 | |
10101 | save_in = input_line_pointer; | |
10102 | input_line_pointer = str; | |
10103 | expression (ep); | |
10104 | expr_end = input_line_pointer; | |
10105 | input_line_pointer = save_in; | |
10106 | ||
10107 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10108 | then we bump the value of the symbol by 1 since that is how other | |
10109 | text symbols are handled. We don't bother to handle complex | |
10110 | expressions, just `.' plus or minus a constant. */ | |
10111 | if (mips_opts.mips16 | |
10112 | && ep->X_op == O_symbol | |
10113 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10114 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10115 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10116 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10117 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10118 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10119 | } |
10120 | ||
10121 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10122 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10123 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10124 | returned, or NULL on OK. */ |
10125 | ||
10126 | char * | |
17a2f251 | 10127 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10128 | { |
10129 | int prec; | |
10130 | LITTLENUM_TYPE words[4]; | |
10131 | char *t; | |
10132 | int i; | |
10133 | ||
10134 | switch (type) | |
10135 | { | |
10136 | case 'f': | |
10137 | prec = 2; | |
10138 | break; | |
10139 | ||
10140 | case 'd': | |
10141 | prec = 4; | |
10142 | break; | |
10143 | ||
10144 | default: | |
10145 | *sizeP = 0; | |
10146 | return _("bad call to md_atof"); | |
10147 | } | |
10148 | ||
10149 | t = atof_ieee (input_line_pointer, type, words); | |
10150 | if (t) | |
10151 | input_line_pointer = t; | |
10152 | ||
10153 | *sizeP = prec * 2; | |
10154 | ||
10155 | if (! target_big_endian) | |
10156 | { | |
10157 | for (i = prec - 1; i >= 0; i--) | |
10158 | { | |
17a2f251 | 10159 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10160 | litP += 2; |
10161 | } | |
10162 | } | |
10163 | else | |
10164 | { | |
10165 | for (i = 0; i < prec; i++) | |
10166 | { | |
17a2f251 | 10167 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10168 | litP += 2; |
10169 | } | |
10170 | } | |
bdaaa2e1 | 10171 | |
252b5132 RH |
10172 | return NULL; |
10173 | } | |
10174 | ||
10175 | void | |
17a2f251 | 10176 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10177 | { |
10178 | if (target_big_endian) | |
10179 | number_to_chars_bigendian (buf, val, n); | |
10180 | else | |
10181 | number_to_chars_littleendian (buf, val, n); | |
10182 | } | |
10183 | \f | |
ae948b86 | 10184 | #ifdef OBJ_ELF |
e013f690 TS |
10185 | static int support_64bit_objects(void) |
10186 | { | |
10187 | const char **list, **l; | |
aa3d8fdf | 10188 | int yes; |
e013f690 TS |
10189 | |
10190 | list = bfd_target_list (); | |
10191 | for (l = list; *l != NULL; l++) | |
10192 | #ifdef TE_TMIPS | |
10193 | /* This is traditional mips */ | |
10194 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10195 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10196 | #else | |
10197 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10198 | || strcmp (*l, "elf64-littlemips") == 0) | |
10199 | #endif | |
10200 | break; | |
aa3d8fdf | 10201 | yes = (*l != NULL); |
e013f690 | 10202 | free (list); |
aa3d8fdf | 10203 | return yes; |
e013f690 | 10204 | } |
ae948b86 | 10205 | #endif /* OBJ_ELF */ |
e013f690 | 10206 | |
5a38dc70 | 10207 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10208 | |
e972090a NC |
10209 | struct option md_longopts[] = |
10210 | { | |
f9b4148d CD |
10211 | /* Options which specify architecture. */ |
10212 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10213 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10214 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10215 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10216 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10217 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10218 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10219 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10220 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10221 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10222 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10223 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10224 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10225 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10226 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10227 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10228 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10229 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10230 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10231 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10232 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10233 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
10234 | ||
10235 | /* Options which specify Application Specific Extensions (ASEs). */ | |
10236 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10) | |
10237 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) | |
10238 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10239 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10240 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10241 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10242 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10243 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10244 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10245 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10246 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10247 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10248 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10249 | ||
10250 | /* Old-style architecture options. Don't add more of these. */ | |
10251 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10252 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10253 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10254 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10255 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10256 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10257 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10258 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10259 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10260 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10261 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10262 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10263 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10264 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10265 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10266 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10267 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10268 | ||
10269 | /* Options which enable bug fixes. */ | |
10270 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10271 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10272 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10273 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10274 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10275 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10276 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10277 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10278 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10279 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10280 | ||
10281 | /* Miscellaneous options. */ | |
10282 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10283 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10284 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10285 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10286 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10287 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10288 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10289 | {"break", no_argument, NULL, OPTION_BREAK}, |
10290 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10291 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10292 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10293 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10294 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10295 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10296 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10297 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10298 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10299 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10300 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10301 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10302 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10303 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10304 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10305 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10306 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10307 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10308 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10309 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10310 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10311 | |
10312 | /* ELF-specific options. */ | |
156c2f8b | 10313 | #ifdef OBJ_ELF |
f9b4148d | 10314 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10315 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10316 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10317 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10318 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10319 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10320 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10321 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10322 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10323 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10324 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10325 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10326 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10327 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10328 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10329 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10330 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10331 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10332 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10333 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10334 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10335 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10336 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10337 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10338 | #endif /* OBJ_ELF */ |
f9b4148d | 10339 | |
252b5132 RH |
10340 | {NULL, no_argument, NULL, 0} |
10341 | }; | |
156c2f8b | 10342 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10343 | |
316f5878 RS |
10344 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10345 | NEW_VALUE. Warn if another value was already specified. Note: | |
10346 | we have to defer parsing the -march and -mtune arguments in order | |
10347 | to handle 'from-abi' correctly, since the ABI might be specified | |
10348 | in a later argument. */ | |
10349 | ||
10350 | static void | |
17a2f251 | 10351 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10352 | { |
10353 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10354 | as_warn (_("A different %s was already specified, is now %s"), | |
10355 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10356 | new_value); | |
10357 | ||
10358 | *string_ptr = new_value; | |
10359 | } | |
10360 | ||
252b5132 | 10361 | int |
17a2f251 | 10362 | md_parse_option (int c, char *arg) |
252b5132 RH |
10363 | { |
10364 | switch (c) | |
10365 | { | |
119d663a NC |
10366 | case OPTION_CONSTRUCT_FLOATS: |
10367 | mips_disable_float_construction = 0; | |
10368 | break; | |
bdaaa2e1 | 10369 | |
119d663a NC |
10370 | case OPTION_NO_CONSTRUCT_FLOATS: |
10371 | mips_disable_float_construction = 1; | |
10372 | break; | |
bdaaa2e1 | 10373 | |
252b5132 RH |
10374 | case OPTION_TRAP: |
10375 | mips_trap = 1; | |
10376 | break; | |
10377 | ||
10378 | case OPTION_BREAK: | |
10379 | mips_trap = 0; | |
10380 | break; | |
10381 | ||
10382 | case OPTION_EB: | |
10383 | target_big_endian = 1; | |
10384 | break; | |
10385 | ||
10386 | case OPTION_EL: | |
10387 | target_big_endian = 0; | |
10388 | break; | |
10389 | ||
39c0a331 L |
10390 | case 'n': |
10391 | warn_nops = 1; | |
10392 | break; | |
10393 | ||
252b5132 RH |
10394 | case 'O': |
10395 | if (arg && arg[1] == '0') | |
10396 | mips_optimize = 1; | |
10397 | else | |
10398 | mips_optimize = 2; | |
10399 | break; | |
10400 | ||
10401 | case 'g': | |
10402 | if (arg == NULL) | |
10403 | mips_debug = 2; | |
10404 | else | |
10405 | mips_debug = atoi (arg); | |
10406 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10407 | optimizations which limit full symbolic debugging. We take | |
10408 | that to be equivalent to -O0. */ | |
10409 | if (mips_debug == 2) | |
10410 | mips_optimize = 1; | |
10411 | break; | |
10412 | ||
10413 | case OPTION_MIPS1: | |
316f5878 | 10414 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10415 | break; |
10416 | ||
10417 | case OPTION_MIPS2: | |
316f5878 | 10418 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10419 | break; |
10420 | ||
10421 | case OPTION_MIPS3: | |
316f5878 | 10422 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10423 | break; |
10424 | ||
10425 | case OPTION_MIPS4: | |
316f5878 | 10426 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10427 | break; |
10428 | ||
84ea6cf2 | 10429 | case OPTION_MIPS5: |
316f5878 | 10430 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10431 | break; |
10432 | ||
e7af610e | 10433 | case OPTION_MIPS32: |
316f5878 | 10434 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10435 | break; |
10436 | ||
af7ee8bf CD |
10437 | case OPTION_MIPS32R2: |
10438 | file_mips_isa = ISA_MIPS32R2; | |
10439 | break; | |
10440 | ||
84ea6cf2 | 10441 | case OPTION_MIPS64: |
316f5878 | 10442 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10443 | break; |
10444 | ||
ec68c924 | 10445 | case OPTION_MTUNE: |
316f5878 RS |
10446 | mips_set_option_string (&mips_tune_string, arg); |
10447 | break; | |
ec68c924 | 10448 | |
316f5878 RS |
10449 | case OPTION_MARCH: |
10450 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10451 | break; |
10452 | ||
10453 | case OPTION_M4650: | |
316f5878 RS |
10454 | mips_set_option_string (&mips_arch_string, "4650"); |
10455 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10456 | break; |
10457 | ||
10458 | case OPTION_NO_M4650: | |
10459 | break; | |
10460 | ||
10461 | case OPTION_M4010: | |
316f5878 RS |
10462 | mips_set_option_string (&mips_arch_string, "4010"); |
10463 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10464 | break; |
10465 | ||
10466 | case OPTION_NO_M4010: | |
10467 | break; | |
10468 | ||
10469 | case OPTION_M4100: | |
316f5878 RS |
10470 | mips_set_option_string (&mips_arch_string, "4100"); |
10471 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10472 | break; |
10473 | ||
10474 | case OPTION_NO_M4100: | |
10475 | break; | |
10476 | ||
252b5132 | 10477 | case OPTION_M3900: |
316f5878 RS |
10478 | mips_set_option_string (&mips_arch_string, "3900"); |
10479 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10480 | break; |
bdaaa2e1 | 10481 | |
252b5132 RH |
10482 | case OPTION_NO_M3900: |
10483 | break; | |
10484 | ||
deec1734 CD |
10485 | case OPTION_MDMX: |
10486 | mips_opts.ase_mdmx = 1; | |
10487 | break; | |
10488 | ||
10489 | case OPTION_NO_MDMX: | |
10490 | mips_opts.ase_mdmx = 0; | |
10491 | break; | |
10492 | ||
252b5132 RH |
10493 | case OPTION_MIPS16: |
10494 | mips_opts.mips16 = 1; | |
b34976b6 | 10495 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10496 | break; |
10497 | ||
10498 | case OPTION_NO_MIPS16: | |
10499 | mips_opts.mips16 = 0; | |
b34976b6 | 10500 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10501 | break; |
10502 | ||
1f25f5d3 CD |
10503 | case OPTION_MIPS3D: |
10504 | mips_opts.ase_mips3d = 1; | |
10505 | break; | |
10506 | ||
10507 | case OPTION_NO_MIPS3D: | |
10508 | mips_opts.ase_mips3d = 0; | |
10509 | break; | |
10510 | ||
252b5132 RH |
10511 | case OPTION_MEMBEDDED_PIC: |
10512 | mips_pic = EMBEDDED_PIC; | |
10513 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10514 | { | |
10515 | as_bad (_("-G may not be used with embedded PIC code")); | |
10516 | return 0; | |
10517 | } | |
10518 | g_switch_value = 0x7fffffff; | |
10519 | break; | |
10520 | ||
60b63b72 RS |
10521 | case OPTION_FIX_VR4122: |
10522 | mips_fix_4122_bugs = 1; | |
10523 | break; | |
10524 | ||
10525 | case OPTION_NO_FIX_VR4122: | |
10526 | mips_fix_4122_bugs = 0; | |
10527 | break; | |
10528 | ||
4a6a3df4 AO |
10529 | case OPTION_RELAX_BRANCH: |
10530 | mips_relax_branch = 1; | |
10531 | break; | |
10532 | ||
10533 | case OPTION_NO_RELAX_BRANCH: | |
10534 | mips_relax_branch = 0; | |
10535 | break; | |
10536 | ||
0f074f60 | 10537 | #ifdef OBJ_ELF |
252b5132 RH |
10538 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10539 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10540 | intended to be compatible with Irix 5. */ | |
10541 | case OPTION_CALL_SHARED: | |
10542 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10543 | { | |
10544 | as_bad (_("-call_shared is supported only for ELF format")); | |
10545 | return 0; | |
10546 | } | |
10547 | mips_pic = SVR4_PIC; | |
143d77c5 | 10548 | mips_abicalls = TRUE; |
252b5132 RH |
10549 | if (g_switch_seen && g_switch_value != 0) |
10550 | { | |
10551 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10552 | return 0; | |
10553 | } | |
10554 | g_switch_value = 0; | |
10555 | break; | |
10556 | ||
10557 | case OPTION_NON_SHARED: | |
10558 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10559 | { | |
10560 | as_bad (_("-non_shared is supported only for ELF format")); | |
10561 | return 0; | |
10562 | } | |
10563 | mips_pic = NO_PIC; | |
143d77c5 | 10564 | mips_abicalls = FALSE; |
252b5132 RH |
10565 | break; |
10566 | ||
10567 | /* The -xgot option tells the assembler to use 32 offsets when | |
10568 | accessing the got in SVR4_PIC mode. It is for Irix | |
10569 | compatibility. */ | |
10570 | case OPTION_XGOT: | |
10571 | mips_big_got = 1; | |
10572 | break; | |
0f074f60 | 10573 | #endif /* OBJ_ELF */ |
252b5132 RH |
10574 | |
10575 | case 'G': | |
10576 | if (! USE_GLOBAL_POINTER_OPT) | |
10577 | { | |
10578 | as_bad (_("-G is not supported for this configuration")); | |
10579 | return 0; | |
10580 | } | |
10581 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10582 | { | |
10583 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10584 | return 0; | |
10585 | } | |
10586 | else | |
10587 | g_switch_value = atoi (arg); | |
10588 | g_switch_seen = 1; | |
10589 | break; | |
10590 | ||
0f074f60 | 10591 | #ifdef OBJ_ELF |
34ba82a8 TS |
10592 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10593 | and -mabi=64. */ | |
252b5132 | 10594 | case OPTION_32: |
34ba82a8 TS |
10595 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10596 | { | |
10597 | as_bad (_("-32 is supported for ELF format only")); | |
10598 | return 0; | |
10599 | } | |
316f5878 | 10600 | mips_abi = O32_ABI; |
252b5132 RH |
10601 | break; |
10602 | ||
e013f690 | 10603 | case OPTION_N32: |
34ba82a8 TS |
10604 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10605 | { | |
10606 | as_bad (_("-n32 is supported for ELF format only")); | |
10607 | return 0; | |
10608 | } | |
316f5878 | 10609 | mips_abi = N32_ABI; |
e013f690 | 10610 | break; |
252b5132 | 10611 | |
e013f690 | 10612 | case OPTION_64: |
34ba82a8 TS |
10613 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10614 | { | |
10615 | as_bad (_("-64 is supported for ELF format only")); | |
10616 | return 0; | |
10617 | } | |
316f5878 | 10618 | mips_abi = N64_ABI; |
e013f690 TS |
10619 | if (! support_64bit_objects()) |
10620 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10621 | break; |
ae948b86 | 10622 | #endif /* OBJ_ELF */ |
252b5132 | 10623 | |
c97ef257 | 10624 | case OPTION_GP32: |
a325df1d | 10625 | file_mips_gp32 = 1; |
c97ef257 AH |
10626 | break; |
10627 | ||
10628 | case OPTION_GP64: | |
a325df1d | 10629 | file_mips_gp32 = 0; |
c97ef257 | 10630 | break; |
252b5132 | 10631 | |
ca4e0257 | 10632 | case OPTION_FP32: |
a325df1d | 10633 | file_mips_fp32 = 1; |
316f5878 RS |
10634 | break; |
10635 | ||
10636 | case OPTION_FP64: | |
10637 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10638 | break; |
10639 | ||
ae948b86 | 10640 | #ifdef OBJ_ELF |
252b5132 | 10641 | case OPTION_MABI: |
34ba82a8 TS |
10642 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10643 | { | |
10644 | as_bad (_("-mabi is supported for ELF format only")); | |
10645 | return 0; | |
10646 | } | |
e013f690 | 10647 | if (strcmp (arg, "32") == 0) |
316f5878 | 10648 | mips_abi = O32_ABI; |
e013f690 | 10649 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10650 | mips_abi = O64_ABI; |
e013f690 | 10651 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10652 | mips_abi = N32_ABI; |
e013f690 TS |
10653 | else if (strcmp (arg, "64") == 0) |
10654 | { | |
316f5878 | 10655 | mips_abi = N64_ABI; |
e013f690 TS |
10656 | if (! support_64bit_objects()) |
10657 | as_fatal (_("No compiled in support for 64 bit object file " | |
10658 | "format")); | |
10659 | } | |
10660 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10661 | mips_abi = EABI_ABI; |
e013f690 | 10662 | else |
da0e507f TS |
10663 | { |
10664 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10665 | return 0; | |
10666 | } | |
252b5132 | 10667 | break; |
e013f690 | 10668 | #endif /* OBJ_ELF */ |
252b5132 | 10669 | |
6b76fefe | 10670 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10671 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10672 | break; |
10673 | ||
9ee72ff1 | 10674 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10675 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10676 | break; |
10677 | ||
ecb4347a DJ |
10678 | #ifdef OBJ_ELF |
10679 | case OPTION_MDEBUG: | |
b34976b6 | 10680 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10681 | break; |
10682 | ||
10683 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10684 | mips_flag_mdebug = FALSE; |
ecb4347a | 10685 | break; |
dcd410fe RO |
10686 | |
10687 | case OPTION_PDR: | |
10688 | mips_flag_pdr = TRUE; | |
10689 | break; | |
10690 | ||
10691 | case OPTION_NO_PDR: | |
10692 | mips_flag_pdr = FALSE; | |
10693 | break; | |
ecb4347a DJ |
10694 | #endif /* OBJ_ELF */ |
10695 | ||
252b5132 RH |
10696 | default: |
10697 | return 0; | |
10698 | } | |
10699 | ||
10700 | return 1; | |
10701 | } | |
316f5878 RS |
10702 | \f |
10703 | /* Set up globals to generate code for the ISA or processor | |
10704 | described by INFO. */ | |
252b5132 | 10705 | |
252b5132 | 10706 | static void |
17a2f251 | 10707 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10708 | { |
316f5878 | 10709 | if (info != 0) |
252b5132 | 10710 | { |
fef14a42 TS |
10711 | file_mips_arch = info->cpu; |
10712 | mips_opts.arch = info->cpu; | |
316f5878 | 10713 | mips_opts.isa = info->isa; |
252b5132 | 10714 | } |
252b5132 RH |
10715 | } |
10716 | ||
252b5132 | 10717 | |
316f5878 | 10718 | /* Likewise for tuning. */ |
252b5132 | 10719 | |
316f5878 | 10720 | static void |
17a2f251 | 10721 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10722 | { |
10723 | if (info != 0) | |
fef14a42 | 10724 | mips_tune = info->cpu; |
316f5878 | 10725 | } |
80cc45a5 | 10726 | |
34ba82a8 | 10727 | |
252b5132 | 10728 | void |
17a2f251 | 10729 | mips_after_parse_args (void) |
e9670677 | 10730 | { |
fef14a42 TS |
10731 | const struct mips_cpu_info *arch_info = 0; |
10732 | const struct mips_cpu_info *tune_info = 0; | |
10733 | ||
e9670677 MR |
10734 | /* GP relative stuff not working for PE */ |
10735 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10736 | && g_switch_value != 0) | |
10737 | { | |
10738 | if (g_switch_seen) | |
10739 | as_bad (_("-G not supported in this configuration.")); | |
10740 | g_switch_value = 0; | |
10741 | } | |
10742 | ||
cac012d6 AO |
10743 | if (mips_abi == NO_ABI) |
10744 | mips_abi = MIPS_DEFAULT_ABI; | |
10745 | ||
22923709 RS |
10746 | /* The following code determines the architecture and register size. |
10747 | Similar code was added to GCC 3.3 (see override_options() in | |
10748 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10749 | as much as possible. */ | |
e9670677 | 10750 | |
316f5878 | 10751 | if (mips_arch_string != 0) |
fef14a42 | 10752 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10753 | |
316f5878 | 10754 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10755 | { |
316f5878 | 10756 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10757 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10758 | the -march selection (if any). */ |
fef14a42 | 10759 | if (arch_info != 0) |
e9670677 | 10760 | { |
316f5878 RS |
10761 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10762 | There's no harm in specifying both as long as the ISA levels | |
10763 | are the same. */ | |
fef14a42 | 10764 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10765 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10766 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10767 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10768 | } |
316f5878 | 10769 | else |
fef14a42 | 10770 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10771 | } |
10772 | ||
fef14a42 TS |
10773 | if (arch_info == 0) |
10774 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10775 | |
fef14a42 | 10776 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10777 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10778 | arch_info->name); |
10779 | ||
10780 | mips_set_architecture (arch_info); | |
10781 | ||
10782 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10783 | if (mips_tune_string != 0) | |
10784 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10785 | |
fef14a42 TS |
10786 | if (tune_info == 0) |
10787 | mips_set_tune (arch_info); | |
10788 | else | |
10789 | mips_set_tune (tune_info); | |
e9670677 | 10790 | |
316f5878 | 10791 | if (file_mips_gp32 >= 0) |
e9670677 | 10792 | { |
316f5878 RS |
10793 | /* The user specified the size of the integer registers. Make sure |
10794 | it agrees with the ABI and ISA. */ | |
10795 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10796 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10797 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10798 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10799 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10800 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10801 | } |
10802 | else | |
10803 | { | |
316f5878 RS |
10804 | /* Infer the integer register size from the ABI and processor. |
10805 | Restrict ourselves to 32-bit registers if that's all the | |
10806 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10807 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10808 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10809 | } |
10810 | ||
316f5878 RS |
10811 | /* ??? GAS treats single-float processors as though they had 64-bit |
10812 | float registers (although it complains when double-precision | |
10813 | instructions are used). As things stand, saying they have 32-bit | |
10814 | registers would lead to spurious "register must be even" messages. | |
10815 | So here we assume float registers are always the same size as | |
10816 | integer ones, unless the user says otherwise. */ | |
10817 | if (file_mips_fp32 < 0) | |
10818 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10819 | |
316f5878 | 10820 | /* End of GCC-shared inference code. */ |
e9670677 | 10821 | |
17a2f251 TS |
10822 | /* This flag is set when we have a 64-bit capable CPU but use only |
10823 | 32-bit wide registers. Note that EABI does not use it. */ | |
10824 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10825 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10826 | || mips_abi == O32_ABI)) | |
316f5878 | 10827 | mips_32bitmode = 1; |
e9670677 MR |
10828 | |
10829 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10830 | as_bad (_("trap exception not supported at ISA 1")); | |
10831 | ||
e9670677 MR |
10832 | /* If the selected architecture includes support for ASEs, enable |
10833 | generation of code for them. */ | |
a4672219 | 10834 | if (mips_opts.mips16 == -1) |
fef14a42 | 10835 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10836 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10837 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10838 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10839 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10840 | |
e9670677 | 10841 | file_mips_isa = mips_opts.isa; |
a4672219 | 10842 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10843 | file_ase_mips3d = mips_opts.ase_mips3d; |
10844 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10845 | mips_opts.gp32 = file_mips_gp32; | |
10846 | mips_opts.fp32 = file_mips_fp32; | |
10847 | ||
ecb4347a DJ |
10848 | if (mips_flag_mdebug < 0) |
10849 | { | |
10850 | #ifdef OBJ_MAYBE_ECOFF | |
10851 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10852 | mips_flag_mdebug = 1; | |
10853 | else | |
10854 | #endif /* OBJ_MAYBE_ECOFF */ | |
10855 | mips_flag_mdebug = 0; | |
10856 | } | |
e9670677 MR |
10857 | } |
10858 | \f | |
10859 | void | |
17a2f251 | 10860 | mips_init_after_args (void) |
252b5132 RH |
10861 | { |
10862 | /* initialize opcodes */ | |
10863 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10864 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10865 | } |
10866 | ||
10867 | long | |
17a2f251 | 10868 | md_pcrel_from (fixS *fixP) |
252b5132 | 10869 | { |
a7ebbfdf TS |
10870 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10871 | switch (fixP->fx_r_type) | |
10872 | { | |
10873 | case BFD_RELOC_16_PCREL_S2: | |
10874 | case BFD_RELOC_MIPS_JMP: | |
10875 | /* Return the address of the delay slot. */ | |
10876 | return addr + 4; | |
10877 | default: | |
10878 | return addr; | |
10879 | } | |
252b5132 RH |
10880 | } |
10881 | ||
252b5132 RH |
10882 | /* This is called before the symbol table is processed. In order to |
10883 | work with gcc when using mips-tfile, we must keep all local labels. | |
10884 | However, in other cases, we want to discard them. If we were | |
10885 | called with -g, but we didn't see any debugging information, it may | |
10886 | mean that gcc is smuggling debugging information through to | |
10887 | mips-tfile, in which case we must generate all local labels. */ | |
10888 | ||
10889 | void | |
17a2f251 | 10890 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10891 | { |
10892 | #ifndef NO_ECOFF_DEBUGGING | |
10893 | if (ECOFF_DEBUGGING | |
10894 | && mips_debug != 0 | |
10895 | && ! ecoff_debugging_seen) | |
10896 | flag_keep_locals = 1; | |
10897 | #endif | |
10898 | } | |
10899 | ||
10900 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10901 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10902 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10903 | explicit use of the %hi modifier. */ | |
10904 | ||
10905 | void | |
17a2f251 | 10906 | mips_frob_file (void) |
252b5132 RH |
10907 | { |
10908 | struct mips_hi_fixup *l; | |
10909 | ||
10910 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10911 | { | |
10912 | segment_info_type *seginfo; | |
10913 | int pass; | |
10914 | ||
5919d012 | 10915 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10916 | |
5919d012 RS |
10917 | /* If a GOT16 relocation turns out to be against a global symbol, |
10918 | there isn't supposed to be a matching LO. */ | |
10919 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10920 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10921 | continue; | |
10922 | ||
10923 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10924 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10925 | continue; |
10926 | ||
10927 | /* Look through the fixups for this segment for a matching %lo. | |
10928 | When we find one, move the %hi just in front of it. We do | |
10929 | this in two passes. In the first pass, we try to find a | |
10930 | unique %lo. In the second pass, we permit multiple %hi | |
10931 | relocs for a single %lo (this is a GNU extension). */ | |
10932 | seginfo = seg_info (l->seg); | |
10933 | for (pass = 0; pass < 2; pass++) | |
10934 | { | |
10935 | fixS *f, *prev; | |
10936 | ||
10937 | prev = NULL; | |
10938 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10939 | { | |
10940 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10941 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10942 | && f->fx_addsy == l->fixp->fx_addsy | |
10943 | && f->fx_offset == l->fixp->fx_offset | |
10944 | && (pass == 1 | |
10945 | || prev == NULL | |
5919d012 RS |
10946 | || !reloc_needs_lo_p (prev->fx_r_type) |
10947 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10948 | { |
10949 | fixS **pf; | |
10950 | ||
10951 | /* Move l->fixp before f. */ | |
10952 | for (pf = &seginfo->fix_root; | |
10953 | *pf != l->fixp; | |
10954 | pf = &(*pf)->fx_next) | |
10955 | assert (*pf != NULL); | |
10956 | ||
10957 | *pf = l->fixp->fx_next; | |
10958 | ||
10959 | l->fixp->fx_next = f; | |
10960 | if (prev == NULL) | |
10961 | seginfo->fix_root = l->fixp; | |
10962 | else | |
10963 | prev->fx_next = l->fixp; | |
10964 | ||
10965 | break; | |
10966 | } | |
10967 | ||
10968 | prev = f; | |
10969 | } | |
10970 | ||
10971 | if (f != NULL) | |
10972 | break; | |
10973 | ||
10974 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10975 | can leave a %hi without a %lo. */ | |
10976 | if (pass == 1) | |
10977 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10978 | _("Unmatched %%hi reloc")); | |
10979 | #endif | |
10980 | } | |
10981 | } | |
10982 | } | |
10983 | ||
10984 | /* When generating embedded PIC code we need to use a special | |
10985 | relocation to represent the difference of two symbols in the .text | |
10986 | section (switch tables use a difference of this sort). See | |
10987 | include/coff/mips.h for details. This macro checks whether this | |
10988 | fixup requires the special reloc. */ | |
10989 | #define SWITCH_TABLE(fixp) \ | |
10990 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10991 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10992 | && (fixp)->fx_addsy != NULL \ |
10993 | && (fixp)->fx_subsy != NULL \ | |
10994 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10995 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10996 | ||
10997 | /* When generating embedded PIC code we must keep all PC relative | |
10998 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10999 | to keep relocations for switch table entries. |
11000 | ||
11001 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11002 | We have to prevent gas from dropping them. */ | |
252b5132 | 11003 | |
252b5132 | 11004 | int |
17a2f251 | 11005 | mips_force_relocation (fixS *fixp) |
252b5132 | 11006 | { |
ae6063d4 | 11007 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11008 | return 1; |
11009 | ||
f6688943 TS |
11010 | if (HAVE_NEWABI |
11011 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11012 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11013 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11014 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11015 | return 1; | |
11016 | ||
252b5132 RH |
11017 | return (mips_pic == EMBEDDED_PIC |
11018 | && (fixp->fx_pcrel | |
11019 | || SWITCH_TABLE (fixp) | |
11020 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11021 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11022 | } | |
11023 | ||
45f8dfe8 AO |
11024 | /* This hook is called before a fix is simplified. We don't really |
11025 | decide whether to skip a fix here. Rather, we turn global symbols | |
11026 | used as branch targets into local symbols, such that they undergo | |
11027 | simplification. We can only do this if the symbol is defined and | |
11028 | it is in the same section as the branch. If this doesn't hold, we | |
11029 | emit a better error message than just saying the relocation is not | |
11030 | valid for the selected object format. | |
11031 | ||
11032 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11033 | segment in which the fix up occurs. The return value should be | |
11034 | non-zero to indicate the fix-up is valid for further | |
11035 | simplifications. */ | |
11036 | ||
11037 | int | |
17a2f251 | 11038 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11039 | { |
11040 | /* There's a lot of discussion on whether it should be possible to | |
11041 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11042 | seems to be that it can, but gas/bfd are very broken in creating | |
11043 | RELA relocations for this, so for now we only accept branches to | |
11044 | symbols in the same section. Anything else is of dubious value, | |
11045 | since there's no guarantee that at link time the symbol would be | |
11046 | in range. Even for branches to local symbols this is arguably | |
11047 | wrong, since it we assume the symbol is not going to be | |
11048 | overridden, which should be possible per ELF library semantics, | |
11049 | but then, there isn't a dynamic relocation that could be used to | |
11050 | this effect, and the target would likely be out of range as well. | |
11051 | ||
11052 | Unfortunately, it seems that there is too much code out there | |
11053 | that relies on branches to symbols that are global to be resolved | |
11054 | as if they were local, like the IRIX tools do, so we do it as | |
11055 | well, but with a warning so that people are reminded to fix their | |
11056 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11057 | targets, this entire block should go away (and probably the | |
11058 | whole function). */ | |
11059 | ||
11060 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11061 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11062 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11063 | && mips_pic != EMBEDDED_PIC) | |
11064 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11065 | && fixP->fx_addsy) | |
11066 | { | |
11067 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11068 | { | |
11069 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11070 | _("Cannot branch to undefined symbol.")); | |
11071 | /* Avoid any further errors about this fixup. */ | |
11072 | fixP->fx_done = 1; | |
11073 | } | |
11074 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11075 | { | |
11076 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11077 | _("Cannot branch to symbol in another section.")); | |
11078 | fixP->fx_done = 1; | |
11079 | } | |
11080 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11081 | { | |
11082 | symbolS *sym = fixP->fx_addsy; | |
11083 | ||
115695a8 CD |
11084 | if (mips_pic == SVR4_PIC) |
11085 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11086 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11087 | |
11088 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11089 | S_GET_SEGMENT (sym), | |
11090 | S_GET_VALUE (sym), | |
11091 | symbol_get_frag (sym)); | |
11092 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11093 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11094 | assert (symbol_resolved_p (sym)); | |
11095 | symbol_mark_resolved (fixP->fx_addsy); | |
11096 | } | |
11097 | } | |
11098 | ||
11099 | return 1; | |
11100 | } | |
11101 | ||
add55e1f RS |
11102 | #ifdef OBJ_ELF |
11103 | static int | |
17a2f251 | 11104 | mips_need_elf_addend_fixup (fixS *fixP) |
add55e1f | 11105 | { |
2d2bf3e0 CD |
11106 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11107 | return 1; | |
b25a253c CD |
11108 | if (mips_pic == EMBEDDED_PIC |
11109 | && S_IS_WEAK (fixP->fx_addsy)) | |
11110 | return 1; | |
11111 | if (mips_pic != EMBEDDED_PIC | |
11112 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11113 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11114 | && !S_IS_COMMON (fixP->fx_addsy)) |
11115 | return 1; | |
9204e615 DJ |
11116 | if (((bfd_get_section_flags (stdoutput, |
11117 | S_GET_SEGMENT (fixP->fx_addsy)) | |
11118 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) | |
11119 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
11120 | ".gnu.linkonce", | |
11121 | sizeof (".gnu.linkonce") - 1)) | |
2d2bf3e0 CD |
11122 | return 1; |
11123 | return 0; | |
add55e1f RS |
11124 | } |
11125 | #endif | |
11126 | ||
252b5132 RH |
11127 | /* Apply a fixup to the object file. */ |
11128 | ||
94f592af | 11129 | void |
17a2f251 | 11130 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11131 | { |
874e8986 | 11132 | bfd_byte *buf; |
98aa84af | 11133 | long insn; |
ed6fb7bd | 11134 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11135 | reloc_howto_type *howto; |
252b5132 | 11136 | |
a7ebbfdf TS |
11137 | /* We ignore generic BFD relocations we don't know about. */ |
11138 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11139 | if (! howto) | |
11140 | return; | |
65551fa4 | 11141 | |
252b5132 RH |
11142 | assert (fixP->fx_size == 4 |
11143 | || fixP->fx_r_type == BFD_RELOC_16 | |
11144 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11145 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11146 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11147 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11148 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11149 | |
a7ebbfdf | 11150 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 RH |
11151 | |
11152 | /* If we aren't adjusting this fixup to be against the section | |
11153 | symbol, we need to adjust the value. */ | |
11154 | #ifdef OBJ_ELF | |
11155 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11156 | { |
a7ebbfdf TS |
11157 | if (mips_need_elf_addend_fixup (fixP) |
11158 | && howto->partial_inplace | |
11159 | && fixP->fx_r_type != BFD_RELOC_GPREL16 | |
11160 | && fixP->fx_r_type != BFD_RELOC_GPREL32 | |
11161 | && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL) | |
11162 | { | |
11163 | /* In this case, the bfd_install_relocation routine will | |
11164 | incorrectly add the symbol value back in. We just want | |
11165 | the addend to appear in the object file. | |
11166 | ||
11167 | The condition above used to include | |
11168 | "&& (! fixP->fx_pcrel || howto->pcrel_offset)". | |
11169 | ||
11170 | However, howto can't be trusted here, because we | |
11171 | might change the reloc type in tc_gen_reloc. We can | |
11172 | check howto->partial_inplace because that conversion | |
11173 | happens to preserve howto->partial_inplace; but it | |
11174 | does not preserve howto->pcrel_offset. I've just | |
11175 | eliminated the check, because all MIPS PC-relative | |
11176 | relocations are marked howto->pcrel_offset. | |
11177 | ||
11178 | howto->pcrel_offset was originally added for | |
11179 | R_MIPS_PC16, which is generated for code like | |
11180 | ||
11181 | globl g1 .text | |
11182 | .text | |
11183 | .space 20 | |
11184 | g1: | |
11185 | x: | |
11186 | bal g1 | |
11187 | */ | |
11188 | *valP -= S_GET_VALUE (fixP->fx_addsy); | |
98aa84af | 11189 | } |
252b5132 | 11190 | |
bb2d6cd7 GK |
11191 | /* This code was generated using trial and error and so is |
11192 | fragile and not trustworthy. If you change it, you should | |
11193 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11194 | they still pass. */ | |
a7ebbfdf | 11195 | if (fixP->fx_pcrel) |
bb2d6cd7 | 11196 | { |
a7ebbfdf | 11197 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11198 | |
11199 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11200 | This gives the right results, but it can't possibly | |
11201 | be the way things are supposed to work. */ | |
a7ebbfdf | 11202 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11203 | } |
11204 | } | |
11205 | #endif | |
252b5132 | 11206 | |
ed6fb7bd SC |
11207 | /* We are not done if this is a composite relocation to set up gp. */ |
11208 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11209 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11210 | || (fixP->fx_r_type == BFD_RELOC_64 |
11211 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11212 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11213 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11214 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11215 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11216 | fixP->fx_done = 1; |
ed6fb7bd | 11217 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11218 | |
11219 | switch (fixP->fx_r_type) | |
11220 | { | |
11221 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11222 | case BFD_RELOC_MIPS_SHIFT5: |
11223 | case BFD_RELOC_MIPS_SHIFT6: | |
11224 | case BFD_RELOC_MIPS_GOT_DISP: | |
11225 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11226 | case BFD_RELOC_MIPS_GOT_OFST: | |
11227 | case BFD_RELOC_MIPS_SUB: | |
11228 | case BFD_RELOC_MIPS_INSERT_A: | |
11229 | case BFD_RELOC_MIPS_INSERT_B: | |
11230 | case BFD_RELOC_MIPS_DELETE: | |
11231 | case BFD_RELOC_MIPS_HIGHEST: | |
11232 | case BFD_RELOC_MIPS_HIGHER: | |
11233 | case BFD_RELOC_MIPS_SCN_DISP: | |
11234 | case BFD_RELOC_MIPS_REL16: | |
11235 | case BFD_RELOC_MIPS_RELGOT: | |
11236 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11237 | case BFD_RELOC_HI16: |
11238 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11239 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11240 | case BFD_RELOC_MIPS_LITERAL: |
11241 | case BFD_RELOC_MIPS_CALL16: | |
11242 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11243 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11244 | case BFD_RELOC_MIPS_GOT_HI16: |
11245 | case BFD_RELOC_MIPS_GOT_LO16: | |
11246 | case BFD_RELOC_MIPS_CALL_HI16: | |
11247 | case BFD_RELOC_MIPS_CALL_LO16: | |
11248 | case BFD_RELOC_MIPS16_GPREL: | |
11249 | if (fixP->fx_pcrel) | |
11250 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11251 | _("Invalid PC relative reloc")); | |
11252 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11253 | break; | |
11254 | ||
11255 | case BFD_RELOC_MIPS16_JMP: | |
11256 | /* We currently always generate a reloc against a symbol, which | |
11257 | means that we don't want an addend even if the symbol is | |
11258 | defined. */ | |
a7ebbfdf | 11259 | *valP = 0; |
252b5132 RH |
11260 | break; |
11261 | ||
11262 | case BFD_RELOC_PCREL_HI16_S: | |
11263 | /* The addend for this is tricky if it is internal, so we just | |
11264 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11265 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11266 | break; |
11267 | if (fixP->fx_addsy | |
11268 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11269 | { |
11270 | /* For an external symbol adjust by the address to make it | |
11271 | pcrel_offset. We use the address of the RELLO reloc | |
11272 | which follows this one. */ | |
a7ebbfdf | 11273 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11274 | + fixP->fx_next->fx_where); |
11275 | } | |
a7ebbfdf | 11276 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11277 | if (target_big_endian) |
11278 | buf += 2; | |
17a2f251 | 11279 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11280 | break; |
11281 | ||
11282 | case BFD_RELOC_PCREL_LO16: | |
11283 | /* The addend for this is tricky if it is internal, so we just | |
11284 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11285 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11286 | break; |
11287 | if (fixP->fx_addsy | |
11288 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11289 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11290 | if (target_big_endian) |
11291 | buf += 2; | |
17a2f251 | 11292 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11293 | break; |
11294 | ||
11295 | case BFD_RELOC_64: | |
11296 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11297 | extended value if we are only 32 bits. */ | |
11298 | if (fixP->fx_done | |
11299 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11300 | { | |
11301 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11302 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11303 | else |
11304 | { | |
a7ebbfdf | 11305 | valueT hiv; |
252b5132 | 11306 | |
a7ebbfdf | 11307 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11308 | hiv = 0xffffffff; |
11309 | else | |
11310 | hiv = 0; | |
a7ebbfdf TS |
11311 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11312 | *valP, 4); | |
11313 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11314 | hiv, 4); | |
252b5132 RH |
11315 | } |
11316 | } | |
11317 | break; | |
11318 | ||
056350c6 | 11319 | case BFD_RELOC_RVA: |
252b5132 RH |
11320 | case BFD_RELOC_32: |
11321 | /* If we are deleting this reloc entry, we must fill in the | |
11322 | value now. This can happen if we have a .word which is not | |
11323 | resolved when it appears but is later defined. We also need | |
11324 | to fill in the value if this is an embedded PIC switch table | |
11325 | entry. */ | |
11326 | if (fixP->fx_done | |
11327 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11328 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11329 | break; |
11330 | ||
11331 | case BFD_RELOC_16: | |
11332 | /* If we are deleting this reloc entry, we must fill in the | |
11333 | value now. */ | |
11334 | assert (fixP->fx_size == 2); | |
11335 | if (fixP->fx_done) | |
a7ebbfdf | 11336 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11337 | break; |
11338 | ||
11339 | case BFD_RELOC_LO16: | |
11340 | /* When handling an embedded PIC switch statement, we can wind | |
11341 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11342 | if (fixP->fx_done) | |
11343 | { | |
a7ebbfdf | 11344 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11345 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11346 | _("relocation overflow")); | |
252b5132 RH |
11347 | if (target_big_endian) |
11348 | buf += 2; | |
17a2f251 | 11349 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11350 | } |
11351 | break; | |
11352 | ||
11353 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11354 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11355 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11356 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11357 | |
252b5132 RH |
11358 | /* |
11359 | * We need to save the bits in the instruction since fixup_segment() | |
11360 | * might be deleting the relocation entry (i.e., a branch within | |
11361 | * the current segment). | |
11362 | */ | |
a7ebbfdf | 11363 | if (! fixP->fx_done) |
bb2d6cd7 | 11364 | break; |
252b5132 RH |
11365 | |
11366 | /* update old instruction data */ | |
252b5132 RH |
11367 | if (target_big_endian) |
11368 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11369 | else | |
11370 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11371 | ||
a7ebbfdf TS |
11372 | if (*valP + 0x20000 <= 0x3ffff) |
11373 | { | |
11374 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11375 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11376 | } |
11377 | else if (mips_pic == NO_PIC | |
11378 | && fixP->fx_done | |
11379 | && fixP->fx_frag->fr_address >= text_section->vma | |
11380 | && (fixP->fx_frag->fr_address | |
11381 | < text_section->vma + text_section->_raw_size) | |
11382 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11383 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11384 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11385 | { |
11386 | /* The branch offset is too large. If this is an | |
11387 | unconditional branch, and we are not generating PIC code, | |
11388 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11389 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11390 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11391 | else |
a7ebbfdf TS |
11392 | insn = 0x08000000; /* j */ |
11393 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11394 | fixP->fx_done = 0; | |
11395 | fixP->fx_addsy = section_symbol (text_section); | |
11396 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11397 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11398 | } |
11399 | else | |
11400 | { | |
11401 | /* If we got here, we have branch-relaxation disabled, | |
11402 | and there's nothing we can do to fix this instruction | |
11403 | without turning it into a longer sequence. */ | |
11404 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11405 | _("Branch out of range")); | |
252b5132 | 11406 | } |
252b5132 RH |
11407 | break; |
11408 | ||
11409 | case BFD_RELOC_VTABLE_INHERIT: | |
11410 | fixP->fx_done = 0; | |
11411 | if (fixP->fx_addsy | |
11412 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11413 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11414 | S_SET_WEAK (fixP->fx_addsy); | |
11415 | break; | |
11416 | ||
11417 | case BFD_RELOC_VTABLE_ENTRY: | |
11418 | fixP->fx_done = 0; | |
11419 | break; | |
11420 | ||
11421 | default: | |
11422 | internalError (); | |
11423 | } | |
a7ebbfdf TS |
11424 | |
11425 | /* Remember value for tc_gen_reloc. */ | |
11426 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11427 | } |
11428 | ||
11429 | #if 0 | |
11430 | void | |
17a2f251 | 11431 | printInsn (unsigned long oc) |
252b5132 RH |
11432 | { |
11433 | const struct mips_opcode *p; | |
11434 | int treg, sreg, dreg, shamt; | |
11435 | short imm; | |
11436 | const char *args; | |
11437 | int i; | |
11438 | ||
11439 | for (i = 0; i < NUMOPCODES; ++i) | |
11440 | { | |
11441 | p = &mips_opcodes[i]; | |
11442 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11443 | { | |
11444 | printf ("%08lx %s\t", oc, p->name); | |
11445 | treg = (oc >> 16) & 0x1f; | |
11446 | sreg = (oc >> 21) & 0x1f; | |
11447 | dreg = (oc >> 11) & 0x1f; | |
11448 | shamt = (oc >> 6) & 0x1f; | |
11449 | imm = oc; | |
11450 | for (args = p->args;; ++args) | |
11451 | { | |
11452 | switch (*args) | |
11453 | { | |
11454 | case '\0': | |
11455 | printf ("\n"); | |
11456 | break; | |
11457 | ||
11458 | case ',': | |
11459 | case '(': | |
11460 | case ')': | |
11461 | printf ("%c", *args); | |
11462 | continue; | |
11463 | ||
11464 | case 'r': | |
11465 | assert (treg == sreg); | |
11466 | printf ("$%d,$%d", treg, sreg); | |
11467 | continue; | |
11468 | ||
11469 | case 'd': | |
11470 | case 'G': | |
11471 | printf ("$%d", dreg); | |
11472 | continue; | |
11473 | ||
11474 | case 't': | |
11475 | case 'E': | |
11476 | printf ("$%d", treg); | |
11477 | continue; | |
11478 | ||
11479 | case 'k': | |
11480 | printf ("0x%x", treg); | |
11481 | continue; | |
11482 | ||
11483 | case 'b': | |
11484 | case 's': | |
11485 | printf ("$%d", sreg); | |
11486 | continue; | |
11487 | ||
11488 | case 'a': | |
11489 | printf ("0x%08lx", oc & 0x1ffffff); | |
11490 | continue; | |
11491 | ||
11492 | case 'i': | |
11493 | case 'j': | |
11494 | case 'o': | |
11495 | case 'u': | |
11496 | printf ("%d", imm); | |
11497 | continue; | |
11498 | ||
11499 | case '<': | |
11500 | case '>': | |
11501 | printf ("$%d", shamt); | |
11502 | continue; | |
11503 | ||
11504 | default: | |
11505 | internalError (); | |
11506 | } | |
11507 | break; | |
11508 | } | |
11509 | return; | |
11510 | } | |
11511 | } | |
11512 | printf (_("%08lx UNDEFINED\n"), oc); | |
11513 | } | |
11514 | #endif | |
11515 | ||
11516 | static symbolS * | |
17a2f251 | 11517 | get_symbol (void) |
252b5132 RH |
11518 | { |
11519 | int c; | |
11520 | char *name; | |
11521 | symbolS *p; | |
11522 | ||
11523 | name = input_line_pointer; | |
11524 | c = get_symbol_end (); | |
11525 | p = (symbolS *) symbol_find_or_make (name); | |
11526 | *input_line_pointer = c; | |
11527 | return p; | |
11528 | } | |
11529 | ||
11530 | /* Align the current frag to a given power of two. The MIPS assembler | |
11531 | also automatically adjusts any preceding label. */ | |
11532 | ||
11533 | static void | |
17a2f251 | 11534 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11535 | { |
b34976b6 | 11536 | mips_emit_delays (FALSE); |
252b5132 RH |
11537 | frag_align (to, fill, 0); |
11538 | record_alignment (now_seg, to); | |
11539 | if (label != NULL) | |
11540 | { | |
11541 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11542 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11543 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11544 | } | |
11545 | } | |
11546 | ||
11547 | /* Align to a given power of two. .align 0 turns off the automatic | |
11548 | alignment used by the data creating pseudo-ops. */ | |
11549 | ||
11550 | static void | |
17a2f251 | 11551 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11552 | { |
11553 | register int temp; | |
11554 | register long temp_fill; | |
11555 | long max_alignment = 15; | |
11556 | ||
11557 | /* | |
11558 | ||
11559 | o Note that the assembler pulls down any immediately preceeding label | |
11560 | to the aligned address. | |
11561 | o It's not documented but auto alignment is reinstated by | |
11562 | a .align pseudo instruction. | |
11563 | o Note also that after auto alignment is turned off the mips assembler | |
11564 | issues an error on attempt to assemble an improperly aligned data item. | |
11565 | We don't. | |
11566 | ||
11567 | */ | |
11568 | ||
11569 | temp = get_absolute_expression (); | |
11570 | if (temp > max_alignment) | |
11571 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11572 | else if (temp < 0) | |
11573 | { | |
11574 | as_warn (_("Alignment negative: 0 assumed.")); | |
11575 | temp = 0; | |
11576 | } | |
11577 | if (*input_line_pointer == ',') | |
11578 | { | |
f9419b05 | 11579 | ++input_line_pointer; |
252b5132 RH |
11580 | temp_fill = get_absolute_expression (); |
11581 | } | |
11582 | else | |
11583 | temp_fill = 0; | |
11584 | if (temp) | |
11585 | { | |
11586 | auto_align = 1; | |
11587 | mips_align (temp, (int) temp_fill, | |
11588 | insn_labels != NULL ? insn_labels->label : NULL); | |
11589 | } | |
11590 | else | |
11591 | { | |
11592 | auto_align = 0; | |
11593 | } | |
11594 | ||
11595 | demand_empty_rest_of_line (); | |
11596 | } | |
11597 | ||
11598 | void | |
17a2f251 | 11599 | mips_flush_pending_output (void) |
252b5132 | 11600 | { |
b34976b6 | 11601 | mips_emit_delays (FALSE); |
252b5132 RH |
11602 | mips_clear_insn_labels (); |
11603 | } | |
11604 | ||
11605 | static void | |
17a2f251 | 11606 | s_change_sec (int sec) |
252b5132 RH |
11607 | { |
11608 | segT seg; | |
11609 | ||
11610 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11611 | .sdata and .sbss sections. We change the .data and .rdata | |
11612 | pseudo-ops to use .sdata. */ | |
11613 | if (mips_pic == EMBEDDED_PIC | |
11614 | && (sec == 'd' || sec == 'r')) | |
11615 | sec = 's'; | |
11616 | ||
11617 | #ifdef OBJ_ELF | |
11618 | /* The ELF backend needs to know that we are changing sections, so | |
11619 | that .previous works correctly. We could do something like check | |
b6ff326e | 11620 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11621 | as it would not be appropriate to use it in the section changing |
11622 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11623 | This should be cleaner, somehow. */ | |
11624 | obj_elf_section_change_hook (); | |
11625 | #endif | |
11626 | ||
b34976b6 | 11627 | mips_emit_delays (FALSE); |
252b5132 RH |
11628 | switch (sec) |
11629 | { | |
11630 | case 't': | |
11631 | s_text (0); | |
11632 | break; | |
11633 | case 'd': | |
11634 | s_data (0); | |
11635 | break; | |
11636 | case 'b': | |
11637 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11638 | demand_empty_rest_of_line (); | |
11639 | break; | |
11640 | ||
11641 | case 'r': | |
11642 | if (USE_GLOBAL_POINTER_OPT) | |
11643 | { | |
11644 | seg = subseg_new (RDATA_SECTION_NAME, | |
11645 | (subsegT) get_absolute_expression ()); | |
11646 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11647 | { | |
11648 | bfd_set_section_flags (stdoutput, seg, | |
11649 | (SEC_ALLOC | |
11650 | | SEC_LOAD | |
11651 | | SEC_READONLY | |
11652 | | SEC_RELOC | |
11653 | | SEC_DATA)); | |
11654 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11655 | record_alignment (seg, 4); |
252b5132 RH |
11656 | } |
11657 | demand_empty_rest_of_line (); | |
11658 | } | |
11659 | else | |
11660 | { | |
11661 | as_bad (_("No read only data section in this object file format")); | |
11662 | demand_empty_rest_of_line (); | |
11663 | return; | |
11664 | } | |
11665 | break; | |
11666 | ||
11667 | case 's': | |
11668 | if (USE_GLOBAL_POINTER_OPT) | |
11669 | { | |
11670 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11671 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11672 | { | |
11673 | bfd_set_section_flags (stdoutput, seg, | |
11674 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11675 | | SEC_DATA); | |
11676 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11677 | record_alignment (seg, 4); |
252b5132 RH |
11678 | } |
11679 | demand_empty_rest_of_line (); | |
11680 | break; | |
11681 | } | |
11682 | else | |
11683 | { | |
11684 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11685 | demand_empty_rest_of_line (); | |
11686 | return; | |
11687 | } | |
11688 | } | |
11689 | ||
11690 | auto_align = 1; | |
11691 | } | |
b34976b6 | 11692 | |
cca86cc8 | 11693 | void |
17a2f251 | 11694 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11695 | { |
7ed4a06a | 11696 | #ifdef OBJ_ELF |
cca86cc8 SC |
11697 | char *section_name; |
11698 | char c; | |
684022ea | 11699 | char next_c = 0; |
cca86cc8 SC |
11700 | int section_type; |
11701 | int section_flag; | |
11702 | int section_entry_size; | |
11703 | int section_alignment; | |
b34976b6 | 11704 | |
7ed4a06a TS |
11705 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11706 | return; | |
11707 | ||
cca86cc8 SC |
11708 | section_name = input_line_pointer; |
11709 | c = get_symbol_end (); | |
a816d1ed AO |
11710 | if (c) |
11711 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11712 | |
4cf0dd0d TS |
11713 | /* Do we have .section Name<,"flags">? */ |
11714 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11715 | { |
4cf0dd0d TS |
11716 | /* just after name is now '\0'. */ |
11717 | *input_line_pointer = c; | |
cca86cc8 SC |
11718 | input_line_pointer = section_name; |
11719 | obj_elf_section (ignore); | |
11720 | return; | |
11721 | } | |
11722 | input_line_pointer++; | |
11723 | ||
11724 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11725 | if (c == ',') | |
11726 | section_type = get_absolute_expression (); | |
11727 | else | |
11728 | section_type = 0; | |
11729 | if (*input_line_pointer++ == ',') | |
11730 | section_flag = get_absolute_expression (); | |
11731 | else | |
11732 | section_flag = 0; | |
11733 | if (*input_line_pointer++ == ',') | |
11734 | section_entry_size = get_absolute_expression (); | |
11735 | else | |
11736 | section_entry_size = 0; | |
11737 | if (*input_line_pointer++ == ',') | |
11738 | section_alignment = get_absolute_expression (); | |
11739 | else | |
11740 | section_alignment = 0; | |
11741 | ||
a816d1ed AO |
11742 | section_name = xstrdup (section_name); |
11743 | ||
cca86cc8 SC |
11744 | obj_elf_change_section (section_name, section_type, section_flag, |
11745 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11746 | |
11747 | if (now_seg->name != section_name) | |
11748 | free (section_name); | |
7ed4a06a | 11749 | #endif /* OBJ_ELF */ |
cca86cc8 | 11750 | } |
252b5132 RH |
11751 | |
11752 | void | |
17a2f251 | 11753 | mips_enable_auto_align (void) |
252b5132 RH |
11754 | { |
11755 | auto_align = 1; | |
11756 | } | |
11757 | ||
11758 | static void | |
17a2f251 | 11759 | s_cons (int log_size) |
252b5132 RH |
11760 | { |
11761 | symbolS *label; | |
11762 | ||
11763 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11764 | mips_emit_delays (FALSE); |
252b5132 RH |
11765 | if (log_size > 0 && auto_align) |
11766 | mips_align (log_size, 0, label); | |
11767 | mips_clear_insn_labels (); | |
11768 | cons (1 << log_size); | |
11769 | } | |
11770 | ||
11771 | static void | |
17a2f251 | 11772 | s_float_cons (int type) |
252b5132 RH |
11773 | { |
11774 | symbolS *label; | |
11775 | ||
11776 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11777 | ||
b34976b6 | 11778 | mips_emit_delays (FALSE); |
252b5132 RH |
11779 | |
11780 | if (auto_align) | |
49309057 ILT |
11781 | { |
11782 | if (type == 'd') | |
11783 | mips_align (3, 0, label); | |
11784 | else | |
11785 | mips_align (2, 0, label); | |
11786 | } | |
252b5132 RH |
11787 | |
11788 | mips_clear_insn_labels (); | |
11789 | ||
11790 | float_cons (type); | |
11791 | } | |
11792 | ||
11793 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11794 | permitted to say | |
11795 | .globl foo .text | |
11796 | where foo is an undefined symbol, to mean that foo should be | |
11797 | considered to be the address of a function. */ | |
11798 | ||
11799 | static void | |
17a2f251 | 11800 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11801 | { |
11802 | char *name; | |
11803 | int c; | |
11804 | symbolS *symbolP; | |
11805 | flagword flag; | |
11806 | ||
11807 | name = input_line_pointer; | |
11808 | c = get_symbol_end (); | |
11809 | symbolP = symbol_find_or_make (name); | |
11810 | *input_line_pointer = c; | |
11811 | SKIP_WHITESPACE (); | |
11812 | ||
11813 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11814 | being a function is apparently labelled as being an object. */ | |
11815 | flag = BSF_OBJECT; | |
11816 | ||
11817 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11818 | { | |
11819 | char *secname; | |
11820 | asection *sec; | |
11821 | ||
11822 | secname = input_line_pointer; | |
11823 | c = get_symbol_end (); | |
11824 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11825 | if (sec == NULL) | |
11826 | as_bad (_("%s: no such section"), secname); | |
11827 | *input_line_pointer = c; | |
11828 | ||
11829 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11830 | flag = BSF_FUNCTION; | |
11831 | } | |
11832 | ||
49309057 | 11833 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11834 | |
11835 | S_SET_EXTERNAL (symbolP); | |
11836 | demand_empty_rest_of_line (); | |
11837 | } | |
11838 | ||
11839 | static void | |
17a2f251 | 11840 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11841 | { |
11842 | char *opt; | |
11843 | char c; | |
11844 | ||
11845 | opt = input_line_pointer; | |
11846 | c = get_symbol_end (); | |
11847 | ||
11848 | if (*opt == 'O') | |
11849 | { | |
11850 | /* FIXME: What does this mean? */ | |
11851 | } | |
11852 | else if (strncmp (opt, "pic", 3) == 0) | |
11853 | { | |
11854 | int i; | |
11855 | ||
11856 | i = atoi (opt + 3); | |
11857 | if (i == 0) | |
11858 | mips_pic = NO_PIC; | |
11859 | else if (i == 2) | |
143d77c5 | 11860 | { |
252b5132 | 11861 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11862 | mips_abicalls = TRUE; |
11863 | } | |
252b5132 RH |
11864 | else |
11865 | as_bad (_(".option pic%d not supported"), i); | |
11866 | ||
11867 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11868 | { | |
11869 | if (g_switch_seen && g_switch_value != 0) | |
11870 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11871 | g_switch_value = 0; | |
11872 | bfd_set_gp_size (stdoutput, 0); | |
11873 | } | |
11874 | } | |
11875 | else | |
11876 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11877 | ||
11878 | *input_line_pointer = c; | |
11879 | demand_empty_rest_of_line (); | |
11880 | } | |
11881 | ||
11882 | /* This structure is used to hold a stack of .set values. */ | |
11883 | ||
e972090a NC |
11884 | struct mips_option_stack |
11885 | { | |
252b5132 RH |
11886 | struct mips_option_stack *next; |
11887 | struct mips_set_options options; | |
11888 | }; | |
11889 | ||
11890 | static struct mips_option_stack *mips_opts_stack; | |
11891 | ||
11892 | /* Handle the .set pseudo-op. */ | |
11893 | ||
11894 | static void | |
17a2f251 | 11895 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11896 | { |
11897 | char *name = input_line_pointer, ch; | |
11898 | ||
11899 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11900 | ++input_line_pointer; |
252b5132 RH |
11901 | ch = *input_line_pointer; |
11902 | *input_line_pointer = '\0'; | |
11903 | ||
11904 | if (strcmp (name, "reorder") == 0) | |
11905 | { | |
11906 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11907 | { | |
11908 | /* If we still have pending nops, we can discard them. The | |
11909 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11910 | needed. */ |
252b5132 RH |
11911 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11912 | * (mips_opts.mips16 ? 2 : 4)); | |
11913 | prev_nop_frag = NULL; | |
11914 | } | |
11915 | mips_opts.noreorder = 0; | |
11916 | } | |
11917 | else if (strcmp (name, "noreorder") == 0) | |
11918 | { | |
b34976b6 | 11919 | mips_emit_delays (TRUE); |
252b5132 RH |
11920 | mips_opts.noreorder = 1; |
11921 | mips_any_noreorder = 1; | |
11922 | } | |
11923 | else if (strcmp (name, "at") == 0) | |
11924 | { | |
11925 | mips_opts.noat = 0; | |
11926 | } | |
11927 | else if (strcmp (name, "noat") == 0) | |
11928 | { | |
11929 | mips_opts.noat = 1; | |
11930 | } | |
11931 | else if (strcmp (name, "macro") == 0) | |
11932 | { | |
11933 | mips_opts.warn_about_macros = 0; | |
11934 | } | |
11935 | else if (strcmp (name, "nomacro") == 0) | |
11936 | { | |
11937 | if (mips_opts.noreorder == 0) | |
11938 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11939 | mips_opts.warn_about_macros = 1; | |
11940 | } | |
11941 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11942 | { | |
11943 | mips_opts.nomove = 0; | |
11944 | } | |
11945 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11946 | { | |
11947 | mips_opts.nomove = 1; | |
11948 | } | |
11949 | else if (strcmp (name, "bopt") == 0) | |
11950 | { | |
11951 | mips_opts.nobopt = 0; | |
11952 | } | |
11953 | else if (strcmp (name, "nobopt") == 0) | |
11954 | { | |
11955 | mips_opts.nobopt = 1; | |
11956 | } | |
11957 | else if (strcmp (name, "mips16") == 0 | |
11958 | || strcmp (name, "MIPS-16") == 0) | |
11959 | mips_opts.mips16 = 1; | |
11960 | else if (strcmp (name, "nomips16") == 0 | |
11961 | || strcmp (name, "noMIPS-16") == 0) | |
11962 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11963 | else if (strcmp (name, "mips3d") == 0) |
11964 | mips_opts.ase_mips3d = 1; | |
11965 | else if (strcmp (name, "nomips3d") == 0) | |
11966 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11967 | else if (strcmp (name, "mdmx") == 0) |
11968 | mips_opts.ase_mdmx = 1; | |
11969 | else if (strcmp (name, "nomdmx") == 0) | |
11970 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11971 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11972 | { |
af7ee8bf | 11973 | int reset = 0; |
252b5132 | 11974 | |
1a2c1fad CD |
11975 | /* Permit the user to change the ISA and architecture on the fly. |
11976 | Needless to say, misuse can cause serious problems. */ | |
af7ee8bf CD |
11977 | if (strcmp (name, "mips0") == 0) |
11978 | { | |
11979 | reset = 1; | |
11980 | mips_opts.isa = file_mips_isa; | |
11981 | } | |
11982 | else if (strcmp (name, "mips1") == 0) | |
11983 | mips_opts.isa = ISA_MIPS1; | |
11984 | else if (strcmp (name, "mips2") == 0) | |
11985 | mips_opts.isa = ISA_MIPS2; | |
11986 | else if (strcmp (name, "mips3") == 0) | |
11987 | mips_opts.isa = ISA_MIPS3; | |
11988 | else if (strcmp (name, "mips4") == 0) | |
11989 | mips_opts.isa = ISA_MIPS4; | |
11990 | else if (strcmp (name, "mips5") == 0) | |
11991 | mips_opts.isa = ISA_MIPS5; | |
11992 | else if (strcmp (name, "mips32") == 0) | |
11993 | mips_opts.isa = ISA_MIPS32; | |
11994 | else if (strcmp (name, "mips32r2") == 0) | |
11995 | mips_opts.isa = ISA_MIPS32R2; | |
11996 | else if (strcmp (name, "mips64") == 0) | |
11997 | mips_opts.isa = ISA_MIPS64; | |
1a2c1fad CD |
11998 | else if (strcmp (name, "arch=default") == 0) |
11999 | { | |
12000 | reset = 1; | |
12001 | mips_opts.arch = file_mips_arch; | |
12002 | mips_opts.isa = file_mips_isa; | |
12003 | } | |
12004 | else if (strncmp (name, "arch=", 5) == 0) | |
12005 | { | |
12006 | const struct mips_cpu_info *p; | |
12007 | ||
12008 | p = mips_parse_cpu("internal use", name + 5); | |
12009 | if (!p) | |
12010 | as_bad (_("unknown architecture %s"), name + 5); | |
12011 | else | |
12012 | { | |
12013 | mips_opts.arch = p->cpu; | |
12014 | mips_opts.isa = p->isa; | |
12015 | } | |
12016 | } | |
af7ee8bf CD |
12017 | else |
12018 | as_bad (_("unknown ISA level %s"), name + 4); | |
12019 | ||
12020 | switch (mips_opts.isa) | |
98d3f06f KH |
12021 | { |
12022 | case 0: | |
98d3f06f | 12023 | break; |
af7ee8bf CD |
12024 | case ISA_MIPS1: |
12025 | case ISA_MIPS2: | |
12026 | case ISA_MIPS32: | |
12027 | case ISA_MIPS32R2: | |
98d3f06f KH |
12028 | mips_opts.gp32 = 1; |
12029 | mips_opts.fp32 = 1; | |
12030 | break; | |
af7ee8bf CD |
12031 | case ISA_MIPS3: |
12032 | case ISA_MIPS4: | |
12033 | case ISA_MIPS5: | |
12034 | case ISA_MIPS64: | |
98d3f06f KH |
12035 | mips_opts.gp32 = 0; |
12036 | mips_opts.fp32 = 0; | |
12037 | break; | |
12038 | default: | |
12039 | as_bad (_("unknown ISA level %s"), name + 4); | |
12040 | break; | |
12041 | } | |
af7ee8bf | 12042 | if (reset) |
98d3f06f | 12043 | { |
af7ee8bf CD |
12044 | mips_opts.gp32 = file_mips_gp32; |
12045 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12046 | } |
252b5132 RH |
12047 | } |
12048 | else if (strcmp (name, "autoextend") == 0) | |
12049 | mips_opts.noautoextend = 0; | |
12050 | else if (strcmp (name, "noautoextend") == 0) | |
12051 | mips_opts.noautoextend = 1; | |
12052 | else if (strcmp (name, "push") == 0) | |
12053 | { | |
12054 | struct mips_option_stack *s; | |
12055 | ||
12056 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12057 | s->next = mips_opts_stack; | |
12058 | s->options = mips_opts; | |
12059 | mips_opts_stack = s; | |
12060 | } | |
12061 | else if (strcmp (name, "pop") == 0) | |
12062 | { | |
12063 | struct mips_option_stack *s; | |
12064 | ||
12065 | s = mips_opts_stack; | |
12066 | if (s == NULL) | |
12067 | as_bad (_(".set pop with no .set push")); | |
12068 | else | |
12069 | { | |
12070 | /* If we're changing the reorder mode we need to handle | |
12071 | delay slots correctly. */ | |
12072 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12073 | mips_emit_delays (TRUE); |
252b5132 RH |
12074 | else if (! s->options.noreorder && mips_opts.noreorder) |
12075 | { | |
12076 | if (prev_nop_frag != NULL) | |
12077 | { | |
12078 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12079 | * (mips_opts.mips16 ? 2 : 4)); | |
12080 | prev_nop_frag = NULL; | |
12081 | } | |
12082 | } | |
12083 | ||
12084 | mips_opts = s->options; | |
12085 | mips_opts_stack = s->next; | |
12086 | free (s); | |
12087 | } | |
12088 | } | |
12089 | else | |
12090 | { | |
12091 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12092 | } | |
12093 | *input_line_pointer = ch; | |
12094 | demand_empty_rest_of_line (); | |
12095 | } | |
12096 | ||
12097 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12098 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12099 | ||
12100 | static void | |
17a2f251 | 12101 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12102 | { |
12103 | mips_pic = SVR4_PIC; | |
143d77c5 | 12104 | mips_abicalls = TRUE; |
252b5132 RH |
12105 | if (USE_GLOBAL_POINTER_OPT) |
12106 | { | |
12107 | if (g_switch_seen && g_switch_value != 0) | |
12108 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12109 | g_switch_value = 0; | |
12110 | } | |
12111 | bfd_set_gp_size (stdoutput, 0); | |
12112 | demand_empty_rest_of_line (); | |
12113 | } | |
12114 | ||
12115 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12116 | PIC code. It sets the $gp register for the function based on the | |
12117 | function address, which is in the register named in the argument. | |
12118 | This uses a relocation against _gp_disp, which is handled specially | |
12119 | by the linker. The result is: | |
12120 | lui $gp,%hi(_gp_disp) | |
12121 | addiu $gp,$gp,%lo(_gp_disp) | |
12122 | addu $gp,$gp,.cpload argument | |
12123 | The .cpload argument is normally $25 == $t9. */ | |
12124 | ||
12125 | static void | |
17a2f251 | 12126 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12127 | { |
12128 | expressionS ex; | |
12129 | int icnt = 0; | |
12130 | ||
6478892d TS |
12131 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12132 | .cpload is ignored. */ | |
12133 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12134 | { |
12135 | s_ignore (0); | |
12136 | return; | |
12137 | } | |
12138 | ||
d3ecfc59 | 12139 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12140 | if (mips_opts.noreorder == 0) |
12141 | as_warn (_(".cpload not in noreorder section")); | |
12142 | ||
12143 | ex.X_op = O_symbol; | |
12144 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12145 | ex.X_op_symbol = NULL; | |
12146 | ex.X_add_number = 0; | |
12147 | ||
12148 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12149 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12150 | |
c9914766 | 12151 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
17a2f251 TS |
12152 | macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register, |
12153 | mips_gp_register, BFD_RELOC_LO16); | |
252b5132 | 12154 | |
17a2f251 TS |
12155 | macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register, |
12156 | mips_gp_register, tc_get_register (0)); | |
252b5132 RH |
12157 | |
12158 | demand_empty_rest_of_line (); | |
12159 | } | |
12160 | ||
6478892d TS |
12161 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12162 | .cpsetup $reg1, offset|$reg2, label | |
12163 | ||
12164 | If offset is given, this results in: | |
12165 | sd $gp, offset($sp) | |
956cd1d6 | 12166 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12167 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12168 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12169 | |
12170 | If $reg2 is given, this results in: | |
12171 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12172 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12173 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12174 | daddu $gp, $gp, $reg1 | |
12175 | $reg1 is normally $25 == $t9. */ | |
6478892d | 12176 | static void |
17a2f251 | 12177 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12178 | { |
12179 | expressionS ex_off; | |
12180 | expressionS ex_sym; | |
12181 | int reg1; | |
12182 | int icnt = 0; | |
f21f8242 | 12183 | char *f; |
6478892d | 12184 | |
8586fc66 | 12185 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12186 | We also need NewABI support. */ |
12187 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12188 | { | |
12189 | s_ignore (0); | |
12190 | return; | |
12191 | } | |
12192 | ||
12193 | reg1 = tc_get_register (0); | |
12194 | SKIP_WHITESPACE (); | |
12195 | if (*input_line_pointer != ',') | |
12196 | { | |
12197 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12198 | return; | |
12199 | } | |
12200 | else | |
80245285 | 12201 | ++input_line_pointer; |
6478892d TS |
12202 | SKIP_WHITESPACE (); |
12203 | if (*input_line_pointer == '$') | |
80245285 TS |
12204 | { |
12205 | mips_cpreturn_register = tc_get_register (0); | |
12206 | mips_cpreturn_offset = -1; | |
12207 | } | |
6478892d | 12208 | else |
80245285 TS |
12209 | { |
12210 | mips_cpreturn_offset = get_absolute_expression (); | |
12211 | mips_cpreturn_register = -1; | |
12212 | } | |
6478892d TS |
12213 | SKIP_WHITESPACE (); |
12214 | if (*input_line_pointer != ',') | |
12215 | { | |
12216 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12217 | return; | |
12218 | } | |
12219 | else | |
f9419b05 | 12220 | ++input_line_pointer; |
6478892d | 12221 | SKIP_WHITESPACE (); |
f21f8242 | 12222 | expression (&ex_sym); |
6478892d TS |
12223 | |
12224 | if (mips_cpreturn_register == -1) | |
12225 | { | |
12226 | ex_off.X_op = O_constant; | |
12227 | ex_off.X_add_symbol = NULL; | |
12228 | ex_off.X_op_symbol = NULL; | |
12229 | ex_off.X_add_number = mips_cpreturn_offset; | |
12230 | ||
17a2f251 TS |
12231 | macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register, |
12232 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12233 | } |
12234 | else | |
17a2f251 TS |
12235 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register, |
12236 | mips_gp_register, 0); | |
6478892d | 12237 | |
f21f8242 AO |
12238 | /* Ensure there's room for the next two instructions, so that `f' |
12239 | doesn't end up with an address in the wrong frag. */ | |
12240 | frag_grow (8); | |
12241 | f = frag_more (0); | |
17a2f251 TS |
12242 | macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12243 | BFD_RELOC_GPREL16); | |
f21f8242 | 12244 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12245 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12246 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12247 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12248 | |
12249 | f = frag_more (0); | |
17a2f251 TS |
12250 | macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register, |
12251 | mips_gp_register, BFD_RELOC_GPREL16); | |
f21f8242 | 12252 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12253 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12254 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12255 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12256 | |
17a2f251 TS |
12257 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
12258 | mips_gp_register, reg1); | |
6478892d TS |
12259 | |
12260 | demand_empty_rest_of_line (); | |
12261 | } | |
12262 | ||
12263 | static void | |
17a2f251 | 12264 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12265 | { |
12266 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12267 | .cplocal is ignored. */ | |
12268 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12269 | { | |
12270 | s_ignore (0); | |
12271 | return; | |
12272 | } | |
12273 | ||
12274 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12275 | demand_empty_rest_of_line (); |
6478892d TS |
12276 | } |
12277 | ||
252b5132 RH |
12278 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12279 | offset from $sp. The offset is remembered, and after making a PIC | |
12280 | call $gp is restored from that location. */ | |
12281 | ||
12282 | static void | |
17a2f251 | 12283 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12284 | { |
12285 | expressionS ex; | |
12286 | int icnt = 0; | |
12287 | ||
6478892d | 12288 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12289 | .cprestore is ignored. */ |
6478892d | 12290 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12291 | { |
12292 | s_ignore (0); | |
12293 | return; | |
12294 | } | |
12295 | ||
12296 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12297 | mips_cprestore_valid = 1; |
252b5132 RH |
12298 | |
12299 | ex.X_op = O_constant; | |
12300 | ex.X_add_symbol = NULL; | |
12301 | ex.X_op_symbol = NULL; | |
12302 | ex.X_add_number = mips_cprestore_offset; | |
12303 | ||
17a2f251 | 12304 | macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN, |
815ddb50 | 12305 | mips_gp_register, SP); |
252b5132 RH |
12306 | |
12307 | demand_empty_rest_of_line (); | |
12308 | } | |
12309 | ||
6478892d TS |
12310 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12311 | was given in the preceeding .gpsetup, it results in: | |
12312 | ld $gp, offset($sp) | |
76b3015f | 12313 | |
6478892d TS |
12314 | If a register $reg2 was given there, it results in: |
12315 | daddiu $gp, $gp, $reg2 | |
12316 | */ | |
12317 | static void | |
17a2f251 | 12318 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12319 | { |
12320 | expressionS ex; | |
12321 | int icnt = 0; | |
12322 | ||
12323 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12324 | We also need NewABI support. */ | |
12325 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12326 | { | |
12327 | s_ignore (0); | |
12328 | return; | |
12329 | } | |
12330 | ||
12331 | if (mips_cpreturn_register == -1) | |
12332 | { | |
12333 | ex.X_op = O_constant; | |
12334 | ex.X_add_symbol = NULL; | |
12335 | ex.X_op_symbol = NULL; | |
12336 | ex.X_add_number = mips_cpreturn_offset; | |
12337 | ||
17a2f251 TS |
12338 | macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register, |
12339 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12340 | } |
12341 | else | |
17a2f251 TS |
12342 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register, |
12343 | mips_cpreturn_register, 0); | |
6478892d TS |
12344 | |
12345 | demand_empty_rest_of_line (); | |
12346 | } | |
12347 | ||
12348 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12349 | code. It sets the offset to use in gp_rel relocations. */ | |
12350 | ||
12351 | static void | |
17a2f251 | 12352 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12353 | { |
12354 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12355 | We also need NewABI support. */ | |
12356 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12357 | { | |
12358 | s_ignore (0); | |
12359 | return; | |
12360 | } | |
12361 | ||
def2e0dd | 12362 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12363 | |
12364 | demand_empty_rest_of_line (); | |
12365 | } | |
12366 | ||
252b5132 RH |
12367 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12368 | code. It generates a 32 bit GP relative reloc. */ | |
12369 | ||
12370 | static void | |
17a2f251 | 12371 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12372 | { |
12373 | symbolS *label; | |
12374 | expressionS ex; | |
12375 | char *p; | |
12376 | ||
12377 | /* When not generating PIC code, this is treated as .word. */ | |
12378 | if (mips_pic != SVR4_PIC) | |
12379 | { | |
12380 | s_cons (2); | |
12381 | return; | |
12382 | } | |
12383 | ||
12384 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12385 | mips_emit_delays (TRUE); |
252b5132 RH |
12386 | if (auto_align) |
12387 | mips_align (2, 0, label); | |
12388 | mips_clear_insn_labels (); | |
12389 | ||
12390 | expression (&ex); | |
12391 | ||
12392 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12393 | { | |
12394 | as_bad (_("Unsupported use of .gpword")); | |
12395 | ignore_rest_of_line (); | |
12396 | } | |
12397 | ||
12398 | p = frag_more (4); | |
17a2f251 | 12399 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12400 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12401 | BFD_RELOC_GPREL32); |
252b5132 RH |
12402 | |
12403 | demand_empty_rest_of_line (); | |
12404 | } | |
12405 | ||
10181a0d | 12406 | static void |
17a2f251 | 12407 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12408 | { |
12409 | symbolS *label; | |
12410 | expressionS ex; | |
12411 | char *p; | |
12412 | ||
12413 | /* When not generating PIC code, this is treated as .dword. */ | |
12414 | if (mips_pic != SVR4_PIC) | |
12415 | { | |
12416 | s_cons (3); | |
12417 | return; | |
12418 | } | |
12419 | ||
12420 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12421 | mips_emit_delays (TRUE); |
10181a0d AO |
12422 | if (auto_align) |
12423 | mips_align (3, 0, label); | |
12424 | mips_clear_insn_labels (); | |
12425 | ||
12426 | expression (&ex); | |
12427 | ||
12428 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12429 | { | |
12430 | as_bad (_("Unsupported use of .gpdword")); | |
12431 | ignore_rest_of_line (); | |
12432 | } | |
12433 | ||
12434 | p = frag_more (8); | |
17a2f251 | 12435 | md_number_to_chars (p, 0, 8); |
a105a300 | 12436 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12437 | BFD_RELOC_GPREL32); |
12438 | ||
12439 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12440 | ex.X_op = O_absent; | |
12441 | ex.X_add_symbol = 0; | |
12442 | ex.X_add_number = 0; | |
b34976b6 | 12443 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12444 | BFD_RELOC_64); |
12445 | ||
12446 | demand_empty_rest_of_line (); | |
12447 | } | |
12448 | ||
252b5132 RH |
12449 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12450 | tables in SVR4 PIC code. */ | |
12451 | ||
12452 | static void | |
17a2f251 | 12453 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12454 | { |
12455 | int icnt = 0; | |
12456 | int reg; | |
12457 | ||
10181a0d AO |
12458 | /* This is ignored when not generating SVR4 PIC code. */ |
12459 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12460 | { |
12461 | s_ignore (0); | |
12462 | return; | |
12463 | } | |
12464 | ||
12465 | /* Add $gp to the register named as an argument. */ | |
12466 | reg = tc_get_register (0); | |
17a2f251 TS |
12467 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
12468 | reg, reg, mips_gp_register); | |
252b5132 | 12469 | |
bdaaa2e1 | 12470 | demand_empty_rest_of_line (); |
252b5132 RH |
12471 | } |
12472 | ||
12473 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12474 | mips16 mode. This permits the linker to handle them specially, | |
12475 | such as generating jalx instructions when needed. We also make | |
12476 | them odd for the duration of the assembly, in order to generate the | |
12477 | right sort of code. We will make them even in the adjust_symtab | |
12478 | routine, while leaving them marked. This is convenient for the | |
12479 | debugger and the disassembler. The linker knows to make them odd | |
12480 | again. */ | |
12481 | ||
12482 | static void | |
17a2f251 | 12483 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12484 | { |
f9419b05 | 12485 | mips16_mark_labels (); |
252b5132 RH |
12486 | |
12487 | demand_empty_rest_of_line (); | |
12488 | } | |
12489 | ||
12490 | /* Handle a .stabn directive. We need these in order to mark a label | |
12491 | as being a mips16 text label correctly. Sometimes the compiler | |
12492 | will emit a label, followed by a .stabn, and then switch sections. | |
12493 | If the label and .stabn are in mips16 mode, then the label is | |
12494 | really a mips16 text label. */ | |
12495 | ||
12496 | static void | |
17a2f251 | 12497 | s_mips_stab (int type) |
252b5132 | 12498 | { |
f9419b05 | 12499 | if (type == 'n') |
252b5132 RH |
12500 | mips16_mark_labels (); |
12501 | ||
12502 | s_stab (type); | |
12503 | } | |
12504 | ||
12505 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12506 | */ | |
12507 | ||
12508 | static void | |
17a2f251 | 12509 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12510 | { |
12511 | char *name; | |
12512 | int c; | |
12513 | symbolS *symbolP; | |
12514 | expressionS exp; | |
12515 | ||
12516 | name = input_line_pointer; | |
12517 | c = get_symbol_end (); | |
12518 | symbolP = symbol_find_or_make (name); | |
12519 | S_SET_WEAK (symbolP); | |
12520 | *input_line_pointer = c; | |
12521 | ||
12522 | SKIP_WHITESPACE (); | |
12523 | ||
12524 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12525 | { | |
12526 | if (S_IS_DEFINED (symbolP)) | |
12527 | { | |
956cd1d6 | 12528 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12529 | S_GET_NAME (symbolP)); |
12530 | ignore_rest_of_line (); | |
12531 | return; | |
12532 | } | |
bdaaa2e1 | 12533 | |
252b5132 RH |
12534 | if (*input_line_pointer == ',') |
12535 | { | |
12536 | ++input_line_pointer; | |
12537 | SKIP_WHITESPACE (); | |
12538 | } | |
bdaaa2e1 | 12539 | |
252b5132 RH |
12540 | expression (&exp); |
12541 | if (exp.X_op != O_symbol) | |
12542 | { | |
12543 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12544 | ignore_rest_of_line (); |
252b5132 RH |
12545 | return; |
12546 | } | |
49309057 | 12547 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12548 | } |
12549 | ||
12550 | demand_empty_rest_of_line (); | |
12551 | } | |
12552 | ||
12553 | /* Parse a register string into a number. Called from the ECOFF code | |
12554 | to parse .frame. The argument is non-zero if this is the frame | |
12555 | register, so that we can record it in mips_frame_reg. */ | |
12556 | ||
12557 | int | |
17a2f251 | 12558 | tc_get_register (int frame) |
252b5132 RH |
12559 | { |
12560 | int reg; | |
12561 | ||
12562 | SKIP_WHITESPACE (); | |
12563 | if (*input_line_pointer++ != '$') | |
12564 | { | |
12565 | as_warn (_("expected `$'")); | |
85b51719 | 12566 | reg = ZERO; |
252b5132 | 12567 | } |
3882b010 | 12568 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12569 | { |
12570 | reg = get_absolute_expression (); | |
12571 | if (reg < 0 || reg >= 32) | |
12572 | { | |
12573 | as_warn (_("Bad register number")); | |
85b51719 | 12574 | reg = ZERO; |
252b5132 RH |
12575 | } |
12576 | } | |
12577 | else | |
12578 | { | |
76db943d | 12579 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12580 | { |
12581 | reg = RA; | |
12582 | input_line_pointer += 2; | |
12583 | } | |
76db943d | 12584 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12585 | { |
12586 | reg = FP; | |
12587 | input_line_pointer += 2; | |
12588 | } | |
252b5132 | 12589 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12590 | { |
12591 | reg = SP; | |
12592 | input_line_pointer += 2; | |
12593 | } | |
252b5132 | 12594 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12595 | { |
12596 | reg = GP; | |
12597 | input_line_pointer += 2; | |
12598 | } | |
252b5132 | 12599 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12600 | { |
12601 | reg = AT; | |
12602 | input_line_pointer += 2; | |
12603 | } | |
12604 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12605 | { | |
12606 | reg = KT0; | |
12607 | input_line_pointer += 3; | |
12608 | } | |
12609 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12610 | { | |
12611 | reg = KT1; | |
12612 | input_line_pointer += 3; | |
12613 | } | |
12614 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12615 | { | |
12616 | reg = ZERO; | |
12617 | input_line_pointer += 4; | |
12618 | } | |
252b5132 RH |
12619 | else |
12620 | { | |
12621 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12622 | reg = ZERO; |
12623 | while (ISALNUM(*input_line_pointer)) | |
12624 | input_line_pointer++; | |
252b5132 | 12625 | } |
252b5132 RH |
12626 | } |
12627 | if (frame) | |
7a621144 DJ |
12628 | { |
12629 | mips_frame_reg = reg != 0 ? reg : SP; | |
12630 | mips_frame_reg_valid = 1; | |
12631 | mips_cprestore_valid = 0; | |
12632 | } | |
252b5132 RH |
12633 | return reg; |
12634 | } | |
12635 | ||
12636 | valueT | |
17a2f251 | 12637 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12638 | { |
12639 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12640 | ||
12641 | #ifdef OBJ_ELF | |
12642 | /* We don't need to align ELF sections to the full alignment. | |
12643 | However, Irix 5 may prefer that we align them at least to a 16 | |
12644 | byte boundary. We don't bother to align the sections if we are | |
12645 | targeted for an embedded system. */ | |
12646 | if (strcmp (TARGET_OS, "elf") == 0) | |
12647 | return addr; | |
12648 | if (align > 4) | |
12649 | align = 4; | |
12650 | #endif | |
12651 | ||
12652 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12653 | } | |
12654 | ||
12655 | /* Utility routine, called from above as well. If called while the | |
12656 | input file is still being read, it's only an approximation. (For | |
12657 | example, a symbol may later become defined which appeared to be | |
12658 | undefined earlier.) */ | |
12659 | ||
12660 | static int | |
17a2f251 | 12661 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12662 | { |
12663 | if (sym == 0) | |
12664 | return 0; | |
12665 | ||
6478892d | 12666 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12667 | { |
12668 | const char *symname; | |
12669 | int change; | |
12670 | ||
c9914766 | 12671 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12672 | register. It can be if it is smaller than the -G size or if |
12673 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12674 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12675 | they can. */ |
12676 | symname = S_GET_NAME (sym); | |
12677 | if (symname != (const char *) NULL | |
12678 | && (strcmp (symname, "eprol") == 0 | |
12679 | || strcmp (symname, "etext") == 0 | |
12680 | || strcmp (symname, "_gp") == 0 | |
12681 | || strcmp (symname, "edata") == 0 | |
12682 | || strcmp (symname, "_fbss") == 0 | |
12683 | || strcmp (symname, "_fdata") == 0 | |
12684 | || strcmp (symname, "_ftext") == 0 | |
12685 | || strcmp (symname, "end") == 0 | |
12686 | || strcmp (symname, "_gp_disp") == 0)) | |
12687 | change = 1; | |
12688 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12689 | && (0 | |
12690 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12691 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12692 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12693 | <= g_switch_value)) | |
252b5132 RH |
12694 | #endif |
12695 | /* We must defer this decision until after the whole | |
12696 | file has been read, since there might be a .extern | |
12697 | after the first use of this symbol. */ | |
12698 | || (before_relaxing | |
12699 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12700 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12701 | #endif |
12702 | && S_GET_VALUE (sym) == 0) | |
12703 | || (S_GET_VALUE (sym) != 0 | |
12704 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12705 | change = 0; | |
12706 | else | |
12707 | { | |
12708 | const char *segname; | |
12709 | ||
12710 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12711 | assert (strcmp (segname, ".lit8") != 0 | |
12712 | && strcmp (segname, ".lit4") != 0); | |
12713 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12714 | && strcmp (segname, ".sbss") != 0 |
12715 | && strncmp (segname, ".sdata.", 7) != 0 | |
12716 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12717 | } |
12718 | return change; | |
12719 | } | |
12720 | else | |
c9914766 | 12721 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12722 | return 1; |
12723 | } | |
12724 | ||
5919d012 RS |
12725 | |
12726 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12727 | ||
12728 | static bfd_boolean | |
17a2f251 | 12729 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12730 | { |
12731 | asection *symsec; | |
12732 | bfd_boolean linkonce; | |
12733 | ||
12734 | /* Handle the case of a symbol equated to another symbol. */ | |
12735 | while (symbol_equated_reloc_p (sym)) | |
12736 | { | |
12737 | symbolS *n; | |
12738 | ||
12739 | /* It's possible to get a loop here in a badly written | |
12740 | program. */ | |
12741 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12742 | if (n == sym) | |
12743 | break; | |
12744 | sym = n; | |
12745 | } | |
12746 | ||
12747 | symsec = S_GET_SEGMENT (sym); | |
12748 | ||
12749 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12750 | linkonce = FALSE; | |
12751 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12752 | { | |
12753 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12754 | != 0) | |
12755 | linkonce = TRUE; | |
12756 | ||
12757 | /* The GNU toolchain uses an extension for ELF: a section | |
12758 | beginning with the magic string .gnu.linkonce is a linkonce | |
12759 | section. */ | |
12760 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12761 | sizeof ".gnu.linkonce" - 1) == 0) | |
12762 | linkonce = TRUE; | |
12763 | } | |
12764 | ||
12765 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12766 | return (symsec != &bfd_und_section | |
12767 | && symsec != &bfd_abs_section | |
12768 | && ! bfd_is_com_section (symsec) | |
12769 | && !linkonce | |
12770 | #ifdef OBJ_ELF | |
12771 | /* A global or weak symbol is treated as external. */ | |
12772 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12773 | || (! S_IS_WEAK (sym) | |
12774 | && (! S_IS_EXTERNAL (sym) | |
12775 | || mips_pic == EMBEDDED_PIC))) | |
12776 | #endif | |
12777 | ); | |
12778 | } | |
12779 | ||
12780 | ||
252b5132 RH |
12781 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12782 | extended opcode. SEC is the section the frag is in. */ | |
12783 | ||
12784 | static int | |
17a2f251 | 12785 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12786 | { |
12787 | int type; | |
12788 | register const struct mips16_immed_operand *op; | |
12789 | offsetT val; | |
12790 | int mintiny, maxtiny; | |
12791 | segT symsec; | |
98aa84af | 12792 | fragS *sym_frag; |
252b5132 RH |
12793 | |
12794 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12795 | return 0; | |
12796 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12797 | return 1; | |
12798 | ||
12799 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12800 | op = mips16_immed_operands; | |
12801 | while (op->type != type) | |
12802 | { | |
12803 | ++op; | |
12804 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12805 | } | |
12806 | ||
12807 | if (op->unsp) | |
12808 | { | |
12809 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12810 | { | |
12811 | mintiny = 1; | |
12812 | maxtiny = 1 << op->nbits; | |
12813 | } | |
12814 | else | |
12815 | { | |
12816 | mintiny = 0; | |
12817 | maxtiny = (1 << op->nbits) - 1; | |
12818 | } | |
12819 | } | |
12820 | else | |
12821 | { | |
12822 | mintiny = - (1 << (op->nbits - 1)); | |
12823 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12824 | } | |
12825 | ||
98aa84af | 12826 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12827 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12828 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12829 | |
12830 | if (op->pcrel) | |
12831 | { | |
12832 | addressT addr; | |
12833 | ||
12834 | /* We won't have the section when we are called from | |
12835 | mips_relax_frag. However, we will always have been called | |
12836 | from md_estimate_size_before_relax first. If this is a | |
12837 | branch to a different section, we mark it as such. If SEC is | |
12838 | NULL, and the frag is not marked, then it must be a branch to | |
12839 | the same section. */ | |
12840 | if (sec == NULL) | |
12841 | { | |
12842 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12843 | return 1; | |
12844 | } | |
12845 | else | |
12846 | { | |
98aa84af | 12847 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12848 | if (symsec != sec) |
12849 | { | |
12850 | fragp->fr_subtype = | |
12851 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12852 | ||
12853 | /* FIXME: We should support this, and let the linker | |
12854 | catch branches and loads that are out of range. */ | |
12855 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12856 | _("unsupported PC relative reference to different section")); | |
12857 | ||
12858 | return 1; | |
12859 | } | |
98aa84af AM |
12860 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12861 | /* Assume non-extended on the first relaxation pass. | |
12862 | The address we have calculated will be bogus if this is | |
12863 | a forward branch to another frag, as the forward frag | |
12864 | will have fr_address == 0. */ | |
12865 | return 0; | |
252b5132 RH |
12866 | } |
12867 | ||
12868 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12869 | the same section. If the relax_marker of the symbol fragment |
12870 | differs from the relax_marker of this fragment, we have not | |
12871 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12872 | in STRETCH in order to get a better estimate of the address. |
12873 | This particularly matters because of the shift bits. */ | |
12874 | if (stretch != 0 | |
98aa84af | 12875 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12876 | { |
12877 | fragS *f; | |
12878 | ||
12879 | /* Adjust stretch for any alignment frag. Note that if have | |
12880 | been expanding the earlier code, the symbol may be | |
12881 | defined in what appears to be an earlier frag. FIXME: | |
12882 | This doesn't handle the fr_subtype field, which specifies | |
12883 | a maximum number of bytes to skip when doing an | |
12884 | alignment. */ | |
98aa84af | 12885 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12886 | { |
12887 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12888 | { | |
12889 | if (stretch < 0) | |
12890 | stretch = - ((- stretch) | |
12891 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12892 | else | |
12893 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12894 | if (stretch == 0) | |
12895 | break; | |
12896 | } | |
12897 | } | |
12898 | if (f != NULL) | |
12899 | val += stretch; | |
12900 | } | |
12901 | ||
12902 | addr = fragp->fr_address + fragp->fr_fix; | |
12903 | ||
12904 | /* The base address rules are complicated. The base address of | |
12905 | a branch is the following instruction. The base address of a | |
12906 | PC relative load or add is the instruction itself, but if it | |
12907 | is in a delay slot (in which case it can not be extended) use | |
12908 | the address of the instruction whose delay slot it is in. */ | |
12909 | if (type == 'p' || type == 'q') | |
12910 | { | |
12911 | addr += 2; | |
12912 | ||
12913 | /* If we are currently assuming that this frag should be | |
12914 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12915 | higher. */ |
252b5132 RH |
12916 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12917 | addr += 2; | |
12918 | ||
12919 | /* Ignore the low bit in the target, since it will be set | |
12920 | for a text label. */ | |
12921 | if ((val & 1) != 0) | |
12922 | --val; | |
12923 | } | |
12924 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12925 | addr -= 4; | |
12926 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12927 | addr -= 2; | |
12928 | ||
12929 | val -= addr & ~ ((1 << op->shift) - 1); | |
12930 | ||
12931 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12932 | if (type == 'p' || type == 'q') | |
12933 | val /= 2; | |
12934 | ||
12935 | /* If any of the shifted bits are set, we must use an extended | |
12936 | opcode. If the address depends on the size of this | |
12937 | instruction, this can lead to a loop, so we arrange to always | |
12938 | use an extended opcode. We only check this when we are in | |
12939 | the main relaxation loop, when SEC is NULL. */ | |
12940 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12941 | { | |
12942 | fragp->fr_subtype = | |
12943 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12944 | return 1; | |
12945 | } | |
12946 | ||
12947 | /* If we are about to mark a frag as extended because the value | |
12948 | is precisely maxtiny + 1, then there is a chance of an | |
12949 | infinite loop as in the following code: | |
12950 | la $4,foo | |
12951 | .skip 1020 | |
12952 | .align 2 | |
12953 | foo: | |
12954 | In this case when the la is extended, foo is 0x3fc bytes | |
12955 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12956 | the la must be extended. To avoid this loop, we mark the | |
12957 | frag as extended if it was small, and is about to become | |
12958 | extended with a value of maxtiny + 1. */ | |
12959 | if (val == ((maxtiny + 1) << op->shift) | |
12960 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12961 | && sec == NULL) | |
12962 | { | |
12963 | fragp->fr_subtype = | |
12964 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12965 | return 1; | |
12966 | } | |
12967 | } | |
12968 | else if (symsec != absolute_section && sec != NULL) | |
12969 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12970 | ||
12971 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12972 | || val < (mintiny << op->shift) | |
12973 | || val > (maxtiny << op->shift)) | |
12974 | return 1; | |
12975 | else | |
12976 | return 0; | |
12977 | } | |
12978 | ||
4a6a3df4 AO |
12979 | /* Compute the length of a branch sequence, and adjust the |
12980 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12981 | worst-case length is computed, with UPDATE being used to indicate | |
12982 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12983 | branch is to be computed. */ | |
12984 | static int | |
17a2f251 | 12985 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12986 | { |
b34976b6 | 12987 | bfd_boolean toofar; |
4a6a3df4 AO |
12988 | int length; |
12989 | ||
12990 | if (fragp | |
12991 | && S_IS_DEFINED (fragp->fr_symbol) | |
12992 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12993 | { | |
12994 | addressT addr; | |
12995 | offsetT val; | |
12996 | ||
12997 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12998 | ||
12999 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13000 | ||
13001 | val -= addr; | |
13002 | ||
13003 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13004 | } | |
13005 | else if (fragp) | |
13006 | /* If the symbol is not defined or it's in a different segment, | |
13007 | assume the user knows what's going on and emit a short | |
13008 | branch. */ | |
b34976b6 | 13009 | toofar = FALSE; |
4a6a3df4 | 13010 | else |
b34976b6 | 13011 | toofar = TRUE; |
4a6a3df4 AO |
13012 | |
13013 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13014 | fragp->fr_subtype | |
af6ae2ad | 13015 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13016 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13017 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13018 | toofar); | |
13019 | ||
13020 | length = 4; | |
13021 | if (toofar) | |
13022 | { | |
13023 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13024 | length += 8; | |
13025 | ||
13026 | if (mips_pic != NO_PIC) | |
13027 | { | |
13028 | /* Additional space for PIC loading of target address. */ | |
13029 | length += 8; | |
13030 | if (mips_opts.isa == ISA_MIPS1) | |
13031 | /* Additional space for $at-stabilizing nop. */ | |
13032 | length += 4; | |
13033 | } | |
13034 | ||
13035 | /* If branch is conditional. */ | |
13036 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13037 | length += 8; | |
13038 | } | |
b34976b6 | 13039 | |
4a6a3df4 AO |
13040 | return length; |
13041 | } | |
13042 | ||
252b5132 RH |
13043 | /* Estimate the size of a frag before relaxing. Unless this is the |
13044 | mips16, we are not really relaxing here, and the final size is | |
13045 | encoded in the subtype information. For the mips16, we have to | |
13046 | decide whether we are using an extended opcode or not. */ | |
13047 | ||
252b5132 | 13048 | int |
17a2f251 | 13049 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13050 | { |
5919d012 | 13051 | int change; |
252b5132 | 13052 | |
4a6a3df4 AO |
13053 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13054 | { | |
13055 | ||
b34976b6 AM |
13056 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13057 | ||
4a6a3df4 AO |
13058 | return fragp->fr_var; |
13059 | } | |
13060 | ||
252b5132 | 13061 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13062 | /* We don't want to modify the EXTENDED bit here; it might get us |
13063 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13064 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13065 | |
13066 | if (mips_pic == NO_PIC) | |
5919d012 | 13067 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13068 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13069 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13070 | else |
13071 | abort (); | |
13072 | ||
13073 | if (change) | |
13074 | { | |
13075 | /* Record the offset to the first reloc in the fr_opcode field. | |
13076 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13077 | must be expanded. */ | |
13078 | fragp->fr_opcode = (fragp->fr_literal | |
13079 | + fragp->fr_fix | |
13080 | - RELAX_OLD (fragp->fr_subtype) | |
13081 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13082 | /* FIXME: This really needs as_warn_where. */ | |
13083 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13084 | as_warn (_("AT used after \".set noat\" or macro used after " |
13085 | "\".set nomacro\"")); | |
13086 | ||
13087 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13088 | } |
13089 | ||
9a41af64 | 13090 | return 0; |
252b5132 RH |
13091 | } |
13092 | ||
13093 | /* This is called to see whether a reloc against a defined symbol | |
13094 | should be converted into a reloc against a section. Don't adjust | |
13095 | MIPS16 jump relocations, so we don't have to worry about the format | |
13096 | of the offset in the .o file. Don't adjust relocations against | |
13097 | mips16 symbols, so that the linker can find them if it needs to set | |
13098 | up a stub. */ | |
13099 | ||
13100 | int | |
17a2f251 | 13101 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
13102 | { |
13103 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13104 | return 0; | |
a161fe53 | 13105 | |
252b5132 RH |
13106 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13107 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13108 | return 0; | |
a161fe53 | 13109 | |
252b5132 RH |
13110 | if (fixp->fx_addsy == NULL) |
13111 | return 1; | |
a161fe53 | 13112 | |
252b5132 RH |
13113 | #ifdef OBJ_ELF |
13114 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13115 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13116 | && fixp->fx_subsy == NULL) | |
13117 | return 0; | |
13118 | #endif | |
a161fe53 | 13119 | |
252b5132 RH |
13120 | return 1; |
13121 | } | |
13122 | ||
13123 | /* Translate internal representation of relocation info to BFD target | |
13124 | format. */ | |
13125 | ||
13126 | arelent ** | |
17a2f251 | 13127 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13128 | { |
13129 | static arelent *retval[4]; | |
13130 | arelent *reloc; | |
13131 | bfd_reloc_code_real_type code; | |
13132 | ||
4b0cff4e TS |
13133 | memset (retval, 0, sizeof(retval)); |
13134 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13135 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13136 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13137 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13138 | ||
13139 | if (mips_pic == EMBEDDED_PIC | |
13140 | && SWITCH_TABLE (fixp)) | |
13141 | { | |
13142 | /* For a switch table entry we use a special reloc. The addend | |
13143 | is actually the difference between the reloc address and the | |
13144 | subtrahend. */ | |
13145 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13146 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13147 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13148 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13149 | } | |
13150 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13151 | { | |
4514d474 CD |
13152 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13153 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13154 | else |
4514d474 CD |
13155 | { |
13156 | /* We use a special addend for an internal RELLO reloc. */ | |
13157 | if (symbol_section_p (fixp->fx_addsy)) | |
13158 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13159 | else | |
13160 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13161 | } | |
252b5132 RH |
13162 | } |
13163 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13164 | { | |
13165 | assert (fixp->fx_next != NULL | |
13166 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13167 | |
13168 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13169 | accordingly. */ |
4514d474 CD |
13170 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13171 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13172 | else |
4514d474 CD |
13173 | { |
13174 | /* We use a special addend for an internal RELHI reloc. */ | |
13175 | if (symbol_section_p (fixp->fx_addsy)) | |
13176 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13177 | + fixp->fx_next->fx_where | |
13178 | - S_GET_VALUE (fixp->fx_subsy)); | |
13179 | else | |
13180 | reloc->addend = (fixp->fx_addnumber | |
13181 | + fixp->fx_next->fx_frag->fr_address | |
13182 | + fixp->fx_next->fx_where); | |
13183 | } | |
252b5132 | 13184 | } |
4514d474 CD |
13185 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13186 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13187 | else |
13188 | { | |
13189 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13190 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13191 | handling. */ | |
13192 | reloc->addend = reloc->address; | |
13193 | else | |
13194 | reloc->addend = -reloc->address; | |
13195 | } | |
13196 | ||
13197 | /* If this is a variant frag, we may need to adjust the existing | |
13198 | reloc and generate a new one. */ | |
13199 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13200 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13201 | && ! HAVE_NEWABI) | |
f5040a92 AO |
13202 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP |
13203 | && HAVE_NEWABI) | |
252b5132 RH |
13204 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13205 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13206 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13207 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13208 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13209 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13210 | ) |
252b5132 RH |
13211 | { |
13212 | arelent *reloc2; | |
13213 | ||
13214 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13215 | ||
13216 | /* If this is not the last reloc in this frag, then we have two | |
13217 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13218 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13219 | the second one handle all of them. */ | |
13220 | if (fixp->fx_next != NULL | |
13221 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13222 | { | |
cdf6fd85 TS |
13223 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13224 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13225 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13226 | && (fixp->fx_next->fx_r_type | |
13227 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13228 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13229 | && (fixp->fx_next->fx_r_type | |
13230 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13231 | retval[0] = NULL; | |
13232 | return retval; | |
13233 | } | |
13234 | ||
13235 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13236 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
f5040a92 | 13237 | reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 | 13238 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
49309057 ILT |
13239 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13240 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13241 | reloc2->address = (reloc->address |
13242 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13243 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
a7ebbfdf | 13244 | reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy) |
f5040a92 | 13245 | + fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 RH |
13246 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
13247 | assert (reloc2->howto != NULL); | |
13248 | ||
13249 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13250 | { | |
13251 | arelent *reloc3; | |
13252 | ||
13253 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
252b5132 RH |
13254 | *reloc3 = *reloc2; |
13255 | reloc3->address += 4; | |
13256 | } | |
13257 | ||
13258 | if (mips_pic == NO_PIC) | |
13259 | { | |
cdf6fd85 | 13260 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13261 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13262 | } | |
13263 | else if (mips_pic == SVR4_PIC) | |
13264 | { | |
13265 | switch (fixp->fx_r_type) | |
13266 | { | |
13267 | default: | |
13268 | abort (); | |
13269 | case BFD_RELOC_MIPS_GOT16: | |
13270 | break; | |
252b5132 RH |
13271 | case BFD_RELOC_MIPS_GOT_LO16: |
13272 | case BFD_RELOC_MIPS_CALL_LO16: | |
ed6fb7bd SC |
13273 | if (HAVE_NEWABI) |
13274 | { | |
ed6fb7bd SC |
13275 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; |
13276 | reloc2->howto = bfd_reloc_type_lookup | |
13277 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13278 | } | |
13279 | else | |
13280 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13281 | break; | |
f5040a92 AO |
13282 | case BFD_RELOC_MIPS_CALL16: |
13283 | case BFD_RELOC_MIPS_GOT_OFST: | |
13284 | case BFD_RELOC_MIPS_GOT_DISP: | |
13285 | if (HAVE_NEWABI) | |
13286 | { | |
13287 | /* It may seem nonsensical to relax GOT_DISP to | |
13288 | GOT_DISP, but we're actually turning a GOT_DISP | |
13289 | without offset into a GOT_DISP with an offset, | |
13290 | getting rid of the separate addition, which we can | |
13291 | do when the symbol is found to be local. */ | |
13292 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13293 | retval[1] = NULL; | |
13294 | } | |
13295 | else | |
13296 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13297 | break; | |
252b5132 RH |
13298 | } |
13299 | } | |
13300 | else | |
13301 | abort (); | |
13302 | } | |
13303 | ||
438c16b8 TS |
13304 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13305 | entry to be used in the relocation's section offset. */ | |
13306 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13307 | { |
13308 | reloc->address = reloc->addend; | |
13309 | reloc->addend = 0; | |
13310 | } | |
13311 | ||
13312 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13313 | fixup_segment converted a non-PC relative reloc into a PC | |
13314 | relative reloc. In such a case, we need to convert the reloc | |
13315 | code. */ | |
13316 | code = fixp->fx_r_type; | |
13317 | if (fixp->fx_pcrel) | |
13318 | { | |
13319 | switch (code) | |
13320 | { | |
13321 | case BFD_RELOC_8: | |
13322 | code = BFD_RELOC_8_PCREL; | |
13323 | break; | |
13324 | case BFD_RELOC_16: | |
13325 | code = BFD_RELOC_16_PCREL; | |
13326 | break; | |
13327 | case BFD_RELOC_32: | |
13328 | code = BFD_RELOC_32_PCREL; | |
13329 | break; | |
13330 | case BFD_RELOC_64: | |
13331 | code = BFD_RELOC_64_PCREL; | |
13332 | break; | |
13333 | case BFD_RELOC_8_PCREL: | |
13334 | case BFD_RELOC_16_PCREL: | |
13335 | case BFD_RELOC_32_PCREL: | |
13336 | case BFD_RELOC_64_PCREL: | |
13337 | case BFD_RELOC_16_PCREL_S2: | |
13338 | case BFD_RELOC_PCREL_HI16_S: | |
13339 | case BFD_RELOC_PCREL_LO16: | |
13340 | break; | |
13341 | default: | |
13342 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13343 | _("Cannot make %s relocation PC relative"), | |
13344 | bfd_get_reloc_code_name (code)); | |
13345 | } | |
13346 | } | |
13347 | ||
0b25d3e6 AO |
13348 | /* To support a PC relative reloc when generating embedded PIC code |
13349 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13350 | make sure that we don't let such a reloc escape normally. */ | |
13351 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13352 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13353 | && code == BFD_RELOC_16_PCREL_S2 | |
13354 | && mips_pic != EMBEDDED_PIC) | |
13355 | reloc->howto = NULL; | |
13356 | else | |
13357 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13358 | ||
252b5132 RH |
13359 | if (reloc->howto == NULL) |
13360 | { | |
13361 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13362 | _("Can not represent %s relocation in this object file format"), | |
13363 | bfd_get_reloc_code_name (code)); | |
13364 | retval[0] = NULL; | |
13365 | } | |
13366 | ||
13367 | return retval; | |
13368 | } | |
13369 | ||
13370 | /* Relax a machine dependent frag. This returns the amount by which | |
13371 | the current size of the frag should change. */ | |
13372 | ||
13373 | int | |
17a2f251 | 13374 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13375 | { |
4a6a3df4 AO |
13376 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13377 | { | |
13378 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13379 | |
13380 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13381 | |
13382 | return fragp->fr_var - old_var; | |
13383 | } | |
13384 | ||
252b5132 RH |
13385 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13386 | return 0; | |
13387 | ||
c4e7957c | 13388 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13389 | { |
13390 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13391 | return 0; | |
13392 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13393 | return 2; | |
13394 | } | |
13395 | else | |
13396 | { | |
13397 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13398 | return 0; | |
13399 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13400 | return -2; | |
13401 | } | |
13402 | ||
13403 | return 0; | |
13404 | } | |
13405 | ||
13406 | /* Convert a machine dependent frag. */ | |
13407 | ||
13408 | void | |
17a2f251 | 13409 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 RH |
13410 | { |
13411 | int old, new; | |
13412 | char *fixptr; | |
13413 | ||
4a6a3df4 AO |
13414 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13415 | { | |
13416 | bfd_byte *buf; | |
13417 | unsigned long insn; | |
13418 | expressionS exp; | |
13419 | fixS *fixp; | |
b34976b6 | 13420 | |
4a6a3df4 AO |
13421 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13422 | ||
13423 | if (target_big_endian) | |
13424 | insn = bfd_getb32 (buf); | |
13425 | else | |
13426 | insn = bfd_getl32 (buf); | |
b34976b6 | 13427 | |
4a6a3df4 AO |
13428 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13429 | { | |
13430 | /* We generate a fixup instead of applying it right now | |
13431 | because, if there are linker relaxations, we're going to | |
13432 | need the relocations. */ | |
13433 | exp.X_op = O_symbol; | |
13434 | exp.X_add_symbol = fragp->fr_symbol; | |
13435 | exp.X_add_number = fragp->fr_offset; | |
13436 | ||
13437 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13438 | 4, &exp, 1, |
13439 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13440 | fixp->fx_file = fragp->fr_file; |
13441 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13442 | |
17a2f251 | 13443 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13444 | buf += 4; |
13445 | } | |
13446 | else | |
13447 | { | |
13448 | int i; | |
13449 | ||
13450 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13451 | _("relaxed out-of-range branch into a jump")); | |
13452 | ||
13453 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13454 | goto uncond; | |
13455 | ||
13456 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13457 | { | |
13458 | /* Reverse the branch. */ | |
13459 | switch ((insn >> 28) & 0xf) | |
13460 | { | |
13461 | case 4: | |
13462 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13463 | have the condition reversed by tweaking a single | |
13464 | bit, and their opcodes all have 0x4???????. */ | |
13465 | assert ((insn & 0xf1000000) == 0x41000000); | |
13466 | insn ^= 0x00010000; | |
13467 | break; | |
13468 | ||
13469 | case 0: | |
13470 | /* bltz 0x04000000 bgez 0x04010000 | |
13471 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13472 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13473 | insn ^= 0x00010000; | |
13474 | break; | |
b34976b6 | 13475 | |
4a6a3df4 AO |
13476 | case 1: |
13477 | /* beq 0x10000000 bne 0x14000000 | |
13478 | blez 0x18000000 bgtz 0x1c000000 */ | |
13479 | insn ^= 0x04000000; | |
13480 | break; | |
13481 | ||
13482 | default: | |
13483 | abort (); | |
13484 | } | |
13485 | } | |
13486 | ||
13487 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13488 | { | |
13489 | /* Clear the and-link bit. */ | |
13490 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13491 | ||
13492 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13493 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13494 | insn &= ~0x00100000; | |
13495 | } | |
13496 | ||
13497 | /* Branch over the branch (if the branch was likely) or the | |
13498 | full jump (not likely case). Compute the offset from the | |
13499 | current instruction to branch to. */ | |
13500 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13501 | i = 16; | |
13502 | else | |
13503 | { | |
13504 | /* How many bytes in instructions we've already emitted? */ | |
13505 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13506 | /* How many bytes in instructions from here to the end? */ | |
13507 | i = fragp->fr_var - i; | |
13508 | } | |
13509 | /* Convert to instruction count. */ | |
13510 | i >>= 2; | |
13511 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13512 | i--; |
4a6a3df4 AO |
13513 | insn |= i; |
13514 | /* Branch over the jump. */ | |
17a2f251 | 13515 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13516 | buf += 4; |
13517 | ||
13518 | /* Nop */ | |
17a2f251 | 13519 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13520 | buf += 4; |
13521 | ||
13522 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13523 | { | |
13524 | /* beql $0, $0, 2f */ | |
13525 | insn = 0x50000000; | |
13526 | /* Compute the PC offset from the current instruction to | |
13527 | the end of the variable frag. */ | |
13528 | /* How many bytes in instructions we've already emitted? */ | |
13529 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13530 | /* How many bytes in instructions from here to the end? */ | |
13531 | i = fragp->fr_var - i; | |
13532 | /* Convert to instruction count. */ | |
13533 | i >>= 2; | |
13534 | /* Don't decrement i, because we want to branch over the | |
13535 | delay slot. */ | |
13536 | ||
13537 | insn |= i; | |
17a2f251 | 13538 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13539 | buf += 4; |
13540 | ||
17a2f251 | 13541 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13542 | buf += 4; |
13543 | } | |
13544 | ||
13545 | uncond: | |
13546 | if (mips_pic == NO_PIC) | |
13547 | { | |
13548 | /* j or jal. */ | |
13549 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13550 | ? 0x0c000000 : 0x08000000); | |
13551 | exp.X_op = O_symbol; | |
13552 | exp.X_add_symbol = fragp->fr_symbol; | |
13553 | exp.X_add_number = fragp->fr_offset; | |
13554 | ||
13555 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13556 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13557 | fixp->fx_file = fragp->fr_file; | |
13558 | fixp->fx_line = fragp->fr_line; | |
13559 | ||
17a2f251 | 13560 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13561 | buf += 4; |
13562 | } | |
13563 | else | |
13564 | { | |
13565 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13566 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13567 | exp.X_op = O_symbol; | |
13568 | exp.X_add_symbol = fragp->fr_symbol; | |
13569 | exp.X_add_number = fragp->fr_offset; | |
13570 | ||
13571 | if (fragp->fr_offset) | |
13572 | { | |
13573 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13574 | exp.X_add_number = 0; | |
13575 | } | |
13576 | ||
13577 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13578 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13579 | fixp->fx_file = fragp->fr_file; | |
13580 | fixp->fx_line = fragp->fr_line; | |
13581 | ||
17a2f251 | 13582 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13583 | buf += 4; |
b34976b6 | 13584 | |
4a6a3df4 AO |
13585 | if (mips_opts.isa == ISA_MIPS1) |
13586 | { | |
13587 | /* nop */ | |
17a2f251 | 13588 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13589 | buf += 4; |
13590 | } | |
13591 | ||
13592 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13593 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13594 | ||
13595 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13596 | 4, &exp, 0, BFD_RELOC_LO16); | |
13597 | fixp->fx_file = fragp->fr_file; | |
13598 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13599 | |
17a2f251 | 13600 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13601 | buf += 4; |
13602 | ||
13603 | /* j(al)r $at. */ | |
13604 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13605 | insn = 0x0020f809; | |
13606 | else | |
13607 | insn = 0x00200008; | |
13608 | ||
17a2f251 | 13609 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13610 | buf += 4; |
13611 | } | |
13612 | } | |
13613 | ||
13614 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13615 | + fragp->fr_fix + fragp->fr_var); | |
13616 | ||
13617 | fragp->fr_fix += fragp->fr_var; | |
13618 | ||
13619 | return; | |
13620 | } | |
13621 | ||
252b5132 RH |
13622 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13623 | { | |
13624 | int type; | |
13625 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13626 | bfd_boolean small, ext; |
252b5132 RH |
13627 | offsetT val; |
13628 | bfd_byte *buf; | |
13629 | unsigned long insn; | |
b34976b6 | 13630 | bfd_boolean use_extend; |
252b5132 RH |
13631 | unsigned short extend; |
13632 | ||
13633 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13634 | op = mips16_immed_operands; | |
13635 | while (op->type != type) | |
13636 | ++op; | |
13637 | ||
13638 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13639 | { | |
b34976b6 AM |
13640 | small = FALSE; |
13641 | ext = TRUE; | |
252b5132 RH |
13642 | } |
13643 | else | |
13644 | { | |
b34976b6 AM |
13645 | small = TRUE; |
13646 | ext = FALSE; | |
252b5132 RH |
13647 | } |
13648 | ||
6386f3a7 | 13649 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13650 | val = S_GET_VALUE (fragp->fr_symbol); |
13651 | if (op->pcrel) | |
13652 | { | |
13653 | addressT addr; | |
13654 | ||
13655 | addr = fragp->fr_address + fragp->fr_fix; | |
13656 | ||
13657 | /* The rules for the base address of a PC relative reloc are | |
13658 | complicated; see mips16_extended_frag. */ | |
13659 | if (type == 'p' || type == 'q') | |
13660 | { | |
13661 | addr += 2; | |
13662 | if (ext) | |
13663 | addr += 2; | |
13664 | /* Ignore the low bit in the target, since it will be | |
13665 | set for a text label. */ | |
13666 | if ((val & 1) != 0) | |
13667 | --val; | |
13668 | } | |
13669 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13670 | addr -= 4; | |
13671 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13672 | addr -= 2; | |
13673 | ||
13674 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13675 | val -= addr; | |
13676 | ||
13677 | /* Make sure the section winds up with the alignment we have | |
13678 | assumed. */ | |
13679 | if (op->shift > 0) | |
13680 | record_alignment (asec, op->shift); | |
13681 | } | |
13682 | ||
13683 | if (ext | |
13684 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13685 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13686 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13687 | _("extended instruction in delay slot")); | |
13688 | ||
13689 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13690 | ||
13691 | if (target_big_endian) | |
13692 | insn = bfd_getb16 (buf); | |
13693 | else | |
13694 | insn = bfd_getl16 (buf); | |
13695 | ||
13696 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13697 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13698 | small, ext, &insn, &use_extend, &extend); | |
13699 | ||
13700 | if (use_extend) | |
13701 | { | |
17a2f251 | 13702 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13703 | fragp->fr_fix += 2; |
13704 | buf += 2; | |
13705 | } | |
13706 | ||
17a2f251 | 13707 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13708 | fragp->fr_fix += 2; |
13709 | buf += 2; | |
13710 | } | |
13711 | else | |
13712 | { | |
13713 | if (fragp->fr_opcode == NULL) | |
13714 | return; | |
13715 | ||
13716 | old = RELAX_OLD (fragp->fr_subtype); | |
13717 | new = RELAX_NEW (fragp->fr_subtype); | |
13718 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13719 | ||
13720 | if (new > 0) | |
f5040a92 | 13721 | memmove (fixptr - old, fixptr, new); |
252b5132 RH |
13722 | |
13723 | fragp->fr_fix += new - old; | |
13724 | } | |
13725 | } | |
13726 | ||
13727 | #ifdef OBJ_ELF | |
13728 | ||
13729 | /* This function is called after the relocs have been generated. | |
13730 | We've been storing mips16 text labels as odd. Here we convert them | |
13731 | back to even for the convenience of the debugger. */ | |
13732 | ||
13733 | void | |
17a2f251 | 13734 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13735 | { |
13736 | asymbol **syms; | |
13737 | unsigned int count, i; | |
13738 | ||
13739 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13740 | return; | |
13741 | ||
13742 | syms = bfd_get_outsymbols (stdoutput); | |
13743 | count = bfd_get_symcount (stdoutput); | |
13744 | for (i = 0; i < count; i++, syms++) | |
13745 | { | |
13746 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13747 | && ((*syms)->value & 1) != 0) | |
13748 | { | |
13749 | (*syms)->value &= ~1; | |
13750 | /* If the symbol has an odd size, it was probably computed | |
13751 | incorrectly, so adjust that as well. */ | |
13752 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13753 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13754 | } | |
13755 | } | |
13756 | } | |
13757 | ||
13758 | #endif | |
13759 | ||
13760 | /* This function is called whenever a label is defined. It is used | |
13761 | when handling branch delays; if a branch has a label, we assume we | |
13762 | can not move it. */ | |
13763 | ||
13764 | void | |
17a2f251 | 13765 | mips_define_label (symbolS *sym) |
252b5132 RH |
13766 | { |
13767 | struct insn_label_list *l; | |
13768 | ||
13769 | if (free_insn_labels == NULL) | |
13770 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13771 | else | |
13772 | { | |
13773 | l = free_insn_labels; | |
13774 | free_insn_labels = l->next; | |
13775 | } | |
13776 | ||
13777 | l->label = sym; | |
13778 | l->next = insn_labels; | |
13779 | insn_labels = l; | |
13780 | } | |
13781 | \f | |
13782 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13783 | ||
13784 | /* Some special processing for a MIPS ELF file. */ | |
13785 | ||
13786 | void | |
17a2f251 | 13787 | mips_elf_final_processing (void) |
252b5132 RH |
13788 | { |
13789 | /* Write out the register information. */ | |
316f5878 | 13790 | if (mips_abi != N64_ABI) |
252b5132 RH |
13791 | { |
13792 | Elf32_RegInfo s; | |
13793 | ||
13794 | s.ri_gprmask = mips_gprmask; | |
13795 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13796 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13797 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13798 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13799 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13800 | ||
13801 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13802 | ((Elf32_External_RegInfo *) | |
13803 | mips_regmask_frag)); | |
13804 | } | |
13805 | else | |
13806 | { | |
13807 | Elf64_Internal_RegInfo s; | |
13808 | ||
13809 | s.ri_gprmask = mips_gprmask; | |
13810 | s.ri_pad = 0; | |
13811 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13812 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13813 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13814 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13815 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13816 | ||
13817 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13818 | ((Elf64_External_RegInfo *) | |
13819 | mips_regmask_frag)); | |
13820 | } | |
13821 | ||
13822 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13823 | sort of BFD interface for this. */ | |
13824 | if (mips_any_noreorder) | |
13825 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13826 | if (mips_pic != NO_PIC) | |
143d77c5 | 13827 | { |
252b5132 | 13828 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13829 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13830 | } | |
13831 | if (mips_abicalls) | |
13832 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13833 | |
98d3f06f | 13834 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13835 | if (file_ase_mips16) |
13836 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13837 | #if 0 /* XXX FIXME */ |
13838 | if (file_ase_mips3d) | |
13839 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13840 | #endif | |
deec1734 CD |
13841 | if (file_ase_mdmx) |
13842 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13843 | |
bdaaa2e1 | 13844 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13845 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13846 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13847 | else if (mips_abi == O64_ABI) |
252b5132 | 13848 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13849 | else if (mips_abi == EABI_ABI) |
252b5132 | 13850 | { |
316f5878 | 13851 | if (!file_mips_gp32) |
252b5132 RH |
13852 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13853 | else | |
13854 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13855 | } | |
316f5878 | 13856 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13857 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13858 | ||
c9914766 | 13859 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13860 | |
13861 | if (mips_32bitmode) | |
13862 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13863 | } | |
13864 | ||
13865 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13866 | \f | |
beae10d5 KH |
13867 | typedef struct proc { |
13868 | symbolS *isym; | |
13869 | unsigned long reg_mask; | |
13870 | unsigned long reg_offset; | |
13871 | unsigned long fpreg_mask; | |
13872 | unsigned long fpreg_offset; | |
13873 | unsigned long frame_offset; | |
13874 | unsigned long frame_reg; | |
13875 | unsigned long pc_reg; | |
13876 | } procS; | |
252b5132 RH |
13877 | |
13878 | static procS cur_proc; | |
13879 | static procS *cur_proc_ptr; | |
13880 | static int numprocs; | |
13881 | ||
0a9ef439 | 13882 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13883 | |
0a9ef439 | 13884 | void |
17a2f251 | 13885 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13886 | { |
0a9ef439 RH |
13887 | if (fragp->fr_type != rs_align_code) |
13888 | return; | |
13889 | ||
13890 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13891 | { |
13892 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13893 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13894 | ||
0a9ef439 RH |
13895 | int bytes; |
13896 | char *p; | |
a19d8eb0 | 13897 | |
0a9ef439 RH |
13898 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13899 | p = fragp->fr_literal + fragp->fr_fix; | |
13900 | ||
13901 | if (bytes & 1) | |
13902 | { | |
13903 | *p++ = 0; | |
f9419b05 | 13904 | fragp->fr_fix++; |
0a9ef439 RH |
13905 | } |
13906 | ||
13907 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13908 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13909 | } |
13910 | ||
0a9ef439 | 13911 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13912 | } |
13913 | ||
252b5132 | 13914 | static void |
17a2f251 | 13915 | md_obj_begin (void) |
252b5132 RH |
13916 | { |
13917 | } | |
13918 | ||
13919 | static void | |
17a2f251 | 13920 | md_obj_end (void) |
252b5132 RH |
13921 | { |
13922 | /* check for premature end, nesting errors, etc */ | |
13923 | if (cur_proc_ptr) | |
9a41af64 | 13924 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13925 | } |
13926 | ||
13927 | static long | |
17a2f251 | 13928 | get_number (void) |
252b5132 RH |
13929 | { |
13930 | int negative = 0; | |
13931 | long val = 0; | |
13932 | ||
13933 | if (*input_line_pointer == '-') | |
13934 | { | |
13935 | ++input_line_pointer; | |
13936 | negative = 1; | |
13937 | } | |
3882b010 | 13938 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13939 | as_bad (_("expected simple number")); |
252b5132 RH |
13940 | if (input_line_pointer[0] == '0') |
13941 | { | |
13942 | if (input_line_pointer[1] == 'x') | |
13943 | { | |
13944 | input_line_pointer += 2; | |
3882b010 | 13945 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13946 | { |
13947 | val <<= 4; | |
13948 | val |= hex_value (*input_line_pointer++); | |
13949 | } | |
13950 | return negative ? -val : val; | |
13951 | } | |
13952 | else | |
13953 | { | |
13954 | ++input_line_pointer; | |
3882b010 | 13955 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13956 | { |
13957 | val <<= 3; | |
13958 | val |= *input_line_pointer++ - '0'; | |
13959 | } | |
13960 | return negative ? -val : val; | |
13961 | } | |
13962 | } | |
3882b010 | 13963 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13964 | { |
13965 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13966 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13967 | as_warn (_("invalid number")); |
252b5132 RH |
13968 | return -1; |
13969 | } | |
3882b010 | 13970 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13971 | { |
13972 | val *= 10; | |
13973 | val += *input_line_pointer++ - '0'; | |
13974 | } | |
13975 | return negative ? -val : val; | |
13976 | } | |
13977 | ||
13978 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13979 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13980 | case .file implies DWARF-2. */ | |
13981 | ||
13982 | static void | |
17a2f251 | 13983 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13984 | { |
ecb4347a DJ |
13985 | static int first_file_directive = 0; |
13986 | ||
c5dd6aab DJ |
13987 | if (ECOFF_DEBUGGING) |
13988 | { | |
13989 | get_number (); | |
13990 | s_app_file (0); | |
13991 | } | |
13992 | else | |
ecb4347a DJ |
13993 | { |
13994 | char *filename; | |
13995 | ||
13996 | filename = dwarf2_directive_file (0); | |
13997 | ||
13998 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13999 | directive even for stabs output. Make sure that this | |
14000 | ".file" is handled. Note that you need a version of GCC | |
14001 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14002 | if (filename != NULL && ! first_file_directive) | |
14003 | { | |
14004 | (void) new_logical_line (filename, -1); | |
14005 | s_app_file_string (filename); | |
14006 | } | |
14007 | first_file_directive = 1; | |
14008 | } | |
c5dd6aab DJ |
14009 | } |
14010 | ||
14011 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14012 | |
14013 | static void | |
17a2f251 | 14014 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14015 | { |
c5dd6aab DJ |
14016 | if (!ECOFF_DEBUGGING) |
14017 | dwarf2_directive_loc (0); | |
252b5132 RH |
14018 | } |
14019 | ||
252b5132 RH |
14020 | /* The .end directive. */ |
14021 | ||
14022 | static void | |
17a2f251 | 14023 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14024 | { |
14025 | symbolS *p; | |
252b5132 | 14026 | |
7a621144 DJ |
14027 | /* Following functions need their own .frame and .cprestore directives. */ |
14028 | mips_frame_reg_valid = 0; | |
14029 | mips_cprestore_valid = 0; | |
14030 | ||
252b5132 RH |
14031 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14032 | { | |
14033 | p = get_symbol (); | |
14034 | demand_empty_rest_of_line (); | |
14035 | } | |
14036 | else | |
14037 | p = NULL; | |
14038 | ||
14949570 | 14039 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14040 | as_warn (_(".end not in text section")); |
14041 | ||
14042 | if (!cur_proc_ptr) | |
14043 | { | |
14044 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14045 | demand_empty_rest_of_line (); | |
14046 | return; | |
14047 | } | |
14048 | ||
14049 | if (p != NULL) | |
14050 | { | |
14051 | assert (S_GET_NAME (p)); | |
14052 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14053 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14054 | |
14055 | if (debug_type == DEBUG_STABS) | |
14056 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14057 | S_GET_NAME (p)); | |
252b5132 RH |
14058 | } |
14059 | else | |
14060 | as_warn (_(".end directive missing or unknown symbol")); | |
14061 | ||
ecb4347a DJ |
14062 | #ifdef OBJ_ELF |
14063 | /* Generate a .pdr section. */ | |
dcd410fe RO |
14064 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14065 | && mips_flag_pdr) | |
ecb4347a DJ |
14066 | { |
14067 | segT saved_seg = now_seg; | |
14068 | subsegT saved_subseg = now_subseg; | |
14069 | valueT dot; | |
14070 | expressionS exp; | |
14071 | char *fragp; | |
252b5132 | 14072 | |
ecb4347a | 14073 | dot = frag_now_fix (); |
252b5132 RH |
14074 | |
14075 | #ifdef md_flush_pending_output | |
ecb4347a | 14076 | md_flush_pending_output (); |
252b5132 RH |
14077 | #endif |
14078 | ||
ecb4347a DJ |
14079 | assert (pdr_seg); |
14080 | subseg_set (pdr_seg, 0); | |
252b5132 | 14081 | |
ecb4347a DJ |
14082 | /* Write the symbol. */ |
14083 | exp.X_op = O_symbol; | |
14084 | exp.X_add_symbol = p; | |
14085 | exp.X_add_number = 0; | |
14086 | emit_expr (&exp, 4); | |
252b5132 | 14087 | |
ecb4347a | 14088 | fragp = frag_more (7 * 4); |
252b5132 | 14089 | |
17a2f251 TS |
14090 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14091 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14092 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14093 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14094 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14095 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14096 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14097 | |
ecb4347a DJ |
14098 | subseg_set (saved_seg, saved_subseg); |
14099 | } | |
14100 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14101 | |
14102 | cur_proc_ptr = NULL; | |
14103 | } | |
14104 | ||
14105 | /* The .aent and .ent directives. */ | |
14106 | ||
14107 | static void | |
17a2f251 | 14108 | s_mips_ent (int aent) |
252b5132 | 14109 | { |
252b5132 | 14110 | symbolS *symbolP; |
252b5132 RH |
14111 | |
14112 | symbolP = get_symbol (); | |
14113 | if (*input_line_pointer == ',') | |
f9419b05 | 14114 | ++input_line_pointer; |
252b5132 | 14115 | SKIP_WHITESPACE (); |
3882b010 | 14116 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14117 | || *input_line_pointer == '-') |
874e8986 | 14118 | get_number (); |
252b5132 | 14119 | |
14949570 | 14120 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14121 | as_warn (_(".ent or .aent not in text section.")); |
14122 | ||
14123 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14124 | as_warn (_("missing .end")); |
252b5132 RH |
14125 | |
14126 | if (!aent) | |
14127 | { | |
7a621144 DJ |
14128 | /* This function needs its own .frame and .cprestore directives. */ |
14129 | mips_frame_reg_valid = 0; | |
14130 | mips_cprestore_valid = 0; | |
14131 | ||
252b5132 RH |
14132 | cur_proc_ptr = &cur_proc; |
14133 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14134 | ||
14135 | cur_proc_ptr->isym = symbolP; | |
14136 | ||
49309057 | 14137 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14138 | |
f9419b05 | 14139 | ++numprocs; |
ecb4347a DJ |
14140 | |
14141 | if (debug_type == DEBUG_STABS) | |
14142 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14143 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14144 | } |
14145 | ||
14146 | demand_empty_rest_of_line (); | |
14147 | } | |
14148 | ||
14149 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14150 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14151 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14152 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14153 | symbol table (in the mdebug section). */ |
14154 | ||
14155 | static void | |
17a2f251 | 14156 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14157 | { |
ecb4347a DJ |
14158 | #ifdef OBJ_ELF |
14159 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14160 | { | |
14161 | long val; | |
252b5132 | 14162 | |
ecb4347a DJ |
14163 | if (cur_proc_ptr == (procS *) NULL) |
14164 | { | |
14165 | as_warn (_(".frame outside of .ent")); | |
14166 | demand_empty_rest_of_line (); | |
14167 | return; | |
14168 | } | |
252b5132 | 14169 | |
ecb4347a DJ |
14170 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14171 | ||
14172 | SKIP_WHITESPACE (); | |
14173 | if (*input_line_pointer++ != ',' | |
14174 | || get_absolute_expression_and_terminator (&val) != ',') | |
14175 | { | |
14176 | as_warn (_("Bad .frame directive")); | |
14177 | --input_line_pointer; | |
14178 | demand_empty_rest_of_line (); | |
14179 | return; | |
14180 | } | |
252b5132 | 14181 | |
ecb4347a DJ |
14182 | cur_proc_ptr->frame_offset = val; |
14183 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14184 | |
252b5132 | 14185 | demand_empty_rest_of_line (); |
252b5132 | 14186 | } |
ecb4347a DJ |
14187 | else |
14188 | #endif /* OBJ_ELF */ | |
14189 | s_ignore (ignore); | |
252b5132 RH |
14190 | } |
14191 | ||
bdaaa2e1 KH |
14192 | /* The .fmask and .mask directives. If the mdebug section is present |
14193 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14194 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14195 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14196 | make reference to the ecoff symbol table (in the mdebug section). */ |
14197 | ||
14198 | static void | |
17a2f251 | 14199 | s_mips_mask (int reg_type) |
252b5132 | 14200 | { |
ecb4347a DJ |
14201 | #ifdef OBJ_ELF |
14202 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14203 | { |
ecb4347a | 14204 | long mask, off; |
252b5132 | 14205 | |
ecb4347a DJ |
14206 | if (cur_proc_ptr == (procS *) NULL) |
14207 | { | |
14208 | as_warn (_(".mask/.fmask outside of .ent")); | |
14209 | demand_empty_rest_of_line (); | |
14210 | return; | |
14211 | } | |
252b5132 | 14212 | |
ecb4347a DJ |
14213 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14214 | { | |
14215 | as_warn (_("Bad .mask/.fmask directive")); | |
14216 | --input_line_pointer; | |
14217 | demand_empty_rest_of_line (); | |
14218 | return; | |
14219 | } | |
252b5132 | 14220 | |
ecb4347a DJ |
14221 | off = get_absolute_expression (); |
14222 | ||
14223 | if (reg_type == 'F') | |
14224 | { | |
14225 | cur_proc_ptr->fpreg_mask = mask; | |
14226 | cur_proc_ptr->fpreg_offset = off; | |
14227 | } | |
14228 | else | |
14229 | { | |
14230 | cur_proc_ptr->reg_mask = mask; | |
14231 | cur_proc_ptr->reg_offset = off; | |
14232 | } | |
14233 | ||
14234 | demand_empty_rest_of_line (); | |
252b5132 RH |
14235 | } |
14236 | else | |
ecb4347a DJ |
14237 | #endif /* OBJ_ELF */ |
14238 | s_ignore (reg_type); | |
252b5132 RH |
14239 | } |
14240 | ||
14241 | /* The .loc directive. */ | |
14242 | ||
14243 | #if 0 | |
14244 | static void | |
17a2f251 | 14245 | s_loc (int x) |
252b5132 RH |
14246 | { |
14247 | symbolS *symbolP; | |
14248 | int lineno; | |
14249 | int addroff; | |
14250 | ||
14251 | assert (now_seg == text_section); | |
14252 | ||
14253 | lineno = get_number (); | |
14254 | addroff = frag_now_fix (); | |
14255 | ||
14256 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14257 | S_SET_TYPE (symbolP, N_SLINE); | |
14258 | S_SET_OTHER (symbolP, 0); | |
14259 | S_SET_DESC (symbolP, lineno); | |
14260 | symbolP->sy_segment = now_seg; | |
14261 | } | |
14262 | #endif | |
e7af610e | 14263 | |
316f5878 RS |
14264 | /* A table describing all the processors gas knows about. Names are |
14265 | matched in the order listed. | |
e7af610e | 14266 | |
316f5878 RS |
14267 | To ease comparison, please keep this table in the same order as |
14268 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14269 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14270 | { | |
316f5878 RS |
14271 | /* Entries for generic ISAs */ |
14272 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14273 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14274 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14275 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14276 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14277 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14278 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 RS |
14279 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
14280 | ||
14281 | /* MIPS I */ | |
14282 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14283 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14284 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14285 | ||
14286 | /* MIPS II */ | |
14287 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14288 | ||
14289 | /* MIPS III */ | |
14290 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14291 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14292 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14293 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14294 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14295 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14296 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14297 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14298 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14299 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14300 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14301 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14302 | ||
14303 | /* MIPS IV */ | |
14304 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14305 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14306 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14307 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14308 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14309 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14310 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14311 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14312 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14313 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14314 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
14315 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
14316 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
14317 | |
14318 | /* MIPS 32 */ | |
fef14a42 | 14319 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14320 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14321 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14322 | |
316f5878 RS |
14323 | /* MIPS 64 */ |
14324 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14325 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14326 | |
c7a23324 | 14327 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14328 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14329 | |
316f5878 RS |
14330 | /* End marker */ |
14331 | { NULL, 0, 0, 0 } | |
14332 | }; | |
e7af610e | 14333 | |
84ea6cf2 | 14334 | |
316f5878 RS |
14335 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14336 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14337 | |
316f5878 | 14338 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14339 | |
b34976b6 | 14340 | static bfd_boolean |
17a2f251 | 14341 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14342 | { |
14343 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14344 | given++, canonical++; | |
14345 | ||
14346 | return ((*given == 0 && *canonical == 0) | |
14347 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14348 | } | |
14349 | ||
14350 | ||
14351 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14352 | CPU name. We've traditionally allowed a lot of variation here. | |
14353 | ||
14354 | Note: this function is shared between GCC and GAS. */ | |
14355 | ||
b34976b6 | 14356 | static bfd_boolean |
17a2f251 | 14357 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14358 | { |
14359 | /* First see if the name matches exactly, or with a final "000" | |
14360 | turned into "k". */ | |
14361 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14362 | return TRUE; |
316f5878 RS |
14363 | |
14364 | /* If not, try comparing based on numerical designation alone. | |
14365 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14366 | if (TOLOWER (*given) == 'r') | |
14367 | given++; | |
14368 | if (!ISDIGIT (*given)) | |
b34976b6 | 14369 | return FALSE; |
316f5878 RS |
14370 | |
14371 | /* Skip over some well-known prefixes in the canonical name, | |
14372 | hoping to find a number there too. */ | |
14373 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14374 | canonical += 2; | |
14375 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14376 | canonical += 2; | |
14377 | else if (TOLOWER (canonical[0]) == 'r') | |
14378 | canonical += 1; | |
14379 | ||
14380 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14381 | } | |
14382 | ||
14383 | ||
14384 | /* Parse an option that takes the name of a processor as its argument. | |
14385 | OPTION is the name of the option and CPU_STRING is the argument. | |
14386 | Return the corresponding processor enumeration if the CPU_STRING is | |
14387 | recognized, otherwise report an error and return null. | |
14388 | ||
14389 | A similar function exists in GCC. */ | |
e7af610e NC |
14390 | |
14391 | static const struct mips_cpu_info * | |
17a2f251 | 14392 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14393 | { |
316f5878 | 14394 | const struct mips_cpu_info *p; |
e7af610e | 14395 | |
316f5878 RS |
14396 | /* 'from-abi' selects the most compatible architecture for the given |
14397 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14398 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14399 | version. Look first at the -mgp options, if given, otherwise base | |
14400 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14401 | |
316f5878 RS |
14402 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14403 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14404 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14405 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14406 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14407 | { | |
14408 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14409 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14410 | ||
14411 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14412 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14413 | ||
14414 | if (file_mips_gp32 >= 0) | |
14415 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14416 | ||
14417 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14418 | ? ISA_MIPS3 | |
14419 | : ISA_MIPS1); | |
14420 | } | |
14421 | ||
14422 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14423 | if (strcasecmp (cpu_string, "default") == 0) | |
14424 | return 0; | |
14425 | ||
14426 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14427 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14428 | return p; | |
14429 | ||
14430 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14431 | return 0; | |
e7af610e NC |
14432 | } |
14433 | ||
316f5878 RS |
14434 | /* Return the canonical processor information for ISA (a member of the |
14435 | ISA_MIPS* enumeration). */ | |
14436 | ||
e7af610e | 14437 | static const struct mips_cpu_info * |
17a2f251 | 14438 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14439 | { |
14440 | int i; | |
14441 | ||
14442 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14443 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14444 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14445 | return (&mips_cpu_info_table[i]); |
14446 | ||
e972090a | 14447 | return NULL; |
e7af610e | 14448 | } |
fef14a42 TS |
14449 | |
14450 | static const struct mips_cpu_info * | |
17a2f251 | 14451 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14452 | { |
14453 | int i; | |
14454 | ||
14455 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14456 | if (arch == mips_cpu_info_table[i].cpu) | |
14457 | return (&mips_cpu_info_table[i]); | |
14458 | ||
14459 | return NULL; | |
14460 | } | |
316f5878 RS |
14461 | \f |
14462 | static void | |
17a2f251 | 14463 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14464 | { |
14465 | if (*first_p) | |
14466 | { | |
14467 | fprintf (stream, "%24s", ""); | |
14468 | *col_p = 24; | |
14469 | } | |
14470 | else | |
14471 | { | |
14472 | fprintf (stream, ", "); | |
14473 | *col_p += 2; | |
14474 | } | |
e7af610e | 14475 | |
316f5878 RS |
14476 | if (*col_p + strlen (string) > 72) |
14477 | { | |
14478 | fprintf (stream, "\n%24s", ""); | |
14479 | *col_p = 24; | |
14480 | } | |
14481 | ||
14482 | fprintf (stream, "%s", string); | |
14483 | *col_p += strlen (string); | |
14484 | ||
14485 | *first_p = 0; | |
14486 | } | |
14487 | ||
14488 | void | |
17a2f251 | 14489 | md_show_usage (FILE *stream) |
e7af610e | 14490 | { |
316f5878 RS |
14491 | int column, first; |
14492 | size_t i; | |
14493 | ||
14494 | fprintf (stream, _("\ | |
14495 | MIPS options:\n\ | |
14496 | -membedded-pic generate embedded position independent code\n\ | |
14497 | -EB generate big endian output\n\ | |
14498 | -EL generate little endian output\n\ | |
14499 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14500 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14501 | implicitly with the gp register [default 8]\n")); | |
14502 | fprintf (stream, _("\ | |
14503 | -mips1 generate MIPS ISA I instructions\n\ | |
14504 | -mips2 generate MIPS ISA II instructions\n\ | |
14505 | -mips3 generate MIPS ISA III instructions\n\ | |
14506 | -mips4 generate MIPS ISA IV instructions\n\ | |
14507 | -mips5 generate MIPS ISA V instructions\n\ | |
14508 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14509 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 RS |
14510 | -mips64 generate MIPS64 ISA instructions\n\ |
14511 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14512 | ||
14513 | first = 1; | |
e7af610e NC |
14514 | |
14515 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14516 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14517 | show (stream, "from-abi", &column, &first); | |
14518 | fputc ('\n', stream); | |
e7af610e | 14519 | |
316f5878 RS |
14520 | fprintf (stream, _("\ |
14521 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14522 | -no-mCPU don't generate code specific to CPU.\n\ | |
14523 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14524 | ||
14525 | first = 1; | |
14526 | ||
14527 | show (stream, "3900", &column, &first); | |
14528 | show (stream, "4010", &column, &first); | |
14529 | show (stream, "4100", &column, &first); | |
14530 | show (stream, "4650", &column, &first); | |
14531 | fputc ('\n', stream); | |
14532 | ||
14533 | fprintf (stream, _("\ | |
14534 | -mips16 generate mips16 instructions\n\ | |
14535 | -no-mips16 do not generate mips16 instructions\n")); | |
14536 | fprintf (stream, _("\ | |
14537 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14538 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14539 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14540 | -O remove unneeded NOPs and swap branches\n\ | |
14541 | -n warn about NOPs generated from macros\n\ | |
14542 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14543 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14544 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14545 | #ifdef OBJ_ELF | |
14546 | fprintf (stream, _("\ | |
14547 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14548 | -non_shared do not generate position independent code\n\ | |
14549 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14550 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14551 | -mabi=ABI create ABI conformant object file for:\n")); |
14552 | ||
14553 | first = 1; | |
14554 | ||
14555 | show (stream, "32", &column, &first); | |
14556 | show (stream, "o64", &column, &first); | |
14557 | show (stream, "n32", &column, &first); | |
14558 | show (stream, "64", &column, &first); | |
14559 | show (stream, "eabi", &column, &first); | |
14560 | ||
14561 | fputc ('\n', stream); | |
14562 | ||
14563 | fprintf (stream, _("\ | |
14564 | -32 create o32 ABI object file (default)\n\ | |
14565 | -n32 create n32 ABI object file\n\ | |
14566 | -64 create 64 ABI object file\n")); | |
14567 | #endif | |
e7af610e | 14568 | } |
14e777e0 KB |
14569 | |
14570 | enum dwarf2_format | |
17a2f251 | 14571 | mips_dwarf2_format (void) |
14e777e0 KB |
14572 | { |
14573 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14574 | { |
14575 | #ifdef TE_IRIX | |
14576 | return dwarf2_format_64bit_irix; | |
14577 | #else | |
14578 | return dwarf2_format_64bit; | |
14579 | #endif | |
14580 | } | |
14e777e0 KB |
14581 | else |
14582 | return dwarf2_format_32bit; | |
14583 | } |