Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
276c2d7d GRK |
151 | /* start-sanitize-r5900 */ |
152 | /* Whether Toshiba r5900 instructions are permitted. */ | |
153 | static int mips_5900 = -1; | |
154 | /* end-sanitize-r5900 */ | |
155 | ||
e532b44c ILT |
156 | /* Whether the processor uses hardware interlocks, and thus does not |
157 | require nops to be inserted. */ | |
158 | static int interlocks = -1; | |
159 | ||
344a8d61 JSC |
160 | /* As with "interlocks" this is used by hardware that has FP |
161 | (co-processor) interlocks. */ | |
162 | static int cop_interlocks = -1; | |
163 | ||
d9aba805 ILT |
164 | /* MIPS PIC level. */ |
165 | ||
166 | enum mips_pic_level | |
167 | { | |
168 | /* Do not generate PIC code. */ | |
169 | NO_PIC, | |
170 | ||
171 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
172 | not sure what it is supposed to do. */ | |
173 | IRIX4_PIC, | |
174 | ||
175 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
176 | SVR4_PIC, | |
177 | ||
178 | /* Generate PIC code without using a global offset table: the data | |
179 | segment has a maximum size of 64K, all data references are off | |
180 | the $gp register, and all text references are PC relative. This | |
181 | is used on some embedded systems. */ | |
182 | EMBEDDED_PIC | |
183 | }; | |
184 | ||
185 | static enum mips_pic_level mips_pic; | |
9226253a | 186 | |
fb251650 ILT |
187 | /* 1 if we should generate 32 bit offsets from the GP register in |
188 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
189 | static int mips_big_got; | |
190 | ||
8ea7f4e8 ILT |
191 | /* 1 if trap instructions should used for overflow rather than break |
192 | instructions. */ | |
193 | static int mips_trap; | |
194 | ||
cc5703cd ILT |
195 | /* 1 if we should autoextend mips16 instructions. */ |
196 | static int mips16_autoextend = 1; | |
197 | ||
3d3c5039 ILT |
198 | static int mips_warn_about_macros; |
199 | static int mips_noreorder; | |
0dd2d296 | 200 | static int mips_any_noreorder; |
3d3c5039 ILT |
201 | static int mips_nomove; |
202 | static int mips_noat; | |
203 | static int mips_nobopt; | |
204 | ||
670a50eb ILT |
205 | /* The size of the small data section. */ |
206 | static int g_switch_value = 8; | |
42562568 ILT |
207 | /* Whether the -G option was used. */ |
208 | static int g_switch_seen = 0; | |
670a50eb | 209 | |
3d3c5039 ILT |
210 | #define N_RMASK 0xc4 |
211 | #define N_VFP 0xd4 | |
212 | ||
d8a1c247 KR |
213 | /* If we can determine in advance that GP optimization won't be |
214 | possible, we can skip the relaxation stuff that tries to produce | |
215 | GP-relative references. This makes delay slot optimization work | |
216 | better. | |
217 | ||
218 | This function can only provide a guess, but it seems to work for | |
219 | gcc output. If it guesses wrong, the only loss should be in | |
220 | efficiency; it shouldn't introduce any bugs. | |
221 | ||
222 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
223 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
224 | static int nopic_need_relax PARAMS ((symbolS *)); | |
225 | ||
3d3c5039 ILT |
226 | /* handle of the OPCODE hash table */ |
227 | static struct hash_control *op_hash = NULL; | |
228 | ||
cc5703cd ILT |
229 | /* The opcode hash table we use for the mips16. */ |
230 | static struct hash_control *mips16_op_hash = NULL; | |
231 | ||
3d3c5039 ILT |
232 | /* This array holds the chars that always start a comment. If the |
233 | pre-processor is disabled, these aren't very useful */ | |
234 | const char comment_chars[] = "#"; | |
235 | ||
236 | /* This array holds the chars that only start a comment at the beginning of | |
237 | a line. If the line seems to have the form '# 123 filename' | |
238 | .line and .file directives will appear in the pre-processed output */ | |
239 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
240 | first line of the input file. This is because the compiler outputs | |
241 | #NO_APP at the beginning of its output. */ | |
242 | /* Also note that C style comments are always supported. */ | |
243 | const char line_comment_chars[] = "#"; | |
244 | ||
245 | /* This array holds machine specific line separator characters. */ | |
246 | const char line_separator_chars[] = ""; | |
247 | ||
248 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
249 | const char EXP_CHARS[] = "eE"; | |
250 | ||
251 | /* Chars that mean this number is a floating point constant */ | |
252 | /* As in 0f12.456 */ | |
253 | /* or 0d1.2345e12 */ | |
254 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
255 | ||
256 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
257 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
258 | but nothing is ideal around here. | |
259 | */ | |
260 | ||
670a50eb | 261 | static char *insn_error; |
3d3c5039 | 262 | |
3d3c5039 | 263 | static int auto_align = 1; |
becfe05e | 264 | |
9226253a ILT |
265 | /* When outputting SVR4 PIC code, the assembler needs to know the |
266 | offset in the stack frame from which to restore the $gp register. | |
267 | This is set by the .cprestore pseudo-op, and saved in this | |
268 | variable. */ | |
0dd2d296 ILT |
269 | static offsetT mips_cprestore_offset = -1; |
270 | ||
271 | /* This is the register which holds the stack frame, as set by the | |
272 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
273 | static int mips_frame_reg = SP; | |
9226253a | 274 | |
becfe05e ILT |
275 | /* To output NOP instructions correctly, we need to keep information |
276 | about the previous two instructions. */ | |
277 | ||
0aa07269 ILT |
278 | /* Whether we are optimizing. The default value of 2 means to remove |
279 | unneeded NOPs and swap branch instructions when possible. A value | |
280 | of 1 means to not swap branches. A value of 0 means to always | |
281 | insert NOPs. */ | |
282 | static int mips_optimize = 2; | |
4e95866e | 283 | |
22ba90ce ILT |
284 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
285 | equivalent to seeing no -g option at all. */ | |
286 | static int mips_debug = 0; | |
287 | ||
becfe05e ILT |
288 | /* The previous instruction. */ |
289 | static struct mips_cl_insn prev_insn; | |
290 | ||
291 | /* The instruction before prev_insn. */ | |
292 | static struct mips_cl_insn prev_prev_insn; | |
293 | ||
294 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
295 | point the insn_mo field at this dummy integer. */ | |
296 | static const struct mips_opcode dummy_opcode = { 0 }; | |
297 | ||
298 | /* Non-zero if prev_insn is valid. */ | |
299 | static int prev_insn_valid; | |
300 | ||
301 | /* The frag for the previous instruction. */ | |
302 | static struct frag *prev_insn_frag; | |
303 | ||
304 | /* The offset into prev_insn_frag for the previous instruction. */ | |
305 | static long prev_insn_where; | |
306 | ||
a677feeb ILT |
307 | /* The reloc type for the previous instruction, if any. */ |
308 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
309 | ||
becfe05e ILT |
310 | /* The reloc for the previous instruction, if any. */ |
311 | static fixS *prev_insn_fixp; | |
312 | ||
313 | /* Non-zero if the previous instruction was in a delay slot. */ | |
314 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
315 | |
316 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
317 | static int prev_insn_unreordered; | |
318 | ||
cc5703cd ILT |
319 | /* Non-zero if the previous instruction uses an extend opcode (if |
320 | mips16). */ | |
321 | static int prev_insn_extended; | |
322 | ||
4e95866e ILT |
323 | /* Non-zero if the previous previous instruction was in a .set |
324 | noreorder. */ | |
325 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
326 | |
327 | /* For ECOFF and ELF, relocations against symbols are done in two | |
328 | parts, with a HI relocation and a LO relocation. Each relocation | |
329 | has only 16 bits of space to store an addend. This means that in | |
330 | order for the linker to handle carries correctly, it must be able | |
331 | to locate both the HI and the LO relocation. This means that the | |
332 | relocations must appear in order in the relocation table. | |
333 | ||
334 | In order to implement this, we keep track of each unmatched HI | |
335 | relocation. We then sort them so that they immediately precede the | |
336 | corresponding LO relocation. */ | |
337 | ||
338 | struct mips_hi_fixup | |
339 | { | |
340 | /* Next HI fixup. */ | |
341 | struct mips_hi_fixup *next; | |
342 | /* This fixup. */ | |
343 | fixS *fixp; | |
344 | /* The section this fixup is in. */ | |
345 | segT seg; | |
346 | }; | |
347 | ||
348 | /* The list of unmatched HI relocs. */ | |
349 | ||
350 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
351 | |
352 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
353 | ||
354 | #define X ILLEGAL_REG | |
355 | static const int mips32_to_16_reg_map[] = | |
356 | { | |
357 | X, X, 2, 3, 4, 5, 6, 7, | |
358 | X, X, X, X, X, X, X, X, | |
359 | 0, 1, X, X, X, X, X, X, | |
360 | X, X, X, X, X, X, X, X | |
361 | }; | |
362 | #undef X | |
363 | ||
364 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
365 | ||
366 | static const int mips16_to_32_reg_map[] = | |
367 | { | |
368 | 16, 17, 2, 3, 4, 5, 6, 7 | |
369 | }; | |
3d3c5039 | 370 | \f |
0dd2d296 ILT |
371 | /* Since the MIPS does not have multiple forms of PC relative |
372 | instructions, we do not have to do relaxing as is done on other | |
373 | platforms. However, we do have to handle GP relative addressing | |
374 | correctly, which turns out to be a similar problem. | |
375 | ||
376 | Every macro that refers to a symbol can occur in (at least) two | |
377 | forms, one with GP relative addressing and one without. For | |
378 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 379 | a macro instruction like this: |
0dd2d296 ILT |
380 | lw $4,i |
381 | If i can be addressed off the GP register (this is true if it is in | |
382 | the .sbss or .sdata section, or if it is known to be smaller than | |
383 | the -G argument) this will generate the following instruction: | |
384 | lw $4,i($gp) | |
385 | This instruction will use a GPREL reloc. If i can not be addressed | |
386 | off the GP register, the following instruction sequence will be used: | |
387 | lui $at,i | |
388 | lw $4,i($at) | |
389 | In this case the first instruction will have a HI16 reloc, and the | |
390 | second reloc will have a LO16 reloc. Both relocs will be against | |
391 | the symbol i. | |
392 | ||
393 | The issue here is that we may not know whether i is GP addressable | |
394 | until after we see the instruction that uses it. Therefore, we | |
395 | want to be able to choose the final instruction sequence only at | |
396 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 397 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
398 | end of assembly. |
399 | ||
400 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
401 | addressing in quite the same way, but the issue still arises as |
402 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
403 | |
404 | We handle these issues by actually generating both possible | |
405 | instruction sequences. The longer one is put in a frag_var with | |
406 | type rs_machine_dependent. We encode what to do with the frag in | |
407 | the subtype field. We encode (1) the number of existing bytes to | |
408 | replace, (2) the number of new bytes to use, (3) the offset from | |
409 | the start of the existing bytes to the first reloc we must generate | |
410 | (that is, the offset is applied from the start of the existing | |
411 | bytes after they are replaced by the new bytes, if any), (4) the | |
412 | offset from the start of the existing bytes to the second reloc, | |
413 | (5) whether a third reloc is needed (the third reloc is always four | |
414 | bytes after the second reloc), and (6) whether to warn if this | |
415 | variant is used (this is sometimes needed if .set nomacro or .set | |
416 | noat is in effect). All these numbers are reasonably small. | |
417 | ||
418 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
419 | ensure that delay slots are handled correctly. Fortunately, there |
420 | are a limited number of cases. When the second instruction | |
421 | sequence is generated, append_insn is directed to maintain the | |
422 | existing delay slot information, so it continues to apply to any | |
423 | code after the second instruction sequence. This means that the | |
424 | second instruction sequence must not impose any requirements not | |
425 | required by the first instruction sequence. | |
0dd2d296 ILT |
426 | |
427 | These variant frags are then handled in functions called by the | |
428 | machine independent code. md_estimate_size_before_relax returns | |
429 | the final size of the frag. md_convert_frag sets up the final form | |
430 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
431 | one if needed. */ | |
432 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
433 | ((relax_substateT) \ | |
cc5703cd | 434 | (((old) << 23) \ |
0dd2d296 ILT |
435 | | ((new) << 16) \ |
436 | | (((reloc1) + 64) << 9) \ | |
437 | | (((reloc2) + 64) << 2) \ | |
438 | | ((reloc3) ? (1 << 1) : 0) \ | |
439 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
440 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
441 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
442 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
443 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
444 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
445 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
446 | |
447 | /* For mips16 code, we use an entirely different form of relaxation. | |
448 | mips16 supports two versions of most instructions which take | |
449 | immediate values: a small one which takes some small value, and a | |
450 | larger one which takes a 16 bit value. Since branches also follow | |
451 | this pattern, relaxing these values is required. | |
452 | ||
453 | We can assemble both mips16 and normal MIPS code in a single | |
454 | object. Therefore, we need to support this type of relaxation at | |
455 | the same time that we support the relaxation described above. We | |
456 | use the high bit of the subtype field to distinguish these cases. | |
457 | ||
a677feeb ILT |
458 | The information we store for this type of relaxation is the |
459 | argument code found in the opcode file for this relocation, whether | |
460 | the user explicitly requested a small or extended form, and whether | |
461 | the relocation is in a jump or jal delay slot. That tells us the | |
462 | size of the value, and how it should be stored. We also store | |
463 | whether the fragment is considered to be extended or not. We also | |
464 | store whether this is known to be a branch to a different section, | |
465 | whether we have tried to relax this frag yet, and whether we have | |
466 | ever extended a PC relative fragment because of a shift count. */ | |
467 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
468 | (0x80000000 \ | |
469 | | ((type) & 0xff) \ | |
470 | | ((small) ? 0x100 : 0) \ | |
471 | | ((ext) ? 0x200 : 0) \ | |
472 | | ((dslot) ? 0x400 : 0) \ | |
473 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
474 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
475 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
476 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
477 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
478 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
479 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
480 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
481 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
482 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
483 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
484 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
485 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 486 | \f |
3d3c5039 ILT |
487 | /* Prototypes for static functions. */ |
488 | ||
489 | #ifdef __STDC__ | |
490 | #define internalError() \ | |
491 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
492 | #else | |
493 | #define internalError() as_fatal ("MIPS internal Error"); | |
494 | #endif | |
495 | ||
cc5703cd ILT |
496 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
497 | ||
becfe05e | 498 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 499 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 500 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
501 | static void append_insn PARAMS ((char *place, |
502 | struct mips_cl_insn * ip, | |
670a50eb | 503 | expressionS * p, |
867a58b3 ILT |
504 | bfd_reloc_code_real_type r, |
505 | boolean)); | |
becfe05e | 506 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 507 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 508 | #ifdef USE_STDARG |
0dd2d296 | 509 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
510 | const char *name, const char *fmt, |
511 | ...)); | |
c625fc23 JSC |
512 | #else |
513 | static void macro_build (); | |
514 | #endif | |
cc5703cd ILT |
515 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
516 | const char *, const char *, | |
517 | va_list)); | |
0dd2d296 ILT |
518 | static void macro_build_lui PARAMS ((char *place, int *counter, |
519 | expressionS * ep, int regnum)); | |
6e8dda9c | 520 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 521 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 522 | expressionS *)); |
d8a1c247 | 523 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 524 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 525 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 526 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
527 | #ifdef LOSING_COMPILER |
528 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
529 | #endif | |
670a50eb | 530 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 531 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
532 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
533 | boolean, boolean, unsigned long *, | |
534 | boolean *, unsigned short *)); | |
670a50eb ILT |
535 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
536 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 537 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 538 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
539 | static void s_align PARAMS ((int)); |
540 | static void s_change_sec PARAMS ((int)); | |
541 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 542 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 543 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
544 | static void s_option PARAMS ((int)); |
545 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
546 | static void s_abicalls PARAMS ((int)); |
547 | static void s_cpload PARAMS ((int)); | |
548 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
549 | static void s_gpword PARAMS ((int)); |
550 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
551 | static void md_obj_begin PARAMS ((void)); |
552 | static void md_obj_end PARAMS ((void)); | |
553 | static long get_number PARAMS ((void)); | |
554 | static void s_ent PARAMS ((int)); | |
555 | static void s_mipsend PARAMS ((int)); | |
556 | static void s_file PARAMS ((int)); | |
cc5703cd | 557 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
558 | \f |
559 | /* Pseudo-op table. | |
560 | ||
561 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
562 | should be defined here, but are currently unsupported: .alias, | |
563 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
564 | ||
565 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
566 | specific to the type of debugging information being generated, and | |
567 | should be defined by the object format: .aent, .begin, .bend, | |
568 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
569 | .vreg. | |
570 | ||
571 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
572 | not MIPS CPU specific, but are also not specific to the object file | |
573 | format. This file is probably the best place to define them, but | |
574 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
575 | .struct, .weakext. */ | |
576 | ||
739708fa | 577 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 578 | { |
670a50eb ILT |
579 | /* MIPS specific pseudo-ops. */ |
580 | {"option", s_option, 0}, | |
581 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
582 | {"rdata", s_change_sec, 'r'}, |
583 | {"sdata", s_change_sec, 's'}, | |
584 | {"livereg", s_ignore, 0}, | |
739708fa KR |
585 | {"abicalls", s_abicalls, 0}, |
586 | {"cpload", s_cpload, 0}, | |
587 | {"cprestore", s_cprestore, 0}, | |
588 | {"gpword", s_gpword, 0}, | |
589 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 590 | |
670a50eb | 591 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 592 | chips. */ |
739708fa | 593 | {"asciiz", stringer, 1}, |
670a50eb ILT |
594 | {"bss", s_change_sec, 'b'}, |
595 | {"err", s_err, 0}, | |
596 | {"half", s_cons, 1}, | |
52aa70b5 | 597 | {"dword", s_cons, 3}, |
3d3c5039 | 598 | |
670a50eb | 599 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 600 | here for one reason or another. */ |
670a50eb ILT |
601 | {"align", s_align, 0}, |
602 | {"byte", s_cons, 0}, | |
603 | {"data", s_change_sec, 'd'}, | |
becfe05e | 604 | {"double", s_float_cons, 'd'}, |
becfe05e | 605 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
606 | {"globl", s_mips_globl, 0}, |
607 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
608 | {"hword", s_cons, 1}, |
609 | {"int", s_cons, 2}, | |
610 | {"long", s_cons, 2}, | |
611 | {"octa", s_cons, 4}, | |
612 | {"quad", s_cons, 3}, | |
613 | {"short", s_cons, 1}, | |
614 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
615 | {"text", s_change_sec, 't'}, |
616 | {"word", s_cons, 2}, | |
739708fa KR |
617 | { 0 }, |
618 | }; | |
3d3c5039 | 619 | |
739708fa | 620 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 621 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 622 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 623 | {"aent", s_ent, 1}, |
9226253a | 624 | {"bgnb", s_ignore, 0}, |
670a50eb | 625 | {"end", s_mipsend, 0}, |
9226253a | 626 | {"endb", s_ignore, 0}, |
670a50eb ILT |
627 | {"ent", s_ent, 0}, |
628 | {"file", s_file, 0}, | |
629 | {"fmask", s_ignore, 'F'}, | |
630 | {"frame", s_ignore, 0}, | |
631 | {"loc", s_ignore, 0}, | |
632 | {"mask", s_ignore, 'R'}, | |
633 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
634 | { 0 }, |
635 | }; | |
61420a20 | 636 | |
739708fa KR |
637 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
638 | ||
639 | void | |
640 | mips_pop_insert () | |
641 | { | |
642 | pop_insert (mips_pseudo_table); | |
643 | if (! ECOFF_DEBUGGING) | |
644 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 645 | } |
3d3c5039 | 646 | \f |
fbcfacb7 ILT |
647 | /* Symbols labelling the current insn. */ |
648 | ||
649 | struct insn_label_list | |
650 | { | |
651 | struct insn_label_list *next; | |
652 | symbolS *label; | |
653 | }; | |
654 | ||
655 | static struct insn_label_list *insn_labels; | |
656 | static struct insn_label_list *free_insn_labels; | |
657 | ||
658 | static void mips_clear_insn_labels PARAMS ((void)); | |
659 | ||
660 | static inline void | |
661 | mips_clear_insn_labels () | |
662 | { | |
663 | register struct insn_label_list **pl; | |
664 | ||
665 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
666 | ; | |
667 | *pl = insn_labels; | |
668 | insn_labels = NULL; | |
669 | } | |
670 | \f | |
3d3c5039 ILT |
671 | static char *expr_end; |
672 | ||
867a58b3 ILT |
673 | /* Expressions which appear in instructions. These are set by |
674 | mips_ip. */ | |
675 | ||
3d3c5039 ILT |
676 | static expressionS imm_expr; |
677 | static expressionS offset_expr; | |
867a58b3 ILT |
678 | |
679 | /* Relocs associated with imm_expr and offset_expr. */ | |
680 | ||
3d3c5039 ILT |
681 | static bfd_reloc_code_real_type imm_reloc; |
682 | static bfd_reloc_code_real_type offset_reloc; | |
683 | ||
867a58b3 ILT |
684 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
685 | ||
686 | static boolean imm_unmatched_hi; | |
687 | ||
8728fa92 ILT |
688 | /* These are set by mips16_ip if an explicit extension is used. */ |
689 | ||
690 | static boolean mips16_small, mips16_ext; | |
691 | ||
3d3c5039 ILT |
692 | /* |
693 | * This function is called once, at assembler startup time. It should | |
694 | * set up all the tables, etc. that the MD part of the assembler will need. | |
695 | */ | |
696 | void | |
670a50eb | 697 | md_begin () |
3d3c5039 | 698 | { |
0dd2d296 | 699 | boolean ok = false; |
604633ae | 700 | register const char *retval = NULL; |
670a50eb | 701 | register unsigned int i = 0; |
3d3c5039 | 702 | |
8358c818 ILT |
703 | if (mips_isa == -1) |
704 | { | |
8c63448a ILT |
705 | const char *cpu; |
706 | char *a = NULL; | |
707 | ||
708 | cpu = TARGET_CPU; | |
709 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
710 | { | |
711 | a = xmalloc (sizeof TARGET_CPU); | |
712 | strcpy (a, TARGET_CPU); | |
713 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
714 | cpu = a; | |
715 | } | |
716 | ||
717 | if (strcmp (cpu, "mips") == 0) | |
718 | { | |
719 | mips_isa = 1; | |
4bb0cc41 ILT |
720 | if (mips_cpu == -1) |
721 | mips_cpu = 3000; | |
8c63448a ILT |
722 | } |
723 | else if (strcmp (cpu, "r6000") == 0 | |
724 | || strcmp (cpu, "mips2") == 0) | |
725 | { | |
726 | mips_isa = 2; | |
4bb0cc41 ILT |
727 | if (mips_cpu == -1) |
728 | mips_cpu = 6000; | |
8c63448a ILT |
729 | } |
730 | else if (strcmp (cpu, "mips64") == 0 | |
731 | || strcmp (cpu, "r4000") == 0 | |
732 | || strcmp (cpu, "mips3") == 0) | |
733 | { | |
734 | mips_isa = 3; | |
4bb0cc41 ILT |
735 | if (mips_cpu == -1) |
736 | mips_cpu = 4000; | |
8c63448a ILT |
737 | } |
738 | else if (strcmp (cpu, "r4400") == 0) | |
739 | { | |
740 | mips_isa = 3; | |
4bb0cc41 ILT |
741 | if (mips_cpu == -1) |
742 | mips_cpu = 4400; | |
8c63448a ILT |
743 | } |
744 | else if (strcmp (cpu, "mips64orion") == 0 | |
745 | || strcmp (cpu, "r4600") == 0) | |
746 | { | |
747 | mips_isa = 3; | |
4bb0cc41 ILT |
748 | if (mips_cpu == -1) |
749 | mips_cpu = 4600; | |
8c63448a | 750 | } |
b2b8c24e ILT |
751 | else if (strcmp (cpu, "r4650") == 0) |
752 | { | |
753 | mips_isa = 3; | |
754 | if (mips_cpu == -1) | |
755 | mips_cpu = 4650; | |
756 | if (mips_4650 == -1) | |
757 | mips_4650 = 1; | |
758 | } | |
c625fc23 JSC |
759 | else if (strcmp (cpu, "mips64vr4300") == 0) |
760 | { | |
761 | mips_isa = 3; | |
762 | if (mips_cpu == -1) | |
763 | mips_cpu = 4300; | |
764 | } | |
765 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
766 | { | |
767 | mips_isa = 3; | |
768 | if (mips_cpu == -1) | |
769 | mips_cpu = 4100; | |
770 | if (mips_4100 == -1) | |
771 | mips_4100 = 1; | |
772 | } | |
e532b44c ILT |
773 | else if (strcmp (cpu, "r4010") == 0) |
774 | { | |
775 | mips_isa = 2; | |
776 | if (mips_cpu == -1) | |
777 | mips_cpu = 4010; | |
778 | if (mips_4010 == -1) | |
779 | mips_4010 = 1; | |
780 | } | |
517078c1 ILT |
781 | else if (strcmp (cpu, "r5000") == 0 |
782 | || strcmp (cpu, "mips64vr5000") == 0) | |
783 | { | |
784 | mips_isa = 4; | |
785 | if (mips_cpu == -1) | |
786 | mips_cpu = 5000; | |
787 | } | |
276c2d7d GRK |
788 | /* start-sanitize-r5900 */ |
789 | else if (strcmp (cpu, "r5900") == 0 | |
790 | || strcmp (cpu, "mips64vr5900") == 0 | |
791 | || strcmp (cpu, "mips64vr5900el") == 0) | |
792 | { | |
793 | mips_isa = 3; | |
794 | if (mips_cpu == -1) | |
795 | mips_cpu = 5900; | |
796 | if (mips_5900 = -1) | |
797 | mips_5900 = 1; | |
798 | } | |
799 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
800 | else if (strcmp (cpu, "r8000") == 0 |
801 | || strcmp (cpu, "mips4") == 0) | |
802 | { | |
803 | mips_isa = 4; | |
804 | if (mips_cpu == -1) | |
805 | mips_cpu = 8000; | |
806 | } | |
807 | else if (strcmp (cpu, "r10000") == 0) | |
808 | { | |
809 | mips_isa = 4; | |
810 | if (mips_cpu == -1) | |
811 | mips_cpu = 10000; | |
812 | } | |
cc5703cd ILT |
813 | else if (strcmp (cpu, "mips16") == 0) |
814 | { | |
815 | mips_isa = 3; | |
816 | if (mips_cpu == -1) | |
817 | mips_cpu = 0; /* FIXME */ | |
818 | } | |
8358c818 | 819 | else |
8c63448a ILT |
820 | { |
821 | mips_isa = 1; | |
4bb0cc41 ILT |
822 | if (mips_cpu == -1) |
823 | mips_cpu = 3000; | |
8c63448a ILT |
824 | } |
825 | ||
826 | if (a != NULL) | |
827 | free (a); | |
8358c818 ILT |
828 | } |
829 | ||
cc5703cd ILT |
830 | if (mips16 < 0) |
831 | { | |
832 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
833 | mips16 = 1; | |
834 | else | |
835 | mips16 = 0; | |
836 | } | |
837 | ||
b2b8c24e ILT |
838 | if (mips_4650 < 0) |
839 | mips_4650 = 0; | |
840 | ||
e532b44c ILT |
841 | if (mips_4010 < 0) |
842 | mips_4010 = 0; | |
843 | ||
c625fc23 JSC |
844 | if (mips_4100 < 0) |
845 | mips_4100 = 0; | |
846 | ||
276c2d7d GRK |
847 | /* start-sanitize-r5900 */ |
848 | if (mips_5900 < 0) | |
849 | mips_5900 = 0; | |
850 | /* end-sanitize-r5900 */ | |
851 | ||
c36a90ef | 852 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
853 | interlocks = 1; |
854 | else | |
855 | interlocks = 0; | |
856 | ||
ca296aab | 857 | if (mips_cpu == 4300) |
344a8d61 JSC |
858 | cop_interlocks = 1; |
859 | else | |
860 | cop_interlocks = 0; | |
861 | ||
8ea7f4e8 ILT |
862 | if (mips_isa < 2 && mips_trap) |
863 | as_bad ("trap exception not supported at ISA 1"); | |
864 | ||
97f99d11 ILT |
865 | switch (mips_isa) |
866 | { | |
867 | case 1: | |
868 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
869 | break; | |
870 | case 2: | |
871 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
872 | break; | |
873 | case 3: | |
874 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
875 | break; | |
d8a1c247 KR |
876 | case 4: |
877 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
878 | break; | |
97f99d11 ILT |
879 | } |
880 | if (! ok) | |
881 | as_warn ("Could not set architecture and machine"); | |
882 | ||
1051c97f ILT |
883 | file_mips_isa = mips_isa; |
884 | ||
13fe1379 ILT |
885 | op_hash = hash_new (); |
886 | ||
670a50eb ILT |
887 | for (i = 0; i < NUMOPCODES;) |
888 | { | |
889 | const char *name = mips_opcodes[i].name; | |
890 | ||
604633ae | 891 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 892 | if (retval != NULL) |
670a50eb ILT |
893 | { |
894 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
895 | mips_opcodes[i].name, retval); | |
896 | as_fatal ("Broken assembler. No assembly attempted."); | |
897 | } | |
898 | do | |
899 | { | |
8358c818 ILT |
900 | if (mips_opcodes[i].pinfo != INSN_MACRO |
901 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
902 | != mips_opcodes[i].match)) | |
670a50eb ILT |
903 | { |
904 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
905 | mips_opcodes[i].name, mips_opcodes[i].args); | |
906 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 907 | } |
670a50eb ILT |
908 | ++i; |
909 | } | |
910 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
911 | } |
912 | ||
cc5703cd ILT |
913 | mips16_op_hash = hash_new (); |
914 | ||
915 | i = 0; | |
916 | while (i < bfd_mips16_num_opcodes) | |
917 | { | |
918 | const char *name = mips16_opcodes[i].name; | |
919 | ||
920 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
921 | if (retval != NULL) | |
922 | as_fatal ("internal error: can't hash `%s': %s\n", | |
923 | mips16_opcodes[i].name, retval); | |
924 | do | |
925 | { | |
926 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
927 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
928 | != mips16_opcodes[i].match)) | |
929 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
930 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
931 | ++i; | |
932 | } | |
933 | while (i < bfd_mips16_num_opcodes | |
934 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
935 | } | |
936 | ||
becfe05e ILT |
937 | mips_no_prev_insn (); |
938 | ||
1aa6938e ILT |
939 | mips_gprmask = 0; |
940 | mips_cprmask[0] = 0; | |
941 | mips_cprmask[1] = 0; | |
942 | mips_cprmask[2] = 0; | |
943 | mips_cprmask[3] = 0; | |
944 | ||
8358c818 | 945 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 946 | record_alignment (text_section, 2); |
8358c818 | 947 | |
1dc1e798 KR |
948 | if (USE_GLOBAL_POINTER_OPT) |
949 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 950 | |
1dc1e798 KR |
951 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
952 | { | |
08e17202 ILT |
953 | /* On a native system, sections must be aligned to 16 byte |
954 | boundaries. When configured for an embedded ELF target, we | |
955 | don't bother. */ | |
956 | if (strcmp (TARGET_OS, "elf") != 0) | |
957 | { | |
958 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
959 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
960 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
961 | } | |
1dc1e798 KR |
962 | |
963 | /* Create a .reginfo section for register masks and a .mdebug | |
964 | section for debugging information. */ | |
965 | { | |
966 | segT seg; | |
967 | subsegT subseg; | |
b3a64736 | 968 | flagword flags; |
1dc1e798 KR |
969 | segT sec; |
970 | ||
971 | seg = now_seg; | |
972 | subseg = now_subseg; | |
1dc1e798 | 973 | |
b3a64736 ILT |
974 | /* The ABI says this section should be loaded so that the |
975 | running program can access it. However, we don't load it | |
976 | if we are configured for an embedded target */ | |
977 | flags = SEC_READONLY | SEC_DATA; | |
978 | if (strcmp (TARGET_OS, "elf") != 0) | |
979 | flags |= SEC_ALLOC | SEC_LOAD; | |
980 | ||
87178180 ILT |
981 | if (! mips_64) |
982 | { | |
983 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 984 | |
b3a64736 ILT |
985 | |
986 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
987 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
988 | ||
f2a663d3 | 989 | #ifdef OBJ_ELF |
87178180 | 990 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 991 | #endif |
87178180 ILT |
992 | } |
993 | else | |
994 | { | |
995 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
996 | .reginfo section. */ | |
997 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 998 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
999 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1000 | ||
1001 | #ifdef OBJ_ELF | |
1002 | /* Set up the option header. */ | |
1003 | { | |
1004 | Elf_Internal_Options opthdr; | |
1005 | char *f; | |
1006 | ||
1007 | opthdr.kind = ODK_REGINFO; | |
1008 | opthdr.size = (sizeof (Elf_External_Options) | |
1009 | + sizeof (Elf64_External_RegInfo)); | |
1010 | opthdr.section = 0; | |
1011 | opthdr.info = 0; | |
1012 | f = frag_more (sizeof (Elf_External_Options)); | |
1013 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1014 | (Elf_External_Options *) f); | |
1015 | ||
1016 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1017 | } | |
1018 | #endif | |
1019 | } | |
f2a663d3 | 1020 | |
739708fa KR |
1021 | if (ECOFF_DEBUGGING) |
1022 | { | |
1023 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1024 | (void) bfd_set_section_flags (stdoutput, sec, | |
1025 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1026 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1027 | } | |
0dd2d296 | 1028 | |
1dc1e798 KR |
1029 | subseg_set (seg, subseg); |
1030 | } | |
1031 | } | |
f2a663d3 | 1032 | |
739708fa KR |
1033 | if (! ECOFF_DEBUGGING) |
1034 | md_obj_begin (); | |
3d3c5039 ILT |
1035 | } |
1036 | ||
1037 | void | |
13fe1379 | 1038 | md_mips_end () |
3d3c5039 | 1039 | { |
739708fa KR |
1040 | if (! ECOFF_DEBUGGING) |
1041 | md_obj_end (); | |
3d3c5039 ILT |
1042 | } |
1043 | ||
1044 | void | |
670a50eb ILT |
1045 | md_assemble (str) |
1046 | char *str; | |
3d3c5039 | 1047 | { |
670a50eb | 1048 | struct mips_cl_insn insn; |
3d3c5039 | 1049 | |
5ac34ac3 | 1050 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1051 | imm_reloc = BFD_RELOC_UNUSED; |
1052 | imm_unmatched_hi = false; | |
5ac34ac3 | 1053 | offset_expr.X_op = O_absent; |
867a58b3 | 1054 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1055 | |
cc5703cd ILT |
1056 | if (mips16) |
1057 | mips16_ip (str, &insn); | |
1058 | else | |
1059 | mips_ip (str, &insn); | |
1060 | ||
670a50eb ILT |
1061 | if (insn_error) |
1062 | { | |
1063 | as_bad ("%s `%s'", insn_error, str); | |
1064 | return; | |
1065 | } | |
cc5703cd | 1066 | |
670a50eb ILT |
1067 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1068 | { | |
cc5703cd ILT |
1069 | if (mips16) |
1070 | mips16_macro (&insn); | |
1071 | else | |
1072 | macro (&insn); | |
3d3c5039 | 1073 | } |
670a50eb ILT |
1074 | else |
1075 | { | |
5ac34ac3 | 1076 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1077 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1078 | imm_unmatched_hi); | |
5ac34ac3 | 1079 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1080 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1081 | else |
867a58b3 | 1082 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1083 | } |
1084 | } | |
1085 | ||
cc5703cd ILT |
1086 | /* See whether instruction IP reads register REG. CLASS is the type |
1087 | of register. */ | |
becfe05e ILT |
1088 | |
1089 | static int | |
cc5703cd | 1090 | insn_uses_reg (ip, reg, class) |
becfe05e | 1091 | struct mips_cl_insn *ip; |
604633ae | 1092 | unsigned int reg; |
cc5703cd | 1093 | enum mips_regclass class; |
becfe05e | 1094 | { |
cc5703cd ILT |
1095 | if (class == MIPS16_REG) |
1096 | { | |
1097 | assert (mips16); | |
1098 | reg = mips16_to_32_reg_map[reg]; | |
1099 | class = MIPS_GR_REG; | |
1100 | } | |
1101 | ||
becfe05e | 1102 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1103 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1104 | return 0; |
1105 | ||
cc5703cd | 1106 | if (class == MIPS_FP_REG) |
becfe05e | 1107 | { |
cc5703cd | 1108 | assert (! mips16); |
becfe05e ILT |
1109 | /* If we are called with either $f0 or $f1, we must check $f0. |
1110 | This is not optimal, because it will introduce an unnecessary | |
1111 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1112 | need to distinguish reading both $f0 and $f1 or just one of | |
1113 | them. Note that we don't have to check the other way, | |
1114 | because there is no instruction that sets both $f0 and $f1 | |
1115 | and requires a delay. */ | |
1116 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1117 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1118 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1119 | return 1; |
1120 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1121 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1122 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1123 | return 1; |
1124 | } | |
cc5703cd | 1125 | else if (! mips16) |
becfe05e ILT |
1126 | { |
1127 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1128 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1129 | return 1; | |
1130 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1131 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1132 | return 1; | |
1133 | } | |
cc5703cd ILT |
1134 | else |
1135 | { | |
1136 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1137 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1138 | return 1; | |
1139 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1140 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1141 | return 1; | |
1142 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1143 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1144 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1145 | return 1; | |
1146 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1147 | return 1; | |
1148 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1149 | return 1; | |
1150 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1151 | return 1; | |
1152 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1153 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1154 | & MIPS16OP_MASK_REGR32) == reg) | |
1155 | return 1; | |
1156 | } | |
becfe05e ILT |
1157 | |
1158 | return 0; | |
1159 | } | |
1160 | ||
fb251650 ILT |
1161 | /* This function returns true if modifying a register requires a |
1162 | delay. */ | |
1163 | ||
1164 | static int | |
1165 | reg_needs_delay (reg) | |
1166 | int reg; | |
1167 | { | |
1168 | unsigned long prev_pinfo; | |
1169 | ||
1170 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1171 | if (! mips_noreorder | |
1172 | && mips_isa < 4 | |
1173 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1174 | || (mips_isa < 2 | |
1175 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1176 | { | |
1177 | /* A load from a coprocessor or from memory. All load | |
1178 | delays delay the use of general register rt for one | |
1179 | instruction on the r3000. The r6000 and r4000 use | |
1180 | interlocks. */ | |
1181 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1182 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1183 | return 1; | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
0dd2d296 ILT |
1189 | /* Output an instruction. PLACE is where to put the instruction; if |
1190 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1191 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1192 | used with RELOC_TYPE. */ | |
3d3c5039 | 1193 | |
3d3c5039 | 1194 | static void |
867a58b3 | 1195 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1196 | char *place; |
670a50eb ILT |
1197 | struct mips_cl_insn *ip; |
1198 | expressionS *address_expr; | |
1199 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1200 | boolean unmatched_hi; |
3d3c5039 | 1201 | { |
1aa6938e | 1202 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1203 | char *f; |
becfe05e ILT |
1204 | fixS *fixp; |
1205 | int nops = 0; | |
3d3c5039 | 1206 | |
fbcfacb7 ILT |
1207 | /* Mark instruction labels in mips16 mode. This permits the linker |
1208 | to handle them specially, such as generating jalx instructions | |
1209 | when needed. We also make them odd for the duration of the | |
1210 | assembly, in order to generate the right sort of code. We will | |
1211 | make them even in the adjust_symtab routine, while leaving them | |
1212 | marked. This is convenient for the debugger and the | |
1213 | disassembler. The linker knows to make them odd again. */ | |
1214 | if (mips16) | |
1215 | { | |
1216 | struct insn_label_list *l; | |
1217 | ||
1218 | for (l = insn_labels; l != NULL; l = l->next) | |
1219 | { | |
1220 | #ifdef S_SET_OTHER | |
1221 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1222 | S_SET_OTHER (l->label, STO_MIPS16); | |
1223 | #endif | |
1224 | ++l->label->sy_value.X_add_number; | |
1225 | } | |
1226 | } | |
1227 | ||
1aa6938e ILT |
1228 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1229 | pinfo = ip->insn_mo->pinfo; | |
1230 | ||
0dd2d296 | 1231 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1232 | { |
1233 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1234 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1235 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1236 | (1) a load from memory delay |
1237 | (2) a load from a coprocessor delay | |
1238 | (3) an unconditional branch delay | |
1239 | (4) a conditional branch delay | |
1240 | (5) a move to coprocessor register delay | |
1241 | (6) a load coprocessor register from memory delay | |
1242 | (7) a coprocessor condition code delay | |
1243 | (8) a HI/LO special register delay | |
becfe05e ILT |
1244 | |
1245 | There are a lot of optimizations we could do that we don't. | |
1246 | In particular, we do not, in general, reorder instructions. | |
1247 | If you use gcc with optimization, it will reorder | |
1248 | instructions and generally do much more optimization then we | |
1249 | do here; repeating all that work in the assembler would only | |
1250 | benefit hand written assembly code, and does not seem worth | |
1251 | it. */ | |
1252 | ||
1253 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1254 | #define emit_nop() \ |
1255 | (mips16 \ | |
1256 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1257 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1258 | |
1259 | /* The previous insn might require a delay slot, depending upon | |
1260 | the contents of the current insn. */ | |
cc5703cd ILT |
1261 | if (! mips16 |
1262 | && mips_isa < 4 | |
5af96dce ILT |
1263 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1264 | && ! cop_interlocks) | |
d8a1c247 KR |
1265 | || (mips_isa < 2 |
1266 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1267 | { |
1268 | /* A load from a coprocessor or from memory. All load | |
1269 | delays delay the use of general register rt for one | |
1270 | instruction on the r3000. The r6000 and r4000 use | |
1271 | interlocks. */ | |
1aa6938e | 1272 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1273 | if (mips_optimize == 0 |
1274 | || insn_uses_reg (ip, | |
1275 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1276 | & OP_MASK_RT), | |
cc5703cd | 1277 | MIPS_GR_REG)) |
becfe05e ILT |
1278 | ++nops; |
1279 | } | |
cc5703cd ILT |
1280 | else if (! mips16 |
1281 | && mips_isa < 4 | |
5af96dce ILT |
1282 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1283 | && ! cop_interlocks) | |
d8a1c247 KR |
1284 | || (mips_isa < 2 |
1285 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1286 | { |
1287 | /* A generic coprocessor delay. The previous instruction | |
1288 | modified a coprocessor general or control register. If | |
1289 | it modified a control register, we need to avoid any | |
1290 | coprocessor instruction (this is probably not always | |
1291 | required, but it sometimes is). If it modified a general | |
1292 | register, we avoid using that register. | |
1293 | ||
8358c818 ILT |
1294 | On the r6000 and r4000 loading a coprocessor register |
1295 | from memory is interlocked, and does not require a delay. | |
1296 | ||
becfe05e ILT |
1297 | This case is not handled very well. There is no special |
1298 | knowledge of CP0 handling, and the coprocessors other | |
1299 | than the floating point unit are not distinguished at | |
1300 | all. */ | |
1aa6938e | 1301 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1302 | { |
0aa07269 ILT |
1303 | if (mips_optimize == 0 |
1304 | || insn_uses_reg (ip, | |
8358c818 ILT |
1305 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1306 | & OP_MASK_FT), | |
cc5703cd | 1307 | MIPS_FP_REG)) |
becfe05e ILT |
1308 | ++nops; |
1309 | } | |
1aa6938e | 1310 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1311 | { |
0aa07269 ILT |
1312 | if (mips_optimize == 0 |
1313 | || insn_uses_reg (ip, | |
8358c818 ILT |
1314 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1315 | & OP_MASK_FS), | |
cc5703cd | 1316 | MIPS_FP_REG)) |
becfe05e ILT |
1317 | ++nops; |
1318 | } | |
1319 | else | |
1320 | { | |
1321 | /* We don't know exactly what the previous instruction | |
1322 | does. If the current instruction uses a coprocessor | |
1323 | register, we must insert a NOP. If previous | |
1324 | instruction may set the condition codes, and the | |
1325 | current instruction uses them, we must insert two | |
1326 | NOPS. */ | |
0aa07269 | 1327 | if (mips_optimize == 0 |
1aa6938e ILT |
1328 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1329 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1330 | nops += 2; |
1aa6938e | 1331 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1332 | ++nops; |
1333 | } | |
1334 | } | |
cc5703cd ILT |
1335 | else if (! mips16 |
1336 | && mips_isa < 4 | |
344a8d61 JSC |
1337 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1338 | && ! cop_interlocks) | |
becfe05e ILT |
1339 | { |
1340 | /* The previous instruction sets the coprocessor condition | |
1341 | codes, but does not require a general coprocessor delay | |
1342 | (this means it is a floating point comparison | |
1343 | instruction). If this instruction uses the condition | |
1344 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1345 | if (mips_optimize == 0 |
1aa6938e | 1346 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1347 | ++nops; |
1348 | } | |
1aa6938e | 1349 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1350 | { |
1351 | /* The previous instruction reads the LO register; if the | |
1352 | current instruction writes to the LO register, we must | |
517078c1 | 1353 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1354 | if (! interlocks |
b2b8c24e ILT |
1355 | && (mips_optimize == 0 |
1356 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1357 | nops += 2; |
1358 | } | |
1359 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1360 | { | |
1361 | /* The previous instruction reads the HI register; if the | |
1362 | current instruction writes to the HI register, we must | |
517078c1 | 1363 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1364 | if (! interlocks |
b2b8c24e ILT |
1365 | && (mips_optimize == 0 |
1366 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1367 | nops += 2; |
1368 | } | |
1369 | ||
1370 | /* There are two cases which require two intervening | |
1371 | instructions: 1) setting the condition codes using a move to | |
1372 | coprocessor instruction which requires a general coprocessor | |
1373 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1374 | or LO register and then writing to it (except on processors |
1375 | which have interlocks). If we are not already emitting a NOP | |
1376 | instruction, we must check for these cases compared to the | |
1377 | instruction previous to the previous instruction. */ | |
becfe05e | 1378 | if (nops == 0 |
cc5703cd ILT |
1379 | && ((! mips16 |
1380 | && mips_isa < 4 | |
d8a1c247 | 1381 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1382 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1383 | && (pinfo & INSN_READ_COND_CODE) |
1384 | && ! cop_interlocks) | |
becfe05e | 1385 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1386 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1387 | && ! interlocks) |
becfe05e | 1388 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1389 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1390 | && ! interlocks))) |
becfe05e ILT |
1391 | ++nops; |
1392 | ||
0dd2d296 ILT |
1393 | /* If we are being given a nop instruction, don't bother with |
1394 | one of the nops we would otherwise output. This will only | |
1395 | happen when a nop instruction is used with mips_optimize set | |
1396 | to 0. */ | |
cc5703cd | 1397 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1398 | --nops; |
1399 | ||
becfe05e ILT |
1400 | /* Now emit the right number of NOP instructions. */ |
1401 | if (nops > 0) | |
1402 | { | |
5af96dce ILT |
1403 | fragS *old_frag; |
1404 | unsigned long old_frag_offset; | |
8c63448a | 1405 | int i; |
fbcfacb7 | 1406 | struct insn_label_list *l; |
8c63448a | 1407 | |
5af96dce ILT |
1408 | old_frag = frag_now; |
1409 | old_frag_offset = frag_now_fix (); | |
1410 | ||
8c63448a | 1411 | for (i = 0; i < nops; i++) |
becfe05e | 1412 | emit_nop (); |
5af96dce | 1413 | |
af255ca0 | 1414 | if (listing) |
546f5536 ILT |
1415 | { |
1416 | listing_prev_line (); | |
1417 | /* We may be at the start of a variant frag. In case we | |
1418 | are, make sure there is enough space for the frag | |
1419 | after the frags created by listing_prev_line. The | |
1420 | argument to frag_grow here must be at least as large | |
1421 | as the argument to all other calls to frag_grow in | |
1422 | this file. We don't have to worry about being in the | |
1423 | middle of a variant frag, because the variants insert | |
1424 | all needed nop instructions themselves. */ | |
1425 | frag_grow (40); | |
1426 | } | |
5af96dce | 1427 | |
fbcfacb7 | 1428 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1429 | { |
fbcfacb7 ILT |
1430 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1431 | l->label->sy_frag = frag_now; | |
1432 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1433 | /* mips16 text labels are stored as odd. */ | |
1434 | if (mips16) | |
1435 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1436 | } |
5af96dce ILT |
1437 | |
1438 | #ifndef NO_ECOFF_DEBUGGING | |
1439 | if (ECOFF_DEBUGGING) | |
1440 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1441 | #endif | |
becfe05e ILT |
1442 | } |
1443 | } | |
1444 | ||
cc5703cd ILT |
1445 | if (reloc_type > BFD_RELOC_UNUSED) |
1446 | { | |
1447 | /* We need to set up a variant frag. */ | |
1448 | assert (mips16 && address_expr != NULL); | |
1449 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1450 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1451 | mips16_small, mips16_ext, |
1452 | (prev_pinfo | |
1453 | & INSN_UNCOND_BRANCH_DELAY), | |
1454 | (prev_insn_reloc_type | |
1455 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1456 | make_expr_symbol (address_expr), (long) 0, |
1457 | (char *) NULL); | |
1458 | } | |
1459 | else if (place != NULL) | |
0dd2d296 | 1460 | f = place; |
cc5703cd | 1461 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1462 | { |
1463 | /* Make sure there is enough room to swap this instruction with | |
1464 | a following jump instruction. */ | |
1465 | frag_grow (6); | |
1466 | f = frag_more (2); | |
1467 | } | |
cc5703cd ILT |
1468 | else |
1469 | f = frag_more (4); | |
becfe05e | 1470 | fixp = NULL; |
cc5703cd | 1471 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1472 | { |
5ac34ac3 | 1473 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1474 | { |
1475 | switch (reloc_type) | |
1476 | { | |
3d3c5039 | 1477 | case BFD_RELOC_32: |
670a50eb ILT |
1478 | ip->insn_opcode |= address_expr->X_add_number; |
1479 | break; | |
3d3c5039 ILT |
1480 | |
1481 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1482 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1483 | break; | |
3d3c5039 ILT |
1484 | |
1485 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1486 | if ((address_expr->X_add_number & 3) != 0) |
1487 | as_bad ("jump to misaligned address (0x%lx)", | |
1488 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1489 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1490 | break; | |
1491 | ||
cc5703cd | 1492 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1493 | if ((address_expr->X_add_number & 3) != 0) |
1494 | as_bad ("jump to misaligned address (0x%lx)", | |
1495 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1496 | ip->insn_opcode |= |
1497 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1498 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1499 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1500 | break; | |
1501 | ||
3d3c5039 | 1502 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1503 | goto need_reloc; |
3d3c5039 ILT |
1504 | |
1505 | default: | |
670a50eb | 1506 | internalError (); |
3d3c5039 | 1507 | } |
670a50eb ILT |
1508 | } |
1509 | else | |
1510 | { | |
3d3c5039 | 1511 | need_reloc: |
0dd2d296 ILT |
1512 | /* Don't generate a reloc if we are writing into a variant |
1513 | frag. */ | |
1514 | if (place == NULL) | |
867a58b3 ILT |
1515 | { |
1516 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1517 | address_expr, | |
1518 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1519 | reloc_type); | |
1520 | if (unmatched_hi) | |
1521 | { | |
1522 | struct mips_hi_fixup *hi_fixup; | |
1523 | ||
1524 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1525 | hi_fixup = ((struct mips_hi_fixup *) | |
1526 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1527 | hi_fixup->fixp = fixp; | |
1528 | hi_fixup->seg = now_seg; | |
1529 | hi_fixup->next = mips_hi_fixup_list; | |
1530 | mips_hi_fixup_list = hi_fixup; | |
1531 | } | |
1532 | } | |
3d3c5039 ILT |
1533 | } |
1534 | } | |
becfe05e | 1535 | |
cc5703cd ILT |
1536 | if (! mips16 || reloc_type == BFD_RELOC_MIPS16_JMP) |
1537 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1538 | else | |
1539 | { | |
1540 | if (ip->use_extend) | |
1541 | { | |
1542 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1543 | f += 2; | |
1544 | } | |
1545 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1546 | } | |
670a50eb | 1547 | |
1aa6938e | 1548 | /* Update the register mask information. */ |
cc5703cd ILT |
1549 | if (! mips16) |
1550 | { | |
1551 | if (pinfo & INSN_WRITE_GPR_D) | |
1552 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1553 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1554 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1555 | if (pinfo & INSN_READ_GPR_S) | |
1556 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1557 | if (pinfo & INSN_WRITE_GPR_31) | |
1558 | mips_gprmask |= 1 << 31; | |
1559 | if (pinfo & INSN_WRITE_FPR_D) | |
1560 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1561 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1562 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1563 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1564 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1565 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1566 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1567 | if (pinfo & INSN_COP) | |
1568 | { | |
1569 | /* We don't keep enough information to sort these cases out. */ | |
1570 | } | |
1571 | /* Never set the bit for $0, which is always zero. */ | |
1572 | mips_gprmask &=~ 1 << 0; | |
1573 | } | |
1574 | else | |
1aa6938e | 1575 | { |
cc5703cd ILT |
1576 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1577 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1578 | & MIPS16OP_MASK_RX); | |
1579 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1580 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1581 | & MIPS16OP_MASK_RY); | |
1582 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1583 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1584 | & MIPS16OP_MASK_RZ); | |
1585 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1586 | mips_gprmask |= 1 << TREG; | |
1587 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1588 | mips_gprmask |= 1 << SP; | |
1589 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1590 | mips_gprmask |= 1 << RA; | |
1591 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1592 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1593 | if (pinfo & MIPS16_INSN_READ_Z) | |
1594 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1595 | & MIPS16OP_MASK_MOVE32Z); | |
1596 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1597 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1598 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1599 | } |
1aa6938e | 1600 | |
0dd2d296 | 1601 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1602 | { |
becfe05e ILT |
1603 | /* Filling the branch delay slot is more complex. We try to |
1604 | switch the branch with the previous instruction, which we can | |
1605 | do if the previous instruction does not set up a condition | |
1606 | that the branch tests and if the branch is not itself the | |
1607 | target of any branch. */ | |
1aa6938e ILT |
1608 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1609 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1610 | { |
0aa07269 | 1611 | if (mips_optimize < 2 |
19ed8960 ILT |
1612 | /* If we have seen .set volatile or .set nomove, don't |
1613 | optimize. */ | |
1614 | || mips_nomove != 0 | |
4e95866e ILT |
1615 | /* If we had to emit any NOP instructions, then we |
1616 | already know we can not swap. */ | |
1617 | || nops != 0 | |
becfe05e ILT |
1618 | /* If we don't even know the previous insn, we can not |
1619 | swap. */ | |
1620 | || ! prev_insn_valid | |
1621 | /* If the previous insn is already in a branch delay | |
1622 | slot, then we can not swap. */ | |
1623 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1624 | /* If the previous previous insn was in a .set |
1625 | noreorder, we can't swap. Actually, the MIPS | |
1626 | assembler will swap in this situation. However, gcc | |
1627 | configured -with-gnu-as will generate code like | |
1628 | .set noreorder | |
1629 | lw $4,XXX | |
1630 | .set reorder | |
1631 | INSN | |
1632 | bne $4,$0,foo | |
1633 | in which we can not swap the bne and INSN. If gcc is | |
1634 | not configured -with-gnu-as, it does not output the | |
1635 | .set pseudo-ops. We don't have to check | |
1636 | prev_insn_unreordered, because prev_insn_valid will | |
1637 | be 0 in that case. We don't want to use | |
1638 | prev_prev_insn_valid, because we do want to be able | |
1639 | to swap at the start of a function. */ | |
1640 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1641 | /* If the branch is itself the target of a branch, we |
1642 | can not swap. We cheat on this; all we check for is | |
1643 | whether there is a label on this instruction. If | |
1644 | there are any branches to anything other than a | |
1645 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1646 | || insn_labels != NULL |
777ad64d | 1647 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1648 | can not do the swap. This does not apply to the |
1649 | mips16, which uses variant frags for different | |
1650 | purposes. */ | |
1651 | || (! mips16 | |
1652 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1653 | /* If the branch reads the condition codes, we don't |
1654 | even try to swap, because in the sequence | |
1655 | ctc1 $X,$31 | |
1656 | INSN | |
1657 | INSN | |
1658 | bc1t LABEL | |
1659 | we can not swap, and I don't feel like handling that | |
1660 | case. */ | |
cc5703cd ILT |
1661 | || (! mips16 |
1662 | && mips_isa < 4 | |
d8a1c247 | 1663 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1664 | /* We can not swap with an instruction that requires a |
1665 | delay slot, becase the target of the branch might | |
1666 | interfere with that instruction. */ | |
cc5703cd ILT |
1667 | || (! mips16 |
1668 | && mips_isa < 4 | |
d8a1c247 KR |
1669 | && (prev_pinfo |
1670 | & (INSN_LOAD_COPROC_DELAY | |
1671 | | INSN_COPROC_MOVE_DELAY | |
1672 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1673 | || (! interlocks |
b2b8c24e ILT |
1674 | && (prev_pinfo |
1675 | & (INSN_READ_LO | |
1676 | | INSN_READ_HI))) | |
cc5703cd ILT |
1677 | || (! mips16 |
1678 | && mips_isa < 2 | |
1aa6938e | 1679 | && (prev_pinfo |
8358c818 ILT |
1680 | & (INSN_LOAD_MEMORY_DELAY |
1681 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1682 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1683 | || (prev_pinfo |
6e8dda9c ILT |
1684 | & (INSN_UNCOND_BRANCH_DELAY |
1685 | | INSN_COND_BRANCH_DELAY | |
1686 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1687 | /* We do not swap with a trap instruction, since it |
1688 | complicates trap handlers to have the trap | |
1689 | instruction be in a delay slot. */ | |
1aa6938e | 1690 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1691 | /* If the branch reads a register that the previous |
1692 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1693 | || (! mips16 |
1694 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1695 | && insn_uses_reg (ip, |
1696 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1697 | & OP_MASK_RT), | |
cc5703cd ILT |
1698 | MIPS_GR_REG)) |
1699 | || (! mips16 | |
1700 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1701 | && insn_uses_reg (ip, |
1702 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1703 | & OP_MASK_RD), | |
cc5703cd ILT |
1704 | MIPS_GR_REG)) |
1705 | || (mips16 | |
1706 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1707 | && insn_uses_reg (ip, | |
1708 | ((prev_insn.insn_opcode | |
1709 | >> MIPS16OP_SH_RX) | |
1710 | & MIPS16OP_MASK_RX), | |
1711 | MIPS16_REG)) | |
1712 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1713 | && insn_uses_reg (ip, | |
1714 | ((prev_insn.insn_opcode | |
1715 | >> MIPS16OP_SH_RY) | |
1716 | & MIPS16OP_MASK_RY), | |
1717 | MIPS16_REG)) | |
1718 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1719 | && insn_uses_reg (ip, | |
1720 | ((prev_insn.insn_opcode | |
1721 | >> MIPS16OP_SH_RZ) | |
1722 | & MIPS16OP_MASK_RZ), | |
1723 | MIPS16_REG)) | |
1724 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1725 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1726 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1727 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1728 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1729 | && insn_uses_reg (ip, | |
1730 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1731 | insn_opcode), | |
1732 | MIPS_GR_REG)))) | |
1849d646 ILT |
1733 | /* If the branch writes a register that the previous |
1734 | instruction sets, we can not swap (we know that | |
1735 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1736 | || (! mips16 |
1737 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1738 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1739 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1740 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1741 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1742 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1743 | & OP_MASK_RT) | |
1744 | == 31)))) | |
cc5703cd ILT |
1745 | || (! mips16 |
1746 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1747 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1748 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1749 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1750 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1751 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1752 | & OP_MASK_RD) | |
1753 | == 31)))) | |
cc5703cd ILT |
1754 | || (mips16 |
1755 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1756 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1757 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1758 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1759 | == RA)))) | |
becfe05e ILT |
1760 | /* If the branch writes a register that the previous |
1761 | instruction reads, we can not swap (we know that | |
1762 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1763 | || (! mips16 |
1764 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1765 | && insn_uses_reg (&prev_insn, |
1766 | ((ip->insn_opcode >> OP_SH_RD) | |
1767 | & OP_MASK_RD), | |
cc5703cd ILT |
1768 | MIPS_GR_REG)) |
1769 | || (! mips16 | |
1770 | && (pinfo & INSN_WRITE_GPR_31) | |
1771 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1772 | || (mips16 | |
1773 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1774 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1775 | /* If we are generating embedded PIC code, the branch |
1776 | might be expanded into a sequence which uses $at, so | |
1777 | we can't swap with an instruction which reads it. */ | |
1778 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1779 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1780 | /* If the previous previous instruction has a load |
1781 | delay, and sets a register that the branch reads, we | |
1782 | can not swap. */ | |
cc5703cd ILT |
1783 | || (! mips16 |
1784 | && mips_isa < 4 | |
d8a1c247 KR |
1785 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1786 | || (mips_isa < 2 | |
1787 | && (prev_prev_insn.insn_mo->pinfo | |
1788 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1789 | && insn_uses_reg (ip, |
1790 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1791 | & OP_MASK_RT), | |
cc5703cd | 1792 | MIPS_GR_REG)) |
d31a3f5e ILT |
1793 | /* If one instruction sets a condition code and the |
1794 | other one uses a condition code, we can not swap. */ | |
1795 | || ((pinfo & INSN_READ_COND_CODE) | |
1796 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1797 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1798 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1799 | /* If the previous instruction uses the PC, we can not | |
1800 | swap. */ | |
1801 | || (mips16 | |
1802 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1803 | /* If the previous instruction was extended, we can not | |
1804 | swap. */ | |
1805 | || (mips16 && prev_insn_extended) | |
1806 | /* If the previous instruction had a fixup in mips16 | |
1807 | mode, we can not swap. This normally means that the | |
1808 | previous instruction was a 4 byte branch anyhow. */ | |
1809 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1810 | { |
1811 | /* We could do even better for unconditional branches to | |
1812 | portions of this object file; we could pick up the | |
1813 | instruction at the destination, put it in the delay | |
1814 | slot, and bump the destination address. */ | |
1815 | emit_nop (); | |
1816 | /* Update the previous insn information. */ | |
1817 | prev_prev_insn = *ip; | |
1818 | prev_insn.insn_mo = &dummy_opcode; | |
1819 | } | |
1820 | else | |
1821 | { | |
becfe05e | 1822 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1823 | if (! mips16) |
1824 | { | |
1825 | char *prev_f; | |
1826 | char temp[4]; | |
1827 | ||
1828 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1829 | memcpy (temp, prev_f, 4); | |
1830 | memcpy (prev_f, f, 4); | |
1831 | memcpy (f, temp, 4); | |
1832 | if (prev_insn_fixp) | |
1833 | { | |
1834 | prev_insn_fixp->fx_frag = frag_now; | |
1835 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1836 | } | |
1837 | if (fixp) | |
1838 | { | |
1839 | fixp->fx_frag = prev_insn_frag; | |
1840 | fixp->fx_where = prev_insn_where; | |
1841 | } | |
1842 | } | |
1843 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1844 | { |
cc5703cd ILT |
1845 | char *prev_f; |
1846 | char temp[2]; | |
1847 | ||
1848 | /* We are in mips16 mode, and we have just created a | |
1849 | variant frag. We need to extract the old | |
1850 | instruction from the end of the previous frag, | |
1851 | and add it to a new frag. */ | |
1852 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1853 | memcpy (temp, prev_f, 2); | |
1854 | prev_insn_frag->fr_fix -= 2; | |
1855 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1856 | { | |
1857 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1858 | memcpy (prev_f, prev_f + 2, 2); | |
1859 | } | |
1860 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1861 | } |
cc5703cd | 1862 | else |
becfe05e | 1863 | { |
cc5703cd ILT |
1864 | char *prev_f; |
1865 | char temp[2]; | |
1866 | ||
1867 | assert (prev_insn_fixp == NULL); | |
1868 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1869 | memcpy (temp, prev_f, 2); | |
1870 | memcpy (prev_f, f, 2); | |
1871 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1872 | memcpy (f, temp, 2); | |
1873 | else | |
1874 | { | |
1875 | memcpy (f, f + 2, 2); | |
1876 | memcpy (f + 2, temp, 2); | |
1877 | } | |
1878 | if (fixp) | |
1879 | { | |
1880 | fixp->fx_frag = prev_insn_frag; | |
1881 | fixp->fx_where = prev_insn_where; | |
1882 | } | |
becfe05e | 1883 | } |
cc5703cd | 1884 | |
becfe05e ILT |
1885 | /* Update the previous insn information; leave prev_insn |
1886 | unchanged. */ | |
1887 | prev_prev_insn = *ip; | |
1888 | } | |
1889 | prev_insn_is_delay_slot = 1; | |
1890 | ||
1891 | /* If that was an unconditional branch, forget the previous | |
1892 | insn information. */ | |
1aa6938e | 1893 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1894 | { |
1895 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1896 | prev_insn.insn_mo = &dummy_opcode; | |
1897 | } | |
a677feeb ILT |
1898 | |
1899 | prev_insn_fixp = NULL; | |
1900 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1901 | prev_insn_extended = 0; | |
becfe05e | 1902 | } |
1aa6938e | 1903 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1904 | { |
1905 | /* We don't yet optimize a branch likely. What we should do | |
1906 | is look at the target, copy the instruction found there | |
1907 | into the delay slot, and increment the branch to jump to | |
1908 | the next instruction. */ | |
1909 | emit_nop (); | |
1910 | /* Update the previous insn information. */ | |
1911 | prev_prev_insn = *ip; | |
1912 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1913 | prev_insn_fixp = NULL; |
1914 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1915 | prev_insn_extended = 0; | |
8358c818 | 1916 | } |
becfe05e | 1917 | else |
670a50eb | 1918 | { |
becfe05e ILT |
1919 | /* Update the previous insn information. */ |
1920 | if (nops > 0) | |
1921 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1922 | else | |
1923 | prev_prev_insn = prev_insn; | |
1924 | prev_insn = *ip; | |
1925 | ||
1926 | /* Any time we see a branch, we always fill the delay slot | |
1927 | immediately; since this insn is not a branch, we know it | |
1928 | is not in a delay slot. */ | |
1929 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1930 | |
1931 | prev_insn_fixp = fixp; | |
1932 | prev_insn_reloc_type = reloc_type; | |
1933 | if (mips16) | |
1934 | prev_insn_extended = (ip->use_extend | |
1935 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1936 | } |
1937 | ||
4e95866e ILT |
1938 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1939 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1940 | prev_insn_frag = frag_now; |
1941 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1942 | prev_insn_valid = 1; |
1943 | } | |
fbcfacb7 | 1944 | else if (place == NULL) |
a677feeb | 1945 | { |
fbcfacb7 | 1946 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1947 | reordering, in order to determine the base address for mips16 |
1948 | PC relative relocs. */ | |
1949 | prev_insn = *ip; | |
1950 | prev_insn_reloc_type = reloc_type; | |
1951 | } | |
3d3c5039 | 1952 | |
becfe05e | 1953 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1954 | mips_clear_insn_labels (); |
becfe05e ILT |
1955 | } |
1956 | ||
1957 | /* This function forgets that there was any previous instruction or | |
1958 | label. */ | |
1959 | ||
1960 | static void | |
1961 | mips_no_prev_insn () | |
1962 | { | |
1963 | prev_insn.insn_mo = &dummy_opcode; | |
1964 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1965 | prev_insn_valid = 0; | |
1966 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1967 | prev_insn_unreordered = 0; |
cc5703cd | 1968 | prev_insn_extended = 0; |
a677feeb | 1969 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 1970 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 1971 | mips_clear_insn_labels (); |
becfe05e ILT |
1972 | } |
1973 | ||
1974 | /* This function must be called whenever we turn on noreorder or emit | |
1975 | something other than instructions. It inserts any NOPS which might | |
1976 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
1977 | kept for the previous instructions. The INSNS parameter is true if |
1978 | instructions are to follow. */ | |
becfe05e ILT |
1979 | |
1980 | static void | |
fbcfacb7 ILT |
1981 | mips_emit_delays (insns) |
1982 | boolean insns; | |
becfe05e ILT |
1983 | { |
1984 | if (! mips_noreorder) | |
1985 | { | |
1986 | int nop; | |
1987 | ||
1988 | nop = 0; | |
cc5703cd ILT |
1989 | if ((! mips16 |
1990 | && mips_isa < 4 | |
344a8d61 JSC |
1991 | && (! cop_interlocks |
1992 | && (prev_insn.insn_mo->pinfo | |
1993 | & (INSN_LOAD_COPROC_DELAY | |
1994 | | INSN_COPROC_MOVE_DELAY | |
1995 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1996 | || (! interlocks |
b2b8c24e ILT |
1997 | && (prev_insn.insn_mo->pinfo |
1998 | & (INSN_READ_LO | |
1999 | | INSN_READ_HI))) | |
cc5703cd ILT |
2000 | || (! mips16 |
2001 | && mips_isa < 2 | |
8358c818 ILT |
2002 | && (prev_insn.insn_mo->pinfo |
2003 | & (INSN_LOAD_MEMORY_DELAY | |
2004 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
2005 | { |
2006 | nop = 1; | |
cc5703cd ILT |
2007 | if ((! mips16 |
2008 | && mips_isa < 4 | |
344a8d61 JSC |
2009 | && (! cop_interlocks |
2010 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2011 | || (! interlocks |
b2b8c24e ILT |
2012 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2013 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2014 | emit_nop (); |
2015 | } | |
cc5703cd ILT |
2016 | else if ((! mips16 |
2017 | && mips_isa < 4 | |
344a8d61 JSC |
2018 | && (! cop_interlocks |
2019 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2020 | || (! interlocks |
b2b8c24e ILT |
2021 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2022 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2023 | nop = 1; |
2024 | if (nop) | |
670a50eb | 2025 | { |
fbcfacb7 ILT |
2026 | struct insn_label_list *l; |
2027 | ||
becfe05e | 2028 | emit_nop (); |
fbcfacb7 | 2029 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2030 | { |
fbcfacb7 ILT |
2031 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2032 | l->label->sy_frag = frag_now; | |
2033 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2034 | /* mips16 text labels are stored as odd. */ | |
2035 | if (mips16) | |
2036 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2037 | } |
3d3c5039 ILT |
2038 | } |
2039 | } | |
0221ddf7 | 2040 | |
fbcfacb7 ILT |
2041 | /* Mark instruction labels in mips16 mode. This permits the linker |
2042 | to handle them specially, such as generating jalx instructions | |
2043 | when needed. We also make them odd for the duration of the | |
2044 | assembly, in order to generate the right sort of code. We will | |
2045 | make them even in the adjust_symtab routine, while leaving them | |
2046 | marked. This is convenient for the debugger and the | |
2047 | disassembler. The linker knows to make them odd again. */ | |
2048 | if (mips16 && insns) | |
2049 | { | |
2050 | struct insn_label_list *l; | |
2051 | ||
2052 | for (l = insn_labels; l != NULL; l = l->next) | |
2053 | { | |
2054 | #ifdef S_SET_OTHER | |
2055 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2056 | S_SET_OTHER (l->label, STO_MIPS16); | |
2057 | #endif | |
2058 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2059 | ++l->label->sy_value.X_add_number; | |
2060 | } | |
2061 | } | |
2062 | ||
0221ddf7 | 2063 | mips_no_prev_insn (); |
3d3c5039 ILT |
2064 | } |
2065 | ||
670a50eb ILT |
2066 | /* Build an instruction created by a macro expansion. This is passed |
2067 | a pointer to the count of instructions created so far, an | |
2068 | expression, the name of the instruction to build, an operand format | |
2069 | string, and corresponding arguments. */ | |
2070 | ||
1dc1e798 | 2071 | #ifdef USE_STDARG |
3d3c5039 | 2072 | static void |
0dd2d296 ILT |
2073 | macro_build (char *place, |
2074 | int *counter, | |
670a50eb | 2075 | expressionS * ep, |
3d3c5039 ILT |
2076 | const char *name, |
2077 | const char *fmt, | |
2078 | ...) | |
1dc1e798 | 2079 | #else |
3d3c5039 | 2080 | static void |
0dd2d296 ILT |
2081 | macro_build (place, counter, ep, name, fmt, va_alist) |
2082 | char *place; | |
3d3c5039 ILT |
2083 | int *counter; |
2084 | expressionS *ep; | |
2085 | const char *name; | |
2086 | const char *fmt; | |
2087 | va_dcl | |
1dc1e798 | 2088 | #endif |
3d3c5039 | 2089 | { |
670a50eb ILT |
2090 | struct mips_cl_insn insn; |
2091 | bfd_reloc_code_real_type r; | |
2092 | va_list args; | |
3d3c5039 | 2093 | |
1dc1e798 | 2094 | #ifdef USE_STDARG |
670a50eb | 2095 | va_start (args, fmt); |
3d3c5039 | 2096 | #else |
670a50eb | 2097 | va_start (args); |
3d3c5039 ILT |
2098 | #endif |
2099 | ||
670a50eb ILT |
2100 | /* |
2101 | * If the macro is about to expand into a second instruction, | |
2102 | * print a warning if needed. We need to pass ip as a parameter | |
2103 | * to generate a better warning message here... | |
2104 | */ | |
0dd2d296 | 2105 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2106 | as_warn ("Macro instruction expanded into multiple instructions"); |
2107 | ||
0dd2d296 ILT |
2108 | if (place == NULL) |
2109 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2110 | |
cc5703cd ILT |
2111 | if (mips16) |
2112 | { | |
2113 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2114 | va_end (args); | |
2115 | return; | |
2116 | } | |
2117 | ||
670a50eb ILT |
2118 | r = BFD_RELOC_UNUSED; |
2119 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2120 | assert (insn.insn_mo); | |
2121 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2122 | ||
9226253a | 2123 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2124 | || insn.insn_mo->pinfo == INSN_MACRO |
2125 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2126 | && mips_isa < 2) | |
2127 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2128 | && mips_isa < 3) | |
2129 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2130 | && mips_isa < 4) | |
2131 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2132 | && ! mips_4650) | |
2133 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2134 | && ! mips_4010) | |
2135 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2136 | && ! mips_4100) |
2137 | /* start-sanitize-r5900 */ | |
2138 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2139 | && ! mips_5900) | |
2140 | /* end-sanitize-r5900 */ | |
2141 | ) | |
670a50eb ILT |
2142 | { |
2143 | ++insn.insn_mo; | |
2144 | assert (insn.insn_mo->name); | |
2145 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2146 | } |
670a50eb ILT |
2147 | insn.insn_opcode = insn.insn_mo->match; |
2148 | for (;;) | |
2149 | { | |
2150 | switch (*fmt++) | |
2151 | { | |
3d3c5039 | 2152 | case '\0': |
670a50eb | 2153 | break; |
3d3c5039 ILT |
2154 | |
2155 | case ',': | |
2156 | case '(': | |
2157 | case ')': | |
670a50eb | 2158 | continue; |
3d3c5039 ILT |
2159 | |
2160 | case 't': | |
2161 | case 'w': | |
918692a5 | 2162 | case 'E': |
670a50eb ILT |
2163 | insn.insn_opcode |= va_arg (args, int) << 16; |
2164 | continue; | |
3d3c5039 ILT |
2165 | |
2166 | case 'c': | |
2167 | case 'T': | |
2168 | case 'W': | |
670a50eb ILT |
2169 | insn.insn_opcode |= va_arg (args, int) << 16; |
2170 | continue; | |
3d3c5039 ILT |
2171 | |
2172 | case 'd': | |
918692a5 | 2173 | case 'G': |
670a50eb ILT |
2174 | insn.insn_opcode |= va_arg (args, int) << 11; |
2175 | continue; | |
3d3c5039 ILT |
2176 | |
2177 | case 'V': | |
2178 | case 'S': | |
670a50eb ILT |
2179 | insn.insn_opcode |= va_arg (args, int) << 11; |
2180 | continue; | |
3d3c5039 | 2181 | |
ff3a5c18 ILT |
2182 | case 'z': |
2183 | continue; | |
2184 | ||
3d3c5039 | 2185 | case '<': |
670a50eb ILT |
2186 | insn.insn_opcode |= va_arg (args, int) << 6; |
2187 | continue; | |
3d3c5039 ILT |
2188 | |
2189 | case 'D': | |
670a50eb ILT |
2190 | insn.insn_opcode |= va_arg (args, int) << 6; |
2191 | continue; | |
3d3c5039 | 2192 | |
918692a5 ILT |
2193 | case 'B': |
2194 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2195 | continue; | |
2196 | ||
3d3c5039 ILT |
2197 | case 'b': |
2198 | case 's': | |
2199 | case 'r': | |
2200 | case 'v': | |
670a50eb ILT |
2201 | insn.insn_opcode |= va_arg (args, int) << 21; |
2202 | continue; | |
3d3c5039 ILT |
2203 | |
2204 | case 'i': | |
2205 | case 'j': | |
2206 | case 'o': | |
9226253a | 2207 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2208 | assert (r == BFD_RELOC_MIPS_GPREL |
2209 | || r == BFD_RELOC_MIPS_LITERAL | |
2210 | || r == BFD_RELOC_LO16 | |
2211 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2212 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2213 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2214 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2215 | || (ep->X_op == O_subtract |
2216 | && now_seg == text_section | |
ecd4ca1c | 2217 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2218 | continue; |
3d3c5039 | 2219 | |
6e8dda9c | 2220 | case 'u': |
ecd4ca1c ILT |
2221 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2222 | assert (ep != NULL | |
2223 | && (ep->X_op == O_constant | |
2224 | || (ep->X_op == O_symbol | |
2225 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2226 | || r == BFD_RELOC_HI16 |
2227 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2228 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2229 | || (ep->X_op == O_subtract |
2230 | && now_seg == text_section | |
ecd4ca1c ILT |
2231 | && r == BFD_RELOC_PCREL_HI16_S))); |
2232 | if (ep->X_op == O_constant) | |
2233 | { | |
2234 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2235 | ep = NULL; | |
2236 | r = BFD_RELOC_UNUSED; | |
2237 | } | |
6e8dda9c ILT |
2238 | continue; |
2239 | ||
3d3c5039 | 2240 | case 'p': |
670a50eb ILT |
2241 | assert (ep != NULL); |
2242 | /* | |
2243 | * This allows macro() to pass an immediate expression for | |
2244 | * creating short branches without creating a symbol. | |
2245 | * Note that the expression still might come from the assembly | |
2246 | * input, in which case the value is not checked for range nor | |
2247 | * is a relocation entry generated (yuck). | |
2248 | */ | |
5ac34ac3 | 2249 | if (ep->X_op == O_constant) |
670a50eb ILT |
2250 | { |
2251 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2252 | ep = NULL; | |
2253 | } | |
2254 | else | |
2255 | r = BFD_RELOC_16_PCREL_S2; | |
2256 | continue; | |
3d3c5039 | 2257 | |
9226253a ILT |
2258 | case 'a': |
2259 | assert (ep != NULL); | |
2260 | r = BFD_RELOC_MIPS_JMP; | |
2261 | continue; | |
2262 | ||
3d3c5039 | 2263 | default: |
670a50eb | 2264 | internalError (); |
3d3c5039 | 2265 | } |
670a50eb | 2266 | break; |
3d3c5039 | 2267 | } |
670a50eb ILT |
2268 | va_end (args); |
2269 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2270 | ||
867a58b3 | 2271 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2272 | } |
2273 | ||
cc5703cd ILT |
2274 | static void |
2275 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2276 | char *place; | |
2277 | int *counter; | |
2278 | expressionS *ep; | |
2279 | const char *name; | |
2280 | const char *fmt; | |
2281 | va_list args; | |
2282 | { | |
2283 | struct mips_cl_insn insn; | |
2284 | bfd_reloc_code_real_type r; | |
2285 | ||
2286 | r = BFD_RELOC_UNUSED; | |
2287 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2288 | assert (insn.insn_mo); | |
2289 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2290 | ||
2291 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2292 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2293 | { | |
2294 | ++insn.insn_mo; | |
2295 | assert (insn.insn_mo->name); | |
2296 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2297 | } | |
2298 | ||
2299 | insn.insn_opcode = insn.insn_mo->match; | |
2300 | insn.use_extend = false; | |
2301 | ||
2302 | for (;;) | |
2303 | { | |
2304 | int c; | |
2305 | ||
2306 | c = *fmt++; | |
2307 | switch (c) | |
2308 | { | |
2309 | case '\0': | |
2310 | break; | |
2311 | ||
2312 | case ',': | |
2313 | case '(': | |
2314 | case ')': | |
2315 | continue; | |
2316 | ||
2317 | case 'y': | |
2318 | case 'w': | |
2319 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2320 | continue; | |
2321 | ||
2322 | case 'x': | |
2323 | case 'v': | |
2324 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2325 | continue; | |
2326 | ||
2327 | case 'z': | |
2328 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2329 | continue; | |
2330 | ||
2331 | case 'Z': | |
2332 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2333 | continue; | |
2334 | ||
2335 | case '0': | |
2336 | case 'S': | |
2337 | case 'P': | |
2338 | case 'R': | |
2339 | continue; | |
2340 | ||
2341 | case 'X': | |
2342 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2343 | continue; | |
2344 | ||
2345 | case 'Y': | |
2346 | { | |
2347 | int regno; | |
2348 | ||
2349 | regno = va_arg (args, int); | |
2350 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2351 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2352 | } | |
2353 | continue; | |
2354 | ||
2355 | case '<': | |
2356 | case '>': | |
2357 | case '4': | |
2358 | case '5': | |
2359 | case 'H': | |
2360 | case 'W': | |
2361 | case 'D': | |
2362 | case 'j': | |
2363 | case '8': | |
2364 | case 'V': | |
2365 | case 'C': | |
2366 | case 'U': | |
2367 | case 'k': | |
2368 | case 'K': | |
2369 | case 'p': | |
2370 | case 'q': | |
2371 | { | |
2372 | assert (ep != NULL); | |
2373 | ||
2374 | if (ep->X_op != O_constant) | |
2375 | r = BFD_RELOC_UNUSED + c; | |
2376 | else | |
2377 | { | |
15e69f98 ILT |
2378 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2379 | false, false, &insn.insn_opcode, | |
2380 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2381 | ep = NULL; |
2382 | r = BFD_RELOC_UNUSED; | |
2383 | } | |
2384 | } | |
2385 | continue; | |
2386 | ||
2387 | case '6': | |
2388 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2389 | continue; | |
2390 | } | |
2391 | ||
2392 | break; | |
2393 | } | |
2394 | ||
2395 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2396 | ||
2397 | append_insn (place, &insn, ep, r, false); | |
2398 | } | |
2399 | ||
3d3c5039 ILT |
2400 | /* |
2401 | * Generate a "lui" instruction. | |
2402 | */ | |
2403 | static void | |
0dd2d296 ILT |
2404 | macro_build_lui (place, counter, ep, regnum) |
2405 | char *place; | |
3d3c5039 ILT |
2406 | int *counter; |
2407 | expressionS *ep; | |
2408 | int regnum; | |
2409 | { | |
670a50eb ILT |
2410 | expressionS high_expr; |
2411 | struct mips_cl_insn insn; | |
2412 | bfd_reloc_code_real_type r; | |
2413 | CONST char *name = "lui"; | |
2414 | CONST char *fmt = "t,u"; | |
2415 | ||
cc5703cd ILT |
2416 | assert (! mips16); |
2417 | ||
0dd2d296 ILT |
2418 | if (place == NULL) |
2419 | high_expr = *ep; | |
2420 | else | |
2421 | { | |
2422 | high_expr.X_op = O_constant; | |
fb251650 | 2423 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2424 | } |
670a50eb | 2425 | |
5ac34ac3 | 2426 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2427 | { |
2428 | /* we can compute the instruction now without a relocation entry */ | |
2429 | if (high_expr.X_add_number & 0x8000) | |
2430 | high_expr.X_add_number += 0x10000; | |
2431 | high_expr.X_add_number = | |
2432 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2433 | r = BFD_RELOC_UNUSED; | |
2434 | } | |
2435 | else | |
0dd2d296 ILT |
2436 | { |
2437 | assert (ep->X_op == O_symbol); | |
2438 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2439 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2440 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2441 | r = BFD_RELOC_HI16_S; | |
2442 | } | |
670a50eb ILT |
2443 | |
2444 | /* | |
2445 | * If the macro is about to expand into a second instruction, | |
2446 | * print a warning if needed. We need to pass ip as a parameter | |
2447 | * to generate a better warning message here... | |
2448 | */ | |
0dd2d296 | 2449 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2450 | as_warn ("Macro instruction expanded into multiple instructions"); |
2451 | ||
0dd2d296 ILT |
2452 | if (place == NULL) |
2453 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2454 | |
2455 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2456 | assert (insn.insn_mo); | |
2457 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2458 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2459 | ||
0dd2d296 | 2460 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2461 | if (r == BFD_RELOC_UNUSED) |
2462 | { | |
2463 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2464 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2465 | } |
2466 | else | |
867a58b3 | 2467 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2468 | } |
2469 | ||
2470 | /* set_at() | |
2471 | * Generates code to set the $at register to true (one) | |
2472 | * if reg is less than the immediate expression. | |
2473 | */ | |
2474 | static void | |
6e8dda9c | 2475 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2476 | int *counter; |
2477 | int reg; | |
6e8dda9c | 2478 | int unsignedp; |
3d3c5039 | 2479 | { |
6e8dda9c | 2480 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2481 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2482 | unsignedp ? "sltiu" : "slti", |
9226253a | 2483 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2484 | else |
670a50eb | 2485 | { |
d8a1c247 | 2486 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2487 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2488 | unsignedp ? "sltu" : "slt", |
2489 | "d,v,t", AT, reg, AT); | |
670a50eb | 2490 | } |
3d3c5039 ILT |
2491 | } |
2492 | ||
6e8dda9c | 2493 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2494 | |
2495 | static void | |
19ed8960 | 2496 | check_absolute_expr (ip, ex) |
3d3c5039 | 2497 | struct mips_cl_insn *ip; |
19ed8960 | 2498 | expressionS *ex; |
3d3c5039 | 2499 | { |
19ed8960 | 2500 | if (ex->X_op != O_constant) |
670a50eb | 2501 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2502 | } |
2503 | ||
ff8716f5 JSC |
2504 | /* Count the leading zeroes by performing a binary chop. This is a |
2505 | bulky bit of source, but performance is a LOT better for the | |
2506 | majority of values than a simple loop to count the bits: | |
2507 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2508 | if ((v) & (1 << (31 - lcnt))) | |
2509 | break; | |
2510 | However it is not code size friendly, and the gain will drop a bit | |
2511 | on certain cached systems. | |
2512 | */ | |
2513 | #define COUNT_TOP_ZEROES(v) \ | |
2514 | (((v) & ~0xffff) == 0 \ | |
2515 | ? ((v) & ~0xff) == 0 \ | |
2516 | ? ((v) & ~0xf) == 0 \ | |
2517 | ? ((v) & ~0x3) == 0 \ | |
2518 | ? ((v) & ~0x1) == 0 \ | |
2519 | ? !(v) \ | |
2520 | ? 32 \ | |
2521 | : 31 \ | |
2522 | : 30 \ | |
2523 | : ((v) & ~0x7) == 0 \ | |
2524 | ? 29 \ | |
2525 | : 28 \ | |
2526 | : ((v) & ~0x3f) == 0 \ | |
2527 | ? ((v) & ~0x1f) == 0 \ | |
2528 | ? 27 \ | |
2529 | : 26 \ | |
2530 | : ((v) & ~0x7f) == 0 \ | |
2531 | ? 25 \ | |
2532 | : 24 \ | |
2533 | : ((v) & ~0xfff) == 0 \ | |
2534 | ? ((v) & ~0x3ff) == 0 \ | |
2535 | ? ((v) & ~0x1ff) == 0 \ | |
2536 | ? 23 \ | |
2537 | : 22 \ | |
2538 | : ((v) & ~0x7ff) == 0 \ | |
2539 | ? 21 \ | |
2540 | : 20 \ | |
2541 | : ((v) & ~0x3fff) == 0 \ | |
2542 | ? ((v) & ~0x1fff) == 0 \ | |
2543 | ? 19 \ | |
2544 | : 18 \ | |
2545 | : ((v) & ~0x7fff) == 0 \ | |
2546 | ? 17 \ | |
2547 | : 16 \ | |
2548 | : ((v) & ~0xffffff) == 0 \ | |
2549 | ? ((v) & ~0xfffff) == 0 \ | |
2550 | ? ((v) & ~0x3ffff) == 0 \ | |
2551 | ? ((v) & ~0x1ffff) == 0 \ | |
2552 | ? 15 \ | |
2553 | : 14 \ | |
2554 | : ((v) & ~0x7ffff) == 0 \ | |
2555 | ? 13 \ | |
2556 | : 12 \ | |
2557 | : ((v) & ~0x3fffff) == 0 \ | |
2558 | ? ((v) & ~0x1fffff) == 0 \ | |
2559 | ? 11 \ | |
2560 | : 10 \ | |
2561 | : ((v) & ~0x7fffff) == 0 \ | |
2562 | ? 9 \ | |
2563 | : 8 \ | |
2564 | : ((v) & ~0xfffffff) == 0 \ | |
2565 | ? ((v) & ~0x3ffffff) == 0 \ | |
2566 | ? ((v) & ~0x1ffffff) == 0 \ | |
2567 | ? 7 \ | |
2568 | : 6 \ | |
2569 | : ((v) & ~0x7ffffff) == 0 \ | |
2570 | ? 5 \ | |
2571 | : 4 \ | |
2572 | : ((v) & ~0x3fffffff) == 0 \ | |
2573 | ? ((v) & ~0x1fffffff) == 0 \ | |
2574 | ? 3 \ | |
2575 | : 2 \ | |
2576 | : ((v) & ~0x7fffffff) == 0 \ | |
2577 | ? 1 \ | |
2578 | : 0) | |
2579 | ||
3d3c5039 ILT |
2580 | /* load_register() |
2581 | * This routine generates the least number of instructions neccessary to load | |
2582 | * an absolute expression value into a register. | |
2583 | */ | |
2584 | static void | |
d8a1c247 | 2585 | load_register (counter, reg, ep, dbl) |
670a50eb | 2586 | int *counter; |
670a50eb ILT |
2587 | int reg; |
2588 | expressionS *ep; | |
d8a1c247 | 2589 | int dbl; |
3d3c5039 | 2590 | { |
c36a90ef ILT |
2591 | int freg; |
2592 | expressionS hi32, lo32; | |
847a01cd ILT |
2593 | |
2594 | if (ep->X_op != O_big) | |
6e8dda9c | 2595 | { |
847a01cd | 2596 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2597 | if (ep->X_add_number < 0x8000 |
2598 | && (ep->X_add_number >= 0 | |
2599 | || (ep->X_add_number >= -0x8000 | |
2600 | && (! dbl | |
2601 | || ! ep->X_unsigned | |
2602 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2603 | { |
2604 | /* We can handle 16 bit signed values with an addiu to | |
2605 | $zero. No need to ever use daddiu here, since $zero and | |
2606 | the result are always correct in 32 bit mode. */ | |
2607 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2608 | (int) BFD_RELOC_LO16); | |
2609 | return; | |
2610 | } | |
2611 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2612 | { | |
2613 | /* We can handle 16 bit unsigned values with an ori to | |
2614 | $zero. */ | |
2615 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2616 | (int) BFD_RELOC_LO16); | |
2617 | return; | |
2618 | } | |
98bfd087 ILT |
2619 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2620 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2621 | == ~ (offsetT) 0x7fffffff)) | |
2622 | && (! dbl | |
2623 | || ! ep->X_unsigned | |
2624 | || sizeof (ep->X_add_number) > 4 | |
2625 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2626 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2627 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2628 | { |
2629 | /* 32 bit values require an lui. */ | |
2630 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2631 | (int) BFD_RELOC_HI16); | |
2632 | if ((ep->X_add_number & 0xffff) != 0) | |
2633 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2634 | (int) BFD_RELOC_LO16); | |
2635 | return; | |
2636 | } | |
6e8dda9c | 2637 | } |
847a01cd ILT |
2638 | |
2639 | /* The value is larger than 32 bits. */ | |
2640 | ||
2641 | if (mips_isa < 3) | |
670a50eb | 2642 | { |
6e8dda9c | 2643 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2644 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2645 | (int) BFD_RELOC_LO16); |
847a01cd | 2646 | return; |
6e8dda9c | 2647 | } |
6e8dda9c | 2648 | |
847a01cd ILT |
2649 | if (ep->X_op != O_big) |
2650 | { | |
6e8dda9c | 2651 | hi32 = *ep; |
c36a90ef ILT |
2652 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2653 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2654 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2655 | lo32 = *ep; |
2656 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2657 | } |
847a01cd ILT |
2658 | else |
2659 | { | |
2660 | assert (ep->X_add_number > 2); | |
2661 | if (ep->X_add_number == 3) | |
2662 | generic_bignum[3] = 0; | |
2663 | else if (ep->X_add_number > 4) | |
2664 | as_bad ("Number larger than 64 bits"); | |
2665 | lo32.X_op = O_constant; | |
2666 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2667 | hi32.X_op = O_constant; | |
2668 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2669 | } | |
2670 | ||
d8a1c247 KR |
2671 | if (hi32.X_add_number == 0) |
2672 | freg = 0; | |
2673 | else | |
2674 | { | |
c36a90ef ILT |
2675 | int shift, bit; |
2676 | unsigned long hi, lo; | |
2677 | ||
fb251650 ILT |
2678 | if (hi32.X_add_number == 0xffffffff) |
2679 | { | |
2680 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2681 | { | |
c36a90ef ILT |
2682 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2683 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2684 | return; |
2685 | } | |
2686 | if (lo32.X_add_number & 0x80000000) | |
2687 | { | |
2688 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2689 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2690 | if (lo32.X_add_number & 0xffff) |
2691 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2692 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2693 | return; |
2694 | } | |
2695 | } | |
ff8716f5 | 2696 | |
c36a90ef ILT |
2697 | /* Check for 16bit shifted constant. We know that hi32 is |
2698 | non-zero, so start the mask on the first bit of the hi32 | |
2699 | value. */ | |
ff8716f5 JSC |
2700 | shift = 17; |
2701 | do | |
2702 | { | |
c36a90ef ILT |
2703 | unsigned long himask, lomask; |
2704 | ||
2705 | if (shift < 32) | |
2706 | { | |
2707 | himask = 0xffff >> (32 - shift); | |
2708 | lomask = (0xffff << shift) & 0xffffffff; | |
2709 | } | |
2710 | else | |
2711 | { | |
2712 | himask = 0xffff << (shift - 32); | |
2713 | lomask = 0; | |
2714 | } | |
2715 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2716 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2717 | { | |
2718 | expressionS tmp; | |
2719 | ||
2720 | tmp.X_op = O_constant; | |
2721 | if (shift < 32) | |
2722 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2723 | | (lo32.X_add_number >> shift)); | |
2724 | else | |
2725 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2726 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2727 | (int) BFD_RELOC_LO16); | |
2728 | macro_build ((char *) NULL, counter, NULL, | |
2729 | (shift >= 32) ? "dsll32" : "dsll", | |
2730 | "d,w,<", reg, reg, | |
2731 | (shift >= 32) ? shift - 32 : shift); | |
2732 | return; | |
2733 | } | |
ff8716f5 JSC |
2734 | shift++; |
2735 | } while (shift <= (64 - 16)); | |
2736 | ||
c36a90ef ILT |
2737 | /* Find the bit number of the lowest one bit, and store the |
2738 | shifted value in hi/lo. */ | |
2739 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2740 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2741 | if (lo != 0) | |
2742 | { | |
2743 | bit = 0; | |
2744 | while ((lo & 1) == 0) | |
2745 | { | |
2746 | lo >>= 1; | |
2747 | ++bit; | |
2748 | } | |
2749 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2750 | hi >>= bit; | |
2751 | } | |
2752 | else | |
2753 | { | |
2754 | bit = 32; | |
2755 | while ((hi & 1) == 0) | |
2756 | { | |
2757 | hi >>= 1; | |
2758 | ++bit; | |
2759 | } | |
2760 | lo = hi; | |
2761 | hi = 0; | |
2762 | } | |
2763 | ||
2764 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2765 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2766 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2767 | { |
c36a90ef | 2768 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2769 | if (shift != 0) |
2770 | { | |
c36a90ef ILT |
2771 | expressionS tmp; |
2772 | ||
2773 | /* This instruction will set the register to be all | |
2774 | ones. */ | |
ff8716f5 | 2775 | tmp.X_op = O_constant; |
c36a90ef ILT |
2776 | tmp.X_add_number = (offsetT) -1; |
2777 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2778 | reg, 0, (int) BFD_RELOC_LO16); | |
2779 | if (bit != 0) | |
ff8716f5 | 2780 | { |
c36a90ef | 2781 | bit += shift; |
ff8716f5 | 2782 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2783 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2784 | "d,w,<", reg, reg, |
c36a90ef | 2785 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2786 | } |
c36a90ef ILT |
2787 | macro_build ((char *) NULL, counter, NULL, |
2788 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2789 | "d,w,<", reg, reg, | |
2790 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2791 | return; |
2792 | } | |
2793 | } | |
c36a90ef ILT |
2794 | |
2795 | /* Sign extend hi32 before calling load_register, because we can | |
2796 | generally get better code when we load a sign extended value. */ | |
2797 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2798 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2799 | load_register (counter, reg, &hi32, 0); |
2800 | freg = reg; | |
2801 | } | |
847a01cd | 2802 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2803 | { |
2804 | if (freg != 0) | |
2805 | { | |
2806 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2807 | freg, 0); | |
2808 | freg = reg; | |
2809 | } | |
2810 | } | |
847a01cd ILT |
2811 | else |
2812 | { | |
2813 | expressionS mid16; | |
2814 | ||
fb251650 ILT |
2815 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2816 | { | |
2817 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2818 | (int) BFD_RELOC_HI16); | |
2819 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2820 | reg, 0); |
fb251650 ILT |
2821 | return; |
2822 | } | |
2823 | ||
d8a1c247 KR |
2824 | if (freg != 0) |
2825 | { | |
2826 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2827 | freg, 16); | |
2828 | freg = reg; | |
2829 | } | |
847a01cd ILT |
2830 | mid16 = lo32; |
2831 | mid16.X_add_number >>= 16; | |
2832 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2833 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2834 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2835 | reg, 16); | |
d8a1c247 | 2836 | freg = reg; |
847a01cd ILT |
2837 | } |
2838 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2839 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2840 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2841 | } |
2842 | ||
0dd2d296 ILT |
2843 | /* Load an address into a register. */ |
2844 | ||
2845 | static void | |
2846 | load_address (counter, reg, ep) | |
2847 | int *counter; | |
2848 | int reg; | |
2849 | expressionS *ep; | |
2850 | { | |
2851 | char *p; | |
2852 | ||
2853 | if (ep->X_op != O_constant | |
2854 | && ep->X_op != O_symbol) | |
2855 | { | |
2856 | as_bad ("expression too complex"); | |
2857 | ep->X_op = O_constant; | |
2858 | } | |
2859 | ||
2860 | if (ep->X_op == O_constant) | |
d9aba805 | 2861 | { |
d8a1c247 | 2862 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2863 | return; |
2864 | } | |
2865 | ||
2866 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2867 | { |
2868 | /* If this is a reference to a GP relative symbol, we want | |
2869 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2870 | Otherwise we want | |
04cb3372 | 2871 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2872 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2873 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2874 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2875 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2876 | p = NULL; |
2877 | else | |
2878 | { | |
8ea7f4e8 | 2879 | frag_grow (20); |
0dd2d296 ILT |
2880 | macro_build ((char *) NULL, counter, ep, |
2881 | mips_isa < 3 ? "addiu" : "daddiu", | |
2882 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2883 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2884 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2885 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2886 | } | |
2887 | macro_build_lui (p, counter, ep, reg); | |
2888 | if (p != NULL) | |
2889 | p += 4; | |
2890 | macro_build (p, counter, ep, | |
2891 | mips_isa < 3 ? "addiu" : "daddiu", | |
2892 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2893 | } | |
fb251650 | 2894 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2895 | { |
2896 | expressionS ex; | |
2897 | ||
2898 | /* If this is a reference to an external symbol, we want | |
2899 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2900 | Otherwise we want | |
2901 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2902 | nop | |
2903 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2904 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2905 | ex.X_add_number = ep->X_add_number; |
2906 | ep->X_add_number = 0; | |
8ea7f4e8 | 2907 | frag_grow (20); |
0dd2d296 ILT |
2908 | macro_build ((char *) NULL, counter, ep, |
2909 | mips_isa < 3 ? "lw" : "ld", | |
2910 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2911 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2912 | p = frag_var (rs_machine_dependent, 4, 0, | |
2913 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2914 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2915 | macro_build (p, counter, ep, | |
2916 | mips_isa < 3 ? "addiu" : "daddiu", | |
2917 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2918 | if (ex.X_add_number != 0) | |
2919 | { | |
2920 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2921 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2922 | ex.X_op = O_constant; | |
fb251650 ILT |
2923 | macro_build ((char *) NULL, counter, &ex, |
2924 | mips_isa < 3 ? "addiu" : "daddiu", | |
2925 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2926 | } | |
2927 | } | |
2928 | else if (mips_pic == SVR4_PIC) | |
2929 | { | |
2930 | expressionS ex; | |
2931 | int off; | |
2932 | ||
2933 | /* This is the large GOT case. If this is a reference to an | |
2934 | external symbol, we want | |
2935 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2936 | addu $reg,$reg,$gp | |
2937 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2938 | Otherwise, for a reference to a local symbol, we want | |
2939 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2940 | nop | |
2941 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2942 | If there is a constant, it must be added in after. */ | |
2943 | ex.X_add_number = ep->X_add_number; | |
2944 | ep->X_add_number = 0; | |
2945 | if (reg_needs_delay (GP)) | |
2946 | off = 4; | |
2947 | else | |
2948 | off = 0; | |
2949 | frag_grow (32); | |
2950 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2951 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2952 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2953 | mips_isa < 3 ? "addu" : "daddu", | |
2954 | "d,v,t", reg, reg, GP); | |
2955 | macro_build ((char *) NULL, counter, ep, | |
2956 | mips_isa < 3 ? "lw" : "ld", | |
2957 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2958 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2959 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2960 | mips_warn_about_macros), | |
2961 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2962 | if (off > 0) | |
2963 | { | |
2964 | /* We need a nop before loading from $gp. This special | |
2965 | check is required because the lui which starts the main | |
2966 | instruction stream does not refer to $gp, and so will not | |
2967 | insert the nop which may be required. */ | |
2968 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2969 | p += 4; | |
2970 | } | |
2971 | macro_build (p, counter, ep, | |
2972 | mips_isa < 3 ? "lw" : "ld", | |
2973 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2974 | p += 4; | |
2975 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2976 | p += 4; | |
2977 | macro_build (p, counter, ep, | |
2978 | mips_isa < 3 ? "addiu" : "daddiu", | |
2979 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2980 | if (ex.X_add_number != 0) | |
2981 | { | |
2982 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2983 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2984 | ex.X_op = O_constant; | |
2985 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2986 | mips_isa < 3 ? "addiu" : "daddiu", |
2987 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2988 | } | |
d9aba805 ILT |
2989 | } |
2990 | else if (mips_pic == EMBEDDED_PIC) | |
2991 | { | |
2992 | /* We always do | |
2993 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2994 | */ | |
2995 | macro_build ((char *) NULL, counter, ep, | |
2996 | mips_isa < 3 ? "addiu" : "daddiu", | |
2997 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2998 | } | |
2999 | else | |
3000 | abort (); | |
0dd2d296 ILT |
3001 | } |
3002 | ||
3d3c5039 ILT |
3003 | /* |
3004 | * Build macros | |
3005 | * This routine implements the seemingly endless macro or synthesized | |
3006 | * instructions and addressing modes in the mips assembly language. Many | |
3007 | * of these macros are simple and are similar to each other. These could | |
3008 | * probably be handled by some kind of table or grammer aproach instead of | |
3009 | * this verbose method. Others are not simple macros but are more like | |
3010 | * optimizing code generation. | |
3011 | * One interesting optimization is when several store macros appear | |
3012 | * consecutivly that would load AT with the upper half of the same address. | |
3013 | * The ensuing load upper instructions are ommited. This implies some kind | |
3014 | * of global optimization. We currently only optimize within a single macro. | |
3015 | * For many of the load and store macros if the address is specified as a | |
3016 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3017 | * first load register 'at' with zero and use it as the base register. The | |
3018 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3019 | * we're missing. | |
3020 | */ | |
3021 | static void | |
3022 | macro (ip) | |
3023 | struct mips_cl_insn *ip; | |
3024 | { | |
670a50eb ILT |
3025 | register int treg, sreg, dreg, breg; |
3026 | int tempreg; | |
3027 | int mask; | |
3028 | int icnt = 0; | |
3029 | int used_at; | |
670a50eb ILT |
3030 | expressionS expr1; |
3031 | const char *s; | |
8358c818 | 3032 | const char *s2; |
670a50eb | 3033 | const char *fmt; |
8358c818 ILT |
3034 | int likely = 0; |
3035 | int dbl = 0; | |
3036 | int coproc = 0; | |
b2b8c24e | 3037 | int lr = 0; |
6e8dda9c | 3038 | offsetT maxnum; |
adcf2b9d | 3039 | int off; |
9226253a | 3040 | bfd_reloc_code_real_type r; |
0dd2d296 | 3041 | char *p; |
55933a58 | 3042 | int hold_mips_optimize; |
670a50eb | 3043 | |
cc5703cd ILT |
3044 | assert (! mips16); |
3045 | ||
670a50eb ILT |
3046 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3047 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3048 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3049 | mask = ip->insn_mo->mask; | |
3050 | ||
5ac34ac3 ILT |
3051 | expr1.X_op = O_constant; |
3052 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3053 | expr1.X_add_symbol = NULL; |
3054 | expr1.X_add_number = 1; | |
3055 | ||
3056 | switch (mask) | |
3057 | { | |
6e8dda9c ILT |
3058 | case M_DABS: |
3059 | dbl = 1; | |
3d3c5039 | 3060 | case M_ABS: |
6e8dda9c ILT |
3061 | /* bgez $a0,.+12 |
3062 | move v0,$a0 | |
3063 | sub v0,$zero,$a0 | |
3064 | */ | |
3d3c5039 | 3065 | |
fbcfacb7 | 3066 | mips_emit_delays (true); |
becfe05e | 3067 | ++mips_noreorder; |
0dd2d296 | 3068 | mips_any_noreorder = 1; |
3d3c5039 | 3069 | |
670a50eb | 3070 | expr1.X_add_number = 8; |
0dd2d296 | 3071 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3072 | if (dreg == sreg) |
0dd2d296 | 3073 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3074 | else |
0dd2d296 ILT |
3075 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3076 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3077 | dbl ? "dsub" : "sub", |
3078 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3079 | |
becfe05e | 3080 | --mips_noreorder; |
670a50eb | 3081 | return; |
3d3c5039 ILT |
3082 | |
3083 | case M_ADD_I: | |
8358c818 ILT |
3084 | s = "addi"; |
3085 | s2 = "add"; | |
3086 | goto do_addi; | |
3d3c5039 | 3087 | case M_ADDU_I: |
8358c818 ILT |
3088 | s = "addiu"; |
3089 | s2 = "addu"; | |
3090 | goto do_addi; | |
3091 | case M_DADD_I: | |
6e8dda9c | 3092 | dbl = 1; |
8358c818 ILT |
3093 | s = "daddi"; |
3094 | s2 = "dadd"; | |
3095 | goto do_addi; | |
3096 | case M_DADDU_I: | |
6e8dda9c | 3097 | dbl = 1; |
8358c818 ILT |
3098 | s = "daddiu"; |
3099 | s2 = "daddu"; | |
3100 | do_addi: | |
6e8dda9c | 3101 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3102 | { |
0dd2d296 | 3103 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3104 | (int) BFD_RELOC_LO16); |
670a50eb | 3105 | return; |
3d3c5039 | 3106 | } |
d8a1c247 | 3107 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3108 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3109 | break; |
3d3c5039 ILT |
3110 | |
3111 | case M_AND_I: | |
6e8dda9c ILT |
3112 | s = "andi"; |
3113 | s2 = "and"; | |
3114 | goto do_bit; | |
3d3c5039 | 3115 | case M_OR_I: |
6e8dda9c ILT |
3116 | s = "ori"; |
3117 | s2 = "or"; | |
3118 | goto do_bit; | |
3d3c5039 | 3119 | case M_NOR_I: |
6e8dda9c ILT |
3120 | s = ""; |
3121 | s2 = "nor"; | |
3122 | goto do_bit; | |
3d3c5039 | 3123 | case M_XOR_I: |
6e8dda9c ILT |
3124 | s = "xori"; |
3125 | s2 = "xor"; | |
3126 | do_bit: | |
3127 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3128 | { |
6e8dda9c | 3129 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3130 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3131 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3132 | else |
670a50eb | 3133 | { |
0dd2d296 ILT |
3134 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3135 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3136 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3137 | treg, treg, 0); |
3d3c5039 | 3138 | } |
6e8dda9c | 3139 | return; |
3d3c5039 | 3140 | } |
6e8dda9c | 3141 | |
d8a1c247 | 3142 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3143 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3144 | break; |
3d3c5039 ILT |
3145 | |
3146 | case M_BEQ_I: | |
8358c818 ILT |
3147 | s = "beq"; |
3148 | goto beq_i; | |
3149 | case M_BEQL_I: | |
3150 | s = "beql"; | |
3151 | likely = 1; | |
3152 | goto beq_i; | |
3d3c5039 | 3153 | case M_BNE_I: |
8358c818 ILT |
3154 | s = "bne"; |
3155 | goto beq_i; | |
3156 | case M_BNEL_I: | |
3157 | s = "bnel"; | |
3158 | likely = 1; | |
3159 | beq_i: | |
670a50eb ILT |
3160 | if (imm_expr.X_add_number == 0) |
3161 | { | |
0dd2d296 ILT |
3162 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3163 | 0); | |
670a50eb ILT |
3164 | return; |
3165 | } | |
d8a1c247 | 3166 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3167 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3168 | break; |
3d3c5039 | 3169 | |
8358c818 ILT |
3170 | case M_BGEL: |
3171 | likely = 1; | |
3d3c5039 | 3172 | case M_BGE: |
670a50eb ILT |
3173 | if (treg == 0) |
3174 | { | |
0dd2d296 | 3175 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3176 | likely ? "bgezl" : "bgez", |
3177 | "s,p", sreg); | |
670a50eb | 3178 | return; |
3d3c5039 | 3179 | } |
9a7d824a ILT |
3180 | if (sreg == 0) |
3181 | { | |
0dd2d296 | 3182 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3183 | likely ? "blezl" : "blez", |
3184 | "s,p", treg); | |
9a7d824a ILT |
3185 | return; |
3186 | } | |
0dd2d296 ILT |
3187 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3188 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3189 | likely ? "beql" : "beq", |
3190 | "s,t,p", AT, 0); | |
670a50eb | 3191 | break; |
3d3c5039 | 3192 | |
8358c818 ILT |
3193 | case M_BGTL_I: |
3194 | likely = 1; | |
3d3c5039 | 3195 | case M_BGT_I: |
9a7d824a | 3196 | /* check for > max integer */ |
6e8dda9c ILT |
3197 | maxnum = 0x7fffffff; |
3198 | if (mips_isa >= 3) | |
3199 | { | |
3200 | maxnum <<= 16; | |
3201 | maxnum |= 0xffff; | |
3202 | maxnum <<= 16; | |
3203 | maxnum |= 0xffff; | |
3204 | } | |
7b777690 ILT |
3205 | if (imm_expr.X_add_number >= maxnum |
3206 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3207 | { |
3208 | do_false: | |
3209 | /* result is always false */ | |
8358c818 ILT |
3210 | if (! likely) |
3211 | { | |
3212 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3213 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3214 | } |
3215 | else | |
3216 | { | |
3217 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3218 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3219 | "s,t,p", 0, 0); | |
8358c818 | 3220 | } |
9a7d824a ILT |
3221 | return; |
3222 | } | |
670a50eb ILT |
3223 | imm_expr.X_add_number++; |
3224 | /* FALLTHROUGH */ | |
3d3c5039 | 3225 | case M_BGE_I: |
8358c818 ILT |
3226 | case M_BGEL_I: |
3227 | if (mask == M_BGEL_I) | |
3228 | likely = 1; | |
670a50eb ILT |
3229 | if (imm_expr.X_add_number == 0) |
3230 | { | |
0dd2d296 | 3231 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3232 | likely ? "bgezl" : "bgez", |
3233 | "s,p", sreg); | |
670a50eb | 3234 | return; |
3d3c5039 | 3235 | } |
670a50eb ILT |
3236 | if (imm_expr.X_add_number == 1) |
3237 | { | |
0dd2d296 | 3238 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3239 | likely ? "bgtzl" : "bgtz", |
3240 | "s,p", sreg); | |
670a50eb | 3241 | return; |
3d3c5039 | 3242 | } |
6e8dda9c ILT |
3243 | maxnum = 0x7fffffff; |
3244 | if (mips_isa >= 3) | |
3245 | { | |
3246 | maxnum <<= 16; | |
3247 | maxnum |= 0xffff; | |
3248 | maxnum <<= 16; | |
3249 | maxnum |= 0xffff; | |
3250 | } | |
3251 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3252 | if (imm_expr.X_add_number <= maxnum |
3253 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3254 | { |
3255 | do_true: | |
3256 | /* result is always true */ | |
3257 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3258 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3259 | return; |
3260 | } | |
6e8dda9c | 3261 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3262 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3263 | likely ? "beql" : "beq", |
3264 | "s,t,p", AT, 0); | |
670a50eb | 3265 | break; |
3d3c5039 | 3266 | |
8358c818 ILT |
3267 | case M_BGEUL: |
3268 | likely = 1; | |
3d3c5039 | 3269 | case M_BGEU: |
670a50eb | 3270 | if (treg == 0) |
9a7d824a ILT |
3271 | goto do_true; |
3272 | if (sreg == 0) | |
670a50eb | 3273 | { |
0dd2d296 | 3274 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3275 | likely ? "beql" : "beq", |
3276 | "s,t,p", 0, treg); | |
670a50eb | 3277 | return; |
3d3c5039 | 3278 | } |
0dd2d296 ILT |
3279 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3280 | treg); | |
3281 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3282 | likely ? "beql" : "beq", |
3283 | "s,t,p", AT, 0); | |
670a50eb | 3284 | break; |
3d3c5039 | 3285 | |
8358c818 ILT |
3286 | case M_BGTUL_I: |
3287 | likely = 1; | |
9a7d824a | 3288 | case M_BGTU_I: |
6e8dda9c | 3289 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3290 | goto do_false; |
3291 | imm_expr.X_add_number++; | |
3292 | /* FALLTHROUGH */ | |
3d3c5039 | 3293 | case M_BGEU_I: |
8358c818 ILT |
3294 | case M_BGEUL_I: |
3295 | if (mask == M_BGEUL_I) | |
3296 | likely = 1; | |
670a50eb | 3297 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3298 | goto do_true; |
670a50eb ILT |
3299 | if (imm_expr.X_add_number == 1) |
3300 | { | |
0dd2d296 | 3301 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3302 | likely ? "bnel" : "bne", |
3303 | "s,t,p", sreg, 0); | |
670a50eb | 3304 | return; |
3d3c5039 | 3305 | } |
6e8dda9c | 3306 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3307 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3308 | likely ? "beql" : "beq", |
3309 | "s,t,p", AT, 0); | |
670a50eb | 3310 | break; |
3d3c5039 | 3311 | |
8358c818 ILT |
3312 | case M_BGTL: |
3313 | likely = 1; | |
3d3c5039 | 3314 | case M_BGT: |
670a50eb ILT |
3315 | if (treg == 0) |
3316 | { | |
0dd2d296 | 3317 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3318 | likely ? "bgtzl" : "bgtz", |
3319 | "s,p", sreg); | |
670a50eb | 3320 | return; |
3d3c5039 | 3321 | } |
9a7d824a ILT |
3322 | if (sreg == 0) |
3323 | { | |
0dd2d296 | 3324 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3325 | likely ? "bltzl" : "bltz", |
3326 | "s,p", treg); | |
9a7d824a ILT |
3327 | return; |
3328 | } | |
0dd2d296 ILT |
3329 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3330 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3331 | likely ? "bnel" : "bne", |
3332 | "s,t,p", AT, 0); | |
670a50eb | 3333 | break; |
3d3c5039 | 3334 | |
8358c818 ILT |
3335 | case M_BGTUL: |
3336 | likely = 1; | |
3d3c5039 | 3337 | case M_BGTU: |
670a50eb ILT |
3338 | if (treg == 0) |
3339 | { | |
0dd2d296 | 3340 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3341 | likely ? "bnel" : "bne", |
3342 | "s,t,p", sreg, 0); | |
670a50eb | 3343 | return; |
3d3c5039 | 3344 | } |
9a7d824a ILT |
3345 | if (sreg == 0) |
3346 | goto do_false; | |
0dd2d296 ILT |
3347 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3348 | sreg); | |
3349 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3350 | likely ? "bnel" : "bne", |
3351 | "s,t,p", AT, 0); | |
670a50eb | 3352 | break; |
3d3c5039 | 3353 | |
8358c818 ILT |
3354 | case M_BLEL: |
3355 | likely = 1; | |
3d3c5039 | 3356 | case M_BLE: |
670a50eb ILT |
3357 | if (treg == 0) |
3358 | { | |
0dd2d296 | 3359 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3360 | likely ? "blezl" : "blez", |
3361 | "s,p", sreg); | |
670a50eb ILT |
3362 | return; |
3363 | } | |
9a7d824a ILT |
3364 | if (sreg == 0) |
3365 | { | |
0dd2d296 | 3366 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3367 | likely ? "bgezl" : "bgez", |
3368 | "s,p", treg); | |
9a7d824a ILT |
3369 | return; |
3370 | } | |
0dd2d296 ILT |
3371 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3372 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3373 | likely ? "beql" : "beq", |
3374 | "s,t,p", AT, 0); | |
670a50eb | 3375 | break; |
3d3c5039 | 3376 | |
8358c818 ILT |
3377 | case M_BLEL_I: |
3378 | likely = 1; | |
3d3c5039 | 3379 | case M_BLE_I: |
6e8dda9c ILT |
3380 | maxnum = 0x7fffffff; |
3381 | if (mips_isa >= 3) | |
3382 | { | |
3383 | maxnum <<= 16; | |
3384 | maxnum |= 0xffff; | |
3385 | maxnum <<= 16; | |
3386 | maxnum |= 0xffff; | |
3387 | } | |
7b777690 ILT |
3388 | if (imm_expr.X_add_number >= maxnum |
3389 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3390 | goto do_true; |
3391 | imm_expr.X_add_number++; | |
3392 | /* FALLTHROUGH */ | |
9a7d824a | 3393 | case M_BLT_I: |
8358c818 ILT |
3394 | case M_BLTL_I: |
3395 | if (mask == M_BLTL_I) | |
3396 | likely = 1; | |
670a50eb ILT |
3397 | if (imm_expr.X_add_number == 0) |
3398 | { | |
0dd2d296 | 3399 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3400 | likely ? "bltzl" : "bltz", |
3401 | "s,p", sreg); | |
670a50eb ILT |
3402 | return; |
3403 | } | |
9a7d824a | 3404 | if (imm_expr.X_add_number == 1) |
670a50eb | 3405 | { |
0dd2d296 | 3406 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3407 | likely ? "blezl" : "blez", |
3408 | "s,p", sreg); | |
670a50eb ILT |
3409 | return; |
3410 | } | |
6e8dda9c | 3411 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3412 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3413 | likely ? "bnel" : "bne", |
3414 | "s,t,p", AT, 0); | |
670a50eb | 3415 | break; |
3d3c5039 | 3416 | |
8358c818 ILT |
3417 | case M_BLEUL: |
3418 | likely = 1; | |
3d3c5039 | 3419 | case M_BLEU: |
670a50eb ILT |
3420 | if (treg == 0) |
3421 | { | |
0dd2d296 | 3422 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3423 | likely ? "beql" : "beq", |
3424 | "s,t,p", sreg, 0); | |
670a50eb | 3425 | return; |
3d3c5039 | 3426 | } |
9a7d824a ILT |
3427 | if (sreg == 0) |
3428 | goto do_true; | |
0dd2d296 ILT |
3429 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3430 | sreg); | |
3431 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3432 | likely ? "beql" : "beq", |
3433 | "s,t,p", AT, 0); | |
670a50eb | 3434 | break; |
3d3c5039 | 3435 | |
8358c818 ILT |
3436 | case M_BLEUL_I: |
3437 | likely = 1; | |
3d3c5039 | 3438 | case M_BLEU_I: |
6e8dda9c | 3439 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3440 | goto do_true; |
3441 | imm_expr.X_add_number++; | |
3442 | /* FALLTHROUGH */ | |
9a7d824a | 3443 | case M_BLTU_I: |
8358c818 ILT |
3444 | case M_BLTUL_I: |
3445 | if (mask == M_BLTUL_I) | |
3446 | likely = 1; | |
670a50eb | 3447 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3448 | goto do_false; |
3449 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3450 | { |
0dd2d296 | 3451 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3452 | likely ? "beql" : "beq", |
3453 | "s,t,p", sreg, 0); | |
670a50eb | 3454 | return; |
3d3c5039 | 3455 | } |
6e8dda9c | 3456 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3457 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3458 | likely ? "bnel" : "bne", |
3459 | "s,t,p", AT, 0); | |
670a50eb | 3460 | break; |
3d3c5039 | 3461 | |
8358c818 ILT |
3462 | case M_BLTL: |
3463 | likely = 1; | |
3d3c5039 | 3464 | case M_BLT: |
670a50eb ILT |
3465 | if (treg == 0) |
3466 | { | |
0dd2d296 | 3467 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3468 | likely ? "bltzl" : "bltz", |
3469 | "s,p", sreg); | |
670a50eb | 3470 | return; |
3d3c5039 | 3471 | } |
9a7d824a | 3472 | if (sreg == 0) |
670a50eb | 3473 | { |
0dd2d296 | 3474 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3475 | likely ? "bgtzl" : "bgtz", |
3476 | "s,p", treg); | |
670a50eb | 3477 | return; |
3d3c5039 | 3478 | } |
0dd2d296 ILT |
3479 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3480 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3481 | likely ? "bnel" : "bne", |
3482 | "s,t,p", AT, 0); | |
670a50eb | 3483 | break; |
3d3c5039 | 3484 | |
8358c818 ILT |
3485 | case M_BLTUL: |
3486 | likely = 1; | |
3d3c5039 | 3487 | case M_BLTU: |
670a50eb | 3488 | if (treg == 0) |
9a7d824a ILT |
3489 | goto do_false; |
3490 | if (sreg == 0) | |
670a50eb | 3491 | { |
0dd2d296 | 3492 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3493 | likely ? "bnel" : "bne", |
3494 | "s,t,p", 0, treg); | |
670a50eb ILT |
3495 | return; |
3496 | } | |
0dd2d296 ILT |
3497 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3498 | treg); | |
3499 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3500 | likely ? "bnel" : "bne", |
3501 | "s,t,p", AT, 0); | |
670a50eb | 3502 | break; |
3d3c5039 | 3503 | |
8358c818 ILT |
3504 | case M_DDIV_3: |
3505 | dbl = 1; | |
3d3c5039 | 3506 | case M_DIV_3: |
8358c818 ILT |
3507 | s = "mflo"; |
3508 | goto do_div3; | |
3509 | case M_DREM_3: | |
3510 | dbl = 1; | |
3d3c5039 | 3511 | case M_REM_3: |
8358c818 ILT |
3512 | s = "mfhi"; |
3513 | do_div3: | |
670a50eb ILT |
3514 | if (treg == 0) |
3515 | { | |
3516 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3517 | if (mips_trap) |
3518 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3519 | else | |
3520 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3521 | return; |
3522 | } | |
3523 | ||
fbcfacb7 | 3524 | mips_emit_delays (true); |
becfe05e | 3525 | ++mips_noreorder; |
0dd2d296 ILT |
3526 | mips_any_noreorder = 1; |
3527 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3528 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3529 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3530 | if (mips_trap) |
3531 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3532 | else | |
3533 | { | |
3534 | expr1.X_add_number = 8; | |
3535 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3536 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3537 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3538 | } | |
670a50eb | 3539 | expr1.X_add_number = -1; |
0dd2d296 | 3540 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3541 | dbl ? "daddiu" : "addiu", |
9226253a | 3542 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3543 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3544 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3545 | if (dbl) |
3546 | { | |
3547 | expr1.X_add_number = 1; | |
0dd2d296 | 3548 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3549 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3550 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3551 | 31); | |
8358c818 ILT |
3552 | } |
3553 | else | |
3554 | { | |
3555 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3556 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3557 | (int) BFD_RELOC_HI16); | |
8358c818 | 3558 | } |
8ea7f4e8 ILT |
3559 | if (mips_trap) |
3560 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3561 | else | |
3562 | { | |
3563 | expr1.X_add_number = 8; | |
3564 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3565 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3566 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3567 | } | |
becfe05e | 3568 | --mips_noreorder; |
0dd2d296 | 3569 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3570 | break; |
3d3c5039 ILT |
3571 | |
3572 | case M_DIV_3I: | |
8358c818 ILT |
3573 | s = "div"; |
3574 | s2 = "mflo"; | |
3575 | goto do_divi; | |
3d3c5039 | 3576 | case M_DIVU_3I: |
8358c818 ILT |
3577 | s = "divu"; |
3578 | s2 = "mflo"; | |
3579 | goto do_divi; | |
3d3c5039 | 3580 | case M_REM_3I: |
8358c818 ILT |
3581 | s = "div"; |
3582 | s2 = "mfhi"; | |
3583 | goto do_divi; | |
3d3c5039 | 3584 | case M_REMU_3I: |
8358c818 ILT |
3585 | s = "divu"; |
3586 | s2 = "mfhi"; | |
3587 | goto do_divi; | |
3588 | case M_DDIV_3I: | |
3589 | dbl = 1; | |
3590 | s = "ddiv"; | |
3591 | s2 = "mflo"; | |
3592 | goto do_divi; | |
3593 | case M_DDIVU_3I: | |
3594 | dbl = 1; | |
3595 | s = "ddivu"; | |
3596 | s2 = "mflo"; | |
3597 | goto do_divi; | |
3598 | case M_DREM_3I: | |
3599 | dbl = 1; | |
3600 | s = "ddiv"; | |
3601 | s2 = "mfhi"; | |
3602 | goto do_divi; | |
3603 | case M_DREMU_3I: | |
3604 | dbl = 1; | |
3605 | s = "ddivu"; | |
3606 | s2 = "mfhi"; | |
3607 | do_divi: | |
670a50eb ILT |
3608 | if (imm_expr.X_add_number == 0) |
3609 | { | |
3610 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3611 | if (mips_trap) |
3612 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3613 | else | |
3614 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3615 | return; |
3616 | } | |
3617 | if (imm_expr.X_add_number == 1) | |
3618 | { | |
8358c818 | 3619 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3620 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3621 | sreg); | |
3d3c5039 | 3622 | else |
0dd2d296 | 3623 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3624 | return; |
3625 | } | |
8358c818 ILT |
3626 | if (imm_expr.X_add_number == -1 |
3627 | && s[strlen (s) - 1] != 'u') | |
3628 | { | |
3629 | if (strcmp (s2, "mflo") == 0) | |
3630 | { | |
3631 | if (dbl) | |
0dd2d296 ILT |
3632 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3633 | sreg); | |
8358c818 | 3634 | else |
0dd2d296 ILT |
3635 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3636 | sreg); | |
8358c818 ILT |
3637 | } |
3638 | else | |
0dd2d296 | 3639 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3640 | return; |
3641 | } | |
3d3c5039 | 3642 | |
d8a1c247 | 3643 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3644 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3645 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3646 | break; |
3647 | ||
3648 | case M_DIVU_3: | |
8358c818 ILT |
3649 | s = "divu"; |
3650 | s2 = "mflo"; | |
3651 | goto do_divu3; | |
670a50eb | 3652 | case M_REMU_3: |
8358c818 ILT |
3653 | s = "divu"; |
3654 | s2 = "mfhi"; | |
3655 | goto do_divu3; | |
3656 | case M_DDIVU_3: | |
3657 | s = "ddivu"; | |
3658 | s2 = "mflo"; | |
3659 | goto do_divu3; | |
3660 | case M_DREMU_3: | |
3661 | s = "ddivu"; | |
3662 | s2 = "mfhi"; | |
3663 | do_divu3: | |
fbcfacb7 | 3664 | mips_emit_delays (true); |
becfe05e | 3665 | ++mips_noreorder; |
0dd2d296 ILT |
3666 | mips_any_noreorder = 1; |
3667 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3668 | if (mips_trap) |
3669 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3670 | else | |
3671 | { | |
3672 | expr1.X_add_number = 8; | |
3673 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3674 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3675 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3676 | } | |
becfe05e | 3677 | --mips_noreorder; |
0dd2d296 | 3678 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3679 | return; |
3d3c5039 | 3680 | |
d8a1c247 KR |
3681 | case M_DLA_AB: |
3682 | dbl = 1; | |
0dd2d296 | 3683 | case M_LA_AB: |
d9aba805 ILT |
3684 | /* Load the address of a symbol into a register. If breg is not |
3685 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3686 | |
3687 | /* When generating embedded PIC code, we permit expressions of | |
3688 | the form | |
3689 | la $4,foo-bar | |
3690 | where bar is an address in the .text section. These are used | |
3691 | when getting the addresses of functions. We don't permit | |
3692 | X_add_number to be non-zero, because if the symbol is | |
3693 | external the relaxing code needs to know that any addend is | |
3694 | purely the offset to X_op_symbol. */ | |
3695 | if (mips_pic == EMBEDDED_PIC | |
3696 | && offset_expr.X_op == O_subtract | |
3697 | && now_seg == text_section | |
847a01cd ILT |
3698 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3699 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3700 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3701 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3702 | ->sy_value.X_add_symbol) | |
3703 | == text_section))) | |
ecd4ca1c ILT |
3704 | && breg == 0 |
3705 | && offset_expr.X_add_number == 0) | |
3706 | { | |
3707 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3708 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3709 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3710 | mips_isa < 3 ? "addiu" : "daddiu", | |
3711 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3712 | return; | |
3713 | } | |
3714 | ||
0dd2d296 ILT |
3715 | if (offset_expr.X_op != O_symbol |
3716 | && offset_expr.X_op != O_constant) | |
670a50eb | 3717 | { |
0dd2d296 ILT |
3718 | as_bad ("expression too complex"); |
3719 | offset_expr.X_op = O_constant; | |
3720 | } | |
3721 | ||
3722 | if (treg == breg) | |
3723 | { | |
3724 | tempreg = AT; | |
3725 | used_at = 1; | |
3d3c5039 | 3726 | } |
670a50eb ILT |
3727 | else |
3728 | { | |
0dd2d296 ILT |
3729 | tempreg = treg; |
3730 | used_at = 0; | |
670a50eb | 3731 | } |
3d3c5039 | 3732 | |
5ac34ac3 | 3733 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3734 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3735 | else if (mips_pic == NO_PIC) |
670a50eb | 3736 | { |
0dd2d296 ILT |
3737 | /* If this is a reference to an GP relative symbol, we want |
3738 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3739 | Otherwise we want | |
3740 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3741 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3742 | If we have a constant, we need two instructions anyhow, | |
3743 | so we may as well always use the latter form. */ | |
7a15a226 | 3744 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3745 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3746 | p = NULL; |
3747 | else | |
3748 | { | |
8ea7f4e8 | 3749 | frag_grow (20); |
0dd2d296 ILT |
3750 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3751 | mips_isa < 3 ? "addiu" : "daddiu", | |
3752 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3753 | p = frag_var (rs_machine_dependent, 8, 0, | |
3754 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3755 | mips_warn_about_macros), | |
3756 | offset_expr.X_add_symbol, (long) 0, | |
3757 | (char *) NULL); | |
3758 | } | |
3759 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3760 | if (p != NULL) | |
3761 | p += 4; | |
3762 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3763 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3764 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3765 | } | |
fb251650 | 3766 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3767 | { |
3768 | /* If this is a reference to an external symbol, and there | |
3769 | is no constant, we want | |
3770 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3771 | For a local symbol, we want | |
3772 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3773 | nop | |
3774 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3775 | ||
3776 | If we have a small constant, and this is a reference to | |
3777 | an external symbol, we want | |
3778 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3779 | nop | |
3780 | addiu $tempreg,$tempreg,<constant> | |
3781 | For a local symbol, we want the same instruction | |
3782 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3783 | addiu instruction. | |
3784 | ||
3785 | If we have a large constant, and this is a reference to | |
3786 | an external symbol, we want | |
3787 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3788 | lui $at,<hiconstant> | |
3789 | addiu $at,$at,<loconstant> | |
3790 | addu $tempreg,$tempreg,$at | |
3791 | For a local symbol, we want the same instruction | |
3792 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3793 | addiu instruction. */ | |
3794 | expr1.X_add_number = offset_expr.X_add_number; | |
3795 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3796 | frag_grow (32); |
0dd2d296 | 3797 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3798 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3799 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3800 | if (expr1.X_add_number == 0) | |
3801 | { | |
3802 | int off; | |
3803 | ||
3804 | if (breg == 0) | |
3805 | off = 0; | |
3806 | else | |
3807 | { | |
3808 | /* We're going to put in an addu instruction using | |
3809 | tempreg, so we may as well insert the nop right | |
3810 | now. */ | |
3811 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3812 | "nop", ""); | |
3813 | off = 4; | |
3814 | } | |
3815 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3816 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3817 | (breg == 0 | |
3818 | ? mips_warn_about_macros | |
3819 | : 0)), | |
3820 | offset_expr.X_add_symbol, (long) 0, | |
3821 | (char *) NULL); | |
3822 | if (breg == 0) | |
3823 | { | |
3824 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3825 | p += 4; | |
3826 | } | |
3827 | macro_build (p, &icnt, &expr1, | |
3828 | mips_isa < 3 ? "addiu" : "daddiu", | |
3829 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3830 | /* FIXME: If breg == 0, and the next instruction uses | |
3831 | $tempreg, then if this variant case is used an extra | |
3832 | nop will be generated. */ | |
3833 | } | |
3834 | else if (expr1.X_add_number >= -0x8000 | |
3835 | && expr1.X_add_number < 0x8000) | |
3836 | { | |
3837 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3838 | "nop", ""); | |
3839 | macro_build ((char *) NULL, &icnt, &expr1, | |
3840 | mips_isa < 3 ? "addiu" : "daddiu", | |
3841 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3842 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3843 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3844 | offset_expr.X_add_symbol, (long) 0, | |
3845 | (char *) NULL); | |
3846 | } | |
3847 | else | |
3848 | { | |
3849 | int off1; | |
3850 | ||
3851 | /* If we are going to add in a base register, and the | |
3852 | target register and the base register are the same, | |
3853 | then we are using AT as a temporary register. Since | |
3854 | we want to load the constant into AT, we add our | |
3855 | current AT (from the global offset table) and the | |
3856 | register into the register now, and pretend we were | |
3857 | not using a base register. */ | |
3858 | if (breg != treg) | |
3859 | off1 = 0; | |
3860 | else | |
3861 | { | |
3862 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3863 | "nop", ""); | |
3864 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3865 | mips_isa < 3 ? "addu" : "daddu", | |
3866 | "d,v,t", treg, AT, breg); | |
3867 | breg = 0; | |
3868 | tempreg = treg; | |
3869 | off1 = -8; | |
3870 | } | |
3871 | ||
55933a58 ILT |
3872 | /* Set mips_optimize around the lui instruction to avoid |
3873 | inserting an unnecessary nop after the lw. */ | |
3874 | hold_mips_optimize = mips_optimize; | |
3875 | mips_optimize = 2; | |
0dd2d296 | 3876 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3877 | mips_optimize = hold_mips_optimize; |
3878 | ||
0dd2d296 ILT |
3879 | macro_build ((char *) NULL, &icnt, &expr1, |
3880 | mips_isa < 3 ? "addiu" : "daddiu", | |
3881 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3882 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3883 | mips_isa < 3 ? "addu" : "daddu", | |
3884 | "d,v,t", tempreg, tempreg, AT); | |
3885 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3886 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3887 | offset_expr.X_add_symbol, (long) 0, | |
3888 | (char *) NULL); | |
3889 | used_at = 1; | |
3890 | } | |
670a50eb | 3891 | } |
fb251650 ILT |
3892 | else if (mips_pic == SVR4_PIC) |
3893 | { | |
3894 | int gpdel; | |
3895 | ||
3896 | /* This is the large GOT case. If this is a reference to an | |
3897 | external symbol, and there is no constant, we want | |
3898 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3899 | addu $tempreg,$tempreg,$gp | |
3900 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3901 | For a local symbol, we want | |
3902 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3903 | nop | |
3904 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3905 | ||
3906 | If we have a small constant, and this is a reference to | |
3907 | an external symbol, we want | |
3908 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3909 | addu $tempreg,$tempreg,$gp | |
3910 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3911 | nop | |
3912 | addiu $tempreg,$tempreg,<constant> | |
3913 | For a local symbol, we want | |
3914 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3915 | nop | |
3916 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3917 | ||
3918 | If we have a large constant, and this is a reference to | |
3919 | an external symbol, we want | |
3920 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3921 | addu $tempreg,$tempreg,$gp | |
3922 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3923 | lui $at,<hiconstant> | |
3924 | addiu $at,$at,<loconstant> | |
3925 | addu $tempreg,$tempreg,$at | |
3926 | For a local symbol, we want | |
3927 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3928 | lui $at,<hiconstant> | |
3929 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3930 | addu $tempreg,$tempreg,$at | |
3931 | */ | |
3932 | expr1.X_add_number = offset_expr.X_add_number; | |
3933 | offset_expr.X_add_number = 0; | |
3934 | frag_grow (52); | |
3935 | if (reg_needs_delay (GP)) | |
3936 | gpdel = 4; | |
3937 | else | |
3938 | gpdel = 0; | |
3939 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3940 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3941 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3942 | mips_isa < 3 ? "addu" : "daddu", | |
3943 | "d,v,t", tempreg, tempreg, GP); | |
3944 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3945 | dbl ? "ld" : "lw", | |
3946 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3947 | tempreg); | |
3948 | if (expr1.X_add_number == 0) | |
3949 | { | |
3950 | int off; | |
3951 | ||
3952 | if (breg == 0) | |
3953 | off = 0; | |
3954 | else | |
3955 | { | |
3956 | /* We're going to put in an addu instruction using | |
3957 | tempreg, so we may as well insert the nop right | |
3958 | now. */ | |
3959 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3960 | "nop", ""); | |
3961 | off = 4; | |
3962 | } | |
3963 | ||
3964 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3965 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3966 | 8 + gpdel, 0, | |
3967 | (breg == 0 | |
3968 | ? mips_warn_about_macros | |
3969 | : 0)), | |
3970 | offset_expr.X_add_symbol, (long) 0, | |
3971 | (char *) NULL); | |
3972 | } | |
3973 | else if (expr1.X_add_number >= -0x8000 | |
3974 | && expr1.X_add_number < 0x8000) | |
3975 | { | |
3976 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3977 | "nop", ""); | |
3978 | macro_build ((char *) NULL, &icnt, &expr1, | |
3979 | mips_isa < 3 ? "addiu" : "daddiu", | |
3980 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3981 | ||
3982 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3983 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3984 | (breg == 0 | |
3985 | ? mips_warn_about_macros | |
3986 | : 0)), | |
3987 | offset_expr.X_add_symbol, (long) 0, | |
3988 | (char *) NULL); | |
3989 | } | |
3990 | else | |
3991 | { | |
3992 | int adj, dreg; | |
3993 | ||
3994 | /* If we are going to add in a base register, and the | |
3995 | target register and the base register are the same, | |
3996 | then we are using AT as a temporary register. Since | |
3997 | we want to load the constant into AT, we add our | |
3998 | current AT (from the global offset table) and the | |
3999 | register into the register now, and pretend we were | |
4000 | not using a base register. */ | |
4001 | if (breg != treg) | |
4002 | { | |
4003 | adj = 0; | |
4004 | dreg = tempreg; | |
4005 | } | |
4006 | else | |
4007 | { | |
4008 | assert (tempreg == AT); | |
4009 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4010 | "nop", ""); | |
4011 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4012 | mips_isa < 3 ? "addu" : "daddu", | |
4013 | "d,v,t", treg, AT, breg); | |
4014 | dreg = treg; | |
4015 | adj = 8; | |
4016 | } | |
4017 | ||
4018 | /* Set mips_optimize around the lui instruction to avoid | |
4019 | inserting an unnecessary nop after the lw. */ | |
4020 | hold_mips_optimize = mips_optimize; | |
4021 | mips_optimize = 2; | |
4022 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4023 | mips_optimize = hold_mips_optimize; | |
4024 | ||
4025 | macro_build ((char *) NULL, &icnt, &expr1, | |
4026 | mips_isa < 3 ? "addiu" : "daddiu", | |
4027 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4028 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4029 | mips_isa < 3 ? "addu" : "daddu", | |
4030 | "d,v,t", dreg, dreg, AT); | |
4031 | ||
4032 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4033 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4034 | 8 + gpdel, 0, | |
4035 | (breg == 0 | |
4036 | ? mips_warn_about_macros | |
4037 | : 0)), | |
4038 | offset_expr.X_add_symbol, (long) 0, | |
4039 | (char *) NULL); | |
4040 | ||
4041 | used_at = 1; | |
4042 | } | |
4043 | ||
4044 | if (gpdel > 0) | |
4045 | { | |
4046 | /* This is needed because this instruction uses $gp, but | |
4047 | the first instruction on the main stream does not. */ | |
4048 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4049 | p += 4; | |
4050 | } | |
4051 | macro_build (p, &icnt, &offset_expr, | |
4052 | dbl ? "ld" : "lw", | |
4053 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4054 | p += 4; | |
4055 | if (expr1.X_add_number >= -0x8000 | |
4056 | && expr1.X_add_number < 0x8000) | |
4057 | { | |
4058 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4059 | p += 4; | |
4060 | macro_build (p, &icnt, &expr1, | |
4061 | mips_isa < 3 ? "addiu" : "daddiu", | |
4062 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4063 | /* FIXME: If add_number is 0, and there was no base | |
4064 | register, the external symbol case ended with a load, | |
4065 | so if the symbol turns out to not be external, and | |
4066 | the next instruction uses tempreg, an unnecessary nop | |
4067 | will be inserted. */ | |
4068 | } | |
4069 | else | |
4070 | { | |
4071 | if (breg == treg) | |
4072 | { | |
4073 | /* We must add in the base register now, as in the | |
4074 | external symbol case. */ | |
4075 | assert (tempreg == AT); | |
4076 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4077 | p += 4; | |
4078 | macro_build (p, &icnt, (expressionS *) NULL, | |
4079 | mips_isa < 3 ? "addu" : "daddu", | |
4080 | "d,v,t", treg, AT, breg); | |
4081 | p += 4; | |
4082 | tempreg = treg; | |
4083 | /* We set breg to 0 because we have arranged to add | |
4084 | it in in both cases. */ | |
4085 | breg = 0; | |
4086 | } | |
4087 | ||
4088 | macro_build_lui (p, &icnt, &expr1, AT); | |
4089 | p += 4; | |
4090 | macro_build (p, &icnt, &expr1, | |
4091 | mips_isa < 3 ? "addiu" : "daddiu", | |
4092 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4093 | p += 4; | |
4094 | macro_build (p, &icnt, (expressionS *) NULL, | |
4095 | mips_isa < 3 ? "addu" : "daddu", | |
4096 | "d,v,t", tempreg, tempreg, AT); | |
4097 | p += 4; | |
4098 | } | |
4099 | } | |
d9aba805 ILT |
4100 | else if (mips_pic == EMBEDDED_PIC) |
4101 | { | |
4102 | /* We use | |
4103 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4104 | */ | |
4105 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4106 | mips_isa < 3 ? "addiu" : "daddiu", | |
4107 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4108 | } | |
4109 | else | |
4110 | abort (); | |
0dd2d296 | 4111 | |
670a50eb | 4112 | if (breg != 0) |
0dd2d296 ILT |
4113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4114 | mips_isa < 3 ? "addu" : "daddu", | |
4115 | "d,v,t", treg, tempreg, breg); | |
4116 | ||
4117 | if (! used_at) | |
4118 | return; | |
4119 | ||
4120 | break; | |
4121 | ||
4122 | case M_J_A: | |
4123 | /* The j instruction may not be used in PIC code, since it | |
4124 | requires an absolute address. We convert it to a b | |
4125 | instruction. */ | |
d9aba805 | 4126 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4127 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4128 | else | |
4129 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4130 | return; |
3d3c5039 | 4131 | |
9226253a ILT |
4132 | /* The jal instructions must be handled as macros because when |
4133 | generating PIC code they expand to multi-instruction | |
4134 | sequences. Normally they are simple instructions. */ | |
4135 | case M_JAL_1: | |
4136 | dreg = RA; | |
4137 | /* Fall through. */ | |
4138 | case M_JAL_2: | |
d9aba805 ILT |
4139 | if (mips_pic == NO_PIC |
4140 | || mips_pic == EMBEDDED_PIC) | |
4141 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4142 | "d,s", dreg, sreg); | |
4143 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4144 | { |
d9aba805 ILT |
4145 | if (sreg != PIC_CALL_REG) |
4146 | as_warn ("MIPS PIC call to register other than $25"); | |
4147 | ||
0dd2d296 ILT |
4148 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4149 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4150 | if (mips_cprestore_offset < 0) |
4151 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4152 | else | |
4153 | { | |
4154 | expr1.X_add_number = mips_cprestore_offset; | |
4155 | macro_build ((char *) NULL, &icnt, &expr1, | |
4156 | mips_isa < 3 ? "lw" : "ld", | |
4157 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4158 | } | |
9226253a | 4159 | } |
0dd2d296 | 4160 | else |
d9aba805 ILT |
4161 | abort (); |
4162 | ||
9226253a ILT |
4163 | return; |
4164 | ||
4165 | case M_JAL_A: | |
d9aba805 ILT |
4166 | if (mips_pic == NO_PIC) |
4167 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4168 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4169 | { |
fb251650 ILT |
4170 | /* If this is a reference to an external symbol, and we are |
4171 | using a small GOT, we want | |
d9aba805 ILT |
4172 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4173 | nop | |
4174 | jalr $25 | |
4175 | nop | |
4176 | lw $gp,cprestore($sp) | |
4177 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4178 | pseudo-op. If we are using a big GOT, we want |
4179 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4180 | addu $25,$25,$gp | |
4181 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4182 | nop | |
4183 | jalr $25 | |
4184 | nop | |
4185 | lw $gp,cprestore($sp) | |
4186 | If the symbol is not external, we want | |
d9aba805 ILT |
4187 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4188 | nop | |
4189 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4190 | jalr $25 | |
4191 | nop | |
fb251650 ILT |
4192 | lw $gp,cprestore($sp) */ |
4193 | frag_grow (40); | |
4194 | if (! mips_big_got) | |
4195 | { | |
4196 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4197 | mips_isa < 3 ? "lw" : "ld", | |
4198 | "t,o(b)", PIC_CALL_REG, | |
4199 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4201 | "nop", ""); | |
4202 | p = frag_var (rs_machine_dependent, 4, 0, | |
4203 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4204 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4205 | } | |
4206 | else | |
4207 | { | |
4208 | int gpdel; | |
4209 | ||
4210 | if (reg_needs_delay (GP)) | |
4211 | gpdel = 4; | |
4212 | else | |
4213 | gpdel = 0; | |
4214 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4215 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4216 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4217 | mips_isa < 3 ? "addu" : "daddu", | |
4218 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4219 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4220 | mips_isa < 3 ? "lw" : "ld", | |
4221 | "t,o(b)", PIC_CALL_REG, | |
4222 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4223 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4224 | "nop", ""); | |
4225 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4226 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4227 | 0, 0), | |
4228 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4229 | if (gpdel > 0) | |
4230 | { | |
4231 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4232 | p += 4; | |
4233 | } | |
4234 | macro_build (p, &icnt, &offset_expr, | |
4235 | mips_isa < 3 ? "lw" : "ld", | |
4236 | "t,o(b)", PIC_CALL_REG, | |
4237 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4238 | p += 4; | |
4239 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4240 | p += 4; | |
4241 | } | |
d9aba805 ILT |
4242 | macro_build (p, &icnt, &offset_expr, |
4243 | mips_isa < 3 ? "addiu" : "daddiu", | |
4244 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4245 | (int) BFD_RELOC_LO16); | |
4246 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4247 | "jalr", "s", PIC_CALL_REG); | |
4248 | if (mips_cprestore_offset < 0) | |
4249 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4250 | else | |
4251 | { | |
4252 | if (mips_noreorder) | |
4253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4254 | "nop", ""); | |
4255 | expr1.X_add_number = mips_cprestore_offset; | |
4256 | macro_build ((char *) NULL, &icnt, &expr1, | |
4257 | mips_isa < 3 ? "lw" : "ld", | |
4258 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4259 | mips_frame_reg); | |
4260 | } | |
0dd2d296 | 4261 | } |
d9aba805 | 4262 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4263 | { |
4264 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4265 | /* The linker may expand the call to a longer sequence which | |
4266 | uses $at, so we must break rather than return. */ | |
4267 | break; | |
4268 | } | |
d9aba805 ILT |
4269 | else |
4270 | abort (); | |
4271 | ||
9226253a ILT |
4272 | return; |
4273 | ||
3d3c5039 | 4274 | case M_LB_AB: |
670a50eb ILT |
4275 | s = "lb"; |
4276 | goto ld; | |
3d3c5039 | 4277 | case M_LBU_AB: |
670a50eb ILT |
4278 | s = "lbu"; |
4279 | goto ld; | |
3d3c5039 | 4280 | case M_LH_AB: |
670a50eb ILT |
4281 | s = "lh"; |
4282 | goto ld; | |
3d3c5039 | 4283 | case M_LHU_AB: |
670a50eb ILT |
4284 | s = "lhu"; |
4285 | goto ld; | |
3d3c5039 | 4286 | case M_LW_AB: |
670a50eb ILT |
4287 | s = "lw"; |
4288 | goto ld; | |
3d3c5039 | 4289 | case M_LWC0_AB: |
670a50eb | 4290 | s = "lwc0"; |
8358c818 | 4291 | coproc = 1; |
670a50eb | 4292 | goto ld; |
3d3c5039 | 4293 | case M_LWC1_AB: |
670a50eb | 4294 | s = "lwc1"; |
8358c818 | 4295 | coproc = 1; |
670a50eb | 4296 | goto ld; |
3d3c5039 | 4297 | case M_LWC2_AB: |
670a50eb | 4298 | s = "lwc2"; |
8358c818 | 4299 | coproc = 1; |
670a50eb | 4300 | goto ld; |
3d3c5039 | 4301 | case M_LWC3_AB: |
670a50eb | 4302 | s = "lwc3"; |
8358c818 | 4303 | coproc = 1; |
670a50eb | 4304 | goto ld; |
3d3c5039 | 4305 | case M_LWL_AB: |
670a50eb | 4306 | s = "lwl"; |
b2b8c24e | 4307 | lr = 1; |
670a50eb | 4308 | goto ld; |
3d3c5039 | 4309 | case M_LWR_AB: |
670a50eb | 4310 | s = "lwr"; |
b2b8c24e | 4311 | lr = 1; |
8358c818 ILT |
4312 | goto ld; |
4313 | case M_LDC1_AB: | |
4314 | s = "ldc1"; | |
4315 | coproc = 1; | |
4316 | goto ld; | |
4317 | case M_LDC2_AB: | |
4318 | s = "ldc2"; | |
4319 | coproc = 1; | |
4320 | goto ld; | |
4321 | case M_LDC3_AB: | |
4322 | s = "ldc3"; | |
4323 | coproc = 1; | |
4324 | goto ld; | |
4325 | case M_LDL_AB: | |
4326 | s = "ldl"; | |
b2b8c24e | 4327 | lr = 1; |
8358c818 ILT |
4328 | goto ld; |
4329 | case M_LDR_AB: | |
4330 | s = "ldr"; | |
b2b8c24e | 4331 | lr = 1; |
8358c818 ILT |
4332 | goto ld; |
4333 | case M_LL_AB: | |
4334 | s = "ll"; | |
4335 | goto ld; | |
4336 | case M_LLD_AB: | |
4337 | s = "lld"; | |
4338 | goto ld; | |
4339 | case M_LWU_AB: | |
4340 | s = "lwu"; | |
3d3c5039 | 4341 | ld: |
b2b8c24e | 4342 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4343 | { |
4344 | tempreg = AT; | |
4345 | used_at = 1; | |
4346 | } | |
4347 | else | |
4348 | { | |
4349 | tempreg = treg; | |
4350 | used_at = 0; | |
4351 | } | |
4352 | goto ld_st; | |
3d3c5039 | 4353 | case M_SB_AB: |
670a50eb ILT |
4354 | s = "sb"; |
4355 | goto st; | |
3d3c5039 | 4356 | case M_SH_AB: |
670a50eb ILT |
4357 | s = "sh"; |
4358 | goto st; | |
3d3c5039 | 4359 | case M_SW_AB: |
670a50eb ILT |
4360 | s = "sw"; |
4361 | goto st; | |
3d3c5039 | 4362 | case M_SWC0_AB: |
670a50eb | 4363 | s = "swc0"; |
8358c818 | 4364 | coproc = 1; |
670a50eb | 4365 | goto st; |
3d3c5039 | 4366 | case M_SWC1_AB: |
670a50eb | 4367 | s = "swc1"; |
8358c818 | 4368 | coproc = 1; |
670a50eb | 4369 | goto st; |
3d3c5039 | 4370 | case M_SWC2_AB: |
670a50eb | 4371 | s = "swc2"; |
8358c818 | 4372 | coproc = 1; |
670a50eb | 4373 | goto st; |
3d3c5039 | 4374 | case M_SWC3_AB: |
670a50eb | 4375 | s = "swc3"; |
8358c818 | 4376 | coproc = 1; |
670a50eb | 4377 | goto st; |
3d3c5039 | 4378 | case M_SWL_AB: |
670a50eb ILT |
4379 | s = "swl"; |
4380 | goto st; | |
3d3c5039 | 4381 | case M_SWR_AB: |
670a50eb | 4382 | s = "swr"; |
8358c818 ILT |
4383 | goto st; |
4384 | case M_SC_AB: | |
4385 | s = "sc"; | |
4386 | goto st; | |
4387 | case M_SCD_AB: | |
4388 | s = "scd"; | |
4389 | goto st; | |
4390 | case M_SDC1_AB: | |
4391 | s = "sdc1"; | |
4392 | coproc = 1; | |
4393 | goto st; | |
4394 | case M_SDC2_AB: | |
4395 | s = "sdc2"; | |
4396 | coproc = 1; | |
4397 | goto st; | |
4398 | case M_SDC3_AB: | |
4399 | s = "sdc3"; | |
4400 | coproc = 1; | |
4401 | goto st; | |
4402 | case M_SDL_AB: | |
4403 | s = "sdl"; | |
4404 | goto st; | |
4405 | case M_SDR_AB: | |
4406 | s = "sdr"; | |
3d3c5039 | 4407 | st: |
670a50eb ILT |
4408 | tempreg = AT; |
4409 | used_at = 1; | |
3d3c5039 | 4410 | ld_st: |
8358c818 ILT |
4411 | if (mask == M_LWC1_AB |
4412 | || mask == M_SWC1_AB | |
8358c818 | 4413 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4414 | || mask == M_SDC1_AB |
4415 | || mask == M_L_DAB | |
4416 | || mask == M_S_DAB) | |
670a50eb | 4417 | fmt = "T,o(b)"; |
8358c818 | 4418 | else if (coproc) |
19ed8960 | 4419 | fmt = "E,o(b)"; |
670a50eb ILT |
4420 | else |
4421 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4422 | |
4423 | if (offset_expr.X_op != O_constant | |
4424 | && offset_expr.X_op != O_symbol) | |
4425 | { | |
4426 | as_bad ("expression too complex"); | |
4427 | offset_expr.X_op = O_constant; | |
4428 | } | |
4429 | ||
4430 | /* A constant expression in PIC code can be handled just as it | |
4431 | is in non PIC code. */ | |
d9aba805 | 4432 | if (mips_pic == NO_PIC |
0dd2d296 | 4433 | || offset_expr.X_op == O_constant) |
670a50eb | 4434 | { |
0dd2d296 ILT |
4435 | /* If this is a reference to a GP relative symbol, and there |
4436 | is no base register, we want | |
4437 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4438 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4439 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4440 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4441 | If we have a constant, we need two instructions anyhow, | |
4442 | so we always use the latter form. | |
4443 | ||
4444 | If we have a base register, and this is a reference to a | |
4445 | GP relative symbol, we want | |
4446 | addu $tempreg,$breg,$gp | |
4447 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4448 | Otherwise we want | |
4449 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4450 | addu $tempreg,$tempreg,$breg | |
4451 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4452 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4453 | if (breg == 0) |
4454 | { | |
7a15a226 | 4455 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4456 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4457 | p = NULL; |
4458 | else | |
4459 | { | |
8ea7f4e8 | 4460 | frag_grow (20); |
0dd2d296 ILT |
4461 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4462 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4463 | p = frag_var (rs_machine_dependent, 8, 0, | |
4464 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4465 | (mips_warn_about_macros |
4466 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4467 | offset_expr.X_add_symbol, (long) 0, |
4468 | (char *) NULL); | |
8197b589 | 4469 | used_at = 0; |
0dd2d296 ILT |
4470 | } |
4471 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4472 | if (p != NULL) | |
4473 | p += 4; | |
4474 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4475 | (int) BFD_RELOC_LO16, tempreg); | |
4476 | } | |
4477 | else | |
4478 | { | |
7a15a226 | 4479 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4480 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4481 | p = NULL; |
4482 | else | |
4483 | { | |
8ea7f4e8 | 4484 | frag_grow (28); |
0dd2d296 ILT |
4485 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4486 | mips_isa < 3 ? "addu" : "daddu", | |
4487 | "d,v,t", tempreg, breg, GP); | |
4488 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4489 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4490 | p = frag_var (rs_machine_dependent, 12, 0, | |
4491 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4492 | offset_expr.X_add_symbol, (long) 0, | |
4493 | (char *) NULL); | |
4494 | } | |
4495 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4496 | if (p != NULL) | |
4497 | p += 4; | |
4498 | macro_build (p, &icnt, (expressionS *) NULL, | |
4499 | mips_isa < 3 ? "addu" : "daddu", | |
4500 | "d,v,t", tempreg, tempreg, breg); | |
4501 | if (p != NULL) | |
4502 | p += 4; | |
4503 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4504 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4505 | } |
670a50eb | 4506 | } |
fb251650 | 4507 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4508 | { |
0dd2d296 ILT |
4509 | /* If this is a reference to an external symbol, we want |
4510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4511 | nop | |
4512 | <op> $treg,0($tempreg) | |
4513 | Otherwise we want | |
4514 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4515 | nop | |
4516 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4517 | <op> $treg,0($tempreg) | |
4518 | If there is a base register, we add it to $tempreg before | |
4519 | the <op>. If there is a constant, we stick it in the | |
4520 | <op> instruction. We don't handle constants larger than | |
4521 | 16 bits, because we have no way to load the upper 16 bits | |
4522 | (actually, we could handle them for the subset of cases | |
4523 | in which we are not using $at). */ | |
4524 | assert (offset_expr.X_op == O_symbol); | |
4525 | expr1.X_add_number = offset_expr.X_add_number; | |
4526 | offset_expr.X_add_number = 0; | |
4527 | if (expr1.X_add_number < -0x8000 | |
4528 | || expr1.X_add_number >= 0x8000) | |
4529 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4530 | frag_grow (20); |
0dd2d296 ILT |
4531 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4532 | mips_isa < 3 ? "lw" : "ld", | |
4533 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4534 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4535 | p = frag_var (rs_machine_dependent, 4, 0, | |
4536 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4537 | offset_expr.X_add_symbol, (long) 0, | |
4538 | (char *) NULL); | |
4539 | macro_build (p, &icnt, &offset_expr, | |
4540 | mips_isa < 3 ? "addiu" : "daddiu", | |
4541 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4542 | if (breg != 0) |
0dd2d296 | 4543 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4544 | mips_isa < 3 ? "addu" : "daddu", |
4545 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4546 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4547 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4548 | } |
fb251650 ILT |
4549 | else if (mips_pic == SVR4_PIC) |
4550 | { | |
4551 | int gpdel; | |
4552 | ||
4553 | /* If this is a reference to an external symbol, we want | |
4554 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4555 | addu $tempreg,$tempreg,$gp | |
4556 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4557 | <op> $treg,0($tempreg) | |
4558 | Otherwise we want | |
4559 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4560 | nop | |
4561 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4562 | <op> $treg,0($tempreg) | |
4563 | If there is a base register, we add it to $tempreg before | |
4564 | the <op>. If there is a constant, we stick it in the | |
4565 | <op> instruction. We don't handle constants larger than | |
4566 | 16 bits, because we have no way to load the upper 16 bits | |
4567 | (actually, we could handle them for the subset of cases | |
4568 | in which we are not using $at). */ | |
4569 | assert (offset_expr.X_op == O_symbol); | |
4570 | expr1.X_add_number = offset_expr.X_add_number; | |
4571 | offset_expr.X_add_number = 0; | |
4572 | if (expr1.X_add_number < -0x8000 | |
4573 | || expr1.X_add_number >= 0x8000) | |
4574 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4575 | if (reg_needs_delay (GP)) | |
4576 | gpdel = 4; | |
4577 | else | |
4578 | gpdel = 0; | |
4579 | frag_grow (36); | |
4580 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4581 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4582 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4583 | mips_isa < 3 ? "addu" : "daddu", | |
4584 | "d,v,t", tempreg, tempreg, GP); | |
4585 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4586 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4587 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4588 | tempreg); | |
fb251650 ILT |
4589 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4590 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4591 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4592 | if (gpdel > 0) | |
4593 | { | |
4594 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4595 | p += 4; | |
4596 | } | |
4597 | macro_build (p, &icnt, &offset_expr, | |
4598 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4599 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4600 | p += 4; |
4601 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4602 | p += 4; | |
4603 | macro_build (p, &icnt, &offset_expr, | |
4604 | mips_isa < 3 ? "addiu" : "daddiu", | |
4605 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4606 | if (breg != 0) | |
4607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4608 | mips_isa < 3 ? "addu" : "daddu", | |
4609 | "d,v,t", tempreg, tempreg, breg); | |
4610 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4611 | (int) BFD_RELOC_LO16, tempreg); | |
4612 | } | |
d9aba805 ILT |
4613 | else if (mips_pic == EMBEDDED_PIC) |
4614 | { | |
4615 | /* If there is no base register, we want | |
4616 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4617 | If there is a base register, we want | |
4618 | addu $tempreg,$breg,$gp | |
4619 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4620 | */ | |
4621 | assert (offset_expr.X_op == O_symbol); | |
4622 | if (breg == 0) | |
4623 | { | |
4624 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4625 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4626 | used_at = 0; | |
4627 | } | |
4628 | else | |
4629 | { | |
4630 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4631 | mips_isa < 3 ? "addu" : "daddu", | |
4632 | "d,v,t", tempreg, breg, GP); | |
4633 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4634 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4635 | } | |
4636 | } | |
4637 | else | |
4638 | abort (); | |
0dd2d296 ILT |
4639 | |
4640 | if (! used_at) | |
4641 | return; | |
4642 | ||
4643 | break; | |
3d3c5039 ILT |
4644 | |
4645 | case M_LI: | |
19ed8960 | 4646 | case M_LI_S: |
d8a1c247 KR |
4647 | load_register (&icnt, treg, &imm_expr, 0); |
4648 | return; | |
4649 | ||
4650 | case M_DLI: | |
4651 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4652 | return; |
3d3c5039 | 4653 | |
0dd2d296 | 4654 | case M_LI_SS: |
55933a58 | 4655 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4656 | { |
d8a1c247 | 4657 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4659 | "mtc1", "t,G", AT, treg); | |
4660 | break; | |
0dd2d296 | 4661 | } |
d9aba805 | 4662 | else |
d2c71068 | 4663 | { |
55933a58 ILT |
4664 | assert (offset_expr.X_op == O_symbol |
4665 | && strcmp (segment_name (S_GET_SEGMENT | |
4666 | (offset_expr.X_add_symbol)), | |
4667 | ".lit4") == 0 | |
4668 | && offset_expr.X_add_number == 0); | |
4669 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4670 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4671 | return; |
4672 | } | |
0dd2d296 | 4673 | |
3d3c5039 | 4674 | case M_LI_D: |
d9aba805 ILT |
4675 | /* We know that sym is in the .rdata section. First we get the |
4676 | upper 16 bits of the address. */ | |
4677 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4678 | { |
4679 | /* FIXME: This won't work for a 64 bit address. */ | |
4680 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4681 | } | |
d9aba805 | 4682 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4683 | { |
4684 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4685 | mips_isa < 3 ? "lw" : "ld", | |
4686 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4687 | } | |
d9aba805 ILT |
4688 | else if (mips_pic == EMBEDDED_PIC) |
4689 | { | |
4690 | /* For embedded PIC we pick up the entire address off $gp in | |
4691 | a single instruction. */ | |
4692 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4693 | mips_isa < 3 ? "addiu" : "daddiu", | |
4694 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4695 | offset_expr.X_op = O_constant; | |
4696 | offset_expr.X_add_number = 0; | |
4697 | } | |
4698 | else | |
4699 | abort (); | |
4700 | ||
0dd2d296 | 4701 | /* Now we load the register(s). */ |
8358c818 | 4702 | if (mips_isa >= 3) |
0dd2d296 ILT |
4703 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4704 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4705 | else |
4706 | { | |
0dd2d296 ILT |
4707 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4708 | treg, (int) BFD_RELOC_LO16, AT); | |
4709 | if (treg != 31) | |
4710 | { | |
4711 | /* FIXME: How in the world do we deal with the possible | |
4712 | overflow here? */ | |
4713 | offset_expr.X_add_number += 4; | |
4714 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4715 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4716 | } | |
8358c818 | 4717 | } |
d2c71068 ILT |
4718 | |
4719 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4720 | does not become a variant frag. */ | |
4721 | frag_wane (frag_now); | |
4722 | frag_new (0); | |
4723 | ||
670a50eb | 4724 | break; |
3d3c5039 ILT |
4725 | |
4726 | case M_LI_DD: | |
55933a58 ILT |
4727 | assert (offset_expr.X_op == O_symbol |
4728 | && offset_expr.X_add_number == 0); | |
4729 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4730 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4731 | { |
0dd2d296 ILT |
4732 | if (mips_isa >= 2) |
4733 | { | |
4734 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4735 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4736 | return; | |
4737 | } | |
4738 | breg = GP; | |
4739 | r = BFD_RELOC_MIPS_LITERAL; | |
4740 | goto dob; | |
4741 | } | |
55933a58 | 4742 | else |
0dd2d296 | 4743 | { |
55933a58 ILT |
4744 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4745 | if (mips_pic == SVR4_PIC) | |
4746 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4747 | mips_isa < 3 ? "lw" : "ld", | |
4748 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4749 | else | |
4750 | { | |
4751 | /* FIXME: This won't work for a 64 bit address. */ | |
4752 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4753 | } | |
4754 | ||
0dd2d296 ILT |
4755 | if (mips_isa >= 2) |
4756 | { | |
4757 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4758 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4759 | |
4760 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4761 | that this does not become a variant frag. */ | |
4762 | frag_wane (frag_now); | |
4763 | frag_new (0); | |
4764 | ||
0dd2d296 ILT |
4765 | break; |
4766 | } | |
4767 | breg = AT; | |
4768 | r = BFD_RELOC_LO16; | |
4769 | goto dob; | |
8358c818 | 4770 | } |
9226253a | 4771 | |
3d3c5039 | 4772 | case M_L_DOB: |
9a7d824a ILT |
4773 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4774 | to adjust when loading from memory. */ | |
9226253a ILT |
4775 | r = BFD_RELOC_LO16; |
4776 | dob: | |
8358c818 | 4777 | assert (mips_isa < 2); |
0dd2d296 | 4778 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4779 | target_big_endian ? treg + 1 : treg, |
9226253a | 4780 | (int) r, breg); |
0dd2d296 ILT |
4781 | /* FIXME: A possible overflow which I don't know how to deal |
4782 | with. */ | |
670a50eb | 4783 | offset_expr.X_add_number += 4; |
0dd2d296 | 4784 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4785 | target_big_endian ? treg : treg + 1, |
9226253a | 4786 | (int) r, breg); |
d2c71068 ILT |
4787 | |
4788 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4789 | does not become a variant frag. */ | |
4790 | frag_wane (frag_now); | |
4791 | frag_new (0); | |
4792 | ||
0dd2d296 ILT |
4793 | if (breg != AT) |
4794 | return; | |
4795 | break; | |
3d3c5039 ILT |
4796 | |
4797 | case M_L_DAB: | |
670a50eb ILT |
4798 | /* |
4799 | * The MIPS assembler seems to check for X_add_number not | |
4800 | * being double aligned and generating: | |
4801 | * lui at,%hi(foo+1) | |
4802 | * addu at,at,v1 | |
4803 | * addiu at,at,%lo(foo+1) | |
4804 | * lwc1 f2,0(at) | |
4805 | * lwc1 f3,4(at) | |
4806 | * But, the resulting address is the same after relocation so why | |
4807 | * generate the extra instruction? | |
4808 | */ | |
4032d3f0 | 4809 | coproc = 1; |
0dd2d296 | 4810 | if (mips_isa >= 2) |
670a50eb | 4811 | { |
0dd2d296 ILT |
4812 | s = "ldc1"; |
4813 | goto ld; | |
670a50eb | 4814 | } |
0dd2d296 ILT |
4815 | |
4816 | s = "lwc1"; | |
4817 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4818 | goto ldd_std; |
4819 | ||
4820 | case M_S_DAB: | |
8358c818 | 4821 | if (mips_isa >= 2) |
8358c818 | 4822 | { |
0dd2d296 ILT |
4823 | s = "sdc1"; |
4824 | goto st; | |
8358c818 | 4825 | } |
3d3c5039 | 4826 | |
0dd2d296 ILT |
4827 | s = "swc1"; |
4828 | fmt = "T,o(b)"; | |
4829 | coproc = 1; | |
4830 | goto ldd_std; | |
3d3c5039 ILT |
4831 | |
4832 | case M_LD_AB: | |
0dd2d296 | 4833 | if (mips_isa >= 3) |
670a50eb | 4834 | { |
0dd2d296 ILT |
4835 | s = "ld"; |
4836 | goto ld; | |
670a50eb | 4837 | } |
0dd2d296 ILT |
4838 | |
4839 | s = "lw"; | |
4840 | fmt = "t,o(b)"; | |
4841 | goto ldd_std; | |
4842 | ||
4843 | case M_SD_AB: | |
4844 | if (mips_isa >= 3) | |
670a50eb | 4845 | { |
0dd2d296 ILT |
4846 | s = "sd"; |
4847 | goto st; | |
670a50eb | 4848 | } |
0dd2d296 | 4849 | |
670a50eb | 4850 | s = "sw"; |
0dd2d296 ILT |
4851 | fmt = "t,o(b)"; |
4852 | ||
4853 | ldd_std: | |
4854 | if (offset_expr.X_op != O_symbol | |
4855 | && offset_expr.X_op != O_constant) | |
670a50eb | 4856 | { |
0dd2d296 ILT |
4857 | as_bad ("expression too complex"); |
4858 | offset_expr.X_op = O_constant; | |
4859 | } | |
4860 | ||
4861 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4862 | to adjust when loading from memory. We set coproc if we must | |
4863 | load $fn+1 first. */ | |
b9129c6f | 4864 | if (! target_big_endian) |
0dd2d296 ILT |
4865 | coproc = 0; |
4866 | ||
d9aba805 | 4867 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4868 | || offset_expr.X_op == O_constant) |
4869 | { | |
4870 | /* If this is a reference to a GP relative symbol, we want | |
4871 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4872 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4873 | If we have a base register, we use this | |
4874 | addu $at,$breg,$gp | |
4875 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4876 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4877 | If this is not a GP relative symbol, we want | |
4878 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4879 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4880 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4881 | If there is a base register, we add it to $at after the | |
4882 | lui instruction. If there is a constant, we always use | |
4883 | the last case. */ | |
7a15a226 | 4884 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4885 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4886 | { |
0dd2d296 ILT |
4887 | p = NULL; |
4888 | used_at = 1; | |
670a50eb ILT |
4889 | } |
4890 | else | |
0dd2d296 ILT |
4891 | { |
4892 | int off; | |
4893 | ||
4894 | if (breg == 0) | |
4895 | { | |
8ea7f4e8 | 4896 | frag_grow (28); |
0dd2d296 ILT |
4897 | tempreg = GP; |
4898 | off = 0; | |
4899 | used_at = 0; | |
4900 | } | |
4901 | else | |
4902 | { | |
8ea7f4e8 | 4903 | frag_grow (36); |
0dd2d296 ILT |
4904 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4905 | mips_isa < 3 ? "addu" : "daddu", | |
4906 | "d,v,t", AT, breg, GP); | |
4907 | tempreg = AT; | |
4908 | off = 4; | |
4909 | used_at = 1; | |
4910 | } | |
4911 | ||
4912 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4913 | coproc ? treg + 1 : treg, | |
4914 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4915 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4916 | |
4917 | /* Set mips_optimize to 2 to avoid inserting an | |
4918 | undesired nop. */ | |
4919 | hold_mips_optimize = mips_optimize; | |
4920 | mips_optimize = 2; | |
0dd2d296 ILT |
4921 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4922 | coproc ? treg : treg + 1, | |
4923 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4924 | mips_optimize = hold_mips_optimize; |
4925 | ||
0dd2d296 ILT |
4926 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4927 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4928 | used_at && mips_noat), |
0dd2d296 ILT |
4929 | offset_expr.X_add_symbol, (long) 0, |
4930 | (char *) NULL); | |
777ad64d ILT |
4931 | |
4932 | /* We just generated two relocs. When tc_gen_reloc | |
4933 | handles this case, it will skip the first reloc and | |
4934 | handle the second. The second reloc already has an | |
4935 | extra addend of 4, which we added above. We must | |
4936 | subtract it out, and then subtract another 4 to make | |
4937 | the first reloc come out right. The second reloc | |
4938 | will come out right because we are going to add 4 to | |
4939 | offset_expr when we build its instruction below. */ | |
4940 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4941 | offset_expr.X_op = O_constant; |
4942 | } | |
4943 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4944 | if (p != NULL) | |
4945 | p += 4; | |
4946 | if (breg != 0) | |
4947 | { | |
4948 | macro_build (p, &icnt, (expressionS *) NULL, | |
4949 | mips_isa < 3 ? "addu" : "daddu", | |
4950 | "d,v,t", AT, breg, AT); | |
4951 | if (p != NULL) | |
4952 | p += 4; | |
4953 | } | |
4954 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4955 | coproc ? treg + 1 : treg, | |
4956 | (int) BFD_RELOC_LO16, AT); | |
4957 | if (p != NULL) | |
4958 | p += 4; | |
4959 | /* FIXME: How do we handle overflow here? */ | |
4960 | offset_expr.X_add_number += 4; | |
4961 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4962 | coproc ? treg : treg + 1, | |
4963 | (int) BFD_RELOC_LO16, AT); | |
4964 | } | |
fb251650 | 4965 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4966 | { |
0dd2d296 ILT |
4967 | int off; |
4968 | ||
4969 | /* If this is a reference to an external symbol, we want | |
4970 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4971 | nop | |
4972 | <op> $treg,0($at) | |
4973 | <op> $treg+1,4($at) | |
4974 | Otherwise we want | |
4975 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4976 | nop | |
4977 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4978 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4979 | If there is a base register we add it to $at before the | |
4980 | lwc1 instructions. If there is a constant we include it | |
4981 | in the lwc1 instructions. */ | |
4982 | used_at = 1; | |
4983 | expr1.X_add_number = offset_expr.X_add_number; | |
4984 | offset_expr.X_add_number = 0; | |
4985 | if (expr1.X_add_number < -0x8000 | |
4986 | || expr1.X_add_number >= 0x8000 - 4) | |
4987 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4988 | if (breg == 0) | |
4989 | off = 0; | |
4990 | else | |
4991 | off = 4; | |
8ea7f4e8 | 4992 | frag_grow (24 + off); |
0dd2d296 ILT |
4993 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4994 | mips_isa < 3 ? "lw" : "ld", | |
4995 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4996 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4997 | if (breg != 0) |
0dd2d296 | 4998 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4999 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5000 | "d,v,t", AT, breg, AT); |
5001 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5002 | coproc ? treg + 1 : treg, | |
5003 | (int) BFD_RELOC_LO16, AT); | |
5004 | expr1.X_add_number += 4; | |
55933a58 ILT |
5005 | |
5006 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5007 | nop. */ | |
5008 | hold_mips_optimize = mips_optimize; | |
5009 | mips_optimize = 2; | |
0dd2d296 ILT |
5010 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5011 | coproc ? treg : treg + 1, | |
5012 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5013 | mips_optimize = hold_mips_optimize; |
5014 | ||
0dd2d296 ILT |
5015 | (void) frag_var (rs_machine_dependent, 0, 0, |
5016 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5017 | offset_expr.X_add_symbol, (long) 0, | |
5018 | (char *) NULL); | |
8358c818 | 5019 | } |
fb251650 ILT |
5020 | else if (mips_pic == SVR4_PIC) |
5021 | { | |
5022 | int gpdel, off; | |
5023 | ||
5024 | /* If this is a reference to an external symbol, we want | |
5025 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5026 | addu $at,$at,$gp | |
5027 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5028 | nop | |
5029 | <op> $treg,0($at) | |
5030 | <op> $treg+1,4($at) | |
5031 | Otherwise we want | |
5032 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5033 | nop | |
5034 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5035 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5036 | If there is a base register we add it to $at before the | |
5037 | lwc1 instructions. If there is a constant we include it | |
5038 | in the lwc1 instructions. */ | |
5039 | used_at = 1; | |
5040 | expr1.X_add_number = offset_expr.X_add_number; | |
5041 | offset_expr.X_add_number = 0; | |
5042 | if (expr1.X_add_number < -0x8000 | |
5043 | || expr1.X_add_number >= 0x8000 - 4) | |
5044 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5045 | if (reg_needs_delay (GP)) | |
5046 | gpdel = 4; | |
5047 | else | |
5048 | gpdel = 0; | |
5049 | if (breg == 0) | |
5050 | off = 0; | |
5051 | else | |
5052 | off = 4; | |
5053 | frag_grow (56); | |
5054 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5055 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5056 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5057 | mips_isa < 3 ? "addu" : "daddu", | |
5058 | "d,v,t", AT, AT, GP); | |
5059 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5060 | mips_isa < 3 ? "lw" : "ld", | |
5061 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5063 | if (breg != 0) | |
5064 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5065 | mips_isa < 3 ? "addu" : "daddu", | |
5066 | "d,v,t", AT, breg, AT); | |
5067 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5068 | coproc ? treg + 1 : treg, | |
5069 | (int) BFD_RELOC_LO16, AT); | |
5070 | expr1.X_add_number += 4; | |
5071 | ||
5072 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5073 | nop. */ | |
5074 | hold_mips_optimize = mips_optimize; | |
5075 | mips_optimize = 2; | |
5076 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5077 | coproc ? treg : treg + 1, | |
5078 | (int) BFD_RELOC_LO16, AT); | |
5079 | mips_optimize = hold_mips_optimize; | |
5080 | expr1.X_add_number -= 4; | |
5081 | ||
5082 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5083 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5084 | 8 + gpdel + off, 1, 0), | |
5085 | offset_expr.X_add_symbol, (long) 0, | |
5086 | (char *) NULL); | |
5087 | if (gpdel > 0) | |
5088 | { | |
5089 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5090 | p += 4; | |
5091 | } | |
5092 | macro_build (p, &icnt, &offset_expr, | |
5093 | mips_isa < 3 ? "lw" : "ld", | |
5094 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5095 | p += 4; | |
5096 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5097 | p += 4; | |
5098 | if (breg != 0) | |
5099 | { | |
5100 | macro_build (p, &icnt, (expressionS *) NULL, | |
5101 | mips_isa < 3 ? "addu" : "daddu", | |
5102 | "d,v,t", AT, breg, AT); | |
5103 | p += 4; | |
5104 | } | |
5105 | macro_build (p, &icnt, &expr1, s, fmt, | |
5106 | coproc ? treg + 1 : treg, | |
5107 | (int) BFD_RELOC_LO16, AT); | |
5108 | p += 4; | |
5109 | expr1.X_add_number += 4; | |
5110 | ||
5111 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5112 | nop. */ | |
5113 | hold_mips_optimize = mips_optimize; | |
5114 | mips_optimize = 2; | |
5115 | macro_build (p, &icnt, &expr1, s, fmt, | |
5116 | coproc ? treg : treg + 1, | |
5117 | (int) BFD_RELOC_LO16, AT); | |
5118 | mips_optimize = hold_mips_optimize; | |
5119 | } | |
d9aba805 ILT |
5120 | else if (mips_pic == EMBEDDED_PIC) |
5121 | { | |
5122 | /* If there is no base register, we use | |
5123 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5124 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5125 | If we have a base register, we use | |
5126 | addu $at,$breg,$gp | |
5127 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5128 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5129 | */ | |
5130 | if (breg == 0) | |
5131 | { | |
5132 | tempreg = GP; | |
5133 | used_at = 0; | |
5134 | } | |
5135 | else | |
5136 | { | |
5137 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5138 | mips_isa < 3 ? "addu" : "daddu", | |
5139 | "d,v,t", AT, breg, GP); | |
5140 | tempreg = AT; | |
5141 | used_at = 1; | |
5142 | } | |
5143 | ||
5144 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5145 | coproc ? treg + 1 : treg, | |
5146 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5147 | offset_expr.X_add_number += 4; | |
5148 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5149 | coproc ? treg : treg + 1, | |
5150 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5151 | } | |
5152 | else | |
5153 | abort (); | |
0dd2d296 ILT |
5154 | |
5155 | if (! used_at) | |
5156 | return; | |
5157 | ||
5158 | break; | |
5159 | ||
5160 | case M_LD_OB: | |
5161 | s = "lw"; | |
5162 | goto sd_ob; | |
5163 | case M_SD_OB: | |
5164 | s = "sw"; | |
5165 | sd_ob: | |
5166 | assert (mips_isa < 3); | |
5167 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5168 | (int) BFD_RELOC_LO16, breg); | |
5169 | offset_expr.X_add_number += 4; | |
5170 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5171 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5172 | return; |
917fae09 SS |
5173 | #ifdef LOSING_COMPILER |
5174 | default: | |
5175 | macro2 (ip); | |
5176 | return; | |
5177 | } | |
5178 | if (mips_noat) | |
5179 | as_warn ("Macro used $at after \".set noat\""); | |
5180 | } | |
5181 | ||
5182 | static void | |
5183 | macro2 (ip) | |
5184 | struct mips_cl_insn *ip; | |
5185 | { | |
5186 | register int treg, sreg, dreg, breg; | |
5187 | int tempreg; | |
5188 | int mask; | |
5189 | int icnt = 0; | |
5190 | int used_at; | |
5191 | expressionS expr1; | |
5192 | const char *s; | |
5193 | const char *s2; | |
5194 | const char *fmt; | |
5195 | int likely = 0; | |
5196 | int dbl = 0; | |
5197 | int coproc = 0; | |
adcf2b9d ILT |
5198 | int lr = 0; |
5199 | int off; | |
917fae09 SS |
5200 | offsetT maxnum; |
5201 | bfd_reloc_code_real_type r; | |
5202 | char *p; | |
5203 | ||
5204 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5205 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5206 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5207 | mask = ip->insn_mo->mask; | |
5208 | ||
5209 | expr1.X_op = O_constant; | |
5210 | expr1.X_op_symbol = NULL; | |
5211 | expr1.X_add_symbol = NULL; | |
5212 | expr1.X_add_number = 1; | |
5213 | ||
5214 | switch (mask) | |
5215 | { | |
5216 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5217 | |
8358c818 ILT |
5218 | case M_DMUL: |
5219 | dbl = 1; | |
3d3c5039 | 5220 | case M_MUL: |
0dd2d296 | 5221 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5222 | dbl ? "dmultu" : "multu", |
5223 | "s,t", sreg, treg); | |
0dd2d296 | 5224 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5225 | return; |
3d3c5039 | 5226 | |
8358c818 ILT |
5227 | case M_DMUL_I: |
5228 | dbl = 1; | |
3d3c5039 | 5229 | case M_MUL_I: |
8358c818 ILT |
5230 | /* The MIPS assembler some times generates shifts and adds. I'm |
5231 | not trying to be that fancy. GCC should do this for us | |
5232 | anyway. */ | |
d8a1c247 | 5233 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5234 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5235 | dbl ? "dmult" : "mult", |
5236 | "s,t", sreg, AT); | |
0dd2d296 | 5237 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5238 | break; |
3d3c5039 | 5239 | |
8358c818 ILT |
5240 | case M_DMULO: |
5241 | dbl = 1; | |
5242 | case M_MULO: | |
fbcfacb7 | 5243 | mips_emit_delays (true); |
8358c818 | 5244 | ++mips_noreorder; |
0dd2d296 ILT |
5245 | mips_any_noreorder = 1; |
5246 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5247 | dbl ? "dmult" : "mult", |
5248 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5249 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5250 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5251 | dbl ? "dsra32" : "sra", |
5252 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5253 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5254 | if (mips_trap) |
5255 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5256 | else | |
5257 | { | |
5258 | expr1.X_add_number = 8; | |
5259 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5260 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5261 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5262 | } | |
8358c818 | 5263 | --mips_noreorder; |
0dd2d296 | 5264 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5265 | break; |
5266 | ||
5267 | case M_DMULOU: | |
5268 | dbl = 1; | |
5269 | case M_MULOU: | |
fbcfacb7 | 5270 | mips_emit_delays (true); |
8358c818 | 5271 | ++mips_noreorder; |
0dd2d296 ILT |
5272 | mips_any_noreorder = 1; |
5273 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5274 | dbl ? "dmultu" : "multu", |
5275 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5276 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5277 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5278 | if (mips_trap) |
5279 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5280 | else | |
5281 | { | |
5282 | expr1.X_add_number = 8; | |
5283 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5284 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5285 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5286 | } | |
8358c818 ILT |
5287 | --mips_noreorder; |
5288 | break; | |
5289 | ||
3d3c5039 | 5290 | case M_ROL: |
0dd2d296 ILT |
5291 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5292 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5293 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5294 | treg); | |
5295 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5296 | break; |
3d3c5039 ILT |
5297 | |
5298 | case M_ROL_I: | |
0dd2d296 | 5299 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5300 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5301 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5302 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5303 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5304 | break; |
3d3c5039 ILT |
5305 | |
5306 | case M_ROR: | |
0dd2d296 ILT |
5307 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5308 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5309 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5310 | treg); | |
5311 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5312 | break; |
3d3c5039 ILT |
5313 | |
5314 | case M_ROR_I: | |
0dd2d296 | 5315 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5316 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5317 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5318 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5319 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5320 | break; |
3d3c5039 ILT |
5321 | |
5322 | case M_S_DOB: | |
8358c818 | 5323 | assert (mips_isa < 2); |
9a7d824a ILT |
5324 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5325 | to adjust when storing to memory. */ | |
0dd2d296 | 5326 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5327 | target_big_endian ? treg + 1 : treg, |
9226253a | 5328 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5329 | offset_expr.X_add_number += 4; |
0dd2d296 | 5330 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5331 | target_big_endian ? treg : treg + 1, |
9226253a | 5332 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5333 | return; |
3d3c5039 | 5334 | |
3d3c5039 | 5335 | case M_SEQ: |
670a50eb | 5336 | if (sreg == 0) |
0dd2d296 ILT |
5337 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5338 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5339 | else if (treg == 0) |
0dd2d296 ILT |
5340 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5341 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5342 | else |
5343 | { | |
0dd2d296 ILT |
5344 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5345 | sreg, treg); | |
5346 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5347 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5348 | } |
670a50eb | 5349 | return; |
3d3c5039 ILT |
5350 | |
5351 | case M_SEQ_I: | |
670a50eb ILT |
5352 | if (imm_expr.X_add_number == 0) |
5353 | { | |
0dd2d296 ILT |
5354 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5355 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5356 | return; |
3d3c5039 | 5357 | } |
670a50eb ILT |
5358 | if (sreg == 0) |
5359 | { | |
9a7d824a | 5360 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5361 | ip->insn_mo->name); |
0dd2d296 | 5362 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5363 | return; |
3d3c5039 | 5364 | } |
6e8dda9c | 5365 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5366 | { |
0dd2d296 ILT |
5367 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5368 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5369 | used_at = 0; |
6e8dda9c ILT |
5370 | } |
5371 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5372 | { | |
5373 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5374 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5375 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5376 | "t,r,j", dreg, sreg, |
5377 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5378 | used_at = 0; |
5379 | } | |
5380 | else | |
5381 | { | |
d8a1c247 | 5382 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5383 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5384 | sreg, AT); | |
670a50eb ILT |
5385 | used_at = 1; |
5386 | } | |
0dd2d296 | 5387 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5388 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5389 | if (used_at) |
5390 | break; | |
5391 | return; | |
3d3c5039 ILT |
5392 | |
5393 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5394 | s = "slt"; |
5395 | goto sge; | |
3d3c5039 | 5396 | case M_SGEU: |
670a50eb | 5397 | s = "sltu"; |
3d3c5039 | 5398 | sge: |
0dd2d296 ILT |
5399 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5400 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5401 | (int) BFD_RELOC_LO16); |
670a50eb | 5402 | return; |
3d3c5039 | 5403 | |
670a50eb | 5404 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5405 | case M_SGEU_I: |
6e8dda9c | 5406 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5407 | { |
0dd2d296 | 5408 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5409 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5410 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5411 | used_at = 0; |
5412 | } | |
5413 | else | |
5414 | { | |
d8a1c247 | 5415 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5416 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5417 | mask == M_SGE_I ? "slt" : "sltu", |
5418 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5419 | used_at = 1; |
5420 | } | |
0dd2d296 | 5421 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5422 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5423 | if (used_at) |
5424 | break; | |
5425 | return; | |
3d3c5039 ILT |
5426 | |
5427 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5428 | s = "slt"; |
5429 | goto sgt; | |
3d3c5039 | 5430 | case M_SGTU: |
670a50eb | 5431 | s = "sltu"; |
3d3c5039 | 5432 | sgt: |
0dd2d296 | 5433 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5434 | return; |
3d3c5039 | 5435 | |
670a50eb ILT |
5436 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5437 | s = "slt"; | |
5438 | goto sgti; | |
3d3c5039 | 5439 | case M_SGTU_I: |
670a50eb | 5440 | s = "sltu"; |
3d3c5039 | 5441 | sgti: |
d8a1c247 | 5442 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5443 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5444 | break; |
3d3c5039 | 5445 | |
670a50eb ILT |
5446 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5447 | s = "slt"; | |
5448 | goto sle; | |
3d3c5039 | 5449 | case M_SLEU: |
670a50eb | 5450 | s = "sltu"; |
3d3c5039 | 5451 | sle: |
0dd2d296 ILT |
5452 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5453 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5454 | (int) BFD_RELOC_LO16); |
670a50eb | 5455 | return; |
3d3c5039 | 5456 | |
670a50eb ILT |
5457 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5458 | s = "slt"; | |
5459 | goto slei; | |
3d3c5039 | 5460 | case M_SLEU_I: |
670a50eb | 5461 | s = "sltu"; |
3d3c5039 | 5462 | slei: |
d8a1c247 | 5463 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5464 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5465 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5466 | (int) BFD_RELOC_LO16); |
670a50eb | 5467 | break; |
3d3c5039 ILT |
5468 | |
5469 | case M_SLT_I: | |
6e8dda9c | 5470 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5471 | { |
0dd2d296 ILT |
5472 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5473 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5474 | return; |
3d3c5039 | 5475 | } |
d8a1c247 | 5476 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5477 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5478 | break; |
3d3c5039 ILT |
5479 | |
5480 | case M_SLTU_I: | |
6e8dda9c | 5481 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5482 | { |
0dd2d296 ILT |
5483 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5484 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5485 | return; |
3d3c5039 | 5486 | } |
d8a1c247 | 5487 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5488 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5489 | AT); | |
670a50eb | 5490 | break; |
3d3c5039 ILT |
5491 | |
5492 | case M_SNE: | |
670a50eb | 5493 | if (sreg == 0) |
0dd2d296 ILT |
5494 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5495 | treg); | |
670a50eb | 5496 | else if (treg == 0) |
0dd2d296 ILT |
5497 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5498 | sreg); | |
670a50eb ILT |
5499 | else |
5500 | { | |
0dd2d296 ILT |
5501 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5502 | sreg, treg); | |
5503 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5504 | dreg); | |
3d3c5039 | 5505 | } |
670a50eb | 5506 | return; |
3d3c5039 ILT |
5507 | |
5508 | case M_SNE_I: | |
670a50eb ILT |
5509 | if (imm_expr.X_add_number == 0) |
5510 | { | |
0dd2d296 ILT |
5511 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5512 | sreg); | |
670a50eb | 5513 | return; |
3d3c5039 | 5514 | } |
670a50eb ILT |
5515 | if (sreg == 0) |
5516 | { | |
9a7d824a | 5517 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5518 | ip->insn_mo->name); |
0dd2d296 | 5519 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5520 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5521 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5522 | return; |
3d3c5039 | 5523 | } |
6e8dda9c | 5524 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5525 | { |
0dd2d296 ILT |
5526 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5527 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5528 | used_at = 0; |
6e8dda9c ILT |
5529 | } |
5530 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5531 | { | |
5532 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5533 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5534 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5535 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5536 | used_at = 0; |
5537 | } | |
5538 | else | |
5539 | { | |
d8a1c247 | 5540 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5541 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5542 | sreg, AT); | |
670a50eb ILT |
5543 | used_at = 1; |
5544 | } | |
0dd2d296 | 5545 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5546 | if (used_at) |
5547 | break; | |
5548 | return; | |
3d3c5039 | 5549 | |
8358c818 ILT |
5550 | case M_DSUB_I: |
5551 | dbl = 1; | |
3d3c5039 | 5552 | case M_SUB_I: |
6e8dda9c | 5553 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5554 | { |
5555 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5556 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5557 | dbl ? "daddi" : "addi", |
9226253a | 5558 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5559 | return; |
3d3c5039 | 5560 | } |
d8a1c247 | 5561 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5562 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5563 | dbl ? "dsub" : "sub", |
5564 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5565 | break; |
3d3c5039 | 5566 | |
8358c818 ILT |
5567 | case M_DSUBU_I: |
5568 | dbl = 1; | |
3d3c5039 | 5569 | case M_SUBU_I: |
6e8dda9c | 5570 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5571 | { |
5572 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5573 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5574 | dbl ? "daddiu" : "addiu", |
9226253a | 5575 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5576 | return; |
3d3c5039 | 5577 | } |
d8a1c247 | 5578 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5579 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5580 | dbl ? "dsubu" : "subu", |
5581 | "d,v,t", dreg, sreg, AT); | |
5582 | break; | |
5583 | ||
5584 | case M_TEQ_I: | |
5585 | s = "teq"; | |
5586 | goto trap; | |
5587 | case M_TGE_I: | |
5588 | s = "tge"; | |
5589 | goto trap; | |
5590 | case M_TGEU_I: | |
5591 | s = "tgeu"; | |
5592 | goto trap; | |
5593 | case M_TLT_I: | |
5594 | s = "tlt"; | |
5595 | goto trap; | |
5596 | case M_TLTU_I: | |
5597 | s = "tltu"; | |
5598 | goto trap; | |
5599 | case M_TNE_I: | |
5600 | s = "tne"; | |
5601 | trap: | |
d8a1c247 | 5602 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5603 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5604 | break; |
3d3c5039 ILT |
5605 | |
5606 | case M_TRUNCWD: | |
5607 | case M_TRUNCWS: | |
8358c818 | 5608 | assert (mips_isa < 2); |
670a50eb ILT |
5609 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5610 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5611 | ||
5612 | /* | |
5613 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5614 | * or is there a reason for it? | |
5615 | */ | |
fbcfacb7 | 5616 | mips_emit_delays (true); |
becfe05e | 5617 | ++mips_noreorder; |
0dd2d296 ILT |
5618 | mips_any_noreorder = 1; |
5619 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5620 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5621 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5622 | expr1.X_add_number = 3; |
0dd2d296 | 5623 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5624 | (int) BFD_RELOC_LO16); |
670a50eb | 5625 | expr1.X_add_number = 2; |
0dd2d296 | 5626 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5627 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5628 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5629 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5630 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5631 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5632 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5633 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5634 | --mips_noreorder; |
670a50eb | 5635 | break; |
3d3c5039 ILT |
5636 | |
5637 | case M_ULH: | |
670a50eb ILT |
5638 | s = "lb"; |
5639 | goto ulh; | |
3d3c5039 | 5640 | case M_ULHU: |
670a50eb | 5641 | s = "lbu"; |
3d3c5039 | 5642 | ulh: |
8ea7f4e8 ILT |
5643 | if (offset_expr.X_add_number >= 0x7fff) |
5644 | as_bad ("operand overflow"); | |
670a50eb | 5645 | /* avoid load delay */ |
b9129c6f | 5646 | if (! target_big_endian) |
8ea7f4e8 | 5647 | offset_expr.X_add_number += 1; |
0dd2d296 | 5648 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5649 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5650 | if (! target_big_endian) |
8ea7f4e8 ILT |
5651 | offset_expr.X_add_number -= 1; |
5652 | else | |
5653 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5654 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5655 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5656 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5657 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5658 | break; |
3d3c5039 | 5659 | |
adcf2b9d ILT |
5660 | case M_ULD: |
5661 | s = "ldl"; | |
5662 | s2 = "ldr"; | |
5663 | off = 7; | |
5664 | goto ulw; | |
3d3c5039 | 5665 | case M_ULW: |
adcf2b9d ILT |
5666 | s = "lwl"; |
5667 | s2 = "lwr"; | |
5668 | off = 3; | |
5669 | ulw: | |
5670 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5671 | as_bad ("operand overflow"); |
b9129c6f | 5672 | if (! target_big_endian) |
adcf2b9d ILT |
5673 | offset_expr.X_add_number += off; |
5674 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5675 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5676 | if (! target_big_endian) |
adcf2b9d | 5677 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5678 | else |
adcf2b9d ILT |
5679 | offset_expr.X_add_number += off; |
5680 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5681 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5682 | return; |
3d3c5039 | 5683 | |
adcf2b9d ILT |
5684 | case M_ULD_A: |
5685 | s = "ldl"; | |
5686 | s2 = "ldr"; | |
5687 | off = 7; | |
5688 | goto ulwa; | |
5689 | case M_ULW_A: | |
5690 | s = "lwl"; | |
5691 | s2 = "lwr"; | |
5692 | off = 3; | |
5693 | ulwa: | |
5694 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5695 | if (breg != 0) |
5696 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5697 | mips_isa < 3 ? "addu" : "daddu", | |
5698 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5699 | if (! target_big_endian) |
adcf2b9d ILT |
5700 | expr1.X_add_number = off; |
5701 | else | |
5702 | expr1.X_add_number = 0; | |
5703 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5704 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5705 | if (! target_big_endian) |
adcf2b9d ILT |
5706 | expr1.X_add_number = 0; |
5707 | else | |
5708 | expr1.X_add_number = off; | |
5709 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5710 | (int) BFD_RELOC_LO16, AT); | |
5711 | break; | |
5712 | ||
3d3c5039 ILT |
5713 | case M_ULH_A: |
5714 | case M_ULHU_A: | |
0dd2d296 | 5715 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5716 | if (breg != 0) |
5717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5718 | mips_isa < 3 ? "addu" : "daddu", | |
5719 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5720 | if (target_big_endian) |
adcf2b9d ILT |
5721 | expr1.X_add_number = 0; |
5722 | macro_build ((char *) NULL, &icnt, &expr1, | |
5723 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5724 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5725 | if (target_big_endian) |
adcf2b9d | 5726 | expr1.X_add_number = 1; |
670a50eb | 5727 | else |
adcf2b9d ILT |
5728 | expr1.X_add_number = 0; |
5729 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5730 | (int) BFD_RELOC_LO16, AT); | |
5731 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5732 | treg, 8); | |
5733 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5734 | treg, AT); | |
670a50eb | 5735 | break; |
3d3c5039 ILT |
5736 | |
5737 | case M_USH: | |
8ea7f4e8 ILT |
5738 | if (offset_expr.X_add_number >= 0x7fff) |
5739 | as_bad ("operand overflow"); | |
b9129c6f | 5740 | if (target_big_endian) |
8ea7f4e8 | 5741 | offset_expr.X_add_number += 1; |
0dd2d296 | 5742 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5743 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5744 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5745 | if (target_big_endian) |
8ea7f4e8 ILT |
5746 | offset_expr.X_add_number -= 1; |
5747 | else | |
5748 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5749 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5750 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5751 | break; |
3d3c5039 | 5752 | |
adcf2b9d ILT |
5753 | case M_USD: |
5754 | s = "sdl"; | |
5755 | s2 = "sdr"; | |
5756 | off = 7; | |
5757 | goto usw; | |
3d3c5039 | 5758 | case M_USW: |
adcf2b9d ILT |
5759 | s = "swl"; |
5760 | s2 = "swr"; | |
5761 | off = 3; | |
5762 | usw: | |
5763 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5764 | as_bad ("operand overflow"); |
b9129c6f | 5765 | if (! target_big_endian) |
adcf2b9d ILT |
5766 | offset_expr.X_add_number += off; |
5767 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5768 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5769 | if (! target_big_endian) |
adcf2b9d | 5770 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5771 | else |
adcf2b9d ILT |
5772 | offset_expr.X_add_number += off; |
5773 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5774 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5775 | return; |
3d3c5039 | 5776 | |
adcf2b9d ILT |
5777 | case M_USD_A: |
5778 | s = "sdl"; | |
5779 | s2 = "sdr"; | |
5780 | off = 7; | |
5781 | goto uswa; | |
3d3c5039 | 5782 | case M_USW_A: |
adcf2b9d ILT |
5783 | s = "swl"; |
5784 | s2 = "swr"; | |
5785 | off = 3; | |
5786 | uswa: | |
0dd2d296 | 5787 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5788 | if (breg != 0) |
5789 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5790 | mips_isa < 3 ? "addu" : "daddu", | |
5791 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5792 | if (! target_big_endian) |
adcf2b9d | 5793 | expr1.X_add_number = off; |
670a50eb | 5794 | else |
adcf2b9d ILT |
5795 | expr1.X_add_number = 0; |
5796 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5797 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5798 | if (! target_big_endian) |
adcf2b9d ILT |
5799 | expr1.X_add_number = 0; |
5800 | else | |
5801 | expr1.X_add_number = off; | |
5802 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5803 | (int) BFD_RELOC_LO16, AT); | |
5804 | break; | |
5805 | ||
5806 | case M_USH_A: | |
5807 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5808 | if (breg != 0) |
5809 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5810 | mips_isa < 3 ? "addu" : "daddu", | |
5811 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5812 | if (! target_big_endian) |
adcf2b9d ILT |
5813 | expr1.X_add_number = 0; |
5814 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5815 | (int) BFD_RELOC_LO16, AT); | |
5816 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5817 | treg, 8); | |
b9129c6f | 5818 | if (! target_big_endian) |
adcf2b9d ILT |
5819 | expr1.X_add_number = 1; |
5820 | else | |
5821 | expr1.X_add_number = 0; | |
5822 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5823 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5824 | if (! target_big_endian) |
adcf2b9d ILT |
5825 | expr1.X_add_number = 0; |
5826 | else | |
5827 | expr1.X_add_number = 1; | |
5828 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5829 | (int) BFD_RELOC_LO16, AT); | |
5830 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5831 | treg, 8); | |
5832 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5833 | treg, AT); | |
670a50eb | 5834 | break; |
3d3c5039 ILT |
5835 | |
5836 | default: | |
670a50eb | 5837 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5838 | break; |
3d3c5039 | 5839 | } |
670a50eb ILT |
5840 | if (mips_noat) |
5841 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5842 | } |
5843 | ||
cc5703cd | 5844 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5845 | |
3d3c5039 | 5846 | static void |
cc5703cd | 5847 | mips16_macro (ip) |
3d3c5039 ILT |
5848 | struct mips_cl_insn *ip; |
5849 | { | |
cc5703cd ILT |
5850 | int mask; |
5851 | int xreg, yreg, zreg, tmp; | |
5852 | int icnt; | |
5853 | expressionS expr1; | |
5854 | int dbl; | |
5855 | const char *s, *s2, *s3; | |
3d3c5039 | 5856 | |
cc5703cd | 5857 | mask = ip->insn_mo->mask; |
3d3c5039 | 5858 | |
cc5703cd ILT |
5859 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5860 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5861 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5862 | |
cc5703cd | 5863 | icnt = 0; |
8358c818 | 5864 | |
cc5703cd ILT |
5865 | expr1.X_op = O_constant; |
5866 | expr1.X_op_symbol = NULL; | |
5867 | expr1.X_add_symbol = NULL; | |
5868 | expr1.X_add_number = 1; | |
8358c818 | 5869 | |
cc5703cd | 5870 | dbl = 0; |
517078c1 | 5871 | |
cc5703cd ILT |
5872 | switch (mask) |
5873 | { | |
5874 | default: | |
5875 | internalError (); | |
5876 | ||
5877 | case M_DDIV_3: | |
5878 | dbl = 1; | |
5879 | case M_DIV_3: | |
5880 | s = "mflo"; | |
5881 | goto do_div3; | |
5882 | case M_DREM_3: | |
5883 | dbl = 1; | |
5884 | case M_REM_3: | |
5885 | s = "mfhi"; | |
5886 | do_div3: | |
fbcfacb7 | 5887 | mips_emit_delays (true); |
cc5703cd ILT |
5888 | ++mips_noreorder; |
5889 | mips_any_noreorder = 1; | |
5890 | macro_build ((char *) NULL, &icnt, NULL, | |
5891 | dbl ? "ddiv" : "div", | |
5892 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5893 | expr1.X_add_number = 2; |
cc5703cd | 5894 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5895 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5896 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5897 | since that causes an overflow. We should do that as well, | |
5898 | but I don't see how to do the comparisons without a temporary | |
5899 | register. */ | |
5900 | --mips_noreorder; | |
5901 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5902 | break; | |
5903 | ||
5904 | case M_DIVU_3: | |
5905 | s = "divu"; | |
5906 | s2 = "mflo"; | |
5907 | goto do_divu3; | |
5908 | case M_REMU_3: | |
5909 | s = "divu"; | |
5910 | s2 = "mfhi"; | |
5911 | goto do_divu3; | |
5912 | case M_DDIVU_3: | |
5913 | s = "ddivu"; | |
5914 | s2 = "mflo"; | |
5915 | goto do_divu3; | |
5916 | case M_DREMU_3: | |
5917 | s = "ddivu"; | |
5918 | s2 = "mfhi"; | |
5919 | do_divu3: | |
fbcfacb7 | 5920 | mips_emit_delays (true); |
cc5703cd ILT |
5921 | ++mips_noreorder; |
5922 | mips_any_noreorder = 1; | |
5923 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5924 | expr1.X_add_number = 2; |
cc5703cd | 5925 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5926 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5927 | --mips_noreorder; | |
5928 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5929 | break; | |
5930 | ||
5931 | case M_DSUBU_I: | |
5932 | dbl = 1; | |
5933 | goto do_subu; | |
5934 | case M_SUBU_I: | |
5935 | do_subu: | |
5936 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5937 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5938 | dbl ? "daddiu" : "addiu", | |
5939 | "y,x,4", yreg, xreg); | |
5940 | break; | |
5941 | ||
5942 | case M_SUBU_I_2: | |
5943 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5944 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5945 | "x,k", xreg); | |
5946 | break; | |
5947 | ||
5948 | case M_DSUBU_I_2: | |
5949 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5950 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5951 | "y,j", yreg); | |
5952 | break; | |
5953 | ||
5954 | case M_BEQ: | |
5955 | s = "cmp"; | |
5956 | s2 = "bteqz"; | |
5957 | goto do_branch; | |
5958 | case M_BNE: | |
5959 | s = "cmp"; | |
5960 | s2 = "btnez"; | |
5961 | goto do_branch; | |
5962 | case M_BLT: | |
5963 | s = "slt"; | |
5964 | s2 = "btnez"; | |
5965 | goto do_branch; | |
5966 | case M_BLTU: | |
5967 | s = "sltu"; | |
5968 | s2 = "btnez"; | |
5969 | goto do_branch; | |
5970 | case M_BLE: | |
5971 | s = "slt"; | |
5972 | s2 = "bteqz"; | |
5973 | goto do_reverse_branch; | |
5974 | case M_BLEU: | |
5975 | s = "sltu"; | |
5976 | s2 = "bteqz"; | |
5977 | goto do_reverse_branch; | |
5978 | case M_BGE: | |
5979 | s = "slt"; | |
5980 | s2 = "bteqz"; | |
5981 | goto do_branch; | |
5982 | case M_BGEU: | |
5983 | s = "sltu"; | |
5984 | s2 = "bteqz"; | |
5985 | goto do_branch; | |
5986 | case M_BGT: | |
5987 | s = "slt"; | |
5988 | s2 = "btnez"; | |
5989 | goto do_reverse_branch; | |
5990 | case M_BGTU: | |
5991 | s = "sltu"; | |
5992 | s2 = "btnez"; | |
5993 | ||
5994 | do_reverse_branch: | |
5995 | tmp = xreg; | |
5996 | xreg = yreg; | |
5997 | yreg = tmp; | |
5998 | ||
5999 | do_branch: | |
6000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6001 | xreg, yreg); | |
6002 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6003 | break; | |
6004 | ||
6005 | case M_BEQ_I: | |
6006 | s = "cmpi"; | |
6007 | s2 = "bteqz"; | |
6008 | s3 = "x,U"; | |
6009 | goto do_branch_i; | |
6010 | case M_BNE_I: | |
6011 | s = "cmpi"; | |
6012 | s2 = "btnez"; | |
6013 | s3 = "x,U"; | |
6014 | goto do_branch_i; | |
6015 | case M_BLT_I: | |
6016 | s = "slti"; | |
6017 | s2 = "btnez"; | |
6018 | s3 = "x,8"; | |
6019 | goto do_branch_i; | |
6020 | case M_BLTU_I: | |
6021 | s = "sltiu"; | |
6022 | s2 = "btnez"; | |
6023 | s3 = "x,8"; | |
6024 | goto do_branch_i; | |
6025 | case M_BLE_I: | |
6026 | s = "slti"; | |
6027 | s2 = "btnez"; | |
6028 | s3 = "x,8"; | |
6029 | goto do_addone_branch_i; | |
6030 | case M_BLEU_I: | |
6031 | s = "sltiu"; | |
6032 | s2 = "btnez"; | |
6033 | s3 = "x,8"; | |
6034 | goto do_addone_branch_i; | |
6035 | case M_BGE_I: | |
6036 | s = "slti"; | |
6037 | s2 = "bteqz"; | |
6038 | s3 = "x,8"; | |
6039 | goto do_branch_i; | |
6040 | case M_BGEU_I: | |
6041 | s = "sltiu"; | |
6042 | s2 = "bteqz"; | |
6043 | s3 = "x,8"; | |
6044 | goto do_branch_i; | |
6045 | case M_BGT_I: | |
6046 | s = "slti"; | |
6047 | s2 = "bteqz"; | |
6048 | s3 = "x,8"; | |
6049 | goto do_addone_branch_i; | |
6050 | case M_BGTU_I: | |
6051 | s = "sltiu"; | |
6052 | s2 = "bteqz"; | |
6053 | s3 = "x,8"; | |
6054 | ||
6055 | do_addone_branch_i: | |
6056 | ++imm_expr.X_add_number; | |
6057 | ||
6058 | do_branch_i: | |
6059 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6060 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6061 | break; | |
18e0764d ILT |
6062 | |
6063 | case M_ABS: | |
6064 | expr1.X_add_number = 0; | |
6065 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6066 | if (xreg != yreg) | |
6067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6068 | "move", "y,X", xreg, yreg); | |
6069 | expr1.X_add_number = 2; | |
6070 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6071 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6072 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6073 | } |
6074 | } | |
6075 | ||
6076 | /* This routine assembles an instruction into its binary format. As a | |
6077 | side effect, it sets one of the global variables imm_reloc or | |
6078 | offset_reloc to the type of relocation to do if one of the operands | |
6079 | is an address expression. */ | |
6080 | ||
6081 | static void | |
6082 | mips_ip (str, ip) | |
6083 | char *str; | |
6084 | struct mips_cl_insn *ip; | |
6085 | { | |
6086 | char *s; | |
6087 | const char *args; | |
6088 | char c; | |
6089 | struct mips_opcode *insn; | |
6090 | char *argsStart; | |
6091 | unsigned int regno; | |
6092 | unsigned int lastregno = 0; | |
6093 | char *s_reset; | |
6094 | ||
6095 | insn_error = NULL; | |
6096 | ||
6097 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6098 | continue; | |
6099 | switch (*s) | |
6100 | { | |
6101 | case '\0': | |
6102 | break; | |
6103 | ||
6104 | case ' ': | |
6105 | *s++ = '\0'; | |
6106 | break; | |
6107 | ||
6108 | default: | |
6109 | as_fatal ("Unknown opcode: `%s'", str); | |
6110 | } | |
6111 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6112 | { | |
6113 | insn_error = "unrecognized opcode"; | |
6114 | return; | |
6115 | } | |
6116 | argsStart = s; | |
6117 | for (;;) | |
6118 | { | |
6119 | int insn_isa; | |
6120 | ||
6121 | assert (strcmp (insn->name, str) == 0); | |
6122 | ||
6123 | if (insn->pinfo == INSN_MACRO) | |
6124 | insn_isa = insn->match; | |
6125 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6126 | insn_isa = 2; | |
6127 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6128 | insn_isa = 3; | |
6129 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6130 | insn_isa = 4; | |
6131 | else | |
6132 | insn_isa = 1; | |
6133 | ||
6134 | if (insn_isa > mips_isa | |
6135 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
6136 | && ! mips_4650) | |
6137 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6138 | && ! mips_4010) | |
6139 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
6140 | && ! mips_4100) |
6141 | /* start-sanitize-r5900 */ | |
6142 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6143 | && ! mips_5900) | |
6144 | /* end-sanitize-r5900 */ | |
6145 | ) | |
cc5703cd ILT |
6146 | { |
6147 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6148 | && strcmp (insn->name, insn[1].name) == 0) | |
6149 | { | |
6150 | ++insn; | |
6151 | continue; | |
6152 | } | |
6153 | if (insn_isa <= mips_isa) | |
6154 | insn_error = "opcode not supported on this processor"; | |
6155 | else | |
6156 | { | |
6157 | static char buf[100]; | |
6158 | ||
6159 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6160 | insn_error = buf; | |
6161 | } | |
6162 | return; | |
6163 | } | |
8358c818 | 6164 | |
670a50eb ILT |
6165 | ip->insn_mo = insn; |
6166 | ip->insn_opcode = insn->match; | |
6167 | for (args = insn->args;; ++args) | |
6168 | { | |
6169 | if (*s == ' ') | |
6170 | ++s; | |
6171 | switch (*args) | |
6172 | { | |
6173 | case '\0': /* end of args */ | |
6174 | if (*s == '\0') | |
6175 | return; | |
6176 | break; | |
3d3c5039 ILT |
6177 | |
6178 | case ',': | |
670a50eb ILT |
6179 | if (*s++ == *args) |
6180 | continue; | |
6181 | s--; | |
6182 | switch (*++args) | |
6183 | { | |
3d3c5039 ILT |
6184 | case 'r': |
6185 | case 'v': | |
670a50eb ILT |
6186 | ip->insn_opcode |= lastregno << 21; |
6187 | continue; | |
3d3c5039 ILT |
6188 | |
6189 | case 'w': | |
6190 | case 'W': | |
670a50eb ILT |
6191 | ip->insn_opcode |= lastregno << 16; |
6192 | continue; | |
3d3c5039 ILT |
6193 | |
6194 | case 'V': | |
670a50eb ILT |
6195 | ip->insn_opcode |= lastregno << 11; |
6196 | continue; | |
3d3c5039 | 6197 | } |
670a50eb | 6198 | break; |
3d3c5039 ILT |
6199 | |
6200 | case '(': | |
670a50eb ILT |
6201 | /* handle optional base register. |
6202 | Either the base register is omitted or | |
6203 | we must have a left paren. */ | |
6204 | /* this is dependent on the next operand specifier | |
6205 | is a 'b' for base register */ | |
6206 | assert (args[1] == 'b'); | |
6207 | if (*s == '\0') | |
6208 | return; | |
3d3c5039 | 6209 | |
670a50eb ILT |
6210 | case ')': /* these must match exactly */ |
6211 | if (*s++ == *args) | |
3d3c5039 | 6212 | continue; |
670a50eb ILT |
6213 | break; |
6214 | ||
6215 | case '<': /* must be at least one digit */ | |
6216 | /* | |
6217 | * According to the manual, if the shift amount is greater | |
6218 | * than 31 or less than 0 the the shift amount should be | |
6219 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6220 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6221 | */ |
6222 | my_getExpression (&imm_expr, s); | |
6223 | check_absolute_expr (ip, &imm_expr); | |
6224 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6225 | { | |
58d4951d ILT |
6226 | as_warn ("Improper shift amount (%ld)", |
6227 | (long) imm_expr.X_add_number); | |
9226253a | 6228 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6229 | } |
6230 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6231 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6232 | s = expr_end; |
6233 | continue; | |
6234 | ||
56c96faa ILT |
6235 | case '>': /* shift amount minus 32 */ |
6236 | my_getExpression (&imm_expr, s); | |
6237 | check_absolute_expr (ip, &imm_expr); | |
6238 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6239 | || (unsigned long) imm_expr.X_add_number > 63) | |
6240 | break; | |
6241 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6242 | imm_expr.X_op = O_absent; | |
6243 | s = expr_end; | |
6244 | continue; | |
6245 | ||
9226253a | 6246 | case 'k': /* cache code */ |
d8a1c247 | 6247 | case 'h': /* prefx code */ |
9226253a ILT |
6248 | my_getExpression (&imm_expr, s); |
6249 | check_absolute_expr (ip, &imm_expr); | |
6250 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6251 | { | |
d8a1c247 KR |
6252 | as_warn ("Invalid value for `%s' (%lu)", |
6253 | ip->insn_mo->name, | |
9226253a ILT |
6254 | (unsigned long) imm_expr.X_add_number); |
6255 | imm_expr.X_add_number &= 0x1f; | |
6256 | } | |
d8a1c247 KR |
6257 | if (*args == 'k') |
6258 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6259 | else | |
6260 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6261 | imm_expr.X_op = O_absent; |
6262 | s = expr_end; | |
6263 | continue; | |
6264 | ||
670a50eb ILT |
6265 | case 'c': /* break code */ |
6266 | my_getExpression (&imm_expr, s); | |
6267 | check_absolute_expr (ip, &imm_expr); | |
6268 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6269 | as_warn ("Illegal break code (%ld)", |
6270 | (long) imm_expr.X_add_number); | |
670a50eb | 6271 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6272 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6273 | s = expr_end; |
6274 | continue; | |
6275 | ||
918692a5 ILT |
6276 | case 'B': /* syscall code */ |
6277 | my_getExpression (&imm_expr, s); | |
6278 | check_absolute_expr (ip, &imm_expr); | |
6279 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6280 | as_warn ("Illegal syscall code (%ld)", |
6281 | (long) imm_expr.X_add_number); | |
918692a5 | 6282 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6283 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6284 | s = expr_end; |
6285 | continue; | |
6286 | ||
0aa07269 ILT |
6287 | case 'C': /* Coprocessor code */ |
6288 | my_getExpression (&imm_expr, s); | |
6289 | check_absolute_expr (ip, &imm_expr); | |
6290 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6291 | { | |
58d4951d ILT |
6292 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6293 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6294 | imm_expr.X_add_number &= ((1<<25) - 1); |
6295 | } | |
6296 | ip->insn_opcode |= imm_expr.X_add_number; | |
6297 | imm_expr.X_op = O_absent; | |
6298 | s = expr_end; | |
6299 | continue; | |
6300 | ||
670a50eb ILT |
6301 | case 'b': /* base register */ |
6302 | case 'd': /* destination register */ | |
6303 | case 's': /* source register */ | |
6304 | case 't': /* target register */ | |
6305 | case 'r': /* both target and source */ | |
6306 | case 'v': /* both dest and source */ | |
6307 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6308 | case 'E': /* coprocessor target register */ |
6309 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6310 | case 'x': /* ignore register name */ |
ff3a5c18 | 6311 | case 'z': /* must be zero register */ |
670a50eb ILT |
6312 | s_reset = s; |
6313 | if (s[0] == '$') | |
6314 | { | |
6315 | if (isdigit (s[1])) | |
6316 | { | |
6317 | ++s; | |
6318 | regno = 0; | |
6319 | do | |
6320 | { | |
6321 | regno *= 10; | |
6322 | regno += *s - '0'; | |
6323 | ++s; | |
6324 | } | |
6325 | while (isdigit (*s)); | |
0aa07269 ILT |
6326 | if (regno > 31) |
6327 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6328 | } |
0dd2d296 ILT |
6329 | else if (*args == 'E' || *args == 'G') |
6330 | goto notreg; | |
6331 | else | |
670a50eb | 6332 | { |
0aa07269 ILT |
6333 | if (s[1] == 'f' && s[2] == 'p') |
6334 | { | |
6335 | s += 3; | |
9226253a | 6336 | regno = FP; |
0aa07269 ILT |
6337 | } |
6338 | else if (s[1] == 's' && s[2] == 'p') | |
6339 | { | |
6340 | s += 3; | |
9226253a | 6341 | regno = SP; |
0aa07269 ILT |
6342 | } |
6343 | else if (s[1] == 'g' && s[2] == 'p') | |
6344 | { | |
6345 | s += 3; | |
9226253a | 6346 | regno = GP; |
0aa07269 ILT |
6347 | } |
6348 | else if (s[1] == 'a' && s[2] == 't') | |
6349 | { | |
6350 | s += 3; | |
9226253a | 6351 | regno = AT; |
0aa07269 | 6352 | } |
b2b8c24e ILT |
6353 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6354 | { | |
6355 | s += 4; | |
6356 | regno = KT0; | |
6357 | } | |
6358 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6359 | { | |
6360 | s += 4; | |
6361 | regno = KT1; | |
6362 | } | |
0aa07269 ILT |
6363 | else |
6364 | goto notreg; | |
670a50eb | 6365 | } |
9753202d ILT |
6366 | if (regno == AT |
6367 | && ! mips_noat | |
6368 | && *args != 'E' | |
6369 | && *args != 'G') | |
13fe1379 | 6370 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6371 | c = *args; |
6372 | if (*s == ' ') | |
6373 | s++; | |
6374 | if (args[1] != *s) | |
6375 | { | |
6376 | if (c == 'r' || c == 'v' || c == 'w') | |
6377 | { | |
6378 | regno = lastregno; | |
6379 | s = s_reset; | |
6380 | args++; | |
6381 | } | |
6382 | } | |
ff3a5c18 ILT |
6383 | /* 'z' only matches $0. */ |
6384 | if (c == 'z' && regno != 0) | |
6385 | break; | |
670a50eb ILT |
6386 | switch (c) |
6387 | { | |
3d3c5039 ILT |
6388 | case 'r': |
6389 | case 's': | |
6390 | case 'v': | |
6391 | case 'b': | |
670a50eb ILT |
6392 | ip->insn_opcode |= regno << 21; |
6393 | break; | |
3d3c5039 | 6394 | case 'd': |
918692a5 | 6395 | case 'G': |
670a50eb ILT |
6396 | ip->insn_opcode |= regno << 11; |
6397 | break; | |
3d3c5039 ILT |
6398 | case 'w': |
6399 | case 't': | |
918692a5 | 6400 | case 'E': |
670a50eb | 6401 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6402 | break; |
6403 | case 'x': | |
6404 | /* This case exists because on the r3000 trunc | |
6405 | expands into a macro which requires a gp | |
6406 | register. On the r6000 or r4000 it is | |
6407 | assembled into a single instruction which | |
6408 | ignores the register. Thus the insn version | |
6409 | is MIPS_ISA2 and uses 'x', and the macro | |
6410 | version is MIPS_ISA1 and uses 't'. */ | |
6411 | break; | |
ff3a5c18 ILT |
6412 | case 'z': |
6413 | /* This case is for the div instruction, which | |
6414 | acts differently if the destination argument | |
6415 | is $0. This only matches $0, and is checked | |
6416 | outside the switch. */ | |
6417 | break; | |
3d3c5039 | 6418 | } |
670a50eb ILT |
6419 | lastregno = regno; |
6420 | continue; | |
3d3c5039 ILT |
6421 | } |
6422 | notreg: | |
670a50eb ILT |
6423 | switch (*args++) |
6424 | { | |
3d3c5039 ILT |
6425 | case 'r': |
6426 | case 'v': | |
670a50eb ILT |
6427 | ip->insn_opcode |= lastregno << 21; |
6428 | continue; | |
3d3c5039 | 6429 | case 'w': |
670a50eb ILT |
6430 | ip->insn_opcode |= lastregno << 16; |
6431 | continue; | |
3d3c5039 | 6432 | } |
670a50eb | 6433 | break; |
3d3c5039 | 6434 | |
670a50eb ILT |
6435 | case 'D': /* floating point destination register */ |
6436 | case 'S': /* floating point source register */ | |
6437 | case 'T': /* floating point target register */ | |
d8a1c247 | 6438 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6439 | case 'V': |
6440 | case 'W': | |
670a50eb ILT |
6441 | s_reset = s; |
6442 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6443 | { | |
6444 | s += 2; | |
6445 | regno = 0; | |
6446 | do | |
6447 | { | |
6448 | regno *= 10; | |
6449 | regno += *s - '0'; | |
6450 | ++s; | |
6451 | } | |
6452 | while (isdigit (*s)); | |
6453 | ||
6454 | if (regno > 31) | |
6455 | as_bad ("Invalid float register number (%d)", regno); | |
6456 | ||
9226253a ILT |
6457 | if ((regno & 1) != 0 |
6458 | && mips_isa < 3 | |
538034cf ILT |
6459 | && ! (strcmp (str, "mtc1") == 0 |
6460 | || strcmp (str, "mfc1") == 0 | |
6461 | || strcmp (str, "lwc1") == 0 | |
6462 | || strcmp (str, "swc1") == 0 | |
6463 | || strcmp (str, "l.s") == 0 | |
6464 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6465 | as_warn ("Float register should be even, was %d", |
6466 | regno); | |
6467 | ||
6468 | c = *args; | |
6469 | if (*s == ' ') | |
6470 | s++; | |
6471 | if (args[1] != *s) | |
6472 | { | |
6473 | if (c == 'V' || c == 'W') | |
6474 | { | |
6475 | regno = lastregno; | |
6476 | s = s_reset; | |
6477 | args++; | |
3d3c5039 ILT |
6478 | } |
6479 | } | |
670a50eb ILT |
6480 | switch (c) |
6481 | { | |
3d3c5039 | 6482 | case 'D': |
670a50eb ILT |
6483 | ip->insn_opcode |= regno << 6; |
6484 | break; | |
3d3c5039 ILT |
6485 | case 'V': |
6486 | case 'S': | |
670a50eb ILT |
6487 | ip->insn_opcode |= regno << 11; |
6488 | break; | |
3d3c5039 ILT |
6489 | case 'W': |
6490 | case 'T': | |
670a50eb | 6491 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6492 | break; |
6493 | case 'R': | |
6494 | ip->insn_opcode |= regno << 21; | |
6495 | break; | |
3d3c5039 | 6496 | } |
670a50eb ILT |
6497 | lastregno = regno; |
6498 | continue; | |
3d3c5039 | 6499 | } |
670a50eb ILT |
6500 | switch (*args++) |
6501 | { | |
3d3c5039 | 6502 | case 'V': |
670a50eb ILT |
6503 | ip->insn_opcode |= lastregno << 11; |
6504 | continue; | |
3d3c5039 | 6505 | case 'W': |
670a50eb ILT |
6506 | ip->insn_opcode |= lastregno << 16; |
6507 | continue; | |
3d3c5039 | 6508 | } |
670a50eb | 6509 | break; |
3d3c5039 ILT |
6510 | |
6511 | case 'I': | |
670a50eb | 6512 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6513 | if (imm_expr.X_op != O_big |
6514 | && imm_expr.X_op != O_constant) | |
6515 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6516 | s = expr_end; |
6517 | continue; | |
3d3c5039 ILT |
6518 | |
6519 | case 'A': | |
670a50eb ILT |
6520 | my_getExpression (&offset_expr, s); |
6521 | imm_reloc = BFD_RELOC_32; | |
6522 | s = expr_end; | |
6523 | continue; | |
3d3c5039 ILT |
6524 | |
6525 | case 'F': | |
19ed8960 ILT |
6526 | case 'L': |
6527 | case 'f': | |
6528 | case 'l': | |
6529 | { | |
6530 | int f64; | |
6531 | char *save_in; | |
6532 | char *err; | |
6533 | unsigned char temp[8]; | |
604633ae ILT |
6534 | int len; |
6535 | unsigned int length; | |
19ed8960 ILT |
6536 | segT seg; |
6537 | subsegT subseg; | |
6538 | char *p; | |
6539 | ||
6540 | /* These only appear as the last operand in an | |
6541 | instruction, and every instruction that accepts | |
6542 | them in any variant accepts them in all variants. | |
6543 | This means we don't have to worry about backing out | |
6544 | any changes if the instruction does not match. | |
6545 | ||
6546 | The difference between them is the size of the | |
6547 | floating point constant and where it goes. For 'F' | |
6548 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6549 | is 32 bits. Where the constant is placed is based | |
6550 | on how the MIPS assembler does things: | |
6551 | F -- .rdata | |
6552 | L -- .lit8 | |
6553 | f -- immediate value | |
6554 | l -- .lit4 | |
0dd2d296 | 6555 | |
55933a58 ILT |
6556 | The .lit4 and .lit8 sections are only used if |
6557 | permitted by the -G argument. | |
6558 | ||
6559 | When generating embedded PIC code, we use the | |
6560 | .lit8 section but not the .lit4 section (we can do | |
6561 | .lit4 inline easily; we need to put .lit8 | |
6562 | somewhere in the data segment, and using .lit8 | |
6563 | permits the linker to eventually combine identical | |
6564 | .lit8 entries). */ | |
19ed8960 ILT |
6565 | |
6566 | f64 = *args == 'F' || *args == 'L'; | |
6567 | ||
6568 | save_in = input_line_pointer; | |
6569 | input_line_pointer = s; | |
604633ae ILT |
6570 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6571 | length = len; | |
19ed8960 ILT |
6572 | s = input_line_pointer; |
6573 | input_line_pointer = save_in; | |
6574 | if (err != NULL && *err != '\0') | |
6575 | { | |
6576 | as_bad ("Bad floating point constant: %s", err); | |
6577 | memset (temp, '\0', sizeof temp); | |
6578 | length = f64 ? 8 : 4; | |
6579 | } | |
6580 | ||
6581 | assert (length == (f64 ? 8 : 4)); | |
6582 | ||
0dd2d296 | 6583 | if (*args == 'f' |
55933a58 | 6584 | || (*args == 'l' |
1dc1e798 KR |
6585 | && (! USE_GLOBAL_POINTER_OPT |
6586 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6587 | || g_switch_value < 4) |
1113140a | 6588 | )) |
19ed8960 ILT |
6589 | { |
6590 | imm_expr.X_op = O_constant; | |
b9129c6f | 6591 | if (! target_big_endian) |
19ed8960 ILT |
6592 | imm_expr.X_add_number = |
6593 | (((((((int) temp[3] << 8) | |
6594 | | temp[2]) << 8) | |
6595 | | temp[1]) << 8) | |
6596 | | temp[0]); | |
6597 | else | |
6598 | imm_expr.X_add_number = | |
6599 | (((((((int) temp[0] << 8) | |
6600 | | temp[1]) << 8) | |
6601 | | temp[2]) << 8) | |
6602 | | temp[3]); | |
6603 | } | |
6604 | else | |
6605 | { | |
0dd2d296 ILT |
6606 | const char *newname; |
6607 | segT new_seg; | |
6608 | ||
19ed8960 ILT |
6609 | /* Switch to the right section. */ |
6610 | seg = now_seg; | |
6611 | subseg = now_subseg; | |
6612 | switch (*args) | |
6613 | { | |
0dd2d296 | 6614 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6615 | case 'L': |
1113140a | 6616 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6617 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6618 | newname = ".lit8"; |
0dd2d296 ILT |
6619 | break; |
6620 | case 'F': | |
d2c71068 | 6621 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6622 | break; |
6623 | case 'l': | |
1dc1e798 KR |
6624 | assert (!USE_GLOBAL_POINTER_OPT |
6625 | || g_switch_value >= 4); | |
0dd2d296 | 6626 | newname = ".lit4"; |
19ed8960 ILT |
6627 | break; |
6628 | } | |
0dd2d296 | 6629 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6630 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6631 | bfd_set_section_flags (stdoutput, new_seg, | |
6632 | (SEC_ALLOC | |
6633 | | SEC_LOAD | |
6634 | | SEC_READONLY | |
6635 | | SEC_DATA)); | |
0221ddf7 | 6636 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6637 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6638 | record_alignment (new_seg, 4); | |
6639 | else | |
6640 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6641 | if (seg == now_seg) |
6642 | as_bad ("Can't use floating point insn in this section"); | |
6643 | ||
6644 | /* Set the argument to the current address in the | |
6e8dda9c | 6645 | section. */ |
19ed8960 ILT |
6646 | offset_expr.X_op = O_symbol; |
6647 | offset_expr.X_add_symbol = | |
6648 | symbol_new ("L0\001", now_seg, | |
6649 | (valueT) frag_now_fix (), frag_now); | |
6650 | offset_expr.X_add_number = 0; | |
6651 | ||
6652 | /* Put the floating point number into the section. */ | |
604633ae | 6653 | p = frag_more ((int) length); |
19ed8960 ILT |
6654 | memcpy (p, temp, length); |
6655 | ||
6656 | /* Switch back to the original section. */ | |
6657 | subseg_set (seg, subseg); | |
6658 | } | |
6659 | } | |
670a50eb ILT |
6660 | continue; |
6661 | ||
6662 | case 'i': /* 16 bit unsigned immediate */ | |
6663 | case 'j': /* 16 bit signed immediate */ | |
6664 | imm_reloc = BFD_RELOC_LO16; | |
6665 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6666 | if (c != '\0') |
670a50eb ILT |
6667 | { |
6668 | if (c != 'l') | |
6669 | { | |
5ac34ac3 | 6670 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6671 | imm_expr.X_add_number = |
6672 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6673 | else if (c == 'h') | |
867a58b3 ILT |
6674 | { |
6675 | imm_reloc = BFD_RELOC_HI16_S; | |
6676 | imm_unmatched_hi = true; | |
6677 | } | |
670a50eb ILT |
6678 | else |
6679 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6680 | } |
670a50eb | 6681 | } |
670a50eb ILT |
6682 | if (*args == 'i') |
6683 | { | |
344a8d61 | 6684 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6685 | || ((imm_expr.X_add_number < 0 |
6686 | || imm_expr.X_add_number >= 0x10000) | |
6687 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6688 | { |
6689 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6690 | !strcmp (insn->name, insn[1].name)) | |
6691 | break; | |
9753202d ILT |
6692 | if (imm_expr.X_op != O_constant |
6693 | && imm_expr.X_op != O_big) | |
6694 | insn_error = "absolute expression required"; | |
6695 | else | |
6696 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6697 | } |
670a50eb ILT |
6698 | } |
6699 | else | |
6700 | { | |
d9aba805 ILT |
6701 | int more; |
6702 | offsetT max; | |
6703 | ||
be22008b ILT |
6704 | /* The upper bound should be 0x8000, but |
6705 | unfortunately the MIPS assembler accepts numbers | |
6706 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6707 | we want to be compatible. We only permit this |
6708 | extended range for an instruction which does not | |
6709 | provide any further alternates, since those | |
6710 | alternates may handle other cases. People should | |
6711 | use the numbers they mean, rather than relying on | |
6712 | a mysterious sign extension. */ | |
6713 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6714 | strcmp (insn->name, insn[1].name) == 0); | |
6715 | if (more) | |
6716 | max = 0x8000; | |
6717 | else | |
6718 | max = 0x10000; | |
344a8d61 | 6719 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6720 | || ((imm_expr.X_add_number < -0x8000 |
6721 | || imm_expr.X_add_number >= max) | |
6722 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6723 | || (more |
6724 | && imm_expr.X_add_number < 0 | |
6725 | && mips_isa >= 3 | |
6726 | && imm_expr.X_unsigned | |
6727 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6728 | { |
d9aba805 | 6729 | if (more) |
99c24539 | 6730 | break; |
9753202d ILT |
6731 | if (imm_expr.X_op != O_constant |
6732 | && imm_expr.X_op != O_big) | |
6733 | insn_error = "absolute expression required"; | |
6734 | else | |
6735 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6736 | } |
3d3c5039 | 6737 | } |
670a50eb ILT |
6738 | s = expr_end; |
6739 | continue; | |
6740 | ||
6741 | case 'o': /* 16 bit offset */ | |
6742 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6743 | |
6744 | /* If this value won't fit into a 16 bit offset, then go | |
6745 | find a macro that will generate the 32 bit offset | |
6746 | code pattern. As a special hack, we accept the | |
6747 | difference of two local symbols as a constant. This | |
6748 | is required to suppose embedded PIC switches, which | |
6749 | use an instruction which looks like | |
6750 | lw $4,$L12-$LS12($4) | |
6751 | The problem with handling this in a more general | |
6752 | fashion is that the macro function doesn't expect to | |
6753 | see anything which can be handled in a single | |
6754 | constant instruction. */ | |
6f0b87c3 SS |
6755 | if (c == 0 |
6756 | && (offset_expr.X_op != O_constant | |
6757 | || offset_expr.X_add_number >= 0x8000 | |
6758 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6759 | && (mips_pic != EMBEDDED_PIC |
6760 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6761 | || now_seg != text_section |
6762 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6763 | != text_section))) | |
670a50eb | 6764 | break; |
3d3c5039 | 6765 | |
670a50eb ILT |
6766 | offset_reloc = BFD_RELOC_LO16; |
6767 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6768 | { |
6769 | assert (offset_expr.X_op == O_constant); | |
6770 | offset_expr.X_add_number = | |
6771 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6772 | } | |
cc5703cd ILT |
6773 | s = expr_end; |
6774 | continue; | |
6775 | ||
6776 | case 'p': /* pc relative offset */ | |
6777 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6778 | my_getExpression (&offset_expr, s); | |
6779 | s = expr_end; | |
6780 | continue; | |
6781 | ||
6782 | case 'u': /* upper 16 bits */ | |
6783 | c = my_getSmallExpression (&imm_expr, s); | |
6784 | if (imm_expr.X_op == O_constant | |
6785 | && (imm_expr.X_add_number < 0 | |
6786 | || imm_expr.X_add_number >= 0x10000)) | |
6787 | as_bad ("lui expression not in range 0..65535"); | |
6788 | imm_reloc = BFD_RELOC_LO16; | |
6789 | if (c) | |
6790 | { | |
6791 | if (c != 'l') | |
6792 | { | |
6793 | if (imm_expr.X_op == O_constant) | |
6794 | imm_expr.X_add_number = | |
6795 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6796 | else if (c == 'h') | |
6797 | { | |
6798 | imm_reloc = BFD_RELOC_HI16_S; | |
6799 | imm_unmatched_hi = true; | |
6800 | } | |
6801 | else | |
6802 | imm_reloc = BFD_RELOC_HI16; | |
6803 | } | |
6804 | } | |
6805 | s = expr_end; | |
6806 | continue; | |
6807 | ||
6808 | case 'a': /* 26 bit address */ | |
6809 | my_getExpression (&offset_expr, s); | |
6810 | s = expr_end; | |
6811 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6812 | continue; | |
6813 | ||
6814 | case 'N': /* 3 bit branch condition code */ | |
6815 | case 'M': /* 3 bit compare condition code */ | |
6816 | if (strncmp (s, "$fcc", 4) != 0) | |
6817 | break; | |
6818 | s += 4; | |
6819 | regno = 0; | |
6820 | do | |
6821 | { | |
6822 | regno *= 10; | |
6823 | regno += *s - '0'; | |
6824 | ++s; | |
6825 | } | |
6826 | while (isdigit (*s)); | |
6827 | if (regno > 7) | |
6828 | as_bad ("invalid condition code register $fcc%d", regno); | |
6829 | if (*args == 'N') | |
6830 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6831 | else | |
6832 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6833 | continue; | |
6834 | ||
6835 | default: | |
6836 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6837 | internalError (); | |
6838 | } | |
6839 | break; | |
6840 | } | |
6841 | /* Args don't match. */ | |
6842 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6843 | !strcmp (insn->name, insn[1].name)) | |
6844 | { | |
6845 | ++insn; | |
6846 | s = argsStart; | |
6847 | continue; | |
6848 | } | |
6849 | insn_error = "illegal operands"; | |
6850 | return; | |
6851 | } | |
6852 | } | |
6853 | ||
6854 | /* This routine assembles an instruction into its binary format when | |
6855 | assembling for the mips16. As a side effect, it sets one of the | |
6856 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6857 | relocation to do if one of the operands is an address expression. |
6858 | It also sets mips16_small and mips16_ext if the user explicitly | |
6859 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6860 | |
6861 | static void | |
6862 | mips16_ip (str, ip) | |
6863 | char *str; | |
6864 | struct mips_cl_insn *ip; | |
6865 | { | |
6866 | char *s; | |
cc5703cd ILT |
6867 | const char *args; |
6868 | struct mips_opcode *insn; | |
6869 | char *argsstart; | |
6870 | unsigned int regno; | |
6871 | unsigned int lastregno = 0; | |
6872 | char *s_reset; | |
6873 | ||
6874 | insn_error = NULL; | |
6875 | ||
8728fa92 ILT |
6876 | mips16_small = false; |
6877 | mips16_ext = false; | |
cc5703cd ILT |
6878 | |
6879 | for (s = str; islower (*s); ++s) | |
6880 | ; | |
6881 | switch (*s) | |
6882 | { | |
6883 | case '\0': | |
6884 | break; | |
6885 | ||
6886 | case ' ': | |
6887 | *s++ = '\0'; | |
6888 | break; | |
6889 | ||
6890 | case '.': | |
6891 | if (s[1] == 't' && s[2] == ' ') | |
6892 | { | |
6893 | *s = '\0'; | |
8728fa92 | 6894 | mips16_small = true; |
cc5703cd ILT |
6895 | s += 3; |
6896 | break; | |
6897 | } | |
6898 | else if (s[1] == 'e' && s[2] == ' ') | |
6899 | { | |
6900 | *s = '\0'; | |
8728fa92 | 6901 | mips16_ext = true; |
cc5703cd ILT |
6902 | s += 3; |
6903 | break; | |
6904 | } | |
6905 | /* Fall through. */ | |
6906 | default: | |
6907 | insn_error = "unknown opcode"; | |
6908 | return; | |
6909 | } | |
6910 | ||
8728fa92 ILT |
6911 | if (! mips16_autoextend && ! mips16_ext) |
6912 | mips16_small = true; | |
6913 | ||
cc5703cd ILT |
6914 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6915 | { | |
6916 | insn_error = "unrecognized opcode"; | |
6917 | return; | |
6918 | } | |
6919 | ||
6920 | argsstart = s; | |
6921 | for (;;) | |
6922 | { | |
6923 | assert (strcmp (insn->name, str) == 0); | |
6924 | ||
6925 | ip->insn_mo = insn; | |
6926 | ip->insn_opcode = insn->match; | |
6927 | ip->use_extend = false; | |
6928 | imm_expr.X_op = O_absent; | |
6929 | imm_reloc = BFD_RELOC_UNUSED; | |
6930 | offset_expr.X_op = O_absent; | |
6931 | offset_reloc = BFD_RELOC_UNUSED; | |
6932 | for (args = insn->args; 1; ++args) | |
6933 | { | |
6934 | int c; | |
6935 | ||
6936 | if (*s == ' ') | |
6937 | ++s; | |
6938 | ||
6939 | /* In this switch statement we call break if we did not find | |
6940 | a match, continue if we did find a match, or return if we | |
6941 | are done. */ | |
6942 | ||
6943 | c = *args; | |
6944 | switch (c) | |
6945 | { | |
6946 | case '\0': | |
6947 | if (*s == '\0') | |
6948 | { | |
6949 | /* Stuff the immediate value in now, if we can. */ | |
6950 | if (imm_expr.X_op == O_constant | |
6951 | && imm_reloc > BFD_RELOC_UNUSED | |
6952 | && insn->pinfo != INSN_MACRO) | |
6953 | { | |
15e69f98 ILT |
6954 | mips16_immed ((char *) NULL, 0, |
6955 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6956 | imm_expr.X_add_number, true, mips16_small, |
6957 | mips16_ext, &ip->insn_opcode, | |
6958 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
6959 | imm_expr.X_op = O_absent; |
6960 | imm_reloc = BFD_RELOC_UNUSED; | |
6961 | } | |
6962 | ||
6963 | return; | |
6964 | } | |
6965 | break; | |
6966 | ||
6967 | case ',': | |
6968 | if (*s++ == c) | |
6969 | continue; | |
6970 | s--; | |
6971 | switch (*++args) | |
6972 | { | |
6973 | case 'v': | |
6974 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6975 | continue; | |
6976 | case 'w': | |
6977 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6978 | continue; | |
6979 | } | |
6980 | break; | |
6981 | ||
6982 | case '(': | |
6983 | case ')': | |
6984 | if (*s++ == c) | |
6985 | continue; | |
6986 | break; | |
6987 | ||
6988 | case 'v': | |
6989 | case 'w': | |
6990 | if (s[0] != '$') | |
6991 | { | |
6992 | if (c == 'v') | |
6993 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6994 | else | |
6995 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6996 | ++args; | |
6997 | continue; | |
6998 | } | |
6999 | /* Fall through. */ | |
7000 | case 'x': | |
7001 | case 'y': | |
7002 | case 'z': | |
7003 | case 'Z': | |
7004 | case '0': | |
7005 | case 'S': | |
7006 | case 'R': | |
7007 | case 'X': | |
7008 | case 'Y': | |
7009 | if (s[0] != '$') | |
7010 | break; | |
7011 | s_reset = s; | |
7012 | if (isdigit (s[1])) | |
7013 | { | |
7014 | ++s; | |
7015 | regno = 0; | |
7016 | do | |
7017 | { | |
7018 | regno *= 10; | |
7019 | regno += *s - '0'; | |
7020 | ++s; | |
7021 | } | |
7022 | while (isdigit (*s)); | |
7023 | if (regno > 31) | |
7024 | { | |
7025 | as_bad ("invalid register number (%d)", regno); | |
7026 | regno = 2; | |
7027 | } | |
7028 | } | |
7029 | else | |
7030 | { | |
7031 | if (s[1] == 'f' && s[2] == 'p') | |
7032 | { | |
7033 | s += 3; | |
7034 | regno = FP; | |
7035 | } | |
7036 | else if (s[1] == 's' && s[2] == 'p') | |
7037 | { | |
7038 | s += 3; | |
7039 | regno = SP; | |
7040 | } | |
7041 | else if (s[1] == 'g' && s[2] == 'p') | |
7042 | { | |
7043 | s += 3; | |
7044 | regno = GP; | |
7045 | } | |
7046 | else if (s[1] == 'a' && s[2] == 't') | |
7047 | { | |
7048 | s += 3; | |
7049 | regno = AT; | |
7050 | } | |
7051 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7052 | { | |
7053 | s += 4; | |
7054 | regno = KT0; | |
7055 | } | |
7056 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7057 | { | |
7058 | s += 4; | |
7059 | regno = KT1; | |
7060 | } | |
7061 | else | |
7062 | break; | |
7063 | } | |
7064 | ||
7065 | if (*s == ' ') | |
7066 | ++s; | |
7067 | if (args[1] != *s) | |
7068 | { | |
7069 | if (c == 'v' || c == 'w') | |
7070 | { | |
7071 | regno = mips16_to_32_reg_map[lastregno]; | |
7072 | s = s_reset; | |
7073 | args++; | |
7074 | } | |
7075 | } | |
7076 | ||
7077 | switch (c) | |
7078 | { | |
7079 | case 'x': | |
7080 | case 'y': | |
7081 | case 'z': | |
7082 | case 'v': | |
7083 | case 'w': | |
7084 | case 'Z': | |
7085 | regno = mips32_to_16_reg_map[regno]; | |
7086 | break; | |
7087 | ||
7088 | case '0': | |
7089 | if (regno != 0) | |
7090 | regno = ILLEGAL_REG; | |
7091 | break; | |
7092 | ||
7093 | case 'S': | |
7094 | if (regno != SP) | |
7095 | regno = ILLEGAL_REG; | |
7096 | break; | |
7097 | ||
7098 | case 'R': | |
7099 | if (regno != RA) | |
7100 | regno = ILLEGAL_REG; | |
7101 | break; | |
7102 | ||
7103 | case 'X': | |
7104 | case 'Y': | |
7105 | if (regno == AT && ! mips_noat) | |
7106 | as_warn ("used $at without \".set noat\""); | |
7107 | break; | |
7108 | ||
7109 | default: | |
7110 | internalError (); | |
7111 | } | |
7112 | ||
7113 | if (regno == ILLEGAL_REG) | |
7114 | break; | |
7115 | ||
7116 | switch (c) | |
7117 | { | |
7118 | case 'x': | |
7119 | case 'v': | |
7120 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7121 | break; | |
7122 | case 'y': | |
7123 | case 'w': | |
7124 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7125 | break; | |
7126 | case 'z': | |
7127 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7128 | break; | |
7129 | case 'Z': | |
7130 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7131 | case '0': | |
7132 | case 'S': | |
7133 | case 'R': | |
7134 | break; | |
7135 | case 'X': | |
7136 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7137 | break; | |
7138 | case 'Y': | |
7139 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7140 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7141 | break; | |
7142 | default: | |
7143 | internalError (); | |
7144 | } | |
7145 | ||
7146 | lastregno = regno; | |
7147 | continue; | |
7148 | ||
7149 | case 'P': | |
7150 | if (strncmp (s, "$pc", 3) == 0) | |
7151 | { | |
7152 | s += 3; | |
7153 | continue; | |
7154 | } | |
7155 | break; | |
7156 | ||
7157 | case '<': | |
7158 | case '>': | |
7159 | case '[': | |
7160 | case ']': | |
7161 | case '4': | |
7162 | case '5': | |
7163 | case 'H': | |
7164 | case 'W': | |
7165 | case 'D': | |
7166 | case 'j': | |
7167 | case '8': | |
7168 | case 'V': | |
7169 | case 'C': | |
7170 | case 'U': | |
7171 | case 'k': | |
7172 | case 'K': | |
7173 | if (s[0] == '$' && isdigit (s[1])) | |
7174 | { | |
7175 | /* Looks like a register name. */ | |
7176 | break; | |
7177 | } | |
c0dea495 ILT |
7178 | |
7179 | if (s[0] == '(' | |
7180 | && args[1] == '(' | |
7181 | && s[1] == '$') | |
7182 | { | |
7183 | /* It looks like the expression was omitted before a | |
7184 | register indirection, which means that the | |
645cb4dc ILT |
7185 | expression is implicitly zero. We still set up |
7186 | imm_expr, so that we handle explicit extensions | |
7187 | correctly. */ | |
7188 | imm_expr.X_op = O_constant; | |
7189 | imm_expr.X_add_number = 0; | |
7190 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
c0dea495 ILT |
7191 | continue; |
7192 | } | |
7193 | ||
cc5703cd ILT |
7194 | my_getExpression (&imm_expr, s); |
7195 | /* We need to relax this instruction. */ | |
7196 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7197 | s = expr_end; | |
7198 | continue; | |
7199 | ||
7200 | case 'p': | |
7201 | case 'q': | |
7202 | case 'A': | |
7203 | case 'B': | |
7204 | case 'E': | |
7205 | /* We use offset_reloc rather than imm_reloc for the PC | |
7206 | relative operands. This lets macros with both | |
7207 | immediate and address operands work correctly. */ | |
7208 | if (s[0] == '$' && isdigit (s[1])) | |
7209 | { | |
7210 | /* Looks like a register name. */ | |
7211 | break; | |
7212 | } | |
670a50eb | 7213 | my_getExpression (&offset_expr, s); |
cc5703cd ILT |
7214 | /* We need to relax this instruction. */ |
7215 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7216 | s = expr_end; |
7217 | continue; | |
7218 | ||
cc5703cd ILT |
7219 | case '6': /* break code */ |
7220 | my_getExpression (&imm_expr, s); | |
7221 | check_absolute_expr (ip, &imm_expr); | |
7222 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7223 | { |
cc5703cd ILT |
7224 | as_warn ("Invalid value for `%s' (%lu)", |
7225 | ip->insn_mo->name, | |
7226 | (unsigned long) imm_expr.X_add_number); | |
7227 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7228 | } |
cc5703cd ILT |
7229 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7230 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7231 | s = expr_end; |
7232 | continue; | |
3d3c5039 | 7233 | |
670a50eb ILT |
7234 | case 'a': /* 26 bit address */ |
7235 | my_getExpression (&offset_expr, s); | |
7236 | s = expr_end; | |
cc5703cd ILT |
7237 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7238 | ip->insn_opcode <<= 16; | |
670a50eb | 7239 | continue; |
3d3c5039 | 7240 | |
cc5703cd ILT |
7241 | case 'l': /* register list for entry macro */ |
7242 | case 'L': /* register list for exit macro */ | |
7243 | { | |
7244 | int mask; | |
7245 | ||
7246 | if (c == 'l') | |
7247 | mask = 0; | |
7248 | else | |
7249 | mask = 7 << 3; | |
7250 | while (*s != '\0') | |
7251 | { | |
c9167640 | 7252 | int freg, reg1, reg2; |
cc5703cd ILT |
7253 | |
7254 | while (*s == ' ' || *s == ',') | |
7255 | ++s; | |
7256 | if (*s != '$') | |
7257 | { | |
7258 | as_bad ("can't parse register list"); | |
7259 | break; | |
7260 | } | |
7261 | ++s; | |
c9167640 ILT |
7262 | if (*s != 'f') |
7263 | freg = 0; | |
7264 | else | |
7265 | { | |
7266 | freg = 1; | |
7267 | ++s; | |
7268 | } | |
cc5703cd ILT |
7269 | reg1 = 0; |
7270 | while (isdigit (*s)) | |
7271 | { | |
7272 | reg1 *= 10; | |
7273 | reg1 += *s - '0'; | |
7274 | ++s; | |
7275 | } | |
7276 | if (*s == ' ') | |
7277 | ++s; | |
7278 | if (*s != '-') | |
7279 | reg2 = reg1; | |
7280 | else | |
7281 | { | |
7282 | ++s; | |
7283 | if (*s != '$') | |
7284 | break; | |
7285 | ++s; | |
c9167640 ILT |
7286 | if (freg) |
7287 | { | |
7288 | if (*s == 'f') | |
7289 | ++s; | |
7290 | else | |
7291 | { | |
7292 | as_bad ("invalid register list"); | |
7293 | break; | |
7294 | } | |
7295 | } | |
cc5703cd ILT |
7296 | reg2 = 0; |
7297 | while (isdigit (*s)) | |
7298 | { | |
7299 | reg2 *= 10; | |
7300 | reg2 += *s - '0'; | |
7301 | ++s; | |
7302 | } | |
7303 | } | |
c9167640 ILT |
7304 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7305 | { | |
7306 | mask &= ~ (7 << 3); | |
7307 | mask |= 5 << 3; | |
7308 | } | |
7309 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7310 | { | |
7311 | mask &= ~ (7 << 3); | |
7312 | mask |= 6 << 3; | |
7313 | } | |
7314 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7315 | mask |= (reg2 - 3) << 3; |
7316 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7317 | mask |= (reg2 - 15) << 1; | |
7318 | else if (reg1 == 31 && reg2 == 31) | |
7319 | mask |= 1; | |
7320 | else | |
c9167640 ILT |
7321 | { |
7322 | as_bad ("invalid register list"); | |
7323 | break; | |
7324 | } | |
cc5703cd | 7325 | } |
c9167640 ILT |
7326 | /* The mask is filled in in the opcode table for the |
7327 | benefit of the disassembler. We remove it before | |
7328 | applying the actual mask. */ | |
7329 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7330 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7331 | } | |
7332 | continue; | |
d8a1c247 | 7333 | |
3d3c5039 | 7334 | default: |
670a50eb | 7335 | internalError (); |
3d3c5039 | 7336 | } |
670a50eb | 7337 | break; |
3d3c5039 | 7338 | } |
cc5703cd | 7339 | |
670a50eb | 7340 | /* Args don't match. */ |
cc5703cd ILT |
7341 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7342 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7343 | { |
7344 | ++insn; | |
cc5703cd | 7345 | s = argsstart; |
670a50eb | 7346 | continue; |
3d3c5039 | 7347 | } |
cc5703cd | 7348 | |
9753202d | 7349 | insn_error = "illegal operands"; |
cc5703cd | 7350 | |
670a50eb | 7351 | return; |
3d3c5039 ILT |
7352 | } |
7353 | } | |
7354 | ||
cc5703cd ILT |
7355 | /* This structure holds information we know about a mips16 immediate |
7356 | argument type. */ | |
7357 | ||
7358 | struct mips16_immed_operand | |
7359 | { | |
7360 | /* The type code used in the argument string in the opcode table. */ | |
7361 | int type; | |
7362 | /* The number of bits in the short form of the opcode. */ | |
7363 | int nbits; | |
7364 | /* The number of bits in the extended form of the opcode. */ | |
7365 | int extbits; | |
7366 | /* The amount by which the short form is shifted when it is used; | |
7367 | for example, the sw instruction has a shift count of 2. */ | |
7368 | int shift; | |
7369 | /* The amount by which the short form is shifted when it is stored | |
7370 | into the instruction code. */ | |
7371 | int op_shift; | |
7372 | /* Non-zero if the short form is unsigned. */ | |
7373 | int unsp; | |
7374 | /* Non-zero if the extended form is unsigned. */ | |
7375 | int extu; | |
7376 | /* Non-zero if the value is PC relative. */ | |
7377 | int pcrel; | |
7378 | }; | |
7379 | ||
7380 | /* The mips16 immediate operand types. */ | |
7381 | ||
7382 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7383 | { | |
7384 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7385 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7386 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7387 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7388 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7389 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7390 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7391 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7392 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7393 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7394 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7395 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7396 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7397 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7398 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7399 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7400 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7401 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7402 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7403 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7404 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7405 | }; | |
7406 | ||
7407 | #define MIPS16_NUM_IMMED \ | |
7408 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7409 | ||
7410 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7411 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7412 | whether an extended value is needed; if one is needed, it sets | |
7413 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7414 | If SMALL is true, an unextended opcode was explicitly requested. | |
7415 | If EXT is true, an extended opcode was explicitly requested. If | |
7416 | WARN is true, warn if EXT does not match reality. */ | |
7417 | ||
7418 | static void | |
15e69f98 ILT |
7419 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7420 | extend) | |
7421 | char *file; | |
7422 | unsigned int line; | |
cc5703cd ILT |
7423 | int type; |
7424 | offsetT val; | |
7425 | boolean warn; | |
7426 | boolean small; | |
7427 | boolean ext; | |
7428 | unsigned long *insn; | |
7429 | boolean *use_extend; | |
7430 | unsigned short *extend; | |
7431 | { | |
7432 | register const struct mips16_immed_operand *op; | |
7433 | int mintiny, maxtiny; | |
7434 | boolean needext; | |
7435 | ||
7436 | op = mips16_immed_operands; | |
7437 | while (op->type != type) | |
7438 | { | |
7439 | ++op; | |
7440 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7441 | } | |
7442 | ||
7443 | if (op->unsp) | |
7444 | { | |
7445 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7446 | { | |
7447 | mintiny = 1; | |
7448 | maxtiny = 1 << op->nbits; | |
7449 | } | |
7450 | else | |
7451 | { | |
7452 | mintiny = 0; | |
7453 | maxtiny = (1 << op->nbits) - 1; | |
7454 | } | |
7455 | } | |
7456 | else | |
7457 | { | |
7458 | mintiny = - (1 << (op->nbits - 1)); | |
7459 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7460 | } | |
7461 | ||
7462 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7463 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7464 | val /= 2; |
cc5703cd ILT |
7465 | |
7466 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7467 | || val < (mintiny << op->shift) | |
7468 | || val > (maxtiny << op->shift)) | |
7469 | needext = true; | |
7470 | else | |
7471 | needext = false; | |
7472 | ||
7473 | if (warn && ext && ! needext) | |
15e69f98 | 7474 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7475 | if (small && needext) |
15e69f98 | 7476 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7477 | |
7478 | if (small || (! ext && ! needext)) | |
7479 | { | |
7480 | int insnval; | |
7481 | ||
7482 | *use_extend = false; | |
7483 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7484 | insnval <<= op->op_shift; | |
7485 | *insn |= insnval; | |
7486 | } | |
7487 | else | |
7488 | { | |
7489 | long minext, maxext; | |
7490 | int extval; | |
7491 | ||
7492 | if (op->extu) | |
7493 | { | |
7494 | minext = 0; | |
7495 | maxext = (1 << op->extbits) - 1; | |
7496 | } | |
7497 | else | |
7498 | { | |
7499 | minext = - (1 << (op->extbits - 1)); | |
7500 | maxext = (1 << (op->extbits - 1)) - 1; | |
7501 | } | |
7502 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7503 | as_bad_where (file, line, |
7504 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7505 | |
7506 | *use_extend = true; | |
7507 | if (op->extbits == 16) | |
7508 | { | |
7509 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7510 | val &= 0x1f; | |
7511 | } | |
7512 | else if (op->extbits == 15) | |
7513 | { | |
7514 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7515 | val &= 0xf; | |
7516 | } | |
7517 | else | |
7518 | { | |
7519 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7520 | val = 0; | |
7521 | } | |
7522 | ||
7523 | *extend = (unsigned short) extval; | |
7524 | *insn |= val; | |
7525 | } | |
7526 | } | |
7527 | \f | |
3d3c5039 ILT |
7528 | #define LP '(' |
7529 | #define RP ')' | |
7530 | ||
7531 | static int | |
7532 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7533 | expressionS *ep; |
7534 | char *str; | |
3d3c5039 | 7535 | { |
670a50eb ILT |
7536 | char *sp; |
7537 | int c = 0; | |
7538 | ||
7539 | if (*str == ' ') | |
7540 | str++; | |
7541 | if (*str == LP | |
7542 | || (*str == '%' && | |
7543 | ((str[1] == 'h' && str[2] == 'i') | |
7544 | || (str[1] == 'H' && str[2] == 'I') | |
7545 | || (str[1] == 'l' && str[2] == 'o')) | |
7546 | && str[3] == LP)) | |
7547 | { | |
7548 | if (*str == LP) | |
7549 | c = 0; | |
7550 | else | |
7551 | { | |
7552 | c = str[1]; | |
7553 | str += 3; | |
7554 | } | |
7555 | ||
7556 | /* | |
7557 | * A small expression may be followed by a base register. | |
7558 | * Scan to the end of this operand, and then back over a possible | |
7559 | * base register. Then scan the small expression up to that | |
7560 | * point. (Based on code in sparc.c...) | |
7561 | */ | |
7562 | for (sp = str; *sp && *sp != ','; sp++) | |
7563 | ; | |
7564 | if (sp - 4 >= str && sp[-1] == RP) | |
7565 | { | |
7566 | if (isdigit (sp[-2])) | |
7567 | { | |
7568 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7569 | ; | |
7570 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7571 | { | |
7572 | sp--; | |
7573 | goto do_it; | |
3d3c5039 | 7574 | } |
670a50eb ILT |
7575 | } |
7576 | else if (sp - 5 >= str | |
7577 | && sp[-5] == LP | |
7578 | && sp[-4] == '$' | |
7579 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7580 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7581 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7582 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7583 | { | |
7584 | sp -= 5; | |
3d3c5039 | 7585 | do_it: |
670a50eb ILT |
7586 | if (sp == str) |
7587 | { | |
7588 | /* no expression means zero offset */ | |
7589 | if (c) | |
7590 | { | |
7591 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7592 | ep->X_op = O_absent; |
670a50eb | 7593 | expr_end = str - 3; |
3d3c5039 | 7594 | } |
670a50eb ILT |
7595 | else |
7596 | { | |
52aa70b5 | 7597 | ep->X_op = O_constant; |
670a50eb ILT |
7598 | expr_end = sp; |
7599 | } | |
7600 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7601 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7602 | ep->X_add_number = 0; |
7603 | } | |
7604 | else | |
7605 | { | |
7606 | *sp = '\0'; | |
7607 | my_getExpression (ep, str); | |
7608 | *sp = LP; | |
3d3c5039 | 7609 | } |
670a50eb | 7610 | return c; |
3d3c5039 ILT |
7611 | } |
7612 | } | |
7613 | } | |
670a50eb ILT |
7614 | my_getExpression (ep, str); |
7615 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7616 | } |
7617 | ||
7618 | static void | |
7619 | my_getExpression (ep, str) | |
670a50eb ILT |
7620 | expressionS *ep; |
7621 | char *str; | |
3d3c5039 | 7622 | { |
670a50eb | 7623 | char *save_in; |
670a50eb ILT |
7624 | |
7625 | save_in = input_line_pointer; | |
7626 | input_line_pointer = str; | |
5ac34ac3 | 7627 | expression (ep); |
670a50eb ILT |
7628 | expr_end = input_line_pointer; |
7629 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7630 | } |
7631 | ||
becfe05e ILT |
7632 | /* Turn a string in input_line_pointer into a floating point constant |
7633 | of type type, and store the appropriate bytes in *litP. The number | |
7634 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7635 | returned, or NULL on OK. */ | |
7636 | ||
3d3c5039 | 7637 | char * |
670a50eb | 7638 | md_atof (type, litP, sizeP) |
becfe05e | 7639 | int type; |
3d3c5039 ILT |
7640 | char *litP; |
7641 | int *sizeP; | |
7642 | { | |
becfe05e ILT |
7643 | int prec; |
7644 | LITTLENUM_TYPE words[4]; | |
7645 | char *t; | |
7646 | int i; | |
7647 | ||
7648 | switch (type) | |
7649 | { | |
7650 | case 'f': | |
7651 | prec = 2; | |
7652 | break; | |
7653 | ||
7654 | case 'd': | |
7655 | prec = 4; | |
7656 | break; | |
7657 | ||
7658 | default: | |
7659 | *sizeP = 0; | |
7660 | return "bad call to md_atof"; | |
7661 | } | |
7662 | ||
7663 | t = atof_ieee (input_line_pointer, type, words); | |
7664 | if (t) | |
7665 | input_line_pointer = t; | |
7666 | ||
7667 | *sizeP = prec * 2; | |
7668 | ||
b9129c6f | 7669 | if (! target_big_endian) |
becfe05e ILT |
7670 | { |
7671 | for (i = prec - 1; i >= 0; i--) | |
7672 | { | |
7673 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7674 | litP += 2; | |
7675 | } | |
7676 | } | |
7677 | else | |
7678 | { | |
7679 | for (i = 0; i < prec; i++) | |
7680 | { | |
7681 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7682 | litP += 2; | |
7683 | } | |
7684 | } | |
7685 | ||
670a50eb | 7686 | return NULL; |
3d3c5039 ILT |
7687 | } |
7688 | ||
7689 | void | |
7690 | md_number_to_chars (buf, val, n) | |
7691 | char *buf; | |
918692a5 | 7692 | valueT val; |
3d3c5039 ILT |
7693 | int n; |
7694 | { | |
b9129c6f ILT |
7695 | if (target_big_endian) |
7696 | number_to_chars_bigendian (buf, val, n); | |
7697 | else | |
7698 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 7699 | } |
f3d817d8 | 7700 | \f |
e8d4d475 | 7701 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7702 | |
f3d817d8 DM |
7703 | struct option md_longopts[] = { |
7704 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7705 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7706 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7707 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7708 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7709 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7710 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7711 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7712 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7713 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7714 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7715 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7716 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7717 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7718 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7719 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7720 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7721 | {"break", no_argument, NULL, OPTION_BREAK}, |
7722 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7723 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7724 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7725 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7726 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7727 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7728 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7729 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7730 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7731 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7732 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7733 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7734 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7735 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7736 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7737 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7738 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7739 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7740 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7741 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7742 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
276c2d7d GRK |
7743 | /* start-sanitize-5900 */ |
7744 | #define OPTION_M5900 (OPTION_MD_BASE + 24) | |
7745 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
7746 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
7747 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
7748 | /* end-sanitize-5900 */ | |
f3d817d8 | 7749 | |
d8a1c247 | 7750 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7751 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7752 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7753 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7754 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7755 | #ifdef OBJ_ELF |
f3d817d8 | 7756 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7757 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7758 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7759 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7760 | {"32", no_argument, NULL, OPTION_32}, |
7761 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7762 | #endif |
7763 | ||
7764 | {NULL, no_argument, NULL, 0} | |
7765 | }; | |
7766 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7767 | |
7768 | int | |
f3d817d8 DM |
7769 | md_parse_option (c, arg) |
7770 | int c; | |
7771 | char *arg; | |
3d3c5039 | 7772 | { |
f3d817d8 | 7773 | switch (c) |
670a50eb | 7774 | { |
f3d817d8 DM |
7775 | case OPTION_TRAP: |
7776 | mips_trap = 1; | |
7777 | break; | |
670a50eb | 7778 | |
f3d817d8 DM |
7779 | case OPTION_BREAK: |
7780 | mips_trap = 0; | |
7781 | break; | |
7782 | ||
e8d4d475 | 7783 | case OPTION_EB: |
1dc1e798 | 7784 | target_big_endian = 1; |
e8d4d475 | 7785 | break; |
04cb3372 | 7786 | |
e8d4d475 | 7787 | case OPTION_EL: |
1dc1e798 | 7788 | target_big_endian = 0; |
f3d817d8 | 7789 | break; |
670a50eb | 7790 | |
f3d817d8 DM |
7791 | case 'O': |
7792 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7793 | mips_optimize = 1; |
7794 | else | |
7795 | mips_optimize = 2; | |
f3d817d8 | 7796 | break; |
0aa07269 | 7797 | |
f3d817d8 | 7798 | case 'g': |
22ba90ce ILT |
7799 | if (arg == NULL) |
7800 | mips_debug = 2; | |
7801 | else | |
7802 | mips_debug = atoi (arg); | |
7803 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7804 | optimizations which limit full symbolic debugging. We take | |
7805 | that to be equivalent to -O0. */ | |
7806 | if (mips_debug == 2) | |
0aa07269 | 7807 | mips_optimize = 0; |
f3d817d8 | 7808 | break; |
4e95866e | 7809 | |
f3d817d8 DM |
7810 | case OPTION_MIPS1: |
7811 | mips_isa = 1; | |
4bb0cc41 ILT |
7812 | if (mips_cpu == -1) |
7813 | mips_cpu = 3000; | |
f3d817d8 | 7814 | break; |
8358c818 | 7815 | |
f3d817d8 DM |
7816 | case OPTION_MIPS2: |
7817 | mips_isa = 2; | |
4bb0cc41 ILT |
7818 | if (mips_cpu == -1) |
7819 | mips_cpu = 6000; | |
f3d817d8 | 7820 | break; |
8358c818 | 7821 | |
f3d817d8 DM |
7822 | case OPTION_MIPS3: |
7823 | mips_isa = 3; | |
4bb0cc41 ILT |
7824 | if (mips_cpu == -1) |
7825 | mips_cpu = 4000; | |
f3d817d8 | 7826 | break; |
8358c818 | 7827 | |
d8a1c247 KR |
7828 | case OPTION_MIPS4: |
7829 | mips_isa = 4; | |
7830 | if (mips_cpu == -1) | |
7831 | mips_cpu = 8000; | |
7832 | break; | |
7833 | ||
f3d817d8 DM |
7834 | case OPTION_MCPU: |
7835 | { | |
7836 | char *p; | |
7837 | ||
7838 | /* Identify the processor type */ | |
7839 | p = arg; | |
7840 | if (strcmp (p, "default") == 0 | |
7841 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7842 | mips_cpu = -1; |
f3d817d8 DM |
7843 | else |
7844 | { | |
c625fc23 JSC |
7845 | int sv = 0; |
7846 | ||
7847 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7848 | processor. */ | |
7849 | if (*p == 'v' || *p == 'V') | |
7850 | { | |
7851 | sv = 1; | |
7852 | p++; | |
7853 | } | |
7854 | ||
f3d817d8 DM |
7855 | if (*p == 'r' || *p == 'R') |
7856 | p++; | |
8358c818 | 7857 | |
4bb0cc41 | 7858 | mips_cpu = -1; |
f3d817d8 DM |
7859 | switch (*p) |
7860 | { | |
d8a1c247 KR |
7861 | case '1': |
7862 | if (strcmp (p, "10000") == 0 | |
7863 | || strcmp (p, "10k") == 0 | |
7864 | || strcmp (p, "10K") == 0) | |
7865 | mips_cpu = 10000; | |
7866 | break; | |
7867 | ||
f3d817d8 DM |
7868 | case '2': |
7869 | if (strcmp (p, "2000") == 0 | |
7870 | || strcmp (p, "2k") == 0 | |
7871 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7872 | mips_cpu = 2000; |
f3d817d8 | 7873 | break; |
8358c818 | 7874 | |
f3d817d8 DM |
7875 | case '3': |
7876 | if (strcmp (p, "3000") == 0 | |
7877 | || strcmp (p, "3k") == 0 | |
7878 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7879 | mips_cpu = 3000; |
f3d817d8 | 7880 | break; |
8358c818 | 7881 | |
f3d817d8 DM |
7882 | case '4': |
7883 | if (strcmp (p, "4000") == 0 | |
7884 | || strcmp (p, "4k") == 0 | |
8c63448a | 7885 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7886 | mips_cpu = 4000; |
c625fc23 JSC |
7887 | else if (strcmp (p, "4100") == 0) |
7888 | { | |
7889 | mips_cpu = 4100; | |
7890 | if (mips_4100 < 0) | |
7891 | mips_4100 = 1; | |
7892 | } | |
7893 | else if (strcmp (p, "4300") == 0) | |
7894 | mips_cpu = 4300; | |
8c63448a | 7895 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7896 | mips_cpu = 4400; |
8c63448a | 7897 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7898 | mips_cpu = 4600; |
b2b8c24e ILT |
7899 | else if (strcmp (p, "4650") == 0) |
7900 | { | |
7901 | mips_cpu = 4650; | |
7902 | if (mips_4650 < 0) | |
7903 | mips_4650 = 1; | |
7904 | } | |
e532b44c ILT |
7905 | else if (strcmp (p, "4010") == 0) |
7906 | { | |
7907 | mips_cpu = 4010; | |
7908 | if (mips_4010 < 0) | |
7909 | mips_4010 = 1; | |
7910 | } | |
f3d817d8 | 7911 | break; |
8358c818 | 7912 | |
517078c1 ILT |
7913 | case '5': |
7914 | if (strcmp (p, "5000") == 0 | |
7915 | || strcmp (p, "5k") == 0 | |
7916 | || strcmp (p, "5K") == 0) | |
7917 | mips_cpu = 5000; | |
276c2d7d GRK |
7918 | /* start-sanitize-r5900 */ |
7919 | else if (strcmp (p, "5900") == 0) | |
7920 | mips_cpu = 5900; | |
7921 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
7922 | break; |
7923 | ||
f3d817d8 DM |
7924 | case '6': |
7925 | if (strcmp (p, "6000") == 0 | |
7926 | || strcmp (p, "6k") == 0 | |
7927 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7928 | mips_cpu = 6000; |
f3d817d8 | 7929 | break; |
55933a58 | 7930 | |
d8a1c247 KR |
7931 | case '8': |
7932 | if (strcmp (p, "8000") == 0 | |
7933 | || strcmp (p, "8k") == 0 | |
7934 | || strcmp (p, "8K") == 0) | |
7935 | mips_cpu = 8000; | |
7936 | break; | |
7937 | ||
55933a58 ILT |
7938 | case 'o': |
7939 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7940 | mips_cpu = 4600; |
55933a58 | 7941 | break; |
f3d817d8 | 7942 | } |
8358c818 | 7943 | |
517078c1 | 7944 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7945 | { |
7946 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
7947 | return 0; | |
7948 | } | |
7949 | ||
4bb0cc41 | 7950 | if (mips_cpu == -1) |
f3d817d8 DM |
7951 | { |
7952 | as_bad ("invalid architecture -mcpu=%s", arg); | |
7953 | return 0; | |
7954 | } | |
7955 | } | |
7956 | } | |
7957 | break; | |
8358c818 | 7958 | |
b2b8c24e ILT |
7959 | case OPTION_M4650: |
7960 | mips_4650 = 1; | |
7961 | break; | |
7962 | ||
7963 | case OPTION_NO_M4650: | |
7964 | mips_4650 = 0; | |
7965 | break; | |
7966 | ||
e532b44c ILT |
7967 | case OPTION_M4010: |
7968 | mips_4010 = 1; | |
7969 | break; | |
7970 | ||
7971 | case OPTION_NO_M4010: | |
7972 | mips_4010 = 0; | |
7973 | break; | |
7974 | ||
c625fc23 JSC |
7975 | case OPTION_M4100: |
7976 | mips_4100 = 1; | |
7977 | break; | |
7978 | ||
7979 | case OPTION_NO_M4100: | |
7980 | mips_4100 = 0; | |
7981 | break; | |
7982 | ||
276c2d7d GRK |
7983 | /* start-sanitize-r5900 */ |
7984 | case OPTION_M5900: | |
7985 | mips_5900 = 1; | |
7986 | break; | |
7987 | ||
7988 | case OPTION_NO_M5900: | |
7989 | mips_5900 = 0; | |
7990 | break; | |
7991 | /* end-sanitize-r5900 */ | |
7992 | ||
cc5703cd ILT |
7993 | case OPTION_MIPS16: |
7994 | mips16 = 1; | |
7995 | mips_no_prev_insn (); | |
7996 | break; | |
7997 | ||
7998 | case OPTION_NO_MIPS16: | |
7999 | mips16 = 0; | |
8000 | mips_no_prev_insn (); | |
8001 | break; | |
8002 | ||
f3d817d8 | 8003 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8004 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8005 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8006 | { |
8007 | as_bad ("-G may not be used with embedded PIC code"); | |
8008 | return 0; | |
8009 | } | |
5b63f465 | 8010 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8011 | break; |
d9aba805 | 8012 | |
fb251650 ILT |
8013 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8014 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8015 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8016 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8017 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8018 | { | |
8019 | as_bad ("-call_shared is supported only for ELF format"); | |
8020 | return 0; | |
8021 | } | |
d9aba805 ILT |
8022 | mips_pic = SVR4_PIC; |
8023 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8024 | { |
8025 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8026 | return 0; | |
8027 | } | |
d9aba805 | 8028 | g_switch_value = 0; |
f3d817d8 DM |
8029 | break; |
8030 | ||
8031 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8032 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8033 | { | |
8034 | as_bad ("-non_shared is supported only for ELF format"); | |
8035 | return 0; | |
8036 | } | |
d9aba805 | 8037 | mips_pic = NO_PIC; |
f3d817d8 | 8038 | break; |
8358c818 | 8039 | |
fb251650 ILT |
8040 | /* The -xgot option tells the assembler to use 32 offsets when |
8041 | accessing the got in SVR4_PIC mode. It is for Irix | |
8042 | compatibility. */ | |
8043 | case OPTION_XGOT: | |
8044 | mips_big_got = 1; | |
8045 | break; | |
8046 | ||
f3d817d8 | 8047 | case 'G': |
1dc1e798 KR |
8048 | if (! USE_GLOBAL_POINTER_OPT) |
8049 | { | |
8050 | as_bad ("-G is not supported for this configuration"); | |
8051 | return 0; | |
8052 | } | |
8053 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8054 | { |
f3d817d8 DM |
8055 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8056 | return 0; | |
670a50eb ILT |
8057 | } |
8058 | else | |
f3d817d8 | 8059 | g_switch_value = atoi (arg); |
42562568 | 8060 | g_switch_seen = 1; |
f3d817d8 | 8061 | break; |
4e95866e | 8062 | |
7f9880e5 ILT |
8063 | /* The -32 and -64 options tell the assembler to output the 32 |
8064 | bit or the 64 bit MIPS ELF format. */ | |
8065 | case OPTION_32: | |
8066 | mips_64 = 0; | |
8067 | break; | |
8068 | ||
8069 | case OPTION_64: | |
9c44af60 ILT |
8070 | { |
8071 | const char **list, **l; | |
8072 | ||
8073 | list = bfd_target_list (); | |
8074 | for (l = list; *l != NULL; l++) | |
8075 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8076 | || strcmp (*l, "elf64-littlemips") == 0) | |
8077 | break; | |
8078 | if (*l == NULL) | |
8079 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8080 | free (list); | |
8081 | mips_64 = 1; | |
8082 | } | |
7f9880e5 ILT |
8083 | break; |
8084 | ||
f3d817d8 DM |
8085 | default: |
8086 | return 0; | |
8ea7f4e8 ILT |
8087 | } |
8088 | ||
f3d817d8 | 8089 | return 1; |
8ea7f4e8 ILT |
8090 | } |
8091 | ||
f3d817d8 DM |
8092 | void |
8093 | md_show_usage (stream) | |
8094 | FILE *stream; | |
8095 | { | |
8096 | fprintf(stream, "\ | |
8097 | MIPS options:\n\ | |
8098 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8099 | -EB generate big endian output\n\ |
8100 | -EL generate little endian output\n\ | |
8101 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8102 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8103 | implicitly with the gp register [default 8]\n"); |
8104 | fprintf(stream, "\ | |
f3d817d8 DM |
8105 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8106 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8107 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8108 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8109 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8110 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8111 | -m4650 permit R4650 instructions\n\ |
8112 | -no-m4650 do not permit R4650 instructions\n\ | |
8113 | -m4010 permit R4010 instructions\n\ | |
8114 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8115 | -m4100 permit VR4100 instructions\n\ |
8116 | -no-m4100 do not permit VR4100 instructions\n"); | |
8117 | fprintf(stream, "\ | |
cc5703cd ILT |
8118 | -mips16 generate mips16 instructions\n\ |
8119 | -no-mips16 do not generate mips16 instructions\n"); | |
8120 | fprintf(stream, "\ | |
f3d817d8 DM |
8121 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8122 | -O remove unneeded NOPs and swap branches\n\ | |
8123 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8124 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8125 | #ifdef OBJ_ELF | |
8126 | fprintf(stream, "\ | |
8127 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8128 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8129 | -xgot assume a 32 bit GOT\n\ |
8130 | -32 create 32 bit object file (default)\n\ | |
8131 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8132 | #endif |
8133 | } | |
8134 | \f | |
3d3c5039 ILT |
8135 | long |
8136 | md_pcrel_from (fixP) | |
8137 | fixS *fixP; | |
8138 | { | |
1dc1e798 KR |
8139 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8140 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8141 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8142 | { | |
8143 | /* This makes a branch to an undefined symbol be a branch to the | |
8144 | current location. */ | |
8145 | return 4; | |
8146 | } | |
5b63f465 | 8147 | |
670a50eb ILT |
8148 | /* return the address of the delay slot */ |
8149 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8150 | } |
8151 | ||
abdad6bc ILT |
8152 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8153 | reloc for a cons. We could use the definition there, except that | |
8154 | we want to handle 64 bit relocs specially. */ | |
8155 | ||
8156 | void | |
8157 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8158 | fragS *frag; | |
8159 | int where; | |
8160 | unsigned int nbytes; | |
8161 | expressionS *exp; | |
8162 | { | |
bf39474f | 8163 | #ifndef OBJ_ELF |
abdad6bc | 8164 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8165 | 4 byte reloc. */ |
8166 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8167 | { |
b9129c6f | 8168 | if (target_big_endian) |
abdad6bc ILT |
8169 | where += 4; |
8170 | nbytes = 4; | |
8171 | } | |
bf39474f | 8172 | #endif |
abdad6bc | 8173 | |
7f9880e5 | 8174 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8175 | as_bad ("Unsupported reloc size %d", nbytes); |
8176 | ||
8177 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8178 | (nbytes == 2 |
8179 | ? BFD_RELOC_16 | |
8180 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8181 | } |
8182 | ||
867a58b3 ILT |
8183 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8184 | the corresponding LO reloc. This is called before md_apply_fix and | |
8185 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8186 | explicit use of the %hi modifier. */ | |
8187 | ||
8188 | void | |
8189 | mips_frob_file () | |
8190 | { | |
8191 | struct mips_hi_fixup *l; | |
8192 | ||
8193 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8194 | { | |
8195 | segment_info_type *seginfo; | |
9b61d62b | 8196 | int pass; |
867a58b3 ILT |
8197 | |
8198 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8199 | ||
8200 | /* Check quickly whether the next fixup happens to be a matching | |
8201 | %lo. */ | |
8202 | if (l->fixp->fx_next != NULL | |
8203 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8204 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8205 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8206 | continue; | |
8207 | ||
8208 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8209 | When we find one, move the %hi just in front of it. We do |
8210 | this in two passes. In the first pass, we try to find a | |
8211 | unique %lo. In the second pass, we permit multiple %hi | |
8212 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8213 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8214 | for (pass = 0; pass < 2; pass++) |
8215 | { | |
8216 | fixS *f, *prev; | |
8217 | ||
8218 | prev = NULL; | |
8219 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8220 | { |
9b61d62b ILT |
8221 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8222 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8223 | && f->fx_addsy == l->fixp->fx_addsy | |
8224 | && f->fx_offset == l->fixp->fx_offset | |
8225 | && (pass == 1 | |
8226 | || prev == NULL | |
8227 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8228 | || prev->fx_addsy != f->fx_addsy | |
8229 | || prev->fx_offset != f->fx_offset)) | |
8230 | { | |
8231 | fixS **pf; | |
867a58b3 | 8232 | |
9b61d62b ILT |
8233 | /* Move l->fixp before f. */ |
8234 | for (pf = &seginfo->fix_root; | |
8235 | *pf != l->fixp; | |
8236 | pf = &(*pf)->fx_next) | |
8237 | assert (*pf != NULL); | |
867a58b3 | 8238 | |
9b61d62b | 8239 | *pf = l->fixp->fx_next; |
867a58b3 | 8240 | |
9b61d62b ILT |
8241 | l->fixp->fx_next = f; |
8242 | if (prev == NULL) | |
8243 | seginfo->fix_root = l->fixp; | |
8244 | else | |
8245 | prev->fx_next = l->fixp; | |
867a58b3 | 8246 | |
9b61d62b ILT |
8247 | break; |
8248 | } | |
8249 | ||
8250 | prev = f; | |
867a58b3 ILT |
8251 | } |
8252 | ||
9b61d62b ILT |
8253 | if (f != NULL) |
8254 | break; | |
867a58b3 | 8255 | |
9b61d62b ILT |
8256 | if (pass == 1) |
8257 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8258 | "Unmatched %%hi reloc"); | |
8259 | } | |
867a58b3 ILT |
8260 | } |
8261 | } | |
8262 | ||
1c803e52 ILT |
8263 | /* When generating embedded PIC code we need to use a special |
8264 | relocation to represent the difference of two symbols in the .text | |
8265 | section (switch tables use a difference of this sort). See | |
8266 | include/coff/mips.h for details. This macro checks whether this | |
8267 | fixup requires the special reloc. */ | |
8268 | #define SWITCH_TABLE(fixp) \ | |
8269 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8270 | && (fixp)->fx_addsy != NULL \ | |
8271 | && (fixp)->fx_subsy != NULL \ | |
8272 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8273 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8274 | ||
5b63f465 | 8275 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8276 | relocations, in case the linker has to relax a call. We also need |
8277 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8278 | |
8279 | /*ARGSUSED*/ | |
8280 | int | |
8281 | mips_force_relocation (fixp) | |
8282 | fixS *fixp; | |
8283 | { | |
1c803e52 | 8284 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8285 | && (fixp->fx_pcrel |
8286 | || SWITCH_TABLE (fixp) | |
8287 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8288 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8289 | } |
8290 | ||
8291 | /* Apply a fixup to the object file. */ | |
8292 | ||
3d3c5039 ILT |
8293 | int |
8294 | md_apply_fix (fixP, valueP) | |
8295 | fixS *fixP; | |
918692a5 | 8296 | valueT *valueP; |
3d3c5039 | 8297 | { |
670a50eb ILT |
8298 | unsigned char *buf; |
8299 | long insn, value; | |
3d3c5039 | 8300 | |
bf39474f ILT |
8301 | assert (fixP->fx_size == 4 |
8302 | || fixP->fx_r_type == BFD_RELOC_16 | |
8303 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8304 | |
670a50eb | 8305 | value = *valueP; |
1748b9d8 ILT |
8306 | |
8307 | /* If we aren't adjusting this fixup to be against the section | |
8308 | symbol, we need to adjust the value. */ | |
8309 | #ifdef S_GET_OTHER | |
8310 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8311 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8312 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8313 | { | |
8314 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8315 | if (value != 0 && ! fixP->fx_pcrel) | |
8316 | { | |
8317 | /* In this case, the bfd_install_relocation routine will | |
8318 | incorrectly add the symbol value back in. We just want | |
8319 | the addend to appear in the object file. */ | |
8320 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8321 | } | |
8322 | } | |
8323 | #endif | |
8324 | ||
670a50eb | 8325 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8326 | |
5b63f465 ILT |
8327 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8328 | fixP->fx_done = 1; | |
8329 | ||
670a50eb ILT |
8330 | switch (fixP->fx_r_type) |
8331 | { | |
3d3c5039 ILT |
8332 | case BFD_RELOC_MIPS_JMP: |
8333 | case BFD_RELOC_HI16: | |
8334 | case BFD_RELOC_HI16_S: | |
670a50eb | 8335 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8336 | case BFD_RELOC_MIPS_LITERAL: |
8337 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8338 | case BFD_RELOC_MIPS_GOT16: |
8339 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8340 | case BFD_RELOC_MIPS_GOT_HI16: |
8341 | case BFD_RELOC_MIPS_GOT_LO16: | |
8342 | case BFD_RELOC_MIPS_CALL_HI16: | |
8343 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 8344 | if (fixP->fx_pcrel) |
7b777690 ILT |
8345 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8346 | "Invalid PC relative reloc"); | |
670a50eb | 8347 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8348 | break; |
3d3c5039 | 8349 | |
cc5703cd ILT |
8350 | case BFD_RELOC_MIPS16_JMP: |
8351 | /* We currently always generate a reloc against a symbol, which | |
8352 | means that we don't want an addend even if the symbol is | |
8353 | defined. */ | |
8354 | fixP->fx_addnumber = 0; | |
8355 | break; | |
8356 | ||
ecd4ca1c ILT |
8357 | case BFD_RELOC_PCREL_HI16_S: |
8358 | /* The addend for this is tricky if it is internal, so we just | |
8359 | do everything here rather than in bfd_perform_relocation. */ | |
8360 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8361 | { | |
8362 | /* For an external symbol adjust by the address to make it | |
8363 | pcrel_offset. We use the address of the RELLO reloc | |
8364 | which follows this one. */ | |
8365 | value += (fixP->fx_next->fx_frag->fr_address | |
8366 | + fixP->fx_next->fx_where); | |
8367 | } | |
8368 | if (value & 0x8000) | |
8369 | value += 0x10000; | |
8370 | value >>= 16; | |
0221ddf7 | 8371 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8372 | if (target_big_endian) |
ecd4ca1c ILT |
8373 | buf += 2; |
8374 | md_number_to_chars (buf, value, 2); | |
8375 | break; | |
8376 | ||
8377 | case BFD_RELOC_PCREL_LO16: | |
8378 | /* The addend for this is tricky if it is internal, so we just | |
8379 | do everything here rather than in bfd_perform_relocation. */ | |
8380 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8381 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8382 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8383 | if (target_big_endian) |
ecd4ca1c ILT |
8384 | buf += 2; |
8385 | md_number_to_chars (buf, value, 2); | |
8386 | break; | |
8387 | ||
bf39474f ILT |
8388 | case BFD_RELOC_64: |
8389 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8390 | extended value if we are only 32 bits. */ | |
8391 | if (fixP->fx_done | |
8392 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8393 | { | |
8394 | if (8 <= sizeof (valueT)) | |
8395 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8396 | value, 8); | |
8397 | else | |
8398 | { | |
8399 | long w1, w2; | |
8400 | long hiv; | |
8401 | ||
8402 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8403 | if (target_big_endian) |
bf39474f ILT |
8404 | w1 += 4; |
8405 | else | |
8406 | w2 += 4; | |
8407 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8408 | if ((value & 0x80000000) != 0) | |
8409 | hiv = 0xffffffff; | |
8410 | else | |
8411 | hiv = 0; | |
8412 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8413 | } | |
8414 | } | |
8415 | break; | |
8416 | ||
f3645945 ILT |
8417 | case BFD_RELOC_32: |
8418 | /* If we are deleting this reloc entry, we must fill in the | |
8419 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8420 | resolved when it appears but is later defined. We also need |
8421 | to fill in the value if this is an embedded PIC switch table | |
8422 | entry. */ | |
8423 | if (fixP->fx_done | |
8424 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8425 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8426 | value, 4); | |
8427 | break; | |
8428 | ||
49ad0c4c ILT |
8429 | case BFD_RELOC_16: |
8430 | /* If we are deleting this reloc entry, we must fill in the | |
8431 | value now. */ | |
8432 | assert (fixP->fx_size == 2); | |
8433 | if (fixP->fx_done) | |
8434 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8435 | value, 2); | |
8436 | break; | |
8437 | ||
f3645945 ILT |
8438 | case BFD_RELOC_LO16: |
8439 | /* When handling an embedded PIC switch statement, we can wind | |
8440 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8441 | if (fixP->fx_done) | |
8442 | { | |
8443 | if (value < -0x8000 || value > 0x7fff) | |
8444 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8445 | "relocation overflow"); | |
0221ddf7 | 8446 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8447 | if (target_big_endian) |
f3645945 ILT |
8448 | buf += 2; |
8449 | md_number_to_chars (buf, value, 2); | |
8450 | } | |
8451 | break; | |
8452 | ||
3d3c5039 | 8453 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8454 | /* |
8455 | * We need to save the bits in the instruction since fixup_segment() | |
8456 | * might be deleting the relocation entry (i.e., a branch within | |
8457 | * the current segment). | |
8458 | */ | |
fbcfacb7 | 8459 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8460 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8461 | "Branch to odd address (%lx)", value); | |
670a50eb | 8462 | value >>= 2; |
670a50eb ILT |
8463 | |
8464 | /* update old instruction data */ | |
8465 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8466 | if (target_big_endian) |
8467 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8468 | else | |
8469 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8470 | |
8471 | if (value >= -0x8000 && value < 0x8000) | |
8472 | insn |= value & 0xffff; | |
8473 | else | |
8474 | { | |
8475 | /* The branch offset is too large. If this is an | |
8476 | unconditional branch, and we are not generating PIC code, | |
8477 | we can convert it to an absolute jump instruction. */ | |
8478 | if (mips_pic == NO_PIC | |
8479 | && fixP->fx_done | |
8480 | && fixP->fx_frag->fr_address >= text_section->vma | |
8481 | && (fixP->fx_frag->fr_address | |
8482 | < text_section->vma + text_section->_raw_size) | |
8483 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8484 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8485 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8486 | { | |
8487 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8488 | insn = 0x0c000000; /* jal */ | |
8489 | else | |
8490 | insn = 0x08000000; /* j */ | |
8491 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8492 | fixP->fx_done = 0; | |
8493 | fixP->fx_addsy = section_symbol (text_section); | |
8494 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8495 | } | |
8496 | else | |
8497 | { | |
8498 | /* FIXME. It would be possible in principle to handle | |
8499 | conditional branches which overflow. They could be | |
8500 | transformed into a branch around a jump. This would | |
8501 | require setting up variant frags for each different | |
8502 | branch type. The native MIPS assembler attempts to | |
8503 | handle these cases, but it appears to do it | |
8504 | incorrectly. */ | |
8505 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8506 | "Relocation overflow"); | |
8507 | } | |
8508 | } | |
8509 | ||
604633ae | 8510 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8511 | break; |
3d3c5039 ILT |
8512 | |
8513 | default: | |
670a50eb | 8514 | internalError (); |
3d3c5039 | 8515 | } |
5b63f465 | 8516 | |
670a50eb | 8517 | return 1; |
3d3c5039 ILT |
8518 | } |
8519 | ||
8520 | #if 0 | |
8521 | void | |
670a50eb ILT |
8522 | printInsn (oc) |
8523 | unsigned long oc; | |
3d3c5039 | 8524 | { |
670a50eb ILT |
8525 | const struct mips_opcode *p; |
8526 | int treg, sreg, dreg, shamt; | |
8527 | short imm; | |
8528 | const char *args; | |
8529 | int i; | |
3d3c5039 | 8530 | |
670a50eb ILT |
8531 | for (i = 0; i < NUMOPCODES; ++i) |
8532 | { | |
8533 | p = &mips_opcodes[i]; | |
8534 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8535 | { | |
8536 | printf ("%08lx %s\t", oc, p->name); | |
8537 | treg = (oc >> 16) & 0x1f; | |
8538 | sreg = (oc >> 21) & 0x1f; | |
8539 | dreg = (oc >> 11) & 0x1f; | |
8540 | shamt = (oc >> 6) & 0x1f; | |
8541 | imm = oc; | |
8542 | for (args = p->args;; ++args) | |
8543 | { | |
8544 | switch (*args) | |
8545 | { | |
3d3c5039 | 8546 | case '\0': |
670a50eb ILT |
8547 | printf ("\n"); |
8548 | break; | |
3d3c5039 ILT |
8549 | |
8550 | case ',': | |
8551 | case '(': | |
8552 | case ')': | |
670a50eb ILT |
8553 | printf ("%c", *args); |
8554 | continue; | |
3d3c5039 ILT |
8555 | |
8556 | case 'r': | |
670a50eb ILT |
8557 | assert (treg == sreg); |
8558 | printf ("$%d,$%d", treg, sreg); | |
8559 | continue; | |
3d3c5039 ILT |
8560 | |
8561 | case 'd': | |
918692a5 | 8562 | case 'G': |
670a50eb ILT |
8563 | printf ("$%d", dreg); |
8564 | continue; | |
3d3c5039 ILT |
8565 | |
8566 | case 't': | |
918692a5 | 8567 | case 'E': |
670a50eb ILT |
8568 | printf ("$%d", treg); |
8569 | continue; | |
3d3c5039 | 8570 | |
9226253a ILT |
8571 | case 'k': |
8572 | printf ("0x%x", treg); | |
8573 | continue; | |
8574 | ||
3d3c5039 ILT |
8575 | case 'b': |
8576 | case 's': | |
670a50eb ILT |
8577 | printf ("$%d", sreg); |
8578 | continue; | |
3d3c5039 ILT |
8579 | |
8580 | case 'a': | |
670a50eb ILT |
8581 | printf ("0x%08lx", oc & 0x1ffffff); |
8582 | continue; | |
3d3c5039 ILT |
8583 | |
8584 | case 'i': | |
8585 | case 'j': | |
8586 | case 'o': | |
8587 | case 'u': | |
670a50eb ILT |
8588 | printf ("%d", imm); |
8589 | continue; | |
3d3c5039 ILT |
8590 | |
8591 | case '<': | |
56c96faa | 8592 | case '>': |
670a50eb ILT |
8593 | printf ("$%d", shamt); |
8594 | continue; | |
3d3c5039 ILT |
8595 | |
8596 | default: | |
670a50eb | 8597 | internalError (); |
3d3c5039 | 8598 | } |
670a50eb | 8599 | break; |
3d3c5039 | 8600 | } |
670a50eb | 8601 | return; |
3d3c5039 ILT |
8602 | } |
8603 | } | |
670a50eb | 8604 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8605 | } |
8606 | #endif | |
8607 | ||
8608 | static symbolS * | |
8609 | get_symbol () | |
8610 | { | |
670a50eb ILT |
8611 | int c; |
8612 | char *name; | |
8613 | symbolS *p; | |
8614 | ||
8615 | name = input_line_pointer; | |
8616 | c = get_symbol_end (); | |
8617 | p = (symbolS *) symbol_find_or_make (name); | |
8618 | *input_line_pointer = c; | |
8619 | return p; | |
3d3c5039 ILT |
8620 | } |
8621 | ||
becfe05e ILT |
8622 | /* Align the current frag to a given power of two. The MIPS assembler |
8623 | also automatically adjusts any preceding label. */ | |
8624 | ||
8625 | static void | |
23dc1ae3 | 8626 | mips_align (to, fill, label) |
becfe05e ILT |
8627 | int to; |
8628 | int fill; | |
23dc1ae3 | 8629 | symbolS *label; |
becfe05e | 8630 | { |
fbcfacb7 | 8631 | mips_emit_delays (false); |
becfe05e ILT |
8632 | frag_align (to, fill); |
8633 | record_alignment (now_seg, to); | |
23dc1ae3 | 8634 | if (label != NULL) |
becfe05e | 8635 | { |
23dc1ae3 ILT |
8636 | assert (S_GET_SEGMENT (label) == now_seg); |
8637 | label->sy_frag = frag_now; | |
8638 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8639 | } |
8640 | } | |
8641 | ||
8642 | /* Align to a given power of two. .align 0 turns off the automatic | |
8643 | alignment used by the data creating pseudo-ops. */ | |
8644 | ||
3d3c5039 ILT |
8645 | static void |
8646 | s_align (x) | |
8647 | int x; | |
8648 | { | |
670a50eb ILT |
8649 | register int temp; |
8650 | register long temp_fill; | |
8651 | long max_alignment = 15; | |
3d3c5039 | 8652 | |
670a50eb | 8653 | /* |
3d3c5039 ILT |
8654 | |
8655 | o Note that the assembler pulls down any immediately preceeding label | |
8656 | to the aligned address. | |
8657 | o It's not documented but auto alignment is reinstated by | |
8658 | a .align pseudo instruction. | |
8659 | o Note also that after auto alignment is turned off the mips assembler | |
8660 | issues an error on attempt to assemble an improperly aligned data item. | |
8661 | We don't. | |
8662 | ||
8663 | */ | |
8664 | ||
670a50eb ILT |
8665 | temp = get_absolute_expression (); |
8666 | if (temp > max_alignment) | |
8667 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8668 | else if (temp < 0) | |
8669 | { | |
8670 | as_warn ("Alignment negative: 0 assumed."); | |
8671 | temp = 0; | |
8672 | } | |
8673 | if (*input_line_pointer == ',') | |
8674 | { | |
8675 | input_line_pointer++; | |
8676 | temp_fill = get_absolute_expression (); | |
8677 | } | |
8678 | else | |
8679 | temp_fill = 0; | |
8680 | if (temp) | |
8681 | { | |
8682 | auto_align = 1; | |
fbcfacb7 ILT |
8683 | mips_align (temp, (int) temp_fill, |
8684 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8685 | } |
670a50eb ILT |
8686 | else |
8687 | { | |
8688 | auto_align = 0; | |
3d3c5039 ILT |
8689 | } |
8690 | ||
670a50eb | 8691 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8692 | } |
8693 | ||
739708fa KR |
8694 | void |
8695 | mips_flush_pending_output () | |
becfe05e | 8696 | { |
fbcfacb7 ILT |
8697 | mips_emit_delays (false); |
8698 | mips_clear_insn_labels (); | |
becfe05e ILT |
8699 | } |
8700 | ||
3d3c5039 ILT |
8701 | static void |
8702 | s_change_sec (sec) | |
8703 | int sec; | |
8704 | { | |
88225433 | 8705 | segT seg; |
becfe05e | 8706 | |
5b63f465 ILT |
8707 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8708 | .sdata and .sbss sections. We change the .data and .rdata | |
8709 | pseudo-ops to use .sdata. */ | |
8710 | if (mips_pic == EMBEDDED_PIC | |
8711 | && (sec == 'd' || sec == 'r')) | |
8712 | sec = 's'; | |
8713 | ||
fbcfacb7 | 8714 | mips_emit_delays (false); |
670a50eb ILT |
8715 | switch (sec) |
8716 | { | |
3d3c5039 | 8717 | case 't': |
604633ae | 8718 | s_text (0); |
670a50eb | 8719 | break; |
3d3c5039 | 8720 | case 'd': |
604633ae | 8721 | s_data (0); |
670a50eb | 8722 | break; |
3d3c5039 | 8723 | case 'b': |
670a50eb | 8724 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8725 | demand_empty_rest_of_line (); |
8726 | break; | |
88225433 ILT |
8727 | |
8728 | case 'r': | |
1dc1e798 KR |
8729 | if (USE_GLOBAL_POINTER_OPT) |
8730 | { | |
8731 | seg = subseg_new (RDATA_SECTION_NAME, | |
8732 | (subsegT) get_absolute_expression ()); | |
8733 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8734 | { | |
8735 | bfd_set_section_flags (stdoutput, seg, | |
8736 | (SEC_ALLOC | |
8737 | | SEC_LOAD | |
8738 | | SEC_READONLY | |
8739 | | SEC_RELOC | |
8740 | | SEC_DATA)); | |
08e17202 ILT |
8741 | if (strcmp (TARGET_OS, "elf") != 0) |
8742 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8743 | } |
8744 | demand_empty_rest_of_line (); | |
8745 | } | |
8746 | else | |
8747 | { | |
8748 | as_bad ("No read only data section in this object file format"); | |
8749 | demand_empty_rest_of_line (); | |
8750 | return; | |
8751 | } | |
88225433 | 8752 | break; |
88225433 ILT |
8753 | |
8754 | case 's': | |
1dc1e798 KR |
8755 | if (USE_GLOBAL_POINTER_OPT) |
8756 | { | |
8757 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8758 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8759 | { | |
8760 | bfd_set_section_flags (stdoutput, seg, | |
8761 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8762 | | SEC_DATA); | |
08e17202 ILT |
8763 | if (strcmp (TARGET_OS, "elf") != 0) |
8764 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8765 | } |
8766 | demand_empty_rest_of_line (); | |
8767 | break; | |
8768 | } | |
8769 | else | |
8770 | { | |
8771 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8772 | demand_empty_rest_of_line (); | |
8773 | return; | |
8774 | } | |
3d3c5039 | 8775 | } |
88225433 | 8776 | |
670a50eb | 8777 | auto_align = 1; |
3d3c5039 ILT |
8778 | } |
8779 | ||
739708fa KR |
8780 | void |
8781 | mips_enable_auto_align () | |
9da4c5d1 | 8782 | { |
9da4c5d1 ILT |
8783 | auto_align = 1; |
8784 | } | |
8785 | ||
3d3c5039 ILT |
8786 | static void |
8787 | s_cons (log_size) | |
8788 | int log_size; | |
8789 | { | |
23dc1ae3 ILT |
8790 | symbolS *label; |
8791 | ||
fbcfacb7 ILT |
8792 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8793 | mips_emit_delays (false); | |
670a50eb | 8794 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8795 | mips_align (log_size, 0, label); |
fbcfacb7 | 8796 | mips_clear_insn_labels (); |
670a50eb | 8797 | cons (1 << log_size); |
3d3c5039 ILT |
8798 | } |
8799 | ||
3d3c5039 | 8800 | static void |
becfe05e ILT |
8801 | s_float_cons (type) |
8802 | int type; | |
3d3c5039 | 8803 | { |
23dc1ae3 ILT |
8804 | symbolS *label; |
8805 | ||
fbcfacb7 | 8806 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8807 | |
fbcfacb7 | 8808 | mips_emit_delays (false); |
670a50eb ILT |
8809 | |
8810 | if (auto_align) | |
becfe05e | 8811 | if (type == 'd') |
23dc1ae3 | 8812 | mips_align (3, 0, label); |
670a50eb | 8813 | else |
23dc1ae3 | 8814 | mips_align (2, 0, label); |
670a50eb | 8815 | |
fbcfacb7 | 8816 | mips_clear_insn_labels (); |
1849d646 | 8817 | |
becfe05e | 8818 | float_cons (type); |
3d3c5039 ILT |
8819 | } |
8820 | ||
c1444ec4 ILT |
8821 | /* Handle .globl. We need to override it because on Irix 5 you are |
8822 | permitted to say | |
8823 | .globl foo .text | |
8824 | where foo is an undefined symbol, to mean that foo should be | |
8825 | considered to be the address of a function. */ | |
8826 | ||
8827 | static void | |
8828 | s_mips_globl (x) | |
8829 | int x; | |
8830 | { | |
8831 | char *name; | |
8832 | int c; | |
8833 | symbolS *symbolP; | |
fb251650 | 8834 | flagword flag; |
c1444ec4 ILT |
8835 | |
8836 | name = input_line_pointer; | |
8837 | c = get_symbol_end (); | |
8838 | symbolP = symbol_find_or_make (name); | |
8839 | *input_line_pointer = c; | |
8840 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8841 | |
8842 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8843 | being a function is apparently labelled as being an object. */ | |
8844 | flag = BSF_OBJECT; | |
8845 | ||
c1444ec4 ILT |
8846 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8847 | { | |
8848 | char *secname; | |
8849 | asection *sec; | |
8850 | ||
8851 | secname = input_line_pointer; | |
8852 | c = get_symbol_end (); | |
8853 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8854 | if (sec == NULL) | |
8855 | as_bad ("%s: no such section", secname); | |
8856 | *input_line_pointer = c; | |
8857 | ||
8858 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8859 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8860 | } |
8861 | ||
fb251650 ILT |
8862 | symbolP->bsym->flags |= flag; |
8863 | ||
c1444ec4 ILT |
8864 | S_SET_EXTERNAL (symbolP); |
8865 | demand_empty_rest_of_line (); | |
8866 | } | |
8867 | ||
3d3c5039 ILT |
8868 | static void |
8869 | s_option (x) | |
8870 | int x; | |
8871 | { | |
dd3f1f76 ILT |
8872 | char *opt; |
8873 | char c; | |
8874 | ||
8875 | opt = input_line_pointer; | |
8876 | c = get_symbol_end (); | |
8877 | ||
dd3f1f76 | 8878 | if (*opt == 'O') |
9226253a ILT |
8879 | { |
8880 | /* FIXME: What does this mean? */ | |
8881 | } | |
dd3f1f76 | 8882 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8883 | { |
d9aba805 | 8884 | int i; |
42562568 | 8885 | |
d9aba805 ILT |
8886 | i = atoi (opt + 3); |
8887 | if (i == 0) | |
8888 | mips_pic = NO_PIC; | |
8889 | else if (i == 2) | |
8890 | mips_pic = SVR4_PIC; | |
8891 | else | |
8892 | as_bad (".option pic%d not supported", i); | |
8893 | ||
1dc1e798 | 8894 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8895 | { |
8896 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8897 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8898 | g_switch_value = 0; |
8899 | bfd_set_gp_size (stdoutput, 0); | |
8900 | } | |
9226253a | 8901 | } |
dd3f1f76 ILT |
8902 | else |
8903 | as_warn ("Unrecognized option \"%s\"", opt); | |
8904 | ||
8905 | *input_line_pointer = c; | |
670a50eb | 8906 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8907 | } |
8908 | ||
8909 | static void | |
8910 | s_mipsset (x) | |
8911 | int x; | |
8912 | { | |
670a50eb ILT |
8913 | char *name = input_line_pointer, ch; |
8914 | ||
8915 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8916 | input_line_pointer++; | |
8917 | ch = *input_line_pointer; | |
8918 | *input_line_pointer = '\0'; | |
8919 | ||
8920 | if (strcmp (name, "reorder") == 0) | |
8921 | { | |
4e95866e ILT |
8922 | if (mips_noreorder) |
8923 | { | |
8924 | prev_insn_unreordered = 1; | |
8925 | prev_prev_insn_unreordered = 1; | |
8926 | } | |
670a50eb ILT |
8927 | mips_noreorder = 0; |
8928 | } | |
8929 | else if (strcmp (name, "noreorder") == 0) | |
8930 | { | |
fbcfacb7 | 8931 | mips_emit_delays (true); |
670a50eb | 8932 | mips_noreorder = 1; |
0dd2d296 | 8933 | mips_any_noreorder = 1; |
670a50eb ILT |
8934 | } |
8935 | else if (strcmp (name, "at") == 0) | |
8936 | { | |
8937 | mips_noat = 0; | |
8938 | } | |
8939 | else if (strcmp (name, "noat") == 0) | |
8940 | { | |
8941 | mips_noat = 1; | |
3d3c5039 | 8942 | } |
670a50eb ILT |
8943 | else if (strcmp (name, "macro") == 0) |
8944 | { | |
8945 | mips_warn_about_macros = 0; | |
8946 | } | |
8947 | else if (strcmp (name, "nomacro") == 0) | |
8948 | { | |
8949 | if (mips_noreorder == 0) | |
8950 | as_bad ("`noreorder' must be set before `nomacro'"); | |
8951 | mips_warn_about_macros = 1; | |
8952 | } | |
8953 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
8954 | { | |
8955 | mips_nomove = 0; | |
8956 | } | |
8957 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
8958 | { | |
8959 | mips_nomove = 1; | |
8960 | } | |
8961 | else if (strcmp (name, "bopt") == 0) | |
8962 | { | |
8963 | mips_nobopt = 0; | |
8964 | } | |
8965 | else if (strcmp (name, "nobopt") == 0) | |
8966 | { | |
8967 | mips_nobopt = 1; | |
8968 | } | |
943321c0 ILT |
8969 | else if (strcmp (name, "mips16") == 0 |
8970 | || strcmp (name, "MIPS-16") == 0) | |
8971 | mips16 = 1; | |
8972 | else if (strcmp (name, "nomips16") == 0 | |
8973 | || strcmp (name, "noMIPS-16") == 0) | |
8974 | mips16 = 0; | |
1051c97f ILT |
8975 | else if (strncmp (name, "mips", 4) == 0) |
8976 | { | |
8977 | int isa; | |
8978 | ||
8979 | /* Permit the user to change the ISA on the fly. Needless to | |
8980 | say, misuse can cause serious problems. */ | |
8981 | isa = atoi (name + 4); | |
8982 | if (isa == 0) | |
8983 | mips_isa = file_mips_isa; | |
d8a1c247 | 8984 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
8985 | as_bad ("unknown ISA level"); |
8986 | else | |
8987 | mips_isa = isa; | |
8988 | } | |
cc5703cd ILT |
8989 | else if (strcmp (name, "autoextend") == 0) |
8990 | mips16_autoextend = 1; | |
8991 | else if (strcmp (name, "noautoextend") == 0) | |
8992 | mips16_autoextend = 0; | |
670a50eb ILT |
8993 | else |
8994 | { | |
8995 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
8996 | } | |
8997 | *input_line_pointer = ch; | |
8998 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
8999 | } |
9000 | ||
9226253a ILT |
9001 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9002 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9003 | ||
9004 | static void | |
9005 | s_abicalls (ignore) | |
9006 | int ignore; | |
9007 | { | |
d9aba805 | 9008 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9009 | if (USE_GLOBAL_POINTER_OPT) |
9010 | { | |
9011 | if (g_switch_seen && g_switch_value != 0) | |
9012 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9013 | g_switch_value = 0; | |
9014 | } | |
d9aba805 | 9015 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9016 | demand_empty_rest_of_line (); |
9017 | } | |
9018 | ||
9019 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9020 | PIC code. It sets the $gp register for the function based on the | |
9021 | function address, which is in the register named in the argument. | |
9022 | This uses a relocation against _gp_disp, which is handled specially | |
9023 | by the linker. The result is: | |
9024 | lui $gp,%hi(_gp_disp) | |
9025 | addiu $gp,$gp,%lo(_gp_disp) | |
9026 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9027 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9028 | |
9029 | static void | |
9030 | s_cpload (ignore) | |
9031 | int ignore; | |
9032 | { | |
9033 | expressionS ex; | |
9034 | int icnt = 0; | |
9035 | ||
d9aba805 ILT |
9036 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9037 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9038 | { |
9039 | s_ignore (0); | |
9040 | return; | |
9041 | } | |
9042 | ||
9043 | /* .cpload should be a in .set noreorder section. */ | |
9044 | if (mips_noreorder == 0) | |
9045 | as_warn (".cpload not in noreorder section"); | |
9046 | ||
9226253a ILT |
9047 | ex.X_op = O_symbol; |
9048 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9049 | ex.X_op_symbol = NULL; | |
9050 | ex.X_add_number = 0; | |
9051 | ||
fb251650 ILT |
9052 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9053 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9054 | ||
0dd2d296 ILT |
9055 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9056 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9057 | (int) BFD_RELOC_LO16); |
9058 | ||
0dd2d296 ILT |
9059 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9060 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9061 | |
9062 | demand_empty_rest_of_line (); | |
9063 | } | |
9064 | ||
9065 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9066 | offset from $sp. The offset is remembered, and after making a PIC | |
9067 | call $gp is restored from that location. */ | |
9068 | ||
9069 | static void | |
9070 | s_cprestore (ignore) | |
9071 | int ignore; | |
9072 | { | |
9073 | expressionS ex; | |
9074 | int icnt = 0; | |
9075 | ||
d9aba805 ILT |
9076 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9077 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9078 | { |
9079 | s_ignore (0); | |
9080 | return; | |
9081 | } | |
9082 | ||
9226253a ILT |
9083 | mips_cprestore_offset = get_absolute_expression (); |
9084 | ||
9085 | ex.X_op = O_constant; | |
9086 | ex.X_add_symbol = NULL; | |
9087 | ex.X_op_symbol = NULL; | |
9088 | ex.X_add_number = mips_cprestore_offset; | |
9089 | ||
0dd2d296 | 9090 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9091 | mips_isa < 3 ? "sw" : "sd", |
9092 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9093 | ||
9094 | demand_empty_rest_of_line (); | |
9095 | } | |
9096 | ||
0dd2d296 ILT |
9097 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9098 | code. It generates a 32 bit GP relative reloc. */ | |
9099 | ||
9100 | static void | |
9101 | s_gpword (ignore) | |
9102 | int ignore; | |
9103 | { | |
23dc1ae3 | 9104 | symbolS *label; |
0dd2d296 ILT |
9105 | expressionS ex; |
9106 | char *p; | |
9107 | ||
9108 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9109 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9110 | { |
9111 | s_cons (2); | |
9112 | return; | |
9113 | } | |
9114 | ||
fbcfacb7 ILT |
9115 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9116 | mips_emit_delays (true); | |
0dd2d296 | 9117 | if (auto_align) |
23dc1ae3 | 9118 | mips_align (2, 0, label); |
fbcfacb7 | 9119 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9120 | |
9121 | expression (&ex); | |
9122 | ||
9123 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9124 | { | |
9125 | as_bad ("Unsupported use of .gpword"); | |
9126 | ignore_rest_of_line (); | |
9127 | } | |
9128 | ||
9129 | p = frag_more (4); | |
9130 | md_number_to_chars (p, (valueT) 0, 4); | |
9131 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9132 | BFD_RELOC_MIPS_GPREL32); | |
9133 | ||
9134 | demand_empty_rest_of_line (); | |
9135 | } | |
9136 | ||
9137 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9138 | tables in SVR4 PIC code. */ | |
9139 | ||
9140 | static void | |
9141 | s_cpadd (ignore) | |
9142 | int ignore; | |
9143 | { | |
9144 | int icnt = 0; | |
9145 | int reg; | |
9146 | ||
9147 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9148 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9149 | { |
9150 | s_ignore (0); | |
9151 | return; | |
9152 | } | |
9153 | ||
9154 | /* Add $gp to the register named as an argument. */ | |
9155 | reg = tc_get_register (0); | |
9156 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9157 | mips_isa < 3 ? "addu" : "daddu", | |
9158 | "d,v,t", reg, reg, GP); | |
9159 | ||
9160 | demand_empty_rest_of_line (); | |
9161 | } | |
9162 | ||
9226253a | 9163 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9164 | to parse .frame. The argument is non-zero if this is the frame |
9165 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9166 | |
3d3c5039 | 9167 | int |
0dd2d296 ILT |
9168 | tc_get_register (frame) |
9169 | int frame; | |
3d3c5039 ILT |
9170 | { |
9171 | int reg; | |
9172 | ||
9173 | SKIP_WHITESPACE (); | |
9174 | if (*input_line_pointer++ != '$') | |
9175 | { | |
9176 | as_warn ("expected `$'"); | |
0dd2d296 | 9177 | reg = 0; |
3d3c5039 | 9178 | } |
0dd2d296 | 9179 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9180 | { |
9181 | reg = get_absolute_expression (); | |
9182 | if (reg < 0 || reg >= 32) | |
9183 | { | |
9184 | as_warn ("Bad register number"); | |
9185 | reg = 0; | |
9186 | } | |
9187 | } | |
9188 | else | |
9189 | { | |
9190 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9191 | reg = FP; |
3d3c5039 | 9192 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9193 | reg = SP; |
3d3c5039 | 9194 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9195 | reg = GP; |
3d3c5039 | 9196 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9197 | reg = AT; |
3d3c5039 ILT |
9198 | else |
9199 | { | |
9200 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9201 | reg = 0; |
3d3c5039 ILT |
9202 | } |
9203 | input_line_pointer += 2; | |
9204 | } | |
0dd2d296 ILT |
9205 | if (frame) |
9206 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9207 | return reg; |
9208 | } | |
9209 | ||
0dd2d296 ILT |
9210 | valueT |
9211 | md_section_align (seg, addr) | |
9212 | asection *seg; | |
9213 | valueT addr; | |
9214 | { | |
9215 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9216 | ||
cf32394d ILT |
9217 | #ifdef OBJ_ELF |
9218 | /* We don't need to align ELF sections to the full alignment. | |
9219 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9220 | byte boundary. We don't bother to align the sections if we are |
9221 | targeted for an embedded system. */ | |
9222 | if (strcmp (TARGET_OS, "elf") == 0) | |
9223 | return addr; | |
943321c0 ILT |
9224 | if (align > 4) |
9225 | align = 4; | |
10a14e36 | 9226 | #endif |
cf32394d ILT |
9227 | |
9228 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9229 | } |
9230 | ||
d8a1c247 KR |
9231 | /* Utility routine, called from above as well. If called while the |
9232 | input file is still being read, it's only an approximation. (For | |
9233 | example, a symbol may later become defined which appeared to be | |
9234 | undefined earlier.) */ | |
22ba90ce ILT |
9235 | |
9236 | static int | |
9237 | nopic_need_relax (sym) | |
d8a1c247 KR |
9238 | symbolS *sym; |
9239 | { | |
9240 | if (sym == 0) | |
9241 | return 0; | |
9242 | ||
1dc1e798 KR |
9243 | if (USE_GLOBAL_POINTER_OPT) |
9244 | { | |
9245 | const char *symname; | |
9246 | int change; | |
9247 | ||
9248 | /* Find out whether this symbol can be referenced off the GP | |
9249 | register. It can be if it is smaller than the -G size or if | |
9250 | it is in the .sdata or .sbss section. Certain symbols can | |
9251 | not be referenced off the GP, although it appears as though | |
9252 | they can. */ | |
9253 | symname = S_GET_NAME (sym); | |
9254 | if (symname != (const char *) NULL | |
9255 | && (strcmp (symname, "eprol") == 0 | |
9256 | || strcmp (symname, "etext") == 0 | |
9257 | || strcmp (symname, "_gp") == 0 | |
9258 | || strcmp (symname, "edata") == 0 | |
9259 | || strcmp (symname, "_fbss") == 0 | |
9260 | || strcmp (symname, "_fdata") == 0 | |
9261 | || strcmp (symname, "_ftext") == 0 | |
9262 | || strcmp (symname, "end") == 0 | |
9263 | || strcmp (symname, "_gp_disp") == 0)) | |
9264 | change = 1; | |
9265 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9266 | && (0 |
9267 | #ifndef NO_ECOFF_DEBUGGING | |
9268 | || (sym->ecoff_extern_size != 0 | |
9269 | && sym->ecoff_extern_size <= g_switch_value) | |
9270 | #endif | |
1dc1e798 KR |
9271 | || (S_GET_VALUE (sym) != 0 |
9272 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9273 | change = 0; | |
9274 | else | |
9275 | { | |
9276 | const char *segname; | |
d8a1c247 | 9277 | |
1dc1e798 KR |
9278 | segname = segment_name (S_GET_SEGMENT (sym)); |
9279 | assert (strcmp (segname, ".lit8") != 0 | |
9280 | && strcmp (segname, ".lit4") != 0); | |
9281 | change = (strcmp (segname, ".sdata") != 0 | |
9282 | && strcmp (segname, ".sbss") != 0); | |
9283 | } | |
9284 | return change; | |
9285 | } | |
9286 | else | |
9287 | /* We are not optimizing for the GP register. */ | |
9288 | return 1; | |
d8a1c247 KR |
9289 | } |
9290 | ||
cc5703cd ILT |
9291 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9292 | extended opcode. SEC is the section the frag is in. */ | |
9293 | ||
9294 | static int | |
9295 | mips16_extended_frag (fragp, sec, stretch) | |
9296 | fragS *fragp; | |
9297 | asection *sec; | |
9298 | long stretch; | |
9299 | { | |
9300 | int type; | |
9301 | register const struct mips16_immed_operand *op; | |
9302 | offsetT val; | |
9303 | int mintiny, maxtiny; | |
f74ba7a3 | 9304 | segT symsec; |
cc5703cd | 9305 | |
8728fa92 ILT |
9306 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9307 | return 0; | |
9308 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9309 | return 1; | |
9310 | ||
cc5703cd ILT |
9311 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9312 | op = mips16_immed_operands; | |
9313 | while (op->type != type) | |
9314 | { | |
9315 | ++op; | |
9316 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9317 | } | |
9318 | ||
9319 | if (op->unsp) | |
9320 | { | |
9321 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9322 | { | |
9323 | mintiny = 1; | |
9324 | maxtiny = 1 << op->nbits; | |
9325 | } | |
9326 | else | |
9327 | { | |
9328 | mintiny = 0; | |
9329 | maxtiny = (1 << op->nbits) - 1; | |
9330 | } | |
9331 | } | |
9332 | else | |
9333 | { | |
9334 | mintiny = - (1 << (op->nbits - 1)); | |
9335 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9336 | } | |
9337 | ||
f74ba7a3 ILT |
9338 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9339 | a particular frag address. */ | |
9340 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9341 | { | |
9342 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9343 | + fragp->fr_symbol->sy_frag->fr_address); | |
9344 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9345 | } | |
9346 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9347 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9348 | == O_constant)) | |
9349 | { | |
9350 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9351 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9352 | + fragp->fr_symbol->sy_value.X_add_number | |
9353 | + fragp->fr_symbol->sy_frag->fr_address); | |
9354 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9355 | } | |
9356 | else | |
9357 | return 1; | |
cc5703cd ILT |
9358 | |
9359 | if (op->pcrel) | |
9360 | { | |
9361 | addressT addr; | |
9362 | ||
9363 | /* We won't have the section when we are called from | |
9364 | mips_relax_frag. However, we will always have been called | |
9365 | from md_estimate_size_before_relax first. If this is a | |
9366 | branch to a different section, we mark it as such. If SEC is | |
9367 | NULL, and the frag is not marked, then it must be a branch to | |
9368 | the same section. */ | |
9369 | if (sec == NULL) | |
9370 | { | |
9371 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9372 | return 1; | |
9373 | } | |
9374 | else | |
9375 | { | |
f74ba7a3 | 9376 | if (symsec != sec) |
cc5703cd ILT |
9377 | { |
9378 | fragp->fr_subtype = | |
9379 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9380 | ||
9381 | /* FIXME: We should support this, and let the linker | |
9382 | catch branches and loads that are out of range. */ | |
9383 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9384 | "unsupported PC relative reference to different section"); | |
9385 | ||
9386 | return 1; | |
9387 | } | |
9388 | } | |
9389 | ||
9390 | /* In this case, we know for sure that the symbol fragment is in | |
9391 | the same section. If the fr_address of the symbol fragment | |
9392 | is greater then the address of this fragment we want to add | |
9393 | in STRETCH in order to get a better estimate of the address. | |
9394 | This particularly matters because of the shift bits. */ | |
9395 | if (stretch != 0 | |
9396 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9397 | { | |
9398 | fragS *f; | |
9399 | ||
9400 | /* Adjust stretch for any alignment frag. */ | |
9401 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9402 | { | |
9403 | assert (f != NULL); | |
9404 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9405 | { | |
9406 | if (stretch < 0) | |
9407 | stretch = - ((- stretch) | |
9408 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9409 | else | |
9410 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9411 | if (stretch == 0) | |
9412 | break; | |
9413 | } | |
9414 | } | |
9415 | val += stretch; | |
9416 | } | |
9417 | ||
a677feeb ILT |
9418 | addr = fragp->fr_address + fragp->fr_fix; |
9419 | ||
9420 | /* The base address rules are complicated. The base address of | |
9421 | a branch is the following instruction. The base address of a | |
9422 | PC relative load or add is the instruction itself, but if it | |
9423 | is extended add 2, and if it is in a delay slot (in which | |
9424 | case it can not be extended) use the address of the | |
9425 | instruction whose delay slot it is in. */ | |
9426 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9427 | { |
9428 | addr += 2; | |
9429 | /* Ignore the low bit in the target, since it will be set | |
9430 | for a text label. */ | |
9431 | if ((val & 1) != 0) | |
9432 | --val; | |
9433 | } | |
a677feeb ILT |
9434 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9435 | addr -= 4; | |
9436 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9437 | addr -= 2; | |
cc5703cd ILT |
9438 | |
9439 | /* If we are currently assuming that this frag should be | |
9440 | extended, then the current address is two bytes higher. */ | |
9441 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9442 | addr += 2; | |
9443 | ||
9444 | val -= addr & ~ ((1 << op->shift) - 1); | |
9445 | ||
9446 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9447 | if (type == 'p' || type == 'q') | |
9448 | val /= 2; | |
9449 | ||
9450 | /* If any of the shifted bits are set, we must use an extended | |
9451 | opcode. If the address depends on the size of this | |
9452 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9453 | use an extended opcode. We only check this when we are in |
9454 | the main relaxation loop, when SEC is NULL. */ | |
9455 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9456 | { | |
9457 | fragp->fr_subtype = | |
9458 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9459 | return 1; | |
9460 | } | |
9461 | ||
9462 | /* If we are about to mark a frag as extended because the value | |
9463 | is precisely maxtiny + 1, then there is a chance of an | |
9464 | infinite loop as in the following code: | |
9465 | la $4,foo | |
9466 | .skip 1020 | |
9467 | .align 2 | |
9468 | foo: | |
9469 | In this case when the la is extended, foo is 0x3fc bytes | |
9470 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9471 | the la must be extended. To avoid this loop, we mark the | |
9472 | frag as extended if it was small, and is about to become | |
9473 | extended with a value of maxtiny + 1. */ | |
9474 | if (val == ((maxtiny + 1) << op->shift) | |
9475 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9476 | && sec == NULL) | |
cc5703cd ILT |
9477 | { |
9478 | fragp->fr_subtype = | |
9479 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9480 | return 1; | |
9481 | } | |
9482 | } | |
41a0ed22 ILT |
9483 | else if (symsec != absolute_section && sec != NULL) |
9484 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9485 | |
9486 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9487 | || val < (mintiny << op->shift) | |
9488 | || val > (maxtiny << op->shift)) | |
9489 | return 1; | |
9490 | else | |
9491 | return 0; | |
9492 | } | |
9493 | ||
9494 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9495 | mips16, we are not really relaxing here, and the final size is | |
9496 | encoded in the subtype information. For the mips16, we have to | |
9497 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9498 | |
0dd2d296 ILT |
9499 | /*ARGSUSED*/ |
9500 | int | |
9501 | md_estimate_size_before_relax (fragp, segtype) | |
9502 | fragS *fragp; | |
9503 | asection *segtype; | |
9504 | { | |
9505 | int change; | |
9506 | ||
cc5703cd ILT |
9507 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9508 | { | |
9509 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9510 | { | |
9511 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9512 | return 4; | |
9513 | } | |
9514 | else | |
9515 | { | |
9516 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9517 | return 2; | |
9518 | } | |
9519 | } | |
9520 | ||
d9aba805 | 9521 | if (mips_pic == NO_PIC) |
0dd2d296 | 9522 | { |
d8a1c247 | 9523 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9524 | } |
d9aba805 | 9525 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9526 | { |
9527 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9528 | ||
9529 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9530 | change = (symsec != &bfd_und_section | |
9531 | && symsec != &bfd_abs_section | |
9532 | && ! bfd_is_com_section (symsec)); | |
9533 | } | |
d9aba805 ILT |
9534 | else |
9535 | abort (); | |
0dd2d296 ILT |
9536 | |
9537 | if (change) | |
9538 | { | |
9539 | /* Record the offset to the first reloc in the fr_opcode field. | |
9540 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9541 | must be expanded. */ | |
9542 | fragp->fr_opcode = (fragp->fr_literal | |
9543 | + fragp->fr_fix | |
9544 | - RELAX_OLD (fragp->fr_subtype) | |
9545 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9546 | /* FIXME: This really needs as_warn_where. */ | |
9547 | if (RELAX_WARN (fragp->fr_subtype)) | |
9548 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9549 | } | |
9550 | ||
9551 | if (! change) | |
9552 | return 0; | |
9553 | else | |
9554 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9555 | } | |
9556 | ||
0d7f9025 ILT |
9557 | /* This is called to see whether a reloc against a defined symbol |
9558 | should be converted into a reloc against a section. Don't adjust | |
9559 | MIPS16 jump relocations, so we don't have to worry about the format | |
9560 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
9561 | mips16 symbols, so that the linker can find them if it needs to set |
9562 | up a stub. */ | |
0d7f9025 ILT |
9563 | |
9564 | int | |
9565 | mips_fix_adjustable (fixp) | |
9566 | fixS *fixp; | |
9567 | { | |
9568 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
9569 | return 0; | |
9570 | if (fixp->fx_addsy == NULL) | |
9571 | return 1; | |
0d7f9025 ILT |
9572 | #ifdef S_GET_OTHER |
9573 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9574 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16) | |
9575 | return 0; | |
9576 | #endif | |
9577 | return 1; | |
9578 | } | |
9579 | ||
0dd2d296 ILT |
9580 | /* Translate internal representation of relocation info to BFD target |
9581 | format. */ | |
9582 | ||
9583 | arelent ** | |
3d3c5039 ILT |
9584 | tc_gen_reloc (section, fixp) |
9585 | asection *section; | |
9586 | fixS *fixp; | |
9587 | { | |
0dd2d296 | 9588 | static arelent *retval[4]; |
3d3c5039 | 9589 | arelent *reloc; |
a8aed9dd | 9590 | bfd_reloc_code_real_type code; |
3d3c5039 | 9591 | |
0dd2d296 ILT |
9592 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9593 | retval[1] = NULL; | |
3d3c5039 ILT |
9594 | |
9595 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9596 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9597 | |
9598 | if (mips_pic == EMBEDDED_PIC | |
9599 | && SWITCH_TABLE (fixp)) | |
9600 | { | |
9601 | /* For a switch table entry we use a special reloc. The addend | |
9602 | is actually the difference between the reloc address and the | |
9603 | subtrahend. */ | |
9604 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9605 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9606 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9607 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9608 | } | |
ecd4ca1c ILT |
9609 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9610 | { | |
9611 | /* We use a special addend for an internal RELLO reloc. */ | |
9612 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9613 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9614 | else | |
9615 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9616 | } | |
9617 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9618 | { | |
9619 | assert (fixp->fx_next != NULL | |
9620 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9621 | /* We use a special addend for an internal RELHI reloc. The | |
9622 | reloc is relative to the RELLO; adjust the addend | |
9623 | accordingly. */ | |
9624 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9625 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9626 | + fixp->fx_next->fx_where | |
9627 | - S_GET_VALUE (fixp->fx_subsy)); | |
9628 | else | |
9629 | reloc->addend = (fixp->fx_addnumber | |
9630 | + fixp->fx_next->fx_frag->fr_address | |
9631 | + fixp->fx_next->fx_where); | |
9632 | } | |
1c803e52 | 9633 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9634 | reloc->addend = fixp->fx_addnumber; |
9635 | else | |
5b63f465 | 9636 | { |
1dc1e798 KR |
9637 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9638 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9639 | handling. */ | |
9640 | reloc->addend = reloc->address; | |
9641 | else | |
9642 | reloc->addend = -reloc->address; | |
5b63f465 | 9643 | } |
0dd2d296 ILT |
9644 | |
9645 | /* If this is a variant frag, we may need to adjust the existing | |
9646 | reloc and generate a new one. */ | |
9647 | if (fixp->fx_frag->fr_opcode != NULL | |
9648 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9649 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9650 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9651 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9652 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9653 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9654 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9655 | { |
9656 | arelent *reloc2; | |
9657 | ||
cc5703cd ILT |
9658 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9659 | ||
0dd2d296 | 9660 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9661 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9662 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9663 | the second one handle all of them. */ | |
0dd2d296 ILT |
9664 | if (fixp->fx_next != NULL |
9665 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9666 | { | |
fb251650 ILT |
9667 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9668 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9669 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9670 | && (fixp->fx_next->fx_r_type | |
9671 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9672 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9673 | && (fixp->fx_next->fx_r_type | |
9674 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9675 | retval[0] = NULL; |
9676 | return retval; | |
9677 | } | |
9678 | ||
9679 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9680 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9681 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9682 | retval[2] = NULL; | |
9683 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9684 | reloc2->address = (reloc->address | |
9685 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9686 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9687 | reloc2->addend = fixp->fx_addnumber; | |
9688 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9689 | assert (reloc2->howto != NULL); | |
9690 | ||
9691 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9692 | { | |
9693 | arelent *reloc3; | |
9694 | ||
9695 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9696 | retval[3] = NULL; | |
9697 | *reloc3 = *reloc2; | |
9698 | reloc3->address += 4; | |
9699 | } | |
9700 | ||
d9aba805 | 9701 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9702 | { |
9703 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9704 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9705 | } | |
d9aba805 | 9706 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9707 | { |
fb251650 | 9708 | switch (fixp->fx_r_type) |
0dd2d296 | 9709 | { |
fb251650 ILT |
9710 | default: |
9711 | abort (); | |
9712 | case BFD_RELOC_MIPS_GOT16: | |
9713 | break; | |
9714 | case BFD_RELOC_MIPS_CALL16: | |
9715 | case BFD_RELOC_MIPS_GOT_LO16: | |
9716 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9717 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9718 | break; |
0dd2d296 ILT |
9719 | } |
9720 | } | |
d9aba805 ILT |
9721 | else |
9722 | abort (); | |
0dd2d296 ILT |
9723 | } |
9724 | ||
a8aed9dd ILT |
9725 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9726 | fixup_segment converted a non-PC relative reloc into a PC | |
9727 | relative reloc. In such a case, we need to convert the reloc | |
9728 | code. */ | |
9729 | code = fixp->fx_r_type; | |
9730 | if (fixp->fx_pcrel) | |
9731 | { | |
9732 | switch (code) | |
9733 | { | |
9734 | case BFD_RELOC_8: | |
9735 | code = BFD_RELOC_8_PCREL; | |
9736 | break; | |
9737 | case BFD_RELOC_16: | |
9738 | code = BFD_RELOC_16_PCREL; | |
9739 | break; | |
9740 | case BFD_RELOC_32: | |
9741 | code = BFD_RELOC_32_PCREL; | |
9742 | break; | |
bf39474f ILT |
9743 | case BFD_RELOC_64: |
9744 | code = BFD_RELOC_64_PCREL; | |
9745 | break; | |
a8aed9dd ILT |
9746 | case BFD_RELOC_8_PCREL: |
9747 | case BFD_RELOC_16_PCREL: | |
9748 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9749 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9750 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9751 | case BFD_RELOC_PCREL_HI16_S: |
9752 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9753 | break; |
9754 | default: | |
9755 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9756 | "Cannot make %s relocation PC relative", | |
9757 | bfd_get_reloc_code_name (code)); | |
9758 | } | |
9759 | } | |
9760 | ||
d9aba805 ILT |
9761 | /* To support a PC relative reloc when generating embedded PIC code |
9762 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9763 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9764 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9765 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9766 | && mips_pic != EMBEDDED_PIC) |
9767 | reloc->howto = NULL; | |
9768 | else | |
a8aed9dd | 9769 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9770 | |
52aa70b5 JW |
9771 | if (reloc->howto == NULL) |
9772 | { | |
9773 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9774 | "Can not represent %s relocation in this object file format", |
9775 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9776 | retval[0] = NULL; |
52aa70b5 | 9777 | } |
3d3c5039 | 9778 | |
0dd2d296 | 9779 | return retval; |
3d3c5039 ILT |
9780 | } |
9781 | ||
cc5703cd ILT |
9782 | /* Relax a machine dependent frag. This returns the amount by which |
9783 | the current size of the frag should change. */ | |
9784 | ||
9785 | int | |
9786 | mips_relax_frag (fragp, stretch) | |
9787 | fragS *fragp; | |
9788 | long stretch; | |
9789 | { | |
9790 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9791 | return 0; | |
9792 | ||
9793 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9794 | { | |
9795 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9796 | return 0; | |
9797 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9798 | return 2; | |
9799 | } | |
9800 | else | |
9801 | { | |
9802 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9803 | return 0; | |
9804 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9805 | return -2; | |
9806 | } | |
9807 | ||
9808 | return 0; | |
9809 | } | |
9810 | ||
0dd2d296 ILT |
9811 | /* Convert a machine dependent frag. */ |
9812 | ||
9813 | void | |
9814 | md_convert_frag (abfd, asec, fragp) | |
9815 | bfd *abfd; | |
9816 | segT asec; | |
9817 | fragS *fragp; | |
3d3c5039 | 9818 | { |
0dd2d296 ILT |
9819 | int old, new; |
9820 | char *fixptr; | |
3d3c5039 | 9821 | |
cc5703cd ILT |
9822 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9823 | { | |
9824 | int type; | |
9825 | register const struct mips16_immed_operand *op; | |
9826 | boolean small, ext; | |
9827 | offsetT val; | |
9828 | bfd_byte *buf; | |
9829 | unsigned long insn; | |
9830 | boolean use_extend; | |
9831 | unsigned short extend; | |
9832 | ||
9833 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9834 | op = mips16_immed_operands; | |
9835 | while (op->type != type) | |
9836 | ++op; | |
9837 | ||
9838 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9839 | { | |
9840 | small = false; | |
9841 | ext = true; | |
9842 | } | |
9843 | else | |
9844 | { | |
9845 | small = true; | |
9846 | ext = false; | |
9847 | } | |
9848 | ||
f74ba7a3 | 9849 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9850 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9851 | if (op->pcrel) |
9852 | { | |
9853 | addressT addr; | |
9854 | ||
a677feeb ILT |
9855 | addr = fragp->fr_address + fragp->fr_fix; |
9856 | ||
9857 | /* The rules for the base address of a PC relative reloc are | |
9858 | complicated; see mips16_extended_frag. */ | |
9859 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9860 | { |
9861 | addr += 2; | |
9862 | /* Ignore the low bit in the target, since it will be | |
9863 | set for a text label. */ | |
9864 | if ((val & 1) != 0) | |
9865 | --val; | |
9866 | } | |
a677feeb ILT |
9867 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9868 | addr -= 4; | |
9869 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9870 | addr -= 2; | |
9871 | ||
cc5703cd ILT |
9872 | if (ext) |
9873 | addr += 2; | |
9874 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9875 | val -= addr; | |
a677feeb ILT |
9876 | |
9877 | /* Make sure the section winds up with the alignment we have | |
9878 | assumed. */ | |
9879 | if (op->shift > 0) | |
9880 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9881 | } |
9882 | ||
9883 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9884 | ||
b9129c6f ILT |
9885 | if (target_big_endian) |
9886 | insn = bfd_getb16 (buf); | |
9887 | else | |
9888 | insn = bfd_getl16 (buf); | |
cc5703cd | 9889 | |
31a2c6ff ILT |
9890 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
9891 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
9892 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9893 | |
9894 | if (use_extend) | |
9895 | { | |
9896 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9897 | fragp->fr_fix += 2; | |
9898 | buf += 2; | |
9899 | } | |
3d3c5039 | 9900 | |
cc5703cd ILT |
9901 | md_number_to_chars (buf, insn, 2); |
9902 | fragp->fr_fix += 2; | |
9903 | buf += 2; | |
9904 | } | |
9905 | else | |
9906 | { | |
9907 | if (fragp->fr_opcode == NULL) | |
9908 | return; | |
0dd2d296 | 9909 | |
cc5703cd ILT |
9910 | old = RELAX_OLD (fragp->fr_subtype); |
9911 | new = RELAX_NEW (fragp->fr_subtype); | |
9912 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9913 | |
cc5703cd ILT |
9914 | if (new > 0) |
9915 | memcpy (fixptr - old, fixptr, new); | |
9916 | ||
9917 | fragp->fr_fix += new - old; | |
9918 | } | |
0dd2d296 | 9919 | } |
becfe05e | 9920 | |
fbcfacb7 ILT |
9921 | #ifdef OBJ_ELF |
9922 | ||
9923 | /* This function is called after the relocs have been generated. | |
9924 | We've been storing mips16 text labels as odd. Here we convert them | |
9925 | back to even for the convenience of the debugger. */ | |
9926 | ||
9927 | void | |
9928 | mips_frob_file_after_relocs () | |
9929 | { | |
9930 | asymbol **syms; | |
9931 | unsigned int count, i; | |
9932 | ||
9933 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9934 | return; | |
9935 | ||
9936 | syms = bfd_get_outsymbols (stdoutput); | |
9937 | count = bfd_get_symcount (stdoutput); | |
9938 | for (i = 0; i < count; i++, syms++) | |
9939 | { | |
9940 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
9941 | && ((*syms)->value & 1) != 0) | |
9942 | { | |
9943 | (*syms)->value &= ~1; | |
9944 | /* If the symbol has an odd size, it was probably computed | |
9945 | incorrectly, so adjust that as well. */ | |
9946 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
9947 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
9948 | } | |
9949 | } | |
9950 | } | |
9951 | ||
9952 | #endif | |
9953 | ||
becfe05e ILT |
9954 | /* This function is called whenever a label is defined. It is used |
9955 | when handling branch delays; if a branch has a label, we assume we | |
9956 | can not move it. */ | |
9957 | ||
9958 | void | |
9959 | mips_define_label (sym) | |
9960 | symbolS *sym; | |
9961 | { | |
fbcfacb7 ILT |
9962 | struct insn_label_list *l; |
9963 | ||
9964 | if (free_insn_labels == NULL) | |
9965 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
9966 | else | |
9967 | { | |
9968 | l = free_insn_labels; | |
9969 | free_insn_labels = l->next; | |
9970 | } | |
9971 | ||
9972 | l->label = sym; | |
9973 | l->next = insn_labels; | |
9974 | insn_labels = l; | |
becfe05e | 9975 | } |
22ba90ce ILT |
9976 | |
9977 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
9978 | In order to work with gcc when using mips-tfile, we must keep all | |
9979 | local labels. However, in other cases, we want to discard them, | |
9980 | since they are useless. */ | |
9981 | ||
9982 | int | |
9983 | mips_local_label (name) | |
9984 | const char *name; | |
9985 | { | |
c625fc23 | 9986 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
9987 | if (ECOFF_DEBUGGING |
9988 | && mips_debug != 0 | |
9989 | && ! ecoff_debugging_seen) | |
9990 | { | |
9991 | /* We were called with -g, but we didn't see any debugging | |
9992 | information. That may mean that gcc is smuggling debugging | |
9993 | information through to mips-tfile, in which case we must | |
9994 | generate all local labels. */ | |
9995 | return 0; | |
9996 | } | |
c625fc23 | 9997 | #endif |
22ba90ce ILT |
9998 | |
9999 | /* Here it's OK to discard local labels. */ | |
10000 | ||
3af584b4 | 10001 | return name[0] == '$'; |
22ba90ce | 10002 | } |
3d3c5039 | 10003 | \f |
739708fa | 10004 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10005 | |
0dd2d296 | 10006 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10007 | |
10008 | void | |
10009 | mips_elf_final_processing () | |
10010 | { | |
87178180 ILT |
10011 | /* Write out the register information. */ |
10012 | if (! mips_64) | |
10013 | { | |
10014 | Elf32_RegInfo s; | |
10015 | ||
10016 | s.ri_gprmask = mips_gprmask; | |
10017 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10018 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10019 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10020 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10021 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10022 | ||
10023 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10024 | ((Elf32_External_RegInfo *) | |
10025 | mips_regmask_frag)); | |
10026 | } | |
10027 | else | |
10028 | { | |
10029 | Elf64_Internal_RegInfo s; | |
10030 | ||
10031 | s.ri_gprmask = mips_gprmask; | |
10032 | s.ri_pad = 0; | |
10033 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10034 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10035 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10036 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10037 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10038 | ||
10039 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10040 | ((Elf64_External_RegInfo *) | |
10041 | mips_regmask_frag)); | |
10042 | } | |
0dd2d296 ILT |
10043 | |
10044 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10045 | sort of BFD interface for this. */ | |
10046 | if (mips_any_noreorder) | |
10047 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10048 | if (mips_pic != NO_PIC) |
0dd2d296 | 10049 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10050 | } |
10051 | ||
739708fa | 10052 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10053 | \f |
3d3c5039 ILT |
10054 | /* These functions should really be defined by the object file format, |
10055 | since they are related to debugging information. However, this | |
10056 | code has to work for the a.out format, which does not define them, | |
10057 | so we provide simple versions here. These don't actually generate | |
10058 | any debugging information, but they do simple checking and someday | |
10059 | somebody may make them useful. */ | |
10060 | ||
670a50eb ILT |
10061 | typedef struct loc |
10062 | { | |
10063 | struct loc *loc_next; | |
10064 | unsigned long loc_fileno; | |
10065 | unsigned long loc_lineno; | |
10066 | unsigned long loc_offset; | |
10067 | unsigned short loc_delta; | |
10068 | unsigned short loc_count; | |
3d3c5039 | 10069 | #if 0 |
670a50eb | 10070 | fragS *loc_frag; |
3d3c5039 | 10071 | #endif |
670a50eb ILT |
10072 | } |
10073 | locS; | |
3d3c5039 | 10074 | |
670a50eb ILT |
10075 | typedef struct proc |
10076 | { | |
3d3c5039 ILT |
10077 | struct proc *proc_next; |
10078 | struct symbol *proc_isym; | |
10079 | struct symbol *proc_end; | |
10080 | unsigned long proc_reg_mask; | |
10081 | unsigned long proc_reg_offset; | |
10082 | unsigned long proc_fpreg_mask; | |
10083 | unsigned long proc_fpreg_offset; | |
10084 | unsigned long proc_frameoffset; | |
10085 | unsigned long proc_framereg; | |
10086 | unsigned long proc_pcreg; | |
10087 | locS *proc_iline; | |
10088 | struct file *proc_file; | |
10089 | int proc_index; | |
670a50eb ILT |
10090 | } |
10091 | procS; | |
3d3c5039 | 10092 | |
670a50eb ILT |
10093 | typedef struct file |
10094 | { | |
3d3c5039 ILT |
10095 | struct file *file_next; |
10096 | unsigned long file_fileno; | |
10097 | struct symbol *file_symbol; | |
10098 | struct symbol *file_end; | |
10099 | struct proc *file_proc; | |
10100 | int file_numprocs; | |
670a50eb ILT |
10101 | } |
10102 | fileS; | |
3d3c5039 ILT |
10103 | |
10104 | static struct obstack proc_frags; | |
10105 | static procS *proc_lastP; | |
10106 | static procS *proc_rootP; | |
10107 | static int numprocs; | |
10108 | ||
10109 | static void | |
10110 | md_obj_begin () | |
10111 | { | |
670a50eb | 10112 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10113 | } |
10114 | ||
10115 | static void | |
10116 | md_obj_end () | |
10117 | { | |
10118 | /* check for premature end, nesting errors, etc */ | |
10119 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10120 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10121 | } |
10122 | ||
3d3c5039 ILT |
10123 | static long |
10124 | get_number () | |
10125 | { | |
670a50eb ILT |
10126 | int negative = 0; |
10127 | long val = 0; | |
3d3c5039 | 10128 | |
670a50eb ILT |
10129 | if (*input_line_pointer == '-') |
10130 | { | |
10131 | ++input_line_pointer; | |
10132 | negative = 1; | |
3d3c5039 | 10133 | } |
670a50eb ILT |
10134 | if (!isdigit (*input_line_pointer)) |
10135 | as_bad ("Expected simple number."); | |
10136 | if (input_line_pointer[0] == '0') | |
10137 | { | |
10138 | if (input_line_pointer[1] == 'x') | |
10139 | { | |
10140 | input_line_pointer += 2; | |
10141 | while (isxdigit (*input_line_pointer)) | |
10142 | { | |
10143 | val <<= 4; | |
3a762a0b | 10144 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10145 | } |
670a50eb ILT |
10146 | return negative ? -val : val; |
10147 | } | |
10148 | else | |
10149 | { | |
10150 | ++input_line_pointer; | |
10151 | while (isdigit (*input_line_pointer)) | |
10152 | { | |
10153 | val <<= 3; | |
10154 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10155 | } |
670a50eb | 10156 | return negative ? -val : val; |
3d3c5039 ILT |
10157 | } |
10158 | } | |
670a50eb ILT |
10159 | if (!isdigit (*input_line_pointer)) |
10160 | { | |
10161 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10162 | *input_line_pointer, *input_line_pointer); | |
10163 | as_warn ("Invalid number"); | |
10164 | return -1; | |
3d3c5039 | 10165 | } |
670a50eb ILT |
10166 | while (isdigit (*input_line_pointer)) |
10167 | { | |
10168 | val *= 10; | |
10169 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10170 | } |
670a50eb | 10171 | return negative ? -val : val; |
3d3c5039 ILT |
10172 | } |
10173 | ||
10174 | /* The .file directive; just like the usual .file directive, but there | |
10175 | is an initial number which is the ECOFF file index. */ | |
10176 | ||
10177 | static void | |
10178 | s_file (x) | |
10179 | int x; | |
10180 | { | |
670a50eb | 10181 | int line; |
3d3c5039 | 10182 | |
670a50eb | 10183 | line = get_number (); |
9a7d824a | 10184 | s_app_file (0); |
3d3c5039 ILT |
10185 | } |
10186 | ||
10187 | ||
10188 | /* The .end directive. */ | |
10189 | ||
10190 | static void | |
10191 | s_mipsend (x) | |
10192 | int x; | |
10193 | { | |
670a50eb ILT |
10194 | symbolS *p; |
10195 | ||
10196 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10197 | { | |
10198 | p = get_symbol (); | |
10199 | demand_empty_rest_of_line (); | |
10200 | } | |
10201 | else | |
10202 | p = NULL; | |
10203 | if (now_seg != text_section) | |
10204 | as_warn (".end not in text section"); | |
10205 | if (!proc_lastP) | |
10206 | { | |
10207 | as_warn (".end and no .ent seen yet."); | |
10208 | return; | |
3d3c5039 ILT |
10209 | } |
10210 | ||
670a50eb ILT |
10211 | if (p != NULL) |
10212 | { | |
10213 | assert (S_GET_NAME (p)); | |
10214 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10215 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10216 | } |
10217 | ||
670a50eb | 10218 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10219 | } |
10220 | ||
10221 | /* The .aent and .ent directives. */ | |
10222 | ||
10223 | static void | |
10224 | s_ent (aent) | |
10225 | int aent; | |
10226 | { | |
670a50eb ILT |
10227 | int number = 0; |
10228 | procS *procP; | |
10229 | symbolS *symbolP; | |
10230 | ||
10231 | symbolP = get_symbol (); | |
10232 | if (*input_line_pointer == ',') | |
10233 | input_line_pointer++; | |
dd3f1f76 | 10234 | SKIP_WHITESPACE (); |
670a50eb ILT |
10235 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10236 | number = get_number (); | |
10237 | if (now_seg != text_section) | |
10238 | as_warn (".ent or .aent not in text section."); | |
10239 | ||
10240 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10241 | as_warn ("missing `.end'"); | |
10242 | ||
10243 | if (!aent) | |
10244 | { | |
10245 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10246 | procP->proc_isym = symbolP; | |
10247 | procP->proc_reg_mask = 0; | |
10248 | procP->proc_reg_offset = 0; | |
10249 | procP->proc_fpreg_mask = 0; | |
10250 | procP->proc_fpreg_offset = 0; | |
10251 | procP->proc_frameoffset = 0; | |
10252 | procP->proc_framereg = 0; | |
10253 | procP->proc_pcreg = 0; | |
10254 | procP->proc_end = NULL; | |
10255 | procP->proc_next = NULL; | |
10256 | if (proc_lastP) | |
10257 | proc_lastP->proc_next = procP; | |
10258 | else | |
10259 | proc_rootP = procP; | |
10260 | proc_lastP = procP; | |
10261 | numprocs++; | |
3d3c5039 | 10262 | } |
670a50eb | 10263 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10264 | } |
10265 | ||
10266 | /* The .frame directive. */ | |
10267 | ||
88225433 | 10268 | #if 0 |
3d3c5039 ILT |
10269 | static void |
10270 | s_frame (x) | |
670a50eb | 10271 | int x; |
3d3c5039 | 10272 | { |
670a50eb ILT |
10273 | char str[100]; |
10274 | symbolS *symP; | |
10275 | int frame_reg; | |
10276 | int frame_off; | |
10277 | int pcreg; | |
10278 | ||
0dd2d296 | 10279 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10280 | if (*input_line_pointer == ',') |
10281 | input_line_pointer++; | |
5ac34ac3 | 10282 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10283 | if (*input_line_pointer == ',') |
10284 | input_line_pointer++; | |
0dd2d296 | 10285 | pcreg = tc_get_register (0); |
670a50eb ILT |
10286 | |
10287 | /* bob third eye */ | |
10288 | assert (proc_rootP); | |
10289 | proc_rootP->proc_framereg = frame_reg; | |
10290 | proc_rootP->proc_frameoffset = frame_off; | |
10291 | proc_rootP->proc_pcreg = pcreg; | |
10292 | /* bob macho .frame */ | |
10293 | ||
10294 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10295 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10296 | { |
10297 | if (!proc_lastP) | |
10298 | as_warn ("No .ent for .frame to use."); | |
10299 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10300 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10301 | S_SET_TYPE (symP, N_RMASK); | |
10302 | S_SET_OTHER (symP, 0); | |
10303 | S_SET_DESC (symP, 0); | |
10304 | symP->sy_forward = proc_lastP->proc_isym; | |
10305 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10306 | } |
670a50eb | 10307 | demand_empty_rest_of_line (); |
3d3c5039 | 10308 | } |
88225433 | 10309 | #endif |
3d3c5039 ILT |
10310 | |
10311 | /* The .fmask and .mask directives. */ | |
10312 | ||
88225433 | 10313 | #if 0 |
3d3c5039 ILT |
10314 | static void |
10315 | s_mask (reg_type) | |
10316 | char reg_type; | |
10317 | { | |
670a50eb ILT |
10318 | char str[100], *strP; |
10319 | symbolS *symP; | |
10320 | int i; | |
10321 | unsigned int mask; | |
10322 | int off; | |
10323 | ||
10324 | mask = get_number (); | |
10325 | if (*input_line_pointer == ',') | |
10326 | input_line_pointer++; | |
10327 | off = get_absolute_expression (); | |
10328 | ||
10329 | /* bob only for coff */ | |
10330 | assert (proc_rootP); | |
10331 | if (reg_type == 'F') | |
10332 | { | |
10333 | proc_rootP->proc_fpreg_mask = mask; | |
10334 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10335 | } |
670a50eb ILT |
10336 | else |
10337 | { | |
10338 | proc_rootP->proc_reg_mask = mask; | |
10339 | proc_rootP->proc_reg_offset = off; | |
10340 | } | |
10341 | ||
10342 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10343 | |
670a50eb ILT |
10344 | /* We don't have to write out a mask stab if no saved regs. */ |
10345 | if (!(mask == 0)) | |
10346 | { | |
10347 | if (!proc_lastP) | |
10348 | as_warn ("No .ent for .mask to use."); | |
10349 | strP = str; | |
10350 | for (i = 0; i < 32; i++) | |
10351 | { | |
10352 | if (mask % 2) | |
10353 | { | |
10354 | sprintf (strP, "%c%d,", reg_type, i); | |
10355 | strP += strlen (strP); | |
10356 | } | |
3d3c5039 | 10357 | mask /= 2; |
670a50eb ILT |
10358 | } |
10359 | sprintf (strP, ";%d,", off); | |
10360 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10361 | S_SET_TYPE (symP, N_RMASK); | |
10362 | S_SET_OTHER (symP, 0); | |
10363 | S_SET_DESC (symP, 0); | |
10364 | symP->sy_forward = proc_lastP->proc_isym; | |
10365 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10366 | } |
3d3c5039 | 10367 | } |
88225433 | 10368 | #endif |
3d3c5039 ILT |
10369 | |
10370 | /* The .loc directive. */ | |
10371 | ||
88225433 | 10372 | #if 0 |
3d3c5039 ILT |
10373 | static void |
10374 | s_loc (x) | |
10375 | int x; | |
10376 | { | |
670a50eb ILT |
10377 | symbolS *symbolP; |
10378 | int lineno; | |
10379 | int addroff; | |
3d3c5039 | 10380 | |
670a50eb | 10381 | assert (now_seg == text_section); |
3d3c5039 | 10382 | |
670a50eb | 10383 | lineno = get_number (); |
87e48495 | 10384 | addroff = frag_now_fix (); |
3d3c5039 | 10385 | |
670a50eb ILT |
10386 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10387 | S_SET_TYPE (symbolP, N_SLINE); | |
10388 | S_SET_OTHER (symbolP, 0); | |
10389 | S_SET_DESC (symbolP, lineno); | |
10390 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10391 | } |
88225433 | 10392 | #endif |