Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
ef2e4d86 | 219 | int ase_mt; |
dec0624d | 220 | int ase_mcu; |
252b5132 RH |
221 | /* Whether we are assembling for the mips16 processor. 0 if we are |
222 | not, 1 if we are, and -1 if the value has not been initialized. | |
223 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
224 | -nomips16 command line options, and the default CPU. */ | |
225 | int mips16; | |
df58fc94 RS |
226 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
227 | 1 if we are, and -1 if the value has not been initialized. Changed | |
228 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
229 | and -mno-micromips command line options, and the default CPU. */ | |
230 | int micromips; | |
252b5132 RH |
231 | /* Non-zero if we should not reorder instructions. Changed by `.set |
232 | reorder' and `.set noreorder'. */ | |
233 | int noreorder; | |
741fe287 MR |
234 | /* Non-zero if we should not permit the register designated "assembler |
235 | temporary" to be used in instructions. The value is the register | |
236 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
237 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
238 | unsigned int at; | |
252b5132 RH |
239 | /* Non-zero if we should warn when a macro instruction expands into |
240 | more than one machine instruction. Changed by `.set nomacro' and | |
241 | `.set macro'. */ | |
242 | int warn_about_macros; | |
243 | /* Non-zero if we should not move instructions. Changed by `.set | |
244 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
245 | int nomove; | |
246 | /* Non-zero if we should not optimize branches by moving the target | |
247 | of the branch into the delay slot. Actually, we don't perform | |
248 | this optimization anyhow. Changed by `.set bopt' and `.set | |
249 | nobopt'. */ | |
250 | int nobopt; | |
251 | /* Non-zero if we should not autoextend mips16 instructions. | |
252 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
253 | int noautoextend; | |
a325df1d TS |
254 | /* Restrict general purpose registers and floating point registers |
255 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
256 | is passed but can changed if the assembler code uses .set mipsN. */ | |
257 | int gp32; | |
258 | int fp32; | |
fef14a42 TS |
259 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
260 | command line option, and the default CPU. */ | |
261 | int arch; | |
aed1a261 RS |
262 | /* True if ".set sym32" is in effect. */ |
263 | bfd_boolean sym32; | |
037b32b9 AN |
264 | /* True if floating-point operations are not allowed. Changed by .set |
265 | softfloat or .set hardfloat, by command line options -msoft-float or | |
266 | -mhard-float. The default is false. */ | |
267 | bfd_boolean soft_float; | |
268 | ||
269 | /* True if only single-precision floating-point operations are allowed. | |
270 | Changed by .set singlefloat or .set doublefloat, command-line options | |
271 | -msingle-float or -mdouble-float. The default is false. */ | |
272 | bfd_boolean single_float; | |
252b5132 RH |
273 | }; |
274 | ||
037b32b9 AN |
275 | /* This is the struct we use to hold the current set of options. Note |
276 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
277 | -1 to indicate that they have not been initialized. */ | |
278 | ||
a325df1d | 279 | /* True if -mgp32 was passed. */ |
a8e8e863 | 280 | static int file_mips_gp32 = -1; |
a325df1d TS |
281 | |
282 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 283 | static int file_mips_fp32 = -1; |
a325df1d | 284 | |
037b32b9 AN |
285 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
286 | static int file_mips_soft_float = 0; | |
287 | ||
288 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
289 | static int file_mips_single_float = 0; | |
252b5132 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
037b32b9 AN |
293 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
294 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
295 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
296 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
297 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
298 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 299 | }; |
252b5132 RH |
300 | |
301 | /* These variables are filled in with the masks of registers used. | |
302 | The object format code reads them and puts them in the appropriate | |
303 | place. */ | |
304 | unsigned long mips_gprmask; | |
305 | unsigned long mips_cprmask[4]; | |
306 | ||
307 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 308 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 309 | |
738f4d98 | 310 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
311 | static int file_ase_mips16; |
312 | ||
3994f87e TS |
313 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2 \ | |
315 | || mips_opts.isa == ISA_MIPS64 \ | |
316 | || mips_opts.isa == ISA_MIPS64R2) | |
317 | ||
df58fc94 RS |
318 | /* True if any microMIPS code was produced. */ |
319 | static int file_ase_micromips; | |
320 | ||
b12dd2e4 CF |
321 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
322 | #ifdef TE_IRIX | |
1180b5a4 | 323 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 324 | #else |
1180b5a4 RS |
325 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
326 | because there's no place for any addend, the only acceptable | |
327 | expression is a bare symbol. */ | |
328 | #define MIPS_JALR_HINT_P(EXPR) \ | |
329 | (!HAVE_IN_PLACE_ADDENDS \ | |
330 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
331 | #endif |
332 | ||
1f25f5d3 CD |
333 | /* True if -mips3d was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mips3d; | |
336 | ||
deec1734 CD |
337 | /* True if -mdmx was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mdmx; | |
340 | ||
e16bfa71 TS |
341 | /* True if -msmartmips was passed or implied by arguments passed on the |
342 | command line (e.g., by -march). */ | |
343 | static int file_ase_smartmips; | |
344 | ||
ad3fea08 TS |
345 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
346 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 347 | |
74cd071d CF |
348 | /* True if -mdsp was passed or implied by arguments passed on the |
349 | command line (e.g., by -march). */ | |
350 | static int file_ase_dsp; | |
351 | ||
ad3fea08 | 352 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
353 | || mips_opts.isa == ISA_MIPS64R2 \ |
354 | || mips_opts.micromips) | |
ad3fea08 | 355 | |
65263ce3 TS |
356 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
357 | ||
8b082fb1 TS |
358 | /* True if -mdspr2 was passed or implied by arguments passed on the |
359 | command line (e.g., by -march). */ | |
360 | static int file_ase_dspr2; | |
361 | ||
362 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
363 | || mips_opts.isa == ISA_MIPS64R2 \ |
364 | || mips_opts.micromips) | |
8b082fb1 | 365 | |
ef2e4d86 CF |
366 | /* True if -mmt was passed or implied by arguments passed on the |
367 | command line (e.g., by -march). */ | |
368 | static int file_ase_mt; | |
369 | ||
ad3fea08 TS |
370 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
371 | || mips_opts.isa == ISA_MIPS64R2) | |
372 | ||
dec0624d | 373 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
374 | || mips_opts.isa == ISA_MIPS64R2 \ |
375 | || mips_opts.micromips) | |
dec0624d | 376 | |
ec68c924 | 377 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 378 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 379 | static const char *mips_arch_string; |
ec68c924 EC |
380 | |
381 | /* The argument of the -mtune= flag. The architecture for which we | |
382 | are optimizing. */ | |
383 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 384 | static const char *mips_tune_string; |
ec68c924 | 385 | |
316f5878 | 386 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
387 | static int mips_32bitmode = 0; |
388 | ||
316f5878 RS |
389 | /* True if the given ABI requires 32-bit registers. */ |
390 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
391 | ||
392 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
393 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
394 | ((ABI) == N32_ABI \ | |
395 | || (ABI) == N64_ABI \ | |
316f5878 RS |
396 | || (ABI) == O64_ABI) |
397 | ||
ad3fea08 | 398 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
399 | #define ISA_HAS_64BIT_REGS(ISA) \ |
400 | ((ISA) == ISA_MIPS3 \ | |
401 | || (ISA) == ISA_MIPS4 \ | |
402 | || (ISA) == ISA_MIPS5 \ | |
403 | || (ISA) == ISA_MIPS64 \ | |
404 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 405 | |
ad3fea08 TS |
406 | /* Return true if ISA supports 64 bit wide float registers. */ |
407 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
408 | ((ISA) == ISA_MIPS3 \ | |
409 | || (ISA) == ISA_MIPS4 \ | |
410 | || (ISA) == ISA_MIPS5 \ | |
411 | || (ISA) == ISA_MIPS32R2 \ | |
412 | || (ISA) == ISA_MIPS64 \ | |
413 | || (ISA) == ISA_MIPS64R2) | |
414 | ||
af7ee8bf CD |
415 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
416 | instructions. */ | |
707bfff6 | 417 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
418 | ((ISA) == ISA_MIPS64R2 \ |
419 | || (mips_opts.micromips \ | |
420 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
421 | ) | |
af7ee8bf CD |
422 | |
423 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
424 | instructions. */ | |
707bfff6 TS |
425 | #define ISA_HAS_ROR(ISA) \ |
426 | ((ISA) == ISA_MIPS32R2 \ | |
427 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
428 | || mips_opts.ase_smartmips \ |
429 | || mips_opts.micromips \ | |
430 | ) | |
707bfff6 | 431 | |
7455baf8 TS |
432 | /* Return true if ISA supports single-precision floats in odd registers. */ |
433 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
434 | ((ISA) == ISA_MIPS32 \ | |
435 | || (ISA) == ISA_MIPS32R2 \ | |
436 | || (ISA) == ISA_MIPS64 \ | |
437 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 438 | |
ad3fea08 TS |
439 | /* Return true if ISA supports move to/from high part of a 64-bit |
440 | floating-point register. */ | |
441 | #define ISA_HAS_MXHC1(ISA) \ | |
442 | ((ISA) == ISA_MIPS32R2 \ | |
443 | || (ISA) == ISA_MIPS64R2) | |
444 | ||
e013f690 | 445 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 446 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 447 | |
e013f690 | 448 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 449 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 450 | |
ad3fea08 TS |
451 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
452 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 453 | |
316f5878 | 454 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 455 | |
316f5878 | 456 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 457 | |
3b91255e RS |
458 | /* True if relocations are stored in-place. */ |
459 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
460 | ||
aed1a261 RS |
461 | /* The ABI-derived address size. */ |
462 | #define HAVE_64BIT_ADDRESSES \ | |
463 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
464 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 465 | |
aed1a261 RS |
466 | /* The size of symbolic constants (i.e., expressions of the form |
467 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
468 | #define HAVE_32BIT_SYMBOLS \ | |
469 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
470 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 471 | |
b7c7d6c1 TS |
472 | /* Addresses are loaded in different ways, depending on the address size |
473 | in use. The n32 ABI Documentation also mandates the use of additions | |
474 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 475 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 476 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
477 | |
478 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 479 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
480 | |
481 | #define ADDRESS_LOAD_INSN \ | |
482 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
483 | ||
484 | #define ADDRESS_STORE_INSN \ | |
485 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
486 | ||
a4672219 | 487 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
488 | #define CPU_HAS_MIPS16(cpu) \ |
489 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
490 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 491 | |
2309ddf2 | 492 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
493 | #define CPU_HAS_MICROMIPS(cpu) 0 |
494 | ||
60b63b72 RS |
495 | /* True if CPU has a dror instruction. */ |
496 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
497 | ||
498 | /* True if CPU has a ror instruction. */ | |
499 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
500 | ||
dd6a37e7 | 501 | /* True if CPU is in the Octeon family */ |
432233b3 | 502 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 503 | |
dd3cbb7e | 504 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 505 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 506 | |
0aa27725 RS |
507 | /* True, if CPU has support for ldc1 and sdc1. */ |
508 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
509 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
510 | ||
c8978940 CD |
511 | /* True if mflo and mfhi can be immediately followed by instructions |
512 | which write to the HI and LO registers. | |
513 | ||
514 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
515 | (at least) two instructions between the reads of HI/LO and | |
516 | instructions which write them, and later ISAs do not. Contradicting | |
517 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
518 | the UM for the NEC Vr5000) document needing the instructions between | |
519 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
520 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
521 | earlier-ISA CPUs for which CPU documentation declares that the | |
522 | instructions are really interlocked. */ | |
523 | #define hilo_interlocks \ | |
524 | (mips_opts.isa == ISA_MIPS32 \ | |
525 | || mips_opts.isa == ISA_MIPS32R2 \ | |
526 | || mips_opts.isa == ISA_MIPS64 \ | |
527 | || mips_opts.isa == ISA_MIPS64R2 \ | |
528 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 529 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
530 | || mips_opts.arch == CPU_R10000 \ |
531 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
532 | || mips_opts.arch == CPU_R14000 \ |
533 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 534 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 535 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 536 | || mips_opts.micromips \ |
c8978940 | 537 | ) |
252b5132 RH |
538 | |
539 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
540 | from the GPRs after they are loaded from memory, and thus does not |
541 | require nops to be inserted. This applies to instructions marked | |
542 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
543 | level I and microMIPS mode instructions are always interlocked. */ |
544 | #define gpr_interlocks \ | |
545 | (mips_opts.isa != ISA_MIPS1 \ | |
546 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
548 | || mips_opts.micromips \ |
549 | ) | |
252b5132 | 550 | |
81912461 ILT |
551 | /* Whether the processor uses hardware interlocks to avoid delays |
552 | required by coprocessor instructions, and thus does not require | |
553 | nops to be inserted. This applies to instructions marked | |
554 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
555 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
556 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
557 | levels I, II, and III and microMIPS mode instructions are always |
558 | interlocked. */ | |
bdaaa2e1 | 559 | /* Itbl support may require additional care here. */ |
81912461 ILT |
560 | #define cop_interlocks \ |
561 | ((mips_opts.isa != ISA_MIPS1 \ | |
562 | && mips_opts.isa != ISA_MIPS2 \ | |
563 | && mips_opts.isa != ISA_MIPS3) \ | |
564 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 565 | || mips_opts.micromips \ |
81912461 ILT |
566 | ) |
567 | ||
568 | /* Whether the processor uses hardware interlocks to protect reads | |
569 | from coprocessor registers after they are loaded from memory, and | |
570 | thus does not require nops to be inserted. This applies to | |
571 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
572 | requires at MIPS ISA level I and microMIPS mode instructions are |
573 | always interlocked. */ | |
574 | #define cop_mem_interlocks \ | |
575 | (mips_opts.isa != ISA_MIPS1 \ | |
576 | || mips_opts.micromips \ | |
577 | ) | |
252b5132 | 578 | |
6b76fefe CM |
579 | /* Is this a mfhi or mflo instruction? */ |
580 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
581 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
582 | ||
df58fc94 RS |
583 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
584 | has been selected. This implies, in particular, that addresses of text | |
585 | labels have their LSB set. */ | |
586 | #define HAVE_CODE_COMPRESSION \ | |
587 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
588 | ||
252b5132 RH |
589 | /* MIPS PIC level. */ |
590 | ||
a161fe53 | 591 | enum mips_pic_level mips_pic; |
252b5132 | 592 | |
c9914766 | 593 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 594 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 595 | static int mips_big_got = 0; |
252b5132 RH |
596 | |
597 | /* 1 if trap instructions should used for overflow rather than break | |
598 | instructions. */ | |
c9914766 | 599 | static int mips_trap = 0; |
252b5132 | 600 | |
119d663a | 601 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 602 | by assembling two single width halves into two single width floating |
119d663a NC |
603 | point registers which just happen to alias the double width destination |
604 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 605 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
606 | automatically at assemble time. */ |
607 | static int mips_disable_float_construction; | |
608 | ||
252b5132 RH |
609 | /* Non-zero if any .set noreorder directives were used. */ |
610 | ||
611 | static int mips_any_noreorder; | |
612 | ||
6b76fefe CM |
613 | /* Non-zero if nops should be inserted when the register referenced in |
614 | an mfhi/mflo instruction is read in the next two instructions. */ | |
615 | static int mips_7000_hilo_fix; | |
616 | ||
02ffd3e4 | 617 | /* The size of objects in the small data section. */ |
156c2f8b | 618 | static unsigned int g_switch_value = 8; |
252b5132 RH |
619 | /* Whether the -G option was used. */ |
620 | static int g_switch_seen = 0; | |
621 | ||
622 | #define N_RMASK 0xc4 | |
623 | #define N_VFP 0xd4 | |
624 | ||
625 | /* If we can determine in advance that GP optimization won't be | |
626 | possible, we can skip the relaxation stuff that tries to produce | |
627 | GP-relative references. This makes delay slot optimization work | |
628 | better. | |
629 | ||
630 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
631 | gcc output. It needs to guess right for gcc, otherwise gcc |
632 | will put what it thinks is a GP-relative instruction in a branch | |
633 | delay slot. | |
252b5132 RH |
634 | |
635 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
636 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 637 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
638 | |
639 | /* handle of the OPCODE hash table */ | |
640 | static struct hash_control *op_hash = NULL; | |
641 | ||
642 | /* The opcode hash table we use for the mips16. */ | |
643 | static struct hash_control *mips16_op_hash = NULL; | |
644 | ||
df58fc94 RS |
645 | /* The opcode hash table we use for the microMIPS ASE. */ |
646 | static struct hash_control *micromips_op_hash = NULL; | |
647 | ||
252b5132 RH |
648 | /* This array holds the chars that always start a comment. If the |
649 | pre-processor is disabled, these aren't very useful */ | |
650 | const char comment_chars[] = "#"; | |
651 | ||
652 | /* This array holds the chars that only start a comment at the beginning of | |
653 | a line. If the line seems to have the form '# 123 filename' | |
654 | .line and .file directives will appear in the pre-processed output */ | |
655 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
656 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 657 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
658 | /* Also note that C style comments are always supported. */ |
659 | const char line_comment_chars[] = "#"; | |
660 | ||
bdaaa2e1 | 661 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 662 | const char line_separator_chars[] = ";"; |
252b5132 RH |
663 | |
664 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
665 | const char EXP_CHARS[] = "eE"; | |
666 | ||
667 | /* Chars that mean this number is a floating point constant */ | |
668 | /* As in 0f12.456 */ | |
669 | /* or 0d1.2345e12 */ | |
670 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
671 | ||
672 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
673 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
674 | but nothing is ideal around here. | |
675 | */ | |
676 | ||
677 | static char *insn_error; | |
678 | ||
679 | static int auto_align = 1; | |
680 | ||
681 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
682 | offset in the stack frame from which to restore the $gp register. | |
683 | This is set by the .cprestore pseudo-op, and saved in this | |
684 | variable. */ | |
685 | static offsetT mips_cprestore_offset = -1; | |
686 | ||
67c1ffbe | 687 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 688 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 689 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
690 | static offsetT mips_cpreturn_offset = -1; |
691 | static int mips_cpreturn_register = -1; | |
692 | static int mips_gp_register = GP; | |
def2e0dd | 693 | static int mips_gprel_offset = 0; |
6478892d | 694 | |
7a621144 DJ |
695 | /* Whether mips_cprestore_offset has been set in the current function |
696 | (or whether it has already been warned about, if not). */ | |
697 | static int mips_cprestore_valid = 0; | |
698 | ||
252b5132 RH |
699 | /* This is the register which holds the stack frame, as set by the |
700 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
701 | static int mips_frame_reg = SP; | |
702 | ||
7a621144 DJ |
703 | /* Whether mips_frame_reg has been set in the current function |
704 | (or whether it has already been warned about, if not). */ | |
705 | static int mips_frame_reg_valid = 0; | |
706 | ||
252b5132 RH |
707 | /* To output NOP instructions correctly, we need to keep information |
708 | about the previous two instructions. */ | |
709 | ||
710 | /* Whether we are optimizing. The default value of 2 means to remove | |
711 | unneeded NOPs and swap branch instructions when possible. A value | |
712 | of 1 means to not swap branches. A value of 0 means to always | |
713 | insert NOPs. */ | |
714 | static int mips_optimize = 2; | |
715 | ||
716 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
717 | equivalent to seeing no -g option at all. */ | |
718 | static int mips_debug = 0; | |
719 | ||
7d8e00cf RS |
720 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
721 | #define MAX_VR4130_NOPS 4 | |
722 | ||
723 | /* The maximum number of NOPs needed to fill delay slots. */ | |
724 | #define MAX_DELAY_NOPS 2 | |
725 | ||
726 | /* The maximum number of NOPs needed for any purpose. */ | |
727 | #define MAX_NOPS 4 | |
71400594 RS |
728 | |
729 | /* A list of previous instructions, with index 0 being the most recent. | |
730 | We need to look back MAX_NOPS instructions when filling delay slots | |
731 | or working around processor errata. We need to look back one | |
732 | instruction further if we're thinking about using history[0] to | |
733 | fill a branch delay slot. */ | |
734 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 735 | |
1e915849 | 736 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
737 | static struct mips_cl_insn nop_insn; |
738 | static struct mips_cl_insn mips16_nop_insn; | |
739 | static struct mips_cl_insn micromips_nop16_insn; | |
740 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
741 | |
742 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
743 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
744 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
745 | ||
746 | /* The size of NOP_INSN in bytes. */ | |
747 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 748 | |
252b5132 RH |
749 | /* If this is set, it points to a frag holding nop instructions which |
750 | were inserted before the start of a noreorder section. If those | |
751 | nops turn out to be unnecessary, the size of the frag can be | |
752 | decreased. */ | |
753 | static fragS *prev_nop_frag; | |
754 | ||
755 | /* The number of nop instructions we created in prev_nop_frag. */ | |
756 | static int prev_nop_frag_holds; | |
757 | ||
758 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 759 | prev_nop_frag. */ |
252b5132 RH |
760 | static int prev_nop_frag_required; |
761 | ||
762 | /* The number of instructions we've seen since prev_nop_frag. */ | |
763 | static int prev_nop_frag_since; | |
764 | ||
765 | /* For ECOFF and ELF, relocations against symbols are done in two | |
766 | parts, with a HI relocation and a LO relocation. Each relocation | |
767 | has only 16 bits of space to store an addend. This means that in | |
768 | order for the linker to handle carries correctly, it must be able | |
769 | to locate both the HI and the LO relocation. This means that the | |
770 | relocations must appear in order in the relocation table. | |
771 | ||
772 | In order to implement this, we keep track of each unmatched HI | |
773 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 774 | corresponding LO relocation. */ |
252b5132 | 775 | |
e972090a NC |
776 | struct mips_hi_fixup |
777 | { | |
252b5132 RH |
778 | /* Next HI fixup. */ |
779 | struct mips_hi_fixup *next; | |
780 | /* This fixup. */ | |
781 | fixS *fixp; | |
782 | /* The section this fixup is in. */ | |
783 | segT seg; | |
784 | }; | |
785 | ||
786 | /* The list of unmatched HI relocs. */ | |
787 | ||
788 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
789 | ||
64bdfcaf RS |
790 | /* The frag containing the last explicit relocation operator. |
791 | Null if explicit relocations have not been used. */ | |
792 | ||
793 | static fragS *prev_reloc_op_frag; | |
794 | ||
252b5132 RH |
795 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
796 | ||
797 | #define X ILLEGAL_REG | |
e972090a NC |
798 | static const int mips32_to_16_reg_map[] = |
799 | { | |
252b5132 RH |
800 | X, X, 2, 3, 4, 5, 6, 7, |
801 | X, X, X, X, X, X, X, X, | |
802 | 0, 1, X, X, X, X, X, X, | |
803 | X, X, X, X, X, X, X, X | |
804 | }; | |
805 | #undef X | |
806 | ||
807 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
808 | ||
e972090a NC |
809 | static const unsigned int mips16_to_32_reg_map[] = |
810 | { | |
252b5132 RH |
811 | 16, 17, 2, 3, 4, 5, 6, 7 |
812 | }; | |
60b63b72 | 813 | |
df58fc94 RS |
814 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
815 | ||
816 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
817 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
818 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
819 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
820 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
821 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
822 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
823 | ||
824 | #define X ILLEGAL_REG | |
825 | /* reg type h: 4, 5, 6. */ | |
826 | static const int mips32_to_micromips_reg_h_map[] = | |
827 | { | |
828 | X, X, X, X, 4, 5, 6, X, | |
829 | X, X, X, X, X, X, X, X, | |
830 | X, X, X, X, X, X, X, X, | |
831 | X, X, X, X, X, X, X, X | |
832 | }; | |
833 | ||
834 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
835 | static const int mips32_to_micromips_reg_m_map[] = | |
836 | { | |
837 | 0, X, 2, 3, X, X, X, X, | |
838 | X, X, X, X, X, X, X, X, | |
839 | 4, 1, 5, 6, 7, X, X, X, | |
840 | X, X, X, X, X, X, X, X | |
841 | }; | |
842 | ||
843 | /* reg type q: 0, 2-7. 17. */ | |
844 | static const int mips32_to_micromips_reg_q_map[] = | |
845 | { | |
846 | 0, X, 2, 3, 4, 5, 6, 7, | |
847 | X, X, X, X, X, X, X, X, | |
848 | X, 1, X, X, X, X, X, X, | |
849 | X, X, X, X, X, X, X, X | |
850 | }; | |
851 | ||
852 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
853 | #undef X | |
854 | ||
855 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
856 | ||
857 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
858 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
859 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
860 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
861 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
862 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
863 | ||
864 | /* The microMIPS registers with type h. */ | |
865 | static const unsigned int micromips_to_32_reg_h_map[] = | |
866 | { | |
867 | 5, 5, 6, 4, 4, 4, 4, 4 | |
868 | }; | |
869 | ||
870 | /* The microMIPS registers with type i. */ | |
871 | static const unsigned int micromips_to_32_reg_i_map[] = | |
872 | { | |
873 | 6, 7, 7, 21, 22, 5, 6, 7 | |
874 | }; | |
875 | ||
876 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
877 | ||
878 | /* The microMIPS registers with type m. */ | |
879 | static const unsigned int micromips_to_32_reg_m_map[] = | |
880 | { | |
881 | 0, 17, 2, 3, 16, 18, 19, 20 | |
882 | }; | |
883 | ||
884 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
885 | ||
886 | /* The microMIPS registers with type q. */ | |
887 | static const unsigned int micromips_to_32_reg_q_map[] = | |
888 | { | |
889 | 0, 17, 2, 3, 4, 5, 6, 7 | |
890 | }; | |
891 | ||
892 | /* microMIPS imm type B. */ | |
893 | static const int micromips_imm_b_map[] = | |
894 | { | |
895 | 1, 4, 8, 12, 16, 20, 24, -1 | |
896 | }; | |
897 | ||
898 | /* microMIPS imm type C. */ | |
899 | static const int micromips_imm_c_map[] = | |
900 | { | |
901 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
902 | }; | |
903 | ||
71400594 RS |
904 | /* Classifies the kind of instructions we're interested in when |
905 | implementing -mfix-vr4120. */ | |
c67a084a NC |
906 | enum fix_vr4120_class |
907 | { | |
71400594 RS |
908 | FIX_VR4120_MACC, |
909 | FIX_VR4120_DMACC, | |
910 | FIX_VR4120_MULT, | |
911 | FIX_VR4120_DMULT, | |
912 | FIX_VR4120_DIV, | |
913 | FIX_VR4120_MTHILO, | |
914 | NUM_FIX_VR4120_CLASSES | |
915 | }; | |
916 | ||
c67a084a NC |
917 | /* ...likewise -mfix-loongson2f-jump. */ |
918 | static bfd_boolean mips_fix_loongson2f_jump; | |
919 | ||
920 | /* ...likewise -mfix-loongson2f-nop. */ | |
921 | static bfd_boolean mips_fix_loongson2f_nop; | |
922 | ||
923 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
924 | static bfd_boolean mips_fix_loongson2f; | |
925 | ||
71400594 RS |
926 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
927 | there must be at least one other instruction between an instruction | |
928 | of type X and an instruction of type Y. */ | |
929 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
930 | ||
931 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 932 | static int mips_fix_vr4120; |
4a6a3df4 | 933 | |
7d8e00cf RS |
934 | /* ...likewise -mfix-vr4130. */ |
935 | static int mips_fix_vr4130; | |
936 | ||
6a32d874 CM |
937 | /* ...likewise -mfix-24k. */ |
938 | static int mips_fix_24k; | |
939 | ||
d954098f DD |
940 | /* ...likewise -mfix-cn63xxp1 */ |
941 | static bfd_boolean mips_fix_cn63xxp1; | |
942 | ||
4a6a3df4 AO |
943 | /* We don't relax branches by default, since this causes us to expand |
944 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
945 | fail to compute the offset before expanding the macro to the most | |
946 | efficient expansion. */ | |
947 | ||
948 | static int mips_relax_branch; | |
252b5132 | 949 | \f |
4d7206a2 RS |
950 | /* The expansion of many macros depends on the type of symbol that |
951 | they refer to. For example, when generating position-dependent code, | |
952 | a macro that refers to a symbol may have two different expansions, | |
953 | one which uses GP-relative addresses and one which uses absolute | |
954 | addresses. When generating SVR4-style PIC, a macro may have | |
955 | different expansions for local and global symbols. | |
956 | ||
957 | We handle these situations by generating both sequences and putting | |
958 | them in variant frags. In position-dependent code, the first sequence | |
959 | will be the GP-relative one and the second sequence will be the | |
960 | absolute one. In SVR4 PIC, the first sequence will be for global | |
961 | symbols and the second will be for local symbols. | |
962 | ||
584892a6 RS |
963 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
964 | SECOND are the lengths of the two sequences in bytes. These fields | |
965 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
966 | the subtype has the following flags: | |
4d7206a2 | 967 | |
584892a6 RS |
968 | RELAX_USE_SECOND |
969 | Set if it has been decided that we should use the second | |
970 | sequence instead of the first. | |
971 | ||
972 | RELAX_SECOND_LONGER | |
973 | Set in the first variant frag if the macro's second implementation | |
974 | is longer than its first. This refers to the macro as a whole, | |
975 | not an individual relaxation. | |
976 | ||
977 | RELAX_NOMACRO | |
978 | Set in the first variant frag if the macro appeared in a .set nomacro | |
979 | block and if one alternative requires a warning but the other does not. | |
980 | ||
981 | RELAX_DELAY_SLOT | |
982 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
983 | delay slot. | |
4d7206a2 | 984 | |
df58fc94 RS |
985 | RELAX_DELAY_SLOT_16BIT |
986 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
987 | 16-bit instruction. | |
988 | ||
989 | RELAX_DELAY_SLOT_SIZE_FIRST | |
990 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
991 | the macro is of the wrong size for the branch delay slot. | |
992 | ||
993 | RELAX_DELAY_SLOT_SIZE_SECOND | |
994 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
995 | the macro is of the wrong size for the branch delay slot. | |
996 | ||
4d7206a2 RS |
997 | The frag's "opcode" points to the first fixup for relaxable code. |
998 | ||
999 | Relaxable macros are generated using a sequence such as: | |
1000 | ||
1001 | relax_start (SYMBOL); | |
1002 | ... generate first expansion ... | |
1003 | relax_switch (); | |
1004 | ... generate second expansion ... | |
1005 | relax_end (); | |
1006 | ||
1007 | The code and fixups for the unwanted alternative are discarded | |
1008 | by md_convert_frag. */ | |
584892a6 | 1009 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1010 | |
584892a6 RS |
1011 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1012 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1013 | #define RELAX_USE_SECOND 0x10000 | |
1014 | #define RELAX_SECOND_LONGER 0x20000 | |
1015 | #define RELAX_NOMACRO 0x40000 | |
1016 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1017 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1018 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1019 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1020 | |
4a6a3df4 AO |
1021 | /* Branch without likely bit. If label is out of range, we turn: |
1022 | ||
1023 | beq reg1, reg2, label | |
1024 | delay slot | |
1025 | ||
1026 | into | |
1027 | ||
1028 | bne reg1, reg2, 0f | |
1029 | nop | |
1030 | j label | |
1031 | 0: delay slot | |
1032 | ||
1033 | with the following opcode replacements: | |
1034 | ||
1035 | beq <-> bne | |
1036 | blez <-> bgtz | |
1037 | bltz <-> bgez | |
1038 | bc1f <-> bc1t | |
1039 | ||
1040 | bltzal <-> bgezal (with jal label instead of j label) | |
1041 | ||
1042 | Even though keeping the delay slot instruction in the delay slot of | |
1043 | the branch would be more efficient, it would be very tricky to do | |
1044 | correctly, because we'd have to introduce a variable frag *after* | |
1045 | the delay slot instruction, and expand that instead. Let's do it | |
1046 | the easy way for now, even if the branch-not-taken case now costs | |
1047 | one additional instruction. Out-of-range branches are not supposed | |
1048 | to be common, anyway. | |
1049 | ||
1050 | Branch likely. If label is out of range, we turn: | |
1051 | ||
1052 | beql reg1, reg2, label | |
1053 | delay slot (annulled if branch not taken) | |
1054 | ||
1055 | into | |
1056 | ||
1057 | beql reg1, reg2, 1f | |
1058 | nop | |
1059 | beql $0, $0, 2f | |
1060 | nop | |
1061 | 1: j[al] label | |
1062 | delay slot (executed only if branch taken) | |
1063 | 2: | |
1064 | ||
1065 | It would be possible to generate a shorter sequence by losing the | |
1066 | likely bit, generating something like: | |
b34976b6 | 1067 | |
4a6a3df4 AO |
1068 | bne reg1, reg2, 0f |
1069 | nop | |
1070 | j[al] label | |
1071 | delay slot (executed only if branch taken) | |
1072 | 0: | |
1073 | ||
1074 | beql -> bne | |
1075 | bnel -> beq | |
1076 | blezl -> bgtz | |
1077 | bgtzl -> blez | |
1078 | bltzl -> bgez | |
1079 | bgezl -> bltz | |
1080 | bc1fl -> bc1t | |
1081 | bc1tl -> bc1f | |
1082 | ||
1083 | bltzall -> bgezal (with jal label instead of j label) | |
1084 | bgezall -> bltzal (ditto) | |
1085 | ||
1086 | ||
1087 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1088 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1089 | ((relax_substateT) \ | |
1090 | (0xc0000000 \ | |
1091 | | ((at) & 0x1f) \ | |
1092 | | ((toofar) ? 0x20 : 0) \ | |
1093 | | ((link) ? 0x40 : 0) \ | |
1094 | | ((likely) ? 0x80 : 0) \ | |
1095 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1096 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1097 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1098 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1099 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1100 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1101 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1102 | |
252b5132 RH |
1103 | /* For mips16 code, we use an entirely different form of relaxation. |
1104 | mips16 supports two versions of most instructions which take | |
1105 | immediate values: a small one which takes some small value, and a | |
1106 | larger one which takes a 16 bit value. Since branches also follow | |
1107 | this pattern, relaxing these values is required. | |
1108 | ||
1109 | We can assemble both mips16 and normal MIPS code in a single | |
1110 | object. Therefore, we need to support this type of relaxation at | |
1111 | the same time that we support the relaxation described above. We | |
1112 | use the high bit of the subtype field to distinguish these cases. | |
1113 | ||
1114 | The information we store for this type of relaxation is the | |
1115 | argument code found in the opcode file for this relocation, whether | |
1116 | the user explicitly requested a small or extended form, and whether | |
1117 | the relocation is in a jump or jal delay slot. That tells us the | |
1118 | size of the value, and how it should be stored. We also store | |
1119 | whether the fragment is considered to be extended or not. We also | |
1120 | store whether this is known to be a branch to a different section, | |
1121 | whether we have tried to relax this frag yet, and whether we have | |
1122 | ever extended a PC relative fragment because of a shift count. */ | |
1123 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1124 | (0x80000000 \ | |
1125 | | ((type) & 0xff) \ | |
1126 | | ((small) ? 0x100 : 0) \ | |
1127 | | ((ext) ? 0x200 : 0) \ | |
1128 | | ((dslot) ? 0x400 : 0) \ | |
1129 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1130 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1131 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1132 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1133 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1134 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1135 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1136 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1137 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1138 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1139 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1140 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1141 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1142 | |
df58fc94 RS |
1143 | /* For microMIPS code, we use relaxation similar to one we use for |
1144 | MIPS16 code. Some instructions that take immediate values support | |
1145 | two encodings: a small one which takes some small value, and a | |
1146 | larger one which takes a 16 bit value. As some branches also follow | |
1147 | this pattern, relaxing these values is required. | |
1148 | ||
1149 | We can assemble both microMIPS and normal MIPS code in a single | |
1150 | object. Therefore, we need to support this type of relaxation at | |
1151 | the same time that we support the relaxation described above. We | |
1152 | use one of the high bits of the subtype field to distinguish these | |
1153 | cases. | |
1154 | ||
1155 | The information we store for this type of relaxation is the argument | |
1156 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1157 | selected as the assembler temporary, whether the branch is |
1158 | unconditional, whether it is compact, whether it stores the link | |
1159 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1160 | branches to a sequence of instructions is enabled, and whether the | |
1161 | displacement of a branch is too large to fit as an immediate argument | |
1162 | of a 16-bit and a 32-bit branch, respectively. */ | |
1163 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1164 | relax32, toofar16, toofar32) \ | |
1165 | (0x40000000 \ | |
1166 | | ((type) & 0xff) \ | |
1167 | | (((at) & 0x1f) << 8) \ | |
1168 | | ((uncond) ? 0x2000 : 0) \ | |
1169 | | ((compact) ? 0x4000 : 0) \ | |
1170 | | ((link) ? 0x8000 : 0) \ | |
1171 | | ((relax32) ? 0x10000 : 0) \ | |
1172 | | ((toofar16) ? 0x20000 : 0) \ | |
1173 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1174 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1175 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1176 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1177 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1178 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1179 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1180 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1181 | ||
1182 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1183 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1184 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1185 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1186 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1187 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1188 | |
43c0598f RS |
1189 | /* Sign-extend 16-bit value X. */ |
1190 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1191 | ||
885add95 CD |
1192 | /* Is the given value a sign-extended 32-bit value? */ |
1193 | #define IS_SEXT_32BIT_NUM(x) \ | |
1194 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1195 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1196 | ||
1197 | /* Is the given value a sign-extended 16-bit value? */ | |
1198 | #define IS_SEXT_16BIT_NUM(x) \ | |
1199 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1200 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1201 | ||
df58fc94 RS |
1202 | /* Is the given value a sign-extended 12-bit value? */ |
1203 | #define IS_SEXT_12BIT_NUM(x) \ | |
1204 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1205 | ||
2051e8c4 MR |
1206 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1207 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1208 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1209 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1210 | ||
bf12938e RS |
1211 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1212 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1213 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1214 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1215 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1216 | ||
1217 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1218 | SHIFT places. */ | |
1219 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1220 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1221 | ||
1222 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1223 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1224 | ||
1225 | include/opcode/mips.h specifies operand fields using the macros | |
1226 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1227 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1228 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1229 | do \ | |
1230 | if (!(MICROMIPS)) \ | |
1231 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1232 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1233 | else \ | |
1234 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1235 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1236 | while (0) | |
bf12938e RS |
1237 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1238 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1239 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1240 | ||
1241 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1242 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1243 | (!(MICROMIPS) \ | |
1244 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1245 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1246 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1247 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1248 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1249 | MIPS16OP_MASK_##FIELD, \ | |
1250 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1251 | |
1252 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1253 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1254 | \f |
df58fc94 RS |
1255 | /* Whether or not we are emitting a branch-likely macro. */ |
1256 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1257 | ||
4d7206a2 RS |
1258 | /* Global variables used when generating relaxable macros. See the |
1259 | comment above RELAX_ENCODE for more details about how relaxation | |
1260 | is used. */ | |
1261 | static struct { | |
1262 | /* 0 if we're not emitting a relaxable macro. | |
1263 | 1 if we're emitting the first of the two relaxation alternatives. | |
1264 | 2 if we're emitting the second alternative. */ | |
1265 | int sequence; | |
1266 | ||
1267 | /* The first relaxable fixup in the current frag. (In other words, | |
1268 | the first fixup that refers to relaxable code.) */ | |
1269 | fixS *first_fixup; | |
1270 | ||
1271 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1272 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1273 | unsigned int sizes[2]; | |
1274 | ||
1275 | /* The symbol on which the choice of sequence depends. */ | |
1276 | symbolS *symbol; | |
1277 | } mips_relax; | |
252b5132 | 1278 | \f |
584892a6 RS |
1279 | /* Global variables used to decide whether a macro needs a warning. */ |
1280 | static struct { | |
1281 | /* True if the macro is in a branch delay slot. */ | |
1282 | bfd_boolean delay_slot_p; | |
1283 | ||
df58fc94 RS |
1284 | /* Set to the length in bytes required if the macro is in a delay slot |
1285 | that requires a specific length of instruction, otherwise zero. */ | |
1286 | unsigned int delay_slot_length; | |
1287 | ||
584892a6 RS |
1288 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1289 | in bytes and sizes[1] is the length of the second alternative. | |
1290 | For non-relaxable macros, both elements give the length of the | |
1291 | macro in bytes. */ | |
1292 | unsigned int sizes[2]; | |
1293 | ||
df58fc94 RS |
1294 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1295 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1296 | is the length of the first instruction of the second alternative. | |
1297 | For non-relaxable macros, both elements give the length of the first | |
1298 | instruction in bytes. | |
1299 | ||
1300 | Set to zero if we haven't yet seen the first instruction. */ | |
1301 | unsigned int first_insn_sizes[2]; | |
1302 | ||
1303 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1304 | first alternative and insns[1] is the number of instructions for the | |
1305 | second alternative. | |
1306 | ||
1307 | For non-relaxable macros, both elements give the number of | |
1308 | instructions for the macro. */ | |
1309 | unsigned int insns[2]; | |
1310 | ||
584892a6 RS |
1311 | /* The first variant frag for this macro. */ |
1312 | fragS *first_frag; | |
1313 | } mips_macro_warning; | |
1314 | \f | |
252b5132 RH |
1315 | /* Prototypes for static functions. */ |
1316 | ||
252b5132 RH |
1317 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1318 | ||
b34976b6 | 1319 | static void append_insn |
df58fc94 RS |
1320 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1321 | bfd_boolean expansionp); | |
7d10b47d | 1322 | static void mips_no_prev_insn (void); |
c67a084a | 1323 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1324 | static void mips16_macro_build |
03ea81db | 1325 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1326 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1327 | static void macro_start (void); |
1328 | static void macro_end (void); | |
17a2f251 TS |
1329 | static void macro (struct mips_cl_insn * ip); |
1330 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1331 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1332 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1333 | static void mips16_immed |
43c0598f RS |
1334 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1335 | unsigned int, unsigned long *); | |
5e0116d5 | 1336 | static size_t my_getSmallExpression |
17a2f251 TS |
1337 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1338 | static void my_getExpression (expressionS *, char *); | |
1339 | static void s_align (int); | |
1340 | static void s_change_sec (int); | |
1341 | static void s_change_section (int); | |
1342 | static void s_cons (int); | |
1343 | static void s_float_cons (int); | |
1344 | static void s_mips_globl (int); | |
1345 | static void s_option (int); | |
1346 | static void s_mipsset (int); | |
1347 | static void s_abicalls (int); | |
1348 | static void s_cpload (int); | |
1349 | static void s_cpsetup (int); | |
1350 | static void s_cplocal (int); | |
1351 | static void s_cprestore (int); | |
1352 | static void s_cpreturn (int); | |
741d6ea8 JM |
1353 | static void s_dtprelword (int); |
1354 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1355 | static void s_tprelword (int); |
1356 | static void s_tpreldword (int); | |
17a2f251 TS |
1357 | static void s_gpvalue (int); |
1358 | static void s_gpword (int); | |
1359 | static void s_gpdword (int); | |
1360 | static void s_cpadd (int); | |
1361 | static void s_insn (int); | |
1362 | static void md_obj_begin (void); | |
1363 | static void md_obj_end (void); | |
1364 | static void s_mips_ent (int); | |
1365 | static void s_mips_end (int); | |
1366 | static void s_mips_frame (int); | |
1367 | static void s_mips_mask (int reg_type); | |
1368 | static void s_mips_stab (int); | |
1369 | static void s_mips_weakext (int); | |
1370 | static void s_mips_file (int); | |
1371 | static void s_mips_loc (int); | |
1372 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1373 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1374 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1375 | static int validate_micromips_insn (const struct mips_opcode *); |
1376 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1377 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1378 | |
1379 | /* Table and functions used to map between CPU/ISA names, and | |
1380 | ISA levels, and CPU numbers. */ | |
1381 | ||
e972090a NC |
1382 | struct mips_cpu_info |
1383 | { | |
e7af610e | 1384 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1385 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1386 | int isa; /* ISA level. */ |
1387 | int cpu; /* CPU number (default CPU if ISA). */ | |
1388 | }; | |
1389 | ||
ad3fea08 TS |
1390 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1391 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1392 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1393 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1394 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1395 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1396 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1397 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1398 | |
17a2f251 TS |
1399 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1400 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1401 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1402 | \f |
1403 | /* Pseudo-op table. | |
1404 | ||
1405 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1406 | should be defined here, but are currently unsupported: .alias, | |
1407 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1408 | ||
1409 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1410 | specific to the type of debugging information being generated, and | |
1411 | should be defined by the object format: .aent, .begin, .bend, | |
1412 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1413 | .vreg. | |
1414 | ||
1415 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1416 | not MIPS CPU specific, but are also not specific to the object file | |
1417 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1418 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1419 | |
e972090a NC |
1420 | static const pseudo_typeS mips_pseudo_table[] = |
1421 | { | |
beae10d5 | 1422 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1423 | {"option", s_option, 0}, |
1424 | {"set", s_mipsset, 0}, | |
1425 | {"rdata", s_change_sec, 'r'}, | |
1426 | {"sdata", s_change_sec, 's'}, | |
1427 | {"livereg", s_ignore, 0}, | |
1428 | {"abicalls", s_abicalls, 0}, | |
1429 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1430 | {"cpsetup", s_cpsetup, 0}, |
1431 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1432 | {"cprestore", s_cprestore, 0}, |
6478892d | 1433 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1434 | {"dtprelword", s_dtprelword, 0}, |
1435 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1436 | {"tprelword", s_tprelword, 0}, |
1437 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1438 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1439 | {"gpword", s_gpword, 0}, |
10181a0d | 1440 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1441 | {"cpadd", s_cpadd, 0}, |
1442 | {"insn", s_insn, 0}, | |
1443 | ||
beae10d5 | 1444 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1445 | chips. */ |
38a57ae7 | 1446 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1447 | {"bss", s_change_sec, 'b'}, |
1448 | {"err", s_err, 0}, | |
1449 | {"half", s_cons, 1}, | |
1450 | {"dword", s_cons, 3}, | |
1451 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1452 | {"origin", s_org, 0}, |
1453 | {"repeat", s_rept, 0}, | |
252b5132 | 1454 | |
998b3c36 MR |
1455 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1456 | {"sbss", s_change_sec, 'B'}, | |
1457 | ||
beae10d5 | 1458 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1459 | here for one reason or another. */ |
1460 | {"align", s_align, 0}, | |
1461 | {"byte", s_cons, 0}, | |
1462 | {"data", s_change_sec, 'd'}, | |
1463 | {"double", s_float_cons, 'd'}, | |
1464 | {"float", s_float_cons, 'f'}, | |
1465 | {"globl", s_mips_globl, 0}, | |
1466 | {"global", s_mips_globl, 0}, | |
1467 | {"hword", s_cons, 1}, | |
1468 | {"int", s_cons, 2}, | |
1469 | {"long", s_cons, 2}, | |
1470 | {"octa", s_cons, 4}, | |
1471 | {"quad", s_cons, 3}, | |
cca86cc8 | 1472 | {"section", s_change_section, 0}, |
252b5132 RH |
1473 | {"short", s_cons, 1}, |
1474 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1475 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1476 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1477 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1478 | {"text", s_change_sec, 't'}, |
1479 | {"word", s_cons, 2}, | |
add56521 | 1480 | |
add56521 | 1481 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1482 | |
43841e91 | 1483 | { NULL, NULL, 0 }, |
252b5132 RH |
1484 | }; |
1485 | ||
e972090a NC |
1486 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1487 | { | |
beae10d5 KH |
1488 | /* These pseudo-ops should be defined by the object file format. |
1489 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1490 | {"aent", s_mips_ent, 1}, |
1491 | {"bgnb", s_ignore, 0}, | |
1492 | {"end", s_mips_end, 0}, | |
1493 | {"endb", s_ignore, 0}, | |
1494 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1495 | {"file", s_mips_file, 0}, |
252b5132 RH |
1496 | {"fmask", s_mips_mask, 'F'}, |
1497 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1498 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1499 | {"mask", s_mips_mask, 'R'}, |
1500 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1501 | { NULL, NULL, 0 }, |
252b5132 RH |
1502 | }; |
1503 | ||
3ae8dd8d MR |
1504 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1505 | purpose of the `.dc.a' internal pseudo-op. */ | |
1506 | ||
1507 | int | |
1508 | mips_address_bytes (void) | |
1509 | { | |
1510 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1511 | } | |
1512 | ||
17a2f251 | 1513 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1514 | |
1515 | void | |
17a2f251 | 1516 | mips_pop_insert (void) |
252b5132 RH |
1517 | { |
1518 | pop_insert (mips_pseudo_table); | |
1519 | if (! ECOFF_DEBUGGING) | |
1520 | pop_insert (mips_nonecoff_pseudo_table); | |
1521 | } | |
1522 | \f | |
1523 | /* Symbols labelling the current insn. */ | |
1524 | ||
e972090a NC |
1525 | struct insn_label_list |
1526 | { | |
252b5132 RH |
1527 | struct insn_label_list *next; |
1528 | symbolS *label; | |
1529 | }; | |
1530 | ||
252b5132 | 1531 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1532 | #define label_list tc_segment_info_data.labels |
252b5132 | 1533 | |
17a2f251 | 1534 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1535 | static void mips_mark_labels (void); |
1536 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1537 | |
1538 | static inline void | |
17a2f251 | 1539 | mips_clear_insn_labels (void) |
252b5132 RH |
1540 | { |
1541 | register struct insn_label_list **pl; | |
a8dbcb85 | 1542 | segment_info_type *si; |
252b5132 | 1543 | |
a8dbcb85 TS |
1544 | if (now_seg) |
1545 | { | |
1546 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1547 | ; | |
1548 | ||
1549 | si = seg_info (now_seg); | |
1550 | *pl = si->label_list; | |
1551 | si->label_list = NULL; | |
1552 | } | |
252b5132 | 1553 | } |
a8dbcb85 | 1554 | |
df58fc94 RS |
1555 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1556 | ||
1557 | static inline void | |
1558 | mips_mark_labels (void) | |
1559 | { | |
1560 | if (HAVE_CODE_COMPRESSION) | |
1561 | mips_compressed_mark_labels (); | |
1562 | } | |
252b5132 RH |
1563 | \f |
1564 | static char *expr_end; | |
1565 | ||
1566 | /* Expressions which appear in instructions. These are set by | |
1567 | mips_ip. */ | |
1568 | ||
1569 | static expressionS imm_expr; | |
5f74bc13 | 1570 | static expressionS imm2_expr; |
252b5132 RH |
1571 | static expressionS offset_expr; |
1572 | ||
1573 | /* Relocs associated with imm_expr and offset_expr. */ | |
1574 | ||
f6688943 TS |
1575 | static bfd_reloc_code_real_type imm_reloc[3] |
1576 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1577 | static bfd_reloc_code_real_type offset_reloc[3] | |
1578 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1579 | |
df58fc94 RS |
1580 | /* This is set to the resulting size of the instruction to be produced |
1581 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1582 | explicit size is supplied. */ | |
252b5132 | 1583 | |
df58fc94 | 1584 | static unsigned int forced_insn_length; |
252b5132 | 1585 | |
e1b47bd5 RS |
1586 | /* True if we are assembling an instruction. All dot symbols defined during |
1587 | this time should be treated as code labels. */ | |
1588 | ||
1589 | static bfd_boolean mips_assembling_insn; | |
1590 | ||
7ed4a06a | 1591 | #ifdef OBJ_ELF |
ecb4347a DJ |
1592 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1593 | ECOFF debugging. */ | |
252b5132 RH |
1594 | |
1595 | static segT pdr_seg; | |
7ed4a06a | 1596 | #endif |
252b5132 | 1597 | |
e013f690 TS |
1598 | /* The default target format to use. */ |
1599 | ||
aeffff67 RS |
1600 | #if defined (TE_FreeBSD) |
1601 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1602 | #elif defined (TE_TMIPS) | |
1603 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1604 | #else | |
1605 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1606 | #endif | |
1607 | ||
e013f690 | 1608 | const char * |
17a2f251 | 1609 | mips_target_format (void) |
e013f690 TS |
1610 | { |
1611 | switch (OUTPUT_FLAVOR) | |
1612 | { | |
e013f690 TS |
1613 | case bfd_target_ecoff_flavour: |
1614 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1615 | case bfd_target_coff_flavour: | |
1616 | return "pe-mips"; | |
1617 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1618 | #ifdef TE_VXWORKS |
1619 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1620 | return (target_big_endian | |
1621 | ? "elf32-bigmips-vxworks" | |
1622 | : "elf32-littlemips-vxworks"); | |
1623 | #endif | |
e013f690 | 1624 | return (target_big_endian |
cfe86eaa | 1625 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1626 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1627 | : (HAVE_NEWABI |
aeffff67 RS |
1628 | ? ELF_TARGET ("elf32-n", "big") |
1629 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1630 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1631 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1632 | : (HAVE_NEWABI |
aeffff67 RS |
1633 | ? ELF_TARGET ("elf32-n", "little") |
1634 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1635 | default: |
1636 | abort (); | |
1637 | return NULL; | |
1638 | } | |
1639 | } | |
1640 | ||
df58fc94 RS |
1641 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1642 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1643 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1644 | major opcode) will require further modifications to the opcode | |
1645 | table. */ | |
1646 | ||
1647 | static inline unsigned int | |
1648 | micromips_insn_length (const struct mips_opcode *mo) | |
1649 | { | |
1650 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1651 | } | |
1652 | ||
5c04167a RS |
1653 | /* Return the length of MIPS16 instruction OPCODE. */ |
1654 | ||
1655 | static inline unsigned int | |
1656 | mips16_opcode_length (unsigned long opcode) | |
1657 | { | |
1658 | return (opcode >> 16) == 0 ? 2 : 4; | |
1659 | } | |
1660 | ||
1e915849 RS |
1661 | /* Return the length of instruction INSN. */ |
1662 | ||
1663 | static inline unsigned int | |
1664 | insn_length (const struct mips_cl_insn *insn) | |
1665 | { | |
df58fc94 RS |
1666 | if (mips_opts.micromips) |
1667 | return micromips_insn_length (insn->insn_mo); | |
1668 | else if (mips_opts.mips16) | |
5c04167a | 1669 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1670 | else |
1e915849 | 1671 | return 4; |
1e915849 RS |
1672 | } |
1673 | ||
1674 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1675 | ||
1676 | static void | |
1677 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1678 | { | |
1679 | size_t i; | |
1680 | ||
1681 | insn->insn_mo = mo; | |
1e915849 RS |
1682 | insn->insn_opcode = mo->match; |
1683 | insn->frag = NULL; | |
1684 | insn->where = 0; | |
1685 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1686 | insn->fixp[i] = NULL; | |
1687 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1688 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1689 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1690 | insn->complete_p = 0; |
e407c74b | 1691 | insn->cleared_p = 0; |
1e915849 RS |
1692 | } |
1693 | ||
df58fc94 | 1694 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1695 | |
1696 | static void | |
df58fc94 | 1697 | mips_record_compressed_mode (void) |
742a56fe RS |
1698 | { |
1699 | segment_info_type *si; | |
1700 | ||
1701 | si = seg_info (now_seg); | |
1702 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1703 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1704 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1705 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1706 | } |
1707 | ||
4d68580a RS |
1708 | /* Read a standard MIPS instruction from BUF. */ |
1709 | ||
1710 | static unsigned long | |
1711 | read_insn (char *buf) | |
1712 | { | |
1713 | if (target_big_endian) | |
1714 | return bfd_getb32 ((bfd_byte *) buf); | |
1715 | else | |
1716 | return bfd_getl32 ((bfd_byte *) buf); | |
1717 | } | |
1718 | ||
1719 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1720 | the next byte. */ | |
1721 | ||
1722 | static char * | |
1723 | write_insn (char *buf, unsigned int insn) | |
1724 | { | |
1725 | md_number_to_chars (buf, insn, 4); | |
1726 | return buf + 4; | |
1727 | } | |
1728 | ||
1729 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1730 | has length LENGTH. */ | |
1731 | ||
1732 | static unsigned long | |
1733 | read_compressed_insn (char *buf, unsigned int length) | |
1734 | { | |
1735 | unsigned long insn; | |
1736 | unsigned int i; | |
1737 | ||
1738 | insn = 0; | |
1739 | for (i = 0; i < length; i += 2) | |
1740 | { | |
1741 | insn <<= 16; | |
1742 | if (target_big_endian) | |
1743 | insn |= bfd_getb16 ((char *) buf); | |
1744 | else | |
1745 | insn |= bfd_getl16 ((char *) buf); | |
1746 | buf += 2; | |
1747 | } | |
1748 | return insn; | |
1749 | } | |
1750 | ||
5c04167a RS |
1751 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1752 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1753 | ||
1754 | static char * | |
1755 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1756 | { | |
1757 | unsigned int i; | |
1758 | ||
1759 | for (i = 0; i < length; i += 2) | |
1760 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1761 | return buf + length; | |
1762 | } | |
1763 | ||
1e915849 RS |
1764 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1765 | ||
1766 | static void | |
1767 | install_insn (const struct mips_cl_insn *insn) | |
1768 | { | |
1769 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1770 | if (HAVE_CODE_COMPRESSION) |
1771 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1772 | else |
4d68580a | 1773 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1774 | mips_record_compressed_mode (); |
1e915849 RS |
1775 | } |
1776 | ||
1777 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1778 | and install the opcode in the new location. */ | |
1779 | ||
1780 | static void | |
1781 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1782 | { | |
1783 | size_t i; | |
1784 | ||
1785 | insn->frag = frag; | |
1786 | insn->where = where; | |
1787 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1788 | if (insn->fixp[i] != NULL) | |
1789 | { | |
1790 | insn->fixp[i]->fx_frag = frag; | |
1791 | insn->fixp[i]->fx_where = where; | |
1792 | } | |
1793 | install_insn (insn); | |
1794 | } | |
1795 | ||
1796 | /* Add INSN to the end of the output. */ | |
1797 | ||
1798 | static void | |
1799 | add_fixed_insn (struct mips_cl_insn *insn) | |
1800 | { | |
1801 | char *f = frag_more (insn_length (insn)); | |
1802 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1803 | } | |
1804 | ||
1805 | /* Start a variant frag and move INSN to the start of the variant part, | |
1806 | marking it as fixed. The other arguments are as for frag_var. */ | |
1807 | ||
1808 | static void | |
1809 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1810 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1811 | { | |
1812 | frag_grow (max_chars); | |
1813 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1814 | insn->fixed_p = 1; | |
1815 | frag_var (rs_machine_dependent, max_chars, var, | |
1816 | subtype, symbol, offset, NULL); | |
1817 | } | |
1818 | ||
1819 | /* Insert N copies of INSN into the history buffer, starting at | |
1820 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1821 | ||
1822 | static void | |
1823 | insert_into_history (unsigned int first, unsigned int n, | |
1824 | const struct mips_cl_insn *insn) | |
1825 | { | |
1826 | if (mips_relax.sequence != 2) | |
1827 | { | |
1828 | unsigned int i; | |
1829 | ||
1830 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1831 | if (i >= first + n) | |
1832 | history[i] = history[i - n]; | |
1833 | else | |
1834 | history[i] = *insn; | |
1835 | } | |
1836 | } | |
1837 | ||
71400594 RS |
1838 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1839 | the idea is to make it obvious at a glance that each errata is | |
1840 | included. */ | |
1841 | ||
1842 | static void | |
1843 | init_vr4120_conflicts (void) | |
1844 | { | |
1845 | #define CONFLICT(FIRST, SECOND) \ | |
1846 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1847 | ||
1848 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1849 | CONFLICT (MACC, DIV); | |
1850 | CONFLICT (DMACC, DIV); | |
1851 | ||
1852 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1853 | CONFLICT (DMULT, DMULT); | |
1854 | CONFLICT (DMULT, DMACC); | |
1855 | CONFLICT (DMACC, DMULT); | |
1856 | CONFLICT (DMACC, DMACC); | |
1857 | ||
1858 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1859 | CONFLICT (MACC, MTHILO); | |
1860 | CONFLICT (DMACC, MTHILO); | |
1861 | ||
1862 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1863 | instruction is executed immediately after a MACC or DMACC | |
1864 | instruction, the result of [either instruction] is incorrect." */ | |
1865 | CONFLICT (MACC, MULT); | |
1866 | CONFLICT (MACC, DMULT); | |
1867 | CONFLICT (DMACC, MULT); | |
1868 | CONFLICT (DMACC, DMULT); | |
1869 | ||
1870 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1871 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1872 | DDIV or DDIVU instruction, the result of the MACC or | |
1873 | DMACC instruction is incorrect.". */ | |
1874 | CONFLICT (DMULT, MACC); | |
1875 | CONFLICT (DMULT, DMACC); | |
1876 | CONFLICT (DIV, MACC); | |
1877 | CONFLICT (DIV, DMACC); | |
1878 | ||
1879 | #undef CONFLICT | |
1880 | } | |
1881 | ||
707bfff6 TS |
1882 | struct regname { |
1883 | const char *name; | |
1884 | unsigned int num; | |
1885 | }; | |
1886 | ||
1887 | #define RTYPE_MASK 0x1ff00 | |
1888 | #define RTYPE_NUM 0x00100 | |
1889 | #define RTYPE_FPU 0x00200 | |
1890 | #define RTYPE_FCC 0x00400 | |
1891 | #define RTYPE_VEC 0x00800 | |
1892 | #define RTYPE_GP 0x01000 | |
1893 | #define RTYPE_CP0 0x02000 | |
1894 | #define RTYPE_PC 0x04000 | |
1895 | #define RTYPE_ACC 0x08000 | |
1896 | #define RTYPE_CCC 0x10000 | |
1897 | #define RNUM_MASK 0x000ff | |
1898 | #define RWARN 0x80000 | |
1899 | ||
1900 | #define GENERIC_REGISTER_NUMBERS \ | |
1901 | {"$0", RTYPE_NUM | 0}, \ | |
1902 | {"$1", RTYPE_NUM | 1}, \ | |
1903 | {"$2", RTYPE_NUM | 2}, \ | |
1904 | {"$3", RTYPE_NUM | 3}, \ | |
1905 | {"$4", RTYPE_NUM | 4}, \ | |
1906 | {"$5", RTYPE_NUM | 5}, \ | |
1907 | {"$6", RTYPE_NUM | 6}, \ | |
1908 | {"$7", RTYPE_NUM | 7}, \ | |
1909 | {"$8", RTYPE_NUM | 8}, \ | |
1910 | {"$9", RTYPE_NUM | 9}, \ | |
1911 | {"$10", RTYPE_NUM | 10}, \ | |
1912 | {"$11", RTYPE_NUM | 11}, \ | |
1913 | {"$12", RTYPE_NUM | 12}, \ | |
1914 | {"$13", RTYPE_NUM | 13}, \ | |
1915 | {"$14", RTYPE_NUM | 14}, \ | |
1916 | {"$15", RTYPE_NUM | 15}, \ | |
1917 | {"$16", RTYPE_NUM | 16}, \ | |
1918 | {"$17", RTYPE_NUM | 17}, \ | |
1919 | {"$18", RTYPE_NUM | 18}, \ | |
1920 | {"$19", RTYPE_NUM | 19}, \ | |
1921 | {"$20", RTYPE_NUM | 20}, \ | |
1922 | {"$21", RTYPE_NUM | 21}, \ | |
1923 | {"$22", RTYPE_NUM | 22}, \ | |
1924 | {"$23", RTYPE_NUM | 23}, \ | |
1925 | {"$24", RTYPE_NUM | 24}, \ | |
1926 | {"$25", RTYPE_NUM | 25}, \ | |
1927 | {"$26", RTYPE_NUM | 26}, \ | |
1928 | {"$27", RTYPE_NUM | 27}, \ | |
1929 | {"$28", RTYPE_NUM | 28}, \ | |
1930 | {"$29", RTYPE_NUM | 29}, \ | |
1931 | {"$30", RTYPE_NUM | 30}, \ | |
1932 | {"$31", RTYPE_NUM | 31} | |
1933 | ||
1934 | #define FPU_REGISTER_NAMES \ | |
1935 | {"$f0", RTYPE_FPU | 0}, \ | |
1936 | {"$f1", RTYPE_FPU | 1}, \ | |
1937 | {"$f2", RTYPE_FPU | 2}, \ | |
1938 | {"$f3", RTYPE_FPU | 3}, \ | |
1939 | {"$f4", RTYPE_FPU | 4}, \ | |
1940 | {"$f5", RTYPE_FPU | 5}, \ | |
1941 | {"$f6", RTYPE_FPU | 6}, \ | |
1942 | {"$f7", RTYPE_FPU | 7}, \ | |
1943 | {"$f8", RTYPE_FPU | 8}, \ | |
1944 | {"$f9", RTYPE_FPU | 9}, \ | |
1945 | {"$f10", RTYPE_FPU | 10}, \ | |
1946 | {"$f11", RTYPE_FPU | 11}, \ | |
1947 | {"$f12", RTYPE_FPU | 12}, \ | |
1948 | {"$f13", RTYPE_FPU | 13}, \ | |
1949 | {"$f14", RTYPE_FPU | 14}, \ | |
1950 | {"$f15", RTYPE_FPU | 15}, \ | |
1951 | {"$f16", RTYPE_FPU | 16}, \ | |
1952 | {"$f17", RTYPE_FPU | 17}, \ | |
1953 | {"$f18", RTYPE_FPU | 18}, \ | |
1954 | {"$f19", RTYPE_FPU | 19}, \ | |
1955 | {"$f20", RTYPE_FPU | 20}, \ | |
1956 | {"$f21", RTYPE_FPU | 21}, \ | |
1957 | {"$f22", RTYPE_FPU | 22}, \ | |
1958 | {"$f23", RTYPE_FPU | 23}, \ | |
1959 | {"$f24", RTYPE_FPU | 24}, \ | |
1960 | {"$f25", RTYPE_FPU | 25}, \ | |
1961 | {"$f26", RTYPE_FPU | 26}, \ | |
1962 | {"$f27", RTYPE_FPU | 27}, \ | |
1963 | {"$f28", RTYPE_FPU | 28}, \ | |
1964 | {"$f29", RTYPE_FPU | 29}, \ | |
1965 | {"$f30", RTYPE_FPU | 30}, \ | |
1966 | {"$f31", RTYPE_FPU | 31} | |
1967 | ||
1968 | #define FPU_CONDITION_CODE_NAMES \ | |
1969 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1970 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1971 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1972 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1973 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1974 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1975 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1976 | {"$fcc7", RTYPE_FCC | 7} | |
1977 | ||
1978 | #define COPROC_CONDITION_CODE_NAMES \ | |
1979 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1980 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1981 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1982 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1983 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1984 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1985 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1986 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1987 | ||
1988 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1989 | {"$a4", RTYPE_GP | 8}, \ | |
1990 | {"$a5", RTYPE_GP | 9}, \ | |
1991 | {"$a6", RTYPE_GP | 10}, \ | |
1992 | {"$a7", RTYPE_GP | 11}, \ | |
1993 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1994 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1995 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1996 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1997 | {"$t0", RTYPE_GP | 12}, \ | |
1998 | {"$t1", RTYPE_GP | 13}, \ | |
1999 | {"$t2", RTYPE_GP | 14}, \ | |
2000 | {"$t3", RTYPE_GP | 15} | |
2001 | ||
2002 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2003 | {"$t0", RTYPE_GP | 8}, \ | |
2004 | {"$t1", RTYPE_GP | 9}, \ | |
2005 | {"$t2", RTYPE_GP | 10}, \ | |
2006 | {"$t3", RTYPE_GP | 11}, \ | |
2007 | {"$t4", RTYPE_GP | 12}, \ | |
2008 | {"$t5", RTYPE_GP | 13}, \ | |
2009 | {"$t6", RTYPE_GP | 14}, \ | |
2010 | {"$t7", RTYPE_GP | 15}, \ | |
2011 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2012 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2013 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2014 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2015 | ||
2016 | /* Remaining symbolic register names */ | |
2017 | #define SYMBOLIC_REGISTER_NAMES \ | |
2018 | {"$zero", RTYPE_GP | 0}, \ | |
2019 | {"$at", RTYPE_GP | 1}, \ | |
2020 | {"$AT", RTYPE_GP | 1}, \ | |
2021 | {"$v0", RTYPE_GP | 2}, \ | |
2022 | {"$v1", RTYPE_GP | 3}, \ | |
2023 | {"$a0", RTYPE_GP | 4}, \ | |
2024 | {"$a1", RTYPE_GP | 5}, \ | |
2025 | {"$a2", RTYPE_GP | 6}, \ | |
2026 | {"$a3", RTYPE_GP | 7}, \ | |
2027 | {"$s0", RTYPE_GP | 16}, \ | |
2028 | {"$s1", RTYPE_GP | 17}, \ | |
2029 | {"$s2", RTYPE_GP | 18}, \ | |
2030 | {"$s3", RTYPE_GP | 19}, \ | |
2031 | {"$s4", RTYPE_GP | 20}, \ | |
2032 | {"$s5", RTYPE_GP | 21}, \ | |
2033 | {"$s6", RTYPE_GP | 22}, \ | |
2034 | {"$s7", RTYPE_GP | 23}, \ | |
2035 | {"$t8", RTYPE_GP | 24}, \ | |
2036 | {"$t9", RTYPE_GP | 25}, \ | |
2037 | {"$k0", RTYPE_GP | 26}, \ | |
2038 | {"$kt0", RTYPE_GP | 26}, \ | |
2039 | {"$k1", RTYPE_GP | 27}, \ | |
2040 | {"$kt1", RTYPE_GP | 27}, \ | |
2041 | {"$gp", RTYPE_GP | 28}, \ | |
2042 | {"$sp", RTYPE_GP | 29}, \ | |
2043 | {"$s8", RTYPE_GP | 30}, \ | |
2044 | {"$fp", RTYPE_GP | 30}, \ | |
2045 | {"$ra", RTYPE_GP | 31} | |
2046 | ||
2047 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2048 | {"$pc", RTYPE_PC | 0} | |
2049 | ||
2050 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2051 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2052 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2053 | {"$v2", RTYPE_VEC | 2}, \ | |
2054 | {"$v3", RTYPE_VEC | 3}, \ | |
2055 | {"$v4", RTYPE_VEC | 4}, \ | |
2056 | {"$v5", RTYPE_VEC | 5}, \ | |
2057 | {"$v6", RTYPE_VEC | 6}, \ | |
2058 | {"$v7", RTYPE_VEC | 7}, \ | |
2059 | {"$v8", RTYPE_VEC | 8}, \ | |
2060 | {"$v9", RTYPE_VEC | 9}, \ | |
2061 | {"$v10", RTYPE_VEC | 10}, \ | |
2062 | {"$v11", RTYPE_VEC | 11}, \ | |
2063 | {"$v12", RTYPE_VEC | 12}, \ | |
2064 | {"$v13", RTYPE_VEC | 13}, \ | |
2065 | {"$v14", RTYPE_VEC | 14}, \ | |
2066 | {"$v15", RTYPE_VEC | 15}, \ | |
2067 | {"$v16", RTYPE_VEC | 16}, \ | |
2068 | {"$v17", RTYPE_VEC | 17}, \ | |
2069 | {"$v18", RTYPE_VEC | 18}, \ | |
2070 | {"$v19", RTYPE_VEC | 19}, \ | |
2071 | {"$v20", RTYPE_VEC | 20}, \ | |
2072 | {"$v21", RTYPE_VEC | 21}, \ | |
2073 | {"$v22", RTYPE_VEC | 22}, \ | |
2074 | {"$v23", RTYPE_VEC | 23}, \ | |
2075 | {"$v24", RTYPE_VEC | 24}, \ | |
2076 | {"$v25", RTYPE_VEC | 25}, \ | |
2077 | {"$v26", RTYPE_VEC | 26}, \ | |
2078 | {"$v27", RTYPE_VEC | 27}, \ | |
2079 | {"$v28", RTYPE_VEC | 28}, \ | |
2080 | {"$v29", RTYPE_VEC | 29}, \ | |
2081 | {"$v30", RTYPE_VEC | 30}, \ | |
2082 | {"$v31", RTYPE_VEC | 31} | |
2083 | ||
2084 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2085 | {"$ac0", RTYPE_ACC | 0}, \ | |
2086 | {"$ac1", RTYPE_ACC | 1}, \ | |
2087 | {"$ac2", RTYPE_ACC | 2}, \ | |
2088 | {"$ac3", RTYPE_ACC | 3} | |
2089 | ||
2090 | static const struct regname reg_names[] = { | |
2091 | GENERIC_REGISTER_NUMBERS, | |
2092 | FPU_REGISTER_NAMES, | |
2093 | FPU_CONDITION_CODE_NAMES, | |
2094 | COPROC_CONDITION_CODE_NAMES, | |
2095 | ||
2096 | /* The $txx registers depends on the abi, | |
2097 | these will be added later into the symbol table from | |
2098 | one of the tables below once mips_abi is set after | |
2099 | parsing of arguments from the command line. */ | |
2100 | SYMBOLIC_REGISTER_NAMES, | |
2101 | ||
2102 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2103 | MDMX_VECTOR_REGISTER_NAMES, | |
2104 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2105 | {0, 0} | |
2106 | }; | |
2107 | ||
2108 | static const struct regname reg_names_o32[] = { | |
2109 | O32_SYMBOLIC_REGISTER_NAMES, | |
2110 | {0, 0} | |
2111 | }; | |
2112 | ||
2113 | static const struct regname reg_names_n32n64[] = { | |
2114 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2115 | {0, 0} | |
2116 | }; | |
2117 | ||
df58fc94 RS |
2118 | /* Check if S points at a valid register specifier according to TYPES. |
2119 | If so, then return 1, advance S to consume the specifier and store | |
2120 | the register's number in REGNOP, otherwise return 0. */ | |
2121 | ||
707bfff6 TS |
2122 | static int |
2123 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2124 | { | |
2125 | symbolS *symbolP; | |
2126 | char *e; | |
2127 | char save_c; | |
2128 | int reg = -1; | |
2129 | ||
2130 | /* Find end of name. */ | |
2131 | e = *s; | |
2132 | if (is_name_beginner (*e)) | |
2133 | ++e; | |
2134 | while (is_part_of_name (*e)) | |
2135 | ++e; | |
2136 | ||
2137 | /* Terminate name. */ | |
2138 | save_c = *e; | |
2139 | *e = '\0'; | |
2140 | ||
2141 | /* Look for a register symbol. */ | |
2142 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2143 | { | |
2144 | int r = S_GET_VALUE (symbolP); | |
2145 | if (r & types) | |
2146 | reg = r & RNUM_MASK; | |
2147 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2148 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2149 | reg = (r & RNUM_MASK) - 2; | |
2150 | } | |
2151 | /* Else see if this is a register defined in an itbl entry. */ | |
2152 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2153 | { | |
2154 | char *n = *s; | |
2155 | unsigned long r; | |
2156 | ||
2157 | if (*n == '$') | |
2158 | ++n; | |
2159 | if (itbl_get_reg_val (n, &r)) | |
2160 | reg = r & RNUM_MASK; | |
2161 | } | |
2162 | ||
2163 | /* Advance to next token if a register was recognised. */ | |
2164 | if (reg >= 0) | |
2165 | *s = e; | |
2166 | else if (types & RWARN) | |
20203fb9 | 2167 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2168 | |
2169 | *e = save_c; | |
2170 | if (regnop) | |
2171 | *regnop = reg; | |
2172 | return reg >= 0; | |
2173 | } | |
2174 | ||
df58fc94 RS |
2175 | /* Check if S points at a valid register list according to TYPES. |
2176 | If so, then return 1, advance S to consume the list and store | |
2177 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2178 | otherwise return 0. A valid list comprises a comma-separated | |
2179 | enumeration of valid single registers and/or dash-separated | |
2180 | contiguous register ranges as determined by their numbers. | |
2181 | ||
2182 | As a special exception if one of s0-s7 registers is specified as | |
2183 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2184 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2185 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2186 | |
2187 | static int | |
2188 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2189 | { | |
2190 | unsigned int reglist = 0; | |
2191 | unsigned int lastregno; | |
2192 | bfd_boolean ok = TRUE; | |
2193 | unsigned int regmask; | |
2309ddf2 | 2194 | char *s_endlist = *s; |
df58fc94 | 2195 | char *s_reset = *s; |
2309ddf2 | 2196 | unsigned int regno; |
df58fc94 RS |
2197 | |
2198 | while (reg_lookup (s, types, ®no)) | |
2199 | { | |
2200 | lastregno = regno; | |
2201 | if (**s == '-') | |
2202 | { | |
2203 | (*s)++; | |
2204 | ok = reg_lookup (s, types, &lastregno); | |
2205 | if (ok && lastregno < regno) | |
2206 | ok = FALSE; | |
2207 | if (!ok) | |
2208 | break; | |
2209 | } | |
2210 | ||
2211 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2212 | { | |
2213 | lastregno = S7; | |
2214 | reglist |= 1 << FP; | |
2215 | } | |
2216 | regmask = 1 << lastregno; | |
2217 | regmask = (regmask << 1) - 1; | |
2218 | regmask ^= (1 << regno) - 1; | |
2219 | reglist |= regmask; | |
2220 | ||
2309ddf2 | 2221 | s_endlist = *s; |
df58fc94 RS |
2222 | if (**s != ',') |
2223 | break; | |
2224 | (*s)++; | |
2225 | } | |
2226 | ||
2227 | if (ok) | |
2309ddf2 | 2228 | *s = s_endlist; |
df58fc94 RS |
2229 | else |
2230 | *s = s_reset; | |
2231 | if (reglistp) | |
2232 | *reglistp = reglist; | |
2233 | return ok && reglist != 0; | |
2234 | } | |
2235 | ||
037b32b9 | 2236 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2237 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2238 | |
2239 | static bfd_boolean | |
f79e2745 | 2240 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2241 | { |
2242 | int isa = mips_opts.isa; | |
2243 | int fp_s, fp_d; | |
2244 | ||
2245 | if (mips_opts.ase_mdmx) | |
2246 | isa |= INSN_MDMX; | |
2247 | if (mips_opts.ase_dsp) | |
2248 | isa |= INSN_DSP; | |
2249 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2250 | isa |= INSN_DSP64; | |
2251 | if (mips_opts.ase_dspr2) | |
2252 | isa |= INSN_DSPR2; | |
2253 | if (mips_opts.ase_mt) | |
2254 | isa |= INSN_MT; | |
2255 | if (mips_opts.ase_mips3d) | |
2256 | isa |= INSN_MIPS3D; | |
2257 | if (mips_opts.ase_smartmips) | |
2258 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2259 | if (mips_opts.ase_mcu) |
2260 | isa |= INSN_MCU; | |
037b32b9 | 2261 | |
35d0a169 | 2262 | if (!opcode_is_member (mo, isa, mips_opts.arch)) |
037b32b9 AN |
2263 | return FALSE; |
2264 | ||
2265 | /* Check whether the instruction or macro requires single-precision or | |
2266 | double-precision floating-point support. Note that this information is | |
2267 | stored differently in the opcode table for insns and macros. */ | |
2268 | if (mo->pinfo == INSN_MACRO) | |
2269 | { | |
2270 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2271 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2272 | } | |
2273 | else | |
2274 | { | |
2275 | fp_s = mo->pinfo & FP_S; | |
2276 | fp_d = mo->pinfo & FP_D; | |
2277 | } | |
2278 | ||
2279 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2280 | return FALSE; | |
2281 | ||
2282 | if (fp_s && mips_opts.soft_float) | |
2283 | return FALSE; | |
2284 | ||
2285 | return TRUE; | |
2286 | } | |
2287 | ||
2288 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2289 | selected ISA and architecture. */ | |
2290 | ||
2291 | static bfd_boolean | |
2292 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2293 | { | |
35d0a169 | 2294 | return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); |
037b32b9 AN |
2295 | } |
2296 | ||
df58fc94 RS |
2297 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2298 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2299 | ||
2300 | static bfd_boolean | |
2301 | is_size_valid (const struct mips_opcode *mo) | |
2302 | { | |
2303 | if (!mips_opts.micromips) | |
2304 | return TRUE; | |
2305 | ||
2306 | if (!forced_insn_length) | |
2307 | return TRUE; | |
2308 | if (mo->pinfo == INSN_MACRO) | |
2309 | return FALSE; | |
2310 | return forced_insn_length == micromips_insn_length (mo); | |
2311 | } | |
2312 | ||
2313 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2314 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2315 | ||
2316 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2317 | a macro expansion fails because it relies on a preceding 32-bit real | |
2318 | instruction to have matched and does not handle the operands correctly. | |
2319 | The only macros that may expand to 16-bit instructions are JAL that | |
2320 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2321 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2322 | a NOP. In all these cases the macros precede any corresponding real | |
2323 | instruction definitions in the opcode table, so they will match in the | |
2324 | second pass where the size of the delay slot is ignored and therefore | |
2325 | produce correct code. */ | |
df58fc94 RS |
2326 | |
2327 | static bfd_boolean | |
2328 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2329 | { | |
2330 | if (!mips_opts.micromips) | |
2331 | return TRUE; | |
2332 | ||
2333 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2334 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2335 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2336 | && micromips_insn_length (mo) != 4) | |
2337 | return FALSE; | |
2338 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2339 | && micromips_insn_length (mo) != 2) | |
2340 | return FALSE; | |
2341 | ||
2342 | return TRUE; | |
2343 | } | |
2344 | ||
707bfff6 TS |
2345 | /* This function is called once, at assembler startup time. It should set up |
2346 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2347 | |
252b5132 | 2348 | void |
17a2f251 | 2349 | md_begin (void) |
252b5132 | 2350 | { |
3994f87e | 2351 | const char *retval = NULL; |
156c2f8b | 2352 | int i = 0; |
252b5132 | 2353 | int broken = 0; |
1f25f5d3 | 2354 | |
0a44bf69 RS |
2355 | if (mips_pic != NO_PIC) |
2356 | { | |
2357 | if (g_switch_seen && g_switch_value != 0) | |
2358 | as_bad (_("-G may not be used in position-independent code")); | |
2359 | g_switch_value = 0; | |
2360 | } | |
2361 | ||
fef14a42 | 2362 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2363 | as_warn (_("Could not set architecture and machine")); |
2364 | ||
252b5132 RH |
2365 | op_hash = hash_new (); |
2366 | ||
2367 | for (i = 0; i < NUMOPCODES;) | |
2368 | { | |
2369 | const char *name = mips_opcodes[i].name; | |
2370 | ||
17a2f251 | 2371 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2372 | if (retval != NULL) |
2373 | { | |
2374 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2375 | mips_opcodes[i].name, retval); | |
2376 | /* Probably a memory allocation problem? Give up now. */ | |
2377 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2378 | } | |
2379 | do | |
2380 | { | |
2381 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2382 | { | |
2383 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2384 | broken = 1; | |
1e915849 RS |
2385 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2386 | { | |
2387 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2388 | if (mips_fix_loongson2f_nop) |
2389 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2390 | nop_insn.fixed_p = 1; |
2391 | } | |
252b5132 RH |
2392 | } |
2393 | ++i; | |
2394 | } | |
2395 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2396 | } | |
2397 | ||
2398 | mips16_op_hash = hash_new (); | |
2399 | ||
2400 | i = 0; | |
2401 | while (i < bfd_mips16_num_opcodes) | |
2402 | { | |
2403 | const char *name = mips16_opcodes[i].name; | |
2404 | ||
17a2f251 | 2405 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2406 | if (retval != NULL) |
2407 | as_fatal (_("internal: can't hash `%s': %s"), | |
2408 | mips16_opcodes[i].name, retval); | |
2409 | do | |
2410 | { | |
2411 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2412 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2413 | != mips16_opcodes[i].match)) | |
2414 | { | |
2415 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2416 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2417 | broken = 1; | |
2418 | } | |
1e915849 RS |
2419 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2420 | { | |
2421 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2422 | mips16_nop_insn.fixed_p = 1; | |
2423 | } | |
252b5132 RH |
2424 | ++i; |
2425 | } | |
2426 | while (i < bfd_mips16_num_opcodes | |
2427 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2428 | } | |
2429 | ||
df58fc94 RS |
2430 | micromips_op_hash = hash_new (); |
2431 | ||
2432 | i = 0; | |
2433 | while (i < bfd_micromips_num_opcodes) | |
2434 | { | |
2435 | const char *name = micromips_opcodes[i].name; | |
2436 | ||
2437 | retval = hash_insert (micromips_op_hash, name, | |
2438 | (void *) µmips_opcodes[i]); | |
2439 | if (retval != NULL) | |
2440 | as_fatal (_("internal: can't hash `%s': %s"), | |
2441 | micromips_opcodes[i].name, retval); | |
2442 | do | |
2443 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2444 | { | |
2445 | struct mips_cl_insn *micromips_nop_insn; | |
2446 | ||
2447 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2448 | broken = 1; | |
2449 | ||
2450 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2451 | micromips_nop_insn = µmips_nop16_insn; | |
2452 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2453 | micromips_nop_insn = µmips_nop32_insn; | |
2454 | else | |
2455 | continue; | |
2456 | ||
2457 | if (micromips_nop_insn->insn_mo == NULL | |
2458 | && strcmp (name, "nop") == 0) | |
2459 | { | |
2460 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2461 | micromips_nop_insn->fixed_p = 1; | |
2462 | } | |
2463 | } | |
2464 | while (++i < bfd_micromips_num_opcodes | |
2465 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2466 | } | |
2467 | ||
252b5132 RH |
2468 | if (broken) |
2469 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2470 | ||
2471 | /* We add all the general register names to the symbol table. This | |
2472 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2473 | for (i = 0; reg_names[i].name; i++) |
2474 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2475 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2476 | &zero_address_frag)); |
2477 | if (HAVE_NEWABI) | |
2478 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2479 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2480 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2481 | &zero_address_frag)); |
707bfff6 TS |
2482 | else |
2483 | for (i = 0; reg_names_o32[i].name; i++) | |
2484 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2485 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2486 | &zero_address_frag)); |
6047c971 | 2487 | |
7d10b47d | 2488 | mips_no_prev_insn (); |
252b5132 RH |
2489 | |
2490 | mips_gprmask = 0; | |
2491 | mips_cprmask[0] = 0; | |
2492 | mips_cprmask[1] = 0; | |
2493 | mips_cprmask[2] = 0; | |
2494 | mips_cprmask[3] = 0; | |
2495 | ||
2496 | /* set the default alignment for the text section (2**2) */ | |
2497 | record_alignment (text_section, 2); | |
2498 | ||
4d0d148d | 2499 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2500 | |
707bfff6 | 2501 | #ifdef OBJ_ELF |
f43abd2b | 2502 | if (IS_ELF) |
252b5132 | 2503 | { |
0a44bf69 RS |
2504 | /* On a native system other than VxWorks, sections must be aligned |
2505 | to 16 byte boundaries. When configured for an embedded ELF | |
2506 | target, we don't bother. */ | |
c41e87e3 CF |
2507 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2508 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2509 | { |
2510 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2511 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2512 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2513 | } | |
2514 | ||
2515 | /* Create a .reginfo section for register masks and a .mdebug | |
2516 | section for debugging information. */ | |
2517 | { | |
2518 | segT seg; | |
2519 | subsegT subseg; | |
2520 | flagword flags; | |
2521 | segT sec; | |
2522 | ||
2523 | seg = now_seg; | |
2524 | subseg = now_subseg; | |
2525 | ||
2526 | /* The ABI says this section should be loaded so that the | |
2527 | running program can access it. However, we don't load it | |
2528 | if we are configured for an embedded target */ | |
2529 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2530 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2531 | flags |= SEC_ALLOC | SEC_LOAD; |
2532 | ||
316f5878 | 2533 | if (mips_abi != N64_ABI) |
252b5132 RH |
2534 | { |
2535 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2536 | ||
195325d2 TS |
2537 | bfd_set_section_flags (stdoutput, sec, flags); |
2538 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2539 | |
252b5132 | 2540 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2541 | } |
2542 | else | |
2543 | { | |
2544 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2545 | .reginfo section. */ | |
2546 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2547 | bfd_set_section_flags (stdoutput, sec, flags); |
2548 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2549 | |
252b5132 RH |
2550 | /* Set up the option header. */ |
2551 | { | |
2552 | Elf_Internal_Options opthdr; | |
2553 | char *f; | |
2554 | ||
2555 | opthdr.kind = ODK_REGINFO; | |
2556 | opthdr.size = (sizeof (Elf_External_Options) | |
2557 | + sizeof (Elf64_External_RegInfo)); | |
2558 | opthdr.section = 0; | |
2559 | opthdr.info = 0; | |
2560 | f = frag_more (sizeof (Elf_External_Options)); | |
2561 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2562 | (Elf_External_Options *) f); | |
2563 | ||
2564 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2565 | } | |
252b5132 RH |
2566 | } |
2567 | ||
2568 | if (ECOFF_DEBUGGING) | |
2569 | { | |
2570 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2571 | (void) bfd_set_section_flags (stdoutput, sec, | |
2572 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2573 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2574 | } | |
f43abd2b | 2575 | else if (mips_flag_pdr) |
ecb4347a DJ |
2576 | { |
2577 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2578 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2579 | SEC_READONLY | SEC_RELOC | |
2580 | | SEC_DEBUGGING); | |
2581 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2582 | } | |
252b5132 RH |
2583 | |
2584 | subseg_set (seg, subseg); | |
2585 | } | |
2586 | } | |
707bfff6 | 2587 | #endif /* OBJ_ELF */ |
252b5132 RH |
2588 | |
2589 | if (! ECOFF_DEBUGGING) | |
2590 | md_obj_begin (); | |
71400594 RS |
2591 | |
2592 | if (mips_fix_vr4120) | |
2593 | init_vr4120_conflicts (); | |
252b5132 RH |
2594 | } |
2595 | ||
2596 | void | |
17a2f251 | 2597 | md_mips_end (void) |
252b5132 | 2598 | { |
02b1ab82 | 2599 | mips_emit_delays (); |
252b5132 RH |
2600 | if (! ECOFF_DEBUGGING) |
2601 | md_obj_end (); | |
2602 | } | |
2603 | ||
2604 | void | |
17a2f251 | 2605 | md_assemble (char *str) |
252b5132 RH |
2606 | { |
2607 | struct mips_cl_insn insn; | |
f6688943 TS |
2608 | bfd_reloc_code_real_type unused_reloc[3] |
2609 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2610 | |
2611 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2612 | imm2_expr.X_op = O_absent; |
252b5132 | 2613 | offset_expr.X_op = O_absent; |
f6688943 TS |
2614 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2615 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2616 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2617 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2618 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2619 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2620 | |
e1b47bd5 RS |
2621 | mips_mark_labels (); |
2622 | mips_assembling_insn = TRUE; | |
2623 | ||
252b5132 RH |
2624 | if (mips_opts.mips16) |
2625 | mips16_ip (str, &insn); | |
2626 | else | |
2627 | { | |
2628 | mips_ip (str, &insn); | |
beae10d5 KH |
2629 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2630 | str, insn.insn_opcode)); | |
252b5132 RH |
2631 | } |
2632 | ||
2633 | if (insn_error) | |
e1b47bd5 RS |
2634 | as_bad ("%s `%s'", insn_error, str); |
2635 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2636 | { |
584892a6 | 2637 | macro_start (); |
252b5132 RH |
2638 | if (mips_opts.mips16) |
2639 | mips16_macro (&insn); | |
2640 | else | |
2641 | macro (&insn); | |
584892a6 | 2642 | macro_end (); |
252b5132 RH |
2643 | } |
2644 | else | |
2645 | { | |
2646 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2647 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2648 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2649 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2650 | else |
df58fc94 | 2651 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2652 | } |
e1b47bd5 RS |
2653 | |
2654 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2655 | } |
2656 | ||
738e5348 RS |
2657 | /* Convenience functions for abstracting away the differences between |
2658 | MIPS16 and non-MIPS16 relocations. */ | |
2659 | ||
2660 | static inline bfd_boolean | |
2661 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2662 | { | |
2663 | switch (reloc) | |
2664 | { | |
2665 | case BFD_RELOC_MIPS16_JMP: | |
2666 | case BFD_RELOC_MIPS16_GPREL: | |
2667 | case BFD_RELOC_MIPS16_GOT16: | |
2668 | case BFD_RELOC_MIPS16_CALL16: | |
2669 | case BFD_RELOC_MIPS16_HI16_S: | |
2670 | case BFD_RELOC_MIPS16_HI16: | |
2671 | case BFD_RELOC_MIPS16_LO16: | |
2672 | return TRUE; | |
2673 | ||
2674 | default: | |
2675 | return FALSE; | |
2676 | } | |
2677 | } | |
2678 | ||
df58fc94 RS |
2679 | static inline bfd_boolean |
2680 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2681 | { | |
2682 | switch (reloc) | |
2683 | { | |
2684 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2685 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2686 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2687 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2688 | case BFD_RELOC_MICROMIPS_JMP: | |
2689 | case BFD_RELOC_MICROMIPS_HI16: | |
2690 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2691 | case BFD_RELOC_MICROMIPS_LO16: | |
2692 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2693 | case BFD_RELOC_MICROMIPS_GOT16: | |
2694 | case BFD_RELOC_MICROMIPS_CALL16: | |
2695 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2696 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2697 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2698 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2699 | case BFD_RELOC_MICROMIPS_SUB: | |
2700 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2701 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2702 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2703 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2704 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2705 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2706 | case BFD_RELOC_MICROMIPS_JALR: | |
2707 | return TRUE; | |
2708 | ||
2709 | default: | |
2710 | return FALSE; | |
2711 | } | |
2712 | } | |
2713 | ||
2309ddf2 MR |
2714 | static inline bfd_boolean |
2715 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2716 | { | |
2717 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2718 | } | |
2719 | ||
738e5348 RS |
2720 | static inline bfd_boolean |
2721 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2722 | { | |
2309ddf2 | 2723 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2724 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2725 | } |
2726 | ||
2727 | static inline bfd_boolean | |
2728 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2729 | { | |
2309ddf2 | 2730 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2731 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2732 | } |
2733 | ||
2734 | static inline bfd_boolean | |
2735 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2736 | { | |
2309ddf2 | 2737 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2738 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2739 | } | |
2740 | ||
df58fc94 RS |
2741 | static inline bfd_boolean |
2742 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2743 | { | |
2309ddf2 | 2744 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2745 | } |
2746 | ||
2de39019 CM |
2747 | /* Return true if RELOC is a PC-relative relocation that does not have |
2748 | full address range. */ | |
2749 | ||
2750 | static inline bfd_boolean | |
2751 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2752 | { | |
2753 | switch (reloc) | |
2754 | { | |
2755 | case BFD_RELOC_16_PCREL_S2: | |
2756 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2757 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2758 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2759 | return TRUE; | |
2760 | ||
2761 | default: | |
2762 | return FALSE; | |
2763 | } | |
2764 | } | |
5919d012 | 2765 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2766 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2767 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2768 | |
2769 | static inline bfd_boolean | |
17a2f251 | 2770 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2771 | { |
3b91255e | 2772 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2773 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2774 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2775 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2776 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2777 | } | |
2778 | ||
2779 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2780 | reloc_needs_lo_p. */ | |
2781 | ||
2782 | static inline bfd_reloc_code_real_type | |
2783 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2784 | { | |
df58fc94 RS |
2785 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2786 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2787 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2788 | } |
2789 | ||
2790 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2791 | relocation. */ | |
2792 | ||
2793 | static inline bfd_boolean | |
17a2f251 | 2794 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2795 | { |
2796 | return (fixp->fx_next != NULL | |
738e5348 | 2797 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2798 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2799 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2800 | } | |
2801 | ||
252b5132 RH |
2802 | /* This function returns true if modifying a register requires a |
2803 | delay. */ | |
2804 | ||
2805 | static int | |
17a2f251 | 2806 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2807 | { |
2808 | unsigned long prev_pinfo; | |
2809 | ||
47e39b9d | 2810 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2811 | if (! mips_opts.noreorder |
81912461 ILT |
2812 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2813 | && ! gpr_interlocks) | |
2814 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2815 | && ! cop_interlocks))) | |
252b5132 | 2816 | { |
81912461 ILT |
2817 | /* A load from a coprocessor or from memory. All load delays |
2818 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2819 | /* Itbl support may require additional care here. */ |
252b5132 | 2820 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2821 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2822 | return 1; |
2823 | } | |
2824 | ||
2825 | return 0; | |
2826 | } | |
2827 | ||
462427c4 RS |
2828 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2829 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2830 | |
2831 | static void | |
462427c4 | 2832 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2833 | { |
2834 | struct insn_label_list *l; | |
2835 | valueT val; | |
2836 | ||
462427c4 | 2837 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2838 | { |
9c2799c2 | 2839 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2840 | symbol_set_frag (l->label, frag_now); |
2841 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2842 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2843 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2844 | ++val; |
2845 | S_SET_VALUE (l->label, val); | |
2846 | } | |
2847 | } | |
2848 | ||
462427c4 RS |
2849 | /* Move all labels in insn_labels to the current insertion point |
2850 | and treat them as text labels. */ | |
2851 | ||
2852 | static void | |
2853 | mips_move_text_labels (void) | |
2854 | { | |
2855 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2856 | } | |
2857 | ||
5f0fe04b TS |
2858 | static bfd_boolean |
2859 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2860 | { | |
2861 | bfd_boolean linkonce = FALSE; | |
2862 | segT symseg = S_GET_SEGMENT (sym); | |
2863 | ||
2864 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2865 | { | |
2866 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2867 | linkonce = TRUE; | |
2868 | #ifdef OBJ_ELF | |
2869 | /* The GNU toolchain uses an extension for ELF: a section | |
2870 | beginning with the magic string .gnu.linkonce is a | |
2871 | linkonce section. */ | |
2872 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2873 | sizeof ".gnu.linkonce" - 1) == 0) | |
2874 | linkonce = TRUE; | |
2875 | #endif | |
2876 | } | |
2877 | return linkonce; | |
2878 | } | |
2879 | ||
e1b47bd5 | 2880 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2881 | linker to handle them specially, such as generating jalx instructions |
2882 | when needed. We also make them odd for the duration of the assembly, | |
2883 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2884 | in the adjust_symtab routine, while leaving them marked. This is |
2885 | convenient for the debugger and the disassembler. The linker knows | |
2886 | to make them odd again. */ | |
2887 | ||
2888 | static void | |
e1b47bd5 | 2889 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2890 | { |
df58fc94 | 2891 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2892 | |
a8dbcb85 | 2893 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2894 | if (IS_ELF) |
2895 | { | |
2896 | if (mips_opts.mips16) | |
2897 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2898 | else | |
2899 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2900 | } |
e1b47bd5 RS |
2901 | #endif |
2902 | if ((S_GET_VALUE (label) & 1) == 0 | |
2903 | /* Don't adjust the address if the label is global or weak, or | |
2904 | in a link-once section, since we'll be emitting symbol reloc | |
2905 | references to it which will be patched up by the linker, and | |
2906 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2907 | && !S_IS_WEAK (label) | |
2908 | && !S_IS_EXTERNAL (label) | |
2909 | && !s_is_linkonce (label, now_seg)) | |
2910 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2911 | } | |
2912 | ||
2913 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2914 | ||
2915 | static void | |
2916 | mips_compressed_mark_labels (void) | |
2917 | { | |
2918 | struct insn_label_list *l; | |
2919 | ||
2920 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2921 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2922 | } |
2923 | ||
4d7206a2 RS |
2924 | /* End the current frag. Make it a variant frag and record the |
2925 | relaxation info. */ | |
2926 | ||
2927 | static void | |
2928 | relax_close_frag (void) | |
2929 | { | |
584892a6 | 2930 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2931 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2932 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2933 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2934 | ||
2935 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2936 | mips_relax.first_fixup = 0; | |
2937 | } | |
2938 | ||
2939 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2940 | See the comment above RELAX_ENCODE for more details. */ | |
2941 | ||
2942 | static void | |
2943 | relax_start (symbolS *symbol) | |
2944 | { | |
9c2799c2 | 2945 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2946 | mips_relax.sequence = 1; |
2947 | mips_relax.symbol = symbol; | |
2948 | } | |
2949 | ||
2950 | /* Start generating the second version of a relaxable sequence. | |
2951 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2952 | |
2953 | static void | |
4d7206a2 RS |
2954 | relax_switch (void) |
2955 | { | |
9c2799c2 | 2956 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2957 | mips_relax.sequence = 2; |
2958 | } | |
2959 | ||
2960 | /* End the current relaxable sequence. */ | |
2961 | ||
2962 | static void | |
2963 | relax_end (void) | |
2964 | { | |
9c2799c2 | 2965 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2966 | relax_close_frag (); |
2967 | mips_relax.sequence = 0; | |
2968 | } | |
2969 | ||
11625dd8 RS |
2970 | /* Return true if IP is a delayed branch or jump. */ |
2971 | ||
2972 | static inline bfd_boolean | |
2973 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2974 | { | |
2975 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2976 | | INSN_COND_BRANCH_DELAY | |
2977 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2978 | } | |
2979 | ||
2980 | /* Return true if IP is a compact branch or jump. */ | |
2981 | ||
2982 | static inline bfd_boolean | |
2983 | compact_branch_p (const struct mips_cl_insn *ip) | |
2984 | { | |
2985 | if (mips_opts.mips16) | |
2986 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2987 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2988 | else | |
2989 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2990 | | INSN2_COND_BRANCH)) != 0; | |
2991 | } | |
2992 | ||
2993 | /* Return true if IP is an unconditional branch or jump. */ | |
2994 | ||
2995 | static inline bfd_boolean | |
2996 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2997 | { | |
2998 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2999 | || (mips_opts.mips16 | |
3000 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3001 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3002 | } | |
3003 | ||
3004 | /* Return true if IP is a branch-likely instruction. */ | |
3005 | ||
3006 | static inline bfd_boolean | |
3007 | branch_likely_p (const struct mips_cl_insn *ip) | |
3008 | { | |
3009 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3010 | } | |
3011 | ||
14fe068b RS |
3012 | /* Return the type of nop that should be used to fill the delay slot |
3013 | of delayed branch IP. */ | |
3014 | ||
3015 | static struct mips_cl_insn * | |
3016 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3017 | { | |
3018 | if (mips_opts.micromips | |
3019 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3020 | return µmips_nop32_insn; | |
3021 | return NOP_INSN; | |
3022 | } | |
3023 | ||
2309ddf2 | 3024 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3025 | |
3026 | static unsigned int | |
3027 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3028 | { | |
2309ddf2 | 3029 | unsigned long pinfo2; |
df58fc94 RS |
3030 | unsigned int mask; |
3031 | ||
3032 | mask = 0; | |
df58fc94 RS |
3033 | pinfo2 = ip->insn_mo->pinfo2; |
3034 | if (mips_opts.micromips) | |
3035 | { | |
df58fc94 RS |
3036 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3037 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3038 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3039 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3040 | if (pinfo2 & INSN2_MOD_SP) |
3041 | mask |= 1 << SP; | |
3042 | } | |
3043 | return mask; | |
3044 | } | |
3045 | ||
4c260379 RS |
3046 | /* Return the mask of core registers that IP reads. */ |
3047 | ||
3048 | static unsigned int | |
3049 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3050 | { | |
3051 | unsigned long pinfo, pinfo2; | |
3052 | unsigned int mask; | |
3053 | ||
df58fc94 | 3054 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3055 | pinfo = ip->insn_mo->pinfo; |
3056 | pinfo2 = ip->insn_mo->pinfo2; | |
3057 | if (mips_opts.mips16) | |
3058 | { | |
3059 | if (pinfo & MIPS16_INSN_READ_X) | |
3060 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3061 | if (pinfo & MIPS16_INSN_READ_Y) | |
3062 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3063 | if (pinfo & MIPS16_INSN_READ_T) | |
3064 | mask |= 1 << TREG; | |
3065 | if (pinfo & MIPS16_INSN_READ_SP) | |
3066 | mask |= 1 << SP; | |
3067 | if (pinfo & MIPS16_INSN_READ_31) | |
3068 | mask |= 1 << RA; | |
3069 | if (pinfo & MIPS16_INSN_READ_Z) | |
3070 | mask |= 1 << (mips16_to_32_reg_map | |
3071 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3072 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3073 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3074 | } | |
3075 | else | |
3076 | { | |
3077 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3078 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3079 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3080 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3081 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3082 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3083 | if (pinfo2 & INSN2_READ_GP) | |
3084 | mask |= 1 << GP; | |
3085 | if (pinfo2 & INSN2_READ_GPR_31) | |
3086 | mask |= 1 << RA; | |
4c260379 | 3087 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3088 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3089 | } |
2b0c8b40 MR |
3090 | if (mips_opts.micromips) |
3091 | { | |
3092 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3093 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3094 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3095 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3096 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3097 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3098 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3099 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3100 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3101 | { | |
3102 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3103 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3104 | } | |
3105 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3106 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3107 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3108 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3109 | } | |
fe35f09f RS |
3110 | /* Don't include register 0. */ |
3111 | return mask & ~1; | |
4c260379 RS |
3112 | } |
3113 | ||
3114 | /* Return the mask of core registers that IP writes. */ | |
3115 | ||
3116 | static unsigned int | |
3117 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3118 | { | |
3119 | unsigned long pinfo, pinfo2; | |
3120 | unsigned int mask; | |
3121 | ||
df58fc94 | 3122 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3123 | pinfo = ip->insn_mo->pinfo; |
3124 | pinfo2 = ip->insn_mo->pinfo2; | |
3125 | if (mips_opts.mips16) | |
3126 | { | |
3127 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3128 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3129 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3130 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3131 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3132 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3133 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3134 | mask |= 1 << TREG; | |
3135 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3136 | mask |= 1 << SP; | |
3137 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3138 | mask |= 1 << RA; | |
3139 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3140 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3141 | } | |
3142 | else | |
3143 | { | |
3144 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3145 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3146 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3147 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3148 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3149 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3150 | if (pinfo & INSN_WRITE_GPR_31) |
3151 | mask |= 1 << RA; | |
3152 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3153 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3154 | } |
2b0c8b40 MR |
3155 | if (mips_opts.micromips) |
3156 | { | |
3157 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3158 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3159 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3160 | { | |
3161 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3162 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3163 | } | |
3164 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3165 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3166 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3167 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3168 | } | |
fe35f09f RS |
3169 | /* Don't include register 0. */ |
3170 | return mask & ~1; | |
4c260379 RS |
3171 | } |
3172 | ||
3173 | /* Return the mask of floating-point registers that IP reads. */ | |
3174 | ||
3175 | static unsigned int | |
3176 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3177 | { | |
3178 | unsigned long pinfo, pinfo2; | |
3179 | unsigned int mask; | |
3180 | ||
3181 | mask = 0; | |
3182 | pinfo = ip->insn_mo->pinfo; | |
3183 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3184 | if (!mips_opts.mips16) |
df58fc94 RS |
3185 | { |
3186 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3187 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3188 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3189 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3190 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3191 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3192 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3193 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3194 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3195 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3196 | } |
3197 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3198 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3199 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3200 | mask |= mask << 1; | |
3201 | return mask; | |
3202 | } | |
3203 | ||
3204 | /* Return the mask of floating-point registers that IP writes. */ | |
3205 | ||
3206 | static unsigned int | |
3207 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3208 | { | |
3209 | unsigned long pinfo, pinfo2; | |
3210 | unsigned int mask; | |
3211 | ||
3212 | mask = 0; | |
3213 | pinfo = ip->insn_mo->pinfo; | |
3214 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3215 | if (!mips_opts.mips16) |
4c260379 RS |
3216 | { |
3217 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3218 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3219 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3220 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3221 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3222 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3223 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3224 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3225 | } |
3226 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3227 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3228 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3229 | mask |= mask << 1; | |
3230 | return mask; | |
3231 | } | |
3232 | ||
71400594 RS |
3233 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3234 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3235 | by VR4120 errata. */ | |
4d7206a2 | 3236 | |
71400594 RS |
3237 | static unsigned int |
3238 | classify_vr4120_insn (const char *name) | |
252b5132 | 3239 | { |
71400594 RS |
3240 | if (strncmp (name, "macc", 4) == 0) |
3241 | return FIX_VR4120_MACC; | |
3242 | if (strncmp (name, "dmacc", 5) == 0) | |
3243 | return FIX_VR4120_DMACC; | |
3244 | if (strncmp (name, "mult", 4) == 0) | |
3245 | return FIX_VR4120_MULT; | |
3246 | if (strncmp (name, "dmult", 5) == 0) | |
3247 | return FIX_VR4120_DMULT; | |
3248 | if (strstr (name, "div")) | |
3249 | return FIX_VR4120_DIV; | |
3250 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3251 | return FIX_VR4120_MTHILO; | |
3252 | return NUM_FIX_VR4120_CLASSES; | |
3253 | } | |
252b5132 | 3254 | |
ff239038 CM |
3255 | #define INSN_ERET 0x42000018 |
3256 | #define INSN_DERET 0x4200001f | |
3257 | ||
71400594 RS |
3258 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3259 | where INSN1 is the earlier instruction. Return the worst-case value | |
3260 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3261 | |
71400594 RS |
3262 | static unsigned int |
3263 | insns_between (const struct mips_cl_insn *insn1, | |
3264 | const struct mips_cl_insn *insn2) | |
3265 | { | |
3266 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3267 | unsigned int mask; |
71400594 RS |
3268 | |
3269 | /* This function needs to know which pinfo flags are set for INSN2 | |
3270 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3271 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3272 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3273 | pinfo1 = insn1->insn_mo->pinfo; |
3274 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3275 | |
4c260379 RS |
3276 | #define INSN2_USES_GPR(REG) \ |
3277 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3278 | |
3279 | /* For most targets, write-after-read dependencies on the HI and LO | |
3280 | registers must be separated by at least two instructions. */ | |
3281 | if (!hilo_interlocks) | |
252b5132 | 3282 | { |
71400594 RS |
3283 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3284 | return 2; | |
3285 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3286 | return 2; | |
3287 | } | |
3288 | ||
3289 | /* If we're working around r7000 errata, there must be two instructions | |
3290 | between an mfhi or mflo and any instruction that uses the result. */ | |
3291 | if (mips_7000_hilo_fix | |
df58fc94 | 3292 | && !mips_opts.micromips |
71400594 | 3293 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3294 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3295 | return 2; |
3296 | ||
ff239038 CM |
3297 | /* If we're working around 24K errata, one instruction is required |
3298 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3299 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3300 | { |
3301 | if (insn1->insn_opcode == INSN_ERET | |
3302 | || insn1->insn_opcode == INSN_DERET) | |
3303 | { | |
3304 | if (insn2 == NULL | |
3305 | || insn2->insn_opcode == INSN_ERET | |
3306 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3307 | || delayed_branch_p (insn2)) |
ff239038 CM |
3308 | return 1; |
3309 | } | |
3310 | } | |
3311 | ||
71400594 RS |
3312 | /* If working around VR4120 errata, check for combinations that need |
3313 | a single intervening instruction. */ | |
df58fc94 | 3314 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3315 | { |
3316 | unsigned int class1, class2; | |
252b5132 | 3317 | |
71400594 RS |
3318 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3319 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3320 | { |
71400594 RS |
3321 | if (insn2 == NULL) |
3322 | return 1; | |
3323 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3324 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3325 | return 1; | |
252b5132 | 3326 | } |
71400594 RS |
3327 | } |
3328 | ||
df58fc94 | 3329 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3330 | { |
3331 | /* Check for GPR or coprocessor load delays. All such delays | |
3332 | are on the RT register. */ | |
3333 | /* Itbl support may require additional care here. */ | |
3334 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3335 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3336 | { |
71400594 | 3337 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3338 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3339 | return 1; |
3340 | } | |
3341 | ||
3342 | /* Check for generic coprocessor hazards. | |
3343 | ||
3344 | This case is not handled very well. There is no special | |
3345 | knowledge of CP0 handling, and the coprocessors other than | |
3346 | the floating point unit are not distinguished at all. */ | |
3347 | /* Itbl support may require additional care here. FIXME! | |
3348 | Need to modify this to include knowledge about | |
3349 | user specified delays! */ | |
3350 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3351 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3352 | { | |
3353 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3354 | register. There must be a one instruction delay before INSN2 | |
3355 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3356 | mask = fpr_write_mask (insn1); |
3357 | if (mask != 0) | |
252b5132 | 3358 | { |
4c260379 | 3359 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3360 | return 1; |
252b5132 RH |
3361 | } |
3362 | else | |
3363 | { | |
71400594 RS |
3364 | /* Read-after-write dependencies on the control registers |
3365 | require a two-instruction gap. */ | |
3366 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3367 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3368 | return 2; | |
3369 | ||
3370 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3371 | also a coprocessor instruction, assume there must be | |
3372 | a one instruction gap. */ | |
3373 | if (pinfo2 & INSN_COP) | |
3374 | return 1; | |
252b5132 RH |
3375 | } |
3376 | } | |
6b76fefe | 3377 | |
71400594 RS |
3378 | /* Check for read-after-write dependencies on the coprocessor |
3379 | control registers in cases where INSN1 does not need a general | |
3380 | coprocessor delay. This means that INSN1 is a floating point | |
3381 | comparison instruction. */ | |
3382 | /* Itbl support may require additional care here. */ | |
3383 | else if (!cop_interlocks | |
3384 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3385 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3386 | return 1; | |
3387 | } | |
6b76fefe | 3388 | |
4c260379 | 3389 | #undef INSN2_USES_GPR |
6b76fefe | 3390 | |
71400594 RS |
3391 | return 0; |
3392 | } | |
6b76fefe | 3393 | |
7d8e00cf RS |
3394 | /* Return the number of nops that would be needed to work around the |
3395 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3396 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3397 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3398 | |
3399 | static int | |
932d1a1b | 3400 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3401 | const struct mips_cl_insn *insn) |
3402 | { | |
4c260379 RS |
3403 | int i, j; |
3404 | unsigned int mask; | |
7d8e00cf RS |
3405 | |
3406 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3407 | are not affected by the errata. */ | |
3408 | if (insn != 0 | |
3409 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3410 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3411 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3412 | return 0; | |
3413 | ||
3414 | /* Search for the first MFLO or MFHI. */ | |
3415 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3416 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3417 | { |
3418 | /* Extract the destination register. */ | |
4c260379 | 3419 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3420 | |
3421 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3422 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3423 | return 0; |
3424 | ||
3425 | /* ...or if any of the intervening instructions do. */ | |
3426 | for (j = 0; j < i; j++) | |
4c260379 | 3427 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3428 | return 0; |
3429 | ||
932d1a1b RS |
3430 | if (i >= ignore) |
3431 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3432 | } |
3433 | return 0; | |
3434 | } | |
3435 | ||
15be625d CM |
3436 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3437 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3438 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3439 | ||
3440 | /* Return the minimum alignment for this store instruction. */ | |
3441 | ||
3442 | static int | |
3443 | fix_24k_align_to (const struct mips_opcode *mo) | |
3444 | { | |
3445 | if (strcmp (mo->name, "sh") == 0) | |
3446 | return 2; | |
3447 | ||
3448 | if (strcmp (mo->name, "swc1") == 0 | |
3449 | || strcmp (mo->name, "swc2") == 0 | |
3450 | || strcmp (mo->name, "sw") == 0 | |
3451 | || strcmp (mo->name, "sc") == 0 | |
3452 | || strcmp (mo->name, "s.s") == 0) | |
3453 | return 4; | |
3454 | ||
3455 | if (strcmp (mo->name, "sdc1") == 0 | |
3456 | || strcmp (mo->name, "sdc2") == 0 | |
3457 | || strcmp (mo->name, "s.d") == 0) | |
3458 | return 8; | |
3459 | ||
3460 | /* sb, swl, swr */ | |
3461 | return 1; | |
3462 | } | |
3463 | ||
3464 | struct fix_24k_store_info | |
3465 | { | |
3466 | /* Immediate offset, if any, for this store instruction. */ | |
3467 | short off; | |
3468 | /* Alignment required by this store instruction. */ | |
3469 | int align_to; | |
3470 | /* True for register offsets. */ | |
3471 | int register_offset; | |
3472 | }; | |
3473 | ||
3474 | /* Comparison function used by qsort. */ | |
3475 | ||
3476 | static int | |
3477 | fix_24k_sort (const void *a, const void *b) | |
3478 | { | |
3479 | const struct fix_24k_store_info *pos1 = a; | |
3480 | const struct fix_24k_store_info *pos2 = b; | |
3481 | ||
3482 | return (pos1->off - pos2->off); | |
3483 | } | |
3484 | ||
3485 | /* INSN is a store instruction. Try to record the store information | |
3486 | in STINFO. Return false if the information isn't known. */ | |
3487 | ||
3488 | static bfd_boolean | |
3489 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3490 | const struct mips_cl_insn *insn) |
15be625d CM |
3491 | { |
3492 | /* The instruction must have a known offset. */ | |
3493 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3494 | return FALSE; | |
3495 | ||
3496 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3497 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3498 | return TRUE; | |
3499 | } | |
3500 | ||
932d1a1b RS |
3501 | /* Return the number of nops that would be needed to work around the 24k |
3502 | "lost data on stores during refill" errata if instruction INSN | |
3503 | immediately followed the 2 instructions described by HIST. | |
3504 | Ignore hazards that are contained within the first IGNORE | |
3505 | instructions of HIST. | |
3506 | ||
3507 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3508 | for the data cache refills and store data. The following describes | |
3509 | the scenario where the store data could be lost. | |
3510 | ||
3511 | * A data cache miss, due to either a load or a store, causing fill | |
3512 | data to be supplied by the memory subsystem | |
3513 | * The first three doublewords of fill data are returned and written | |
3514 | into the cache | |
3515 | * A sequence of four stores occurs in consecutive cycles around the | |
3516 | final doubleword of the fill: | |
3517 | * Store A | |
3518 | * Store B | |
3519 | * Store C | |
3520 | * Zero, One or more instructions | |
3521 | * Store D | |
3522 | ||
3523 | The four stores A-D must be to different doublewords of the line that | |
3524 | is being filled. The fourth instruction in the sequence above permits | |
3525 | the fill of the final doubleword to be transferred from the FSB into | |
3526 | the cache. In the sequence above, the stores may be either integer | |
3527 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3528 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3529 | different doublewords on the line. If the floating point unit is | |
3530 | running in 1:2 mode, it is not possible to create the sequence above | |
3531 | using only floating point store instructions. | |
15be625d CM |
3532 | |
3533 | In this case, the cache line being filled is incorrectly marked | |
3534 | invalid, thereby losing the data from any store to the line that | |
3535 | occurs between the original miss and the completion of the five | |
3536 | cycle sequence shown above. | |
3537 | ||
932d1a1b | 3538 | The workarounds are: |
15be625d | 3539 | |
932d1a1b RS |
3540 | * Run the data cache in write-through mode. |
3541 | * Insert a non-store instruction between | |
3542 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3543 | |
3544 | static int | |
932d1a1b | 3545 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3546 | const struct mips_cl_insn *insn) |
3547 | { | |
3548 | struct fix_24k_store_info pos[3]; | |
3549 | int align, i, base_offset; | |
3550 | ||
932d1a1b RS |
3551 | if (ignore >= 2) |
3552 | return 0; | |
3553 | ||
ab9794cf RS |
3554 | /* If the previous instruction wasn't a store, there's nothing to |
3555 | worry about. */ | |
15be625d CM |
3556 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3557 | return 0; | |
3558 | ||
ab9794cf RS |
3559 | /* If the instructions after the previous one are unknown, we have |
3560 | to assume the worst. */ | |
3561 | if (!insn) | |
15be625d CM |
3562 | return 1; |
3563 | ||
ab9794cf RS |
3564 | /* Check whether we are dealing with three consecutive stores. */ |
3565 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3566 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3567 | return 0; |
3568 | ||
3569 | /* If we don't know the relationship between the store addresses, | |
3570 | assume the worst. */ | |
ab9794cf | 3571 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3572 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3573 | return 1; | |
3574 | ||
3575 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3576 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3577 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3578 | return 1; | |
3579 | ||
3580 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3581 | ||
3582 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3583 | X bytes and such that the base register + X is known to be aligned | |
3584 | to align bytes. */ | |
3585 | ||
3586 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3587 | align = 8; | |
3588 | else | |
3589 | { | |
3590 | align = pos[0].align_to; | |
3591 | base_offset = pos[0].off; | |
3592 | for (i = 1; i < 3; i++) | |
3593 | if (align < pos[i].align_to) | |
3594 | { | |
3595 | align = pos[i].align_to; | |
3596 | base_offset = pos[i].off; | |
3597 | } | |
3598 | for (i = 0; i < 3; i++) | |
3599 | pos[i].off -= base_offset; | |
3600 | } | |
3601 | ||
3602 | pos[0].off &= ~align + 1; | |
3603 | pos[1].off &= ~align + 1; | |
3604 | pos[2].off &= ~align + 1; | |
3605 | ||
3606 | /* If any two stores write to the same chunk, they also write to the | |
3607 | same doubleword. The offsets are still sorted at this point. */ | |
3608 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3609 | return 0; | |
3610 | ||
3611 | /* A range of at least 9 bytes is needed for the stores to be in | |
3612 | non-overlapping doublewords. */ | |
3613 | if (pos[2].off - pos[0].off <= 8) | |
3614 | return 0; | |
3615 | ||
3616 | if (pos[2].off - pos[1].off >= 24 | |
3617 | || pos[1].off - pos[0].off >= 24 | |
3618 | || pos[2].off - pos[0].off >= 32) | |
3619 | return 0; | |
3620 | ||
3621 | return 1; | |
3622 | } | |
3623 | ||
71400594 | 3624 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3625 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3626 | where HIST[0] is the most recent instruction. Ignore hazards |
3627 | between INSN and the first IGNORE instructions in HIST. | |
3628 | ||
3629 | If INSN is null, return the worse-case number of nops for any | |
3630 | instruction. */ | |
bdaaa2e1 | 3631 | |
71400594 | 3632 | static int |
932d1a1b | 3633 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3634 | const struct mips_cl_insn *insn) |
3635 | { | |
3636 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3637 | |
71400594 | 3638 | nops = 0; |
932d1a1b | 3639 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3640 | { |
91d6fa6a | 3641 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3642 | if (tmp_nops > nops) |
3643 | nops = tmp_nops; | |
3644 | } | |
7d8e00cf | 3645 | |
df58fc94 | 3646 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3647 | { |
932d1a1b | 3648 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3649 | if (tmp_nops > nops) |
3650 | nops = tmp_nops; | |
3651 | } | |
3652 | ||
df58fc94 | 3653 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3654 | { |
932d1a1b | 3655 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3656 | if (tmp_nops > nops) |
3657 | nops = tmp_nops; | |
3658 | } | |
3659 | ||
71400594 RS |
3660 | return nops; |
3661 | } | |
252b5132 | 3662 | |
71400594 | 3663 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3664 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3665 | would be needed after the extended sequence, ignoring hazards |
3666 | in the first IGNORE instructions. */ | |
252b5132 | 3667 | |
71400594 | 3668 | static int |
932d1a1b RS |
3669 | nops_for_sequence (int num_insns, int ignore, |
3670 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3671 | { |
3672 | va_list args; | |
3673 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3674 | struct mips_cl_insn *cursor; | |
3675 | int nops; | |
3676 | ||
91d6fa6a | 3677 | va_start (args, hist); |
71400594 | 3678 | cursor = buffer + num_insns; |
91d6fa6a | 3679 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3680 | while (cursor > buffer) |
3681 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3682 | ||
932d1a1b | 3683 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3684 | va_end (args); |
3685 | return nops; | |
3686 | } | |
252b5132 | 3687 | |
71400594 RS |
3688 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3689 | worst-case delay for the branch target. */ | |
252b5132 | 3690 | |
71400594 | 3691 | static int |
932d1a1b | 3692 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3693 | const struct mips_cl_insn *insn) |
3694 | { | |
3695 | int nops, tmp_nops; | |
60b63b72 | 3696 | |
932d1a1b | 3697 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3698 | if (delayed_branch_p (insn)) |
71400594 | 3699 | { |
932d1a1b | 3700 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3701 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3702 | if (tmp_nops > nops) |
3703 | nops = tmp_nops; | |
3704 | } | |
11625dd8 | 3705 | else if (compact_branch_p (insn)) |
71400594 | 3706 | { |
932d1a1b | 3707 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3708 | if (tmp_nops > nops) |
3709 | nops = tmp_nops; | |
3710 | } | |
3711 | return nops; | |
3712 | } | |
3713 | ||
c67a084a NC |
3714 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3715 | ||
3716 | static void | |
3717 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3718 | { | |
df58fc94 | 3719 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3720 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3721 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3722 | } | |
3723 | ||
3724 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3725 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3726 | ||
3727 | static void | |
3728 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3729 | { | |
df58fc94 | 3730 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3731 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3732 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3733 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3734 | { | |
3735 | int sreg; | |
3736 | expressionS ep; | |
3737 | ||
3738 | if (! mips_opts.at) | |
3739 | return; | |
3740 | ||
df58fc94 | 3741 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3742 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3743 | return; | |
3744 | ||
3745 | ep.X_op = O_constant; | |
3746 | ep.X_add_number = 0xcfff0000; | |
3747 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3748 | ep.X_add_number = 0xffff; | |
3749 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3750 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3751 | } | |
3752 | } | |
3753 | ||
3754 | static void | |
3755 | fix_loongson2f (struct mips_cl_insn * ip) | |
3756 | { | |
3757 | if (mips_fix_loongson2f_nop) | |
3758 | fix_loongson2f_nop (ip); | |
3759 | ||
3760 | if (mips_fix_loongson2f_jump) | |
3761 | fix_loongson2f_jump (ip); | |
3762 | } | |
3763 | ||
a4e06468 RS |
3764 | /* IP is a branch that has a delay slot, and we need to fill it |
3765 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3766 | with the previous instruction. |
3767 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3768 | RELOC_TYPE. */ | |
a4e06468 RS |
3769 | |
3770 | static bfd_boolean | |
e407c74b NC |
3771 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3772 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3773 | { |
2b0c8b40 | 3774 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3775 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3776 | ||
3777 | /* -O2 and above is required for this optimization. */ | |
3778 | if (mips_optimize < 2) | |
3779 | return FALSE; | |
3780 | ||
3781 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3782 | if (mips_opts.nomove) | |
3783 | return FALSE; | |
3784 | ||
3785 | /* We can't swap if the previous instruction's position is fixed. */ | |
3786 | if (history[0].fixed_p) | |
3787 | return FALSE; | |
3788 | ||
3789 | /* If the previous previous insn was in a .set noreorder, we can't | |
3790 | swap. Actually, the MIPS assembler will swap in this situation. | |
3791 | However, gcc configured -with-gnu-as will generate code like | |
3792 | ||
3793 | .set noreorder | |
3794 | lw $4,XXX | |
3795 | .set reorder | |
3796 | INSN | |
3797 | bne $4,$0,foo | |
3798 | ||
3799 | in which we can not swap the bne and INSN. If gcc is not configured | |
3800 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3801 | if (history[1].noreorder_p) | |
3802 | return FALSE; | |
3803 | ||
87333bb7 MR |
3804 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3805 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3806 | if (mips_opts.mips16 && history[0].fixp[0]) |
3807 | return FALSE; | |
3808 | ||
3809 | /* If the branch is itself the target of a branch, we can not swap. | |
3810 | We cheat on this; all we check for is whether there is a label on | |
3811 | this instruction. If there are any branches to anything other than | |
3812 | a label, users must use .set noreorder. */ | |
3813 | if (seg_info (now_seg)->label_list) | |
3814 | return FALSE; | |
3815 | ||
3816 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3817 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3818 | MIPS16 code, which uses variant frags for different purposes. */ |
3819 | if (!mips_opts.mips16 | |
a4e06468 RS |
3820 | && history[0].frag |
3821 | && history[0].frag->fr_type == rs_machine_dependent) | |
3822 | return FALSE; | |
3823 | ||
bcd530a7 RS |
3824 | /* We do not swap with instructions that cannot architecturally |
3825 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3826 | also refrain from swapping with a trap instruction, since it | |
3827 | complicates trap handlers to have the trap instruction be in | |
3828 | a delay slot. */ | |
a4e06468 | 3829 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3830 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3831 | return FALSE; |
3832 | ||
3833 | /* Check for conflicts between the branch and the instructions | |
3834 | before the candidate delay slot. */ | |
3835 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3836 | return FALSE; | |
3837 | ||
3838 | /* Check for conflicts between the swapped sequence and the | |
3839 | target of the branch. */ | |
3840 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3841 | return FALSE; | |
3842 | ||
3843 | /* If the branch reads a register that the previous | |
3844 | instruction sets, we can not swap. */ | |
3845 | gpr_read = gpr_read_mask (ip); | |
3846 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3847 | if (gpr_read & prev_gpr_write) | |
3848 | return FALSE; | |
3849 | ||
3850 | /* If the branch writes a register that the previous | |
3851 | instruction sets, we can not swap. */ | |
3852 | gpr_write = gpr_write_mask (ip); | |
3853 | if (gpr_write & prev_gpr_write) | |
3854 | return FALSE; | |
3855 | ||
3856 | /* If the branch writes a register that the previous | |
3857 | instruction reads, we can not swap. */ | |
3858 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3859 | if (gpr_write & prev_gpr_read) | |
3860 | return FALSE; | |
3861 | ||
3862 | /* If one instruction sets a condition code and the | |
3863 | other one uses a condition code, we can not swap. */ | |
3864 | pinfo = ip->insn_mo->pinfo; | |
3865 | if ((pinfo & INSN_READ_COND_CODE) | |
3866 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3867 | return FALSE; | |
3868 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3869 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3870 | return FALSE; | |
3871 | ||
3872 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3873 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3874 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3875 | return FALSE; | |
2b0c8b40 MR |
3876 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3877 | return FALSE; | |
a4e06468 | 3878 | |
df58fc94 RS |
3879 | /* If the previous instruction has an incorrect size for a fixed |
3880 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3881 | pinfo2 = ip->insn_mo->pinfo2; |
3882 | if (mips_opts.micromips | |
3883 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3884 | && insn_length (history) != 2) | |
3885 | return FALSE; | |
3886 | if (mips_opts.micromips | |
3887 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3888 | && insn_length (history) != 4) | |
3889 | return FALSE; | |
3890 | ||
e407c74b NC |
3891 | /* On R5900 short loops need to be fixed by inserting a nop in |
3892 | the branch delay slots. | |
3893 | A short loop can be terminated too early. */ | |
3894 | if (mips_opts.arch == CPU_R5900 | |
3895 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3896 | && (address_expr != NULL) | |
3897 | /* Parameter must be 16 bit. */ | |
3898 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3899 | /* Branch to same segment. */ | |
3900 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3901 | /* Branch to same code fragment. */ | |
3902 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3903 | /* Can only calculate branch offset if value is known. */ | |
3904 | && symbol_constant_p(address_expr->X_add_symbol) | |
3905 | /* Check if branch is really conditional. */ | |
3906 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3907 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3908 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3909 | { | |
3910 | int distance; | |
3911 | /* Check if loop is shorter than 6 instructions including | |
3912 | branch and delay slot. */ | |
3913 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3914 | if (distance <= 20) | |
3915 | { | |
3916 | int i; | |
3917 | int rv; | |
3918 | ||
3919 | rv = FALSE; | |
3920 | /* When the loop includes branches or jumps, | |
3921 | it is not a short loop. */ | |
3922 | for (i = 0; i < (distance / 4); i++) | |
3923 | { | |
3924 | if ((history[i].cleared_p) | |
3925 | || delayed_branch_p(&history[i])) | |
3926 | { | |
3927 | rv = TRUE; | |
3928 | break; | |
3929 | } | |
3930 | } | |
3931 | if (rv == FALSE) | |
3932 | { | |
3933 | /* Insert nop after branch to fix short loop. */ | |
3934 | return FALSE; | |
3935 | } | |
3936 | } | |
3937 | } | |
3938 | ||
a4e06468 RS |
3939 | return TRUE; |
3940 | } | |
3941 | ||
e407c74b NC |
3942 | /* Decide how we should add IP to the instruction stream. |
3943 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3944 | RELOC_TYPE. */ | |
a4e06468 RS |
3945 | |
3946 | static enum append_method | |
e407c74b NC |
3947 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3948 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3949 | { |
3950 | unsigned long pinfo; | |
3951 | ||
3952 | /* The relaxed version of a macro sequence must be inherently | |
3953 | hazard-free. */ | |
3954 | if (mips_relax.sequence == 2) | |
3955 | return APPEND_ADD; | |
3956 | ||
3957 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3958 | if (mips_opts.noreorder) | |
3959 | return APPEND_ADD; | |
3960 | ||
3961 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3962 | if (delayed_branch_p (ip)) |
a4e06468 | 3963 | { |
e407c74b NC |
3964 | if (!branch_likely_p (ip) |
3965 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
3966 | return APPEND_SWAP; |
3967 | ||
11625dd8 | 3968 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3969 | if (mips_opts.mips16 |
3970 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3971 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3972 | return APPEND_ADD_COMPACT; | |
3973 | ||
3974 | return APPEND_ADD_WITH_NOP; | |
3975 | } | |
3976 | ||
a4e06468 RS |
3977 | return APPEND_ADD; |
3978 | } | |
3979 | ||
ceb94aa5 RS |
3980 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3981 | Point IP->insn_mo to the new opcode's definition. */ | |
3982 | ||
3983 | static void | |
3984 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3985 | { | |
3986 | const struct mips_opcode *mo, *end; | |
3987 | ||
3988 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3989 | for (mo = ip->insn_mo; mo < end; mo++) | |
3990 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3991 | { | |
3992 | ip->insn_mo = mo; | |
3993 | return; | |
3994 | } | |
3995 | abort (); | |
3996 | } | |
3997 | ||
df58fc94 RS |
3998 | /* For microMIPS macros, we need to generate a local number label |
3999 | as the target of branches. */ | |
4000 | #define MICROMIPS_LABEL_CHAR '\037' | |
4001 | static unsigned long micromips_target_label; | |
4002 | static char micromips_target_name[32]; | |
4003 | ||
4004 | static char * | |
4005 | micromips_label_name (void) | |
4006 | { | |
4007 | char *p = micromips_target_name; | |
4008 | char symbol_name_temporary[24]; | |
4009 | unsigned long l; | |
4010 | int i; | |
4011 | ||
4012 | if (*p) | |
4013 | return p; | |
4014 | ||
4015 | i = 0; | |
4016 | l = micromips_target_label; | |
4017 | #ifdef LOCAL_LABEL_PREFIX | |
4018 | *p++ = LOCAL_LABEL_PREFIX; | |
4019 | #endif | |
4020 | *p++ = 'L'; | |
4021 | *p++ = MICROMIPS_LABEL_CHAR; | |
4022 | do | |
4023 | { | |
4024 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4025 | l /= 10; | |
4026 | } | |
4027 | while (l != 0); | |
4028 | while (i > 0) | |
4029 | *p++ = symbol_name_temporary[--i]; | |
4030 | *p = '\0'; | |
4031 | ||
4032 | return micromips_target_name; | |
4033 | } | |
4034 | ||
4035 | static void | |
4036 | micromips_label_expr (expressionS *label_expr) | |
4037 | { | |
4038 | label_expr->X_op = O_symbol; | |
4039 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4040 | label_expr->X_add_number = 0; | |
4041 | } | |
4042 | ||
4043 | static void | |
4044 | micromips_label_inc (void) | |
4045 | { | |
4046 | micromips_target_label++; | |
4047 | *micromips_target_name = '\0'; | |
4048 | } | |
4049 | ||
4050 | static void | |
4051 | micromips_add_label (void) | |
4052 | { | |
4053 | symbolS *s; | |
4054 | ||
4055 | s = colon (micromips_label_name ()); | |
4056 | micromips_label_inc (); | |
4057 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4058 | if (IS_ELF) | |
4059 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4060 | #else |
4061 | (void) s; | |
df58fc94 RS |
4062 | #endif |
4063 | } | |
4064 | ||
4065 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4066 | corresponding to the requested one if any. Otherwise return | |
4067 | the reloc unchanged. */ | |
4068 | ||
4069 | static bfd_reloc_code_real_type | |
4070 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4071 | { | |
4072 | static const bfd_reloc_code_real_type relocs[][2] = | |
4073 | { | |
4074 | /* Keep sorted incrementally by the left-hand key. */ | |
4075 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4076 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4077 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4078 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4079 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4080 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4081 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4082 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4083 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4084 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4085 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4086 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4087 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4088 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4089 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4090 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4091 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4092 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4093 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4094 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4095 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4096 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4097 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4098 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4099 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4100 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4101 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4102 | }; | |
4103 | bfd_reloc_code_real_type r; | |
4104 | size_t i; | |
4105 | ||
4106 | if (!mips_opts.micromips) | |
4107 | return reloc; | |
4108 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4109 | { | |
4110 | r = relocs[i][0]; | |
4111 | if (r > reloc) | |
4112 | return reloc; | |
4113 | if (r == reloc) | |
4114 | return relocs[i][1]; | |
4115 | } | |
4116 | return reloc; | |
4117 | } | |
4118 | ||
b886a2ab RS |
4119 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4120 | Return true on success, storing the resolved value in RESULT. */ | |
4121 | ||
4122 | static bfd_boolean | |
4123 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4124 | offsetT *result) | |
4125 | { | |
4126 | switch (reloc) | |
4127 | { | |
4128 | case BFD_RELOC_MIPS_HIGHEST: | |
4129 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4130 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4131 | return TRUE; | |
4132 | ||
4133 | case BFD_RELOC_MIPS_HIGHER: | |
4134 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4135 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4136 | return TRUE; | |
4137 | ||
4138 | case BFD_RELOC_HI16_S: | |
4139 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4140 | case BFD_RELOC_MIPS16_HI16_S: | |
4141 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4142 | return TRUE; | |
4143 | ||
4144 | case BFD_RELOC_HI16: | |
4145 | case BFD_RELOC_MICROMIPS_HI16: | |
4146 | case BFD_RELOC_MIPS16_HI16: | |
4147 | *result = (operand >> 16) & 0xffff; | |
4148 | return TRUE; | |
4149 | ||
4150 | case BFD_RELOC_LO16: | |
4151 | case BFD_RELOC_MICROMIPS_LO16: | |
4152 | case BFD_RELOC_MIPS16_LO16: | |
4153 | *result = operand & 0xffff; | |
4154 | return TRUE; | |
4155 | ||
4156 | case BFD_RELOC_UNUSED: | |
4157 | *result = operand; | |
4158 | return TRUE; | |
4159 | ||
4160 | default: | |
4161 | return FALSE; | |
4162 | } | |
4163 | } | |
4164 | ||
71400594 RS |
4165 | /* Output an instruction. IP is the instruction information. |
4166 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4167 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4168 | a macro expansion. */ | |
71400594 RS |
4169 | |
4170 | static void | |
4171 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4172 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4173 | { |
14fe068b | 4174 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4175 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4176 | enum append_method method; |
2309ddf2 | 4177 | bfd_boolean relax32; |
2b0c8b40 | 4178 | int branch_disp; |
71400594 | 4179 | |
2309ddf2 | 4180 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4181 | fix_loongson2f (ip); |
4182 | ||
738f4d98 | 4183 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4184 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4185 | |
df58fc94 | 4186 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4187 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4188 | |
4189 | if (mips_opts.micromips | |
4190 | && !expansionp | |
4191 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4192 | && micromips_insn_length (ip->insn_mo) != 2) | |
4193 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4194 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4195 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4196 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4197 | |
15be625d CM |
4198 | if (address_expr == NULL) |
4199 | ip->complete_p = 1; | |
b886a2ab RS |
4200 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4201 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4202 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4203 | && address_expr->X_op == O_constant) |
4204 | { | |
15be625d CM |
4205 | switch (*reloc_type) |
4206 | { | |
15be625d | 4207 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4208 | { |
4209 | int shift; | |
4210 | ||
4211 | shift = mips_opts.micromips ? 1 : 2; | |
4212 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4213 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4214 | (unsigned long) address_expr->X_add_number); | |
4215 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4216 | & 0x3ffffff); | |
335574df | 4217 | ip->complete_p = 1; |
df58fc94 | 4218 | } |
15be625d CM |
4219 | break; |
4220 | ||
4221 | case BFD_RELOC_MIPS16_JMP: | |
4222 | if ((address_expr->X_add_number & 3) != 0) | |
4223 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4224 | (unsigned long) address_expr->X_add_number); | |
4225 | ip->insn_opcode |= | |
4226 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4227 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4228 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4229 | ip->complete_p = 1; |
15be625d CM |
4230 | break; |
4231 | ||
4232 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4233 | { |
4234 | int shift; | |
4235 | ||
4236 | shift = mips_opts.micromips ? 1 : 2; | |
4237 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4238 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4239 | (unsigned long) address_expr->X_add_number); | |
4240 | if (!mips_relax_branch) | |
4241 | { | |
4242 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4243 | & ~((1 << (shift + 16)) - 1)) | |
4244 | as_bad (_("branch address range overflow (0x%lx)"), | |
4245 | (unsigned long) address_expr->X_add_number); | |
4246 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4247 | & 0xffff); | |
4248 | } | |
df58fc94 | 4249 | } |
15be625d CM |
4250 | break; |
4251 | ||
4252 | default: | |
b886a2ab RS |
4253 | { |
4254 | offsetT value; | |
4255 | ||
4256 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4257 | &value)) | |
4258 | { | |
4259 | ip->insn_opcode |= value & 0xffff; | |
4260 | ip->complete_p = 1; | |
4261 | } | |
4262 | } | |
4263 | break; | |
4264 | } | |
15be625d CM |
4265 | } |
4266 | ||
71400594 RS |
4267 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4268 | { | |
4269 | /* There are a lot of optimizations we could do that we don't. | |
4270 | In particular, we do not, in general, reorder instructions. | |
4271 | If you use gcc with optimization, it will reorder | |
4272 | instructions and generally do much more optimization then we | |
4273 | do here; repeating all that work in the assembler would only | |
4274 | benefit hand written assembly code, and does not seem worth | |
4275 | it. */ | |
4276 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4277 | ? nops_for_insn (0, history, NULL) |
4278 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4279 | if (nops > 0) |
252b5132 RH |
4280 | { |
4281 | fragS *old_frag; | |
4282 | unsigned long old_frag_offset; | |
4283 | int i; | |
252b5132 RH |
4284 | |
4285 | old_frag = frag_now; | |
4286 | old_frag_offset = frag_now_fix (); | |
4287 | ||
4288 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4289 | add_fixed_insn (NOP_INSN); |
4290 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4291 | |
4292 | if (listing) | |
4293 | { | |
4294 | listing_prev_line (); | |
4295 | /* We may be at the start of a variant frag. In case we | |
4296 | are, make sure there is enough space for the frag | |
4297 | after the frags created by listing_prev_line. The | |
4298 | argument to frag_grow here must be at least as large | |
4299 | as the argument to all other calls to frag_grow in | |
4300 | this file. We don't have to worry about being in the | |
4301 | middle of a variant frag, because the variants insert | |
4302 | all needed nop instructions themselves. */ | |
4303 | frag_grow (40); | |
4304 | } | |
4305 | ||
462427c4 | 4306 | mips_move_text_labels (); |
252b5132 RH |
4307 | |
4308 | #ifndef NO_ECOFF_DEBUGGING | |
4309 | if (ECOFF_DEBUGGING) | |
4310 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4311 | #endif | |
4312 | } | |
71400594 RS |
4313 | } |
4314 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4315 | { | |
932d1a1b RS |
4316 | int nops; |
4317 | ||
4318 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4319 | ignoring hazards generated by the first prev_nop_frag_since | |
4320 | instructions. */ | |
4321 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4322 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4323 | |
71400594 RS |
4324 | /* Enforce NOPS as a minimum. */ |
4325 | if (nops > prev_nop_frag_required) | |
4326 | prev_nop_frag_required = nops; | |
252b5132 | 4327 | |
71400594 RS |
4328 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4329 | { | |
4330 | /* Settle for the current number of nops. Update the history | |
4331 | accordingly (for the benefit of any future .set reorder code). */ | |
4332 | prev_nop_frag = NULL; | |
4333 | insert_into_history (prev_nop_frag_since, | |
4334 | prev_nop_frag_holds, NOP_INSN); | |
4335 | } | |
4336 | else | |
4337 | { | |
4338 | /* Allow this instruction to replace one of the nops that was | |
4339 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4340 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4341 | prev_nop_frag_holds--; |
4342 | prev_nop_frag_since++; | |
252b5132 RH |
4343 | } |
4344 | } | |
4345 | ||
e407c74b | 4346 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4347 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4348 | |
58e2ea4d MR |
4349 | #ifdef OBJ_ELF |
4350 | /* The value passed to dwarf2_emit_insn is the distance between | |
4351 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4352 | should be recorded in the debug tables. This is normally the |
4353 | current address. | |
4354 | ||
df58fc94 RS |
4355 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4356 | addresses, so we use -1 for an address higher by one than the | |
4357 | current one. | |
e3a82c8e MR |
4358 | |
4359 | If the instruction produced is a branch that we will swap with | |
4360 | the preceding instruction, then we add the displacement by which | |
4361 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4362 | and for MIPS16/microMIPS code also prevents a debugger from |
4363 | placing a breakpoint in the middle of the branch (and corrupting | |
4364 | code if software breakpoints are used). */ | |
2b0c8b40 | 4365 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4366 | #endif |
4367 | ||
df58fc94 RS |
4368 | relax32 = (mips_relax_branch |
4369 | /* Don't try branch relaxation within .set nomacro, or within | |
4370 | .set noat if we use $at for PIC computations. If it turns | |
4371 | out that the branch was out-of-range, we'll get an error. */ | |
4372 | && !mips_opts.warn_about_macros | |
4373 | && (mips_opts.at || mips_pic == NO_PIC) | |
4374 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4375 | branches. */ | |
40209cad | 4376 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4377 | |
4378 | if (!HAVE_CODE_COMPRESSION | |
4379 | && address_expr | |
4380 | && relax32 | |
0b25d3e6 | 4381 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4382 | && delayed_branch_p (ip)) |
4a6a3df4 | 4383 | { |
895921c9 | 4384 | relaxed_branch = TRUE; |
1e915849 RS |
4385 | add_relaxed_insn (ip, (relaxed_branch_length |
4386 | (NULL, NULL, | |
11625dd8 RS |
4387 | uncond_branch_p (ip) ? -1 |
4388 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4389 | : 0)), 4, |
4390 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4391 | (AT, |
11625dd8 RS |
4392 | uncond_branch_p (ip), |
4393 | branch_likely_p (ip), | |
1e915849 RS |
4394 | pinfo & INSN_WRITE_GPR_31, |
4395 | 0), | |
4396 | address_expr->X_add_symbol, | |
4397 | address_expr->X_add_number); | |
4a6a3df4 AO |
4398 | *reloc_type = BFD_RELOC_UNUSED; |
4399 | } | |
df58fc94 RS |
4400 | else if (mips_opts.micromips |
4401 | && address_expr | |
4402 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4403 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4404 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4405 | /* Don't try branch relaxation when users specify | |
4406 | 16-bit/32-bit instructions. */ | |
4407 | && !forced_insn_length) | |
df58fc94 RS |
4408 | { |
4409 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4410 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4411 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4412 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4413 | int al = pinfo & INSN_WRITE_GPR_31; |
4414 | int length32; | |
4415 | ||
4416 | gas_assert (address_expr != NULL); | |
4417 | gas_assert (!mips_relax.sequence); | |
4418 | ||
2b0c8b40 | 4419 | relaxed_branch = TRUE; |
df58fc94 RS |
4420 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4421 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4422 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4423 | relax32, 0, 0), | |
df58fc94 RS |
4424 | address_expr->X_add_symbol, |
4425 | address_expr->X_add_number); | |
4426 | *reloc_type = BFD_RELOC_UNUSED; | |
4427 | } | |
4428 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4429 | { |
4430 | /* We need to set up a variant frag. */ | |
df58fc94 | 4431 | gas_assert (address_expr != NULL); |
1e915849 RS |
4432 | add_relaxed_insn (ip, 4, 0, |
4433 | RELAX_MIPS16_ENCODE | |
4434 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4435 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4436 | delayed_branch_p (&history[0]), |
1e915849 RS |
4437 | history[0].mips16_absolute_jump_p), |
4438 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4439 | } |
5c04167a | 4440 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4441 | { |
11625dd8 | 4442 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4443 | /* Make sure there is enough room to swap this instruction with |
4444 | a following jump instruction. */ | |
4445 | frag_grow (6); | |
1e915849 | 4446 | add_fixed_insn (ip); |
252b5132 RH |
4447 | } |
4448 | else | |
4449 | { | |
4450 | if (mips_opts.mips16 | |
4451 | && mips_opts.noreorder | |
11625dd8 | 4452 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4453 | as_warn (_("extended instruction in delay slot")); |
4454 | ||
4d7206a2 RS |
4455 | if (mips_relax.sequence) |
4456 | { | |
4457 | /* If we've reached the end of this frag, turn it into a variant | |
4458 | frag and record the information for the instructions we've | |
4459 | written so far. */ | |
4460 | if (frag_room () < 4) | |
4461 | relax_close_frag (); | |
df58fc94 | 4462 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4463 | } |
4464 | ||
584892a6 | 4465 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4466 | { |
4467 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4468 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4469 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4470 | mips_macro_warning.insns[0]++; | |
4471 | } | |
584892a6 | 4472 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4473 | { |
4474 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4475 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4476 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4477 | mips_macro_warning.insns[1]++; | |
4478 | } | |
584892a6 | 4479 | |
1e915849 RS |
4480 | if (mips_opts.mips16) |
4481 | { | |
4482 | ip->fixed_p = 1; | |
4483 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4484 | } | |
4485 | add_fixed_insn (ip); | |
252b5132 RH |
4486 | } |
4487 | ||
9fe77896 | 4488 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4489 | { |
df58fc94 | 4490 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4491 | reloc_howto_type *howto0; |
9fe77896 RS |
4492 | reloc_howto_type *howto; |
4493 | int i; | |
34ce925e | 4494 | |
df58fc94 RS |
4495 | /* Perform any necessary conversion to microMIPS relocations |
4496 | and find out how many relocations there actually are. */ | |
4497 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4498 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4499 | ||
9fe77896 RS |
4500 | /* In a compound relocation, it is the final (outermost) |
4501 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4502 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4503 | ||
9fe77896 RS |
4504 | if (howto == NULL) |
4505 | { | |
4506 | /* To reproduce this failure try assembling gas/testsuites/ | |
4507 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4508 | assembler. */ | |
df58fc94 RS |
4509 | as_bad (_("Unsupported MIPS relocation number %d"), |
4510 | final_type[i - 1]); | |
9fe77896 RS |
4511 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4512 | } | |
2309ddf2 MR |
4513 | |
4514 | if (i > 1) | |
4515 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4516 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4517 | bfd_get_reloc_size (howto), | |
4518 | address_expr, | |
2309ddf2 MR |
4519 | howto0 && howto0->pc_relative, |
4520 | final_type[0]); | |
9fe77896 RS |
4521 | |
4522 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4523 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4524 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4525 | ||
4526 | /* These relocations can have an addend that won't fit in | |
4527 | 4 octets for 64bit assembly. */ | |
4528 | if (HAVE_64BIT_GPRS | |
4529 | && ! howto->partial_inplace | |
4530 | && (reloc_type[0] == BFD_RELOC_16 | |
4531 | || reloc_type[0] == BFD_RELOC_32 | |
4532 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4533 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4534 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4535 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4536 | || reloc_type[0] == BFD_RELOC_64 | |
4537 | || reloc_type[0] == BFD_RELOC_CTOR | |
4538 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4539 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4540 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4541 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4542 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4543 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4544 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4545 | || hi16_reloc_p (reloc_type[0]) | |
4546 | || lo16_reloc_p (reloc_type[0]))) | |
4547 | ip->fixp[0]->fx_no_overflow = 1; | |
4548 | ||
ddaf2c41 MR |
4549 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4550 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4551 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4552 | ip->fixp[0]->fx_no_overflow = 1; | |
4553 | ||
9fe77896 RS |
4554 | if (mips_relax.sequence) |
4555 | { | |
4556 | if (mips_relax.first_fixup == 0) | |
4557 | mips_relax.first_fixup = ip->fixp[0]; | |
4558 | } | |
4559 | else if (reloc_needs_lo_p (*reloc_type)) | |
4560 | { | |
4561 | struct mips_hi_fixup *hi_fixup; | |
4562 | ||
4563 | /* Reuse the last entry if it already has a matching %lo. */ | |
4564 | hi_fixup = mips_hi_fixup_list; | |
4565 | if (hi_fixup == 0 | |
4566 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4567 | { |
9fe77896 RS |
4568 | hi_fixup = ((struct mips_hi_fixup *) |
4569 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4570 | hi_fixup->next = mips_hi_fixup_list; | |
4571 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4572 | } |
9fe77896 RS |
4573 | hi_fixup->fixp = ip->fixp[0]; |
4574 | hi_fixup->seg = now_seg; | |
4575 | } | |
252b5132 | 4576 | |
9fe77896 RS |
4577 | /* Add fixups for the second and third relocations, if given. |
4578 | Note that the ABI allows the second relocation to be | |
4579 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4580 | moment we only use RSS_UNDEF, but we could add support | |
4581 | for the others if it ever becomes necessary. */ | |
4582 | for (i = 1; i < 3; i++) | |
4583 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4584 | { | |
4585 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4586 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4587 | FALSE, final_type[i]); |
f6688943 | 4588 | |
9fe77896 RS |
4589 | /* Use fx_tcbit to mark compound relocs. */ |
4590 | ip->fixp[0]->fx_tcbit = 1; | |
4591 | ip->fixp[i]->fx_tcbit = 1; | |
4592 | } | |
252b5132 | 4593 | } |
1e915849 | 4594 | install_insn (ip); |
252b5132 RH |
4595 | |
4596 | /* Update the register mask information. */ | |
4c260379 RS |
4597 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4598 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4599 | |
a4e06468 | 4600 | switch (method) |
252b5132 | 4601 | { |
a4e06468 RS |
4602 | case APPEND_ADD: |
4603 | insert_into_history (0, 1, ip); | |
4604 | break; | |
4605 | ||
4606 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4607 | { |
4608 | struct mips_cl_insn *nop; | |
4609 | ||
4610 | insert_into_history (0, 1, ip); | |
4611 | nop = get_delay_slot_nop (ip); | |
4612 | add_fixed_insn (nop); | |
4613 | insert_into_history (0, 1, nop); | |
4614 | if (mips_relax.sequence) | |
4615 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4616 | } | |
a4e06468 RS |
4617 | break; |
4618 | ||
4619 | case APPEND_ADD_COMPACT: | |
4620 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4621 | gas_assert (mips_opts.mips16); | |
4622 | ip->insn_opcode |= 0x0080; | |
4623 | find_altered_mips16_opcode (ip); | |
4624 | install_insn (ip); | |
4625 | insert_into_history (0, 1, ip); | |
4626 | break; | |
4627 | ||
4628 | case APPEND_SWAP: | |
4629 | { | |
4630 | struct mips_cl_insn delay = history[0]; | |
4631 | if (mips_opts.mips16) | |
4632 | { | |
4633 | know (delay.frag == ip->frag); | |
4634 | move_insn (ip, delay.frag, delay.where); | |
4635 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4636 | } | |
464ab0e5 | 4637 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4638 | { |
4639 | /* Add the delay slot instruction to the end of the | |
4640 | current frag and shrink the fixed part of the | |
4641 | original frag. If the branch occupies the tail of | |
4642 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4643 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4644 | if (delay.frag == ip->frag) |
2b0c8b40 | 4645 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4646 | add_fixed_insn (&delay); |
4647 | } | |
4648 | else | |
4649 | { | |
2b0c8b40 MR |
4650 | move_insn (&delay, ip->frag, |
4651 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4652 | move_insn (ip, history[0].frag, history[0].where); |
4653 | } | |
4654 | history[0] = *ip; | |
4655 | delay.fixed_p = 1; | |
4656 | insert_into_history (0, 1, &delay); | |
4657 | } | |
4658 | break; | |
252b5132 RH |
4659 | } |
4660 | ||
13408f1e | 4661 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4662 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4663 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4664 | { |
4665 | unsigned int i; | |
4666 | ||
79850f26 | 4667 | mips_no_prev_insn (); |
13408f1e | 4668 | |
e407c74b | 4669 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4670 | history[i].cleared_p = 1; |
e407c74b NC |
4671 | } |
4672 | ||
df58fc94 RS |
4673 | /* We need to emit a label at the end of branch-likely macros. */ |
4674 | if (emit_branch_likely_macro) | |
4675 | { | |
4676 | emit_branch_likely_macro = FALSE; | |
4677 | micromips_add_label (); | |
4678 | } | |
4679 | ||
252b5132 RH |
4680 | /* We just output an insn, so the next one doesn't have a label. */ |
4681 | mips_clear_insn_labels (); | |
252b5132 RH |
4682 | } |
4683 | ||
e407c74b NC |
4684 | /* Forget that there was any previous instruction or label. |
4685 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4686 | |
4687 | static void | |
7d10b47d | 4688 | mips_no_prev_insn (void) |
252b5132 | 4689 | { |
7d10b47d RS |
4690 | prev_nop_frag = NULL; |
4691 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4692 | mips_clear_insn_labels (); |
4693 | } | |
4694 | ||
7d10b47d RS |
4695 | /* This function must be called before we emit something other than |
4696 | instructions. It is like mips_no_prev_insn except that it inserts | |
4697 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4698 | |
7d10b47d RS |
4699 | void |
4700 | mips_emit_delays (void) | |
252b5132 RH |
4701 | { |
4702 | if (! mips_opts.noreorder) | |
4703 | { | |
932d1a1b | 4704 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4705 | if (nops > 0) |
4706 | { | |
7d10b47d RS |
4707 | while (nops-- > 0) |
4708 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4709 | mips_move_text_labels (); |
7d10b47d RS |
4710 | } |
4711 | } | |
4712 | mips_no_prev_insn (); | |
4713 | } | |
4714 | ||
4715 | /* Start a (possibly nested) noreorder block. */ | |
4716 | ||
4717 | static void | |
4718 | start_noreorder (void) | |
4719 | { | |
4720 | if (mips_opts.noreorder == 0) | |
4721 | { | |
4722 | unsigned int i; | |
4723 | int nops; | |
4724 | ||
4725 | /* None of the instructions before the .set noreorder can be moved. */ | |
4726 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4727 | history[i].fixed_p = 1; | |
4728 | ||
4729 | /* Insert any nops that might be needed between the .set noreorder | |
4730 | block and the previous instructions. We will later remove any | |
4731 | nops that turn out not to be needed. */ | |
932d1a1b | 4732 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4733 | if (nops > 0) |
4734 | { | |
4735 | if (mips_optimize != 0) | |
252b5132 RH |
4736 | { |
4737 | /* Record the frag which holds the nop instructions, so | |
4738 | that we can remove them if we don't need them. */ | |
df58fc94 | 4739 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4740 | prev_nop_frag = frag_now; |
4741 | prev_nop_frag_holds = nops; | |
4742 | prev_nop_frag_required = 0; | |
4743 | prev_nop_frag_since = 0; | |
4744 | } | |
4745 | ||
4746 | for (; nops > 0; --nops) | |
1e915849 | 4747 | add_fixed_insn (NOP_INSN); |
252b5132 | 4748 | |
7d10b47d RS |
4749 | /* Move on to a new frag, so that it is safe to simply |
4750 | decrease the size of prev_nop_frag. */ | |
4751 | frag_wane (frag_now); | |
4752 | frag_new (0); | |
462427c4 | 4753 | mips_move_text_labels (); |
252b5132 | 4754 | } |
df58fc94 | 4755 | mips_mark_labels (); |
7d10b47d | 4756 | mips_clear_insn_labels (); |
252b5132 | 4757 | } |
7d10b47d RS |
4758 | mips_opts.noreorder++; |
4759 | mips_any_noreorder = 1; | |
4760 | } | |
252b5132 | 4761 | |
7d10b47d | 4762 | /* End a nested noreorder block. */ |
252b5132 | 4763 | |
7d10b47d RS |
4764 | static void |
4765 | end_noreorder (void) | |
4766 | { | |
4767 | mips_opts.noreorder--; | |
4768 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4769 | { | |
4770 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4771 | handling nop insertion the .set reorder way. */ | |
4772 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4773 | * NOP_INSN_SIZE); |
7d10b47d RS |
4774 | insert_into_history (prev_nop_frag_since, |
4775 | prev_nop_frag_required, NOP_INSN); | |
4776 | prev_nop_frag = NULL; | |
4777 | } | |
252b5132 RH |
4778 | } |
4779 | ||
584892a6 RS |
4780 | /* Set up global variables for the start of a new macro. */ |
4781 | ||
4782 | static void | |
4783 | macro_start (void) | |
4784 | { | |
4785 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4786 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4787 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4788 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4789 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4790 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4791 | switch (history[0].insn_mo->pinfo2 |
4792 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4793 | { | |
4794 | case INSN2_BRANCH_DELAY_32BIT: | |
4795 | mips_macro_warning.delay_slot_length = 4; | |
4796 | break; | |
4797 | case INSN2_BRANCH_DELAY_16BIT: | |
4798 | mips_macro_warning.delay_slot_length = 2; | |
4799 | break; | |
4800 | default: | |
4801 | mips_macro_warning.delay_slot_length = 0; | |
4802 | break; | |
4803 | } | |
4804 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4805 | } |
4806 | ||
df58fc94 RS |
4807 | /* Given that a macro is longer than one instruction or of the wrong size, |
4808 | return the appropriate warning for it. Return null if no warning is | |
4809 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4810 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4811 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4812 | |
4813 | static const char * | |
4814 | macro_warning (relax_substateT subtype) | |
4815 | { | |
4816 | if (subtype & RELAX_DELAY_SLOT) | |
4817 | return _("Macro instruction expanded into multiple instructions" | |
4818 | " in a branch delay slot"); | |
4819 | else if (subtype & RELAX_NOMACRO) | |
4820 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4821 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4822 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4823 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4824 | ? _("Macro instruction expanded into a wrong size instruction" | |
4825 | " in a 16-bit branch delay slot") | |
4826 | : _("Macro instruction expanded into a wrong size instruction" | |
4827 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4828 | else |
4829 | return 0; | |
4830 | } | |
4831 | ||
4832 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4833 | ||
4834 | static void | |
4835 | macro_end (void) | |
4836 | { | |
df58fc94 RS |
4837 | /* Relaxation warning flags. */ |
4838 | relax_substateT subtype = 0; | |
4839 | ||
4840 | /* Check delay slot size requirements. */ | |
4841 | if (mips_macro_warning.delay_slot_length == 2) | |
4842 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4843 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4844 | { |
df58fc94 RS |
4845 | if (mips_macro_warning.delay_slot_length |
4846 | != mips_macro_warning.first_insn_sizes[0]) | |
4847 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4848 | if (mips_macro_warning.delay_slot_length | |
4849 | != mips_macro_warning.first_insn_sizes[1]) | |
4850 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4851 | } | |
584892a6 | 4852 | |
df58fc94 RS |
4853 | /* Check instruction count requirements. */ |
4854 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4855 | { | |
4856 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4857 | subtype |= RELAX_SECOND_LONGER; |
4858 | if (mips_opts.warn_about_macros) | |
4859 | subtype |= RELAX_NOMACRO; | |
4860 | if (mips_macro_warning.delay_slot_p) | |
4861 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4862 | } |
584892a6 | 4863 | |
df58fc94 RS |
4864 | /* If both alternatives fail to fill a delay slot correctly, |
4865 | emit the warning now. */ | |
4866 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4867 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4868 | { | |
4869 | relax_substateT s; | |
4870 | const char *msg; | |
4871 | ||
4872 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4873 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4874 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4875 | msg = macro_warning (s); | |
4876 | if (msg != NULL) | |
4877 | as_warn ("%s", msg); | |
4878 | subtype &= ~s; | |
4879 | } | |
4880 | ||
4881 | /* If both implementations are longer than 1 instruction, then emit the | |
4882 | warning now. */ | |
4883 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4884 | { | |
4885 | relax_substateT s; | |
4886 | const char *msg; | |
4887 | ||
4888 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4889 | msg = macro_warning (s); | |
4890 | if (msg != NULL) | |
4891 | as_warn ("%s", msg); | |
4892 | subtype &= ~s; | |
584892a6 | 4893 | } |
df58fc94 RS |
4894 | |
4895 | /* If any flags still set, then one implementation might need a warning | |
4896 | and the other either will need one of a different kind or none at all. | |
4897 | Pass any remaining flags over to relaxation. */ | |
4898 | if (mips_macro_warning.first_frag != NULL) | |
4899 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4900 | } |
4901 | ||
df58fc94 RS |
4902 | /* Instruction operand formats used in macros that vary between |
4903 | standard MIPS and microMIPS code. */ | |
4904 | ||
4905 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4906 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4907 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4908 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4909 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4910 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4911 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4912 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4913 | ||
4914 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4915 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4916 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4917 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4918 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4919 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4920 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4921 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4922 | ||
6e1304d8 RS |
4923 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4924 | The first argument in *ARGS will be either the code for a single | |
4925 | relocation or -1 followed by the three codes that make up a | |
4926 | composite relocation. */ | |
4927 | ||
4928 | static void | |
4929 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4930 | { | |
4931 | int i, next; | |
4932 | ||
4933 | next = va_arg (*args, int); | |
4934 | if (next >= 0) | |
4935 | r[0] = (bfd_reloc_code_real_type) next; | |
4936 | else | |
4937 | for (i = 0; i < 3; i++) | |
4938 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4939 | } | |
4940 | ||
252b5132 RH |
4941 | /* Build an instruction created by a macro expansion. This is passed |
4942 | a pointer to the count of instructions created so far, an | |
4943 | expression, the name of the instruction to build, an operand format | |
4944 | string, and corresponding arguments. */ | |
4945 | ||
252b5132 | 4946 | static void |
67c0d1eb | 4947 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4948 | { |
df58fc94 | 4949 | const struct mips_opcode *mo = NULL; |
f6688943 | 4950 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4951 | const struct mips_opcode *amo; |
4952 | struct hash_control *hash; | |
4953 | struct mips_cl_insn insn; | |
252b5132 | 4954 | va_list args; |
252b5132 | 4955 | |
252b5132 | 4956 | va_start (args, fmt); |
252b5132 | 4957 | |
252b5132 RH |
4958 | if (mips_opts.mips16) |
4959 | { | |
03ea81db | 4960 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4961 | va_end (args); |
4962 | return; | |
4963 | } | |
4964 | ||
f6688943 TS |
4965 | r[0] = BFD_RELOC_UNUSED; |
4966 | r[1] = BFD_RELOC_UNUSED; | |
4967 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4968 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4969 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4970 | gas_assert (amo); | |
4971 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4972 | |
df58fc94 | 4973 | do |
8b082fb1 TS |
4974 | { |
4975 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4976 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4977 | We try to match an instruction that fulfils the branch delay | |
4978 | slot instruction length requirement (if any) of the previous | |
4979 | instruction. While doing this we record the first instruction | |
4980 | seen that matches all the other conditions and use it anyway | |
4981 | if the requirement cannot be met; we will issue an appropriate | |
4982 | warning later on. */ | |
4983 | if (strcmp (fmt, amo->args) == 0 | |
4984 | && amo->pinfo != INSN_MACRO | |
4985 | && is_opcode_valid (amo) | |
4986 | && is_size_valid (amo)) | |
4987 | { | |
4988 | if (is_delay_slot_valid (amo)) | |
4989 | { | |
4990 | mo = amo; | |
4991 | break; | |
4992 | } | |
4993 | else if (!mo) | |
4994 | mo = amo; | |
4995 | } | |
8b082fb1 | 4996 | |
df58fc94 RS |
4997 | ++amo; |
4998 | gas_assert (amo->name); | |
252b5132 | 4999 | } |
df58fc94 | 5000 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5001 | |
df58fc94 | 5002 | gas_assert (mo); |
1e915849 | 5003 | create_insn (&insn, mo); |
252b5132 RH |
5004 | for (;;) |
5005 | { | |
5006 | switch (*fmt++) | |
5007 | { | |
5008 | case '\0': | |
5009 | break; | |
5010 | ||
5011 | case ',': | |
5012 | case '(': | |
5013 | case ')': | |
5014 | continue; | |
5015 | ||
5f74bc13 CD |
5016 | case '+': |
5017 | switch (*fmt++) | |
5018 | { | |
5019 | case 'A': | |
5020 | case 'E': | |
df58fc94 RS |
5021 | INSERT_OPERAND (mips_opts.micromips, |
5022 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5023 | continue; |
5024 | ||
5025 | case 'B': | |
5026 | case 'F': | |
5027 | /* Note that in the macro case, these arguments are already | |
5028 | in MSB form. (When handling the instruction in the | |
5029 | non-macro case, these arguments are sizes from which | |
5030 | MSB values must be calculated.) */ | |
df58fc94 RS |
5031 | INSERT_OPERAND (mips_opts.micromips, |
5032 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5033 | continue; |
5034 | ||
5035 | case 'C': | |
5036 | case 'G': | |
5037 | case 'H': | |
5038 | /* Note that in the macro case, these arguments are already | |
5039 | in MSBD form. (When handling the instruction in the | |
5040 | non-macro case, these arguments are sizes from which | |
5041 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5042 | INSERT_OPERAND (mips_opts.micromips, |
5043 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5044 | continue; |
5045 | ||
dd3cbb7e | 5046 | case 'Q': |
df58fc94 RS |
5047 | gas_assert (!mips_opts.micromips); |
5048 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5049 | continue; |
5050 | ||
5f74bc13 | 5051 | default: |
b37df7c4 | 5052 | abort (); |
5f74bc13 CD |
5053 | } |
5054 | continue; | |
5055 | ||
8b082fb1 | 5056 | case '2': |
03f66e8a | 5057 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5058 | continue; |
5059 | ||
df58fc94 RS |
5060 | case 'n': |
5061 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5062 | case 't': |
5063 | case 'w': | |
5064 | case 'E': | |
df58fc94 | 5065 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5066 | continue; |
5067 | ||
5068 | case 'c': | |
df58fc94 RS |
5069 | gas_assert (!mips_opts.micromips); |
5070 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5071 | continue; |
5072 | ||
252b5132 | 5073 | case 'W': |
df58fc94 RS |
5074 | gas_assert (!mips_opts.micromips); |
5075 | case 'T': | |
5076 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5077 | continue; |
5078 | ||
252b5132 | 5079 | case 'G': |
df58fc94 RS |
5080 | if (mips_opts.micromips) |
5081 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5082 | else | |
5083 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5084 | continue; | |
5085 | ||
af7ee8bf | 5086 | case 'K': |
df58fc94 RS |
5087 | gas_assert (!mips_opts.micromips); |
5088 | case 'd': | |
5089 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5090 | continue; |
5091 | ||
4372b673 | 5092 | case 'U': |
df58fc94 | 5093 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5094 | { |
5095 | int tmp = va_arg (args, int); | |
5096 | ||
df58fc94 RS |
5097 | INSERT_OPERAND (0, RT, insn, tmp); |
5098 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5099 | } |
df58fc94 | 5100 | continue; |
4372b673 | 5101 | |
252b5132 RH |
5102 | case 'V': |
5103 | case 'S': | |
df58fc94 RS |
5104 | gas_assert (!mips_opts.micromips); |
5105 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5106 | continue; |
5107 | ||
5108 | case 'z': | |
5109 | continue; | |
5110 | ||
5111 | case '<': | |
df58fc94 RS |
5112 | INSERT_OPERAND (mips_opts.micromips, |
5113 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5114 | continue; |
5115 | ||
5116 | case 'D': | |
df58fc94 RS |
5117 | gas_assert (!mips_opts.micromips); |
5118 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5119 | continue; |
5120 | ||
5121 | case 'B': | |
df58fc94 RS |
5122 | gas_assert (!mips_opts.micromips); |
5123 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5124 | continue; |
5125 | ||
4372b673 | 5126 | case 'J': |
df58fc94 RS |
5127 | gas_assert (!mips_opts.micromips); |
5128 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5129 | continue; |
5130 | ||
252b5132 | 5131 | case 'q': |
df58fc94 RS |
5132 | gas_assert (!mips_opts.micromips); |
5133 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5134 | continue; |
5135 | ||
5136 | case 'b': | |
5137 | case 's': | |
5138 | case 'r': | |
5139 | case 'v': | |
df58fc94 | 5140 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5141 | continue; |
5142 | ||
5143 | case 'i': | |
5144 | case 'j': | |
6e1304d8 | 5145 | macro_read_relocs (&args, r); |
9c2799c2 | 5146 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5147 | || *r == BFD_RELOC_MIPS_HIGHER |
5148 | || *r == BFD_RELOC_HI16_S | |
5149 | || *r == BFD_RELOC_LO16 | |
5150 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5151 | continue; | |
5152 | ||
5153 | case 'o': | |
5154 | macro_read_relocs (&args, r); | |
252b5132 RH |
5155 | continue; |
5156 | ||
5157 | case 'u': | |
6e1304d8 | 5158 | macro_read_relocs (&args, r); |
9c2799c2 | 5159 | gas_assert (ep != NULL |
90ecf173 MR |
5160 | && (ep->X_op == O_constant |
5161 | || (ep->X_op == O_symbol | |
5162 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5163 | || *r == BFD_RELOC_HI16_S | |
5164 | || *r == BFD_RELOC_HI16 | |
5165 | || *r == BFD_RELOC_GPREL16 | |
5166 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5167 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5168 | continue; |
5169 | ||
5170 | case 'p': | |
9c2799c2 | 5171 | gas_assert (ep != NULL); |
bad36eac | 5172 | |
252b5132 RH |
5173 | /* |
5174 | * This allows macro() to pass an immediate expression for | |
5175 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5176 | * |
5177 | * We don't allow branch relaxation for these branches, as | |
5178 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5179 | */ |
5180 | if (ep->X_op == O_constant) | |
5181 | { | |
df58fc94 RS |
5182 | /* For microMIPS we always use relocations for branches. |
5183 | So we should not resolve immediate values. */ | |
5184 | gas_assert (!mips_opts.micromips); | |
5185 | ||
bad36eac DJ |
5186 | if ((ep->X_add_number & 3) != 0) |
5187 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5188 | (unsigned long) ep->X_add_number); | |
5189 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5190 | as_bad (_("branch address range overflow (0x%lx)"), | |
5191 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5192 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5193 | ep = NULL; | |
5194 | } | |
5195 | else | |
0b25d3e6 | 5196 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5197 | continue; |
5198 | ||
5199 | case 'a': | |
9c2799c2 | 5200 | gas_assert (ep != NULL); |
f6688943 | 5201 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5202 | continue; |
5203 | ||
5204 | case 'C': | |
df58fc94 RS |
5205 | gas_assert (!mips_opts.micromips); |
5206 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5207 | continue; |
5208 | ||
d43b4baf | 5209 | case 'k': |
df58fc94 RS |
5210 | INSERT_OPERAND (mips_opts.micromips, |
5211 | CACHE, insn, va_arg (args, unsigned long)); | |
5212 | continue; | |
5213 | ||
5214 | case '|': | |
5215 | gas_assert (mips_opts.micromips); | |
5216 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5217 | continue; | |
5218 | ||
5219 | case '.': | |
5220 | gas_assert (mips_opts.micromips); | |
5221 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5222 | continue; | |
5223 | ||
dec0624d MR |
5224 | case '\\': |
5225 | INSERT_OPERAND (mips_opts.micromips, | |
5226 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5227 | continue; | |
5228 | ||
df58fc94 | 5229 | case '~': |
dec0624d MR |
5230 | INSERT_OPERAND (mips_opts.micromips, |
5231 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5232 | continue; |
5233 | ||
5234 | case 'N': | |
5235 | gas_assert (mips_opts.micromips); | |
5236 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5237 | continue; | |
5238 | ||
5239 | case 'm': /* Opcode extension character. */ | |
5240 | gas_assert (mips_opts.micromips); | |
5241 | switch (*fmt++) | |
5242 | { | |
5243 | case 'j': | |
5244 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5245 | break; | |
5246 | ||
5247 | case 'p': | |
5248 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5249 | break; | |
5250 | ||
5251 | case 'F': | |
5252 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5253 | break; | |
5254 | ||
5255 | default: | |
b37df7c4 | 5256 | abort (); |
df58fc94 | 5257 | } |
d43b4baf TS |
5258 | continue; |
5259 | ||
252b5132 | 5260 | default: |
b37df7c4 | 5261 | abort (); |
252b5132 RH |
5262 | } |
5263 | break; | |
5264 | } | |
5265 | va_end (args); | |
9c2799c2 | 5266 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5267 | |
df58fc94 | 5268 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5269 | } |
5270 | ||
5271 | static void | |
67c0d1eb | 5272 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5273 | va_list *args) |
252b5132 | 5274 | { |
1e915849 | 5275 | struct mips_opcode *mo; |
252b5132 | 5276 | struct mips_cl_insn insn; |
f6688943 TS |
5277 | bfd_reloc_code_real_type r[3] |
5278 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5279 | |
1e915849 | 5280 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5281 | gas_assert (mo); |
5282 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5283 | |
1e915849 | 5284 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5285 | { |
1e915849 | 5286 | ++mo; |
9c2799c2 NC |
5287 | gas_assert (mo->name); |
5288 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5289 | } |
5290 | ||
1e915849 | 5291 | create_insn (&insn, mo); |
252b5132 RH |
5292 | for (;;) |
5293 | { | |
5294 | int c; | |
5295 | ||
5296 | c = *fmt++; | |
5297 | switch (c) | |
5298 | { | |
5299 | case '\0': | |
5300 | break; | |
5301 | ||
5302 | case ',': | |
5303 | case '(': | |
5304 | case ')': | |
5305 | continue; | |
5306 | ||
5307 | case 'y': | |
5308 | case 'w': | |
03ea81db | 5309 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5310 | continue; |
5311 | ||
5312 | case 'x': | |
5313 | case 'v': | |
03ea81db | 5314 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5315 | continue; |
5316 | ||
5317 | case 'z': | |
03ea81db | 5318 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5319 | continue; |
5320 | ||
5321 | case 'Z': | |
03ea81db | 5322 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5323 | continue; |
5324 | ||
5325 | case '0': | |
5326 | case 'S': | |
5327 | case 'P': | |
5328 | case 'R': | |
5329 | continue; | |
5330 | ||
5331 | case 'X': | |
03ea81db | 5332 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5333 | continue; |
5334 | ||
5335 | case 'Y': | |
5336 | { | |
5337 | int regno; | |
5338 | ||
03ea81db | 5339 | regno = va_arg (*args, int); |
252b5132 | 5340 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5341 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5342 | } |
5343 | continue; | |
5344 | ||
5345 | case '<': | |
5346 | case '>': | |
5347 | case '4': | |
5348 | case '5': | |
5349 | case 'H': | |
5350 | case 'W': | |
5351 | case 'D': | |
5352 | case 'j': | |
5353 | case '8': | |
5354 | case 'V': | |
5355 | case 'C': | |
5356 | case 'U': | |
5357 | case 'k': | |
5358 | case 'K': | |
5359 | case 'p': | |
5360 | case 'q': | |
5361 | { | |
b886a2ab RS |
5362 | offsetT value; |
5363 | ||
9c2799c2 | 5364 | gas_assert (ep != NULL); |
252b5132 RH |
5365 | |
5366 | if (ep->X_op != O_constant) | |
874e8986 | 5367 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5368 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5369 | { |
b886a2ab | 5370 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5371 | ep = NULL; |
f6688943 | 5372 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5373 | } |
5374 | } | |
5375 | continue; | |
5376 | ||
5377 | case '6': | |
03ea81db | 5378 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5379 | continue; |
5380 | } | |
5381 | ||
5382 | break; | |
5383 | } | |
5384 | ||
9c2799c2 | 5385 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5386 | |
df58fc94 | 5387 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5388 | } |
5389 | ||
2051e8c4 MR |
5390 | /* |
5391 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5392 | * higher bits unset. | |
5393 | */ | |
9f872bbe | 5394 | static void |
2051e8c4 MR |
5395 | normalize_constant_expr (expressionS *ex) |
5396 | { | |
9ee2a2d4 | 5397 | if (ex->X_op == O_constant |
2051e8c4 MR |
5398 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5399 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5400 | - 0x80000000); | |
5401 | } | |
5402 | ||
5403 | /* | |
5404 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5405 | * all higher bits unset. | |
5406 | */ | |
5407 | static void | |
5408 | normalize_address_expr (expressionS *ex) | |
5409 | { | |
5410 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5411 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5412 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5413 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5414 | - 0x80000000); | |
5415 | } | |
5416 | ||
438c16b8 TS |
5417 | /* |
5418 | * Generate a "jalr" instruction with a relocation hint to the called | |
5419 | * function. This occurs in NewABI PIC code. | |
5420 | */ | |
5421 | static void | |
df58fc94 | 5422 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5423 | { |
df58fc94 RS |
5424 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5425 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5426 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5427 | const char *jalr; | |
685736be | 5428 | char *f = NULL; |
b34976b6 | 5429 | |
1180b5a4 | 5430 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5431 | { |
cc3d92a5 | 5432 | frag_grow (8); |
f21f8242 AO |
5433 | f = frag_more (0); |
5434 | } | |
2906b037 | 5435 | if (mips_opts.micromips) |
df58fc94 RS |
5436 | { |
5437 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5438 | if (MIPS_JALR_HINT_P (ep) |
5439 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5440 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5441 | else | |
5442 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5443 | } | |
2906b037 MR |
5444 | else |
5445 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5446 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5447 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5448 | } |
5449 | ||
252b5132 RH |
5450 | /* |
5451 | * Generate a "lui" instruction. | |
5452 | */ | |
5453 | static void | |
67c0d1eb | 5454 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5455 | { |
9c2799c2 | 5456 | gas_assert (! mips_opts.mips16); |
252b5132 | 5457 | |
df58fc94 | 5458 | if (ep->X_op != O_constant) |
252b5132 | 5459 | { |
9c2799c2 | 5460 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5461 | /* _gp_disp is a special case, used from s_cpload. |
5462 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5463 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5464 | || (! HAVE_NEWABI |
aa6975fb ILT |
5465 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5466 | || (! mips_in_shared | |
bbe506e8 TS |
5467 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5468 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5469 | } |
5470 | ||
df58fc94 | 5471 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5472 | } |
5473 | ||
885add95 CD |
5474 | /* Generate a sequence of instructions to do a load or store from a constant |
5475 | offset off of a base register (breg) into/from a target register (treg), | |
5476 | using AT if necessary. */ | |
5477 | static void | |
67c0d1eb RS |
5478 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5479 | int treg, int breg, int dbl) | |
885add95 | 5480 | { |
9c2799c2 | 5481 | gas_assert (ep->X_op == O_constant); |
885add95 | 5482 | |
256ab948 | 5483 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5484 | if (!dbl) |
5485 | normalize_constant_expr (ep); | |
256ab948 | 5486 | |
67c1ffbe | 5487 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5488 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5489 | as_warn (_("operand overflow")); |
5490 | ||
5491 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5492 | { | |
5493 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5494 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5495 | } |
5496 | else | |
5497 | { | |
5498 | /* 32-bit offset, need multiple instructions and AT, like: | |
5499 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5500 | addu $tempreg,$tempreg,$breg | |
5501 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5502 | to handle the complete offset. */ | |
67c0d1eb RS |
5503 | macro_build_lui (ep, AT); |
5504 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5505 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5506 | |
741fe287 | 5507 | if (!mips_opts.at) |
8fc2e39e | 5508 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5509 | } |
5510 | } | |
5511 | ||
252b5132 RH |
5512 | /* set_at() |
5513 | * Generates code to set the $at register to true (one) | |
5514 | * if reg is less than the immediate expression. | |
5515 | */ | |
5516 | static void | |
67c0d1eb | 5517 | set_at (int reg, int unsignedp) |
252b5132 RH |
5518 | { |
5519 | if (imm_expr.X_op == O_constant | |
5520 | && imm_expr.X_add_number >= -0x8000 | |
5521 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5522 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5523 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5524 | else |
5525 | { | |
67c0d1eb RS |
5526 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5527 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5528 | } |
5529 | } | |
5530 | ||
5531 | /* Warn if an expression is not a constant. */ | |
5532 | ||
5533 | static void | |
17a2f251 | 5534 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5535 | { |
5536 | if (ex->X_op == O_big) | |
5537 | as_bad (_("unsupported large constant")); | |
5538 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5539 | as_bad (_("Instruction %s requires absolute expression"), |
5540 | ip->insn_mo->name); | |
13757d0c | 5541 | |
9ee2a2d4 MR |
5542 | if (HAVE_32BIT_GPRS) |
5543 | normalize_constant_expr (ex); | |
252b5132 RH |
5544 | } |
5545 | ||
5546 | /* Count the leading zeroes by performing a binary chop. This is a | |
5547 | bulky bit of source, but performance is a LOT better for the | |
5548 | majority of values than a simple loop to count the bits: | |
5549 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5550 | if ((v) & (1 << (31 - lcnt))) | |
5551 | break; | |
5552 | However it is not code size friendly, and the gain will drop a bit | |
5553 | on certain cached systems. | |
5554 | */ | |
5555 | #define COUNT_TOP_ZEROES(v) \ | |
5556 | (((v) & ~0xffff) == 0 \ | |
5557 | ? ((v) & ~0xff) == 0 \ | |
5558 | ? ((v) & ~0xf) == 0 \ | |
5559 | ? ((v) & ~0x3) == 0 \ | |
5560 | ? ((v) & ~0x1) == 0 \ | |
5561 | ? !(v) \ | |
5562 | ? 32 \ | |
5563 | : 31 \ | |
5564 | : 30 \ | |
5565 | : ((v) & ~0x7) == 0 \ | |
5566 | ? 29 \ | |
5567 | : 28 \ | |
5568 | : ((v) & ~0x3f) == 0 \ | |
5569 | ? ((v) & ~0x1f) == 0 \ | |
5570 | ? 27 \ | |
5571 | : 26 \ | |
5572 | : ((v) & ~0x7f) == 0 \ | |
5573 | ? 25 \ | |
5574 | : 24 \ | |
5575 | : ((v) & ~0xfff) == 0 \ | |
5576 | ? ((v) & ~0x3ff) == 0 \ | |
5577 | ? ((v) & ~0x1ff) == 0 \ | |
5578 | ? 23 \ | |
5579 | : 22 \ | |
5580 | : ((v) & ~0x7ff) == 0 \ | |
5581 | ? 21 \ | |
5582 | : 20 \ | |
5583 | : ((v) & ~0x3fff) == 0 \ | |
5584 | ? ((v) & ~0x1fff) == 0 \ | |
5585 | ? 19 \ | |
5586 | : 18 \ | |
5587 | : ((v) & ~0x7fff) == 0 \ | |
5588 | ? 17 \ | |
5589 | : 16 \ | |
5590 | : ((v) & ~0xffffff) == 0 \ | |
5591 | ? ((v) & ~0xfffff) == 0 \ | |
5592 | ? ((v) & ~0x3ffff) == 0 \ | |
5593 | ? ((v) & ~0x1ffff) == 0 \ | |
5594 | ? 15 \ | |
5595 | : 14 \ | |
5596 | : ((v) & ~0x7ffff) == 0 \ | |
5597 | ? 13 \ | |
5598 | : 12 \ | |
5599 | : ((v) & ~0x3fffff) == 0 \ | |
5600 | ? ((v) & ~0x1fffff) == 0 \ | |
5601 | ? 11 \ | |
5602 | : 10 \ | |
5603 | : ((v) & ~0x7fffff) == 0 \ | |
5604 | ? 9 \ | |
5605 | : 8 \ | |
5606 | : ((v) & ~0xfffffff) == 0 \ | |
5607 | ? ((v) & ~0x3ffffff) == 0 \ | |
5608 | ? ((v) & ~0x1ffffff) == 0 \ | |
5609 | ? 7 \ | |
5610 | : 6 \ | |
5611 | : ((v) & ~0x7ffffff) == 0 \ | |
5612 | ? 5 \ | |
5613 | : 4 \ | |
5614 | : ((v) & ~0x3fffffff) == 0 \ | |
5615 | ? ((v) & ~0x1fffffff) == 0 \ | |
5616 | ? 3 \ | |
5617 | : 2 \ | |
5618 | : ((v) & ~0x7fffffff) == 0 \ | |
5619 | ? 1 \ | |
5620 | : 0) | |
5621 | ||
5622 | /* load_register() | |
67c1ffbe | 5623 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5624 | * an absolute expression value into a register. |
5625 | */ | |
5626 | static void | |
67c0d1eb | 5627 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5628 | { |
5629 | int freg; | |
5630 | expressionS hi32, lo32; | |
5631 | ||
5632 | if (ep->X_op != O_big) | |
5633 | { | |
9c2799c2 | 5634 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5635 | |
5636 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5637 | if (!dbl) |
5638 | normalize_constant_expr (ep); | |
256ab948 TS |
5639 | |
5640 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5641 | { |
5642 | /* We can handle 16 bit signed values with an addiu to | |
5643 | $zero. No need to ever use daddiu here, since $zero and | |
5644 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5645 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5646 | return; |
5647 | } | |
5648 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5649 | { | |
5650 | /* We can handle 16 bit unsigned values with an ori to | |
5651 | $zero. */ | |
67c0d1eb | 5652 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5653 | return; |
5654 | } | |
256ab948 | 5655 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5656 | { |
5657 | /* 32 bit values require an lui. */ | |
df58fc94 | 5658 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5659 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5660 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5661 | return; |
5662 | } | |
5663 | } | |
5664 | ||
5665 | /* The value is larger than 32 bits. */ | |
5666 | ||
2051e8c4 | 5667 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5668 | { |
55e08f71 NC |
5669 | char value[32]; |
5670 | ||
5671 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5672 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5673 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5674 | return; |
5675 | } | |
5676 | ||
5677 | if (ep->X_op != O_big) | |
5678 | { | |
5679 | hi32 = *ep; | |
5680 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5681 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5682 | hi32.X_add_number &= 0xffffffff; | |
5683 | lo32 = *ep; | |
5684 | lo32.X_add_number &= 0xffffffff; | |
5685 | } | |
5686 | else | |
5687 | { | |
9c2799c2 | 5688 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5689 | if (ep->X_add_number == 3) |
5690 | generic_bignum[3] = 0; | |
5691 | else if (ep->X_add_number > 4) | |
5692 | as_bad (_("Number larger than 64 bits")); | |
5693 | lo32.X_op = O_constant; | |
5694 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5695 | hi32.X_op = O_constant; | |
5696 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5697 | } | |
5698 | ||
5699 | if (hi32.X_add_number == 0) | |
5700 | freg = 0; | |
5701 | else | |
5702 | { | |
5703 | int shift, bit; | |
5704 | unsigned long hi, lo; | |
5705 | ||
956cd1d6 | 5706 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5707 | { |
5708 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5709 | { | |
67c0d1eb | 5710 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5711 | return; |
5712 | } | |
5713 | if (lo32.X_add_number & 0x80000000) | |
5714 | { | |
df58fc94 | 5715 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5716 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5717 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5718 | return; |
5719 | } | |
5720 | } | |
252b5132 RH |
5721 | |
5722 | /* Check for 16bit shifted constant. We know that hi32 is | |
5723 | non-zero, so start the mask on the first bit of the hi32 | |
5724 | value. */ | |
5725 | shift = 17; | |
5726 | do | |
beae10d5 KH |
5727 | { |
5728 | unsigned long himask, lomask; | |
5729 | ||
5730 | if (shift < 32) | |
5731 | { | |
5732 | himask = 0xffff >> (32 - shift); | |
5733 | lomask = (0xffff << shift) & 0xffffffff; | |
5734 | } | |
5735 | else | |
5736 | { | |
5737 | himask = 0xffff << (shift - 32); | |
5738 | lomask = 0; | |
5739 | } | |
5740 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5741 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5742 | { | |
5743 | expressionS tmp; | |
5744 | ||
5745 | tmp.X_op = O_constant; | |
5746 | if (shift < 32) | |
5747 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5748 | | (lo32.X_add_number >> shift)); | |
5749 | else | |
5750 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5751 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5752 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5753 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5754 | return; |
5755 | } | |
f9419b05 | 5756 | ++shift; |
beae10d5 KH |
5757 | } |
5758 | while (shift <= (64 - 16)); | |
252b5132 RH |
5759 | |
5760 | /* Find the bit number of the lowest one bit, and store the | |
5761 | shifted value in hi/lo. */ | |
5762 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5763 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5764 | if (lo != 0) | |
5765 | { | |
5766 | bit = 0; | |
5767 | while ((lo & 1) == 0) | |
5768 | { | |
5769 | lo >>= 1; | |
5770 | ++bit; | |
5771 | } | |
5772 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5773 | hi >>= bit; | |
5774 | } | |
5775 | else | |
5776 | { | |
5777 | bit = 32; | |
5778 | while ((hi & 1) == 0) | |
5779 | { | |
5780 | hi >>= 1; | |
5781 | ++bit; | |
5782 | } | |
5783 | lo = hi; | |
5784 | hi = 0; | |
5785 | } | |
5786 | ||
5787 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5788 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5789 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5790 | { |
5791 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5792 | if (shift != 0) |
beae10d5 | 5793 | { |
252b5132 RH |
5794 | expressionS tmp; |
5795 | ||
5796 | /* This instruction will set the register to be all | |
5797 | ones. */ | |
beae10d5 KH |
5798 | tmp.X_op = O_constant; |
5799 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5800 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5801 | if (bit != 0) |
5802 | { | |
5803 | bit += shift; | |
df58fc94 | 5804 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5805 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5806 | } |
df58fc94 | 5807 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5808 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5809 | return; |
5810 | } | |
5811 | } | |
252b5132 RH |
5812 | |
5813 | /* Sign extend hi32 before calling load_register, because we can | |
5814 | generally get better code when we load a sign extended value. */ | |
5815 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5816 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5817 | load_register (reg, &hi32, 0); |
252b5132 RH |
5818 | freg = reg; |
5819 | } | |
5820 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5821 | { | |
5822 | if (freg != 0) | |
5823 | { | |
df58fc94 | 5824 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5825 | freg = reg; |
5826 | } | |
5827 | } | |
5828 | else | |
5829 | { | |
5830 | expressionS mid16; | |
5831 | ||
956cd1d6 | 5832 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5833 | { |
df58fc94 RS |
5834 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5835 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5836 | return; |
5837 | } | |
252b5132 RH |
5838 | |
5839 | if (freg != 0) | |
5840 | { | |
df58fc94 | 5841 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5842 | freg = reg; |
5843 | } | |
5844 | mid16 = lo32; | |
5845 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5846 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5847 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5848 | freg = reg; |
5849 | } | |
5850 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5851 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5852 | } |
5853 | ||
269137b2 TS |
5854 | static inline void |
5855 | load_delay_nop (void) | |
5856 | { | |
5857 | if (!gpr_interlocks) | |
5858 | macro_build (NULL, "nop", ""); | |
5859 | } | |
5860 | ||
252b5132 RH |
5861 | /* Load an address into a register. */ |
5862 | ||
5863 | static void | |
67c0d1eb | 5864 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5865 | { |
252b5132 RH |
5866 | if (ep->X_op != O_constant |
5867 | && ep->X_op != O_symbol) | |
5868 | { | |
5869 | as_bad (_("expression too complex")); | |
5870 | ep->X_op = O_constant; | |
5871 | } | |
5872 | ||
5873 | if (ep->X_op == O_constant) | |
5874 | { | |
67c0d1eb | 5875 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5876 | return; |
5877 | } | |
5878 | ||
5879 | if (mips_pic == NO_PIC) | |
5880 | { | |
5881 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5882 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5883 | Otherwise we want |
5884 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5885 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5886 | If we have an addend, we always use the latter form. |
76b3015f | 5887 | |
d6bc6245 TS |
5888 | With 64bit address space and a usable $at we want |
5889 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5890 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5891 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5892 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5893 | dsll32 $reg,0 | |
3a482fd5 | 5894 | daddu $reg,$reg,$at |
76b3015f | 5895 | |
c03099e6 | 5896 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5897 | on superscalar processors. |
5898 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5899 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5900 | dsll $reg,16 | |
5901 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5902 | dsll $reg,16 | |
5903 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5904 | |
5905 | For GP relative symbols in 64bit address space we can use | |
5906 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5907 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5908 | { |
6caf9ef4 TS |
5909 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5910 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5911 | { | |
5912 | relax_start (ep->X_add_symbol); | |
5913 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5914 | mips_gp_register, BFD_RELOC_GPREL16); | |
5915 | relax_switch (); | |
5916 | } | |
d6bc6245 | 5917 | |
741fe287 | 5918 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5919 | { |
df58fc94 RS |
5920 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5921 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5922 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5923 | BFD_RELOC_MIPS_HIGHER); | |
5924 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5925 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5926 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5927 | *used_at = 1; |
5928 | } | |
5929 | else | |
5930 | { | |
df58fc94 | 5931 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5932 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5933 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5934 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5935 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5936 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5937 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5938 | } |
6caf9ef4 TS |
5939 | |
5940 | if (mips_relax.sequence) | |
5941 | relax_end (); | |
d6bc6245 | 5942 | } |
252b5132 RH |
5943 | else |
5944 | { | |
d6bc6245 | 5945 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5946 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5947 | { |
4d7206a2 | 5948 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5949 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5950 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5951 | relax_switch (); |
d6bc6245 | 5952 | } |
67c0d1eb RS |
5953 | macro_build_lui (ep, reg); |
5954 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5955 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5956 | if (mips_relax.sequence) |
5957 | relax_end (); | |
d6bc6245 | 5958 | } |
252b5132 | 5959 | } |
0a44bf69 | 5960 | else if (!mips_big_got) |
252b5132 RH |
5961 | { |
5962 | expressionS ex; | |
5963 | ||
5964 | /* If this is a reference to an external symbol, we want | |
5965 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5966 | Otherwise we want | |
5967 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5968 | nop | |
5969 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5970 | If there is a constant, it must be added in after. |
5971 | ||
ed6fb7bd | 5972 | If we have NewABI, we want |
f5040a92 AO |
5973 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5974 | unless we're referencing a global symbol with a non-zero | |
5975 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5976 | if (HAVE_NEWABI) |
5977 | { | |
f5040a92 AO |
5978 | if (ep->X_add_number) |
5979 | { | |
4d7206a2 | 5980 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5981 | ep->X_add_number = 0; |
4d7206a2 | 5982 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5983 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5984 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5985 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5986 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5987 | ex.X_op = O_constant; | |
67c0d1eb | 5988 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5989 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5990 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5991 | relax_switch (); |
f5040a92 | 5992 | } |
67c0d1eb | 5993 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5994 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5995 | if (mips_relax.sequence) |
5996 | relax_end (); | |
ed6fb7bd SC |
5997 | } |
5998 | else | |
5999 | { | |
f5040a92 AO |
6000 | ex.X_add_number = ep->X_add_number; |
6001 | ep->X_add_number = 0; | |
67c0d1eb RS |
6002 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6003 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6004 | load_delay_nop (); |
4d7206a2 RS |
6005 | relax_start (ep->X_add_symbol); |
6006 | relax_switch (); | |
67c0d1eb | 6007 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6008 | BFD_RELOC_LO16); |
4d7206a2 | 6009 | relax_end (); |
ed6fb7bd | 6010 | |
f5040a92 AO |
6011 | if (ex.X_add_number != 0) |
6012 | { | |
6013 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6014 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6015 | ex.X_op = O_constant; | |
67c0d1eb | 6016 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6017 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6018 | } |
252b5132 RH |
6019 | } |
6020 | } | |
0a44bf69 | 6021 | else if (mips_big_got) |
252b5132 RH |
6022 | { |
6023 | expressionS ex; | |
252b5132 RH |
6024 | |
6025 | /* This is the large GOT case. If this is a reference to an | |
6026 | external symbol, we want | |
6027 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6028 | addu $reg,$reg,$gp | |
6029 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6030 | |
6031 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6032 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6033 | nop | |
6034 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6035 | If there is a constant, it must be added in after. |
f5040a92 AO |
6036 | |
6037 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6038 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6039 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6040 | */ |
438c16b8 TS |
6041 | if (HAVE_NEWABI) |
6042 | { | |
4d7206a2 | 6043 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6044 | ep->X_add_number = 0; |
4d7206a2 | 6045 | relax_start (ep->X_add_symbol); |
df58fc94 | 6046 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6048 | reg, reg, mips_gp_register); | |
6049 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6050 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6051 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6052 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6053 | else if (ex.X_add_number) | |
6054 | { | |
6055 | ex.X_op = O_constant; | |
67c0d1eb RS |
6056 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6057 | BFD_RELOC_LO16); | |
f5040a92 AO |
6058 | } |
6059 | ||
6060 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6061 | relax_switch (); |
67c0d1eb | 6062 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6063 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6064 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6065 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6066 | relax_end (); |
438c16b8 | 6067 | } |
252b5132 | 6068 | else |
438c16b8 | 6069 | { |
f5040a92 AO |
6070 | ex.X_add_number = ep->X_add_number; |
6071 | ep->X_add_number = 0; | |
4d7206a2 | 6072 | relax_start (ep->X_add_symbol); |
df58fc94 | 6073 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6074 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6075 | reg, reg, mips_gp_register); | |
6076 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6077 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6078 | relax_switch (); |
6079 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6080 | { |
6081 | /* We need a nop before loading from $gp. This special | |
6082 | check is required because the lui which starts the main | |
6083 | instruction stream does not refer to $gp, and so will not | |
6084 | insert the nop which may be required. */ | |
67c0d1eb | 6085 | macro_build (NULL, "nop", ""); |
438c16b8 | 6086 | } |
67c0d1eb | 6087 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6088 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6089 | load_delay_nop (); |
67c0d1eb | 6090 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6091 | BFD_RELOC_LO16); |
4d7206a2 | 6092 | relax_end (); |
438c16b8 | 6093 | |
f5040a92 AO |
6094 | if (ex.X_add_number != 0) |
6095 | { | |
6096 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6097 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6098 | ex.X_op = O_constant; | |
67c0d1eb RS |
6099 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6100 | BFD_RELOC_LO16); | |
f5040a92 | 6101 | } |
252b5132 RH |
6102 | } |
6103 | } | |
252b5132 RH |
6104 | else |
6105 | abort (); | |
8fc2e39e | 6106 | |
741fe287 | 6107 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6108 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6109 | } |
6110 | ||
ea1fb5dc RS |
6111 | /* Move the contents of register SOURCE into register DEST. */ |
6112 | ||
6113 | static void | |
67c0d1eb | 6114 | move_register (int dest, int source) |
ea1fb5dc | 6115 | { |
df58fc94 RS |
6116 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6117 | instruction specifically requires a 32-bit one. */ | |
6118 | if (mips_opts.micromips | |
6119 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6120 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6121 | else |
6122 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6123 | dest, source, 0); | |
ea1fb5dc RS |
6124 | } |
6125 | ||
4d7206a2 | 6126 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6127 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6128 | The two alternatives are: | |
4d7206a2 RS |
6129 | |
6130 | Global symbol Local sybmol | |
6131 | ------------- ------------ | |
6132 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6133 | ... ... | |
6134 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6135 | ||
6136 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6137 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6138 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6139 | |
6140 | static void | |
67c0d1eb | 6141 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6142 | { |
6143 | expressionS global; | |
6144 | ||
6145 | global = *local; | |
6146 | global.X_add_number = 0; | |
6147 | ||
6148 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6149 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6150 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6151 | relax_switch (); |
67c0d1eb RS |
6152 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6153 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6154 | relax_end (); |
6155 | } | |
6156 | ||
6157 | static void | |
67c0d1eb | 6158 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6159 | { |
6160 | expressionS global; | |
6161 | ||
6162 | global.X_op = O_constant; | |
6163 | global.X_op_symbol = NULL; | |
6164 | global.X_add_symbol = NULL; | |
6165 | global.X_add_number = local->X_add_number; | |
6166 | ||
6167 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6168 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6169 | dest, dest, BFD_RELOC_LO16); |
6170 | relax_switch (); | |
67c0d1eb | 6171 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6172 | relax_end (); |
6173 | } | |
6174 | ||
f6a22291 MR |
6175 | static void |
6176 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6177 | { | |
6178 | expressionS global; | |
6179 | int hold_mips_optimize; | |
6180 | ||
6181 | global.X_op = O_constant; | |
6182 | global.X_op_symbol = NULL; | |
6183 | global.X_add_symbol = NULL; | |
6184 | global.X_add_number = local->X_add_number; | |
6185 | ||
6186 | relax_start (local->X_add_symbol); | |
6187 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6188 | relax_switch (); | |
6189 | /* Set mips_optimize around the lui instruction to avoid | |
6190 | inserting an unnecessary nop after the lw. */ | |
6191 | hold_mips_optimize = mips_optimize; | |
6192 | mips_optimize = 2; | |
6193 | macro_build_lui (&global, tmp); | |
6194 | mips_optimize = hold_mips_optimize; | |
6195 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6196 | relax_end (); | |
6197 | ||
6198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6199 | } | |
6200 | ||
df58fc94 RS |
6201 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6202 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6203 | is its complementing branch with the original condition negated. | |
6204 | CALL is set if the original branch specified the link operation. | |
6205 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6206 | ||
6207 | Code like this is produced in the noreorder mode: | |
6208 | ||
6209 | BRNEG <args>, 1f | |
6210 | nop | |
6211 | b <sym> | |
6212 | delay slot (executed only if branch taken) | |
6213 | 1: | |
6214 | ||
6215 | or, if CALL is set: | |
6216 | ||
6217 | BRNEG <args>, 1f | |
6218 | nop | |
6219 | bal <sym> | |
6220 | delay slot (executed only if branch taken) | |
6221 | 1: | |
6222 | ||
6223 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6224 | so code produced is simply: | |
6225 | ||
6226 | BR <args>, <sym> | |
6227 | nop | |
6228 | ||
6229 | This function is used when producing code for the microMIPS ASE that | |
6230 | does not implement branch likely instructions in hardware. */ | |
6231 | ||
6232 | static void | |
6233 | macro_build_branch_likely (const char *br, const char *brneg, | |
6234 | int call, expressionS *ep, const char *fmt, | |
6235 | unsigned int sreg, unsigned int treg) | |
6236 | { | |
6237 | int noreorder = mips_opts.noreorder; | |
6238 | expressionS expr1; | |
6239 | ||
6240 | gas_assert (mips_opts.micromips); | |
6241 | start_noreorder (); | |
6242 | if (noreorder) | |
6243 | { | |
6244 | micromips_label_expr (&expr1); | |
6245 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6246 | macro_build (NULL, "nop", ""); | |
6247 | macro_build (ep, call ? "bal" : "b", "p"); | |
6248 | ||
6249 | /* Set to true so that append_insn adds a label. */ | |
6250 | emit_branch_likely_macro = TRUE; | |
6251 | } | |
6252 | else | |
6253 | { | |
6254 | macro_build (ep, br, fmt, sreg, treg); | |
6255 | macro_build (NULL, "nop", ""); | |
6256 | } | |
6257 | end_noreorder (); | |
6258 | } | |
6259 | ||
6260 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6261 | the condition code tested. EP specifies the branch target. */ | |
6262 | ||
6263 | static void | |
6264 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6265 | { | |
6266 | const int call = 0; | |
6267 | const char *brneg; | |
6268 | const char *br; | |
6269 | ||
6270 | switch (type) | |
6271 | { | |
6272 | case M_BC1FL: | |
6273 | br = "bc1f"; | |
6274 | brneg = "bc1t"; | |
6275 | break; | |
6276 | case M_BC1TL: | |
6277 | br = "bc1t"; | |
6278 | brneg = "bc1f"; | |
6279 | break; | |
6280 | case M_BC2FL: | |
6281 | br = "bc2f"; | |
6282 | brneg = "bc2t"; | |
6283 | break; | |
6284 | case M_BC2TL: | |
6285 | br = "bc2t"; | |
6286 | brneg = "bc2f"; | |
6287 | break; | |
6288 | default: | |
6289 | abort (); | |
6290 | } | |
6291 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6292 | } | |
6293 | ||
6294 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6295 | the register tested. EP specifies the branch target. */ | |
6296 | ||
6297 | static void | |
6298 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6299 | { | |
6300 | const char *brneg = NULL; | |
6301 | const char *br; | |
6302 | int call = 0; | |
6303 | ||
6304 | switch (type) | |
6305 | { | |
6306 | case M_BGEZ: | |
6307 | br = "bgez"; | |
6308 | break; | |
6309 | case M_BGEZL: | |
6310 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6311 | brneg = "bltz"; | |
6312 | break; | |
6313 | case M_BGEZALL: | |
6314 | gas_assert (mips_opts.micromips); | |
6315 | br = "bgezals"; | |
6316 | brneg = "bltz"; | |
6317 | call = 1; | |
6318 | break; | |
6319 | case M_BGTZ: | |
6320 | br = "bgtz"; | |
6321 | break; | |
6322 | case M_BGTZL: | |
6323 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6324 | brneg = "blez"; | |
6325 | break; | |
6326 | case M_BLEZ: | |
6327 | br = "blez"; | |
6328 | break; | |
6329 | case M_BLEZL: | |
6330 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6331 | brneg = "bgtz"; | |
6332 | break; | |
6333 | case M_BLTZ: | |
6334 | br = "bltz"; | |
6335 | break; | |
6336 | case M_BLTZL: | |
6337 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6338 | brneg = "bgez"; | |
6339 | break; | |
6340 | case M_BLTZALL: | |
6341 | gas_assert (mips_opts.micromips); | |
6342 | br = "bltzals"; | |
6343 | brneg = "bgez"; | |
6344 | call = 1; | |
6345 | break; | |
6346 | default: | |
6347 | abort (); | |
6348 | } | |
6349 | if (mips_opts.micromips && brneg) | |
6350 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6351 | else | |
6352 | macro_build (ep, br, "s,p", sreg); | |
6353 | } | |
6354 | ||
6355 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6356 | TREG as the registers tested. EP specifies the branch target. */ | |
6357 | ||
6358 | static void | |
6359 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6360 | unsigned int sreg, unsigned int treg) | |
6361 | { | |
6362 | const char *brneg = NULL; | |
6363 | const int call = 0; | |
6364 | const char *br; | |
6365 | ||
6366 | switch (type) | |
6367 | { | |
6368 | case M_BEQ: | |
6369 | case M_BEQ_I: | |
6370 | br = "beq"; | |
6371 | break; | |
6372 | case M_BEQL: | |
6373 | case M_BEQL_I: | |
6374 | br = mips_opts.micromips ? "beq" : "beql"; | |
6375 | brneg = "bne"; | |
6376 | break; | |
6377 | case M_BNE: | |
6378 | case M_BNE_I: | |
6379 | br = "bne"; | |
6380 | break; | |
6381 | case M_BNEL: | |
6382 | case M_BNEL_I: | |
6383 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6384 | brneg = "beq"; | |
6385 | break; | |
6386 | default: | |
6387 | abort (); | |
6388 | } | |
6389 | if (mips_opts.micromips && brneg) | |
6390 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6391 | else | |
6392 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6393 | } | |
6394 | ||
252b5132 RH |
6395 | /* |
6396 | * Build macros | |
6397 | * This routine implements the seemingly endless macro or synthesized | |
6398 | * instructions and addressing modes in the mips assembly language. Many | |
6399 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6400 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6401 | * this verbose method. Others are not simple macros but are more like |
6402 | * optimizing code generation. | |
6403 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6404 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6405 | * The ensuing load upper instructions are ommited. This implies some kind |
6406 | * of global optimization. We currently only optimize within a single macro. | |
6407 | * For many of the load and store macros if the address is specified as a | |
6408 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6409 | * first load register 'at' with zero and use it as the base register. The | |
6410 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6411 | * we're missing. | |
6412 | */ | |
6413 | static void | |
17a2f251 | 6414 | macro (struct mips_cl_insn *ip) |
252b5132 | 6415 | { |
741fe287 MR |
6416 | unsigned int treg, sreg, dreg, breg; |
6417 | unsigned int tempreg; | |
252b5132 | 6418 | int mask; |
43841e91 | 6419 | int used_at = 0; |
df58fc94 | 6420 | expressionS label_expr; |
252b5132 | 6421 | expressionS expr1; |
df58fc94 | 6422 | expressionS *ep; |
252b5132 RH |
6423 | const char *s; |
6424 | const char *s2; | |
6425 | const char *fmt; | |
6426 | int likely = 0; | |
252b5132 | 6427 | int coproc = 0; |
df58fc94 | 6428 | int off12 = 0; |
1abe91b1 | 6429 | int call = 0; |
df58fc94 RS |
6430 | int jals = 0; |
6431 | int dbl = 0; | |
6432 | int imm = 0; | |
6433 | int ust = 0; | |
6434 | int lp = 0; | |
6435 | int ab = 0; | |
dd6a37e7 | 6436 | int off0 = 0; |
252b5132 | 6437 | int off; |
67c0d1eb | 6438 | offsetT maxnum; |
252b5132 | 6439 | bfd_reloc_code_real_type r; |
252b5132 RH |
6440 | int hold_mips_optimize; |
6441 | ||
9c2799c2 | 6442 | gas_assert (! mips_opts.mips16); |
252b5132 | 6443 | |
df58fc94 RS |
6444 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6445 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6446 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6447 | mask = ip->insn_mo->mask; |
6448 | ||
df58fc94 RS |
6449 | label_expr.X_op = O_constant; |
6450 | label_expr.X_op_symbol = NULL; | |
6451 | label_expr.X_add_symbol = NULL; | |
6452 | label_expr.X_add_number = 0; | |
6453 | ||
252b5132 RH |
6454 | expr1.X_op = O_constant; |
6455 | expr1.X_op_symbol = NULL; | |
6456 | expr1.X_add_symbol = NULL; | |
6457 | expr1.X_add_number = 1; | |
6458 | ||
6459 | switch (mask) | |
6460 | { | |
6461 | case M_DABS: | |
6462 | dbl = 1; | |
6463 | case M_ABS: | |
df58fc94 RS |
6464 | /* bgez $a0,1f |
6465 | move v0,$a0 | |
6466 | sub v0,$zero,$a0 | |
6467 | 1: | |
6468 | */ | |
252b5132 | 6469 | |
7d10b47d | 6470 | start_noreorder (); |
252b5132 | 6471 | |
df58fc94 RS |
6472 | if (mips_opts.micromips) |
6473 | micromips_label_expr (&label_expr); | |
6474 | else | |
6475 | label_expr.X_add_number = 8; | |
6476 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6477 | if (dreg == sreg) |
a605d2b3 | 6478 | macro_build (NULL, "nop", ""); |
252b5132 | 6479 | else |
67c0d1eb RS |
6480 | move_register (dreg, sreg); |
6481 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6482 | if (mips_opts.micromips) |
6483 | micromips_add_label (); | |
252b5132 | 6484 | |
7d10b47d | 6485 | end_noreorder (); |
8fc2e39e | 6486 | break; |
252b5132 RH |
6487 | |
6488 | case M_ADD_I: | |
6489 | s = "addi"; | |
6490 | s2 = "add"; | |
6491 | goto do_addi; | |
6492 | case M_ADDU_I: | |
6493 | s = "addiu"; | |
6494 | s2 = "addu"; | |
6495 | goto do_addi; | |
6496 | case M_DADD_I: | |
6497 | dbl = 1; | |
6498 | s = "daddi"; | |
6499 | s2 = "dadd"; | |
df58fc94 RS |
6500 | if (!mips_opts.micromips) |
6501 | goto do_addi; | |
6502 | if (imm_expr.X_op == O_constant | |
6503 | && imm_expr.X_add_number >= -0x200 | |
6504 | && imm_expr.X_add_number < 0x200) | |
6505 | { | |
6506 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6507 | break; | |
6508 | } | |
6509 | goto do_addi_i; | |
252b5132 RH |
6510 | case M_DADDU_I: |
6511 | dbl = 1; | |
6512 | s = "daddiu"; | |
6513 | s2 = "daddu"; | |
6514 | do_addi: | |
6515 | if (imm_expr.X_op == O_constant | |
6516 | && imm_expr.X_add_number >= -0x8000 | |
6517 | && imm_expr.X_add_number < 0x8000) | |
6518 | { | |
67c0d1eb | 6519 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6520 | break; |
252b5132 | 6521 | } |
df58fc94 | 6522 | do_addi_i: |
8fc2e39e | 6523 | used_at = 1; |
67c0d1eb RS |
6524 | load_register (AT, &imm_expr, dbl); |
6525 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6526 | break; |
6527 | ||
6528 | case M_AND_I: | |
6529 | s = "andi"; | |
6530 | s2 = "and"; | |
6531 | goto do_bit; | |
6532 | case M_OR_I: | |
6533 | s = "ori"; | |
6534 | s2 = "or"; | |
6535 | goto do_bit; | |
6536 | case M_NOR_I: | |
6537 | s = ""; | |
6538 | s2 = "nor"; | |
6539 | goto do_bit; | |
6540 | case M_XOR_I: | |
6541 | s = "xori"; | |
6542 | s2 = "xor"; | |
6543 | do_bit: | |
6544 | if (imm_expr.X_op == O_constant | |
6545 | && imm_expr.X_add_number >= 0 | |
6546 | && imm_expr.X_add_number < 0x10000) | |
6547 | { | |
6548 | if (mask != M_NOR_I) | |
67c0d1eb | 6549 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6550 | else |
6551 | { | |
67c0d1eb RS |
6552 | macro_build (&imm_expr, "ori", "t,r,i", |
6553 | treg, sreg, BFD_RELOC_LO16); | |
6554 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6555 | } |
8fc2e39e | 6556 | break; |
252b5132 RH |
6557 | } |
6558 | ||
8fc2e39e | 6559 | used_at = 1; |
67c0d1eb RS |
6560 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6561 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6562 | break; |
6563 | ||
8b082fb1 TS |
6564 | case M_BALIGN: |
6565 | switch (imm_expr.X_add_number) | |
6566 | { | |
6567 | case 0: | |
6568 | macro_build (NULL, "nop", ""); | |
6569 | break; | |
6570 | case 2: | |
6571 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6572 | break; | |
03f66e8a MR |
6573 | case 1: |
6574 | case 3: | |
8b082fb1 | 6575 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6576 | (int) imm_expr.X_add_number); |
8b082fb1 | 6577 | break; |
03f66e8a MR |
6578 | default: |
6579 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6580 | (unsigned long) imm_expr.X_add_number); | |
6581 | break; | |
8b082fb1 TS |
6582 | } |
6583 | break; | |
6584 | ||
df58fc94 RS |
6585 | case M_BC1FL: |
6586 | case M_BC1TL: | |
6587 | case M_BC2FL: | |
6588 | case M_BC2TL: | |
6589 | gas_assert (mips_opts.micromips); | |
6590 | macro_build_branch_ccl (mask, &offset_expr, | |
6591 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6592 | break; | |
6593 | ||
252b5132 | 6594 | case M_BEQ_I: |
252b5132 | 6595 | case M_BEQL_I: |
252b5132 | 6596 | case M_BNE_I: |
252b5132 | 6597 | case M_BNEL_I: |
252b5132 | 6598 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6599 | treg = 0; |
6600 | else | |
252b5132 | 6601 | { |
df58fc94 RS |
6602 | treg = AT; |
6603 | used_at = 1; | |
6604 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6605 | } |
df58fc94 RS |
6606 | /* Fall through. */ |
6607 | case M_BEQL: | |
6608 | case M_BNEL: | |
6609 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6610 | break; |
6611 | ||
6612 | case M_BGEL: | |
6613 | likely = 1; | |
6614 | case M_BGE: | |
6615 | if (treg == 0) | |
df58fc94 RS |
6616 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6617 | else if (sreg == 0) | |
6618 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6619 | else | |
252b5132 | 6620 | { |
df58fc94 RS |
6621 | used_at = 1; |
6622 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6623 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6624 | &offset_expr, AT, ZERO); | |
252b5132 | 6625 | } |
df58fc94 RS |
6626 | break; |
6627 | ||
6628 | case M_BGEZL: | |
6629 | case M_BGEZALL: | |
6630 | case M_BGTZL: | |
6631 | case M_BLEZL: | |
6632 | case M_BLTZL: | |
6633 | case M_BLTZALL: | |
6634 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6635 | break; |
6636 | ||
6637 | case M_BGTL_I: | |
6638 | likely = 1; | |
6639 | case M_BGT_I: | |
90ecf173 | 6640 | /* Check for > max integer. */ |
252b5132 | 6641 | maxnum = 0x7fffffff; |
ca4e0257 | 6642 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6643 | { |
6644 | maxnum <<= 16; | |
6645 | maxnum |= 0xffff; | |
6646 | maxnum <<= 16; | |
6647 | maxnum |= 0xffff; | |
6648 | } | |
6649 | if (imm_expr.X_op == O_constant | |
6650 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6651 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6652 | { |
6653 | do_false: | |
90ecf173 | 6654 | /* Result is always false. */ |
252b5132 | 6655 | if (! likely) |
a605d2b3 | 6656 | macro_build (NULL, "nop", ""); |
252b5132 | 6657 | else |
df58fc94 | 6658 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6659 | break; |
252b5132 RH |
6660 | } |
6661 | if (imm_expr.X_op != O_constant) | |
6662 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6663 | ++imm_expr.X_add_number; |
252b5132 RH |
6664 | /* FALLTHROUGH */ |
6665 | case M_BGE_I: | |
6666 | case M_BGEL_I: | |
6667 | if (mask == M_BGEL_I) | |
6668 | likely = 1; | |
6669 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6670 | { | |
df58fc94 RS |
6671 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6672 | &offset_expr, sreg); | |
8fc2e39e | 6673 | break; |
252b5132 RH |
6674 | } |
6675 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6676 | { | |
df58fc94 RS |
6677 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6678 | &offset_expr, sreg); | |
8fc2e39e | 6679 | break; |
252b5132 RH |
6680 | } |
6681 | maxnum = 0x7fffffff; | |
ca4e0257 | 6682 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6683 | { |
6684 | maxnum <<= 16; | |
6685 | maxnum |= 0xffff; | |
6686 | maxnum <<= 16; | |
6687 | maxnum |= 0xffff; | |
6688 | } | |
6689 | maxnum = - maxnum - 1; | |
6690 | if (imm_expr.X_op == O_constant | |
6691 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6692 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6693 | { |
6694 | do_true: | |
6695 | /* result is always true */ | |
6696 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6697 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6698 | break; |
252b5132 | 6699 | } |
8fc2e39e | 6700 | used_at = 1; |
67c0d1eb | 6701 | set_at (sreg, 0); |
df58fc94 RS |
6702 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6703 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6704 | break; |
6705 | ||
6706 | case M_BGEUL: | |
6707 | likely = 1; | |
6708 | case M_BGEU: | |
6709 | if (treg == 0) | |
6710 | goto do_true; | |
df58fc94 RS |
6711 | else if (sreg == 0) |
6712 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6713 | &offset_expr, ZERO, treg); | |
6714 | else | |
252b5132 | 6715 | { |
df58fc94 RS |
6716 | used_at = 1; |
6717 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6718 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6719 | &offset_expr, AT, ZERO); | |
252b5132 | 6720 | } |
252b5132 RH |
6721 | break; |
6722 | ||
6723 | case M_BGTUL_I: | |
6724 | likely = 1; | |
6725 | case M_BGTU_I: | |
6726 | if (sreg == 0 | |
ca4e0257 | 6727 | || (HAVE_32BIT_GPRS |
252b5132 | 6728 | && imm_expr.X_op == O_constant |
f01dc953 | 6729 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6730 | goto do_false; |
6731 | if (imm_expr.X_op != O_constant) | |
6732 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6733 | ++imm_expr.X_add_number; |
252b5132 RH |
6734 | /* FALLTHROUGH */ |
6735 | case M_BGEU_I: | |
6736 | case M_BGEUL_I: | |
6737 | if (mask == M_BGEUL_I) | |
6738 | likely = 1; | |
6739 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6740 | goto do_true; | |
df58fc94 RS |
6741 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6742 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6743 | &offset_expr, sreg, ZERO); | |
6744 | else | |
252b5132 | 6745 | { |
df58fc94 RS |
6746 | used_at = 1; |
6747 | set_at (sreg, 1); | |
6748 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6749 | &offset_expr, AT, ZERO); | |
252b5132 | 6750 | } |
252b5132 RH |
6751 | break; |
6752 | ||
6753 | case M_BGTL: | |
6754 | likely = 1; | |
6755 | case M_BGT: | |
6756 | if (treg == 0) | |
df58fc94 RS |
6757 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6758 | else if (sreg == 0) | |
6759 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6760 | else | |
252b5132 | 6761 | { |
df58fc94 RS |
6762 | used_at = 1; |
6763 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6764 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6765 | &offset_expr, AT, ZERO); | |
252b5132 | 6766 | } |
252b5132 RH |
6767 | break; |
6768 | ||
6769 | case M_BGTUL: | |
6770 | likely = 1; | |
6771 | case M_BGTU: | |
6772 | if (treg == 0) | |
df58fc94 RS |
6773 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6774 | &offset_expr, sreg, ZERO); | |
6775 | else if (sreg == 0) | |
6776 | goto do_false; | |
6777 | else | |
252b5132 | 6778 | { |
df58fc94 RS |
6779 | used_at = 1; |
6780 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6781 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6782 | &offset_expr, AT, ZERO); | |
252b5132 | 6783 | } |
252b5132 RH |
6784 | break; |
6785 | ||
6786 | case M_BLEL: | |
6787 | likely = 1; | |
6788 | case M_BLE: | |
6789 | if (treg == 0) | |
df58fc94 RS |
6790 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6791 | else if (sreg == 0) | |
6792 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6793 | else | |
252b5132 | 6794 | { |
df58fc94 RS |
6795 | used_at = 1; |
6796 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6797 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6798 | &offset_expr, AT, ZERO); | |
252b5132 | 6799 | } |
252b5132 RH |
6800 | break; |
6801 | ||
6802 | case M_BLEL_I: | |
6803 | likely = 1; | |
6804 | case M_BLE_I: | |
6805 | maxnum = 0x7fffffff; | |
ca4e0257 | 6806 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6807 | { |
6808 | maxnum <<= 16; | |
6809 | maxnum |= 0xffff; | |
6810 | maxnum <<= 16; | |
6811 | maxnum |= 0xffff; | |
6812 | } | |
6813 | if (imm_expr.X_op == O_constant | |
6814 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6815 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6816 | goto do_true; |
6817 | if (imm_expr.X_op != O_constant) | |
6818 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6819 | ++imm_expr.X_add_number; |
252b5132 RH |
6820 | /* FALLTHROUGH */ |
6821 | case M_BLT_I: | |
6822 | case M_BLTL_I: | |
6823 | if (mask == M_BLTL_I) | |
6824 | likely = 1; | |
6825 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6826 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6827 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6828 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6829 | else | |
252b5132 | 6830 | { |
df58fc94 RS |
6831 | used_at = 1; |
6832 | set_at (sreg, 0); | |
6833 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6834 | &offset_expr, AT, ZERO); | |
252b5132 | 6835 | } |
252b5132 RH |
6836 | break; |
6837 | ||
6838 | case M_BLEUL: | |
6839 | likely = 1; | |
6840 | case M_BLEU: | |
6841 | if (treg == 0) | |
df58fc94 RS |
6842 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6843 | &offset_expr, sreg, ZERO); | |
6844 | else if (sreg == 0) | |
6845 | goto do_true; | |
6846 | else | |
252b5132 | 6847 | { |
df58fc94 RS |
6848 | used_at = 1; |
6849 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6850 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6851 | &offset_expr, AT, ZERO); | |
252b5132 | 6852 | } |
252b5132 RH |
6853 | break; |
6854 | ||
6855 | case M_BLEUL_I: | |
6856 | likely = 1; | |
6857 | case M_BLEU_I: | |
6858 | if (sreg == 0 | |
ca4e0257 | 6859 | || (HAVE_32BIT_GPRS |
252b5132 | 6860 | && imm_expr.X_op == O_constant |
f01dc953 | 6861 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6862 | goto do_true; |
6863 | if (imm_expr.X_op != O_constant) | |
6864 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6865 | ++imm_expr.X_add_number; |
252b5132 RH |
6866 | /* FALLTHROUGH */ |
6867 | case M_BLTU_I: | |
6868 | case M_BLTUL_I: | |
6869 | if (mask == M_BLTUL_I) | |
6870 | likely = 1; | |
6871 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6872 | goto do_false; | |
df58fc94 RS |
6873 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6874 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6875 | &offset_expr, sreg, ZERO); | |
6876 | else | |
252b5132 | 6877 | { |
df58fc94 RS |
6878 | used_at = 1; |
6879 | set_at (sreg, 1); | |
6880 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6881 | &offset_expr, AT, ZERO); | |
252b5132 | 6882 | } |
252b5132 RH |
6883 | break; |
6884 | ||
6885 | case M_BLTL: | |
6886 | likely = 1; | |
6887 | case M_BLT: | |
6888 | if (treg == 0) | |
df58fc94 RS |
6889 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6890 | else if (sreg == 0) | |
6891 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6892 | else | |
252b5132 | 6893 | { |
df58fc94 RS |
6894 | used_at = 1; |
6895 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6896 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6897 | &offset_expr, AT, ZERO); | |
252b5132 | 6898 | } |
252b5132 RH |
6899 | break; |
6900 | ||
6901 | case M_BLTUL: | |
6902 | likely = 1; | |
6903 | case M_BLTU: | |
6904 | if (treg == 0) | |
6905 | goto do_false; | |
df58fc94 RS |
6906 | else if (sreg == 0) |
6907 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6908 | &offset_expr, ZERO, treg); | |
6909 | else | |
252b5132 | 6910 | { |
df58fc94 RS |
6911 | used_at = 1; |
6912 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6913 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6914 | &offset_expr, AT, ZERO); | |
252b5132 | 6915 | } |
252b5132 RH |
6916 | break; |
6917 | ||
5f74bc13 CD |
6918 | case M_DEXT: |
6919 | { | |
d5818fca MR |
6920 | /* Use unsigned arithmetic. */ |
6921 | addressT pos; | |
6922 | addressT size; | |
5f74bc13 | 6923 | |
90ecf173 | 6924 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6925 | { |
6926 | as_bad (_("Unsupported large constant")); | |
6927 | pos = size = 1; | |
6928 | } | |
6929 | else | |
6930 | { | |
d5818fca MR |
6931 | pos = imm_expr.X_add_number; |
6932 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6933 | } |
6934 | ||
6935 | if (pos > 63) | |
6936 | { | |
d5818fca | 6937 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6938 | pos = 1; |
6939 | } | |
90ecf173 | 6940 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6941 | { |
6942 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6943 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6944 | size = 1; |
6945 | } | |
6946 | ||
6947 | if (size <= 32 && pos < 32) | |
6948 | { | |
6949 | s = "dext"; | |
6950 | fmt = "t,r,+A,+C"; | |
6951 | } | |
6952 | else if (size <= 32) | |
6953 | { | |
6954 | s = "dextu"; | |
6955 | fmt = "t,r,+E,+H"; | |
6956 | } | |
6957 | else | |
6958 | { | |
6959 | s = "dextm"; | |
6960 | fmt = "t,r,+A,+G"; | |
6961 | } | |
d5818fca MR |
6962 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6963 | (int) (size - 1)); | |
5f74bc13 | 6964 | } |
8fc2e39e | 6965 | break; |
5f74bc13 CD |
6966 | |
6967 | case M_DINS: | |
6968 | { | |
d5818fca MR |
6969 | /* Use unsigned arithmetic. */ |
6970 | addressT pos; | |
6971 | addressT size; | |
5f74bc13 | 6972 | |
90ecf173 | 6973 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6974 | { |
6975 | as_bad (_("Unsupported large constant")); | |
6976 | pos = size = 1; | |
6977 | } | |
6978 | else | |
6979 | { | |
d5818fca MR |
6980 | pos = imm_expr.X_add_number; |
6981 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6982 | } |
6983 | ||
6984 | if (pos > 63) | |
6985 | { | |
d5818fca | 6986 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6987 | pos = 1; |
6988 | } | |
90ecf173 | 6989 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6990 | { |
6991 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6992 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6993 | size = 1; |
6994 | } | |
6995 | ||
6996 | if (pos < 32 && (pos + size - 1) < 32) | |
6997 | { | |
6998 | s = "dins"; | |
6999 | fmt = "t,r,+A,+B"; | |
7000 | } | |
7001 | else if (pos >= 32) | |
7002 | { | |
7003 | s = "dinsu"; | |
7004 | fmt = "t,r,+E,+F"; | |
7005 | } | |
7006 | else | |
7007 | { | |
7008 | s = "dinsm"; | |
7009 | fmt = "t,r,+A,+F"; | |
7010 | } | |
750bdd57 AS |
7011 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7012 | (int) (pos + size - 1)); | |
5f74bc13 | 7013 | } |
8fc2e39e | 7014 | break; |
5f74bc13 | 7015 | |
252b5132 RH |
7016 | case M_DDIV_3: |
7017 | dbl = 1; | |
7018 | case M_DIV_3: | |
7019 | s = "mflo"; | |
7020 | goto do_div3; | |
7021 | case M_DREM_3: | |
7022 | dbl = 1; | |
7023 | case M_REM_3: | |
7024 | s = "mfhi"; | |
7025 | do_div3: | |
7026 | if (treg == 0) | |
7027 | { | |
7028 | as_warn (_("Divide by zero.")); | |
7029 | if (mips_trap) | |
df58fc94 | 7030 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7031 | else |
df58fc94 | 7032 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7033 | break; |
252b5132 RH |
7034 | } |
7035 | ||
7d10b47d | 7036 | start_noreorder (); |
252b5132 RH |
7037 | if (mips_trap) |
7038 | { | |
df58fc94 | 7039 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7040 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7041 | } |
7042 | else | |
7043 | { | |
df58fc94 RS |
7044 | if (mips_opts.micromips) |
7045 | micromips_label_expr (&label_expr); | |
7046 | else | |
7047 | label_expr.X_add_number = 8; | |
7048 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7049 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7050 | macro_build (NULL, "break", BRK_FMT, 7); |
7051 | if (mips_opts.micromips) | |
7052 | micromips_add_label (); | |
252b5132 RH |
7053 | } |
7054 | expr1.X_add_number = -1; | |
8fc2e39e | 7055 | used_at = 1; |
f6a22291 | 7056 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7057 | if (mips_opts.micromips) |
7058 | micromips_label_expr (&label_expr); | |
7059 | else | |
7060 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7061 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7062 | if (dbl) |
7063 | { | |
7064 | expr1.X_add_number = 1; | |
f6a22291 | 7065 | load_register (AT, &expr1, dbl); |
df58fc94 | 7066 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7067 | } |
7068 | else | |
7069 | { | |
7070 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7071 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7072 | } |
7073 | if (mips_trap) | |
7074 | { | |
df58fc94 | 7075 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7076 | /* We want to close the noreorder block as soon as possible, so |
7077 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7078 | end_noreorder (); |
252b5132 RH |
7079 | } |
7080 | else | |
7081 | { | |
df58fc94 RS |
7082 | if (mips_opts.micromips) |
7083 | micromips_label_expr (&label_expr); | |
7084 | else | |
7085 | label_expr.X_add_number = 8; | |
7086 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7087 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7088 | |
7089 | /* We want to close the noreorder block as soon as possible, so | |
7090 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7091 | end_noreorder (); |
252b5132 | 7092 | |
df58fc94 | 7093 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7094 | } |
df58fc94 RS |
7095 | if (mips_opts.micromips) |
7096 | micromips_add_label (); | |
7097 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7098 | break; |
7099 | ||
7100 | case M_DIV_3I: | |
7101 | s = "div"; | |
7102 | s2 = "mflo"; | |
7103 | goto do_divi; | |
7104 | case M_DIVU_3I: | |
7105 | s = "divu"; | |
7106 | s2 = "mflo"; | |
7107 | goto do_divi; | |
7108 | case M_REM_3I: | |
7109 | s = "div"; | |
7110 | s2 = "mfhi"; | |
7111 | goto do_divi; | |
7112 | case M_REMU_3I: | |
7113 | s = "divu"; | |
7114 | s2 = "mfhi"; | |
7115 | goto do_divi; | |
7116 | case M_DDIV_3I: | |
7117 | dbl = 1; | |
7118 | s = "ddiv"; | |
7119 | s2 = "mflo"; | |
7120 | goto do_divi; | |
7121 | case M_DDIVU_3I: | |
7122 | dbl = 1; | |
7123 | s = "ddivu"; | |
7124 | s2 = "mflo"; | |
7125 | goto do_divi; | |
7126 | case M_DREM_3I: | |
7127 | dbl = 1; | |
7128 | s = "ddiv"; | |
7129 | s2 = "mfhi"; | |
7130 | goto do_divi; | |
7131 | case M_DREMU_3I: | |
7132 | dbl = 1; | |
7133 | s = "ddivu"; | |
7134 | s2 = "mfhi"; | |
7135 | do_divi: | |
7136 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7137 | { | |
7138 | as_warn (_("Divide by zero.")); | |
7139 | if (mips_trap) | |
df58fc94 | 7140 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7141 | else |
df58fc94 | 7142 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7143 | break; |
252b5132 RH |
7144 | } |
7145 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7146 | { | |
7147 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7148 | move_register (dreg, sreg); |
252b5132 | 7149 | else |
c80c840e | 7150 | move_register (dreg, ZERO); |
8fc2e39e | 7151 | break; |
252b5132 RH |
7152 | } |
7153 | if (imm_expr.X_op == O_constant | |
7154 | && imm_expr.X_add_number == -1 | |
7155 | && s[strlen (s) - 1] != 'u') | |
7156 | { | |
7157 | if (strcmp (s2, "mflo") == 0) | |
7158 | { | |
67c0d1eb | 7159 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7160 | } |
7161 | else | |
c80c840e | 7162 | move_register (dreg, ZERO); |
8fc2e39e | 7163 | break; |
252b5132 RH |
7164 | } |
7165 | ||
8fc2e39e | 7166 | used_at = 1; |
67c0d1eb RS |
7167 | load_register (AT, &imm_expr, dbl); |
7168 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7169 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7170 | break; |
7171 | ||
7172 | case M_DIVU_3: | |
7173 | s = "divu"; | |
7174 | s2 = "mflo"; | |
7175 | goto do_divu3; | |
7176 | case M_REMU_3: | |
7177 | s = "divu"; | |
7178 | s2 = "mfhi"; | |
7179 | goto do_divu3; | |
7180 | case M_DDIVU_3: | |
7181 | s = "ddivu"; | |
7182 | s2 = "mflo"; | |
7183 | goto do_divu3; | |
7184 | case M_DREMU_3: | |
7185 | s = "ddivu"; | |
7186 | s2 = "mfhi"; | |
7187 | do_divu3: | |
7d10b47d | 7188 | start_noreorder (); |
252b5132 RH |
7189 | if (mips_trap) |
7190 | { | |
df58fc94 | 7191 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7192 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7193 | /* We want to close the noreorder block as soon as possible, so |
7194 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7195 | end_noreorder (); |
252b5132 RH |
7196 | } |
7197 | else | |
7198 | { | |
df58fc94 RS |
7199 | if (mips_opts.micromips) |
7200 | micromips_label_expr (&label_expr); | |
7201 | else | |
7202 | label_expr.X_add_number = 8; | |
7203 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7204 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7205 | |
7206 | /* We want to close the noreorder block as soon as possible, so | |
7207 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7208 | end_noreorder (); |
df58fc94 RS |
7209 | macro_build (NULL, "break", BRK_FMT, 7); |
7210 | if (mips_opts.micromips) | |
7211 | micromips_add_label (); | |
252b5132 | 7212 | } |
df58fc94 | 7213 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7214 | break; |
252b5132 | 7215 | |
1abe91b1 MR |
7216 | case M_DLCA_AB: |
7217 | dbl = 1; | |
7218 | case M_LCA_AB: | |
7219 | call = 1; | |
7220 | goto do_la; | |
252b5132 RH |
7221 | case M_DLA_AB: |
7222 | dbl = 1; | |
7223 | case M_LA_AB: | |
1abe91b1 | 7224 | do_la: |
252b5132 RH |
7225 | /* Load the address of a symbol into a register. If breg is not |
7226 | zero, we then add a base register to it. */ | |
7227 | ||
3bec30a8 TS |
7228 | if (dbl && HAVE_32BIT_GPRS) |
7229 | as_warn (_("dla used to load 32-bit register")); | |
7230 | ||
90ecf173 | 7231 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7232 | as_warn (_("la used to load 64-bit address")); |
7233 | ||
0c11417f MR |
7234 | if (offset_expr.X_op == O_constant |
7235 | && offset_expr.X_add_number >= -0x8000 | |
7236 | && offset_expr.X_add_number < 0x8000) | |
7237 | { | |
aed1a261 | 7238 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7239 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7240 | break; |
0c11417f MR |
7241 | } |
7242 | ||
741fe287 | 7243 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7244 | { |
7245 | tempreg = AT; | |
7246 | used_at = 1; | |
7247 | } | |
7248 | else | |
7249 | { | |
7250 | tempreg = treg; | |
afdbd6d0 CD |
7251 | } |
7252 | ||
252b5132 RH |
7253 | if (offset_expr.X_op != O_symbol |
7254 | && offset_expr.X_op != O_constant) | |
7255 | { | |
f71d0d44 | 7256 | as_bad (_("Expression too complex")); |
252b5132 RH |
7257 | offset_expr.X_op = O_constant; |
7258 | } | |
7259 | ||
252b5132 | 7260 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7261 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7262 | else if (mips_pic == NO_PIC) |
7263 | { | |
d6bc6245 | 7264 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7265 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7266 | Otherwise we want |
7267 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7268 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7269 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7270 | so we may as well always use the latter form. |
76b3015f | 7271 | |
6caf9ef4 TS |
7272 | With 64bit address space and a usable $at we want |
7273 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7274 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7275 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7276 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7277 | dsll32 $tempreg,0 | |
7278 | daddu $tempreg,$tempreg,$at | |
7279 | ||
7280 | If $at is already in use, we use a path which is suboptimal | |
7281 | on superscalar processors. | |
7282 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7283 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7284 | dsll $tempreg,16 | |
7285 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7286 | dsll $tempreg,16 | |
7287 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7288 | ||
7289 | For GP relative symbols in 64bit address space we can use | |
7290 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7291 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7292 | { |
6caf9ef4 TS |
7293 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7294 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7295 | { | |
7296 | relax_start (offset_expr.X_add_symbol); | |
7297 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7298 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7299 | relax_switch (); | |
7300 | } | |
d6bc6245 | 7301 | |
741fe287 | 7302 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7303 | { |
df58fc94 | 7304 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7305 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7306 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7307 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7308 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7309 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7310 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7311 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7312 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7313 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7314 | used_at = 1; |
7315 | } | |
7316 | else | |
7317 | { | |
df58fc94 | 7318 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7319 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7320 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7321 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7322 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7323 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7324 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7325 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7326 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7327 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7328 | } |
6caf9ef4 TS |
7329 | |
7330 | if (mips_relax.sequence) | |
7331 | relax_end (); | |
98d3f06f KH |
7332 | } |
7333 | else | |
7334 | { | |
7335 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7336 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7337 | { |
4d7206a2 | 7338 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7339 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7340 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7341 | relax_switch (); |
98d3f06f | 7342 | } |
6943caf0 | 7343 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7344 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7345 | macro_build_lui (&offset_expr, tempreg); |
7346 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7347 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7348 | if (mips_relax.sequence) |
7349 | relax_end (); | |
98d3f06f | 7350 | } |
252b5132 | 7351 | } |
0a44bf69 | 7352 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7353 | { |
9117d219 NC |
7354 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7355 | ||
252b5132 RH |
7356 | /* If this is a reference to an external symbol, and there |
7357 | is no constant, we want | |
7358 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7359 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7360 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7361 | For a local symbol, we want |
7362 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7363 | nop | |
7364 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7365 | ||
7366 | If we have a small constant, and this is a reference to | |
7367 | an external symbol, we want | |
7368 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7369 | nop | |
7370 | addiu $tempreg,$tempreg,<constant> | |
7371 | For a local symbol, we want the same instruction | |
7372 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7373 | addiu instruction. | |
7374 | ||
7375 | If we have a large constant, and this is a reference to | |
7376 | an external symbol, we want | |
7377 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7378 | lui $at,<hiconstant> | |
7379 | addiu $at,$at,<loconstant> | |
7380 | addu $tempreg,$tempreg,$at | |
7381 | For a local symbol, we want the same instruction | |
7382 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7383 | addiu instruction. |
ed6fb7bd SC |
7384 | */ |
7385 | ||
4d7206a2 | 7386 | if (offset_expr.X_add_number == 0) |
252b5132 | 7387 | { |
0a44bf69 RS |
7388 | if (mips_pic == SVR4_PIC |
7389 | && breg == 0 | |
7390 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7391 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7392 | ||
7393 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7394 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7395 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7396 | if (breg != 0) |
252b5132 RH |
7397 | { |
7398 | /* We're going to put in an addu instruction using | |
7399 | tempreg, so we may as well insert the nop right | |
7400 | now. */ | |
269137b2 | 7401 | load_delay_nop (); |
252b5132 | 7402 | } |
4d7206a2 | 7403 | relax_switch (); |
67c0d1eb RS |
7404 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7405 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7406 | load_delay_nop (); |
67c0d1eb RS |
7407 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7408 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7409 | relax_end (); |
252b5132 RH |
7410 | /* FIXME: If breg == 0, and the next instruction uses |
7411 | $tempreg, then if this variant case is used an extra | |
7412 | nop will be generated. */ | |
7413 | } | |
4d7206a2 RS |
7414 | else if (offset_expr.X_add_number >= -0x8000 |
7415 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7416 | { |
67c0d1eb | 7417 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7418 | load_delay_nop (); |
67c0d1eb | 7419 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7420 | } |
7421 | else | |
7422 | { | |
4d7206a2 RS |
7423 | expr1.X_add_number = offset_expr.X_add_number; |
7424 | offset_expr.X_add_number = | |
43c0598f | 7425 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7426 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7427 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7428 | /* If we are going to add in a base register, and the |
7429 | target register and the base register are the same, | |
7430 | then we are using AT as a temporary register. Since | |
7431 | we want to load the constant into AT, we add our | |
7432 | current AT (from the global offset table) and the | |
7433 | register into the register now, and pretend we were | |
7434 | not using a base register. */ | |
67c0d1eb | 7435 | if (breg == treg) |
252b5132 | 7436 | { |
269137b2 | 7437 | load_delay_nop (); |
67c0d1eb | 7438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7439 | treg, AT, breg); |
252b5132 RH |
7440 | breg = 0; |
7441 | tempreg = treg; | |
252b5132 | 7442 | } |
f6a22291 | 7443 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7444 | used_at = 1; |
7445 | } | |
7446 | } | |
0a44bf69 | 7447 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7448 | { |
67c0d1eb | 7449 | int add_breg_early = 0; |
f5040a92 AO |
7450 | |
7451 | /* If this is a reference to an external, and there is no | |
7452 | constant, or local symbol (*), with or without a | |
7453 | constant, we want | |
7454 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7455 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7456 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7457 | ||
7458 | If we have a small constant, and this is a reference to | |
7459 | an external symbol, we want | |
7460 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7461 | addiu $tempreg,$tempreg,<constant> | |
7462 | ||
7463 | If we have a large constant, and this is a reference to | |
7464 | an external symbol, we want | |
7465 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7466 | lui $at,<hiconstant> | |
7467 | addiu $at,$at,<loconstant> | |
7468 | addu $tempreg,$tempreg,$at | |
7469 | ||
7470 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7471 | local symbols, even though it introduces an additional | |
7472 | instruction. */ | |
7473 | ||
f5040a92 AO |
7474 | if (offset_expr.X_add_number) |
7475 | { | |
4d7206a2 | 7476 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7477 | offset_expr.X_add_number = 0; |
7478 | ||
4d7206a2 | 7479 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7480 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7481 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7482 | |
7483 | if (expr1.X_add_number >= -0x8000 | |
7484 | && expr1.X_add_number < 0x8000) | |
7485 | { | |
67c0d1eb RS |
7486 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7487 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7488 | } |
ecd13cd3 | 7489 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7490 | { |
f5040a92 AO |
7491 | /* If we are going to add in a base register, and the |
7492 | target register and the base register are the same, | |
7493 | then we are using AT as a temporary register. Since | |
7494 | we want to load the constant into AT, we add our | |
7495 | current AT (from the global offset table) and the | |
7496 | register into the register now, and pretend we were | |
7497 | not using a base register. */ | |
7498 | if (breg != treg) | |
7499 | dreg = tempreg; | |
7500 | else | |
7501 | { | |
9c2799c2 | 7502 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7503 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7504 | treg, AT, breg); | |
f5040a92 | 7505 | dreg = treg; |
67c0d1eb | 7506 | add_breg_early = 1; |
f5040a92 AO |
7507 | } |
7508 | ||
f6a22291 | 7509 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7510 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7511 | dreg, dreg, AT); |
f5040a92 | 7512 | |
f5040a92 AO |
7513 | used_at = 1; |
7514 | } | |
7515 | else | |
7516 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7517 | ||
4d7206a2 | 7518 | relax_switch (); |
f5040a92 AO |
7519 | offset_expr.X_add_number = expr1.X_add_number; |
7520 | ||
67c0d1eb RS |
7521 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7522 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7523 | if (add_breg_early) | |
f5040a92 | 7524 | { |
67c0d1eb | 7525 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7526 | treg, tempreg, breg); |
f5040a92 AO |
7527 | breg = 0; |
7528 | tempreg = treg; | |
7529 | } | |
4d7206a2 | 7530 | relax_end (); |
f5040a92 | 7531 | } |
4d7206a2 | 7532 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7533 | { |
4d7206a2 | 7534 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7535 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7536 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7537 | relax_switch (); |
67c0d1eb RS |
7538 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7539 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7540 | relax_end (); |
f5040a92 | 7541 | } |
4d7206a2 | 7542 | else |
f5040a92 | 7543 | { |
67c0d1eb RS |
7544 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7545 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7546 | } |
7547 | } | |
0a44bf69 | 7548 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7549 | { |
67c0d1eb | 7550 | int gpdelay; |
9117d219 NC |
7551 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7552 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7553 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7554 | |
7555 | /* This is the large GOT case. If this is a reference to an | |
7556 | external symbol, and there is no constant, we want | |
7557 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7558 | addu $tempreg,$tempreg,$gp | |
7559 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7560 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7561 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7562 | addu $tempreg,$tempreg,$gp | |
7563 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7564 | For a local symbol, we want |
7565 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7566 | nop | |
7567 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7568 | ||
7569 | If we have a small constant, and this is a reference to | |
7570 | an external symbol, we want | |
7571 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7572 | addu $tempreg,$tempreg,$gp | |
7573 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7574 | nop | |
7575 | addiu $tempreg,$tempreg,<constant> | |
7576 | For a local symbol, we want | |
7577 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7578 | nop | |
7579 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7580 | ||
7581 | If we have a large constant, and this is a reference to | |
7582 | an external symbol, we want | |
7583 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7584 | addu $tempreg,$tempreg,$gp | |
7585 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7586 | lui $at,<hiconstant> | |
7587 | addiu $at,$at,<loconstant> | |
7588 | addu $tempreg,$tempreg,$at | |
7589 | For a local symbol, we want | |
7590 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7591 | lui $at,<hiconstant> | |
7592 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7593 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7594 | */ |
438c16b8 | 7595 | |
252b5132 RH |
7596 | expr1.X_add_number = offset_expr.X_add_number; |
7597 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7598 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7599 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7600 | if (expr1.X_add_number == 0 && breg == 0 |
7601 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7602 | { |
7603 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7604 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7605 | } | |
df58fc94 | 7606 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7607 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7608 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7609 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7610 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7611 | if (expr1.X_add_number == 0) |
7612 | { | |
67c0d1eb | 7613 | if (breg != 0) |
252b5132 RH |
7614 | { |
7615 | /* We're going to put in an addu instruction using | |
7616 | tempreg, so we may as well insert the nop right | |
7617 | now. */ | |
269137b2 | 7618 | load_delay_nop (); |
252b5132 | 7619 | } |
252b5132 RH |
7620 | } |
7621 | else if (expr1.X_add_number >= -0x8000 | |
7622 | && expr1.X_add_number < 0x8000) | |
7623 | { | |
269137b2 | 7624 | load_delay_nop (); |
67c0d1eb | 7625 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7626 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7627 | } |
7628 | else | |
7629 | { | |
252b5132 RH |
7630 | /* If we are going to add in a base register, and the |
7631 | target register and the base register are the same, | |
7632 | then we are using AT as a temporary register. Since | |
7633 | we want to load the constant into AT, we add our | |
7634 | current AT (from the global offset table) and the | |
7635 | register into the register now, and pretend we were | |
7636 | not using a base register. */ | |
7637 | if (breg != treg) | |
67c0d1eb | 7638 | dreg = tempreg; |
252b5132 RH |
7639 | else |
7640 | { | |
9c2799c2 | 7641 | gas_assert (tempreg == AT); |
269137b2 | 7642 | load_delay_nop (); |
67c0d1eb | 7643 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7644 | treg, AT, breg); |
252b5132 | 7645 | dreg = treg; |
252b5132 RH |
7646 | } |
7647 | ||
f6a22291 | 7648 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7649 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7650 | |
252b5132 RH |
7651 | used_at = 1; |
7652 | } | |
43c0598f | 7653 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7654 | relax_switch (); |
252b5132 | 7655 | |
67c0d1eb | 7656 | if (gpdelay) |
252b5132 RH |
7657 | { |
7658 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7659 | the first instruction on the main stream does not. */ |
67c0d1eb | 7660 | macro_build (NULL, "nop", ""); |
252b5132 | 7661 | } |
ed6fb7bd | 7662 | |
67c0d1eb RS |
7663 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7664 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7665 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7666 | && expr1.X_add_number < 0x8000) |
7667 | { | |
269137b2 | 7668 | load_delay_nop (); |
67c0d1eb RS |
7669 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7670 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7671 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7672 | register, the external symbol case ended with a load, |
7673 | so if the symbol turns out to not be external, and | |
7674 | the next instruction uses tempreg, an unnecessary nop | |
7675 | will be inserted. */ | |
252b5132 RH |
7676 | } |
7677 | else | |
7678 | { | |
7679 | if (breg == treg) | |
7680 | { | |
7681 | /* We must add in the base register now, as in the | |
f5040a92 | 7682 | external symbol case. */ |
9c2799c2 | 7683 | gas_assert (tempreg == AT); |
269137b2 | 7684 | load_delay_nop (); |
67c0d1eb | 7685 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7686 | treg, AT, breg); |
252b5132 RH |
7687 | tempreg = treg; |
7688 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7689 | it in in both cases. */ |
252b5132 RH |
7690 | breg = 0; |
7691 | } | |
7692 | ||
67c0d1eb RS |
7693 | macro_build_lui (&expr1, AT); |
7694 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7695 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7696 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7697 | tempreg, tempreg, AT); |
8fc2e39e | 7698 | used_at = 1; |
252b5132 | 7699 | } |
4d7206a2 | 7700 | relax_end (); |
252b5132 | 7701 | } |
0a44bf69 | 7702 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7703 | { |
f5040a92 AO |
7704 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7705 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7706 | int add_breg_early = 0; |
f5040a92 AO |
7707 | |
7708 | /* This is the large GOT case. If this is a reference to an | |
7709 | external symbol, and there is no constant, we want | |
7710 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7711 | add $tempreg,$tempreg,$gp | |
7712 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7713 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7714 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7715 | add $tempreg,$tempreg,$gp | |
7716 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7717 | ||
7718 | If we have a small constant, and this is a reference to | |
7719 | an external symbol, we want | |
7720 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7721 | add $tempreg,$tempreg,$gp | |
7722 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7723 | addi $tempreg,$tempreg,<constant> | |
7724 | ||
7725 | If we have a large constant, and this is a reference to | |
7726 | an external symbol, we want | |
7727 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7728 | addu $tempreg,$tempreg,$gp | |
7729 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7730 | lui $at,<hiconstant> | |
7731 | addi $at,$at,<loconstant> | |
7732 | add $tempreg,$tempreg,$at | |
7733 | ||
7734 | If we have NewABI, and we know it's a local symbol, we want | |
7735 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7736 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7737 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7738 | ||
4d7206a2 | 7739 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7740 | |
4d7206a2 | 7741 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7742 | offset_expr.X_add_number = 0; |
7743 | ||
1abe91b1 MR |
7744 | if (expr1.X_add_number == 0 && breg == 0 |
7745 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7746 | { |
7747 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7748 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7749 | } | |
df58fc94 | 7750 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7751 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7752 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7753 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7754 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7755 | |
7756 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7757 | ; |
f5040a92 AO |
7758 | else if (expr1.X_add_number >= -0x8000 |
7759 | && expr1.X_add_number < 0x8000) | |
7760 | { | |
67c0d1eb | 7761 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7762 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7763 | } |
ecd13cd3 | 7764 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7765 | { |
f5040a92 AO |
7766 | /* If we are going to add in a base register, and the |
7767 | target register and the base register are the same, | |
7768 | then we are using AT as a temporary register. Since | |
7769 | we want to load the constant into AT, we add our | |
7770 | current AT (from the global offset table) and the | |
7771 | register into the register now, and pretend we were | |
7772 | not using a base register. */ | |
7773 | if (breg != treg) | |
7774 | dreg = tempreg; | |
7775 | else | |
7776 | { | |
9c2799c2 | 7777 | gas_assert (tempreg == AT); |
67c0d1eb | 7778 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7779 | treg, AT, breg); |
f5040a92 | 7780 | dreg = treg; |
67c0d1eb | 7781 | add_breg_early = 1; |
f5040a92 AO |
7782 | } |
7783 | ||
f6a22291 | 7784 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7785 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7786 | |
f5040a92 AO |
7787 | used_at = 1; |
7788 | } | |
7789 | else | |
7790 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7791 | ||
4d7206a2 | 7792 | relax_switch (); |
f5040a92 | 7793 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7794 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7795 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7796 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7797 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7798 | if (add_breg_early) | |
f5040a92 | 7799 | { |
67c0d1eb | 7800 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7801 | treg, tempreg, breg); |
f5040a92 AO |
7802 | breg = 0; |
7803 | tempreg = treg; | |
7804 | } | |
4d7206a2 | 7805 | relax_end (); |
f5040a92 | 7806 | } |
252b5132 RH |
7807 | else |
7808 | abort (); | |
7809 | ||
7810 | if (breg != 0) | |
aed1a261 | 7811 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7812 | break; |
7813 | ||
52b6b6b9 | 7814 | case M_MSGSND: |
df58fc94 | 7815 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7816 | { |
7817 | unsigned long temp = (treg << 16) | (0x01); | |
7818 | macro_build (NULL, "c2", "C", temp); | |
7819 | } | |
c7af4273 | 7820 | break; |
52b6b6b9 JM |
7821 | |
7822 | case M_MSGLD: | |
df58fc94 | 7823 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7824 | { |
7825 | unsigned long temp = (0x02); | |
7826 | macro_build (NULL, "c2", "C", temp); | |
7827 | } | |
c7af4273 | 7828 | break; |
52b6b6b9 JM |
7829 | |
7830 | case M_MSGLD_T: | |
df58fc94 | 7831 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7832 | { |
7833 | unsigned long temp = (treg << 16) | (0x02); | |
7834 | macro_build (NULL, "c2", "C", temp); | |
7835 | } | |
c7af4273 | 7836 | break; |
52b6b6b9 JM |
7837 | |
7838 | case M_MSGWAIT: | |
df58fc94 | 7839 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7840 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7841 | break; |
52b6b6b9 JM |
7842 | |
7843 | case M_MSGWAIT_T: | |
df58fc94 | 7844 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7845 | { |
7846 | unsigned long temp = (treg << 16) | 0x03; | |
7847 | macro_build (NULL, "c2", "C", temp); | |
7848 | } | |
c7af4273 | 7849 | break; |
52b6b6b9 | 7850 | |
252b5132 RH |
7851 | case M_J_A: |
7852 | /* The j instruction may not be used in PIC code, since it | |
7853 | requires an absolute address. We convert it to a b | |
7854 | instruction. */ | |
7855 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7856 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7857 | else |
67c0d1eb | 7858 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7859 | break; |
252b5132 RH |
7860 | |
7861 | /* The jal instructions must be handled as macros because when | |
7862 | generating PIC code they expand to multi-instruction | |
7863 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7864 | case M_JALS_1: |
7865 | dreg = RA; | |
7866 | /* Fall through. */ | |
7867 | case M_JALS_2: | |
7868 | gas_assert (mips_opts.micromips); | |
7869 | jals = 1; | |
7870 | goto jal; | |
252b5132 RH |
7871 | case M_JAL_1: |
7872 | dreg = RA; | |
7873 | /* Fall through. */ | |
7874 | case M_JAL_2: | |
df58fc94 | 7875 | jal: |
3e722fb5 | 7876 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7877 | { |
7878 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7879 | if (mips_opts.micromips |
7880 | && dreg == RA | |
7881 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7882 | macro_build (NULL, s, "mj", sreg); |
7883 | else | |
7884 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7885 | } | |
0a44bf69 | 7886 | else |
252b5132 | 7887 | { |
df58fc94 RS |
7888 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7889 | && mips_cprestore_offset >= 0); | |
7890 | ||
252b5132 RH |
7891 | if (sreg != PIC_CALL_REG) |
7892 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7893 | |
df58fc94 RS |
7894 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7895 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7896 | if (mips_opts.micromips |
7897 | && dreg == RA | |
7898 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7899 | macro_build (NULL, s, "mj", sreg); |
7900 | else | |
7901 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7902 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7903 | { |
6478892d TS |
7904 | if (mips_cprestore_offset < 0) |
7905 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7906 | else | |
7907 | { | |
90ecf173 | 7908 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7909 | { |
7910 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7911 | /* Quiet this warning. */ | |
7912 | mips_frame_reg_valid = 1; | |
7913 | } | |
90ecf173 | 7914 | if (!mips_cprestore_valid) |
7a621144 DJ |
7915 | { |
7916 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7917 | /* Quiet this warning. */ | |
7918 | mips_cprestore_valid = 1; | |
7919 | } | |
d3fca0b5 MR |
7920 | if (mips_opts.noreorder) |
7921 | macro_build (NULL, "nop", ""); | |
6478892d | 7922 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7923 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7924 | mips_gp_register, |
256ab948 TS |
7925 | mips_frame_reg, |
7926 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7927 | } |
252b5132 RH |
7928 | } |
7929 | } | |
252b5132 | 7930 | |
8fc2e39e | 7931 | break; |
252b5132 | 7932 | |
df58fc94 RS |
7933 | case M_JALS_A: |
7934 | gas_assert (mips_opts.micromips); | |
7935 | jals = 1; | |
7936 | /* Fall through. */ | |
252b5132 RH |
7937 | case M_JAL_A: |
7938 | if (mips_pic == NO_PIC) | |
df58fc94 | 7939 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7940 | else if (mips_pic == SVR4_PIC) |
7941 | { | |
7942 | /* If this is a reference to an external symbol, and we are | |
7943 | using a small GOT, we want | |
7944 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7945 | nop | |
f9419b05 | 7946 | jalr $ra,$25 |
252b5132 RH |
7947 | nop |
7948 | lw $gp,cprestore($sp) | |
7949 | The cprestore value is set using the .cprestore | |
7950 | pseudo-op. If we are using a big GOT, we want | |
7951 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7952 | addu $25,$25,$gp | |
7953 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7954 | nop | |
f9419b05 | 7955 | jalr $ra,$25 |
252b5132 RH |
7956 | nop |
7957 | lw $gp,cprestore($sp) | |
7958 | If the symbol is not external, we want | |
7959 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7960 | nop | |
7961 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7962 | jalr $ra,$25 |
252b5132 | 7963 | nop |
438c16b8 | 7964 | lw $gp,cprestore($sp) |
f5040a92 AO |
7965 | |
7966 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7967 | sequences above, minus nops, unless the symbol is local, | |
7968 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7969 | GOT_DISP. */ | |
438c16b8 | 7970 | if (HAVE_NEWABI) |
252b5132 | 7971 | { |
90ecf173 | 7972 | if (!mips_big_got) |
f5040a92 | 7973 | { |
4d7206a2 | 7974 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7975 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7976 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7977 | mips_gp_register); |
4d7206a2 | 7978 | relax_switch (); |
67c0d1eb RS |
7979 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7980 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7981 | mips_gp_register); |
7982 | relax_end (); | |
f5040a92 AO |
7983 | } |
7984 | else | |
7985 | { | |
4d7206a2 | 7986 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7987 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7988 | BFD_RELOC_MIPS_CALL_HI16); |
7989 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7990 | PIC_CALL_REG, mips_gp_register); | |
7991 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7992 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7993 | PIC_CALL_REG); | |
4d7206a2 | 7994 | relax_switch (); |
67c0d1eb RS |
7995 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7996 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7997 | mips_gp_register); | |
7998 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7999 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8000 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8001 | relax_end (); |
f5040a92 | 8002 | } |
684022ea | 8003 | |
df58fc94 | 8004 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8005 | } |
8006 | else | |
8007 | { | |
4d7206a2 | 8008 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8009 | if (!mips_big_got) |
438c16b8 | 8010 | { |
67c0d1eb RS |
8011 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8012 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8013 | mips_gp_register); |
269137b2 | 8014 | load_delay_nop (); |
4d7206a2 | 8015 | relax_switch (); |
438c16b8 | 8016 | } |
252b5132 | 8017 | else |
252b5132 | 8018 | { |
67c0d1eb RS |
8019 | int gpdelay; |
8020 | ||
8021 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8022 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8023 | BFD_RELOC_MIPS_CALL_HI16); |
8024 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8025 | PIC_CALL_REG, mips_gp_register); | |
8026 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8027 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8028 | PIC_CALL_REG); | |
269137b2 | 8029 | load_delay_nop (); |
4d7206a2 | 8030 | relax_switch (); |
67c0d1eb RS |
8031 | if (gpdelay) |
8032 | macro_build (NULL, "nop", ""); | |
252b5132 | 8033 | } |
67c0d1eb RS |
8034 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8035 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8036 | mips_gp_register); |
269137b2 | 8037 | load_delay_nop (); |
67c0d1eb RS |
8038 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8039 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8040 | relax_end (); |
df58fc94 | 8041 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8042 | |
6478892d TS |
8043 | if (mips_cprestore_offset < 0) |
8044 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8045 | else | |
8046 | { | |
90ecf173 | 8047 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8048 | { |
8049 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8050 | /* Quiet this warning. */ | |
8051 | mips_frame_reg_valid = 1; | |
8052 | } | |
90ecf173 | 8053 | if (!mips_cprestore_valid) |
7a621144 DJ |
8054 | { |
8055 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8056 | /* Quiet this warning. */ | |
8057 | mips_cprestore_valid = 1; | |
8058 | } | |
6478892d | 8059 | if (mips_opts.noreorder) |
67c0d1eb | 8060 | macro_build (NULL, "nop", ""); |
6478892d | 8061 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8062 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8063 | mips_gp_register, |
256ab948 TS |
8064 | mips_frame_reg, |
8065 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8066 | } |
252b5132 RH |
8067 | } |
8068 | } | |
0a44bf69 RS |
8069 | else if (mips_pic == VXWORKS_PIC) |
8070 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8071 | else |
8072 | abort (); | |
8073 | ||
8fc2e39e | 8074 | break; |
252b5132 | 8075 | |
dec0624d MR |
8076 | case M_ACLR_AB: |
8077 | ab = 1; | |
8078 | case M_ACLR_OB: | |
8079 | s = "aclr"; | |
8080 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8081 | fmt = "\\,~(b)"; | |
8082 | off12 = 1; | |
8083 | goto ld_st; | |
8084 | case M_ASET_AB: | |
8085 | ab = 1; | |
8086 | case M_ASET_OB: | |
8087 | s = "aset"; | |
8088 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8089 | fmt = "\\,~(b)"; | |
8090 | off12 = 1; | |
8091 | goto ld_st; | |
252b5132 | 8092 | case M_LB_AB: |
df58fc94 | 8093 | ab = 1; |
252b5132 | 8094 | s = "lb"; |
df58fc94 | 8095 | fmt = "t,o(b)"; |
252b5132 RH |
8096 | goto ld; |
8097 | case M_LBU_AB: | |
df58fc94 | 8098 | ab = 1; |
252b5132 | 8099 | s = "lbu"; |
df58fc94 | 8100 | fmt = "t,o(b)"; |
252b5132 RH |
8101 | goto ld; |
8102 | case M_LH_AB: | |
df58fc94 | 8103 | ab = 1; |
252b5132 | 8104 | s = "lh"; |
df58fc94 | 8105 | fmt = "t,o(b)"; |
252b5132 RH |
8106 | goto ld; |
8107 | case M_LHU_AB: | |
df58fc94 | 8108 | ab = 1; |
252b5132 | 8109 | s = "lhu"; |
df58fc94 | 8110 | fmt = "t,o(b)"; |
252b5132 RH |
8111 | goto ld; |
8112 | case M_LW_AB: | |
df58fc94 | 8113 | ab = 1; |
252b5132 | 8114 | s = "lw"; |
df58fc94 | 8115 | fmt = "t,o(b)"; |
252b5132 RH |
8116 | goto ld; |
8117 | case M_LWC0_AB: | |
df58fc94 RS |
8118 | ab = 1; |
8119 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8120 | s = "lwc0"; |
df58fc94 | 8121 | fmt = "E,o(b)"; |
bdaaa2e1 | 8122 | /* Itbl support may require additional care here. */ |
252b5132 | 8123 | coproc = 1; |
df58fc94 | 8124 | goto ld_st; |
252b5132 | 8125 | case M_LWC1_AB: |
df58fc94 | 8126 | ab = 1; |
252b5132 | 8127 | s = "lwc1"; |
df58fc94 | 8128 | fmt = "T,o(b)"; |
bdaaa2e1 | 8129 | /* Itbl support may require additional care here. */ |
252b5132 | 8130 | coproc = 1; |
df58fc94 | 8131 | goto ld_st; |
252b5132 | 8132 | case M_LWC2_AB: |
df58fc94 RS |
8133 | ab = 1; |
8134 | case M_LWC2_OB: | |
252b5132 | 8135 | s = "lwc2"; |
df58fc94 RS |
8136 | fmt = COP12_FMT; |
8137 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8138 | /* Itbl support may require additional care here. */ |
252b5132 | 8139 | coproc = 1; |
df58fc94 | 8140 | goto ld_st; |
252b5132 | 8141 | case M_LWC3_AB: |
df58fc94 RS |
8142 | ab = 1; |
8143 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8144 | s = "lwc3"; |
df58fc94 | 8145 | fmt = "E,o(b)"; |
bdaaa2e1 | 8146 | /* Itbl support may require additional care here. */ |
252b5132 | 8147 | coproc = 1; |
df58fc94 | 8148 | goto ld_st; |
252b5132 | 8149 | case M_LWL_AB: |
df58fc94 RS |
8150 | ab = 1; |
8151 | case M_LWL_OB: | |
252b5132 | 8152 | s = "lwl"; |
df58fc94 RS |
8153 | fmt = MEM12_FMT; |
8154 | off12 = mips_opts.micromips; | |
8155 | goto ld_st; | |
252b5132 | 8156 | case M_LWR_AB: |
df58fc94 RS |
8157 | ab = 1; |
8158 | case M_LWR_OB: | |
252b5132 | 8159 | s = "lwr"; |
df58fc94 RS |
8160 | fmt = MEM12_FMT; |
8161 | off12 = mips_opts.micromips; | |
8162 | goto ld_st; | |
252b5132 | 8163 | case M_LDC1_AB: |
df58fc94 | 8164 | ab = 1; |
252b5132 | 8165 | s = "ldc1"; |
df58fc94 | 8166 | fmt = "T,o(b)"; |
bdaaa2e1 | 8167 | /* Itbl support may require additional care here. */ |
252b5132 | 8168 | coproc = 1; |
df58fc94 | 8169 | goto ld_st; |
252b5132 | 8170 | case M_LDC2_AB: |
df58fc94 RS |
8171 | ab = 1; |
8172 | case M_LDC2_OB: | |
252b5132 | 8173 | s = "ldc2"; |
df58fc94 RS |
8174 | fmt = COP12_FMT; |
8175 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8176 | /* Itbl support may require additional care here. */ |
252b5132 | 8177 | coproc = 1; |
df58fc94 | 8178 | goto ld_st; |
252b5132 | 8179 | case M_LDC3_AB: |
df58fc94 | 8180 | ab = 1; |
252b5132 | 8181 | s = "ldc3"; |
df58fc94 | 8182 | fmt = "E,o(b)"; |
bdaaa2e1 | 8183 | /* Itbl support may require additional care here. */ |
252b5132 | 8184 | coproc = 1; |
df58fc94 | 8185 | goto ld_st; |
252b5132 | 8186 | case M_LDL_AB: |
df58fc94 RS |
8187 | ab = 1; |
8188 | case M_LDL_OB: | |
252b5132 | 8189 | s = "ldl"; |
df58fc94 RS |
8190 | fmt = MEM12_FMT; |
8191 | off12 = mips_opts.micromips; | |
8192 | goto ld_st; | |
252b5132 | 8193 | case M_LDR_AB: |
df58fc94 RS |
8194 | ab = 1; |
8195 | case M_LDR_OB: | |
252b5132 | 8196 | s = "ldr"; |
df58fc94 RS |
8197 | fmt = MEM12_FMT; |
8198 | off12 = mips_opts.micromips; | |
8199 | goto ld_st; | |
252b5132 | 8200 | case M_LL_AB: |
df58fc94 RS |
8201 | ab = 1; |
8202 | case M_LL_OB: | |
252b5132 | 8203 | s = "ll"; |
df58fc94 RS |
8204 | fmt = MEM12_FMT; |
8205 | off12 = mips_opts.micromips; | |
252b5132 RH |
8206 | goto ld; |
8207 | case M_LLD_AB: | |
df58fc94 RS |
8208 | ab = 1; |
8209 | case M_LLD_OB: | |
252b5132 | 8210 | s = "lld"; |
df58fc94 RS |
8211 | fmt = MEM12_FMT; |
8212 | off12 = mips_opts.micromips; | |
252b5132 RH |
8213 | goto ld; |
8214 | case M_LWU_AB: | |
df58fc94 RS |
8215 | ab = 1; |
8216 | case M_LWU_OB: | |
252b5132 | 8217 | s = "lwu"; |
df58fc94 RS |
8218 | fmt = MEM12_FMT; |
8219 | off12 = mips_opts.micromips; | |
8220 | goto ld; | |
8221 | case M_LWP_AB: | |
8222 | ab = 1; | |
8223 | case M_LWP_OB: | |
8224 | gas_assert (mips_opts.micromips); | |
8225 | s = "lwp"; | |
8226 | fmt = "t,~(b)"; | |
8227 | off12 = 1; | |
8228 | lp = 1; | |
8229 | goto ld; | |
8230 | case M_LDP_AB: | |
8231 | ab = 1; | |
8232 | case M_LDP_OB: | |
8233 | gas_assert (mips_opts.micromips); | |
8234 | s = "ldp"; | |
8235 | fmt = "t,~(b)"; | |
8236 | off12 = 1; | |
8237 | lp = 1; | |
8238 | goto ld; | |
8239 | case M_LWM_AB: | |
8240 | ab = 1; | |
8241 | case M_LWM_OB: | |
8242 | gas_assert (mips_opts.micromips); | |
8243 | s = "lwm"; | |
8244 | fmt = "n,~(b)"; | |
8245 | off12 = 1; | |
8246 | goto ld_st; | |
8247 | case M_LDM_AB: | |
8248 | ab = 1; | |
8249 | case M_LDM_OB: | |
8250 | gas_assert (mips_opts.micromips); | |
8251 | s = "ldm"; | |
8252 | fmt = "n,~(b)"; | |
8253 | off12 = 1; | |
8254 | goto ld_st; | |
8255 | ||
252b5132 | 8256 | ld: |
df58fc94 RS |
8257 | if (breg == treg + lp) |
8258 | goto ld_st; | |
252b5132 | 8259 | else |
df58fc94 RS |
8260 | tempreg = treg + lp; |
8261 | goto ld_noat; | |
8262 | ||
252b5132 | 8263 | case M_SB_AB: |
df58fc94 | 8264 | ab = 1; |
252b5132 | 8265 | s = "sb"; |
df58fc94 RS |
8266 | fmt = "t,o(b)"; |
8267 | goto ld_st; | |
252b5132 | 8268 | case M_SH_AB: |
df58fc94 | 8269 | ab = 1; |
252b5132 | 8270 | s = "sh"; |
df58fc94 RS |
8271 | fmt = "t,o(b)"; |
8272 | goto ld_st; | |
252b5132 | 8273 | case M_SW_AB: |
df58fc94 | 8274 | ab = 1; |
252b5132 | 8275 | s = "sw"; |
df58fc94 RS |
8276 | fmt = "t,o(b)"; |
8277 | goto ld_st; | |
252b5132 | 8278 | case M_SWC0_AB: |
df58fc94 RS |
8279 | ab = 1; |
8280 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8281 | s = "swc0"; |
df58fc94 | 8282 | fmt = "E,o(b)"; |
bdaaa2e1 | 8283 | /* Itbl support may require additional care here. */ |
252b5132 | 8284 | coproc = 1; |
df58fc94 | 8285 | goto ld_st; |
252b5132 | 8286 | case M_SWC1_AB: |
df58fc94 | 8287 | ab = 1; |
252b5132 | 8288 | s = "swc1"; |
df58fc94 | 8289 | fmt = "T,o(b)"; |
bdaaa2e1 | 8290 | /* Itbl support may require additional care here. */ |
252b5132 | 8291 | coproc = 1; |
df58fc94 | 8292 | goto ld_st; |
252b5132 | 8293 | case M_SWC2_AB: |
df58fc94 RS |
8294 | ab = 1; |
8295 | case M_SWC2_OB: | |
252b5132 | 8296 | s = "swc2"; |
df58fc94 RS |
8297 | fmt = COP12_FMT; |
8298 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8299 | /* Itbl support may require additional care here. */ |
252b5132 | 8300 | coproc = 1; |
df58fc94 | 8301 | goto ld_st; |
252b5132 | 8302 | case M_SWC3_AB: |
df58fc94 RS |
8303 | ab = 1; |
8304 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8305 | s = "swc3"; |
df58fc94 | 8306 | fmt = "E,o(b)"; |
bdaaa2e1 | 8307 | /* Itbl support may require additional care here. */ |
252b5132 | 8308 | coproc = 1; |
df58fc94 | 8309 | goto ld_st; |
252b5132 | 8310 | case M_SWL_AB: |
df58fc94 RS |
8311 | ab = 1; |
8312 | case M_SWL_OB: | |
252b5132 | 8313 | s = "swl"; |
df58fc94 RS |
8314 | fmt = MEM12_FMT; |
8315 | off12 = mips_opts.micromips; | |
8316 | goto ld_st; | |
252b5132 | 8317 | case M_SWR_AB: |
df58fc94 RS |
8318 | ab = 1; |
8319 | case M_SWR_OB: | |
252b5132 | 8320 | s = "swr"; |
df58fc94 RS |
8321 | fmt = MEM12_FMT; |
8322 | off12 = mips_opts.micromips; | |
8323 | goto ld_st; | |
252b5132 | 8324 | case M_SC_AB: |
df58fc94 RS |
8325 | ab = 1; |
8326 | case M_SC_OB: | |
252b5132 | 8327 | s = "sc"; |
df58fc94 RS |
8328 | fmt = MEM12_FMT; |
8329 | off12 = mips_opts.micromips; | |
8330 | goto ld_st; | |
252b5132 | 8331 | case M_SCD_AB: |
df58fc94 RS |
8332 | ab = 1; |
8333 | case M_SCD_OB: | |
252b5132 | 8334 | s = "scd"; |
df58fc94 RS |
8335 | fmt = MEM12_FMT; |
8336 | off12 = mips_opts.micromips; | |
8337 | goto ld_st; | |
d43b4baf | 8338 | case M_CACHE_AB: |
df58fc94 RS |
8339 | ab = 1; |
8340 | case M_CACHE_OB: | |
d43b4baf | 8341 | s = "cache"; |
df58fc94 RS |
8342 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8343 | off12 = mips_opts.micromips; | |
8344 | goto ld_st; | |
3eebd5eb | 8345 | case M_PREF_AB: |
df58fc94 RS |
8346 | ab = 1; |
8347 | case M_PREF_OB: | |
3eebd5eb | 8348 | s = "pref"; |
df58fc94 RS |
8349 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8350 | off12 = mips_opts.micromips; | |
8351 | goto ld_st; | |
252b5132 | 8352 | case M_SDC1_AB: |
df58fc94 | 8353 | ab = 1; |
252b5132 | 8354 | s = "sdc1"; |
df58fc94 | 8355 | fmt = "T,o(b)"; |
252b5132 | 8356 | coproc = 1; |
bdaaa2e1 | 8357 | /* Itbl support may require additional care here. */ |
df58fc94 | 8358 | goto ld_st; |
252b5132 | 8359 | case M_SDC2_AB: |
df58fc94 RS |
8360 | ab = 1; |
8361 | case M_SDC2_OB: | |
252b5132 | 8362 | s = "sdc2"; |
df58fc94 RS |
8363 | fmt = COP12_FMT; |
8364 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8365 | /* Itbl support may require additional care here. */ |
252b5132 | 8366 | coproc = 1; |
df58fc94 | 8367 | goto ld_st; |
252b5132 | 8368 | case M_SDC3_AB: |
df58fc94 RS |
8369 | ab = 1; |
8370 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8371 | s = "sdc3"; |
df58fc94 | 8372 | fmt = "E,o(b)"; |
bdaaa2e1 | 8373 | /* Itbl support may require additional care here. */ |
252b5132 | 8374 | coproc = 1; |
df58fc94 | 8375 | goto ld_st; |
252b5132 | 8376 | case M_SDL_AB: |
df58fc94 RS |
8377 | ab = 1; |
8378 | case M_SDL_OB: | |
252b5132 | 8379 | s = "sdl"; |
df58fc94 RS |
8380 | fmt = MEM12_FMT; |
8381 | off12 = mips_opts.micromips; | |
8382 | goto ld_st; | |
252b5132 | 8383 | case M_SDR_AB: |
df58fc94 RS |
8384 | ab = 1; |
8385 | case M_SDR_OB: | |
252b5132 | 8386 | s = "sdr"; |
df58fc94 RS |
8387 | fmt = MEM12_FMT; |
8388 | off12 = mips_opts.micromips; | |
8389 | goto ld_st; | |
8390 | case M_SWP_AB: | |
8391 | ab = 1; | |
8392 | case M_SWP_OB: | |
8393 | gas_assert (mips_opts.micromips); | |
8394 | s = "swp"; | |
8395 | fmt = "t,~(b)"; | |
8396 | off12 = 1; | |
8397 | goto ld_st; | |
8398 | case M_SDP_AB: | |
8399 | ab = 1; | |
8400 | case M_SDP_OB: | |
8401 | gas_assert (mips_opts.micromips); | |
8402 | s = "sdp"; | |
8403 | fmt = "t,~(b)"; | |
8404 | off12 = 1; | |
8405 | goto ld_st; | |
8406 | case M_SWM_AB: | |
8407 | ab = 1; | |
8408 | case M_SWM_OB: | |
8409 | gas_assert (mips_opts.micromips); | |
8410 | s = "swm"; | |
8411 | fmt = "n,~(b)"; | |
8412 | off12 = 1; | |
8413 | goto ld_st; | |
8414 | case M_SDM_AB: | |
8415 | ab = 1; | |
8416 | case M_SDM_OB: | |
8417 | gas_assert (mips_opts.micromips); | |
8418 | s = "sdm"; | |
8419 | fmt = "n,~(b)"; | |
8420 | off12 = 1; | |
8421 | ||
8422 | ld_st: | |
8fc2e39e TS |
8423 | tempreg = AT; |
8424 | used_at = 1; | |
df58fc94 | 8425 | ld_noat: |
252b5132 RH |
8426 | if (offset_expr.X_op != O_constant |
8427 | && offset_expr.X_op != O_symbol) | |
8428 | { | |
f71d0d44 | 8429 | as_bad (_("Expression too complex")); |
252b5132 RH |
8430 | offset_expr.X_op = O_constant; |
8431 | } | |
8432 | ||
2051e8c4 MR |
8433 | if (HAVE_32BIT_ADDRESSES |
8434 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8435 | { |
8436 | char value [32]; | |
8437 | ||
8438 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8439 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8440 | } |
2051e8c4 | 8441 | |
252b5132 RH |
8442 | /* A constant expression in PIC code can be handled just as it |
8443 | is in non PIC code. */ | |
aed1a261 RS |
8444 | if (offset_expr.X_op == O_constant) |
8445 | { | |
df58fc94 RS |
8446 | int hipart = 0; |
8447 | ||
842f8b2a | 8448 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8449 | normalize_address_expr (&expr1); |
df58fc94 | 8450 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8451 | { |
8452 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8453 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8454 | hipart = 1; |
8455 | } | |
8456 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8457 | { | |
8458 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8459 | & ~(bfd_vma) 0xfff); | |
8460 | hipart = 1; | |
8461 | } | |
8462 | if (hipart) | |
8463 | { | |
842f8b2a MR |
8464 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8465 | if (breg != 0) | |
8466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8467 | tempreg, tempreg, breg); | |
8468 | breg = tempreg; | |
8469 | } | |
dd6a37e7 AP |
8470 | if (off0) |
8471 | { | |
8472 | if (offset_expr.X_add_number == 0) | |
8473 | tempreg = breg; | |
8474 | else | |
8475 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8476 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8477 | macro_build (NULL, s, fmt, treg, tempreg); | |
8478 | } | |
8479 | else if (!off12) | |
df58fc94 RS |
8480 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8481 | else | |
8482 | macro_build (NULL, s, fmt, | |
8483 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8484 | } | |
dd6a37e7 | 8485 | else if (off12 || off0) |
df58fc94 | 8486 | { |
dd6a37e7 AP |
8487 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8488 | for a low-part relocation, so load the whole address into | |
8489 | the auxillary register. In the case of "A(b)" addresses, | |
8490 | we first load absolute address "A" into the register and | |
8491 | then add base register "b". In the case of "o(b)" addresses, | |
8492 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8493 | offset_reloc already contains the relocations associated |
8494 | with "o". */ | |
8495 | if (ab) | |
8496 | { | |
8497 | load_address (tempreg, &offset_expr, &used_at); | |
8498 | if (breg != 0) | |
8499 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8500 | tempreg, tempreg, breg); | |
8501 | } | |
8502 | else | |
8503 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8504 | tempreg, breg, -1, | |
8505 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8506 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8507 | if (off0) |
8508 | macro_build (NULL, s, fmt, treg, tempreg); | |
8509 | else | |
8510 | macro_build (NULL, s, fmt, | |
8511 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8512 | } |
8513 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8514 | { |
8515 | /* If this is a reference to a GP relative symbol, and there | |
8516 | is no base register, we want | |
cdf6fd85 | 8517 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8518 | Otherwise, if there is no base register, we want |
8519 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8520 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8521 | If we have a constant, we need two instructions anyhow, | |
8522 | so we always use the latter form. | |
8523 | ||
8524 | If we have a base register, and this is a reference to a | |
8525 | GP relative symbol, we want | |
8526 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8527 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8528 | Otherwise we want |
8529 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8530 | addu $tempreg,$tempreg,$breg | |
8531 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8532 | With a constant we always use the latter case. |
76b3015f | 8533 | |
d6bc6245 TS |
8534 | With 64bit address space and no base register and $at usable, |
8535 | we want | |
8536 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8537 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8538 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8539 | dsll32 $tempreg,0 | |
8540 | daddu $tempreg,$at | |
8541 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8542 | If we have a base register, we want | |
8543 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8544 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8545 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8546 | daddu $at,$breg | |
8547 | dsll32 $tempreg,0 | |
8548 | daddu $tempreg,$at | |
8549 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8550 | ||
8551 | Without $at we can't generate the optimal path for superscalar | |
8552 | processors here since this would require two temporary registers. | |
8553 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8554 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8555 | dsll $tempreg,16 | |
8556 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8557 | dsll $tempreg,16 | |
8558 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8559 | If we have a base register, we want | |
8560 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8561 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8562 | dsll $tempreg,16 | |
8563 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8564 | dsll $tempreg,16 | |
8565 | daddu $tempreg,$tempreg,$breg | |
8566 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8567 | |
6caf9ef4 | 8568 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8569 | the same sequence as in 32bit address space. */ |
8570 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8571 | { |
aed1a261 | 8572 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8573 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8574 | { | |
8575 | relax_start (offset_expr.X_add_symbol); | |
8576 | if (breg == 0) | |
8577 | { | |
8578 | macro_build (&offset_expr, s, fmt, treg, | |
8579 | BFD_RELOC_GPREL16, mips_gp_register); | |
8580 | } | |
8581 | else | |
8582 | { | |
8583 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8584 | tempreg, breg, mips_gp_register); | |
8585 | macro_build (&offset_expr, s, fmt, treg, | |
8586 | BFD_RELOC_GPREL16, tempreg); | |
8587 | } | |
8588 | relax_switch (); | |
8589 | } | |
d6bc6245 | 8590 | |
741fe287 | 8591 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8592 | { |
df58fc94 | 8593 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8594 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8595 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8596 | BFD_RELOC_HI16_S); |
8597 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8598 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8599 | if (breg != 0) |
67c0d1eb | 8600 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8601 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8602 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8603 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8604 | tempreg); | |
d6bc6245 TS |
8605 | used_at = 1; |
8606 | } | |
8607 | else | |
8608 | { | |
df58fc94 | 8609 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8610 | BFD_RELOC_MIPS_HIGHEST); |
8611 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8612 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8613 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8614 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8615 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8616 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8617 | if (breg != 0) |
67c0d1eb | 8618 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8619 | tempreg, tempreg, breg); |
67c0d1eb | 8620 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8621 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8622 | } |
6caf9ef4 TS |
8623 | |
8624 | if (mips_relax.sequence) | |
8625 | relax_end (); | |
8fc2e39e | 8626 | break; |
d6bc6245 | 8627 | } |
256ab948 | 8628 | |
252b5132 RH |
8629 | if (breg == 0) |
8630 | { | |
67c0d1eb | 8631 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8632 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8633 | { |
4d7206a2 | 8634 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8635 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8636 | mips_gp_register); | |
4d7206a2 | 8637 | relax_switch (); |
252b5132 | 8638 | } |
67c0d1eb RS |
8639 | macro_build_lui (&offset_expr, tempreg); |
8640 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8641 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8642 | if (mips_relax.sequence) |
8643 | relax_end (); | |
252b5132 RH |
8644 | } |
8645 | else | |
8646 | { | |
67c0d1eb | 8647 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8648 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8649 | { |
4d7206a2 | 8650 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8651 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8652 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8653 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8654 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8655 | relax_switch (); |
252b5132 | 8656 | } |
67c0d1eb RS |
8657 | macro_build_lui (&offset_expr, tempreg); |
8658 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8659 | tempreg, tempreg, breg); |
67c0d1eb | 8660 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8661 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8662 | if (mips_relax.sequence) |
8663 | relax_end (); | |
252b5132 RH |
8664 | } |
8665 | } | |
0a44bf69 | 8666 | else if (!mips_big_got) |
252b5132 | 8667 | { |
ed6fb7bd | 8668 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8669 | |
252b5132 RH |
8670 | /* If this is a reference to an external symbol, we want |
8671 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8672 | nop | |
8673 | <op> $treg,0($tempreg) | |
8674 | Otherwise we want | |
8675 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8676 | nop | |
8677 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8678 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8679 | |
8680 | For NewABI, we want | |
8681 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8682 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8683 | ||
252b5132 RH |
8684 | If there is a base register, we add it to $tempreg before |
8685 | the <op>. If there is a constant, we stick it in the | |
8686 | <op> instruction. We don't handle constants larger than | |
8687 | 16 bits, because we have no way to load the upper 16 bits | |
8688 | (actually, we could handle them for the subset of cases | |
8689 | in which we are not using $at). */ | |
9c2799c2 | 8690 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8691 | if (HAVE_NEWABI) |
8692 | { | |
67c0d1eb RS |
8693 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8694 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8695 | if (breg != 0) |
67c0d1eb | 8696 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8697 | tempreg, tempreg, breg); |
67c0d1eb | 8698 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8699 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8700 | break; |
8701 | } | |
252b5132 RH |
8702 | expr1.X_add_number = offset_expr.X_add_number; |
8703 | offset_expr.X_add_number = 0; | |
8704 | if (expr1.X_add_number < -0x8000 | |
8705 | || expr1.X_add_number >= 0x8000) | |
8706 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8707 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8708 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8709 | load_delay_nop (); |
4d7206a2 RS |
8710 | relax_start (offset_expr.X_add_symbol); |
8711 | relax_switch (); | |
67c0d1eb RS |
8712 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8713 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8714 | relax_end (); |
252b5132 | 8715 | if (breg != 0) |
67c0d1eb | 8716 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8717 | tempreg, tempreg, breg); |
67c0d1eb | 8718 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8719 | } |
0a44bf69 | 8720 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8721 | { |
67c0d1eb | 8722 | int gpdelay; |
252b5132 RH |
8723 | |
8724 | /* If this is a reference to an external symbol, we want | |
8725 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8726 | addu $tempreg,$tempreg,$gp | |
8727 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8728 | <op> $treg,0($tempreg) | |
8729 | Otherwise we want | |
8730 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8731 | nop | |
8732 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8733 | <op> $treg,0($tempreg) | |
8734 | If there is a base register, we add it to $tempreg before | |
8735 | the <op>. If there is a constant, we stick it in the | |
8736 | <op> instruction. We don't handle constants larger than | |
8737 | 16 bits, because we have no way to load the upper 16 bits | |
8738 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8739 | in which we are not using $at). */ |
9c2799c2 | 8740 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8741 | expr1.X_add_number = offset_expr.X_add_number; |
8742 | offset_expr.X_add_number = 0; | |
8743 | if (expr1.X_add_number < -0x8000 | |
8744 | || expr1.X_add_number >= 0x8000) | |
8745 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8746 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8747 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8748 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8749 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8750 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8751 | mips_gp_register); | |
8752 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8753 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8754 | relax_switch (); |
67c0d1eb RS |
8755 | if (gpdelay) |
8756 | macro_build (NULL, "nop", ""); | |
8757 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8758 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8759 | load_delay_nop (); |
67c0d1eb RS |
8760 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8761 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8762 | relax_end (); |
8763 | ||
252b5132 | 8764 | if (breg != 0) |
67c0d1eb | 8765 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8766 | tempreg, tempreg, breg); |
67c0d1eb | 8767 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8768 | } |
0a44bf69 | 8769 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8770 | { |
f5040a92 AO |
8771 | /* If this is a reference to an external symbol, we want |
8772 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8773 | add $tempreg,$tempreg,$gp | |
8774 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8775 | <op> $treg,<ofst>($tempreg) | |
8776 | Otherwise, for local symbols, we want: | |
8777 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8778 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8779 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8780 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8781 | offset_expr.X_add_number = 0; |
8782 | if (expr1.X_add_number < -0x8000 | |
8783 | || expr1.X_add_number >= 0x8000) | |
8784 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8785 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8786 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8787 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8788 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8789 | mips_gp_register); | |
8790 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8791 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8792 | if (breg != 0) |
67c0d1eb | 8793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8794 | tempreg, tempreg, breg); |
67c0d1eb | 8795 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8796 | |
4d7206a2 | 8797 | relax_switch (); |
f5040a92 | 8798 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8799 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8800 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8801 | if (breg != 0) |
67c0d1eb | 8802 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8803 | tempreg, tempreg, breg); |
67c0d1eb | 8804 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8805 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8806 | relax_end (); |
f5040a92 | 8807 | } |
252b5132 RH |
8808 | else |
8809 | abort (); | |
8810 | ||
252b5132 RH |
8811 | break; |
8812 | ||
8813 | case M_LI: | |
8814 | case M_LI_S: | |
67c0d1eb | 8815 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8816 | break; |
252b5132 RH |
8817 | |
8818 | case M_DLI: | |
67c0d1eb | 8819 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8820 | break; |
252b5132 RH |
8821 | |
8822 | case M_LI_SS: | |
8823 | if (imm_expr.X_op == O_constant) | |
8824 | { | |
8fc2e39e | 8825 | used_at = 1; |
67c0d1eb RS |
8826 | load_register (AT, &imm_expr, 0); |
8827 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8828 | break; |
8829 | } | |
8830 | else | |
8831 | { | |
9c2799c2 | 8832 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8833 | && strcmp (segment_name (S_GET_SEGMENT |
8834 | (offset_expr.X_add_symbol)), | |
8835 | ".lit4") == 0 | |
8836 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8837 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8838 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8839 | break; |
252b5132 RH |
8840 | } |
8841 | ||
8842 | case M_LI_D: | |
ca4e0257 RS |
8843 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8844 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8845 | order 32 bits of the value and the low order 32 bits are either | |
8846 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8847 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8848 | { | |
ca4e0257 | 8849 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8850 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8851 | else |
8852 | { | |
8853 | int hreg, lreg; | |
8854 | ||
8855 | if (target_big_endian) | |
8856 | { | |
8857 | hreg = treg; | |
8858 | lreg = treg + 1; | |
8859 | } | |
8860 | else | |
8861 | { | |
8862 | hreg = treg + 1; | |
8863 | lreg = treg; | |
8864 | } | |
8865 | ||
8866 | if (hreg <= 31) | |
67c0d1eb | 8867 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8868 | if (lreg <= 31) |
8869 | { | |
8870 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8871 | move_register (lreg, 0); |
252b5132 RH |
8872 | else |
8873 | { | |
9c2799c2 | 8874 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8875 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8876 | } |
8877 | } | |
8878 | } | |
8fc2e39e | 8879 | break; |
252b5132 RH |
8880 | } |
8881 | ||
8882 | /* We know that sym is in the .rdata section. First we get the | |
8883 | upper 16 bits of the address. */ | |
8884 | if (mips_pic == NO_PIC) | |
8885 | { | |
67c0d1eb | 8886 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8887 | used_at = 1; |
252b5132 | 8888 | } |
0a44bf69 | 8889 | else |
252b5132 | 8890 | { |
67c0d1eb RS |
8891 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8892 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8893 | used_at = 1; |
252b5132 | 8894 | } |
bdaaa2e1 | 8895 | |
252b5132 | 8896 | /* Now we load the register(s). */ |
ca4e0257 | 8897 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8898 | { |
8899 | used_at = 1; | |
8900 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8901 | } | |
252b5132 RH |
8902 | else |
8903 | { | |
8fc2e39e | 8904 | used_at = 1; |
67c0d1eb | 8905 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8906 | if (treg != RA) |
252b5132 RH |
8907 | { |
8908 | /* FIXME: How in the world do we deal with the possible | |
8909 | overflow here? */ | |
8910 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8911 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8912 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8913 | } |
8914 | } | |
252b5132 RH |
8915 | break; |
8916 | ||
8917 | case M_LI_DD: | |
ca4e0257 RS |
8918 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8919 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8920 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8921 | the value and the low order 32 bits are either zero or in | |
8922 | OFFSET_EXPR. */ | |
252b5132 RH |
8923 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8924 | { | |
8fc2e39e | 8925 | used_at = 1; |
67c0d1eb | 8926 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8927 | if (HAVE_64BIT_FPRS) |
8928 | { | |
9c2799c2 | 8929 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8930 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8931 | } |
252b5132 RH |
8932 | else |
8933 | { | |
67c0d1eb | 8934 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8935 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8936 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8937 | else |
8938 | { | |
9c2799c2 | 8939 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8940 | load_register (AT, &offset_expr, 0); |
8941 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8942 | } |
8943 | } | |
8944 | break; | |
8945 | } | |
8946 | ||
9c2799c2 | 8947 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8948 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8949 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8950 | if (strcmp (s, ".lit8") == 0) | |
8951 | { | |
0aa27725 | 8952 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 8953 | { |
67c0d1eb | 8954 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8955 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8956 | break; |
252b5132 | 8957 | } |
c9914766 | 8958 | breg = mips_gp_register; |
252b5132 RH |
8959 | r = BFD_RELOC_MIPS_LITERAL; |
8960 | goto dob; | |
8961 | } | |
8962 | else | |
8963 | { | |
9c2799c2 | 8964 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8965 | used_at = 1; |
0a44bf69 | 8966 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8967 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8968 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8969 | else |
8970 | { | |
8971 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8972 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8973 | } |
bdaaa2e1 | 8974 | |
0aa27725 | 8975 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 8976 | { |
67c0d1eb RS |
8977 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8978 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8979 | break; |
8980 | } | |
8981 | breg = AT; | |
8982 | r = BFD_RELOC_LO16; | |
8983 | goto dob; | |
8984 | } | |
8985 | ||
8986 | case M_L_DOB: | |
252b5132 RH |
8987 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8988 | to adjust when loading from memory. */ | |
8989 | r = BFD_RELOC_LO16; | |
8990 | dob: | |
df58fc94 | 8991 | gas_assert (!mips_opts.micromips); |
0aa27725 | 8992 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 8993 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8994 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8995 | /* FIXME: A possible overflow which I don't know how to deal |
8996 | with. */ | |
8997 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8998 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8999 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9000 | break; |
9001 | ||
c4a68bea | 9002 | case M_S_DOB: |
df58fc94 | 9003 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9004 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9005 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9006 | to adjust when storing to memory. */ | |
9007 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9008 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9009 | offset_expr.X_add_number += 4; | |
9010 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9011 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9012 | break; | |
9013 | ||
252b5132 | 9014 | case M_L_DAB: |
df58fc94 | 9015 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9016 | /* |
9017 | * The MIPS assembler seems to check for X_add_number not | |
9018 | * being double aligned and generating: | |
9019 | * lui at,%hi(foo+1) | |
9020 | * addu at,at,v1 | |
9021 | * addiu at,at,%lo(foo+1) | |
9022 | * lwc1 f2,0(at) | |
9023 | * lwc1 f3,4(at) | |
9024 | * But, the resulting address is the same after relocation so why | |
9025 | * generate the extra instruction? | |
9026 | */ | |
bdaaa2e1 | 9027 | /* Itbl support may require additional care here. */ |
252b5132 | 9028 | coproc = 1; |
df58fc94 | 9029 | fmt = "T,o(b)"; |
0aa27725 | 9030 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9031 | { |
9032 | s = "ldc1"; | |
df58fc94 | 9033 | goto ld_st; |
252b5132 | 9034 | } |
252b5132 | 9035 | s = "lwc1"; |
252b5132 RH |
9036 | goto ldd_std; |
9037 | ||
9038 | case M_S_DAB: | |
df58fc94 RS |
9039 | gas_assert (!mips_opts.micromips); |
9040 | /* Itbl support may require additional care here. */ | |
9041 | coproc = 1; | |
9042 | fmt = "T,o(b)"; | |
0aa27725 | 9043 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9044 | { |
9045 | s = "sdc1"; | |
df58fc94 | 9046 | goto ld_st; |
252b5132 | 9047 | } |
252b5132 | 9048 | s = "swc1"; |
252b5132 RH |
9049 | goto ldd_std; |
9050 | ||
e407c74b NC |
9051 | case M_LQ_AB: |
9052 | fmt = "t,o(b)"; | |
9053 | s = "lq"; | |
9054 | goto ld; | |
9055 | ||
9056 | case M_SQ_AB: | |
9057 | fmt = "t,o(b)"; | |
9058 | s = "sq"; | |
9059 | goto ld_st; | |
9060 | ||
252b5132 | 9061 | case M_LD_AB: |
df58fc94 | 9062 | fmt = "t,o(b)"; |
ca4e0257 | 9063 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9064 | { |
9065 | s = "ld"; | |
9066 | goto ld; | |
9067 | } | |
252b5132 | 9068 | s = "lw"; |
252b5132 RH |
9069 | goto ldd_std; |
9070 | ||
9071 | case M_SD_AB: | |
df58fc94 | 9072 | fmt = "t,o(b)"; |
ca4e0257 | 9073 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9074 | { |
9075 | s = "sd"; | |
df58fc94 | 9076 | goto ld_st; |
252b5132 | 9077 | } |
252b5132 | 9078 | s = "sw"; |
252b5132 RH |
9079 | |
9080 | ldd_std: | |
9081 | if (offset_expr.X_op != O_symbol | |
9082 | && offset_expr.X_op != O_constant) | |
9083 | { | |
f71d0d44 | 9084 | as_bad (_("Expression too complex")); |
252b5132 RH |
9085 | offset_expr.X_op = O_constant; |
9086 | } | |
9087 | ||
2051e8c4 MR |
9088 | if (HAVE_32BIT_ADDRESSES |
9089 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9090 | { |
9091 | char value [32]; | |
9092 | ||
9093 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9094 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9095 | } |
2051e8c4 | 9096 | |
252b5132 RH |
9097 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9098 | to adjust when loading from memory. We set coproc if we must | |
9099 | load $fn+1 first. */ | |
bdaaa2e1 | 9100 | /* Itbl support may require additional care here. */ |
90ecf173 | 9101 | if (!target_big_endian) |
252b5132 RH |
9102 | coproc = 0; |
9103 | ||
90ecf173 | 9104 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9105 | { |
9106 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9107 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9108 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9109 | If we have a base register, we use this |
9110 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9111 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9112 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9113 | If this is not a GP relative symbol, we want |
9114 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9115 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9116 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9117 | If there is a base register, we add it to $at after the | |
9118 | lui instruction. If there is a constant, we always use | |
9119 | the last case. */ | |
39a59cf8 MR |
9120 | if (offset_expr.X_op == O_symbol |
9121 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9122 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9123 | { |
4d7206a2 | 9124 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9125 | if (breg == 0) |
9126 | { | |
c9914766 | 9127 | tempreg = mips_gp_register; |
252b5132 RH |
9128 | } |
9129 | else | |
9130 | { | |
67c0d1eb | 9131 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9132 | AT, breg, mips_gp_register); |
252b5132 | 9133 | tempreg = AT; |
252b5132 RH |
9134 | used_at = 1; |
9135 | } | |
9136 | ||
beae10d5 | 9137 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9138 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9139 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9140 | offset_expr.X_add_number += 4; |
9141 | ||
9142 | /* Set mips_optimize to 2 to avoid inserting an | |
9143 | undesired nop. */ | |
9144 | hold_mips_optimize = mips_optimize; | |
9145 | mips_optimize = 2; | |
beae10d5 | 9146 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9147 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9148 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9149 | mips_optimize = hold_mips_optimize; |
9150 | ||
4d7206a2 | 9151 | relax_switch (); |
252b5132 | 9152 | |
0970e49e | 9153 | offset_expr.X_add_number -= 4; |
252b5132 | 9154 | } |
8fc2e39e | 9155 | used_at = 1; |
67c0d1eb | 9156 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9157 | if (breg != 0) |
67c0d1eb | 9158 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9159 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9160 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9161 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9162 | /* FIXME: How do we handle overflow here? */ |
9163 | offset_expr.X_add_number += 4; | |
beae10d5 | 9164 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9165 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9166 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9167 | if (mips_relax.sequence) |
9168 | relax_end (); | |
bdaaa2e1 | 9169 | } |
0a44bf69 | 9170 | else if (!mips_big_got) |
252b5132 | 9171 | { |
252b5132 RH |
9172 | /* If this is a reference to an external symbol, we want |
9173 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9174 | nop | |
9175 | <op> $treg,0($at) | |
9176 | <op> $treg+1,4($at) | |
9177 | Otherwise we want | |
9178 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9179 | nop | |
9180 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9181 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9182 | If there is a base register we add it to $at before the | |
9183 | lwc1 instructions. If there is a constant we include it | |
9184 | in the lwc1 instructions. */ | |
9185 | used_at = 1; | |
9186 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9187 | if (expr1.X_add_number < -0x8000 |
9188 | || expr1.X_add_number >= 0x8000 - 4) | |
9189 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9190 | load_got_offset (AT, &offset_expr); |
269137b2 | 9191 | load_delay_nop (); |
252b5132 | 9192 | if (breg != 0) |
67c0d1eb | 9193 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9194 | |
9195 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9196 | nop. */ | |
9197 | hold_mips_optimize = mips_optimize; | |
9198 | mips_optimize = 2; | |
4d7206a2 | 9199 | |
beae10d5 | 9200 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9201 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9202 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9203 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9204 | expr1.X_add_number += 4; |
67c0d1eb RS |
9205 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9206 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9207 | relax_switch (); |
67c0d1eb RS |
9208 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9209 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9210 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9211 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9212 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9213 | relax_end (); |
252b5132 | 9214 | |
4d7206a2 | 9215 | mips_optimize = hold_mips_optimize; |
252b5132 | 9216 | } |
0a44bf69 | 9217 | else if (mips_big_got) |
252b5132 | 9218 | { |
67c0d1eb | 9219 | int gpdelay; |
252b5132 RH |
9220 | |
9221 | /* If this is a reference to an external symbol, we want | |
9222 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9223 | addu $at,$at,$gp | |
9224 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9225 | nop | |
9226 | <op> $treg,0($at) | |
9227 | <op> $treg+1,4($at) | |
9228 | Otherwise we want | |
9229 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9230 | nop | |
9231 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9232 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9233 | If there is a base register we add it to $at before the | |
9234 | lwc1 instructions. If there is a constant we include it | |
9235 | in the lwc1 instructions. */ | |
9236 | used_at = 1; | |
9237 | expr1.X_add_number = offset_expr.X_add_number; | |
9238 | offset_expr.X_add_number = 0; | |
9239 | if (expr1.X_add_number < -0x8000 | |
9240 | || expr1.X_add_number >= 0x8000 - 4) | |
9241 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9242 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9243 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9244 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9245 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9246 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9247 | AT, AT, mips_gp_register); |
67c0d1eb | 9248 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9249 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9250 | load_delay_nop (); |
252b5132 | 9251 | if (breg != 0) |
67c0d1eb | 9252 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9253 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9254 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9255 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9256 | expr1.X_add_number += 4; |
9257 | ||
9258 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9259 | nop. */ | |
9260 | hold_mips_optimize = mips_optimize; | |
9261 | mips_optimize = 2; | |
beae10d5 | 9262 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9263 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9264 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9265 | mips_optimize = hold_mips_optimize; |
9266 | expr1.X_add_number -= 4; | |
9267 | ||
4d7206a2 RS |
9268 | relax_switch (); |
9269 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9270 | if (gpdelay) |
9271 | macro_build (NULL, "nop", ""); | |
9272 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9273 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9274 | load_delay_nop (); |
252b5132 | 9275 | if (breg != 0) |
67c0d1eb | 9276 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9277 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9278 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9279 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9280 | offset_expr.X_add_number += 4; |
252b5132 RH |
9281 | |
9282 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9283 | nop. */ | |
9284 | hold_mips_optimize = mips_optimize; | |
9285 | mips_optimize = 2; | |
beae10d5 | 9286 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9287 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9288 | BFD_RELOC_LO16, AT); | |
252b5132 | 9289 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9290 | relax_end (); |
252b5132 | 9291 | } |
252b5132 RH |
9292 | else |
9293 | abort (); | |
9294 | ||
252b5132 RH |
9295 | break; |
9296 | ||
9297 | case M_LD_OB: | |
704897fb | 9298 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9299 | goto sd_ob; |
9300 | case M_SD_OB: | |
704897fb | 9301 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9302 | sd_ob: |
4614d845 MR |
9303 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9304 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9305 | breg); | |
704897fb MR |
9306 | if (!HAVE_64BIT_GPRS) |
9307 | { | |
9308 | offset_expr.X_add_number += 4; | |
9309 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9310 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9311 | breg); | |
704897fb | 9312 | } |
8fc2e39e | 9313 | break; |
252b5132 | 9314 | |
dd6a37e7 AP |
9315 | |
9316 | case M_SAA_AB: | |
9317 | ab = 1; | |
9318 | case M_SAA_OB: | |
9319 | s = "saa"; | |
9320 | off0 = 1; | |
9321 | fmt = "t,(b)"; | |
9322 | goto ld_st; | |
9323 | case M_SAAD_AB: | |
9324 | ab = 1; | |
9325 | case M_SAAD_OB: | |
9326 | s = "saad"; | |
9327 | off0 = 1; | |
9328 | fmt = "t,(b)"; | |
9329 | goto ld_st; | |
9330 | ||
252b5132 RH |
9331 | /* New code added to support COPZ instructions. |
9332 | This code builds table entries out of the macros in mip_opcodes. | |
9333 | R4000 uses interlocks to handle coproc delays. | |
9334 | Other chips (like the R3000) require nops to be inserted for delays. | |
9335 | ||
f72c8c98 | 9336 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9337 | In order to fill delay slots for non-interlocked chips, |
9338 | we must have a way to specify delays based on the coprocessor. | |
9339 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9340 | What are the side-effects of the cop instruction? | |
9341 | What cache support might we have and what are its effects? | |
9342 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9343 | What registers are read/set/modified? |
252b5132 RH |
9344 | |
9345 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9346 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9347 | |
9348 | case M_COP0: | |
9349 | s = "c0"; | |
9350 | goto copz; | |
9351 | case M_COP1: | |
9352 | s = "c1"; | |
9353 | goto copz; | |
9354 | case M_COP2: | |
9355 | s = "c2"; | |
9356 | goto copz; | |
9357 | case M_COP3: | |
9358 | s = "c3"; | |
9359 | copz: | |
df58fc94 | 9360 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9361 | /* For now we just do C (same as Cz). The parameter will be |
9362 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9363 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9364 | break; |
252b5132 | 9365 | |
ea1fb5dc | 9366 | case M_MOVE: |
67c0d1eb | 9367 | move_register (dreg, sreg); |
8fc2e39e | 9368 | break; |
ea1fb5dc | 9369 | |
252b5132 RH |
9370 | case M_DMUL: |
9371 | dbl = 1; | |
9372 | case M_MUL: | |
e407c74b NC |
9373 | if (mips_opts.arch == CPU_R5900) |
9374 | { | |
9375 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9376 | } | |
9377 | else | |
9378 | { | |
67c0d1eb | 9379 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9380 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9381 | } |
8fc2e39e | 9382 | break; |
252b5132 RH |
9383 | |
9384 | case M_DMUL_I: | |
9385 | dbl = 1; | |
9386 | case M_MUL_I: | |
9387 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9388 | not trying to be that fancy. GCC should do this for us | |
9389 | anyway. */ | |
8fc2e39e | 9390 | used_at = 1; |
67c0d1eb RS |
9391 | load_register (AT, &imm_expr, dbl); |
9392 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9393 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9394 | break; |
9395 | ||
9396 | case M_DMULO_I: | |
9397 | dbl = 1; | |
9398 | case M_MULO_I: | |
9399 | imm = 1; | |
9400 | goto do_mulo; | |
9401 | ||
9402 | case M_DMULO: | |
9403 | dbl = 1; | |
9404 | case M_MULO: | |
9405 | do_mulo: | |
7d10b47d | 9406 | start_noreorder (); |
8fc2e39e | 9407 | used_at = 1; |
252b5132 | 9408 | if (imm) |
67c0d1eb RS |
9409 | load_register (AT, &imm_expr, dbl); |
9410 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9411 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9412 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9413 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9414 | if (mips_trap) |
df58fc94 | 9415 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9416 | else |
9417 | { | |
df58fc94 RS |
9418 | if (mips_opts.micromips) |
9419 | micromips_label_expr (&label_expr); | |
9420 | else | |
9421 | label_expr.X_add_number = 8; | |
9422 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9423 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9424 | macro_build (NULL, "break", BRK_FMT, 6); |
9425 | if (mips_opts.micromips) | |
9426 | micromips_add_label (); | |
252b5132 | 9427 | } |
7d10b47d | 9428 | end_noreorder (); |
df58fc94 | 9429 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9430 | break; |
9431 | ||
9432 | case M_DMULOU_I: | |
9433 | dbl = 1; | |
9434 | case M_MULOU_I: | |
9435 | imm = 1; | |
9436 | goto do_mulou; | |
9437 | ||
9438 | case M_DMULOU: | |
9439 | dbl = 1; | |
9440 | case M_MULOU: | |
9441 | do_mulou: | |
7d10b47d | 9442 | start_noreorder (); |
8fc2e39e | 9443 | used_at = 1; |
252b5132 | 9444 | if (imm) |
67c0d1eb RS |
9445 | load_register (AT, &imm_expr, dbl); |
9446 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9447 | sreg, imm ? AT : treg); |
df58fc94 RS |
9448 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9449 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9450 | if (mips_trap) |
df58fc94 | 9451 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9452 | else |
9453 | { | |
df58fc94 RS |
9454 | if (mips_opts.micromips) |
9455 | micromips_label_expr (&label_expr); | |
9456 | else | |
9457 | label_expr.X_add_number = 8; | |
9458 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9459 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9460 | macro_build (NULL, "break", BRK_FMT, 6); |
9461 | if (mips_opts.micromips) | |
9462 | micromips_add_label (); | |
252b5132 | 9463 | } |
7d10b47d | 9464 | end_noreorder (); |
252b5132 RH |
9465 | break; |
9466 | ||
771c7ce4 | 9467 | case M_DROL: |
fef14a42 | 9468 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9469 | { |
9470 | if (dreg == sreg) | |
9471 | { | |
9472 | tempreg = AT; | |
9473 | used_at = 1; | |
9474 | } | |
9475 | else | |
9476 | { | |
9477 | tempreg = dreg; | |
82dd0097 | 9478 | } |
67c0d1eb RS |
9479 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9480 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9481 | break; |
82dd0097 | 9482 | } |
8fc2e39e | 9483 | used_at = 1; |
c80c840e | 9484 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9485 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9486 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9487 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9488 | break; |
9489 | ||
252b5132 | 9490 | case M_ROL: |
fef14a42 | 9491 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9492 | { |
9493 | if (dreg == sreg) | |
9494 | { | |
9495 | tempreg = AT; | |
9496 | used_at = 1; | |
9497 | } | |
9498 | else | |
9499 | { | |
9500 | tempreg = dreg; | |
82dd0097 | 9501 | } |
67c0d1eb RS |
9502 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9503 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9504 | break; |
82dd0097 | 9505 | } |
8fc2e39e | 9506 | used_at = 1; |
c80c840e | 9507 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9508 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9509 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9510 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9511 | break; |
9512 | ||
771c7ce4 TS |
9513 | case M_DROL_I: |
9514 | { | |
9515 | unsigned int rot; | |
91d6fa6a NC |
9516 | char *l; |
9517 | char *rr; | |
771c7ce4 TS |
9518 | |
9519 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9520 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9521 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9522 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9523 | { |
9524 | rot = (64 - rot) & 0x3f; | |
9525 | if (rot >= 32) | |
df58fc94 | 9526 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9527 | else |
df58fc94 | 9528 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9529 | break; |
60b63b72 | 9530 | } |
483fc7cd | 9531 | if (rot == 0) |
483fc7cd | 9532 | { |
df58fc94 | 9533 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9534 | break; |
483fc7cd | 9535 | } |
82dd0097 | 9536 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9537 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9538 | rot &= 0x1f; |
8fc2e39e | 9539 | used_at = 1; |
df58fc94 RS |
9540 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9541 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9542 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9543 | } |
9544 | break; | |
9545 | ||
252b5132 | 9546 | case M_ROL_I: |
771c7ce4 TS |
9547 | { |
9548 | unsigned int rot; | |
9549 | ||
9550 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9551 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9552 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9553 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9554 | { |
df58fc94 | 9555 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9556 | break; |
60b63b72 | 9557 | } |
483fc7cd | 9558 | if (rot == 0) |
483fc7cd | 9559 | { |
df58fc94 | 9560 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9561 | break; |
483fc7cd | 9562 | } |
8fc2e39e | 9563 | used_at = 1; |
df58fc94 RS |
9564 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9565 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9566 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9567 | } |
9568 | break; | |
9569 | ||
9570 | case M_DROR: | |
fef14a42 | 9571 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9572 | { |
67c0d1eb | 9573 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9574 | break; |
82dd0097 | 9575 | } |
8fc2e39e | 9576 | used_at = 1; |
c80c840e | 9577 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9578 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9579 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9580 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9581 | break; |
9582 | ||
9583 | case M_ROR: | |
fef14a42 | 9584 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9585 | { |
67c0d1eb | 9586 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9587 | break; |
82dd0097 | 9588 | } |
8fc2e39e | 9589 | used_at = 1; |
c80c840e | 9590 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9591 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9592 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9593 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9594 | break; |
9595 | ||
771c7ce4 TS |
9596 | case M_DROR_I: |
9597 | { | |
9598 | unsigned int rot; | |
91d6fa6a NC |
9599 | char *l; |
9600 | char *rr; | |
771c7ce4 TS |
9601 | |
9602 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9603 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9604 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9605 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9606 | { |
9607 | if (rot >= 32) | |
df58fc94 | 9608 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9609 | else |
df58fc94 | 9610 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9611 | break; |
82dd0097 | 9612 | } |
483fc7cd | 9613 | if (rot == 0) |
483fc7cd | 9614 | { |
df58fc94 | 9615 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9616 | break; |
483fc7cd | 9617 | } |
91d6fa6a | 9618 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9619 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9620 | rot &= 0x1f; | |
8fc2e39e | 9621 | used_at = 1; |
df58fc94 RS |
9622 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9623 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9624 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9625 | } |
9626 | break; | |
9627 | ||
252b5132 | 9628 | case M_ROR_I: |
771c7ce4 TS |
9629 | { |
9630 | unsigned int rot; | |
9631 | ||
9632 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9633 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9634 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9635 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9636 | { |
df58fc94 | 9637 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9638 | break; |
82dd0097 | 9639 | } |
483fc7cd | 9640 | if (rot == 0) |
483fc7cd | 9641 | { |
df58fc94 | 9642 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9643 | break; |
483fc7cd | 9644 | } |
8fc2e39e | 9645 | used_at = 1; |
df58fc94 RS |
9646 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9647 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9648 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9649 | } |
252b5132 RH |
9650 | break; |
9651 | ||
252b5132 RH |
9652 | case M_SEQ: |
9653 | if (sreg == 0) | |
67c0d1eb | 9654 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9655 | else if (treg == 0) |
67c0d1eb | 9656 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9657 | else |
9658 | { | |
67c0d1eb RS |
9659 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9660 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9661 | } |
8fc2e39e | 9662 | break; |
252b5132 RH |
9663 | |
9664 | case M_SEQ_I: | |
9665 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9666 | { | |
67c0d1eb | 9667 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9668 | break; |
252b5132 RH |
9669 | } |
9670 | if (sreg == 0) | |
9671 | { | |
9672 | as_warn (_("Instruction %s: result is always false"), | |
9673 | ip->insn_mo->name); | |
67c0d1eb | 9674 | move_register (dreg, 0); |
8fc2e39e | 9675 | break; |
252b5132 | 9676 | } |
dd3cbb7e NC |
9677 | if (CPU_HAS_SEQ (mips_opts.arch) |
9678 | && -512 <= imm_expr.X_add_number | |
9679 | && imm_expr.X_add_number < 512) | |
9680 | { | |
9681 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9682 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9683 | break; |
9684 | } | |
252b5132 RH |
9685 | if (imm_expr.X_op == O_constant |
9686 | && imm_expr.X_add_number >= 0 | |
9687 | && imm_expr.X_add_number < 0x10000) | |
9688 | { | |
67c0d1eb | 9689 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9690 | } |
9691 | else if (imm_expr.X_op == O_constant | |
9692 | && imm_expr.X_add_number > -0x8000 | |
9693 | && imm_expr.X_add_number < 0) | |
9694 | { | |
9695 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9696 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9697 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9698 | } |
dd3cbb7e NC |
9699 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9700 | { | |
9701 | used_at = 1; | |
9702 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9703 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9704 | break; | |
9705 | } | |
252b5132 RH |
9706 | else |
9707 | { | |
67c0d1eb RS |
9708 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9709 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9710 | used_at = 1; |
9711 | } | |
67c0d1eb | 9712 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9713 | break; |
252b5132 RH |
9714 | |
9715 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9716 | s = "slt"; | |
9717 | goto sge; | |
9718 | case M_SGEU: | |
9719 | s = "sltu"; | |
9720 | sge: | |
67c0d1eb RS |
9721 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9722 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9723 | break; |
252b5132 RH |
9724 | |
9725 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9726 | case M_SGEU_I: | |
9727 | if (imm_expr.X_op == O_constant | |
9728 | && imm_expr.X_add_number >= -0x8000 | |
9729 | && imm_expr.X_add_number < 0x8000) | |
9730 | { | |
67c0d1eb RS |
9731 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9732 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9733 | } |
9734 | else | |
9735 | { | |
67c0d1eb RS |
9736 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9737 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9738 | dreg, sreg, AT); | |
252b5132 RH |
9739 | used_at = 1; |
9740 | } | |
67c0d1eb | 9741 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9742 | break; |
252b5132 RH |
9743 | |
9744 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9745 | s = "slt"; | |
9746 | goto sgt; | |
9747 | case M_SGTU: | |
9748 | s = "sltu"; | |
9749 | sgt: | |
67c0d1eb | 9750 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9751 | break; |
252b5132 RH |
9752 | |
9753 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9754 | s = "slt"; | |
9755 | goto sgti; | |
9756 | case M_SGTU_I: | |
9757 | s = "sltu"; | |
9758 | sgti: | |
8fc2e39e | 9759 | used_at = 1; |
67c0d1eb RS |
9760 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9761 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9762 | break; |
9763 | ||
2396cfb9 | 9764 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9765 | s = "slt"; |
9766 | goto sle; | |
9767 | case M_SLEU: | |
9768 | s = "sltu"; | |
9769 | sle: | |
67c0d1eb RS |
9770 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9771 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9772 | break; |
252b5132 | 9773 | |
2396cfb9 | 9774 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9775 | s = "slt"; |
9776 | goto slei; | |
9777 | case M_SLEU_I: | |
9778 | s = "sltu"; | |
9779 | slei: | |
8fc2e39e | 9780 | used_at = 1; |
67c0d1eb RS |
9781 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9782 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9783 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9784 | break; |
9785 | ||
9786 | case M_SLT_I: | |
9787 | if (imm_expr.X_op == O_constant | |
9788 | && imm_expr.X_add_number >= -0x8000 | |
9789 | && imm_expr.X_add_number < 0x8000) | |
9790 | { | |
67c0d1eb | 9791 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9792 | break; |
252b5132 | 9793 | } |
8fc2e39e | 9794 | used_at = 1; |
67c0d1eb RS |
9795 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9796 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9797 | break; |
9798 | ||
9799 | case M_SLTU_I: | |
9800 | if (imm_expr.X_op == O_constant | |
9801 | && imm_expr.X_add_number >= -0x8000 | |
9802 | && imm_expr.X_add_number < 0x8000) | |
9803 | { | |
67c0d1eb | 9804 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9805 | BFD_RELOC_LO16); |
8fc2e39e | 9806 | break; |
252b5132 | 9807 | } |
8fc2e39e | 9808 | used_at = 1; |
67c0d1eb RS |
9809 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9810 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9811 | break; |
9812 | ||
9813 | case M_SNE: | |
9814 | if (sreg == 0) | |
67c0d1eb | 9815 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9816 | else if (treg == 0) |
67c0d1eb | 9817 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9818 | else |
9819 | { | |
67c0d1eb RS |
9820 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9821 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9822 | } |
8fc2e39e | 9823 | break; |
252b5132 RH |
9824 | |
9825 | case M_SNE_I: | |
9826 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9827 | { | |
67c0d1eb | 9828 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9829 | break; |
252b5132 RH |
9830 | } |
9831 | if (sreg == 0) | |
9832 | { | |
9833 | as_warn (_("Instruction %s: result is always true"), | |
9834 | ip->insn_mo->name); | |
67c0d1eb RS |
9835 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9836 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9837 | break; |
252b5132 | 9838 | } |
dd3cbb7e NC |
9839 | if (CPU_HAS_SEQ (mips_opts.arch) |
9840 | && -512 <= imm_expr.X_add_number | |
9841 | && imm_expr.X_add_number < 512) | |
9842 | { | |
9843 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9844 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9845 | break; |
9846 | } | |
252b5132 RH |
9847 | if (imm_expr.X_op == O_constant |
9848 | && imm_expr.X_add_number >= 0 | |
9849 | && imm_expr.X_add_number < 0x10000) | |
9850 | { | |
67c0d1eb | 9851 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9852 | } |
9853 | else if (imm_expr.X_op == O_constant | |
9854 | && imm_expr.X_add_number > -0x8000 | |
9855 | && imm_expr.X_add_number < 0) | |
9856 | { | |
9857 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9858 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9859 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9860 | } |
dd3cbb7e NC |
9861 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9862 | { | |
9863 | used_at = 1; | |
9864 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9865 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9866 | break; | |
9867 | } | |
252b5132 RH |
9868 | else |
9869 | { | |
67c0d1eb RS |
9870 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9871 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9872 | used_at = 1; |
9873 | } | |
67c0d1eb | 9874 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9875 | break; |
252b5132 | 9876 | |
df58fc94 RS |
9877 | case M_SUB_I: |
9878 | s = "addi"; | |
9879 | s2 = "sub"; | |
9880 | goto do_subi; | |
9881 | case M_SUBU_I: | |
9882 | s = "addiu"; | |
9883 | s2 = "subu"; | |
9884 | goto do_subi; | |
252b5132 RH |
9885 | case M_DSUB_I: |
9886 | dbl = 1; | |
df58fc94 RS |
9887 | s = "daddi"; |
9888 | s2 = "dsub"; | |
9889 | if (!mips_opts.micromips) | |
9890 | goto do_subi; | |
252b5132 | 9891 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9892 | && imm_expr.X_add_number > -0x200 |
9893 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9894 | { |
df58fc94 | 9895 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9896 | break; |
252b5132 | 9897 | } |
df58fc94 | 9898 | goto do_subi_i; |
252b5132 RH |
9899 | case M_DSUBU_I: |
9900 | dbl = 1; | |
df58fc94 RS |
9901 | s = "daddiu"; |
9902 | s2 = "dsubu"; | |
9903 | do_subi: | |
252b5132 RH |
9904 | if (imm_expr.X_op == O_constant |
9905 | && imm_expr.X_add_number > -0x8000 | |
9906 | && imm_expr.X_add_number <= 0x8000) | |
9907 | { | |
9908 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9909 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9910 | break; |
252b5132 | 9911 | } |
df58fc94 | 9912 | do_subi_i: |
8fc2e39e | 9913 | used_at = 1; |
67c0d1eb | 9914 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9915 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9916 | break; |
9917 | ||
9918 | case M_TEQ_I: | |
9919 | s = "teq"; | |
9920 | goto trap; | |
9921 | case M_TGE_I: | |
9922 | s = "tge"; | |
9923 | goto trap; | |
9924 | case M_TGEU_I: | |
9925 | s = "tgeu"; | |
9926 | goto trap; | |
9927 | case M_TLT_I: | |
9928 | s = "tlt"; | |
9929 | goto trap; | |
9930 | case M_TLTU_I: | |
9931 | s = "tltu"; | |
9932 | goto trap; | |
9933 | case M_TNE_I: | |
9934 | s = "tne"; | |
9935 | trap: | |
8fc2e39e | 9936 | used_at = 1; |
67c0d1eb RS |
9937 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9938 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9939 | break; |
9940 | ||
252b5132 | 9941 | case M_TRUNCWS: |
43841e91 | 9942 | case M_TRUNCWD: |
df58fc94 | 9943 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9944 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9945 | used_at = 1; |
252b5132 RH |
9946 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9947 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9948 | ||
9949 | /* | |
9950 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9951 | * or is there a reason for it? | |
9952 | */ | |
7d10b47d | 9953 | start_noreorder (); |
67c0d1eb RS |
9954 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9955 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9956 | macro_build (NULL, "nop", ""); | |
252b5132 | 9957 | expr1.X_add_number = 3; |
67c0d1eb | 9958 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9959 | expr1.X_add_number = 2; |
67c0d1eb RS |
9960 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9961 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9962 | macro_build (NULL, "nop", ""); | |
9963 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9964 | dreg, sreg); | |
9965 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9966 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9967 | end_noreorder (); |
252b5132 RH |
9968 | break; |
9969 | ||
df58fc94 RS |
9970 | case M_ULH_A: |
9971 | ab = 1; | |
252b5132 RH |
9972 | case M_ULH: |
9973 | s = "lb"; | |
df58fc94 RS |
9974 | s2 = "lbu"; |
9975 | off = 1; | |
9976 | goto uld_st; | |
9977 | case M_ULHU_A: | |
9978 | ab = 1; | |
252b5132 RH |
9979 | case M_ULHU: |
9980 | s = "lbu"; | |
df58fc94 RS |
9981 | s2 = "lbu"; |
9982 | off = 1; | |
9983 | goto uld_st; | |
9984 | case M_ULW_A: | |
9985 | ab = 1; | |
9986 | case M_ULW: | |
9987 | s = "lwl"; | |
9988 | s2 = "lwr"; | |
9989 | off12 = mips_opts.micromips; | |
9990 | off = 3; | |
9991 | goto uld_st; | |
9992 | case M_ULD_A: | |
9993 | ab = 1; | |
252b5132 RH |
9994 | case M_ULD: |
9995 | s = "ldl"; | |
9996 | s2 = "ldr"; | |
df58fc94 | 9997 | off12 = mips_opts.micromips; |
252b5132 | 9998 | off = 7; |
df58fc94 RS |
9999 | goto uld_st; |
10000 | case M_USH_A: | |
10001 | ab = 1; | |
10002 | case M_USH: | |
10003 | s = "sb"; | |
10004 | s2 = "sb"; | |
10005 | off = 1; | |
10006 | ust = 1; | |
10007 | goto uld_st; | |
10008 | case M_USW_A: | |
10009 | ab = 1; | |
10010 | case M_USW: | |
10011 | s = "swl"; | |
10012 | s2 = "swr"; | |
10013 | off12 = mips_opts.micromips; | |
252b5132 | 10014 | off = 3; |
df58fc94 RS |
10015 | ust = 1; |
10016 | goto uld_st; | |
10017 | case M_USD_A: | |
10018 | ab = 1; | |
10019 | case M_USD: | |
10020 | s = "sdl"; | |
10021 | s2 = "sdr"; | |
10022 | off12 = mips_opts.micromips; | |
10023 | off = 7; | |
10024 | ust = 1; | |
10025 | ||
10026 | uld_st: | |
10027 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10028 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10029 | |
10030 | ep = &offset_expr; | |
10031 | expr1.X_add_number = 0; | |
10032 | if (ab) | |
10033 | { | |
10034 | used_at = 1; | |
10035 | tempreg = AT; | |
10036 | load_address (tempreg, ep, &used_at); | |
10037 | if (breg != 0) | |
10038 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10039 | tempreg, tempreg, breg); | |
10040 | breg = tempreg; | |
10041 | tempreg = treg; | |
10042 | ep = &expr1; | |
10043 | } | |
10044 | else if (off12 | |
10045 | && (offset_expr.X_op != O_constant | |
10046 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10047 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10048 | { | |
10049 | used_at = 1; | |
10050 | tempreg = AT; | |
10051 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10052 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10053 | breg = tempreg; | |
10054 | tempreg = treg; | |
10055 | ep = &expr1; | |
10056 | } | |
10057 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10058 | { |
10059 | used_at = 1; | |
10060 | tempreg = AT; | |
10061 | } | |
252b5132 | 10062 | else |
df58fc94 | 10063 | tempreg = treg; |
af22f5b2 | 10064 | |
df58fc94 RS |
10065 | if (off == 1) |
10066 | goto ulh_sh; | |
252b5132 | 10067 | |
90ecf173 | 10068 | if (!target_big_endian) |
df58fc94 RS |
10069 | ep->X_add_number += off; |
10070 | if (!off12) | |
10071 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10072 | else |
df58fc94 RS |
10073 | macro_build (NULL, s, "t,~(b)", |
10074 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10075 | ||
90ecf173 | 10076 | if (!target_big_endian) |
df58fc94 | 10077 | ep->X_add_number -= off; |
252b5132 | 10078 | else |
df58fc94 RS |
10079 | ep->X_add_number += off; |
10080 | if (!off12) | |
10081 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10082 | else | |
10083 | macro_build (NULL, s2, "t,~(b)", | |
10084 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10085 | |
df58fc94 RS |
10086 | /* If necessary, move the result in tempreg to the final destination. */ |
10087 | if (!ust && treg != tempreg) | |
10088 | { | |
10089 | /* Protect second load's delay slot. */ | |
10090 | load_delay_nop (); | |
10091 | move_register (treg, tempreg); | |
10092 | } | |
8fc2e39e | 10093 | break; |
252b5132 | 10094 | |
df58fc94 | 10095 | ulh_sh: |
d6bc6245 | 10096 | used_at = 1; |
df58fc94 RS |
10097 | if (target_big_endian == ust) |
10098 | ep->X_add_number += off; | |
10099 | tempreg = ust || ab ? treg : AT; | |
10100 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10101 | ||
10102 | /* For halfword transfers we need a temporary register to shuffle | |
10103 | bytes. Unfortunately for M_USH_A we have none available before | |
10104 | the next store as AT holds the base address. We deal with this | |
10105 | case by clobbering TREG and then restoring it as with ULH. */ | |
10106 | tempreg = ust == ab ? treg : AT; | |
10107 | if (ust) | |
10108 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10109 | ||
10110 | if (target_big_endian == ust) | |
10111 | ep->X_add_number -= off; | |
252b5132 | 10112 | else |
df58fc94 RS |
10113 | ep->X_add_number += off; |
10114 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10115 | |
df58fc94 RS |
10116 | /* For M_USH_A re-retrieve the LSB. */ |
10117 | if (ust && ab) | |
10118 | { | |
10119 | if (target_big_endian) | |
10120 | ep->X_add_number += off; | |
10121 | else | |
10122 | ep->X_add_number -= off; | |
10123 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10124 | } | |
10125 | /* For ULH and M_USH_A OR the LSB in. */ | |
10126 | if (!ust || ab) | |
10127 | { | |
10128 | tempreg = !ab ? AT : treg; | |
10129 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10130 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10131 | } | |
252b5132 RH |
10132 | break; |
10133 | ||
10134 | default: | |
10135 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10136 | are added dynamically. */ |
252b5132 RH |
10137 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10138 | break; | |
10139 | } | |
741fe287 | 10140 | if (!mips_opts.at && used_at) |
8fc2e39e | 10141 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10142 | } |
10143 | ||
10144 | /* Implement macros in mips16 mode. */ | |
10145 | ||
10146 | static void | |
17a2f251 | 10147 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10148 | { |
10149 | int mask; | |
10150 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10151 | expressionS expr1; |
10152 | int dbl; | |
10153 | const char *s, *s2, *s3; | |
10154 | ||
10155 | mask = ip->insn_mo->mask; | |
10156 | ||
bf12938e RS |
10157 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10158 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10159 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10160 | |
252b5132 RH |
10161 | expr1.X_op = O_constant; |
10162 | expr1.X_op_symbol = NULL; | |
10163 | expr1.X_add_symbol = NULL; | |
10164 | expr1.X_add_number = 1; | |
10165 | ||
10166 | dbl = 0; | |
10167 | ||
10168 | switch (mask) | |
10169 | { | |
10170 | default: | |
b37df7c4 | 10171 | abort (); |
252b5132 RH |
10172 | |
10173 | case M_DDIV_3: | |
10174 | dbl = 1; | |
10175 | case M_DIV_3: | |
10176 | s = "mflo"; | |
10177 | goto do_div3; | |
10178 | case M_DREM_3: | |
10179 | dbl = 1; | |
10180 | case M_REM_3: | |
10181 | s = "mfhi"; | |
10182 | do_div3: | |
7d10b47d | 10183 | start_noreorder (); |
67c0d1eb | 10184 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10185 | expr1.X_add_number = 2; |
67c0d1eb RS |
10186 | macro_build (&expr1, "bnez", "x,p", yreg); |
10187 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10188 | |
252b5132 RH |
10189 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10190 | since that causes an overflow. We should do that as well, | |
10191 | but I don't see how to do the comparisons without a temporary | |
10192 | register. */ | |
7d10b47d | 10193 | end_noreorder (); |
67c0d1eb | 10194 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10195 | break; |
10196 | ||
10197 | case M_DIVU_3: | |
10198 | s = "divu"; | |
10199 | s2 = "mflo"; | |
10200 | goto do_divu3; | |
10201 | case M_REMU_3: | |
10202 | s = "divu"; | |
10203 | s2 = "mfhi"; | |
10204 | goto do_divu3; | |
10205 | case M_DDIVU_3: | |
10206 | s = "ddivu"; | |
10207 | s2 = "mflo"; | |
10208 | goto do_divu3; | |
10209 | case M_DREMU_3: | |
10210 | s = "ddivu"; | |
10211 | s2 = "mfhi"; | |
10212 | do_divu3: | |
7d10b47d | 10213 | start_noreorder (); |
67c0d1eb | 10214 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10215 | expr1.X_add_number = 2; |
67c0d1eb RS |
10216 | macro_build (&expr1, "bnez", "x,p", yreg); |
10217 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10218 | end_noreorder (); |
67c0d1eb | 10219 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10220 | break; |
10221 | ||
10222 | case M_DMUL: | |
10223 | dbl = 1; | |
10224 | case M_MUL: | |
67c0d1eb RS |
10225 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10226 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10227 | break; |
252b5132 RH |
10228 | |
10229 | case M_DSUBU_I: | |
10230 | dbl = 1; | |
10231 | goto do_subu; | |
10232 | case M_SUBU_I: | |
10233 | do_subu: | |
10234 | if (imm_expr.X_op != O_constant) | |
10235 | as_bad (_("Unsupported large constant")); | |
10236 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10237 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10238 | break; |
10239 | ||
10240 | case M_SUBU_I_2: | |
10241 | if (imm_expr.X_op != O_constant) | |
10242 | as_bad (_("Unsupported large constant")); | |
10243 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10244 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10245 | break; |
10246 | ||
10247 | case M_DSUBU_I_2: | |
10248 | if (imm_expr.X_op != O_constant) | |
10249 | as_bad (_("Unsupported large constant")); | |
10250 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10251 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10252 | break; |
10253 | ||
10254 | case M_BEQ: | |
10255 | s = "cmp"; | |
10256 | s2 = "bteqz"; | |
10257 | goto do_branch; | |
10258 | case M_BNE: | |
10259 | s = "cmp"; | |
10260 | s2 = "btnez"; | |
10261 | goto do_branch; | |
10262 | case M_BLT: | |
10263 | s = "slt"; | |
10264 | s2 = "btnez"; | |
10265 | goto do_branch; | |
10266 | case M_BLTU: | |
10267 | s = "sltu"; | |
10268 | s2 = "btnez"; | |
10269 | goto do_branch; | |
10270 | case M_BLE: | |
10271 | s = "slt"; | |
10272 | s2 = "bteqz"; | |
10273 | goto do_reverse_branch; | |
10274 | case M_BLEU: | |
10275 | s = "sltu"; | |
10276 | s2 = "bteqz"; | |
10277 | goto do_reverse_branch; | |
10278 | case M_BGE: | |
10279 | s = "slt"; | |
10280 | s2 = "bteqz"; | |
10281 | goto do_branch; | |
10282 | case M_BGEU: | |
10283 | s = "sltu"; | |
10284 | s2 = "bteqz"; | |
10285 | goto do_branch; | |
10286 | case M_BGT: | |
10287 | s = "slt"; | |
10288 | s2 = "btnez"; | |
10289 | goto do_reverse_branch; | |
10290 | case M_BGTU: | |
10291 | s = "sltu"; | |
10292 | s2 = "btnez"; | |
10293 | ||
10294 | do_reverse_branch: | |
10295 | tmp = xreg; | |
10296 | xreg = yreg; | |
10297 | yreg = tmp; | |
10298 | ||
10299 | do_branch: | |
67c0d1eb RS |
10300 | macro_build (NULL, s, "x,y", xreg, yreg); |
10301 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10302 | break; |
10303 | ||
10304 | case M_BEQ_I: | |
10305 | s = "cmpi"; | |
10306 | s2 = "bteqz"; | |
10307 | s3 = "x,U"; | |
10308 | goto do_branch_i; | |
10309 | case M_BNE_I: | |
10310 | s = "cmpi"; | |
10311 | s2 = "btnez"; | |
10312 | s3 = "x,U"; | |
10313 | goto do_branch_i; | |
10314 | case M_BLT_I: | |
10315 | s = "slti"; | |
10316 | s2 = "btnez"; | |
10317 | s3 = "x,8"; | |
10318 | goto do_branch_i; | |
10319 | case M_BLTU_I: | |
10320 | s = "sltiu"; | |
10321 | s2 = "btnez"; | |
10322 | s3 = "x,8"; | |
10323 | goto do_branch_i; | |
10324 | case M_BLE_I: | |
10325 | s = "slti"; | |
10326 | s2 = "btnez"; | |
10327 | s3 = "x,8"; | |
10328 | goto do_addone_branch_i; | |
10329 | case M_BLEU_I: | |
10330 | s = "sltiu"; | |
10331 | s2 = "btnez"; | |
10332 | s3 = "x,8"; | |
10333 | goto do_addone_branch_i; | |
10334 | case M_BGE_I: | |
10335 | s = "slti"; | |
10336 | s2 = "bteqz"; | |
10337 | s3 = "x,8"; | |
10338 | goto do_branch_i; | |
10339 | case M_BGEU_I: | |
10340 | s = "sltiu"; | |
10341 | s2 = "bteqz"; | |
10342 | s3 = "x,8"; | |
10343 | goto do_branch_i; | |
10344 | case M_BGT_I: | |
10345 | s = "slti"; | |
10346 | s2 = "bteqz"; | |
10347 | s3 = "x,8"; | |
10348 | goto do_addone_branch_i; | |
10349 | case M_BGTU_I: | |
10350 | s = "sltiu"; | |
10351 | s2 = "bteqz"; | |
10352 | s3 = "x,8"; | |
10353 | ||
10354 | do_addone_branch_i: | |
10355 | if (imm_expr.X_op != O_constant) | |
10356 | as_bad (_("Unsupported large constant")); | |
10357 | ++imm_expr.X_add_number; | |
10358 | ||
10359 | do_branch_i: | |
67c0d1eb RS |
10360 | macro_build (&imm_expr, s, s3, xreg); |
10361 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10362 | break; |
10363 | ||
10364 | case M_ABS: | |
10365 | expr1.X_add_number = 0; | |
67c0d1eb | 10366 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10367 | if (xreg != yreg) |
67c0d1eb | 10368 | move_register (xreg, yreg); |
252b5132 | 10369 | expr1.X_add_number = 2; |
67c0d1eb RS |
10370 | macro_build (&expr1, "bteqz", "p"); |
10371 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10372 | } |
10373 | } | |
10374 | ||
10375 | /* For consistency checking, verify that all bits are specified either | |
10376 | by the match/mask part of the instruction definition, or by the | |
10377 | operand list. */ | |
10378 | static int | |
17a2f251 | 10379 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10380 | { |
10381 | const char *p = opc->args; | |
10382 | char c; | |
10383 | unsigned long used_bits = opc->mask; | |
10384 | ||
10385 | if ((used_bits & opc->match) != opc->match) | |
10386 | { | |
10387 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10388 | opc->name, opc->args); | |
10389 | return 0; | |
10390 | } | |
10391 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10392 | while (*p) | |
10393 | switch (c = *p++) | |
10394 | { | |
10395 | case ',': break; | |
10396 | case '(': break; | |
10397 | case ')': break; | |
af7ee8bf CD |
10398 | case '+': |
10399 | switch (c = *p++) | |
10400 | { | |
9bcd4f99 TS |
10401 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10402 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10403 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10404 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10405 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10406 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10407 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10408 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10409 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10410 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10411 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10412 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10413 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10414 | case 'I': break; | |
ef2e4d86 CF |
10415 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10416 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10417 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10418 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10419 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10420 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10421 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10422 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10423 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10424 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10425 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10426 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10427 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10428 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10429 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10430 | |
af7ee8bf CD |
10431 | default: |
10432 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10433 | c, opc->name, opc->args); | |
10434 | return 0; | |
10435 | } | |
10436 | break; | |
252b5132 RH |
10437 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10438 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10439 | case 'A': break; | |
4372b673 | 10440 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10441 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10442 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10443 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10444 | case 'F': break; | |
10445 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10446 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10447 | case 'I': break; |
e972090a | 10448 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10449 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10450 | case 'L': break; |
10451 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10452 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10453 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10454 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10455 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10456 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10457 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10458 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10459 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10460 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10461 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10462 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10463 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10464 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10465 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10466 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10467 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10468 | case 'f': break; | |
10469 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10470 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10471 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10472 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10473 | case 'l': break; | |
10474 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10475 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10476 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10477 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10478 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10479 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10480 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10481 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10482 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10483 | case 'x': break; | |
10484 | case 'z': break; | |
10485 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10486 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10487 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10488 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10489 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10490 | case '[': break; | |
10491 | case ']': break; | |
620edafd | 10492 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10493 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10494 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10495 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10496 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10497 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10498 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10499 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10500 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10501 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10502 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10503 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10504 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10505 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10506 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10507 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10508 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10509 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10510 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10511 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10512 | default: |
10513 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10514 | c, opc->name, opc->args); | |
10515 | return 0; | |
10516 | } | |
10517 | #undef USE_BITS | |
10518 | if (used_bits != 0xffffffff) | |
10519 | { | |
10520 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10521 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10522 | return 0; | |
10523 | } | |
10524 | return 1; | |
10525 | } | |
10526 | ||
df58fc94 RS |
10527 | /* For consistency checking, verify that the length implied matches the |
10528 | major opcode and that all bits are specified either by the match/mask | |
10529 | part of the instruction definition, or by the operand list. */ | |
10530 | ||
10531 | static int | |
10532 | validate_micromips_insn (const struct mips_opcode *opc) | |
10533 | { | |
10534 | unsigned long match = opc->match; | |
10535 | unsigned long mask = opc->mask; | |
10536 | const char *p = opc->args; | |
10537 | unsigned long insn_bits; | |
10538 | unsigned long used_bits; | |
10539 | unsigned long major; | |
10540 | unsigned int length; | |
10541 | char e; | |
10542 | char c; | |
10543 | ||
10544 | if ((mask & match) != match) | |
10545 | { | |
10546 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10547 | opc->name, opc->args); | |
10548 | return 0; | |
10549 | } | |
10550 | length = micromips_insn_length (opc); | |
10551 | if (length != 2 && length != 4) | |
10552 | { | |
10553 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10554 | "%s %s"), length, opc->name, opc->args); | |
10555 | return 0; | |
10556 | } | |
10557 | major = match >> (10 + 8 * (length - 2)); | |
10558 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10559 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10560 | { | |
10561 | as_bad (_("Internal error: bad microMIPS opcode " | |
10562 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10563 | return 0; | |
10564 | } | |
10565 | ||
10566 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10567 | insn_bits = 1 << 4 * length; | |
10568 | insn_bits <<= 4 * length; | |
10569 | insn_bits -= 1; | |
10570 | used_bits = mask; | |
10571 | #define USE_BITS(field) \ | |
10572 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10573 | while (*p) | |
10574 | switch (c = *p++) | |
10575 | { | |
10576 | case ',': break; | |
10577 | case '(': break; | |
10578 | case ')': break; | |
10579 | case '+': | |
10580 | e = c; | |
10581 | switch (c = *p++) | |
10582 | { | |
10583 | case 'A': USE_BITS (EXTLSB); break; | |
10584 | case 'B': USE_BITS (INSMSB); break; | |
10585 | case 'C': USE_BITS (EXTMSBD); break; | |
10586 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10587 | case 'E': USE_BITS (EXTLSB); break; | |
10588 | case 'F': USE_BITS (INSMSB); break; | |
10589 | case 'G': USE_BITS (EXTMSBD); break; | |
10590 | case 'H': USE_BITS (EXTMSBD); break; | |
10591 | default: | |
10592 | as_bad (_("Internal error: bad mips opcode " | |
10593 | "(unknown extension operand type `%c%c'): %s %s"), | |
10594 | e, c, opc->name, opc->args); | |
10595 | return 0; | |
10596 | } | |
10597 | break; | |
10598 | case 'm': | |
10599 | e = c; | |
10600 | switch (c = *p++) | |
10601 | { | |
10602 | case 'A': USE_BITS (IMMA); break; | |
10603 | case 'B': USE_BITS (IMMB); break; | |
10604 | case 'C': USE_BITS (IMMC); break; | |
10605 | case 'D': USE_BITS (IMMD); break; | |
10606 | case 'E': USE_BITS (IMME); break; | |
10607 | case 'F': USE_BITS (IMMF); break; | |
10608 | case 'G': USE_BITS (IMMG); break; | |
10609 | case 'H': USE_BITS (IMMH); break; | |
10610 | case 'I': USE_BITS (IMMI); break; | |
10611 | case 'J': USE_BITS (IMMJ); break; | |
10612 | case 'L': USE_BITS (IMML); break; | |
10613 | case 'M': USE_BITS (IMMM); break; | |
10614 | case 'N': USE_BITS (IMMN); break; | |
10615 | case 'O': USE_BITS (IMMO); break; | |
10616 | case 'P': USE_BITS (IMMP); break; | |
10617 | case 'Q': USE_BITS (IMMQ); break; | |
10618 | case 'U': USE_BITS (IMMU); break; | |
10619 | case 'W': USE_BITS (IMMW); break; | |
10620 | case 'X': USE_BITS (IMMX); break; | |
10621 | case 'Y': USE_BITS (IMMY); break; | |
10622 | case 'Z': break; | |
10623 | case 'a': break; | |
10624 | case 'b': USE_BITS (MB); break; | |
10625 | case 'c': USE_BITS (MC); break; | |
10626 | case 'd': USE_BITS (MD); break; | |
10627 | case 'e': USE_BITS (ME); break; | |
10628 | case 'f': USE_BITS (MF); break; | |
10629 | case 'g': USE_BITS (MG); break; | |
10630 | case 'h': USE_BITS (MH); break; | |
10631 | case 'i': USE_BITS (MI); break; | |
10632 | case 'j': USE_BITS (MJ); break; | |
10633 | case 'l': USE_BITS (ML); break; | |
10634 | case 'm': USE_BITS (MM); break; | |
10635 | case 'n': USE_BITS (MN); break; | |
10636 | case 'p': USE_BITS (MP); break; | |
10637 | case 'q': USE_BITS (MQ); break; | |
10638 | case 'r': break; | |
10639 | case 's': break; | |
10640 | case 't': break; | |
10641 | case 'x': break; | |
10642 | case 'y': break; | |
10643 | case 'z': break; | |
10644 | default: | |
10645 | as_bad (_("Internal error: bad mips opcode " | |
10646 | "(unknown extension operand type `%c%c'): %s %s"), | |
10647 | e, c, opc->name, opc->args); | |
10648 | return 0; | |
10649 | } | |
10650 | break; | |
10651 | case '.': USE_BITS (OFFSET10); break; | |
10652 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10653 | case '2': USE_BITS (BP); break; |
10654 | case '3': USE_BITS (SA3); break; | |
10655 | case '4': USE_BITS (SA4); break; | |
10656 | case '5': USE_BITS (IMM8); break; | |
10657 | case '6': USE_BITS (RS); break; | |
10658 | case '7': USE_BITS (DSPACC); break; | |
10659 | case '8': USE_BITS (WRDSP); break; | |
10660 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10661 | case '<': USE_BITS (SHAMT); break; |
10662 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10663 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10664 | case 'B': USE_BITS (CODE10); break; |
10665 | case 'C': USE_BITS (COPZ); break; | |
10666 | case 'D': USE_BITS (FD); break; | |
10667 | case 'E': USE_BITS (RT); break; | |
10668 | case 'G': USE_BITS (RS); break; | |
444d75be | 10669 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10670 | case 'K': USE_BITS (RS); break; |
10671 | case 'M': USE_BITS (CCC); break; | |
10672 | case 'N': USE_BITS (BCC); break; | |
10673 | case 'R': USE_BITS (FR); break; | |
10674 | case 'S': USE_BITS (FS); break; | |
10675 | case 'T': USE_BITS (FT); break; | |
10676 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10677 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10678 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10679 | case 'a': USE_BITS (TARGET); break; |
10680 | case 'b': USE_BITS (RS); break; | |
10681 | case 'c': USE_BITS (CODE); break; | |
10682 | case 'd': USE_BITS (RD); break; | |
10683 | case 'h': USE_BITS (PREFX); break; | |
10684 | case 'i': USE_BITS (IMMEDIATE); break; | |
10685 | case 'j': USE_BITS (DELTA); break; | |
10686 | case 'k': USE_BITS (CACHE); break; | |
10687 | case 'n': USE_BITS (RT); break; | |
10688 | case 'o': USE_BITS (DELTA); break; | |
10689 | case 'p': USE_BITS (DELTA); break; | |
10690 | case 'q': USE_BITS (CODE2); break; | |
10691 | case 'r': USE_BITS (RS); break; | |
10692 | case 's': USE_BITS (RS); break; | |
10693 | case 't': USE_BITS (RT); break; | |
10694 | case 'u': USE_BITS (IMMEDIATE); break; | |
10695 | case 'v': USE_BITS (RS); break; | |
10696 | case 'w': USE_BITS (RT); break; | |
10697 | case 'y': USE_BITS (RS3); break; | |
10698 | case 'z': break; | |
10699 | case '|': USE_BITS (TRAP); break; | |
10700 | case '~': USE_BITS (OFFSET12); break; | |
10701 | default: | |
10702 | as_bad (_("Internal error: bad microMIPS opcode " | |
10703 | "(unknown operand type `%c'): %s %s"), | |
10704 | c, opc->name, opc->args); | |
10705 | return 0; | |
10706 | } | |
10707 | #undef USE_BITS | |
10708 | if (used_bits != insn_bits) | |
10709 | { | |
10710 | if (~used_bits & insn_bits) | |
10711 | as_bad (_("Internal error: bad microMIPS opcode " | |
10712 | "(bits 0x%lx undefined): %s %s"), | |
10713 | ~used_bits & insn_bits, opc->name, opc->args); | |
10714 | if (used_bits & ~insn_bits) | |
10715 | as_bad (_("Internal error: bad microMIPS opcode " | |
10716 | "(bits 0x%lx defined): %s %s"), | |
10717 | used_bits & ~insn_bits, opc->name, opc->args); | |
10718 | return 0; | |
10719 | } | |
10720 | return 1; | |
10721 | } | |
10722 | ||
9bcd4f99 TS |
10723 | /* UDI immediates. */ |
10724 | struct mips_immed { | |
10725 | char type; | |
10726 | unsigned int shift; | |
10727 | unsigned long mask; | |
10728 | const char * desc; | |
10729 | }; | |
10730 | ||
10731 | static const struct mips_immed mips_immed[] = { | |
10732 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10733 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10734 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10735 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10736 | { 0,0,0,0 } | |
10737 | }; | |
10738 | ||
7455baf8 TS |
10739 | /* Check whether an odd floating-point register is allowed. */ |
10740 | static int | |
10741 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10742 | { | |
10743 | const char *s = insn->name; | |
10744 | ||
10745 | if (insn->pinfo == INSN_MACRO) | |
10746 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10747 | return 1; | |
10748 | ||
e407c74b | 10749 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10750 | { |
10751 | /* Allow odd registers for single-precision ops. */ | |
10752 | switch (insn->pinfo & (FP_S | FP_D)) | |
10753 | { | |
10754 | case FP_S: | |
10755 | case 0: | |
10756 | return 1; /* both single precision - ok */ | |
10757 | case FP_D: | |
10758 | return 0; /* both double precision - fail */ | |
10759 | default: | |
10760 | break; | |
10761 | } | |
10762 | ||
10763 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10764 | s = strchr (insn->name, '.'); | |
10765 | if (argnum == 2) | |
10766 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10767 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10768 | } | |
10769 | ||
10770 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10771 | if ((insn->pinfo & FP_S) | |
10772 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10773 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10774 | return 1; | |
10775 | ||
10776 | return 0; | |
10777 | } | |
10778 | ||
df58fc94 RS |
10779 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10780 | taking bits from BIT up. */ | |
10781 | static int | |
10782 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10783 | { | |
10784 | return (ep->X_op == O_constant | |
10785 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10786 | && ep->X_add_number >= min << bit | |
10787 | && ep->X_add_number < max << bit); | |
10788 | } | |
10789 | ||
252b5132 RH |
10790 | /* This routine assembles an instruction into its binary format. As a |
10791 | side effect, it sets one of the global variables imm_reloc or | |
10792 | offset_reloc to the type of relocation to do if one of the operands | |
10793 | is an address expression. */ | |
10794 | ||
10795 | static void | |
17a2f251 | 10796 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10797 | { |
df58fc94 RS |
10798 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10799 | bfd_boolean need_delay_slot_ok = TRUE; | |
10800 | struct mips_opcode *firstinsn = NULL; | |
10801 | const struct mips_opcode *past; | |
10802 | struct hash_control *hash; | |
252b5132 RH |
10803 | char *s; |
10804 | const char *args; | |
43841e91 | 10805 | char c = 0; |
252b5132 RH |
10806 | struct mips_opcode *insn; |
10807 | char *argsStart; | |
10808 | unsigned int regno; | |
34224acf | 10809 | unsigned int lastregno; |
df58fc94 | 10810 | unsigned int destregno = 0; |
af7ee8bf | 10811 | unsigned int lastpos = 0; |
071742cf | 10812 | unsigned int limlo, limhi; |
f02d8318 | 10813 | int sizelo; |
252b5132 | 10814 | char *s_reset; |
74cd071d | 10815 | offsetT min_range, max_range; |
df58fc94 | 10816 | long opend; |
a40bc9dd | 10817 | char *name; |
707bfff6 TS |
10818 | int argnum; |
10819 | unsigned int rtype; | |
df58fc94 | 10820 | char *dot; |
a40bc9dd | 10821 | long end; |
252b5132 RH |
10822 | |
10823 | insn_error = NULL; | |
10824 | ||
df58fc94 RS |
10825 | if (mips_opts.micromips) |
10826 | { | |
10827 | hash = micromips_op_hash; | |
10828 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10829 | } | |
10830 | else | |
10831 | { | |
10832 | hash = op_hash; | |
10833 | past = &mips_opcodes[NUMOPCODES]; | |
10834 | } | |
10835 | forced_insn_length = 0; | |
252b5132 | 10836 | insn = NULL; |
252b5132 | 10837 | |
df58fc94 | 10838 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10839 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10840 | continue; | |
bdaaa2e1 | 10841 | |
a40bc9dd RS |
10842 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10843 | name = alloca (end + 1); | |
10844 | memcpy (name, str, end); | |
10845 | name[end] = '\0'; | |
252b5132 | 10846 | |
df58fc94 RS |
10847 | for (;;) |
10848 | { | |
10849 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10850 | ||
10851 | if (insn != NULL || !mips_opts.micromips) | |
10852 | break; | |
10853 | if (forced_insn_length) | |
10854 | break; | |
10855 | ||
10856 | /* See if there's an instruction size override suffix, | |
10857 | either `16' or `32', at the end of the mnemonic proper, | |
10858 | that defines the operation, i.e. before the first `.' | |
10859 | character if any. Strip it and retry. */ | |
10860 | dot = strchr (name, '.'); | |
10861 | opend = dot != NULL ? dot - name : end; | |
10862 | if (opend < 3) | |
10863 | break; | |
10864 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10865 | forced_insn_length = 2; | |
10866 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10867 | forced_insn_length = 4; | |
10868 | else | |
10869 | break; | |
10870 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10871 | } | |
252b5132 RH |
10872 | if (insn == NULL) |
10873 | { | |
a40bc9dd RS |
10874 | insn_error = _("Unrecognized opcode"); |
10875 | return; | |
252b5132 RH |
10876 | } |
10877 | ||
df58fc94 RS |
10878 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10879 | we make up to two passes over the relevant fragment of the opcode | |
10880 | table. First we try instructions that meet the delay slot's length | |
10881 | requirement. If none matched, then we retry with the remaining ones | |
10882 | and if one matches, then we use it and then issue an appropriate | |
10883 | warning later on. */ | |
a40bc9dd | 10884 | argsStart = s = str + end; |
252b5132 RH |
10885 | for (;;) |
10886 | { | |
df58fc94 RS |
10887 | bfd_boolean delay_slot_ok; |
10888 | bfd_boolean size_ok; | |
b34976b6 | 10889 | bfd_boolean ok; |
252b5132 | 10890 | |
a40bc9dd | 10891 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10892 | |
f79e2745 | 10893 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10894 | size_ok = is_size_valid (insn); |
10895 | delay_slot_ok = is_delay_slot_valid (insn); | |
10896 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10897 | { |
df58fc94 RS |
10898 | firstinsn = insn; |
10899 | wrong_delay_slot_insns = TRUE; | |
10900 | } | |
10901 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10902 | { | |
10903 | static char buf[256]; | |
10904 | ||
10905 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10906 | { |
10907 | ++insn; | |
10908 | continue; | |
10909 | } | |
df58fc94 | 10910 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10911 | { |
df58fc94 RS |
10912 | gas_assert (firstinsn); |
10913 | need_delay_slot_ok = FALSE; | |
10914 | past = insn + 1; | |
10915 | insn = firstinsn; | |
10916 | continue; | |
252b5132 | 10917 | } |
df58fc94 RS |
10918 | |
10919 | if (insn_error) | |
10920 | return; | |
10921 | ||
10922 | if (!ok) | |
7bd942df | 10923 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10924 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10925 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10926 | else | |
10927 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10928 | 8 * forced_insn_length); | |
10929 | insn_error = buf; | |
10930 | ||
10931 | return; | |
252b5132 RH |
10932 | } |
10933 | ||
1e915849 | 10934 | create_insn (ip, insn); |
268f6bed | 10935 | insn_error = NULL; |
707bfff6 | 10936 | argnum = 1; |
24864476 | 10937 | lastregno = 0xffffffff; |
252b5132 RH |
10938 | for (args = insn->args;; ++args) |
10939 | { | |
deec1734 CD |
10940 | int is_mdmx; |
10941 | ||
ad8d3bb3 | 10942 | s += strspn (s, " \t"); |
deec1734 | 10943 | is_mdmx = 0; |
252b5132 RH |
10944 | switch (*args) |
10945 | { | |
10946 | case '\0': /* end of args */ | |
10947 | if (*s == '\0') | |
10948 | return; | |
10949 | break; | |
10950 | ||
03f66e8a MR |
10951 | case '2': |
10952 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10953 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10954 | my_getExpression (&imm_expr, s); |
10955 | check_absolute_expr (ip, &imm_expr); | |
10956 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10957 | && (unsigned long) imm_expr.X_add_number != 3) | |
10958 | { | |
10959 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10960 | (unsigned long) imm_expr.X_add_number); | |
10961 | } | |
03f66e8a MR |
10962 | INSERT_OPERAND (mips_opts.micromips, |
10963 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
10964 | imm_expr.X_op = O_absent; |
10965 | s = expr_end; | |
10966 | continue; | |
10967 | ||
03f66e8a MR |
10968 | case '3': |
10969 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
10970 | code) or 21 (for microMIPS code). */ | |
10971 | { | |
10972 | unsigned long mask = (mips_opts.micromips | |
10973 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
10974 | ||
10975 | my_getExpression (&imm_expr, s); | |
10976 | check_absolute_expr (ip, &imm_expr); | |
10977 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10978 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10979 | mask, (unsigned long) imm_expr.X_add_number); | |
10980 | INSERT_OPERAND (mips_opts.micromips, | |
10981 | SA3, *ip, imm_expr.X_add_number); | |
10982 | imm_expr.X_op = O_absent; | |
10983 | s = expr_end; | |
10984 | } | |
74cd071d CF |
10985 | continue; |
10986 | ||
03f66e8a MR |
10987 | case '4': |
10988 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
10989 | code) or 21 (for microMIPS code). */ | |
10990 | { | |
10991 | unsigned long mask = (mips_opts.micromips | |
10992 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
10993 | ||
10994 | my_getExpression (&imm_expr, s); | |
10995 | check_absolute_expr (ip, &imm_expr); | |
10996 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10997 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10998 | mask, (unsigned long) imm_expr.X_add_number); | |
10999 | INSERT_OPERAND (mips_opts.micromips, | |
11000 | SA4, *ip, imm_expr.X_add_number); | |
11001 | imm_expr.X_op = O_absent; | |
11002 | s = expr_end; | |
11003 | } | |
74cd071d CF |
11004 | continue; |
11005 | ||
03f66e8a MR |
11006 | case '5': |
11007 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11008 | code) or 16 (for microMIPS code). */ | |
11009 | { | |
11010 | unsigned long mask = (mips_opts.micromips | |
11011 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11012 | ||
11013 | my_getExpression (&imm_expr, s); | |
11014 | check_absolute_expr (ip, &imm_expr); | |
11015 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11016 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11017 | mask, (unsigned long) imm_expr.X_add_number); | |
11018 | INSERT_OPERAND (mips_opts.micromips, | |
11019 | IMM8, *ip, imm_expr.X_add_number); | |
11020 | imm_expr.X_op = O_absent; | |
11021 | s = expr_end; | |
11022 | } | |
74cd071d CF |
11023 | continue; |
11024 | ||
03f66e8a MR |
11025 | case '6': |
11026 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11027 | code) or 21 (for microMIPS code). */ | |
11028 | { | |
11029 | unsigned long mask = (mips_opts.micromips | |
11030 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11031 | ||
11032 | my_getExpression (&imm_expr, s); | |
11033 | check_absolute_expr (ip, &imm_expr); | |
11034 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11035 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11036 | mask, (unsigned long) imm_expr.X_add_number); | |
11037 | INSERT_OPERAND (mips_opts.micromips, | |
11038 | RS, *ip, imm_expr.X_add_number); | |
11039 | imm_expr.X_op = O_absent; | |
11040 | s = expr_end; | |
11041 | } | |
74cd071d CF |
11042 | continue; |
11043 | ||
90ecf173 | 11044 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11045 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11046 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11047 | { |
11048 | regno = s[3] - '0'; | |
11049 | s += 4; | |
03f66e8a | 11050 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11051 | continue; |
11052 | } | |
11053 | else | |
11054 | as_bad (_("Invalid dsp acc register")); | |
11055 | break; | |
11056 | ||
03f66e8a MR |
11057 | case '8': |
11058 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11059 | code) or 14 (for microMIPS code). */ | |
11060 | { | |
11061 | unsigned long mask = (mips_opts.micromips | |
11062 | ? MICROMIPSOP_MASK_WRDSP | |
11063 | : OP_MASK_WRDSP); | |
11064 | ||
11065 | my_getExpression (&imm_expr, s); | |
11066 | check_absolute_expr (ip, &imm_expr); | |
11067 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11068 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11069 | mask, (unsigned long) imm_expr.X_add_number); | |
11070 | INSERT_OPERAND (mips_opts.micromips, | |
11071 | WRDSP, *ip, imm_expr.X_add_number); | |
11072 | imm_expr.X_op = O_absent; | |
11073 | s = expr_end; | |
11074 | } | |
74cd071d CF |
11075 | continue; |
11076 | ||
90ecf173 | 11077 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11078 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11079 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11080 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11081 | { |
11082 | regno = s[3] - '0'; | |
11083 | s += 4; | |
df58fc94 | 11084 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11085 | continue; |
11086 | } | |
11087 | else | |
11088 | as_bad (_("Invalid dsp acc register")); | |
11089 | break; | |
11090 | ||
03f66e8a MR |
11091 | case '0': |
11092 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11093 | code) or 20 (for microMIPS code). */ | |
11094 | { | |
11095 | long mask = (mips_opts.micromips | |
11096 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11097 | ||
11098 | my_getExpression (&imm_expr, s); | |
11099 | check_absolute_expr (ip, &imm_expr); | |
11100 | min_range = -((mask + 1) >> 1); | |
11101 | max_range = ((mask + 1) >> 1) - 1; | |
11102 | if (imm_expr.X_add_number < min_range | |
11103 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11104 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11105 | (long) min_range, (long) max_range, | |
11106 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11107 | INSERT_OPERAND (mips_opts.micromips, |
11108 | DSPSFT, *ip, imm_expr.X_add_number); | |
11109 | imm_expr.X_op = O_absent; | |
11110 | s = expr_end; | |
11111 | } | |
74cd071d CF |
11112 | continue; |
11113 | ||
90ecf173 | 11114 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11115 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11116 | my_getExpression (&imm_expr, s); |
11117 | check_absolute_expr (ip, &imm_expr); | |
11118 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11119 | { | |
a9e24354 TS |
11120 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11121 | OP_MASK_RDDSP, | |
11122 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11123 | } |
df58fc94 | 11124 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11125 | imm_expr.X_op = O_absent; |
11126 | s = expr_end; | |
11127 | continue; | |
11128 | ||
90ecf173 | 11129 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11130 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11131 | my_getExpression (&imm_expr, s); |
11132 | check_absolute_expr (ip, &imm_expr); | |
11133 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11134 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11135 | if (imm_expr.X_add_number < min_range || | |
11136 | imm_expr.X_add_number > max_range) | |
11137 | { | |
a9e24354 TS |
11138 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11139 | (long) min_range, (long) max_range, | |
11140 | (long) imm_expr.X_add_number); | |
74cd071d | 11141 | } |
df58fc94 | 11142 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11143 | imm_expr.X_op = O_absent; |
11144 | s = expr_end; | |
11145 | continue; | |
11146 | ||
90ecf173 | 11147 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11148 | { |
11149 | long mask = (mips_opts.micromips | |
11150 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11151 | ||
11152 | my_getExpression (&imm_expr, s); | |
11153 | check_absolute_expr (ip, &imm_expr); | |
11154 | min_range = -((mask + 1) >> 1); | |
11155 | max_range = ((mask + 1) >> 1) - 1; | |
11156 | if (imm_expr.X_add_number < min_range | |
11157 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11158 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11159 | (long) min_range, (long) max_range, | |
11160 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11161 | INSERT_OPERAND (mips_opts.micromips, |
11162 | IMM10, *ip, imm_expr.X_add_number); | |
11163 | imm_expr.X_op = O_absent; | |
11164 | s = expr_end; | |
11165 | } | |
11166 | continue; | |
11167 | ||
11168 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11169 | gas_assert (mips_opts.micromips); | |
11170 | my_getExpression (&imm_expr, s); | |
11171 | check_absolute_expr (ip, &imm_expr); | |
11172 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11173 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11174 | MICROMIPSOP_MASK_RD, | |
11175 | (unsigned long) imm_expr.X_add_number); | |
11176 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11177 | imm_expr.X_op = O_absent; |
11178 | s = expr_end; | |
11179 | continue; | |
11180 | ||
a9e24354 | 11181 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11182 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11183 | my_getExpression (&imm_expr, s); |
11184 | check_absolute_expr (ip, &imm_expr); | |
11185 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11186 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11187 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11188 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11189 | imm_expr.X_op = O_absent; |
11190 | s = expr_end; | |
11191 | continue; | |
11192 | ||
a9e24354 | 11193 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11194 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11195 | my_getExpression (&imm_expr, s); |
11196 | check_absolute_expr (ip, &imm_expr); | |
11197 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11198 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11199 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11200 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11201 | imm_expr.X_op = O_absent; |
11202 | s = expr_end; | |
11203 | continue; | |
11204 | ||
90ecf173 | 11205 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11206 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11207 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11208 | s[3] >= '0' && s[3] <= '3') | |
11209 | { | |
11210 | regno = s[3] - '0'; | |
11211 | s += 4; | |
df58fc94 | 11212 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11213 | continue; |
11214 | } | |
11215 | else | |
11216 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11217 | break; | |
11218 | ||
90ecf173 | 11219 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11220 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11221 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11222 | s[3] >= '0' && s[3] <= '3') | |
11223 | { | |
11224 | regno = s[3] - '0'; | |
11225 | s += 4; | |
df58fc94 | 11226 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11227 | continue; |
11228 | } | |
11229 | else | |
11230 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11231 | break; | |
11232 | ||
dec0624d MR |
11233 | case '\\': /* 3-bit bit position. */ |
11234 | { | |
2906b037 MR |
11235 | unsigned long mask = (mips_opts.micromips |
11236 | ? MICROMIPSOP_MASK_3BITPOS | |
11237 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11238 | |
11239 | my_getExpression (&imm_expr, s); | |
11240 | check_absolute_expr (ip, &imm_expr); | |
11241 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11242 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11243 | ip->insn_mo->name, | |
11244 | mask, (unsigned long) imm_expr.X_add_number); | |
11245 | INSERT_OPERAND (mips_opts.micromips, | |
11246 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11247 | imm_expr.X_op = O_absent; | |
11248 | s = expr_end; | |
11249 | } | |
11250 | continue; | |
11251 | ||
252b5132 | 11252 | case ',': |
a339155f | 11253 | ++argnum; |
252b5132 RH |
11254 | if (*s++ == *args) |
11255 | continue; | |
11256 | s--; | |
11257 | switch (*++args) | |
11258 | { | |
11259 | case 'r': | |
11260 | case 'v': | |
df58fc94 | 11261 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11262 | continue; |
11263 | ||
11264 | case 'w': | |
df58fc94 | 11265 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11266 | continue; |
11267 | ||
252b5132 | 11268 | case 'W': |
df58fc94 RS |
11269 | gas_assert (!mips_opts.micromips); |
11270 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11271 | continue; |
11272 | ||
11273 | case 'V': | |
df58fc94 | 11274 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11275 | continue; |
11276 | } | |
11277 | break; | |
11278 | ||
11279 | case '(': | |
11280 | /* Handle optional base register. | |
11281 | Either the base register is omitted or | |
bdaaa2e1 | 11282 | we must have a left paren. */ |
252b5132 RH |
11283 | /* This is dependent on the next operand specifier |
11284 | is a base register specification. */ | |
df58fc94 RS |
11285 | gas_assert (args[1] == 'b' |
11286 | || (mips_opts.micromips | |
11287 | && args[1] == 'm' | |
11288 | && (args[2] == 'l' || args[2] == 'n' | |
11289 | || args[2] == 's' || args[2] == 'a'))); | |
11290 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11291 | return; |
df58fc94 | 11292 | /* Fall through. */ |
252b5132 | 11293 | |
90ecf173 | 11294 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11295 | if (*s++ == *args) |
11296 | continue; | |
11297 | break; | |
11298 | ||
11299 | case '[': /* These must match exactly. */ | |
60b63b72 | 11300 | case ']': |
df58fc94 | 11301 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11302 | if (*s++ == *args) |
11303 | continue; | |
11304 | break; | |
11305 | ||
af7ee8bf CD |
11306 | case '+': /* Opcode extension character. */ |
11307 | switch (*++args) | |
11308 | { | |
9bcd4f99 TS |
11309 | case '1': /* UDI immediates. */ |
11310 | case '2': | |
11311 | case '3': | |
11312 | case '4': | |
df58fc94 | 11313 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11314 | { |
11315 | const struct mips_immed *imm = mips_immed; | |
11316 | ||
11317 | while (imm->type && imm->type != *args) | |
11318 | ++imm; | |
11319 | if (! imm->type) | |
b37df7c4 | 11320 | abort (); |
9bcd4f99 TS |
11321 | my_getExpression (&imm_expr, s); |
11322 | check_absolute_expr (ip, &imm_expr); | |
11323 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11324 | { | |
11325 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11326 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11327 | (unsigned long) imm_expr.X_add_number, | |
11328 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11329 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11330 | } |
11331 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11332 | << imm->shift); | |
11333 | imm_expr.X_op = O_absent; | |
11334 | s = expr_end; | |
11335 | } | |
11336 | continue; | |
90ecf173 | 11337 | |
071742cf CD |
11338 | case 'A': /* ins/ext position, becomes LSB. */ |
11339 | limlo = 0; | |
11340 | limhi = 31; | |
5f74bc13 CD |
11341 | goto do_lsb; |
11342 | case 'E': | |
11343 | limlo = 32; | |
11344 | limhi = 63; | |
11345 | goto do_lsb; | |
90ecf173 | 11346 | do_lsb: |
071742cf CD |
11347 | my_getExpression (&imm_expr, s); |
11348 | check_absolute_expr (ip, &imm_expr); | |
11349 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11350 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11351 | { | |
11352 | as_bad (_("Improper position (%lu)"), | |
11353 | (unsigned long) imm_expr.X_add_number); | |
11354 | imm_expr.X_add_number = limlo; | |
11355 | } | |
11356 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11357 | INSERT_OPERAND (mips_opts.micromips, |
11358 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11359 | imm_expr.X_op = O_absent; |
11360 | s = expr_end; | |
11361 | continue; | |
11362 | ||
11363 | case 'B': /* ins size, becomes MSB. */ | |
11364 | limlo = 1; | |
11365 | limhi = 32; | |
5f74bc13 CD |
11366 | goto do_msb; |
11367 | case 'F': | |
11368 | limlo = 33; | |
11369 | limhi = 64; | |
11370 | goto do_msb; | |
90ecf173 | 11371 | do_msb: |
071742cf CD |
11372 | my_getExpression (&imm_expr, s); |
11373 | check_absolute_expr (ip, &imm_expr); | |
11374 | /* Check for negative input so that small negative numbers | |
11375 | will not succeed incorrectly. The checks against | |
11376 | (pos+size) transitively check "size" itself, | |
11377 | assuming that "pos" is reasonable. */ | |
11378 | if ((long) imm_expr.X_add_number < 0 | |
11379 | || ((unsigned long) imm_expr.X_add_number | |
11380 | + lastpos) < limlo | |
11381 | || ((unsigned long) imm_expr.X_add_number | |
11382 | + lastpos) > limhi) | |
11383 | { | |
11384 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11385 | (unsigned long) imm_expr.X_add_number, | |
11386 | (unsigned long) lastpos); | |
11387 | imm_expr.X_add_number = limlo - lastpos; | |
11388 | } | |
df58fc94 RS |
11389 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11390 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11391 | imm_expr.X_op = O_absent; |
11392 | s = expr_end; | |
11393 | continue; | |
11394 | ||
11395 | case 'C': /* ext size, becomes MSBD. */ | |
11396 | limlo = 1; | |
11397 | limhi = 32; | |
f02d8318 | 11398 | sizelo = 1; |
5f74bc13 CD |
11399 | goto do_msbd; |
11400 | case 'G': | |
11401 | limlo = 33; | |
11402 | limhi = 64; | |
f02d8318 | 11403 | sizelo = 33; |
5f74bc13 CD |
11404 | goto do_msbd; |
11405 | case 'H': | |
11406 | limlo = 33; | |
11407 | limhi = 64; | |
f02d8318 | 11408 | sizelo = 1; |
5f74bc13 | 11409 | goto do_msbd; |
90ecf173 | 11410 | do_msbd: |
071742cf CD |
11411 | my_getExpression (&imm_expr, s); |
11412 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11413 | /* The checks against (pos+size) don't transitively check |
11414 | "size" itself, assuming that "pos" is reasonable. | |
11415 | We also need to check the lower bound of "size". */ | |
11416 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11417 | || ((unsigned long) imm_expr.X_add_number |
11418 | + lastpos) < limlo | |
11419 | || ((unsigned long) imm_expr.X_add_number | |
11420 | + lastpos) > limhi) | |
11421 | { | |
11422 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11423 | (unsigned long) imm_expr.X_add_number, | |
11424 | (unsigned long) lastpos); | |
11425 | imm_expr.X_add_number = limlo - lastpos; | |
11426 | } | |
df58fc94 RS |
11427 | INSERT_OPERAND (mips_opts.micromips, |
11428 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11429 | imm_expr.X_op = O_absent; |
11430 | s = expr_end; | |
11431 | continue; | |
af7ee8bf | 11432 | |
bbcc0807 CD |
11433 | case 'D': |
11434 | /* +D is for disassembly only; never match. */ | |
11435 | break; | |
11436 | ||
5f74bc13 CD |
11437 | case 'I': |
11438 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11439 | my_getExpression (&imm2_expr, s); | |
11440 | if (imm2_expr.X_op != O_big | |
11441 | && imm2_expr.X_op != O_constant) | |
11442 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11443 | if (HAVE_32BIT_GPRS) |
11444 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11445 | s = expr_end; |
11446 | continue; | |
11447 | ||
707bfff6 | 11448 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11449 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11450 | /* +T is for disassembly only; never match. */ |
11451 | break; | |
11452 | ||
707bfff6 | 11453 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11454 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11455 | if (s[0] == '$' && ISDIGIT (s[1])) |
11456 | { | |
11457 | ++s; | |
11458 | regno = 0; | |
11459 | do | |
11460 | { | |
11461 | regno *= 10; | |
11462 | regno += *s - '0'; | |
11463 | ++s; | |
11464 | } | |
11465 | while (ISDIGIT (*s)); | |
11466 | if (regno > 31) | |
11467 | as_bad (_("Invalid register number (%d)"), regno); | |
11468 | else | |
11469 | { | |
df58fc94 | 11470 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11471 | continue; |
11472 | } | |
11473 | } | |
11474 | else | |
11475 | as_bad (_("Invalid coprocessor 0 register number")); | |
11476 | break; | |
11477 | ||
bb35fb24 NC |
11478 | case 'x': |
11479 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11480 | is not in the valid range. */ | |
df58fc94 | 11481 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11482 | my_getExpression (&imm_expr, s); |
11483 | check_absolute_expr (ip, &imm_expr); | |
11484 | if ((unsigned) imm_expr.X_add_number > 31) | |
11485 | { | |
11486 | as_bad (_("Improper bit index (%lu)"), | |
11487 | (unsigned long) imm_expr.X_add_number); | |
11488 | imm_expr.X_add_number = 0; | |
11489 | } | |
df58fc94 | 11490 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11491 | imm_expr.X_op = O_absent; |
11492 | s = expr_end; | |
11493 | continue; | |
11494 | ||
11495 | case 'X': | |
11496 | /* bbit[01] bit index when bbit is used but we generate | |
11497 | bbit[01]32 because the index is over 32. Move to the | |
11498 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11499 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11500 | my_getExpression (&imm_expr, s); |
11501 | check_absolute_expr (ip, &imm_expr); | |
11502 | if ((unsigned) imm_expr.X_add_number < 32 | |
11503 | || (unsigned) imm_expr.X_add_number > 63) | |
11504 | break; | |
df58fc94 | 11505 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11506 | imm_expr.X_op = O_absent; |
11507 | s = expr_end; | |
11508 | continue; | |
11509 | ||
11510 | case 'p': | |
11511 | /* cins, cins32, exts and exts32 position field. Give error | |
11512 | if it's not in the valid range. */ | |
df58fc94 | 11513 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11514 | my_getExpression (&imm_expr, s); |
11515 | check_absolute_expr (ip, &imm_expr); | |
11516 | if ((unsigned) imm_expr.X_add_number > 31) | |
11517 | { | |
11518 | as_bad (_("Improper position (%lu)"), | |
11519 | (unsigned long) imm_expr.X_add_number); | |
11520 | imm_expr.X_add_number = 0; | |
11521 | } | |
11522 | /* Make the pos explicit to simplify +S. */ | |
11523 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11524 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11525 | imm_expr.X_op = O_absent; |
11526 | s = expr_end; | |
11527 | continue; | |
11528 | ||
11529 | case 'P': | |
11530 | /* cins, cins32, exts and exts32 position field. Move to | |
11531 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11532 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11533 | my_getExpression (&imm_expr, s); |
11534 | check_absolute_expr (ip, &imm_expr); | |
11535 | if ((unsigned) imm_expr.X_add_number < 32 | |
11536 | || (unsigned) imm_expr.X_add_number > 63) | |
11537 | break; | |
11538 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11539 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11540 | imm_expr.X_op = O_absent; |
11541 | s = expr_end; | |
11542 | continue; | |
11543 | ||
11544 | case 's': | |
11545 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11546 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11547 | my_getExpression (&imm_expr, s); |
11548 | check_absolute_expr (ip, &imm_expr); | |
11549 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11550 | { | |
11551 | as_bad (_("Improper size (%lu)"), | |
11552 | (unsigned long) imm_expr.X_add_number); | |
11553 | imm_expr.X_add_number = 0; | |
11554 | } | |
df58fc94 | 11555 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11556 | imm_expr.X_op = O_absent; |
11557 | s = expr_end; | |
11558 | continue; | |
11559 | ||
11560 | case 'S': | |
11561 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11562 | length-minus-one field. */ | |
df58fc94 | 11563 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11564 | my_getExpression (&imm_expr, s); |
11565 | check_absolute_expr (ip, &imm_expr); | |
11566 | if ((long) imm_expr.X_add_number < 0 | |
11567 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11568 | { | |
11569 | as_bad (_("Improper size (%lu)"), | |
11570 | (unsigned long) imm_expr.X_add_number); | |
11571 | imm_expr.X_add_number = 0; | |
11572 | } | |
df58fc94 | 11573 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11574 | imm_expr.X_op = O_absent; |
11575 | s = expr_end; | |
11576 | continue; | |
11577 | ||
dd3cbb7e NC |
11578 | case 'Q': |
11579 | /* seqi/snei immediate field. */ | |
df58fc94 | 11580 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11581 | my_getExpression (&imm_expr, s); |
11582 | check_absolute_expr (ip, &imm_expr); | |
11583 | if ((long) imm_expr.X_add_number < -512 | |
11584 | || (long) imm_expr.X_add_number >= 512) | |
11585 | { | |
11586 | as_bad (_("Improper immediate (%ld)"), | |
11587 | (long) imm_expr.X_add_number); | |
11588 | imm_expr.X_add_number = 0; | |
11589 | } | |
df58fc94 | 11590 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11591 | imm_expr.X_op = O_absent; |
11592 | s = expr_end; | |
11593 | continue; | |
11594 | ||
98675402 | 11595 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11596 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11597 | my_getExpression (&imm_expr, s); |
11598 | check_absolute_expr (ip, &imm_expr); | |
11599 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11600 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11601 | if (imm_expr.X_add_number < min_range | |
11602 | || imm_expr.X_add_number > max_range) | |
11603 | { | |
c95354ed | 11604 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11605 | (long) min_range, (long) max_range, |
11606 | (long) imm_expr.X_add_number); | |
11607 | } | |
df58fc94 | 11608 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11609 | imm_expr.X_op = O_absent; |
11610 | s = expr_end; | |
11611 | continue; | |
11612 | ||
11613 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11614 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11615 | my_getExpression (&imm_expr, s); |
11616 | check_absolute_expr (ip, &imm_expr); | |
11617 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11618 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11619 | if (imm_expr.X_add_number < min_range | |
11620 | || imm_expr.X_add_number > max_range) | |
11621 | { | |
c95354ed | 11622 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11623 | (long) min_range, (long) max_range, |
11624 | (long) imm_expr.X_add_number); | |
11625 | } | |
df58fc94 | 11626 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11627 | imm_expr.X_op = O_absent; |
11628 | s = expr_end; | |
11629 | continue; | |
11630 | ||
11631 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11632 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11633 | my_getExpression (&imm_expr, s); |
11634 | check_absolute_expr (ip, &imm_expr); | |
11635 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11636 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11637 | /* We check the offset range before adjusted. */ |
11638 | min_range <<= 4; | |
11639 | max_range <<= 4; | |
98675402 RS |
11640 | if (imm_expr.X_add_number < min_range |
11641 | || imm_expr.X_add_number > max_range) | |
11642 | { | |
c95354ed | 11643 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11644 | (long) min_range, (long) max_range, |
11645 | (long) imm_expr.X_add_number); | |
11646 | } | |
c95354ed MX |
11647 | if (imm_expr.X_add_number & 0xf) |
11648 | { | |
11649 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11650 | (long) imm_expr.X_add_number); | |
11651 | } | |
11652 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11653 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11654 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11655 | imm_expr.X_op = O_absent; |
11656 | s = expr_end; | |
11657 | continue; | |
11658 | ||
11659 | case 'z': | |
df58fc94 | 11660 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11661 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11662 | break; | |
11663 | if (regno == AT && mips_opts.at) | |
11664 | { | |
11665 | if (mips_opts.at == ATREG) | |
11666 | as_warn (_("used $at without \".set noat\"")); | |
11667 | else | |
11668 | as_warn (_("used $%u with \".set at=$%u\""), | |
11669 | regno, mips_opts.at); | |
11670 | } | |
df58fc94 | 11671 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11672 | continue; |
11673 | ||
11674 | case 'Z': | |
df58fc94 | 11675 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11676 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11677 | break; | |
df58fc94 | 11678 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11679 | continue; |
11680 | ||
af7ee8bf | 11681 | default: |
df58fc94 | 11682 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11683 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11684 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11685 | *args, insn->name, insn->args); |
af7ee8bf CD |
11686 | /* Further processing is fruitless. */ |
11687 | return; | |
11688 | } | |
11689 | break; | |
11690 | ||
df58fc94 | 11691 | case '.': /* 10-bit offset. */ |
df58fc94 | 11692 | gas_assert (mips_opts.micromips); |
dec0624d | 11693 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11694 | { |
11695 | int shift = *args == '.' ? 9 : 11; | |
11696 | size_t i; | |
11697 | ||
11698 | /* Check whether there is only a single bracketed expression | |
11699 | left. If so, it must be the base register and the | |
11700 | constant must be zero. */ | |
11701 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11702 | continue; | |
11703 | ||
11704 | /* If this value won't fit into the offset, then go find | |
11705 | a macro that will generate a 16- or 32-bit offset code | |
11706 | pattern. */ | |
11707 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11708 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11709 | || imm_expr.X_add_number >= 1 << shift | |
11710 | || imm_expr.X_add_number < -1 << shift)) | |
11711 | || i > 0) | |
11712 | { | |
11713 | imm_expr.X_op = O_absent; | |
11714 | break; | |
11715 | } | |
11716 | if (shift == 9) | |
11717 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11718 | else | |
dec0624d MR |
11719 | INSERT_OPERAND (mips_opts.micromips, |
11720 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11721 | imm_expr.X_op = O_absent; |
11722 | s = expr_end; | |
11723 | } | |
11724 | continue; | |
11725 | ||
252b5132 RH |
11726 | case '<': /* must be at least one digit */ |
11727 | /* | |
11728 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11729 | * than 31 or less than 0, then the shift amount should be |
11730 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11731 | * We issue a warning and mask out all but the low 5 bits. |
11732 | */ | |
11733 | my_getExpression (&imm_expr, s); | |
11734 | check_absolute_expr (ip, &imm_expr); | |
11735 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11736 | as_warn (_("Improper shift amount (%lu)"), |
11737 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11738 | INSERT_OPERAND (mips_opts.micromips, |
11739 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11740 | imm_expr.X_op = O_absent; |
11741 | s = expr_end; | |
11742 | continue; | |
11743 | ||
11744 | case '>': /* shift amount minus 32 */ | |
11745 | my_getExpression (&imm_expr, s); | |
11746 | check_absolute_expr (ip, &imm_expr); | |
11747 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11748 | || (unsigned long) imm_expr.X_add_number > 63) | |
11749 | break; | |
df58fc94 RS |
11750 | INSERT_OPERAND (mips_opts.micromips, |
11751 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11752 | imm_expr.X_op = O_absent; |
11753 | s = expr_end; | |
11754 | continue; | |
11755 | ||
90ecf173 MR |
11756 | case 'k': /* CACHE code. */ |
11757 | case 'h': /* PREFX code. */ | |
11758 | case '1': /* SYNC type. */ | |
252b5132 RH |
11759 | my_getExpression (&imm_expr, s); |
11760 | check_absolute_expr (ip, &imm_expr); | |
11761 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11762 | as_warn (_("Invalid value for `%s' (%lu)"), |
11763 | ip->insn_mo->name, | |
11764 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11765 | switch (*args) |
d954098f | 11766 | { |
df58fc94 RS |
11767 | case 'k': |
11768 | if (mips_fix_cn63xxp1 | |
11769 | && !mips_opts.micromips | |
11770 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11771 | switch (imm_expr.X_add_number) |
11772 | { | |
11773 | case 5: | |
11774 | case 25: | |
11775 | case 26: | |
11776 | case 27: | |
11777 | case 28: | |
11778 | case 29: | |
11779 | case 30: | |
11780 | case 31: /* These are ok. */ | |
11781 | break; | |
11782 | ||
11783 | default: /* The rest must be changed to 28. */ | |
11784 | imm_expr.X_add_number = 28; | |
11785 | break; | |
11786 | } | |
df58fc94 RS |
11787 | INSERT_OPERAND (mips_opts.micromips, |
11788 | CACHE, *ip, imm_expr.X_add_number); | |
11789 | break; | |
11790 | case 'h': | |
11791 | INSERT_OPERAND (mips_opts.micromips, | |
11792 | PREFX, *ip, imm_expr.X_add_number); | |
11793 | break; | |
11794 | case '1': | |
11795 | INSERT_OPERAND (mips_opts.micromips, | |
11796 | STYPE, *ip, imm_expr.X_add_number); | |
11797 | break; | |
d954098f | 11798 | } |
252b5132 RH |
11799 | imm_expr.X_op = O_absent; |
11800 | s = expr_end; | |
11801 | continue; | |
11802 | ||
90ecf173 | 11803 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11804 | { |
11805 | unsigned long mask = (mips_opts.micromips | |
11806 | ? MICROMIPSOP_MASK_CODE | |
11807 | : OP_MASK_CODE); | |
11808 | ||
11809 | my_getExpression (&imm_expr, s); | |
11810 | check_absolute_expr (ip, &imm_expr); | |
11811 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11812 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11813 | ip->insn_mo->name, | |
11814 | mask, (unsigned long) imm_expr.X_add_number); | |
11815 | INSERT_OPERAND (mips_opts.micromips, | |
11816 | CODE, *ip, imm_expr.X_add_number); | |
11817 | imm_expr.X_op = O_absent; | |
11818 | s = expr_end; | |
11819 | } | |
252b5132 RH |
11820 | continue; |
11821 | ||
90ecf173 | 11822 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11823 | { |
11824 | unsigned long mask = (mips_opts.micromips | |
11825 | ? MICROMIPSOP_MASK_CODE2 | |
11826 | : OP_MASK_CODE2); | |
11827 | ||
11828 | my_getExpression (&imm_expr, s); | |
11829 | check_absolute_expr (ip, &imm_expr); | |
11830 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11831 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11832 | ip->insn_mo->name, | |
11833 | mask, (unsigned long) imm_expr.X_add_number); | |
11834 | INSERT_OPERAND (mips_opts.micromips, | |
11835 | CODE2, *ip, imm_expr.X_add_number); | |
11836 | imm_expr.X_op = O_absent; | |
11837 | s = expr_end; | |
11838 | } | |
252b5132 RH |
11839 | continue; |
11840 | ||
df58fc94 RS |
11841 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11842 | { | |
11843 | unsigned long mask = (mips_opts.micromips | |
11844 | ? MICROMIPSOP_MASK_CODE10 | |
11845 | : OP_MASK_CODE20); | |
11846 | ||
11847 | my_getExpression (&imm_expr, s); | |
11848 | check_absolute_expr (ip, &imm_expr); | |
11849 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11850 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11851 | ip->insn_mo->name, | |
11852 | mask, (unsigned long) imm_expr.X_add_number); | |
11853 | if (mips_opts.micromips) | |
11854 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11855 | else | |
11856 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11857 | imm_expr.X_op = O_absent; | |
11858 | s = expr_end; | |
11859 | } | |
252b5132 RH |
11860 | continue; |
11861 | ||
df58fc94 RS |
11862 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11863 | { | |
11864 | unsigned long mask = (mips_opts.micromips | |
11865 | ? MICROMIPSOP_MASK_COPZ | |
11866 | : OP_MASK_COPZ); | |
11867 | ||
11868 | my_getExpression (&imm_expr, s); | |
11869 | check_absolute_expr (ip, &imm_expr); | |
11870 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11871 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11872 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11873 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11874 | INSERT_OPERAND (mips_opts.micromips, |
11875 | COPZ, *ip, imm_expr.X_add_number); | |
11876 | imm_expr.X_op = O_absent; | |
11877 | s = expr_end; | |
11878 | } | |
beae10d5 | 11879 | continue; |
252b5132 | 11880 | |
df58fc94 RS |
11881 | case 'J': /* 19-bit WAIT code. */ |
11882 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11883 | my_getExpression (&imm_expr, s); |
11884 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11885 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11886 | { |
11887 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11888 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11889 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11890 | } | |
11891 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11892 | imm_expr.X_op = O_absent; |
11893 | s = expr_end; | |
11894 | continue; | |
11895 | ||
707bfff6 | 11896 | case 'P': /* Performance register. */ |
df58fc94 | 11897 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11898 | my_getExpression (&imm_expr, s); |
252b5132 | 11899 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11900 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11901 | as_warn (_("Invalid performance register (%lu)"), |
11902 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
11903 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
11904 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
11905 | as_warn (_("Invalid performance register (%lu)"), | |
11906 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11907 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11908 | imm_expr.X_op = O_absent; |
11909 | s = expr_end; | |
11910 | continue; | |
252b5132 | 11911 | |
707bfff6 | 11912 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11913 | { |
11914 | unsigned long opcode = ip->insn_opcode; | |
11915 | unsigned long mask; | |
11916 | unsigned int types; | |
11917 | int cop0; | |
11918 | ||
11919 | if (mips_opts.micromips) | |
11920 | { | |
11921 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11922 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11923 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11924 | opcode &= mask; | |
11925 | switch (opcode) | |
11926 | { | |
11927 | case 0x000000fc: /* mfc0 */ | |
11928 | case 0x000002fc: /* mtc0 */ | |
11929 | case 0x580000fc: /* dmfc0 */ | |
11930 | case 0x580002fc: /* dmtc0 */ | |
11931 | cop0 = 1; | |
11932 | break; | |
11933 | default: | |
11934 | cop0 = 0; | |
11935 | break; | |
11936 | } | |
11937 | } | |
11938 | else | |
11939 | { | |
11940 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11941 | cop0 = opcode == OP_OP_COP0; | |
11942 | } | |
11943 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11944 | ok = reg_lookup (&s, types, ®no); | |
11945 | if (mips_opts.micromips) | |
11946 | INSERT_OPERAND (1, RS, *ip, regno); | |
11947 | else | |
11948 | INSERT_OPERAND (0, RD, *ip, regno); | |
11949 | if (ok) | |
11950 | { | |
11951 | lastregno = regno; | |
11952 | continue; | |
11953 | } | |
11954 | } | |
11955 | break; | |
707bfff6 | 11956 | |
df58fc94 RS |
11957 | case 'y': /* ALNV.PS source register. */ |
11958 | gas_assert (mips_opts.micromips); | |
11959 | goto do_reg; | |
11960 | case 'x': /* Ignore register name. */ | |
11961 | case 'U': /* Destination register (CLO/CLZ). */ | |
11962 | case 'g': /* Coprocessor destination register. */ | |
11963 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11964 | case 'b': /* Base register. */ |
11965 | case 'd': /* Destination register. */ | |
11966 | case 's': /* Source register. */ | |
11967 | case 't': /* Target register. */ | |
11968 | case 'r': /* Both target and source. */ | |
11969 | case 'v': /* Both dest and source. */ | |
11970 | case 'w': /* Both dest and target. */ | |
11971 | case 'E': /* Coprocessor target register. */ | |
11972 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11973 | case 'z': /* Must be zero register. */ |
df58fc94 | 11974 | do_reg: |
90ecf173 | 11975 | s_reset = s; |
707bfff6 TS |
11976 | if (*args == 'E' || *args == 'K') |
11977 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11978 | else | |
11979 | { | |
11980 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11981 | if (regno == AT && mips_opts.at) |
11982 | { | |
11983 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11984 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11985 | else |
f71d0d44 | 11986 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11987 | regno, mips_opts.at); |
11988 | } | |
707bfff6 TS |
11989 | } |
11990 | if (ok) | |
252b5132 | 11991 | { |
252b5132 RH |
11992 | c = *args; |
11993 | if (*s == ' ') | |
f9419b05 | 11994 | ++s; |
252b5132 RH |
11995 | if (args[1] != *s) |
11996 | { | |
11997 | if (c == 'r' || c == 'v' || c == 'w') | |
11998 | { | |
11999 | regno = lastregno; | |
12000 | s = s_reset; | |
f9419b05 | 12001 | ++args; |
252b5132 RH |
12002 | } |
12003 | } | |
12004 | /* 'z' only matches $0. */ | |
12005 | if (c == 'z' && regno != 0) | |
12006 | break; | |
12007 | ||
24864476 | 12008 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12009 | { |
12010 | if (regno == lastregno) | |
90ecf173 MR |
12011 | { |
12012 | insn_error | |
f71d0d44 | 12013 | = _("Source and destination must be different"); |
e7c604dd | 12014 | continue; |
90ecf173 | 12015 | } |
24864476 | 12016 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12017 | { |
12018 | insn_error | |
f71d0d44 | 12019 | = _("A destination register must be supplied"); |
e7c604dd | 12020 | continue; |
90ecf173 | 12021 | } |
e7c604dd | 12022 | } |
90ecf173 MR |
12023 | /* Now that we have assembled one operand, we use the args |
12024 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12025 | switch (c) |
12026 | { | |
12027 | case 'r': | |
12028 | case 's': | |
12029 | case 'v': | |
12030 | case 'b': | |
df58fc94 | 12031 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12032 | break; |
df58fc94 | 12033 | |
af7ee8bf | 12034 | case 'K': |
df58fc94 RS |
12035 | if (mips_opts.micromips) |
12036 | INSERT_OPERAND (1, RS, *ip, regno); | |
12037 | else | |
12038 | INSERT_OPERAND (0, RD, *ip, regno); | |
12039 | break; | |
12040 | ||
12041 | case 'd': | |
ef2e4d86 | 12042 | case 'g': |
df58fc94 | 12043 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12044 | break; |
df58fc94 | 12045 | |
4372b673 | 12046 | case 'U': |
df58fc94 RS |
12047 | gas_assert (!mips_opts.micromips); |
12048 | INSERT_OPERAND (0, RD, *ip, regno); | |
12049 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12050 | break; |
df58fc94 | 12051 | |
252b5132 RH |
12052 | case 'w': |
12053 | case 't': | |
12054 | case 'E': | |
df58fc94 RS |
12055 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12056 | break; | |
12057 | ||
12058 | case 'y': | |
12059 | gas_assert (mips_opts.micromips); | |
12060 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12061 | break; |
df58fc94 | 12062 | |
252b5132 RH |
12063 | case 'x': |
12064 | /* This case exists because on the r3000 trunc | |
12065 | expands into a macro which requires a gp | |
12066 | register. On the r6000 or r4000 it is | |
12067 | assembled into a single instruction which | |
12068 | ignores the register. Thus the insn version | |
12069 | is MIPS_ISA2 and uses 'x', and the macro | |
12070 | version is MIPS_ISA1 and uses 't'. */ | |
12071 | break; | |
df58fc94 | 12072 | |
252b5132 RH |
12073 | case 'z': |
12074 | /* This case is for the div instruction, which | |
12075 | acts differently if the destination argument | |
12076 | is $0. This only matches $0, and is checked | |
12077 | outside the switch. */ | |
12078 | break; | |
252b5132 RH |
12079 | } |
12080 | lastregno = regno; | |
12081 | continue; | |
12082 | } | |
252b5132 RH |
12083 | switch (*args++) |
12084 | { | |
12085 | case 'r': | |
12086 | case 'v': | |
df58fc94 | 12087 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12088 | continue; |
df58fc94 | 12089 | |
252b5132 | 12090 | case 'w': |
df58fc94 | 12091 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12092 | continue; |
12093 | } | |
12094 | break; | |
12095 | ||
deec1734 | 12096 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12097 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12098 | my_getExpression (&imm_expr, s); |
12099 | check_absolute_expr (ip, &imm_expr); | |
12100 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12101 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12102 | (long) imm_expr.X_add_number); |
df58fc94 | 12103 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12104 | imm_expr.X_op = O_absent; |
12105 | s = expr_end; | |
12106 | continue; | |
12107 | ||
12108 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12109 | if (s[0] != '$') | |
12110 | { | |
12111 | /* MDMX Immediate. */ | |
df58fc94 | 12112 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12113 | my_getExpression (&imm_expr, s); |
12114 | check_absolute_expr (ip, &imm_expr); | |
12115 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12116 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12117 | (long) imm_expr.X_add_number); | |
df58fc94 | 12118 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12119 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12120 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12121 | else | |
12122 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12123 | imm_expr.X_op = O_absent; |
12124 | s = expr_end; | |
12125 | continue; | |
12126 | } | |
12127 | /* Not MDMX Immediate. Fall through. */ | |
12128 | case 'X': /* MDMX destination register. */ | |
12129 | case 'Y': /* MDMX source register. */ | |
12130 | case 'Z': /* MDMX target register. */ | |
12131 | is_mdmx = 1; | |
df58fc94 RS |
12132 | case 'W': |
12133 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12134 | case 'D': /* Floating point destination register. */ |
12135 | case 'S': /* Floating point source register. */ | |
12136 | case 'T': /* Floating point target register. */ | |
12137 | case 'R': /* Floating point source register. */ | |
252b5132 | 12138 | case 'V': |
707bfff6 TS |
12139 | rtype = RTYPE_FPU; |
12140 | if (is_mdmx | |
12141 | || (mips_opts.ase_mdmx | |
12142 | && (ip->insn_mo->pinfo & FP_D) | |
12143 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12144 | | INSN_COPROC_MEMORY_DELAY | |
12145 | | INSN_LOAD_COPROC_DELAY | |
12146 | | INSN_LOAD_MEMORY_DELAY | |
12147 | | INSN_STORE_MEMORY)))) | |
12148 | rtype |= RTYPE_VEC; | |
252b5132 | 12149 | s_reset = s; |
707bfff6 | 12150 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12151 | { |
252b5132 | 12152 | if ((regno & 1) != 0 |
ca4e0257 | 12153 | && HAVE_32BIT_FPRS |
90ecf173 | 12154 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12155 | as_warn (_("Float register should be even, was %d"), |
12156 | regno); | |
12157 | ||
12158 | c = *args; | |
12159 | if (*s == ' ') | |
f9419b05 | 12160 | ++s; |
252b5132 RH |
12161 | if (args[1] != *s) |
12162 | { | |
12163 | if (c == 'V' || c == 'W') | |
12164 | { | |
12165 | regno = lastregno; | |
12166 | s = s_reset; | |
f9419b05 | 12167 | ++args; |
252b5132 RH |
12168 | } |
12169 | } | |
12170 | switch (c) | |
12171 | { | |
12172 | case 'D': | |
deec1734 | 12173 | case 'X': |
df58fc94 | 12174 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12175 | break; |
df58fc94 | 12176 | |
252b5132 RH |
12177 | case 'V': |
12178 | case 'S': | |
deec1734 | 12179 | case 'Y': |
df58fc94 | 12180 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12181 | break; |
df58fc94 | 12182 | |
deec1734 CD |
12183 | case 'Q': |
12184 | /* This is like 'Z', but also needs to fix the MDMX | |
12185 | vector/scalar select bits. Note that the | |
12186 | scalar immediate case is handled above. */ | |
12187 | if (*s == '[') | |
12188 | { | |
12189 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12190 | int max_el = (is_qh ? 3 : 7); | |
12191 | s++; | |
12192 | my_getExpression(&imm_expr, s); | |
12193 | check_absolute_expr (ip, &imm_expr); | |
12194 | s = expr_end; | |
12195 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12196 | as_bad (_("Bad element selector %ld"), |
12197 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12198 | imm_expr.X_add_number &= max_el; |
12199 | ip->insn_opcode |= (imm_expr.X_add_number | |
12200 | << (OP_SH_VSEL + | |
12201 | (is_qh ? 2 : 1))); | |
01a3f561 | 12202 | imm_expr.X_op = O_absent; |
deec1734 | 12203 | if (*s != ']') |
20203fb9 | 12204 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12205 | else |
12206 | s++; | |
12207 | } | |
12208 | else | |
12209 | { | |
12210 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12211 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12212 | << OP_SH_VSEL); | |
12213 | else | |
12214 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12215 | OP_SH_VSEL); | |
12216 | } | |
90ecf173 | 12217 | /* Fall through. */ |
252b5132 RH |
12218 | case 'W': |
12219 | case 'T': | |
deec1734 | 12220 | case 'Z': |
df58fc94 | 12221 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12222 | break; |
df58fc94 | 12223 | |
252b5132 | 12224 | case 'R': |
df58fc94 | 12225 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12226 | break; |
12227 | } | |
12228 | lastregno = regno; | |
12229 | continue; | |
12230 | } | |
12231 | ||
252b5132 RH |
12232 | switch (*args++) |
12233 | { | |
12234 | case 'V': | |
df58fc94 | 12235 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12236 | continue; |
df58fc94 | 12237 | |
252b5132 | 12238 | case 'W': |
df58fc94 | 12239 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12240 | continue; |
12241 | } | |
12242 | break; | |
12243 | ||
12244 | case 'I': | |
12245 | my_getExpression (&imm_expr, s); | |
12246 | if (imm_expr.X_op != O_big | |
12247 | && imm_expr.X_op != O_constant) | |
12248 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12249 | if (HAVE_32BIT_GPRS) |
12250 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12251 | s = expr_end; |
12252 | continue; | |
12253 | ||
12254 | case 'A': | |
12255 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12256 | normalize_address_expr (&offset_expr); |
f6688943 | 12257 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12258 | s = expr_end; |
12259 | continue; | |
12260 | ||
12261 | case 'F': | |
12262 | case 'L': | |
12263 | case 'f': | |
12264 | case 'l': | |
12265 | { | |
12266 | int f64; | |
ca4e0257 | 12267 | int using_gprs; |
252b5132 RH |
12268 | char *save_in; |
12269 | char *err; | |
12270 | unsigned char temp[8]; | |
12271 | int len; | |
12272 | unsigned int length; | |
12273 | segT seg; | |
12274 | subsegT subseg; | |
12275 | char *p; | |
12276 | ||
12277 | /* These only appear as the last operand in an | |
12278 | instruction, and every instruction that accepts | |
12279 | them in any variant accepts them in all variants. | |
12280 | This means we don't have to worry about backing out | |
12281 | any changes if the instruction does not match. | |
12282 | ||
12283 | The difference between them is the size of the | |
12284 | floating point constant and where it goes. For 'F' | |
12285 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12286 | is 32 bits. Where the constant is placed is based | |
12287 | on how the MIPS assembler does things: | |
12288 | F -- .rdata | |
12289 | L -- .lit8 | |
12290 | f -- immediate value | |
12291 | l -- .lit4 | |
12292 | ||
12293 | The .lit4 and .lit8 sections are only used if | |
12294 | permitted by the -G argument. | |
12295 | ||
ca4e0257 RS |
12296 | The code below needs to know whether the target register |
12297 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12298 | 'F' are used with GPR-based instructions and 'l' and | |
12299 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12300 | |
12301 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12302 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12303 | |
12304 | save_in = input_line_pointer; | |
12305 | input_line_pointer = s; | |
12306 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12307 | length = len; | |
12308 | s = input_line_pointer; | |
12309 | input_line_pointer = save_in; | |
12310 | if (err != NULL && *err != '\0') | |
12311 | { | |
12312 | as_bad (_("Bad floating point constant: %s"), err); | |
12313 | memset (temp, '\0', sizeof temp); | |
12314 | length = f64 ? 8 : 4; | |
12315 | } | |
12316 | ||
9c2799c2 | 12317 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12318 | |
12319 | if (*args == 'f' | |
12320 | || (*args == 'l' | |
3e722fb5 | 12321 | && (g_switch_value < 4 |
252b5132 RH |
12322 | || (temp[0] == 0 && temp[1] == 0) |
12323 | || (temp[2] == 0 && temp[3] == 0)))) | |
12324 | { | |
12325 | imm_expr.X_op = O_constant; | |
90ecf173 | 12326 | if (!target_big_endian) |
252b5132 RH |
12327 | imm_expr.X_add_number = bfd_getl32 (temp); |
12328 | else | |
12329 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12330 | } | |
12331 | else if (length > 4 | |
90ecf173 | 12332 | && !mips_disable_float_construction |
ca4e0257 RS |
12333 | /* Constants can only be constructed in GPRs and |
12334 | copied to FPRs if the GPRs are at least as wide | |
12335 | as the FPRs. Force the constant into memory if | |
12336 | we are using 64-bit FPRs but the GPRs are only | |
12337 | 32 bits wide. */ | |
12338 | && (using_gprs | |
90ecf173 | 12339 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12340 | && ((temp[0] == 0 && temp[1] == 0) |
12341 | || (temp[2] == 0 && temp[3] == 0)) | |
12342 | && ((temp[4] == 0 && temp[5] == 0) | |
12343 | || (temp[6] == 0 && temp[7] == 0))) | |
12344 | { | |
ca4e0257 | 12345 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12346 | instructions. If using 32-bit registers, set |
12347 | imm_expr to the high order 32 bits and offset_expr to | |
12348 | the low order 32 bits. Otherwise, set imm_expr to | |
12349 | the entire 64 bit constant. */ | |
ca4e0257 | 12350 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12351 | { |
12352 | imm_expr.X_op = O_constant; | |
12353 | offset_expr.X_op = O_constant; | |
90ecf173 | 12354 | if (!target_big_endian) |
252b5132 RH |
12355 | { |
12356 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12357 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12358 | } | |
12359 | else | |
12360 | { | |
12361 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12362 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12363 | } | |
12364 | if (offset_expr.X_add_number == 0) | |
12365 | offset_expr.X_op = O_absent; | |
12366 | } | |
12367 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12368 | { | |
12369 | imm_expr.X_op = O_constant; | |
90ecf173 | 12370 | if (!target_big_endian) |
252b5132 RH |
12371 | imm_expr.X_add_number = bfd_getl64 (temp); |
12372 | else | |
12373 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12374 | } | |
12375 | else | |
12376 | { | |
12377 | imm_expr.X_op = O_big; | |
12378 | imm_expr.X_add_number = 4; | |
90ecf173 | 12379 | if (!target_big_endian) |
252b5132 RH |
12380 | { |
12381 | generic_bignum[0] = bfd_getl16 (temp); | |
12382 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12383 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12384 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12385 | } | |
12386 | else | |
12387 | { | |
12388 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12389 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12390 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12391 | generic_bignum[3] = bfd_getb16 (temp); | |
12392 | } | |
12393 | } | |
12394 | } | |
12395 | else | |
12396 | { | |
12397 | const char *newname; | |
12398 | segT new_seg; | |
12399 | ||
12400 | /* Switch to the right section. */ | |
12401 | seg = now_seg; | |
12402 | subseg = now_subseg; | |
12403 | switch (*args) | |
12404 | { | |
12405 | default: /* unused default case avoids warnings. */ | |
12406 | case 'L': | |
12407 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12408 | if (g_switch_value >= 8) |
252b5132 RH |
12409 | newname = ".lit8"; |
12410 | break; | |
12411 | case 'F': | |
3e722fb5 | 12412 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12413 | break; |
12414 | case 'l': | |
9c2799c2 | 12415 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12416 | newname = ".lit4"; |
12417 | break; | |
12418 | } | |
12419 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12420 | if (IS_ELF) |
252b5132 RH |
12421 | bfd_set_section_flags (stdoutput, new_seg, |
12422 | (SEC_ALLOC | |
12423 | | SEC_LOAD | |
12424 | | SEC_READONLY | |
12425 | | SEC_DATA)); | |
12426 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12427 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12428 | record_alignment (new_seg, 4); |
12429 | else | |
12430 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12431 | if (seg == now_seg) | |
12432 | as_bad (_("Can't use floating point insn in this section")); | |
12433 | ||
df58fc94 RS |
12434 | /* Set the argument to the current address in the |
12435 | section. */ | |
12436 | offset_expr.X_op = O_symbol; | |
12437 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12438 | offset_expr.X_add_number = 0; | |
12439 | ||
12440 | /* Put the floating point number into the section. */ | |
12441 | p = frag_more ((int) length); | |
12442 | memcpy (p, temp, length); | |
12443 | ||
12444 | /* Switch back to the original section. */ | |
12445 | subseg_set (seg, subseg); | |
12446 | } | |
12447 | } | |
12448 | continue; | |
12449 | ||
12450 | case 'i': /* 16-bit unsigned immediate. */ | |
12451 | case 'j': /* 16-bit signed immediate. */ | |
12452 | *imm_reloc = BFD_RELOC_LO16; | |
12453 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12454 | { | |
12455 | int more; | |
12456 | offsetT minval, maxval; | |
12457 | ||
12458 | more = (insn + 1 < past | |
12459 | && strcmp (insn->name, insn[1].name) == 0); | |
12460 | ||
12461 | /* If the expression was written as an unsigned number, | |
12462 | only treat it as signed if there are no more | |
12463 | alternatives. */ | |
12464 | if (more | |
12465 | && *args == 'j' | |
12466 | && sizeof (imm_expr.X_add_number) <= 4 | |
12467 | && imm_expr.X_op == O_constant | |
12468 | && imm_expr.X_add_number < 0 | |
12469 | && imm_expr.X_unsigned | |
12470 | && HAVE_64BIT_GPRS) | |
12471 | break; | |
12472 | ||
12473 | /* For compatibility with older assemblers, we accept | |
12474 | 0x8000-0xffff as signed 16-bit numbers when only | |
12475 | signed numbers are allowed. */ | |
12476 | if (*args == 'i') | |
12477 | minval = 0, maxval = 0xffff; | |
12478 | else if (more) | |
12479 | minval = -0x8000, maxval = 0x7fff; | |
12480 | else | |
12481 | minval = -0x8000, maxval = 0xffff; | |
12482 | ||
12483 | if (imm_expr.X_op != O_constant | |
12484 | || imm_expr.X_add_number < minval | |
12485 | || imm_expr.X_add_number > maxval) | |
12486 | { | |
12487 | if (more) | |
12488 | break; | |
12489 | if (imm_expr.X_op == O_constant | |
12490 | || imm_expr.X_op == O_big) | |
12491 | as_bad (_("Expression out of range")); | |
12492 | } | |
12493 | } | |
12494 | s = expr_end; | |
12495 | continue; | |
12496 | ||
12497 | case 'o': /* 16-bit offset. */ | |
12498 | offset_reloc[0] = BFD_RELOC_LO16; | |
12499 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12500 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12501 | ||
12502 | /* Check whether there is only a single bracketed expression | |
12503 | left. If so, it must be the base register and the | |
12504 | constant must be zero. */ | |
12505 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12506 | { | |
12507 | offset_expr.X_op = O_constant; | |
12508 | offset_expr.X_add_number = 0; | |
12509 | continue; | |
12510 | } | |
12511 | ||
12512 | /* If this value won't fit into a 16 bit offset, then go | |
12513 | find a macro that will generate the 32 bit offset | |
12514 | code pattern. */ | |
12515 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12516 | && (offset_expr.X_op != O_constant | |
12517 | || offset_expr.X_add_number >= 0x8000 | |
12518 | || offset_expr.X_add_number < -0x8000)) | |
12519 | break; | |
12520 | ||
12521 | s = expr_end; | |
12522 | continue; | |
12523 | ||
12524 | case 'p': /* PC-relative offset. */ | |
12525 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12526 | my_getExpression (&offset_expr, s); | |
12527 | s = expr_end; | |
12528 | continue; | |
12529 | ||
12530 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12531 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12532 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12533 | && imm_expr.X_op == O_constant | |
12534 | && (imm_expr.X_add_number < 0 | |
12535 | || imm_expr.X_add_number >= 0x10000)) | |
12536 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12537 | (unsigned long) imm_expr.X_add_number); | |
12538 | s = expr_end; | |
12539 | continue; | |
12540 | ||
12541 | case 'a': /* 26-bit address. */ | |
12542 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12543 | my_getExpression (&offset_expr, s); | |
12544 | s = expr_end; | |
12545 | continue; | |
12546 | ||
12547 | case 'N': /* 3-bit branch condition code. */ | |
12548 | case 'M': /* 3-bit compare condition code. */ | |
12549 | rtype = RTYPE_CCC; | |
12550 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12551 | rtype |= RTYPE_FCC; | |
12552 | if (!reg_lookup (&s, rtype, ®no)) | |
12553 | break; | |
12554 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12555 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12556 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12557 | && (regno & 1) != 0) | |
12558 | as_warn (_("Condition code register should be even for %s, " | |
12559 | "was %d"), | |
12560 | str, regno); | |
12561 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12562 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12563 | && (regno & 3) != 0) | |
12564 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12565 | "was %d"), | |
12566 | str, regno); | |
12567 | if (*args == 'N') | |
12568 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12569 | else | |
12570 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12571 | continue; | |
12572 | ||
12573 | case 'H': | |
12574 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12575 | s += 2; | |
12576 | if (ISDIGIT (*s)) | |
12577 | { | |
12578 | c = 0; | |
12579 | do | |
12580 | { | |
12581 | c *= 10; | |
12582 | c += *s - '0'; | |
12583 | ++s; | |
12584 | } | |
12585 | while (ISDIGIT (*s)); | |
12586 | } | |
12587 | else | |
12588 | c = 8; /* Invalid sel value. */ | |
12589 | ||
12590 | if (c > 7) | |
12591 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12592 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12593 | continue; | |
12594 | ||
12595 | case 'e': | |
12596 | gas_assert (!mips_opts.micromips); | |
12597 | /* Must be at least one digit. */ | |
12598 | my_getExpression (&imm_expr, s); | |
12599 | check_absolute_expr (ip, &imm_expr); | |
12600 | ||
12601 | if ((unsigned long) imm_expr.X_add_number | |
12602 | > (unsigned long) OP_MASK_VECBYTE) | |
12603 | { | |
12604 | as_bad (_("bad byte vector index (%ld)"), | |
12605 | (long) imm_expr.X_add_number); | |
12606 | imm_expr.X_add_number = 0; | |
12607 | } | |
12608 | ||
12609 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12610 | imm_expr.X_op = O_absent; | |
12611 | s = expr_end; | |
12612 | continue; | |
12613 | ||
12614 | case '%': | |
12615 | gas_assert (!mips_opts.micromips); | |
12616 | my_getExpression (&imm_expr, s); | |
12617 | check_absolute_expr (ip, &imm_expr); | |
12618 | ||
12619 | if ((unsigned long) imm_expr.X_add_number | |
12620 | > (unsigned long) OP_MASK_VECALIGN) | |
12621 | { | |
12622 | as_bad (_("bad byte vector index (%ld)"), | |
12623 | (long) imm_expr.X_add_number); | |
12624 | imm_expr.X_add_number = 0; | |
12625 | } | |
12626 | ||
12627 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12628 | imm_expr.X_op = O_absent; | |
12629 | s = expr_end; | |
12630 | continue; | |
12631 | ||
12632 | case 'm': /* Opcode extension character. */ | |
12633 | gas_assert (mips_opts.micromips); | |
12634 | c = *++args; | |
12635 | switch (c) | |
12636 | { | |
12637 | case 'r': | |
12638 | if (strncmp (s, "$pc", 3) == 0) | |
12639 | { | |
12640 | s += 3; | |
12641 | continue; | |
12642 | } | |
12643 | break; | |
12644 | ||
12645 | case 'a': | |
12646 | case 'b': | |
12647 | case 'c': | |
12648 | case 'd': | |
12649 | case 'e': | |
12650 | case 'f': | |
12651 | case 'g': | |
12652 | case 'h': | |
12653 | case 'i': | |
12654 | case 'j': | |
12655 | case 'l': | |
12656 | case 'm': | |
12657 | case 'n': | |
12658 | case 'p': | |
12659 | case 'q': | |
12660 | case 's': | |
12661 | case 't': | |
12662 | case 'x': | |
12663 | case 'y': | |
12664 | case 'z': | |
12665 | s_reset = s; | |
12666 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12667 | if (regno == AT && mips_opts.at) | |
12668 | { | |
12669 | if (mips_opts.at == ATREG) | |
12670 | as_warn (_("Used $at without \".set noat\"")); | |
12671 | else | |
12672 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12673 | regno, mips_opts.at); | |
12674 | } | |
12675 | if (!ok) | |
12676 | { | |
12677 | if (c == 'c') | |
12678 | { | |
12679 | gas_assert (args[1] == ','); | |
12680 | regno = lastregno; | |
12681 | ++args; | |
12682 | } | |
12683 | else if (c == 't') | |
12684 | { | |
12685 | gas_assert (args[1] == ','); | |
12686 | ++args; | |
12687 | continue; /* Nothing to do. */ | |
12688 | } | |
12689 | else | |
12690 | break; | |
12691 | } | |
12692 | ||
12693 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12694 | { | |
12695 | if (regno == lastregno) | |
12696 | { | |
12697 | insn_error | |
12698 | = _("Source and destination must be different"); | |
12699 | continue; | |
12700 | } | |
12701 | if (regno == 31 && lastregno == 0xffffffff) | |
12702 | { | |
12703 | insn_error | |
12704 | = _("A destination register must be supplied"); | |
12705 | continue; | |
12706 | } | |
12707 | } | |
12708 | ||
12709 | if (*s == ' ') | |
12710 | ++s; | |
12711 | if (args[1] != *s) | |
12712 | { | |
12713 | if (c == 'e') | |
12714 | { | |
12715 | gas_assert (args[1] == ','); | |
12716 | regno = lastregno; | |
12717 | s = s_reset; | |
12718 | ++args; | |
12719 | } | |
12720 | else if (c == 't') | |
12721 | { | |
12722 | gas_assert (args[1] == ','); | |
12723 | s = s_reset; | |
12724 | ++args; | |
12725 | continue; /* Nothing to do. */ | |
12726 | } | |
12727 | } | |
12728 | ||
12729 | /* Make sure regno is the same as lastregno. */ | |
12730 | if (c == 't' && regno != lastregno) | |
12731 | break; | |
12732 | ||
12733 | /* Make sure regno is the same as destregno. */ | |
12734 | if (c == 'x' && regno != destregno) | |
12735 | break; | |
12736 | ||
12737 | /* We need to save regno, before regno maps to the | |
12738 | microMIPS register encoding. */ | |
12739 | lastregno = regno; | |
12740 | ||
12741 | if (c == 'f') | |
12742 | destregno = regno; | |
12743 | ||
12744 | switch (c) | |
12745 | { | |
12746 | case 'a': | |
12747 | if (regno != GP) | |
12748 | regno = ILLEGAL_REG; | |
12749 | break; | |
12750 | ||
12751 | case 'b': | |
12752 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12753 | break; | |
12754 | ||
12755 | case 'c': | |
12756 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12757 | break; | |
12758 | ||
12759 | case 'd': | |
12760 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12761 | break; | |
12762 | ||
12763 | case 'e': | |
12764 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12765 | break; | |
12766 | ||
12767 | case 'f': | |
12768 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12769 | break; | |
12770 | ||
12771 | case 'g': | |
12772 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12773 | break; | |
12774 | ||
12775 | case 'h': | |
12776 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12777 | break; | |
12778 | ||
12779 | case 'i': | |
12780 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12781 | { | |
12782 | case 4: | |
12783 | if (regno == 21) | |
12784 | regno = 3; | |
12785 | else if (regno == 22) | |
12786 | regno = 4; | |
12787 | else if (regno == 5) | |
12788 | regno = 5; | |
12789 | else if (regno == 6) | |
12790 | regno = 6; | |
12791 | else if (regno == 7) | |
12792 | regno = 7; | |
12793 | else | |
12794 | regno = ILLEGAL_REG; | |
12795 | break; | |
12796 | ||
12797 | case 5: | |
12798 | if (regno == 6) | |
12799 | regno = 0; | |
12800 | else if (regno == 7) | |
12801 | regno = 1; | |
12802 | else | |
12803 | regno = ILLEGAL_REG; | |
12804 | break; | |
12805 | ||
12806 | case 6: | |
12807 | if (regno == 7) | |
12808 | regno = 2; | |
12809 | else | |
12810 | regno = ILLEGAL_REG; | |
12811 | break; | |
12812 | ||
12813 | default: | |
12814 | regno = ILLEGAL_REG; | |
12815 | break; | |
12816 | } | |
12817 | break; | |
12818 | ||
12819 | case 'l': | |
12820 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12821 | break; | |
12822 | ||
12823 | case 'm': | |
12824 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12825 | break; | |
12826 | ||
12827 | case 'n': | |
12828 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12829 | break; | |
12830 | ||
12831 | case 'q': | |
12832 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12833 | break; | |
12834 | ||
12835 | case 's': | |
12836 | if (regno != SP) | |
12837 | regno = ILLEGAL_REG; | |
12838 | break; | |
12839 | ||
12840 | case 'y': | |
12841 | if (regno != 31) | |
12842 | regno = ILLEGAL_REG; | |
12843 | break; | |
12844 | ||
12845 | case 'z': | |
12846 | if (regno != ZERO) | |
12847 | regno = ILLEGAL_REG; | |
12848 | break; | |
12849 | ||
12850 | case 'j': /* Do nothing. */ | |
12851 | case 'p': | |
12852 | case 't': | |
12853 | case 'x': | |
12854 | break; | |
12855 | ||
12856 | default: | |
b37df7c4 | 12857 | abort (); |
df58fc94 RS |
12858 | } |
12859 | ||
12860 | if (regno == ILLEGAL_REG) | |
12861 | break; | |
12862 | ||
12863 | switch (c) | |
12864 | { | |
12865 | case 'b': | |
12866 | INSERT_OPERAND (1, MB, *ip, regno); | |
12867 | break; | |
12868 | ||
12869 | case 'c': | |
12870 | INSERT_OPERAND (1, MC, *ip, regno); | |
12871 | break; | |
12872 | ||
12873 | case 'd': | |
12874 | INSERT_OPERAND (1, MD, *ip, regno); | |
12875 | break; | |
12876 | ||
12877 | case 'e': | |
12878 | INSERT_OPERAND (1, ME, *ip, regno); | |
12879 | break; | |
12880 | ||
12881 | case 'f': | |
12882 | INSERT_OPERAND (1, MF, *ip, regno); | |
12883 | break; | |
12884 | ||
12885 | case 'g': | |
12886 | INSERT_OPERAND (1, MG, *ip, regno); | |
12887 | break; | |
12888 | ||
12889 | case 'h': | |
12890 | INSERT_OPERAND (1, MH, *ip, regno); | |
12891 | break; | |
12892 | ||
12893 | case 'i': | |
12894 | INSERT_OPERAND (1, MI, *ip, regno); | |
12895 | break; | |
12896 | ||
12897 | case 'j': | |
12898 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12899 | break; | |
12900 | ||
12901 | case 'l': | |
12902 | INSERT_OPERAND (1, ML, *ip, regno); | |
12903 | break; | |
12904 | ||
12905 | case 'm': | |
12906 | INSERT_OPERAND (1, MM, *ip, regno); | |
12907 | break; | |
12908 | ||
12909 | case 'n': | |
12910 | INSERT_OPERAND (1, MN, *ip, regno); | |
12911 | break; | |
12912 | ||
12913 | case 'p': | |
12914 | INSERT_OPERAND (1, MP, *ip, regno); | |
12915 | break; | |
12916 | ||
12917 | case 'q': | |
12918 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12919 | break; | |
12920 | ||
12921 | case 'a': /* Do nothing. */ | |
12922 | case 's': /* Do nothing. */ | |
12923 | case 't': /* Do nothing. */ | |
12924 | case 'x': /* Do nothing. */ | |
12925 | case 'y': /* Do nothing. */ | |
12926 | case 'z': /* Do nothing. */ | |
12927 | break; | |
12928 | ||
12929 | default: | |
b37df7c4 | 12930 | abort (); |
df58fc94 RS |
12931 | } |
12932 | continue; | |
12933 | ||
12934 | case 'A': | |
12935 | { | |
12936 | bfd_reloc_code_real_type r[3]; | |
12937 | expressionS ep; | |
12938 | int imm; | |
12939 | ||
12940 | /* Check whether there is only a single bracketed | |
12941 | expression left. If so, it must be the base register | |
12942 | and the constant must be zero. */ | |
12943 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12944 | { | |
12945 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12946 | continue; | |
12947 | } | |
12948 | ||
12949 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12950 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12951 | break; | |
12952 | ||
12953 | imm = ep.X_add_number >> 2; | |
12954 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12955 | } | |
12956 | s = expr_end; | |
12957 | continue; | |
12958 | ||
12959 | case 'B': | |
12960 | { | |
12961 | bfd_reloc_code_real_type r[3]; | |
12962 | expressionS ep; | |
12963 | int imm; | |
12964 | ||
12965 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12966 | || ep.X_op != O_constant) | |
12967 | break; | |
12968 | ||
12969 | for (imm = 0; imm < 8; imm++) | |
12970 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12971 | break; | |
12972 | if (imm >= 8) | |
12973 | break; | |
12974 | ||
12975 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12976 | } | |
12977 | s = expr_end; | |
12978 | continue; | |
12979 | ||
12980 | case 'C': | |
12981 | { | |
12982 | bfd_reloc_code_real_type r[3]; | |
12983 | expressionS ep; | |
12984 | int imm; | |
12985 | ||
12986 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12987 | || ep.X_op != O_constant) | |
12988 | break; | |
12989 | ||
12990 | for (imm = 0; imm < 16; imm++) | |
12991 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12992 | break; | |
12993 | if (imm >= 16) | |
12994 | break; | |
12995 | ||
12996 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12997 | } | |
12998 | s = expr_end; | |
12999 | continue; | |
13000 | ||
13001 | case 'D': /* pc relative offset */ | |
13002 | case 'E': /* pc relative offset */ | |
13003 | my_getExpression (&offset_expr, s); | |
13004 | if (offset_expr.X_op == O_register) | |
13005 | break; | |
13006 | ||
40209cad MR |
13007 | if (!forced_insn_length) |
13008 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13009 | else if (c == 'D') | |
13010 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13011 | else | |
13012 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13013 | s = expr_end; |
13014 | continue; | |
13015 | ||
13016 | case 'F': | |
13017 | { | |
13018 | bfd_reloc_code_real_type r[3]; | |
13019 | expressionS ep; | |
13020 | int imm; | |
13021 | ||
13022 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13023 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13024 | break; | |
13025 | ||
13026 | imm = ep.X_add_number; | |
13027 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13028 | } | |
13029 | s = expr_end; | |
13030 | continue; | |
13031 | ||
13032 | case 'G': | |
13033 | { | |
13034 | bfd_reloc_code_real_type r[3]; | |
13035 | expressionS ep; | |
13036 | int imm; | |
13037 | ||
13038 | /* Check whether there is only a single bracketed | |
13039 | expression left. If so, it must be the base register | |
13040 | and the constant must be zero. */ | |
13041 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13042 | { | |
13043 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13044 | continue; | |
13045 | } | |
13046 | ||
13047 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13048 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13049 | break; | |
13050 | ||
13051 | imm = ep.X_add_number & 15; | |
13052 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13053 | } | |
13054 | s = expr_end; | |
13055 | continue; | |
13056 | ||
13057 | case 'H': | |
13058 | { | |
13059 | bfd_reloc_code_real_type r[3]; | |
13060 | expressionS ep; | |
13061 | int imm; | |
13062 | ||
13063 | /* Check whether there is only a single bracketed | |
13064 | expression left. If so, it must be the base register | |
13065 | and the constant must be zero. */ | |
13066 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13067 | { | |
13068 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13069 | continue; | |
13070 | } | |
13071 | ||
13072 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13073 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13074 | break; | |
13075 | ||
13076 | imm = ep.X_add_number >> 1; | |
13077 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13078 | } | |
13079 | s = expr_end; | |
13080 | continue; | |
13081 | ||
13082 | case 'I': | |
13083 | { | |
13084 | bfd_reloc_code_real_type r[3]; | |
13085 | expressionS ep; | |
13086 | int imm; | |
13087 | ||
13088 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13089 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13090 | break; | |
13091 | ||
13092 | imm = ep.X_add_number & 127; | |
13093 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13094 | } | |
13095 | s = expr_end; | |
13096 | continue; | |
13097 | ||
13098 | case 'J': | |
13099 | { | |
13100 | bfd_reloc_code_real_type r[3]; | |
13101 | expressionS ep; | |
13102 | int imm; | |
13103 | ||
13104 | /* Check whether there is only a single bracketed | |
13105 | expression left. If so, it must be the base register | |
13106 | and the constant must be zero. */ | |
13107 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13108 | { | |
13109 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13110 | continue; | |
13111 | } | |
13112 | ||
13113 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13114 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13115 | break; | |
13116 | ||
13117 | imm = ep.X_add_number >> 2; | |
13118 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13119 | } | |
13120 | s = expr_end; | |
13121 | continue; | |
13122 | ||
13123 | case 'L': | |
13124 | { | |
13125 | bfd_reloc_code_real_type r[3]; | |
13126 | expressionS ep; | |
13127 | int imm; | |
13128 | ||
13129 | /* Check whether there is only a single bracketed | |
13130 | expression left. If so, it must be the base register | |
13131 | and the constant must be zero. */ | |
13132 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13133 | { | |
13134 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13135 | continue; | |
13136 | } | |
13137 | ||
13138 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13139 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13140 | break; | |
13141 | ||
13142 | imm = ep.X_add_number; | |
13143 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13144 | } | |
13145 | s = expr_end; | |
13146 | continue; | |
13147 | ||
13148 | case 'M': | |
13149 | { | |
13150 | bfd_reloc_code_real_type r[3]; | |
13151 | expressionS ep; | |
13152 | int imm; | |
13153 | ||
13154 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13155 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13156 | break; | |
13157 | ||
13158 | imm = ep.X_add_number & 7; | |
13159 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13160 | } | |
13161 | s = expr_end; | |
13162 | continue; | |
13163 | ||
13164 | case 'N': /* Register list for lwm and swm. */ | |
13165 | { | |
13166 | /* A comma-separated list of registers and/or | |
13167 | dash-separated contiguous ranges including | |
13168 | both ra and a set of one or more registers | |
13169 | starting at s0 up to s3 which have to be | |
13170 | consecutive, e.g.: | |
13171 | ||
13172 | s0, ra | |
13173 | s0, s1, ra, s2, s3 | |
13174 | s0-s2, ra | |
13175 | ||
13176 | and any permutations of these. */ | |
13177 | unsigned int reglist; | |
13178 | int imm; | |
13179 | ||
13180 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13181 | break; | |
13182 | ||
13183 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13184 | break; | |
13185 | ||
13186 | reglist = (reglist >> 17) & 7; | |
13187 | reglist += 1; | |
13188 | if ((reglist & -reglist) != reglist) | |
13189 | break; | |
252b5132 | 13190 | |
df58fc94 RS |
13191 | imm = ffs (reglist) - 1; |
13192 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13193 | } | |
13194 | continue; | |
252b5132 | 13195 | |
df58fc94 RS |
13196 | case 'O': /* sdbbp 4-bit code. */ |
13197 | { | |
13198 | bfd_reloc_code_real_type r[3]; | |
13199 | expressionS ep; | |
13200 | int imm; | |
13201 | ||
13202 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13203 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13204 | break; | |
13205 | ||
13206 | imm = ep.X_add_number; | |
13207 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13208 | } |
df58fc94 RS |
13209 | s = expr_end; |
13210 | continue; | |
252b5132 | 13211 | |
df58fc94 RS |
13212 | case 'P': |
13213 | { | |
13214 | bfd_reloc_code_real_type r[3]; | |
13215 | expressionS ep; | |
13216 | int imm; | |
5e0116d5 | 13217 | |
df58fc94 RS |
13218 | if (my_getSmallExpression (&ep, r, s) > 0 |
13219 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13220 | break; | |
5e0116d5 | 13221 | |
df58fc94 RS |
13222 | imm = ep.X_add_number >> 2; |
13223 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13224 | } | |
13225 | s = expr_end; | |
13226 | continue; | |
5e0116d5 | 13227 | |
df58fc94 RS |
13228 | case 'Q': |
13229 | { | |
13230 | bfd_reloc_code_real_type r[3]; | |
13231 | expressionS ep; | |
13232 | int imm; | |
5e0116d5 | 13233 | |
df58fc94 RS |
13234 | if (my_getSmallExpression (&ep, r, s) > 0 |
13235 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13236 | break; | |
252b5132 | 13237 | |
df58fc94 RS |
13238 | imm = ep.X_add_number >> 2; |
13239 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13240 | } | |
13241 | s = expr_end; | |
13242 | continue; | |
4614d845 | 13243 | |
df58fc94 RS |
13244 | case 'U': |
13245 | { | |
13246 | bfd_reloc_code_real_type r[3]; | |
13247 | expressionS ep; | |
13248 | int imm; | |
13249 | ||
13250 | /* Check whether there is only a single bracketed | |
13251 | expression left. If so, it must be the base register | |
13252 | and the constant must be zero. */ | |
13253 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13254 | { | |
13255 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13256 | continue; | |
13257 | } | |
13258 | ||
13259 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13260 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13261 | break; | |
13262 | ||
13263 | imm = ep.X_add_number >> 2; | |
13264 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13265 | } | |
13266 | s = expr_end; | |
5e0116d5 | 13267 | continue; |
252b5132 | 13268 | |
df58fc94 RS |
13269 | case 'W': |
13270 | { | |
13271 | bfd_reloc_code_real_type r[3]; | |
13272 | expressionS ep; | |
13273 | int imm; | |
252b5132 | 13274 | |
df58fc94 RS |
13275 | if (my_getSmallExpression (&ep, r, s) > 0 |
13276 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13277 | break; | |
252b5132 | 13278 | |
df58fc94 RS |
13279 | imm = ep.X_add_number >> 2; |
13280 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13281 | } | |
13282 | s = expr_end; | |
13283 | continue; | |
252b5132 | 13284 | |
df58fc94 RS |
13285 | case 'X': |
13286 | { | |
13287 | bfd_reloc_code_real_type r[3]; | |
13288 | expressionS ep; | |
13289 | int imm; | |
252b5132 | 13290 | |
df58fc94 RS |
13291 | if (my_getSmallExpression (&ep, r, s) > 0 |
13292 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13293 | break; | |
252b5132 | 13294 | |
df58fc94 RS |
13295 | imm = ep.X_add_number; |
13296 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13297 | } | |
13298 | s = expr_end; | |
13299 | continue; | |
252b5132 | 13300 | |
df58fc94 RS |
13301 | case 'Y': |
13302 | { | |
13303 | bfd_reloc_code_real_type r[3]; | |
13304 | expressionS ep; | |
13305 | int imm; | |
156c2f8b | 13306 | |
df58fc94 RS |
13307 | if (my_getSmallExpression (&ep, r, s) > 0 |
13308 | || expr_const_in_range (&ep, -2, 2, 2) | |
13309 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13310 | break; | |
156c2f8b | 13311 | |
df58fc94 RS |
13312 | imm = ep.X_add_number >> 2; |
13313 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13314 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13315 | } | |
13316 | s = expr_end; | |
13317 | continue; | |
60b63b72 | 13318 | |
df58fc94 RS |
13319 | case 'Z': |
13320 | { | |
13321 | bfd_reloc_code_real_type r[3]; | |
13322 | expressionS ep; | |
13323 | ||
13324 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13325 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13326 | break; | |
13327 | } | |
13328 | s = expr_end; | |
13329 | continue; | |
13330 | ||
13331 | default: | |
13332 | as_bad (_("Internal error: bad microMIPS opcode " | |
13333 | "(unknown extension operand type `m%c'): %s %s"), | |
13334 | *args, insn->name, insn->args); | |
13335 | /* Further processing is fruitless. */ | |
13336 | return; | |
60b63b72 | 13337 | } |
df58fc94 | 13338 | break; |
60b63b72 | 13339 | |
df58fc94 RS |
13340 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13341 | gas_assert (mips_opts.micromips); | |
13342 | { | |
13343 | /* A comma-separated list of registers and/or | |
13344 | dash-separated contiguous ranges including | |
13345 | at least one of ra and a set of one or more | |
13346 | registers starting at s0 up to s7 and then | |
13347 | s8 which have to be consecutive, e.g.: | |
13348 | ||
13349 | ra | |
13350 | s0 | |
13351 | ra, s0, s1, s2 | |
13352 | s0-s8 | |
13353 | s0-s5, ra | |
13354 | ||
13355 | and any permutations of these. */ | |
13356 | unsigned int reglist; | |
13357 | int imm; | |
13358 | int ra; | |
13359 | ||
13360 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13361 | break; | |
13362 | ||
13363 | if ((reglist & 0x3f00ffff) != 0) | |
13364 | break; | |
13365 | ||
13366 | ra = (reglist >> 27) & 0x10; | |
13367 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13368 | reglist += 1; | |
13369 | if ((reglist & -reglist) != reglist) | |
13370 | break; | |
13371 | ||
13372 | imm = (ffs (reglist) - 1) | ra; | |
13373 | INSERT_OPERAND (1, RT, *ip, imm); | |
13374 | imm_expr.X_op = O_absent; | |
13375 | } | |
60b63b72 RS |
13376 | continue; |
13377 | ||
df58fc94 RS |
13378 | case '|': /* 4-bit trap code. */ |
13379 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13380 | my_getExpression (&imm_expr, s); |
13381 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13382 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13383 | > MICROMIPSOP_MASK_TRAP) |
13384 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13385 | (unsigned long) imm_expr.X_add_number, | |
13386 | ip->insn_mo->name); | |
13387 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13388 | imm_expr.X_op = O_absent; |
13389 | s = expr_end; | |
13390 | continue; | |
13391 | ||
252b5132 | 13392 | default: |
f71d0d44 | 13393 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13394 | abort (); |
252b5132 RH |
13395 | } |
13396 | break; | |
13397 | } | |
13398 | /* Args don't match. */ | |
df58fc94 RS |
13399 | s = argsStart; |
13400 | insn_error = _("Illegal operands"); | |
13401 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13402 | { |
13403 | ++insn; | |
252b5132 RH |
13404 | continue; |
13405 | } | |
df58fc94 RS |
13406 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13407 | { | |
13408 | gas_assert (firstinsn); | |
13409 | need_delay_slot_ok = FALSE; | |
13410 | past = insn + 1; | |
13411 | insn = firstinsn; | |
13412 | continue; | |
13413 | } | |
252b5132 RH |
13414 | return; |
13415 | } | |
13416 | } | |
13417 | ||
0499d65b TS |
13418 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13419 | ||
252b5132 RH |
13420 | /* This routine assembles an instruction into its binary format when |
13421 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13422 | global variables imm_reloc or offset_reloc to the type of relocation |
13423 | to do if one of the operands is an address expression. It also sets | |
13424 | forced_insn_length to the resulting instruction size in bytes if the | |
13425 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13426 | |
13427 | static void | |
17a2f251 | 13428 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13429 | { |
13430 | char *s; | |
13431 | const char *args; | |
13432 | struct mips_opcode *insn; | |
13433 | char *argsstart; | |
13434 | unsigned int regno; | |
13435 | unsigned int lastregno = 0; | |
13436 | char *s_reset; | |
d6f16593 | 13437 | size_t i; |
252b5132 RH |
13438 | |
13439 | insn_error = NULL; | |
13440 | ||
df58fc94 | 13441 | forced_insn_length = 0; |
252b5132 | 13442 | |
3882b010 | 13443 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13444 | ; |
13445 | switch (*s) | |
13446 | { | |
13447 | case '\0': | |
13448 | break; | |
13449 | ||
13450 | case ' ': | |
13451 | *s++ = '\0'; | |
13452 | break; | |
13453 | ||
13454 | case '.': | |
13455 | if (s[1] == 't' && s[2] == ' ') | |
13456 | { | |
13457 | *s = '\0'; | |
df58fc94 | 13458 | forced_insn_length = 2; |
252b5132 RH |
13459 | s += 3; |
13460 | break; | |
13461 | } | |
13462 | else if (s[1] == 'e' && s[2] == ' ') | |
13463 | { | |
13464 | *s = '\0'; | |
df58fc94 | 13465 | forced_insn_length = 4; |
252b5132 RH |
13466 | s += 3; |
13467 | break; | |
13468 | } | |
13469 | /* Fall through. */ | |
13470 | default: | |
13471 | insn_error = _("unknown opcode"); | |
13472 | return; | |
13473 | } | |
13474 | ||
df58fc94 RS |
13475 | if (mips_opts.noautoextend && !forced_insn_length) |
13476 | forced_insn_length = 2; | |
252b5132 RH |
13477 | |
13478 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13479 | { | |
13480 | insn_error = _("unrecognized opcode"); | |
13481 | return; | |
13482 | } | |
13483 | ||
13484 | argsstart = s; | |
13485 | for (;;) | |
13486 | { | |
9b3f89ee TS |
13487 | bfd_boolean ok; |
13488 | ||
9c2799c2 | 13489 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13490 | |
037b32b9 | 13491 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13492 | if (! ok) |
13493 | { | |
13494 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13495 | && strcmp (insn->name, insn[1].name) == 0) | |
13496 | { | |
13497 | ++insn; | |
13498 | continue; | |
13499 | } | |
13500 | else | |
13501 | { | |
13502 | if (!insn_error) | |
13503 | { | |
13504 | static char buf[100]; | |
13505 | sprintf (buf, | |
7bd942df | 13506 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13507 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13508 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13509 | insn_error = buf; | |
13510 | } | |
13511 | return; | |
13512 | } | |
13513 | } | |
13514 | ||
1e915849 | 13515 | create_insn (ip, insn); |
252b5132 | 13516 | imm_expr.X_op = O_absent; |
f6688943 TS |
13517 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13518 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13519 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13520 | imm2_expr.X_op = O_absent; |
252b5132 | 13521 | offset_expr.X_op = O_absent; |
f6688943 TS |
13522 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13523 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13524 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13525 | for (args = insn->args; 1; ++args) |
13526 | { | |
13527 | int c; | |
13528 | ||
13529 | if (*s == ' ') | |
13530 | ++s; | |
13531 | ||
13532 | /* In this switch statement we call break if we did not find | |
13533 | a match, continue if we did find a match, or return if we | |
13534 | are done. */ | |
13535 | ||
13536 | c = *args; | |
13537 | switch (c) | |
13538 | { | |
13539 | case '\0': | |
13540 | if (*s == '\0') | |
13541 | { | |
b886a2ab RS |
13542 | offsetT value; |
13543 | ||
252b5132 RH |
13544 | /* Stuff the immediate value in now, if we can. */ |
13545 | if (imm_expr.X_op == O_constant | |
f6688943 | 13546 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13547 | && insn->pinfo != INSN_MACRO |
13548 | && calculate_reloc (*offset_reloc, | |
13549 | imm_expr.X_add_number, &value)) | |
252b5132 | 13550 | { |
c4e7957c | 13551 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13552 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13553 | &ip->insn_opcode); |
252b5132 | 13554 | imm_expr.X_op = O_absent; |
f6688943 | 13555 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13556 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13557 | } |
13558 | ||
13559 | return; | |
13560 | } | |
13561 | break; | |
13562 | ||
13563 | case ',': | |
13564 | if (*s++ == c) | |
13565 | continue; | |
13566 | s--; | |
13567 | switch (*++args) | |
13568 | { | |
13569 | case 'v': | |
bf12938e | 13570 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13571 | continue; |
13572 | case 'w': | |
bf12938e | 13573 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13574 | continue; |
13575 | } | |
13576 | break; | |
13577 | ||
13578 | case '(': | |
13579 | case ')': | |
13580 | if (*s++ == c) | |
13581 | continue; | |
13582 | break; | |
13583 | ||
13584 | case 'v': | |
13585 | case 'w': | |
13586 | if (s[0] != '$') | |
13587 | { | |
13588 | if (c == 'v') | |
bf12938e | 13589 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13590 | else |
bf12938e | 13591 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13592 | ++args; |
13593 | continue; | |
13594 | } | |
13595 | /* Fall through. */ | |
13596 | case 'x': | |
13597 | case 'y': | |
13598 | case 'z': | |
13599 | case 'Z': | |
13600 | case '0': | |
13601 | case 'S': | |
13602 | case 'R': | |
13603 | case 'X': | |
13604 | case 'Y': | |
707bfff6 TS |
13605 | s_reset = s; |
13606 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13607 | { |
707bfff6 | 13608 | if (c == 'v' || c == 'w') |
85b51719 | 13609 | { |
707bfff6 | 13610 | if (c == 'v') |
a9e24354 | 13611 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13612 | else |
a9e24354 | 13613 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13614 | ++args; |
13615 | continue; | |
85b51719 | 13616 | } |
707bfff6 | 13617 | break; |
252b5132 RH |
13618 | } |
13619 | ||
13620 | if (*s == ' ') | |
13621 | ++s; | |
13622 | if (args[1] != *s) | |
13623 | { | |
13624 | if (c == 'v' || c == 'w') | |
13625 | { | |
13626 | regno = mips16_to_32_reg_map[lastregno]; | |
13627 | s = s_reset; | |
f9419b05 | 13628 | ++args; |
252b5132 RH |
13629 | } |
13630 | } | |
13631 | ||
13632 | switch (c) | |
13633 | { | |
13634 | case 'x': | |
13635 | case 'y': | |
13636 | case 'z': | |
13637 | case 'v': | |
13638 | case 'w': | |
13639 | case 'Z': | |
13640 | regno = mips32_to_16_reg_map[regno]; | |
13641 | break; | |
13642 | ||
13643 | case '0': | |
13644 | if (regno != 0) | |
13645 | regno = ILLEGAL_REG; | |
13646 | break; | |
13647 | ||
13648 | case 'S': | |
13649 | if (regno != SP) | |
13650 | regno = ILLEGAL_REG; | |
13651 | break; | |
13652 | ||
13653 | case 'R': | |
13654 | if (regno != RA) | |
13655 | regno = ILLEGAL_REG; | |
13656 | break; | |
13657 | ||
13658 | case 'X': | |
13659 | case 'Y': | |
741fe287 MR |
13660 | if (regno == AT && mips_opts.at) |
13661 | { | |
13662 | if (mips_opts.at == ATREG) | |
13663 | as_warn (_("used $at without \".set noat\"")); | |
13664 | else | |
13665 | as_warn (_("used $%u with \".set at=$%u\""), | |
13666 | regno, mips_opts.at); | |
13667 | } | |
252b5132 RH |
13668 | break; |
13669 | ||
13670 | default: | |
b37df7c4 | 13671 | abort (); |
252b5132 RH |
13672 | } |
13673 | ||
13674 | if (regno == ILLEGAL_REG) | |
13675 | break; | |
13676 | ||
13677 | switch (c) | |
13678 | { | |
13679 | case 'x': | |
13680 | case 'v': | |
bf12938e | 13681 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13682 | break; |
13683 | case 'y': | |
13684 | case 'w': | |
bf12938e | 13685 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13686 | break; |
13687 | case 'z': | |
bf12938e | 13688 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13689 | break; |
13690 | case 'Z': | |
bf12938e | 13691 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13692 | case '0': |
13693 | case 'S': | |
13694 | case 'R': | |
13695 | break; | |
13696 | case 'X': | |
bf12938e | 13697 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13698 | break; |
13699 | case 'Y': | |
13700 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13701 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13702 | break; |
13703 | default: | |
b37df7c4 | 13704 | abort (); |
252b5132 RH |
13705 | } |
13706 | ||
13707 | lastregno = regno; | |
13708 | continue; | |
13709 | ||
13710 | case 'P': | |
13711 | if (strncmp (s, "$pc", 3) == 0) | |
13712 | { | |
13713 | s += 3; | |
13714 | continue; | |
13715 | } | |
13716 | break; | |
13717 | ||
252b5132 RH |
13718 | case '5': |
13719 | case 'H': | |
13720 | case 'W': | |
13721 | case 'D': | |
13722 | case 'j': | |
252b5132 RH |
13723 | case 'V': |
13724 | case 'C': | |
13725 | case 'U': | |
13726 | case 'k': | |
13727 | case 'K': | |
d6f16593 MR |
13728 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13729 | if (i > 0) | |
252b5132 | 13730 | { |
d6f16593 | 13731 | if (imm_expr.X_op != O_constant) |
252b5132 | 13732 | { |
df58fc94 | 13733 | forced_insn_length = 4; |
5c04167a | 13734 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13735 | } |
d6f16593 MR |
13736 | else |
13737 | { | |
13738 | /* We need to relax this instruction. */ | |
13739 | *offset_reloc = *imm_reloc; | |
13740 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13741 | } | |
13742 | s = expr_end; | |
13743 | continue; | |
252b5132 | 13744 | } |
d6f16593 MR |
13745 | *imm_reloc = BFD_RELOC_UNUSED; |
13746 | /* Fall through. */ | |
13747 | case '<': | |
13748 | case '>': | |
13749 | case '[': | |
13750 | case ']': | |
13751 | case '4': | |
13752 | case '8': | |
13753 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13754 | if (imm_expr.X_op == O_register) |
13755 | { | |
13756 | /* What we thought was an expression turned out to | |
13757 | be a register. */ | |
13758 | ||
13759 | if (s[0] == '(' && args[1] == '(') | |
13760 | { | |
13761 | /* It looks like the expression was omitted | |
13762 | before a register indirection, which means | |
13763 | that the expression is implicitly zero. We | |
13764 | still set up imm_expr, so that we handle | |
13765 | explicit extensions correctly. */ | |
13766 | imm_expr.X_op = O_constant; | |
13767 | imm_expr.X_add_number = 0; | |
f6688943 | 13768 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13769 | continue; |
13770 | } | |
13771 | ||
13772 | break; | |
13773 | } | |
13774 | ||
13775 | /* We need to relax this instruction. */ | |
f6688943 | 13776 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13777 | s = expr_end; |
13778 | continue; | |
13779 | ||
13780 | case 'p': | |
13781 | case 'q': | |
13782 | case 'A': | |
13783 | case 'B': | |
13784 | case 'E': | |
13785 | /* We use offset_reloc rather than imm_reloc for the PC | |
13786 | relative operands. This lets macros with both | |
13787 | immediate and address operands work correctly. */ | |
13788 | my_getExpression (&offset_expr, s); | |
13789 | ||
13790 | if (offset_expr.X_op == O_register) | |
13791 | break; | |
13792 | ||
13793 | /* We need to relax this instruction. */ | |
f6688943 | 13794 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13795 | s = expr_end; |
13796 | continue; | |
13797 | ||
13798 | case '6': /* break code */ | |
13799 | my_getExpression (&imm_expr, s); | |
13800 | check_absolute_expr (ip, &imm_expr); | |
13801 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13802 | as_warn (_("Invalid value for `%s' (%lu)"), |
13803 | ip->insn_mo->name, | |
13804 | (unsigned long) imm_expr.X_add_number); | |
13805 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13806 | imm_expr.X_op = O_absent; |
13807 | s = expr_end; | |
13808 | continue; | |
13809 | ||
13810 | case 'a': /* 26 bit address */ | |
13811 | my_getExpression (&offset_expr, s); | |
13812 | s = expr_end; | |
f6688943 | 13813 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13814 | ip->insn_opcode <<= 16; |
13815 | continue; | |
13816 | ||
13817 | case 'l': /* register list for entry macro */ | |
13818 | case 'L': /* register list for exit macro */ | |
13819 | { | |
13820 | int mask; | |
13821 | ||
13822 | if (c == 'l') | |
13823 | mask = 0; | |
13824 | else | |
13825 | mask = 7 << 3; | |
13826 | while (*s != '\0') | |
13827 | { | |
707bfff6 | 13828 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13829 | |
13830 | while (*s == ' ' || *s == ',') | |
13831 | ++s; | |
707bfff6 | 13832 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13833 | freg = 0; |
707bfff6 TS |
13834 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13835 | freg = 1; | |
252b5132 RH |
13836 | else |
13837 | { | |
707bfff6 TS |
13838 | as_bad (_("can't parse register list")); |
13839 | break; | |
252b5132 RH |
13840 | } |
13841 | if (*s == ' ') | |
13842 | ++s; | |
13843 | if (*s != '-') | |
13844 | reg2 = reg1; | |
13845 | else | |
13846 | { | |
13847 | ++s; | |
707bfff6 TS |
13848 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13849 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13850 | { |
707bfff6 TS |
13851 | as_bad (_("invalid register list")); |
13852 | break; | |
252b5132 RH |
13853 | } |
13854 | } | |
13855 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13856 | { | |
13857 | mask &= ~ (7 << 3); | |
13858 | mask |= 5 << 3; | |
13859 | } | |
13860 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13861 | { | |
13862 | mask &= ~ (7 << 3); | |
13863 | mask |= 6 << 3; | |
13864 | } | |
13865 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13866 | mask |= (reg2 - 3) << 3; | |
13867 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13868 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13869 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13870 | mask |= 1; |
13871 | else | |
13872 | { | |
13873 | as_bad (_("invalid register list")); | |
13874 | break; | |
13875 | } | |
13876 | } | |
13877 | /* The mask is filled in in the opcode table for the | |
13878 | benefit of the disassembler. We remove it before | |
13879 | applying the actual mask. */ | |
13880 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13881 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13882 | } | |
13883 | continue; | |
13884 | ||
0499d65b TS |
13885 | case 'm': /* Register list for save insn. */ |
13886 | case 'M': /* Register list for restore insn. */ | |
13887 | { | |
5c04167a | 13888 | int opcode = ip->insn_opcode; |
0499d65b | 13889 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13890 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13891 | |
13892 | while (*s != '\0') | |
13893 | { | |
13894 | unsigned int reg1, reg2; | |
13895 | ||
13896 | SKIP_SPACE_TABS (s); | |
13897 | while (*s == ',') | |
13898 | ++s; | |
13899 | SKIP_SPACE_TABS (s); | |
13900 | ||
13901 | my_getExpression (&imm_expr, s); | |
13902 | if (imm_expr.X_op == O_constant) | |
13903 | { | |
13904 | /* Handle the frame size. */ | |
13905 | if (seen_framesz) | |
13906 | { | |
13907 | as_bad (_("more than one frame size in list")); | |
13908 | break; | |
13909 | } | |
13910 | seen_framesz = 1; | |
13911 | framesz = imm_expr.X_add_number; | |
13912 | imm_expr.X_op = O_absent; | |
13913 | s = expr_end; | |
13914 | continue; | |
13915 | } | |
13916 | ||
707bfff6 | 13917 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13918 | { |
13919 | as_bad (_("can't parse register list")); | |
13920 | break; | |
13921 | } | |
0499d65b | 13922 | |
707bfff6 TS |
13923 | while (*s == ' ') |
13924 | ++s; | |
13925 | ||
0499d65b TS |
13926 | if (*s != '-') |
13927 | reg2 = reg1; | |
13928 | else | |
13929 | { | |
13930 | ++s; | |
707bfff6 TS |
13931 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13932 | || reg2 < reg1) | |
0499d65b TS |
13933 | { |
13934 | as_bad (_("can't parse register list")); | |
13935 | break; | |
13936 | } | |
0499d65b TS |
13937 | } |
13938 | ||
13939 | while (reg1 <= reg2) | |
13940 | { | |
13941 | if (reg1 >= 4 && reg1 <= 7) | |
13942 | { | |
3a93f742 | 13943 | if (!seen_framesz) |
0499d65b | 13944 | /* args $a0-$a3 */ |
91d6fa6a | 13945 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13946 | else |
13947 | /* statics $a0-$a3 */ | |
13948 | statics |= 1 << (reg1 - 4); | |
13949 | } | |
13950 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13951 | { | |
13952 | /* $s0-$s8 */ | |
13953 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13954 | } | |
13955 | else if (reg1 == 31) | |
13956 | { | |
13957 | /* Add $ra to insn. */ | |
13958 | opcode |= 0x40; | |
13959 | } | |
13960 | else | |
13961 | { | |
13962 | as_bad (_("unexpected register in list")); | |
13963 | break; | |
13964 | } | |
13965 | if (++reg1 == 24) | |
13966 | reg1 = 30; | |
13967 | } | |
13968 | } | |
13969 | ||
13970 | /* Encode args/statics combination. */ | |
91d6fa6a | 13971 | if (nargs & statics) |
0499d65b | 13972 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13973 | else if (nargs == 0xf) |
0499d65b TS |
13974 | /* All $a0-$a3 are args. */ |
13975 | opcode |= MIPS16_ALL_ARGS << 16; | |
13976 | else if (statics == 0xf) | |
13977 | /* All $a0-$a3 are statics. */ | |
13978 | opcode |= MIPS16_ALL_STATICS << 16; | |
13979 | else | |
13980 | { | |
13981 | int narg = 0, nstat = 0; | |
13982 | ||
13983 | /* Count arg registers. */ | |
91d6fa6a | 13984 | while (nargs & 0x1) |
0499d65b | 13985 | { |
91d6fa6a | 13986 | nargs >>= 1; |
0499d65b TS |
13987 | narg++; |
13988 | } | |
91d6fa6a | 13989 | if (nargs != 0) |
0499d65b TS |
13990 | as_bad (_("invalid arg register list")); |
13991 | ||
13992 | /* Count static registers. */ | |
13993 | while (statics & 0x8) | |
13994 | { | |
13995 | statics = (statics << 1) & 0xf; | |
13996 | nstat++; | |
13997 | } | |
13998 | if (statics != 0) | |
13999 | as_bad (_("invalid static register list")); | |
14000 | ||
14001 | /* Encode args/statics. */ | |
14002 | opcode |= ((narg << 2) | nstat) << 16; | |
14003 | } | |
14004 | ||
14005 | /* Encode $s0/$s1. */ | |
14006 | if (sregs & (1 << 0)) /* $s0 */ | |
14007 | opcode |= 0x20; | |
14008 | if (sregs & (1 << 1)) /* $s1 */ | |
14009 | opcode |= 0x10; | |
14010 | sregs >>= 2; | |
14011 | ||
14012 | if (sregs != 0) | |
14013 | { | |
14014 | /* Count regs $s2-$s8. */ | |
14015 | int nsreg = 0; | |
14016 | while (sregs & 1) | |
14017 | { | |
14018 | sregs >>= 1; | |
14019 | nsreg++; | |
14020 | } | |
14021 | if (sregs != 0) | |
14022 | as_bad (_("invalid static register list")); | |
14023 | /* Encode $s2-$s8. */ | |
14024 | opcode |= nsreg << 24; | |
14025 | } | |
14026 | ||
14027 | /* Encode frame size. */ | |
14028 | if (!seen_framesz) | |
14029 | as_bad (_("missing frame size")); | |
14030 | else if ((framesz & 7) != 0 || framesz < 0 | |
14031 | || framesz > 0xff * 8) | |
14032 | as_bad (_("invalid frame size")); | |
14033 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14034 | { | |
14035 | framesz /= 8; | |
14036 | opcode |= (((framesz & 0xf0) << 16) | |
14037 | | (framesz & 0x0f)); | |
14038 | } | |
14039 | ||
14040 | /* Finally build the instruction. */ | |
14041 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14042 | opcode |= MIPS16_EXTEND; |
14043 | ip->insn_opcode = opcode; | |
0499d65b TS |
14044 | } |
14045 | continue; | |
14046 | ||
252b5132 RH |
14047 | case 'e': /* extend code */ |
14048 | my_getExpression (&imm_expr, s); | |
14049 | check_absolute_expr (ip, &imm_expr); | |
14050 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14051 | { | |
14052 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14053 | ip->insn_mo->name, | |
14054 | (unsigned long) imm_expr.X_add_number); | |
14055 | imm_expr.X_add_number &= 0x7ff; | |
14056 | } | |
14057 | ip->insn_opcode |= imm_expr.X_add_number; | |
14058 | imm_expr.X_op = O_absent; | |
14059 | s = expr_end; | |
14060 | continue; | |
14061 | ||
14062 | default: | |
b37df7c4 | 14063 | abort (); |
252b5132 RH |
14064 | } |
14065 | break; | |
14066 | } | |
14067 | ||
14068 | /* Args don't match. */ | |
14069 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14070 | strcmp (insn->name, insn[1].name) == 0) | |
14071 | { | |
14072 | ++insn; | |
14073 | s = argsstart; | |
14074 | continue; | |
14075 | } | |
14076 | ||
14077 | insn_error = _("illegal operands"); | |
14078 | ||
14079 | return; | |
14080 | } | |
14081 | } | |
14082 | ||
14083 | /* This structure holds information we know about a mips16 immediate | |
14084 | argument type. */ | |
14085 | ||
e972090a NC |
14086 | struct mips16_immed_operand |
14087 | { | |
252b5132 RH |
14088 | /* The type code used in the argument string in the opcode table. */ |
14089 | int type; | |
14090 | /* The number of bits in the short form of the opcode. */ | |
14091 | int nbits; | |
14092 | /* The number of bits in the extended form of the opcode. */ | |
14093 | int extbits; | |
14094 | /* The amount by which the short form is shifted when it is used; | |
14095 | for example, the sw instruction has a shift count of 2. */ | |
14096 | int shift; | |
14097 | /* The amount by which the short form is shifted when it is stored | |
14098 | into the instruction code. */ | |
14099 | int op_shift; | |
14100 | /* Non-zero if the short form is unsigned. */ | |
14101 | int unsp; | |
14102 | /* Non-zero if the extended form is unsigned. */ | |
14103 | int extu; | |
14104 | /* Non-zero if the value is PC relative. */ | |
14105 | int pcrel; | |
14106 | }; | |
14107 | ||
14108 | /* The mips16 immediate operand types. */ | |
14109 | ||
14110 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14111 | { | |
14112 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14113 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14114 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14115 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14116 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14117 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14118 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14119 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14120 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14121 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14122 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14123 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14124 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14125 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14126 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14127 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14128 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14129 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14130 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14131 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14132 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14133 | }; | |
14134 | ||
14135 | #define MIPS16_NUM_IMMED \ | |
14136 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14137 | ||
b886a2ab RS |
14138 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14139 | NBITS is the number of significant bits in VAL. */ | |
14140 | ||
14141 | static unsigned long | |
14142 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14143 | { | |
14144 | int extval; | |
14145 | if (nbits == 16) | |
14146 | { | |
14147 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14148 | val &= 0x1f; | |
14149 | } | |
14150 | else if (nbits == 15) | |
14151 | { | |
14152 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14153 | val &= 0xf; | |
14154 | } | |
14155 | else | |
14156 | { | |
14157 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14158 | val = 0; | |
14159 | } | |
14160 | return (extval << 16) | val; | |
14161 | } | |
14162 | ||
5c04167a RS |
14163 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14164 | extending it if necessary. The instruction in *INSN may | |
14165 | already be extended. | |
14166 | ||
43c0598f RS |
14167 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14168 | if none. In the former case, VAL is a 16-bit number with no | |
14169 | defined signedness. | |
14170 | ||
14171 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14172 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14173 | |
14174 | static void | |
43c0598f RS |
14175 | mips16_immed (char *file, unsigned int line, int type, |
14176 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14177 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14178 | { |
3994f87e | 14179 | const struct mips16_immed_operand *op; |
252b5132 | 14180 | int mintiny, maxtiny; |
252b5132 RH |
14181 | |
14182 | op = mips16_immed_operands; | |
14183 | while (op->type != type) | |
14184 | { | |
14185 | ++op; | |
9c2799c2 | 14186 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14187 | } |
14188 | ||
14189 | if (op->unsp) | |
14190 | { | |
14191 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14192 | { | |
14193 | mintiny = 1; | |
14194 | maxtiny = 1 << op->nbits; | |
14195 | } | |
14196 | else | |
14197 | { | |
14198 | mintiny = 0; | |
14199 | maxtiny = (1 << op->nbits) - 1; | |
14200 | } | |
43c0598f RS |
14201 | if (reloc != BFD_RELOC_UNUSED) |
14202 | val &= 0xffff; | |
252b5132 RH |
14203 | } |
14204 | else | |
14205 | { | |
14206 | mintiny = - (1 << (op->nbits - 1)); | |
14207 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14208 | if (reloc != BFD_RELOC_UNUSED) |
14209 | val = SEXT_16BIT (val); | |
252b5132 RH |
14210 | } |
14211 | ||
14212 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14213 | if (type == 'p' || type == 'q') | |
14214 | val /= 2; | |
14215 | ||
14216 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14217 | || val < (mintiny << op->shift) | |
14218 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14219 | { |
14220 | /* We need an extended instruction. */ | |
14221 | if (user_insn_length == 2) | |
14222 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14223 | else | |
14224 | *insn |= MIPS16_EXTEND; | |
14225 | } | |
14226 | else if (user_insn_length == 4) | |
14227 | { | |
14228 | /* The operand doesn't force an unextended instruction to be extended. | |
14229 | Warn if the user wanted an extended instruction anyway. */ | |
14230 | *insn |= MIPS16_EXTEND; | |
14231 | as_warn_where (file, line, | |
14232 | _("extended operand requested but not required")); | |
14233 | } | |
252b5132 | 14234 | |
5c04167a | 14235 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14236 | { |
14237 | int insnval; | |
14238 | ||
252b5132 RH |
14239 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14240 | insnval <<= op->op_shift; | |
14241 | *insn |= insnval; | |
14242 | } | |
14243 | else | |
14244 | { | |
14245 | long minext, maxext; | |
252b5132 | 14246 | |
43c0598f | 14247 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14248 | { |
43c0598f RS |
14249 | if (op->extu) |
14250 | { | |
14251 | minext = 0; | |
14252 | maxext = (1 << op->extbits) - 1; | |
14253 | } | |
14254 | else | |
14255 | { | |
14256 | minext = - (1 << (op->extbits - 1)); | |
14257 | maxext = (1 << (op->extbits - 1)) - 1; | |
14258 | } | |
14259 | if (val < minext || val > maxext) | |
14260 | as_bad_where (file, line, | |
14261 | _("operand value out of range for instruction")); | |
252b5132 | 14262 | } |
252b5132 | 14263 | |
b886a2ab | 14264 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14265 | } |
14266 | } | |
14267 | \f | |
d6f16593 | 14268 | struct percent_op_match |
ad8d3bb3 | 14269 | { |
5e0116d5 RS |
14270 | const char *str; |
14271 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14272 | }; |
14273 | ||
14274 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14275 | { |
5e0116d5 | 14276 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14277 | #ifdef OBJ_ELF |
5e0116d5 RS |
14278 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14279 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14280 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14281 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14282 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14283 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14284 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14285 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14286 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14287 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14288 | {"%half", BFD_RELOC_16}, | |
14289 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14290 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14291 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14292 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14293 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14294 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14295 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14296 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14297 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14298 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14299 | #endif |
5e0116d5 | 14300 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14301 | }; |
14302 | ||
d6f16593 MR |
14303 | static const struct percent_op_match mips16_percent_op[] = |
14304 | { | |
14305 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14306 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14307 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14308 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14309 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14310 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14311 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14312 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14313 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14314 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14315 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14316 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14317 | }; |
14318 | ||
252b5132 | 14319 | |
5e0116d5 RS |
14320 | /* Return true if *STR points to a relocation operator. When returning true, |
14321 | move *STR over the operator and store its relocation code in *RELOC. | |
14322 | Leave both *STR and *RELOC alone when returning false. */ | |
14323 | ||
14324 | static bfd_boolean | |
17a2f251 | 14325 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14326 | { |
d6f16593 MR |
14327 | const struct percent_op_match *percent_op; |
14328 | size_t limit, i; | |
14329 | ||
14330 | if (mips_opts.mips16) | |
14331 | { | |
14332 | percent_op = mips16_percent_op; | |
14333 | limit = ARRAY_SIZE (mips16_percent_op); | |
14334 | } | |
14335 | else | |
14336 | { | |
14337 | percent_op = mips_percent_op; | |
14338 | limit = ARRAY_SIZE (mips_percent_op); | |
14339 | } | |
76b3015f | 14340 | |
d6f16593 | 14341 | for (i = 0; i < limit; i++) |
5e0116d5 | 14342 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14343 | { |
3f98094e DJ |
14344 | int len = strlen (percent_op[i].str); |
14345 | ||
14346 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14347 | continue; | |
14348 | ||
5e0116d5 RS |
14349 | *str += strlen (percent_op[i].str); |
14350 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14351 | |
5e0116d5 RS |
14352 | /* Check whether the output BFD supports this relocation. |
14353 | If not, issue an error and fall back on something safe. */ | |
14354 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14355 | { |
20203fb9 | 14356 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14357 | percent_op[i].str); |
01a3f561 | 14358 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14359 | } |
5e0116d5 | 14360 | return TRUE; |
394f9b3a | 14361 | } |
5e0116d5 | 14362 | return FALSE; |
394f9b3a | 14363 | } |
ad8d3bb3 | 14364 | |
ad8d3bb3 | 14365 | |
5e0116d5 RS |
14366 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14367 | expression in *EP and the relocations in the array starting | |
14368 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14369 | |
01a3f561 | 14370 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14371 | |
5e0116d5 | 14372 | static size_t |
17a2f251 TS |
14373 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14374 | char *str) | |
ad8d3bb3 | 14375 | { |
5e0116d5 RS |
14376 | bfd_reloc_code_real_type reversed_reloc[3]; |
14377 | size_t reloc_index, i; | |
09b8f35a RS |
14378 | int crux_depth, str_depth; |
14379 | char *crux; | |
5e0116d5 RS |
14380 | |
14381 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14382 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14383 | of the main expression and with CRUX_DEPTH containing the number | |
14384 | of open brackets at that point. */ | |
14385 | reloc_index = -1; | |
14386 | str_depth = 0; | |
14387 | do | |
fb1b3232 | 14388 | { |
09b8f35a RS |
14389 | reloc_index++; |
14390 | crux = str; | |
14391 | crux_depth = str_depth; | |
14392 | ||
14393 | /* Skip over whitespace and brackets, keeping count of the number | |
14394 | of brackets. */ | |
14395 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14396 | if (*str++ == '(') | |
14397 | str_depth++; | |
5e0116d5 | 14398 | } |
09b8f35a RS |
14399 | while (*str == '%' |
14400 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14401 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14402 | |
09b8f35a | 14403 | my_getExpression (ep, crux); |
5e0116d5 | 14404 | str = expr_end; |
394f9b3a | 14405 | |
5e0116d5 | 14406 | /* Match every open bracket. */ |
09b8f35a | 14407 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14408 | if (*str++ == ')') |
09b8f35a | 14409 | crux_depth--; |
394f9b3a | 14410 | |
09b8f35a | 14411 | if (crux_depth > 0) |
20203fb9 | 14412 | as_bad (_("unclosed '('")); |
394f9b3a | 14413 | |
5e0116d5 | 14414 | expr_end = str; |
252b5132 | 14415 | |
01a3f561 | 14416 | if (reloc_index != 0) |
64bdfcaf RS |
14417 | { |
14418 | prev_reloc_op_frag = frag_now; | |
14419 | for (i = 0; i < reloc_index; i++) | |
14420 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14421 | } | |
fb1b3232 | 14422 | |
5e0116d5 | 14423 | return reloc_index; |
252b5132 RH |
14424 | } |
14425 | ||
14426 | static void | |
17a2f251 | 14427 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14428 | { |
14429 | char *save_in; | |
14430 | ||
14431 | save_in = input_line_pointer; | |
14432 | input_line_pointer = str; | |
14433 | expression (ep); | |
14434 | expr_end = input_line_pointer; | |
14435 | input_line_pointer = save_in; | |
252b5132 RH |
14436 | } |
14437 | ||
252b5132 | 14438 | char * |
17a2f251 | 14439 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14440 | { |
499ac353 | 14441 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14442 | } |
14443 | ||
14444 | void | |
17a2f251 | 14445 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14446 | { |
14447 | if (target_big_endian) | |
14448 | number_to_chars_bigendian (buf, val, n); | |
14449 | else | |
14450 | number_to_chars_littleendian (buf, val, n); | |
14451 | } | |
14452 | \f | |
ae948b86 | 14453 | #ifdef OBJ_ELF |
e013f690 TS |
14454 | static int support_64bit_objects(void) |
14455 | { | |
14456 | const char **list, **l; | |
aa3d8fdf | 14457 | int yes; |
e013f690 TS |
14458 | |
14459 | list = bfd_target_list (); | |
14460 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14461 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14462 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14463 | break; |
aa3d8fdf | 14464 | yes = (*l != NULL); |
e013f690 | 14465 | free (list); |
aa3d8fdf | 14466 | return yes; |
e013f690 | 14467 | } |
ae948b86 | 14468 | #endif /* OBJ_ELF */ |
e013f690 | 14469 | |
78849248 | 14470 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14471 | |
23fce1e3 NC |
14472 | enum options |
14473 | { | |
14474 | OPTION_MARCH = OPTION_MD_BASE, | |
14475 | OPTION_MTUNE, | |
14476 | OPTION_MIPS1, | |
14477 | OPTION_MIPS2, | |
14478 | OPTION_MIPS3, | |
14479 | OPTION_MIPS4, | |
14480 | OPTION_MIPS5, | |
14481 | OPTION_MIPS32, | |
14482 | OPTION_MIPS64, | |
14483 | OPTION_MIPS32R2, | |
14484 | OPTION_MIPS64R2, | |
14485 | OPTION_MIPS16, | |
14486 | OPTION_NO_MIPS16, | |
14487 | OPTION_MIPS3D, | |
14488 | OPTION_NO_MIPS3D, | |
14489 | OPTION_MDMX, | |
14490 | OPTION_NO_MDMX, | |
14491 | OPTION_DSP, | |
14492 | OPTION_NO_DSP, | |
14493 | OPTION_MT, | |
14494 | OPTION_NO_MT, | |
14495 | OPTION_SMARTMIPS, | |
14496 | OPTION_NO_SMARTMIPS, | |
14497 | OPTION_DSPR2, | |
14498 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14499 | OPTION_MICROMIPS, |
14500 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14501 | OPTION_MCU, |
14502 | OPTION_NO_MCU, | |
23fce1e3 NC |
14503 | OPTION_COMPAT_ARCH_BASE, |
14504 | OPTION_M4650, | |
14505 | OPTION_NO_M4650, | |
14506 | OPTION_M4010, | |
14507 | OPTION_NO_M4010, | |
14508 | OPTION_M4100, | |
14509 | OPTION_NO_M4100, | |
14510 | OPTION_M3900, | |
14511 | OPTION_NO_M3900, | |
14512 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14513 | OPTION_MNO_7000_HILO_FIX, |
14514 | OPTION_FIX_24K, | |
14515 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14516 | OPTION_FIX_LOONGSON2F_JUMP, |
14517 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14518 | OPTION_FIX_LOONGSON2F_NOP, | |
14519 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14520 | OPTION_FIX_VR4120, |
14521 | OPTION_NO_FIX_VR4120, | |
14522 | OPTION_FIX_VR4130, | |
14523 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14524 | OPTION_FIX_CN63XXP1, |
14525 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14526 | OPTION_TRAP, |
14527 | OPTION_BREAK, | |
14528 | OPTION_EB, | |
14529 | OPTION_EL, | |
14530 | OPTION_FP32, | |
14531 | OPTION_GP32, | |
14532 | OPTION_CONSTRUCT_FLOATS, | |
14533 | OPTION_NO_CONSTRUCT_FLOATS, | |
14534 | OPTION_FP64, | |
14535 | OPTION_GP64, | |
14536 | OPTION_RELAX_BRANCH, | |
14537 | OPTION_NO_RELAX_BRANCH, | |
14538 | OPTION_MSHARED, | |
14539 | OPTION_MNO_SHARED, | |
14540 | OPTION_MSYM32, | |
14541 | OPTION_MNO_SYM32, | |
14542 | OPTION_SOFT_FLOAT, | |
14543 | OPTION_HARD_FLOAT, | |
14544 | OPTION_SINGLE_FLOAT, | |
14545 | OPTION_DOUBLE_FLOAT, | |
14546 | OPTION_32, | |
14547 | #ifdef OBJ_ELF | |
14548 | OPTION_CALL_SHARED, | |
14549 | OPTION_CALL_NONPIC, | |
14550 | OPTION_NON_SHARED, | |
14551 | OPTION_XGOT, | |
14552 | OPTION_MABI, | |
14553 | OPTION_N32, | |
14554 | OPTION_64, | |
14555 | OPTION_MDEBUG, | |
14556 | OPTION_NO_MDEBUG, | |
14557 | OPTION_PDR, | |
14558 | OPTION_NO_PDR, | |
14559 | OPTION_MVXWORKS_PIC, | |
14560 | #endif /* OBJ_ELF */ | |
14561 | OPTION_END_OF_ENUM | |
14562 | }; | |
14563 | ||
e972090a NC |
14564 | struct option md_longopts[] = |
14565 | { | |
f9b4148d | 14566 | /* Options which specify architecture. */ |
f9b4148d | 14567 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14568 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14569 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14570 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14571 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14572 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14573 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14574 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14575 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14576 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14577 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14578 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14579 | |
14580 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14581 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14582 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14583 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14584 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14585 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14586 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14587 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14588 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14589 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14590 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14591 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14592 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14593 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14594 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14595 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14596 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14597 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14598 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14599 | |
14600 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14601 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14602 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14603 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14604 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14605 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14606 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14607 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14608 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14609 | ||
14610 | /* Options which enable bug fixes. */ | |
f9b4148d | 14611 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14612 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14613 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14614 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14615 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14616 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14617 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14618 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14619 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14620 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14621 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14622 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14623 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14624 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14625 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14626 | |
14627 | /* Miscellaneous options. */ | |
252b5132 RH |
14628 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14629 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14630 | {"break", no_argument, NULL, OPTION_BREAK}, |
14631 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14632 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14633 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14634 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14635 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14636 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14637 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14638 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14639 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14640 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14641 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14642 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14643 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14644 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14645 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14646 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14647 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14648 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14649 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14650 | |
14651 | /* Strictly speaking this next option is ELF specific, | |
14652 | but we allow it for other ports as well in order to | |
14653 | make testing easier. */ | |
14654 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14655 | |
f9b4148d | 14656 | /* ELF-specific options. */ |
156c2f8b | 14657 | #ifdef OBJ_ELF |
156c2f8b NC |
14658 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14659 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14660 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14661 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14662 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14663 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14664 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14665 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14666 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14667 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14668 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14669 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14670 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14671 | #endif /* OBJ_ELF */ |
f9b4148d | 14672 | |
252b5132 RH |
14673 | {NULL, no_argument, NULL, 0} |
14674 | }; | |
156c2f8b | 14675 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14676 | |
316f5878 RS |
14677 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14678 | NEW_VALUE. Warn if another value was already specified. Note: | |
14679 | we have to defer parsing the -march and -mtune arguments in order | |
14680 | to handle 'from-abi' correctly, since the ABI might be specified | |
14681 | in a later argument. */ | |
14682 | ||
14683 | static void | |
17a2f251 | 14684 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14685 | { |
14686 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14687 | as_warn (_("A different %s was already specified, is now %s"), | |
14688 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14689 | new_value); | |
14690 | ||
14691 | *string_ptr = new_value; | |
14692 | } | |
14693 | ||
252b5132 | 14694 | int |
17a2f251 | 14695 | md_parse_option (int c, char *arg) |
252b5132 RH |
14696 | { |
14697 | switch (c) | |
14698 | { | |
119d663a NC |
14699 | case OPTION_CONSTRUCT_FLOATS: |
14700 | mips_disable_float_construction = 0; | |
14701 | break; | |
bdaaa2e1 | 14702 | |
119d663a NC |
14703 | case OPTION_NO_CONSTRUCT_FLOATS: |
14704 | mips_disable_float_construction = 1; | |
14705 | break; | |
bdaaa2e1 | 14706 | |
252b5132 RH |
14707 | case OPTION_TRAP: |
14708 | mips_trap = 1; | |
14709 | break; | |
14710 | ||
14711 | case OPTION_BREAK: | |
14712 | mips_trap = 0; | |
14713 | break; | |
14714 | ||
14715 | case OPTION_EB: | |
14716 | target_big_endian = 1; | |
14717 | break; | |
14718 | ||
14719 | case OPTION_EL: | |
14720 | target_big_endian = 0; | |
14721 | break; | |
14722 | ||
14723 | case 'O': | |
4ffff32f TS |
14724 | if (arg == NULL) |
14725 | mips_optimize = 1; | |
14726 | else if (arg[0] == '0') | |
14727 | mips_optimize = 0; | |
14728 | else if (arg[0] == '1') | |
252b5132 RH |
14729 | mips_optimize = 1; |
14730 | else | |
14731 | mips_optimize = 2; | |
14732 | break; | |
14733 | ||
14734 | case 'g': | |
14735 | if (arg == NULL) | |
14736 | mips_debug = 2; | |
14737 | else | |
14738 | mips_debug = atoi (arg); | |
252b5132 RH |
14739 | break; |
14740 | ||
14741 | case OPTION_MIPS1: | |
316f5878 | 14742 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14743 | break; |
14744 | ||
14745 | case OPTION_MIPS2: | |
316f5878 | 14746 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14747 | break; |
14748 | ||
14749 | case OPTION_MIPS3: | |
316f5878 | 14750 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14751 | break; |
14752 | ||
14753 | case OPTION_MIPS4: | |
316f5878 | 14754 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14755 | break; |
14756 | ||
84ea6cf2 | 14757 | case OPTION_MIPS5: |
316f5878 | 14758 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14759 | break; |
14760 | ||
e7af610e | 14761 | case OPTION_MIPS32: |
316f5878 | 14762 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14763 | break; |
14764 | ||
af7ee8bf CD |
14765 | case OPTION_MIPS32R2: |
14766 | file_mips_isa = ISA_MIPS32R2; | |
14767 | break; | |
14768 | ||
5f74bc13 CD |
14769 | case OPTION_MIPS64R2: |
14770 | file_mips_isa = ISA_MIPS64R2; | |
14771 | break; | |
14772 | ||
84ea6cf2 | 14773 | case OPTION_MIPS64: |
316f5878 | 14774 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14775 | break; |
14776 | ||
ec68c924 | 14777 | case OPTION_MTUNE: |
316f5878 RS |
14778 | mips_set_option_string (&mips_tune_string, arg); |
14779 | break; | |
ec68c924 | 14780 | |
316f5878 RS |
14781 | case OPTION_MARCH: |
14782 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14783 | break; |
14784 | ||
14785 | case OPTION_M4650: | |
316f5878 RS |
14786 | mips_set_option_string (&mips_arch_string, "4650"); |
14787 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14788 | break; |
14789 | ||
14790 | case OPTION_NO_M4650: | |
14791 | break; | |
14792 | ||
14793 | case OPTION_M4010: | |
316f5878 RS |
14794 | mips_set_option_string (&mips_arch_string, "4010"); |
14795 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14796 | break; |
14797 | ||
14798 | case OPTION_NO_M4010: | |
14799 | break; | |
14800 | ||
14801 | case OPTION_M4100: | |
316f5878 RS |
14802 | mips_set_option_string (&mips_arch_string, "4100"); |
14803 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14804 | break; |
14805 | ||
14806 | case OPTION_NO_M4100: | |
14807 | break; | |
14808 | ||
252b5132 | 14809 | case OPTION_M3900: |
316f5878 RS |
14810 | mips_set_option_string (&mips_arch_string, "3900"); |
14811 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14812 | break; |
bdaaa2e1 | 14813 | |
252b5132 RH |
14814 | case OPTION_NO_M3900: |
14815 | break; | |
14816 | ||
deec1734 CD |
14817 | case OPTION_MDMX: |
14818 | mips_opts.ase_mdmx = 1; | |
14819 | break; | |
14820 | ||
14821 | case OPTION_NO_MDMX: | |
14822 | mips_opts.ase_mdmx = 0; | |
14823 | break; | |
14824 | ||
74cd071d CF |
14825 | case OPTION_DSP: |
14826 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14827 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14828 | break; |
14829 | ||
14830 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14831 | mips_opts.ase_dsp = 0; |
14832 | mips_opts.ase_dspr2 = 0; | |
14833 | break; | |
14834 | ||
14835 | case OPTION_DSPR2: | |
14836 | mips_opts.ase_dspr2 = 1; | |
14837 | mips_opts.ase_dsp = 1; | |
14838 | break; | |
14839 | ||
14840 | case OPTION_NO_DSPR2: | |
14841 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14842 | mips_opts.ase_dsp = 0; |
14843 | break; | |
14844 | ||
ef2e4d86 CF |
14845 | case OPTION_MT: |
14846 | mips_opts.ase_mt = 1; | |
14847 | break; | |
14848 | ||
14849 | case OPTION_NO_MT: | |
14850 | mips_opts.ase_mt = 0; | |
14851 | break; | |
14852 | ||
dec0624d MR |
14853 | case OPTION_MCU: |
14854 | mips_opts.ase_mcu = 1; | |
14855 | break; | |
14856 | ||
14857 | case OPTION_NO_MCU: | |
14858 | mips_opts.ase_mcu = 0; | |
14859 | break; | |
14860 | ||
df58fc94 RS |
14861 | case OPTION_MICROMIPS: |
14862 | if (mips_opts.mips16 == 1) | |
14863 | { | |
14864 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14865 | return 0; | |
14866 | } | |
14867 | mips_opts.micromips = 1; | |
14868 | mips_no_prev_insn (); | |
14869 | break; | |
14870 | ||
14871 | case OPTION_NO_MICROMIPS: | |
14872 | mips_opts.micromips = 0; | |
14873 | mips_no_prev_insn (); | |
14874 | break; | |
14875 | ||
252b5132 | 14876 | case OPTION_MIPS16: |
df58fc94 RS |
14877 | if (mips_opts.micromips == 1) |
14878 | { | |
14879 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14880 | return 0; | |
14881 | } | |
252b5132 | 14882 | mips_opts.mips16 = 1; |
7d10b47d | 14883 | mips_no_prev_insn (); |
252b5132 RH |
14884 | break; |
14885 | ||
14886 | case OPTION_NO_MIPS16: | |
14887 | mips_opts.mips16 = 0; | |
7d10b47d | 14888 | mips_no_prev_insn (); |
252b5132 RH |
14889 | break; |
14890 | ||
1f25f5d3 CD |
14891 | case OPTION_MIPS3D: |
14892 | mips_opts.ase_mips3d = 1; | |
14893 | break; | |
14894 | ||
14895 | case OPTION_NO_MIPS3D: | |
14896 | mips_opts.ase_mips3d = 0; | |
14897 | break; | |
14898 | ||
e16bfa71 TS |
14899 | case OPTION_SMARTMIPS: |
14900 | mips_opts.ase_smartmips = 1; | |
14901 | break; | |
14902 | ||
14903 | case OPTION_NO_SMARTMIPS: | |
14904 | mips_opts.ase_smartmips = 0; | |
14905 | break; | |
14906 | ||
6a32d874 CM |
14907 | case OPTION_FIX_24K: |
14908 | mips_fix_24k = 1; | |
14909 | break; | |
14910 | ||
14911 | case OPTION_NO_FIX_24K: | |
14912 | mips_fix_24k = 0; | |
14913 | break; | |
14914 | ||
c67a084a NC |
14915 | case OPTION_FIX_LOONGSON2F_JUMP: |
14916 | mips_fix_loongson2f_jump = TRUE; | |
14917 | break; | |
14918 | ||
14919 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14920 | mips_fix_loongson2f_jump = FALSE; | |
14921 | break; | |
14922 | ||
14923 | case OPTION_FIX_LOONGSON2F_NOP: | |
14924 | mips_fix_loongson2f_nop = TRUE; | |
14925 | break; | |
14926 | ||
14927 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14928 | mips_fix_loongson2f_nop = FALSE; | |
14929 | break; | |
14930 | ||
d766e8ec RS |
14931 | case OPTION_FIX_VR4120: |
14932 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14933 | break; |
14934 | ||
d766e8ec RS |
14935 | case OPTION_NO_FIX_VR4120: |
14936 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14937 | break; |
14938 | ||
7d8e00cf RS |
14939 | case OPTION_FIX_VR4130: |
14940 | mips_fix_vr4130 = 1; | |
14941 | break; | |
14942 | ||
14943 | case OPTION_NO_FIX_VR4130: | |
14944 | mips_fix_vr4130 = 0; | |
14945 | break; | |
14946 | ||
d954098f DD |
14947 | case OPTION_FIX_CN63XXP1: |
14948 | mips_fix_cn63xxp1 = TRUE; | |
14949 | break; | |
14950 | ||
14951 | case OPTION_NO_FIX_CN63XXP1: | |
14952 | mips_fix_cn63xxp1 = FALSE; | |
14953 | break; | |
14954 | ||
4a6a3df4 AO |
14955 | case OPTION_RELAX_BRANCH: |
14956 | mips_relax_branch = 1; | |
14957 | break; | |
14958 | ||
14959 | case OPTION_NO_RELAX_BRANCH: | |
14960 | mips_relax_branch = 0; | |
14961 | break; | |
14962 | ||
aa6975fb ILT |
14963 | case OPTION_MSHARED: |
14964 | mips_in_shared = TRUE; | |
14965 | break; | |
14966 | ||
14967 | case OPTION_MNO_SHARED: | |
14968 | mips_in_shared = FALSE; | |
14969 | break; | |
14970 | ||
aed1a261 RS |
14971 | case OPTION_MSYM32: |
14972 | mips_opts.sym32 = TRUE; | |
14973 | break; | |
14974 | ||
14975 | case OPTION_MNO_SYM32: | |
14976 | mips_opts.sym32 = FALSE; | |
14977 | break; | |
14978 | ||
0f074f60 | 14979 | #ifdef OBJ_ELF |
252b5132 RH |
14980 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14981 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14982 | intended to be compatible with Irix 5. */ | |
14983 | case OPTION_CALL_SHARED: | |
f43abd2b | 14984 | if (!IS_ELF) |
252b5132 RH |
14985 | { |
14986 | as_bad (_("-call_shared is supported only for ELF format")); | |
14987 | return 0; | |
14988 | } | |
14989 | mips_pic = SVR4_PIC; | |
143d77c5 | 14990 | mips_abicalls = TRUE; |
252b5132 RH |
14991 | break; |
14992 | ||
861fb55a DJ |
14993 | case OPTION_CALL_NONPIC: |
14994 | if (!IS_ELF) | |
14995 | { | |
14996 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14997 | return 0; | |
14998 | } | |
14999 | mips_pic = NO_PIC; | |
15000 | mips_abicalls = TRUE; | |
15001 | break; | |
15002 | ||
252b5132 | 15003 | case OPTION_NON_SHARED: |
f43abd2b | 15004 | if (!IS_ELF) |
252b5132 RH |
15005 | { |
15006 | as_bad (_("-non_shared is supported only for ELF format")); | |
15007 | return 0; | |
15008 | } | |
15009 | mips_pic = NO_PIC; | |
143d77c5 | 15010 | mips_abicalls = FALSE; |
252b5132 RH |
15011 | break; |
15012 | ||
44075ae2 TS |
15013 | /* The -xgot option tells the assembler to use 32 bit offsets |
15014 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15015 | compatibility. */ |
15016 | case OPTION_XGOT: | |
15017 | mips_big_got = 1; | |
15018 | break; | |
0f074f60 | 15019 | #endif /* OBJ_ELF */ |
252b5132 RH |
15020 | |
15021 | case 'G': | |
6caf9ef4 TS |
15022 | g_switch_value = atoi (arg); |
15023 | g_switch_seen = 1; | |
252b5132 RH |
15024 | break; |
15025 | ||
34ba82a8 TS |
15026 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15027 | and -mabi=64. */ | |
252b5132 | 15028 | case OPTION_32: |
23fce1e3 NC |
15029 | if (IS_ELF) |
15030 | mips_abi = O32_ABI; | |
15031 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15032 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15033 | break; |
15034 | ||
23fce1e3 | 15035 | #ifdef OBJ_ELF |
e013f690 | 15036 | case OPTION_N32: |
f43abd2b | 15037 | if (!IS_ELF) |
34ba82a8 TS |
15038 | { |
15039 | as_bad (_("-n32 is supported for ELF format only")); | |
15040 | return 0; | |
15041 | } | |
316f5878 | 15042 | mips_abi = N32_ABI; |
e013f690 | 15043 | break; |
252b5132 | 15044 | |
e013f690 | 15045 | case OPTION_64: |
f43abd2b | 15046 | if (!IS_ELF) |
34ba82a8 TS |
15047 | { |
15048 | as_bad (_("-64 is supported for ELF format only")); | |
15049 | return 0; | |
15050 | } | |
316f5878 | 15051 | mips_abi = N64_ABI; |
f43abd2b | 15052 | if (!support_64bit_objects()) |
e013f690 | 15053 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15054 | break; |
ae948b86 | 15055 | #endif /* OBJ_ELF */ |
252b5132 | 15056 | |
c97ef257 | 15057 | case OPTION_GP32: |
a325df1d | 15058 | file_mips_gp32 = 1; |
c97ef257 AH |
15059 | break; |
15060 | ||
15061 | case OPTION_GP64: | |
a325df1d | 15062 | file_mips_gp32 = 0; |
c97ef257 | 15063 | break; |
252b5132 | 15064 | |
ca4e0257 | 15065 | case OPTION_FP32: |
a325df1d | 15066 | file_mips_fp32 = 1; |
316f5878 RS |
15067 | break; |
15068 | ||
15069 | case OPTION_FP64: | |
15070 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15071 | break; |
15072 | ||
037b32b9 AN |
15073 | case OPTION_SINGLE_FLOAT: |
15074 | file_mips_single_float = 1; | |
15075 | break; | |
15076 | ||
15077 | case OPTION_DOUBLE_FLOAT: | |
15078 | file_mips_single_float = 0; | |
15079 | break; | |
15080 | ||
15081 | case OPTION_SOFT_FLOAT: | |
15082 | file_mips_soft_float = 1; | |
15083 | break; | |
15084 | ||
15085 | case OPTION_HARD_FLOAT: | |
15086 | file_mips_soft_float = 0; | |
15087 | break; | |
15088 | ||
ae948b86 | 15089 | #ifdef OBJ_ELF |
252b5132 | 15090 | case OPTION_MABI: |
f43abd2b | 15091 | if (!IS_ELF) |
34ba82a8 TS |
15092 | { |
15093 | as_bad (_("-mabi is supported for ELF format only")); | |
15094 | return 0; | |
15095 | } | |
e013f690 | 15096 | if (strcmp (arg, "32") == 0) |
316f5878 | 15097 | mips_abi = O32_ABI; |
e013f690 | 15098 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15099 | mips_abi = O64_ABI; |
e013f690 | 15100 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15101 | mips_abi = N32_ABI; |
e013f690 TS |
15102 | else if (strcmp (arg, "64") == 0) |
15103 | { | |
316f5878 | 15104 | mips_abi = N64_ABI; |
e013f690 TS |
15105 | if (! support_64bit_objects()) |
15106 | as_fatal (_("No compiled in support for 64 bit object file " | |
15107 | "format")); | |
15108 | } | |
15109 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15110 | mips_abi = EABI_ABI; |
e013f690 | 15111 | else |
da0e507f TS |
15112 | { |
15113 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15114 | return 0; | |
15115 | } | |
252b5132 | 15116 | break; |
e013f690 | 15117 | #endif /* OBJ_ELF */ |
252b5132 | 15118 | |
6b76fefe | 15119 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15120 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15121 | break; |
15122 | ||
9ee72ff1 | 15123 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15124 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15125 | break; |
15126 | ||
ecb4347a DJ |
15127 | #ifdef OBJ_ELF |
15128 | case OPTION_MDEBUG: | |
b34976b6 | 15129 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15130 | break; |
15131 | ||
15132 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15133 | mips_flag_mdebug = FALSE; |
ecb4347a | 15134 | break; |
dcd410fe RO |
15135 | |
15136 | case OPTION_PDR: | |
15137 | mips_flag_pdr = TRUE; | |
15138 | break; | |
15139 | ||
15140 | case OPTION_NO_PDR: | |
15141 | mips_flag_pdr = FALSE; | |
15142 | break; | |
0a44bf69 RS |
15143 | |
15144 | case OPTION_MVXWORKS_PIC: | |
15145 | mips_pic = VXWORKS_PIC; | |
15146 | break; | |
ecb4347a DJ |
15147 | #endif /* OBJ_ELF */ |
15148 | ||
252b5132 RH |
15149 | default: |
15150 | return 0; | |
15151 | } | |
15152 | ||
c67a084a NC |
15153 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15154 | ||
252b5132 RH |
15155 | return 1; |
15156 | } | |
316f5878 RS |
15157 | \f |
15158 | /* Set up globals to generate code for the ISA or processor | |
15159 | described by INFO. */ | |
252b5132 | 15160 | |
252b5132 | 15161 | static void |
17a2f251 | 15162 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15163 | { |
316f5878 | 15164 | if (info != 0) |
252b5132 | 15165 | { |
fef14a42 TS |
15166 | file_mips_arch = info->cpu; |
15167 | mips_opts.arch = info->cpu; | |
316f5878 | 15168 | mips_opts.isa = info->isa; |
252b5132 | 15169 | } |
252b5132 RH |
15170 | } |
15171 | ||
252b5132 | 15172 | |
316f5878 | 15173 | /* Likewise for tuning. */ |
252b5132 | 15174 | |
316f5878 | 15175 | static void |
17a2f251 | 15176 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15177 | { |
15178 | if (info != 0) | |
fef14a42 | 15179 | mips_tune = info->cpu; |
316f5878 | 15180 | } |
80cc45a5 | 15181 | |
34ba82a8 | 15182 | |
252b5132 | 15183 | void |
17a2f251 | 15184 | mips_after_parse_args (void) |
e9670677 | 15185 | { |
fef14a42 TS |
15186 | const struct mips_cpu_info *arch_info = 0; |
15187 | const struct mips_cpu_info *tune_info = 0; | |
15188 | ||
e9670677 | 15189 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15190 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15191 | { |
6caf9ef4 | 15192 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15193 | as_bad (_("-G not supported in this configuration.")); |
15194 | g_switch_value = 0; | |
15195 | } | |
15196 | ||
cac012d6 AO |
15197 | if (mips_abi == NO_ABI) |
15198 | mips_abi = MIPS_DEFAULT_ABI; | |
15199 | ||
22923709 RS |
15200 | /* The following code determines the architecture and register size. |
15201 | Similar code was added to GCC 3.3 (see override_options() in | |
15202 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15203 | as much as possible. */ | |
e9670677 | 15204 | |
316f5878 | 15205 | if (mips_arch_string != 0) |
fef14a42 | 15206 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15207 | |
316f5878 | 15208 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15209 | { |
316f5878 | 15210 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15211 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15212 | the -march selection (if any). */ |
fef14a42 | 15213 | if (arch_info != 0) |
e9670677 | 15214 | { |
316f5878 RS |
15215 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15216 | There's no harm in specifying both as long as the ISA levels | |
15217 | are the same. */ | |
fef14a42 | 15218 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15219 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15220 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15221 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15222 | } |
316f5878 | 15223 | else |
fef14a42 | 15224 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15225 | } |
15226 | ||
fef14a42 | 15227 | if (arch_info == 0) |
95bfe26e MF |
15228 | { |
15229 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15230 | gas_assert (arch_info); | |
15231 | } | |
e9670677 | 15232 | |
fef14a42 | 15233 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15234 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15235 | arch_info->name); |
15236 | ||
15237 | mips_set_architecture (arch_info); | |
15238 | ||
15239 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15240 | if (mips_tune_string != 0) | |
15241 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15242 | |
fef14a42 TS |
15243 | if (tune_info == 0) |
15244 | mips_set_tune (arch_info); | |
15245 | else | |
15246 | mips_set_tune (tune_info); | |
e9670677 | 15247 | |
316f5878 | 15248 | if (file_mips_gp32 >= 0) |
e9670677 | 15249 | { |
316f5878 RS |
15250 | /* The user specified the size of the integer registers. Make sure |
15251 | it agrees with the ABI and ISA. */ | |
15252 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15253 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15254 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15255 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15256 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15257 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15258 | } |
15259 | else | |
15260 | { | |
316f5878 RS |
15261 | /* Infer the integer register size from the ABI and processor. |
15262 | Restrict ourselves to 32-bit registers if that's all the | |
15263 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15264 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15265 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15266 | } |
15267 | ||
ad3fea08 TS |
15268 | switch (file_mips_fp32) |
15269 | { | |
15270 | default: | |
15271 | case -1: | |
15272 | /* No user specified float register size. | |
15273 | ??? GAS treats single-float processors as though they had 64-bit | |
15274 | float registers (although it complains when double-precision | |
15275 | instructions are used). As things stand, saying they have 32-bit | |
15276 | registers would lead to spurious "register must be even" messages. | |
15277 | So here we assume float registers are never smaller than the | |
15278 | integer ones. */ | |
15279 | if (file_mips_gp32 == 0) | |
15280 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15281 | file_mips_fp32 = 0; | |
15282 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15283 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15284 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15285 | file_mips_fp32 = 0; | |
15286 | else | |
15287 | /* 32-bit float registers. */ | |
15288 | file_mips_fp32 = 1; | |
15289 | break; | |
15290 | ||
15291 | /* The user specified the size of the float registers. Check if it | |
15292 | agrees with the ABI and ISA. */ | |
15293 | case 0: | |
15294 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15295 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15296 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15297 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15298 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15299 | break; | |
15300 | case 1: | |
15301 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15302 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15303 | break; | |
15304 | } | |
e9670677 | 15305 | |
316f5878 | 15306 | /* End of GCC-shared inference code. */ |
e9670677 | 15307 | |
17a2f251 TS |
15308 | /* This flag is set when we have a 64-bit capable CPU but use only |
15309 | 32-bit wide registers. Note that EABI does not use it. */ | |
15310 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15311 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15312 | || mips_abi == O32_ABI)) | |
316f5878 | 15313 | mips_32bitmode = 1; |
e9670677 MR |
15314 | |
15315 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15316 | as_bad (_("trap exception not supported at ISA 1")); | |
15317 | ||
e9670677 MR |
15318 | /* If the selected architecture includes support for ASEs, enable |
15319 | generation of code for them. */ | |
a4672219 | 15320 | if (mips_opts.mips16 == -1) |
fef14a42 | 15321 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15322 | if (mips_opts.micromips == -1) |
15323 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15324 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15325 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15326 | && file_mips_fp32 == 0) ? 1 : 0; |
15327 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15328 | as_bad (_("-mfp32 used with -mips3d")); | |
15329 | ||
ffdefa66 | 15330 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15331 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15332 | && file_mips_fp32 == 0) ? 1 : 0; |
15333 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15334 | as_bad (_("-mfp32 used with -mdmx")); | |
15335 | ||
15336 | if (mips_opts.ase_smartmips == -1) | |
15337 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15338 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15339 | as_warn (_("%s ISA does not support SmartMIPS"), |
15340 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15341 | |
74cd071d | 15342 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15343 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15344 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15345 | as_warn (_("%s ISA does not support DSP ASE"), |
15346 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15347 | |
8b082fb1 TS |
15348 | if (mips_opts.ase_dspr2 == -1) |
15349 | { | |
15350 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15351 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15352 | } | |
15353 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15354 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15355 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15356 | |
ef2e4d86 | 15357 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15358 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15359 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15360 | as_warn (_("%s ISA does not support MT ASE"), |
15361 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15362 | |
dec0624d MR |
15363 | if (mips_opts.ase_mcu == -1) |
15364 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15365 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15366 | as_warn (_("%s ISA does not support MCU ASE"), | |
15367 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15368 | ||
e9670677 | 15369 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15370 | file_ase_mips3d = mips_opts.ase_mips3d; |
15371 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15372 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15373 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15374 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15375 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15376 | mips_opts.gp32 = file_mips_gp32; |
15377 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15378 | mips_opts.soft_float = file_mips_soft_float; |
15379 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15380 | |
ecb4347a DJ |
15381 | if (mips_flag_mdebug < 0) |
15382 | { | |
15383 | #ifdef OBJ_MAYBE_ECOFF | |
15384 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15385 | mips_flag_mdebug = 1; | |
15386 | else | |
15387 | #endif /* OBJ_MAYBE_ECOFF */ | |
15388 | mips_flag_mdebug = 0; | |
15389 | } | |
e9670677 MR |
15390 | } |
15391 | \f | |
15392 | void | |
17a2f251 | 15393 | mips_init_after_args (void) |
252b5132 RH |
15394 | { |
15395 | /* initialize opcodes */ | |
15396 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15397 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15398 | } |
15399 | ||
15400 | long | |
17a2f251 | 15401 | md_pcrel_from (fixS *fixP) |
252b5132 | 15402 | { |
a7ebbfdf TS |
15403 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15404 | switch (fixP->fx_r_type) | |
15405 | { | |
df58fc94 RS |
15406 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15407 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15408 | /* Return the address of the delay slot. */ | |
15409 | return addr + 2; | |
15410 | ||
15411 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15412 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15413 | case BFD_RELOC_16_PCREL_S2: |
15414 | case BFD_RELOC_MIPS_JMP: | |
15415 | /* Return the address of the delay slot. */ | |
15416 | return addr + 4; | |
df58fc94 | 15417 | |
a7ebbfdf | 15418 | default: |
58ea3d6a | 15419 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15420 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15421 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15422 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15423 | return addr; |
15424 | } | |
252b5132 RH |
15425 | } |
15426 | ||
252b5132 RH |
15427 | /* This is called before the symbol table is processed. In order to |
15428 | work with gcc when using mips-tfile, we must keep all local labels. | |
15429 | However, in other cases, we want to discard them. If we were | |
15430 | called with -g, but we didn't see any debugging information, it may | |
15431 | mean that gcc is smuggling debugging information through to | |
15432 | mips-tfile, in which case we must generate all local labels. */ | |
15433 | ||
15434 | void | |
17a2f251 | 15435 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15436 | { |
15437 | #ifndef NO_ECOFF_DEBUGGING | |
15438 | if (ECOFF_DEBUGGING | |
15439 | && mips_debug != 0 | |
15440 | && ! ecoff_debugging_seen) | |
15441 | flag_keep_locals = 1; | |
15442 | #endif | |
15443 | } | |
15444 | ||
3b91255e | 15445 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15446 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15447 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15448 | relocation operators. | |
15449 | ||
15450 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15451 | expression if: | |
15452 | ||
15453 | (a) it refers to the same symbol; and | |
15454 | (b) the offset applied in the %lo() expression is no lower than | |
15455 | the offset applied in the %got() or %hi(). | |
15456 | ||
15457 | (b) allows us to cope with code like: | |
15458 | ||
15459 | lui $4,%hi(foo) | |
15460 | lh $4,%lo(foo+2)($4) | |
15461 | ||
15462 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15463 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15464 | the high 16 bits. | |
15465 | ||
15466 | When several %lo()s match a particular %got() or %hi(), we use the | |
15467 | following rules to distinguish them: | |
15468 | ||
15469 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15470 | higher offsets. | |
15471 | ||
15472 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15473 | that already have a matching %got() or %hi(). | |
15474 | ||
15475 | (3) later %lo()s are better than earlier %lo()s. | |
15476 | ||
15477 | These rules are applied in order. | |
15478 | ||
15479 | (1) means, among other things, that %lo()s with identical offsets are | |
15480 | chosen if they exist. | |
15481 | ||
15482 | (2) means that we won't associate several high-part relocations with | |
15483 | the same low-part relocation unless there's no alternative. Having | |
15484 | several high parts for the same low part is a GNU extension; this rule | |
15485 | allows careful users to avoid it. | |
15486 | ||
15487 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15488 | with the last high-part relocation being at the front of the list. | |
15489 | It therefore makes sense to choose the last matching low-part | |
15490 | relocation, all other things being equal. It's also easier | |
15491 | to code that way. */ | |
252b5132 RH |
15492 | |
15493 | void | |
17a2f251 | 15494 | mips_frob_file (void) |
252b5132 RH |
15495 | { |
15496 | struct mips_hi_fixup *l; | |
35903be0 | 15497 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15498 | |
15499 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15500 | { | |
15501 | segment_info_type *seginfo; | |
3b91255e RS |
15502 | bfd_boolean matched_lo_p; |
15503 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15504 | |
9c2799c2 | 15505 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15506 | |
5919d012 | 15507 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15508 | there isn't supposed to be a matching LO. Ignore %gots against |
15509 | constants; we'll report an error for those later. */ | |
738e5348 | 15510 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15511 | && !(l->fixp->fx_addsy |
15512 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15513 | continue; |
15514 | ||
15515 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15516 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15517 | continue; |
15518 | ||
252b5132 | 15519 | seginfo = seg_info (l->seg); |
252b5132 | 15520 | |
3b91255e RS |
15521 | /* Set HI_POS to the position of this relocation in the chain. |
15522 | Set LO_POS to the position of the chosen low-part relocation. | |
15523 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15524 | relocation that matches an immediately-preceding high-part | |
15525 | relocation. */ | |
15526 | hi_pos = NULL; | |
15527 | lo_pos = NULL; | |
15528 | matched_lo_p = FALSE; | |
738e5348 | 15529 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15530 | |
3b91255e RS |
15531 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15532 | { | |
15533 | if (*pos == l->fixp) | |
15534 | hi_pos = pos; | |
15535 | ||
35903be0 | 15536 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15537 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15538 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15539 | && (lo_pos == NULL | |
15540 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15541 | || (!matched_lo_p | |
15542 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15543 | lo_pos = pos; | |
15544 | ||
15545 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15546 | && fixup_has_matching_lo_p (*pos)); | |
15547 | } | |
15548 | ||
15549 | /* If we found a match, remove the high-part relocation from its | |
15550 | current position and insert it before the low-part relocation. | |
15551 | Make the offsets match so that fixup_has_matching_lo_p() | |
15552 | will return true. | |
15553 | ||
15554 | We don't warn about unmatched high-part relocations since some | |
15555 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15556 | instructions. */ | |
15557 | if (lo_pos != NULL) | |
15558 | { | |
15559 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15560 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15561 | { |
3b91255e RS |
15562 | *hi_pos = l->fixp->fx_next; |
15563 | l->fixp->fx_next = *lo_pos; | |
15564 | *lo_pos = l->fixp; | |
252b5132 | 15565 | } |
252b5132 RH |
15566 | } |
15567 | } | |
15568 | } | |
15569 | ||
252b5132 | 15570 | int |
17a2f251 | 15571 | mips_force_relocation (fixS *fixp) |
252b5132 | 15572 | { |
ae6063d4 | 15573 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15574 | return 1; |
15575 | ||
df58fc94 RS |
15576 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15577 | so that the linker relaxation can update targets. */ | |
15578 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15579 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15580 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15581 | return 1; | |
15582 | ||
3e722fb5 | 15583 | return 0; |
252b5132 RH |
15584 | } |
15585 | ||
b886a2ab RS |
15586 | /* Read the instruction associated with RELOC from BUF. */ |
15587 | ||
15588 | static unsigned int | |
15589 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15590 | { | |
15591 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15592 | return read_compressed_insn (buf, 4); | |
15593 | else | |
15594 | return read_insn (buf); | |
15595 | } | |
15596 | ||
15597 | /* Write instruction INSN to BUF, given that it has been relocated | |
15598 | by RELOC. */ | |
15599 | ||
15600 | static void | |
15601 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15602 | unsigned long insn) | |
15603 | { | |
15604 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15605 | write_compressed_insn (buf, insn, 4); | |
15606 | else | |
15607 | write_insn (buf, insn); | |
15608 | } | |
15609 | ||
252b5132 RH |
15610 | /* Apply a fixup to the object file. */ |
15611 | ||
94f592af | 15612 | void |
55cf6793 | 15613 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15614 | { |
4d68580a | 15615 | char *buf; |
b886a2ab | 15616 | unsigned long insn; |
a7ebbfdf | 15617 | reloc_howto_type *howto; |
252b5132 | 15618 | |
a7ebbfdf TS |
15619 | /* We ignore generic BFD relocations we don't know about. */ |
15620 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15621 | if (! howto) | |
15622 | return; | |
65551fa4 | 15623 | |
df58fc94 RS |
15624 | gas_assert (fixP->fx_size == 2 |
15625 | || fixP->fx_size == 4 | |
90ecf173 MR |
15626 | || fixP->fx_r_type == BFD_RELOC_16 |
15627 | || fixP->fx_r_type == BFD_RELOC_64 | |
15628 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15629 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15630 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15631 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15632 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15633 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15634 | |
4d68580a | 15635 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15636 | |
df58fc94 RS |
15637 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15638 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15639 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15640 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15641 | |
15642 | /* Don't treat parts of a composite relocation as done. There are two | |
15643 | reasons for this: | |
15644 | ||
15645 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15646 | should nevertheless be emitted if the first part is. | |
15647 | ||
15648 | (2) In normal usage, composite relocations are never assembly-time | |
15649 | constants. The easiest way of dealing with the pathological | |
15650 | exceptions is to generate a relocation against STN_UNDEF and | |
15651 | leave everything up to the linker. */ | |
3994f87e | 15652 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15653 | fixP->fx_done = 1; |
15654 | ||
15655 | switch (fixP->fx_r_type) | |
15656 | { | |
3f98094e DJ |
15657 | case BFD_RELOC_MIPS_TLS_GD: |
15658 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15659 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15660 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15661 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15662 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15663 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15664 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15665 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15666 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15667 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15668 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15669 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15670 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15671 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15672 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15673 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15674 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15675 | case BFD_RELOC_MIPS16_TLS_GD: |
15676 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15677 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15678 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15679 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15680 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15681 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15682 | if (!fixP->fx_addsy) |
15683 | { | |
15684 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15685 | _("TLS relocation against a constant")); | |
15686 | break; | |
15687 | } | |
3f98094e DJ |
15688 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15689 | /* fall through */ | |
15690 | ||
252b5132 | 15691 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15692 | case BFD_RELOC_MIPS_SHIFT5: |
15693 | case BFD_RELOC_MIPS_SHIFT6: | |
15694 | case BFD_RELOC_MIPS_GOT_DISP: | |
15695 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15696 | case BFD_RELOC_MIPS_GOT_OFST: | |
15697 | case BFD_RELOC_MIPS_SUB: | |
15698 | case BFD_RELOC_MIPS_INSERT_A: | |
15699 | case BFD_RELOC_MIPS_INSERT_B: | |
15700 | case BFD_RELOC_MIPS_DELETE: | |
15701 | case BFD_RELOC_MIPS_HIGHEST: | |
15702 | case BFD_RELOC_MIPS_HIGHER: | |
15703 | case BFD_RELOC_MIPS_SCN_DISP: | |
15704 | case BFD_RELOC_MIPS_REL16: | |
15705 | case BFD_RELOC_MIPS_RELGOT: | |
15706 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15707 | case BFD_RELOC_HI16: |
15708 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15709 | case BFD_RELOC_LO16: |
cdf6fd85 | 15710 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15711 | case BFD_RELOC_MIPS_LITERAL: |
15712 | case BFD_RELOC_MIPS_CALL16: | |
15713 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15714 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15715 | case BFD_RELOC_MIPS_GOT_HI16: |
15716 | case BFD_RELOC_MIPS_GOT_LO16: | |
15717 | case BFD_RELOC_MIPS_CALL_HI16: | |
15718 | case BFD_RELOC_MIPS_CALL_LO16: | |
15719 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15720 | case BFD_RELOC_MIPS16_GOT16: |
15721 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15722 | case BFD_RELOC_MIPS16_HI16: |
15723 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15724 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15725 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15726 | case BFD_RELOC_MICROMIPS_JMP: |
15727 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15728 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15729 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15730 | case BFD_RELOC_MICROMIPS_SUB: | |
15731 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15732 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15733 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15734 | case BFD_RELOC_MICROMIPS_JALR: | |
15735 | case BFD_RELOC_MICROMIPS_HI16: | |
15736 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15737 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15738 | case BFD_RELOC_MICROMIPS_GPREL16: |
15739 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15740 | case BFD_RELOC_MICROMIPS_CALL16: | |
15741 | case BFD_RELOC_MICROMIPS_GOT16: | |
15742 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15743 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15744 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15745 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
b886a2ab RS |
15746 | if (fixP->fx_done) |
15747 | { | |
15748 | offsetT value; | |
15749 | ||
15750 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15751 | { | |
15752 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15753 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15754 | insn |= mips16_immed_extend (value, 16); | |
15755 | else | |
15756 | insn |= (value & 0xffff); | |
15757 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15758 | } | |
15759 | else | |
15760 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15761 | _("Unsupported constant in relocation")); | |
15762 | } | |
252b5132 RH |
15763 | break; |
15764 | ||
252b5132 RH |
15765 | case BFD_RELOC_64: |
15766 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15767 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15768 | if (fixP->fx_done) |
252b5132 RH |
15769 | { |
15770 | if (8 <= sizeof (valueT)) | |
4d68580a | 15771 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15772 | else |
15773 | { | |
a7ebbfdf | 15774 | valueT hiv; |
252b5132 | 15775 | |
a7ebbfdf | 15776 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15777 | hiv = 0xffffffff; |
15778 | else | |
15779 | hiv = 0; | |
4d68580a RS |
15780 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15781 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15782 | } |
15783 | } | |
15784 | break; | |
15785 | ||
056350c6 | 15786 | case BFD_RELOC_RVA: |
252b5132 | 15787 | case BFD_RELOC_32: |
252b5132 RH |
15788 | case BFD_RELOC_16: |
15789 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15790 | value now. This can happen if we have a .word which is not |
15791 | resolved when it appears but is later defined. */ | |
252b5132 | 15792 | if (fixP->fx_done) |
4d68580a | 15793 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15794 | break; |
15795 | ||
252b5132 | 15796 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15797 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15798 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15799 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15800 | |
54f4ddb3 TS |
15801 | /* We need to save the bits in the instruction since fixup_segment() |
15802 | might be deleting the relocation entry (i.e., a branch within | |
15803 | the current segment). */ | |
a7ebbfdf | 15804 | if (! fixP->fx_done) |
bb2d6cd7 | 15805 | break; |
252b5132 | 15806 | |
54f4ddb3 | 15807 | /* Update old instruction data. */ |
4d68580a | 15808 | insn = read_insn (buf); |
252b5132 | 15809 | |
a7ebbfdf TS |
15810 | if (*valP + 0x20000 <= 0x3ffff) |
15811 | { | |
15812 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15813 | write_insn (buf, insn); |
a7ebbfdf TS |
15814 | } |
15815 | else if (mips_pic == NO_PIC | |
15816 | && fixP->fx_done | |
15817 | && fixP->fx_frag->fr_address >= text_section->vma | |
15818 | && (fixP->fx_frag->fr_address | |
587aac4e | 15819 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15820 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15821 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15822 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15823 | { |
15824 | /* The branch offset is too large. If this is an | |
15825 | unconditional branch, and we are not generating PIC code, | |
15826 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15827 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15828 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15829 | else |
a7ebbfdf TS |
15830 | insn = 0x08000000; /* j */ |
15831 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15832 | fixP->fx_done = 0; | |
15833 | fixP->fx_addsy = section_symbol (text_section); | |
15834 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15835 | write_insn (buf, insn); |
a7ebbfdf TS |
15836 | } |
15837 | else | |
15838 | { | |
15839 | /* If we got here, we have branch-relaxation disabled, | |
15840 | and there's nothing we can do to fix this instruction | |
15841 | without turning it into a longer sequence. */ | |
15842 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15843 | _("Branch out of range")); | |
252b5132 | 15844 | } |
252b5132 RH |
15845 | break; |
15846 | ||
df58fc94 RS |
15847 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15848 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15849 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15850 | /* We adjust the offset back to even. */ | |
15851 | if ((*valP & 0x1) != 0) | |
15852 | --(*valP); | |
15853 | ||
15854 | if (! fixP->fx_done) | |
15855 | break; | |
15856 | ||
15857 | /* Should never visit here, because we keep the relocation. */ | |
15858 | abort (); | |
15859 | break; | |
15860 | ||
252b5132 RH |
15861 | case BFD_RELOC_VTABLE_INHERIT: |
15862 | fixP->fx_done = 0; | |
15863 | if (fixP->fx_addsy | |
15864 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15865 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15866 | S_SET_WEAK (fixP->fx_addsy); | |
15867 | break; | |
15868 | ||
15869 | case BFD_RELOC_VTABLE_ENTRY: | |
15870 | fixP->fx_done = 0; | |
15871 | break; | |
15872 | ||
15873 | default: | |
b37df7c4 | 15874 | abort (); |
252b5132 | 15875 | } |
a7ebbfdf TS |
15876 | |
15877 | /* Remember value for tc_gen_reloc. */ | |
15878 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15879 | } |
15880 | ||
252b5132 | 15881 | static symbolS * |
17a2f251 | 15882 | get_symbol (void) |
252b5132 RH |
15883 | { |
15884 | int c; | |
15885 | char *name; | |
15886 | symbolS *p; | |
15887 | ||
15888 | name = input_line_pointer; | |
15889 | c = get_symbol_end (); | |
15890 | p = (symbolS *) symbol_find_or_make (name); | |
15891 | *input_line_pointer = c; | |
15892 | return p; | |
15893 | } | |
15894 | ||
742a56fe RS |
15895 | /* Align the current frag to a given power of two. If a particular |
15896 | fill byte should be used, FILL points to an integer that contains | |
15897 | that byte, otherwise FILL is null. | |
15898 | ||
462427c4 RS |
15899 | This function used to have the comment: |
15900 | ||
15901 | The MIPS assembler also automatically adjusts any preceding label. | |
15902 | ||
15903 | The implementation therefore applied the adjustment to a maximum of | |
15904 | one label. However, other label adjustments are applied to batches | |
15905 | of labels, and adjusting just one caused problems when new labels | |
15906 | were added for the sake of debugging or unwind information. | |
15907 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15908 | |
15909 | static void | |
462427c4 | 15910 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15911 | { |
7d10b47d | 15912 | mips_emit_delays (); |
df58fc94 | 15913 | mips_record_compressed_mode (); |
742a56fe RS |
15914 | if (fill == NULL && subseg_text_p (now_seg)) |
15915 | frag_align_code (to, 0); | |
15916 | else | |
15917 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15918 | record_alignment (now_seg, to); |
462427c4 | 15919 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15920 | } |
15921 | ||
15922 | /* Align to a given power of two. .align 0 turns off the automatic | |
15923 | alignment used by the data creating pseudo-ops. */ | |
15924 | ||
15925 | static void | |
17a2f251 | 15926 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15927 | { |
742a56fe | 15928 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15929 | long max_alignment = 28; |
252b5132 | 15930 | |
54f4ddb3 | 15931 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15932 | to the aligned address. |
54f4ddb3 | 15933 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15934 | a .align pseudo instruction. |
54f4ddb3 | 15935 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15936 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15937 | We don't. */ |
252b5132 RH |
15938 | |
15939 | temp = get_absolute_expression (); | |
15940 | if (temp > max_alignment) | |
15941 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15942 | else if (temp < 0) | |
15943 | { | |
15944 | as_warn (_("Alignment negative: 0 assumed.")); | |
15945 | temp = 0; | |
15946 | } | |
15947 | if (*input_line_pointer == ',') | |
15948 | { | |
f9419b05 | 15949 | ++input_line_pointer; |
742a56fe RS |
15950 | fill_value = get_absolute_expression (); |
15951 | fill_ptr = &fill_value; | |
252b5132 RH |
15952 | } |
15953 | else | |
742a56fe | 15954 | fill_ptr = 0; |
252b5132 RH |
15955 | if (temp) |
15956 | { | |
a8dbcb85 TS |
15957 | segment_info_type *si = seg_info (now_seg); |
15958 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15959 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15960 | auto_align = 1; |
462427c4 | 15961 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15962 | } |
15963 | else | |
15964 | { | |
15965 | auto_align = 0; | |
15966 | } | |
15967 | ||
15968 | demand_empty_rest_of_line (); | |
15969 | } | |
15970 | ||
252b5132 | 15971 | static void |
17a2f251 | 15972 | s_change_sec (int sec) |
252b5132 RH |
15973 | { |
15974 | segT seg; | |
15975 | ||
252b5132 RH |
15976 | #ifdef OBJ_ELF |
15977 | /* The ELF backend needs to know that we are changing sections, so | |
15978 | that .previous works correctly. We could do something like check | |
b6ff326e | 15979 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15980 | as it would not be appropriate to use it in the section changing |
15981 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15982 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15983 | if (IS_ELF) |
15984 | obj_elf_section_change_hook (); | |
252b5132 RH |
15985 | #endif |
15986 | ||
7d10b47d | 15987 | mips_emit_delays (); |
6a32d874 | 15988 | |
252b5132 RH |
15989 | switch (sec) |
15990 | { | |
15991 | case 't': | |
15992 | s_text (0); | |
15993 | break; | |
15994 | case 'd': | |
15995 | s_data (0); | |
15996 | break; | |
15997 | case 'b': | |
15998 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15999 | demand_empty_rest_of_line (); | |
16000 | break; | |
16001 | ||
16002 | case 'r': | |
4d0d148d TS |
16003 | seg = subseg_new (RDATA_SECTION_NAME, |
16004 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16005 | if (IS_ELF) |
252b5132 | 16006 | { |
4d0d148d TS |
16007 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16008 | | SEC_READONLY | SEC_RELOC | |
16009 | | SEC_DATA)); | |
c41e87e3 | 16010 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16011 | record_alignment (seg, 4); |
252b5132 | 16012 | } |
4d0d148d | 16013 | demand_empty_rest_of_line (); |
252b5132 RH |
16014 | break; |
16015 | ||
16016 | case 's': | |
4d0d148d | 16017 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16018 | if (IS_ELF) |
252b5132 | 16019 | { |
4d0d148d TS |
16020 | bfd_set_section_flags (stdoutput, seg, |
16021 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16022 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16023 | record_alignment (seg, 4); |
252b5132 | 16024 | } |
4d0d148d TS |
16025 | demand_empty_rest_of_line (); |
16026 | break; | |
998b3c36 MR |
16027 | |
16028 | case 'B': | |
16029 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16030 | if (IS_ELF) | |
16031 | { | |
16032 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16033 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16034 | record_alignment (seg, 4); | |
16035 | } | |
16036 | demand_empty_rest_of_line (); | |
16037 | break; | |
252b5132 RH |
16038 | } |
16039 | ||
16040 | auto_align = 1; | |
16041 | } | |
b34976b6 | 16042 | |
cca86cc8 | 16043 | void |
17a2f251 | 16044 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16045 | { |
7ed4a06a | 16046 | #ifdef OBJ_ELF |
cca86cc8 SC |
16047 | char *section_name; |
16048 | char c; | |
684022ea | 16049 | char next_c = 0; |
cca86cc8 SC |
16050 | int section_type; |
16051 | int section_flag; | |
16052 | int section_entry_size; | |
16053 | int section_alignment; | |
b34976b6 | 16054 | |
f43abd2b | 16055 | if (!IS_ELF) |
7ed4a06a TS |
16056 | return; |
16057 | ||
cca86cc8 SC |
16058 | section_name = input_line_pointer; |
16059 | c = get_symbol_end (); | |
a816d1ed AO |
16060 | if (c) |
16061 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16062 | |
4cf0dd0d TS |
16063 | /* Do we have .section Name<,"flags">? */ |
16064 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16065 | { |
4cf0dd0d TS |
16066 | /* just after name is now '\0'. */ |
16067 | *input_line_pointer = c; | |
cca86cc8 SC |
16068 | input_line_pointer = section_name; |
16069 | obj_elf_section (ignore); | |
16070 | return; | |
16071 | } | |
16072 | input_line_pointer++; | |
16073 | ||
16074 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16075 | if (c == ',') | |
16076 | section_type = get_absolute_expression (); | |
16077 | else | |
16078 | section_type = 0; | |
16079 | if (*input_line_pointer++ == ',') | |
16080 | section_flag = get_absolute_expression (); | |
16081 | else | |
16082 | section_flag = 0; | |
16083 | if (*input_line_pointer++ == ',') | |
16084 | section_entry_size = get_absolute_expression (); | |
16085 | else | |
16086 | section_entry_size = 0; | |
16087 | if (*input_line_pointer++ == ',') | |
16088 | section_alignment = get_absolute_expression (); | |
16089 | else | |
16090 | section_alignment = 0; | |
87975d2a AM |
16091 | /* FIXME: really ignore? */ |
16092 | (void) section_alignment; | |
cca86cc8 | 16093 | |
a816d1ed AO |
16094 | section_name = xstrdup (section_name); |
16095 | ||
8ab8a5c8 RS |
16096 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16097 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16098 | traditionally had to fall back on the more common @progbits instead. | |
16099 | ||
16100 | There's nothing really harmful in this, since bfd will correct | |
16101 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16102 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16103 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16104 | ||
16105 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16106 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16107 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16108 | generic type-checking code. */ | |
16109 | if (section_type == SHT_MIPS_DWARF) | |
16110 | section_type = SHT_PROGBITS; | |
16111 | ||
cca86cc8 SC |
16112 | obj_elf_change_section (section_name, section_type, section_flag, |
16113 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16114 | |
16115 | if (now_seg->name != section_name) | |
16116 | free (section_name); | |
7ed4a06a | 16117 | #endif /* OBJ_ELF */ |
cca86cc8 | 16118 | } |
252b5132 RH |
16119 | |
16120 | void | |
17a2f251 | 16121 | mips_enable_auto_align (void) |
252b5132 RH |
16122 | { |
16123 | auto_align = 1; | |
16124 | } | |
16125 | ||
16126 | static void | |
17a2f251 | 16127 | s_cons (int log_size) |
252b5132 | 16128 | { |
a8dbcb85 TS |
16129 | segment_info_type *si = seg_info (now_seg); |
16130 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16131 | |
7d10b47d | 16132 | mips_emit_delays (); |
252b5132 | 16133 | if (log_size > 0 && auto_align) |
462427c4 | 16134 | mips_align (log_size, 0, l); |
252b5132 | 16135 | cons (1 << log_size); |
a1facbec | 16136 | mips_clear_insn_labels (); |
252b5132 RH |
16137 | } |
16138 | ||
16139 | static void | |
17a2f251 | 16140 | s_float_cons (int type) |
252b5132 | 16141 | { |
a8dbcb85 TS |
16142 | segment_info_type *si = seg_info (now_seg); |
16143 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16144 | |
7d10b47d | 16145 | mips_emit_delays (); |
252b5132 RH |
16146 | |
16147 | if (auto_align) | |
49309057 ILT |
16148 | { |
16149 | if (type == 'd') | |
462427c4 | 16150 | mips_align (3, 0, l); |
49309057 | 16151 | else |
462427c4 | 16152 | mips_align (2, 0, l); |
49309057 | 16153 | } |
252b5132 | 16154 | |
252b5132 | 16155 | float_cons (type); |
a1facbec | 16156 | mips_clear_insn_labels (); |
252b5132 RH |
16157 | } |
16158 | ||
16159 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16160 | permitted to say | |
16161 | .globl foo .text | |
16162 | where foo is an undefined symbol, to mean that foo should be | |
16163 | considered to be the address of a function. */ | |
16164 | ||
16165 | static void | |
17a2f251 | 16166 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16167 | { |
16168 | char *name; | |
16169 | int c; | |
16170 | symbolS *symbolP; | |
16171 | flagword flag; | |
16172 | ||
8a06b769 | 16173 | do |
252b5132 | 16174 | { |
8a06b769 | 16175 | name = input_line_pointer; |
252b5132 | 16176 | c = get_symbol_end (); |
8a06b769 TS |
16177 | symbolP = symbol_find_or_make (name); |
16178 | S_SET_EXTERNAL (symbolP); | |
16179 | ||
252b5132 | 16180 | *input_line_pointer = c; |
8a06b769 | 16181 | SKIP_WHITESPACE (); |
252b5132 | 16182 | |
8a06b769 TS |
16183 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16184 | being a function is apparently labelled as being an object. */ | |
16185 | flag = BSF_OBJECT; | |
252b5132 | 16186 | |
8a06b769 TS |
16187 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16188 | && (*input_line_pointer != ',')) | |
16189 | { | |
16190 | char *secname; | |
16191 | asection *sec; | |
16192 | ||
16193 | secname = input_line_pointer; | |
16194 | c = get_symbol_end (); | |
16195 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16196 | if (sec == NULL) | |
16197 | as_bad (_("%s: no such section"), secname); | |
16198 | *input_line_pointer = c; | |
16199 | ||
16200 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16201 | flag = BSF_FUNCTION; | |
16202 | } | |
16203 | ||
16204 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16205 | ||
16206 | c = *input_line_pointer; | |
16207 | if (c == ',') | |
16208 | { | |
16209 | input_line_pointer++; | |
16210 | SKIP_WHITESPACE (); | |
16211 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16212 | c = '\n'; | |
16213 | } | |
16214 | } | |
16215 | while (c == ','); | |
252b5132 | 16216 | |
252b5132 RH |
16217 | demand_empty_rest_of_line (); |
16218 | } | |
16219 | ||
16220 | static void | |
17a2f251 | 16221 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16222 | { |
16223 | char *opt; | |
16224 | char c; | |
16225 | ||
16226 | opt = input_line_pointer; | |
16227 | c = get_symbol_end (); | |
16228 | ||
16229 | if (*opt == 'O') | |
16230 | { | |
16231 | /* FIXME: What does this mean? */ | |
16232 | } | |
16233 | else if (strncmp (opt, "pic", 3) == 0) | |
16234 | { | |
16235 | int i; | |
16236 | ||
16237 | i = atoi (opt + 3); | |
16238 | if (i == 0) | |
16239 | mips_pic = NO_PIC; | |
16240 | else if (i == 2) | |
143d77c5 | 16241 | { |
8b828383 | 16242 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16243 | mips_abicalls = TRUE; |
16244 | } | |
252b5132 RH |
16245 | else |
16246 | as_bad (_(".option pic%d not supported"), i); | |
16247 | ||
4d0d148d | 16248 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16249 | { |
16250 | if (g_switch_seen && g_switch_value != 0) | |
16251 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16252 | g_switch_value = 0; | |
16253 | bfd_set_gp_size (stdoutput, 0); | |
16254 | } | |
16255 | } | |
16256 | else | |
16257 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16258 | ||
16259 | *input_line_pointer = c; | |
16260 | demand_empty_rest_of_line (); | |
16261 | } | |
16262 | ||
16263 | /* This structure is used to hold a stack of .set values. */ | |
16264 | ||
e972090a NC |
16265 | struct mips_option_stack |
16266 | { | |
252b5132 RH |
16267 | struct mips_option_stack *next; |
16268 | struct mips_set_options options; | |
16269 | }; | |
16270 | ||
16271 | static struct mips_option_stack *mips_opts_stack; | |
16272 | ||
16273 | /* Handle the .set pseudo-op. */ | |
16274 | ||
16275 | static void | |
17a2f251 | 16276 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16277 | { |
16278 | char *name = input_line_pointer, ch; | |
16279 | ||
16280 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16281 | ++input_line_pointer; |
252b5132 RH |
16282 | ch = *input_line_pointer; |
16283 | *input_line_pointer = '\0'; | |
16284 | ||
16285 | if (strcmp (name, "reorder") == 0) | |
16286 | { | |
7d10b47d RS |
16287 | if (mips_opts.noreorder) |
16288 | end_noreorder (); | |
252b5132 RH |
16289 | } |
16290 | else if (strcmp (name, "noreorder") == 0) | |
16291 | { | |
7d10b47d RS |
16292 | if (!mips_opts.noreorder) |
16293 | start_noreorder (); | |
252b5132 | 16294 | } |
741fe287 MR |
16295 | else if (strncmp (name, "at=", 3) == 0) |
16296 | { | |
16297 | char *s = name + 3; | |
16298 | ||
16299 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16300 | as_bad (_("Unrecognized register name `%s'"), s); | |
16301 | } | |
252b5132 RH |
16302 | else if (strcmp (name, "at") == 0) |
16303 | { | |
741fe287 | 16304 | mips_opts.at = ATREG; |
252b5132 RH |
16305 | } |
16306 | else if (strcmp (name, "noat") == 0) | |
16307 | { | |
741fe287 | 16308 | mips_opts.at = ZERO; |
252b5132 RH |
16309 | } |
16310 | else if (strcmp (name, "macro") == 0) | |
16311 | { | |
16312 | mips_opts.warn_about_macros = 0; | |
16313 | } | |
16314 | else if (strcmp (name, "nomacro") == 0) | |
16315 | { | |
16316 | if (mips_opts.noreorder == 0) | |
16317 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16318 | mips_opts.warn_about_macros = 1; | |
16319 | } | |
16320 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16321 | { | |
16322 | mips_opts.nomove = 0; | |
16323 | } | |
16324 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16325 | { | |
16326 | mips_opts.nomove = 1; | |
16327 | } | |
16328 | else if (strcmp (name, "bopt") == 0) | |
16329 | { | |
16330 | mips_opts.nobopt = 0; | |
16331 | } | |
16332 | else if (strcmp (name, "nobopt") == 0) | |
16333 | { | |
16334 | mips_opts.nobopt = 1; | |
16335 | } | |
ad3fea08 TS |
16336 | else if (strcmp (name, "gp=default") == 0) |
16337 | mips_opts.gp32 = file_mips_gp32; | |
16338 | else if (strcmp (name, "gp=32") == 0) | |
16339 | mips_opts.gp32 = 1; | |
16340 | else if (strcmp (name, "gp=64") == 0) | |
16341 | { | |
16342 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16343 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16344 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16345 | mips_opts.gp32 = 0; | |
16346 | } | |
16347 | else if (strcmp (name, "fp=default") == 0) | |
16348 | mips_opts.fp32 = file_mips_fp32; | |
16349 | else if (strcmp (name, "fp=32") == 0) | |
16350 | mips_opts.fp32 = 1; | |
16351 | else if (strcmp (name, "fp=64") == 0) | |
16352 | { | |
16353 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16354 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16355 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16356 | mips_opts.fp32 = 0; | |
16357 | } | |
037b32b9 AN |
16358 | else if (strcmp (name, "softfloat") == 0) |
16359 | mips_opts.soft_float = 1; | |
16360 | else if (strcmp (name, "hardfloat") == 0) | |
16361 | mips_opts.soft_float = 0; | |
16362 | else if (strcmp (name, "singlefloat") == 0) | |
16363 | mips_opts.single_float = 1; | |
16364 | else if (strcmp (name, "doublefloat") == 0) | |
16365 | mips_opts.single_float = 0; | |
252b5132 RH |
16366 | else if (strcmp (name, "mips16") == 0 |
16367 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16368 | { |
16369 | if (mips_opts.micromips == 1) | |
16370 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16371 | mips_opts.mips16 = 1; | |
16372 | } | |
252b5132 RH |
16373 | else if (strcmp (name, "nomips16") == 0 |
16374 | || strcmp (name, "noMIPS-16") == 0) | |
16375 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16376 | else if (strcmp (name, "micromips") == 0) |
16377 | { | |
16378 | if (mips_opts.mips16 == 1) | |
16379 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16380 | mips_opts.micromips = 1; | |
16381 | } | |
16382 | else if (strcmp (name, "nomicromips") == 0) | |
16383 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16384 | else if (strcmp (name, "smartmips") == 0) |
16385 | { | |
ad3fea08 | 16386 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16387 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16388 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16389 | mips_opts.ase_smartmips = 1; | |
16390 | } | |
16391 | else if (strcmp (name, "nosmartmips") == 0) | |
16392 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16393 | else if (strcmp (name, "mips3d") == 0) |
16394 | mips_opts.ase_mips3d = 1; | |
16395 | else if (strcmp (name, "nomips3d") == 0) | |
16396 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16397 | else if (strcmp (name, "mdmx") == 0) |
16398 | mips_opts.ase_mdmx = 1; | |
16399 | else if (strcmp (name, "nomdmx") == 0) | |
16400 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16401 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16402 | { |
16403 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16404 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16405 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16406 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16407 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16408 | } |
74cd071d | 16409 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16410 | { |
16411 | mips_opts.ase_dsp = 0; | |
16412 | mips_opts.ase_dspr2 = 0; | |
16413 | } | |
16414 | else if (strcmp (name, "dspr2") == 0) | |
16415 | { | |
16416 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16417 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16418 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16419 | mips_opts.ase_dspr2 = 1; | |
16420 | mips_opts.ase_dsp = 1; | |
16421 | } | |
16422 | else if (strcmp (name, "nodspr2") == 0) | |
16423 | { | |
16424 | mips_opts.ase_dspr2 = 0; | |
16425 | mips_opts.ase_dsp = 0; | |
16426 | } | |
ef2e4d86 | 16427 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16428 | { |
16429 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16430 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16431 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16432 | mips_opts.ase_mt = 1; | |
16433 | } | |
ef2e4d86 CF |
16434 | else if (strcmp (name, "nomt") == 0) |
16435 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16436 | else if (strcmp (name, "mcu") == 0) |
16437 | mips_opts.ase_mcu = 1; | |
16438 | else if (strcmp (name, "nomcu") == 0) | |
16439 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16440 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16441 | { |
af7ee8bf | 16442 | int reset = 0; |
252b5132 | 16443 | |
1a2c1fad CD |
16444 | /* Permit the user to change the ISA and architecture on the fly. |
16445 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16446 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16447 | { |
16448 | reset = 1; | |
16449 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16450 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16451 | } |
16452 | else if (strncmp (name, "arch=", 5) == 0) | |
16453 | { | |
16454 | const struct mips_cpu_info *p; | |
16455 | ||
16456 | p = mips_parse_cpu("internal use", name + 5); | |
16457 | if (!p) | |
16458 | as_bad (_("unknown architecture %s"), name + 5); | |
16459 | else | |
16460 | { | |
16461 | mips_opts.arch = p->cpu; | |
16462 | mips_opts.isa = p->isa; | |
16463 | } | |
16464 | } | |
81a21e38 TS |
16465 | else if (strncmp (name, "mips", 4) == 0) |
16466 | { | |
16467 | const struct mips_cpu_info *p; | |
16468 | ||
16469 | p = mips_parse_cpu("internal use", name); | |
16470 | if (!p) | |
16471 | as_bad (_("unknown ISA level %s"), name + 4); | |
16472 | else | |
16473 | { | |
16474 | mips_opts.arch = p->cpu; | |
16475 | mips_opts.isa = p->isa; | |
16476 | } | |
16477 | } | |
af7ee8bf | 16478 | else |
81a21e38 | 16479 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16480 | |
16481 | switch (mips_opts.isa) | |
98d3f06f KH |
16482 | { |
16483 | case 0: | |
98d3f06f | 16484 | break; |
af7ee8bf CD |
16485 | case ISA_MIPS1: |
16486 | case ISA_MIPS2: | |
16487 | case ISA_MIPS32: | |
16488 | case ISA_MIPS32R2: | |
98d3f06f KH |
16489 | mips_opts.gp32 = 1; |
16490 | mips_opts.fp32 = 1; | |
16491 | break; | |
af7ee8bf CD |
16492 | case ISA_MIPS3: |
16493 | case ISA_MIPS4: | |
16494 | case ISA_MIPS5: | |
16495 | case ISA_MIPS64: | |
5f74bc13 | 16496 | case ISA_MIPS64R2: |
98d3f06f | 16497 | mips_opts.gp32 = 0; |
e407c74b NC |
16498 | if (mips_opts.arch == CPU_R5900) |
16499 | { | |
16500 | mips_opts.fp32 = 1; | |
16501 | } | |
16502 | else | |
16503 | { | |
98d3f06f | 16504 | mips_opts.fp32 = 0; |
e407c74b | 16505 | } |
98d3f06f KH |
16506 | break; |
16507 | default: | |
16508 | as_bad (_("unknown ISA level %s"), name + 4); | |
16509 | break; | |
16510 | } | |
af7ee8bf | 16511 | if (reset) |
98d3f06f | 16512 | { |
af7ee8bf CD |
16513 | mips_opts.gp32 = file_mips_gp32; |
16514 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16515 | } |
252b5132 RH |
16516 | } |
16517 | else if (strcmp (name, "autoextend") == 0) | |
16518 | mips_opts.noautoextend = 0; | |
16519 | else if (strcmp (name, "noautoextend") == 0) | |
16520 | mips_opts.noautoextend = 1; | |
16521 | else if (strcmp (name, "push") == 0) | |
16522 | { | |
16523 | struct mips_option_stack *s; | |
16524 | ||
16525 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16526 | s->next = mips_opts_stack; | |
16527 | s->options = mips_opts; | |
16528 | mips_opts_stack = s; | |
16529 | } | |
16530 | else if (strcmp (name, "pop") == 0) | |
16531 | { | |
16532 | struct mips_option_stack *s; | |
16533 | ||
16534 | s = mips_opts_stack; | |
16535 | if (s == NULL) | |
16536 | as_bad (_(".set pop with no .set push")); | |
16537 | else | |
16538 | { | |
16539 | /* If we're changing the reorder mode we need to handle | |
16540 | delay slots correctly. */ | |
16541 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16542 | start_noreorder (); |
252b5132 | 16543 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16544 | end_noreorder (); |
252b5132 RH |
16545 | |
16546 | mips_opts = s->options; | |
16547 | mips_opts_stack = s->next; | |
16548 | free (s); | |
16549 | } | |
16550 | } | |
aed1a261 RS |
16551 | else if (strcmp (name, "sym32") == 0) |
16552 | mips_opts.sym32 = TRUE; | |
16553 | else if (strcmp (name, "nosym32") == 0) | |
16554 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16555 | else if (strchr (name, ',')) |
16556 | { | |
16557 | /* Generic ".set" directive; use the generic handler. */ | |
16558 | *input_line_pointer = ch; | |
16559 | input_line_pointer = name; | |
16560 | s_set (0); | |
16561 | return; | |
16562 | } | |
252b5132 RH |
16563 | else |
16564 | { | |
16565 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16566 | } | |
16567 | *input_line_pointer = ch; | |
16568 | demand_empty_rest_of_line (); | |
16569 | } | |
16570 | ||
16571 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16572 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16573 | ||
16574 | static void | |
17a2f251 | 16575 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16576 | { |
16577 | mips_pic = SVR4_PIC; | |
143d77c5 | 16578 | mips_abicalls = TRUE; |
4d0d148d TS |
16579 | |
16580 | if (g_switch_seen && g_switch_value != 0) | |
16581 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16582 | g_switch_value = 0; | |
16583 | ||
252b5132 RH |
16584 | bfd_set_gp_size (stdoutput, 0); |
16585 | demand_empty_rest_of_line (); | |
16586 | } | |
16587 | ||
16588 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16589 | PIC code. It sets the $gp register for the function based on the | |
16590 | function address, which is in the register named in the argument. | |
16591 | This uses a relocation against _gp_disp, which is handled specially | |
16592 | by the linker. The result is: | |
16593 | lui $gp,%hi(_gp_disp) | |
16594 | addiu $gp,$gp,%lo(_gp_disp) | |
16595 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16596 | The .cpload argument is normally $25 == $t9. |
16597 | ||
16598 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16599 | lui $gp,%hi(__gnu_local_gp) |
16600 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16601 | and the argument is ignored. This saves an instruction, but the |
16602 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16603 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16604 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16605 | |
16606 | static void | |
17a2f251 | 16607 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16608 | { |
16609 | expressionS ex; | |
aa6975fb ILT |
16610 | int reg; |
16611 | int in_shared; | |
252b5132 | 16612 | |
6478892d TS |
16613 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16614 | .cpload is ignored. */ | |
16615 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16616 | { |
16617 | s_ignore (0); | |
16618 | return; | |
16619 | } | |
16620 | ||
a276b80c MR |
16621 | if (mips_opts.mips16) |
16622 | { | |
16623 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16624 | ignore_rest_of_line (); | |
16625 | return; | |
16626 | } | |
16627 | ||
d3ecfc59 | 16628 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16629 | if (mips_opts.noreorder == 0) |
16630 | as_warn (_(".cpload not in noreorder section")); | |
16631 | ||
aa6975fb ILT |
16632 | reg = tc_get_register (0); |
16633 | ||
16634 | /* If we need to produce a 64-bit address, we are better off using | |
16635 | the default instruction sequence. */ | |
aed1a261 | 16636 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16637 | |
252b5132 | 16638 | ex.X_op = O_symbol; |
bbe506e8 TS |
16639 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16640 | "__gnu_local_gp"); | |
252b5132 RH |
16641 | ex.X_op_symbol = NULL; |
16642 | ex.X_add_number = 0; | |
16643 | ||
16644 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16645 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16646 | |
8a75745d MR |
16647 | mips_mark_labels (); |
16648 | mips_assembling_insn = TRUE; | |
16649 | ||
584892a6 | 16650 | macro_start (); |
67c0d1eb RS |
16651 | macro_build_lui (&ex, mips_gp_register); |
16652 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16653 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16654 | if (in_shared) |
16655 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16656 | mips_gp_register, reg); | |
584892a6 | 16657 | macro_end (); |
252b5132 | 16658 | |
8a75745d | 16659 | mips_assembling_insn = FALSE; |
252b5132 RH |
16660 | demand_empty_rest_of_line (); |
16661 | } | |
16662 | ||
6478892d TS |
16663 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16664 | .cpsetup $reg1, offset|$reg2, label | |
16665 | ||
16666 | If offset is given, this results in: | |
16667 | sd $gp, offset($sp) | |
956cd1d6 | 16668 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16669 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16670 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16671 | |
16672 | If $reg2 is given, this results in: | |
16673 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16674 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16675 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16676 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16677 | $reg1 is normally $25 == $t9. |
16678 | ||
16679 | The -mno-shared option replaces the last three instructions with | |
16680 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16681 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16682 | |
6478892d | 16683 | static void |
17a2f251 | 16684 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16685 | { |
16686 | expressionS ex_off; | |
16687 | expressionS ex_sym; | |
16688 | int reg1; | |
6478892d | 16689 | |
8586fc66 | 16690 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16691 | We also need NewABI support. */ |
16692 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16693 | { | |
16694 | s_ignore (0); | |
16695 | return; | |
16696 | } | |
16697 | ||
a276b80c MR |
16698 | if (mips_opts.mips16) |
16699 | { | |
16700 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16701 | ignore_rest_of_line (); | |
16702 | return; | |
16703 | } | |
16704 | ||
6478892d TS |
16705 | reg1 = tc_get_register (0); |
16706 | SKIP_WHITESPACE (); | |
16707 | if (*input_line_pointer != ',') | |
16708 | { | |
16709 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16710 | return; | |
16711 | } | |
16712 | else | |
80245285 | 16713 | ++input_line_pointer; |
6478892d TS |
16714 | SKIP_WHITESPACE (); |
16715 | if (*input_line_pointer == '$') | |
80245285 TS |
16716 | { |
16717 | mips_cpreturn_register = tc_get_register (0); | |
16718 | mips_cpreturn_offset = -1; | |
16719 | } | |
6478892d | 16720 | else |
80245285 TS |
16721 | { |
16722 | mips_cpreturn_offset = get_absolute_expression (); | |
16723 | mips_cpreturn_register = -1; | |
16724 | } | |
6478892d TS |
16725 | SKIP_WHITESPACE (); |
16726 | if (*input_line_pointer != ',') | |
16727 | { | |
16728 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16729 | return; | |
16730 | } | |
16731 | else | |
f9419b05 | 16732 | ++input_line_pointer; |
6478892d | 16733 | SKIP_WHITESPACE (); |
f21f8242 | 16734 | expression (&ex_sym); |
6478892d | 16735 | |
8a75745d MR |
16736 | mips_mark_labels (); |
16737 | mips_assembling_insn = TRUE; | |
16738 | ||
584892a6 | 16739 | macro_start (); |
6478892d TS |
16740 | if (mips_cpreturn_register == -1) |
16741 | { | |
16742 | ex_off.X_op = O_constant; | |
16743 | ex_off.X_add_symbol = NULL; | |
16744 | ex_off.X_op_symbol = NULL; | |
16745 | ex_off.X_add_number = mips_cpreturn_offset; | |
16746 | ||
67c0d1eb | 16747 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16748 | BFD_RELOC_LO16, SP); |
6478892d TS |
16749 | } |
16750 | else | |
67c0d1eb | 16751 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16752 | mips_gp_register, 0); |
6478892d | 16753 | |
aed1a261 | 16754 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16755 | { |
df58fc94 | 16756 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16757 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16758 | BFD_RELOC_HI16_S); | |
16759 | ||
16760 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16761 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16762 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16763 | ||
16764 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16765 | mips_gp_register, reg1); | |
16766 | } | |
16767 | else | |
16768 | { | |
16769 | expressionS ex; | |
16770 | ||
16771 | ex.X_op = O_symbol; | |
4184909a | 16772 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16773 | ex.X_op_symbol = NULL; |
16774 | ex.X_add_number = 0; | |
6e1304d8 | 16775 | |
aa6975fb ILT |
16776 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16777 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16778 | ||
16779 | macro_build_lui (&ex, mips_gp_register); | |
16780 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16781 | mips_gp_register, BFD_RELOC_LO16); | |
16782 | } | |
f21f8242 | 16783 | |
584892a6 | 16784 | macro_end (); |
6478892d | 16785 | |
8a75745d | 16786 | mips_assembling_insn = FALSE; |
6478892d TS |
16787 | demand_empty_rest_of_line (); |
16788 | } | |
16789 | ||
16790 | static void | |
17a2f251 | 16791 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16792 | { |
16793 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16794 | .cplocal is ignored. */ |
6478892d TS |
16795 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16796 | { | |
16797 | s_ignore (0); | |
16798 | return; | |
16799 | } | |
16800 | ||
a276b80c MR |
16801 | if (mips_opts.mips16) |
16802 | { | |
16803 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16804 | ignore_rest_of_line (); | |
16805 | return; | |
16806 | } | |
16807 | ||
6478892d | 16808 | mips_gp_register = tc_get_register (0); |
85b51719 | 16809 | demand_empty_rest_of_line (); |
6478892d TS |
16810 | } |
16811 | ||
252b5132 RH |
16812 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16813 | offset from $sp. The offset is remembered, and after making a PIC | |
16814 | call $gp is restored from that location. */ | |
16815 | ||
16816 | static void | |
17a2f251 | 16817 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16818 | { |
16819 | expressionS ex; | |
252b5132 | 16820 | |
6478892d | 16821 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16822 | .cprestore is ignored. */ |
6478892d | 16823 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16824 | { |
16825 | s_ignore (0); | |
16826 | return; | |
16827 | } | |
16828 | ||
a276b80c MR |
16829 | if (mips_opts.mips16) |
16830 | { | |
16831 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16832 | ignore_rest_of_line (); | |
16833 | return; | |
16834 | } | |
16835 | ||
252b5132 | 16836 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16837 | mips_cprestore_valid = 1; |
252b5132 RH |
16838 | |
16839 | ex.X_op = O_constant; | |
16840 | ex.X_add_symbol = NULL; | |
16841 | ex.X_op_symbol = NULL; | |
16842 | ex.X_add_number = mips_cprestore_offset; | |
16843 | ||
8a75745d MR |
16844 | mips_mark_labels (); |
16845 | mips_assembling_insn = TRUE; | |
16846 | ||
584892a6 | 16847 | macro_start (); |
67c0d1eb RS |
16848 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16849 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16850 | macro_end (); |
252b5132 | 16851 | |
8a75745d | 16852 | mips_assembling_insn = FALSE; |
252b5132 RH |
16853 | demand_empty_rest_of_line (); |
16854 | } | |
16855 | ||
6478892d | 16856 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16857 | was given in the preceding .cpsetup, it results in: |
6478892d | 16858 | ld $gp, offset($sp) |
76b3015f | 16859 | |
6478892d | 16860 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16861 | daddu $gp, $reg2, $0 */ |
16862 | ||
6478892d | 16863 | static void |
17a2f251 | 16864 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16865 | { |
16866 | expressionS ex; | |
6478892d TS |
16867 | |
16868 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16869 | We also need NewABI support. */ | |
16870 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16871 | { | |
16872 | s_ignore (0); | |
16873 | return; | |
16874 | } | |
16875 | ||
a276b80c MR |
16876 | if (mips_opts.mips16) |
16877 | { | |
16878 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16879 | ignore_rest_of_line (); | |
16880 | return; | |
16881 | } | |
16882 | ||
8a75745d MR |
16883 | mips_mark_labels (); |
16884 | mips_assembling_insn = TRUE; | |
16885 | ||
584892a6 | 16886 | macro_start (); |
6478892d TS |
16887 | if (mips_cpreturn_register == -1) |
16888 | { | |
16889 | ex.X_op = O_constant; | |
16890 | ex.X_add_symbol = NULL; | |
16891 | ex.X_op_symbol = NULL; | |
16892 | ex.X_add_number = mips_cpreturn_offset; | |
16893 | ||
67c0d1eb | 16894 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16895 | } |
16896 | else | |
67c0d1eb | 16897 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16898 | mips_cpreturn_register, 0); |
584892a6 | 16899 | macro_end (); |
6478892d | 16900 | |
8a75745d | 16901 | mips_assembling_insn = FALSE; |
6478892d TS |
16902 | demand_empty_rest_of_line (); |
16903 | } | |
16904 | ||
d0f13682 CLT |
16905 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16906 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16907 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16908 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16909 | |
16910 | static void | |
d0f13682 CLT |
16911 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16912 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16913 | { |
16914 | expressionS ex; | |
16915 | char *p; | |
16916 | ||
16917 | expression (&ex); | |
16918 | ||
16919 | if (ex.X_op != O_symbol) | |
16920 | { | |
d0f13682 | 16921 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16922 | ignore_rest_of_line (); |
16923 | } | |
16924 | ||
16925 | p = frag_more (bytes); | |
16926 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16927 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16928 | demand_empty_rest_of_line (); |
de64cffd | 16929 | mips_clear_insn_labels (); |
741d6ea8 JM |
16930 | } |
16931 | ||
16932 | /* Handle .dtprelword. */ | |
16933 | ||
16934 | static void | |
16935 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16936 | { | |
d0f13682 | 16937 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16938 | } |
16939 | ||
16940 | /* Handle .dtpreldword. */ | |
16941 | ||
16942 | static void | |
16943 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16944 | { | |
d0f13682 CLT |
16945 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16946 | } | |
16947 | ||
16948 | /* Handle .tprelword. */ | |
16949 | ||
16950 | static void | |
16951 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16952 | { | |
16953 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16954 | } | |
16955 | ||
16956 | /* Handle .tpreldword. */ | |
16957 | ||
16958 | static void | |
16959 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16960 | { | |
16961 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16962 | } |
16963 | ||
6478892d TS |
16964 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16965 | code. It sets the offset to use in gp_rel relocations. */ | |
16966 | ||
16967 | static void | |
17a2f251 | 16968 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16969 | { |
16970 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16971 | We also need NewABI support. */ | |
16972 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16973 | { | |
16974 | s_ignore (0); | |
16975 | return; | |
16976 | } | |
16977 | ||
def2e0dd | 16978 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16979 | |
16980 | demand_empty_rest_of_line (); | |
16981 | } | |
16982 | ||
252b5132 RH |
16983 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16984 | code. It generates a 32 bit GP relative reloc. */ | |
16985 | ||
16986 | static void | |
17a2f251 | 16987 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16988 | { |
a8dbcb85 TS |
16989 | segment_info_type *si; |
16990 | struct insn_label_list *l; | |
252b5132 RH |
16991 | expressionS ex; |
16992 | char *p; | |
16993 | ||
16994 | /* When not generating PIC code, this is treated as .word. */ | |
16995 | if (mips_pic != SVR4_PIC) | |
16996 | { | |
16997 | s_cons (2); | |
16998 | return; | |
16999 | } | |
17000 | ||
a8dbcb85 TS |
17001 | si = seg_info (now_seg); |
17002 | l = si->label_list; | |
7d10b47d | 17003 | mips_emit_delays (); |
252b5132 | 17004 | if (auto_align) |
462427c4 | 17005 | mips_align (2, 0, l); |
252b5132 RH |
17006 | |
17007 | expression (&ex); | |
a1facbec | 17008 | mips_clear_insn_labels (); |
252b5132 RH |
17009 | |
17010 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17011 | { | |
17012 | as_bad (_("Unsupported use of .gpword")); | |
17013 | ignore_rest_of_line (); | |
17014 | } | |
17015 | ||
17016 | p = frag_more (4); | |
17a2f251 | 17017 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17018 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17019 | BFD_RELOC_GPREL32); |
252b5132 RH |
17020 | |
17021 | demand_empty_rest_of_line (); | |
17022 | } | |
17023 | ||
10181a0d | 17024 | static void |
17a2f251 | 17025 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17026 | { |
a8dbcb85 TS |
17027 | segment_info_type *si; |
17028 | struct insn_label_list *l; | |
10181a0d AO |
17029 | expressionS ex; |
17030 | char *p; | |
17031 | ||
17032 | /* When not generating PIC code, this is treated as .dword. */ | |
17033 | if (mips_pic != SVR4_PIC) | |
17034 | { | |
17035 | s_cons (3); | |
17036 | return; | |
17037 | } | |
17038 | ||
a8dbcb85 TS |
17039 | si = seg_info (now_seg); |
17040 | l = si->label_list; | |
7d10b47d | 17041 | mips_emit_delays (); |
10181a0d | 17042 | if (auto_align) |
462427c4 | 17043 | mips_align (3, 0, l); |
10181a0d AO |
17044 | |
17045 | expression (&ex); | |
a1facbec | 17046 | mips_clear_insn_labels (); |
10181a0d AO |
17047 | |
17048 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17049 | { | |
17050 | as_bad (_("Unsupported use of .gpdword")); | |
17051 | ignore_rest_of_line (); | |
17052 | } | |
17053 | ||
17054 | p = frag_more (8); | |
17a2f251 | 17055 | md_number_to_chars (p, 0, 8); |
a105a300 | 17056 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17057 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17058 | |
17059 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17060 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17061 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17062 | |
17063 | demand_empty_rest_of_line (); | |
17064 | } | |
17065 | ||
252b5132 RH |
17066 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17067 | tables in SVR4 PIC code. */ | |
17068 | ||
17069 | static void | |
17a2f251 | 17070 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17071 | { |
252b5132 RH |
17072 | int reg; |
17073 | ||
10181a0d AO |
17074 | /* This is ignored when not generating SVR4 PIC code. */ |
17075 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17076 | { |
17077 | s_ignore (0); | |
17078 | return; | |
17079 | } | |
17080 | ||
8a75745d MR |
17081 | mips_mark_labels (); |
17082 | mips_assembling_insn = TRUE; | |
17083 | ||
252b5132 | 17084 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17085 | macro_start (); |
252b5132 | 17086 | reg = tc_get_register (0); |
67c0d1eb | 17087 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17088 | macro_end (); |
252b5132 | 17089 | |
8a75745d | 17090 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17091 | demand_empty_rest_of_line (); |
252b5132 RH |
17092 | } |
17093 | ||
17094 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17095 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17096 | such as generating jalx instructions when needed. We also make |
17097 | them odd for the duration of the assembly, in order to generate the | |
17098 | right sort of code. We will make them even in the adjust_symtab | |
17099 | routine, while leaving them marked. This is convenient for the | |
17100 | debugger and the disassembler. The linker knows to make them odd | |
17101 | again. */ | |
17102 | ||
17103 | static void | |
17a2f251 | 17104 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17105 | { |
df58fc94 | 17106 | mips_mark_labels (); |
252b5132 RH |
17107 | |
17108 | demand_empty_rest_of_line (); | |
17109 | } | |
17110 | ||
754e2bb9 RS |
17111 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17112 | implemented in a transparent way, so that removing them would not | |
17113 | have any effect on the generated instructions. However, s_stab | |
17114 | internally changes the section, so in practice we need to decide | |
17115 | now whether the preceding label marks compressed code. We do not | |
17116 | support changing the compression mode of a label after a .stab* | |
17117 | directive, such as in: | |
17118 | ||
17119 | foo: | |
17120 | .stabs ... | |
17121 | .set mips16 | |
17122 | ||
17123 | so the current mode wins. */ | |
252b5132 RH |
17124 | |
17125 | static void | |
17a2f251 | 17126 | s_mips_stab (int type) |
252b5132 | 17127 | { |
754e2bb9 | 17128 | mips_mark_labels (); |
252b5132 RH |
17129 | s_stab (type); |
17130 | } | |
17131 | ||
54f4ddb3 | 17132 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17133 | |
17134 | static void | |
17a2f251 | 17135 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17136 | { |
17137 | char *name; | |
17138 | int c; | |
17139 | symbolS *symbolP; | |
17140 | expressionS exp; | |
17141 | ||
17142 | name = input_line_pointer; | |
17143 | c = get_symbol_end (); | |
17144 | symbolP = symbol_find_or_make (name); | |
17145 | S_SET_WEAK (symbolP); | |
17146 | *input_line_pointer = c; | |
17147 | ||
17148 | SKIP_WHITESPACE (); | |
17149 | ||
17150 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17151 | { | |
17152 | if (S_IS_DEFINED (symbolP)) | |
17153 | { | |
20203fb9 | 17154 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17155 | S_GET_NAME (symbolP)); |
17156 | ignore_rest_of_line (); | |
17157 | return; | |
17158 | } | |
bdaaa2e1 | 17159 | |
252b5132 RH |
17160 | if (*input_line_pointer == ',') |
17161 | { | |
17162 | ++input_line_pointer; | |
17163 | SKIP_WHITESPACE (); | |
17164 | } | |
bdaaa2e1 | 17165 | |
252b5132 RH |
17166 | expression (&exp); |
17167 | if (exp.X_op != O_symbol) | |
17168 | { | |
20203fb9 | 17169 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17170 | ignore_rest_of_line (); |
252b5132 RH |
17171 | return; |
17172 | } | |
49309057 | 17173 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17174 | } |
17175 | ||
17176 | demand_empty_rest_of_line (); | |
17177 | } | |
17178 | ||
17179 | /* Parse a register string into a number. Called from the ECOFF code | |
17180 | to parse .frame. The argument is non-zero if this is the frame | |
17181 | register, so that we can record it in mips_frame_reg. */ | |
17182 | ||
17183 | int | |
17a2f251 | 17184 | tc_get_register (int frame) |
252b5132 | 17185 | { |
707bfff6 | 17186 | unsigned int reg; |
252b5132 RH |
17187 | |
17188 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17189 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17190 | reg = 0; | |
252b5132 | 17191 | if (frame) |
7a621144 DJ |
17192 | { |
17193 | mips_frame_reg = reg != 0 ? reg : SP; | |
17194 | mips_frame_reg_valid = 1; | |
17195 | mips_cprestore_valid = 0; | |
17196 | } | |
252b5132 RH |
17197 | return reg; |
17198 | } | |
17199 | ||
17200 | valueT | |
17a2f251 | 17201 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17202 | { |
17203 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17204 | ||
b4c71f56 TS |
17205 | if (IS_ELF) |
17206 | { | |
17207 | /* We don't need to align ELF sections to the full alignment. | |
17208 | However, Irix 5 may prefer that we align them at least to a 16 | |
17209 | byte boundary. We don't bother to align the sections if we | |
17210 | are targeted for an embedded system. */ | |
c41e87e3 | 17211 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17212 | return addr; |
17213 | if (align > 4) | |
17214 | align = 4; | |
17215 | } | |
252b5132 RH |
17216 | |
17217 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17218 | } | |
17219 | ||
17220 | /* Utility routine, called from above as well. If called while the | |
17221 | input file is still being read, it's only an approximation. (For | |
17222 | example, a symbol may later become defined which appeared to be | |
17223 | undefined earlier.) */ | |
17224 | ||
17225 | static int | |
17a2f251 | 17226 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17227 | { |
17228 | if (sym == 0) | |
17229 | return 0; | |
17230 | ||
4d0d148d | 17231 | if (g_switch_value > 0) |
252b5132 RH |
17232 | { |
17233 | const char *symname; | |
17234 | int change; | |
17235 | ||
c9914766 | 17236 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17237 | register. It can be if it is smaller than the -G size or if |
17238 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17239 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17240 | they can. */ |
17241 | symname = S_GET_NAME (sym); | |
17242 | if (symname != (const char *) NULL | |
17243 | && (strcmp (symname, "eprol") == 0 | |
17244 | || strcmp (symname, "etext") == 0 | |
17245 | || strcmp (symname, "_gp") == 0 | |
17246 | || strcmp (symname, "edata") == 0 | |
17247 | || strcmp (symname, "_fbss") == 0 | |
17248 | || strcmp (symname, "_fdata") == 0 | |
17249 | || strcmp (symname, "_ftext") == 0 | |
17250 | || strcmp (symname, "end") == 0 | |
17251 | || strcmp (symname, "_gp_disp") == 0)) | |
17252 | change = 1; | |
17253 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17254 | && (0 | |
17255 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17256 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17257 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17258 | <= g_switch_value)) | |
252b5132 RH |
17259 | #endif |
17260 | /* We must defer this decision until after the whole | |
17261 | file has been read, since there might be a .extern | |
17262 | after the first use of this symbol. */ | |
17263 | || (before_relaxing | |
17264 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17265 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17266 | #endif |
17267 | && S_GET_VALUE (sym) == 0) | |
17268 | || (S_GET_VALUE (sym) != 0 | |
17269 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17270 | change = 0; | |
17271 | else | |
17272 | { | |
17273 | const char *segname; | |
17274 | ||
17275 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17276 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17277 | && strcmp (segname, ".lit4") != 0); |
17278 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17279 | && strcmp (segname, ".sbss") != 0 |
17280 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17281 | && strncmp (segname, ".sbss.", 6) != 0 |
17282 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17283 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17284 | } |
17285 | return change; | |
17286 | } | |
17287 | else | |
c9914766 | 17288 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17289 | return 1; |
17290 | } | |
17291 | ||
5919d012 RS |
17292 | |
17293 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17294 | ||
17295 | static bfd_boolean | |
17a2f251 | 17296 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17297 | { |
17298 | asection *symsec; | |
5919d012 RS |
17299 | |
17300 | /* Handle the case of a symbol equated to another symbol. */ | |
17301 | while (symbol_equated_reloc_p (sym)) | |
17302 | { | |
17303 | symbolS *n; | |
17304 | ||
5f0fe04b | 17305 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17306 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17307 | if (n == sym) | |
17308 | break; | |
17309 | sym = n; | |
17310 | } | |
17311 | ||
df1f3cda DD |
17312 | if (symbol_section_p (sym)) |
17313 | return TRUE; | |
17314 | ||
5919d012 RS |
17315 | symsec = S_GET_SEGMENT (sym); |
17316 | ||
5919d012 | 17317 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17318 | return (!bfd_is_und_section (symsec) |
17319 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17320 | && !bfd_is_com_section (symsec) |
17321 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17322 | #ifdef OBJ_ELF |
17323 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17324 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17325 | #endif |
17326 | ); | |
17327 | } | |
17328 | ||
17329 | ||
252b5132 RH |
17330 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17331 | extended opcode. SEC is the section the frag is in. */ | |
17332 | ||
17333 | static int | |
17a2f251 | 17334 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17335 | { |
17336 | int type; | |
3994f87e | 17337 | const struct mips16_immed_operand *op; |
252b5132 RH |
17338 | offsetT val; |
17339 | int mintiny, maxtiny; | |
17340 | segT symsec; | |
98aa84af | 17341 | fragS *sym_frag; |
252b5132 RH |
17342 | |
17343 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17344 | return 0; | |
17345 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17346 | return 1; | |
17347 | ||
17348 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17349 | op = mips16_immed_operands; | |
17350 | while (op->type != type) | |
17351 | { | |
17352 | ++op; | |
9c2799c2 | 17353 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17354 | } |
17355 | ||
17356 | if (op->unsp) | |
17357 | { | |
17358 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17359 | { | |
17360 | mintiny = 1; | |
17361 | maxtiny = 1 << op->nbits; | |
17362 | } | |
17363 | else | |
17364 | { | |
17365 | mintiny = 0; | |
17366 | maxtiny = (1 << op->nbits) - 1; | |
17367 | } | |
17368 | } | |
17369 | else | |
17370 | { | |
17371 | mintiny = - (1 << (op->nbits - 1)); | |
17372 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17373 | } | |
17374 | ||
98aa84af | 17375 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17376 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17377 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17378 | |
17379 | if (op->pcrel) | |
17380 | { | |
17381 | addressT addr; | |
17382 | ||
17383 | /* We won't have the section when we are called from | |
17384 | mips_relax_frag. However, we will always have been called | |
17385 | from md_estimate_size_before_relax first. If this is a | |
17386 | branch to a different section, we mark it as such. If SEC is | |
17387 | NULL, and the frag is not marked, then it must be a branch to | |
17388 | the same section. */ | |
17389 | if (sec == NULL) | |
17390 | { | |
17391 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17392 | return 1; | |
17393 | } | |
17394 | else | |
17395 | { | |
98aa84af | 17396 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17397 | if (symsec != sec) |
17398 | { | |
17399 | fragp->fr_subtype = | |
17400 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17401 | ||
17402 | /* FIXME: We should support this, and let the linker | |
17403 | catch branches and loads that are out of range. */ | |
17404 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17405 | _("unsupported PC relative reference to different section")); | |
17406 | ||
17407 | return 1; | |
17408 | } | |
98aa84af AM |
17409 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17410 | /* Assume non-extended on the first relaxation pass. | |
17411 | The address we have calculated will be bogus if this is | |
17412 | a forward branch to another frag, as the forward frag | |
17413 | will have fr_address == 0. */ | |
17414 | return 0; | |
252b5132 RH |
17415 | } |
17416 | ||
17417 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17418 | the same section. If the relax_marker of the symbol fragment |
17419 | differs from the relax_marker of this fragment, we have not | |
17420 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17421 | in STRETCH in order to get a better estimate of the address. |
17422 | This particularly matters because of the shift bits. */ | |
17423 | if (stretch != 0 | |
98aa84af | 17424 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17425 | { |
17426 | fragS *f; | |
17427 | ||
17428 | /* Adjust stretch for any alignment frag. Note that if have | |
17429 | been expanding the earlier code, the symbol may be | |
17430 | defined in what appears to be an earlier frag. FIXME: | |
17431 | This doesn't handle the fr_subtype field, which specifies | |
17432 | a maximum number of bytes to skip when doing an | |
17433 | alignment. */ | |
98aa84af | 17434 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17435 | { |
17436 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17437 | { | |
17438 | if (stretch < 0) | |
17439 | stretch = - ((- stretch) | |
17440 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17441 | else | |
17442 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17443 | if (stretch == 0) | |
17444 | break; | |
17445 | } | |
17446 | } | |
17447 | if (f != NULL) | |
17448 | val += stretch; | |
17449 | } | |
17450 | ||
17451 | addr = fragp->fr_address + fragp->fr_fix; | |
17452 | ||
17453 | /* The base address rules are complicated. The base address of | |
17454 | a branch is the following instruction. The base address of a | |
17455 | PC relative load or add is the instruction itself, but if it | |
17456 | is in a delay slot (in which case it can not be extended) use | |
17457 | the address of the instruction whose delay slot it is in. */ | |
17458 | if (type == 'p' || type == 'q') | |
17459 | { | |
17460 | addr += 2; | |
17461 | ||
17462 | /* If we are currently assuming that this frag should be | |
17463 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17464 | higher. */ |
252b5132 RH |
17465 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17466 | addr += 2; | |
17467 | ||
17468 | /* Ignore the low bit in the target, since it will be set | |
17469 | for a text label. */ | |
17470 | if ((val & 1) != 0) | |
17471 | --val; | |
17472 | } | |
17473 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17474 | addr -= 4; | |
17475 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17476 | addr -= 2; | |
17477 | ||
17478 | val -= addr & ~ ((1 << op->shift) - 1); | |
17479 | ||
17480 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17481 | if (type == 'p' || type == 'q') | |
17482 | val /= 2; | |
17483 | ||
17484 | /* If any of the shifted bits are set, we must use an extended | |
17485 | opcode. If the address depends on the size of this | |
17486 | instruction, this can lead to a loop, so we arrange to always | |
17487 | use an extended opcode. We only check this when we are in | |
17488 | the main relaxation loop, when SEC is NULL. */ | |
17489 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17490 | { | |
17491 | fragp->fr_subtype = | |
17492 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17493 | return 1; | |
17494 | } | |
17495 | ||
17496 | /* If we are about to mark a frag as extended because the value | |
17497 | is precisely maxtiny + 1, then there is a chance of an | |
17498 | infinite loop as in the following code: | |
17499 | la $4,foo | |
17500 | .skip 1020 | |
17501 | .align 2 | |
17502 | foo: | |
17503 | In this case when the la is extended, foo is 0x3fc bytes | |
17504 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17505 | the la must be extended. To avoid this loop, we mark the | |
17506 | frag as extended if it was small, and is about to become | |
17507 | extended with a value of maxtiny + 1. */ | |
17508 | if (val == ((maxtiny + 1) << op->shift) | |
17509 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17510 | && sec == NULL) | |
17511 | { | |
17512 | fragp->fr_subtype = | |
17513 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17514 | return 1; | |
17515 | } | |
17516 | } | |
17517 | else if (symsec != absolute_section && sec != NULL) | |
17518 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17519 | ||
17520 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17521 | || val < (mintiny << op->shift) | |
17522 | || val > (maxtiny << op->shift)) | |
17523 | return 1; | |
17524 | else | |
17525 | return 0; | |
17526 | } | |
17527 | ||
4a6a3df4 AO |
17528 | /* Compute the length of a branch sequence, and adjust the |
17529 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17530 | worst-case length is computed, with UPDATE being used to indicate | |
17531 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17532 | branch is to be computed. */ | |
17533 | static int | |
17a2f251 | 17534 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17535 | { |
b34976b6 | 17536 | bfd_boolean toofar; |
4a6a3df4 AO |
17537 | int length; |
17538 | ||
17539 | if (fragp | |
17540 | && S_IS_DEFINED (fragp->fr_symbol) | |
17541 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17542 | { | |
17543 | addressT addr; | |
17544 | offsetT val; | |
17545 | ||
17546 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17547 | ||
17548 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17549 | ||
17550 | val -= addr; | |
17551 | ||
17552 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17553 | } | |
17554 | else if (fragp) | |
17555 | /* If the symbol is not defined or it's in a different segment, | |
17556 | assume the user knows what's going on and emit a short | |
17557 | branch. */ | |
b34976b6 | 17558 | toofar = FALSE; |
4a6a3df4 | 17559 | else |
b34976b6 | 17560 | toofar = TRUE; |
4a6a3df4 AO |
17561 | |
17562 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17563 | fragp->fr_subtype | |
66b3e8da MR |
17564 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17565 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17566 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17567 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17568 | toofar); | |
17569 | ||
17570 | length = 4; | |
17571 | if (toofar) | |
17572 | { | |
17573 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17574 | length += 8; | |
17575 | ||
17576 | if (mips_pic != NO_PIC) | |
17577 | { | |
17578 | /* Additional space for PIC loading of target address. */ | |
17579 | length += 8; | |
17580 | if (mips_opts.isa == ISA_MIPS1) | |
17581 | /* Additional space for $at-stabilizing nop. */ | |
17582 | length += 4; | |
17583 | } | |
17584 | ||
17585 | /* If branch is conditional. */ | |
17586 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17587 | length += 8; | |
17588 | } | |
b34976b6 | 17589 | |
4a6a3df4 AO |
17590 | return length; |
17591 | } | |
17592 | ||
df58fc94 RS |
17593 | /* Compute the length of a branch sequence, and adjust the |
17594 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17595 | worst-case length is computed, with UPDATE being used to indicate | |
17596 | whether an unconditional (-1), or regular (0) branch is to be | |
17597 | computed. */ | |
17598 | ||
17599 | static int | |
17600 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17601 | { | |
17602 | bfd_boolean toofar; | |
17603 | int length; | |
17604 | ||
17605 | if (fragp | |
17606 | && S_IS_DEFINED (fragp->fr_symbol) | |
17607 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17608 | { | |
17609 | addressT addr; | |
17610 | offsetT val; | |
17611 | ||
17612 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17613 | /* Ignore the low bit in the target, since it will be set | |
17614 | for a text label. */ | |
17615 | if ((val & 1) != 0) | |
17616 | --val; | |
17617 | ||
17618 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17619 | ||
17620 | val -= addr; | |
17621 | ||
17622 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17623 | } | |
17624 | else if (fragp) | |
17625 | /* If the symbol is not defined or it's in a different segment, | |
17626 | assume the user knows what's going on and emit a short | |
17627 | branch. */ | |
17628 | toofar = FALSE; | |
17629 | else | |
17630 | toofar = TRUE; | |
17631 | ||
17632 | if (fragp && update | |
17633 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17634 | fragp->fr_subtype = (toofar | |
17635 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17636 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17637 | ||
17638 | length = 4; | |
17639 | if (toofar) | |
17640 | { | |
17641 | bfd_boolean compact_known = fragp != NULL; | |
17642 | bfd_boolean compact = FALSE; | |
17643 | bfd_boolean uncond; | |
17644 | ||
17645 | if (compact_known) | |
17646 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17647 | if (fragp) | |
17648 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17649 | else | |
17650 | uncond = update < 0; | |
17651 | ||
17652 | /* If label is out of range, we turn branch <br>: | |
17653 | ||
17654 | <br> label # 4 bytes | |
17655 | 0: | |
17656 | ||
17657 | into: | |
17658 | ||
17659 | j label # 4 bytes | |
17660 | nop # 2 bytes if compact && !PIC | |
17661 | 0: | |
17662 | */ | |
17663 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17664 | length += 2; | |
17665 | ||
17666 | /* If assembling PIC code, we further turn: | |
17667 | ||
17668 | j label # 4 bytes | |
17669 | ||
17670 | into: | |
17671 | ||
17672 | lw/ld at, %got(label)(gp) # 4 bytes | |
17673 | d/addiu at, %lo(label) # 4 bytes | |
17674 | jr/c at # 2 bytes | |
17675 | */ | |
17676 | if (mips_pic != NO_PIC) | |
17677 | length += 6; | |
17678 | ||
17679 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17680 | ||
17681 | <brneg> 0f # 4 bytes | |
17682 | nop # 2 bytes if !compact | |
17683 | */ | |
17684 | if (!uncond) | |
17685 | length += (compact_known && compact) ? 4 : 6; | |
17686 | } | |
17687 | ||
17688 | return length; | |
17689 | } | |
17690 | ||
17691 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17692 | bit accordingly. */ | |
17693 | ||
17694 | static int | |
17695 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17696 | { | |
17697 | bfd_boolean toofar; | |
17698 | ||
df58fc94 RS |
17699 | if (fragp |
17700 | && S_IS_DEFINED (fragp->fr_symbol) | |
17701 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17702 | { | |
17703 | addressT addr; | |
17704 | offsetT val; | |
17705 | int type; | |
17706 | ||
17707 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17708 | /* Ignore the low bit in the target, since it will be set | |
17709 | for a text label. */ | |
17710 | if ((val & 1) != 0) | |
17711 | --val; | |
17712 | ||
17713 | /* Assume this is a 2-byte branch. */ | |
17714 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17715 | ||
17716 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17717 | long branches. */ | |
17718 | ||
17719 | val -= addr; | |
17720 | ||
17721 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17722 | if (type == 'D') | |
17723 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17724 | else if (type == 'E') | |
17725 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17726 | else | |
17727 | abort (); | |
17728 | } | |
17729 | else | |
17730 | /* If the symbol is not defined or it's in a different segment, | |
17731 | we emit a normal 32-bit branch. */ | |
17732 | toofar = TRUE; | |
17733 | ||
17734 | if (fragp && update | |
17735 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17736 | fragp->fr_subtype | |
17737 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17738 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17739 | ||
17740 | if (toofar) | |
17741 | return 4; | |
17742 | ||
17743 | return 2; | |
17744 | } | |
17745 | ||
252b5132 RH |
17746 | /* Estimate the size of a frag before relaxing. Unless this is the |
17747 | mips16, we are not really relaxing here, and the final size is | |
17748 | encoded in the subtype information. For the mips16, we have to | |
17749 | decide whether we are using an extended opcode or not. */ | |
17750 | ||
252b5132 | 17751 | int |
17a2f251 | 17752 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17753 | { |
5919d012 | 17754 | int change; |
252b5132 | 17755 | |
4a6a3df4 AO |
17756 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17757 | { | |
17758 | ||
b34976b6 AM |
17759 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17760 | ||
4a6a3df4 AO |
17761 | return fragp->fr_var; |
17762 | } | |
17763 | ||
252b5132 | 17764 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17765 | /* We don't want to modify the EXTENDED bit here; it might get us |
17766 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17767 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17768 | |
df58fc94 RS |
17769 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17770 | { | |
17771 | int length = 4; | |
17772 | ||
17773 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17774 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17775 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17776 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17777 | fragp->fr_var = length; | |
17778 | ||
17779 | return length; | |
17780 | } | |
17781 | ||
252b5132 | 17782 | if (mips_pic == NO_PIC) |
5919d012 | 17783 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17784 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17785 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17786 | else if (mips_pic == VXWORKS_PIC) |
17787 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17788 | change = 0; | |
252b5132 RH |
17789 | else |
17790 | abort (); | |
17791 | ||
17792 | if (change) | |
17793 | { | |
4d7206a2 | 17794 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17795 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17796 | } |
4d7206a2 RS |
17797 | else |
17798 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17799 | } |
17800 | ||
17801 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17802 | should be converted into a reloc against a section. */ |
252b5132 RH |
17803 | |
17804 | int | |
17a2f251 | 17805 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17806 | { |
252b5132 RH |
17807 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17808 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17809 | return 0; | |
a161fe53 | 17810 | |
252b5132 RH |
17811 | if (fixp->fx_addsy == NULL) |
17812 | return 1; | |
a161fe53 | 17813 | |
de7e6852 RS |
17814 | /* If symbol SYM is in a mergeable section, relocations of the form |
17815 | SYM + 0 can usually be made section-relative. The mergeable data | |
17816 | is then identified by the section offset rather than by the symbol. | |
17817 | ||
17818 | However, if we're generating REL LO16 relocations, the offset is split | |
17819 | between the LO16 and parterning high part relocation. The linker will | |
17820 | need to recalculate the complete offset in order to correctly identify | |
17821 | the merge data. | |
17822 | ||
17823 | The linker has traditionally not looked for the parterning high part | |
17824 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17825 | placed anywhere. Rather than break backwards compatibility by changing | |
17826 | this, it seems better not to force the issue, and instead keep the | |
17827 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17828 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17829 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17830 | && HAVE_IN_PLACE_ADDENDS |
17831 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17832 | return 0; | |
17833 | ||
ce70d90a | 17834 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17835 | Likewise an in-range offset of limited PC-relative relocations may |
17836 | overflow the in-place relocatable field if recalculated against the | |
17837 | start address of the symbol's containing section. */ | |
ce70d90a | 17838 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17839 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17840 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17841 | return 0; |
17842 | ||
252b5132 | 17843 | #ifdef OBJ_ELF |
b314ec0e RS |
17844 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17845 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17846 | relocations against MIPS16 functions; in this case, the stub becomes | |
17847 | the function's canonical address. | |
17848 | ||
17849 | Floating-point stubs are stored in unique .mips16.call.* or | |
17850 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17851 | the first relocation in section S must be against F; this is how the | |
17852 | linker determines the target function. All relocations that might | |
17853 | resolve to T must also be against F. We therefore have the following | |
17854 | restrictions, which are given in an intentionally-redundant way: | |
17855 | ||
17856 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17857 | symbols. | |
17858 | ||
17859 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17860 | if that stub might be used. | |
17861 | ||
17862 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17863 | symbols. | |
17864 | ||
17865 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17866 | that stub might be used. | |
17867 | ||
17868 | There is a further restriction: | |
17869 | ||
df58fc94 RS |
17870 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17871 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17872 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17873 | encode the low bit. |
17874 | ||
df58fc94 RS |
17875 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17876 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17877 | such relocations on REL targets. | |
b314ec0e RS |
17878 | |
17879 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17880 | relocation against some symbol R, no relocation against R may be | |
17881 | reduced. (Note that this deals with (2) as well as (1) because | |
17882 | relocations against global symbols will never be reduced on ELF | |
17883 | targets.) This approach is a little simpler than trying to detect | |
17884 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17885 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17886 | if (IS_ELF |
b314ec0e | 17887 | && fixp->fx_subsy == NULL |
30c09090 | 17888 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17889 | || *symbol_get_tc (fixp->fx_addsy) |
17890 | || (HAVE_IN_PLACE_ADDENDS | |
17891 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17892 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17893 | return 0; |
17894 | #endif | |
a161fe53 | 17895 | |
252b5132 RH |
17896 | return 1; |
17897 | } | |
17898 | ||
17899 | /* Translate internal representation of relocation info to BFD target | |
17900 | format. */ | |
17901 | ||
17902 | arelent ** | |
17a2f251 | 17903 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17904 | { |
17905 | static arelent *retval[4]; | |
17906 | arelent *reloc; | |
17907 | bfd_reloc_code_real_type code; | |
17908 | ||
4b0cff4e TS |
17909 | memset (retval, 0, sizeof(retval)); |
17910 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17911 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17912 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17913 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17914 | ||
bad36eac DJ |
17915 | if (fixp->fx_pcrel) |
17916 | { | |
df58fc94 RS |
17917 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17918 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17919 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17920 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17921 | |
17922 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17923 | Relocations want only the symbol offset. */ | |
17924 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17925 | if (!IS_ELF) |
bad36eac DJ |
17926 | { |
17927 | /* A gruesome hack which is a result of the gruesome gas | |
17928 | reloc handling. What's worse, for COFF (as opposed to | |
17929 | ECOFF), we might need yet another copy of reloc->address. | |
17930 | See bfd_install_relocation. */ | |
17931 | reloc->addend += reloc->address; | |
17932 | } | |
17933 | } | |
17934 | else | |
17935 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17936 | |
438c16b8 TS |
17937 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17938 | entry to be used in the relocation's section offset. */ | |
17939 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17940 | { |
17941 | reloc->address = reloc->addend; | |
17942 | reloc->addend = 0; | |
17943 | } | |
17944 | ||
252b5132 | 17945 | code = fixp->fx_r_type; |
252b5132 | 17946 | |
bad36eac | 17947 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17948 | if (reloc->howto == NULL) |
17949 | { | |
17950 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17951 | _("Can not represent %s relocation in this object file format"), | |
17952 | bfd_get_reloc_code_name (code)); | |
17953 | retval[0] = NULL; | |
17954 | } | |
17955 | ||
17956 | return retval; | |
17957 | } | |
17958 | ||
17959 | /* Relax a machine dependent frag. This returns the amount by which | |
17960 | the current size of the frag should change. */ | |
17961 | ||
17962 | int | |
17a2f251 | 17963 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17964 | { |
4a6a3df4 AO |
17965 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17966 | { | |
17967 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17968 | |
17969 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17970 | |
17971 | return fragp->fr_var - old_var; | |
17972 | } | |
17973 | ||
df58fc94 RS |
17974 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17975 | { | |
17976 | offsetT old_var = fragp->fr_var; | |
17977 | offsetT new_var = 4; | |
17978 | ||
17979 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17980 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17981 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17982 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17983 | fragp->fr_var = new_var; | |
17984 | ||
17985 | return new_var - old_var; | |
17986 | } | |
17987 | ||
252b5132 RH |
17988 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17989 | return 0; | |
17990 | ||
c4e7957c | 17991 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17992 | { |
17993 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17994 | return 0; | |
17995 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17996 | return 2; | |
17997 | } | |
17998 | else | |
17999 | { | |
18000 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18001 | return 0; | |
18002 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18003 | return -2; | |
18004 | } | |
18005 | ||
18006 | return 0; | |
18007 | } | |
18008 | ||
18009 | /* Convert a machine dependent frag. */ | |
18010 | ||
18011 | void | |
17a2f251 | 18012 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18013 | { |
4a6a3df4 AO |
18014 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18015 | { | |
4d68580a | 18016 | char *buf; |
4a6a3df4 AO |
18017 | unsigned long insn; |
18018 | expressionS exp; | |
18019 | fixS *fixp; | |
b34976b6 | 18020 | |
4d68580a RS |
18021 | buf = fragp->fr_literal + fragp->fr_fix; |
18022 | insn = read_insn (buf); | |
b34976b6 | 18023 | |
4a6a3df4 AO |
18024 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18025 | { | |
18026 | /* We generate a fixup instead of applying it right now | |
18027 | because, if there are linker relaxations, we're going to | |
18028 | need the relocations. */ | |
18029 | exp.X_op = O_symbol; | |
18030 | exp.X_add_symbol = fragp->fr_symbol; | |
18031 | exp.X_add_number = fragp->fr_offset; | |
18032 | ||
4d68580a RS |
18033 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18034 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18035 | fixp->fx_file = fragp->fr_file; |
18036 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18037 | |
4d68580a | 18038 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18039 | } |
18040 | else | |
18041 | { | |
18042 | int i; | |
18043 | ||
18044 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18045 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18046 | |
18047 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18048 | goto uncond; | |
18049 | ||
18050 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18051 | { | |
18052 | /* Reverse the branch. */ | |
18053 | switch ((insn >> 28) & 0xf) | |
18054 | { | |
18055 | case 4: | |
18056 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
18057 | have the condition reversed by tweaking a single | |
18058 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 18059 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
18060 | insn ^= 0x00010000; |
18061 | break; | |
18062 | ||
18063 | case 0: | |
18064 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18065 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18066 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18067 | insn ^= 0x00010000; |
18068 | break; | |
b34976b6 | 18069 | |
4a6a3df4 AO |
18070 | case 1: |
18071 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18072 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18073 | insn ^= 0x04000000; |
18074 | break; | |
18075 | ||
18076 | default: | |
18077 | abort (); | |
18078 | } | |
18079 | } | |
18080 | ||
18081 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18082 | { | |
18083 | /* Clear the and-link bit. */ | |
9c2799c2 | 18084 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18085 | |
54f4ddb3 TS |
18086 | /* bltzal 0x04100000 bgezal 0x04110000 |
18087 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18088 | insn &= ~0x00100000; |
18089 | } | |
18090 | ||
18091 | /* Branch over the branch (if the branch was likely) or the | |
18092 | full jump (not likely case). Compute the offset from the | |
18093 | current instruction to branch to. */ | |
18094 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18095 | i = 16; | |
18096 | else | |
18097 | { | |
18098 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18099 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18100 | /* How many bytes in instructions from here to the end? */ |
18101 | i = fragp->fr_var - i; | |
18102 | } | |
18103 | /* Convert to instruction count. */ | |
18104 | i >>= 2; | |
18105 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18106 | i--; |
4a6a3df4 AO |
18107 | insn |= i; |
18108 | /* Branch over the jump. */ | |
4d68580a | 18109 | buf = write_insn (buf, insn); |
4a6a3df4 | 18110 | |
54f4ddb3 | 18111 | /* nop */ |
4d68580a | 18112 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18113 | |
18114 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18115 | { | |
18116 | /* beql $0, $0, 2f */ | |
18117 | insn = 0x50000000; | |
18118 | /* Compute the PC offset from the current instruction to | |
18119 | the end of the variable frag. */ | |
18120 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18121 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18122 | /* How many bytes in instructions from here to the end? */ |
18123 | i = fragp->fr_var - i; | |
18124 | /* Convert to instruction count. */ | |
18125 | i >>= 2; | |
18126 | /* Don't decrement i, because we want to branch over the | |
18127 | delay slot. */ | |
4a6a3df4 | 18128 | insn |= i; |
4a6a3df4 | 18129 | |
4d68580a RS |
18130 | buf = write_insn (buf, insn); |
18131 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18132 | } |
18133 | ||
18134 | uncond: | |
18135 | if (mips_pic == NO_PIC) | |
18136 | { | |
18137 | /* j or jal. */ | |
18138 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18139 | ? 0x0c000000 : 0x08000000); | |
18140 | exp.X_op = O_symbol; | |
18141 | exp.X_add_symbol = fragp->fr_symbol; | |
18142 | exp.X_add_number = fragp->fr_offset; | |
18143 | ||
4d68580a RS |
18144 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18145 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18146 | fixp->fx_file = fragp->fr_file; |
18147 | fixp->fx_line = fragp->fr_line; | |
18148 | ||
4d68580a | 18149 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18150 | } |
18151 | else | |
18152 | { | |
66b3e8da MR |
18153 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18154 | ||
4a6a3df4 | 18155 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18156 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18157 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18158 | exp.X_op = O_symbol; |
18159 | exp.X_add_symbol = fragp->fr_symbol; | |
18160 | exp.X_add_number = fragp->fr_offset; | |
18161 | ||
18162 | if (fragp->fr_offset) | |
18163 | { | |
18164 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18165 | exp.X_add_number = 0; | |
18166 | } | |
18167 | ||
4d68580a RS |
18168 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18169 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18170 | fixp->fx_file = fragp->fr_file; |
18171 | fixp->fx_line = fragp->fr_line; | |
18172 | ||
4d68580a | 18173 | buf = write_insn (buf, insn); |
b34976b6 | 18174 | |
4a6a3df4 | 18175 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18176 | /* nop */ |
18177 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18178 | |
18179 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18180 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18181 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18182 | |
4d68580a RS |
18183 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18184 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18185 | fixp->fx_file = fragp->fr_file; |
18186 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18187 | |
4d68580a | 18188 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18189 | |
18190 | /* j(al)r $at. */ | |
18191 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18192 | insn = 0x0000f809; |
4a6a3df4 | 18193 | else |
66b3e8da MR |
18194 | insn = 0x00000008; |
18195 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18196 | |
4d68580a | 18197 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18198 | } |
18199 | } | |
18200 | ||
4a6a3df4 | 18201 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18202 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18203 | return; |
18204 | } | |
18205 | ||
df58fc94 RS |
18206 | /* Relax microMIPS branches. */ |
18207 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18208 | { | |
4d68580a | 18209 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18210 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18211 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18212 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18213 | bfd_boolean short_ds; |
df58fc94 RS |
18214 | unsigned long insn; |
18215 | expressionS exp; | |
18216 | fixS *fixp; | |
18217 | ||
18218 | exp.X_op = O_symbol; | |
18219 | exp.X_add_symbol = fragp->fr_symbol; | |
18220 | exp.X_add_number = fragp->fr_offset; | |
18221 | ||
18222 | fragp->fr_fix += fragp->fr_var; | |
18223 | ||
18224 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18225 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18226 | { | |
18227 | /* We generate a fixup instead of applying it right now, | |
18228 | because if there is linker relaxation, we're going to | |
18229 | need the relocations. */ | |
18230 | if (type == 'D') | |
4d68580a | 18231 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18232 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18233 | else if (type == 'E') | |
4d68580a | 18234 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18235 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18236 | else | |
18237 | abort (); | |
18238 | ||
18239 | fixp->fx_file = fragp->fr_file; | |
18240 | fixp->fx_line = fragp->fr_line; | |
18241 | ||
18242 | /* These relocations can have an addend that won't fit in | |
18243 | 2 octets. */ | |
18244 | fixp->fx_no_overflow = 1; | |
18245 | ||
18246 | return; | |
18247 | } | |
18248 | ||
2309ddf2 | 18249 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18250 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18251 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18252 | { | |
18253 | /* We generate a fixup instead of applying it right now, | |
18254 | because if there is linker relaxation, we're going to | |
18255 | need the relocations. */ | |
4d68580a RS |
18256 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18257 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18258 | fixp->fx_file = fragp->fr_file; |
18259 | fixp->fx_line = fragp->fr_line; | |
18260 | ||
18261 | if (type == 0) | |
18262 | return; | |
18263 | } | |
18264 | ||
18265 | /* Relax 16-bit branches to 32-bit branches. */ | |
18266 | if (type != 0) | |
18267 | { | |
4d68580a | 18268 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18269 | |
18270 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18271 | insn = 0x94000000; /* beq */ | |
18272 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18273 | { | |
18274 | unsigned long regno; | |
18275 | ||
18276 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18277 | regno = micromips_to_32_reg_d_map [regno]; | |
18278 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18279 | insn |= regno << MICROMIPSOP_SH_RS; | |
18280 | } | |
18281 | else | |
18282 | abort (); | |
18283 | ||
18284 | /* Nothing else to do, just write it out. */ | |
18285 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18286 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18287 | { | |
4d68580a RS |
18288 | buf = write_compressed_insn (buf, insn, 4); |
18289 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18290 | return; |
18291 | } | |
18292 | } | |
18293 | else | |
4d68580a | 18294 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18295 | |
18296 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18297 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18298 | _("Relaxed out-of-range branch into a jump")); | |
18299 | ||
2309ddf2 MR |
18300 | /* Set the short-delay-slot bit. */ |
18301 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18302 | |
18303 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18304 | { | |
18305 | symbolS *l; | |
18306 | ||
18307 | /* Reverse the branch. */ | |
18308 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18309 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18310 | insn ^= 0x20000000; | |
18311 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18312 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18313 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18314 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18315 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18316 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18317 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18318 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18319 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18320 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18321 | insn ^= 0x00400000; | |
18322 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18323 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18324 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18325 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18326 | insn ^= 0x00200000; | |
18327 | else | |
18328 | abort (); | |
18329 | ||
18330 | if (al) | |
18331 | { | |
18332 | /* Clear the and-link and short-delay-slot bits. */ | |
18333 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18334 | ||
18335 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18336 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18337 | insn &= ~0x02200000; | |
18338 | } | |
18339 | ||
18340 | /* Make a label at the end for use with the branch. */ | |
18341 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18342 | micromips_label_inc (); | |
18343 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18344 | if (IS_ELF) | |
18345 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18346 | #endif | |
18347 | ||
18348 | /* Refer to it. */ | |
4d68580a RS |
18349 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18350 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18351 | fixp->fx_file = fragp->fr_file; |
18352 | fixp->fx_line = fragp->fr_line; | |
18353 | ||
18354 | /* Branch over the jump. */ | |
4d68580a | 18355 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18356 | if (!compact) |
4d68580a RS |
18357 | /* nop */ |
18358 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18359 | } |
18360 | ||
18361 | if (mips_pic == NO_PIC) | |
18362 | { | |
2309ddf2 MR |
18363 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18364 | ||
df58fc94 RS |
18365 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18366 | insn = al ? jal : 0xd4000000; | |
18367 | ||
4d68580a RS |
18368 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18369 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18370 | fixp->fx_file = fragp->fr_file; |
18371 | fixp->fx_line = fragp->fr_line; | |
18372 | ||
4d68580a | 18373 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18374 | if (compact) |
4d68580a RS |
18375 | /* nop */ |
18376 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18377 | } |
18378 | else | |
18379 | { | |
18380 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18381 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18382 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18383 | |
18384 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18385 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18386 | insn |= at << MICROMIPSOP_SH_RT; | |
18387 | ||
18388 | if (exp.X_add_number) | |
18389 | { | |
18390 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18391 | exp.X_add_number = 0; | |
18392 | } | |
18393 | ||
4d68580a RS |
18394 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18395 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18396 | fixp->fx_file = fragp->fr_file; |
18397 | fixp->fx_line = fragp->fr_line; | |
18398 | ||
4d68580a | 18399 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18400 | |
18401 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18402 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18403 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18404 | ||
4d68580a RS |
18405 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18406 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18407 | fixp->fx_file = fragp->fr_file; |
18408 | fixp->fx_line = fragp->fr_line; | |
18409 | ||
4d68580a | 18410 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18411 | |
18412 | /* jr/jrc/jalr/jalrs $at */ | |
18413 | insn = al ? jalr : jr; | |
18414 | insn |= at << MICROMIPSOP_SH_MJ; | |
18415 | ||
4d68580a | 18416 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18417 | } |
18418 | ||
4d68580a | 18419 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18420 | return; |
18421 | } | |
18422 | ||
252b5132 RH |
18423 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18424 | { | |
18425 | int type; | |
3994f87e | 18426 | const struct mips16_immed_operand *op; |
252b5132 | 18427 | offsetT val; |
5c04167a RS |
18428 | char *buf; |
18429 | unsigned int user_length, length; | |
252b5132 | 18430 | unsigned long insn; |
5c04167a | 18431 | bfd_boolean ext; |
252b5132 RH |
18432 | |
18433 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18434 | op = mips16_immed_operands; | |
18435 | while (op->type != type) | |
18436 | ++op; | |
18437 | ||
5c04167a | 18438 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18439 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18440 | if (op->pcrel) |
18441 | { | |
18442 | addressT addr; | |
18443 | ||
18444 | addr = fragp->fr_address + fragp->fr_fix; | |
18445 | ||
18446 | /* The rules for the base address of a PC relative reloc are | |
18447 | complicated; see mips16_extended_frag. */ | |
18448 | if (type == 'p' || type == 'q') | |
18449 | { | |
18450 | addr += 2; | |
18451 | if (ext) | |
18452 | addr += 2; | |
18453 | /* Ignore the low bit in the target, since it will be | |
18454 | set for a text label. */ | |
18455 | if ((val & 1) != 0) | |
18456 | --val; | |
18457 | } | |
18458 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18459 | addr -= 4; | |
18460 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18461 | addr -= 2; | |
18462 | ||
18463 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18464 | val -= addr; | |
18465 | ||
18466 | /* Make sure the section winds up with the alignment we have | |
18467 | assumed. */ | |
18468 | if (op->shift > 0) | |
18469 | record_alignment (asec, op->shift); | |
18470 | } | |
18471 | ||
18472 | if (ext | |
18473 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18474 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18475 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18476 | _("extended instruction in delay slot")); | |
18477 | ||
5c04167a | 18478 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18479 | |
4d68580a | 18480 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18481 | if (ext) |
18482 | insn |= MIPS16_EXTEND; | |
252b5132 | 18483 | |
5c04167a RS |
18484 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18485 | user_length = 4; | |
18486 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18487 | user_length = 2; | |
18488 | else | |
18489 | user_length = 0; | |
18490 | ||
43c0598f | 18491 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18492 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18493 | |
5c04167a RS |
18494 | length = (ext ? 4 : 2); |
18495 | gas_assert (mips16_opcode_length (insn) == length); | |
18496 | write_compressed_insn (buf, insn, length); | |
18497 | fragp->fr_fix += length; | |
252b5132 RH |
18498 | } |
18499 | else | |
18500 | { | |
df58fc94 RS |
18501 | relax_substateT subtype = fragp->fr_subtype; |
18502 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18503 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18504 | int first, second; |
18505 | fixS *fixp; | |
252b5132 | 18506 | |
df58fc94 RS |
18507 | first = RELAX_FIRST (subtype); |
18508 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18509 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18510 | |
df58fc94 RS |
18511 | /* If the delay slot chosen does not match the size of the instruction, |
18512 | then emit a warning. */ | |
18513 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18514 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18515 | { | |
18516 | relax_substateT s; | |
18517 | const char *msg; | |
18518 | ||
18519 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18520 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18521 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18522 | msg = macro_warning (s); | |
18523 | if (msg != NULL) | |
db9b2be4 | 18524 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18525 | subtype &= ~s; |
18526 | } | |
18527 | ||
584892a6 | 18528 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18529 | if (use_second == second_longer) |
584892a6 | 18530 | { |
df58fc94 RS |
18531 | relax_substateT s; |
18532 | const char *msg; | |
18533 | ||
18534 | s = (subtype | |
18535 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18536 | msg = macro_warning (s); | |
18537 | if (msg != NULL) | |
db9b2be4 | 18538 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18539 | subtype &= ~s; |
584892a6 RS |
18540 | } |
18541 | ||
4d7206a2 RS |
18542 | /* Go through all the fixups for the first sequence. Disable them |
18543 | (by marking them as done) if we're going to use the second | |
18544 | sequence instead. */ | |
18545 | while (fixp | |
18546 | && fixp->fx_frag == fragp | |
18547 | && fixp->fx_where < fragp->fr_fix - second) | |
18548 | { | |
df58fc94 | 18549 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18550 | fixp->fx_done = 1; |
18551 | fixp = fixp->fx_next; | |
18552 | } | |
252b5132 | 18553 | |
4d7206a2 RS |
18554 | /* Go through the fixups for the second sequence. Disable them if |
18555 | we're going to use the first sequence, otherwise adjust their | |
18556 | addresses to account for the relaxation. */ | |
18557 | while (fixp && fixp->fx_frag == fragp) | |
18558 | { | |
df58fc94 | 18559 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18560 | fixp->fx_where -= first; |
18561 | else | |
18562 | fixp->fx_done = 1; | |
18563 | fixp = fixp->fx_next; | |
18564 | } | |
18565 | ||
18566 | /* Now modify the frag contents. */ | |
df58fc94 | 18567 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18568 | { |
18569 | char *start; | |
18570 | ||
18571 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18572 | memmove (start, start + first, second); | |
18573 | fragp->fr_fix -= first; | |
18574 | } | |
18575 | else | |
18576 | fragp->fr_fix -= second; | |
252b5132 RH |
18577 | } |
18578 | } | |
18579 | ||
18580 | #ifdef OBJ_ELF | |
18581 | ||
18582 | /* This function is called after the relocs have been generated. | |
18583 | We've been storing mips16 text labels as odd. Here we convert them | |
18584 | back to even for the convenience of the debugger. */ | |
18585 | ||
18586 | void | |
17a2f251 | 18587 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18588 | { |
18589 | asymbol **syms; | |
18590 | unsigned int count, i; | |
18591 | ||
f43abd2b | 18592 | if (!IS_ELF) |
252b5132 RH |
18593 | return; |
18594 | ||
18595 | syms = bfd_get_outsymbols (stdoutput); | |
18596 | count = bfd_get_symcount (stdoutput); | |
18597 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18598 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18599 | && ((*syms)->value & 1) != 0) | |
18600 | { | |
18601 | (*syms)->value &= ~1; | |
18602 | /* If the symbol has an odd size, it was probably computed | |
18603 | incorrectly, so adjust that as well. */ | |
18604 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18605 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18606 | } | |
252b5132 RH |
18607 | } |
18608 | ||
18609 | #endif | |
18610 | ||
a1facbec MR |
18611 | /* This function is called whenever a label is defined, including fake |
18612 | labels instantiated off the dot special symbol. It is used when | |
18613 | handling branch delays; if a branch has a label, we assume we cannot | |
18614 | move it. This also bumps the value of the symbol by 1 in compressed | |
18615 | code. */ | |
252b5132 | 18616 | |
e1b47bd5 | 18617 | static void |
a1facbec | 18618 | mips_record_label (symbolS *sym) |
252b5132 | 18619 | { |
a8dbcb85 | 18620 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18621 | struct insn_label_list *l; |
18622 | ||
18623 | if (free_insn_labels == NULL) | |
18624 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18625 | else | |
18626 | { | |
18627 | l = free_insn_labels; | |
18628 | free_insn_labels = l->next; | |
18629 | } | |
18630 | ||
18631 | l->label = sym; | |
a8dbcb85 TS |
18632 | l->next = si->label_list; |
18633 | si->label_list = l; | |
a1facbec | 18634 | } |
07a53e5c | 18635 | |
a1facbec MR |
18636 | /* This function is called as tc_frob_label() whenever a label is defined |
18637 | and adds a DWARF-2 record we only want for true labels. */ | |
18638 | ||
18639 | void | |
18640 | mips_define_label (symbolS *sym) | |
18641 | { | |
18642 | mips_record_label (sym); | |
07a53e5c RH |
18643 | #ifdef OBJ_ELF |
18644 | dwarf2_emit_label (sym); | |
18645 | #endif | |
252b5132 | 18646 | } |
e1b47bd5 RS |
18647 | |
18648 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18649 | is defined. */ | |
18650 | ||
18651 | void | |
18652 | mips_add_dot_label (symbolS *sym) | |
18653 | { | |
18654 | mips_record_label (sym); | |
18655 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18656 | mips_compressed_mark_label (sym); | |
18657 | } | |
252b5132 RH |
18658 | \f |
18659 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18660 | ||
18661 | /* Some special processing for a MIPS ELF file. */ | |
18662 | ||
18663 | void | |
17a2f251 | 18664 | mips_elf_final_processing (void) |
252b5132 RH |
18665 | { |
18666 | /* Write out the register information. */ | |
316f5878 | 18667 | if (mips_abi != N64_ABI) |
252b5132 RH |
18668 | { |
18669 | Elf32_RegInfo s; | |
18670 | ||
18671 | s.ri_gprmask = mips_gprmask; | |
18672 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18673 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18674 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18675 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18676 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18677 | ||
18678 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18679 | ((Elf32_External_RegInfo *) | |
18680 | mips_regmask_frag)); | |
18681 | } | |
18682 | else | |
18683 | { | |
18684 | Elf64_Internal_RegInfo s; | |
18685 | ||
18686 | s.ri_gprmask = mips_gprmask; | |
18687 | s.ri_pad = 0; | |
18688 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18689 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18690 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18691 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18692 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18693 | ||
18694 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18695 | ((Elf64_External_RegInfo *) | |
18696 | mips_regmask_frag)); | |
18697 | } | |
18698 | ||
18699 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18700 | sort of BFD interface for this. */ | |
18701 | if (mips_any_noreorder) | |
18702 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18703 | if (mips_pic != NO_PIC) | |
143d77c5 | 18704 | { |
8b828383 | 18705 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18706 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18707 | } | |
18708 | if (mips_abicalls) | |
18709 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18710 | |
98d3f06f | 18711 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18712 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18713 | file_ase_dsp is true. */ | |
8b082fb1 | 18714 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18715 | /* We may need to define a new flag for MT ASE, and set this flag when |
18716 | file_ase_mt is true. */ | |
a4672219 TS |
18717 | if (file_ase_mips16) |
18718 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18719 | if (file_ase_micromips) |
18720 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18721 | #if 0 /* XXX FIXME */ |
18722 | if (file_ase_mips3d) | |
18723 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18724 | #endif | |
deec1734 CD |
18725 | if (file_ase_mdmx) |
18726 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18727 | |
bdaaa2e1 | 18728 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18729 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18730 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18731 | else if (mips_abi == O64_ABI) |
252b5132 | 18732 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18733 | else if (mips_abi == EABI_ABI) |
252b5132 | 18734 | { |
316f5878 | 18735 | if (!file_mips_gp32) |
252b5132 RH |
18736 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18737 | else | |
18738 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18739 | } | |
316f5878 | 18740 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18741 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18742 | ||
c9914766 | 18743 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18744 | |
18745 | if (mips_32bitmode) | |
18746 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18747 | |
18748 | #if 0 /* XXX FIXME */ | |
18749 | /* 32 bit code with 64 bit FP registers. */ | |
18750 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18751 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18752 | #endif | |
252b5132 RH |
18753 | } |
18754 | ||
18755 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18756 | \f | |
beae10d5 | 18757 | typedef struct proc { |
9b2f1d35 EC |
18758 | symbolS *func_sym; |
18759 | symbolS *func_end_sym; | |
beae10d5 KH |
18760 | unsigned long reg_mask; |
18761 | unsigned long reg_offset; | |
18762 | unsigned long fpreg_mask; | |
18763 | unsigned long fpreg_offset; | |
18764 | unsigned long frame_offset; | |
18765 | unsigned long frame_reg; | |
18766 | unsigned long pc_reg; | |
18767 | } procS; | |
252b5132 RH |
18768 | |
18769 | static procS cur_proc; | |
18770 | static procS *cur_proc_ptr; | |
18771 | static int numprocs; | |
18772 | ||
df58fc94 RS |
18773 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18774 | as "2", and a normal nop as "0". */ | |
18775 | ||
18776 | #define NOP_OPCODE_MIPS 0 | |
18777 | #define NOP_OPCODE_MIPS16 1 | |
18778 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18779 | |
18780 | char | |
18781 | mips_nop_opcode (void) | |
18782 | { | |
df58fc94 RS |
18783 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18784 | return NOP_OPCODE_MICROMIPS; | |
18785 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18786 | return NOP_OPCODE_MIPS16; | |
18787 | else | |
18788 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18789 | } |
18790 | ||
df58fc94 RS |
18791 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18792 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18793 | |
0a9ef439 | 18794 | void |
17a2f251 | 18795 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18796 | { |
df58fc94 | 18797 | char nop_opcode; |
742a56fe | 18798 | char *p; |
c67a084a NC |
18799 | int bytes, size, excess; |
18800 | valueT opcode; | |
742a56fe | 18801 | |
0a9ef439 RH |
18802 | if (fragp->fr_type != rs_align_code) |
18803 | return; | |
18804 | ||
742a56fe | 18805 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18806 | nop_opcode = *p; |
18807 | switch (nop_opcode) | |
a19d8eb0 | 18808 | { |
df58fc94 RS |
18809 | case NOP_OPCODE_MICROMIPS: |
18810 | opcode = micromips_nop32_insn.insn_opcode; | |
18811 | size = 4; | |
18812 | break; | |
18813 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18814 | opcode = mips16_nop_insn.insn_opcode; |
18815 | size = 2; | |
df58fc94 RS |
18816 | break; |
18817 | case NOP_OPCODE_MIPS: | |
18818 | default: | |
c67a084a NC |
18819 | opcode = nop_insn.insn_opcode; |
18820 | size = 4; | |
df58fc94 | 18821 | break; |
c67a084a | 18822 | } |
a19d8eb0 | 18823 | |
c67a084a NC |
18824 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18825 | excess = bytes % size; | |
df58fc94 RS |
18826 | |
18827 | /* Handle the leading part if we're not inserting a whole number of | |
18828 | instructions, and make it the end of the fixed part of the frag. | |
18829 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18830 | and use zeroes otherwise. */ | |
18831 | gas_assert (excess < 4); | |
18832 | fragp->fr_fix += excess; | |
18833 | switch (excess) | |
c67a084a | 18834 | { |
df58fc94 RS |
18835 | case 3: |
18836 | *p++ = '\0'; | |
18837 | /* Fall through. */ | |
18838 | case 2: | |
18839 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18840 | { | |
4d68580a | 18841 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18842 | break; |
18843 | } | |
18844 | *p++ = '\0'; | |
18845 | /* Fall through. */ | |
18846 | case 1: | |
18847 | *p++ = '\0'; | |
18848 | /* Fall through. */ | |
18849 | case 0: | |
18850 | break; | |
a19d8eb0 | 18851 | } |
c67a084a NC |
18852 | |
18853 | md_number_to_chars (p, opcode, size); | |
18854 | fragp->fr_var = size; | |
a19d8eb0 CP |
18855 | } |
18856 | ||
252b5132 | 18857 | static void |
17a2f251 | 18858 | md_obj_begin (void) |
252b5132 RH |
18859 | { |
18860 | } | |
18861 | ||
18862 | static void | |
17a2f251 | 18863 | md_obj_end (void) |
252b5132 | 18864 | { |
54f4ddb3 | 18865 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18866 | if (cur_proc_ptr) |
9a41af64 | 18867 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18868 | } |
18869 | ||
18870 | static long | |
17a2f251 | 18871 | get_number (void) |
252b5132 RH |
18872 | { |
18873 | int negative = 0; | |
18874 | long val = 0; | |
18875 | ||
18876 | if (*input_line_pointer == '-') | |
18877 | { | |
18878 | ++input_line_pointer; | |
18879 | negative = 1; | |
18880 | } | |
3882b010 | 18881 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18882 | as_bad (_("expected simple number")); |
252b5132 RH |
18883 | if (input_line_pointer[0] == '0') |
18884 | { | |
18885 | if (input_line_pointer[1] == 'x') | |
18886 | { | |
18887 | input_line_pointer += 2; | |
3882b010 | 18888 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18889 | { |
18890 | val <<= 4; | |
18891 | val |= hex_value (*input_line_pointer++); | |
18892 | } | |
18893 | return negative ? -val : val; | |
18894 | } | |
18895 | else | |
18896 | { | |
18897 | ++input_line_pointer; | |
3882b010 | 18898 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18899 | { |
18900 | val <<= 3; | |
18901 | val |= *input_line_pointer++ - '0'; | |
18902 | } | |
18903 | return negative ? -val : val; | |
18904 | } | |
18905 | } | |
3882b010 | 18906 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18907 | { |
18908 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18909 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18910 | as_warn (_("invalid number")); |
252b5132 RH |
18911 | return -1; |
18912 | } | |
3882b010 | 18913 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18914 | { |
18915 | val *= 10; | |
18916 | val += *input_line_pointer++ - '0'; | |
18917 | } | |
18918 | return negative ? -val : val; | |
18919 | } | |
18920 | ||
18921 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18922 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18923 | case .file implies DWARF-2. */ | |
18924 | ||
18925 | static void | |
17a2f251 | 18926 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18927 | { |
ecb4347a DJ |
18928 | static int first_file_directive = 0; |
18929 | ||
c5dd6aab DJ |
18930 | if (ECOFF_DEBUGGING) |
18931 | { | |
18932 | get_number (); | |
18933 | s_app_file (0); | |
18934 | } | |
18935 | else | |
ecb4347a DJ |
18936 | { |
18937 | char *filename; | |
18938 | ||
18939 | filename = dwarf2_directive_file (0); | |
18940 | ||
18941 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18942 | directive even for stabs output. Make sure that this | |
18943 | ".file" is handled. Note that you need a version of GCC | |
18944 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18945 | if (filename != NULL && ! first_file_directive) | |
18946 | { | |
18947 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18948 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18949 | } |
18950 | first_file_directive = 1; | |
18951 | } | |
c5dd6aab DJ |
18952 | } |
18953 | ||
18954 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18955 | |
18956 | static void | |
17a2f251 | 18957 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18958 | { |
c5dd6aab DJ |
18959 | if (!ECOFF_DEBUGGING) |
18960 | dwarf2_directive_loc (0); | |
252b5132 RH |
18961 | } |
18962 | ||
252b5132 RH |
18963 | /* The .end directive. */ |
18964 | ||
18965 | static void | |
17a2f251 | 18966 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18967 | { |
18968 | symbolS *p; | |
252b5132 | 18969 | |
7a621144 DJ |
18970 | /* Following functions need their own .frame and .cprestore directives. */ |
18971 | mips_frame_reg_valid = 0; | |
18972 | mips_cprestore_valid = 0; | |
18973 | ||
252b5132 RH |
18974 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18975 | { | |
18976 | p = get_symbol (); | |
18977 | demand_empty_rest_of_line (); | |
18978 | } | |
18979 | else | |
18980 | p = NULL; | |
18981 | ||
14949570 | 18982 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18983 | as_warn (_(".end not in text section")); |
18984 | ||
18985 | if (!cur_proc_ptr) | |
18986 | { | |
18987 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18988 | demand_empty_rest_of_line (); | |
18989 | return; | |
18990 | } | |
18991 | ||
18992 | if (p != NULL) | |
18993 | { | |
9c2799c2 | 18994 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18995 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18996 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18997 | |
18998 | if (debug_type == DEBUG_STABS) | |
18999 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19000 | S_GET_NAME (p)); | |
252b5132 RH |
19001 | } |
19002 | else | |
19003 | as_warn (_(".end directive missing or unknown symbol")); | |
19004 | ||
2132e3a3 | 19005 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19006 | /* Create an expression to calculate the size of the function. */ |
19007 | if (p && cur_proc_ptr) | |
19008 | { | |
19009 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19010 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19011 | ||
19012 | obj->size = exp; | |
19013 | exp->X_op = O_subtract; | |
19014 | exp->X_add_symbol = symbol_temp_new_now (); | |
19015 | exp->X_op_symbol = p; | |
19016 | exp->X_add_number = 0; | |
19017 | ||
19018 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19019 | } | |
19020 | ||
ecb4347a | 19021 | /* Generate a .pdr section. */ |
f43abd2b | 19022 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19023 | { |
19024 | segT saved_seg = now_seg; | |
19025 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19026 | expressionS exp; |
19027 | char *fragp; | |
252b5132 | 19028 | |
252b5132 | 19029 | #ifdef md_flush_pending_output |
ecb4347a | 19030 | md_flush_pending_output (); |
252b5132 RH |
19031 | #endif |
19032 | ||
9c2799c2 | 19033 | gas_assert (pdr_seg); |
ecb4347a | 19034 | subseg_set (pdr_seg, 0); |
252b5132 | 19035 | |
ecb4347a DJ |
19036 | /* Write the symbol. */ |
19037 | exp.X_op = O_symbol; | |
19038 | exp.X_add_symbol = p; | |
19039 | exp.X_add_number = 0; | |
19040 | emit_expr (&exp, 4); | |
252b5132 | 19041 | |
ecb4347a | 19042 | fragp = frag_more (7 * 4); |
252b5132 | 19043 | |
17a2f251 TS |
19044 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19045 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19046 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19047 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19048 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19049 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19050 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19051 | |
ecb4347a DJ |
19052 | subseg_set (saved_seg, saved_subseg); |
19053 | } | |
19054 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19055 | |
19056 | cur_proc_ptr = NULL; | |
19057 | } | |
19058 | ||
19059 | /* The .aent and .ent directives. */ | |
19060 | ||
19061 | static void | |
17a2f251 | 19062 | s_mips_ent (int aent) |
252b5132 | 19063 | { |
252b5132 | 19064 | symbolS *symbolP; |
252b5132 RH |
19065 | |
19066 | symbolP = get_symbol (); | |
19067 | if (*input_line_pointer == ',') | |
f9419b05 | 19068 | ++input_line_pointer; |
252b5132 | 19069 | SKIP_WHITESPACE (); |
3882b010 | 19070 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19071 | || *input_line_pointer == '-') |
874e8986 | 19072 | get_number (); |
252b5132 | 19073 | |
14949570 | 19074 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19075 | as_warn (_(".ent or .aent not in text section.")); |
19076 | ||
19077 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19078 | as_warn (_("missing .end")); |
252b5132 RH |
19079 | |
19080 | if (!aent) | |
19081 | { | |
7a621144 DJ |
19082 | /* This function needs its own .frame and .cprestore directives. */ |
19083 | mips_frame_reg_valid = 0; | |
19084 | mips_cprestore_valid = 0; | |
19085 | ||
252b5132 RH |
19086 | cur_proc_ptr = &cur_proc; |
19087 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19088 | ||
9b2f1d35 | 19089 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19090 | |
f9419b05 | 19091 | ++numprocs; |
ecb4347a DJ |
19092 | |
19093 | if (debug_type == DEBUG_STABS) | |
19094 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19095 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19096 | } |
19097 | ||
7c0fc524 MR |
19098 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19099 | ||
252b5132 RH |
19100 | demand_empty_rest_of_line (); |
19101 | } | |
19102 | ||
19103 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19104 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19105 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19106 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19107 | symbol table (in the mdebug section). */ |
19108 | ||
19109 | static void | |
17a2f251 | 19110 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19111 | { |
ecb4347a | 19112 | #ifdef OBJ_ELF |
f43abd2b | 19113 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19114 | { |
19115 | long val; | |
252b5132 | 19116 | |
ecb4347a DJ |
19117 | if (cur_proc_ptr == (procS *) NULL) |
19118 | { | |
19119 | as_warn (_(".frame outside of .ent")); | |
19120 | demand_empty_rest_of_line (); | |
19121 | return; | |
19122 | } | |
252b5132 | 19123 | |
ecb4347a DJ |
19124 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19125 | ||
19126 | SKIP_WHITESPACE (); | |
19127 | if (*input_line_pointer++ != ',' | |
19128 | || get_absolute_expression_and_terminator (&val) != ',') | |
19129 | { | |
19130 | as_warn (_("Bad .frame directive")); | |
19131 | --input_line_pointer; | |
19132 | demand_empty_rest_of_line (); | |
19133 | return; | |
19134 | } | |
252b5132 | 19135 | |
ecb4347a DJ |
19136 | cur_proc_ptr->frame_offset = val; |
19137 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19138 | |
252b5132 | 19139 | demand_empty_rest_of_line (); |
252b5132 | 19140 | } |
ecb4347a DJ |
19141 | else |
19142 | #endif /* OBJ_ELF */ | |
19143 | s_ignore (ignore); | |
252b5132 RH |
19144 | } |
19145 | ||
bdaaa2e1 KH |
19146 | /* The .fmask and .mask directives. If the mdebug section is present |
19147 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19148 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19149 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19150 | make reference to the ecoff symbol table (in the mdebug section). */ |
19151 | ||
19152 | static void | |
17a2f251 | 19153 | s_mips_mask (int reg_type) |
252b5132 | 19154 | { |
ecb4347a | 19155 | #ifdef OBJ_ELF |
f43abd2b | 19156 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19157 | { |
ecb4347a | 19158 | long mask, off; |
252b5132 | 19159 | |
ecb4347a DJ |
19160 | if (cur_proc_ptr == (procS *) NULL) |
19161 | { | |
19162 | as_warn (_(".mask/.fmask outside of .ent")); | |
19163 | demand_empty_rest_of_line (); | |
19164 | return; | |
19165 | } | |
252b5132 | 19166 | |
ecb4347a DJ |
19167 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19168 | { | |
19169 | as_warn (_("Bad .mask/.fmask directive")); | |
19170 | --input_line_pointer; | |
19171 | demand_empty_rest_of_line (); | |
19172 | return; | |
19173 | } | |
252b5132 | 19174 | |
ecb4347a DJ |
19175 | off = get_absolute_expression (); |
19176 | ||
19177 | if (reg_type == 'F') | |
19178 | { | |
19179 | cur_proc_ptr->fpreg_mask = mask; | |
19180 | cur_proc_ptr->fpreg_offset = off; | |
19181 | } | |
19182 | else | |
19183 | { | |
19184 | cur_proc_ptr->reg_mask = mask; | |
19185 | cur_proc_ptr->reg_offset = off; | |
19186 | } | |
19187 | ||
19188 | demand_empty_rest_of_line (); | |
252b5132 RH |
19189 | } |
19190 | else | |
ecb4347a DJ |
19191 | #endif /* OBJ_ELF */ |
19192 | s_ignore (reg_type); | |
252b5132 RH |
19193 | } |
19194 | ||
316f5878 RS |
19195 | /* A table describing all the processors gas knows about. Names are |
19196 | matched in the order listed. | |
e7af610e | 19197 | |
316f5878 RS |
19198 | To ease comparison, please keep this table in the same order as |
19199 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19200 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19201 | { | |
316f5878 | 19202 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19203 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19204 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19205 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19206 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19207 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19208 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19209 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19210 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19211 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19212 | |
19213 | /* MIPS I */ | |
ad3fea08 TS |
19214 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19215 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19216 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19217 | |
19218 | /* MIPS II */ | |
ad3fea08 | 19219 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19220 | |
19221 | /* MIPS III */ | |
ad3fea08 TS |
19222 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19223 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19224 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19225 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19226 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19227 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19228 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19229 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19230 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19231 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19232 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19233 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19234 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19235 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19236 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19237 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19238 | |
19239 | /* MIPS IV */ | |
ad3fea08 TS |
19240 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19241 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19242 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19243 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19244 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19245 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19246 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19247 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19248 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19249 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19250 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19251 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19252 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19253 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19254 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19255 | |
19256 | /* MIPS 32 */ | |
ad3fea08 TS |
19257 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19258 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19259 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19260 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19261 | ||
19262 | /* MIPS 32 Release 2 */ | |
19263 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19264 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19265 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19266 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19267 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19268 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19269 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19270 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19271 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19272 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19273 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19274 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19275 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19276 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19277 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19278 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19279 | /* Deprecated forms of the above. */ | |
19280 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19281 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19282 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19283 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19284 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19285 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19286 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19287 | /* Deprecated forms of the above. */ | |
19288 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19289 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19290 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19291 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19292 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19293 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19294 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19295 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19296 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19297 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19298 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19299 | /* Deprecated forms of the above. */ | |
19300 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19301 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19302 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19303 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19304 | /* 34Kn is a 34kc without DSP. */ |
19305 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19306 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19307 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19308 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19309 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19310 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19311 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19312 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19313 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19314 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19315 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19316 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19317 | /* Deprecated forms of the above. */ | |
19318 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19319 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19320 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19321 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19322 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19323 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19324 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19325 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19326 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19327 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19328 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19329 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19330 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19331 | |
316f5878 | 19332 | /* MIPS 64 */ |
ad3fea08 TS |
19333 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19334 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19335 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19336 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19337 | |
c7a23324 | 19338 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19339 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19340 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19341 | /* Broadcom SB-1A CPU core */ |
19342 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19343 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19344 | |
19345 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19346 | |
ed163775 MR |
19347 | /* MIPS 64 Release 2 */ |
19348 | ||
967344c6 AN |
19349 | /* Cavium Networks Octeon CPU core */ |
19350 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19351 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19352 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19353 | |
52b6b6b9 JM |
19354 | /* RMI Xlr */ |
19355 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19356 | ||
55a36193 MK |
19357 | /* Broadcom XLP. |
19358 | XLP is mostly like XLR, with the prominent exception that it is | |
19359 | MIPS64R2 rather than MIPS64. */ | |
19360 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19361 | ||
316f5878 RS |
19362 | /* End marker */ |
19363 | { NULL, 0, 0, 0 } | |
19364 | }; | |
e7af610e | 19365 | |
84ea6cf2 | 19366 | |
316f5878 RS |
19367 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19368 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19369 | |
316f5878 | 19370 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19371 | |
b34976b6 | 19372 | static bfd_boolean |
17a2f251 | 19373 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19374 | { |
19375 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19376 | given++, canonical++; | |
19377 | ||
19378 | return ((*given == 0 && *canonical == 0) | |
19379 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19380 | } | |
19381 | ||
19382 | ||
19383 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19384 | CPU name. We've traditionally allowed a lot of variation here. | |
19385 | ||
19386 | Note: this function is shared between GCC and GAS. */ | |
19387 | ||
b34976b6 | 19388 | static bfd_boolean |
17a2f251 | 19389 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19390 | { |
19391 | /* First see if the name matches exactly, or with a final "000" | |
19392 | turned into "k". */ | |
19393 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19394 | return TRUE; |
316f5878 RS |
19395 | |
19396 | /* If not, try comparing based on numerical designation alone. | |
19397 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19398 | if (TOLOWER (*given) == 'r') | |
19399 | given++; | |
19400 | if (!ISDIGIT (*given)) | |
b34976b6 | 19401 | return FALSE; |
316f5878 RS |
19402 | |
19403 | /* Skip over some well-known prefixes in the canonical name, | |
19404 | hoping to find a number there too. */ | |
19405 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19406 | canonical += 2; | |
19407 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19408 | canonical += 2; | |
19409 | else if (TOLOWER (canonical[0]) == 'r') | |
19410 | canonical += 1; | |
19411 | ||
19412 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19413 | } | |
19414 | ||
19415 | ||
19416 | /* Parse an option that takes the name of a processor as its argument. | |
19417 | OPTION is the name of the option and CPU_STRING is the argument. | |
19418 | Return the corresponding processor enumeration if the CPU_STRING is | |
19419 | recognized, otherwise report an error and return null. | |
19420 | ||
19421 | A similar function exists in GCC. */ | |
e7af610e NC |
19422 | |
19423 | static const struct mips_cpu_info * | |
17a2f251 | 19424 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19425 | { |
316f5878 | 19426 | const struct mips_cpu_info *p; |
e7af610e | 19427 | |
316f5878 RS |
19428 | /* 'from-abi' selects the most compatible architecture for the given |
19429 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19430 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19431 | version. Look first at the -mgp options, if given, otherwise base | |
19432 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19433 | |
316f5878 RS |
19434 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19435 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19436 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19437 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19438 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19439 | { | |
19440 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19441 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19442 | ||
19443 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19444 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19445 | ||
19446 | if (file_mips_gp32 >= 0) | |
19447 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19448 | ||
19449 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19450 | ? ISA_MIPS3 | |
19451 | : ISA_MIPS1); | |
19452 | } | |
19453 | ||
19454 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19455 | if (strcasecmp (cpu_string, "default") == 0) | |
19456 | return 0; | |
19457 | ||
19458 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19459 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19460 | return p; | |
19461 | ||
20203fb9 | 19462 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19463 | return 0; |
e7af610e NC |
19464 | } |
19465 | ||
316f5878 RS |
19466 | /* Return the canonical processor information for ISA (a member of the |
19467 | ISA_MIPS* enumeration). */ | |
19468 | ||
e7af610e | 19469 | static const struct mips_cpu_info * |
17a2f251 | 19470 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19471 | { |
19472 | int i; | |
19473 | ||
19474 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19475 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19476 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19477 | return (&mips_cpu_info_table[i]); |
19478 | ||
e972090a | 19479 | return NULL; |
e7af610e | 19480 | } |
fef14a42 TS |
19481 | |
19482 | static const struct mips_cpu_info * | |
17a2f251 | 19483 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19484 | { |
19485 | int i; | |
19486 | ||
19487 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19488 | if (arch == mips_cpu_info_table[i].cpu) | |
19489 | return (&mips_cpu_info_table[i]); | |
19490 | ||
19491 | return NULL; | |
19492 | } | |
316f5878 RS |
19493 | \f |
19494 | static void | |
17a2f251 | 19495 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19496 | { |
19497 | if (*first_p) | |
19498 | { | |
19499 | fprintf (stream, "%24s", ""); | |
19500 | *col_p = 24; | |
19501 | } | |
19502 | else | |
19503 | { | |
19504 | fprintf (stream, ", "); | |
19505 | *col_p += 2; | |
19506 | } | |
e7af610e | 19507 | |
316f5878 RS |
19508 | if (*col_p + strlen (string) > 72) |
19509 | { | |
19510 | fprintf (stream, "\n%24s", ""); | |
19511 | *col_p = 24; | |
19512 | } | |
19513 | ||
19514 | fprintf (stream, "%s", string); | |
19515 | *col_p += strlen (string); | |
19516 | ||
19517 | *first_p = 0; | |
19518 | } | |
19519 | ||
19520 | void | |
17a2f251 | 19521 | md_show_usage (FILE *stream) |
e7af610e | 19522 | { |
316f5878 RS |
19523 | int column, first; |
19524 | size_t i; | |
19525 | ||
19526 | fprintf (stream, _("\ | |
19527 | MIPS options:\n\ | |
316f5878 RS |
19528 | -EB generate big endian output\n\ |
19529 | -EL generate little endian output\n\ | |
19530 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19531 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19532 | implicitly with the gp register [default 8]\n")); | |
19533 | fprintf (stream, _("\ | |
19534 | -mips1 generate MIPS ISA I instructions\n\ | |
19535 | -mips2 generate MIPS ISA II instructions\n\ | |
19536 | -mips3 generate MIPS ISA III instructions\n\ | |
19537 | -mips4 generate MIPS ISA IV instructions\n\ | |
19538 | -mips5 generate MIPS ISA V instructions\n\ | |
19539 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19540 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19541 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19542 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19543 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19544 | ||
19545 | first = 1; | |
e7af610e NC |
19546 | |
19547 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19548 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19549 | show (stream, "from-abi", &column, &first); | |
19550 | fputc ('\n', stream); | |
e7af610e | 19551 | |
316f5878 RS |
19552 | fprintf (stream, _("\ |
19553 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19554 | -no-mCPU don't generate code specific to CPU.\n\ | |
19555 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19556 | ||
19557 | first = 1; | |
19558 | ||
19559 | show (stream, "3900", &column, &first); | |
19560 | show (stream, "4010", &column, &first); | |
19561 | show (stream, "4100", &column, &first); | |
19562 | show (stream, "4650", &column, &first); | |
19563 | fputc ('\n', stream); | |
19564 | ||
19565 | fprintf (stream, _("\ | |
19566 | -mips16 generate mips16 instructions\n\ | |
19567 | -no-mips16 do not generate mips16 instructions\n")); | |
19568 | fprintf (stream, _("\ | |
df58fc94 RS |
19569 | -mmicromips generate microMIPS instructions\n\ |
19570 | -mno-micromips do not generate microMIPS instructions\n")); | |
19571 | fprintf (stream, _("\ | |
e16bfa71 TS |
19572 | -msmartmips generate smartmips instructions\n\ |
19573 | -mno-smartmips do not generate smartmips instructions\n")); | |
19574 | fprintf (stream, _("\ | |
74cd071d CF |
19575 | -mdsp generate DSP instructions\n\ |
19576 | -mno-dsp do not generate DSP instructions\n")); | |
19577 | fprintf (stream, _("\ | |
8b082fb1 TS |
19578 | -mdspr2 generate DSP R2 instructions\n\ |
19579 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19580 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19581 | -mmt generate MT instructions\n\ |
19582 | -mno-mt do not generate MT instructions\n")); | |
19583 | fprintf (stream, _("\ | |
dec0624d MR |
19584 | -mmcu generate MCU instructions\n\ |
19585 | -mno-mcu do not generate MCU instructions\n")); | |
19586 | fprintf (stream, _("\ | |
c67a084a NC |
19587 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19588 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19589 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19590 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19591 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19592 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19593 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19594 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19595 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19596 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19597 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19598 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19599 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19600 | fprintf (stream, _("\ |
19601 | -mhard-float allow floating-point instructions\n\ | |
19602 | -msoft-float do not allow floating-point instructions\n\ | |
19603 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19604 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19605 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19606 | )); | |
316f5878 RS |
19607 | #ifdef OBJ_ELF |
19608 | fprintf (stream, _("\ | |
19609 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19610 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19611 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19612 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19613 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19614 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19615 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19616 | position dependent (non shared) code\n\ |
316f5878 RS |
19617 | -mabi=ABI create ABI conformant object file for:\n")); |
19618 | ||
19619 | first = 1; | |
19620 | ||
19621 | show (stream, "32", &column, &first); | |
19622 | show (stream, "o64", &column, &first); | |
19623 | show (stream, "n32", &column, &first); | |
19624 | show (stream, "64", &column, &first); | |
19625 | show (stream, "eabi", &column, &first); | |
19626 | ||
19627 | fputc ('\n', stream); | |
19628 | ||
19629 | fprintf (stream, _("\ | |
19630 | -32 create o32 ABI object file (default)\n\ | |
19631 | -n32 create n32 ABI object file\n\ | |
19632 | -64 create 64 ABI object file\n")); | |
19633 | #endif | |
e7af610e | 19634 | } |
14e777e0 | 19635 | |
1575952e | 19636 | #ifdef TE_IRIX |
14e777e0 | 19637 | enum dwarf2_format |
413a266c | 19638 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19639 | { |
369943fe | 19640 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19641 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19642 | else |
19643 | return dwarf2_format_32bit; | |
19644 | } | |
1575952e | 19645 | #endif |
73369e65 EC |
19646 | |
19647 | int | |
19648 | mips_dwarf2_addr_size (void) | |
19649 | { | |
6b6b3450 | 19650 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19651 | return 8; |
73369e65 EC |
19652 | else |
19653 | return 4; | |
19654 | } | |
5862107c EC |
19655 | |
19656 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19657 | void | |
19658 | mips_cfi_frame_initial_instructions (void) | |
19659 | { | |
19660 | cfi_add_CFA_def_cfa_register (SP); | |
19661 | } | |
19662 | ||
707bfff6 TS |
19663 | int |
19664 | tc_mips_regname_to_dw2regnum (char *regname) | |
19665 | { | |
19666 | unsigned int regnum = -1; | |
19667 | unsigned int reg; | |
19668 | ||
19669 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19670 | regnum = reg; | |
19671 | ||
19672 | return regnum; | |
19673 | } |