Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
1f25f5d3 CD |
211 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
212 | if they have not been initialized. Changed by `.set <asename>', by | |
213 | command line options, and based on the default architecture. */ | |
214 | int ase_mips3d; | |
deec1734 | 215 | int ase_mdmx; |
e16bfa71 | 216 | int ase_smartmips; |
74cd071d | 217 | int ase_dsp; |
8b082fb1 | 218 | int ase_dspr2; |
ef2e4d86 | 219 | int ase_mt; |
dec0624d | 220 | int ase_mcu; |
b015e599 | 221 | int ase_virt; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
b015e599 AP |
296 | /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1, |
297 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
298 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
299 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
300 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 301 | }; |
252b5132 RH |
302 | |
303 | /* These variables are filled in with the masks of registers used. | |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
309 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 310 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 311 | |
738f4d98 | 312 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
313 | static int file_ase_mips16; |
314 | ||
3994f87e TS |
315 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
316 | || mips_opts.isa == ISA_MIPS32R2 \ | |
317 | || mips_opts.isa == ISA_MIPS64 \ | |
318 | || mips_opts.isa == ISA_MIPS64R2) | |
319 | ||
df58fc94 RS |
320 | /* True if any microMIPS code was produced. */ |
321 | static int file_ase_micromips; | |
322 | ||
b12dd2e4 CF |
323 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
324 | #ifdef TE_IRIX | |
1180b5a4 | 325 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 326 | #else |
1180b5a4 RS |
327 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
328 | because there's no place for any addend, the only acceptable | |
329 | expression is a bare symbol. */ | |
330 | #define MIPS_JALR_HINT_P(EXPR) \ | |
331 | (!HAVE_IN_PLACE_ADDENDS \ | |
332 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
333 | #endif |
334 | ||
1f25f5d3 CD |
335 | /* True if -mips3d was passed or implied by arguments passed on the |
336 | command line (e.g., by -march). */ | |
337 | static int file_ase_mips3d; | |
338 | ||
deec1734 CD |
339 | /* True if -mdmx was passed or implied by arguments passed on the |
340 | command line (e.g., by -march). */ | |
341 | static int file_ase_mdmx; | |
342 | ||
e16bfa71 TS |
343 | /* True if -msmartmips was passed or implied by arguments passed on the |
344 | command line (e.g., by -march). */ | |
345 | static int file_ase_smartmips; | |
346 | ||
ad3fea08 TS |
347 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
348 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 349 | |
74cd071d CF |
350 | /* True if -mdsp was passed or implied by arguments passed on the |
351 | command line (e.g., by -march). */ | |
352 | static int file_ase_dsp; | |
353 | ||
ad3fea08 | 354 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
355 | || mips_opts.isa == ISA_MIPS64R2 \ |
356 | || mips_opts.micromips) | |
ad3fea08 | 357 | |
65263ce3 TS |
358 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
359 | ||
8b082fb1 TS |
360 | /* True if -mdspr2 was passed or implied by arguments passed on the |
361 | command line (e.g., by -march). */ | |
362 | static int file_ase_dspr2; | |
363 | ||
364 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
365 | || mips_opts.isa == ISA_MIPS64R2 \ |
366 | || mips_opts.micromips) | |
8b082fb1 | 367 | |
ef2e4d86 CF |
368 | /* True if -mmt was passed or implied by arguments passed on the |
369 | command line (e.g., by -march). */ | |
370 | static int file_ase_mt; | |
371 | ||
ad3fea08 TS |
372 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
373 | || mips_opts.isa == ISA_MIPS64R2) | |
374 | ||
dec0624d | 375 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
376 | || mips_opts.isa == ISA_MIPS64R2 \ |
377 | || mips_opts.micromips) | |
dec0624d | 378 | |
b015e599 AP |
379 | /* True if -mvirt was passed or implied by arguments passed on the |
380 | command line (e.g., by -march). */ | |
381 | static int file_ase_virt; | |
382 | ||
383 | #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
384 | || mips_opts.isa == ISA_MIPS64R2) | |
385 | ||
386 | #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2) | |
387 | ||
ec68c924 | 388 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 389 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 390 | static const char *mips_arch_string; |
ec68c924 EC |
391 | |
392 | /* The argument of the -mtune= flag. The architecture for which we | |
393 | are optimizing. */ | |
394 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 395 | static const char *mips_tune_string; |
ec68c924 | 396 | |
316f5878 | 397 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
398 | static int mips_32bitmode = 0; |
399 | ||
316f5878 RS |
400 | /* True if the given ABI requires 32-bit registers. */ |
401 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
402 | ||
403 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
404 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
405 | ((ABI) == N32_ABI \ | |
406 | || (ABI) == N64_ABI \ | |
316f5878 RS |
407 | || (ABI) == O64_ABI) |
408 | ||
ad3fea08 | 409 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
410 | #define ISA_HAS_64BIT_REGS(ISA) \ |
411 | ((ISA) == ISA_MIPS3 \ | |
412 | || (ISA) == ISA_MIPS4 \ | |
413 | || (ISA) == ISA_MIPS5 \ | |
414 | || (ISA) == ISA_MIPS64 \ | |
415 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 416 | |
ad3fea08 TS |
417 | /* Return true if ISA supports 64 bit wide float registers. */ |
418 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
419 | ((ISA) == ISA_MIPS3 \ | |
420 | || (ISA) == ISA_MIPS4 \ | |
421 | || (ISA) == ISA_MIPS5 \ | |
422 | || (ISA) == ISA_MIPS32R2 \ | |
423 | || (ISA) == ISA_MIPS64 \ | |
424 | || (ISA) == ISA_MIPS64R2) | |
425 | ||
af7ee8bf CD |
426 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
427 | instructions. */ | |
707bfff6 | 428 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
429 | ((ISA) == ISA_MIPS64R2 \ |
430 | || (mips_opts.micromips \ | |
431 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
432 | ) | |
af7ee8bf CD |
433 | |
434 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
435 | instructions. */ | |
707bfff6 TS |
436 | #define ISA_HAS_ROR(ISA) \ |
437 | ((ISA) == ISA_MIPS32R2 \ | |
438 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
439 | || mips_opts.ase_smartmips \ |
440 | || mips_opts.micromips \ | |
441 | ) | |
707bfff6 | 442 | |
7455baf8 TS |
443 | /* Return true if ISA supports single-precision floats in odd registers. */ |
444 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
445 | ((ISA) == ISA_MIPS32 \ | |
446 | || (ISA) == ISA_MIPS32R2 \ | |
447 | || (ISA) == ISA_MIPS64 \ | |
448 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 449 | |
ad3fea08 TS |
450 | /* Return true if ISA supports move to/from high part of a 64-bit |
451 | floating-point register. */ | |
452 | #define ISA_HAS_MXHC1(ISA) \ | |
453 | ((ISA) == ISA_MIPS32R2 \ | |
454 | || (ISA) == ISA_MIPS64R2) | |
455 | ||
e013f690 | 456 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 457 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 458 | |
e013f690 | 459 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 460 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 461 | |
ad3fea08 TS |
462 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
463 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
474 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
432233b3 | 513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 514 | |
dd3cbb7e | 515 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 516 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 517 | |
0aa27725 RS |
518 | /* True, if CPU has support for ldc1 and sdc1. */ |
519 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
520 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
521 | ||
c8978940 CD |
522 | /* True if mflo and mfhi can be immediately followed by instructions |
523 | which write to the HI and LO registers. | |
524 | ||
525 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
526 | (at least) two instructions between the reads of HI/LO and | |
527 | instructions which write them, and later ISAs do not. Contradicting | |
528 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
529 | the UM for the NEC Vr5000) document needing the instructions between | |
530 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
531 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
532 | earlier-ISA CPUs for which CPU documentation declares that the | |
533 | instructions are really interlocked. */ | |
534 | #define hilo_interlocks \ | |
535 | (mips_opts.isa == ISA_MIPS32 \ | |
536 | || mips_opts.isa == ISA_MIPS32R2 \ | |
537 | || mips_opts.isa == ISA_MIPS64 \ | |
538 | || mips_opts.isa == ISA_MIPS64R2 \ | |
539 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 540 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
541 | || mips_opts.arch == CPU_R10000 \ |
542 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
543 | || mips_opts.arch == CPU_R14000 \ |
544 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 545 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 546 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 547 | || mips_opts.micromips \ |
c8978940 | 548 | ) |
252b5132 RH |
549 | |
550 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
551 | from the GPRs after they are loaded from memory, and thus does not |
552 | require nops to be inserted. This applies to instructions marked | |
553 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
554 | level I and microMIPS mode instructions are always interlocked. */ |
555 | #define gpr_interlocks \ | |
556 | (mips_opts.isa != ISA_MIPS1 \ | |
557 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 558 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
559 | || mips_opts.micromips \ |
560 | ) | |
252b5132 | 561 | |
81912461 ILT |
562 | /* Whether the processor uses hardware interlocks to avoid delays |
563 | required by coprocessor instructions, and thus does not require | |
564 | nops to be inserted. This applies to instructions marked | |
565 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
566 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
567 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
568 | levels I, II, and III and microMIPS mode instructions are always |
569 | interlocked. */ | |
bdaaa2e1 | 570 | /* Itbl support may require additional care here. */ |
81912461 ILT |
571 | #define cop_interlocks \ |
572 | ((mips_opts.isa != ISA_MIPS1 \ | |
573 | && mips_opts.isa != ISA_MIPS2 \ | |
574 | && mips_opts.isa != ISA_MIPS3) \ | |
575 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 576 | || mips_opts.micromips \ |
81912461 ILT |
577 | ) |
578 | ||
579 | /* Whether the processor uses hardware interlocks to protect reads | |
580 | from coprocessor registers after they are loaded from memory, and | |
581 | thus does not require nops to be inserted. This applies to | |
582 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
583 | requires at MIPS ISA level I and microMIPS mode instructions are |
584 | always interlocked. */ | |
585 | #define cop_mem_interlocks \ | |
586 | (mips_opts.isa != ISA_MIPS1 \ | |
587 | || mips_opts.micromips \ | |
588 | ) | |
252b5132 | 589 | |
6b76fefe CM |
590 | /* Is this a mfhi or mflo instruction? */ |
591 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
592 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
593 | ||
df58fc94 RS |
594 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
595 | has been selected. This implies, in particular, that addresses of text | |
596 | labels have their LSB set. */ | |
597 | #define HAVE_CODE_COMPRESSION \ | |
598 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
599 | ||
252b5132 RH |
600 | /* MIPS PIC level. */ |
601 | ||
a161fe53 | 602 | enum mips_pic_level mips_pic; |
252b5132 | 603 | |
c9914766 | 604 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 605 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 606 | static int mips_big_got = 0; |
252b5132 RH |
607 | |
608 | /* 1 if trap instructions should used for overflow rather than break | |
609 | instructions. */ | |
c9914766 | 610 | static int mips_trap = 0; |
252b5132 | 611 | |
119d663a | 612 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 613 | by assembling two single width halves into two single width floating |
119d663a NC |
614 | point registers which just happen to alias the double width destination |
615 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 616 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
617 | automatically at assemble time. */ |
618 | static int mips_disable_float_construction; | |
619 | ||
252b5132 RH |
620 | /* Non-zero if any .set noreorder directives were used. */ |
621 | ||
622 | static int mips_any_noreorder; | |
623 | ||
6b76fefe CM |
624 | /* Non-zero if nops should be inserted when the register referenced in |
625 | an mfhi/mflo instruction is read in the next two instructions. */ | |
626 | static int mips_7000_hilo_fix; | |
627 | ||
02ffd3e4 | 628 | /* The size of objects in the small data section. */ |
156c2f8b | 629 | static unsigned int g_switch_value = 8; |
252b5132 RH |
630 | /* Whether the -G option was used. */ |
631 | static int g_switch_seen = 0; | |
632 | ||
633 | #define N_RMASK 0xc4 | |
634 | #define N_VFP 0xd4 | |
635 | ||
636 | /* If we can determine in advance that GP optimization won't be | |
637 | possible, we can skip the relaxation stuff that tries to produce | |
638 | GP-relative references. This makes delay slot optimization work | |
639 | better. | |
640 | ||
641 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
642 | gcc output. It needs to guess right for gcc, otherwise gcc |
643 | will put what it thinks is a GP-relative instruction in a branch | |
644 | delay slot. | |
252b5132 RH |
645 | |
646 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
647 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 648 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
649 | |
650 | /* handle of the OPCODE hash table */ | |
651 | static struct hash_control *op_hash = NULL; | |
652 | ||
653 | /* The opcode hash table we use for the mips16. */ | |
654 | static struct hash_control *mips16_op_hash = NULL; | |
655 | ||
df58fc94 RS |
656 | /* The opcode hash table we use for the microMIPS ASE. */ |
657 | static struct hash_control *micromips_op_hash = NULL; | |
658 | ||
252b5132 RH |
659 | /* This array holds the chars that always start a comment. If the |
660 | pre-processor is disabled, these aren't very useful */ | |
661 | const char comment_chars[] = "#"; | |
662 | ||
663 | /* This array holds the chars that only start a comment at the beginning of | |
664 | a line. If the line seems to have the form '# 123 filename' | |
665 | .line and .file directives will appear in the pre-processed output */ | |
666 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
667 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 668 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
669 | /* Also note that C style comments are always supported. */ |
670 | const char line_comment_chars[] = "#"; | |
671 | ||
bdaaa2e1 | 672 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 673 | const char line_separator_chars[] = ";"; |
252b5132 RH |
674 | |
675 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
676 | const char EXP_CHARS[] = "eE"; | |
677 | ||
678 | /* Chars that mean this number is a floating point constant */ | |
679 | /* As in 0f12.456 */ | |
680 | /* or 0d1.2345e12 */ | |
681 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
682 | ||
683 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
684 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
685 | but nothing is ideal around here. | |
686 | */ | |
687 | ||
688 | static char *insn_error; | |
689 | ||
690 | static int auto_align = 1; | |
691 | ||
692 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
693 | offset in the stack frame from which to restore the $gp register. | |
694 | This is set by the .cprestore pseudo-op, and saved in this | |
695 | variable. */ | |
696 | static offsetT mips_cprestore_offset = -1; | |
697 | ||
67c1ffbe | 698 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 699 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 700 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
701 | static offsetT mips_cpreturn_offset = -1; |
702 | static int mips_cpreturn_register = -1; | |
703 | static int mips_gp_register = GP; | |
def2e0dd | 704 | static int mips_gprel_offset = 0; |
6478892d | 705 | |
7a621144 DJ |
706 | /* Whether mips_cprestore_offset has been set in the current function |
707 | (or whether it has already been warned about, if not). */ | |
708 | static int mips_cprestore_valid = 0; | |
709 | ||
252b5132 RH |
710 | /* This is the register which holds the stack frame, as set by the |
711 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
712 | static int mips_frame_reg = SP; | |
713 | ||
7a621144 DJ |
714 | /* Whether mips_frame_reg has been set in the current function |
715 | (or whether it has already been warned about, if not). */ | |
716 | static int mips_frame_reg_valid = 0; | |
717 | ||
252b5132 RH |
718 | /* To output NOP instructions correctly, we need to keep information |
719 | about the previous two instructions. */ | |
720 | ||
721 | /* Whether we are optimizing. The default value of 2 means to remove | |
722 | unneeded NOPs and swap branch instructions when possible. A value | |
723 | of 1 means to not swap branches. A value of 0 means to always | |
724 | insert NOPs. */ | |
725 | static int mips_optimize = 2; | |
726 | ||
727 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
728 | equivalent to seeing no -g option at all. */ | |
729 | static int mips_debug = 0; | |
730 | ||
7d8e00cf RS |
731 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
732 | #define MAX_VR4130_NOPS 4 | |
733 | ||
734 | /* The maximum number of NOPs needed to fill delay slots. */ | |
735 | #define MAX_DELAY_NOPS 2 | |
736 | ||
737 | /* The maximum number of NOPs needed for any purpose. */ | |
738 | #define MAX_NOPS 4 | |
71400594 RS |
739 | |
740 | /* A list of previous instructions, with index 0 being the most recent. | |
741 | We need to look back MAX_NOPS instructions when filling delay slots | |
742 | or working around processor errata. We need to look back one | |
743 | instruction further if we're thinking about using history[0] to | |
744 | fill a branch delay slot. */ | |
745 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 746 | |
1e915849 | 747 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
748 | static struct mips_cl_insn nop_insn; |
749 | static struct mips_cl_insn mips16_nop_insn; | |
750 | static struct mips_cl_insn micromips_nop16_insn; | |
751 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
752 | |
753 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
754 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
755 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
756 | ||
757 | /* The size of NOP_INSN in bytes. */ | |
758 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 759 | |
252b5132 RH |
760 | /* If this is set, it points to a frag holding nop instructions which |
761 | were inserted before the start of a noreorder section. If those | |
762 | nops turn out to be unnecessary, the size of the frag can be | |
763 | decreased. */ | |
764 | static fragS *prev_nop_frag; | |
765 | ||
766 | /* The number of nop instructions we created in prev_nop_frag. */ | |
767 | static int prev_nop_frag_holds; | |
768 | ||
769 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 770 | prev_nop_frag. */ |
252b5132 RH |
771 | static int prev_nop_frag_required; |
772 | ||
773 | /* The number of instructions we've seen since prev_nop_frag. */ | |
774 | static int prev_nop_frag_since; | |
775 | ||
776 | /* For ECOFF and ELF, relocations against symbols are done in two | |
777 | parts, with a HI relocation and a LO relocation. Each relocation | |
778 | has only 16 bits of space to store an addend. This means that in | |
779 | order for the linker to handle carries correctly, it must be able | |
780 | to locate both the HI and the LO relocation. This means that the | |
781 | relocations must appear in order in the relocation table. | |
782 | ||
783 | In order to implement this, we keep track of each unmatched HI | |
784 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 785 | corresponding LO relocation. */ |
252b5132 | 786 | |
e972090a NC |
787 | struct mips_hi_fixup |
788 | { | |
252b5132 RH |
789 | /* Next HI fixup. */ |
790 | struct mips_hi_fixup *next; | |
791 | /* This fixup. */ | |
792 | fixS *fixp; | |
793 | /* The section this fixup is in. */ | |
794 | segT seg; | |
795 | }; | |
796 | ||
797 | /* The list of unmatched HI relocs. */ | |
798 | ||
799 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
800 | ||
64bdfcaf RS |
801 | /* The frag containing the last explicit relocation operator. |
802 | Null if explicit relocations have not been used. */ | |
803 | ||
804 | static fragS *prev_reloc_op_frag; | |
805 | ||
252b5132 RH |
806 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
807 | ||
808 | #define X ILLEGAL_REG | |
e972090a NC |
809 | static const int mips32_to_16_reg_map[] = |
810 | { | |
252b5132 RH |
811 | X, X, 2, 3, 4, 5, 6, 7, |
812 | X, X, X, X, X, X, X, X, | |
813 | 0, 1, X, X, X, X, X, X, | |
814 | X, X, X, X, X, X, X, X | |
815 | }; | |
816 | #undef X | |
817 | ||
818 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
819 | ||
e972090a NC |
820 | static const unsigned int mips16_to_32_reg_map[] = |
821 | { | |
252b5132 RH |
822 | 16, 17, 2, 3, 4, 5, 6, 7 |
823 | }; | |
60b63b72 | 824 | |
df58fc94 RS |
825 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
826 | ||
827 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
828 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
829 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
830 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
831 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
832 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
833 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
834 | ||
835 | #define X ILLEGAL_REG | |
836 | /* reg type h: 4, 5, 6. */ | |
837 | static const int mips32_to_micromips_reg_h_map[] = | |
838 | { | |
839 | X, X, X, X, 4, 5, 6, X, | |
840 | X, X, X, X, X, X, X, X, | |
841 | X, X, X, X, X, X, X, X, | |
842 | X, X, X, X, X, X, X, X | |
843 | }; | |
844 | ||
845 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
846 | static const int mips32_to_micromips_reg_m_map[] = | |
847 | { | |
848 | 0, X, 2, 3, X, X, X, X, | |
849 | X, X, X, X, X, X, X, X, | |
850 | 4, 1, 5, 6, 7, X, X, X, | |
851 | X, X, X, X, X, X, X, X | |
852 | }; | |
853 | ||
854 | /* reg type q: 0, 2-7. 17. */ | |
855 | static const int mips32_to_micromips_reg_q_map[] = | |
856 | { | |
857 | 0, X, 2, 3, 4, 5, 6, 7, | |
858 | X, X, X, X, X, X, X, X, | |
859 | X, 1, X, X, X, X, X, X, | |
860 | X, X, X, X, X, X, X, X | |
861 | }; | |
862 | ||
863 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
864 | #undef X | |
865 | ||
866 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
867 | ||
868 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
869 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
870 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
871 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
872 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
873 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
874 | ||
875 | /* The microMIPS registers with type h. */ | |
876 | static const unsigned int micromips_to_32_reg_h_map[] = | |
877 | { | |
878 | 5, 5, 6, 4, 4, 4, 4, 4 | |
879 | }; | |
880 | ||
881 | /* The microMIPS registers with type i. */ | |
882 | static const unsigned int micromips_to_32_reg_i_map[] = | |
883 | { | |
884 | 6, 7, 7, 21, 22, 5, 6, 7 | |
885 | }; | |
886 | ||
887 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
888 | ||
889 | /* The microMIPS registers with type m. */ | |
890 | static const unsigned int micromips_to_32_reg_m_map[] = | |
891 | { | |
892 | 0, 17, 2, 3, 16, 18, 19, 20 | |
893 | }; | |
894 | ||
895 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
896 | ||
897 | /* The microMIPS registers with type q. */ | |
898 | static const unsigned int micromips_to_32_reg_q_map[] = | |
899 | { | |
900 | 0, 17, 2, 3, 4, 5, 6, 7 | |
901 | }; | |
902 | ||
903 | /* microMIPS imm type B. */ | |
904 | static const int micromips_imm_b_map[] = | |
905 | { | |
906 | 1, 4, 8, 12, 16, 20, 24, -1 | |
907 | }; | |
908 | ||
909 | /* microMIPS imm type C. */ | |
910 | static const int micromips_imm_c_map[] = | |
911 | { | |
912 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
913 | }; | |
914 | ||
71400594 RS |
915 | /* Classifies the kind of instructions we're interested in when |
916 | implementing -mfix-vr4120. */ | |
c67a084a NC |
917 | enum fix_vr4120_class |
918 | { | |
71400594 RS |
919 | FIX_VR4120_MACC, |
920 | FIX_VR4120_DMACC, | |
921 | FIX_VR4120_MULT, | |
922 | FIX_VR4120_DMULT, | |
923 | FIX_VR4120_DIV, | |
924 | FIX_VR4120_MTHILO, | |
925 | NUM_FIX_VR4120_CLASSES | |
926 | }; | |
927 | ||
c67a084a NC |
928 | /* ...likewise -mfix-loongson2f-jump. */ |
929 | static bfd_boolean mips_fix_loongson2f_jump; | |
930 | ||
931 | /* ...likewise -mfix-loongson2f-nop. */ | |
932 | static bfd_boolean mips_fix_loongson2f_nop; | |
933 | ||
934 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
935 | static bfd_boolean mips_fix_loongson2f; | |
936 | ||
71400594 RS |
937 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
938 | there must be at least one other instruction between an instruction | |
939 | of type X and an instruction of type Y. */ | |
940 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
941 | ||
942 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 943 | static int mips_fix_vr4120; |
4a6a3df4 | 944 | |
7d8e00cf RS |
945 | /* ...likewise -mfix-vr4130. */ |
946 | static int mips_fix_vr4130; | |
947 | ||
6a32d874 CM |
948 | /* ...likewise -mfix-24k. */ |
949 | static int mips_fix_24k; | |
950 | ||
d954098f DD |
951 | /* ...likewise -mfix-cn63xxp1 */ |
952 | static bfd_boolean mips_fix_cn63xxp1; | |
953 | ||
4a6a3df4 AO |
954 | /* We don't relax branches by default, since this causes us to expand |
955 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
956 | fail to compute the offset before expanding the macro to the most | |
957 | efficient expansion. */ | |
958 | ||
959 | static int mips_relax_branch; | |
252b5132 | 960 | \f |
4d7206a2 RS |
961 | /* The expansion of many macros depends on the type of symbol that |
962 | they refer to. For example, when generating position-dependent code, | |
963 | a macro that refers to a symbol may have two different expansions, | |
964 | one which uses GP-relative addresses and one which uses absolute | |
965 | addresses. When generating SVR4-style PIC, a macro may have | |
966 | different expansions for local and global symbols. | |
967 | ||
968 | We handle these situations by generating both sequences and putting | |
969 | them in variant frags. In position-dependent code, the first sequence | |
970 | will be the GP-relative one and the second sequence will be the | |
971 | absolute one. In SVR4 PIC, the first sequence will be for global | |
972 | symbols and the second will be for local symbols. | |
973 | ||
584892a6 RS |
974 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
975 | SECOND are the lengths of the two sequences in bytes. These fields | |
976 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
977 | the subtype has the following flags: | |
4d7206a2 | 978 | |
584892a6 RS |
979 | RELAX_USE_SECOND |
980 | Set if it has been decided that we should use the second | |
981 | sequence instead of the first. | |
982 | ||
983 | RELAX_SECOND_LONGER | |
984 | Set in the first variant frag if the macro's second implementation | |
985 | is longer than its first. This refers to the macro as a whole, | |
986 | not an individual relaxation. | |
987 | ||
988 | RELAX_NOMACRO | |
989 | Set in the first variant frag if the macro appeared in a .set nomacro | |
990 | block and if one alternative requires a warning but the other does not. | |
991 | ||
992 | RELAX_DELAY_SLOT | |
993 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
994 | delay slot. | |
4d7206a2 | 995 | |
df58fc94 RS |
996 | RELAX_DELAY_SLOT_16BIT |
997 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
998 | 16-bit instruction. | |
999 | ||
1000 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1001 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1002 | the macro is of the wrong size for the branch delay slot. | |
1003 | ||
1004 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1005 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1006 | the macro is of the wrong size for the branch delay slot. | |
1007 | ||
4d7206a2 RS |
1008 | The frag's "opcode" points to the first fixup for relaxable code. |
1009 | ||
1010 | Relaxable macros are generated using a sequence such as: | |
1011 | ||
1012 | relax_start (SYMBOL); | |
1013 | ... generate first expansion ... | |
1014 | relax_switch (); | |
1015 | ... generate second expansion ... | |
1016 | relax_end (); | |
1017 | ||
1018 | The code and fixups for the unwanted alternative are discarded | |
1019 | by md_convert_frag. */ | |
584892a6 | 1020 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1021 | |
584892a6 RS |
1022 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1023 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1024 | #define RELAX_USE_SECOND 0x10000 | |
1025 | #define RELAX_SECOND_LONGER 0x20000 | |
1026 | #define RELAX_NOMACRO 0x40000 | |
1027 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1028 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1029 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1030 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1031 | |
4a6a3df4 AO |
1032 | /* Branch without likely bit. If label is out of range, we turn: |
1033 | ||
1034 | beq reg1, reg2, label | |
1035 | delay slot | |
1036 | ||
1037 | into | |
1038 | ||
1039 | bne reg1, reg2, 0f | |
1040 | nop | |
1041 | j label | |
1042 | 0: delay slot | |
1043 | ||
1044 | with the following opcode replacements: | |
1045 | ||
1046 | beq <-> bne | |
1047 | blez <-> bgtz | |
1048 | bltz <-> bgez | |
1049 | bc1f <-> bc1t | |
1050 | ||
1051 | bltzal <-> bgezal (with jal label instead of j label) | |
1052 | ||
1053 | Even though keeping the delay slot instruction in the delay slot of | |
1054 | the branch would be more efficient, it would be very tricky to do | |
1055 | correctly, because we'd have to introduce a variable frag *after* | |
1056 | the delay slot instruction, and expand that instead. Let's do it | |
1057 | the easy way for now, even if the branch-not-taken case now costs | |
1058 | one additional instruction. Out-of-range branches are not supposed | |
1059 | to be common, anyway. | |
1060 | ||
1061 | Branch likely. If label is out of range, we turn: | |
1062 | ||
1063 | beql reg1, reg2, label | |
1064 | delay slot (annulled if branch not taken) | |
1065 | ||
1066 | into | |
1067 | ||
1068 | beql reg1, reg2, 1f | |
1069 | nop | |
1070 | beql $0, $0, 2f | |
1071 | nop | |
1072 | 1: j[al] label | |
1073 | delay slot (executed only if branch taken) | |
1074 | 2: | |
1075 | ||
1076 | It would be possible to generate a shorter sequence by losing the | |
1077 | likely bit, generating something like: | |
b34976b6 | 1078 | |
4a6a3df4 AO |
1079 | bne reg1, reg2, 0f |
1080 | nop | |
1081 | j[al] label | |
1082 | delay slot (executed only if branch taken) | |
1083 | 0: | |
1084 | ||
1085 | beql -> bne | |
1086 | bnel -> beq | |
1087 | blezl -> bgtz | |
1088 | bgtzl -> blez | |
1089 | bltzl -> bgez | |
1090 | bgezl -> bltz | |
1091 | bc1fl -> bc1t | |
1092 | bc1tl -> bc1f | |
1093 | ||
1094 | bltzall -> bgezal (with jal label instead of j label) | |
1095 | bgezall -> bltzal (ditto) | |
1096 | ||
1097 | ||
1098 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1099 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1100 | ((relax_substateT) \ | |
1101 | (0xc0000000 \ | |
1102 | | ((at) & 0x1f) \ | |
1103 | | ((toofar) ? 0x20 : 0) \ | |
1104 | | ((link) ? 0x40 : 0) \ | |
1105 | | ((likely) ? 0x80 : 0) \ | |
1106 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1107 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1108 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1109 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1110 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1111 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1112 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1113 | |
252b5132 RH |
1114 | /* For mips16 code, we use an entirely different form of relaxation. |
1115 | mips16 supports two versions of most instructions which take | |
1116 | immediate values: a small one which takes some small value, and a | |
1117 | larger one which takes a 16 bit value. Since branches also follow | |
1118 | this pattern, relaxing these values is required. | |
1119 | ||
1120 | We can assemble both mips16 and normal MIPS code in a single | |
1121 | object. Therefore, we need to support this type of relaxation at | |
1122 | the same time that we support the relaxation described above. We | |
1123 | use the high bit of the subtype field to distinguish these cases. | |
1124 | ||
1125 | The information we store for this type of relaxation is the | |
1126 | argument code found in the opcode file for this relocation, whether | |
1127 | the user explicitly requested a small or extended form, and whether | |
1128 | the relocation is in a jump or jal delay slot. That tells us the | |
1129 | size of the value, and how it should be stored. We also store | |
1130 | whether the fragment is considered to be extended or not. We also | |
1131 | store whether this is known to be a branch to a different section, | |
1132 | whether we have tried to relax this frag yet, and whether we have | |
1133 | ever extended a PC relative fragment because of a shift count. */ | |
1134 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1135 | (0x80000000 \ | |
1136 | | ((type) & 0xff) \ | |
1137 | | ((small) ? 0x100 : 0) \ | |
1138 | | ((ext) ? 0x200 : 0) \ | |
1139 | | ((dslot) ? 0x400 : 0) \ | |
1140 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1141 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1142 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1143 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1144 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1145 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1146 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1147 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1148 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1149 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1150 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1151 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1152 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1153 | |
df58fc94 RS |
1154 | /* For microMIPS code, we use relaxation similar to one we use for |
1155 | MIPS16 code. Some instructions that take immediate values support | |
1156 | two encodings: a small one which takes some small value, and a | |
1157 | larger one which takes a 16 bit value. As some branches also follow | |
1158 | this pattern, relaxing these values is required. | |
1159 | ||
1160 | We can assemble both microMIPS and normal MIPS code in a single | |
1161 | object. Therefore, we need to support this type of relaxation at | |
1162 | the same time that we support the relaxation described above. We | |
1163 | use one of the high bits of the subtype field to distinguish these | |
1164 | cases. | |
1165 | ||
1166 | The information we store for this type of relaxation is the argument | |
1167 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1168 | selected as the assembler temporary, whether the branch is |
1169 | unconditional, whether it is compact, whether it stores the link | |
1170 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1171 | branches to a sequence of instructions is enabled, and whether the | |
1172 | displacement of a branch is too large to fit as an immediate argument | |
1173 | of a 16-bit and a 32-bit branch, respectively. */ | |
1174 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1175 | relax32, toofar16, toofar32) \ | |
1176 | (0x40000000 \ | |
1177 | | ((type) & 0xff) \ | |
1178 | | (((at) & 0x1f) << 8) \ | |
1179 | | ((uncond) ? 0x2000 : 0) \ | |
1180 | | ((compact) ? 0x4000 : 0) \ | |
1181 | | ((link) ? 0x8000 : 0) \ | |
1182 | | ((relax32) ? 0x10000 : 0) \ | |
1183 | | ((toofar16) ? 0x20000 : 0) \ | |
1184 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1185 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1186 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1187 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1188 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1189 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1190 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1191 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1192 | ||
1193 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1194 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1195 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1196 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1197 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1198 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1199 | |
43c0598f RS |
1200 | /* Sign-extend 16-bit value X. */ |
1201 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1202 | ||
885add95 CD |
1203 | /* Is the given value a sign-extended 32-bit value? */ |
1204 | #define IS_SEXT_32BIT_NUM(x) \ | |
1205 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1206 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1207 | ||
1208 | /* Is the given value a sign-extended 16-bit value? */ | |
1209 | #define IS_SEXT_16BIT_NUM(x) \ | |
1210 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1211 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1212 | ||
df58fc94 RS |
1213 | /* Is the given value a sign-extended 12-bit value? */ |
1214 | #define IS_SEXT_12BIT_NUM(x) \ | |
1215 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1216 | ||
2051e8c4 MR |
1217 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1218 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1219 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1220 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1221 | ||
bf12938e RS |
1222 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1223 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1224 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1225 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1226 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1227 | ||
1228 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1229 | SHIFT places. */ | |
1230 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1231 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1232 | ||
1233 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1234 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1235 | ||
1236 | include/opcode/mips.h specifies operand fields using the macros | |
1237 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1238 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1239 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1240 | do \ | |
1241 | if (!(MICROMIPS)) \ | |
1242 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1243 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1244 | else \ | |
1245 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1246 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1247 | while (0) | |
bf12938e RS |
1248 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1249 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1250 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1251 | ||
1252 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1253 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1254 | (!(MICROMIPS) \ | |
1255 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1256 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1257 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1258 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1259 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1260 | MIPS16OP_MASK_##FIELD, \ | |
1261 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1262 | |
1263 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1264 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1265 | \f |
df58fc94 RS |
1266 | /* Whether or not we are emitting a branch-likely macro. */ |
1267 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1268 | ||
4d7206a2 RS |
1269 | /* Global variables used when generating relaxable macros. See the |
1270 | comment above RELAX_ENCODE for more details about how relaxation | |
1271 | is used. */ | |
1272 | static struct { | |
1273 | /* 0 if we're not emitting a relaxable macro. | |
1274 | 1 if we're emitting the first of the two relaxation alternatives. | |
1275 | 2 if we're emitting the second alternative. */ | |
1276 | int sequence; | |
1277 | ||
1278 | /* The first relaxable fixup in the current frag. (In other words, | |
1279 | the first fixup that refers to relaxable code.) */ | |
1280 | fixS *first_fixup; | |
1281 | ||
1282 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1283 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1284 | unsigned int sizes[2]; | |
1285 | ||
1286 | /* The symbol on which the choice of sequence depends. */ | |
1287 | symbolS *symbol; | |
1288 | } mips_relax; | |
252b5132 | 1289 | \f |
584892a6 RS |
1290 | /* Global variables used to decide whether a macro needs a warning. */ |
1291 | static struct { | |
1292 | /* True if the macro is in a branch delay slot. */ | |
1293 | bfd_boolean delay_slot_p; | |
1294 | ||
df58fc94 RS |
1295 | /* Set to the length in bytes required if the macro is in a delay slot |
1296 | that requires a specific length of instruction, otherwise zero. */ | |
1297 | unsigned int delay_slot_length; | |
1298 | ||
584892a6 RS |
1299 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1300 | in bytes and sizes[1] is the length of the second alternative. | |
1301 | For non-relaxable macros, both elements give the length of the | |
1302 | macro in bytes. */ | |
1303 | unsigned int sizes[2]; | |
1304 | ||
df58fc94 RS |
1305 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1306 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1307 | is the length of the first instruction of the second alternative. | |
1308 | For non-relaxable macros, both elements give the length of the first | |
1309 | instruction in bytes. | |
1310 | ||
1311 | Set to zero if we haven't yet seen the first instruction. */ | |
1312 | unsigned int first_insn_sizes[2]; | |
1313 | ||
1314 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1315 | first alternative and insns[1] is the number of instructions for the | |
1316 | second alternative. | |
1317 | ||
1318 | For non-relaxable macros, both elements give the number of | |
1319 | instructions for the macro. */ | |
1320 | unsigned int insns[2]; | |
1321 | ||
584892a6 RS |
1322 | /* The first variant frag for this macro. */ |
1323 | fragS *first_frag; | |
1324 | } mips_macro_warning; | |
1325 | \f | |
252b5132 RH |
1326 | /* Prototypes for static functions. */ |
1327 | ||
252b5132 RH |
1328 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1329 | ||
b34976b6 | 1330 | static void append_insn |
df58fc94 RS |
1331 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1332 | bfd_boolean expansionp); | |
7d10b47d | 1333 | static void mips_no_prev_insn (void); |
c67a084a | 1334 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1335 | static void mips16_macro_build |
03ea81db | 1336 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1337 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1338 | static void macro_start (void); |
1339 | static void macro_end (void); | |
17a2f251 TS |
1340 | static void macro (struct mips_cl_insn * ip); |
1341 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1342 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1343 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1344 | static void mips16_immed |
43c0598f RS |
1345 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1346 | unsigned int, unsigned long *); | |
5e0116d5 | 1347 | static size_t my_getSmallExpression |
17a2f251 TS |
1348 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1349 | static void my_getExpression (expressionS *, char *); | |
1350 | static void s_align (int); | |
1351 | static void s_change_sec (int); | |
1352 | static void s_change_section (int); | |
1353 | static void s_cons (int); | |
1354 | static void s_float_cons (int); | |
1355 | static void s_mips_globl (int); | |
1356 | static void s_option (int); | |
1357 | static void s_mipsset (int); | |
1358 | static void s_abicalls (int); | |
1359 | static void s_cpload (int); | |
1360 | static void s_cpsetup (int); | |
1361 | static void s_cplocal (int); | |
1362 | static void s_cprestore (int); | |
1363 | static void s_cpreturn (int); | |
741d6ea8 JM |
1364 | static void s_dtprelword (int); |
1365 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1366 | static void s_tprelword (int); |
1367 | static void s_tpreldword (int); | |
17a2f251 TS |
1368 | static void s_gpvalue (int); |
1369 | static void s_gpword (int); | |
1370 | static void s_gpdword (int); | |
a3f278e2 | 1371 | static void s_ehword (int); |
17a2f251 TS |
1372 | static void s_cpadd (int); |
1373 | static void s_insn (int); | |
1374 | static void md_obj_begin (void); | |
1375 | static void md_obj_end (void); | |
1376 | static void s_mips_ent (int); | |
1377 | static void s_mips_end (int); | |
1378 | static void s_mips_frame (int); | |
1379 | static void s_mips_mask (int reg_type); | |
1380 | static void s_mips_stab (int); | |
1381 | static void s_mips_weakext (int); | |
1382 | static void s_mips_file (int); | |
1383 | static void s_mips_loc (int); | |
1384 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1385 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1386 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1387 | static int validate_micromips_insn (const struct mips_opcode *); |
1388 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1389 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1390 | |
1391 | /* Table and functions used to map between CPU/ISA names, and | |
1392 | ISA levels, and CPU numbers. */ | |
1393 | ||
e972090a NC |
1394 | struct mips_cpu_info |
1395 | { | |
e7af610e | 1396 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1397 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1398 | int isa; /* ISA level. */ |
1399 | int cpu; /* CPU number (default CPU if ISA). */ | |
1400 | }; | |
1401 | ||
ad3fea08 TS |
1402 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1403 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1404 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1405 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1406 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1407 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1408 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1409 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
b015e599 | 1410 | #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */ |
ad3fea08 | 1411 | |
17a2f251 TS |
1412 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1413 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1414 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1415 | \f |
1416 | /* Pseudo-op table. | |
1417 | ||
1418 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1419 | should be defined here, but are currently unsupported: .alias, | |
1420 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1421 | ||
1422 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1423 | specific to the type of debugging information being generated, and | |
1424 | should be defined by the object format: .aent, .begin, .bend, | |
1425 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1426 | .vreg. | |
1427 | ||
1428 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1429 | not MIPS CPU specific, but are also not specific to the object file | |
1430 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1431 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1432 | |
e972090a NC |
1433 | static const pseudo_typeS mips_pseudo_table[] = |
1434 | { | |
beae10d5 | 1435 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1436 | {"option", s_option, 0}, |
1437 | {"set", s_mipsset, 0}, | |
1438 | {"rdata", s_change_sec, 'r'}, | |
1439 | {"sdata", s_change_sec, 's'}, | |
1440 | {"livereg", s_ignore, 0}, | |
1441 | {"abicalls", s_abicalls, 0}, | |
1442 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1443 | {"cpsetup", s_cpsetup, 0}, |
1444 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1445 | {"cprestore", s_cprestore, 0}, |
6478892d | 1446 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1447 | {"dtprelword", s_dtprelword, 0}, |
1448 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1449 | {"tprelword", s_tprelword, 0}, |
1450 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1451 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1452 | {"gpword", s_gpword, 0}, |
10181a0d | 1453 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1454 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1455 | {"cpadd", s_cpadd, 0}, |
1456 | {"insn", s_insn, 0}, | |
1457 | ||
beae10d5 | 1458 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1459 | chips. */ |
38a57ae7 | 1460 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1461 | {"bss", s_change_sec, 'b'}, |
1462 | {"err", s_err, 0}, | |
1463 | {"half", s_cons, 1}, | |
1464 | {"dword", s_cons, 3}, | |
1465 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1466 | {"origin", s_org, 0}, |
1467 | {"repeat", s_rept, 0}, | |
252b5132 | 1468 | |
998b3c36 MR |
1469 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1470 | {"sbss", s_change_sec, 'B'}, | |
1471 | ||
beae10d5 | 1472 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1473 | here for one reason or another. */ |
1474 | {"align", s_align, 0}, | |
1475 | {"byte", s_cons, 0}, | |
1476 | {"data", s_change_sec, 'd'}, | |
1477 | {"double", s_float_cons, 'd'}, | |
1478 | {"float", s_float_cons, 'f'}, | |
1479 | {"globl", s_mips_globl, 0}, | |
1480 | {"global", s_mips_globl, 0}, | |
1481 | {"hword", s_cons, 1}, | |
1482 | {"int", s_cons, 2}, | |
1483 | {"long", s_cons, 2}, | |
1484 | {"octa", s_cons, 4}, | |
1485 | {"quad", s_cons, 3}, | |
cca86cc8 | 1486 | {"section", s_change_section, 0}, |
252b5132 RH |
1487 | {"short", s_cons, 1}, |
1488 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1489 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1490 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1491 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1492 | {"text", s_change_sec, 't'}, |
1493 | {"word", s_cons, 2}, | |
add56521 | 1494 | |
add56521 | 1495 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1496 | |
43841e91 | 1497 | { NULL, NULL, 0 }, |
252b5132 RH |
1498 | }; |
1499 | ||
e972090a NC |
1500 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1501 | { | |
beae10d5 KH |
1502 | /* These pseudo-ops should be defined by the object file format. |
1503 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1504 | {"aent", s_mips_ent, 1}, |
1505 | {"bgnb", s_ignore, 0}, | |
1506 | {"end", s_mips_end, 0}, | |
1507 | {"endb", s_ignore, 0}, | |
1508 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1509 | {"file", s_mips_file, 0}, |
252b5132 RH |
1510 | {"fmask", s_mips_mask, 'F'}, |
1511 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1512 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1513 | {"mask", s_mips_mask, 'R'}, |
1514 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1515 | { NULL, NULL, 0 }, |
252b5132 RH |
1516 | }; |
1517 | ||
3ae8dd8d MR |
1518 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1519 | purpose of the `.dc.a' internal pseudo-op. */ | |
1520 | ||
1521 | int | |
1522 | mips_address_bytes (void) | |
1523 | { | |
1524 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1525 | } | |
1526 | ||
17a2f251 | 1527 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1528 | |
1529 | void | |
17a2f251 | 1530 | mips_pop_insert (void) |
252b5132 RH |
1531 | { |
1532 | pop_insert (mips_pseudo_table); | |
1533 | if (! ECOFF_DEBUGGING) | |
1534 | pop_insert (mips_nonecoff_pseudo_table); | |
1535 | } | |
1536 | \f | |
1537 | /* Symbols labelling the current insn. */ | |
1538 | ||
e972090a NC |
1539 | struct insn_label_list |
1540 | { | |
252b5132 RH |
1541 | struct insn_label_list *next; |
1542 | symbolS *label; | |
1543 | }; | |
1544 | ||
252b5132 | 1545 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1546 | #define label_list tc_segment_info_data.labels |
252b5132 | 1547 | |
17a2f251 | 1548 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1549 | static void mips_mark_labels (void); |
1550 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1551 | |
1552 | static inline void | |
17a2f251 | 1553 | mips_clear_insn_labels (void) |
252b5132 RH |
1554 | { |
1555 | register struct insn_label_list **pl; | |
a8dbcb85 | 1556 | segment_info_type *si; |
252b5132 | 1557 | |
a8dbcb85 TS |
1558 | if (now_seg) |
1559 | { | |
1560 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1561 | ; | |
1562 | ||
1563 | si = seg_info (now_seg); | |
1564 | *pl = si->label_list; | |
1565 | si->label_list = NULL; | |
1566 | } | |
252b5132 | 1567 | } |
a8dbcb85 | 1568 | |
df58fc94 RS |
1569 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1570 | ||
1571 | static inline void | |
1572 | mips_mark_labels (void) | |
1573 | { | |
1574 | if (HAVE_CODE_COMPRESSION) | |
1575 | mips_compressed_mark_labels (); | |
1576 | } | |
252b5132 RH |
1577 | \f |
1578 | static char *expr_end; | |
1579 | ||
1580 | /* Expressions which appear in instructions. These are set by | |
1581 | mips_ip. */ | |
1582 | ||
1583 | static expressionS imm_expr; | |
5f74bc13 | 1584 | static expressionS imm2_expr; |
252b5132 RH |
1585 | static expressionS offset_expr; |
1586 | ||
1587 | /* Relocs associated with imm_expr and offset_expr. */ | |
1588 | ||
f6688943 TS |
1589 | static bfd_reloc_code_real_type imm_reloc[3] |
1590 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1591 | static bfd_reloc_code_real_type offset_reloc[3] | |
1592 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1593 | |
df58fc94 RS |
1594 | /* This is set to the resulting size of the instruction to be produced |
1595 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1596 | explicit size is supplied. */ | |
252b5132 | 1597 | |
df58fc94 | 1598 | static unsigned int forced_insn_length; |
252b5132 | 1599 | |
e1b47bd5 RS |
1600 | /* True if we are assembling an instruction. All dot symbols defined during |
1601 | this time should be treated as code labels. */ | |
1602 | ||
1603 | static bfd_boolean mips_assembling_insn; | |
1604 | ||
7ed4a06a | 1605 | #ifdef OBJ_ELF |
ecb4347a DJ |
1606 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1607 | ECOFF debugging. */ | |
252b5132 RH |
1608 | |
1609 | static segT pdr_seg; | |
7ed4a06a | 1610 | #endif |
252b5132 | 1611 | |
e013f690 TS |
1612 | /* The default target format to use. */ |
1613 | ||
aeffff67 RS |
1614 | #if defined (TE_FreeBSD) |
1615 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1616 | #elif defined (TE_TMIPS) | |
1617 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1618 | #else | |
1619 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1620 | #endif | |
1621 | ||
e013f690 | 1622 | const char * |
17a2f251 | 1623 | mips_target_format (void) |
e013f690 TS |
1624 | { |
1625 | switch (OUTPUT_FLAVOR) | |
1626 | { | |
e013f690 TS |
1627 | case bfd_target_ecoff_flavour: |
1628 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1629 | case bfd_target_coff_flavour: | |
1630 | return "pe-mips"; | |
1631 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1632 | #ifdef TE_VXWORKS |
1633 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1634 | return (target_big_endian | |
1635 | ? "elf32-bigmips-vxworks" | |
1636 | : "elf32-littlemips-vxworks"); | |
1637 | #endif | |
e013f690 | 1638 | return (target_big_endian |
cfe86eaa | 1639 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1640 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1641 | : (HAVE_NEWABI |
aeffff67 RS |
1642 | ? ELF_TARGET ("elf32-n", "big") |
1643 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1644 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1645 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1646 | : (HAVE_NEWABI |
aeffff67 RS |
1647 | ? ELF_TARGET ("elf32-n", "little") |
1648 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1649 | default: |
1650 | abort (); | |
1651 | return NULL; | |
1652 | } | |
1653 | } | |
1654 | ||
df58fc94 RS |
1655 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1656 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1657 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1658 | major opcode) will require further modifications to the opcode | |
1659 | table. */ | |
1660 | ||
1661 | static inline unsigned int | |
1662 | micromips_insn_length (const struct mips_opcode *mo) | |
1663 | { | |
1664 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1665 | } | |
1666 | ||
5c04167a RS |
1667 | /* Return the length of MIPS16 instruction OPCODE. */ |
1668 | ||
1669 | static inline unsigned int | |
1670 | mips16_opcode_length (unsigned long opcode) | |
1671 | { | |
1672 | return (opcode >> 16) == 0 ? 2 : 4; | |
1673 | } | |
1674 | ||
1e915849 RS |
1675 | /* Return the length of instruction INSN. */ |
1676 | ||
1677 | static inline unsigned int | |
1678 | insn_length (const struct mips_cl_insn *insn) | |
1679 | { | |
df58fc94 RS |
1680 | if (mips_opts.micromips) |
1681 | return micromips_insn_length (insn->insn_mo); | |
1682 | else if (mips_opts.mips16) | |
5c04167a | 1683 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1684 | else |
1e915849 | 1685 | return 4; |
1e915849 RS |
1686 | } |
1687 | ||
1688 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1689 | ||
1690 | static void | |
1691 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1692 | { | |
1693 | size_t i; | |
1694 | ||
1695 | insn->insn_mo = mo; | |
1e915849 RS |
1696 | insn->insn_opcode = mo->match; |
1697 | insn->frag = NULL; | |
1698 | insn->where = 0; | |
1699 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1700 | insn->fixp[i] = NULL; | |
1701 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1702 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1703 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1704 | insn->complete_p = 0; |
e407c74b | 1705 | insn->cleared_p = 0; |
1e915849 RS |
1706 | } |
1707 | ||
df58fc94 | 1708 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1709 | |
1710 | static void | |
df58fc94 | 1711 | mips_record_compressed_mode (void) |
742a56fe RS |
1712 | { |
1713 | segment_info_type *si; | |
1714 | ||
1715 | si = seg_info (now_seg); | |
1716 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1717 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1718 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1719 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1720 | } |
1721 | ||
4d68580a RS |
1722 | /* Read a standard MIPS instruction from BUF. */ |
1723 | ||
1724 | static unsigned long | |
1725 | read_insn (char *buf) | |
1726 | { | |
1727 | if (target_big_endian) | |
1728 | return bfd_getb32 ((bfd_byte *) buf); | |
1729 | else | |
1730 | return bfd_getl32 ((bfd_byte *) buf); | |
1731 | } | |
1732 | ||
1733 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1734 | the next byte. */ | |
1735 | ||
1736 | static char * | |
1737 | write_insn (char *buf, unsigned int insn) | |
1738 | { | |
1739 | md_number_to_chars (buf, insn, 4); | |
1740 | return buf + 4; | |
1741 | } | |
1742 | ||
1743 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1744 | has length LENGTH. */ | |
1745 | ||
1746 | static unsigned long | |
1747 | read_compressed_insn (char *buf, unsigned int length) | |
1748 | { | |
1749 | unsigned long insn; | |
1750 | unsigned int i; | |
1751 | ||
1752 | insn = 0; | |
1753 | for (i = 0; i < length; i += 2) | |
1754 | { | |
1755 | insn <<= 16; | |
1756 | if (target_big_endian) | |
1757 | insn |= bfd_getb16 ((char *) buf); | |
1758 | else | |
1759 | insn |= bfd_getl16 ((char *) buf); | |
1760 | buf += 2; | |
1761 | } | |
1762 | return insn; | |
1763 | } | |
1764 | ||
5c04167a RS |
1765 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1766 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1767 | ||
1768 | static char * | |
1769 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1770 | { | |
1771 | unsigned int i; | |
1772 | ||
1773 | for (i = 0; i < length; i += 2) | |
1774 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1775 | return buf + length; | |
1776 | } | |
1777 | ||
1e915849 RS |
1778 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1779 | ||
1780 | static void | |
1781 | install_insn (const struct mips_cl_insn *insn) | |
1782 | { | |
1783 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1784 | if (HAVE_CODE_COMPRESSION) |
1785 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1786 | else |
4d68580a | 1787 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1788 | mips_record_compressed_mode (); |
1e915849 RS |
1789 | } |
1790 | ||
1791 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1792 | and install the opcode in the new location. */ | |
1793 | ||
1794 | static void | |
1795 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1796 | { | |
1797 | size_t i; | |
1798 | ||
1799 | insn->frag = frag; | |
1800 | insn->where = where; | |
1801 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1802 | if (insn->fixp[i] != NULL) | |
1803 | { | |
1804 | insn->fixp[i]->fx_frag = frag; | |
1805 | insn->fixp[i]->fx_where = where; | |
1806 | } | |
1807 | install_insn (insn); | |
1808 | } | |
1809 | ||
1810 | /* Add INSN to the end of the output. */ | |
1811 | ||
1812 | static void | |
1813 | add_fixed_insn (struct mips_cl_insn *insn) | |
1814 | { | |
1815 | char *f = frag_more (insn_length (insn)); | |
1816 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1817 | } | |
1818 | ||
1819 | /* Start a variant frag and move INSN to the start of the variant part, | |
1820 | marking it as fixed. The other arguments are as for frag_var. */ | |
1821 | ||
1822 | static void | |
1823 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1824 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1825 | { | |
1826 | frag_grow (max_chars); | |
1827 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1828 | insn->fixed_p = 1; | |
1829 | frag_var (rs_machine_dependent, max_chars, var, | |
1830 | subtype, symbol, offset, NULL); | |
1831 | } | |
1832 | ||
1833 | /* Insert N copies of INSN into the history buffer, starting at | |
1834 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1835 | ||
1836 | static void | |
1837 | insert_into_history (unsigned int first, unsigned int n, | |
1838 | const struct mips_cl_insn *insn) | |
1839 | { | |
1840 | if (mips_relax.sequence != 2) | |
1841 | { | |
1842 | unsigned int i; | |
1843 | ||
1844 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1845 | if (i >= first + n) | |
1846 | history[i] = history[i - n]; | |
1847 | else | |
1848 | history[i] = *insn; | |
1849 | } | |
1850 | } | |
1851 | ||
71400594 RS |
1852 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1853 | the idea is to make it obvious at a glance that each errata is | |
1854 | included. */ | |
1855 | ||
1856 | static void | |
1857 | init_vr4120_conflicts (void) | |
1858 | { | |
1859 | #define CONFLICT(FIRST, SECOND) \ | |
1860 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1861 | ||
1862 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1863 | CONFLICT (MACC, DIV); | |
1864 | CONFLICT (DMACC, DIV); | |
1865 | ||
1866 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1867 | CONFLICT (DMULT, DMULT); | |
1868 | CONFLICT (DMULT, DMACC); | |
1869 | CONFLICT (DMACC, DMULT); | |
1870 | CONFLICT (DMACC, DMACC); | |
1871 | ||
1872 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1873 | CONFLICT (MACC, MTHILO); | |
1874 | CONFLICT (DMACC, MTHILO); | |
1875 | ||
1876 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1877 | instruction is executed immediately after a MACC or DMACC | |
1878 | instruction, the result of [either instruction] is incorrect." */ | |
1879 | CONFLICT (MACC, MULT); | |
1880 | CONFLICT (MACC, DMULT); | |
1881 | CONFLICT (DMACC, MULT); | |
1882 | CONFLICT (DMACC, DMULT); | |
1883 | ||
1884 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1885 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1886 | DDIV or DDIVU instruction, the result of the MACC or | |
1887 | DMACC instruction is incorrect.". */ | |
1888 | CONFLICT (DMULT, MACC); | |
1889 | CONFLICT (DMULT, DMACC); | |
1890 | CONFLICT (DIV, MACC); | |
1891 | CONFLICT (DIV, DMACC); | |
1892 | ||
1893 | #undef CONFLICT | |
1894 | } | |
1895 | ||
707bfff6 TS |
1896 | struct regname { |
1897 | const char *name; | |
1898 | unsigned int num; | |
1899 | }; | |
1900 | ||
1901 | #define RTYPE_MASK 0x1ff00 | |
1902 | #define RTYPE_NUM 0x00100 | |
1903 | #define RTYPE_FPU 0x00200 | |
1904 | #define RTYPE_FCC 0x00400 | |
1905 | #define RTYPE_VEC 0x00800 | |
1906 | #define RTYPE_GP 0x01000 | |
1907 | #define RTYPE_CP0 0x02000 | |
1908 | #define RTYPE_PC 0x04000 | |
1909 | #define RTYPE_ACC 0x08000 | |
1910 | #define RTYPE_CCC 0x10000 | |
1911 | #define RNUM_MASK 0x000ff | |
1912 | #define RWARN 0x80000 | |
1913 | ||
1914 | #define GENERIC_REGISTER_NUMBERS \ | |
1915 | {"$0", RTYPE_NUM | 0}, \ | |
1916 | {"$1", RTYPE_NUM | 1}, \ | |
1917 | {"$2", RTYPE_NUM | 2}, \ | |
1918 | {"$3", RTYPE_NUM | 3}, \ | |
1919 | {"$4", RTYPE_NUM | 4}, \ | |
1920 | {"$5", RTYPE_NUM | 5}, \ | |
1921 | {"$6", RTYPE_NUM | 6}, \ | |
1922 | {"$7", RTYPE_NUM | 7}, \ | |
1923 | {"$8", RTYPE_NUM | 8}, \ | |
1924 | {"$9", RTYPE_NUM | 9}, \ | |
1925 | {"$10", RTYPE_NUM | 10}, \ | |
1926 | {"$11", RTYPE_NUM | 11}, \ | |
1927 | {"$12", RTYPE_NUM | 12}, \ | |
1928 | {"$13", RTYPE_NUM | 13}, \ | |
1929 | {"$14", RTYPE_NUM | 14}, \ | |
1930 | {"$15", RTYPE_NUM | 15}, \ | |
1931 | {"$16", RTYPE_NUM | 16}, \ | |
1932 | {"$17", RTYPE_NUM | 17}, \ | |
1933 | {"$18", RTYPE_NUM | 18}, \ | |
1934 | {"$19", RTYPE_NUM | 19}, \ | |
1935 | {"$20", RTYPE_NUM | 20}, \ | |
1936 | {"$21", RTYPE_NUM | 21}, \ | |
1937 | {"$22", RTYPE_NUM | 22}, \ | |
1938 | {"$23", RTYPE_NUM | 23}, \ | |
1939 | {"$24", RTYPE_NUM | 24}, \ | |
1940 | {"$25", RTYPE_NUM | 25}, \ | |
1941 | {"$26", RTYPE_NUM | 26}, \ | |
1942 | {"$27", RTYPE_NUM | 27}, \ | |
1943 | {"$28", RTYPE_NUM | 28}, \ | |
1944 | {"$29", RTYPE_NUM | 29}, \ | |
1945 | {"$30", RTYPE_NUM | 30}, \ | |
1946 | {"$31", RTYPE_NUM | 31} | |
1947 | ||
1948 | #define FPU_REGISTER_NAMES \ | |
1949 | {"$f0", RTYPE_FPU | 0}, \ | |
1950 | {"$f1", RTYPE_FPU | 1}, \ | |
1951 | {"$f2", RTYPE_FPU | 2}, \ | |
1952 | {"$f3", RTYPE_FPU | 3}, \ | |
1953 | {"$f4", RTYPE_FPU | 4}, \ | |
1954 | {"$f5", RTYPE_FPU | 5}, \ | |
1955 | {"$f6", RTYPE_FPU | 6}, \ | |
1956 | {"$f7", RTYPE_FPU | 7}, \ | |
1957 | {"$f8", RTYPE_FPU | 8}, \ | |
1958 | {"$f9", RTYPE_FPU | 9}, \ | |
1959 | {"$f10", RTYPE_FPU | 10}, \ | |
1960 | {"$f11", RTYPE_FPU | 11}, \ | |
1961 | {"$f12", RTYPE_FPU | 12}, \ | |
1962 | {"$f13", RTYPE_FPU | 13}, \ | |
1963 | {"$f14", RTYPE_FPU | 14}, \ | |
1964 | {"$f15", RTYPE_FPU | 15}, \ | |
1965 | {"$f16", RTYPE_FPU | 16}, \ | |
1966 | {"$f17", RTYPE_FPU | 17}, \ | |
1967 | {"$f18", RTYPE_FPU | 18}, \ | |
1968 | {"$f19", RTYPE_FPU | 19}, \ | |
1969 | {"$f20", RTYPE_FPU | 20}, \ | |
1970 | {"$f21", RTYPE_FPU | 21}, \ | |
1971 | {"$f22", RTYPE_FPU | 22}, \ | |
1972 | {"$f23", RTYPE_FPU | 23}, \ | |
1973 | {"$f24", RTYPE_FPU | 24}, \ | |
1974 | {"$f25", RTYPE_FPU | 25}, \ | |
1975 | {"$f26", RTYPE_FPU | 26}, \ | |
1976 | {"$f27", RTYPE_FPU | 27}, \ | |
1977 | {"$f28", RTYPE_FPU | 28}, \ | |
1978 | {"$f29", RTYPE_FPU | 29}, \ | |
1979 | {"$f30", RTYPE_FPU | 30}, \ | |
1980 | {"$f31", RTYPE_FPU | 31} | |
1981 | ||
1982 | #define FPU_CONDITION_CODE_NAMES \ | |
1983 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1984 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1985 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1986 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1987 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1988 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1989 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1990 | {"$fcc7", RTYPE_FCC | 7} | |
1991 | ||
1992 | #define COPROC_CONDITION_CODE_NAMES \ | |
1993 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1994 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1995 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1996 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1997 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1998 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1999 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2000 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2001 | ||
2002 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2003 | {"$a4", RTYPE_GP | 8}, \ | |
2004 | {"$a5", RTYPE_GP | 9}, \ | |
2005 | {"$a6", RTYPE_GP | 10}, \ | |
2006 | {"$a7", RTYPE_GP | 11}, \ | |
2007 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2008 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2009 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2010 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2011 | {"$t0", RTYPE_GP | 12}, \ | |
2012 | {"$t1", RTYPE_GP | 13}, \ | |
2013 | {"$t2", RTYPE_GP | 14}, \ | |
2014 | {"$t3", RTYPE_GP | 15} | |
2015 | ||
2016 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2017 | {"$t0", RTYPE_GP | 8}, \ | |
2018 | {"$t1", RTYPE_GP | 9}, \ | |
2019 | {"$t2", RTYPE_GP | 10}, \ | |
2020 | {"$t3", RTYPE_GP | 11}, \ | |
2021 | {"$t4", RTYPE_GP | 12}, \ | |
2022 | {"$t5", RTYPE_GP | 13}, \ | |
2023 | {"$t6", RTYPE_GP | 14}, \ | |
2024 | {"$t7", RTYPE_GP | 15}, \ | |
2025 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2026 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2027 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2028 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2029 | ||
2030 | /* Remaining symbolic register names */ | |
2031 | #define SYMBOLIC_REGISTER_NAMES \ | |
2032 | {"$zero", RTYPE_GP | 0}, \ | |
2033 | {"$at", RTYPE_GP | 1}, \ | |
2034 | {"$AT", RTYPE_GP | 1}, \ | |
2035 | {"$v0", RTYPE_GP | 2}, \ | |
2036 | {"$v1", RTYPE_GP | 3}, \ | |
2037 | {"$a0", RTYPE_GP | 4}, \ | |
2038 | {"$a1", RTYPE_GP | 5}, \ | |
2039 | {"$a2", RTYPE_GP | 6}, \ | |
2040 | {"$a3", RTYPE_GP | 7}, \ | |
2041 | {"$s0", RTYPE_GP | 16}, \ | |
2042 | {"$s1", RTYPE_GP | 17}, \ | |
2043 | {"$s2", RTYPE_GP | 18}, \ | |
2044 | {"$s3", RTYPE_GP | 19}, \ | |
2045 | {"$s4", RTYPE_GP | 20}, \ | |
2046 | {"$s5", RTYPE_GP | 21}, \ | |
2047 | {"$s6", RTYPE_GP | 22}, \ | |
2048 | {"$s7", RTYPE_GP | 23}, \ | |
2049 | {"$t8", RTYPE_GP | 24}, \ | |
2050 | {"$t9", RTYPE_GP | 25}, \ | |
2051 | {"$k0", RTYPE_GP | 26}, \ | |
2052 | {"$kt0", RTYPE_GP | 26}, \ | |
2053 | {"$k1", RTYPE_GP | 27}, \ | |
2054 | {"$kt1", RTYPE_GP | 27}, \ | |
2055 | {"$gp", RTYPE_GP | 28}, \ | |
2056 | {"$sp", RTYPE_GP | 29}, \ | |
2057 | {"$s8", RTYPE_GP | 30}, \ | |
2058 | {"$fp", RTYPE_GP | 30}, \ | |
2059 | {"$ra", RTYPE_GP | 31} | |
2060 | ||
2061 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2062 | {"$pc", RTYPE_PC | 0} | |
2063 | ||
2064 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2065 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2066 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2067 | {"$v2", RTYPE_VEC | 2}, \ | |
2068 | {"$v3", RTYPE_VEC | 3}, \ | |
2069 | {"$v4", RTYPE_VEC | 4}, \ | |
2070 | {"$v5", RTYPE_VEC | 5}, \ | |
2071 | {"$v6", RTYPE_VEC | 6}, \ | |
2072 | {"$v7", RTYPE_VEC | 7}, \ | |
2073 | {"$v8", RTYPE_VEC | 8}, \ | |
2074 | {"$v9", RTYPE_VEC | 9}, \ | |
2075 | {"$v10", RTYPE_VEC | 10}, \ | |
2076 | {"$v11", RTYPE_VEC | 11}, \ | |
2077 | {"$v12", RTYPE_VEC | 12}, \ | |
2078 | {"$v13", RTYPE_VEC | 13}, \ | |
2079 | {"$v14", RTYPE_VEC | 14}, \ | |
2080 | {"$v15", RTYPE_VEC | 15}, \ | |
2081 | {"$v16", RTYPE_VEC | 16}, \ | |
2082 | {"$v17", RTYPE_VEC | 17}, \ | |
2083 | {"$v18", RTYPE_VEC | 18}, \ | |
2084 | {"$v19", RTYPE_VEC | 19}, \ | |
2085 | {"$v20", RTYPE_VEC | 20}, \ | |
2086 | {"$v21", RTYPE_VEC | 21}, \ | |
2087 | {"$v22", RTYPE_VEC | 22}, \ | |
2088 | {"$v23", RTYPE_VEC | 23}, \ | |
2089 | {"$v24", RTYPE_VEC | 24}, \ | |
2090 | {"$v25", RTYPE_VEC | 25}, \ | |
2091 | {"$v26", RTYPE_VEC | 26}, \ | |
2092 | {"$v27", RTYPE_VEC | 27}, \ | |
2093 | {"$v28", RTYPE_VEC | 28}, \ | |
2094 | {"$v29", RTYPE_VEC | 29}, \ | |
2095 | {"$v30", RTYPE_VEC | 30}, \ | |
2096 | {"$v31", RTYPE_VEC | 31} | |
2097 | ||
2098 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2099 | {"$ac0", RTYPE_ACC | 0}, \ | |
2100 | {"$ac1", RTYPE_ACC | 1}, \ | |
2101 | {"$ac2", RTYPE_ACC | 2}, \ | |
2102 | {"$ac3", RTYPE_ACC | 3} | |
2103 | ||
2104 | static const struct regname reg_names[] = { | |
2105 | GENERIC_REGISTER_NUMBERS, | |
2106 | FPU_REGISTER_NAMES, | |
2107 | FPU_CONDITION_CODE_NAMES, | |
2108 | COPROC_CONDITION_CODE_NAMES, | |
2109 | ||
2110 | /* The $txx registers depends on the abi, | |
2111 | these will be added later into the symbol table from | |
2112 | one of the tables below once mips_abi is set after | |
2113 | parsing of arguments from the command line. */ | |
2114 | SYMBOLIC_REGISTER_NAMES, | |
2115 | ||
2116 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2117 | MDMX_VECTOR_REGISTER_NAMES, | |
2118 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2119 | {0, 0} | |
2120 | }; | |
2121 | ||
2122 | static const struct regname reg_names_o32[] = { | |
2123 | O32_SYMBOLIC_REGISTER_NAMES, | |
2124 | {0, 0} | |
2125 | }; | |
2126 | ||
2127 | static const struct regname reg_names_n32n64[] = { | |
2128 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2129 | {0, 0} | |
2130 | }; | |
2131 | ||
df58fc94 RS |
2132 | /* Check if S points at a valid register specifier according to TYPES. |
2133 | If so, then return 1, advance S to consume the specifier and store | |
2134 | the register's number in REGNOP, otherwise return 0. */ | |
2135 | ||
707bfff6 TS |
2136 | static int |
2137 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2138 | { | |
2139 | symbolS *symbolP; | |
2140 | char *e; | |
2141 | char save_c; | |
2142 | int reg = -1; | |
2143 | ||
2144 | /* Find end of name. */ | |
2145 | e = *s; | |
2146 | if (is_name_beginner (*e)) | |
2147 | ++e; | |
2148 | while (is_part_of_name (*e)) | |
2149 | ++e; | |
2150 | ||
2151 | /* Terminate name. */ | |
2152 | save_c = *e; | |
2153 | *e = '\0'; | |
2154 | ||
2155 | /* Look for a register symbol. */ | |
2156 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2157 | { | |
2158 | int r = S_GET_VALUE (symbolP); | |
2159 | if (r & types) | |
2160 | reg = r & RNUM_MASK; | |
2161 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2162 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2163 | reg = (r & RNUM_MASK) - 2; | |
2164 | } | |
2165 | /* Else see if this is a register defined in an itbl entry. */ | |
2166 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2167 | { | |
2168 | char *n = *s; | |
2169 | unsigned long r; | |
2170 | ||
2171 | if (*n == '$') | |
2172 | ++n; | |
2173 | if (itbl_get_reg_val (n, &r)) | |
2174 | reg = r & RNUM_MASK; | |
2175 | } | |
2176 | ||
2177 | /* Advance to next token if a register was recognised. */ | |
2178 | if (reg >= 0) | |
2179 | *s = e; | |
2180 | else if (types & RWARN) | |
20203fb9 | 2181 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2182 | |
2183 | *e = save_c; | |
2184 | if (regnop) | |
2185 | *regnop = reg; | |
2186 | return reg >= 0; | |
2187 | } | |
2188 | ||
df58fc94 RS |
2189 | /* Check if S points at a valid register list according to TYPES. |
2190 | If so, then return 1, advance S to consume the list and store | |
2191 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2192 | otherwise return 0. A valid list comprises a comma-separated | |
2193 | enumeration of valid single registers and/or dash-separated | |
2194 | contiguous register ranges as determined by their numbers. | |
2195 | ||
2196 | As a special exception if one of s0-s7 registers is specified as | |
2197 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2198 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2199 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2200 | |
2201 | static int | |
2202 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2203 | { | |
2204 | unsigned int reglist = 0; | |
2205 | unsigned int lastregno; | |
2206 | bfd_boolean ok = TRUE; | |
2207 | unsigned int regmask; | |
2309ddf2 | 2208 | char *s_endlist = *s; |
df58fc94 | 2209 | char *s_reset = *s; |
2309ddf2 | 2210 | unsigned int regno; |
df58fc94 RS |
2211 | |
2212 | while (reg_lookup (s, types, ®no)) | |
2213 | { | |
2214 | lastregno = regno; | |
2215 | if (**s == '-') | |
2216 | { | |
2217 | (*s)++; | |
2218 | ok = reg_lookup (s, types, &lastregno); | |
2219 | if (ok && lastregno < regno) | |
2220 | ok = FALSE; | |
2221 | if (!ok) | |
2222 | break; | |
2223 | } | |
2224 | ||
2225 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2226 | { | |
2227 | lastregno = S7; | |
2228 | reglist |= 1 << FP; | |
2229 | } | |
2230 | regmask = 1 << lastregno; | |
2231 | regmask = (regmask << 1) - 1; | |
2232 | regmask ^= (1 << regno) - 1; | |
2233 | reglist |= regmask; | |
2234 | ||
2309ddf2 | 2235 | s_endlist = *s; |
df58fc94 RS |
2236 | if (**s != ',') |
2237 | break; | |
2238 | (*s)++; | |
2239 | } | |
2240 | ||
2241 | if (ok) | |
2309ddf2 | 2242 | *s = s_endlist; |
df58fc94 RS |
2243 | else |
2244 | *s = s_reset; | |
2245 | if (reglistp) | |
2246 | *reglistp = reglist; | |
2247 | return ok && reglist != 0; | |
2248 | } | |
2249 | ||
d301a56b RS |
2250 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2251 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2252 | |
2253 | static bfd_boolean | |
f79e2745 | 2254 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2255 | { |
2256 | int isa = mips_opts.isa; | |
d301a56b | 2257 | int ase = 0; |
037b32b9 AN |
2258 | int fp_s, fp_d; |
2259 | ||
2260 | if (mips_opts.ase_mdmx) | |
d301a56b | 2261 | ase |= ASE_MDMX; |
037b32b9 | 2262 | if (mips_opts.ase_dsp) |
d301a56b | 2263 | ase |= ASE_DSP; |
037b32b9 | 2264 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
d301a56b | 2265 | ase |= ASE_DSP64; |
037b32b9 | 2266 | if (mips_opts.ase_dspr2) |
d301a56b | 2267 | ase |= ASE_DSPR2; |
037b32b9 | 2268 | if (mips_opts.ase_mt) |
d301a56b | 2269 | ase |= ASE_MT; |
037b32b9 | 2270 | if (mips_opts.ase_mips3d) |
d301a56b | 2271 | ase |= ASE_MIPS3D; |
037b32b9 | 2272 | if (mips_opts.ase_smartmips) |
d301a56b | 2273 | ase |= ASE_SMARTMIPS; |
dec0624d | 2274 | if (mips_opts.ase_mcu) |
d301a56b | 2275 | ase |= ASE_MCU; |
b015e599 | 2276 | if (mips_opts.ase_virt) |
d301a56b | 2277 | ase |= ASE_VIRT; |
b015e599 | 2278 | if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE) |
d301a56b | 2279 | ase |= ASE_VIRT64; |
037b32b9 | 2280 | |
d301a56b | 2281 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2282 | return FALSE; |
2283 | ||
2284 | /* Check whether the instruction or macro requires single-precision or | |
2285 | double-precision floating-point support. Note that this information is | |
2286 | stored differently in the opcode table for insns and macros. */ | |
2287 | if (mo->pinfo == INSN_MACRO) | |
2288 | { | |
2289 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2290 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2291 | } | |
2292 | else | |
2293 | { | |
2294 | fp_s = mo->pinfo & FP_S; | |
2295 | fp_d = mo->pinfo & FP_D; | |
2296 | } | |
2297 | ||
2298 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2299 | return FALSE; | |
2300 | ||
2301 | if (fp_s && mips_opts.soft_float) | |
2302 | return FALSE; | |
2303 | ||
2304 | return TRUE; | |
2305 | } | |
2306 | ||
2307 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2308 | selected ISA and architecture. */ | |
2309 | ||
2310 | static bfd_boolean | |
2311 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2312 | { | |
d301a56b | 2313 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2314 | } |
2315 | ||
df58fc94 RS |
2316 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2317 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2318 | ||
2319 | static bfd_boolean | |
2320 | is_size_valid (const struct mips_opcode *mo) | |
2321 | { | |
2322 | if (!mips_opts.micromips) | |
2323 | return TRUE; | |
2324 | ||
2325 | if (!forced_insn_length) | |
2326 | return TRUE; | |
2327 | if (mo->pinfo == INSN_MACRO) | |
2328 | return FALSE; | |
2329 | return forced_insn_length == micromips_insn_length (mo); | |
2330 | } | |
2331 | ||
2332 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2333 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2334 | ||
2335 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2336 | a macro expansion fails because it relies on a preceding 32-bit real | |
2337 | instruction to have matched and does not handle the operands correctly. | |
2338 | The only macros that may expand to 16-bit instructions are JAL that | |
2339 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2340 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2341 | a NOP. In all these cases the macros precede any corresponding real | |
2342 | instruction definitions in the opcode table, so they will match in the | |
2343 | second pass where the size of the delay slot is ignored and therefore | |
2344 | produce correct code. */ | |
df58fc94 RS |
2345 | |
2346 | static bfd_boolean | |
2347 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2348 | { | |
2349 | if (!mips_opts.micromips) | |
2350 | return TRUE; | |
2351 | ||
2352 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2353 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2354 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2355 | && micromips_insn_length (mo) != 4) | |
2356 | return FALSE; | |
2357 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2358 | && micromips_insn_length (mo) != 2) | |
2359 | return FALSE; | |
2360 | ||
2361 | return TRUE; | |
2362 | } | |
2363 | ||
707bfff6 TS |
2364 | /* This function is called once, at assembler startup time. It should set up |
2365 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2366 | |
252b5132 | 2367 | void |
17a2f251 | 2368 | md_begin (void) |
252b5132 | 2369 | { |
3994f87e | 2370 | const char *retval = NULL; |
156c2f8b | 2371 | int i = 0; |
252b5132 | 2372 | int broken = 0; |
1f25f5d3 | 2373 | |
0a44bf69 RS |
2374 | if (mips_pic != NO_PIC) |
2375 | { | |
2376 | if (g_switch_seen && g_switch_value != 0) | |
2377 | as_bad (_("-G may not be used in position-independent code")); | |
2378 | g_switch_value = 0; | |
2379 | } | |
2380 | ||
fef14a42 | 2381 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2382 | as_warn (_("Could not set architecture and machine")); |
2383 | ||
252b5132 RH |
2384 | op_hash = hash_new (); |
2385 | ||
2386 | for (i = 0; i < NUMOPCODES;) | |
2387 | { | |
2388 | const char *name = mips_opcodes[i].name; | |
2389 | ||
17a2f251 | 2390 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2391 | if (retval != NULL) |
2392 | { | |
2393 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2394 | mips_opcodes[i].name, retval); | |
2395 | /* Probably a memory allocation problem? Give up now. */ | |
2396 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2397 | } | |
2398 | do | |
2399 | { | |
2400 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2401 | { | |
2402 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2403 | broken = 1; | |
1e915849 RS |
2404 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2405 | { | |
2406 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2407 | if (mips_fix_loongson2f_nop) |
2408 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2409 | nop_insn.fixed_p = 1; |
2410 | } | |
252b5132 RH |
2411 | } |
2412 | ++i; | |
2413 | } | |
2414 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2415 | } | |
2416 | ||
2417 | mips16_op_hash = hash_new (); | |
2418 | ||
2419 | i = 0; | |
2420 | while (i < bfd_mips16_num_opcodes) | |
2421 | { | |
2422 | const char *name = mips16_opcodes[i].name; | |
2423 | ||
17a2f251 | 2424 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2425 | if (retval != NULL) |
2426 | as_fatal (_("internal: can't hash `%s': %s"), | |
2427 | mips16_opcodes[i].name, retval); | |
2428 | do | |
2429 | { | |
2430 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2431 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2432 | != mips16_opcodes[i].match)) | |
2433 | { | |
2434 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2435 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2436 | broken = 1; | |
2437 | } | |
1e915849 RS |
2438 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2439 | { | |
2440 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2441 | mips16_nop_insn.fixed_p = 1; | |
2442 | } | |
252b5132 RH |
2443 | ++i; |
2444 | } | |
2445 | while (i < bfd_mips16_num_opcodes | |
2446 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2447 | } | |
2448 | ||
df58fc94 RS |
2449 | micromips_op_hash = hash_new (); |
2450 | ||
2451 | i = 0; | |
2452 | while (i < bfd_micromips_num_opcodes) | |
2453 | { | |
2454 | const char *name = micromips_opcodes[i].name; | |
2455 | ||
2456 | retval = hash_insert (micromips_op_hash, name, | |
2457 | (void *) µmips_opcodes[i]); | |
2458 | if (retval != NULL) | |
2459 | as_fatal (_("internal: can't hash `%s': %s"), | |
2460 | micromips_opcodes[i].name, retval); | |
2461 | do | |
2462 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2463 | { | |
2464 | struct mips_cl_insn *micromips_nop_insn; | |
2465 | ||
2466 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2467 | broken = 1; | |
2468 | ||
2469 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2470 | micromips_nop_insn = µmips_nop16_insn; | |
2471 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2472 | micromips_nop_insn = µmips_nop32_insn; | |
2473 | else | |
2474 | continue; | |
2475 | ||
2476 | if (micromips_nop_insn->insn_mo == NULL | |
2477 | && strcmp (name, "nop") == 0) | |
2478 | { | |
2479 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2480 | micromips_nop_insn->fixed_p = 1; | |
2481 | } | |
2482 | } | |
2483 | while (++i < bfd_micromips_num_opcodes | |
2484 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2485 | } | |
2486 | ||
252b5132 RH |
2487 | if (broken) |
2488 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2489 | ||
2490 | /* We add all the general register names to the symbol table. This | |
2491 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2492 | for (i = 0; reg_names[i].name; i++) |
2493 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2494 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2495 | &zero_address_frag)); |
2496 | if (HAVE_NEWABI) | |
2497 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2498 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2499 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2500 | &zero_address_frag)); |
707bfff6 TS |
2501 | else |
2502 | for (i = 0; reg_names_o32[i].name; i++) | |
2503 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2504 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2505 | &zero_address_frag)); |
6047c971 | 2506 | |
7d10b47d | 2507 | mips_no_prev_insn (); |
252b5132 RH |
2508 | |
2509 | mips_gprmask = 0; | |
2510 | mips_cprmask[0] = 0; | |
2511 | mips_cprmask[1] = 0; | |
2512 | mips_cprmask[2] = 0; | |
2513 | mips_cprmask[3] = 0; | |
2514 | ||
2515 | /* set the default alignment for the text section (2**2) */ | |
2516 | record_alignment (text_section, 2); | |
2517 | ||
4d0d148d | 2518 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2519 | |
707bfff6 | 2520 | #ifdef OBJ_ELF |
f43abd2b | 2521 | if (IS_ELF) |
252b5132 | 2522 | { |
0a44bf69 RS |
2523 | /* On a native system other than VxWorks, sections must be aligned |
2524 | to 16 byte boundaries. When configured for an embedded ELF | |
2525 | target, we don't bother. */ | |
c41e87e3 CF |
2526 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2527 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2528 | { |
2529 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2530 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2531 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2532 | } | |
2533 | ||
2534 | /* Create a .reginfo section for register masks and a .mdebug | |
2535 | section for debugging information. */ | |
2536 | { | |
2537 | segT seg; | |
2538 | subsegT subseg; | |
2539 | flagword flags; | |
2540 | segT sec; | |
2541 | ||
2542 | seg = now_seg; | |
2543 | subseg = now_subseg; | |
2544 | ||
2545 | /* The ABI says this section should be loaded so that the | |
2546 | running program can access it. However, we don't load it | |
2547 | if we are configured for an embedded target */ | |
2548 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2549 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2550 | flags |= SEC_ALLOC | SEC_LOAD; |
2551 | ||
316f5878 | 2552 | if (mips_abi != N64_ABI) |
252b5132 RH |
2553 | { |
2554 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2555 | ||
195325d2 TS |
2556 | bfd_set_section_flags (stdoutput, sec, flags); |
2557 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2558 | |
252b5132 | 2559 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2560 | } |
2561 | else | |
2562 | { | |
2563 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2564 | .reginfo section. */ | |
2565 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2566 | bfd_set_section_flags (stdoutput, sec, flags); |
2567 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2568 | |
252b5132 RH |
2569 | /* Set up the option header. */ |
2570 | { | |
2571 | Elf_Internal_Options opthdr; | |
2572 | char *f; | |
2573 | ||
2574 | opthdr.kind = ODK_REGINFO; | |
2575 | opthdr.size = (sizeof (Elf_External_Options) | |
2576 | + sizeof (Elf64_External_RegInfo)); | |
2577 | opthdr.section = 0; | |
2578 | opthdr.info = 0; | |
2579 | f = frag_more (sizeof (Elf_External_Options)); | |
2580 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2581 | (Elf_External_Options *) f); | |
2582 | ||
2583 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2584 | } | |
252b5132 RH |
2585 | } |
2586 | ||
2587 | if (ECOFF_DEBUGGING) | |
2588 | { | |
2589 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2590 | (void) bfd_set_section_flags (stdoutput, sec, | |
2591 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2592 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2593 | } | |
f43abd2b | 2594 | else if (mips_flag_pdr) |
ecb4347a DJ |
2595 | { |
2596 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2597 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2598 | SEC_READONLY | SEC_RELOC | |
2599 | | SEC_DEBUGGING); | |
2600 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2601 | } | |
252b5132 RH |
2602 | |
2603 | subseg_set (seg, subseg); | |
2604 | } | |
2605 | } | |
707bfff6 | 2606 | #endif /* OBJ_ELF */ |
252b5132 RH |
2607 | |
2608 | if (! ECOFF_DEBUGGING) | |
2609 | md_obj_begin (); | |
71400594 RS |
2610 | |
2611 | if (mips_fix_vr4120) | |
2612 | init_vr4120_conflicts (); | |
252b5132 RH |
2613 | } |
2614 | ||
2615 | void | |
17a2f251 | 2616 | md_mips_end (void) |
252b5132 | 2617 | { |
02b1ab82 | 2618 | mips_emit_delays (); |
252b5132 RH |
2619 | if (! ECOFF_DEBUGGING) |
2620 | md_obj_end (); | |
2621 | } | |
2622 | ||
2623 | void | |
17a2f251 | 2624 | md_assemble (char *str) |
252b5132 RH |
2625 | { |
2626 | struct mips_cl_insn insn; | |
f6688943 TS |
2627 | bfd_reloc_code_real_type unused_reloc[3] |
2628 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2629 | |
2630 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2631 | imm2_expr.X_op = O_absent; |
252b5132 | 2632 | offset_expr.X_op = O_absent; |
f6688943 TS |
2633 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2634 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2635 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2636 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2637 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2638 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2639 | |
e1b47bd5 RS |
2640 | mips_mark_labels (); |
2641 | mips_assembling_insn = TRUE; | |
2642 | ||
252b5132 RH |
2643 | if (mips_opts.mips16) |
2644 | mips16_ip (str, &insn); | |
2645 | else | |
2646 | { | |
2647 | mips_ip (str, &insn); | |
beae10d5 KH |
2648 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2649 | str, insn.insn_opcode)); | |
252b5132 RH |
2650 | } |
2651 | ||
2652 | if (insn_error) | |
e1b47bd5 RS |
2653 | as_bad ("%s `%s'", insn_error, str); |
2654 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2655 | { |
584892a6 | 2656 | macro_start (); |
252b5132 RH |
2657 | if (mips_opts.mips16) |
2658 | mips16_macro (&insn); | |
2659 | else | |
2660 | macro (&insn); | |
584892a6 | 2661 | macro_end (); |
252b5132 RH |
2662 | } |
2663 | else | |
2664 | { | |
2665 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2666 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2667 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2668 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2669 | else |
df58fc94 | 2670 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2671 | } |
e1b47bd5 RS |
2672 | |
2673 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2674 | } |
2675 | ||
738e5348 RS |
2676 | /* Convenience functions for abstracting away the differences between |
2677 | MIPS16 and non-MIPS16 relocations. */ | |
2678 | ||
2679 | static inline bfd_boolean | |
2680 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2681 | { | |
2682 | switch (reloc) | |
2683 | { | |
2684 | case BFD_RELOC_MIPS16_JMP: | |
2685 | case BFD_RELOC_MIPS16_GPREL: | |
2686 | case BFD_RELOC_MIPS16_GOT16: | |
2687 | case BFD_RELOC_MIPS16_CALL16: | |
2688 | case BFD_RELOC_MIPS16_HI16_S: | |
2689 | case BFD_RELOC_MIPS16_HI16: | |
2690 | case BFD_RELOC_MIPS16_LO16: | |
2691 | return TRUE; | |
2692 | ||
2693 | default: | |
2694 | return FALSE; | |
2695 | } | |
2696 | } | |
2697 | ||
df58fc94 RS |
2698 | static inline bfd_boolean |
2699 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2700 | { | |
2701 | switch (reloc) | |
2702 | { | |
2703 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2704 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2705 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2706 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2707 | case BFD_RELOC_MICROMIPS_JMP: | |
2708 | case BFD_RELOC_MICROMIPS_HI16: | |
2709 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2710 | case BFD_RELOC_MICROMIPS_LO16: | |
2711 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2712 | case BFD_RELOC_MICROMIPS_GOT16: | |
2713 | case BFD_RELOC_MICROMIPS_CALL16: | |
2714 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2715 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2716 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2717 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2718 | case BFD_RELOC_MICROMIPS_SUB: | |
2719 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2720 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2721 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2722 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2723 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2724 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2725 | case BFD_RELOC_MICROMIPS_JALR: | |
2726 | return TRUE; | |
2727 | ||
2728 | default: | |
2729 | return FALSE; | |
2730 | } | |
2731 | } | |
2732 | ||
2309ddf2 MR |
2733 | static inline bfd_boolean |
2734 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2735 | { | |
2736 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2737 | } | |
2738 | ||
738e5348 RS |
2739 | static inline bfd_boolean |
2740 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2741 | { | |
2309ddf2 | 2742 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2743 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2744 | } |
2745 | ||
2746 | static inline bfd_boolean | |
2747 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2748 | { | |
2309ddf2 | 2749 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2750 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2751 | } |
2752 | ||
2753 | static inline bfd_boolean | |
2754 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2755 | { | |
2309ddf2 | 2756 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2757 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2758 | } | |
2759 | ||
df58fc94 RS |
2760 | static inline bfd_boolean |
2761 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2762 | { | |
2309ddf2 | 2763 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2764 | } |
2765 | ||
2de39019 CM |
2766 | /* Return true if RELOC is a PC-relative relocation that does not have |
2767 | full address range. */ | |
2768 | ||
2769 | static inline bfd_boolean | |
2770 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2771 | { | |
2772 | switch (reloc) | |
2773 | { | |
2774 | case BFD_RELOC_16_PCREL_S2: | |
2775 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2776 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2777 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2778 | return TRUE; | |
2779 | ||
b47468a6 CM |
2780 | case BFD_RELOC_32_PCREL: |
2781 | return HAVE_64BIT_ADDRESSES; | |
2782 | ||
2de39019 CM |
2783 | default: |
2784 | return FALSE; | |
2785 | } | |
2786 | } | |
b47468a6 | 2787 | |
5919d012 | 2788 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2789 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2790 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2791 | |
2792 | static inline bfd_boolean | |
17a2f251 | 2793 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2794 | { |
3b91255e | 2795 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2796 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2797 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2798 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2799 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2800 | } | |
2801 | ||
2802 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2803 | reloc_needs_lo_p. */ | |
2804 | ||
2805 | static inline bfd_reloc_code_real_type | |
2806 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2807 | { | |
df58fc94 RS |
2808 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2809 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2810 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2811 | } |
2812 | ||
2813 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2814 | relocation. */ | |
2815 | ||
2816 | static inline bfd_boolean | |
17a2f251 | 2817 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2818 | { |
2819 | return (fixp->fx_next != NULL | |
738e5348 | 2820 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2821 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2822 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2823 | } | |
2824 | ||
252b5132 RH |
2825 | /* This function returns true if modifying a register requires a |
2826 | delay. */ | |
2827 | ||
2828 | static int | |
17a2f251 | 2829 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2830 | { |
2831 | unsigned long prev_pinfo; | |
2832 | ||
47e39b9d | 2833 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2834 | if (! mips_opts.noreorder |
81912461 ILT |
2835 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2836 | && ! gpr_interlocks) | |
2837 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2838 | && ! cop_interlocks))) | |
252b5132 | 2839 | { |
81912461 ILT |
2840 | /* A load from a coprocessor or from memory. All load delays |
2841 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2842 | /* Itbl support may require additional care here. */ |
252b5132 | 2843 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2844 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2845 | return 1; |
2846 | } | |
2847 | ||
2848 | return 0; | |
2849 | } | |
2850 | ||
462427c4 RS |
2851 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2852 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2853 | |
2854 | static void | |
462427c4 | 2855 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2856 | { |
2857 | struct insn_label_list *l; | |
2858 | valueT val; | |
2859 | ||
462427c4 | 2860 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2861 | { |
9c2799c2 | 2862 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2863 | symbol_set_frag (l->label, frag_now); |
2864 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2865 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2866 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2867 | ++val; |
2868 | S_SET_VALUE (l->label, val); | |
2869 | } | |
2870 | } | |
2871 | ||
462427c4 RS |
2872 | /* Move all labels in insn_labels to the current insertion point |
2873 | and treat them as text labels. */ | |
2874 | ||
2875 | static void | |
2876 | mips_move_text_labels (void) | |
2877 | { | |
2878 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2879 | } | |
2880 | ||
5f0fe04b TS |
2881 | static bfd_boolean |
2882 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2883 | { | |
2884 | bfd_boolean linkonce = FALSE; | |
2885 | segT symseg = S_GET_SEGMENT (sym); | |
2886 | ||
2887 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2888 | { | |
2889 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2890 | linkonce = TRUE; | |
2891 | #ifdef OBJ_ELF | |
2892 | /* The GNU toolchain uses an extension for ELF: a section | |
2893 | beginning with the magic string .gnu.linkonce is a | |
2894 | linkonce section. */ | |
2895 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2896 | sizeof ".gnu.linkonce" - 1) == 0) | |
2897 | linkonce = TRUE; | |
2898 | #endif | |
2899 | } | |
2900 | return linkonce; | |
2901 | } | |
2902 | ||
e1b47bd5 | 2903 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
2904 | linker to handle them specially, such as generating jalx instructions |
2905 | when needed. We also make them odd for the duration of the assembly, | |
2906 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2907 | in the adjust_symtab routine, while leaving them marked. This is |
2908 | convenient for the debugger and the disassembler. The linker knows | |
2909 | to make them odd again. */ | |
2910 | ||
2911 | static void | |
e1b47bd5 | 2912 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 2913 | { |
df58fc94 | 2914 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 2915 | |
a8dbcb85 | 2916 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
2917 | if (IS_ELF) |
2918 | { | |
2919 | if (mips_opts.mips16) | |
2920 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2921 | else | |
2922 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 2923 | } |
e1b47bd5 RS |
2924 | #endif |
2925 | if ((S_GET_VALUE (label) & 1) == 0 | |
2926 | /* Don't adjust the address if the label is global or weak, or | |
2927 | in a link-once section, since we'll be emitting symbol reloc | |
2928 | references to it which will be patched up by the linker, and | |
2929 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
2930 | && !S_IS_WEAK (label) | |
2931 | && !S_IS_EXTERNAL (label) | |
2932 | && !s_is_linkonce (label, now_seg)) | |
2933 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
2934 | } | |
2935 | ||
2936 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
2937 | ||
2938 | static void | |
2939 | mips_compressed_mark_labels (void) | |
2940 | { | |
2941 | struct insn_label_list *l; | |
2942 | ||
2943 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
2944 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
2945 | } |
2946 | ||
4d7206a2 RS |
2947 | /* End the current frag. Make it a variant frag and record the |
2948 | relaxation info. */ | |
2949 | ||
2950 | static void | |
2951 | relax_close_frag (void) | |
2952 | { | |
584892a6 | 2953 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2954 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2955 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2956 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2957 | ||
2958 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2959 | mips_relax.first_fixup = 0; | |
2960 | } | |
2961 | ||
2962 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2963 | See the comment above RELAX_ENCODE for more details. */ | |
2964 | ||
2965 | static void | |
2966 | relax_start (symbolS *symbol) | |
2967 | { | |
9c2799c2 | 2968 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2969 | mips_relax.sequence = 1; |
2970 | mips_relax.symbol = symbol; | |
2971 | } | |
2972 | ||
2973 | /* Start generating the second version of a relaxable sequence. | |
2974 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2975 | |
2976 | static void | |
4d7206a2 RS |
2977 | relax_switch (void) |
2978 | { | |
9c2799c2 | 2979 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2980 | mips_relax.sequence = 2; |
2981 | } | |
2982 | ||
2983 | /* End the current relaxable sequence. */ | |
2984 | ||
2985 | static void | |
2986 | relax_end (void) | |
2987 | { | |
9c2799c2 | 2988 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2989 | relax_close_frag (); |
2990 | mips_relax.sequence = 0; | |
2991 | } | |
2992 | ||
11625dd8 RS |
2993 | /* Return true if IP is a delayed branch or jump. */ |
2994 | ||
2995 | static inline bfd_boolean | |
2996 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2997 | { | |
2998 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2999 | | INSN_COND_BRANCH_DELAY | |
3000 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3001 | } | |
3002 | ||
3003 | /* Return true if IP is a compact branch or jump. */ | |
3004 | ||
3005 | static inline bfd_boolean | |
3006 | compact_branch_p (const struct mips_cl_insn *ip) | |
3007 | { | |
3008 | if (mips_opts.mips16) | |
3009 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3010 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3011 | else | |
3012 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3013 | | INSN2_COND_BRANCH)) != 0; | |
3014 | } | |
3015 | ||
3016 | /* Return true if IP is an unconditional branch or jump. */ | |
3017 | ||
3018 | static inline bfd_boolean | |
3019 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3020 | { | |
3021 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3022 | || (mips_opts.mips16 | |
3023 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3024 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3025 | } | |
3026 | ||
3027 | /* Return true if IP is a branch-likely instruction. */ | |
3028 | ||
3029 | static inline bfd_boolean | |
3030 | branch_likely_p (const struct mips_cl_insn *ip) | |
3031 | { | |
3032 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3033 | } | |
3034 | ||
14fe068b RS |
3035 | /* Return the type of nop that should be used to fill the delay slot |
3036 | of delayed branch IP. */ | |
3037 | ||
3038 | static struct mips_cl_insn * | |
3039 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3040 | { | |
3041 | if (mips_opts.micromips | |
3042 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3043 | return µmips_nop32_insn; | |
3044 | return NOP_INSN; | |
3045 | } | |
3046 | ||
2309ddf2 | 3047 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3048 | |
3049 | static unsigned int | |
3050 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3051 | { | |
2309ddf2 | 3052 | unsigned long pinfo2; |
df58fc94 RS |
3053 | unsigned int mask; |
3054 | ||
3055 | mask = 0; | |
df58fc94 RS |
3056 | pinfo2 = ip->insn_mo->pinfo2; |
3057 | if (mips_opts.micromips) | |
3058 | { | |
df58fc94 RS |
3059 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3060 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3061 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3062 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3063 | if (pinfo2 & INSN2_MOD_SP) |
3064 | mask |= 1 << SP; | |
3065 | } | |
3066 | return mask; | |
3067 | } | |
3068 | ||
4c260379 RS |
3069 | /* Return the mask of core registers that IP reads. */ |
3070 | ||
3071 | static unsigned int | |
3072 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3073 | { | |
3074 | unsigned long pinfo, pinfo2; | |
3075 | unsigned int mask; | |
3076 | ||
df58fc94 | 3077 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3078 | pinfo = ip->insn_mo->pinfo; |
3079 | pinfo2 = ip->insn_mo->pinfo2; | |
3080 | if (mips_opts.mips16) | |
3081 | { | |
3082 | if (pinfo & MIPS16_INSN_READ_X) | |
3083 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3084 | if (pinfo & MIPS16_INSN_READ_Y) | |
3085 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3086 | if (pinfo & MIPS16_INSN_READ_T) | |
3087 | mask |= 1 << TREG; | |
3088 | if (pinfo & MIPS16_INSN_READ_SP) | |
3089 | mask |= 1 << SP; | |
3090 | if (pinfo & MIPS16_INSN_READ_31) | |
3091 | mask |= 1 << RA; | |
3092 | if (pinfo & MIPS16_INSN_READ_Z) | |
3093 | mask |= 1 << (mips16_to_32_reg_map | |
3094 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3095 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3096 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3097 | } | |
3098 | else | |
3099 | { | |
3100 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3101 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3102 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3103 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3104 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3105 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3106 | if (pinfo2 & INSN2_READ_GP) | |
3107 | mask |= 1 << GP; | |
3108 | if (pinfo2 & INSN2_READ_GPR_31) | |
3109 | mask |= 1 << RA; | |
4c260379 | 3110 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3111 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3112 | } |
2b0c8b40 MR |
3113 | if (mips_opts.micromips) |
3114 | { | |
3115 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3116 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3117 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3118 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3119 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3120 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3121 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3122 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3123 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3124 | { | |
3125 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3126 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3127 | } | |
3128 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3129 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3130 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3131 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3132 | } | |
fe35f09f RS |
3133 | /* Don't include register 0. */ |
3134 | return mask & ~1; | |
4c260379 RS |
3135 | } |
3136 | ||
3137 | /* Return the mask of core registers that IP writes. */ | |
3138 | ||
3139 | static unsigned int | |
3140 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3141 | { | |
3142 | unsigned long pinfo, pinfo2; | |
3143 | unsigned int mask; | |
3144 | ||
df58fc94 | 3145 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3146 | pinfo = ip->insn_mo->pinfo; |
3147 | pinfo2 = ip->insn_mo->pinfo2; | |
3148 | if (mips_opts.mips16) | |
3149 | { | |
3150 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3151 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3152 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3153 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3154 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3155 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3156 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3157 | mask |= 1 << TREG; | |
3158 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3159 | mask |= 1 << SP; | |
3160 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3161 | mask |= 1 << RA; | |
3162 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3163 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3164 | } | |
3165 | else | |
3166 | { | |
3167 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3168 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3169 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3170 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3171 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3172 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3173 | if (pinfo & INSN_WRITE_GPR_31) |
3174 | mask |= 1 << RA; | |
3175 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3176 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3177 | } |
2b0c8b40 MR |
3178 | if (mips_opts.micromips) |
3179 | { | |
3180 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3181 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3182 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3183 | { | |
3184 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3185 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3186 | } | |
3187 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3188 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3189 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3190 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3191 | } | |
fe35f09f RS |
3192 | /* Don't include register 0. */ |
3193 | return mask & ~1; | |
4c260379 RS |
3194 | } |
3195 | ||
3196 | /* Return the mask of floating-point registers that IP reads. */ | |
3197 | ||
3198 | static unsigned int | |
3199 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3200 | { | |
3201 | unsigned long pinfo, pinfo2; | |
3202 | unsigned int mask; | |
3203 | ||
3204 | mask = 0; | |
3205 | pinfo = ip->insn_mo->pinfo; | |
3206 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3207 | if (!mips_opts.mips16) |
df58fc94 RS |
3208 | { |
3209 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3210 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3211 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3212 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3213 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3214 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3215 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3216 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3217 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3218 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3219 | } |
3220 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3221 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3222 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3223 | mask |= mask << 1; | |
3224 | return mask; | |
3225 | } | |
3226 | ||
3227 | /* Return the mask of floating-point registers that IP writes. */ | |
3228 | ||
3229 | static unsigned int | |
3230 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3231 | { | |
3232 | unsigned long pinfo, pinfo2; | |
3233 | unsigned int mask; | |
3234 | ||
3235 | mask = 0; | |
3236 | pinfo = ip->insn_mo->pinfo; | |
3237 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3238 | if (!mips_opts.mips16) |
4c260379 RS |
3239 | { |
3240 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3241 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3242 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3243 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3244 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3245 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3246 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3247 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3248 | } |
3249 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3250 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3251 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3252 | mask |= mask << 1; | |
3253 | return mask; | |
3254 | } | |
3255 | ||
71400594 RS |
3256 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3257 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3258 | by VR4120 errata. */ | |
4d7206a2 | 3259 | |
71400594 RS |
3260 | static unsigned int |
3261 | classify_vr4120_insn (const char *name) | |
252b5132 | 3262 | { |
71400594 RS |
3263 | if (strncmp (name, "macc", 4) == 0) |
3264 | return FIX_VR4120_MACC; | |
3265 | if (strncmp (name, "dmacc", 5) == 0) | |
3266 | return FIX_VR4120_DMACC; | |
3267 | if (strncmp (name, "mult", 4) == 0) | |
3268 | return FIX_VR4120_MULT; | |
3269 | if (strncmp (name, "dmult", 5) == 0) | |
3270 | return FIX_VR4120_DMULT; | |
3271 | if (strstr (name, "div")) | |
3272 | return FIX_VR4120_DIV; | |
3273 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3274 | return FIX_VR4120_MTHILO; | |
3275 | return NUM_FIX_VR4120_CLASSES; | |
3276 | } | |
252b5132 | 3277 | |
ff239038 CM |
3278 | #define INSN_ERET 0x42000018 |
3279 | #define INSN_DERET 0x4200001f | |
3280 | ||
71400594 RS |
3281 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3282 | where INSN1 is the earlier instruction. Return the worst-case value | |
3283 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3284 | |
71400594 RS |
3285 | static unsigned int |
3286 | insns_between (const struct mips_cl_insn *insn1, | |
3287 | const struct mips_cl_insn *insn2) | |
3288 | { | |
3289 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3290 | unsigned int mask; |
71400594 RS |
3291 | |
3292 | /* This function needs to know which pinfo flags are set for INSN2 | |
3293 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3294 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3295 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3296 | pinfo1 = insn1->insn_mo->pinfo; |
3297 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3298 | |
4c260379 RS |
3299 | #define INSN2_USES_GPR(REG) \ |
3300 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3301 | |
3302 | /* For most targets, write-after-read dependencies on the HI and LO | |
3303 | registers must be separated by at least two instructions. */ | |
3304 | if (!hilo_interlocks) | |
252b5132 | 3305 | { |
71400594 RS |
3306 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3307 | return 2; | |
3308 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3309 | return 2; | |
3310 | } | |
3311 | ||
3312 | /* If we're working around r7000 errata, there must be two instructions | |
3313 | between an mfhi or mflo and any instruction that uses the result. */ | |
3314 | if (mips_7000_hilo_fix | |
df58fc94 | 3315 | && !mips_opts.micromips |
71400594 | 3316 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3317 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3318 | return 2; |
3319 | ||
ff239038 CM |
3320 | /* If we're working around 24K errata, one instruction is required |
3321 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3322 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3323 | { |
3324 | if (insn1->insn_opcode == INSN_ERET | |
3325 | || insn1->insn_opcode == INSN_DERET) | |
3326 | { | |
3327 | if (insn2 == NULL | |
3328 | || insn2->insn_opcode == INSN_ERET | |
3329 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3330 | || delayed_branch_p (insn2)) |
ff239038 CM |
3331 | return 1; |
3332 | } | |
3333 | } | |
3334 | ||
71400594 RS |
3335 | /* If working around VR4120 errata, check for combinations that need |
3336 | a single intervening instruction. */ | |
df58fc94 | 3337 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3338 | { |
3339 | unsigned int class1, class2; | |
252b5132 | 3340 | |
71400594 RS |
3341 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3342 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3343 | { |
71400594 RS |
3344 | if (insn2 == NULL) |
3345 | return 1; | |
3346 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3347 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3348 | return 1; | |
252b5132 | 3349 | } |
71400594 RS |
3350 | } |
3351 | ||
df58fc94 | 3352 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3353 | { |
3354 | /* Check for GPR or coprocessor load delays. All such delays | |
3355 | are on the RT register. */ | |
3356 | /* Itbl support may require additional care here. */ | |
3357 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3358 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3359 | { |
71400594 | 3360 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3361 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3362 | return 1; |
3363 | } | |
3364 | ||
3365 | /* Check for generic coprocessor hazards. | |
3366 | ||
3367 | This case is not handled very well. There is no special | |
3368 | knowledge of CP0 handling, and the coprocessors other than | |
3369 | the floating point unit are not distinguished at all. */ | |
3370 | /* Itbl support may require additional care here. FIXME! | |
3371 | Need to modify this to include knowledge about | |
3372 | user specified delays! */ | |
3373 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3374 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3375 | { | |
3376 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3377 | register. There must be a one instruction delay before INSN2 | |
3378 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3379 | mask = fpr_write_mask (insn1); |
3380 | if (mask != 0) | |
252b5132 | 3381 | { |
4c260379 | 3382 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3383 | return 1; |
252b5132 RH |
3384 | } |
3385 | else | |
3386 | { | |
71400594 RS |
3387 | /* Read-after-write dependencies on the control registers |
3388 | require a two-instruction gap. */ | |
3389 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3390 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3391 | return 2; | |
3392 | ||
3393 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3394 | also a coprocessor instruction, assume there must be | |
3395 | a one instruction gap. */ | |
3396 | if (pinfo2 & INSN_COP) | |
3397 | return 1; | |
252b5132 RH |
3398 | } |
3399 | } | |
6b76fefe | 3400 | |
71400594 RS |
3401 | /* Check for read-after-write dependencies on the coprocessor |
3402 | control registers in cases where INSN1 does not need a general | |
3403 | coprocessor delay. This means that INSN1 is a floating point | |
3404 | comparison instruction. */ | |
3405 | /* Itbl support may require additional care here. */ | |
3406 | else if (!cop_interlocks | |
3407 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3408 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3409 | return 1; | |
3410 | } | |
6b76fefe | 3411 | |
4c260379 | 3412 | #undef INSN2_USES_GPR |
6b76fefe | 3413 | |
71400594 RS |
3414 | return 0; |
3415 | } | |
6b76fefe | 3416 | |
7d8e00cf RS |
3417 | /* Return the number of nops that would be needed to work around the |
3418 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3419 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3420 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3421 | |
3422 | static int | |
932d1a1b | 3423 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3424 | const struct mips_cl_insn *insn) |
3425 | { | |
4c260379 RS |
3426 | int i, j; |
3427 | unsigned int mask; | |
7d8e00cf RS |
3428 | |
3429 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3430 | are not affected by the errata. */ | |
3431 | if (insn != 0 | |
3432 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3433 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3434 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3435 | return 0; | |
3436 | ||
3437 | /* Search for the first MFLO or MFHI. */ | |
3438 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3439 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3440 | { |
3441 | /* Extract the destination register. */ | |
4c260379 | 3442 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3443 | |
3444 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3445 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3446 | return 0; |
3447 | ||
3448 | /* ...or if any of the intervening instructions do. */ | |
3449 | for (j = 0; j < i; j++) | |
4c260379 | 3450 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3451 | return 0; |
3452 | ||
932d1a1b RS |
3453 | if (i >= ignore) |
3454 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3455 | } |
3456 | return 0; | |
3457 | } | |
3458 | ||
15be625d CM |
3459 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3460 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3461 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3462 | ||
3463 | /* Return the minimum alignment for this store instruction. */ | |
3464 | ||
3465 | static int | |
3466 | fix_24k_align_to (const struct mips_opcode *mo) | |
3467 | { | |
3468 | if (strcmp (mo->name, "sh") == 0) | |
3469 | return 2; | |
3470 | ||
3471 | if (strcmp (mo->name, "swc1") == 0 | |
3472 | || strcmp (mo->name, "swc2") == 0 | |
3473 | || strcmp (mo->name, "sw") == 0 | |
3474 | || strcmp (mo->name, "sc") == 0 | |
3475 | || strcmp (mo->name, "s.s") == 0) | |
3476 | return 4; | |
3477 | ||
3478 | if (strcmp (mo->name, "sdc1") == 0 | |
3479 | || strcmp (mo->name, "sdc2") == 0 | |
3480 | || strcmp (mo->name, "s.d") == 0) | |
3481 | return 8; | |
3482 | ||
3483 | /* sb, swl, swr */ | |
3484 | return 1; | |
3485 | } | |
3486 | ||
3487 | struct fix_24k_store_info | |
3488 | { | |
3489 | /* Immediate offset, if any, for this store instruction. */ | |
3490 | short off; | |
3491 | /* Alignment required by this store instruction. */ | |
3492 | int align_to; | |
3493 | /* True for register offsets. */ | |
3494 | int register_offset; | |
3495 | }; | |
3496 | ||
3497 | /* Comparison function used by qsort. */ | |
3498 | ||
3499 | static int | |
3500 | fix_24k_sort (const void *a, const void *b) | |
3501 | { | |
3502 | const struct fix_24k_store_info *pos1 = a; | |
3503 | const struct fix_24k_store_info *pos2 = b; | |
3504 | ||
3505 | return (pos1->off - pos2->off); | |
3506 | } | |
3507 | ||
3508 | /* INSN is a store instruction. Try to record the store information | |
3509 | in STINFO. Return false if the information isn't known. */ | |
3510 | ||
3511 | static bfd_boolean | |
3512 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3513 | const struct mips_cl_insn *insn) |
15be625d CM |
3514 | { |
3515 | /* The instruction must have a known offset. */ | |
3516 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3517 | return FALSE; | |
3518 | ||
3519 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3520 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3521 | return TRUE; | |
3522 | } | |
3523 | ||
932d1a1b RS |
3524 | /* Return the number of nops that would be needed to work around the 24k |
3525 | "lost data on stores during refill" errata if instruction INSN | |
3526 | immediately followed the 2 instructions described by HIST. | |
3527 | Ignore hazards that are contained within the first IGNORE | |
3528 | instructions of HIST. | |
3529 | ||
3530 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3531 | for the data cache refills and store data. The following describes | |
3532 | the scenario where the store data could be lost. | |
3533 | ||
3534 | * A data cache miss, due to either a load or a store, causing fill | |
3535 | data to be supplied by the memory subsystem | |
3536 | * The first three doublewords of fill data are returned and written | |
3537 | into the cache | |
3538 | * A sequence of four stores occurs in consecutive cycles around the | |
3539 | final doubleword of the fill: | |
3540 | * Store A | |
3541 | * Store B | |
3542 | * Store C | |
3543 | * Zero, One or more instructions | |
3544 | * Store D | |
3545 | ||
3546 | The four stores A-D must be to different doublewords of the line that | |
3547 | is being filled. The fourth instruction in the sequence above permits | |
3548 | the fill of the final doubleword to be transferred from the FSB into | |
3549 | the cache. In the sequence above, the stores may be either integer | |
3550 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3551 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3552 | different doublewords on the line. If the floating point unit is | |
3553 | running in 1:2 mode, it is not possible to create the sequence above | |
3554 | using only floating point store instructions. | |
15be625d CM |
3555 | |
3556 | In this case, the cache line being filled is incorrectly marked | |
3557 | invalid, thereby losing the data from any store to the line that | |
3558 | occurs between the original miss and the completion of the five | |
3559 | cycle sequence shown above. | |
3560 | ||
932d1a1b | 3561 | The workarounds are: |
15be625d | 3562 | |
932d1a1b RS |
3563 | * Run the data cache in write-through mode. |
3564 | * Insert a non-store instruction between | |
3565 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3566 | |
3567 | static int | |
932d1a1b | 3568 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3569 | const struct mips_cl_insn *insn) |
3570 | { | |
3571 | struct fix_24k_store_info pos[3]; | |
3572 | int align, i, base_offset; | |
3573 | ||
932d1a1b RS |
3574 | if (ignore >= 2) |
3575 | return 0; | |
3576 | ||
ab9794cf RS |
3577 | /* If the previous instruction wasn't a store, there's nothing to |
3578 | worry about. */ | |
15be625d CM |
3579 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3580 | return 0; | |
3581 | ||
ab9794cf RS |
3582 | /* If the instructions after the previous one are unknown, we have |
3583 | to assume the worst. */ | |
3584 | if (!insn) | |
15be625d CM |
3585 | return 1; |
3586 | ||
ab9794cf RS |
3587 | /* Check whether we are dealing with three consecutive stores. */ |
3588 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3589 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3590 | return 0; |
3591 | ||
3592 | /* If we don't know the relationship between the store addresses, | |
3593 | assume the worst. */ | |
ab9794cf | 3594 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3595 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3596 | return 1; | |
3597 | ||
3598 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3599 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3600 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3601 | return 1; | |
3602 | ||
3603 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3604 | ||
3605 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3606 | X bytes and such that the base register + X is known to be aligned | |
3607 | to align bytes. */ | |
3608 | ||
3609 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3610 | align = 8; | |
3611 | else | |
3612 | { | |
3613 | align = pos[0].align_to; | |
3614 | base_offset = pos[0].off; | |
3615 | for (i = 1; i < 3; i++) | |
3616 | if (align < pos[i].align_to) | |
3617 | { | |
3618 | align = pos[i].align_to; | |
3619 | base_offset = pos[i].off; | |
3620 | } | |
3621 | for (i = 0; i < 3; i++) | |
3622 | pos[i].off -= base_offset; | |
3623 | } | |
3624 | ||
3625 | pos[0].off &= ~align + 1; | |
3626 | pos[1].off &= ~align + 1; | |
3627 | pos[2].off &= ~align + 1; | |
3628 | ||
3629 | /* If any two stores write to the same chunk, they also write to the | |
3630 | same doubleword. The offsets are still sorted at this point. */ | |
3631 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3632 | return 0; | |
3633 | ||
3634 | /* A range of at least 9 bytes is needed for the stores to be in | |
3635 | non-overlapping doublewords. */ | |
3636 | if (pos[2].off - pos[0].off <= 8) | |
3637 | return 0; | |
3638 | ||
3639 | if (pos[2].off - pos[1].off >= 24 | |
3640 | || pos[1].off - pos[0].off >= 24 | |
3641 | || pos[2].off - pos[0].off >= 32) | |
3642 | return 0; | |
3643 | ||
3644 | return 1; | |
3645 | } | |
3646 | ||
71400594 | 3647 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3648 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3649 | where HIST[0] is the most recent instruction. Ignore hazards |
3650 | between INSN and the first IGNORE instructions in HIST. | |
3651 | ||
3652 | If INSN is null, return the worse-case number of nops for any | |
3653 | instruction. */ | |
bdaaa2e1 | 3654 | |
71400594 | 3655 | static int |
932d1a1b | 3656 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3657 | const struct mips_cl_insn *insn) |
3658 | { | |
3659 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3660 | |
71400594 | 3661 | nops = 0; |
932d1a1b | 3662 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3663 | { |
91d6fa6a | 3664 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3665 | if (tmp_nops > nops) |
3666 | nops = tmp_nops; | |
3667 | } | |
7d8e00cf | 3668 | |
df58fc94 | 3669 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3670 | { |
932d1a1b | 3671 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3672 | if (tmp_nops > nops) |
3673 | nops = tmp_nops; | |
3674 | } | |
3675 | ||
df58fc94 | 3676 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3677 | { |
932d1a1b | 3678 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3679 | if (tmp_nops > nops) |
3680 | nops = tmp_nops; | |
3681 | } | |
3682 | ||
71400594 RS |
3683 | return nops; |
3684 | } | |
252b5132 | 3685 | |
71400594 | 3686 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3687 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3688 | would be needed after the extended sequence, ignoring hazards |
3689 | in the first IGNORE instructions. */ | |
252b5132 | 3690 | |
71400594 | 3691 | static int |
932d1a1b RS |
3692 | nops_for_sequence (int num_insns, int ignore, |
3693 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3694 | { |
3695 | va_list args; | |
3696 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3697 | struct mips_cl_insn *cursor; | |
3698 | int nops; | |
3699 | ||
91d6fa6a | 3700 | va_start (args, hist); |
71400594 | 3701 | cursor = buffer + num_insns; |
91d6fa6a | 3702 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3703 | while (cursor > buffer) |
3704 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3705 | ||
932d1a1b | 3706 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3707 | va_end (args); |
3708 | return nops; | |
3709 | } | |
252b5132 | 3710 | |
71400594 RS |
3711 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3712 | worst-case delay for the branch target. */ | |
252b5132 | 3713 | |
71400594 | 3714 | static int |
932d1a1b | 3715 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3716 | const struct mips_cl_insn *insn) |
3717 | { | |
3718 | int nops, tmp_nops; | |
60b63b72 | 3719 | |
932d1a1b | 3720 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3721 | if (delayed_branch_p (insn)) |
71400594 | 3722 | { |
932d1a1b | 3723 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3724 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3725 | if (tmp_nops > nops) |
3726 | nops = tmp_nops; | |
3727 | } | |
11625dd8 | 3728 | else if (compact_branch_p (insn)) |
71400594 | 3729 | { |
932d1a1b | 3730 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3731 | if (tmp_nops > nops) |
3732 | nops = tmp_nops; | |
3733 | } | |
3734 | return nops; | |
3735 | } | |
3736 | ||
c67a084a NC |
3737 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3738 | ||
3739 | static void | |
3740 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3741 | { | |
df58fc94 | 3742 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3743 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3744 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3745 | } | |
3746 | ||
3747 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3748 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3749 | ||
3750 | static void | |
3751 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3752 | { | |
df58fc94 | 3753 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3754 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3755 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3756 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3757 | { | |
3758 | int sreg; | |
3759 | expressionS ep; | |
3760 | ||
3761 | if (! mips_opts.at) | |
3762 | return; | |
3763 | ||
df58fc94 | 3764 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3765 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3766 | return; | |
3767 | ||
3768 | ep.X_op = O_constant; | |
3769 | ep.X_add_number = 0xcfff0000; | |
3770 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3771 | ep.X_add_number = 0xffff; | |
3772 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3773 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3774 | } | |
3775 | } | |
3776 | ||
3777 | static void | |
3778 | fix_loongson2f (struct mips_cl_insn * ip) | |
3779 | { | |
3780 | if (mips_fix_loongson2f_nop) | |
3781 | fix_loongson2f_nop (ip); | |
3782 | ||
3783 | if (mips_fix_loongson2f_jump) | |
3784 | fix_loongson2f_jump (ip); | |
3785 | } | |
3786 | ||
a4e06468 RS |
3787 | /* IP is a branch that has a delay slot, and we need to fill it |
3788 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3789 | with the previous instruction. |
3790 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3791 | RELOC_TYPE. */ | |
a4e06468 RS |
3792 | |
3793 | static bfd_boolean | |
e407c74b NC |
3794 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3795 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3796 | { |
2b0c8b40 | 3797 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3798 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3799 | ||
3800 | /* -O2 and above is required for this optimization. */ | |
3801 | if (mips_optimize < 2) | |
3802 | return FALSE; | |
3803 | ||
3804 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3805 | if (mips_opts.nomove) | |
3806 | return FALSE; | |
3807 | ||
3808 | /* We can't swap if the previous instruction's position is fixed. */ | |
3809 | if (history[0].fixed_p) | |
3810 | return FALSE; | |
3811 | ||
3812 | /* If the previous previous insn was in a .set noreorder, we can't | |
3813 | swap. Actually, the MIPS assembler will swap in this situation. | |
3814 | However, gcc configured -with-gnu-as will generate code like | |
3815 | ||
3816 | .set noreorder | |
3817 | lw $4,XXX | |
3818 | .set reorder | |
3819 | INSN | |
3820 | bne $4,$0,foo | |
3821 | ||
3822 | in which we can not swap the bne and INSN. If gcc is not configured | |
3823 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3824 | if (history[1].noreorder_p) | |
3825 | return FALSE; | |
3826 | ||
87333bb7 MR |
3827 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3828 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3829 | if (mips_opts.mips16 && history[0].fixp[0]) |
3830 | return FALSE; | |
3831 | ||
3832 | /* If the branch is itself the target of a branch, we can not swap. | |
3833 | We cheat on this; all we check for is whether there is a label on | |
3834 | this instruction. If there are any branches to anything other than | |
3835 | a label, users must use .set noreorder. */ | |
3836 | if (seg_info (now_seg)->label_list) | |
3837 | return FALSE; | |
3838 | ||
3839 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3840 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3841 | MIPS16 code, which uses variant frags for different purposes. */ |
3842 | if (!mips_opts.mips16 | |
a4e06468 RS |
3843 | && history[0].frag |
3844 | && history[0].frag->fr_type == rs_machine_dependent) | |
3845 | return FALSE; | |
3846 | ||
bcd530a7 RS |
3847 | /* We do not swap with instructions that cannot architecturally |
3848 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3849 | also refrain from swapping with a trap instruction, since it | |
3850 | complicates trap handlers to have the trap instruction be in | |
3851 | a delay slot. */ | |
a4e06468 | 3852 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3853 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3854 | return FALSE; |
3855 | ||
3856 | /* Check for conflicts between the branch and the instructions | |
3857 | before the candidate delay slot. */ | |
3858 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3859 | return FALSE; | |
3860 | ||
3861 | /* Check for conflicts between the swapped sequence and the | |
3862 | target of the branch. */ | |
3863 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3864 | return FALSE; | |
3865 | ||
3866 | /* If the branch reads a register that the previous | |
3867 | instruction sets, we can not swap. */ | |
3868 | gpr_read = gpr_read_mask (ip); | |
3869 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3870 | if (gpr_read & prev_gpr_write) | |
3871 | return FALSE; | |
3872 | ||
3873 | /* If the branch writes a register that the previous | |
3874 | instruction sets, we can not swap. */ | |
3875 | gpr_write = gpr_write_mask (ip); | |
3876 | if (gpr_write & prev_gpr_write) | |
3877 | return FALSE; | |
3878 | ||
3879 | /* If the branch writes a register that the previous | |
3880 | instruction reads, we can not swap. */ | |
3881 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3882 | if (gpr_write & prev_gpr_read) | |
3883 | return FALSE; | |
3884 | ||
3885 | /* If one instruction sets a condition code and the | |
3886 | other one uses a condition code, we can not swap. */ | |
3887 | pinfo = ip->insn_mo->pinfo; | |
3888 | if ((pinfo & INSN_READ_COND_CODE) | |
3889 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3890 | return FALSE; | |
3891 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3892 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3893 | return FALSE; | |
3894 | ||
3895 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3896 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3897 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3898 | return FALSE; | |
2b0c8b40 MR |
3899 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3900 | return FALSE; | |
a4e06468 | 3901 | |
df58fc94 RS |
3902 | /* If the previous instruction has an incorrect size for a fixed |
3903 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3904 | pinfo2 = ip->insn_mo->pinfo2; |
3905 | if (mips_opts.micromips | |
3906 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3907 | && insn_length (history) != 2) | |
3908 | return FALSE; | |
3909 | if (mips_opts.micromips | |
3910 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3911 | && insn_length (history) != 4) | |
3912 | return FALSE; | |
3913 | ||
e407c74b NC |
3914 | /* On R5900 short loops need to be fixed by inserting a nop in |
3915 | the branch delay slots. | |
3916 | A short loop can be terminated too early. */ | |
3917 | if (mips_opts.arch == CPU_R5900 | |
3918 | /* Check if instruction has a parameter, ignore "j $31". */ | |
3919 | && (address_expr != NULL) | |
3920 | /* Parameter must be 16 bit. */ | |
3921 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
3922 | /* Branch to same segment. */ | |
3923 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
3924 | /* Branch to same code fragment. */ | |
3925 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
3926 | /* Can only calculate branch offset if value is known. */ | |
3927 | && symbol_constant_p(address_expr->X_add_symbol) | |
3928 | /* Check if branch is really conditional. */ | |
3929 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
3930 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
3931 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
3932 | { | |
3933 | int distance; | |
3934 | /* Check if loop is shorter than 6 instructions including | |
3935 | branch and delay slot. */ | |
3936 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
3937 | if (distance <= 20) | |
3938 | { | |
3939 | int i; | |
3940 | int rv; | |
3941 | ||
3942 | rv = FALSE; | |
3943 | /* When the loop includes branches or jumps, | |
3944 | it is not a short loop. */ | |
3945 | for (i = 0; i < (distance / 4); i++) | |
3946 | { | |
3947 | if ((history[i].cleared_p) | |
3948 | || delayed_branch_p(&history[i])) | |
3949 | { | |
3950 | rv = TRUE; | |
3951 | break; | |
3952 | } | |
3953 | } | |
3954 | if (rv == FALSE) | |
3955 | { | |
3956 | /* Insert nop after branch to fix short loop. */ | |
3957 | return FALSE; | |
3958 | } | |
3959 | } | |
3960 | } | |
3961 | ||
a4e06468 RS |
3962 | return TRUE; |
3963 | } | |
3964 | ||
e407c74b NC |
3965 | /* Decide how we should add IP to the instruction stream. |
3966 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3967 | RELOC_TYPE. */ | |
a4e06468 RS |
3968 | |
3969 | static enum append_method | |
e407c74b NC |
3970 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
3971 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
3972 | { |
3973 | unsigned long pinfo; | |
3974 | ||
3975 | /* The relaxed version of a macro sequence must be inherently | |
3976 | hazard-free. */ | |
3977 | if (mips_relax.sequence == 2) | |
3978 | return APPEND_ADD; | |
3979 | ||
3980 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3981 | if (mips_opts.noreorder) | |
3982 | return APPEND_ADD; | |
3983 | ||
3984 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3985 | if (delayed_branch_p (ip)) |
a4e06468 | 3986 | { |
e407c74b NC |
3987 | if (!branch_likely_p (ip) |
3988 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
3989 | return APPEND_SWAP; |
3990 | ||
11625dd8 | 3991 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3992 | if (mips_opts.mips16 |
3993 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3994 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3995 | return APPEND_ADD_COMPACT; | |
3996 | ||
3997 | return APPEND_ADD_WITH_NOP; | |
3998 | } | |
3999 | ||
a4e06468 RS |
4000 | return APPEND_ADD; |
4001 | } | |
4002 | ||
ceb94aa5 RS |
4003 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4004 | Point IP->insn_mo to the new opcode's definition. */ | |
4005 | ||
4006 | static void | |
4007 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4008 | { | |
4009 | const struct mips_opcode *mo, *end; | |
4010 | ||
4011 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4012 | for (mo = ip->insn_mo; mo < end; mo++) | |
4013 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4014 | { | |
4015 | ip->insn_mo = mo; | |
4016 | return; | |
4017 | } | |
4018 | abort (); | |
4019 | } | |
4020 | ||
df58fc94 RS |
4021 | /* For microMIPS macros, we need to generate a local number label |
4022 | as the target of branches. */ | |
4023 | #define MICROMIPS_LABEL_CHAR '\037' | |
4024 | static unsigned long micromips_target_label; | |
4025 | static char micromips_target_name[32]; | |
4026 | ||
4027 | static char * | |
4028 | micromips_label_name (void) | |
4029 | { | |
4030 | char *p = micromips_target_name; | |
4031 | char symbol_name_temporary[24]; | |
4032 | unsigned long l; | |
4033 | int i; | |
4034 | ||
4035 | if (*p) | |
4036 | return p; | |
4037 | ||
4038 | i = 0; | |
4039 | l = micromips_target_label; | |
4040 | #ifdef LOCAL_LABEL_PREFIX | |
4041 | *p++ = LOCAL_LABEL_PREFIX; | |
4042 | #endif | |
4043 | *p++ = 'L'; | |
4044 | *p++ = MICROMIPS_LABEL_CHAR; | |
4045 | do | |
4046 | { | |
4047 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4048 | l /= 10; | |
4049 | } | |
4050 | while (l != 0); | |
4051 | while (i > 0) | |
4052 | *p++ = symbol_name_temporary[--i]; | |
4053 | *p = '\0'; | |
4054 | ||
4055 | return micromips_target_name; | |
4056 | } | |
4057 | ||
4058 | static void | |
4059 | micromips_label_expr (expressionS *label_expr) | |
4060 | { | |
4061 | label_expr->X_op = O_symbol; | |
4062 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4063 | label_expr->X_add_number = 0; | |
4064 | } | |
4065 | ||
4066 | static void | |
4067 | micromips_label_inc (void) | |
4068 | { | |
4069 | micromips_target_label++; | |
4070 | *micromips_target_name = '\0'; | |
4071 | } | |
4072 | ||
4073 | static void | |
4074 | micromips_add_label (void) | |
4075 | { | |
4076 | symbolS *s; | |
4077 | ||
4078 | s = colon (micromips_label_name ()); | |
4079 | micromips_label_inc (); | |
4080 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4081 | if (IS_ELF) | |
4082 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4083 | #else |
4084 | (void) s; | |
df58fc94 RS |
4085 | #endif |
4086 | } | |
4087 | ||
4088 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4089 | corresponding to the requested one if any. Otherwise return | |
4090 | the reloc unchanged. */ | |
4091 | ||
4092 | static bfd_reloc_code_real_type | |
4093 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4094 | { | |
4095 | static const bfd_reloc_code_real_type relocs[][2] = | |
4096 | { | |
4097 | /* Keep sorted incrementally by the left-hand key. */ | |
4098 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4099 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4100 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4101 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4102 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4103 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4104 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4105 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4106 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4107 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4108 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4109 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4110 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4111 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4112 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4113 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4114 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4115 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4116 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4117 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4118 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4119 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4120 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4121 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4122 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4123 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4124 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4125 | }; | |
4126 | bfd_reloc_code_real_type r; | |
4127 | size_t i; | |
4128 | ||
4129 | if (!mips_opts.micromips) | |
4130 | return reloc; | |
4131 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4132 | { | |
4133 | r = relocs[i][0]; | |
4134 | if (r > reloc) | |
4135 | return reloc; | |
4136 | if (r == reloc) | |
4137 | return relocs[i][1]; | |
4138 | } | |
4139 | return reloc; | |
4140 | } | |
4141 | ||
b886a2ab RS |
4142 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4143 | Return true on success, storing the resolved value in RESULT. */ | |
4144 | ||
4145 | static bfd_boolean | |
4146 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4147 | offsetT *result) | |
4148 | { | |
4149 | switch (reloc) | |
4150 | { | |
4151 | case BFD_RELOC_MIPS_HIGHEST: | |
4152 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4153 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4154 | return TRUE; | |
4155 | ||
4156 | case BFD_RELOC_MIPS_HIGHER: | |
4157 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4158 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4159 | return TRUE; | |
4160 | ||
4161 | case BFD_RELOC_HI16_S: | |
4162 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4163 | case BFD_RELOC_MIPS16_HI16_S: | |
4164 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4165 | return TRUE; | |
4166 | ||
4167 | case BFD_RELOC_HI16: | |
4168 | case BFD_RELOC_MICROMIPS_HI16: | |
4169 | case BFD_RELOC_MIPS16_HI16: | |
4170 | *result = (operand >> 16) & 0xffff; | |
4171 | return TRUE; | |
4172 | ||
4173 | case BFD_RELOC_LO16: | |
4174 | case BFD_RELOC_MICROMIPS_LO16: | |
4175 | case BFD_RELOC_MIPS16_LO16: | |
4176 | *result = operand & 0xffff; | |
4177 | return TRUE; | |
4178 | ||
4179 | case BFD_RELOC_UNUSED: | |
4180 | *result = operand; | |
4181 | return TRUE; | |
4182 | ||
4183 | default: | |
4184 | return FALSE; | |
4185 | } | |
4186 | } | |
4187 | ||
71400594 RS |
4188 | /* Output an instruction. IP is the instruction information. |
4189 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4190 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4191 | a macro expansion. */ | |
71400594 RS |
4192 | |
4193 | static void | |
4194 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4195 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4196 | { |
14fe068b | 4197 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4198 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4199 | enum append_method method; |
2309ddf2 | 4200 | bfd_boolean relax32; |
2b0c8b40 | 4201 | int branch_disp; |
71400594 | 4202 | |
2309ddf2 | 4203 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4204 | fix_loongson2f (ip); |
4205 | ||
738f4d98 | 4206 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4207 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4208 | |
df58fc94 | 4209 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4210 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4211 | |
4212 | if (mips_opts.micromips | |
4213 | && !expansionp | |
4214 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4215 | && micromips_insn_length (ip->insn_mo) != 2) | |
4216 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4217 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4218 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4219 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4220 | |
15be625d CM |
4221 | if (address_expr == NULL) |
4222 | ip->complete_p = 1; | |
b886a2ab RS |
4223 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4224 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4225 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4226 | && address_expr->X_op == O_constant) |
4227 | { | |
15be625d CM |
4228 | switch (*reloc_type) |
4229 | { | |
15be625d | 4230 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4231 | { |
4232 | int shift; | |
4233 | ||
4234 | shift = mips_opts.micromips ? 1 : 2; | |
4235 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4236 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4237 | (unsigned long) address_expr->X_add_number); | |
4238 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4239 | & 0x3ffffff); | |
335574df | 4240 | ip->complete_p = 1; |
df58fc94 | 4241 | } |
15be625d CM |
4242 | break; |
4243 | ||
4244 | case BFD_RELOC_MIPS16_JMP: | |
4245 | if ((address_expr->X_add_number & 3) != 0) | |
4246 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4247 | (unsigned long) address_expr->X_add_number); | |
4248 | ip->insn_opcode |= | |
4249 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4250 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4251 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4252 | ip->complete_p = 1; |
15be625d CM |
4253 | break; |
4254 | ||
4255 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4256 | { |
4257 | int shift; | |
4258 | ||
4259 | shift = mips_opts.micromips ? 1 : 2; | |
4260 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4261 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4262 | (unsigned long) address_expr->X_add_number); | |
4263 | if (!mips_relax_branch) | |
4264 | { | |
4265 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4266 | & ~((1 << (shift + 16)) - 1)) | |
4267 | as_bad (_("branch address range overflow (0x%lx)"), | |
4268 | (unsigned long) address_expr->X_add_number); | |
4269 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4270 | & 0xffff); | |
4271 | } | |
df58fc94 | 4272 | } |
15be625d CM |
4273 | break; |
4274 | ||
4275 | default: | |
b886a2ab RS |
4276 | { |
4277 | offsetT value; | |
4278 | ||
4279 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4280 | &value)) | |
4281 | { | |
4282 | ip->insn_opcode |= value & 0xffff; | |
4283 | ip->complete_p = 1; | |
4284 | } | |
4285 | } | |
4286 | break; | |
4287 | } | |
15be625d CM |
4288 | } |
4289 | ||
71400594 RS |
4290 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4291 | { | |
4292 | /* There are a lot of optimizations we could do that we don't. | |
4293 | In particular, we do not, in general, reorder instructions. | |
4294 | If you use gcc with optimization, it will reorder | |
4295 | instructions and generally do much more optimization then we | |
4296 | do here; repeating all that work in the assembler would only | |
4297 | benefit hand written assembly code, and does not seem worth | |
4298 | it. */ | |
4299 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4300 | ? nops_for_insn (0, history, NULL) |
4301 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4302 | if (nops > 0) |
252b5132 RH |
4303 | { |
4304 | fragS *old_frag; | |
4305 | unsigned long old_frag_offset; | |
4306 | int i; | |
252b5132 RH |
4307 | |
4308 | old_frag = frag_now; | |
4309 | old_frag_offset = frag_now_fix (); | |
4310 | ||
4311 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4312 | add_fixed_insn (NOP_INSN); |
4313 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4314 | |
4315 | if (listing) | |
4316 | { | |
4317 | listing_prev_line (); | |
4318 | /* We may be at the start of a variant frag. In case we | |
4319 | are, make sure there is enough space for the frag | |
4320 | after the frags created by listing_prev_line. The | |
4321 | argument to frag_grow here must be at least as large | |
4322 | as the argument to all other calls to frag_grow in | |
4323 | this file. We don't have to worry about being in the | |
4324 | middle of a variant frag, because the variants insert | |
4325 | all needed nop instructions themselves. */ | |
4326 | frag_grow (40); | |
4327 | } | |
4328 | ||
462427c4 | 4329 | mips_move_text_labels (); |
252b5132 RH |
4330 | |
4331 | #ifndef NO_ECOFF_DEBUGGING | |
4332 | if (ECOFF_DEBUGGING) | |
4333 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4334 | #endif | |
4335 | } | |
71400594 RS |
4336 | } |
4337 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4338 | { | |
932d1a1b RS |
4339 | int nops; |
4340 | ||
4341 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4342 | ignoring hazards generated by the first prev_nop_frag_since | |
4343 | instructions. */ | |
4344 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4345 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4346 | |
71400594 RS |
4347 | /* Enforce NOPS as a minimum. */ |
4348 | if (nops > prev_nop_frag_required) | |
4349 | prev_nop_frag_required = nops; | |
252b5132 | 4350 | |
71400594 RS |
4351 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4352 | { | |
4353 | /* Settle for the current number of nops. Update the history | |
4354 | accordingly (for the benefit of any future .set reorder code). */ | |
4355 | prev_nop_frag = NULL; | |
4356 | insert_into_history (prev_nop_frag_since, | |
4357 | prev_nop_frag_holds, NOP_INSN); | |
4358 | } | |
4359 | else | |
4360 | { | |
4361 | /* Allow this instruction to replace one of the nops that was | |
4362 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4363 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4364 | prev_nop_frag_holds--; |
4365 | prev_nop_frag_since++; | |
252b5132 RH |
4366 | } |
4367 | } | |
4368 | ||
e407c74b | 4369 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4370 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4371 | |
58e2ea4d MR |
4372 | #ifdef OBJ_ELF |
4373 | /* The value passed to dwarf2_emit_insn is the distance between | |
4374 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4375 | should be recorded in the debug tables. This is normally the |
4376 | current address. | |
4377 | ||
df58fc94 RS |
4378 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4379 | addresses, so we use -1 for an address higher by one than the | |
4380 | current one. | |
e3a82c8e MR |
4381 | |
4382 | If the instruction produced is a branch that we will swap with | |
4383 | the preceding instruction, then we add the displacement by which | |
4384 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4385 | and for MIPS16/microMIPS code also prevents a debugger from |
4386 | placing a breakpoint in the middle of the branch (and corrupting | |
4387 | code if software breakpoints are used). */ | |
2b0c8b40 | 4388 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4389 | #endif |
4390 | ||
df58fc94 RS |
4391 | relax32 = (mips_relax_branch |
4392 | /* Don't try branch relaxation within .set nomacro, or within | |
4393 | .set noat if we use $at for PIC computations. If it turns | |
4394 | out that the branch was out-of-range, we'll get an error. */ | |
4395 | && !mips_opts.warn_about_macros | |
4396 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4397 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4398 | as they have no complementing branches. */ | |
4399 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4400 | |
4401 | if (!HAVE_CODE_COMPRESSION | |
4402 | && address_expr | |
4403 | && relax32 | |
0b25d3e6 | 4404 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4405 | && delayed_branch_p (ip)) |
4a6a3df4 | 4406 | { |
895921c9 | 4407 | relaxed_branch = TRUE; |
1e915849 RS |
4408 | add_relaxed_insn (ip, (relaxed_branch_length |
4409 | (NULL, NULL, | |
11625dd8 RS |
4410 | uncond_branch_p (ip) ? -1 |
4411 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4412 | : 0)), 4, |
4413 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4414 | (AT, |
11625dd8 RS |
4415 | uncond_branch_p (ip), |
4416 | branch_likely_p (ip), | |
1e915849 RS |
4417 | pinfo & INSN_WRITE_GPR_31, |
4418 | 0), | |
4419 | address_expr->X_add_symbol, | |
4420 | address_expr->X_add_number); | |
4a6a3df4 AO |
4421 | *reloc_type = BFD_RELOC_UNUSED; |
4422 | } | |
df58fc94 RS |
4423 | else if (mips_opts.micromips |
4424 | && address_expr | |
4425 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4426 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4427 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4428 | /* Don't try branch relaxation when users specify | |
4429 | 16-bit/32-bit instructions. */ | |
4430 | && !forced_insn_length) | |
df58fc94 RS |
4431 | { |
4432 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4433 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4434 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4435 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4436 | int al = pinfo & INSN_WRITE_GPR_31; |
4437 | int length32; | |
4438 | ||
4439 | gas_assert (address_expr != NULL); | |
4440 | gas_assert (!mips_relax.sequence); | |
4441 | ||
2b0c8b40 | 4442 | relaxed_branch = TRUE; |
df58fc94 RS |
4443 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4444 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4445 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4446 | relax32, 0, 0), | |
df58fc94 RS |
4447 | address_expr->X_add_symbol, |
4448 | address_expr->X_add_number); | |
4449 | *reloc_type = BFD_RELOC_UNUSED; | |
4450 | } | |
4451 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4452 | { |
4453 | /* We need to set up a variant frag. */ | |
df58fc94 | 4454 | gas_assert (address_expr != NULL); |
1e915849 RS |
4455 | add_relaxed_insn (ip, 4, 0, |
4456 | RELAX_MIPS16_ENCODE | |
4457 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4458 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4459 | delayed_branch_p (&history[0]), |
1e915849 RS |
4460 | history[0].mips16_absolute_jump_p), |
4461 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4462 | } |
5c04167a | 4463 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4464 | { |
11625dd8 | 4465 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4466 | /* Make sure there is enough room to swap this instruction with |
4467 | a following jump instruction. */ | |
4468 | frag_grow (6); | |
1e915849 | 4469 | add_fixed_insn (ip); |
252b5132 RH |
4470 | } |
4471 | else | |
4472 | { | |
4473 | if (mips_opts.mips16 | |
4474 | && mips_opts.noreorder | |
11625dd8 | 4475 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4476 | as_warn (_("extended instruction in delay slot")); |
4477 | ||
4d7206a2 RS |
4478 | if (mips_relax.sequence) |
4479 | { | |
4480 | /* If we've reached the end of this frag, turn it into a variant | |
4481 | frag and record the information for the instructions we've | |
4482 | written so far. */ | |
4483 | if (frag_room () < 4) | |
4484 | relax_close_frag (); | |
df58fc94 | 4485 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4486 | } |
4487 | ||
584892a6 | 4488 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4489 | { |
4490 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4491 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4492 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4493 | mips_macro_warning.insns[0]++; | |
4494 | } | |
584892a6 | 4495 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4496 | { |
4497 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4498 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4499 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4500 | mips_macro_warning.insns[1]++; | |
4501 | } | |
584892a6 | 4502 | |
1e915849 RS |
4503 | if (mips_opts.mips16) |
4504 | { | |
4505 | ip->fixed_p = 1; | |
4506 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4507 | } | |
4508 | add_fixed_insn (ip); | |
252b5132 RH |
4509 | } |
4510 | ||
9fe77896 | 4511 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4512 | { |
df58fc94 | 4513 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4514 | reloc_howto_type *howto0; |
9fe77896 RS |
4515 | reloc_howto_type *howto; |
4516 | int i; | |
34ce925e | 4517 | |
df58fc94 RS |
4518 | /* Perform any necessary conversion to microMIPS relocations |
4519 | and find out how many relocations there actually are. */ | |
4520 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4521 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4522 | ||
9fe77896 RS |
4523 | /* In a compound relocation, it is the final (outermost) |
4524 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4525 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4526 | ||
9fe77896 RS |
4527 | if (howto == NULL) |
4528 | { | |
4529 | /* To reproduce this failure try assembling gas/testsuites/ | |
4530 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4531 | assembler. */ | |
df58fc94 RS |
4532 | as_bad (_("Unsupported MIPS relocation number %d"), |
4533 | final_type[i - 1]); | |
9fe77896 RS |
4534 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4535 | } | |
2309ddf2 MR |
4536 | |
4537 | if (i > 1) | |
4538 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4539 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4540 | bfd_get_reloc_size (howto), | |
4541 | address_expr, | |
2309ddf2 MR |
4542 | howto0 && howto0->pc_relative, |
4543 | final_type[0]); | |
9fe77896 RS |
4544 | |
4545 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4546 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4547 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4548 | ||
4549 | /* These relocations can have an addend that won't fit in | |
4550 | 4 octets for 64bit assembly. */ | |
4551 | if (HAVE_64BIT_GPRS | |
4552 | && ! howto->partial_inplace | |
4553 | && (reloc_type[0] == BFD_RELOC_16 | |
4554 | || reloc_type[0] == BFD_RELOC_32 | |
4555 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4556 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4557 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4558 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4559 | || reloc_type[0] == BFD_RELOC_64 | |
4560 | || reloc_type[0] == BFD_RELOC_CTOR | |
4561 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4562 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4563 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4564 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4565 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4566 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4567 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4568 | || hi16_reloc_p (reloc_type[0]) | |
4569 | || lo16_reloc_p (reloc_type[0]))) | |
4570 | ip->fixp[0]->fx_no_overflow = 1; | |
4571 | ||
ddaf2c41 MR |
4572 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4573 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4574 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4575 | ip->fixp[0]->fx_no_overflow = 1; | |
4576 | ||
9fe77896 RS |
4577 | if (mips_relax.sequence) |
4578 | { | |
4579 | if (mips_relax.first_fixup == 0) | |
4580 | mips_relax.first_fixup = ip->fixp[0]; | |
4581 | } | |
4582 | else if (reloc_needs_lo_p (*reloc_type)) | |
4583 | { | |
4584 | struct mips_hi_fixup *hi_fixup; | |
4585 | ||
4586 | /* Reuse the last entry if it already has a matching %lo. */ | |
4587 | hi_fixup = mips_hi_fixup_list; | |
4588 | if (hi_fixup == 0 | |
4589 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4590 | { |
9fe77896 RS |
4591 | hi_fixup = ((struct mips_hi_fixup *) |
4592 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4593 | hi_fixup->next = mips_hi_fixup_list; | |
4594 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4595 | } |
9fe77896 RS |
4596 | hi_fixup->fixp = ip->fixp[0]; |
4597 | hi_fixup->seg = now_seg; | |
4598 | } | |
252b5132 | 4599 | |
9fe77896 RS |
4600 | /* Add fixups for the second and third relocations, if given. |
4601 | Note that the ABI allows the second relocation to be | |
4602 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4603 | moment we only use RSS_UNDEF, but we could add support | |
4604 | for the others if it ever becomes necessary. */ | |
4605 | for (i = 1; i < 3; i++) | |
4606 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4607 | { | |
4608 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4609 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4610 | FALSE, final_type[i]); |
f6688943 | 4611 | |
9fe77896 RS |
4612 | /* Use fx_tcbit to mark compound relocs. */ |
4613 | ip->fixp[0]->fx_tcbit = 1; | |
4614 | ip->fixp[i]->fx_tcbit = 1; | |
4615 | } | |
252b5132 | 4616 | } |
1e915849 | 4617 | install_insn (ip); |
252b5132 RH |
4618 | |
4619 | /* Update the register mask information. */ | |
4c260379 RS |
4620 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4621 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4622 | |
a4e06468 | 4623 | switch (method) |
252b5132 | 4624 | { |
a4e06468 RS |
4625 | case APPEND_ADD: |
4626 | insert_into_history (0, 1, ip); | |
4627 | break; | |
4628 | ||
4629 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4630 | { |
4631 | struct mips_cl_insn *nop; | |
4632 | ||
4633 | insert_into_history (0, 1, ip); | |
4634 | nop = get_delay_slot_nop (ip); | |
4635 | add_fixed_insn (nop); | |
4636 | insert_into_history (0, 1, nop); | |
4637 | if (mips_relax.sequence) | |
4638 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4639 | } | |
a4e06468 RS |
4640 | break; |
4641 | ||
4642 | case APPEND_ADD_COMPACT: | |
4643 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4644 | gas_assert (mips_opts.mips16); | |
4645 | ip->insn_opcode |= 0x0080; | |
4646 | find_altered_mips16_opcode (ip); | |
4647 | install_insn (ip); | |
4648 | insert_into_history (0, 1, ip); | |
4649 | break; | |
4650 | ||
4651 | case APPEND_SWAP: | |
4652 | { | |
4653 | struct mips_cl_insn delay = history[0]; | |
4654 | if (mips_opts.mips16) | |
4655 | { | |
4656 | know (delay.frag == ip->frag); | |
4657 | move_insn (ip, delay.frag, delay.where); | |
4658 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4659 | } | |
464ab0e5 | 4660 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4661 | { |
4662 | /* Add the delay slot instruction to the end of the | |
4663 | current frag and shrink the fixed part of the | |
4664 | original frag. If the branch occupies the tail of | |
4665 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4666 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4667 | if (delay.frag == ip->frag) |
2b0c8b40 | 4668 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4669 | add_fixed_insn (&delay); |
4670 | } | |
4671 | else | |
4672 | { | |
2b0c8b40 MR |
4673 | move_insn (&delay, ip->frag, |
4674 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4675 | move_insn (ip, history[0].frag, history[0].where); |
4676 | } | |
4677 | history[0] = *ip; | |
4678 | delay.fixed_p = 1; | |
4679 | insert_into_history (0, 1, &delay); | |
4680 | } | |
4681 | break; | |
252b5132 RH |
4682 | } |
4683 | ||
13408f1e | 4684 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4685 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4686 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4687 | { |
4688 | unsigned int i; | |
4689 | ||
79850f26 | 4690 | mips_no_prev_insn (); |
13408f1e | 4691 | |
e407c74b | 4692 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4693 | history[i].cleared_p = 1; |
e407c74b NC |
4694 | } |
4695 | ||
df58fc94 RS |
4696 | /* We need to emit a label at the end of branch-likely macros. */ |
4697 | if (emit_branch_likely_macro) | |
4698 | { | |
4699 | emit_branch_likely_macro = FALSE; | |
4700 | micromips_add_label (); | |
4701 | } | |
4702 | ||
252b5132 RH |
4703 | /* We just output an insn, so the next one doesn't have a label. */ |
4704 | mips_clear_insn_labels (); | |
252b5132 RH |
4705 | } |
4706 | ||
e407c74b NC |
4707 | /* Forget that there was any previous instruction or label. |
4708 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4709 | |
4710 | static void | |
7d10b47d | 4711 | mips_no_prev_insn (void) |
252b5132 | 4712 | { |
7d10b47d RS |
4713 | prev_nop_frag = NULL; |
4714 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4715 | mips_clear_insn_labels (); |
4716 | } | |
4717 | ||
7d10b47d RS |
4718 | /* This function must be called before we emit something other than |
4719 | instructions. It is like mips_no_prev_insn except that it inserts | |
4720 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4721 | |
7d10b47d RS |
4722 | void |
4723 | mips_emit_delays (void) | |
252b5132 RH |
4724 | { |
4725 | if (! mips_opts.noreorder) | |
4726 | { | |
932d1a1b | 4727 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4728 | if (nops > 0) |
4729 | { | |
7d10b47d RS |
4730 | while (nops-- > 0) |
4731 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4732 | mips_move_text_labels (); |
7d10b47d RS |
4733 | } |
4734 | } | |
4735 | mips_no_prev_insn (); | |
4736 | } | |
4737 | ||
4738 | /* Start a (possibly nested) noreorder block. */ | |
4739 | ||
4740 | static void | |
4741 | start_noreorder (void) | |
4742 | { | |
4743 | if (mips_opts.noreorder == 0) | |
4744 | { | |
4745 | unsigned int i; | |
4746 | int nops; | |
4747 | ||
4748 | /* None of the instructions before the .set noreorder can be moved. */ | |
4749 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4750 | history[i].fixed_p = 1; | |
4751 | ||
4752 | /* Insert any nops that might be needed between the .set noreorder | |
4753 | block and the previous instructions. We will later remove any | |
4754 | nops that turn out not to be needed. */ | |
932d1a1b | 4755 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4756 | if (nops > 0) |
4757 | { | |
4758 | if (mips_optimize != 0) | |
252b5132 RH |
4759 | { |
4760 | /* Record the frag which holds the nop instructions, so | |
4761 | that we can remove them if we don't need them. */ | |
df58fc94 | 4762 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4763 | prev_nop_frag = frag_now; |
4764 | prev_nop_frag_holds = nops; | |
4765 | prev_nop_frag_required = 0; | |
4766 | prev_nop_frag_since = 0; | |
4767 | } | |
4768 | ||
4769 | for (; nops > 0; --nops) | |
1e915849 | 4770 | add_fixed_insn (NOP_INSN); |
252b5132 | 4771 | |
7d10b47d RS |
4772 | /* Move on to a new frag, so that it is safe to simply |
4773 | decrease the size of prev_nop_frag. */ | |
4774 | frag_wane (frag_now); | |
4775 | frag_new (0); | |
462427c4 | 4776 | mips_move_text_labels (); |
252b5132 | 4777 | } |
df58fc94 | 4778 | mips_mark_labels (); |
7d10b47d | 4779 | mips_clear_insn_labels (); |
252b5132 | 4780 | } |
7d10b47d RS |
4781 | mips_opts.noreorder++; |
4782 | mips_any_noreorder = 1; | |
4783 | } | |
252b5132 | 4784 | |
7d10b47d | 4785 | /* End a nested noreorder block. */ |
252b5132 | 4786 | |
7d10b47d RS |
4787 | static void |
4788 | end_noreorder (void) | |
4789 | { | |
4790 | mips_opts.noreorder--; | |
4791 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4792 | { | |
4793 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4794 | handling nop insertion the .set reorder way. */ | |
4795 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4796 | * NOP_INSN_SIZE); |
7d10b47d RS |
4797 | insert_into_history (prev_nop_frag_since, |
4798 | prev_nop_frag_required, NOP_INSN); | |
4799 | prev_nop_frag = NULL; | |
4800 | } | |
252b5132 RH |
4801 | } |
4802 | ||
584892a6 RS |
4803 | /* Set up global variables for the start of a new macro. */ |
4804 | ||
4805 | static void | |
4806 | macro_start (void) | |
4807 | { | |
4808 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4809 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4810 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4811 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4812 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4813 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4814 | switch (history[0].insn_mo->pinfo2 |
4815 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4816 | { | |
4817 | case INSN2_BRANCH_DELAY_32BIT: | |
4818 | mips_macro_warning.delay_slot_length = 4; | |
4819 | break; | |
4820 | case INSN2_BRANCH_DELAY_16BIT: | |
4821 | mips_macro_warning.delay_slot_length = 2; | |
4822 | break; | |
4823 | default: | |
4824 | mips_macro_warning.delay_slot_length = 0; | |
4825 | break; | |
4826 | } | |
4827 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4828 | } |
4829 | ||
df58fc94 RS |
4830 | /* Given that a macro is longer than one instruction or of the wrong size, |
4831 | return the appropriate warning for it. Return null if no warning is | |
4832 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4833 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4834 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4835 | |
4836 | static const char * | |
4837 | macro_warning (relax_substateT subtype) | |
4838 | { | |
4839 | if (subtype & RELAX_DELAY_SLOT) | |
4840 | return _("Macro instruction expanded into multiple instructions" | |
4841 | " in a branch delay slot"); | |
4842 | else if (subtype & RELAX_NOMACRO) | |
4843 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4844 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4845 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4846 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4847 | ? _("Macro instruction expanded into a wrong size instruction" | |
4848 | " in a 16-bit branch delay slot") | |
4849 | : _("Macro instruction expanded into a wrong size instruction" | |
4850 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4851 | else |
4852 | return 0; | |
4853 | } | |
4854 | ||
4855 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4856 | ||
4857 | static void | |
4858 | macro_end (void) | |
4859 | { | |
df58fc94 RS |
4860 | /* Relaxation warning flags. */ |
4861 | relax_substateT subtype = 0; | |
4862 | ||
4863 | /* Check delay slot size requirements. */ | |
4864 | if (mips_macro_warning.delay_slot_length == 2) | |
4865 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4866 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4867 | { |
df58fc94 RS |
4868 | if (mips_macro_warning.delay_slot_length |
4869 | != mips_macro_warning.first_insn_sizes[0]) | |
4870 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4871 | if (mips_macro_warning.delay_slot_length | |
4872 | != mips_macro_warning.first_insn_sizes[1]) | |
4873 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4874 | } | |
584892a6 | 4875 | |
df58fc94 RS |
4876 | /* Check instruction count requirements. */ |
4877 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4878 | { | |
4879 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4880 | subtype |= RELAX_SECOND_LONGER; |
4881 | if (mips_opts.warn_about_macros) | |
4882 | subtype |= RELAX_NOMACRO; | |
4883 | if (mips_macro_warning.delay_slot_p) | |
4884 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4885 | } |
584892a6 | 4886 | |
df58fc94 RS |
4887 | /* If both alternatives fail to fill a delay slot correctly, |
4888 | emit the warning now. */ | |
4889 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4890 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4891 | { | |
4892 | relax_substateT s; | |
4893 | const char *msg; | |
4894 | ||
4895 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4896 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4897 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4898 | msg = macro_warning (s); | |
4899 | if (msg != NULL) | |
4900 | as_warn ("%s", msg); | |
4901 | subtype &= ~s; | |
4902 | } | |
4903 | ||
4904 | /* If both implementations are longer than 1 instruction, then emit the | |
4905 | warning now. */ | |
4906 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4907 | { | |
4908 | relax_substateT s; | |
4909 | const char *msg; | |
4910 | ||
4911 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4912 | msg = macro_warning (s); | |
4913 | if (msg != NULL) | |
4914 | as_warn ("%s", msg); | |
4915 | subtype &= ~s; | |
584892a6 | 4916 | } |
df58fc94 RS |
4917 | |
4918 | /* If any flags still set, then one implementation might need a warning | |
4919 | and the other either will need one of a different kind or none at all. | |
4920 | Pass any remaining flags over to relaxation. */ | |
4921 | if (mips_macro_warning.first_frag != NULL) | |
4922 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4923 | } |
4924 | ||
df58fc94 RS |
4925 | /* Instruction operand formats used in macros that vary between |
4926 | standard MIPS and microMIPS code. */ | |
4927 | ||
4928 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4929 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4930 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4931 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4932 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4933 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4934 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4935 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4936 | ||
4937 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4938 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4939 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4940 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4941 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4942 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4943 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4944 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4945 | ||
6e1304d8 RS |
4946 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4947 | The first argument in *ARGS will be either the code for a single | |
4948 | relocation or -1 followed by the three codes that make up a | |
4949 | composite relocation. */ | |
4950 | ||
4951 | static void | |
4952 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4953 | { | |
4954 | int i, next; | |
4955 | ||
4956 | next = va_arg (*args, int); | |
4957 | if (next >= 0) | |
4958 | r[0] = (bfd_reloc_code_real_type) next; | |
4959 | else | |
4960 | for (i = 0; i < 3; i++) | |
4961 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4962 | } | |
4963 | ||
252b5132 RH |
4964 | /* Build an instruction created by a macro expansion. This is passed |
4965 | a pointer to the count of instructions created so far, an | |
4966 | expression, the name of the instruction to build, an operand format | |
4967 | string, and corresponding arguments. */ | |
4968 | ||
252b5132 | 4969 | static void |
67c0d1eb | 4970 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4971 | { |
df58fc94 | 4972 | const struct mips_opcode *mo = NULL; |
f6688943 | 4973 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4974 | const struct mips_opcode *amo; |
4975 | struct hash_control *hash; | |
4976 | struct mips_cl_insn insn; | |
252b5132 | 4977 | va_list args; |
252b5132 | 4978 | |
252b5132 | 4979 | va_start (args, fmt); |
252b5132 | 4980 | |
252b5132 RH |
4981 | if (mips_opts.mips16) |
4982 | { | |
03ea81db | 4983 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4984 | va_end (args); |
4985 | return; | |
4986 | } | |
4987 | ||
f6688943 TS |
4988 | r[0] = BFD_RELOC_UNUSED; |
4989 | r[1] = BFD_RELOC_UNUSED; | |
4990 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4991 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4992 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4993 | gas_assert (amo); | |
4994 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4995 | |
df58fc94 | 4996 | do |
8b082fb1 TS |
4997 | { |
4998 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4999 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5000 | We try to match an instruction that fulfils the branch delay | |
5001 | slot instruction length requirement (if any) of the previous | |
5002 | instruction. While doing this we record the first instruction | |
5003 | seen that matches all the other conditions and use it anyway | |
5004 | if the requirement cannot be met; we will issue an appropriate | |
5005 | warning later on. */ | |
5006 | if (strcmp (fmt, amo->args) == 0 | |
5007 | && amo->pinfo != INSN_MACRO | |
5008 | && is_opcode_valid (amo) | |
5009 | && is_size_valid (amo)) | |
5010 | { | |
5011 | if (is_delay_slot_valid (amo)) | |
5012 | { | |
5013 | mo = amo; | |
5014 | break; | |
5015 | } | |
5016 | else if (!mo) | |
5017 | mo = amo; | |
5018 | } | |
8b082fb1 | 5019 | |
df58fc94 RS |
5020 | ++amo; |
5021 | gas_assert (amo->name); | |
252b5132 | 5022 | } |
df58fc94 | 5023 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5024 | |
df58fc94 | 5025 | gas_assert (mo); |
1e915849 | 5026 | create_insn (&insn, mo); |
252b5132 RH |
5027 | for (;;) |
5028 | { | |
5029 | switch (*fmt++) | |
5030 | { | |
5031 | case '\0': | |
5032 | break; | |
5033 | ||
5034 | case ',': | |
5035 | case '(': | |
5036 | case ')': | |
5037 | continue; | |
5038 | ||
5f74bc13 CD |
5039 | case '+': |
5040 | switch (*fmt++) | |
5041 | { | |
5042 | case 'A': | |
5043 | case 'E': | |
df58fc94 RS |
5044 | INSERT_OPERAND (mips_opts.micromips, |
5045 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5046 | continue; |
5047 | ||
5048 | case 'B': | |
5049 | case 'F': | |
5050 | /* Note that in the macro case, these arguments are already | |
5051 | in MSB form. (When handling the instruction in the | |
5052 | non-macro case, these arguments are sizes from which | |
5053 | MSB values must be calculated.) */ | |
df58fc94 RS |
5054 | INSERT_OPERAND (mips_opts.micromips, |
5055 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5056 | continue; |
5057 | ||
b015e599 AP |
5058 | case 'J': |
5059 | gas_assert (!mips_opts.micromips); | |
5060 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5061 | continue; | |
5062 | ||
5f74bc13 CD |
5063 | case 'C': |
5064 | case 'G': | |
5065 | case 'H': | |
5066 | /* Note that in the macro case, these arguments are already | |
5067 | in MSBD form. (When handling the instruction in the | |
5068 | non-macro case, these arguments are sizes from which | |
5069 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5070 | INSERT_OPERAND (mips_opts.micromips, |
5071 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5072 | continue; |
5073 | ||
dd3cbb7e | 5074 | case 'Q': |
df58fc94 RS |
5075 | gas_assert (!mips_opts.micromips); |
5076 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5077 | continue; |
5078 | ||
5f74bc13 | 5079 | default: |
b37df7c4 | 5080 | abort (); |
5f74bc13 CD |
5081 | } |
5082 | continue; | |
5083 | ||
8b082fb1 | 5084 | case '2': |
03f66e8a | 5085 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5086 | continue; |
5087 | ||
df58fc94 RS |
5088 | case 'n': |
5089 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5090 | case 't': |
5091 | case 'w': | |
5092 | case 'E': | |
df58fc94 | 5093 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5094 | continue; |
5095 | ||
5096 | case 'c': | |
df58fc94 RS |
5097 | gas_assert (!mips_opts.micromips); |
5098 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5099 | continue; |
5100 | ||
252b5132 | 5101 | case 'W': |
df58fc94 RS |
5102 | gas_assert (!mips_opts.micromips); |
5103 | case 'T': | |
5104 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5105 | continue; |
5106 | ||
252b5132 | 5107 | case 'G': |
df58fc94 RS |
5108 | if (mips_opts.micromips) |
5109 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5110 | else | |
5111 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5112 | continue; | |
5113 | ||
af7ee8bf | 5114 | case 'K': |
df58fc94 RS |
5115 | gas_assert (!mips_opts.micromips); |
5116 | case 'd': | |
5117 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5118 | continue; |
5119 | ||
4372b673 | 5120 | case 'U': |
df58fc94 | 5121 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5122 | { |
5123 | int tmp = va_arg (args, int); | |
5124 | ||
df58fc94 RS |
5125 | INSERT_OPERAND (0, RT, insn, tmp); |
5126 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5127 | } |
df58fc94 | 5128 | continue; |
4372b673 | 5129 | |
252b5132 RH |
5130 | case 'V': |
5131 | case 'S': | |
df58fc94 RS |
5132 | gas_assert (!mips_opts.micromips); |
5133 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5134 | continue; |
5135 | ||
5136 | case 'z': | |
5137 | continue; | |
5138 | ||
5139 | case '<': | |
df58fc94 RS |
5140 | INSERT_OPERAND (mips_opts.micromips, |
5141 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5142 | continue; |
5143 | ||
5144 | case 'D': | |
df58fc94 RS |
5145 | gas_assert (!mips_opts.micromips); |
5146 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5147 | continue; |
5148 | ||
5149 | case 'B': | |
df58fc94 RS |
5150 | gas_assert (!mips_opts.micromips); |
5151 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5152 | continue; |
5153 | ||
4372b673 | 5154 | case 'J': |
df58fc94 RS |
5155 | gas_assert (!mips_opts.micromips); |
5156 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5157 | continue; |
5158 | ||
252b5132 | 5159 | case 'q': |
df58fc94 RS |
5160 | gas_assert (!mips_opts.micromips); |
5161 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5162 | continue; |
5163 | ||
5164 | case 'b': | |
5165 | case 's': | |
5166 | case 'r': | |
5167 | case 'v': | |
df58fc94 | 5168 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5169 | continue; |
5170 | ||
5171 | case 'i': | |
5172 | case 'j': | |
6e1304d8 | 5173 | macro_read_relocs (&args, r); |
9c2799c2 | 5174 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5175 | || *r == BFD_RELOC_MIPS_HIGHER |
5176 | || *r == BFD_RELOC_HI16_S | |
5177 | || *r == BFD_RELOC_LO16 | |
5178 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5179 | continue; | |
5180 | ||
5181 | case 'o': | |
5182 | macro_read_relocs (&args, r); | |
252b5132 RH |
5183 | continue; |
5184 | ||
5185 | case 'u': | |
6e1304d8 | 5186 | macro_read_relocs (&args, r); |
9c2799c2 | 5187 | gas_assert (ep != NULL |
90ecf173 MR |
5188 | && (ep->X_op == O_constant |
5189 | || (ep->X_op == O_symbol | |
5190 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5191 | || *r == BFD_RELOC_HI16_S | |
5192 | || *r == BFD_RELOC_HI16 | |
5193 | || *r == BFD_RELOC_GPREL16 | |
5194 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5195 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5196 | continue; |
5197 | ||
5198 | case 'p': | |
9c2799c2 | 5199 | gas_assert (ep != NULL); |
bad36eac | 5200 | |
252b5132 RH |
5201 | /* |
5202 | * This allows macro() to pass an immediate expression for | |
5203 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5204 | * |
5205 | * We don't allow branch relaxation for these branches, as | |
5206 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5207 | */ |
5208 | if (ep->X_op == O_constant) | |
5209 | { | |
df58fc94 RS |
5210 | /* For microMIPS we always use relocations for branches. |
5211 | So we should not resolve immediate values. */ | |
5212 | gas_assert (!mips_opts.micromips); | |
5213 | ||
bad36eac DJ |
5214 | if ((ep->X_add_number & 3) != 0) |
5215 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5216 | (unsigned long) ep->X_add_number); | |
5217 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5218 | as_bad (_("branch address range overflow (0x%lx)"), | |
5219 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5220 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5221 | ep = NULL; | |
5222 | } | |
5223 | else | |
0b25d3e6 | 5224 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5225 | continue; |
5226 | ||
5227 | case 'a': | |
9c2799c2 | 5228 | gas_assert (ep != NULL); |
f6688943 | 5229 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5230 | continue; |
5231 | ||
5232 | case 'C': | |
df58fc94 RS |
5233 | gas_assert (!mips_opts.micromips); |
5234 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5235 | continue; |
5236 | ||
d43b4baf | 5237 | case 'k': |
df58fc94 RS |
5238 | INSERT_OPERAND (mips_opts.micromips, |
5239 | CACHE, insn, va_arg (args, unsigned long)); | |
5240 | continue; | |
5241 | ||
5242 | case '|': | |
5243 | gas_assert (mips_opts.micromips); | |
5244 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5245 | continue; | |
5246 | ||
5247 | case '.': | |
5248 | gas_assert (mips_opts.micromips); | |
5249 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5250 | continue; | |
5251 | ||
dec0624d MR |
5252 | case '\\': |
5253 | INSERT_OPERAND (mips_opts.micromips, | |
5254 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5255 | continue; | |
5256 | ||
df58fc94 | 5257 | case '~': |
dec0624d MR |
5258 | INSERT_OPERAND (mips_opts.micromips, |
5259 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5260 | continue; |
5261 | ||
5262 | case 'N': | |
5263 | gas_assert (mips_opts.micromips); | |
5264 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5265 | continue; | |
5266 | ||
5267 | case 'm': /* Opcode extension character. */ | |
5268 | gas_assert (mips_opts.micromips); | |
5269 | switch (*fmt++) | |
5270 | { | |
5271 | case 'j': | |
5272 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5273 | break; | |
5274 | ||
5275 | case 'p': | |
5276 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5277 | break; | |
5278 | ||
5279 | case 'F': | |
5280 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5281 | break; | |
5282 | ||
5283 | default: | |
b37df7c4 | 5284 | abort (); |
df58fc94 | 5285 | } |
d43b4baf TS |
5286 | continue; |
5287 | ||
252b5132 | 5288 | default: |
b37df7c4 | 5289 | abort (); |
252b5132 RH |
5290 | } |
5291 | break; | |
5292 | } | |
5293 | va_end (args); | |
9c2799c2 | 5294 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5295 | |
df58fc94 | 5296 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5297 | } |
5298 | ||
5299 | static void | |
67c0d1eb | 5300 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5301 | va_list *args) |
252b5132 | 5302 | { |
1e915849 | 5303 | struct mips_opcode *mo; |
252b5132 | 5304 | struct mips_cl_insn insn; |
f6688943 TS |
5305 | bfd_reloc_code_real_type r[3] |
5306 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5307 | |
1e915849 | 5308 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5309 | gas_assert (mo); |
5310 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5311 | |
1e915849 | 5312 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5313 | { |
1e915849 | 5314 | ++mo; |
9c2799c2 NC |
5315 | gas_assert (mo->name); |
5316 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5317 | } |
5318 | ||
1e915849 | 5319 | create_insn (&insn, mo); |
252b5132 RH |
5320 | for (;;) |
5321 | { | |
5322 | int c; | |
5323 | ||
5324 | c = *fmt++; | |
5325 | switch (c) | |
5326 | { | |
5327 | case '\0': | |
5328 | break; | |
5329 | ||
5330 | case ',': | |
5331 | case '(': | |
5332 | case ')': | |
5333 | continue; | |
5334 | ||
5335 | case 'y': | |
5336 | case 'w': | |
03ea81db | 5337 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5338 | continue; |
5339 | ||
5340 | case 'x': | |
5341 | case 'v': | |
03ea81db | 5342 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5343 | continue; |
5344 | ||
5345 | case 'z': | |
03ea81db | 5346 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5347 | continue; |
5348 | ||
5349 | case 'Z': | |
03ea81db | 5350 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5351 | continue; |
5352 | ||
5353 | case '0': | |
5354 | case 'S': | |
5355 | case 'P': | |
5356 | case 'R': | |
5357 | continue; | |
5358 | ||
5359 | case 'X': | |
03ea81db | 5360 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5361 | continue; |
5362 | ||
5363 | case 'Y': | |
5364 | { | |
5365 | int regno; | |
5366 | ||
03ea81db | 5367 | regno = va_arg (*args, int); |
252b5132 | 5368 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5369 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5370 | } |
5371 | continue; | |
5372 | ||
5373 | case '<': | |
5374 | case '>': | |
5375 | case '4': | |
5376 | case '5': | |
5377 | case 'H': | |
5378 | case 'W': | |
5379 | case 'D': | |
5380 | case 'j': | |
5381 | case '8': | |
5382 | case 'V': | |
5383 | case 'C': | |
5384 | case 'U': | |
5385 | case 'k': | |
5386 | case 'K': | |
5387 | case 'p': | |
5388 | case 'q': | |
5389 | { | |
b886a2ab RS |
5390 | offsetT value; |
5391 | ||
9c2799c2 | 5392 | gas_assert (ep != NULL); |
252b5132 RH |
5393 | |
5394 | if (ep->X_op != O_constant) | |
874e8986 | 5395 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5396 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5397 | { |
b886a2ab | 5398 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5399 | ep = NULL; |
f6688943 | 5400 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5401 | } |
5402 | } | |
5403 | continue; | |
5404 | ||
5405 | case '6': | |
03ea81db | 5406 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5407 | continue; |
5408 | } | |
5409 | ||
5410 | break; | |
5411 | } | |
5412 | ||
9c2799c2 | 5413 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5414 | |
df58fc94 | 5415 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5416 | } |
5417 | ||
2051e8c4 MR |
5418 | /* |
5419 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5420 | * higher bits unset. | |
5421 | */ | |
9f872bbe | 5422 | static void |
2051e8c4 MR |
5423 | normalize_constant_expr (expressionS *ex) |
5424 | { | |
9ee2a2d4 | 5425 | if (ex->X_op == O_constant |
2051e8c4 MR |
5426 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5427 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5428 | - 0x80000000); | |
5429 | } | |
5430 | ||
5431 | /* | |
5432 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5433 | * all higher bits unset. | |
5434 | */ | |
5435 | static void | |
5436 | normalize_address_expr (expressionS *ex) | |
5437 | { | |
5438 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5439 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5440 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5441 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5442 | - 0x80000000); | |
5443 | } | |
5444 | ||
438c16b8 TS |
5445 | /* |
5446 | * Generate a "jalr" instruction with a relocation hint to the called | |
5447 | * function. This occurs in NewABI PIC code. | |
5448 | */ | |
5449 | static void | |
df58fc94 | 5450 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5451 | { |
df58fc94 RS |
5452 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5453 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5454 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5455 | const char *jalr; | |
685736be | 5456 | char *f = NULL; |
b34976b6 | 5457 | |
1180b5a4 | 5458 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5459 | { |
cc3d92a5 | 5460 | frag_grow (8); |
f21f8242 AO |
5461 | f = frag_more (0); |
5462 | } | |
2906b037 | 5463 | if (mips_opts.micromips) |
df58fc94 RS |
5464 | { |
5465 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5466 | if (MIPS_JALR_HINT_P (ep) |
5467 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5468 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5469 | else | |
5470 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5471 | } | |
2906b037 MR |
5472 | else |
5473 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5474 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5475 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5476 | } |
5477 | ||
252b5132 RH |
5478 | /* |
5479 | * Generate a "lui" instruction. | |
5480 | */ | |
5481 | static void | |
67c0d1eb | 5482 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5483 | { |
9c2799c2 | 5484 | gas_assert (! mips_opts.mips16); |
252b5132 | 5485 | |
df58fc94 | 5486 | if (ep->X_op != O_constant) |
252b5132 | 5487 | { |
9c2799c2 | 5488 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5489 | /* _gp_disp is a special case, used from s_cpload. |
5490 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5491 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5492 | || (! HAVE_NEWABI |
aa6975fb ILT |
5493 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5494 | || (! mips_in_shared | |
bbe506e8 TS |
5495 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5496 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5497 | } |
5498 | ||
df58fc94 | 5499 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5500 | } |
5501 | ||
885add95 CD |
5502 | /* Generate a sequence of instructions to do a load or store from a constant |
5503 | offset off of a base register (breg) into/from a target register (treg), | |
5504 | using AT if necessary. */ | |
5505 | static void | |
67c0d1eb RS |
5506 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5507 | int treg, int breg, int dbl) | |
885add95 | 5508 | { |
9c2799c2 | 5509 | gas_assert (ep->X_op == O_constant); |
885add95 | 5510 | |
256ab948 | 5511 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5512 | if (!dbl) |
5513 | normalize_constant_expr (ep); | |
256ab948 | 5514 | |
67c1ffbe | 5515 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5516 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5517 | as_warn (_("operand overflow")); |
5518 | ||
5519 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5520 | { | |
5521 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5522 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5523 | } |
5524 | else | |
5525 | { | |
5526 | /* 32-bit offset, need multiple instructions and AT, like: | |
5527 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5528 | addu $tempreg,$tempreg,$breg | |
5529 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5530 | to handle the complete offset. */ | |
67c0d1eb RS |
5531 | macro_build_lui (ep, AT); |
5532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5533 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5534 | |
741fe287 | 5535 | if (!mips_opts.at) |
8fc2e39e | 5536 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5537 | } |
5538 | } | |
5539 | ||
252b5132 RH |
5540 | /* set_at() |
5541 | * Generates code to set the $at register to true (one) | |
5542 | * if reg is less than the immediate expression. | |
5543 | */ | |
5544 | static void | |
67c0d1eb | 5545 | set_at (int reg, int unsignedp) |
252b5132 RH |
5546 | { |
5547 | if (imm_expr.X_op == O_constant | |
5548 | && imm_expr.X_add_number >= -0x8000 | |
5549 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5550 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5551 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5552 | else |
5553 | { | |
67c0d1eb RS |
5554 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5555 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5556 | } |
5557 | } | |
5558 | ||
5559 | /* Warn if an expression is not a constant. */ | |
5560 | ||
5561 | static void | |
17a2f251 | 5562 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5563 | { |
5564 | if (ex->X_op == O_big) | |
5565 | as_bad (_("unsupported large constant")); | |
5566 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5567 | as_bad (_("Instruction %s requires absolute expression"), |
5568 | ip->insn_mo->name); | |
13757d0c | 5569 | |
9ee2a2d4 MR |
5570 | if (HAVE_32BIT_GPRS) |
5571 | normalize_constant_expr (ex); | |
252b5132 RH |
5572 | } |
5573 | ||
5574 | /* Count the leading zeroes by performing a binary chop. This is a | |
5575 | bulky bit of source, but performance is a LOT better for the | |
5576 | majority of values than a simple loop to count the bits: | |
5577 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5578 | if ((v) & (1 << (31 - lcnt))) | |
5579 | break; | |
5580 | However it is not code size friendly, and the gain will drop a bit | |
5581 | on certain cached systems. | |
5582 | */ | |
5583 | #define COUNT_TOP_ZEROES(v) \ | |
5584 | (((v) & ~0xffff) == 0 \ | |
5585 | ? ((v) & ~0xff) == 0 \ | |
5586 | ? ((v) & ~0xf) == 0 \ | |
5587 | ? ((v) & ~0x3) == 0 \ | |
5588 | ? ((v) & ~0x1) == 0 \ | |
5589 | ? !(v) \ | |
5590 | ? 32 \ | |
5591 | : 31 \ | |
5592 | : 30 \ | |
5593 | : ((v) & ~0x7) == 0 \ | |
5594 | ? 29 \ | |
5595 | : 28 \ | |
5596 | : ((v) & ~0x3f) == 0 \ | |
5597 | ? ((v) & ~0x1f) == 0 \ | |
5598 | ? 27 \ | |
5599 | : 26 \ | |
5600 | : ((v) & ~0x7f) == 0 \ | |
5601 | ? 25 \ | |
5602 | : 24 \ | |
5603 | : ((v) & ~0xfff) == 0 \ | |
5604 | ? ((v) & ~0x3ff) == 0 \ | |
5605 | ? ((v) & ~0x1ff) == 0 \ | |
5606 | ? 23 \ | |
5607 | : 22 \ | |
5608 | : ((v) & ~0x7ff) == 0 \ | |
5609 | ? 21 \ | |
5610 | : 20 \ | |
5611 | : ((v) & ~0x3fff) == 0 \ | |
5612 | ? ((v) & ~0x1fff) == 0 \ | |
5613 | ? 19 \ | |
5614 | : 18 \ | |
5615 | : ((v) & ~0x7fff) == 0 \ | |
5616 | ? 17 \ | |
5617 | : 16 \ | |
5618 | : ((v) & ~0xffffff) == 0 \ | |
5619 | ? ((v) & ~0xfffff) == 0 \ | |
5620 | ? ((v) & ~0x3ffff) == 0 \ | |
5621 | ? ((v) & ~0x1ffff) == 0 \ | |
5622 | ? 15 \ | |
5623 | : 14 \ | |
5624 | : ((v) & ~0x7ffff) == 0 \ | |
5625 | ? 13 \ | |
5626 | : 12 \ | |
5627 | : ((v) & ~0x3fffff) == 0 \ | |
5628 | ? ((v) & ~0x1fffff) == 0 \ | |
5629 | ? 11 \ | |
5630 | : 10 \ | |
5631 | : ((v) & ~0x7fffff) == 0 \ | |
5632 | ? 9 \ | |
5633 | : 8 \ | |
5634 | : ((v) & ~0xfffffff) == 0 \ | |
5635 | ? ((v) & ~0x3ffffff) == 0 \ | |
5636 | ? ((v) & ~0x1ffffff) == 0 \ | |
5637 | ? 7 \ | |
5638 | : 6 \ | |
5639 | : ((v) & ~0x7ffffff) == 0 \ | |
5640 | ? 5 \ | |
5641 | : 4 \ | |
5642 | : ((v) & ~0x3fffffff) == 0 \ | |
5643 | ? ((v) & ~0x1fffffff) == 0 \ | |
5644 | ? 3 \ | |
5645 | : 2 \ | |
5646 | : ((v) & ~0x7fffffff) == 0 \ | |
5647 | ? 1 \ | |
5648 | : 0) | |
5649 | ||
5650 | /* load_register() | |
67c1ffbe | 5651 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5652 | * an absolute expression value into a register. |
5653 | */ | |
5654 | static void | |
67c0d1eb | 5655 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5656 | { |
5657 | int freg; | |
5658 | expressionS hi32, lo32; | |
5659 | ||
5660 | if (ep->X_op != O_big) | |
5661 | { | |
9c2799c2 | 5662 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5663 | |
5664 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5665 | if (!dbl) |
5666 | normalize_constant_expr (ep); | |
256ab948 TS |
5667 | |
5668 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5669 | { |
5670 | /* We can handle 16 bit signed values with an addiu to | |
5671 | $zero. No need to ever use daddiu here, since $zero and | |
5672 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5673 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5674 | return; |
5675 | } | |
5676 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5677 | { | |
5678 | /* We can handle 16 bit unsigned values with an ori to | |
5679 | $zero. */ | |
67c0d1eb | 5680 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5681 | return; |
5682 | } | |
256ab948 | 5683 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5684 | { |
5685 | /* 32 bit values require an lui. */ | |
df58fc94 | 5686 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5687 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5688 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5689 | return; |
5690 | } | |
5691 | } | |
5692 | ||
5693 | /* The value is larger than 32 bits. */ | |
5694 | ||
2051e8c4 | 5695 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5696 | { |
55e08f71 NC |
5697 | char value[32]; |
5698 | ||
5699 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5700 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5701 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5702 | return; |
5703 | } | |
5704 | ||
5705 | if (ep->X_op != O_big) | |
5706 | { | |
5707 | hi32 = *ep; | |
5708 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5709 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5710 | hi32.X_add_number &= 0xffffffff; | |
5711 | lo32 = *ep; | |
5712 | lo32.X_add_number &= 0xffffffff; | |
5713 | } | |
5714 | else | |
5715 | { | |
9c2799c2 | 5716 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5717 | if (ep->X_add_number == 3) |
5718 | generic_bignum[3] = 0; | |
5719 | else if (ep->X_add_number > 4) | |
5720 | as_bad (_("Number larger than 64 bits")); | |
5721 | lo32.X_op = O_constant; | |
5722 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5723 | hi32.X_op = O_constant; | |
5724 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5725 | } | |
5726 | ||
5727 | if (hi32.X_add_number == 0) | |
5728 | freg = 0; | |
5729 | else | |
5730 | { | |
5731 | int shift, bit; | |
5732 | unsigned long hi, lo; | |
5733 | ||
956cd1d6 | 5734 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5735 | { |
5736 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5737 | { | |
67c0d1eb | 5738 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5739 | return; |
5740 | } | |
5741 | if (lo32.X_add_number & 0x80000000) | |
5742 | { | |
df58fc94 | 5743 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5744 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5745 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5746 | return; |
5747 | } | |
5748 | } | |
252b5132 RH |
5749 | |
5750 | /* Check for 16bit shifted constant. We know that hi32 is | |
5751 | non-zero, so start the mask on the first bit of the hi32 | |
5752 | value. */ | |
5753 | shift = 17; | |
5754 | do | |
beae10d5 KH |
5755 | { |
5756 | unsigned long himask, lomask; | |
5757 | ||
5758 | if (shift < 32) | |
5759 | { | |
5760 | himask = 0xffff >> (32 - shift); | |
5761 | lomask = (0xffff << shift) & 0xffffffff; | |
5762 | } | |
5763 | else | |
5764 | { | |
5765 | himask = 0xffff << (shift - 32); | |
5766 | lomask = 0; | |
5767 | } | |
5768 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5769 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5770 | { | |
5771 | expressionS tmp; | |
5772 | ||
5773 | tmp.X_op = O_constant; | |
5774 | if (shift < 32) | |
5775 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5776 | | (lo32.X_add_number >> shift)); | |
5777 | else | |
5778 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5779 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5780 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5781 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5782 | return; |
5783 | } | |
f9419b05 | 5784 | ++shift; |
beae10d5 KH |
5785 | } |
5786 | while (shift <= (64 - 16)); | |
252b5132 RH |
5787 | |
5788 | /* Find the bit number of the lowest one bit, and store the | |
5789 | shifted value in hi/lo. */ | |
5790 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5791 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5792 | if (lo != 0) | |
5793 | { | |
5794 | bit = 0; | |
5795 | while ((lo & 1) == 0) | |
5796 | { | |
5797 | lo >>= 1; | |
5798 | ++bit; | |
5799 | } | |
5800 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5801 | hi >>= bit; | |
5802 | } | |
5803 | else | |
5804 | { | |
5805 | bit = 32; | |
5806 | while ((hi & 1) == 0) | |
5807 | { | |
5808 | hi >>= 1; | |
5809 | ++bit; | |
5810 | } | |
5811 | lo = hi; | |
5812 | hi = 0; | |
5813 | } | |
5814 | ||
5815 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5816 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5817 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5818 | { |
5819 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5820 | if (shift != 0) |
beae10d5 | 5821 | { |
252b5132 RH |
5822 | expressionS tmp; |
5823 | ||
5824 | /* This instruction will set the register to be all | |
5825 | ones. */ | |
beae10d5 KH |
5826 | tmp.X_op = O_constant; |
5827 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5828 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5829 | if (bit != 0) |
5830 | { | |
5831 | bit += shift; | |
df58fc94 | 5832 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5833 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5834 | } |
df58fc94 | 5835 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5836 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5837 | return; |
5838 | } | |
5839 | } | |
252b5132 RH |
5840 | |
5841 | /* Sign extend hi32 before calling load_register, because we can | |
5842 | generally get better code when we load a sign extended value. */ | |
5843 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5844 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5845 | load_register (reg, &hi32, 0); |
252b5132 RH |
5846 | freg = reg; |
5847 | } | |
5848 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5849 | { | |
5850 | if (freg != 0) | |
5851 | { | |
df58fc94 | 5852 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5853 | freg = reg; |
5854 | } | |
5855 | } | |
5856 | else | |
5857 | { | |
5858 | expressionS mid16; | |
5859 | ||
956cd1d6 | 5860 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5861 | { |
df58fc94 RS |
5862 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5863 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5864 | return; |
5865 | } | |
252b5132 RH |
5866 | |
5867 | if (freg != 0) | |
5868 | { | |
df58fc94 | 5869 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5870 | freg = reg; |
5871 | } | |
5872 | mid16 = lo32; | |
5873 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5874 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5875 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5876 | freg = reg; |
5877 | } | |
5878 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5879 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5880 | } |
5881 | ||
269137b2 TS |
5882 | static inline void |
5883 | load_delay_nop (void) | |
5884 | { | |
5885 | if (!gpr_interlocks) | |
5886 | macro_build (NULL, "nop", ""); | |
5887 | } | |
5888 | ||
252b5132 RH |
5889 | /* Load an address into a register. */ |
5890 | ||
5891 | static void | |
67c0d1eb | 5892 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5893 | { |
252b5132 RH |
5894 | if (ep->X_op != O_constant |
5895 | && ep->X_op != O_symbol) | |
5896 | { | |
5897 | as_bad (_("expression too complex")); | |
5898 | ep->X_op = O_constant; | |
5899 | } | |
5900 | ||
5901 | if (ep->X_op == O_constant) | |
5902 | { | |
67c0d1eb | 5903 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5904 | return; |
5905 | } | |
5906 | ||
5907 | if (mips_pic == NO_PIC) | |
5908 | { | |
5909 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5910 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5911 | Otherwise we want |
5912 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5913 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5914 | If we have an addend, we always use the latter form. |
76b3015f | 5915 | |
d6bc6245 TS |
5916 | With 64bit address space and a usable $at we want |
5917 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5918 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5919 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5920 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5921 | dsll32 $reg,0 | |
3a482fd5 | 5922 | daddu $reg,$reg,$at |
76b3015f | 5923 | |
c03099e6 | 5924 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5925 | on superscalar processors. |
5926 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5927 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5928 | dsll $reg,16 | |
5929 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5930 | dsll $reg,16 | |
5931 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5932 | |
5933 | For GP relative symbols in 64bit address space we can use | |
5934 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5935 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5936 | { |
6caf9ef4 TS |
5937 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5938 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5939 | { | |
5940 | relax_start (ep->X_add_symbol); | |
5941 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5942 | mips_gp_register, BFD_RELOC_GPREL16); | |
5943 | relax_switch (); | |
5944 | } | |
d6bc6245 | 5945 | |
741fe287 | 5946 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5947 | { |
df58fc94 RS |
5948 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5949 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5950 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5951 | BFD_RELOC_MIPS_HIGHER); | |
5952 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5953 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5954 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5955 | *used_at = 1; |
5956 | } | |
5957 | else | |
5958 | { | |
df58fc94 | 5959 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5960 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5961 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5962 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5963 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5964 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5965 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5966 | } |
6caf9ef4 TS |
5967 | |
5968 | if (mips_relax.sequence) | |
5969 | relax_end (); | |
d6bc6245 | 5970 | } |
252b5132 RH |
5971 | else |
5972 | { | |
d6bc6245 | 5973 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5974 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5975 | { |
4d7206a2 | 5976 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5977 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5978 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5979 | relax_switch (); |
d6bc6245 | 5980 | } |
67c0d1eb RS |
5981 | macro_build_lui (ep, reg); |
5982 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5983 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5984 | if (mips_relax.sequence) |
5985 | relax_end (); | |
d6bc6245 | 5986 | } |
252b5132 | 5987 | } |
0a44bf69 | 5988 | else if (!mips_big_got) |
252b5132 RH |
5989 | { |
5990 | expressionS ex; | |
5991 | ||
5992 | /* If this is a reference to an external symbol, we want | |
5993 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5994 | Otherwise we want | |
5995 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5996 | nop | |
5997 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5998 | If there is a constant, it must be added in after. |
5999 | ||
ed6fb7bd | 6000 | If we have NewABI, we want |
f5040a92 AO |
6001 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6002 | unless we're referencing a global symbol with a non-zero | |
6003 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6004 | if (HAVE_NEWABI) |
6005 | { | |
f5040a92 AO |
6006 | if (ep->X_add_number) |
6007 | { | |
4d7206a2 | 6008 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6009 | ep->X_add_number = 0; |
4d7206a2 | 6010 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6011 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6012 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6013 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6014 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6015 | ex.X_op = O_constant; | |
67c0d1eb | 6016 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6017 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6018 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6019 | relax_switch (); |
f5040a92 | 6020 | } |
67c0d1eb | 6021 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6022 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6023 | if (mips_relax.sequence) |
6024 | relax_end (); | |
ed6fb7bd SC |
6025 | } |
6026 | else | |
6027 | { | |
f5040a92 AO |
6028 | ex.X_add_number = ep->X_add_number; |
6029 | ep->X_add_number = 0; | |
67c0d1eb RS |
6030 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6031 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6032 | load_delay_nop (); |
4d7206a2 RS |
6033 | relax_start (ep->X_add_symbol); |
6034 | relax_switch (); | |
67c0d1eb | 6035 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6036 | BFD_RELOC_LO16); |
4d7206a2 | 6037 | relax_end (); |
ed6fb7bd | 6038 | |
f5040a92 AO |
6039 | if (ex.X_add_number != 0) |
6040 | { | |
6041 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6042 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6043 | ex.X_op = O_constant; | |
67c0d1eb | 6044 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6045 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6046 | } |
252b5132 RH |
6047 | } |
6048 | } | |
0a44bf69 | 6049 | else if (mips_big_got) |
252b5132 RH |
6050 | { |
6051 | expressionS ex; | |
252b5132 RH |
6052 | |
6053 | /* This is the large GOT case. If this is a reference to an | |
6054 | external symbol, we want | |
6055 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6056 | addu $reg,$reg,$gp | |
6057 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6058 | |
6059 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6060 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6061 | nop | |
6062 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6063 | If there is a constant, it must be added in after. |
f5040a92 AO |
6064 | |
6065 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6066 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6067 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6068 | */ |
438c16b8 TS |
6069 | if (HAVE_NEWABI) |
6070 | { | |
4d7206a2 | 6071 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6072 | ep->X_add_number = 0; |
4d7206a2 | 6073 | relax_start (ep->X_add_symbol); |
df58fc94 | 6074 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6076 | reg, reg, mips_gp_register); | |
6077 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6078 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6079 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6080 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6081 | else if (ex.X_add_number) | |
6082 | { | |
6083 | ex.X_op = O_constant; | |
67c0d1eb RS |
6084 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6085 | BFD_RELOC_LO16); | |
f5040a92 AO |
6086 | } |
6087 | ||
6088 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6089 | relax_switch (); |
67c0d1eb | 6090 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6091 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6092 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6093 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6094 | relax_end (); |
438c16b8 | 6095 | } |
252b5132 | 6096 | else |
438c16b8 | 6097 | { |
f5040a92 AO |
6098 | ex.X_add_number = ep->X_add_number; |
6099 | ep->X_add_number = 0; | |
4d7206a2 | 6100 | relax_start (ep->X_add_symbol); |
df58fc94 | 6101 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6102 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6103 | reg, reg, mips_gp_register); | |
6104 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6105 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6106 | relax_switch (); |
6107 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6108 | { |
6109 | /* We need a nop before loading from $gp. This special | |
6110 | check is required because the lui which starts the main | |
6111 | instruction stream does not refer to $gp, and so will not | |
6112 | insert the nop which may be required. */ | |
67c0d1eb | 6113 | macro_build (NULL, "nop", ""); |
438c16b8 | 6114 | } |
67c0d1eb | 6115 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6116 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6117 | load_delay_nop (); |
67c0d1eb | 6118 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6119 | BFD_RELOC_LO16); |
4d7206a2 | 6120 | relax_end (); |
438c16b8 | 6121 | |
f5040a92 AO |
6122 | if (ex.X_add_number != 0) |
6123 | { | |
6124 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6125 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6126 | ex.X_op = O_constant; | |
67c0d1eb RS |
6127 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6128 | BFD_RELOC_LO16); | |
f5040a92 | 6129 | } |
252b5132 RH |
6130 | } |
6131 | } | |
252b5132 RH |
6132 | else |
6133 | abort (); | |
8fc2e39e | 6134 | |
741fe287 | 6135 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6136 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6137 | } |
6138 | ||
ea1fb5dc RS |
6139 | /* Move the contents of register SOURCE into register DEST. */ |
6140 | ||
6141 | static void | |
67c0d1eb | 6142 | move_register (int dest, int source) |
ea1fb5dc | 6143 | { |
df58fc94 RS |
6144 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6145 | instruction specifically requires a 32-bit one. */ | |
6146 | if (mips_opts.micromips | |
6147 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6148 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6149 | else |
6150 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6151 | dest, source, 0); | |
ea1fb5dc RS |
6152 | } |
6153 | ||
4d7206a2 | 6154 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6155 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6156 | The two alternatives are: | |
4d7206a2 RS |
6157 | |
6158 | Global symbol Local sybmol | |
6159 | ------------- ------------ | |
6160 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6161 | ... ... | |
6162 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6163 | ||
6164 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6165 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6166 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6167 | |
6168 | static void | |
67c0d1eb | 6169 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6170 | { |
6171 | expressionS global; | |
6172 | ||
6173 | global = *local; | |
6174 | global.X_add_number = 0; | |
6175 | ||
6176 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6177 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6178 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6179 | relax_switch (); |
67c0d1eb RS |
6180 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6181 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6182 | relax_end (); |
6183 | } | |
6184 | ||
6185 | static void | |
67c0d1eb | 6186 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6187 | { |
6188 | expressionS global; | |
6189 | ||
6190 | global.X_op = O_constant; | |
6191 | global.X_op_symbol = NULL; | |
6192 | global.X_add_symbol = NULL; | |
6193 | global.X_add_number = local->X_add_number; | |
6194 | ||
6195 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6196 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6197 | dest, dest, BFD_RELOC_LO16); |
6198 | relax_switch (); | |
67c0d1eb | 6199 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6200 | relax_end (); |
6201 | } | |
6202 | ||
f6a22291 MR |
6203 | static void |
6204 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6205 | { | |
6206 | expressionS global; | |
6207 | int hold_mips_optimize; | |
6208 | ||
6209 | global.X_op = O_constant; | |
6210 | global.X_op_symbol = NULL; | |
6211 | global.X_add_symbol = NULL; | |
6212 | global.X_add_number = local->X_add_number; | |
6213 | ||
6214 | relax_start (local->X_add_symbol); | |
6215 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6216 | relax_switch (); | |
6217 | /* Set mips_optimize around the lui instruction to avoid | |
6218 | inserting an unnecessary nop after the lw. */ | |
6219 | hold_mips_optimize = mips_optimize; | |
6220 | mips_optimize = 2; | |
6221 | macro_build_lui (&global, tmp); | |
6222 | mips_optimize = hold_mips_optimize; | |
6223 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6224 | relax_end (); | |
6225 | ||
6226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6227 | } | |
6228 | ||
df58fc94 RS |
6229 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6230 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6231 | is its complementing branch with the original condition negated. | |
6232 | CALL is set if the original branch specified the link operation. | |
6233 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6234 | ||
6235 | Code like this is produced in the noreorder mode: | |
6236 | ||
6237 | BRNEG <args>, 1f | |
6238 | nop | |
6239 | b <sym> | |
6240 | delay slot (executed only if branch taken) | |
6241 | 1: | |
6242 | ||
6243 | or, if CALL is set: | |
6244 | ||
6245 | BRNEG <args>, 1f | |
6246 | nop | |
6247 | bal <sym> | |
6248 | delay slot (executed only if branch taken) | |
6249 | 1: | |
6250 | ||
6251 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6252 | so code produced is simply: | |
6253 | ||
6254 | BR <args>, <sym> | |
6255 | nop | |
6256 | ||
6257 | This function is used when producing code for the microMIPS ASE that | |
6258 | does not implement branch likely instructions in hardware. */ | |
6259 | ||
6260 | static void | |
6261 | macro_build_branch_likely (const char *br, const char *brneg, | |
6262 | int call, expressionS *ep, const char *fmt, | |
6263 | unsigned int sreg, unsigned int treg) | |
6264 | { | |
6265 | int noreorder = mips_opts.noreorder; | |
6266 | expressionS expr1; | |
6267 | ||
6268 | gas_assert (mips_opts.micromips); | |
6269 | start_noreorder (); | |
6270 | if (noreorder) | |
6271 | { | |
6272 | micromips_label_expr (&expr1); | |
6273 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6274 | macro_build (NULL, "nop", ""); | |
6275 | macro_build (ep, call ? "bal" : "b", "p"); | |
6276 | ||
6277 | /* Set to true so that append_insn adds a label. */ | |
6278 | emit_branch_likely_macro = TRUE; | |
6279 | } | |
6280 | else | |
6281 | { | |
6282 | macro_build (ep, br, fmt, sreg, treg); | |
6283 | macro_build (NULL, "nop", ""); | |
6284 | } | |
6285 | end_noreorder (); | |
6286 | } | |
6287 | ||
6288 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6289 | the condition code tested. EP specifies the branch target. */ | |
6290 | ||
6291 | static void | |
6292 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6293 | { | |
6294 | const int call = 0; | |
6295 | const char *brneg; | |
6296 | const char *br; | |
6297 | ||
6298 | switch (type) | |
6299 | { | |
6300 | case M_BC1FL: | |
6301 | br = "bc1f"; | |
6302 | brneg = "bc1t"; | |
6303 | break; | |
6304 | case M_BC1TL: | |
6305 | br = "bc1t"; | |
6306 | brneg = "bc1f"; | |
6307 | break; | |
6308 | case M_BC2FL: | |
6309 | br = "bc2f"; | |
6310 | brneg = "bc2t"; | |
6311 | break; | |
6312 | case M_BC2TL: | |
6313 | br = "bc2t"; | |
6314 | brneg = "bc2f"; | |
6315 | break; | |
6316 | default: | |
6317 | abort (); | |
6318 | } | |
6319 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6320 | } | |
6321 | ||
6322 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6323 | the register tested. EP specifies the branch target. */ | |
6324 | ||
6325 | static void | |
6326 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6327 | { | |
6328 | const char *brneg = NULL; | |
6329 | const char *br; | |
6330 | int call = 0; | |
6331 | ||
6332 | switch (type) | |
6333 | { | |
6334 | case M_BGEZ: | |
6335 | br = "bgez"; | |
6336 | break; | |
6337 | case M_BGEZL: | |
6338 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6339 | brneg = "bltz"; | |
6340 | break; | |
6341 | case M_BGEZALL: | |
6342 | gas_assert (mips_opts.micromips); | |
6343 | br = "bgezals"; | |
6344 | brneg = "bltz"; | |
6345 | call = 1; | |
6346 | break; | |
6347 | case M_BGTZ: | |
6348 | br = "bgtz"; | |
6349 | break; | |
6350 | case M_BGTZL: | |
6351 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6352 | brneg = "blez"; | |
6353 | break; | |
6354 | case M_BLEZ: | |
6355 | br = "blez"; | |
6356 | break; | |
6357 | case M_BLEZL: | |
6358 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6359 | brneg = "bgtz"; | |
6360 | break; | |
6361 | case M_BLTZ: | |
6362 | br = "bltz"; | |
6363 | break; | |
6364 | case M_BLTZL: | |
6365 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6366 | brneg = "bgez"; | |
6367 | break; | |
6368 | case M_BLTZALL: | |
6369 | gas_assert (mips_opts.micromips); | |
6370 | br = "bltzals"; | |
6371 | brneg = "bgez"; | |
6372 | call = 1; | |
6373 | break; | |
6374 | default: | |
6375 | abort (); | |
6376 | } | |
6377 | if (mips_opts.micromips && brneg) | |
6378 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6379 | else | |
6380 | macro_build (ep, br, "s,p", sreg); | |
6381 | } | |
6382 | ||
6383 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6384 | TREG as the registers tested. EP specifies the branch target. */ | |
6385 | ||
6386 | static void | |
6387 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6388 | unsigned int sreg, unsigned int treg) | |
6389 | { | |
6390 | const char *brneg = NULL; | |
6391 | const int call = 0; | |
6392 | const char *br; | |
6393 | ||
6394 | switch (type) | |
6395 | { | |
6396 | case M_BEQ: | |
6397 | case M_BEQ_I: | |
6398 | br = "beq"; | |
6399 | break; | |
6400 | case M_BEQL: | |
6401 | case M_BEQL_I: | |
6402 | br = mips_opts.micromips ? "beq" : "beql"; | |
6403 | brneg = "bne"; | |
6404 | break; | |
6405 | case M_BNE: | |
6406 | case M_BNE_I: | |
6407 | br = "bne"; | |
6408 | break; | |
6409 | case M_BNEL: | |
6410 | case M_BNEL_I: | |
6411 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6412 | brneg = "beq"; | |
6413 | break; | |
6414 | default: | |
6415 | abort (); | |
6416 | } | |
6417 | if (mips_opts.micromips && brneg) | |
6418 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6419 | else | |
6420 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6421 | } | |
6422 | ||
252b5132 RH |
6423 | /* |
6424 | * Build macros | |
6425 | * This routine implements the seemingly endless macro or synthesized | |
6426 | * instructions and addressing modes in the mips assembly language. Many | |
6427 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6428 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6429 | * this verbose method. Others are not simple macros but are more like |
6430 | * optimizing code generation. | |
6431 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6432 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6433 | * The ensuing load upper instructions are ommited. This implies some kind |
6434 | * of global optimization. We currently only optimize within a single macro. | |
6435 | * For many of the load and store macros if the address is specified as a | |
6436 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6437 | * first load register 'at' with zero and use it as the base register. The | |
6438 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6439 | * we're missing. | |
6440 | */ | |
6441 | static void | |
17a2f251 | 6442 | macro (struct mips_cl_insn *ip) |
252b5132 | 6443 | { |
741fe287 MR |
6444 | unsigned int treg, sreg, dreg, breg; |
6445 | unsigned int tempreg; | |
252b5132 | 6446 | int mask; |
43841e91 | 6447 | int used_at = 0; |
df58fc94 | 6448 | expressionS label_expr; |
252b5132 | 6449 | expressionS expr1; |
df58fc94 | 6450 | expressionS *ep; |
252b5132 RH |
6451 | const char *s; |
6452 | const char *s2; | |
6453 | const char *fmt; | |
6454 | int likely = 0; | |
252b5132 | 6455 | int coproc = 0; |
df58fc94 | 6456 | int off12 = 0; |
1abe91b1 | 6457 | int call = 0; |
df58fc94 RS |
6458 | int jals = 0; |
6459 | int dbl = 0; | |
6460 | int imm = 0; | |
6461 | int ust = 0; | |
6462 | int lp = 0; | |
6463 | int ab = 0; | |
dd6a37e7 | 6464 | int off0 = 0; |
252b5132 | 6465 | int off; |
67c0d1eb | 6466 | offsetT maxnum; |
252b5132 | 6467 | bfd_reloc_code_real_type r; |
252b5132 RH |
6468 | int hold_mips_optimize; |
6469 | ||
9c2799c2 | 6470 | gas_assert (! mips_opts.mips16); |
252b5132 | 6471 | |
df58fc94 RS |
6472 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6473 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6474 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6475 | mask = ip->insn_mo->mask; |
6476 | ||
df58fc94 RS |
6477 | label_expr.X_op = O_constant; |
6478 | label_expr.X_op_symbol = NULL; | |
6479 | label_expr.X_add_symbol = NULL; | |
6480 | label_expr.X_add_number = 0; | |
6481 | ||
252b5132 RH |
6482 | expr1.X_op = O_constant; |
6483 | expr1.X_op_symbol = NULL; | |
6484 | expr1.X_add_symbol = NULL; | |
6485 | expr1.X_add_number = 1; | |
6486 | ||
6487 | switch (mask) | |
6488 | { | |
6489 | case M_DABS: | |
6490 | dbl = 1; | |
6491 | case M_ABS: | |
df58fc94 RS |
6492 | /* bgez $a0,1f |
6493 | move v0,$a0 | |
6494 | sub v0,$zero,$a0 | |
6495 | 1: | |
6496 | */ | |
252b5132 | 6497 | |
7d10b47d | 6498 | start_noreorder (); |
252b5132 | 6499 | |
df58fc94 RS |
6500 | if (mips_opts.micromips) |
6501 | micromips_label_expr (&label_expr); | |
6502 | else | |
6503 | label_expr.X_add_number = 8; | |
6504 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6505 | if (dreg == sreg) |
a605d2b3 | 6506 | macro_build (NULL, "nop", ""); |
252b5132 | 6507 | else |
67c0d1eb RS |
6508 | move_register (dreg, sreg); |
6509 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6510 | if (mips_opts.micromips) |
6511 | micromips_add_label (); | |
252b5132 | 6512 | |
7d10b47d | 6513 | end_noreorder (); |
8fc2e39e | 6514 | break; |
252b5132 RH |
6515 | |
6516 | case M_ADD_I: | |
6517 | s = "addi"; | |
6518 | s2 = "add"; | |
6519 | goto do_addi; | |
6520 | case M_ADDU_I: | |
6521 | s = "addiu"; | |
6522 | s2 = "addu"; | |
6523 | goto do_addi; | |
6524 | case M_DADD_I: | |
6525 | dbl = 1; | |
6526 | s = "daddi"; | |
6527 | s2 = "dadd"; | |
df58fc94 RS |
6528 | if (!mips_opts.micromips) |
6529 | goto do_addi; | |
6530 | if (imm_expr.X_op == O_constant | |
6531 | && imm_expr.X_add_number >= -0x200 | |
6532 | && imm_expr.X_add_number < 0x200) | |
6533 | { | |
6534 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6535 | break; | |
6536 | } | |
6537 | goto do_addi_i; | |
252b5132 RH |
6538 | case M_DADDU_I: |
6539 | dbl = 1; | |
6540 | s = "daddiu"; | |
6541 | s2 = "daddu"; | |
6542 | do_addi: | |
6543 | if (imm_expr.X_op == O_constant | |
6544 | && imm_expr.X_add_number >= -0x8000 | |
6545 | && imm_expr.X_add_number < 0x8000) | |
6546 | { | |
67c0d1eb | 6547 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6548 | break; |
252b5132 | 6549 | } |
df58fc94 | 6550 | do_addi_i: |
8fc2e39e | 6551 | used_at = 1; |
67c0d1eb RS |
6552 | load_register (AT, &imm_expr, dbl); |
6553 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6554 | break; |
6555 | ||
6556 | case M_AND_I: | |
6557 | s = "andi"; | |
6558 | s2 = "and"; | |
6559 | goto do_bit; | |
6560 | case M_OR_I: | |
6561 | s = "ori"; | |
6562 | s2 = "or"; | |
6563 | goto do_bit; | |
6564 | case M_NOR_I: | |
6565 | s = ""; | |
6566 | s2 = "nor"; | |
6567 | goto do_bit; | |
6568 | case M_XOR_I: | |
6569 | s = "xori"; | |
6570 | s2 = "xor"; | |
6571 | do_bit: | |
6572 | if (imm_expr.X_op == O_constant | |
6573 | && imm_expr.X_add_number >= 0 | |
6574 | && imm_expr.X_add_number < 0x10000) | |
6575 | { | |
6576 | if (mask != M_NOR_I) | |
67c0d1eb | 6577 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6578 | else |
6579 | { | |
67c0d1eb RS |
6580 | macro_build (&imm_expr, "ori", "t,r,i", |
6581 | treg, sreg, BFD_RELOC_LO16); | |
6582 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6583 | } |
8fc2e39e | 6584 | break; |
252b5132 RH |
6585 | } |
6586 | ||
8fc2e39e | 6587 | used_at = 1; |
67c0d1eb RS |
6588 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6589 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6590 | break; |
6591 | ||
8b082fb1 TS |
6592 | case M_BALIGN: |
6593 | switch (imm_expr.X_add_number) | |
6594 | { | |
6595 | case 0: | |
6596 | macro_build (NULL, "nop", ""); | |
6597 | break; | |
6598 | case 2: | |
6599 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6600 | break; | |
03f66e8a MR |
6601 | case 1: |
6602 | case 3: | |
8b082fb1 | 6603 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6604 | (int) imm_expr.X_add_number); |
8b082fb1 | 6605 | break; |
03f66e8a MR |
6606 | default: |
6607 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6608 | (unsigned long) imm_expr.X_add_number); | |
6609 | break; | |
8b082fb1 TS |
6610 | } |
6611 | break; | |
6612 | ||
df58fc94 RS |
6613 | case M_BC1FL: |
6614 | case M_BC1TL: | |
6615 | case M_BC2FL: | |
6616 | case M_BC2TL: | |
6617 | gas_assert (mips_opts.micromips); | |
6618 | macro_build_branch_ccl (mask, &offset_expr, | |
6619 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6620 | break; | |
6621 | ||
252b5132 | 6622 | case M_BEQ_I: |
252b5132 | 6623 | case M_BEQL_I: |
252b5132 | 6624 | case M_BNE_I: |
252b5132 | 6625 | case M_BNEL_I: |
252b5132 | 6626 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6627 | treg = 0; |
6628 | else | |
252b5132 | 6629 | { |
df58fc94 RS |
6630 | treg = AT; |
6631 | used_at = 1; | |
6632 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6633 | } |
df58fc94 RS |
6634 | /* Fall through. */ |
6635 | case M_BEQL: | |
6636 | case M_BNEL: | |
6637 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6638 | break; |
6639 | ||
6640 | case M_BGEL: | |
6641 | likely = 1; | |
6642 | case M_BGE: | |
6643 | if (treg == 0) | |
df58fc94 RS |
6644 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6645 | else if (sreg == 0) | |
6646 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6647 | else | |
252b5132 | 6648 | { |
df58fc94 RS |
6649 | used_at = 1; |
6650 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6651 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6652 | &offset_expr, AT, ZERO); | |
252b5132 | 6653 | } |
df58fc94 RS |
6654 | break; |
6655 | ||
6656 | case M_BGEZL: | |
6657 | case M_BGEZALL: | |
6658 | case M_BGTZL: | |
6659 | case M_BLEZL: | |
6660 | case M_BLTZL: | |
6661 | case M_BLTZALL: | |
6662 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6663 | break; |
6664 | ||
6665 | case M_BGTL_I: | |
6666 | likely = 1; | |
6667 | case M_BGT_I: | |
90ecf173 | 6668 | /* Check for > max integer. */ |
252b5132 | 6669 | maxnum = 0x7fffffff; |
ca4e0257 | 6670 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6671 | { |
6672 | maxnum <<= 16; | |
6673 | maxnum |= 0xffff; | |
6674 | maxnum <<= 16; | |
6675 | maxnum |= 0xffff; | |
6676 | } | |
6677 | if (imm_expr.X_op == O_constant | |
6678 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6679 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6680 | { |
6681 | do_false: | |
90ecf173 | 6682 | /* Result is always false. */ |
252b5132 | 6683 | if (! likely) |
a605d2b3 | 6684 | macro_build (NULL, "nop", ""); |
252b5132 | 6685 | else |
df58fc94 | 6686 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6687 | break; |
252b5132 RH |
6688 | } |
6689 | if (imm_expr.X_op != O_constant) | |
6690 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6691 | ++imm_expr.X_add_number; |
252b5132 RH |
6692 | /* FALLTHROUGH */ |
6693 | case M_BGE_I: | |
6694 | case M_BGEL_I: | |
6695 | if (mask == M_BGEL_I) | |
6696 | likely = 1; | |
6697 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6698 | { | |
df58fc94 RS |
6699 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6700 | &offset_expr, sreg); | |
8fc2e39e | 6701 | break; |
252b5132 RH |
6702 | } |
6703 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6704 | { | |
df58fc94 RS |
6705 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6706 | &offset_expr, sreg); | |
8fc2e39e | 6707 | break; |
252b5132 RH |
6708 | } |
6709 | maxnum = 0x7fffffff; | |
ca4e0257 | 6710 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6711 | { |
6712 | maxnum <<= 16; | |
6713 | maxnum |= 0xffff; | |
6714 | maxnum <<= 16; | |
6715 | maxnum |= 0xffff; | |
6716 | } | |
6717 | maxnum = - maxnum - 1; | |
6718 | if (imm_expr.X_op == O_constant | |
6719 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6720 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6721 | { |
6722 | do_true: | |
6723 | /* result is always true */ | |
6724 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6725 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6726 | break; |
252b5132 | 6727 | } |
8fc2e39e | 6728 | used_at = 1; |
67c0d1eb | 6729 | set_at (sreg, 0); |
df58fc94 RS |
6730 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6731 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6732 | break; |
6733 | ||
6734 | case M_BGEUL: | |
6735 | likely = 1; | |
6736 | case M_BGEU: | |
6737 | if (treg == 0) | |
6738 | goto do_true; | |
df58fc94 RS |
6739 | else if (sreg == 0) |
6740 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6741 | &offset_expr, ZERO, treg); | |
6742 | else | |
252b5132 | 6743 | { |
df58fc94 RS |
6744 | used_at = 1; |
6745 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6746 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6747 | &offset_expr, AT, ZERO); | |
252b5132 | 6748 | } |
252b5132 RH |
6749 | break; |
6750 | ||
6751 | case M_BGTUL_I: | |
6752 | likely = 1; | |
6753 | case M_BGTU_I: | |
6754 | if (sreg == 0 | |
ca4e0257 | 6755 | || (HAVE_32BIT_GPRS |
252b5132 | 6756 | && imm_expr.X_op == O_constant |
f01dc953 | 6757 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6758 | goto do_false; |
6759 | if (imm_expr.X_op != O_constant) | |
6760 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6761 | ++imm_expr.X_add_number; |
252b5132 RH |
6762 | /* FALLTHROUGH */ |
6763 | case M_BGEU_I: | |
6764 | case M_BGEUL_I: | |
6765 | if (mask == M_BGEUL_I) | |
6766 | likely = 1; | |
6767 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6768 | goto do_true; | |
df58fc94 RS |
6769 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6770 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6771 | &offset_expr, sreg, ZERO); | |
6772 | else | |
252b5132 | 6773 | { |
df58fc94 RS |
6774 | used_at = 1; |
6775 | set_at (sreg, 1); | |
6776 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6777 | &offset_expr, AT, ZERO); | |
252b5132 | 6778 | } |
252b5132 RH |
6779 | break; |
6780 | ||
6781 | case M_BGTL: | |
6782 | likely = 1; | |
6783 | case M_BGT: | |
6784 | if (treg == 0) | |
df58fc94 RS |
6785 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6786 | else if (sreg == 0) | |
6787 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6788 | else | |
252b5132 | 6789 | { |
df58fc94 RS |
6790 | used_at = 1; |
6791 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6792 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6793 | &offset_expr, AT, ZERO); | |
252b5132 | 6794 | } |
252b5132 RH |
6795 | break; |
6796 | ||
6797 | case M_BGTUL: | |
6798 | likely = 1; | |
6799 | case M_BGTU: | |
6800 | if (treg == 0) | |
df58fc94 RS |
6801 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6802 | &offset_expr, sreg, ZERO); | |
6803 | else if (sreg == 0) | |
6804 | goto do_false; | |
6805 | else | |
252b5132 | 6806 | { |
df58fc94 RS |
6807 | used_at = 1; |
6808 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6809 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6810 | &offset_expr, AT, ZERO); | |
252b5132 | 6811 | } |
252b5132 RH |
6812 | break; |
6813 | ||
6814 | case M_BLEL: | |
6815 | likely = 1; | |
6816 | case M_BLE: | |
6817 | if (treg == 0) | |
df58fc94 RS |
6818 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6819 | else if (sreg == 0) | |
6820 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6821 | else | |
252b5132 | 6822 | { |
df58fc94 RS |
6823 | used_at = 1; |
6824 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6825 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6826 | &offset_expr, AT, ZERO); | |
252b5132 | 6827 | } |
252b5132 RH |
6828 | break; |
6829 | ||
6830 | case M_BLEL_I: | |
6831 | likely = 1; | |
6832 | case M_BLE_I: | |
6833 | maxnum = 0x7fffffff; | |
ca4e0257 | 6834 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6835 | { |
6836 | maxnum <<= 16; | |
6837 | maxnum |= 0xffff; | |
6838 | maxnum <<= 16; | |
6839 | maxnum |= 0xffff; | |
6840 | } | |
6841 | if (imm_expr.X_op == O_constant | |
6842 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6843 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6844 | goto do_true; |
6845 | if (imm_expr.X_op != O_constant) | |
6846 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6847 | ++imm_expr.X_add_number; |
252b5132 RH |
6848 | /* FALLTHROUGH */ |
6849 | case M_BLT_I: | |
6850 | case M_BLTL_I: | |
6851 | if (mask == M_BLTL_I) | |
6852 | likely = 1; | |
6853 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6854 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6855 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6856 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6857 | else | |
252b5132 | 6858 | { |
df58fc94 RS |
6859 | used_at = 1; |
6860 | set_at (sreg, 0); | |
6861 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6862 | &offset_expr, AT, ZERO); | |
252b5132 | 6863 | } |
252b5132 RH |
6864 | break; |
6865 | ||
6866 | case M_BLEUL: | |
6867 | likely = 1; | |
6868 | case M_BLEU: | |
6869 | if (treg == 0) | |
df58fc94 RS |
6870 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6871 | &offset_expr, sreg, ZERO); | |
6872 | else if (sreg == 0) | |
6873 | goto do_true; | |
6874 | else | |
252b5132 | 6875 | { |
df58fc94 RS |
6876 | used_at = 1; |
6877 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6878 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6879 | &offset_expr, AT, ZERO); | |
252b5132 | 6880 | } |
252b5132 RH |
6881 | break; |
6882 | ||
6883 | case M_BLEUL_I: | |
6884 | likely = 1; | |
6885 | case M_BLEU_I: | |
6886 | if (sreg == 0 | |
ca4e0257 | 6887 | || (HAVE_32BIT_GPRS |
252b5132 | 6888 | && imm_expr.X_op == O_constant |
f01dc953 | 6889 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6890 | goto do_true; |
6891 | if (imm_expr.X_op != O_constant) | |
6892 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6893 | ++imm_expr.X_add_number; |
252b5132 RH |
6894 | /* FALLTHROUGH */ |
6895 | case M_BLTU_I: | |
6896 | case M_BLTUL_I: | |
6897 | if (mask == M_BLTUL_I) | |
6898 | likely = 1; | |
6899 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6900 | goto do_false; | |
df58fc94 RS |
6901 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6902 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6903 | &offset_expr, sreg, ZERO); | |
6904 | else | |
252b5132 | 6905 | { |
df58fc94 RS |
6906 | used_at = 1; |
6907 | set_at (sreg, 1); | |
6908 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6909 | &offset_expr, AT, ZERO); | |
252b5132 | 6910 | } |
252b5132 RH |
6911 | break; |
6912 | ||
6913 | case M_BLTL: | |
6914 | likely = 1; | |
6915 | case M_BLT: | |
6916 | if (treg == 0) | |
df58fc94 RS |
6917 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6918 | else if (sreg == 0) | |
6919 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6920 | else | |
252b5132 | 6921 | { |
df58fc94 RS |
6922 | used_at = 1; |
6923 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6924 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6925 | &offset_expr, AT, ZERO); | |
252b5132 | 6926 | } |
252b5132 RH |
6927 | break; |
6928 | ||
6929 | case M_BLTUL: | |
6930 | likely = 1; | |
6931 | case M_BLTU: | |
6932 | if (treg == 0) | |
6933 | goto do_false; | |
df58fc94 RS |
6934 | else if (sreg == 0) |
6935 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6936 | &offset_expr, ZERO, treg); | |
6937 | else | |
252b5132 | 6938 | { |
df58fc94 RS |
6939 | used_at = 1; |
6940 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6941 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6942 | &offset_expr, AT, ZERO); | |
252b5132 | 6943 | } |
252b5132 RH |
6944 | break; |
6945 | ||
5f74bc13 CD |
6946 | case M_DEXT: |
6947 | { | |
d5818fca MR |
6948 | /* Use unsigned arithmetic. */ |
6949 | addressT pos; | |
6950 | addressT size; | |
5f74bc13 | 6951 | |
90ecf173 | 6952 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6953 | { |
6954 | as_bad (_("Unsupported large constant")); | |
6955 | pos = size = 1; | |
6956 | } | |
6957 | else | |
6958 | { | |
d5818fca MR |
6959 | pos = imm_expr.X_add_number; |
6960 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6961 | } |
6962 | ||
6963 | if (pos > 63) | |
6964 | { | |
d5818fca | 6965 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6966 | pos = 1; |
6967 | } | |
90ecf173 | 6968 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6969 | { |
6970 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6971 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6972 | size = 1; |
6973 | } | |
6974 | ||
6975 | if (size <= 32 && pos < 32) | |
6976 | { | |
6977 | s = "dext"; | |
6978 | fmt = "t,r,+A,+C"; | |
6979 | } | |
6980 | else if (size <= 32) | |
6981 | { | |
6982 | s = "dextu"; | |
6983 | fmt = "t,r,+E,+H"; | |
6984 | } | |
6985 | else | |
6986 | { | |
6987 | s = "dextm"; | |
6988 | fmt = "t,r,+A,+G"; | |
6989 | } | |
d5818fca MR |
6990 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6991 | (int) (size - 1)); | |
5f74bc13 | 6992 | } |
8fc2e39e | 6993 | break; |
5f74bc13 CD |
6994 | |
6995 | case M_DINS: | |
6996 | { | |
d5818fca MR |
6997 | /* Use unsigned arithmetic. */ |
6998 | addressT pos; | |
6999 | addressT size; | |
5f74bc13 | 7000 | |
90ecf173 | 7001 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7002 | { |
7003 | as_bad (_("Unsupported large constant")); | |
7004 | pos = size = 1; | |
7005 | } | |
7006 | else | |
7007 | { | |
d5818fca MR |
7008 | pos = imm_expr.X_add_number; |
7009 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7010 | } |
7011 | ||
7012 | if (pos > 63) | |
7013 | { | |
d5818fca | 7014 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7015 | pos = 1; |
7016 | } | |
90ecf173 | 7017 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7018 | { |
7019 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7020 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7021 | size = 1; |
7022 | } | |
7023 | ||
7024 | if (pos < 32 && (pos + size - 1) < 32) | |
7025 | { | |
7026 | s = "dins"; | |
7027 | fmt = "t,r,+A,+B"; | |
7028 | } | |
7029 | else if (pos >= 32) | |
7030 | { | |
7031 | s = "dinsu"; | |
7032 | fmt = "t,r,+E,+F"; | |
7033 | } | |
7034 | else | |
7035 | { | |
7036 | s = "dinsm"; | |
7037 | fmt = "t,r,+A,+F"; | |
7038 | } | |
750bdd57 AS |
7039 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7040 | (int) (pos + size - 1)); | |
5f74bc13 | 7041 | } |
8fc2e39e | 7042 | break; |
5f74bc13 | 7043 | |
252b5132 RH |
7044 | case M_DDIV_3: |
7045 | dbl = 1; | |
7046 | case M_DIV_3: | |
7047 | s = "mflo"; | |
7048 | goto do_div3; | |
7049 | case M_DREM_3: | |
7050 | dbl = 1; | |
7051 | case M_REM_3: | |
7052 | s = "mfhi"; | |
7053 | do_div3: | |
7054 | if (treg == 0) | |
7055 | { | |
7056 | as_warn (_("Divide by zero.")); | |
7057 | if (mips_trap) | |
df58fc94 | 7058 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7059 | else |
df58fc94 | 7060 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7061 | break; |
252b5132 RH |
7062 | } |
7063 | ||
7d10b47d | 7064 | start_noreorder (); |
252b5132 RH |
7065 | if (mips_trap) |
7066 | { | |
df58fc94 | 7067 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7068 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7069 | } |
7070 | else | |
7071 | { | |
df58fc94 RS |
7072 | if (mips_opts.micromips) |
7073 | micromips_label_expr (&label_expr); | |
7074 | else | |
7075 | label_expr.X_add_number = 8; | |
7076 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7077 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7078 | macro_build (NULL, "break", BRK_FMT, 7); |
7079 | if (mips_opts.micromips) | |
7080 | micromips_add_label (); | |
252b5132 RH |
7081 | } |
7082 | expr1.X_add_number = -1; | |
8fc2e39e | 7083 | used_at = 1; |
f6a22291 | 7084 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7085 | if (mips_opts.micromips) |
7086 | micromips_label_expr (&label_expr); | |
7087 | else | |
7088 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7089 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7090 | if (dbl) |
7091 | { | |
7092 | expr1.X_add_number = 1; | |
f6a22291 | 7093 | load_register (AT, &expr1, dbl); |
df58fc94 | 7094 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7095 | } |
7096 | else | |
7097 | { | |
7098 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7099 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7100 | } |
7101 | if (mips_trap) | |
7102 | { | |
df58fc94 | 7103 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7104 | /* We want to close the noreorder block as soon as possible, so |
7105 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7106 | end_noreorder (); |
252b5132 RH |
7107 | } |
7108 | else | |
7109 | { | |
df58fc94 RS |
7110 | if (mips_opts.micromips) |
7111 | micromips_label_expr (&label_expr); | |
7112 | else | |
7113 | label_expr.X_add_number = 8; | |
7114 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7115 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7116 | |
7117 | /* We want to close the noreorder block as soon as possible, so | |
7118 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7119 | end_noreorder (); |
252b5132 | 7120 | |
df58fc94 | 7121 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7122 | } |
df58fc94 RS |
7123 | if (mips_opts.micromips) |
7124 | micromips_add_label (); | |
7125 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7126 | break; |
7127 | ||
7128 | case M_DIV_3I: | |
7129 | s = "div"; | |
7130 | s2 = "mflo"; | |
7131 | goto do_divi; | |
7132 | case M_DIVU_3I: | |
7133 | s = "divu"; | |
7134 | s2 = "mflo"; | |
7135 | goto do_divi; | |
7136 | case M_REM_3I: | |
7137 | s = "div"; | |
7138 | s2 = "mfhi"; | |
7139 | goto do_divi; | |
7140 | case M_REMU_3I: | |
7141 | s = "divu"; | |
7142 | s2 = "mfhi"; | |
7143 | goto do_divi; | |
7144 | case M_DDIV_3I: | |
7145 | dbl = 1; | |
7146 | s = "ddiv"; | |
7147 | s2 = "mflo"; | |
7148 | goto do_divi; | |
7149 | case M_DDIVU_3I: | |
7150 | dbl = 1; | |
7151 | s = "ddivu"; | |
7152 | s2 = "mflo"; | |
7153 | goto do_divi; | |
7154 | case M_DREM_3I: | |
7155 | dbl = 1; | |
7156 | s = "ddiv"; | |
7157 | s2 = "mfhi"; | |
7158 | goto do_divi; | |
7159 | case M_DREMU_3I: | |
7160 | dbl = 1; | |
7161 | s = "ddivu"; | |
7162 | s2 = "mfhi"; | |
7163 | do_divi: | |
7164 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7165 | { | |
7166 | as_warn (_("Divide by zero.")); | |
7167 | if (mips_trap) | |
df58fc94 | 7168 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7169 | else |
df58fc94 | 7170 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7171 | break; |
252b5132 RH |
7172 | } |
7173 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7174 | { | |
7175 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7176 | move_register (dreg, sreg); |
252b5132 | 7177 | else |
c80c840e | 7178 | move_register (dreg, ZERO); |
8fc2e39e | 7179 | break; |
252b5132 RH |
7180 | } |
7181 | if (imm_expr.X_op == O_constant | |
7182 | && imm_expr.X_add_number == -1 | |
7183 | && s[strlen (s) - 1] != 'u') | |
7184 | { | |
7185 | if (strcmp (s2, "mflo") == 0) | |
7186 | { | |
67c0d1eb | 7187 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7188 | } |
7189 | else | |
c80c840e | 7190 | move_register (dreg, ZERO); |
8fc2e39e | 7191 | break; |
252b5132 RH |
7192 | } |
7193 | ||
8fc2e39e | 7194 | used_at = 1; |
67c0d1eb RS |
7195 | load_register (AT, &imm_expr, dbl); |
7196 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7197 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7198 | break; |
7199 | ||
7200 | case M_DIVU_3: | |
7201 | s = "divu"; | |
7202 | s2 = "mflo"; | |
7203 | goto do_divu3; | |
7204 | case M_REMU_3: | |
7205 | s = "divu"; | |
7206 | s2 = "mfhi"; | |
7207 | goto do_divu3; | |
7208 | case M_DDIVU_3: | |
7209 | s = "ddivu"; | |
7210 | s2 = "mflo"; | |
7211 | goto do_divu3; | |
7212 | case M_DREMU_3: | |
7213 | s = "ddivu"; | |
7214 | s2 = "mfhi"; | |
7215 | do_divu3: | |
7d10b47d | 7216 | start_noreorder (); |
252b5132 RH |
7217 | if (mips_trap) |
7218 | { | |
df58fc94 | 7219 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7220 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7221 | /* We want to close the noreorder block as soon as possible, so |
7222 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7223 | end_noreorder (); |
252b5132 RH |
7224 | } |
7225 | else | |
7226 | { | |
df58fc94 RS |
7227 | if (mips_opts.micromips) |
7228 | micromips_label_expr (&label_expr); | |
7229 | else | |
7230 | label_expr.X_add_number = 8; | |
7231 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7232 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7233 | |
7234 | /* We want to close the noreorder block as soon as possible, so | |
7235 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7236 | end_noreorder (); |
df58fc94 RS |
7237 | macro_build (NULL, "break", BRK_FMT, 7); |
7238 | if (mips_opts.micromips) | |
7239 | micromips_add_label (); | |
252b5132 | 7240 | } |
df58fc94 | 7241 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7242 | break; |
252b5132 | 7243 | |
1abe91b1 MR |
7244 | case M_DLCA_AB: |
7245 | dbl = 1; | |
7246 | case M_LCA_AB: | |
7247 | call = 1; | |
7248 | goto do_la; | |
252b5132 RH |
7249 | case M_DLA_AB: |
7250 | dbl = 1; | |
7251 | case M_LA_AB: | |
1abe91b1 | 7252 | do_la: |
252b5132 RH |
7253 | /* Load the address of a symbol into a register. If breg is not |
7254 | zero, we then add a base register to it. */ | |
7255 | ||
3bec30a8 TS |
7256 | if (dbl && HAVE_32BIT_GPRS) |
7257 | as_warn (_("dla used to load 32-bit register")); | |
7258 | ||
90ecf173 | 7259 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7260 | as_warn (_("la used to load 64-bit address")); |
7261 | ||
0c11417f MR |
7262 | if (offset_expr.X_op == O_constant |
7263 | && offset_expr.X_add_number >= -0x8000 | |
7264 | && offset_expr.X_add_number < 0x8000) | |
7265 | { | |
aed1a261 | 7266 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7267 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7268 | break; |
0c11417f MR |
7269 | } |
7270 | ||
741fe287 | 7271 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7272 | { |
7273 | tempreg = AT; | |
7274 | used_at = 1; | |
7275 | } | |
7276 | else | |
7277 | { | |
7278 | tempreg = treg; | |
afdbd6d0 CD |
7279 | } |
7280 | ||
252b5132 RH |
7281 | if (offset_expr.X_op != O_symbol |
7282 | && offset_expr.X_op != O_constant) | |
7283 | { | |
f71d0d44 | 7284 | as_bad (_("Expression too complex")); |
252b5132 RH |
7285 | offset_expr.X_op = O_constant; |
7286 | } | |
7287 | ||
252b5132 | 7288 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7289 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7290 | else if (mips_pic == NO_PIC) |
7291 | { | |
d6bc6245 | 7292 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7293 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7294 | Otherwise we want |
7295 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7296 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7297 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7298 | so we may as well always use the latter form. |
76b3015f | 7299 | |
6caf9ef4 TS |
7300 | With 64bit address space and a usable $at we want |
7301 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7302 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7303 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7304 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7305 | dsll32 $tempreg,0 | |
7306 | daddu $tempreg,$tempreg,$at | |
7307 | ||
7308 | If $at is already in use, we use a path which is suboptimal | |
7309 | on superscalar processors. | |
7310 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7311 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7312 | dsll $tempreg,16 | |
7313 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7314 | dsll $tempreg,16 | |
7315 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7316 | ||
7317 | For GP relative symbols in 64bit address space we can use | |
7318 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7319 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7320 | { |
6caf9ef4 TS |
7321 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7322 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7323 | { | |
7324 | relax_start (offset_expr.X_add_symbol); | |
7325 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7326 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7327 | relax_switch (); | |
7328 | } | |
d6bc6245 | 7329 | |
741fe287 | 7330 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7331 | { |
df58fc94 | 7332 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7333 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7334 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7335 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7336 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7337 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7338 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7339 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7340 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7341 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7342 | used_at = 1; |
7343 | } | |
7344 | else | |
7345 | { | |
df58fc94 | 7346 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7347 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7348 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7349 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7350 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7351 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7352 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7353 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7354 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7355 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7356 | } |
6caf9ef4 TS |
7357 | |
7358 | if (mips_relax.sequence) | |
7359 | relax_end (); | |
98d3f06f KH |
7360 | } |
7361 | else | |
7362 | { | |
7363 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7364 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7365 | { |
4d7206a2 | 7366 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7367 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7368 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7369 | relax_switch (); |
98d3f06f | 7370 | } |
6943caf0 | 7371 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7372 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7373 | macro_build_lui (&offset_expr, tempreg); |
7374 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7375 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7376 | if (mips_relax.sequence) |
7377 | relax_end (); | |
98d3f06f | 7378 | } |
252b5132 | 7379 | } |
0a44bf69 | 7380 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7381 | { |
9117d219 NC |
7382 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7383 | ||
252b5132 RH |
7384 | /* If this is a reference to an external symbol, and there |
7385 | is no constant, we want | |
7386 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7387 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7388 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7389 | For a local symbol, we want |
7390 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7391 | nop | |
7392 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7393 | ||
7394 | If we have a small constant, and this is a reference to | |
7395 | an external symbol, we want | |
7396 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7397 | nop | |
7398 | addiu $tempreg,$tempreg,<constant> | |
7399 | For a local symbol, we want the same instruction | |
7400 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7401 | addiu instruction. | |
7402 | ||
7403 | If we have a large constant, and this is a reference to | |
7404 | an external symbol, we want | |
7405 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7406 | lui $at,<hiconstant> | |
7407 | addiu $at,$at,<loconstant> | |
7408 | addu $tempreg,$tempreg,$at | |
7409 | For a local symbol, we want the same instruction | |
7410 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7411 | addiu instruction. |
ed6fb7bd SC |
7412 | */ |
7413 | ||
4d7206a2 | 7414 | if (offset_expr.X_add_number == 0) |
252b5132 | 7415 | { |
0a44bf69 RS |
7416 | if (mips_pic == SVR4_PIC |
7417 | && breg == 0 | |
7418 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7419 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7420 | ||
7421 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7422 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7423 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7424 | if (breg != 0) |
252b5132 RH |
7425 | { |
7426 | /* We're going to put in an addu instruction using | |
7427 | tempreg, so we may as well insert the nop right | |
7428 | now. */ | |
269137b2 | 7429 | load_delay_nop (); |
252b5132 | 7430 | } |
4d7206a2 | 7431 | relax_switch (); |
67c0d1eb RS |
7432 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7433 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7434 | load_delay_nop (); |
67c0d1eb RS |
7435 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7436 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7437 | relax_end (); |
252b5132 RH |
7438 | /* FIXME: If breg == 0, and the next instruction uses |
7439 | $tempreg, then if this variant case is used an extra | |
7440 | nop will be generated. */ | |
7441 | } | |
4d7206a2 RS |
7442 | else if (offset_expr.X_add_number >= -0x8000 |
7443 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7444 | { |
67c0d1eb | 7445 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7446 | load_delay_nop (); |
67c0d1eb | 7447 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7448 | } |
7449 | else | |
7450 | { | |
4d7206a2 RS |
7451 | expr1.X_add_number = offset_expr.X_add_number; |
7452 | offset_expr.X_add_number = | |
43c0598f | 7453 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7454 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7455 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7456 | /* If we are going to add in a base register, and the |
7457 | target register and the base register are the same, | |
7458 | then we are using AT as a temporary register. Since | |
7459 | we want to load the constant into AT, we add our | |
7460 | current AT (from the global offset table) and the | |
7461 | register into the register now, and pretend we were | |
7462 | not using a base register. */ | |
67c0d1eb | 7463 | if (breg == treg) |
252b5132 | 7464 | { |
269137b2 | 7465 | load_delay_nop (); |
67c0d1eb | 7466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7467 | treg, AT, breg); |
252b5132 RH |
7468 | breg = 0; |
7469 | tempreg = treg; | |
252b5132 | 7470 | } |
f6a22291 | 7471 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7472 | used_at = 1; |
7473 | } | |
7474 | } | |
0a44bf69 | 7475 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7476 | { |
67c0d1eb | 7477 | int add_breg_early = 0; |
f5040a92 AO |
7478 | |
7479 | /* If this is a reference to an external, and there is no | |
7480 | constant, or local symbol (*), with or without a | |
7481 | constant, we want | |
7482 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7483 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7484 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7485 | ||
7486 | If we have a small constant, and this is a reference to | |
7487 | an external symbol, we want | |
7488 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7489 | addiu $tempreg,$tempreg,<constant> | |
7490 | ||
7491 | If we have a large constant, and this is a reference to | |
7492 | an external symbol, we want | |
7493 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7494 | lui $at,<hiconstant> | |
7495 | addiu $at,$at,<loconstant> | |
7496 | addu $tempreg,$tempreg,$at | |
7497 | ||
7498 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7499 | local symbols, even though it introduces an additional | |
7500 | instruction. */ | |
7501 | ||
f5040a92 AO |
7502 | if (offset_expr.X_add_number) |
7503 | { | |
4d7206a2 | 7504 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7505 | offset_expr.X_add_number = 0; |
7506 | ||
4d7206a2 | 7507 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7508 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7509 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7510 | |
7511 | if (expr1.X_add_number >= -0x8000 | |
7512 | && expr1.X_add_number < 0x8000) | |
7513 | { | |
67c0d1eb RS |
7514 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7515 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7516 | } |
ecd13cd3 | 7517 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7518 | { |
f5040a92 AO |
7519 | /* If we are going to add in a base register, and the |
7520 | target register and the base register are the same, | |
7521 | then we are using AT as a temporary register. Since | |
7522 | we want to load the constant into AT, we add our | |
7523 | current AT (from the global offset table) and the | |
7524 | register into the register now, and pretend we were | |
7525 | not using a base register. */ | |
7526 | if (breg != treg) | |
7527 | dreg = tempreg; | |
7528 | else | |
7529 | { | |
9c2799c2 | 7530 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7531 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7532 | treg, AT, breg); | |
f5040a92 | 7533 | dreg = treg; |
67c0d1eb | 7534 | add_breg_early = 1; |
f5040a92 AO |
7535 | } |
7536 | ||
f6a22291 | 7537 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7538 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7539 | dreg, dreg, AT); |
f5040a92 | 7540 | |
f5040a92 AO |
7541 | used_at = 1; |
7542 | } | |
7543 | else | |
7544 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7545 | ||
4d7206a2 | 7546 | relax_switch (); |
f5040a92 AO |
7547 | offset_expr.X_add_number = expr1.X_add_number; |
7548 | ||
67c0d1eb RS |
7549 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7550 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7551 | if (add_breg_early) | |
f5040a92 | 7552 | { |
67c0d1eb | 7553 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7554 | treg, tempreg, breg); |
f5040a92 AO |
7555 | breg = 0; |
7556 | tempreg = treg; | |
7557 | } | |
4d7206a2 | 7558 | relax_end (); |
f5040a92 | 7559 | } |
4d7206a2 | 7560 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7561 | { |
4d7206a2 | 7562 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7563 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7564 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7565 | relax_switch (); |
67c0d1eb RS |
7566 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7567 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7568 | relax_end (); |
f5040a92 | 7569 | } |
4d7206a2 | 7570 | else |
f5040a92 | 7571 | { |
67c0d1eb RS |
7572 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7573 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7574 | } |
7575 | } | |
0a44bf69 | 7576 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7577 | { |
67c0d1eb | 7578 | int gpdelay; |
9117d219 NC |
7579 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7580 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7581 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7582 | |
7583 | /* This is the large GOT case. If this is a reference to an | |
7584 | external symbol, and there is no constant, we want | |
7585 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7586 | addu $tempreg,$tempreg,$gp | |
7587 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7588 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7589 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7590 | addu $tempreg,$tempreg,$gp | |
7591 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7592 | For a local symbol, we want |
7593 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7594 | nop | |
7595 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7596 | ||
7597 | If we have a small constant, and this is a reference to | |
7598 | an external symbol, we want | |
7599 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7600 | addu $tempreg,$tempreg,$gp | |
7601 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7602 | nop | |
7603 | addiu $tempreg,$tempreg,<constant> | |
7604 | For a local symbol, we want | |
7605 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7606 | nop | |
7607 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7608 | ||
7609 | If we have a large constant, and this is a reference to | |
7610 | an external symbol, we want | |
7611 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7612 | addu $tempreg,$tempreg,$gp | |
7613 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7614 | lui $at,<hiconstant> | |
7615 | addiu $at,$at,<loconstant> | |
7616 | addu $tempreg,$tempreg,$at | |
7617 | For a local symbol, we want | |
7618 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7619 | lui $at,<hiconstant> | |
7620 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7621 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7622 | */ |
438c16b8 | 7623 | |
252b5132 RH |
7624 | expr1.X_add_number = offset_expr.X_add_number; |
7625 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7626 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7627 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7628 | if (expr1.X_add_number == 0 && breg == 0 |
7629 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7630 | { |
7631 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7632 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7633 | } | |
df58fc94 | 7634 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7635 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7636 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7637 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7638 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7639 | if (expr1.X_add_number == 0) |
7640 | { | |
67c0d1eb | 7641 | if (breg != 0) |
252b5132 RH |
7642 | { |
7643 | /* We're going to put in an addu instruction using | |
7644 | tempreg, so we may as well insert the nop right | |
7645 | now. */ | |
269137b2 | 7646 | load_delay_nop (); |
252b5132 | 7647 | } |
252b5132 RH |
7648 | } |
7649 | else if (expr1.X_add_number >= -0x8000 | |
7650 | && expr1.X_add_number < 0x8000) | |
7651 | { | |
269137b2 | 7652 | load_delay_nop (); |
67c0d1eb | 7653 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7654 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7655 | } |
7656 | else | |
7657 | { | |
252b5132 RH |
7658 | /* If we are going to add in a base register, and the |
7659 | target register and the base register are the same, | |
7660 | then we are using AT as a temporary register. Since | |
7661 | we want to load the constant into AT, we add our | |
7662 | current AT (from the global offset table) and the | |
7663 | register into the register now, and pretend we were | |
7664 | not using a base register. */ | |
7665 | if (breg != treg) | |
67c0d1eb | 7666 | dreg = tempreg; |
252b5132 RH |
7667 | else |
7668 | { | |
9c2799c2 | 7669 | gas_assert (tempreg == AT); |
269137b2 | 7670 | load_delay_nop (); |
67c0d1eb | 7671 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7672 | treg, AT, breg); |
252b5132 | 7673 | dreg = treg; |
252b5132 RH |
7674 | } |
7675 | ||
f6a22291 | 7676 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7677 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7678 | |
252b5132 RH |
7679 | used_at = 1; |
7680 | } | |
43c0598f | 7681 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7682 | relax_switch (); |
252b5132 | 7683 | |
67c0d1eb | 7684 | if (gpdelay) |
252b5132 RH |
7685 | { |
7686 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7687 | the first instruction on the main stream does not. */ |
67c0d1eb | 7688 | macro_build (NULL, "nop", ""); |
252b5132 | 7689 | } |
ed6fb7bd | 7690 | |
67c0d1eb RS |
7691 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7692 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7693 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7694 | && expr1.X_add_number < 0x8000) |
7695 | { | |
269137b2 | 7696 | load_delay_nop (); |
67c0d1eb RS |
7697 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7698 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7699 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7700 | register, the external symbol case ended with a load, |
7701 | so if the symbol turns out to not be external, and | |
7702 | the next instruction uses tempreg, an unnecessary nop | |
7703 | will be inserted. */ | |
252b5132 RH |
7704 | } |
7705 | else | |
7706 | { | |
7707 | if (breg == treg) | |
7708 | { | |
7709 | /* We must add in the base register now, as in the | |
f5040a92 | 7710 | external symbol case. */ |
9c2799c2 | 7711 | gas_assert (tempreg == AT); |
269137b2 | 7712 | load_delay_nop (); |
67c0d1eb | 7713 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7714 | treg, AT, breg); |
252b5132 RH |
7715 | tempreg = treg; |
7716 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7717 | it in in both cases. */ |
252b5132 RH |
7718 | breg = 0; |
7719 | } | |
7720 | ||
67c0d1eb RS |
7721 | macro_build_lui (&expr1, AT); |
7722 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7723 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7724 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7725 | tempreg, tempreg, AT); |
8fc2e39e | 7726 | used_at = 1; |
252b5132 | 7727 | } |
4d7206a2 | 7728 | relax_end (); |
252b5132 | 7729 | } |
0a44bf69 | 7730 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7731 | { |
f5040a92 AO |
7732 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7733 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7734 | int add_breg_early = 0; |
f5040a92 AO |
7735 | |
7736 | /* This is the large GOT case. If this is a reference to an | |
7737 | external symbol, and there is no constant, we want | |
7738 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7739 | add $tempreg,$tempreg,$gp | |
7740 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7741 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7742 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7743 | add $tempreg,$tempreg,$gp | |
7744 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7745 | ||
7746 | If we have a small constant, and this is a reference to | |
7747 | an external symbol, we want | |
7748 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7749 | add $tempreg,$tempreg,$gp | |
7750 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7751 | addi $tempreg,$tempreg,<constant> | |
7752 | ||
7753 | If we have a large constant, and this is a reference to | |
7754 | an external symbol, we want | |
7755 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7756 | addu $tempreg,$tempreg,$gp | |
7757 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7758 | lui $at,<hiconstant> | |
7759 | addi $at,$at,<loconstant> | |
7760 | add $tempreg,$tempreg,$at | |
7761 | ||
7762 | If we have NewABI, and we know it's a local symbol, we want | |
7763 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7764 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7765 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7766 | ||
4d7206a2 | 7767 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7768 | |
4d7206a2 | 7769 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7770 | offset_expr.X_add_number = 0; |
7771 | ||
1abe91b1 MR |
7772 | if (expr1.X_add_number == 0 && breg == 0 |
7773 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7774 | { |
7775 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7776 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7777 | } | |
df58fc94 | 7778 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7779 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7780 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7781 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7782 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7783 | |
7784 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7785 | ; |
f5040a92 AO |
7786 | else if (expr1.X_add_number >= -0x8000 |
7787 | && expr1.X_add_number < 0x8000) | |
7788 | { | |
67c0d1eb | 7789 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7790 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7791 | } |
ecd13cd3 | 7792 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7793 | { |
f5040a92 AO |
7794 | /* If we are going to add in a base register, and the |
7795 | target register and the base register are the same, | |
7796 | then we are using AT as a temporary register. Since | |
7797 | we want to load the constant into AT, we add our | |
7798 | current AT (from the global offset table) and the | |
7799 | register into the register now, and pretend we were | |
7800 | not using a base register. */ | |
7801 | if (breg != treg) | |
7802 | dreg = tempreg; | |
7803 | else | |
7804 | { | |
9c2799c2 | 7805 | gas_assert (tempreg == AT); |
67c0d1eb | 7806 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7807 | treg, AT, breg); |
f5040a92 | 7808 | dreg = treg; |
67c0d1eb | 7809 | add_breg_early = 1; |
f5040a92 AO |
7810 | } |
7811 | ||
f6a22291 | 7812 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7813 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7814 | |
f5040a92 AO |
7815 | used_at = 1; |
7816 | } | |
7817 | else | |
7818 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7819 | ||
4d7206a2 | 7820 | relax_switch (); |
f5040a92 | 7821 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7822 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7823 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7824 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7825 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7826 | if (add_breg_early) | |
f5040a92 | 7827 | { |
67c0d1eb | 7828 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7829 | treg, tempreg, breg); |
f5040a92 AO |
7830 | breg = 0; |
7831 | tempreg = treg; | |
7832 | } | |
4d7206a2 | 7833 | relax_end (); |
f5040a92 | 7834 | } |
252b5132 RH |
7835 | else |
7836 | abort (); | |
7837 | ||
7838 | if (breg != 0) | |
aed1a261 | 7839 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7840 | break; |
7841 | ||
52b6b6b9 | 7842 | case M_MSGSND: |
df58fc94 | 7843 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7844 | { |
7845 | unsigned long temp = (treg << 16) | (0x01); | |
7846 | macro_build (NULL, "c2", "C", temp); | |
7847 | } | |
c7af4273 | 7848 | break; |
52b6b6b9 JM |
7849 | |
7850 | case M_MSGLD: | |
df58fc94 | 7851 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7852 | { |
7853 | unsigned long temp = (0x02); | |
7854 | macro_build (NULL, "c2", "C", temp); | |
7855 | } | |
c7af4273 | 7856 | break; |
52b6b6b9 JM |
7857 | |
7858 | case M_MSGLD_T: | |
df58fc94 | 7859 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7860 | { |
7861 | unsigned long temp = (treg << 16) | (0x02); | |
7862 | macro_build (NULL, "c2", "C", temp); | |
7863 | } | |
c7af4273 | 7864 | break; |
52b6b6b9 JM |
7865 | |
7866 | case M_MSGWAIT: | |
df58fc94 | 7867 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7868 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7869 | break; |
52b6b6b9 JM |
7870 | |
7871 | case M_MSGWAIT_T: | |
df58fc94 | 7872 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7873 | { |
7874 | unsigned long temp = (treg << 16) | 0x03; | |
7875 | macro_build (NULL, "c2", "C", temp); | |
7876 | } | |
c7af4273 | 7877 | break; |
52b6b6b9 | 7878 | |
252b5132 RH |
7879 | case M_J_A: |
7880 | /* The j instruction may not be used in PIC code, since it | |
7881 | requires an absolute address. We convert it to a b | |
7882 | instruction. */ | |
7883 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7884 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7885 | else |
67c0d1eb | 7886 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7887 | break; |
252b5132 RH |
7888 | |
7889 | /* The jal instructions must be handled as macros because when | |
7890 | generating PIC code they expand to multi-instruction | |
7891 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7892 | case M_JALS_1: |
7893 | dreg = RA; | |
7894 | /* Fall through. */ | |
7895 | case M_JALS_2: | |
7896 | gas_assert (mips_opts.micromips); | |
7897 | jals = 1; | |
7898 | goto jal; | |
252b5132 RH |
7899 | case M_JAL_1: |
7900 | dreg = RA; | |
7901 | /* Fall through. */ | |
7902 | case M_JAL_2: | |
df58fc94 | 7903 | jal: |
3e722fb5 | 7904 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7905 | { |
7906 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
7907 | if (mips_opts.micromips |
7908 | && dreg == RA | |
7909 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7910 | macro_build (NULL, s, "mj", sreg); |
7911 | else | |
7912 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7913 | } | |
0a44bf69 | 7914 | else |
252b5132 | 7915 | { |
df58fc94 RS |
7916 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7917 | && mips_cprestore_offset >= 0); | |
7918 | ||
252b5132 RH |
7919 | if (sreg != PIC_CALL_REG) |
7920 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7921 | |
df58fc94 RS |
7922 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7923 | ? "jalrs" : "jalr"); | |
e64af278 MR |
7924 | if (mips_opts.micromips |
7925 | && dreg == RA | |
7926 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
7927 | macro_build (NULL, s, "mj", sreg); |
7928 | else | |
7929 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7930 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7931 | { |
6478892d TS |
7932 | if (mips_cprestore_offset < 0) |
7933 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7934 | else | |
7935 | { | |
90ecf173 | 7936 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7937 | { |
7938 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7939 | /* Quiet this warning. */ | |
7940 | mips_frame_reg_valid = 1; | |
7941 | } | |
90ecf173 | 7942 | if (!mips_cprestore_valid) |
7a621144 DJ |
7943 | { |
7944 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7945 | /* Quiet this warning. */ | |
7946 | mips_cprestore_valid = 1; | |
7947 | } | |
d3fca0b5 MR |
7948 | if (mips_opts.noreorder) |
7949 | macro_build (NULL, "nop", ""); | |
6478892d | 7950 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7951 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7952 | mips_gp_register, |
256ab948 TS |
7953 | mips_frame_reg, |
7954 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7955 | } |
252b5132 RH |
7956 | } |
7957 | } | |
252b5132 | 7958 | |
8fc2e39e | 7959 | break; |
252b5132 | 7960 | |
df58fc94 RS |
7961 | case M_JALS_A: |
7962 | gas_assert (mips_opts.micromips); | |
7963 | jals = 1; | |
7964 | /* Fall through. */ | |
252b5132 RH |
7965 | case M_JAL_A: |
7966 | if (mips_pic == NO_PIC) | |
df58fc94 | 7967 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7968 | else if (mips_pic == SVR4_PIC) |
7969 | { | |
7970 | /* If this is a reference to an external symbol, and we are | |
7971 | using a small GOT, we want | |
7972 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7973 | nop | |
f9419b05 | 7974 | jalr $ra,$25 |
252b5132 RH |
7975 | nop |
7976 | lw $gp,cprestore($sp) | |
7977 | The cprestore value is set using the .cprestore | |
7978 | pseudo-op. If we are using a big GOT, we want | |
7979 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7980 | addu $25,$25,$gp | |
7981 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7982 | nop | |
f9419b05 | 7983 | jalr $ra,$25 |
252b5132 RH |
7984 | nop |
7985 | lw $gp,cprestore($sp) | |
7986 | If the symbol is not external, we want | |
7987 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7988 | nop | |
7989 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7990 | jalr $ra,$25 |
252b5132 | 7991 | nop |
438c16b8 | 7992 | lw $gp,cprestore($sp) |
f5040a92 AO |
7993 | |
7994 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7995 | sequences above, minus nops, unless the symbol is local, | |
7996 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7997 | GOT_DISP. */ | |
438c16b8 | 7998 | if (HAVE_NEWABI) |
252b5132 | 7999 | { |
90ecf173 | 8000 | if (!mips_big_got) |
f5040a92 | 8001 | { |
4d7206a2 | 8002 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8003 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8004 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8005 | mips_gp_register); |
4d7206a2 | 8006 | relax_switch (); |
67c0d1eb RS |
8007 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8008 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8009 | mips_gp_register); |
8010 | relax_end (); | |
f5040a92 AO |
8011 | } |
8012 | else | |
8013 | { | |
4d7206a2 | 8014 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8015 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8016 | BFD_RELOC_MIPS_CALL_HI16); |
8017 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8018 | PIC_CALL_REG, mips_gp_register); | |
8019 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8020 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8021 | PIC_CALL_REG); | |
4d7206a2 | 8022 | relax_switch (); |
67c0d1eb RS |
8023 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8024 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8025 | mips_gp_register); | |
8026 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8027 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8028 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8029 | relax_end (); |
f5040a92 | 8030 | } |
684022ea | 8031 | |
df58fc94 | 8032 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8033 | } |
8034 | else | |
8035 | { | |
4d7206a2 | 8036 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8037 | if (!mips_big_got) |
438c16b8 | 8038 | { |
67c0d1eb RS |
8039 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8040 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8041 | mips_gp_register); |
269137b2 | 8042 | load_delay_nop (); |
4d7206a2 | 8043 | relax_switch (); |
438c16b8 | 8044 | } |
252b5132 | 8045 | else |
252b5132 | 8046 | { |
67c0d1eb RS |
8047 | int gpdelay; |
8048 | ||
8049 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8050 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8051 | BFD_RELOC_MIPS_CALL_HI16); |
8052 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8053 | PIC_CALL_REG, mips_gp_register); | |
8054 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8055 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8056 | PIC_CALL_REG); | |
269137b2 | 8057 | load_delay_nop (); |
4d7206a2 | 8058 | relax_switch (); |
67c0d1eb RS |
8059 | if (gpdelay) |
8060 | macro_build (NULL, "nop", ""); | |
252b5132 | 8061 | } |
67c0d1eb RS |
8062 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8063 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8064 | mips_gp_register); |
269137b2 | 8065 | load_delay_nop (); |
67c0d1eb RS |
8066 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8067 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8068 | relax_end (); |
df58fc94 | 8069 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8070 | |
6478892d TS |
8071 | if (mips_cprestore_offset < 0) |
8072 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8073 | else | |
8074 | { | |
90ecf173 | 8075 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8076 | { |
8077 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8078 | /* Quiet this warning. */ | |
8079 | mips_frame_reg_valid = 1; | |
8080 | } | |
90ecf173 | 8081 | if (!mips_cprestore_valid) |
7a621144 DJ |
8082 | { |
8083 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8084 | /* Quiet this warning. */ | |
8085 | mips_cprestore_valid = 1; | |
8086 | } | |
6478892d | 8087 | if (mips_opts.noreorder) |
67c0d1eb | 8088 | macro_build (NULL, "nop", ""); |
6478892d | 8089 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8090 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8091 | mips_gp_register, |
256ab948 TS |
8092 | mips_frame_reg, |
8093 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8094 | } |
252b5132 RH |
8095 | } |
8096 | } | |
0a44bf69 RS |
8097 | else if (mips_pic == VXWORKS_PIC) |
8098 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8099 | else |
8100 | abort (); | |
8101 | ||
8fc2e39e | 8102 | break; |
252b5132 | 8103 | |
dec0624d MR |
8104 | case M_ACLR_AB: |
8105 | ab = 1; | |
8106 | case M_ACLR_OB: | |
8107 | s = "aclr"; | |
8108 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8109 | fmt = "\\,~(b)"; | |
8110 | off12 = 1; | |
8111 | goto ld_st; | |
8112 | case M_ASET_AB: | |
8113 | ab = 1; | |
8114 | case M_ASET_OB: | |
8115 | s = "aset"; | |
8116 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8117 | fmt = "\\,~(b)"; | |
8118 | off12 = 1; | |
8119 | goto ld_st; | |
252b5132 | 8120 | case M_LB_AB: |
df58fc94 | 8121 | ab = 1; |
252b5132 | 8122 | s = "lb"; |
df58fc94 | 8123 | fmt = "t,o(b)"; |
252b5132 RH |
8124 | goto ld; |
8125 | case M_LBU_AB: | |
df58fc94 | 8126 | ab = 1; |
252b5132 | 8127 | s = "lbu"; |
df58fc94 | 8128 | fmt = "t,o(b)"; |
252b5132 RH |
8129 | goto ld; |
8130 | case M_LH_AB: | |
df58fc94 | 8131 | ab = 1; |
252b5132 | 8132 | s = "lh"; |
df58fc94 | 8133 | fmt = "t,o(b)"; |
252b5132 RH |
8134 | goto ld; |
8135 | case M_LHU_AB: | |
df58fc94 | 8136 | ab = 1; |
252b5132 | 8137 | s = "lhu"; |
df58fc94 | 8138 | fmt = "t,o(b)"; |
252b5132 RH |
8139 | goto ld; |
8140 | case M_LW_AB: | |
df58fc94 | 8141 | ab = 1; |
252b5132 | 8142 | s = "lw"; |
df58fc94 | 8143 | fmt = "t,o(b)"; |
252b5132 RH |
8144 | goto ld; |
8145 | case M_LWC0_AB: | |
df58fc94 RS |
8146 | ab = 1; |
8147 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8148 | s = "lwc0"; |
df58fc94 | 8149 | fmt = "E,o(b)"; |
bdaaa2e1 | 8150 | /* Itbl support may require additional care here. */ |
252b5132 | 8151 | coproc = 1; |
df58fc94 | 8152 | goto ld_st; |
252b5132 | 8153 | case M_LWC1_AB: |
df58fc94 | 8154 | ab = 1; |
252b5132 | 8155 | s = "lwc1"; |
df58fc94 | 8156 | fmt = "T,o(b)"; |
bdaaa2e1 | 8157 | /* Itbl support may require additional care here. */ |
252b5132 | 8158 | coproc = 1; |
df58fc94 | 8159 | goto ld_st; |
252b5132 | 8160 | case M_LWC2_AB: |
df58fc94 RS |
8161 | ab = 1; |
8162 | case M_LWC2_OB: | |
252b5132 | 8163 | s = "lwc2"; |
df58fc94 RS |
8164 | fmt = COP12_FMT; |
8165 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8166 | /* Itbl support may require additional care here. */ |
252b5132 | 8167 | coproc = 1; |
df58fc94 | 8168 | goto ld_st; |
252b5132 | 8169 | case M_LWC3_AB: |
df58fc94 RS |
8170 | ab = 1; |
8171 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8172 | s = "lwc3"; |
df58fc94 | 8173 | fmt = "E,o(b)"; |
bdaaa2e1 | 8174 | /* Itbl support may require additional care here. */ |
252b5132 | 8175 | coproc = 1; |
df58fc94 | 8176 | goto ld_st; |
252b5132 | 8177 | case M_LWL_AB: |
df58fc94 RS |
8178 | ab = 1; |
8179 | case M_LWL_OB: | |
252b5132 | 8180 | s = "lwl"; |
df58fc94 RS |
8181 | fmt = MEM12_FMT; |
8182 | off12 = mips_opts.micromips; | |
8183 | goto ld_st; | |
252b5132 | 8184 | case M_LWR_AB: |
df58fc94 RS |
8185 | ab = 1; |
8186 | case M_LWR_OB: | |
252b5132 | 8187 | s = "lwr"; |
df58fc94 RS |
8188 | fmt = MEM12_FMT; |
8189 | off12 = mips_opts.micromips; | |
8190 | goto ld_st; | |
252b5132 | 8191 | case M_LDC1_AB: |
df58fc94 | 8192 | ab = 1; |
252b5132 | 8193 | s = "ldc1"; |
df58fc94 | 8194 | fmt = "T,o(b)"; |
bdaaa2e1 | 8195 | /* Itbl support may require additional care here. */ |
252b5132 | 8196 | coproc = 1; |
df58fc94 | 8197 | goto ld_st; |
252b5132 | 8198 | case M_LDC2_AB: |
df58fc94 RS |
8199 | ab = 1; |
8200 | case M_LDC2_OB: | |
252b5132 | 8201 | s = "ldc2"; |
df58fc94 RS |
8202 | fmt = COP12_FMT; |
8203 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8204 | /* Itbl support may require additional care here. */ |
252b5132 | 8205 | coproc = 1; |
df58fc94 | 8206 | goto ld_st; |
c77c0862 RS |
8207 | case M_LQC2_AB: |
8208 | ab = 1; | |
8209 | s = "lqc2"; | |
8210 | fmt = "E,o(b)"; | |
8211 | /* Itbl support may require additional care here. */ | |
8212 | coproc = 1; | |
8213 | goto ld_st; | |
252b5132 | 8214 | case M_LDC3_AB: |
df58fc94 | 8215 | ab = 1; |
252b5132 | 8216 | s = "ldc3"; |
df58fc94 | 8217 | fmt = "E,o(b)"; |
bdaaa2e1 | 8218 | /* Itbl support may require additional care here. */ |
252b5132 | 8219 | coproc = 1; |
df58fc94 | 8220 | goto ld_st; |
252b5132 | 8221 | case M_LDL_AB: |
df58fc94 RS |
8222 | ab = 1; |
8223 | case M_LDL_OB: | |
252b5132 | 8224 | s = "ldl"; |
df58fc94 RS |
8225 | fmt = MEM12_FMT; |
8226 | off12 = mips_opts.micromips; | |
8227 | goto ld_st; | |
252b5132 | 8228 | case M_LDR_AB: |
df58fc94 RS |
8229 | ab = 1; |
8230 | case M_LDR_OB: | |
252b5132 | 8231 | s = "ldr"; |
df58fc94 RS |
8232 | fmt = MEM12_FMT; |
8233 | off12 = mips_opts.micromips; | |
8234 | goto ld_st; | |
252b5132 | 8235 | case M_LL_AB: |
df58fc94 RS |
8236 | ab = 1; |
8237 | case M_LL_OB: | |
252b5132 | 8238 | s = "ll"; |
df58fc94 RS |
8239 | fmt = MEM12_FMT; |
8240 | off12 = mips_opts.micromips; | |
252b5132 RH |
8241 | goto ld; |
8242 | case M_LLD_AB: | |
df58fc94 RS |
8243 | ab = 1; |
8244 | case M_LLD_OB: | |
252b5132 | 8245 | s = "lld"; |
df58fc94 RS |
8246 | fmt = MEM12_FMT; |
8247 | off12 = mips_opts.micromips; | |
252b5132 RH |
8248 | goto ld; |
8249 | case M_LWU_AB: | |
df58fc94 RS |
8250 | ab = 1; |
8251 | case M_LWU_OB: | |
252b5132 | 8252 | s = "lwu"; |
df58fc94 RS |
8253 | fmt = MEM12_FMT; |
8254 | off12 = mips_opts.micromips; | |
8255 | goto ld; | |
8256 | case M_LWP_AB: | |
8257 | ab = 1; | |
8258 | case M_LWP_OB: | |
8259 | gas_assert (mips_opts.micromips); | |
8260 | s = "lwp"; | |
8261 | fmt = "t,~(b)"; | |
8262 | off12 = 1; | |
8263 | lp = 1; | |
8264 | goto ld; | |
8265 | case M_LDP_AB: | |
8266 | ab = 1; | |
8267 | case M_LDP_OB: | |
8268 | gas_assert (mips_opts.micromips); | |
8269 | s = "ldp"; | |
8270 | fmt = "t,~(b)"; | |
8271 | off12 = 1; | |
8272 | lp = 1; | |
8273 | goto ld; | |
8274 | case M_LWM_AB: | |
8275 | ab = 1; | |
8276 | case M_LWM_OB: | |
8277 | gas_assert (mips_opts.micromips); | |
8278 | s = "lwm"; | |
8279 | fmt = "n,~(b)"; | |
8280 | off12 = 1; | |
8281 | goto ld_st; | |
8282 | case M_LDM_AB: | |
8283 | ab = 1; | |
8284 | case M_LDM_OB: | |
8285 | gas_assert (mips_opts.micromips); | |
8286 | s = "ldm"; | |
8287 | fmt = "n,~(b)"; | |
8288 | off12 = 1; | |
8289 | goto ld_st; | |
8290 | ||
252b5132 | 8291 | ld: |
f19ccbda MR |
8292 | /* We don't want to use $0 as tempreg. */ |
8293 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8294 | goto ld_st; |
252b5132 | 8295 | else |
df58fc94 RS |
8296 | tempreg = treg + lp; |
8297 | goto ld_noat; | |
8298 | ||
252b5132 | 8299 | case M_SB_AB: |
df58fc94 | 8300 | ab = 1; |
252b5132 | 8301 | s = "sb"; |
df58fc94 RS |
8302 | fmt = "t,o(b)"; |
8303 | goto ld_st; | |
252b5132 | 8304 | case M_SH_AB: |
df58fc94 | 8305 | ab = 1; |
252b5132 | 8306 | s = "sh"; |
df58fc94 RS |
8307 | fmt = "t,o(b)"; |
8308 | goto ld_st; | |
252b5132 | 8309 | case M_SW_AB: |
df58fc94 | 8310 | ab = 1; |
252b5132 | 8311 | s = "sw"; |
df58fc94 RS |
8312 | fmt = "t,o(b)"; |
8313 | goto ld_st; | |
252b5132 | 8314 | case M_SWC0_AB: |
df58fc94 RS |
8315 | ab = 1; |
8316 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8317 | s = "swc0"; |
df58fc94 | 8318 | fmt = "E,o(b)"; |
bdaaa2e1 | 8319 | /* Itbl support may require additional care here. */ |
252b5132 | 8320 | coproc = 1; |
df58fc94 | 8321 | goto ld_st; |
252b5132 | 8322 | case M_SWC1_AB: |
df58fc94 | 8323 | ab = 1; |
252b5132 | 8324 | s = "swc1"; |
df58fc94 | 8325 | fmt = "T,o(b)"; |
bdaaa2e1 | 8326 | /* Itbl support may require additional care here. */ |
252b5132 | 8327 | coproc = 1; |
df58fc94 | 8328 | goto ld_st; |
252b5132 | 8329 | case M_SWC2_AB: |
df58fc94 RS |
8330 | ab = 1; |
8331 | case M_SWC2_OB: | |
252b5132 | 8332 | s = "swc2"; |
df58fc94 RS |
8333 | fmt = COP12_FMT; |
8334 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8335 | /* Itbl support may require additional care here. */ |
252b5132 | 8336 | coproc = 1; |
df58fc94 | 8337 | goto ld_st; |
252b5132 | 8338 | case M_SWC3_AB: |
df58fc94 RS |
8339 | ab = 1; |
8340 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8341 | s = "swc3"; |
df58fc94 | 8342 | fmt = "E,o(b)"; |
bdaaa2e1 | 8343 | /* Itbl support may require additional care here. */ |
252b5132 | 8344 | coproc = 1; |
df58fc94 | 8345 | goto ld_st; |
252b5132 | 8346 | case M_SWL_AB: |
df58fc94 RS |
8347 | ab = 1; |
8348 | case M_SWL_OB: | |
252b5132 | 8349 | s = "swl"; |
df58fc94 RS |
8350 | fmt = MEM12_FMT; |
8351 | off12 = mips_opts.micromips; | |
8352 | goto ld_st; | |
252b5132 | 8353 | case M_SWR_AB: |
df58fc94 RS |
8354 | ab = 1; |
8355 | case M_SWR_OB: | |
252b5132 | 8356 | s = "swr"; |
df58fc94 RS |
8357 | fmt = MEM12_FMT; |
8358 | off12 = mips_opts.micromips; | |
8359 | goto ld_st; | |
252b5132 | 8360 | case M_SC_AB: |
df58fc94 RS |
8361 | ab = 1; |
8362 | case M_SC_OB: | |
252b5132 | 8363 | s = "sc"; |
df58fc94 RS |
8364 | fmt = MEM12_FMT; |
8365 | off12 = mips_opts.micromips; | |
8366 | goto ld_st; | |
252b5132 | 8367 | case M_SCD_AB: |
df58fc94 RS |
8368 | ab = 1; |
8369 | case M_SCD_OB: | |
252b5132 | 8370 | s = "scd"; |
df58fc94 RS |
8371 | fmt = MEM12_FMT; |
8372 | off12 = mips_opts.micromips; | |
8373 | goto ld_st; | |
d43b4baf | 8374 | case M_CACHE_AB: |
df58fc94 RS |
8375 | ab = 1; |
8376 | case M_CACHE_OB: | |
d43b4baf | 8377 | s = "cache"; |
df58fc94 RS |
8378 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8379 | off12 = mips_opts.micromips; | |
8380 | goto ld_st; | |
3eebd5eb | 8381 | case M_PREF_AB: |
df58fc94 RS |
8382 | ab = 1; |
8383 | case M_PREF_OB: | |
3eebd5eb | 8384 | s = "pref"; |
df58fc94 RS |
8385 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8386 | off12 = mips_opts.micromips; | |
8387 | goto ld_st; | |
252b5132 | 8388 | case M_SDC1_AB: |
df58fc94 | 8389 | ab = 1; |
252b5132 | 8390 | s = "sdc1"; |
df58fc94 | 8391 | fmt = "T,o(b)"; |
252b5132 | 8392 | coproc = 1; |
bdaaa2e1 | 8393 | /* Itbl support may require additional care here. */ |
df58fc94 | 8394 | goto ld_st; |
252b5132 | 8395 | case M_SDC2_AB: |
df58fc94 RS |
8396 | ab = 1; |
8397 | case M_SDC2_OB: | |
252b5132 | 8398 | s = "sdc2"; |
df58fc94 RS |
8399 | fmt = COP12_FMT; |
8400 | off12 = mips_opts.micromips; | |
c77c0862 RS |
8401 | /* Itbl support may require additional care here. */ |
8402 | coproc = 1; | |
8403 | goto ld_st; | |
8404 | case M_SQC2_AB: | |
8405 | ab = 1; | |
8406 | s = "sqc2"; | |
8407 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8408 | /* Itbl support may require additional care here. */ |
252b5132 | 8409 | coproc = 1; |
df58fc94 | 8410 | goto ld_st; |
252b5132 | 8411 | case M_SDC3_AB: |
df58fc94 RS |
8412 | ab = 1; |
8413 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8414 | s = "sdc3"; |
df58fc94 | 8415 | fmt = "E,o(b)"; |
bdaaa2e1 | 8416 | /* Itbl support may require additional care here. */ |
252b5132 | 8417 | coproc = 1; |
df58fc94 | 8418 | goto ld_st; |
252b5132 | 8419 | case M_SDL_AB: |
df58fc94 RS |
8420 | ab = 1; |
8421 | case M_SDL_OB: | |
252b5132 | 8422 | s = "sdl"; |
df58fc94 RS |
8423 | fmt = MEM12_FMT; |
8424 | off12 = mips_opts.micromips; | |
8425 | goto ld_st; | |
252b5132 | 8426 | case M_SDR_AB: |
df58fc94 RS |
8427 | ab = 1; |
8428 | case M_SDR_OB: | |
252b5132 | 8429 | s = "sdr"; |
df58fc94 RS |
8430 | fmt = MEM12_FMT; |
8431 | off12 = mips_opts.micromips; | |
8432 | goto ld_st; | |
8433 | case M_SWP_AB: | |
8434 | ab = 1; | |
8435 | case M_SWP_OB: | |
8436 | gas_assert (mips_opts.micromips); | |
8437 | s = "swp"; | |
8438 | fmt = "t,~(b)"; | |
8439 | off12 = 1; | |
8440 | goto ld_st; | |
8441 | case M_SDP_AB: | |
8442 | ab = 1; | |
8443 | case M_SDP_OB: | |
8444 | gas_assert (mips_opts.micromips); | |
8445 | s = "sdp"; | |
8446 | fmt = "t,~(b)"; | |
8447 | off12 = 1; | |
8448 | goto ld_st; | |
8449 | case M_SWM_AB: | |
8450 | ab = 1; | |
8451 | case M_SWM_OB: | |
8452 | gas_assert (mips_opts.micromips); | |
8453 | s = "swm"; | |
8454 | fmt = "n,~(b)"; | |
8455 | off12 = 1; | |
8456 | goto ld_st; | |
8457 | case M_SDM_AB: | |
8458 | ab = 1; | |
8459 | case M_SDM_OB: | |
8460 | gas_assert (mips_opts.micromips); | |
8461 | s = "sdm"; | |
8462 | fmt = "n,~(b)"; | |
8463 | off12 = 1; | |
8464 | ||
8465 | ld_st: | |
8fc2e39e TS |
8466 | tempreg = AT; |
8467 | used_at = 1; | |
df58fc94 | 8468 | ld_noat: |
252b5132 RH |
8469 | if (offset_expr.X_op != O_constant |
8470 | && offset_expr.X_op != O_symbol) | |
8471 | { | |
f71d0d44 | 8472 | as_bad (_("Expression too complex")); |
252b5132 RH |
8473 | offset_expr.X_op = O_constant; |
8474 | } | |
8475 | ||
2051e8c4 MR |
8476 | if (HAVE_32BIT_ADDRESSES |
8477 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8478 | { |
8479 | char value [32]; | |
8480 | ||
8481 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8482 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8483 | } |
2051e8c4 | 8484 | |
252b5132 RH |
8485 | /* A constant expression in PIC code can be handled just as it |
8486 | is in non PIC code. */ | |
aed1a261 RS |
8487 | if (offset_expr.X_op == O_constant) |
8488 | { | |
df58fc94 RS |
8489 | int hipart = 0; |
8490 | ||
842f8b2a | 8491 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8492 | normalize_address_expr (&expr1); |
df58fc94 | 8493 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8494 | { |
8495 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8496 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8497 | hipart = 1; |
8498 | } | |
8499 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8500 | { | |
8501 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8502 | & ~(bfd_vma) 0xfff); | |
8503 | hipart = 1; | |
8504 | } | |
8505 | if (hipart) | |
8506 | { | |
842f8b2a MR |
8507 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8508 | if (breg != 0) | |
8509 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8510 | tempreg, tempreg, breg); | |
8511 | breg = tempreg; | |
8512 | } | |
dd6a37e7 AP |
8513 | if (off0) |
8514 | { | |
8515 | if (offset_expr.X_add_number == 0) | |
8516 | tempreg = breg; | |
8517 | else | |
8518 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8519 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8520 | macro_build (NULL, s, fmt, treg, tempreg); | |
8521 | } | |
8522 | else if (!off12) | |
df58fc94 RS |
8523 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8524 | else | |
8525 | macro_build (NULL, s, fmt, | |
8526 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8527 | } | |
dd6a37e7 | 8528 | else if (off12 || off0) |
df58fc94 | 8529 | { |
dd6a37e7 AP |
8530 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8531 | for a low-part relocation, so load the whole address into | |
8532 | the auxillary register. In the case of "A(b)" addresses, | |
8533 | we first load absolute address "A" into the register and | |
8534 | then add base register "b". In the case of "o(b)" addresses, | |
8535 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8536 | offset_reloc already contains the relocations associated |
8537 | with "o". */ | |
8538 | if (ab) | |
8539 | { | |
8540 | load_address (tempreg, &offset_expr, &used_at); | |
8541 | if (breg != 0) | |
8542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8543 | tempreg, tempreg, breg); | |
8544 | } | |
8545 | else | |
8546 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8547 | tempreg, breg, -1, | |
8548 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8549 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8550 | if (off0) |
8551 | macro_build (NULL, s, fmt, treg, tempreg); | |
8552 | else | |
8553 | macro_build (NULL, s, fmt, | |
8554 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8555 | } |
8556 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8557 | { |
8558 | /* If this is a reference to a GP relative symbol, and there | |
8559 | is no base register, we want | |
cdf6fd85 | 8560 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8561 | Otherwise, if there is no base register, we want |
8562 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8563 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8564 | If we have a constant, we need two instructions anyhow, | |
8565 | so we always use the latter form. | |
8566 | ||
8567 | If we have a base register, and this is a reference to a | |
8568 | GP relative symbol, we want | |
8569 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8570 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8571 | Otherwise we want |
8572 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8573 | addu $tempreg,$tempreg,$breg | |
8574 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8575 | With a constant we always use the latter case. |
76b3015f | 8576 | |
d6bc6245 TS |
8577 | With 64bit address space and no base register and $at usable, |
8578 | we want | |
8579 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8580 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8581 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8582 | dsll32 $tempreg,0 | |
8583 | daddu $tempreg,$at | |
8584 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8585 | If we have a base register, we want | |
8586 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8587 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8588 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8589 | daddu $at,$breg | |
8590 | dsll32 $tempreg,0 | |
8591 | daddu $tempreg,$at | |
8592 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8593 | ||
8594 | Without $at we can't generate the optimal path for superscalar | |
8595 | processors here since this would require two temporary registers. | |
8596 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8597 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8598 | dsll $tempreg,16 | |
8599 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8600 | dsll $tempreg,16 | |
8601 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8602 | If we have a base register, we want | |
8603 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8604 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8605 | dsll $tempreg,16 | |
8606 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8607 | dsll $tempreg,16 | |
8608 | daddu $tempreg,$tempreg,$breg | |
8609 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8610 | |
6caf9ef4 | 8611 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8612 | the same sequence as in 32bit address space. */ |
8613 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8614 | { |
aed1a261 | 8615 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8616 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8617 | { | |
8618 | relax_start (offset_expr.X_add_symbol); | |
8619 | if (breg == 0) | |
8620 | { | |
8621 | macro_build (&offset_expr, s, fmt, treg, | |
8622 | BFD_RELOC_GPREL16, mips_gp_register); | |
8623 | } | |
8624 | else | |
8625 | { | |
8626 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8627 | tempreg, breg, mips_gp_register); | |
8628 | macro_build (&offset_expr, s, fmt, treg, | |
8629 | BFD_RELOC_GPREL16, tempreg); | |
8630 | } | |
8631 | relax_switch (); | |
8632 | } | |
d6bc6245 | 8633 | |
741fe287 | 8634 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8635 | { |
df58fc94 | 8636 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8637 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8638 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8639 | BFD_RELOC_HI16_S); |
8640 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8641 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8642 | if (breg != 0) |
67c0d1eb | 8643 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8644 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8645 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8646 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8647 | tempreg); | |
d6bc6245 TS |
8648 | used_at = 1; |
8649 | } | |
8650 | else | |
8651 | { | |
df58fc94 | 8652 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8653 | BFD_RELOC_MIPS_HIGHEST); |
8654 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8655 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8656 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8657 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8658 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8659 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8660 | if (breg != 0) |
67c0d1eb | 8661 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8662 | tempreg, tempreg, breg); |
67c0d1eb | 8663 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8664 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8665 | } |
6caf9ef4 TS |
8666 | |
8667 | if (mips_relax.sequence) | |
8668 | relax_end (); | |
8fc2e39e | 8669 | break; |
d6bc6245 | 8670 | } |
256ab948 | 8671 | |
252b5132 RH |
8672 | if (breg == 0) |
8673 | { | |
67c0d1eb | 8674 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8675 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8676 | { |
4d7206a2 | 8677 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8678 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8679 | mips_gp_register); | |
4d7206a2 | 8680 | relax_switch (); |
252b5132 | 8681 | } |
67c0d1eb RS |
8682 | macro_build_lui (&offset_expr, tempreg); |
8683 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8684 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8685 | if (mips_relax.sequence) |
8686 | relax_end (); | |
252b5132 RH |
8687 | } |
8688 | else | |
8689 | { | |
67c0d1eb | 8690 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8691 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8692 | { |
4d7206a2 | 8693 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8694 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8695 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8696 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8697 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8698 | relax_switch (); |
252b5132 | 8699 | } |
67c0d1eb RS |
8700 | macro_build_lui (&offset_expr, tempreg); |
8701 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8702 | tempreg, tempreg, breg); |
67c0d1eb | 8703 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8704 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8705 | if (mips_relax.sequence) |
8706 | relax_end (); | |
252b5132 RH |
8707 | } |
8708 | } | |
0a44bf69 | 8709 | else if (!mips_big_got) |
252b5132 | 8710 | { |
ed6fb7bd | 8711 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8712 | |
252b5132 RH |
8713 | /* If this is a reference to an external symbol, we want |
8714 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8715 | nop | |
8716 | <op> $treg,0($tempreg) | |
8717 | Otherwise we want | |
8718 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8719 | nop | |
8720 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8721 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8722 | |
8723 | For NewABI, we want | |
8724 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8725 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8726 | ||
252b5132 RH |
8727 | If there is a base register, we add it to $tempreg before |
8728 | the <op>. If there is a constant, we stick it in the | |
8729 | <op> instruction. We don't handle constants larger than | |
8730 | 16 bits, because we have no way to load the upper 16 bits | |
8731 | (actually, we could handle them for the subset of cases | |
8732 | in which we are not using $at). */ | |
9c2799c2 | 8733 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8734 | if (HAVE_NEWABI) |
8735 | { | |
67c0d1eb RS |
8736 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8737 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8738 | if (breg != 0) |
67c0d1eb | 8739 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8740 | tempreg, tempreg, breg); |
67c0d1eb | 8741 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8742 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8743 | break; |
8744 | } | |
252b5132 RH |
8745 | expr1.X_add_number = offset_expr.X_add_number; |
8746 | offset_expr.X_add_number = 0; | |
8747 | if (expr1.X_add_number < -0x8000 | |
8748 | || expr1.X_add_number >= 0x8000) | |
8749 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8750 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8751 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8752 | load_delay_nop (); |
4d7206a2 RS |
8753 | relax_start (offset_expr.X_add_symbol); |
8754 | relax_switch (); | |
67c0d1eb RS |
8755 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8756 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8757 | relax_end (); |
252b5132 | 8758 | if (breg != 0) |
67c0d1eb | 8759 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8760 | tempreg, tempreg, breg); |
67c0d1eb | 8761 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8762 | } |
0a44bf69 | 8763 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8764 | { |
67c0d1eb | 8765 | int gpdelay; |
252b5132 RH |
8766 | |
8767 | /* If this is a reference to an external symbol, we want | |
8768 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8769 | addu $tempreg,$tempreg,$gp | |
8770 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8771 | <op> $treg,0($tempreg) | |
8772 | Otherwise we want | |
8773 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8774 | nop | |
8775 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8776 | <op> $treg,0($tempreg) | |
8777 | If there is a base register, we add it to $tempreg before | |
8778 | the <op>. If there is a constant, we stick it in the | |
8779 | <op> instruction. We don't handle constants larger than | |
8780 | 16 bits, because we have no way to load the upper 16 bits | |
8781 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8782 | in which we are not using $at). */ |
9c2799c2 | 8783 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8784 | expr1.X_add_number = offset_expr.X_add_number; |
8785 | offset_expr.X_add_number = 0; | |
8786 | if (expr1.X_add_number < -0x8000 | |
8787 | || expr1.X_add_number >= 0x8000) | |
8788 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8789 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8790 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8791 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8792 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8794 | mips_gp_register); | |
8795 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8796 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8797 | relax_switch (); |
67c0d1eb RS |
8798 | if (gpdelay) |
8799 | macro_build (NULL, "nop", ""); | |
8800 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8801 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8802 | load_delay_nop (); |
67c0d1eb RS |
8803 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8804 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8805 | relax_end (); |
8806 | ||
252b5132 | 8807 | if (breg != 0) |
67c0d1eb | 8808 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8809 | tempreg, tempreg, breg); |
67c0d1eb | 8810 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8811 | } |
0a44bf69 | 8812 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8813 | { |
f5040a92 AO |
8814 | /* If this is a reference to an external symbol, we want |
8815 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8816 | add $tempreg,$tempreg,$gp | |
8817 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8818 | <op> $treg,<ofst>($tempreg) | |
8819 | Otherwise, for local symbols, we want: | |
8820 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8821 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8822 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8823 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8824 | offset_expr.X_add_number = 0; |
8825 | if (expr1.X_add_number < -0x8000 | |
8826 | || expr1.X_add_number >= 0x8000) | |
8827 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8828 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8829 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8830 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8832 | mips_gp_register); | |
8833 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8834 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8835 | if (breg != 0) |
67c0d1eb | 8836 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8837 | tempreg, tempreg, breg); |
67c0d1eb | 8838 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8839 | |
4d7206a2 | 8840 | relax_switch (); |
f5040a92 | 8841 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8842 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8843 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8844 | if (breg != 0) |
67c0d1eb | 8845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8846 | tempreg, tempreg, breg); |
67c0d1eb | 8847 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8848 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8849 | relax_end (); |
f5040a92 | 8850 | } |
252b5132 RH |
8851 | else |
8852 | abort (); | |
8853 | ||
252b5132 RH |
8854 | break; |
8855 | ||
8856 | case M_LI: | |
8857 | case M_LI_S: | |
67c0d1eb | 8858 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8859 | break; |
252b5132 RH |
8860 | |
8861 | case M_DLI: | |
67c0d1eb | 8862 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8863 | break; |
252b5132 RH |
8864 | |
8865 | case M_LI_SS: | |
8866 | if (imm_expr.X_op == O_constant) | |
8867 | { | |
8fc2e39e | 8868 | used_at = 1; |
67c0d1eb RS |
8869 | load_register (AT, &imm_expr, 0); |
8870 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8871 | break; |
8872 | } | |
8873 | else | |
8874 | { | |
9c2799c2 | 8875 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8876 | && strcmp (segment_name (S_GET_SEGMENT |
8877 | (offset_expr.X_add_symbol)), | |
8878 | ".lit4") == 0 | |
8879 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8880 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8881 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8882 | break; |
252b5132 RH |
8883 | } |
8884 | ||
8885 | case M_LI_D: | |
ca4e0257 RS |
8886 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8887 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8888 | order 32 bits of the value and the low order 32 bits are either | |
8889 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8890 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8891 | { | |
ca4e0257 | 8892 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8893 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8894 | else |
8895 | { | |
8896 | int hreg, lreg; | |
8897 | ||
8898 | if (target_big_endian) | |
8899 | { | |
8900 | hreg = treg; | |
8901 | lreg = treg + 1; | |
8902 | } | |
8903 | else | |
8904 | { | |
8905 | hreg = treg + 1; | |
8906 | lreg = treg; | |
8907 | } | |
8908 | ||
8909 | if (hreg <= 31) | |
67c0d1eb | 8910 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8911 | if (lreg <= 31) |
8912 | { | |
8913 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8914 | move_register (lreg, 0); |
252b5132 RH |
8915 | else |
8916 | { | |
9c2799c2 | 8917 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8918 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8919 | } |
8920 | } | |
8921 | } | |
8fc2e39e | 8922 | break; |
252b5132 RH |
8923 | } |
8924 | ||
8925 | /* We know that sym is in the .rdata section. First we get the | |
8926 | upper 16 bits of the address. */ | |
8927 | if (mips_pic == NO_PIC) | |
8928 | { | |
67c0d1eb | 8929 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8930 | used_at = 1; |
252b5132 | 8931 | } |
0a44bf69 | 8932 | else |
252b5132 | 8933 | { |
67c0d1eb RS |
8934 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8935 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8936 | used_at = 1; |
252b5132 | 8937 | } |
bdaaa2e1 | 8938 | |
252b5132 | 8939 | /* Now we load the register(s). */ |
ca4e0257 | 8940 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8941 | { |
8942 | used_at = 1; | |
8943 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8944 | } | |
252b5132 RH |
8945 | else |
8946 | { | |
8fc2e39e | 8947 | used_at = 1; |
67c0d1eb | 8948 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8949 | if (treg != RA) |
252b5132 RH |
8950 | { |
8951 | /* FIXME: How in the world do we deal with the possible | |
8952 | overflow here? */ | |
8953 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8954 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8955 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8956 | } |
8957 | } | |
252b5132 RH |
8958 | break; |
8959 | ||
8960 | case M_LI_DD: | |
ca4e0257 RS |
8961 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8962 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8963 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8964 | the value and the low order 32 bits are either zero or in | |
8965 | OFFSET_EXPR. */ | |
252b5132 RH |
8966 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8967 | { | |
8fc2e39e | 8968 | used_at = 1; |
67c0d1eb | 8969 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8970 | if (HAVE_64BIT_FPRS) |
8971 | { | |
9c2799c2 | 8972 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8973 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8974 | } |
252b5132 RH |
8975 | else |
8976 | { | |
67c0d1eb | 8977 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8978 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8979 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8980 | else |
8981 | { | |
9c2799c2 | 8982 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8983 | load_register (AT, &offset_expr, 0); |
8984 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8985 | } |
8986 | } | |
8987 | break; | |
8988 | } | |
8989 | ||
9c2799c2 | 8990 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8991 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8992 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8993 | if (strcmp (s, ".lit8") == 0) | |
8994 | { | |
0aa27725 | 8995 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 8996 | { |
67c0d1eb | 8997 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8998 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8999 | break; |
252b5132 | 9000 | } |
c9914766 | 9001 | breg = mips_gp_register; |
252b5132 RH |
9002 | r = BFD_RELOC_MIPS_LITERAL; |
9003 | goto dob; | |
9004 | } | |
9005 | else | |
9006 | { | |
9c2799c2 | 9007 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9008 | used_at = 1; |
0a44bf69 | 9009 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9010 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9011 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9012 | else |
9013 | { | |
9014 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9015 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9016 | } |
bdaaa2e1 | 9017 | |
0aa27725 | 9018 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9019 | { |
67c0d1eb RS |
9020 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9021 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9022 | break; |
9023 | } | |
9024 | breg = AT; | |
9025 | r = BFD_RELOC_LO16; | |
9026 | goto dob; | |
9027 | } | |
9028 | ||
9029 | case M_L_DOB: | |
252b5132 RH |
9030 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9031 | to adjust when loading from memory. */ | |
9032 | r = BFD_RELOC_LO16; | |
9033 | dob: | |
df58fc94 | 9034 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9035 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9036 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9037 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9038 | /* FIXME: A possible overflow which I don't know how to deal |
9039 | with. */ | |
9040 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9041 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9042 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9043 | break; |
9044 | ||
c4a68bea | 9045 | case M_S_DOB: |
df58fc94 | 9046 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9047 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9048 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9049 | to adjust when storing to memory. */ | |
9050 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9051 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9052 | offset_expr.X_add_number += 4; | |
9053 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9054 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9055 | break; | |
9056 | ||
252b5132 | 9057 | case M_L_DAB: |
df58fc94 | 9058 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9059 | /* |
9060 | * The MIPS assembler seems to check for X_add_number not | |
9061 | * being double aligned and generating: | |
9062 | * lui at,%hi(foo+1) | |
9063 | * addu at,at,v1 | |
9064 | * addiu at,at,%lo(foo+1) | |
9065 | * lwc1 f2,0(at) | |
9066 | * lwc1 f3,4(at) | |
9067 | * But, the resulting address is the same after relocation so why | |
9068 | * generate the extra instruction? | |
9069 | */ | |
bdaaa2e1 | 9070 | /* Itbl support may require additional care here. */ |
252b5132 | 9071 | coproc = 1; |
df58fc94 | 9072 | fmt = "T,o(b)"; |
0aa27725 | 9073 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9074 | { |
9075 | s = "ldc1"; | |
df58fc94 | 9076 | goto ld_st; |
252b5132 | 9077 | } |
252b5132 | 9078 | s = "lwc1"; |
252b5132 RH |
9079 | goto ldd_std; |
9080 | ||
9081 | case M_S_DAB: | |
df58fc94 RS |
9082 | gas_assert (!mips_opts.micromips); |
9083 | /* Itbl support may require additional care here. */ | |
9084 | coproc = 1; | |
9085 | fmt = "T,o(b)"; | |
0aa27725 | 9086 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9087 | { |
9088 | s = "sdc1"; | |
df58fc94 | 9089 | goto ld_st; |
252b5132 | 9090 | } |
252b5132 | 9091 | s = "swc1"; |
252b5132 RH |
9092 | goto ldd_std; |
9093 | ||
e407c74b NC |
9094 | case M_LQ_AB: |
9095 | fmt = "t,o(b)"; | |
9096 | s = "lq"; | |
9097 | goto ld; | |
9098 | ||
9099 | case M_SQ_AB: | |
9100 | fmt = "t,o(b)"; | |
9101 | s = "sq"; | |
9102 | goto ld_st; | |
9103 | ||
252b5132 | 9104 | case M_LD_AB: |
df58fc94 | 9105 | fmt = "t,o(b)"; |
ca4e0257 | 9106 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9107 | { |
9108 | s = "ld"; | |
9109 | goto ld; | |
9110 | } | |
252b5132 | 9111 | s = "lw"; |
252b5132 RH |
9112 | goto ldd_std; |
9113 | ||
9114 | case M_SD_AB: | |
df58fc94 | 9115 | fmt = "t,o(b)"; |
ca4e0257 | 9116 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9117 | { |
9118 | s = "sd"; | |
df58fc94 | 9119 | goto ld_st; |
252b5132 | 9120 | } |
252b5132 | 9121 | s = "sw"; |
252b5132 RH |
9122 | |
9123 | ldd_std: | |
9124 | if (offset_expr.X_op != O_symbol | |
9125 | && offset_expr.X_op != O_constant) | |
9126 | { | |
f71d0d44 | 9127 | as_bad (_("Expression too complex")); |
252b5132 RH |
9128 | offset_expr.X_op = O_constant; |
9129 | } | |
9130 | ||
2051e8c4 MR |
9131 | if (HAVE_32BIT_ADDRESSES |
9132 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9133 | { |
9134 | char value [32]; | |
9135 | ||
9136 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9137 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9138 | } |
2051e8c4 | 9139 | |
252b5132 RH |
9140 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9141 | to adjust when loading from memory. We set coproc if we must | |
9142 | load $fn+1 first. */ | |
bdaaa2e1 | 9143 | /* Itbl support may require additional care here. */ |
90ecf173 | 9144 | if (!target_big_endian) |
252b5132 RH |
9145 | coproc = 0; |
9146 | ||
90ecf173 | 9147 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9148 | { |
9149 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9150 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9151 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9152 | If we have a base register, we use this |
9153 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9154 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9155 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9156 | If this is not a GP relative symbol, we want |
9157 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9158 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9159 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9160 | If there is a base register, we add it to $at after the | |
9161 | lui instruction. If there is a constant, we always use | |
9162 | the last case. */ | |
39a59cf8 MR |
9163 | if (offset_expr.X_op == O_symbol |
9164 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9165 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9166 | { |
4d7206a2 | 9167 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9168 | if (breg == 0) |
9169 | { | |
c9914766 | 9170 | tempreg = mips_gp_register; |
252b5132 RH |
9171 | } |
9172 | else | |
9173 | { | |
67c0d1eb | 9174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9175 | AT, breg, mips_gp_register); |
252b5132 | 9176 | tempreg = AT; |
252b5132 RH |
9177 | used_at = 1; |
9178 | } | |
9179 | ||
beae10d5 | 9180 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9181 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9182 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9183 | offset_expr.X_add_number += 4; |
9184 | ||
9185 | /* Set mips_optimize to 2 to avoid inserting an | |
9186 | undesired nop. */ | |
9187 | hold_mips_optimize = mips_optimize; | |
9188 | mips_optimize = 2; | |
beae10d5 | 9189 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9190 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9191 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9192 | mips_optimize = hold_mips_optimize; |
9193 | ||
4d7206a2 | 9194 | relax_switch (); |
252b5132 | 9195 | |
0970e49e | 9196 | offset_expr.X_add_number -= 4; |
252b5132 | 9197 | } |
8fc2e39e | 9198 | used_at = 1; |
67c0d1eb | 9199 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9200 | if (breg != 0) |
67c0d1eb | 9201 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9202 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9203 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9204 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9205 | /* FIXME: How do we handle overflow here? */ |
9206 | offset_expr.X_add_number += 4; | |
beae10d5 | 9207 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9208 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9209 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9210 | if (mips_relax.sequence) |
9211 | relax_end (); | |
bdaaa2e1 | 9212 | } |
0a44bf69 | 9213 | else if (!mips_big_got) |
252b5132 | 9214 | { |
252b5132 RH |
9215 | /* If this is a reference to an external symbol, we want |
9216 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9217 | nop | |
9218 | <op> $treg,0($at) | |
9219 | <op> $treg+1,4($at) | |
9220 | Otherwise we want | |
9221 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9222 | nop | |
9223 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9224 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9225 | If there is a base register we add it to $at before the | |
9226 | lwc1 instructions. If there is a constant we include it | |
9227 | in the lwc1 instructions. */ | |
9228 | used_at = 1; | |
9229 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9230 | if (expr1.X_add_number < -0x8000 |
9231 | || expr1.X_add_number >= 0x8000 - 4) | |
9232 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9233 | load_got_offset (AT, &offset_expr); |
269137b2 | 9234 | load_delay_nop (); |
252b5132 | 9235 | if (breg != 0) |
67c0d1eb | 9236 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9237 | |
9238 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9239 | nop. */ | |
9240 | hold_mips_optimize = mips_optimize; | |
9241 | mips_optimize = 2; | |
4d7206a2 | 9242 | |
beae10d5 | 9243 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9244 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9245 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9246 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9247 | expr1.X_add_number += 4; |
67c0d1eb RS |
9248 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9249 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9250 | relax_switch (); |
67c0d1eb RS |
9251 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9252 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9253 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9254 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9255 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9256 | relax_end (); |
252b5132 | 9257 | |
4d7206a2 | 9258 | mips_optimize = hold_mips_optimize; |
252b5132 | 9259 | } |
0a44bf69 | 9260 | else if (mips_big_got) |
252b5132 | 9261 | { |
67c0d1eb | 9262 | int gpdelay; |
252b5132 RH |
9263 | |
9264 | /* If this is a reference to an external symbol, we want | |
9265 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9266 | addu $at,$at,$gp | |
9267 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9268 | nop | |
9269 | <op> $treg,0($at) | |
9270 | <op> $treg+1,4($at) | |
9271 | Otherwise we want | |
9272 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9273 | nop | |
9274 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9275 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9276 | If there is a base register we add it to $at before the | |
9277 | lwc1 instructions. If there is a constant we include it | |
9278 | in the lwc1 instructions. */ | |
9279 | used_at = 1; | |
9280 | expr1.X_add_number = offset_expr.X_add_number; | |
9281 | offset_expr.X_add_number = 0; | |
9282 | if (expr1.X_add_number < -0x8000 | |
9283 | || expr1.X_add_number >= 0x8000 - 4) | |
9284 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9285 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9286 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9287 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9288 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9289 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9290 | AT, AT, mips_gp_register); |
67c0d1eb | 9291 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9292 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9293 | load_delay_nop (); |
252b5132 | 9294 | if (breg != 0) |
67c0d1eb | 9295 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9296 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9297 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9298 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9299 | expr1.X_add_number += 4; |
9300 | ||
9301 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9302 | nop. */ | |
9303 | hold_mips_optimize = mips_optimize; | |
9304 | mips_optimize = 2; | |
beae10d5 | 9305 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9306 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9307 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9308 | mips_optimize = hold_mips_optimize; |
9309 | expr1.X_add_number -= 4; | |
9310 | ||
4d7206a2 RS |
9311 | relax_switch (); |
9312 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9313 | if (gpdelay) |
9314 | macro_build (NULL, "nop", ""); | |
9315 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9316 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9317 | load_delay_nop (); |
252b5132 | 9318 | if (breg != 0) |
67c0d1eb | 9319 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9320 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9321 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9322 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9323 | offset_expr.X_add_number += 4; |
252b5132 RH |
9324 | |
9325 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9326 | nop. */ | |
9327 | hold_mips_optimize = mips_optimize; | |
9328 | mips_optimize = 2; | |
beae10d5 | 9329 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9330 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9331 | BFD_RELOC_LO16, AT); | |
252b5132 | 9332 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9333 | relax_end (); |
252b5132 | 9334 | } |
252b5132 RH |
9335 | else |
9336 | abort (); | |
9337 | ||
252b5132 RH |
9338 | break; |
9339 | ||
9340 | case M_LD_OB: | |
704897fb | 9341 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9342 | goto sd_ob; |
9343 | case M_SD_OB: | |
704897fb | 9344 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9345 | sd_ob: |
4614d845 MR |
9346 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9347 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9348 | breg); | |
704897fb MR |
9349 | if (!HAVE_64BIT_GPRS) |
9350 | { | |
9351 | offset_expr.X_add_number += 4; | |
9352 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9353 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9354 | breg); | |
704897fb | 9355 | } |
8fc2e39e | 9356 | break; |
252b5132 | 9357 | |
dd6a37e7 AP |
9358 | |
9359 | case M_SAA_AB: | |
9360 | ab = 1; | |
9361 | case M_SAA_OB: | |
9362 | s = "saa"; | |
9363 | off0 = 1; | |
9364 | fmt = "t,(b)"; | |
9365 | goto ld_st; | |
9366 | case M_SAAD_AB: | |
9367 | ab = 1; | |
9368 | case M_SAAD_OB: | |
9369 | s = "saad"; | |
9370 | off0 = 1; | |
9371 | fmt = "t,(b)"; | |
9372 | goto ld_st; | |
9373 | ||
252b5132 RH |
9374 | /* New code added to support COPZ instructions. |
9375 | This code builds table entries out of the macros in mip_opcodes. | |
9376 | R4000 uses interlocks to handle coproc delays. | |
9377 | Other chips (like the R3000) require nops to be inserted for delays. | |
9378 | ||
f72c8c98 | 9379 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9380 | In order to fill delay slots for non-interlocked chips, |
9381 | we must have a way to specify delays based on the coprocessor. | |
9382 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9383 | What are the side-effects of the cop instruction? | |
9384 | What cache support might we have and what are its effects? | |
9385 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9386 | What registers are read/set/modified? |
252b5132 RH |
9387 | |
9388 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9389 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9390 | |
9391 | case M_COP0: | |
9392 | s = "c0"; | |
9393 | goto copz; | |
9394 | case M_COP1: | |
9395 | s = "c1"; | |
9396 | goto copz; | |
9397 | case M_COP2: | |
9398 | s = "c2"; | |
9399 | goto copz; | |
9400 | case M_COP3: | |
9401 | s = "c3"; | |
9402 | copz: | |
df58fc94 | 9403 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9404 | /* For now we just do C (same as Cz). The parameter will be |
9405 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9406 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9407 | break; |
252b5132 | 9408 | |
ea1fb5dc | 9409 | case M_MOVE: |
67c0d1eb | 9410 | move_register (dreg, sreg); |
8fc2e39e | 9411 | break; |
ea1fb5dc | 9412 | |
252b5132 RH |
9413 | case M_DMUL: |
9414 | dbl = 1; | |
9415 | case M_MUL: | |
e407c74b NC |
9416 | if (mips_opts.arch == CPU_R5900) |
9417 | { | |
9418 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9419 | } | |
9420 | else | |
9421 | { | |
67c0d1eb | 9422 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9423 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9424 | } |
8fc2e39e | 9425 | break; |
252b5132 RH |
9426 | |
9427 | case M_DMUL_I: | |
9428 | dbl = 1; | |
9429 | case M_MUL_I: | |
9430 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9431 | not trying to be that fancy. GCC should do this for us | |
9432 | anyway. */ | |
8fc2e39e | 9433 | used_at = 1; |
67c0d1eb RS |
9434 | load_register (AT, &imm_expr, dbl); |
9435 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9436 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9437 | break; |
9438 | ||
9439 | case M_DMULO_I: | |
9440 | dbl = 1; | |
9441 | case M_MULO_I: | |
9442 | imm = 1; | |
9443 | goto do_mulo; | |
9444 | ||
9445 | case M_DMULO: | |
9446 | dbl = 1; | |
9447 | case M_MULO: | |
9448 | do_mulo: | |
7d10b47d | 9449 | start_noreorder (); |
8fc2e39e | 9450 | used_at = 1; |
252b5132 | 9451 | if (imm) |
67c0d1eb RS |
9452 | load_register (AT, &imm_expr, dbl); |
9453 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9454 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9455 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9456 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9457 | if (mips_trap) |
df58fc94 | 9458 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9459 | else |
9460 | { | |
df58fc94 RS |
9461 | if (mips_opts.micromips) |
9462 | micromips_label_expr (&label_expr); | |
9463 | else | |
9464 | label_expr.X_add_number = 8; | |
9465 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9466 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9467 | macro_build (NULL, "break", BRK_FMT, 6); |
9468 | if (mips_opts.micromips) | |
9469 | micromips_add_label (); | |
252b5132 | 9470 | } |
7d10b47d | 9471 | end_noreorder (); |
df58fc94 | 9472 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9473 | break; |
9474 | ||
9475 | case M_DMULOU_I: | |
9476 | dbl = 1; | |
9477 | case M_MULOU_I: | |
9478 | imm = 1; | |
9479 | goto do_mulou; | |
9480 | ||
9481 | case M_DMULOU: | |
9482 | dbl = 1; | |
9483 | case M_MULOU: | |
9484 | do_mulou: | |
7d10b47d | 9485 | start_noreorder (); |
8fc2e39e | 9486 | used_at = 1; |
252b5132 | 9487 | if (imm) |
67c0d1eb RS |
9488 | load_register (AT, &imm_expr, dbl); |
9489 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9490 | sreg, imm ? AT : treg); |
df58fc94 RS |
9491 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9492 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9493 | if (mips_trap) |
df58fc94 | 9494 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9495 | else |
9496 | { | |
df58fc94 RS |
9497 | if (mips_opts.micromips) |
9498 | micromips_label_expr (&label_expr); | |
9499 | else | |
9500 | label_expr.X_add_number = 8; | |
9501 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9502 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9503 | macro_build (NULL, "break", BRK_FMT, 6); |
9504 | if (mips_opts.micromips) | |
9505 | micromips_add_label (); | |
252b5132 | 9506 | } |
7d10b47d | 9507 | end_noreorder (); |
252b5132 RH |
9508 | break; |
9509 | ||
771c7ce4 | 9510 | case M_DROL: |
fef14a42 | 9511 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9512 | { |
9513 | if (dreg == sreg) | |
9514 | { | |
9515 | tempreg = AT; | |
9516 | used_at = 1; | |
9517 | } | |
9518 | else | |
9519 | { | |
9520 | tempreg = dreg; | |
82dd0097 | 9521 | } |
67c0d1eb RS |
9522 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9523 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9524 | break; |
82dd0097 | 9525 | } |
8fc2e39e | 9526 | used_at = 1; |
c80c840e | 9527 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9528 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9529 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9530 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9531 | break; |
9532 | ||
252b5132 | 9533 | case M_ROL: |
fef14a42 | 9534 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9535 | { |
9536 | if (dreg == sreg) | |
9537 | { | |
9538 | tempreg = AT; | |
9539 | used_at = 1; | |
9540 | } | |
9541 | else | |
9542 | { | |
9543 | tempreg = dreg; | |
82dd0097 | 9544 | } |
67c0d1eb RS |
9545 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9546 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9547 | break; |
82dd0097 | 9548 | } |
8fc2e39e | 9549 | used_at = 1; |
c80c840e | 9550 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9551 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9552 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9553 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9554 | break; |
9555 | ||
771c7ce4 TS |
9556 | case M_DROL_I: |
9557 | { | |
9558 | unsigned int rot; | |
91d6fa6a NC |
9559 | char *l; |
9560 | char *rr; | |
771c7ce4 TS |
9561 | |
9562 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9563 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9564 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9565 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9566 | { |
9567 | rot = (64 - rot) & 0x3f; | |
9568 | if (rot >= 32) | |
df58fc94 | 9569 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9570 | else |
df58fc94 | 9571 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9572 | break; |
60b63b72 | 9573 | } |
483fc7cd | 9574 | if (rot == 0) |
483fc7cd | 9575 | { |
df58fc94 | 9576 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9577 | break; |
483fc7cd | 9578 | } |
82dd0097 | 9579 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9580 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9581 | rot &= 0x1f; |
8fc2e39e | 9582 | used_at = 1; |
df58fc94 RS |
9583 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9584 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9585 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9586 | } |
9587 | break; | |
9588 | ||
252b5132 | 9589 | case M_ROL_I: |
771c7ce4 TS |
9590 | { |
9591 | unsigned int rot; | |
9592 | ||
9593 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9594 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9595 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9596 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9597 | { |
df58fc94 | 9598 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9599 | break; |
60b63b72 | 9600 | } |
483fc7cd | 9601 | if (rot == 0) |
483fc7cd | 9602 | { |
df58fc94 | 9603 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9604 | break; |
483fc7cd | 9605 | } |
8fc2e39e | 9606 | used_at = 1; |
df58fc94 RS |
9607 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9608 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9609 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9610 | } |
9611 | break; | |
9612 | ||
9613 | case M_DROR: | |
fef14a42 | 9614 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9615 | { |
67c0d1eb | 9616 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9617 | break; |
82dd0097 | 9618 | } |
8fc2e39e | 9619 | used_at = 1; |
c80c840e | 9620 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9621 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9622 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9623 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9624 | break; |
9625 | ||
9626 | case M_ROR: | |
fef14a42 | 9627 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9628 | { |
67c0d1eb | 9629 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9630 | break; |
82dd0097 | 9631 | } |
8fc2e39e | 9632 | used_at = 1; |
c80c840e | 9633 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9634 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9635 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9636 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9637 | break; |
9638 | ||
771c7ce4 TS |
9639 | case M_DROR_I: |
9640 | { | |
9641 | unsigned int rot; | |
91d6fa6a NC |
9642 | char *l; |
9643 | char *rr; | |
771c7ce4 TS |
9644 | |
9645 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9646 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9647 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9648 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9649 | { |
9650 | if (rot >= 32) | |
df58fc94 | 9651 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9652 | else |
df58fc94 | 9653 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9654 | break; |
82dd0097 | 9655 | } |
483fc7cd | 9656 | if (rot == 0) |
483fc7cd | 9657 | { |
df58fc94 | 9658 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9659 | break; |
483fc7cd | 9660 | } |
91d6fa6a | 9661 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9662 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9663 | rot &= 0x1f; | |
8fc2e39e | 9664 | used_at = 1; |
df58fc94 RS |
9665 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9666 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9667 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9668 | } |
9669 | break; | |
9670 | ||
252b5132 | 9671 | case M_ROR_I: |
771c7ce4 TS |
9672 | { |
9673 | unsigned int rot; | |
9674 | ||
9675 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9676 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9677 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9678 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9679 | { |
df58fc94 | 9680 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9681 | break; |
82dd0097 | 9682 | } |
483fc7cd | 9683 | if (rot == 0) |
483fc7cd | 9684 | { |
df58fc94 | 9685 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9686 | break; |
483fc7cd | 9687 | } |
8fc2e39e | 9688 | used_at = 1; |
df58fc94 RS |
9689 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9690 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9691 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9692 | } |
252b5132 RH |
9693 | break; |
9694 | ||
252b5132 RH |
9695 | case M_SEQ: |
9696 | if (sreg == 0) | |
67c0d1eb | 9697 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9698 | else if (treg == 0) |
67c0d1eb | 9699 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9700 | else |
9701 | { | |
67c0d1eb RS |
9702 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9703 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9704 | } |
8fc2e39e | 9705 | break; |
252b5132 RH |
9706 | |
9707 | case M_SEQ_I: | |
9708 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9709 | { | |
67c0d1eb | 9710 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9711 | break; |
252b5132 RH |
9712 | } |
9713 | if (sreg == 0) | |
9714 | { | |
9715 | as_warn (_("Instruction %s: result is always false"), | |
9716 | ip->insn_mo->name); | |
67c0d1eb | 9717 | move_register (dreg, 0); |
8fc2e39e | 9718 | break; |
252b5132 | 9719 | } |
dd3cbb7e NC |
9720 | if (CPU_HAS_SEQ (mips_opts.arch) |
9721 | && -512 <= imm_expr.X_add_number | |
9722 | && imm_expr.X_add_number < 512) | |
9723 | { | |
9724 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9725 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9726 | break; |
9727 | } | |
252b5132 RH |
9728 | if (imm_expr.X_op == O_constant |
9729 | && imm_expr.X_add_number >= 0 | |
9730 | && imm_expr.X_add_number < 0x10000) | |
9731 | { | |
67c0d1eb | 9732 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9733 | } |
9734 | else if (imm_expr.X_op == O_constant | |
9735 | && imm_expr.X_add_number > -0x8000 | |
9736 | && imm_expr.X_add_number < 0) | |
9737 | { | |
9738 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9739 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9740 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9741 | } |
dd3cbb7e NC |
9742 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9743 | { | |
9744 | used_at = 1; | |
9745 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9746 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9747 | break; | |
9748 | } | |
252b5132 RH |
9749 | else |
9750 | { | |
67c0d1eb RS |
9751 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9752 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9753 | used_at = 1; |
9754 | } | |
67c0d1eb | 9755 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9756 | break; |
252b5132 RH |
9757 | |
9758 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9759 | s = "slt"; | |
9760 | goto sge; | |
9761 | case M_SGEU: | |
9762 | s = "sltu"; | |
9763 | sge: | |
67c0d1eb RS |
9764 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9765 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9766 | break; |
252b5132 RH |
9767 | |
9768 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9769 | case M_SGEU_I: | |
9770 | if (imm_expr.X_op == O_constant | |
9771 | && imm_expr.X_add_number >= -0x8000 | |
9772 | && imm_expr.X_add_number < 0x8000) | |
9773 | { | |
67c0d1eb RS |
9774 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9775 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9776 | } |
9777 | else | |
9778 | { | |
67c0d1eb RS |
9779 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9780 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9781 | dreg, sreg, AT); | |
252b5132 RH |
9782 | used_at = 1; |
9783 | } | |
67c0d1eb | 9784 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9785 | break; |
252b5132 RH |
9786 | |
9787 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9788 | s = "slt"; | |
9789 | goto sgt; | |
9790 | case M_SGTU: | |
9791 | s = "sltu"; | |
9792 | sgt: | |
67c0d1eb | 9793 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9794 | break; |
252b5132 RH |
9795 | |
9796 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9797 | s = "slt"; | |
9798 | goto sgti; | |
9799 | case M_SGTU_I: | |
9800 | s = "sltu"; | |
9801 | sgti: | |
8fc2e39e | 9802 | used_at = 1; |
67c0d1eb RS |
9803 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9804 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9805 | break; |
9806 | ||
2396cfb9 | 9807 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9808 | s = "slt"; |
9809 | goto sle; | |
9810 | case M_SLEU: | |
9811 | s = "sltu"; | |
9812 | sle: | |
67c0d1eb RS |
9813 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9814 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9815 | break; |
252b5132 | 9816 | |
2396cfb9 | 9817 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9818 | s = "slt"; |
9819 | goto slei; | |
9820 | case M_SLEU_I: | |
9821 | s = "sltu"; | |
9822 | slei: | |
8fc2e39e | 9823 | used_at = 1; |
67c0d1eb RS |
9824 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9825 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9826 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9827 | break; |
9828 | ||
9829 | case M_SLT_I: | |
9830 | if (imm_expr.X_op == O_constant | |
9831 | && imm_expr.X_add_number >= -0x8000 | |
9832 | && imm_expr.X_add_number < 0x8000) | |
9833 | { | |
67c0d1eb | 9834 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9835 | break; |
252b5132 | 9836 | } |
8fc2e39e | 9837 | used_at = 1; |
67c0d1eb RS |
9838 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9839 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9840 | break; |
9841 | ||
9842 | case M_SLTU_I: | |
9843 | if (imm_expr.X_op == O_constant | |
9844 | && imm_expr.X_add_number >= -0x8000 | |
9845 | && imm_expr.X_add_number < 0x8000) | |
9846 | { | |
67c0d1eb | 9847 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9848 | BFD_RELOC_LO16); |
8fc2e39e | 9849 | break; |
252b5132 | 9850 | } |
8fc2e39e | 9851 | used_at = 1; |
67c0d1eb RS |
9852 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9853 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9854 | break; |
9855 | ||
9856 | case M_SNE: | |
9857 | if (sreg == 0) | |
67c0d1eb | 9858 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9859 | else if (treg == 0) |
67c0d1eb | 9860 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9861 | else |
9862 | { | |
67c0d1eb RS |
9863 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9864 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9865 | } |
8fc2e39e | 9866 | break; |
252b5132 RH |
9867 | |
9868 | case M_SNE_I: | |
9869 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9870 | { | |
67c0d1eb | 9871 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9872 | break; |
252b5132 RH |
9873 | } |
9874 | if (sreg == 0) | |
9875 | { | |
9876 | as_warn (_("Instruction %s: result is always true"), | |
9877 | ip->insn_mo->name); | |
67c0d1eb RS |
9878 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9879 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9880 | break; |
252b5132 | 9881 | } |
dd3cbb7e NC |
9882 | if (CPU_HAS_SEQ (mips_opts.arch) |
9883 | && -512 <= imm_expr.X_add_number | |
9884 | && imm_expr.X_add_number < 512) | |
9885 | { | |
9886 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9887 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9888 | break; |
9889 | } | |
252b5132 RH |
9890 | if (imm_expr.X_op == O_constant |
9891 | && imm_expr.X_add_number >= 0 | |
9892 | && imm_expr.X_add_number < 0x10000) | |
9893 | { | |
67c0d1eb | 9894 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9895 | } |
9896 | else if (imm_expr.X_op == O_constant | |
9897 | && imm_expr.X_add_number > -0x8000 | |
9898 | && imm_expr.X_add_number < 0) | |
9899 | { | |
9900 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9901 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9902 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9903 | } |
dd3cbb7e NC |
9904 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9905 | { | |
9906 | used_at = 1; | |
9907 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9908 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9909 | break; | |
9910 | } | |
252b5132 RH |
9911 | else |
9912 | { | |
67c0d1eb RS |
9913 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9914 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9915 | used_at = 1; |
9916 | } | |
67c0d1eb | 9917 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9918 | break; |
252b5132 | 9919 | |
df58fc94 RS |
9920 | case M_SUB_I: |
9921 | s = "addi"; | |
9922 | s2 = "sub"; | |
9923 | goto do_subi; | |
9924 | case M_SUBU_I: | |
9925 | s = "addiu"; | |
9926 | s2 = "subu"; | |
9927 | goto do_subi; | |
252b5132 RH |
9928 | case M_DSUB_I: |
9929 | dbl = 1; | |
df58fc94 RS |
9930 | s = "daddi"; |
9931 | s2 = "dsub"; | |
9932 | if (!mips_opts.micromips) | |
9933 | goto do_subi; | |
252b5132 | 9934 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9935 | && imm_expr.X_add_number > -0x200 |
9936 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9937 | { |
df58fc94 | 9938 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9939 | break; |
252b5132 | 9940 | } |
df58fc94 | 9941 | goto do_subi_i; |
252b5132 RH |
9942 | case M_DSUBU_I: |
9943 | dbl = 1; | |
df58fc94 RS |
9944 | s = "daddiu"; |
9945 | s2 = "dsubu"; | |
9946 | do_subi: | |
252b5132 RH |
9947 | if (imm_expr.X_op == O_constant |
9948 | && imm_expr.X_add_number > -0x8000 | |
9949 | && imm_expr.X_add_number <= 0x8000) | |
9950 | { | |
9951 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9952 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9953 | break; |
252b5132 | 9954 | } |
df58fc94 | 9955 | do_subi_i: |
8fc2e39e | 9956 | used_at = 1; |
67c0d1eb | 9957 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9958 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9959 | break; |
9960 | ||
9961 | case M_TEQ_I: | |
9962 | s = "teq"; | |
9963 | goto trap; | |
9964 | case M_TGE_I: | |
9965 | s = "tge"; | |
9966 | goto trap; | |
9967 | case M_TGEU_I: | |
9968 | s = "tgeu"; | |
9969 | goto trap; | |
9970 | case M_TLT_I: | |
9971 | s = "tlt"; | |
9972 | goto trap; | |
9973 | case M_TLTU_I: | |
9974 | s = "tltu"; | |
9975 | goto trap; | |
9976 | case M_TNE_I: | |
9977 | s = "tne"; | |
9978 | trap: | |
8fc2e39e | 9979 | used_at = 1; |
67c0d1eb RS |
9980 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9981 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9982 | break; |
9983 | ||
252b5132 | 9984 | case M_TRUNCWS: |
43841e91 | 9985 | case M_TRUNCWD: |
df58fc94 | 9986 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9987 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9988 | used_at = 1; |
252b5132 RH |
9989 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9990 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9991 | ||
9992 | /* | |
9993 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9994 | * or is there a reason for it? | |
9995 | */ | |
7d10b47d | 9996 | start_noreorder (); |
67c0d1eb RS |
9997 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9998 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9999 | macro_build (NULL, "nop", ""); | |
252b5132 | 10000 | expr1.X_add_number = 3; |
67c0d1eb | 10001 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10002 | expr1.X_add_number = 2; |
67c0d1eb RS |
10003 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10004 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10005 | macro_build (NULL, "nop", ""); | |
10006 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10007 | dreg, sreg); | |
10008 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10009 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10010 | end_noreorder (); |
252b5132 RH |
10011 | break; |
10012 | ||
df58fc94 RS |
10013 | case M_ULH_A: |
10014 | ab = 1; | |
252b5132 RH |
10015 | case M_ULH: |
10016 | s = "lb"; | |
df58fc94 RS |
10017 | s2 = "lbu"; |
10018 | off = 1; | |
10019 | goto uld_st; | |
10020 | case M_ULHU_A: | |
10021 | ab = 1; | |
252b5132 RH |
10022 | case M_ULHU: |
10023 | s = "lbu"; | |
df58fc94 RS |
10024 | s2 = "lbu"; |
10025 | off = 1; | |
10026 | goto uld_st; | |
10027 | case M_ULW_A: | |
10028 | ab = 1; | |
10029 | case M_ULW: | |
10030 | s = "lwl"; | |
10031 | s2 = "lwr"; | |
10032 | off12 = mips_opts.micromips; | |
10033 | off = 3; | |
10034 | goto uld_st; | |
10035 | case M_ULD_A: | |
10036 | ab = 1; | |
252b5132 RH |
10037 | case M_ULD: |
10038 | s = "ldl"; | |
10039 | s2 = "ldr"; | |
df58fc94 | 10040 | off12 = mips_opts.micromips; |
252b5132 | 10041 | off = 7; |
df58fc94 RS |
10042 | goto uld_st; |
10043 | case M_USH_A: | |
10044 | ab = 1; | |
10045 | case M_USH: | |
10046 | s = "sb"; | |
10047 | s2 = "sb"; | |
10048 | off = 1; | |
10049 | ust = 1; | |
10050 | goto uld_st; | |
10051 | case M_USW_A: | |
10052 | ab = 1; | |
10053 | case M_USW: | |
10054 | s = "swl"; | |
10055 | s2 = "swr"; | |
10056 | off12 = mips_opts.micromips; | |
252b5132 | 10057 | off = 3; |
df58fc94 RS |
10058 | ust = 1; |
10059 | goto uld_st; | |
10060 | case M_USD_A: | |
10061 | ab = 1; | |
10062 | case M_USD: | |
10063 | s = "sdl"; | |
10064 | s2 = "sdr"; | |
10065 | off12 = mips_opts.micromips; | |
10066 | off = 7; | |
10067 | ust = 1; | |
10068 | ||
10069 | uld_st: | |
10070 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10071 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10072 | |
10073 | ep = &offset_expr; | |
10074 | expr1.X_add_number = 0; | |
10075 | if (ab) | |
10076 | { | |
10077 | used_at = 1; | |
10078 | tempreg = AT; | |
10079 | load_address (tempreg, ep, &used_at); | |
10080 | if (breg != 0) | |
10081 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10082 | tempreg, tempreg, breg); | |
10083 | breg = tempreg; | |
10084 | tempreg = treg; | |
10085 | ep = &expr1; | |
10086 | } | |
10087 | else if (off12 | |
10088 | && (offset_expr.X_op != O_constant | |
10089 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10090 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10091 | { | |
10092 | used_at = 1; | |
10093 | tempreg = AT; | |
10094 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10095 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10096 | breg = tempreg; | |
10097 | tempreg = treg; | |
10098 | ep = &expr1; | |
10099 | } | |
10100 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10101 | { |
10102 | used_at = 1; | |
10103 | tempreg = AT; | |
10104 | } | |
252b5132 | 10105 | else |
df58fc94 | 10106 | tempreg = treg; |
af22f5b2 | 10107 | |
df58fc94 RS |
10108 | if (off == 1) |
10109 | goto ulh_sh; | |
252b5132 | 10110 | |
90ecf173 | 10111 | if (!target_big_endian) |
df58fc94 RS |
10112 | ep->X_add_number += off; |
10113 | if (!off12) | |
10114 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10115 | else |
df58fc94 RS |
10116 | macro_build (NULL, s, "t,~(b)", |
10117 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10118 | ||
90ecf173 | 10119 | if (!target_big_endian) |
df58fc94 | 10120 | ep->X_add_number -= off; |
252b5132 | 10121 | else |
df58fc94 RS |
10122 | ep->X_add_number += off; |
10123 | if (!off12) | |
10124 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10125 | else | |
10126 | macro_build (NULL, s2, "t,~(b)", | |
10127 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10128 | |
df58fc94 RS |
10129 | /* If necessary, move the result in tempreg to the final destination. */ |
10130 | if (!ust && treg != tempreg) | |
10131 | { | |
10132 | /* Protect second load's delay slot. */ | |
10133 | load_delay_nop (); | |
10134 | move_register (treg, tempreg); | |
10135 | } | |
8fc2e39e | 10136 | break; |
252b5132 | 10137 | |
df58fc94 | 10138 | ulh_sh: |
d6bc6245 | 10139 | used_at = 1; |
df58fc94 RS |
10140 | if (target_big_endian == ust) |
10141 | ep->X_add_number += off; | |
10142 | tempreg = ust || ab ? treg : AT; | |
10143 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10144 | ||
10145 | /* For halfword transfers we need a temporary register to shuffle | |
10146 | bytes. Unfortunately for M_USH_A we have none available before | |
10147 | the next store as AT holds the base address. We deal with this | |
10148 | case by clobbering TREG and then restoring it as with ULH. */ | |
10149 | tempreg = ust == ab ? treg : AT; | |
10150 | if (ust) | |
10151 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10152 | ||
10153 | if (target_big_endian == ust) | |
10154 | ep->X_add_number -= off; | |
252b5132 | 10155 | else |
df58fc94 RS |
10156 | ep->X_add_number += off; |
10157 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10158 | |
df58fc94 RS |
10159 | /* For M_USH_A re-retrieve the LSB. */ |
10160 | if (ust && ab) | |
10161 | { | |
10162 | if (target_big_endian) | |
10163 | ep->X_add_number += off; | |
10164 | else | |
10165 | ep->X_add_number -= off; | |
10166 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10167 | } | |
10168 | /* For ULH and M_USH_A OR the LSB in. */ | |
10169 | if (!ust || ab) | |
10170 | { | |
10171 | tempreg = !ab ? AT : treg; | |
10172 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10173 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10174 | } | |
252b5132 RH |
10175 | break; |
10176 | ||
10177 | default: | |
10178 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10179 | are added dynamically. */ |
252b5132 RH |
10180 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10181 | break; | |
10182 | } | |
741fe287 | 10183 | if (!mips_opts.at && used_at) |
8fc2e39e | 10184 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10185 | } |
10186 | ||
10187 | /* Implement macros in mips16 mode. */ | |
10188 | ||
10189 | static void | |
17a2f251 | 10190 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10191 | { |
10192 | int mask; | |
10193 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10194 | expressionS expr1; |
10195 | int dbl; | |
10196 | const char *s, *s2, *s3; | |
10197 | ||
10198 | mask = ip->insn_mo->mask; | |
10199 | ||
bf12938e RS |
10200 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10201 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10202 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10203 | |
252b5132 RH |
10204 | expr1.X_op = O_constant; |
10205 | expr1.X_op_symbol = NULL; | |
10206 | expr1.X_add_symbol = NULL; | |
10207 | expr1.X_add_number = 1; | |
10208 | ||
10209 | dbl = 0; | |
10210 | ||
10211 | switch (mask) | |
10212 | { | |
10213 | default: | |
b37df7c4 | 10214 | abort (); |
252b5132 RH |
10215 | |
10216 | case M_DDIV_3: | |
10217 | dbl = 1; | |
10218 | case M_DIV_3: | |
10219 | s = "mflo"; | |
10220 | goto do_div3; | |
10221 | case M_DREM_3: | |
10222 | dbl = 1; | |
10223 | case M_REM_3: | |
10224 | s = "mfhi"; | |
10225 | do_div3: | |
7d10b47d | 10226 | start_noreorder (); |
67c0d1eb | 10227 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10228 | expr1.X_add_number = 2; |
67c0d1eb RS |
10229 | macro_build (&expr1, "bnez", "x,p", yreg); |
10230 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10231 | |
252b5132 RH |
10232 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10233 | since that causes an overflow. We should do that as well, | |
10234 | but I don't see how to do the comparisons without a temporary | |
10235 | register. */ | |
7d10b47d | 10236 | end_noreorder (); |
67c0d1eb | 10237 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10238 | break; |
10239 | ||
10240 | case M_DIVU_3: | |
10241 | s = "divu"; | |
10242 | s2 = "mflo"; | |
10243 | goto do_divu3; | |
10244 | case M_REMU_3: | |
10245 | s = "divu"; | |
10246 | s2 = "mfhi"; | |
10247 | goto do_divu3; | |
10248 | case M_DDIVU_3: | |
10249 | s = "ddivu"; | |
10250 | s2 = "mflo"; | |
10251 | goto do_divu3; | |
10252 | case M_DREMU_3: | |
10253 | s = "ddivu"; | |
10254 | s2 = "mfhi"; | |
10255 | do_divu3: | |
7d10b47d | 10256 | start_noreorder (); |
67c0d1eb | 10257 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10258 | expr1.X_add_number = 2; |
67c0d1eb RS |
10259 | macro_build (&expr1, "bnez", "x,p", yreg); |
10260 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10261 | end_noreorder (); |
67c0d1eb | 10262 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10263 | break; |
10264 | ||
10265 | case M_DMUL: | |
10266 | dbl = 1; | |
10267 | case M_MUL: | |
67c0d1eb RS |
10268 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10269 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10270 | break; |
252b5132 RH |
10271 | |
10272 | case M_DSUBU_I: | |
10273 | dbl = 1; | |
10274 | goto do_subu; | |
10275 | case M_SUBU_I: | |
10276 | do_subu: | |
10277 | if (imm_expr.X_op != O_constant) | |
10278 | as_bad (_("Unsupported large constant")); | |
10279 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10280 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10281 | break; |
10282 | ||
10283 | case M_SUBU_I_2: | |
10284 | if (imm_expr.X_op != O_constant) | |
10285 | as_bad (_("Unsupported large constant")); | |
10286 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10287 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10288 | break; |
10289 | ||
10290 | case M_DSUBU_I_2: | |
10291 | if (imm_expr.X_op != O_constant) | |
10292 | as_bad (_("Unsupported large constant")); | |
10293 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10294 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10295 | break; |
10296 | ||
10297 | case M_BEQ: | |
10298 | s = "cmp"; | |
10299 | s2 = "bteqz"; | |
10300 | goto do_branch; | |
10301 | case M_BNE: | |
10302 | s = "cmp"; | |
10303 | s2 = "btnez"; | |
10304 | goto do_branch; | |
10305 | case M_BLT: | |
10306 | s = "slt"; | |
10307 | s2 = "btnez"; | |
10308 | goto do_branch; | |
10309 | case M_BLTU: | |
10310 | s = "sltu"; | |
10311 | s2 = "btnez"; | |
10312 | goto do_branch; | |
10313 | case M_BLE: | |
10314 | s = "slt"; | |
10315 | s2 = "bteqz"; | |
10316 | goto do_reverse_branch; | |
10317 | case M_BLEU: | |
10318 | s = "sltu"; | |
10319 | s2 = "bteqz"; | |
10320 | goto do_reverse_branch; | |
10321 | case M_BGE: | |
10322 | s = "slt"; | |
10323 | s2 = "bteqz"; | |
10324 | goto do_branch; | |
10325 | case M_BGEU: | |
10326 | s = "sltu"; | |
10327 | s2 = "bteqz"; | |
10328 | goto do_branch; | |
10329 | case M_BGT: | |
10330 | s = "slt"; | |
10331 | s2 = "btnez"; | |
10332 | goto do_reverse_branch; | |
10333 | case M_BGTU: | |
10334 | s = "sltu"; | |
10335 | s2 = "btnez"; | |
10336 | ||
10337 | do_reverse_branch: | |
10338 | tmp = xreg; | |
10339 | xreg = yreg; | |
10340 | yreg = tmp; | |
10341 | ||
10342 | do_branch: | |
67c0d1eb RS |
10343 | macro_build (NULL, s, "x,y", xreg, yreg); |
10344 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10345 | break; |
10346 | ||
10347 | case M_BEQ_I: | |
10348 | s = "cmpi"; | |
10349 | s2 = "bteqz"; | |
10350 | s3 = "x,U"; | |
10351 | goto do_branch_i; | |
10352 | case M_BNE_I: | |
10353 | s = "cmpi"; | |
10354 | s2 = "btnez"; | |
10355 | s3 = "x,U"; | |
10356 | goto do_branch_i; | |
10357 | case M_BLT_I: | |
10358 | s = "slti"; | |
10359 | s2 = "btnez"; | |
10360 | s3 = "x,8"; | |
10361 | goto do_branch_i; | |
10362 | case M_BLTU_I: | |
10363 | s = "sltiu"; | |
10364 | s2 = "btnez"; | |
10365 | s3 = "x,8"; | |
10366 | goto do_branch_i; | |
10367 | case M_BLE_I: | |
10368 | s = "slti"; | |
10369 | s2 = "btnez"; | |
10370 | s3 = "x,8"; | |
10371 | goto do_addone_branch_i; | |
10372 | case M_BLEU_I: | |
10373 | s = "sltiu"; | |
10374 | s2 = "btnez"; | |
10375 | s3 = "x,8"; | |
10376 | goto do_addone_branch_i; | |
10377 | case M_BGE_I: | |
10378 | s = "slti"; | |
10379 | s2 = "bteqz"; | |
10380 | s3 = "x,8"; | |
10381 | goto do_branch_i; | |
10382 | case M_BGEU_I: | |
10383 | s = "sltiu"; | |
10384 | s2 = "bteqz"; | |
10385 | s3 = "x,8"; | |
10386 | goto do_branch_i; | |
10387 | case M_BGT_I: | |
10388 | s = "slti"; | |
10389 | s2 = "bteqz"; | |
10390 | s3 = "x,8"; | |
10391 | goto do_addone_branch_i; | |
10392 | case M_BGTU_I: | |
10393 | s = "sltiu"; | |
10394 | s2 = "bteqz"; | |
10395 | s3 = "x,8"; | |
10396 | ||
10397 | do_addone_branch_i: | |
10398 | if (imm_expr.X_op != O_constant) | |
10399 | as_bad (_("Unsupported large constant")); | |
10400 | ++imm_expr.X_add_number; | |
10401 | ||
10402 | do_branch_i: | |
67c0d1eb RS |
10403 | macro_build (&imm_expr, s, s3, xreg); |
10404 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10405 | break; |
10406 | ||
10407 | case M_ABS: | |
10408 | expr1.X_add_number = 0; | |
67c0d1eb | 10409 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10410 | if (xreg != yreg) |
67c0d1eb | 10411 | move_register (xreg, yreg); |
252b5132 | 10412 | expr1.X_add_number = 2; |
67c0d1eb RS |
10413 | macro_build (&expr1, "bteqz", "p"); |
10414 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10415 | } |
10416 | } | |
10417 | ||
10418 | /* For consistency checking, verify that all bits are specified either | |
10419 | by the match/mask part of the instruction definition, or by the | |
10420 | operand list. */ | |
10421 | static int | |
17a2f251 | 10422 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10423 | { |
10424 | const char *p = opc->args; | |
10425 | char c; | |
10426 | unsigned long used_bits = opc->mask; | |
10427 | ||
10428 | if ((used_bits & opc->match) != opc->match) | |
10429 | { | |
10430 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10431 | opc->name, opc->args); | |
10432 | return 0; | |
10433 | } | |
10434 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10435 | while (*p) | |
10436 | switch (c = *p++) | |
10437 | { | |
10438 | case ',': break; | |
10439 | case '(': break; | |
10440 | case ')': break; | |
af7ee8bf CD |
10441 | case '+': |
10442 | switch (c = *p++) | |
10443 | { | |
9bcd4f99 TS |
10444 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10445 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10446 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10447 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10448 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10449 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10450 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10451 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10452 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10453 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10454 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10455 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10456 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10457 | case 'I': break; | |
b015e599 | 10458 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10459 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10460 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10461 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10462 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10463 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10464 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10465 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10466 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10467 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10468 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10469 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10470 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10471 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10472 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10473 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10474 | |
af7ee8bf CD |
10475 | default: |
10476 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10477 | c, opc->name, opc->args); | |
10478 | return 0; | |
10479 | } | |
10480 | break; | |
252b5132 RH |
10481 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10482 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10483 | case 'A': break; | |
4372b673 | 10484 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10485 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10486 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10487 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10488 | case 'F': break; | |
10489 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10490 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10491 | case 'I': break; |
e972090a | 10492 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10493 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10494 | case 'L': break; |
10495 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10496 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10497 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10498 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10499 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10500 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10501 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10502 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10503 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10504 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10505 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10506 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10507 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10508 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10509 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10510 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10511 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10512 | case 'f': break; | |
10513 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10514 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10515 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10516 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10517 | case 'l': break; | |
10518 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10519 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10520 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10521 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10522 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10523 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10524 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10525 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10526 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10527 | case 'x': break; | |
10528 | case 'z': break; | |
10529 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10530 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10531 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10532 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10533 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10534 | case '[': break; | |
10535 | case ']': break; | |
620edafd | 10536 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10537 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10538 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10539 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10540 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10541 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10542 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10543 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10544 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10545 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10546 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10547 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10548 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10549 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10550 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10551 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10552 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10553 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10554 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10555 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10556 | default: |
10557 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10558 | c, opc->name, opc->args); | |
10559 | return 0; | |
10560 | } | |
10561 | #undef USE_BITS | |
10562 | if (used_bits != 0xffffffff) | |
10563 | { | |
10564 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10565 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10566 | return 0; | |
10567 | } | |
10568 | return 1; | |
10569 | } | |
10570 | ||
df58fc94 RS |
10571 | /* For consistency checking, verify that the length implied matches the |
10572 | major opcode and that all bits are specified either by the match/mask | |
10573 | part of the instruction definition, or by the operand list. */ | |
10574 | ||
10575 | static int | |
10576 | validate_micromips_insn (const struct mips_opcode *opc) | |
10577 | { | |
10578 | unsigned long match = opc->match; | |
10579 | unsigned long mask = opc->mask; | |
10580 | const char *p = opc->args; | |
10581 | unsigned long insn_bits; | |
10582 | unsigned long used_bits; | |
10583 | unsigned long major; | |
10584 | unsigned int length; | |
10585 | char e; | |
10586 | char c; | |
10587 | ||
10588 | if ((mask & match) != match) | |
10589 | { | |
10590 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10591 | opc->name, opc->args); | |
10592 | return 0; | |
10593 | } | |
10594 | length = micromips_insn_length (opc); | |
10595 | if (length != 2 && length != 4) | |
10596 | { | |
10597 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10598 | "%s %s"), length, opc->name, opc->args); | |
10599 | return 0; | |
10600 | } | |
10601 | major = match >> (10 + 8 * (length - 2)); | |
10602 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10603 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10604 | { | |
10605 | as_bad (_("Internal error: bad microMIPS opcode " | |
10606 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10607 | return 0; | |
10608 | } | |
10609 | ||
10610 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10611 | insn_bits = 1 << 4 * length; | |
10612 | insn_bits <<= 4 * length; | |
10613 | insn_bits -= 1; | |
10614 | used_bits = mask; | |
10615 | #define USE_BITS(field) \ | |
10616 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10617 | while (*p) | |
10618 | switch (c = *p++) | |
10619 | { | |
10620 | case ',': break; | |
10621 | case '(': break; | |
10622 | case ')': break; | |
10623 | case '+': | |
10624 | e = c; | |
10625 | switch (c = *p++) | |
10626 | { | |
10627 | case 'A': USE_BITS (EXTLSB); break; | |
10628 | case 'B': USE_BITS (INSMSB); break; | |
10629 | case 'C': USE_BITS (EXTMSBD); break; | |
10630 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10631 | case 'E': USE_BITS (EXTLSB); break; | |
10632 | case 'F': USE_BITS (INSMSB); break; | |
10633 | case 'G': USE_BITS (EXTMSBD); break; | |
10634 | case 'H': USE_BITS (EXTMSBD); break; | |
10635 | default: | |
10636 | as_bad (_("Internal error: bad mips opcode " | |
10637 | "(unknown extension operand type `%c%c'): %s %s"), | |
10638 | e, c, opc->name, opc->args); | |
10639 | return 0; | |
10640 | } | |
10641 | break; | |
10642 | case 'm': | |
10643 | e = c; | |
10644 | switch (c = *p++) | |
10645 | { | |
10646 | case 'A': USE_BITS (IMMA); break; | |
10647 | case 'B': USE_BITS (IMMB); break; | |
10648 | case 'C': USE_BITS (IMMC); break; | |
10649 | case 'D': USE_BITS (IMMD); break; | |
10650 | case 'E': USE_BITS (IMME); break; | |
10651 | case 'F': USE_BITS (IMMF); break; | |
10652 | case 'G': USE_BITS (IMMG); break; | |
10653 | case 'H': USE_BITS (IMMH); break; | |
10654 | case 'I': USE_BITS (IMMI); break; | |
10655 | case 'J': USE_BITS (IMMJ); break; | |
10656 | case 'L': USE_BITS (IMML); break; | |
10657 | case 'M': USE_BITS (IMMM); break; | |
10658 | case 'N': USE_BITS (IMMN); break; | |
10659 | case 'O': USE_BITS (IMMO); break; | |
10660 | case 'P': USE_BITS (IMMP); break; | |
10661 | case 'Q': USE_BITS (IMMQ); break; | |
10662 | case 'U': USE_BITS (IMMU); break; | |
10663 | case 'W': USE_BITS (IMMW); break; | |
10664 | case 'X': USE_BITS (IMMX); break; | |
10665 | case 'Y': USE_BITS (IMMY); break; | |
10666 | case 'Z': break; | |
10667 | case 'a': break; | |
10668 | case 'b': USE_BITS (MB); break; | |
10669 | case 'c': USE_BITS (MC); break; | |
10670 | case 'd': USE_BITS (MD); break; | |
10671 | case 'e': USE_BITS (ME); break; | |
10672 | case 'f': USE_BITS (MF); break; | |
10673 | case 'g': USE_BITS (MG); break; | |
10674 | case 'h': USE_BITS (MH); break; | |
10675 | case 'i': USE_BITS (MI); break; | |
10676 | case 'j': USE_BITS (MJ); break; | |
10677 | case 'l': USE_BITS (ML); break; | |
10678 | case 'm': USE_BITS (MM); break; | |
10679 | case 'n': USE_BITS (MN); break; | |
10680 | case 'p': USE_BITS (MP); break; | |
10681 | case 'q': USE_BITS (MQ); break; | |
10682 | case 'r': break; | |
10683 | case 's': break; | |
10684 | case 't': break; | |
10685 | case 'x': break; | |
10686 | case 'y': break; | |
10687 | case 'z': break; | |
10688 | default: | |
10689 | as_bad (_("Internal error: bad mips opcode " | |
10690 | "(unknown extension operand type `%c%c'): %s %s"), | |
10691 | e, c, opc->name, opc->args); | |
10692 | return 0; | |
10693 | } | |
10694 | break; | |
10695 | case '.': USE_BITS (OFFSET10); break; | |
10696 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10697 | case '2': USE_BITS (BP); break; |
10698 | case '3': USE_BITS (SA3); break; | |
10699 | case '4': USE_BITS (SA4); break; | |
10700 | case '5': USE_BITS (IMM8); break; | |
10701 | case '6': USE_BITS (RS); break; | |
10702 | case '7': USE_BITS (DSPACC); break; | |
10703 | case '8': USE_BITS (WRDSP); break; | |
10704 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10705 | case '<': USE_BITS (SHAMT); break; |
10706 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10707 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10708 | case 'B': USE_BITS (CODE10); break; |
10709 | case 'C': USE_BITS (COPZ); break; | |
10710 | case 'D': USE_BITS (FD); break; | |
10711 | case 'E': USE_BITS (RT); break; | |
10712 | case 'G': USE_BITS (RS); break; | |
444d75be | 10713 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10714 | case 'K': USE_BITS (RS); break; |
10715 | case 'M': USE_BITS (CCC); break; | |
10716 | case 'N': USE_BITS (BCC); break; | |
10717 | case 'R': USE_BITS (FR); break; | |
10718 | case 'S': USE_BITS (FS); break; | |
10719 | case 'T': USE_BITS (FT); break; | |
10720 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10721 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10722 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10723 | case 'a': USE_BITS (TARGET); break; |
10724 | case 'b': USE_BITS (RS); break; | |
10725 | case 'c': USE_BITS (CODE); break; | |
10726 | case 'd': USE_BITS (RD); break; | |
10727 | case 'h': USE_BITS (PREFX); break; | |
10728 | case 'i': USE_BITS (IMMEDIATE); break; | |
10729 | case 'j': USE_BITS (DELTA); break; | |
10730 | case 'k': USE_BITS (CACHE); break; | |
10731 | case 'n': USE_BITS (RT); break; | |
10732 | case 'o': USE_BITS (DELTA); break; | |
10733 | case 'p': USE_BITS (DELTA); break; | |
10734 | case 'q': USE_BITS (CODE2); break; | |
10735 | case 'r': USE_BITS (RS); break; | |
10736 | case 's': USE_BITS (RS); break; | |
10737 | case 't': USE_BITS (RT); break; | |
10738 | case 'u': USE_BITS (IMMEDIATE); break; | |
10739 | case 'v': USE_BITS (RS); break; | |
10740 | case 'w': USE_BITS (RT); break; | |
10741 | case 'y': USE_BITS (RS3); break; | |
10742 | case 'z': break; | |
10743 | case '|': USE_BITS (TRAP); break; | |
10744 | case '~': USE_BITS (OFFSET12); break; | |
10745 | default: | |
10746 | as_bad (_("Internal error: bad microMIPS opcode " | |
10747 | "(unknown operand type `%c'): %s %s"), | |
10748 | c, opc->name, opc->args); | |
10749 | return 0; | |
10750 | } | |
10751 | #undef USE_BITS | |
10752 | if (used_bits != insn_bits) | |
10753 | { | |
10754 | if (~used_bits & insn_bits) | |
10755 | as_bad (_("Internal error: bad microMIPS opcode " | |
10756 | "(bits 0x%lx undefined): %s %s"), | |
10757 | ~used_bits & insn_bits, opc->name, opc->args); | |
10758 | if (used_bits & ~insn_bits) | |
10759 | as_bad (_("Internal error: bad microMIPS opcode " | |
10760 | "(bits 0x%lx defined): %s %s"), | |
10761 | used_bits & ~insn_bits, opc->name, opc->args); | |
10762 | return 0; | |
10763 | } | |
10764 | return 1; | |
10765 | } | |
10766 | ||
9bcd4f99 TS |
10767 | /* UDI immediates. */ |
10768 | struct mips_immed { | |
10769 | char type; | |
10770 | unsigned int shift; | |
10771 | unsigned long mask; | |
10772 | const char * desc; | |
10773 | }; | |
10774 | ||
10775 | static const struct mips_immed mips_immed[] = { | |
10776 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10777 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10778 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10779 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10780 | { 0,0,0,0 } | |
10781 | }; | |
10782 | ||
7455baf8 TS |
10783 | /* Check whether an odd floating-point register is allowed. */ |
10784 | static int | |
10785 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10786 | { | |
10787 | const char *s = insn->name; | |
10788 | ||
10789 | if (insn->pinfo == INSN_MACRO) | |
10790 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10791 | return 1; | |
10792 | ||
e407c74b | 10793 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
10794 | { |
10795 | /* Allow odd registers for single-precision ops. */ | |
10796 | switch (insn->pinfo & (FP_S | FP_D)) | |
10797 | { | |
10798 | case FP_S: | |
10799 | case 0: | |
10800 | return 1; /* both single precision - ok */ | |
10801 | case FP_D: | |
10802 | return 0; /* both double precision - fail */ | |
10803 | default: | |
10804 | break; | |
10805 | } | |
10806 | ||
10807 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10808 | s = strchr (insn->name, '.'); | |
10809 | if (argnum == 2) | |
10810 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10811 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10812 | } | |
10813 | ||
10814 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10815 | if ((insn->pinfo & FP_S) | |
10816 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10817 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10818 | return 1; | |
10819 | ||
10820 | return 0; | |
10821 | } | |
10822 | ||
df58fc94 RS |
10823 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10824 | taking bits from BIT up. */ | |
10825 | static int | |
10826 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10827 | { | |
10828 | return (ep->X_op == O_constant | |
10829 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10830 | && ep->X_add_number >= min << bit | |
10831 | && ep->X_add_number < max << bit); | |
10832 | } | |
10833 | ||
252b5132 RH |
10834 | /* This routine assembles an instruction into its binary format. As a |
10835 | side effect, it sets one of the global variables imm_reloc or | |
10836 | offset_reloc to the type of relocation to do if one of the operands | |
10837 | is an address expression. */ | |
10838 | ||
10839 | static void | |
17a2f251 | 10840 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10841 | { |
df58fc94 RS |
10842 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10843 | bfd_boolean need_delay_slot_ok = TRUE; | |
10844 | struct mips_opcode *firstinsn = NULL; | |
10845 | const struct mips_opcode *past; | |
10846 | struct hash_control *hash; | |
252b5132 RH |
10847 | char *s; |
10848 | const char *args; | |
43841e91 | 10849 | char c = 0; |
252b5132 RH |
10850 | struct mips_opcode *insn; |
10851 | char *argsStart; | |
10852 | unsigned int regno; | |
34224acf | 10853 | unsigned int lastregno; |
df58fc94 | 10854 | unsigned int destregno = 0; |
af7ee8bf | 10855 | unsigned int lastpos = 0; |
071742cf | 10856 | unsigned int limlo, limhi; |
f02d8318 | 10857 | int sizelo; |
252b5132 | 10858 | char *s_reset; |
74cd071d | 10859 | offsetT min_range, max_range; |
df58fc94 | 10860 | long opend; |
a40bc9dd | 10861 | char *name; |
707bfff6 TS |
10862 | int argnum; |
10863 | unsigned int rtype; | |
df58fc94 | 10864 | char *dot; |
a40bc9dd | 10865 | long end; |
252b5132 RH |
10866 | |
10867 | insn_error = NULL; | |
10868 | ||
df58fc94 RS |
10869 | if (mips_opts.micromips) |
10870 | { | |
10871 | hash = micromips_op_hash; | |
10872 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10873 | } | |
10874 | else | |
10875 | { | |
10876 | hash = op_hash; | |
10877 | past = &mips_opcodes[NUMOPCODES]; | |
10878 | } | |
10879 | forced_insn_length = 0; | |
252b5132 | 10880 | insn = NULL; |
252b5132 | 10881 | |
df58fc94 | 10882 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10883 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10884 | continue; | |
bdaaa2e1 | 10885 | |
a40bc9dd RS |
10886 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10887 | name = alloca (end + 1); | |
10888 | memcpy (name, str, end); | |
10889 | name[end] = '\0'; | |
252b5132 | 10890 | |
df58fc94 RS |
10891 | for (;;) |
10892 | { | |
10893 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10894 | ||
10895 | if (insn != NULL || !mips_opts.micromips) | |
10896 | break; | |
10897 | if (forced_insn_length) | |
10898 | break; | |
10899 | ||
10900 | /* See if there's an instruction size override suffix, | |
10901 | either `16' or `32', at the end of the mnemonic proper, | |
10902 | that defines the operation, i.e. before the first `.' | |
10903 | character if any. Strip it and retry. */ | |
10904 | dot = strchr (name, '.'); | |
10905 | opend = dot != NULL ? dot - name : end; | |
10906 | if (opend < 3) | |
10907 | break; | |
10908 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10909 | forced_insn_length = 2; | |
10910 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10911 | forced_insn_length = 4; | |
10912 | else | |
10913 | break; | |
10914 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10915 | } | |
252b5132 RH |
10916 | if (insn == NULL) |
10917 | { | |
a40bc9dd RS |
10918 | insn_error = _("Unrecognized opcode"); |
10919 | return; | |
252b5132 RH |
10920 | } |
10921 | ||
df58fc94 RS |
10922 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10923 | we make up to two passes over the relevant fragment of the opcode | |
10924 | table. First we try instructions that meet the delay slot's length | |
10925 | requirement. If none matched, then we retry with the remaining ones | |
10926 | and if one matches, then we use it and then issue an appropriate | |
10927 | warning later on. */ | |
a40bc9dd | 10928 | argsStart = s = str + end; |
252b5132 RH |
10929 | for (;;) |
10930 | { | |
df58fc94 RS |
10931 | bfd_boolean delay_slot_ok; |
10932 | bfd_boolean size_ok; | |
b34976b6 | 10933 | bfd_boolean ok; |
252b5132 | 10934 | |
a40bc9dd | 10935 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10936 | |
f79e2745 | 10937 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10938 | size_ok = is_size_valid (insn); |
10939 | delay_slot_ok = is_delay_slot_valid (insn); | |
10940 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10941 | { |
df58fc94 RS |
10942 | firstinsn = insn; |
10943 | wrong_delay_slot_insns = TRUE; | |
10944 | } | |
10945 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10946 | { | |
10947 | static char buf[256]; | |
10948 | ||
10949 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10950 | { |
10951 | ++insn; | |
10952 | continue; | |
10953 | } | |
df58fc94 | 10954 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10955 | { |
df58fc94 RS |
10956 | gas_assert (firstinsn); |
10957 | need_delay_slot_ok = FALSE; | |
10958 | past = insn + 1; | |
10959 | insn = firstinsn; | |
10960 | continue; | |
252b5132 | 10961 | } |
df58fc94 RS |
10962 | |
10963 | if (insn_error) | |
10964 | return; | |
10965 | ||
10966 | if (!ok) | |
7bd942df | 10967 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10968 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10969 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10970 | else | |
10971 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10972 | 8 * forced_insn_length); | |
10973 | insn_error = buf; | |
10974 | ||
10975 | return; | |
252b5132 RH |
10976 | } |
10977 | ||
1e915849 | 10978 | create_insn (ip, insn); |
268f6bed | 10979 | insn_error = NULL; |
707bfff6 | 10980 | argnum = 1; |
24864476 | 10981 | lastregno = 0xffffffff; |
252b5132 RH |
10982 | for (args = insn->args;; ++args) |
10983 | { | |
deec1734 CD |
10984 | int is_mdmx; |
10985 | ||
ad8d3bb3 | 10986 | s += strspn (s, " \t"); |
deec1734 | 10987 | is_mdmx = 0; |
252b5132 RH |
10988 | switch (*args) |
10989 | { | |
10990 | case '\0': /* end of args */ | |
10991 | if (*s == '\0') | |
10992 | return; | |
10993 | break; | |
10994 | ||
03f66e8a MR |
10995 | case '2': |
10996 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10997 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10998 | my_getExpression (&imm_expr, s); |
10999 | check_absolute_expr (ip, &imm_expr); | |
11000 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11001 | && (unsigned long) imm_expr.X_add_number != 3) | |
11002 | { | |
11003 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11004 | (unsigned long) imm_expr.X_add_number); | |
11005 | } | |
03f66e8a MR |
11006 | INSERT_OPERAND (mips_opts.micromips, |
11007 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11008 | imm_expr.X_op = O_absent; |
11009 | s = expr_end; | |
11010 | continue; | |
11011 | ||
03f66e8a MR |
11012 | case '3': |
11013 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11014 | code) or 21 (for microMIPS code). */ | |
11015 | { | |
11016 | unsigned long mask = (mips_opts.micromips | |
11017 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11018 | ||
11019 | my_getExpression (&imm_expr, s); | |
11020 | check_absolute_expr (ip, &imm_expr); | |
11021 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11022 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11023 | mask, (unsigned long) imm_expr.X_add_number); | |
11024 | INSERT_OPERAND (mips_opts.micromips, | |
11025 | SA3, *ip, imm_expr.X_add_number); | |
11026 | imm_expr.X_op = O_absent; | |
11027 | s = expr_end; | |
11028 | } | |
74cd071d CF |
11029 | continue; |
11030 | ||
03f66e8a MR |
11031 | case '4': |
11032 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11033 | code) or 21 (for microMIPS code). */ | |
11034 | { | |
11035 | unsigned long mask = (mips_opts.micromips | |
11036 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11037 | ||
11038 | my_getExpression (&imm_expr, s); | |
11039 | check_absolute_expr (ip, &imm_expr); | |
11040 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11041 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11042 | mask, (unsigned long) imm_expr.X_add_number); | |
11043 | INSERT_OPERAND (mips_opts.micromips, | |
11044 | SA4, *ip, imm_expr.X_add_number); | |
11045 | imm_expr.X_op = O_absent; | |
11046 | s = expr_end; | |
11047 | } | |
74cd071d CF |
11048 | continue; |
11049 | ||
03f66e8a MR |
11050 | case '5': |
11051 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11052 | code) or 16 (for microMIPS code). */ | |
11053 | { | |
11054 | unsigned long mask = (mips_opts.micromips | |
11055 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11056 | ||
11057 | my_getExpression (&imm_expr, s); | |
11058 | check_absolute_expr (ip, &imm_expr); | |
11059 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11060 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11061 | mask, (unsigned long) imm_expr.X_add_number); | |
11062 | INSERT_OPERAND (mips_opts.micromips, | |
11063 | IMM8, *ip, imm_expr.X_add_number); | |
11064 | imm_expr.X_op = O_absent; | |
11065 | s = expr_end; | |
11066 | } | |
74cd071d CF |
11067 | continue; |
11068 | ||
03f66e8a MR |
11069 | case '6': |
11070 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11071 | code) or 21 (for microMIPS code). */ | |
11072 | { | |
11073 | unsigned long mask = (mips_opts.micromips | |
11074 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11075 | ||
11076 | my_getExpression (&imm_expr, s); | |
11077 | check_absolute_expr (ip, &imm_expr); | |
11078 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11079 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11080 | mask, (unsigned long) imm_expr.X_add_number); | |
11081 | INSERT_OPERAND (mips_opts.micromips, | |
11082 | RS, *ip, imm_expr.X_add_number); | |
11083 | imm_expr.X_op = O_absent; | |
11084 | s = expr_end; | |
11085 | } | |
74cd071d CF |
11086 | continue; |
11087 | ||
90ecf173 | 11088 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11089 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11090 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11091 | { |
11092 | regno = s[3] - '0'; | |
11093 | s += 4; | |
03f66e8a | 11094 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11095 | continue; |
11096 | } | |
11097 | else | |
11098 | as_bad (_("Invalid dsp acc register")); | |
11099 | break; | |
11100 | ||
03f66e8a MR |
11101 | case '8': |
11102 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11103 | code) or 14 (for microMIPS code). */ | |
11104 | { | |
11105 | unsigned long mask = (mips_opts.micromips | |
11106 | ? MICROMIPSOP_MASK_WRDSP | |
11107 | : OP_MASK_WRDSP); | |
11108 | ||
11109 | my_getExpression (&imm_expr, s); | |
11110 | check_absolute_expr (ip, &imm_expr); | |
11111 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11112 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11113 | mask, (unsigned long) imm_expr.X_add_number); | |
11114 | INSERT_OPERAND (mips_opts.micromips, | |
11115 | WRDSP, *ip, imm_expr.X_add_number); | |
11116 | imm_expr.X_op = O_absent; | |
11117 | s = expr_end; | |
11118 | } | |
74cd071d CF |
11119 | continue; |
11120 | ||
90ecf173 | 11121 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11122 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11123 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11124 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11125 | { |
11126 | regno = s[3] - '0'; | |
11127 | s += 4; | |
df58fc94 | 11128 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11129 | continue; |
11130 | } | |
11131 | else | |
11132 | as_bad (_("Invalid dsp acc register")); | |
11133 | break; | |
11134 | ||
03f66e8a MR |
11135 | case '0': |
11136 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11137 | code) or 20 (for microMIPS code). */ | |
11138 | { | |
11139 | long mask = (mips_opts.micromips | |
11140 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11141 | ||
11142 | my_getExpression (&imm_expr, s); | |
11143 | check_absolute_expr (ip, &imm_expr); | |
11144 | min_range = -((mask + 1) >> 1); | |
11145 | max_range = ((mask + 1) >> 1) - 1; | |
11146 | if (imm_expr.X_add_number < min_range | |
11147 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11148 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11149 | (long) min_range, (long) max_range, | |
11150 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11151 | INSERT_OPERAND (mips_opts.micromips, |
11152 | DSPSFT, *ip, imm_expr.X_add_number); | |
11153 | imm_expr.X_op = O_absent; | |
11154 | s = expr_end; | |
11155 | } | |
74cd071d CF |
11156 | continue; |
11157 | ||
90ecf173 | 11158 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11159 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11160 | my_getExpression (&imm_expr, s); |
11161 | check_absolute_expr (ip, &imm_expr); | |
11162 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11163 | { | |
a9e24354 TS |
11164 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11165 | OP_MASK_RDDSP, | |
11166 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11167 | } |
df58fc94 | 11168 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11169 | imm_expr.X_op = O_absent; |
11170 | s = expr_end; | |
11171 | continue; | |
11172 | ||
90ecf173 | 11173 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11174 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11175 | my_getExpression (&imm_expr, s); |
11176 | check_absolute_expr (ip, &imm_expr); | |
11177 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11178 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11179 | if (imm_expr.X_add_number < min_range || | |
11180 | imm_expr.X_add_number > max_range) | |
11181 | { | |
a9e24354 TS |
11182 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11183 | (long) min_range, (long) max_range, | |
11184 | (long) imm_expr.X_add_number); | |
74cd071d | 11185 | } |
df58fc94 | 11186 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11187 | imm_expr.X_op = O_absent; |
11188 | s = expr_end; | |
11189 | continue; | |
11190 | ||
90ecf173 | 11191 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11192 | { |
11193 | long mask = (mips_opts.micromips | |
11194 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11195 | ||
11196 | my_getExpression (&imm_expr, s); | |
11197 | check_absolute_expr (ip, &imm_expr); | |
11198 | min_range = -((mask + 1) >> 1); | |
11199 | max_range = ((mask + 1) >> 1) - 1; | |
11200 | if (imm_expr.X_add_number < min_range | |
11201 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11202 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11203 | (long) min_range, (long) max_range, | |
11204 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11205 | INSERT_OPERAND (mips_opts.micromips, |
11206 | IMM10, *ip, imm_expr.X_add_number); | |
11207 | imm_expr.X_op = O_absent; | |
11208 | s = expr_end; | |
11209 | } | |
11210 | continue; | |
11211 | ||
11212 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11213 | gas_assert (mips_opts.micromips); | |
11214 | my_getExpression (&imm_expr, s); | |
11215 | check_absolute_expr (ip, &imm_expr); | |
11216 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11217 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11218 | MICROMIPSOP_MASK_RD, | |
11219 | (unsigned long) imm_expr.X_add_number); | |
11220 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11221 | imm_expr.X_op = O_absent; |
11222 | s = expr_end; | |
11223 | continue; | |
11224 | ||
a9e24354 | 11225 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11226 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11227 | my_getExpression (&imm_expr, s); |
11228 | check_absolute_expr (ip, &imm_expr); | |
11229 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11230 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11231 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11232 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11233 | imm_expr.X_op = O_absent; |
11234 | s = expr_end; | |
11235 | continue; | |
11236 | ||
a9e24354 | 11237 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11238 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11239 | my_getExpression (&imm_expr, s); |
11240 | check_absolute_expr (ip, &imm_expr); | |
11241 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11242 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11243 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11244 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11245 | imm_expr.X_op = O_absent; |
11246 | s = expr_end; | |
11247 | continue; | |
11248 | ||
90ecf173 | 11249 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11250 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11251 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11252 | s[3] >= '0' && s[3] <= '3') | |
11253 | { | |
11254 | regno = s[3] - '0'; | |
11255 | s += 4; | |
df58fc94 | 11256 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11257 | continue; |
11258 | } | |
11259 | else | |
11260 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11261 | break; | |
11262 | ||
90ecf173 | 11263 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11264 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11265 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11266 | s[3] >= '0' && s[3] <= '3') | |
11267 | { | |
11268 | regno = s[3] - '0'; | |
11269 | s += 4; | |
df58fc94 | 11270 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11271 | continue; |
11272 | } | |
11273 | else | |
11274 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11275 | break; | |
11276 | ||
dec0624d MR |
11277 | case '\\': /* 3-bit bit position. */ |
11278 | { | |
2906b037 MR |
11279 | unsigned long mask = (mips_opts.micromips |
11280 | ? MICROMIPSOP_MASK_3BITPOS | |
11281 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11282 | |
11283 | my_getExpression (&imm_expr, s); | |
11284 | check_absolute_expr (ip, &imm_expr); | |
11285 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11286 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11287 | ip->insn_mo->name, | |
11288 | mask, (unsigned long) imm_expr.X_add_number); | |
11289 | INSERT_OPERAND (mips_opts.micromips, | |
11290 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11291 | imm_expr.X_op = O_absent; | |
11292 | s = expr_end; | |
11293 | } | |
11294 | continue; | |
11295 | ||
252b5132 | 11296 | case ',': |
a339155f | 11297 | ++argnum; |
252b5132 RH |
11298 | if (*s++ == *args) |
11299 | continue; | |
11300 | s--; | |
11301 | switch (*++args) | |
11302 | { | |
11303 | case 'r': | |
11304 | case 'v': | |
df58fc94 | 11305 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11306 | continue; |
11307 | ||
11308 | case 'w': | |
df58fc94 | 11309 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11310 | continue; |
11311 | ||
252b5132 | 11312 | case 'W': |
df58fc94 RS |
11313 | gas_assert (!mips_opts.micromips); |
11314 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11315 | continue; |
11316 | ||
11317 | case 'V': | |
df58fc94 | 11318 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11319 | continue; |
11320 | } | |
11321 | break; | |
11322 | ||
11323 | case '(': | |
11324 | /* Handle optional base register. | |
11325 | Either the base register is omitted or | |
bdaaa2e1 | 11326 | we must have a left paren. */ |
252b5132 RH |
11327 | /* This is dependent on the next operand specifier |
11328 | is a base register specification. */ | |
df58fc94 RS |
11329 | gas_assert (args[1] == 'b' |
11330 | || (mips_opts.micromips | |
11331 | && args[1] == 'm' | |
11332 | && (args[2] == 'l' || args[2] == 'n' | |
11333 | || args[2] == 's' || args[2] == 'a'))); | |
11334 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11335 | return; |
df58fc94 | 11336 | /* Fall through. */ |
252b5132 | 11337 | |
90ecf173 | 11338 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11339 | if (*s++ == *args) |
11340 | continue; | |
11341 | break; | |
11342 | ||
11343 | case '[': /* These must match exactly. */ | |
60b63b72 | 11344 | case ']': |
df58fc94 | 11345 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11346 | if (*s++ == *args) |
11347 | continue; | |
11348 | break; | |
11349 | ||
af7ee8bf CD |
11350 | case '+': /* Opcode extension character. */ |
11351 | switch (*++args) | |
11352 | { | |
9bcd4f99 TS |
11353 | case '1': /* UDI immediates. */ |
11354 | case '2': | |
11355 | case '3': | |
11356 | case '4': | |
df58fc94 | 11357 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11358 | { |
11359 | const struct mips_immed *imm = mips_immed; | |
11360 | ||
11361 | while (imm->type && imm->type != *args) | |
11362 | ++imm; | |
11363 | if (! imm->type) | |
b37df7c4 | 11364 | abort (); |
9bcd4f99 TS |
11365 | my_getExpression (&imm_expr, s); |
11366 | check_absolute_expr (ip, &imm_expr); | |
11367 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11368 | { | |
11369 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11370 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11371 | (unsigned long) imm_expr.X_add_number, | |
11372 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11373 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11374 | } |
11375 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11376 | << imm->shift); | |
11377 | imm_expr.X_op = O_absent; | |
11378 | s = expr_end; | |
11379 | } | |
11380 | continue; | |
90ecf173 | 11381 | |
b015e599 AP |
11382 | case 'J': /* 10-bit hypcall code. */ |
11383 | gas_assert (!mips_opts.micromips); | |
11384 | { | |
11385 | unsigned long mask = OP_MASK_CODE10; | |
11386 | ||
11387 | my_getExpression (&imm_expr, s); | |
11388 | check_absolute_expr (ip, &imm_expr); | |
11389 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11390 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11391 | ip->insn_mo->name, | |
11392 | mask, (unsigned long) imm_expr.X_add_number); | |
11393 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11394 | imm_expr.X_op = O_absent; | |
11395 | s = expr_end; | |
11396 | } | |
11397 | continue; | |
11398 | ||
071742cf CD |
11399 | case 'A': /* ins/ext position, becomes LSB. */ |
11400 | limlo = 0; | |
11401 | limhi = 31; | |
5f74bc13 CD |
11402 | goto do_lsb; |
11403 | case 'E': | |
11404 | limlo = 32; | |
11405 | limhi = 63; | |
11406 | goto do_lsb; | |
90ecf173 | 11407 | do_lsb: |
071742cf CD |
11408 | my_getExpression (&imm_expr, s); |
11409 | check_absolute_expr (ip, &imm_expr); | |
11410 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11411 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11412 | { | |
11413 | as_bad (_("Improper position (%lu)"), | |
11414 | (unsigned long) imm_expr.X_add_number); | |
11415 | imm_expr.X_add_number = limlo; | |
11416 | } | |
11417 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11418 | INSERT_OPERAND (mips_opts.micromips, |
11419 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11420 | imm_expr.X_op = O_absent; |
11421 | s = expr_end; | |
11422 | continue; | |
11423 | ||
11424 | case 'B': /* ins size, becomes MSB. */ | |
11425 | limlo = 1; | |
11426 | limhi = 32; | |
5f74bc13 CD |
11427 | goto do_msb; |
11428 | case 'F': | |
11429 | limlo = 33; | |
11430 | limhi = 64; | |
11431 | goto do_msb; | |
90ecf173 | 11432 | do_msb: |
071742cf CD |
11433 | my_getExpression (&imm_expr, s); |
11434 | check_absolute_expr (ip, &imm_expr); | |
11435 | /* Check for negative input so that small negative numbers | |
11436 | will not succeed incorrectly. The checks against | |
11437 | (pos+size) transitively check "size" itself, | |
11438 | assuming that "pos" is reasonable. */ | |
11439 | if ((long) imm_expr.X_add_number < 0 | |
11440 | || ((unsigned long) imm_expr.X_add_number | |
11441 | + lastpos) < limlo | |
11442 | || ((unsigned long) imm_expr.X_add_number | |
11443 | + lastpos) > limhi) | |
11444 | { | |
11445 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11446 | (unsigned long) imm_expr.X_add_number, | |
11447 | (unsigned long) lastpos); | |
11448 | imm_expr.X_add_number = limlo - lastpos; | |
11449 | } | |
df58fc94 RS |
11450 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11451 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11452 | imm_expr.X_op = O_absent; |
11453 | s = expr_end; | |
11454 | continue; | |
11455 | ||
11456 | case 'C': /* ext size, becomes MSBD. */ | |
11457 | limlo = 1; | |
11458 | limhi = 32; | |
f02d8318 | 11459 | sizelo = 1; |
5f74bc13 CD |
11460 | goto do_msbd; |
11461 | case 'G': | |
11462 | limlo = 33; | |
11463 | limhi = 64; | |
f02d8318 | 11464 | sizelo = 33; |
5f74bc13 CD |
11465 | goto do_msbd; |
11466 | case 'H': | |
11467 | limlo = 33; | |
11468 | limhi = 64; | |
f02d8318 | 11469 | sizelo = 1; |
5f74bc13 | 11470 | goto do_msbd; |
90ecf173 | 11471 | do_msbd: |
071742cf CD |
11472 | my_getExpression (&imm_expr, s); |
11473 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11474 | /* The checks against (pos+size) don't transitively check |
11475 | "size" itself, assuming that "pos" is reasonable. | |
11476 | We also need to check the lower bound of "size". */ | |
11477 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11478 | || ((unsigned long) imm_expr.X_add_number |
11479 | + lastpos) < limlo | |
11480 | || ((unsigned long) imm_expr.X_add_number | |
11481 | + lastpos) > limhi) | |
11482 | { | |
11483 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11484 | (unsigned long) imm_expr.X_add_number, | |
11485 | (unsigned long) lastpos); | |
11486 | imm_expr.X_add_number = limlo - lastpos; | |
11487 | } | |
df58fc94 RS |
11488 | INSERT_OPERAND (mips_opts.micromips, |
11489 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11490 | imm_expr.X_op = O_absent; |
11491 | s = expr_end; | |
11492 | continue; | |
af7ee8bf | 11493 | |
bbcc0807 CD |
11494 | case 'D': |
11495 | /* +D is for disassembly only; never match. */ | |
11496 | break; | |
11497 | ||
5f74bc13 CD |
11498 | case 'I': |
11499 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11500 | my_getExpression (&imm2_expr, s); | |
11501 | if (imm2_expr.X_op != O_big | |
11502 | && imm2_expr.X_op != O_constant) | |
11503 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11504 | if (HAVE_32BIT_GPRS) |
11505 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11506 | s = expr_end; |
11507 | continue; | |
11508 | ||
707bfff6 | 11509 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11510 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11511 | /* +T is for disassembly only; never match. */ |
11512 | break; | |
11513 | ||
707bfff6 | 11514 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11515 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11516 | if (s[0] == '$' && ISDIGIT (s[1])) |
11517 | { | |
11518 | ++s; | |
11519 | regno = 0; | |
11520 | do | |
11521 | { | |
11522 | regno *= 10; | |
11523 | regno += *s - '0'; | |
11524 | ++s; | |
11525 | } | |
11526 | while (ISDIGIT (*s)); | |
11527 | if (regno > 31) | |
11528 | as_bad (_("Invalid register number (%d)"), regno); | |
11529 | else | |
11530 | { | |
df58fc94 | 11531 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11532 | continue; |
11533 | } | |
11534 | } | |
11535 | else | |
11536 | as_bad (_("Invalid coprocessor 0 register number")); | |
11537 | break; | |
11538 | ||
bb35fb24 NC |
11539 | case 'x': |
11540 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11541 | is not in the valid range. */ | |
df58fc94 | 11542 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11543 | my_getExpression (&imm_expr, s); |
11544 | check_absolute_expr (ip, &imm_expr); | |
11545 | if ((unsigned) imm_expr.X_add_number > 31) | |
11546 | { | |
11547 | as_bad (_("Improper bit index (%lu)"), | |
11548 | (unsigned long) imm_expr.X_add_number); | |
11549 | imm_expr.X_add_number = 0; | |
11550 | } | |
df58fc94 | 11551 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11552 | imm_expr.X_op = O_absent; |
11553 | s = expr_end; | |
11554 | continue; | |
11555 | ||
11556 | case 'X': | |
11557 | /* bbit[01] bit index when bbit is used but we generate | |
11558 | bbit[01]32 because the index is over 32. Move to the | |
11559 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11560 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11561 | my_getExpression (&imm_expr, s); |
11562 | check_absolute_expr (ip, &imm_expr); | |
11563 | if ((unsigned) imm_expr.X_add_number < 32 | |
11564 | || (unsigned) imm_expr.X_add_number > 63) | |
11565 | break; | |
df58fc94 | 11566 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11567 | imm_expr.X_op = O_absent; |
11568 | s = expr_end; | |
11569 | continue; | |
11570 | ||
11571 | case 'p': | |
11572 | /* cins, cins32, exts and exts32 position field. Give error | |
11573 | if it's not in the valid range. */ | |
df58fc94 | 11574 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11575 | my_getExpression (&imm_expr, s); |
11576 | check_absolute_expr (ip, &imm_expr); | |
11577 | if ((unsigned) imm_expr.X_add_number > 31) | |
11578 | { | |
11579 | as_bad (_("Improper position (%lu)"), | |
11580 | (unsigned long) imm_expr.X_add_number); | |
11581 | imm_expr.X_add_number = 0; | |
11582 | } | |
11583 | /* Make the pos explicit to simplify +S. */ | |
11584 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11585 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11586 | imm_expr.X_op = O_absent; |
11587 | s = expr_end; | |
11588 | continue; | |
11589 | ||
11590 | case 'P': | |
11591 | /* cins, cins32, exts and exts32 position field. Move to | |
11592 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11593 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11594 | my_getExpression (&imm_expr, s); |
11595 | check_absolute_expr (ip, &imm_expr); | |
11596 | if ((unsigned) imm_expr.X_add_number < 32 | |
11597 | || (unsigned) imm_expr.X_add_number > 63) | |
11598 | break; | |
11599 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11600 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11601 | imm_expr.X_op = O_absent; |
11602 | s = expr_end; | |
11603 | continue; | |
11604 | ||
11605 | case 's': | |
11606 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11607 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11608 | my_getExpression (&imm_expr, s); |
11609 | check_absolute_expr (ip, &imm_expr); | |
11610 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11611 | { | |
11612 | as_bad (_("Improper size (%lu)"), | |
11613 | (unsigned long) imm_expr.X_add_number); | |
11614 | imm_expr.X_add_number = 0; | |
11615 | } | |
df58fc94 | 11616 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11617 | imm_expr.X_op = O_absent; |
11618 | s = expr_end; | |
11619 | continue; | |
11620 | ||
11621 | case 'S': | |
11622 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11623 | length-minus-one field. */ | |
df58fc94 | 11624 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11625 | my_getExpression (&imm_expr, s); |
11626 | check_absolute_expr (ip, &imm_expr); | |
11627 | if ((long) imm_expr.X_add_number < 0 | |
11628 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11629 | { | |
11630 | as_bad (_("Improper size (%lu)"), | |
11631 | (unsigned long) imm_expr.X_add_number); | |
11632 | imm_expr.X_add_number = 0; | |
11633 | } | |
df58fc94 | 11634 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11635 | imm_expr.X_op = O_absent; |
11636 | s = expr_end; | |
11637 | continue; | |
11638 | ||
dd3cbb7e NC |
11639 | case 'Q': |
11640 | /* seqi/snei immediate field. */ | |
df58fc94 | 11641 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11642 | my_getExpression (&imm_expr, s); |
11643 | check_absolute_expr (ip, &imm_expr); | |
11644 | if ((long) imm_expr.X_add_number < -512 | |
11645 | || (long) imm_expr.X_add_number >= 512) | |
11646 | { | |
11647 | as_bad (_("Improper immediate (%ld)"), | |
11648 | (long) imm_expr.X_add_number); | |
11649 | imm_expr.X_add_number = 0; | |
11650 | } | |
df58fc94 | 11651 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11652 | imm_expr.X_op = O_absent; |
11653 | s = expr_end; | |
11654 | continue; | |
11655 | ||
98675402 | 11656 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11657 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11658 | my_getExpression (&imm_expr, s); |
11659 | check_absolute_expr (ip, &imm_expr); | |
11660 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11661 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11662 | if (imm_expr.X_add_number < min_range | |
11663 | || imm_expr.X_add_number > max_range) | |
11664 | { | |
c95354ed | 11665 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11666 | (long) min_range, (long) max_range, |
11667 | (long) imm_expr.X_add_number); | |
11668 | } | |
df58fc94 | 11669 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11670 | imm_expr.X_op = O_absent; |
11671 | s = expr_end; | |
11672 | continue; | |
11673 | ||
11674 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11675 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11676 | my_getExpression (&imm_expr, s); |
11677 | check_absolute_expr (ip, &imm_expr); | |
11678 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11679 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11680 | if (imm_expr.X_add_number < min_range | |
11681 | || imm_expr.X_add_number > max_range) | |
11682 | { | |
c95354ed | 11683 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11684 | (long) min_range, (long) max_range, |
11685 | (long) imm_expr.X_add_number); | |
11686 | } | |
df58fc94 | 11687 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11688 | imm_expr.X_op = O_absent; |
11689 | s = expr_end; | |
11690 | continue; | |
11691 | ||
11692 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11693 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11694 | my_getExpression (&imm_expr, s); |
11695 | check_absolute_expr (ip, &imm_expr); | |
11696 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11697 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11698 | /* We check the offset range before adjusted. */ |
11699 | min_range <<= 4; | |
11700 | max_range <<= 4; | |
98675402 RS |
11701 | if (imm_expr.X_add_number < min_range |
11702 | || imm_expr.X_add_number > max_range) | |
11703 | { | |
c95354ed | 11704 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11705 | (long) min_range, (long) max_range, |
11706 | (long) imm_expr.X_add_number); | |
11707 | } | |
c95354ed MX |
11708 | if (imm_expr.X_add_number & 0xf) |
11709 | { | |
11710 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11711 | (long) imm_expr.X_add_number); | |
11712 | } | |
11713 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11714 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11715 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11716 | imm_expr.X_op = O_absent; |
11717 | s = expr_end; | |
11718 | continue; | |
11719 | ||
11720 | case 'z': | |
df58fc94 | 11721 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11722 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11723 | break; | |
11724 | if (regno == AT && mips_opts.at) | |
11725 | { | |
11726 | if (mips_opts.at == ATREG) | |
11727 | as_warn (_("used $at without \".set noat\"")); | |
11728 | else | |
11729 | as_warn (_("used $%u with \".set at=$%u\""), | |
11730 | regno, mips_opts.at); | |
11731 | } | |
df58fc94 | 11732 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11733 | continue; |
11734 | ||
11735 | case 'Z': | |
df58fc94 | 11736 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11737 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11738 | break; | |
df58fc94 | 11739 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11740 | continue; |
11741 | ||
af7ee8bf | 11742 | default: |
df58fc94 | 11743 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11744 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11745 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11746 | *args, insn->name, insn->args); |
af7ee8bf CD |
11747 | /* Further processing is fruitless. */ |
11748 | return; | |
11749 | } | |
11750 | break; | |
11751 | ||
df58fc94 | 11752 | case '.': /* 10-bit offset. */ |
df58fc94 | 11753 | gas_assert (mips_opts.micromips); |
dec0624d | 11754 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11755 | { |
11756 | int shift = *args == '.' ? 9 : 11; | |
11757 | size_t i; | |
11758 | ||
11759 | /* Check whether there is only a single bracketed expression | |
11760 | left. If so, it must be the base register and the | |
11761 | constant must be zero. */ | |
11762 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11763 | continue; | |
11764 | ||
11765 | /* If this value won't fit into the offset, then go find | |
11766 | a macro that will generate a 16- or 32-bit offset code | |
11767 | pattern. */ | |
11768 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11769 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11770 | || imm_expr.X_add_number >= 1 << shift | |
11771 | || imm_expr.X_add_number < -1 << shift)) | |
11772 | || i > 0) | |
11773 | { | |
11774 | imm_expr.X_op = O_absent; | |
11775 | break; | |
11776 | } | |
11777 | if (shift == 9) | |
11778 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11779 | else | |
dec0624d MR |
11780 | INSERT_OPERAND (mips_opts.micromips, |
11781 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11782 | imm_expr.X_op = O_absent; |
11783 | s = expr_end; | |
11784 | } | |
11785 | continue; | |
11786 | ||
252b5132 RH |
11787 | case '<': /* must be at least one digit */ |
11788 | /* | |
11789 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11790 | * than 31 or less than 0, then the shift amount should be |
11791 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11792 | * We issue a warning and mask out all but the low 5 bits. |
11793 | */ | |
11794 | my_getExpression (&imm_expr, s); | |
11795 | check_absolute_expr (ip, &imm_expr); | |
11796 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11797 | as_warn (_("Improper shift amount (%lu)"), |
11798 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11799 | INSERT_OPERAND (mips_opts.micromips, |
11800 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11801 | imm_expr.X_op = O_absent; |
11802 | s = expr_end; | |
11803 | continue; | |
11804 | ||
11805 | case '>': /* shift amount minus 32 */ | |
11806 | my_getExpression (&imm_expr, s); | |
11807 | check_absolute_expr (ip, &imm_expr); | |
11808 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11809 | || (unsigned long) imm_expr.X_add_number > 63) | |
11810 | break; | |
df58fc94 RS |
11811 | INSERT_OPERAND (mips_opts.micromips, |
11812 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11813 | imm_expr.X_op = O_absent; |
11814 | s = expr_end; | |
11815 | continue; | |
11816 | ||
90ecf173 MR |
11817 | case 'k': /* CACHE code. */ |
11818 | case 'h': /* PREFX code. */ | |
11819 | case '1': /* SYNC type. */ | |
252b5132 RH |
11820 | my_getExpression (&imm_expr, s); |
11821 | check_absolute_expr (ip, &imm_expr); | |
11822 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11823 | as_warn (_("Invalid value for `%s' (%lu)"), |
11824 | ip->insn_mo->name, | |
11825 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11826 | switch (*args) |
d954098f | 11827 | { |
df58fc94 RS |
11828 | case 'k': |
11829 | if (mips_fix_cn63xxp1 | |
11830 | && !mips_opts.micromips | |
11831 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11832 | switch (imm_expr.X_add_number) |
11833 | { | |
11834 | case 5: | |
11835 | case 25: | |
11836 | case 26: | |
11837 | case 27: | |
11838 | case 28: | |
11839 | case 29: | |
11840 | case 30: | |
11841 | case 31: /* These are ok. */ | |
11842 | break; | |
11843 | ||
11844 | default: /* The rest must be changed to 28. */ | |
11845 | imm_expr.X_add_number = 28; | |
11846 | break; | |
11847 | } | |
df58fc94 RS |
11848 | INSERT_OPERAND (mips_opts.micromips, |
11849 | CACHE, *ip, imm_expr.X_add_number); | |
11850 | break; | |
11851 | case 'h': | |
11852 | INSERT_OPERAND (mips_opts.micromips, | |
11853 | PREFX, *ip, imm_expr.X_add_number); | |
11854 | break; | |
11855 | case '1': | |
11856 | INSERT_OPERAND (mips_opts.micromips, | |
11857 | STYPE, *ip, imm_expr.X_add_number); | |
11858 | break; | |
d954098f | 11859 | } |
252b5132 RH |
11860 | imm_expr.X_op = O_absent; |
11861 | s = expr_end; | |
11862 | continue; | |
11863 | ||
90ecf173 | 11864 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11865 | { |
11866 | unsigned long mask = (mips_opts.micromips | |
11867 | ? MICROMIPSOP_MASK_CODE | |
11868 | : OP_MASK_CODE); | |
11869 | ||
11870 | my_getExpression (&imm_expr, s); | |
11871 | check_absolute_expr (ip, &imm_expr); | |
11872 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11873 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11874 | ip->insn_mo->name, | |
11875 | mask, (unsigned long) imm_expr.X_add_number); | |
11876 | INSERT_OPERAND (mips_opts.micromips, | |
11877 | CODE, *ip, imm_expr.X_add_number); | |
11878 | imm_expr.X_op = O_absent; | |
11879 | s = expr_end; | |
11880 | } | |
252b5132 RH |
11881 | continue; |
11882 | ||
90ecf173 | 11883 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11884 | { |
11885 | unsigned long mask = (mips_opts.micromips | |
11886 | ? MICROMIPSOP_MASK_CODE2 | |
11887 | : OP_MASK_CODE2); | |
11888 | ||
11889 | my_getExpression (&imm_expr, s); | |
11890 | check_absolute_expr (ip, &imm_expr); | |
11891 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11892 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11893 | ip->insn_mo->name, | |
11894 | mask, (unsigned long) imm_expr.X_add_number); | |
11895 | INSERT_OPERAND (mips_opts.micromips, | |
11896 | CODE2, *ip, imm_expr.X_add_number); | |
11897 | imm_expr.X_op = O_absent; | |
11898 | s = expr_end; | |
11899 | } | |
252b5132 RH |
11900 | continue; |
11901 | ||
df58fc94 RS |
11902 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11903 | { | |
11904 | unsigned long mask = (mips_opts.micromips | |
11905 | ? MICROMIPSOP_MASK_CODE10 | |
11906 | : OP_MASK_CODE20); | |
11907 | ||
11908 | my_getExpression (&imm_expr, s); | |
11909 | check_absolute_expr (ip, &imm_expr); | |
11910 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11911 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11912 | ip->insn_mo->name, | |
11913 | mask, (unsigned long) imm_expr.X_add_number); | |
11914 | if (mips_opts.micromips) | |
11915 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11916 | else | |
11917 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11918 | imm_expr.X_op = O_absent; | |
11919 | s = expr_end; | |
11920 | } | |
252b5132 RH |
11921 | continue; |
11922 | ||
df58fc94 RS |
11923 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11924 | { | |
11925 | unsigned long mask = (mips_opts.micromips | |
11926 | ? MICROMIPSOP_MASK_COPZ | |
11927 | : OP_MASK_COPZ); | |
11928 | ||
11929 | my_getExpression (&imm_expr, s); | |
11930 | check_absolute_expr (ip, &imm_expr); | |
11931 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11932 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11933 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11934 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11935 | INSERT_OPERAND (mips_opts.micromips, |
11936 | COPZ, *ip, imm_expr.X_add_number); | |
11937 | imm_expr.X_op = O_absent; | |
11938 | s = expr_end; | |
11939 | } | |
beae10d5 | 11940 | continue; |
252b5132 | 11941 | |
df58fc94 RS |
11942 | case 'J': /* 19-bit WAIT code. */ |
11943 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11944 | my_getExpression (&imm_expr, s); |
11945 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11946 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11947 | { |
11948 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11949 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11950 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11951 | } | |
11952 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11953 | imm_expr.X_op = O_absent; |
11954 | s = expr_end; | |
11955 | continue; | |
11956 | ||
707bfff6 | 11957 | case 'P': /* Performance register. */ |
df58fc94 | 11958 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11959 | my_getExpression (&imm_expr, s); |
252b5132 | 11960 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11961 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11962 | as_warn (_("Invalid performance register (%lu)"), |
11963 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
11964 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
11965 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
11966 | as_warn (_("Invalid performance register (%lu)"), | |
11967 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11968 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11969 | imm_expr.X_op = O_absent; |
11970 | s = expr_end; | |
11971 | continue; | |
252b5132 | 11972 | |
707bfff6 | 11973 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11974 | { |
11975 | unsigned long opcode = ip->insn_opcode; | |
11976 | unsigned long mask; | |
11977 | unsigned int types; | |
11978 | int cop0; | |
11979 | ||
11980 | if (mips_opts.micromips) | |
11981 | { | |
11982 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11983 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11984 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11985 | opcode &= mask; | |
11986 | switch (opcode) | |
11987 | { | |
11988 | case 0x000000fc: /* mfc0 */ | |
11989 | case 0x000002fc: /* mtc0 */ | |
11990 | case 0x580000fc: /* dmfc0 */ | |
11991 | case 0x580002fc: /* dmtc0 */ | |
11992 | cop0 = 1; | |
11993 | break; | |
11994 | default: | |
11995 | cop0 = 0; | |
11996 | break; | |
11997 | } | |
11998 | } | |
11999 | else | |
12000 | { | |
12001 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12002 | cop0 = opcode == OP_OP_COP0; | |
12003 | } | |
12004 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12005 | ok = reg_lookup (&s, types, ®no); | |
12006 | if (mips_opts.micromips) | |
12007 | INSERT_OPERAND (1, RS, *ip, regno); | |
12008 | else | |
12009 | INSERT_OPERAND (0, RD, *ip, regno); | |
12010 | if (ok) | |
12011 | { | |
12012 | lastregno = regno; | |
12013 | continue; | |
12014 | } | |
12015 | } | |
12016 | break; | |
707bfff6 | 12017 | |
df58fc94 RS |
12018 | case 'y': /* ALNV.PS source register. */ |
12019 | gas_assert (mips_opts.micromips); | |
12020 | goto do_reg; | |
12021 | case 'x': /* Ignore register name. */ | |
12022 | case 'U': /* Destination register (CLO/CLZ). */ | |
12023 | case 'g': /* Coprocessor destination register. */ | |
12024 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12025 | case 'b': /* Base register. */ |
12026 | case 'd': /* Destination register. */ | |
12027 | case 's': /* Source register. */ | |
12028 | case 't': /* Target register. */ | |
12029 | case 'r': /* Both target and source. */ | |
12030 | case 'v': /* Both dest and source. */ | |
12031 | case 'w': /* Both dest and target. */ | |
12032 | case 'E': /* Coprocessor target register. */ | |
12033 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12034 | case 'z': /* Must be zero register. */ |
df58fc94 | 12035 | do_reg: |
90ecf173 | 12036 | s_reset = s; |
707bfff6 TS |
12037 | if (*args == 'E' || *args == 'K') |
12038 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12039 | else | |
12040 | { | |
12041 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12042 | if (regno == AT && mips_opts.at) |
12043 | { | |
12044 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12045 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12046 | else |
f71d0d44 | 12047 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12048 | regno, mips_opts.at); |
12049 | } | |
707bfff6 TS |
12050 | } |
12051 | if (ok) | |
252b5132 | 12052 | { |
252b5132 RH |
12053 | c = *args; |
12054 | if (*s == ' ') | |
f9419b05 | 12055 | ++s; |
252b5132 RH |
12056 | if (args[1] != *s) |
12057 | { | |
12058 | if (c == 'r' || c == 'v' || c == 'w') | |
12059 | { | |
12060 | regno = lastregno; | |
12061 | s = s_reset; | |
f9419b05 | 12062 | ++args; |
252b5132 RH |
12063 | } |
12064 | } | |
12065 | /* 'z' only matches $0. */ | |
12066 | if (c == 'z' && regno != 0) | |
12067 | break; | |
12068 | ||
24864476 | 12069 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12070 | { |
12071 | if (regno == lastregno) | |
90ecf173 MR |
12072 | { |
12073 | insn_error | |
f71d0d44 | 12074 | = _("Source and destination must be different"); |
e7c604dd | 12075 | continue; |
90ecf173 | 12076 | } |
24864476 | 12077 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12078 | { |
12079 | insn_error | |
f71d0d44 | 12080 | = _("A destination register must be supplied"); |
e7c604dd | 12081 | continue; |
90ecf173 | 12082 | } |
e7c604dd | 12083 | } |
90ecf173 MR |
12084 | /* Now that we have assembled one operand, we use the args |
12085 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12086 | switch (c) |
12087 | { | |
12088 | case 'r': | |
12089 | case 's': | |
12090 | case 'v': | |
12091 | case 'b': | |
df58fc94 | 12092 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12093 | break; |
df58fc94 | 12094 | |
af7ee8bf | 12095 | case 'K': |
df58fc94 RS |
12096 | if (mips_opts.micromips) |
12097 | INSERT_OPERAND (1, RS, *ip, regno); | |
12098 | else | |
12099 | INSERT_OPERAND (0, RD, *ip, regno); | |
12100 | break; | |
12101 | ||
12102 | case 'd': | |
ef2e4d86 | 12103 | case 'g': |
df58fc94 | 12104 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12105 | break; |
df58fc94 | 12106 | |
4372b673 | 12107 | case 'U': |
df58fc94 RS |
12108 | gas_assert (!mips_opts.micromips); |
12109 | INSERT_OPERAND (0, RD, *ip, regno); | |
12110 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12111 | break; |
df58fc94 | 12112 | |
252b5132 RH |
12113 | case 'w': |
12114 | case 't': | |
12115 | case 'E': | |
df58fc94 RS |
12116 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12117 | break; | |
12118 | ||
12119 | case 'y': | |
12120 | gas_assert (mips_opts.micromips); | |
12121 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12122 | break; |
df58fc94 | 12123 | |
252b5132 RH |
12124 | case 'x': |
12125 | /* This case exists because on the r3000 trunc | |
12126 | expands into a macro which requires a gp | |
12127 | register. On the r6000 or r4000 it is | |
12128 | assembled into a single instruction which | |
12129 | ignores the register. Thus the insn version | |
12130 | is MIPS_ISA2 and uses 'x', and the macro | |
12131 | version is MIPS_ISA1 and uses 't'. */ | |
12132 | break; | |
df58fc94 | 12133 | |
252b5132 RH |
12134 | case 'z': |
12135 | /* This case is for the div instruction, which | |
12136 | acts differently if the destination argument | |
12137 | is $0. This only matches $0, and is checked | |
12138 | outside the switch. */ | |
12139 | break; | |
252b5132 RH |
12140 | } |
12141 | lastregno = regno; | |
12142 | continue; | |
12143 | } | |
252b5132 RH |
12144 | switch (*args++) |
12145 | { | |
12146 | case 'r': | |
12147 | case 'v': | |
df58fc94 | 12148 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12149 | continue; |
df58fc94 | 12150 | |
252b5132 | 12151 | case 'w': |
df58fc94 | 12152 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12153 | continue; |
12154 | } | |
12155 | break; | |
12156 | ||
deec1734 | 12157 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12158 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12159 | my_getExpression (&imm_expr, s); |
12160 | check_absolute_expr (ip, &imm_expr); | |
12161 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12162 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12163 | (long) imm_expr.X_add_number); |
df58fc94 | 12164 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12165 | imm_expr.X_op = O_absent; |
12166 | s = expr_end; | |
12167 | continue; | |
12168 | ||
12169 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12170 | if (s[0] != '$') | |
12171 | { | |
12172 | /* MDMX Immediate. */ | |
df58fc94 | 12173 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12174 | my_getExpression (&imm_expr, s); |
12175 | check_absolute_expr (ip, &imm_expr); | |
12176 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12177 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12178 | (long) imm_expr.X_add_number); | |
df58fc94 | 12179 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12180 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12181 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12182 | else | |
12183 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12184 | imm_expr.X_op = O_absent; |
12185 | s = expr_end; | |
12186 | continue; | |
12187 | } | |
12188 | /* Not MDMX Immediate. Fall through. */ | |
12189 | case 'X': /* MDMX destination register. */ | |
12190 | case 'Y': /* MDMX source register. */ | |
12191 | case 'Z': /* MDMX target register. */ | |
12192 | is_mdmx = 1; | |
df58fc94 RS |
12193 | case 'W': |
12194 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12195 | case 'D': /* Floating point destination register. */ |
12196 | case 'S': /* Floating point source register. */ | |
12197 | case 'T': /* Floating point target register. */ | |
12198 | case 'R': /* Floating point source register. */ | |
252b5132 | 12199 | case 'V': |
707bfff6 TS |
12200 | rtype = RTYPE_FPU; |
12201 | if (is_mdmx | |
12202 | || (mips_opts.ase_mdmx | |
12203 | && (ip->insn_mo->pinfo & FP_D) | |
12204 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12205 | | INSN_COPROC_MEMORY_DELAY | |
12206 | | INSN_LOAD_COPROC_DELAY | |
12207 | | INSN_LOAD_MEMORY_DELAY | |
12208 | | INSN_STORE_MEMORY)))) | |
12209 | rtype |= RTYPE_VEC; | |
252b5132 | 12210 | s_reset = s; |
707bfff6 | 12211 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12212 | { |
252b5132 | 12213 | if ((regno & 1) != 0 |
ca4e0257 | 12214 | && HAVE_32BIT_FPRS |
90ecf173 | 12215 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12216 | as_warn (_("Float register should be even, was %d"), |
12217 | regno); | |
12218 | ||
12219 | c = *args; | |
12220 | if (*s == ' ') | |
f9419b05 | 12221 | ++s; |
252b5132 RH |
12222 | if (args[1] != *s) |
12223 | { | |
12224 | if (c == 'V' || c == 'W') | |
12225 | { | |
12226 | regno = lastregno; | |
12227 | s = s_reset; | |
f9419b05 | 12228 | ++args; |
252b5132 RH |
12229 | } |
12230 | } | |
12231 | switch (c) | |
12232 | { | |
12233 | case 'D': | |
deec1734 | 12234 | case 'X': |
df58fc94 | 12235 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12236 | break; |
df58fc94 | 12237 | |
252b5132 RH |
12238 | case 'V': |
12239 | case 'S': | |
deec1734 | 12240 | case 'Y': |
df58fc94 | 12241 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12242 | break; |
df58fc94 | 12243 | |
deec1734 CD |
12244 | case 'Q': |
12245 | /* This is like 'Z', but also needs to fix the MDMX | |
12246 | vector/scalar select bits. Note that the | |
12247 | scalar immediate case is handled above. */ | |
12248 | if (*s == '[') | |
12249 | { | |
12250 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12251 | int max_el = (is_qh ? 3 : 7); | |
12252 | s++; | |
12253 | my_getExpression(&imm_expr, s); | |
12254 | check_absolute_expr (ip, &imm_expr); | |
12255 | s = expr_end; | |
12256 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12257 | as_bad (_("Bad element selector %ld"), |
12258 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12259 | imm_expr.X_add_number &= max_el; |
12260 | ip->insn_opcode |= (imm_expr.X_add_number | |
12261 | << (OP_SH_VSEL + | |
12262 | (is_qh ? 2 : 1))); | |
01a3f561 | 12263 | imm_expr.X_op = O_absent; |
deec1734 | 12264 | if (*s != ']') |
20203fb9 | 12265 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12266 | else |
12267 | s++; | |
12268 | } | |
12269 | else | |
12270 | { | |
12271 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12272 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12273 | << OP_SH_VSEL); | |
12274 | else | |
12275 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12276 | OP_SH_VSEL); | |
12277 | } | |
90ecf173 | 12278 | /* Fall through. */ |
252b5132 RH |
12279 | case 'W': |
12280 | case 'T': | |
deec1734 | 12281 | case 'Z': |
df58fc94 | 12282 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12283 | break; |
df58fc94 | 12284 | |
252b5132 | 12285 | case 'R': |
df58fc94 | 12286 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12287 | break; |
12288 | } | |
12289 | lastregno = regno; | |
12290 | continue; | |
12291 | } | |
12292 | ||
252b5132 RH |
12293 | switch (*args++) |
12294 | { | |
12295 | case 'V': | |
df58fc94 | 12296 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12297 | continue; |
df58fc94 | 12298 | |
252b5132 | 12299 | case 'W': |
df58fc94 | 12300 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12301 | continue; |
12302 | } | |
12303 | break; | |
12304 | ||
12305 | case 'I': | |
12306 | my_getExpression (&imm_expr, s); | |
12307 | if (imm_expr.X_op != O_big | |
12308 | && imm_expr.X_op != O_constant) | |
12309 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12310 | if (HAVE_32BIT_GPRS) |
12311 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12312 | s = expr_end; |
12313 | continue; | |
12314 | ||
12315 | case 'A': | |
12316 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12317 | normalize_address_expr (&offset_expr); |
f6688943 | 12318 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12319 | s = expr_end; |
12320 | continue; | |
12321 | ||
12322 | case 'F': | |
12323 | case 'L': | |
12324 | case 'f': | |
12325 | case 'l': | |
12326 | { | |
12327 | int f64; | |
ca4e0257 | 12328 | int using_gprs; |
252b5132 RH |
12329 | char *save_in; |
12330 | char *err; | |
12331 | unsigned char temp[8]; | |
12332 | int len; | |
12333 | unsigned int length; | |
12334 | segT seg; | |
12335 | subsegT subseg; | |
12336 | char *p; | |
12337 | ||
12338 | /* These only appear as the last operand in an | |
12339 | instruction, and every instruction that accepts | |
12340 | them in any variant accepts them in all variants. | |
12341 | This means we don't have to worry about backing out | |
12342 | any changes if the instruction does not match. | |
12343 | ||
12344 | The difference between them is the size of the | |
12345 | floating point constant and where it goes. For 'F' | |
12346 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12347 | is 32 bits. Where the constant is placed is based | |
12348 | on how the MIPS assembler does things: | |
12349 | F -- .rdata | |
12350 | L -- .lit8 | |
12351 | f -- immediate value | |
12352 | l -- .lit4 | |
12353 | ||
12354 | The .lit4 and .lit8 sections are only used if | |
12355 | permitted by the -G argument. | |
12356 | ||
ca4e0257 RS |
12357 | The code below needs to know whether the target register |
12358 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12359 | 'F' are used with GPR-based instructions and 'l' and | |
12360 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12361 | |
12362 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12363 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12364 | |
12365 | save_in = input_line_pointer; | |
12366 | input_line_pointer = s; | |
12367 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12368 | length = len; | |
12369 | s = input_line_pointer; | |
12370 | input_line_pointer = save_in; | |
12371 | if (err != NULL && *err != '\0') | |
12372 | { | |
12373 | as_bad (_("Bad floating point constant: %s"), err); | |
12374 | memset (temp, '\0', sizeof temp); | |
12375 | length = f64 ? 8 : 4; | |
12376 | } | |
12377 | ||
9c2799c2 | 12378 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12379 | |
12380 | if (*args == 'f' | |
12381 | || (*args == 'l' | |
3e722fb5 | 12382 | && (g_switch_value < 4 |
252b5132 RH |
12383 | || (temp[0] == 0 && temp[1] == 0) |
12384 | || (temp[2] == 0 && temp[3] == 0)))) | |
12385 | { | |
12386 | imm_expr.X_op = O_constant; | |
90ecf173 | 12387 | if (!target_big_endian) |
252b5132 RH |
12388 | imm_expr.X_add_number = bfd_getl32 (temp); |
12389 | else | |
12390 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12391 | } | |
12392 | else if (length > 4 | |
90ecf173 | 12393 | && !mips_disable_float_construction |
ca4e0257 RS |
12394 | /* Constants can only be constructed in GPRs and |
12395 | copied to FPRs if the GPRs are at least as wide | |
12396 | as the FPRs. Force the constant into memory if | |
12397 | we are using 64-bit FPRs but the GPRs are only | |
12398 | 32 bits wide. */ | |
12399 | && (using_gprs | |
90ecf173 | 12400 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12401 | && ((temp[0] == 0 && temp[1] == 0) |
12402 | || (temp[2] == 0 && temp[3] == 0)) | |
12403 | && ((temp[4] == 0 && temp[5] == 0) | |
12404 | || (temp[6] == 0 && temp[7] == 0))) | |
12405 | { | |
ca4e0257 | 12406 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12407 | instructions. If using 32-bit registers, set |
12408 | imm_expr to the high order 32 bits and offset_expr to | |
12409 | the low order 32 bits. Otherwise, set imm_expr to | |
12410 | the entire 64 bit constant. */ | |
ca4e0257 | 12411 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12412 | { |
12413 | imm_expr.X_op = O_constant; | |
12414 | offset_expr.X_op = O_constant; | |
90ecf173 | 12415 | if (!target_big_endian) |
252b5132 RH |
12416 | { |
12417 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12418 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12419 | } | |
12420 | else | |
12421 | { | |
12422 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12423 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12424 | } | |
12425 | if (offset_expr.X_add_number == 0) | |
12426 | offset_expr.X_op = O_absent; | |
12427 | } | |
12428 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12429 | { | |
12430 | imm_expr.X_op = O_constant; | |
90ecf173 | 12431 | if (!target_big_endian) |
252b5132 RH |
12432 | imm_expr.X_add_number = bfd_getl64 (temp); |
12433 | else | |
12434 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12435 | } | |
12436 | else | |
12437 | { | |
12438 | imm_expr.X_op = O_big; | |
12439 | imm_expr.X_add_number = 4; | |
90ecf173 | 12440 | if (!target_big_endian) |
252b5132 RH |
12441 | { |
12442 | generic_bignum[0] = bfd_getl16 (temp); | |
12443 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12444 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12445 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12446 | } | |
12447 | else | |
12448 | { | |
12449 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12450 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12451 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12452 | generic_bignum[3] = bfd_getb16 (temp); | |
12453 | } | |
12454 | } | |
12455 | } | |
12456 | else | |
12457 | { | |
12458 | const char *newname; | |
12459 | segT new_seg; | |
12460 | ||
12461 | /* Switch to the right section. */ | |
12462 | seg = now_seg; | |
12463 | subseg = now_subseg; | |
12464 | switch (*args) | |
12465 | { | |
12466 | default: /* unused default case avoids warnings. */ | |
12467 | case 'L': | |
12468 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12469 | if (g_switch_value >= 8) |
252b5132 RH |
12470 | newname = ".lit8"; |
12471 | break; | |
12472 | case 'F': | |
3e722fb5 | 12473 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12474 | break; |
12475 | case 'l': | |
9c2799c2 | 12476 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12477 | newname = ".lit4"; |
12478 | break; | |
12479 | } | |
12480 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12481 | if (IS_ELF) |
252b5132 RH |
12482 | bfd_set_section_flags (stdoutput, new_seg, |
12483 | (SEC_ALLOC | |
12484 | | SEC_LOAD | |
12485 | | SEC_READONLY | |
12486 | | SEC_DATA)); | |
12487 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12488 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12489 | record_alignment (new_seg, 4); |
12490 | else | |
12491 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12492 | if (seg == now_seg) | |
12493 | as_bad (_("Can't use floating point insn in this section")); | |
12494 | ||
df58fc94 RS |
12495 | /* Set the argument to the current address in the |
12496 | section. */ | |
12497 | offset_expr.X_op = O_symbol; | |
12498 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12499 | offset_expr.X_add_number = 0; | |
12500 | ||
12501 | /* Put the floating point number into the section. */ | |
12502 | p = frag_more ((int) length); | |
12503 | memcpy (p, temp, length); | |
12504 | ||
12505 | /* Switch back to the original section. */ | |
12506 | subseg_set (seg, subseg); | |
12507 | } | |
12508 | } | |
12509 | continue; | |
12510 | ||
12511 | case 'i': /* 16-bit unsigned immediate. */ | |
12512 | case 'j': /* 16-bit signed immediate. */ | |
12513 | *imm_reloc = BFD_RELOC_LO16; | |
12514 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12515 | { | |
12516 | int more; | |
12517 | offsetT minval, maxval; | |
12518 | ||
12519 | more = (insn + 1 < past | |
12520 | && strcmp (insn->name, insn[1].name) == 0); | |
12521 | ||
12522 | /* If the expression was written as an unsigned number, | |
12523 | only treat it as signed if there are no more | |
12524 | alternatives. */ | |
12525 | if (more | |
12526 | && *args == 'j' | |
12527 | && sizeof (imm_expr.X_add_number) <= 4 | |
12528 | && imm_expr.X_op == O_constant | |
12529 | && imm_expr.X_add_number < 0 | |
12530 | && imm_expr.X_unsigned | |
12531 | && HAVE_64BIT_GPRS) | |
12532 | break; | |
12533 | ||
12534 | /* For compatibility with older assemblers, we accept | |
12535 | 0x8000-0xffff as signed 16-bit numbers when only | |
12536 | signed numbers are allowed. */ | |
12537 | if (*args == 'i') | |
12538 | minval = 0, maxval = 0xffff; | |
12539 | else if (more) | |
12540 | minval = -0x8000, maxval = 0x7fff; | |
12541 | else | |
12542 | minval = -0x8000, maxval = 0xffff; | |
12543 | ||
12544 | if (imm_expr.X_op != O_constant | |
12545 | || imm_expr.X_add_number < minval | |
12546 | || imm_expr.X_add_number > maxval) | |
12547 | { | |
12548 | if (more) | |
12549 | break; | |
12550 | if (imm_expr.X_op == O_constant | |
12551 | || imm_expr.X_op == O_big) | |
12552 | as_bad (_("Expression out of range")); | |
12553 | } | |
12554 | } | |
12555 | s = expr_end; | |
12556 | continue; | |
12557 | ||
12558 | case 'o': /* 16-bit offset. */ | |
12559 | offset_reloc[0] = BFD_RELOC_LO16; | |
12560 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12561 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12562 | ||
12563 | /* Check whether there is only a single bracketed expression | |
12564 | left. If so, it must be the base register and the | |
12565 | constant must be zero. */ | |
12566 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12567 | { | |
12568 | offset_expr.X_op = O_constant; | |
12569 | offset_expr.X_add_number = 0; | |
12570 | continue; | |
12571 | } | |
12572 | ||
12573 | /* If this value won't fit into a 16 bit offset, then go | |
12574 | find a macro that will generate the 32 bit offset | |
12575 | code pattern. */ | |
12576 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12577 | && (offset_expr.X_op != O_constant | |
12578 | || offset_expr.X_add_number >= 0x8000 | |
12579 | || offset_expr.X_add_number < -0x8000)) | |
12580 | break; | |
12581 | ||
12582 | s = expr_end; | |
12583 | continue; | |
12584 | ||
12585 | case 'p': /* PC-relative offset. */ | |
12586 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12587 | my_getExpression (&offset_expr, s); | |
12588 | s = expr_end; | |
12589 | continue; | |
12590 | ||
12591 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12592 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12593 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12594 | && imm_expr.X_op == O_constant | |
12595 | && (imm_expr.X_add_number < 0 | |
12596 | || imm_expr.X_add_number >= 0x10000)) | |
12597 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12598 | (unsigned long) imm_expr.X_add_number); | |
12599 | s = expr_end; | |
12600 | continue; | |
12601 | ||
12602 | case 'a': /* 26-bit address. */ | |
12603 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12604 | my_getExpression (&offset_expr, s); | |
12605 | s = expr_end; | |
12606 | continue; | |
12607 | ||
12608 | case 'N': /* 3-bit branch condition code. */ | |
12609 | case 'M': /* 3-bit compare condition code. */ | |
12610 | rtype = RTYPE_CCC; | |
12611 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12612 | rtype |= RTYPE_FCC; | |
12613 | if (!reg_lookup (&s, rtype, ®no)) | |
12614 | break; | |
12615 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12616 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12617 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12618 | && (regno & 1) != 0) | |
12619 | as_warn (_("Condition code register should be even for %s, " | |
12620 | "was %d"), | |
12621 | str, regno); | |
12622 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12623 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12624 | && (regno & 3) != 0) | |
12625 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12626 | "was %d"), | |
12627 | str, regno); | |
12628 | if (*args == 'N') | |
12629 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12630 | else | |
12631 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12632 | continue; | |
12633 | ||
12634 | case 'H': | |
12635 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12636 | s += 2; | |
12637 | if (ISDIGIT (*s)) | |
12638 | { | |
12639 | c = 0; | |
12640 | do | |
12641 | { | |
12642 | c *= 10; | |
12643 | c += *s - '0'; | |
12644 | ++s; | |
12645 | } | |
12646 | while (ISDIGIT (*s)); | |
12647 | } | |
12648 | else | |
12649 | c = 8; /* Invalid sel value. */ | |
12650 | ||
12651 | if (c > 7) | |
12652 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12653 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12654 | continue; | |
12655 | ||
12656 | case 'e': | |
12657 | gas_assert (!mips_opts.micromips); | |
12658 | /* Must be at least one digit. */ | |
12659 | my_getExpression (&imm_expr, s); | |
12660 | check_absolute_expr (ip, &imm_expr); | |
12661 | ||
12662 | if ((unsigned long) imm_expr.X_add_number | |
12663 | > (unsigned long) OP_MASK_VECBYTE) | |
12664 | { | |
12665 | as_bad (_("bad byte vector index (%ld)"), | |
12666 | (long) imm_expr.X_add_number); | |
12667 | imm_expr.X_add_number = 0; | |
12668 | } | |
12669 | ||
12670 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12671 | imm_expr.X_op = O_absent; | |
12672 | s = expr_end; | |
12673 | continue; | |
12674 | ||
12675 | case '%': | |
12676 | gas_assert (!mips_opts.micromips); | |
12677 | my_getExpression (&imm_expr, s); | |
12678 | check_absolute_expr (ip, &imm_expr); | |
12679 | ||
12680 | if ((unsigned long) imm_expr.X_add_number | |
12681 | > (unsigned long) OP_MASK_VECALIGN) | |
12682 | { | |
12683 | as_bad (_("bad byte vector index (%ld)"), | |
12684 | (long) imm_expr.X_add_number); | |
12685 | imm_expr.X_add_number = 0; | |
12686 | } | |
12687 | ||
12688 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12689 | imm_expr.X_op = O_absent; | |
12690 | s = expr_end; | |
12691 | continue; | |
12692 | ||
12693 | case 'm': /* Opcode extension character. */ | |
12694 | gas_assert (mips_opts.micromips); | |
12695 | c = *++args; | |
12696 | switch (c) | |
12697 | { | |
12698 | case 'r': | |
12699 | if (strncmp (s, "$pc", 3) == 0) | |
12700 | { | |
12701 | s += 3; | |
12702 | continue; | |
12703 | } | |
12704 | break; | |
12705 | ||
12706 | case 'a': | |
12707 | case 'b': | |
12708 | case 'c': | |
12709 | case 'd': | |
12710 | case 'e': | |
12711 | case 'f': | |
12712 | case 'g': | |
12713 | case 'h': | |
12714 | case 'i': | |
12715 | case 'j': | |
12716 | case 'l': | |
12717 | case 'm': | |
12718 | case 'n': | |
12719 | case 'p': | |
12720 | case 'q': | |
12721 | case 's': | |
12722 | case 't': | |
12723 | case 'x': | |
12724 | case 'y': | |
12725 | case 'z': | |
12726 | s_reset = s; | |
12727 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12728 | if (regno == AT && mips_opts.at) | |
12729 | { | |
12730 | if (mips_opts.at == ATREG) | |
12731 | as_warn (_("Used $at without \".set noat\"")); | |
12732 | else | |
12733 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12734 | regno, mips_opts.at); | |
12735 | } | |
12736 | if (!ok) | |
12737 | { | |
12738 | if (c == 'c') | |
12739 | { | |
12740 | gas_assert (args[1] == ','); | |
12741 | regno = lastregno; | |
12742 | ++args; | |
12743 | } | |
12744 | else if (c == 't') | |
12745 | { | |
12746 | gas_assert (args[1] == ','); | |
12747 | ++args; | |
12748 | continue; /* Nothing to do. */ | |
12749 | } | |
12750 | else | |
12751 | break; | |
12752 | } | |
12753 | ||
12754 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12755 | { | |
12756 | if (regno == lastregno) | |
12757 | { | |
12758 | insn_error | |
12759 | = _("Source and destination must be different"); | |
12760 | continue; | |
12761 | } | |
12762 | if (regno == 31 && lastregno == 0xffffffff) | |
12763 | { | |
12764 | insn_error | |
12765 | = _("A destination register must be supplied"); | |
12766 | continue; | |
12767 | } | |
12768 | } | |
12769 | ||
12770 | if (*s == ' ') | |
12771 | ++s; | |
12772 | if (args[1] != *s) | |
12773 | { | |
12774 | if (c == 'e') | |
12775 | { | |
12776 | gas_assert (args[1] == ','); | |
12777 | regno = lastregno; | |
12778 | s = s_reset; | |
12779 | ++args; | |
12780 | } | |
12781 | else if (c == 't') | |
12782 | { | |
12783 | gas_assert (args[1] == ','); | |
12784 | s = s_reset; | |
12785 | ++args; | |
12786 | continue; /* Nothing to do. */ | |
12787 | } | |
12788 | } | |
12789 | ||
12790 | /* Make sure regno is the same as lastregno. */ | |
12791 | if (c == 't' && regno != lastregno) | |
12792 | break; | |
12793 | ||
12794 | /* Make sure regno is the same as destregno. */ | |
12795 | if (c == 'x' && regno != destregno) | |
12796 | break; | |
12797 | ||
12798 | /* We need to save regno, before regno maps to the | |
12799 | microMIPS register encoding. */ | |
12800 | lastregno = regno; | |
12801 | ||
12802 | if (c == 'f') | |
12803 | destregno = regno; | |
12804 | ||
12805 | switch (c) | |
12806 | { | |
12807 | case 'a': | |
12808 | if (regno != GP) | |
12809 | regno = ILLEGAL_REG; | |
12810 | break; | |
12811 | ||
12812 | case 'b': | |
12813 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12814 | break; | |
12815 | ||
12816 | case 'c': | |
12817 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12818 | break; | |
12819 | ||
12820 | case 'd': | |
12821 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12822 | break; | |
12823 | ||
12824 | case 'e': | |
12825 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12826 | break; | |
12827 | ||
12828 | case 'f': | |
12829 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12830 | break; | |
12831 | ||
12832 | case 'g': | |
12833 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12834 | break; | |
12835 | ||
12836 | case 'h': | |
12837 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12838 | break; | |
12839 | ||
12840 | case 'i': | |
12841 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12842 | { | |
12843 | case 4: | |
12844 | if (regno == 21) | |
12845 | regno = 3; | |
12846 | else if (regno == 22) | |
12847 | regno = 4; | |
12848 | else if (regno == 5) | |
12849 | regno = 5; | |
12850 | else if (regno == 6) | |
12851 | regno = 6; | |
12852 | else if (regno == 7) | |
12853 | regno = 7; | |
12854 | else | |
12855 | regno = ILLEGAL_REG; | |
12856 | break; | |
12857 | ||
12858 | case 5: | |
12859 | if (regno == 6) | |
12860 | regno = 0; | |
12861 | else if (regno == 7) | |
12862 | regno = 1; | |
12863 | else | |
12864 | regno = ILLEGAL_REG; | |
12865 | break; | |
12866 | ||
12867 | case 6: | |
12868 | if (regno == 7) | |
12869 | regno = 2; | |
12870 | else | |
12871 | regno = ILLEGAL_REG; | |
12872 | break; | |
12873 | ||
12874 | default: | |
12875 | regno = ILLEGAL_REG; | |
12876 | break; | |
12877 | } | |
12878 | break; | |
12879 | ||
12880 | case 'l': | |
12881 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12882 | break; | |
12883 | ||
12884 | case 'm': | |
12885 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12886 | break; | |
12887 | ||
12888 | case 'n': | |
12889 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12890 | break; | |
12891 | ||
12892 | case 'q': | |
12893 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12894 | break; | |
12895 | ||
12896 | case 's': | |
12897 | if (regno != SP) | |
12898 | regno = ILLEGAL_REG; | |
12899 | break; | |
12900 | ||
12901 | case 'y': | |
12902 | if (regno != 31) | |
12903 | regno = ILLEGAL_REG; | |
12904 | break; | |
12905 | ||
12906 | case 'z': | |
12907 | if (regno != ZERO) | |
12908 | regno = ILLEGAL_REG; | |
12909 | break; | |
12910 | ||
12911 | case 'j': /* Do nothing. */ | |
12912 | case 'p': | |
12913 | case 't': | |
12914 | case 'x': | |
12915 | break; | |
12916 | ||
12917 | default: | |
b37df7c4 | 12918 | abort (); |
df58fc94 RS |
12919 | } |
12920 | ||
12921 | if (regno == ILLEGAL_REG) | |
12922 | break; | |
12923 | ||
12924 | switch (c) | |
12925 | { | |
12926 | case 'b': | |
12927 | INSERT_OPERAND (1, MB, *ip, regno); | |
12928 | break; | |
12929 | ||
12930 | case 'c': | |
12931 | INSERT_OPERAND (1, MC, *ip, regno); | |
12932 | break; | |
12933 | ||
12934 | case 'd': | |
12935 | INSERT_OPERAND (1, MD, *ip, regno); | |
12936 | break; | |
12937 | ||
12938 | case 'e': | |
12939 | INSERT_OPERAND (1, ME, *ip, regno); | |
12940 | break; | |
12941 | ||
12942 | case 'f': | |
12943 | INSERT_OPERAND (1, MF, *ip, regno); | |
12944 | break; | |
12945 | ||
12946 | case 'g': | |
12947 | INSERT_OPERAND (1, MG, *ip, regno); | |
12948 | break; | |
12949 | ||
12950 | case 'h': | |
12951 | INSERT_OPERAND (1, MH, *ip, regno); | |
12952 | break; | |
12953 | ||
12954 | case 'i': | |
12955 | INSERT_OPERAND (1, MI, *ip, regno); | |
12956 | break; | |
12957 | ||
12958 | case 'j': | |
12959 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12960 | break; | |
12961 | ||
12962 | case 'l': | |
12963 | INSERT_OPERAND (1, ML, *ip, regno); | |
12964 | break; | |
12965 | ||
12966 | case 'm': | |
12967 | INSERT_OPERAND (1, MM, *ip, regno); | |
12968 | break; | |
12969 | ||
12970 | case 'n': | |
12971 | INSERT_OPERAND (1, MN, *ip, regno); | |
12972 | break; | |
12973 | ||
12974 | case 'p': | |
12975 | INSERT_OPERAND (1, MP, *ip, regno); | |
12976 | break; | |
12977 | ||
12978 | case 'q': | |
12979 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12980 | break; | |
12981 | ||
12982 | case 'a': /* Do nothing. */ | |
12983 | case 's': /* Do nothing. */ | |
12984 | case 't': /* Do nothing. */ | |
12985 | case 'x': /* Do nothing. */ | |
12986 | case 'y': /* Do nothing. */ | |
12987 | case 'z': /* Do nothing. */ | |
12988 | break; | |
12989 | ||
12990 | default: | |
b37df7c4 | 12991 | abort (); |
df58fc94 RS |
12992 | } |
12993 | continue; | |
12994 | ||
12995 | case 'A': | |
12996 | { | |
12997 | bfd_reloc_code_real_type r[3]; | |
12998 | expressionS ep; | |
12999 | int imm; | |
13000 | ||
13001 | /* Check whether there is only a single bracketed | |
13002 | expression left. If so, it must be the base register | |
13003 | and the constant must be zero. */ | |
13004 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13005 | { | |
13006 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13007 | continue; | |
13008 | } | |
13009 | ||
13010 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13011 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13012 | break; | |
13013 | ||
13014 | imm = ep.X_add_number >> 2; | |
13015 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13016 | } | |
13017 | s = expr_end; | |
13018 | continue; | |
13019 | ||
13020 | case 'B': | |
13021 | { | |
13022 | bfd_reloc_code_real_type r[3]; | |
13023 | expressionS ep; | |
13024 | int imm; | |
13025 | ||
13026 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13027 | || ep.X_op != O_constant) | |
13028 | break; | |
13029 | ||
13030 | for (imm = 0; imm < 8; imm++) | |
13031 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13032 | break; | |
13033 | if (imm >= 8) | |
13034 | break; | |
13035 | ||
13036 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13037 | } | |
13038 | s = expr_end; | |
13039 | continue; | |
13040 | ||
13041 | case 'C': | |
13042 | { | |
13043 | bfd_reloc_code_real_type r[3]; | |
13044 | expressionS ep; | |
13045 | int imm; | |
13046 | ||
13047 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13048 | || ep.X_op != O_constant) | |
13049 | break; | |
13050 | ||
13051 | for (imm = 0; imm < 16; imm++) | |
13052 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13053 | break; | |
13054 | if (imm >= 16) | |
13055 | break; | |
13056 | ||
13057 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13058 | } | |
13059 | s = expr_end; | |
13060 | continue; | |
13061 | ||
13062 | case 'D': /* pc relative offset */ | |
13063 | case 'E': /* pc relative offset */ | |
13064 | my_getExpression (&offset_expr, s); | |
13065 | if (offset_expr.X_op == O_register) | |
13066 | break; | |
13067 | ||
40209cad MR |
13068 | if (!forced_insn_length) |
13069 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13070 | else if (c == 'D') | |
13071 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13072 | else | |
13073 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13074 | s = expr_end; |
13075 | continue; | |
13076 | ||
13077 | case 'F': | |
13078 | { | |
13079 | bfd_reloc_code_real_type r[3]; | |
13080 | expressionS ep; | |
13081 | int imm; | |
13082 | ||
13083 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13084 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13085 | break; | |
13086 | ||
13087 | imm = ep.X_add_number; | |
13088 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13089 | } | |
13090 | s = expr_end; | |
13091 | continue; | |
13092 | ||
13093 | case 'G': | |
13094 | { | |
13095 | bfd_reloc_code_real_type r[3]; | |
13096 | expressionS ep; | |
13097 | int imm; | |
13098 | ||
13099 | /* Check whether there is only a single bracketed | |
13100 | expression left. If so, it must be the base register | |
13101 | and the constant must be zero. */ | |
13102 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13103 | { | |
13104 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13105 | continue; | |
13106 | } | |
13107 | ||
13108 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13109 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13110 | break; | |
13111 | ||
13112 | imm = ep.X_add_number & 15; | |
13113 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13114 | } | |
13115 | s = expr_end; | |
13116 | continue; | |
13117 | ||
13118 | case 'H': | |
13119 | { | |
13120 | bfd_reloc_code_real_type r[3]; | |
13121 | expressionS ep; | |
13122 | int imm; | |
13123 | ||
13124 | /* Check whether there is only a single bracketed | |
13125 | expression left. If so, it must be the base register | |
13126 | and the constant must be zero. */ | |
13127 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13128 | { | |
13129 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13130 | continue; | |
13131 | } | |
13132 | ||
13133 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13134 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13135 | break; | |
13136 | ||
13137 | imm = ep.X_add_number >> 1; | |
13138 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13139 | } | |
13140 | s = expr_end; | |
13141 | continue; | |
13142 | ||
13143 | case 'I': | |
13144 | { | |
13145 | bfd_reloc_code_real_type r[3]; | |
13146 | expressionS ep; | |
13147 | int imm; | |
13148 | ||
13149 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13150 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13151 | break; | |
13152 | ||
13153 | imm = ep.X_add_number & 127; | |
13154 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13155 | } | |
13156 | s = expr_end; | |
13157 | continue; | |
13158 | ||
13159 | case 'J': | |
13160 | { | |
13161 | bfd_reloc_code_real_type r[3]; | |
13162 | expressionS ep; | |
13163 | int imm; | |
13164 | ||
13165 | /* Check whether there is only a single bracketed | |
13166 | expression left. If so, it must be the base register | |
13167 | and the constant must be zero. */ | |
13168 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13169 | { | |
13170 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13171 | continue; | |
13172 | } | |
13173 | ||
13174 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13175 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13176 | break; | |
13177 | ||
13178 | imm = ep.X_add_number >> 2; | |
13179 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13180 | } | |
13181 | s = expr_end; | |
13182 | continue; | |
13183 | ||
13184 | case 'L': | |
13185 | { | |
13186 | bfd_reloc_code_real_type r[3]; | |
13187 | expressionS ep; | |
13188 | int imm; | |
13189 | ||
13190 | /* Check whether there is only a single bracketed | |
13191 | expression left. If so, it must be the base register | |
13192 | and the constant must be zero. */ | |
13193 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13194 | { | |
13195 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13196 | continue; | |
13197 | } | |
13198 | ||
13199 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13200 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13201 | break; | |
13202 | ||
13203 | imm = ep.X_add_number; | |
13204 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13205 | } | |
13206 | s = expr_end; | |
13207 | continue; | |
13208 | ||
13209 | case 'M': | |
13210 | { | |
13211 | bfd_reloc_code_real_type r[3]; | |
13212 | expressionS ep; | |
13213 | int imm; | |
13214 | ||
13215 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13216 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13217 | break; | |
13218 | ||
13219 | imm = ep.X_add_number & 7; | |
13220 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13221 | } | |
13222 | s = expr_end; | |
13223 | continue; | |
13224 | ||
13225 | case 'N': /* Register list for lwm and swm. */ | |
13226 | { | |
13227 | /* A comma-separated list of registers and/or | |
13228 | dash-separated contiguous ranges including | |
13229 | both ra and a set of one or more registers | |
13230 | starting at s0 up to s3 which have to be | |
13231 | consecutive, e.g.: | |
13232 | ||
13233 | s0, ra | |
13234 | s0, s1, ra, s2, s3 | |
13235 | s0-s2, ra | |
13236 | ||
13237 | and any permutations of these. */ | |
13238 | unsigned int reglist; | |
13239 | int imm; | |
13240 | ||
13241 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13242 | break; | |
13243 | ||
13244 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13245 | break; | |
13246 | ||
13247 | reglist = (reglist >> 17) & 7; | |
13248 | reglist += 1; | |
13249 | if ((reglist & -reglist) != reglist) | |
13250 | break; | |
252b5132 | 13251 | |
df58fc94 RS |
13252 | imm = ffs (reglist) - 1; |
13253 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13254 | } | |
13255 | continue; | |
252b5132 | 13256 | |
df58fc94 RS |
13257 | case 'O': /* sdbbp 4-bit code. */ |
13258 | { | |
13259 | bfd_reloc_code_real_type r[3]; | |
13260 | expressionS ep; | |
13261 | int imm; | |
13262 | ||
13263 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13264 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13265 | break; | |
13266 | ||
13267 | imm = ep.X_add_number; | |
13268 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13269 | } |
df58fc94 RS |
13270 | s = expr_end; |
13271 | continue; | |
252b5132 | 13272 | |
df58fc94 RS |
13273 | case 'P': |
13274 | { | |
13275 | bfd_reloc_code_real_type r[3]; | |
13276 | expressionS ep; | |
13277 | int imm; | |
5e0116d5 | 13278 | |
df58fc94 RS |
13279 | if (my_getSmallExpression (&ep, r, s) > 0 |
13280 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13281 | break; | |
5e0116d5 | 13282 | |
df58fc94 RS |
13283 | imm = ep.X_add_number >> 2; |
13284 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13285 | } | |
13286 | s = expr_end; | |
13287 | continue; | |
5e0116d5 | 13288 | |
df58fc94 RS |
13289 | case 'Q': |
13290 | { | |
13291 | bfd_reloc_code_real_type r[3]; | |
13292 | expressionS ep; | |
13293 | int imm; | |
5e0116d5 | 13294 | |
df58fc94 RS |
13295 | if (my_getSmallExpression (&ep, r, s) > 0 |
13296 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13297 | break; | |
252b5132 | 13298 | |
df58fc94 RS |
13299 | imm = ep.X_add_number >> 2; |
13300 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13301 | } | |
13302 | s = expr_end; | |
13303 | continue; | |
4614d845 | 13304 | |
df58fc94 RS |
13305 | case 'U': |
13306 | { | |
13307 | bfd_reloc_code_real_type r[3]; | |
13308 | expressionS ep; | |
13309 | int imm; | |
13310 | ||
13311 | /* Check whether there is only a single bracketed | |
13312 | expression left. If so, it must be the base register | |
13313 | and the constant must be zero. */ | |
13314 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13315 | { | |
13316 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13317 | continue; | |
13318 | } | |
13319 | ||
13320 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13321 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13322 | break; | |
13323 | ||
13324 | imm = ep.X_add_number >> 2; | |
13325 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13326 | } | |
13327 | s = expr_end; | |
5e0116d5 | 13328 | continue; |
252b5132 | 13329 | |
df58fc94 RS |
13330 | case 'W': |
13331 | { | |
13332 | bfd_reloc_code_real_type r[3]; | |
13333 | expressionS ep; | |
13334 | int imm; | |
252b5132 | 13335 | |
df58fc94 RS |
13336 | if (my_getSmallExpression (&ep, r, s) > 0 |
13337 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13338 | break; | |
252b5132 | 13339 | |
df58fc94 RS |
13340 | imm = ep.X_add_number >> 2; |
13341 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13342 | } | |
13343 | s = expr_end; | |
13344 | continue; | |
252b5132 | 13345 | |
df58fc94 RS |
13346 | case 'X': |
13347 | { | |
13348 | bfd_reloc_code_real_type r[3]; | |
13349 | expressionS ep; | |
13350 | int imm; | |
252b5132 | 13351 | |
df58fc94 RS |
13352 | if (my_getSmallExpression (&ep, r, s) > 0 |
13353 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13354 | break; | |
252b5132 | 13355 | |
df58fc94 RS |
13356 | imm = ep.X_add_number; |
13357 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13358 | } | |
13359 | s = expr_end; | |
13360 | continue; | |
252b5132 | 13361 | |
df58fc94 RS |
13362 | case 'Y': |
13363 | { | |
13364 | bfd_reloc_code_real_type r[3]; | |
13365 | expressionS ep; | |
13366 | int imm; | |
156c2f8b | 13367 | |
df58fc94 RS |
13368 | if (my_getSmallExpression (&ep, r, s) > 0 |
13369 | || expr_const_in_range (&ep, -2, 2, 2) | |
13370 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13371 | break; | |
156c2f8b | 13372 | |
df58fc94 RS |
13373 | imm = ep.X_add_number >> 2; |
13374 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13375 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13376 | } | |
13377 | s = expr_end; | |
13378 | continue; | |
60b63b72 | 13379 | |
df58fc94 RS |
13380 | case 'Z': |
13381 | { | |
13382 | bfd_reloc_code_real_type r[3]; | |
13383 | expressionS ep; | |
13384 | ||
13385 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13386 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13387 | break; | |
13388 | } | |
13389 | s = expr_end; | |
13390 | continue; | |
13391 | ||
13392 | default: | |
13393 | as_bad (_("Internal error: bad microMIPS opcode " | |
13394 | "(unknown extension operand type `m%c'): %s %s"), | |
13395 | *args, insn->name, insn->args); | |
13396 | /* Further processing is fruitless. */ | |
13397 | return; | |
60b63b72 | 13398 | } |
df58fc94 | 13399 | break; |
60b63b72 | 13400 | |
df58fc94 RS |
13401 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13402 | gas_assert (mips_opts.micromips); | |
13403 | { | |
13404 | /* A comma-separated list of registers and/or | |
13405 | dash-separated contiguous ranges including | |
13406 | at least one of ra and a set of one or more | |
13407 | registers starting at s0 up to s7 and then | |
13408 | s8 which have to be consecutive, e.g.: | |
13409 | ||
13410 | ra | |
13411 | s0 | |
13412 | ra, s0, s1, s2 | |
13413 | s0-s8 | |
13414 | s0-s5, ra | |
13415 | ||
13416 | and any permutations of these. */ | |
13417 | unsigned int reglist; | |
13418 | int imm; | |
13419 | int ra; | |
13420 | ||
13421 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13422 | break; | |
13423 | ||
13424 | if ((reglist & 0x3f00ffff) != 0) | |
13425 | break; | |
13426 | ||
13427 | ra = (reglist >> 27) & 0x10; | |
13428 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13429 | reglist += 1; | |
13430 | if ((reglist & -reglist) != reglist) | |
13431 | break; | |
13432 | ||
13433 | imm = (ffs (reglist) - 1) | ra; | |
13434 | INSERT_OPERAND (1, RT, *ip, imm); | |
13435 | imm_expr.X_op = O_absent; | |
13436 | } | |
60b63b72 RS |
13437 | continue; |
13438 | ||
df58fc94 RS |
13439 | case '|': /* 4-bit trap code. */ |
13440 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13441 | my_getExpression (&imm_expr, s); |
13442 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13443 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13444 | > MICROMIPSOP_MASK_TRAP) |
13445 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13446 | (unsigned long) imm_expr.X_add_number, | |
13447 | ip->insn_mo->name); | |
13448 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13449 | imm_expr.X_op = O_absent; |
13450 | s = expr_end; | |
13451 | continue; | |
13452 | ||
252b5132 | 13453 | default: |
f71d0d44 | 13454 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13455 | abort (); |
252b5132 RH |
13456 | } |
13457 | break; | |
13458 | } | |
13459 | /* Args don't match. */ | |
df58fc94 RS |
13460 | s = argsStart; |
13461 | insn_error = _("Illegal operands"); | |
13462 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13463 | { |
13464 | ++insn; | |
252b5132 RH |
13465 | continue; |
13466 | } | |
df58fc94 RS |
13467 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13468 | { | |
13469 | gas_assert (firstinsn); | |
13470 | need_delay_slot_ok = FALSE; | |
13471 | past = insn + 1; | |
13472 | insn = firstinsn; | |
13473 | continue; | |
13474 | } | |
252b5132 RH |
13475 | return; |
13476 | } | |
13477 | } | |
13478 | ||
0499d65b TS |
13479 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13480 | ||
252b5132 RH |
13481 | /* This routine assembles an instruction into its binary format when |
13482 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13483 | global variables imm_reloc or offset_reloc to the type of relocation |
13484 | to do if one of the operands is an address expression. It also sets | |
13485 | forced_insn_length to the resulting instruction size in bytes if the | |
13486 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13487 | |
13488 | static void | |
17a2f251 | 13489 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13490 | { |
13491 | char *s; | |
13492 | const char *args; | |
13493 | struct mips_opcode *insn; | |
13494 | char *argsstart; | |
13495 | unsigned int regno; | |
13496 | unsigned int lastregno = 0; | |
13497 | char *s_reset; | |
d6f16593 | 13498 | size_t i; |
252b5132 RH |
13499 | |
13500 | insn_error = NULL; | |
13501 | ||
df58fc94 | 13502 | forced_insn_length = 0; |
252b5132 | 13503 | |
3882b010 | 13504 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13505 | ; |
13506 | switch (*s) | |
13507 | { | |
13508 | case '\0': | |
13509 | break; | |
13510 | ||
13511 | case ' ': | |
13512 | *s++ = '\0'; | |
13513 | break; | |
13514 | ||
13515 | case '.': | |
13516 | if (s[1] == 't' && s[2] == ' ') | |
13517 | { | |
13518 | *s = '\0'; | |
df58fc94 | 13519 | forced_insn_length = 2; |
252b5132 RH |
13520 | s += 3; |
13521 | break; | |
13522 | } | |
13523 | else if (s[1] == 'e' && s[2] == ' ') | |
13524 | { | |
13525 | *s = '\0'; | |
df58fc94 | 13526 | forced_insn_length = 4; |
252b5132 RH |
13527 | s += 3; |
13528 | break; | |
13529 | } | |
13530 | /* Fall through. */ | |
13531 | default: | |
13532 | insn_error = _("unknown opcode"); | |
13533 | return; | |
13534 | } | |
13535 | ||
df58fc94 RS |
13536 | if (mips_opts.noautoextend && !forced_insn_length) |
13537 | forced_insn_length = 2; | |
252b5132 RH |
13538 | |
13539 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13540 | { | |
13541 | insn_error = _("unrecognized opcode"); | |
13542 | return; | |
13543 | } | |
13544 | ||
13545 | argsstart = s; | |
13546 | for (;;) | |
13547 | { | |
9b3f89ee TS |
13548 | bfd_boolean ok; |
13549 | ||
9c2799c2 | 13550 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13551 | |
037b32b9 | 13552 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13553 | if (! ok) |
13554 | { | |
13555 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13556 | && strcmp (insn->name, insn[1].name) == 0) | |
13557 | { | |
13558 | ++insn; | |
13559 | continue; | |
13560 | } | |
13561 | else | |
13562 | { | |
13563 | if (!insn_error) | |
13564 | { | |
13565 | static char buf[100]; | |
13566 | sprintf (buf, | |
7bd942df | 13567 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13568 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13569 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13570 | insn_error = buf; | |
13571 | } | |
13572 | return; | |
13573 | } | |
13574 | } | |
13575 | ||
1e915849 | 13576 | create_insn (ip, insn); |
252b5132 | 13577 | imm_expr.X_op = O_absent; |
f6688943 TS |
13578 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13579 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13580 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13581 | imm2_expr.X_op = O_absent; |
252b5132 | 13582 | offset_expr.X_op = O_absent; |
f6688943 TS |
13583 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13584 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13585 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13586 | for (args = insn->args; 1; ++args) |
13587 | { | |
13588 | int c; | |
13589 | ||
13590 | if (*s == ' ') | |
13591 | ++s; | |
13592 | ||
13593 | /* In this switch statement we call break if we did not find | |
13594 | a match, continue if we did find a match, or return if we | |
13595 | are done. */ | |
13596 | ||
13597 | c = *args; | |
13598 | switch (c) | |
13599 | { | |
13600 | case '\0': | |
13601 | if (*s == '\0') | |
13602 | { | |
b886a2ab RS |
13603 | offsetT value; |
13604 | ||
252b5132 RH |
13605 | /* Stuff the immediate value in now, if we can. */ |
13606 | if (imm_expr.X_op == O_constant | |
f6688943 | 13607 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13608 | && insn->pinfo != INSN_MACRO |
13609 | && calculate_reloc (*offset_reloc, | |
13610 | imm_expr.X_add_number, &value)) | |
252b5132 | 13611 | { |
c4e7957c | 13612 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13613 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13614 | &ip->insn_opcode); |
252b5132 | 13615 | imm_expr.X_op = O_absent; |
f6688943 | 13616 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13617 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13618 | } |
13619 | ||
13620 | return; | |
13621 | } | |
13622 | break; | |
13623 | ||
13624 | case ',': | |
13625 | if (*s++ == c) | |
13626 | continue; | |
13627 | s--; | |
13628 | switch (*++args) | |
13629 | { | |
13630 | case 'v': | |
bf12938e | 13631 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13632 | continue; |
13633 | case 'w': | |
bf12938e | 13634 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13635 | continue; |
13636 | } | |
13637 | break; | |
13638 | ||
13639 | case '(': | |
13640 | case ')': | |
13641 | if (*s++ == c) | |
13642 | continue; | |
13643 | break; | |
13644 | ||
13645 | case 'v': | |
13646 | case 'w': | |
13647 | if (s[0] != '$') | |
13648 | { | |
13649 | if (c == 'v') | |
bf12938e | 13650 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13651 | else |
bf12938e | 13652 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13653 | ++args; |
13654 | continue; | |
13655 | } | |
13656 | /* Fall through. */ | |
13657 | case 'x': | |
13658 | case 'y': | |
13659 | case 'z': | |
13660 | case 'Z': | |
13661 | case '0': | |
13662 | case 'S': | |
13663 | case 'R': | |
13664 | case 'X': | |
13665 | case 'Y': | |
707bfff6 TS |
13666 | s_reset = s; |
13667 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13668 | { |
707bfff6 | 13669 | if (c == 'v' || c == 'w') |
85b51719 | 13670 | { |
707bfff6 | 13671 | if (c == 'v') |
a9e24354 | 13672 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13673 | else |
a9e24354 | 13674 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13675 | ++args; |
13676 | continue; | |
85b51719 | 13677 | } |
707bfff6 | 13678 | break; |
252b5132 RH |
13679 | } |
13680 | ||
13681 | if (*s == ' ') | |
13682 | ++s; | |
13683 | if (args[1] != *s) | |
13684 | { | |
13685 | if (c == 'v' || c == 'w') | |
13686 | { | |
13687 | regno = mips16_to_32_reg_map[lastregno]; | |
13688 | s = s_reset; | |
f9419b05 | 13689 | ++args; |
252b5132 RH |
13690 | } |
13691 | } | |
13692 | ||
13693 | switch (c) | |
13694 | { | |
13695 | case 'x': | |
13696 | case 'y': | |
13697 | case 'z': | |
13698 | case 'v': | |
13699 | case 'w': | |
13700 | case 'Z': | |
13701 | regno = mips32_to_16_reg_map[regno]; | |
13702 | break; | |
13703 | ||
13704 | case '0': | |
13705 | if (regno != 0) | |
13706 | regno = ILLEGAL_REG; | |
13707 | break; | |
13708 | ||
13709 | case 'S': | |
13710 | if (regno != SP) | |
13711 | regno = ILLEGAL_REG; | |
13712 | break; | |
13713 | ||
13714 | case 'R': | |
13715 | if (regno != RA) | |
13716 | regno = ILLEGAL_REG; | |
13717 | break; | |
13718 | ||
13719 | case 'X': | |
13720 | case 'Y': | |
741fe287 MR |
13721 | if (regno == AT && mips_opts.at) |
13722 | { | |
13723 | if (mips_opts.at == ATREG) | |
13724 | as_warn (_("used $at without \".set noat\"")); | |
13725 | else | |
13726 | as_warn (_("used $%u with \".set at=$%u\""), | |
13727 | regno, mips_opts.at); | |
13728 | } | |
252b5132 RH |
13729 | break; |
13730 | ||
13731 | default: | |
b37df7c4 | 13732 | abort (); |
252b5132 RH |
13733 | } |
13734 | ||
13735 | if (regno == ILLEGAL_REG) | |
13736 | break; | |
13737 | ||
13738 | switch (c) | |
13739 | { | |
13740 | case 'x': | |
13741 | case 'v': | |
bf12938e | 13742 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13743 | break; |
13744 | case 'y': | |
13745 | case 'w': | |
bf12938e | 13746 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13747 | break; |
13748 | case 'z': | |
bf12938e | 13749 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13750 | break; |
13751 | case 'Z': | |
bf12938e | 13752 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13753 | case '0': |
13754 | case 'S': | |
13755 | case 'R': | |
13756 | break; | |
13757 | case 'X': | |
bf12938e | 13758 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13759 | break; |
13760 | case 'Y': | |
13761 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13762 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13763 | break; |
13764 | default: | |
b37df7c4 | 13765 | abort (); |
252b5132 RH |
13766 | } |
13767 | ||
13768 | lastregno = regno; | |
13769 | continue; | |
13770 | ||
13771 | case 'P': | |
13772 | if (strncmp (s, "$pc", 3) == 0) | |
13773 | { | |
13774 | s += 3; | |
13775 | continue; | |
13776 | } | |
13777 | break; | |
13778 | ||
252b5132 RH |
13779 | case '5': |
13780 | case 'H': | |
13781 | case 'W': | |
13782 | case 'D': | |
13783 | case 'j': | |
252b5132 RH |
13784 | case 'V': |
13785 | case 'C': | |
13786 | case 'U': | |
13787 | case 'k': | |
13788 | case 'K': | |
d6f16593 MR |
13789 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13790 | if (i > 0) | |
252b5132 | 13791 | { |
d6f16593 | 13792 | if (imm_expr.X_op != O_constant) |
252b5132 | 13793 | { |
df58fc94 | 13794 | forced_insn_length = 4; |
5c04167a | 13795 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13796 | } |
d6f16593 MR |
13797 | else |
13798 | { | |
13799 | /* We need to relax this instruction. */ | |
13800 | *offset_reloc = *imm_reloc; | |
13801 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13802 | } | |
13803 | s = expr_end; | |
13804 | continue; | |
252b5132 | 13805 | } |
d6f16593 MR |
13806 | *imm_reloc = BFD_RELOC_UNUSED; |
13807 | /* Fall through. */ | |
13808 | case '<': | |
13809 | case '>': | |
13810 | case '[': | |
13811 | case ']': | |
13812 | case '4': | |
13813 | case '8': | |
13814 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13815 | if (imm_expr.X_op == O_register) |
13816 | { | |
13817 | /* What we thought was an expression turned out to | |
13818 | be a register. */ | |
13819 | ||
13820 | if (s[0] == '(' && args[1] == '(') | |
13821 | { | |
13822 | /* It looks like the expression was omitted | |
13823 | before a register indirection, which means | |
13824 | that the expression is implicitly zero. We | |
13825 | still set up imm_expr, so that we handle | |
13826 | explicit extensions correctly. */ | |
13827 | imm_expr.X_op = O_constant; | |
13828 | imm_expr.X_add_number = 0; | |
f6688943 | 13829 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13830 | continue; |
13831 | } | |
13832 | ||
13833 | break; | |
13834 | } | |
13835 | ||
13836 | /* We need to relax this instruction. */ | |
f6688943 | 13837 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13838 | s = expr_end; |
13839 | continue; | |
13840 | ||
13841 | case 'p': | |
13842 | case 'q': | |
13843 | case 'A': | |
13844 | case 'B': | |
13845 | case 'E': | |
13846 | /* We use offset_reloc rather than imm_reloc for the PC | |
13847 | relative operands. This lets macros with both | |
13848 | immediate and address operands work correctly. */ | |
13849 | my_getExpression (&offset_expr, s); | |
13850 | ||
13851 | if (offset_expr.X_op == O_register) | |
13852 | break; | |
13853 | ||
13854 | /* We need to relax this instruction. */ | |
f6688943 | 13855 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13856 | s = expr_end; |
13857 | continue; | |
13858 | ||
13859 | case '6': /* break code */ | |
13860 | my_getExpression (&imm_expr, s); | |
13861 | check_absolute_expr (ip, &imm_expr); | |
13862 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13863 | as_warn (_("Invalid value for `%s' (%lu)"), |
13864 | ip->insn_mo->name, | |
13865 | (unsigned long) imm_expr.X_add_number); | |
13866 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13867 | imm_expr.X_op = O_absent; |
13868 | s = expr_end; | |
13869 | continue; | |
13870 | ||
13871 | case 'a': /* 26 bit address */ | |
13872 | my_getExpression (&offset_expr, s); | |
13873 | s = expr_end; | |
f6688943 | 13874 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13875 | ip->insn_opcode <<= 16; |
13876 | continue; | |
13877 | ||
13878 | case 'l': /* register list for entry macro */ | |
13879 | case 'L': /* register list for exit macro */ | |
13880 | { | |
13881 | int mask; | |
13882 | ||
13883 | if (c == 'l') | |
13884 | mask = 0; | |
13885 | else | |
13886 | mask = 7 << 3; | |
13887 | while (*s != '\0') | |
13888 | { | |
707bfff6 | 13889 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13890 | |
13891 | while (*s == ' ' || *s == ',') | |
13892 | ++s; | |
707bfff6 | 13893 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13894 | freg = 0; |
707bfff6 TS |
13895 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13896 | freg = 1; | |
252b5132 RH |
13897 | else |
13898 | { | |
707bfff6 TS |
13899 | as_bad (_("can't parse register list")); |
13900 | break; | |
252b5132 RH |
13901 | } |
13902 | if (*s == ' ') | |
13903 | ++s; | |
13904 | if (*s != '-') | |
13905 | reg2 = reg1; | |
13906 | else | |
13907 | { | |
13908 | ++s; | |
707bfff6 TS |
13909 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13910 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13911 | { |
707bfff6 TS |
13912 | as_bad (_("invalid register list")); |
13913 | break; | |
252b5132 RH |
13914 | } |
13915 | } | |
13916 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13917 | { | |
13918 | mask &= ~ (7 << 3); | |
13919 | mask |= 5 << 3; | |
13920 | } | |
13921 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13922 | { | |
13923 | mask &= ~ (7 << 3); | |
13924 | mask |= 6 << 3; | |
13925 | } | |
13926 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13927 | mask |= (reg2 - 3) << 3; | |
13928 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13929 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13930 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13931 | mask |= 1; |
13932 | else | |
13933 | { | |
13934 | as_bad (_("invalid register list")); | |
13935 | break; | |
13936 | } | |
13937 | } | |
13938 | /* The mask is filled in in the opcode table for the | |
13939 | benefit of the disassembler. We remove it before | |
13940 | applying the actual mask. */ | |
13941 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13942 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13943 | } | |
13944 | continue; | |
13945 | ||
0499d65b TS |
13946 | case 'm': /* Register list for save insn. */ |
13947 | case 'M': /* Register list for restore insn. */ | |
13948 | { | |
5c04167a | 13949 | int opcode = ip->insn_opcode; |
0499d65b | 13950 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13951 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13952 | |
13953 | while (*s != '\0') | |
13954 | { | |
13955 | unsigned int reg1, reg2; | |
13956 | ||
13957 | SKIP_SPACE_TABS (s); | |
13958 | while (*s == ',') | |
13959 | ++s; | |
13960 | SKIP_SPACE_TABS (s); | |
13961 | ||
13962 | my_getExpression (&imm_expr, s); | |
13963 | if (imm_expr.X_op == O_constant) | |
13964 | { | |
13965 | /* Handle the frame size. */ | |
13966 | if (seen_framesz) | |
13967 | { | |
13968 | as_bad (_("more than one frame size in list")); | |
13969 | break; | |
13970 | } | |
13971 | seen_framesz = 1; | |
13972 | framesz = imm_expr.X_add_number; | |
13973 | imm_expr.X_op = O_absent; | |
13974 | s = expr_end; | |
13975 | continue; | |
13976 | } | |
13977 | ||
707bfff6 | 13978 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13979 | { |
13980 | as_bad (_("can't parse register list")); | |
13981 | break; | |
13982 | } | |
0499d65b | 13983 | |
707bfff6 TS |
13984 | while (*s == ' ') |
13985 | ++s; | |
13986 | ||
0499d65b TS |
13987 | if (*s != '-') |
13988 | reg2 = reg1; | |
13989 | else | |
13990 | { | |
13991 | ++s; | |
707bfff6 TS |
13992 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13993 | || reg2 < reg1) | |
0499d65b TS |
13994 | { |
13995 | as_bad (_("can't parse register list")); | |
13996 | break; | |
13997 | } | |
0499d65b TS |
13998 | } |
13999 | ||
14000 | while (reg1 <= reg2) | |
14001 | { | |
14002 | if (reg1 >= 4 && reg1 <= 7) | |
14003 | { | |
3a93f742 | 14004 | if (!seen_framesz) |
0499d65b | 14005 | /* args $a0-$a3 */ |
91d6fa6a | 14006 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14007 | else |
14008 | /* statics $a0-$a3 */ | |
14009 | statics |= 1 << (reg1 - 4); | |
14010 | } | |
14011 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14012 | { | |
14013 | /* $s0-$s8 */ | |
14014 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14015 | } | |
14016 | else if (reg1 == 31) | |
14017 | { | |
14018 | /* Add $ra to insn. */ | |
14019 | opcode |= 0x40; | |
14020 | } | |
14021 | else | |
14022 | { | |
14023 | as_bad (_("unexpected register in list")); | |
14024 | break; | |
14025 | } | |
14026 | if (++reg1 == 24) | |
14027 | reg1 = 30; | |
14028 | } | |
14029 | } | |
14030 | ||
14031 | /* Encode args/statics combination. */ | |
91d6fa6a | 14032 | if (nargs & statics) |
0499d65b | 14033 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14034 | else if (nargs == 0xf) |
0499d65b TS |
14035 | /* All $a0-$a3 are args. */ |
14036 | opcode |= MIPS16_ALL_ARGS << 16; | |
14037 | else if (statics == 0xf) | |
14038 | /* All $a0-$a3 are statics. */ | |
14039 | opcode |= MIPS16_ALL_STATICS << 16; | |
14040 | else | |
14041 | { | |
14042 | int narg = 0, nstat = 0; | |
14043 | ||
14044 | /* Count arg registers. */ | |
91d6fa6a | 14045 | while (nargs & 0x1) |
0499d65b | 14046 | { |
91d6fa6a | 14047 | nargs >>= 1; |
0499d65b TS |
14048 | narg++; |
14049 | } | |
91d6fa6a | 14050 | if (nargs != 0) |
0499d65b TS |
14051 | as_bad (_("invalid arg register list")); |
14052 | ||
14053 | /* Count static registers. */ | |
14054 | while (statics & 0x8) | |
14055 | { | |
14056 | statics = (statics << 1) & 0xf; | |
14057 | nstat++; | |
14058 | } | |
14059 | if (statics != 0) | |
14060 | as_bad (_("invalid static register list")); | |
14061 | ||
14062 | /* Encode args/statics. */ | |
14063 | opcode |= ((narg << 2) | nstat) << 16; | |
14064 | } | |
14065 | ||
14066 | /* Encode $s0/$s1. */ | |
14067 | if (sregs & (1 << 0)) /* $s0 */ | |
14068 | opcode |= 0x20; | |
14069 | if (sregs & (1 << 1)) /* $s1 */ | |
14070 | opcode |= 0x10; | |
14071 | sregs >>= 2; | |
14072 | ||
14073 | if (sregs != 0) | |
14074 | { | |
14075 | /* Count regs $s2-$s8. */ | |
14076 | int nsreg = 0; | |
14077 | while (sregs & 1) | |
14078 | { | |
14079 | sregs >>= 1; | |
14080 | nsreg++; | |
14081 | } | |
14082 | if (sregs != 0) | |
14083 | as_bad (_("invalid static register list")); | |
14084 | /* Encode $s2-$s8. */ | |
14085 | opcode |= nsreg << 24; | |
14086 | } | |
14087 | ||
14088 | /* Encode frame size. */ | |
14089 | if (!seen_framesz) | |
14090 | as_bad (_("missing frame size")); | |
14091 | else if ((framesz & 7) != 0 || framesz < 0 | |
14092 | || framesz > 0xff * 8) | |
14093 | as_bad (_("invalid frame size")); | |
14094 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14095 | { | |
14096 | framesz /= 8; | |
14097 | opcode |= (((framesz & 0xf0) << 16) | |
14098 | | (framesz & 0x0f)); | |
14099 | } | |
14100 | ||
14101 | /* Finally build the instruction. */ | |
14102 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14103 | opcode |= MIPS16_EXTEND; |
14104 | ip->insn_opcode = opcode; | |
0499d65b TS |
14105 | } |
14106 | continue; | |
14107 | ||
252b5132 RH |
14108 | case 'e': /* extend code */ |
14109 | my_getExpression (&imm_expr, s); | |
14110 | check_absolute_expr (ip, &imm_expr); | |
14111 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14112 | { | |
14113 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14114 | ip->insn_mo->name, | |
14115 | (unsigned long) imm_expr.X_add_number); | |
14116 | imm_expr.X_add_number &= 0x7ff; | |
14117 | } | |
14118 | ip->insn_opcode |= imm_expr.X_add_number; | |
14119 | imm_expr.X_op = O_absent; | |
14120 | s = expr_end; | |
14121 | continue; | |
14122 | ||
14123 | default: | |
b37df7c4 | 14124 | abort (); |
252b5132 RH |
14125 | } |
14126 | break; | |
14127 | } | |
14128 | ||
14129 | /* Args don't match. */ | |
14130 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14131 | strcmp (insn->name, insn[1].name) == 0) | |
14132 | { | |
14133 | ++insn; | |
14134 | s = argsstart; | |
14135 | continue; | |
14136 | } | |
14137 | ||
14138 | insn_error = _("illegal operands"); | |
14139 | ||
14140 | return; | |
14141 | } | |
14142 | } | |
14143 | ||
14144 | /* This structure holds information we know about a mips16 immediate | |
14145 | argument type. */ | |
14146 | ||
e972090a NC |
14147 | struct mips16_immed_operand |
14148 | { | |
252b5132 RH |
14149 | /* The type code used in the argument string in the opcode table. */ |
14150 | int type; | |
14151 | /* The number of bits in the short form of the opcode. */ | |
14152 | int nbits; | |
14153 | /* The number of bits in the extended form of the opcode. */ | |
14154 | int extbits; | |
14155 | /* The amount by which the short form is shifted when it is used; | |
14156 | for example, the sw instruction has a shift count of 2. */ | |
14157 | int shift; | |
14158 | /* The amount by which the short form is shifted when it is stored | |
14159 | into the instruction code. */ | |
14160 | int op_shift; | |
14161 | /* Non-zero if the short form is unsigned. */ | |
14162 | int unsp; | |
14163 | /* Non-zero if the extended form is unsigned. */ | |
14164 | int extu; | |
14165 | /* Non-zero if the value is PC relative. */ | |
14166 | int pcrel; | |
14167 | }; | |
14168 | ||
14169 | /* The mips16 immediate operand types. */ | |
14170 | ||
14171 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14172 | { | |
14173 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14174 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14175 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14176 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14177 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14178 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14179 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14180 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14181 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14182 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14183 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14184 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14185 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14186 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14187 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14188 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14189 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14190 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14191 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14192 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14193 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14194 | }; | |
14195 | ||
14196 | #define MIPS16_NUM_IMMED \ | |
14197 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14198 | ||
b886a2ab RS |
14199 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14200 | NBITS is the number of significant bits in VAL. */ | |
14201 | ||
14202 | static unsigned long | |
14203 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14204 | { | |
14205 | int extval; | |
14206 | if (nbits == 16) | |
14207 | { | |
14208 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14209 | val &= 0x1f; | |
14210 | } | |
14211 | else if (nbits == 15) | |
14212 | { | |
14213 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14214 | val &= 0xf; | |
14215 | } | |
14216 | else | |
14217 | { | |
14218 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14219 | val = 0; | |
14220 | } | |
14221 | return (extval << 16) | val; | |
14222 | } | |
14223 | ||
5c04167a RS |
14224 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14225 | extending it if necessary. The instruction in *INSN may | |
14226 | already be extended. | |
14227 | ||
43c0598f RS |
14228 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14229 | if none. In the former case, VAL is a 16-bit number with no | |
14230 | defined signedness. | |
14231 | ||
14232 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14233 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14234 | |
14235 | static void | |
43c0598f RS |
14236 | mips16_immed (char *file, unsigned int line, int type, |
14237 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14238 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14239 | { |
3994f87e | 14240 | const struct mips16_immed_operand *op; |
252b5132 | 14241 | int mintiny, maxtiny; |
252b5132 RH |
14242 | |
14243 | op = mips16_immed_operands; | |
14244 | while (op->type != type) | |
14245 | { | |
14246 | ++op; | |
9c2799c2 | 14247 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14248 | } |
14249 | ||
14250 | if (op->unsp) | |
14251 | { | |
14252 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14253 | { | |
14254 | mintiny = 1; | |
14255 | maxtiny = 1 << op->nbits; | |
14256 | } | |
14257 | else | |
14258 | { | |
14259 | mintiny = 0; | |
14260 | maxtiny = (1 << op->nbits) - 1; | |
14261 | } | |
43c0598f RS |
14262 | if (reloc != BFD_RELOC_UNUSED) |
14263 | val &= 0xffff; | |
252b5132 RH |
14264 | } |
14265 | else | |
14266 | { | |
14267 | mintiny = - (1 << (op->nbits - 1)); | |
14268 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14269 | if (reloc != BFD_RELOC_UNUSED) |
14270 | val = SEXT_16BIT (val); | |
252b5132 RH |
14271 | } |
14272 | ||
14273 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14274 | if (type == 'p' || type == 'q') | |
14275 | val /= 2; | |
14276 | ||
14277 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14278 | || val < (mintiny << op->shift) | |
14279 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14280 | { |
14281 | /* We need an extended instruction. */ | |
14282 | if (user_insn_length == 2) | |
14283 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14284 | else | |
14285 | *insn |= MIPS16_EXTEND; | |
14286 | } | |
14287 | else if (user_insn_length == 4) | |
14288 | { | |
14289 | /* The operand doesn't force an unextended instruction to be extended. | |
14290 | Warn if the user wanted an extended instruction anyway. */ | |
14291 | *insn |= MIPS16_EXTEND; | |
14292 | as_warn_where (file, line, | |
14293 | _("extended operand requested but not required")); | |
14294 | } | |
252b5132 | 14295 | |
5c04167a | 14296 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14297 | { |
14298 | int insnval; | |
14299 | ||
252b5132 RH |
14300 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14301 | insnval <<= op->op_shift; | |
14302 | *insn |= insnval; | |
14303 | } | |
14304 | else | |
14305 | { | |
14306 | long minext, maxext; | |
252b5132 | 14307 | |
43c0598f | 14308 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14309 | { |
43c0598f RS |
14310 | if (op->extu) |
14311 | { | |
14312 | minext = 0; | |
14313 | maxext = (1 << op->extbits) - 1; | |
14314 | } | |
14315 | else | |
14316 | { | |
14317 | minext = - (1 << (op->extbits - 1)); | |
14318 | maxext = (1 << (op->extbits - 1)) - 1; | |
14319 | } | |
14320 | if (val < minext || val > maxext) | |
14321 | as_bad_where (file, line, | |
14322 | _("operand value out of range for instruction")); | |
252b5132 | 14323 | } |
252b5132 | 14324 | |
b886a2ab | 14325 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14326 | } |
14327 | } | |
14328 | \f | |
d6f16593 | 14329 | struct percent_op_match |
ad8d3bb3 | 14330 | { |
5e0116d5 RS |
14331 | const char *str; |
14332 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14333 | }; |
14334 | ||
14335 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14336 | { |
5e0116d5 | 14337 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14338 | #ifdef OBJ_ELF |
5e0116d5 RS |
14339 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14340 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14341 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14342 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14343 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14344 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14345 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14346 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14347 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14348 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14349 | {"%half", BFD_RELOC_16}, | |
14350 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14351 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14352 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14353 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14354 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14355 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14356 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14357 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14358 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14359 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14360 | #endif |
5e0116d5 | 14361 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14362 | }; |
14363 | ||
d6f16593 MR |
14364 | static const struct percent_op_match mips16_percent_op[] = |
14365 | { | |
14366 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14367 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14368 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14369 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14370 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14371 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14372 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14373 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14374 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14375 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14376 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14377 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14378 | }; |
14379 | ||
252b5132 | 14380 | |
5e0116d5 RS |
14381 | /* Return true if *STR points to a relocation operator. When returning true, |
14382 | move *STR over the operator and store its relocation code in *RELOC. | |
14383 | Leave both *STR and *RELOC alone when returning false. */ | |
14384 | ||
14385 | static bfd_boolean | |
17a2f251 | 14386 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14387 | { |
d6f16593 MR |
14388 | const struct percent_op_match *percent_op; |
14389 | size_t limit, i; | |
14390 | ||
14391 | if (mips_opts.mips16) | |
14392 | { | |
14393 | percent_op = mips16_percent_op; | |
14394 | limit = ARRAY_SIZE (mips16_percent_op); | |
14395 | } | |
14396 | else | |
14397 | { | |
14398 | percent_op = mips_percent_op; | |
14399 | limit = ARRAY_SIZE (mips_percent_op); | |
14400 | } | |
76b3015f | 14401 | |
d6f16593 | 14402 | for (i = 0; i < limit; i++) |
5e0116d5 | 14403 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14404 | { |
3f98094e DJ |
14405 | int len = strlen (percent_op[i].str); |
14406 | ||
14407 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14408 | continue; | |
14409 | ||
5e0116d5 RS |
14410 | *str += strlen (percent_op[i].str); |
14411 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14412 | |
5e0116d5 RS |
14413 | /* Check whether the output BFD supports this relocation. |
14414 | If not, issue an error and fall back on something safe. */ | |
14415 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14416 | { |
20203fb9 | 14417 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14418 | percent_op[i].str); |
01a3f561 | 14419 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14420 | } |
5e0116d5 | 14421 | return TRUE; |
394f9b3a | 14422 | } |
5e0116d5 | 14423 | return FALSE; |
394f9b3a | 14424 | } |
ad8d3bb3 | 14425 | |
ad8d3bb3 | 14426 | |
5e0116d5 RS |
14427 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14428 | expression in *EP and the relocations in the array starting | |
14429 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14430 | |
01a3f561 | 14431 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14432 | |
5e0116d5 | 14433 | static size_t |
17a2f251 TS |
14434 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14435 | char *str) | |
ad8d3bb3 | 14436 | { |
5e0116d5 RS |
14437 | bfd_reloc_code_real_type reversed_reloc[3]; |
14438 | size_t reloc_index, i; | |
09b8f35a RS |
14439 | int crux_depth, str_depth; |
14440 | char *crux; | |
5e0116d5 RS |
14441 | |
14442 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14443 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14444 | of the main expression and with CRUX_DEPTH containing the number | |
14445 | of open brackets at that point. */ | |
14446 | reloc_index = -1; | |
14447 | str_depth = 0; | |
14448 | do | |
fb1b3232 | 14449 | { |
09b8f35a RS |
14450 | reloc_index++; |
14451 | crux = str; | |
14452 | crux_depth = str_depth; | |
14453 | ||
14454 | /* Skip over whitespace and brackets, keeping count of the number | |
14455 | of brackets. */ | |
14456 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14457 | if (*str++ == '(') | |
14458 | str_depth++; | |
5e0116d5 | 14459 | } |
09b8f35a RS |
14460 | while (*str == '%' |
14461 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14462 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14463 | |
09b8f35a | 14464 | my_getExpression (ep, crux); |
5e0116d5 | 14465 | str = expr_end; |
394f9b3a | 14466 | |
5e0116d5 | 14467 | /* Match every open bracket. */ |
09b8f35a | 14468 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14469 | if (*str++ == ')') |
09b8f35a | 14470 | crux_depth--; |
394f9b3a | 14471 | |
09b8f35a | 14472 | if (crux_depth > 0) |
20203fb9 | 14473 | as_bad (_("unclosed '('")); |
394f9b3a | 14474 | |
5e0116d5 | 14475 | expr_end = str; |
252b5132 | 14476 | |
01a3f561 | 14477 | if (reloc_index != 0) |
64bdfcaf RS |
14478 | { |
14479 | prev_reloc_op_frag = frag_now; | |
14480 | for (i = 0; i < reloc_index; i++) | |
14481 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14482 | } | |
fb1b3232 | 14483 | |
5e0116d5 | 14484 | return reloc_index; |
252b5132 RH |
14485 | } |
14486 | ||
14487 | static void | |
17a2f251 | 14488 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14489 | { |
14490 | char *save_in; | |
14491 | ||
14492 | save_in = input_line_pointer; | |
14493 | input_line_pointer = str; | |
14494 | expression (ep); | |
14495 | expr_end = input_line_pointer; | |
14496 | input_line_pointer = save_in; | |
252b5132 RH |
14497 | } |
14498 | ||
252b5132 | 14499 | char * |
17a2f251 | 14500 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14501 | { |
499ac353 | 14502 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14503 | } |
14504 | ||
14505 | void | |
17a2f251 | 14506 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14507 | { |
14508 | if (target_big_endian) | |
14509 | number_to_chars_bigendian (buf, val, n); | |
14510 | else | |
14511 | number_to_chars_littleendian (buf, val, n); | |
14512 | } | |
14513 | \f | |
ae948b86 | 14514 | #ifdef OBJ_ELF |
e013f690 TS |
14515 | static int support_64bit_objects(void) |
14516 | { | |
14517 | const char **list, **l; | |
aa3d8fdf | 14518 | int yes; |
e013f690 TS |
14519 | |
14520 | list = bfd_target_list (); | |
14521 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14522 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14523 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14524 | break; |
aa3d8fdf | 14525 | yes = (*l != NULL); |
e013f690 | 14526 | free (list); |
aa3d8fdf | 14527 | return yes; |
e013f690 | 14528 | } |
ae948b86 | 14529 | #endif /* OBJ_ELF */ |
e013f690 | 14530 | |
78849248 | 14531 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14532 | |
23fce1e3 NC |
14533 | enum options |
14534 | { | |
14535 | OPTION_MARCH = OPTION_MD_BASE, | |
14536 | OPTION_MTUNE, | |
14537 | OPTION_MIPS1, | |
14538 | OPTION_MIPS2, | |
14539 | OPTION_MIPS3, | |
14540 | OPTION_MIPS4, | |
14541 | OPTION_MIPS5, | |
14542 | OPTION_MIPS32, | |
14543 | OPTION_MIPS64, | |
14544 | OPTION_MIPS32R2, | |
14545 | OPTION_MIPS64R2, | |
14546 | OPTION_MIPS16, | |
14547 | OPTION_NO_MIPS16, | |
14548 | OPTION_MIPS3D, | |
14549 | OPTION_NO_MIPS3D, | |
14550 | OPTION_MDMX, | |
14551 | OPTION_NO_MDMX, | |
14552 | OPTION_DSP, | |
14553 | OPTION_NO_DSP, | |
14554 | OPTION_MT, | |
14555 | OPTION_NO_MT, | |
b015e599 AP |
14556 | OPTION_VIRT, |
14557 | OPTION_NO_VIRT, | |
23fce1e3 NC |
14558 | OPTION_SMARTMIPS, |
14559 | OPTION_NO_SMARTMIPS, | |
14560 | OPTION_DSPR2, | |
14561 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14562 | OPTION_MICROMIPS, |
14563 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14564 | OPTION_MCU, |
14565 | OPTION_NO_MCU, | |
23fce1e3 NC |
14566 | OPTION_COMPAT_ARCH_BASE, |
14567 | OPTION_M4650, | |
14568 | OPTION_NO_M4650, | |
14569 | OPTION_M4010, | |
14570 | OPTION_NO_M4010, | |
14571 | OPTION_M4100, | |
14572 | OPTION_NO_M4100, | |
14573 | OPTION_M3900, | |
14574 | OPTION_NO_M3900, | |
14575 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14576 | OPTION_MNO_7000_HILO_FIX, |
14577 | OPTION_FIX_24K, | |
14578 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14579 | OPTION_FIX_LOONGSON2F_JUMP, |
14580 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14581 | OPTION_FIX_LOONGSON2F_NOP, | |
14582 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14583 | OPTION_FIX_VR4120, |
14584 | OPTION_NO_FIX_VR4120, | |
14585 | OPTION_FIX_VR4130, | |
14586 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14587 | OPTION_FIX_CN63XXP1, |
14588 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14589 | OPTION_TRAP, |
14590 | OPTION_BREAK, | |
14591 | OPTION_EB, | |
14592 | OPTION_EL, | |
14593 | OPTION_FP32, | |
14594 | OPTION_GP32, | |
14595 | OPTION_CONSTRUCT_FLOATS, | |
14596 | OPTION_NO_CONSTRUCT_FLOATS, | |
14597 | OPTION_FP64, | |
14598 | OPTION_GP64, | |
14599 | OPTION_RELAX_BRANCH, | |
14600 | OPTION_NO_RELAX_BRANCH, | |
14601 | OPTION_MSHARED, | |
14602 | OPTION_MNO_SHARED, | |
14603 | OPTION_MSYM32, | |
14604 | OPTION_MNO_SYM32, | |
14605 | OPTION_SOFT_FLOAT, | |
14606 | OPTION_HARD_FLOAT, | |
14607 | OPTION_SINGLE_FLOAT, | |
14608 | OPTION_DOUBLE_FLOAT, | |
14609 | OPTION_32, | |
14610 | #ifdef OBJ_ELF | |
14611 | OPTION_CALL_SHARED, | |
14612 | OPTION_CALL_NONPIC, | |
14613 | OPTION_NON_SHARED, | |
14614 | OPTION_XGOT, | |
14615 | OPTION_MABI, | |
14616 | OPTION_N32, | |
14617 | OPTION_64, | |
14618 | OPTION_MDEBUG, | |
14619 | OPTION_NO_MDEBUG, | |
14620 | OPTION_PDR, | |
14621 | OPTION_NO_PDR, | |
14622 | OPTION_MVXWORKS_PIC, | |
14623 | #endif /* OBJ_ELF */ | |
14624 | OPTION_END_OF_ENUM | |
14625 | }; | |
14626 | ||
e972090a NC |
14627 | struct option md_longopts[] = |
14628 | { | |
f9b4148d | 14629 | /* Options which specify architecture. */ |
f9b4148d | 14630 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14631 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14632 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14633 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14634 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14635 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14636 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14637 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14638 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14639 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14640 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14641 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14642 | |
14643 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14644 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14645 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14646 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14647 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14648 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14649 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14650 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14651 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14652 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14653 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14654 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14655 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14656 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14657 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14658 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14659 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14660 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14661 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
b015e599 AP |
14662 | {"mvirt", no_argument, NULL, OPTION_VIRT}, |
14663 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
f9b4148d CD |
14664 | |
14665 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14666 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14667 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14668 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14669 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14670 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14671 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14672 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14673 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14674 | ||
14675 | /* Options which enable bug fixes. */ | |
f9b4148d | 14676 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14677 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14678 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14679 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14680 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14681 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14682 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14683 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14684 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14685 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14686 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14687 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14688 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14689 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14690 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14691 | |
14692 | /* Miscellaneous options. */ | |
252b5132 RH |
14693 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14694 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14695 | {"break", no_argument, NULL, OPTION_BREAK}, |
14696 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14697 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14698 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14699 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14700 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14701 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14702 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14703 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14704 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14705 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14706 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14707 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14708 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14709 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14710 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14711 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14712 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14713 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14714 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14715 | |
14716 | /* Strictly speaking this next option is ELF specific, | |
14717 | but we allow it for other ports as well in order to | |
14718 | make testing easier. */ | |
14719 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14720 | |
f9b4148d | 14721 | /* ELF-specific options. */ |
156c2f8b | 14722 | #ifdef OBJ_ELF |
156c2f8b NC |
14723 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14724 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14725 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14726 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14727 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14728 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14729 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14730 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14731 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14732 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14733 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14734 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14735 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14736 | #endif /* OBJ_ELF */ |
f9b4148d | 14737 | |
252b5132 RH |
14738 | {NULL, no_argument, NULL, 0} |
14739 | }; | |
156c2f8b | 14740 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14741 | |
316f5878 RS |
14742 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14743 | NEW_VALUE. Warn if another value was already specified. Note: | |
14744 | we have to defer parsing the -march and -mtune arguments in order | |
14745 | to handle 'from-abi' correctly, since the ABI might be specified | |
14746 | in a later argument. */ | |
14747 | ||
14748 | static void | |
17a2f251 | 14749 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14750 | { |
14751 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14752 | as_warn (_("A different %s was already specified, is now %s"), | |
14753 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14754 | new_value); | |
14755 | ||
14756 | *string_ptr = new_value; | |
14757 | } | |
14758 | ||
252b5132 | 14759 | int |
17a2f251 | 14760 | md_parse_option (int c, char *arg) |
252b5132 RH |
14761 | { |
14762 | switch (c) | |
14763 | { | |
119d663a NC |
14764 | case OPTION_CONSTRUCT_FLOATS: |
14765 | mips_disable_float_construction = 0; | |
14766 | break; | |
bdaaa2e1 | 14767 | |
119d663a NC |
14768 | case OPTION_NO_CONSTRUCT_FLOATS: |
14769 | mips_disable_float_construction = 1; | |
14770 | break; | |
bdaaa2e1 | 14771 | |
252b5132 RH |
14772 | case OPTION_TRAP: |
14773 | mips_trap = 1; | |
14774 | break; | |
14775 | ||
14776 | case OPTION_BREAK: | |
14777 | mips_trap = 0; | |
14778 | break; | |
14779 | ||
14780 | case OPTION_EB: | |
14781 | target_big_endian = 1; | |
14782 | break; | |
14783 | ||
14784 | case OPTION_EL: | |
14785 | target_big_endian = 0; | |
14786 | break; | |
14787 | ||
14788 | case 'O': | |
4ffff32f TS |
14789 | if (arg == NULL) |
14790 | mips_optimize = 1; | |
14791 | else if (arg[0] == '0') | |
14792 | mips_optimize = 0; | |
14793 | else if (arg[0] == '1') | |
252b5132 RH |
14794 | mips_optimize = 1; |
14795 | else | |
14796 | mips_optimize = 2; | |
14797 | break; | |
14798 | ||
14799 | case 'g': | |
14800 | if (arg == NULL) | |
14801 | mips_debug = 2; | |
14802 | else | |
14803 | mips_debug = atoi (arg); | |
252b5132 RH |
14804 | break; |
14805 | ||
14806 | case OPTION_MIPS1: | |
316f5878 | 14807 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14808 | break; |
14809 | ||
14810 | case OPTION_MIPS2: | |
316f5878 | 14811 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14812 | break; |
14813 | ||
14814 | case OPTION_MIPS3: | |
316f5878 | 14815 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14816 | break; |
14817 | ||
14818 | case OPTION_MIPS4: | |
316f5878 | 14819 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14820 | break; |
14821 | ||
84ea6cf2 | 14822 | case OPTION_MIPS5: |
316f5878 | 14823 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14824 | break; |
14825 | ||
e7af610e | 14826 | case OPTION_MIPS32: |
316f5878 | 14827 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14828 | break; |
14829 | ||
af7ee8bf CD |
14830 | case OPTION_MIPS32R2: |
14831 | file_mips_isa = ISA_MIPS32R2; | |
14832 | break; | |
14833 | ||
5f74bc13 CD |
14834 | case OPTION_MIPS64R2: |
14835 | file_mips_isa = ISA_MIPS64R2; | |
14836 | break; | |
14837 | ||
84ea6cf2 | 14838 | case OPTION_MIPS64: |
316f5878 | 14839 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14840 | break; |
14841 | ||
ec68c924 | 14842 | case OPTION_MTUNE: |
316f5878 RS |
14843 | mips_set_option_string (&mips_tune_string, arg); |
14844 | break; | |
ec68c924 | 14845 | |
316f5878 RS |
14846 | case OPTION_MARCH: |
14847 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14848 | break; |
14849 | ||
14850 | case OPTION_M4650: | |
316f5878 RS |
14851 | mips_set_option_string (&mips_arch_string, "4650"); |
14852 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14853 | break; |
14854 | ||
14855 | case OPTION_NO_M4650: | |
14856 | break; | |
14857 | ||
14858 | case OPTION_M4010: | |
316f5878 RS |
14859 | mips_set_option_string (&mips_arch_string, "4010"); |
14860 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14861 | break; |
14862 | ||
14863 | case OPTION_NO_M4010: | |
14864 | break; | |
14865 | ||
14866 | case OPTION_M4100: | |
316f5878 RS |
14867 | mips_set_option_string (&mips_arch_string, "4100"); |
14868 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14869 | break; |
14870 | ||
14871 | case OPTION_NO_M4100: | |
14872 | break; | |
14873 | ||
252b5132 | 14874 | case OPTION_M3900: |
316f5878 RS |
14875 | mips_set_option_string (&mips_arch_string, "3900"); |
14876 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14877 | break; |
bdaaa2e1 | 14878 | |
252b5132 RH |
14879 | case OPTION_NO_M3900: |
14880 | break; | |
14881 | ||
deec1734 CD |
14882 | case OPTION_MDMX: |
14883 | mips_opts.ase_mdmx = 1; | |
14884 | break; | |
14885 | ||
14886 | case OPTION_NO_MDMX: | |
14887 | mips_opts.ase_mdmx = 0; | |
14888 | break; | |
14889 | ||
74cd071d CF |
14890 | case OPTION_DSP: |
14891 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14892 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14893 | break; |
14894 | ||
14895 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14896 | mips_opts.ase_dsp = 0; |
14897 | mips_opts.ase_dspr2 = 0; | |
14898 | break; | |
14899 | ||
14900 | case OPTION_DSPR2: | |
14901 | mips_opts.ase_dspr2 = 1; | |
14902 | mips_opts.ase_dsp = 1; | |
14903 | break; | |
14904 | ||
14905 | case OPTION_NO_DSPR2: | |
14906 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14907 | mips_opts.ase_dsp = 0; |
14908 | break; | |
14909 | ||
ef2e4d86 CF |
14910 | case OPTION_MT: |
14911 | mips_opts.ase_mt = 1; | |
14912 | break; | |
14913 | ||
14914 | case OPTION_NO_MT: | |
14915 | mips_opts.ase_mt = 0; | |
14916 | break; | |
14917 | ||
dec0624d MR |
14918 | case OPTION_MCU: |
14919 | mips_opts.ase_mcu = 1; | |
14920 | break; | |
14921 | ||
14922 | case OPTION_NO_MCU: | |
14923 | mips_opts.ase_mcu = 0; | |
14924 | break; | |
14925 | ||
df58fc94 RS |
14926 | case OPTION_MICROMIPS: |
14927 | if (mips_opts.mips16 == 1) | |
14928 | { | |
14929 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14930 | return 0; | |
14931 | } | |
14932 | mips_opts.micromips = 1; | |
14933 | mips_no_prev_insn (); | |
14934 | break; | |
14935 | ||
14936 | case OPTION_NO_MICROMIPS: | |
14937 | mips_opts.micromips = 0; | |
14938 | mips_no_prev_insn (); | |
14939 | break; | |
14940 | ||
b015e599 AP |
14941 | case OPTION_VIRT: |
14942 | mips_opts.ase_virt = 1; | |
14943 | break; | |
14944 | ||
14945 | case OPTION_NO_VIRT: | |
14946 | mips_opts.ase_virt = 0; | |
14947 | break; | |
14948 | ||
252b5132 | 14949 | case OPTION_MIPS16: |
df58fc94 RS |
14950 | if (mips_opts.micromips == 1) |
14951 | { | |
14952 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14953 | return 0; | |
14954 | } | |
252b5132 | 14955 | mips_opts.mips16 = 1; |
7d10b47d | 14956 | mips_no_prev_insn (); |
252b5132 RH |
14957 | break; |
14958 | ||
14959 | case OPTION_NO_MIPS16: | |
14960 | mips_opts.mips16 = 0; | |
7d10b47d | 14961 | mips_no_prev_insn (); |
252b5132 RH |
14962 | break; |
14963 | ||
1f25f5d3 CD |
14964 | case OPTION_MIPS3D: |
14965 | mips_opts.ase_mips3d = 1; | |
14966 | break; | |
14967 | ||
14968 | case OPTION_NO_MIPS3D: | |
14969 | mips_opts.ase_mips3d = 0; | |
14970 | break; | |
14971 | ||
e16bfa71 TS |
14972 | case OPTION_SMARTMIPS: |
14973 | mips_opts.ase_smartmips = 1; | |
14974 | break; | |
14975 | ||
14976 | case OPTION_NO_SMARTMIPS: | |
14977 | mips_opts.ase_smartmips = 0; | |
14978 | break; | |
14979 | ||
6a32d874 CM |
14980 | case OPTION_FIX_24K: |
14981 | mips_fix_24k = 1; | |
14982 | break; | |
14983 | ||
14984 | case OPTION_NO_FIX_24K: | |
14985 | mips_fix_24k = 0; | |
14986 | break; | |
14987 | ||
c67a084a NC |
14988 | case OPTION_FIX_LOONGSON2F_JUMP: |
14989 | mips_fix_loongson2f_jump = TRUE; | |
14990 | break; | |
14991 | ||
14992 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14993 | mips_fix_loongson2f_jump = FALSE; | |
14994 | break; | |
14995 | ||
14996 | case OPTION_FIX_LOONGSON2F_NOP: | |
14997 | mips_fix_loongson2f_nop = TRUE; | |
14998 | break; | |
14999 | ||
15000 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15001 | mips_fix_loongson2f_nop = FALSE; | |
15002 | break; | |
15003 | ||
d766e8ec RS |
15004 | case OPTION_FIX_VR4120: |
15005 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15006 | break; |
15007 | ||
d766e8ec RS |
15008 | case OPTION_NO_FIX_VR4120: |
15009 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15010 | break; |
15011 | ||
7d8e00cf RS |
15012 | case OPTION_FIX_VR4130: |
15013 | mips_fix_vr4130 = 1; | |
15014 | break; | |
15015 | ||
15016 | case OPTION_NO_FIX_VR4130: | |
15017 | mips_fix_vr4130 = 0; | |
15018 | break; | |
15019 | ||
d954098f DD |
15020 | case OPTION_FIX_CN63XXP1: |
15021 | mips_fix_cn63xxp1 = TRUE; | |
15022 | break; | |
15023 | ||
15024 | case OPTION_NO_FIX_CN63XXP1: | |
15025 | mips_fix_cn63xxp1 = FALSE; | |
15026 | break; | |
15027 | ||
4a6a3df4 AO |
15028 | case OPTION_RELAX_BRANCH: |
15029 | mips_relax_branch = 1; | |
15030 | break; | |
15031 | ||
15032 | case OPTION_NO_RELAX_BRANCH: | |
15033 | mips_relax_branch = 0; | |
15034 | break; | |
15035 | ||
aa6975fb ILT |
15036 | case OPTION_MSHARED: |
15037 | mips_in_shared = TRUE; | |
15038 | break; | |
15039 | ||
15040 | case OPTION_MNO_SHARED: | |
15041 | mips_in_shared = FALSE; | |
15042 | break; | |
15043 | ||
aed1a261 RS |
15044 | case OPTION_MSYM32: |
15045 | mips_opts.sym32 = TRUE; | |
15046 | break; | |
15047 | ||
15048 | case OPTION_MNO_SYM32: | |
15049 | mips_opts.sym32 = FALSE; | |
15050 | break; | |
15051 | ||
0f074f60 | 15052 | #ifdef OBJ_ELF |
252b5132 RH |
15053 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15054 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15055 | intended to be compatible with Irix 5. */ | |
15056 | case OPTION_CALL_SHARED: | |
f43abd2b | 15057 | if (!IS_ELF) |
252b5132 RH |
15058 | { |
15059 | as_bad (_("-call_shared is supported only for ELF format")); | |
15060 | return 0; | |
15061 | } | |
15062 | mips_pic = SVR4_PIC; | |
143d77c5 | 15063 | mips_abicalls = TRUE; |
252b5132 RH |
15064 | break; |
15065 | ||
861fb55a DJ |
15066 | case OPTION_CALL_NONPIC: |
15067 | if (!IS_ELF) | |
15068 | { | |
15069 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
15070 | return 0; | |
15071 | } | |
15072 | mips_pic = NO_PIC; | |
15073 | mips_abicalls = TRUE; | |
15074 | break; | |
15075 | ||
252b5132 | 15076 | case OPTION_NON_SHARED: |
f43abd2b | 15077 | if (!IS_ELF) |
252b5132 RH |
15078 | { |
15079 | as_bad (_("-non_shared is supported only for ELF format")); | |
15080 | return 0; | |
15081 | } | |
15082 | mips_pic = NO_PIC; | |
143d77c5 | 15083 | mips_abicalls = FALSE; |
252b5132 RH |
15084 | break; |
15085 | ||
44075ae2 TS |
15086 | /* The -xgot option tells the assembler to use 32 bit offsets |
15087 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15088 | compatibility. */ |
15089 | case OPTION_XGOT: | |
15090 | mips_big_got = 1; | |
15091 | break; | |
0f074f60 | 15092 | #endif /* OBJ_ELF */ |
252b5132 RH |
15093 | |
15094 | case 'G': | |
6caf9ef4 TS |
15095 | g_switch_value = atoi (arg); |
15096 | g_switch_seen = 1; | |
252b5132 RH |
15097 | break; |
15098 | ||
34ba82a8 TS |
15099 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15100 | and -mabi=64. */ | |
252b5132 | 15101 | case OPTION_32: |
23fce1e3 NC |
15102 | if (IS_ELF) |
15103 | mips_abi = O32_ABI; | |
15104 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15105 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15106 | break; |
15107 | ||
23fce1e3 | 15108 | #ifdef OBJ_ELF |
e013f690 | 15109 | case OPTION_N32: |
f43abd2b | 15110 | if (!IS_ELF) |
34ba82a8 TS |
15111 | { |
15112 | as_bad (_("-n32 is supported for ELF format only")); | |
15113 | return 0; | |
15114 | } | |
316f5878 | 15115 | mips_abi = N32_ABI; |
e013f690 | 15116 | break; |
252b5132 | 15117 | |
e013f690 | 15118 | case OPTION_64: |
f43abd2b | 15119 | if (!IS_ELF) |
34ba82a8 TS |
15120 | { |
15121 | as_bad (_("-64 is supported for ELF format only")); | |
15122 | return 0; | |
15123 | } | |
316f5878 | 15124 | mips_abi = N64_ABI; |
f43abd2b | 15125 | if (!support_64bit_objects()) |
e013f690 | 15126 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15127 | break; |
ae948b86 | 15128 | #endif /* OBJ_ELF */ |
252b5132 | 15129 | |
c97ef257 | 15130 | case OPTION_GP32: |
a325df1d | 15131 | file_mips_gp32 = 1; |
c97ef257 AH |
15132 | break; |
15133 | ||
15134 | case OPTION_GP64: | |
a325df1d | 15135 | file_mips_gp32 = 0; |
c97ef257 | 15136 | break; |
252b5132 | 15137 | |
ca4e0257 | 15138 | case OPTION_FP32: |
a325df1d | 15139 | file_mips_fp32 = 1; |
316f5878 RS |
15140 | break; |
15141 | ||
15142 | case OPTION_FP64: | |
15143 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15144 | break; |
15145 | ||
037b32b9 AN |
15146 | case OPTION_SINGLE_FLOAT: |
15147 | file_mips_single_float = 1; | |
15148 | break; | |
15149 | ||
15150 | case OPTION_DOUBLE_FLOAT: | |
15151 | file_mips_single_float = 0; | |
15152 | break; | |
15153 | ||
15154 | case OPTION_SOFT_FLOAT: | |
15155 | file_mips_soft_float = 1; | |
15156 | break; | |
15157 | ||
15158 | case OPTION_HARD_FLOAT: | |
15159 | file_mips_soft_float = 0; | |
15160 | break; | |
15161 | ||
ae948b86 | 15162 | #ifdef OBJ_ELF |
252b5132 | 15163 | case OPTION_MABI: |
f43abd2b | 15164 | if (!IS_ELF) |
34ba82a8 TS |
15165 | { |
15166 | as_bad (_("-mabi is supported for ELF format only")); | |
15167 | return 0; | |
15168 | } | |
e013f690 | 15169 | if (strcmp (arg, "32") == 0) |
316f5878 | 15170 | mips_abi = O32_ABI; |
e013f690 | 15171 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15172 | mips_abi = O64_ABI; |
e013f690 | 15173 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15174 | mips_abi = N32_ABI; |
e013f690 TS |
15175 | else if (strcmp (arg, "64") == 0) |
15176 | { | |
316f5878 | 15177 | mips_abi = N64_ABI; |
e013f690 TS |
15178 | if (! support_64bit_objects()) |
15179 | as_fatal (_("No compiled in support for 64 bit object file " | |
15180 | "format")); | |
15181 | } | |
15182 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15183 | mips_abi = EABI_ABI; |
e013f690 | 15184 | else |
da0e507f TS |
15185 | { |
15186 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15187 | return 0; | |
15188 | } | |
252b5132 | 15189 | break; |
e013f690 | 15190 | #endif /* OBJ_ELF */ |
252b5132 | 15191 | |
6b76fefe | 15192 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15193 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15194 | break; |
15195 | ||
9ee72ff1 | 15196 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15197 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15198 | break; |
15199 | ||
ecb4347a DJ |
15200 | #ifdef OBJ_ELF |
15201 | case OPTION_MDEBUG: | |
b34976b6 | 15202 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15203 | break; |
15204 | ||
15205 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15206 | mips_flag_mdebug = FALSE; |
ecb4347a | 15207 | break; |
dcd410fe RO |
15208 | |
15209 | case OPTION_PDR: | |
15210 | mips_flag_pdr = TRUE; | |
15211 | break; | |
15212 | ||
15213 | case OPTION_NO_PDR: | |
15214 | mips_flag_pdr = FALSE; | |
15215 | break; | |
0a44bf69 RS |
15216 | |
15217 | case OPTION_MVXWORKS_PIC: | |
15218 | mips_pic = VXWORKS_PIC; | |
15219 | break; | |
ecb4347a DJ |
15220 | #endif /* OBJ_ELF */ |
15221 | ||
252b5132 RH |
15222 | default: |
15223 | return 0; | |
15224 | } | |
15225 | ||
c67a084a NC |
15226 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15227 | ||
252b5132 RH |
15228 | return 1; |
15229 | } | |
316f5878 RS |
15230 | \f |
15231 | /* Set up globals to generate code for the ISA or processor | |
15232 | described by INFO. */ | |
252b5132 | 15233 | |
252b5132 | 15234 | static void |
17a2f251 | 15235 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15236 | { |
316f5878 | 15237 | if (info != 0) |
252b5132 | 15238 | { |
fef14a42 TS |
15239 | file_mips_arch = info->cpu; |
15240 | mips_opts.arch = info->cpu; | |
316f5878 | 15241 | mips_opts.isa = info->isa; |
252b5132 | 15242 | } |
252b5132 RH |
15243 | } |
15244 | ||
252b5132 | 15245 | |
316f5878 | 15246 | /* Likewise for tuning. */ |
252b5132 | 15247 | |
316f5878 | 15248 | static void |
17a2f251 | 15249 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15250 | { |
15251 | if (info != 0) | |
fef14a42 | 15252 | mips_tune = info->cpu; |
316f5878 | 15253 | } |
80cc45a5 | 15254 | |
34ba82a8 | 15255 | |
252b5132 | 15256 | void |
17a2f251 | 15257 | mips_after_parse_args (void) |
e9670677 | 15258 | { |
fef14a42 TS |
15259 | const struct mips_cpu_info *arch_info = 0; |
15260 | const struct mips_cpu_info *tune_info = 0; | |
15261 | ||
e9670677 | 15262 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15263 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15264 | { |
6caf9ef4 | 15265 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15266 | as_bad (_("-G not supported in this configuration.")); |
15267 | g_switch_value = 0; | |
15268 | } | |
15269 | ||
cac012d6 AO |
15270 | if (mips_abi == NO_ABI) |
15271 | mips_abi = MIPS_DEFAULT_ABI; | |
15272 | ||
22923709 RS |
15273 | /* The following code determines the architecture and register size. |
15274 | Similar code was added to GCC 3.3 (see override_options() in | |
15275 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15276 | as much as possible. */ | |
e9670677 | 15277 | |
316f5878 | 15278 | if (mips_arch_string != 0) |
fef14a42 | 15279 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15280 | |
316f5878 | 15281 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15282 | { |
316f5878 | 15283 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15284 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15285 | the -march selection (if any). */ |
fef14a42 | 15286 | if (arch_info != 0) |
e9670677 | 15287 | { |
316f5878 RS |
15288 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15289 | There's no harm in specifying both as long as the ISA levels | |
15290 | are the same. */ | |
fef14a42 | 15291 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15292 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15293 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15294 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15295 | } |
316f5878 | 15296 | else |
fef14a42 | 15297 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15298 | } |
15299 | ||
fef14a42 | 15300 | if (arch_info == 0) |
95bfe26e MF |
15301 | { |
15302 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15303 | gas_assert (arch_info); | |
15304 | } | |
e9670677 | 15305 | |
fef14a42 | 15306 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15307 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15308 | arch_info->name); |
15309 | ||
15310 | mips_set_architecture (arch_info); | |
15311 | ||
15312 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15313 | if (mips_tune_string != 0) | |
15314 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15315 | |
fef14a42 TS |
15316 | if (tune_info == 0) |
15317 | mips_set_tune (arch_info); | |
15318 | else | |
15319 | mips_set_tune (tune_info); | |
e9670677 | 15320 | |
316f5878 | 15321 | if (file_mips_gp32 >= 0) |
e9670677 | 15322 | { |
316f5878 RS |
15323 | /* The user specified the size of the integer registers. Make sure |
15324 | it agrees with the ABI and ISA. */ | |
15325 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15326 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15327 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15328 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15329 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15330 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15331 | } |
15332 | else | |
15333 | { | |
316f5878 RS |
15334 | /* Infer the integer register size from the ABI and processor. |
15335 | Restrict ourselves to 32-bit registers if that's all the | |
15336 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15337 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15338 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15339 | } |
15340 | ||
ad3fea08 TS |
15341 | switch (file_mips_fp32) |
15342 | { | |
15343 | default: | |
15344 | case -1: | |
15345 | /* No user specified float register size. | |
15346 | ??? GAS treats single-float processors as though they had 64-bit | |
15347 | float registers (although it complains when double-precision | |
15348 | instructions are used). As things stand, saying they have 32-bit | |
15349 | registers would lead to spurious "register must be even" messages. | |
15350 | So here we assume float registers are never smaller than the | |
15351 | integer ones. */ | |
15352 | if (file_mips_gp32 == 0) | |
15353 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15354 | file_mips_fp32 = 0; | |
15355 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15356 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15357 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15358 | file_mips_fp32 = 0; | |
15359 | else | |
15360 | /* 32-bit float registers. */ | |
15361 | file_mips_fp32 = 1; | |
15362 | break; | |
15363 | ||
15364 | /* The user specified the size of the float registers. Check if it | |
15365 | agrees with the ABI and ISA. */ | |
15366 | case 0: | |
15367 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15368 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15369 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15370 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15371 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15372 | break; | |
15373 | case 1: | |
15374 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15375 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15376 | break; | |
15377 | } | |
e9670677 | 15378 | |
316f5878 | 15379 | /* End of GCC-shared inference code. */ |
e9670677 | 15380 | |
17a2f251 TS |
15381 | /* This flag is set when we have a 64-bit capable CPU but use only |
15382 | 32-bit wide registers. Note that EABI does not use it. */ | |
15383 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15384 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15385 | || mips_abi == O32_ABI)) | |
316f5878 | 15386 | mips_32bitmode = 1; |
e9670677 MR |
15387 | |
15388 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15389 | as_bad (_("trap exception not supported at ISA 1")); | |
15390 | ||
e9670677 MR |
15391 | /* If the selected architecture includes support for ASEs, enable |
15392 | generation of code for them. */ | |
a4672219 | 15393 | if (mips_opts.mips16 == -1) |
fef14a42 | 15394 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15395 | if (mips_opts.micromips == -1) |
15396 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15397 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15398 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15399 | && file_mips_fp32 == 0) ? 1 : 0; |
15400 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15401 | as_bad (_("-mfp32 used with -mips3d")); | |
15402 | ||
ffdefa66 | 15403 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15404 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15405 | && file_mips_fp32 == 0) ? 1 : 0; |
15406 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15407 | as_bad (_("-mfp32 used with -mdmx")); | |
15408 | ||
15409 | if (mips_opts.ase_smartmips == -1) | |
15410 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15411 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15412 | as_warn (_("%s ISA does not support SmartMIPS"), |
15413 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15414 | |
74cd071d | 15415 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15416 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15417 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15418 | as_warn (_("%s ISA does not support DSP ASE"), |
15419 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15420 | |
8b082fb1 TS |
15421 | if (mips_opts.ase_dspr2 == -1) |
15422 | { | |
15423 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15424 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15425 | } | |
15426 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15427 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15428 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15429 | |
ef2e4d86 | 15430 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15431 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15432 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15433 | as_warn (_("%s ISA does not support MT ASE"), |
15434 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15435 | |
dec0624d MR |
15436 | if (mips_opts.ase_mcu == -1) |
15437 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15438 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15439 | as_warn (_("%s ISA does not support MCU ASE"), | |
15440 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15441 | ||
b015e599 AP |
15442 | if (mips_opts.ase_virt == -1) |
15443 | mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0; | |
15444 | if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE) | |
15445 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
15446 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15447 | ||
e9670677 | 15448 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15449 | file_ase_mips3d = mips_opts.ase_mips3d; |
15450 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15451 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15452 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15453 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15454 | file_ase_mt = mips_opts.ase_mt; |
b015e599 | 15455 | file_ase_virt = mips_opts.ase_virt; |
e9670677 MR |
15456 | mips_opts.gp32 = file_mips_gp32; |
15457 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15458 | mips_opts.soft_float = file_mips_soft_float; |
15459 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15460 | |
ecb4347a DJ |
15461 | if (mips_flag_mdebug < 0) |
15462 | { | |
15463 | #ifdef OBJ_MAYBE_ECOFF | |
15464 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15465 | mips_flag_mdebug = 1; | |
15466 | else | |
15467 | #endif /* OBJ_MAYBE_ECOFF */ | |
15468 | mips_flag_mdebug = 0; | |
15469 | } | |
e9670677 MR |
15470 | } |
15471 | \f | |
15472 | void | |
17a2f251 | 15473 | mips_init_after_args (void) |
252b5132 RH |
15474 | { |
15475 | /* initialize opcodes */ | |
15476 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15477 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15478 | } |
15479 | ||
15480 | long | |
17a2f251 | 15481 | md_pcrel_from (fixS *fixP) |
252b5132 | 15482 | { |
a7ebbfdf TS |
15483 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15484 | switch (fixP->fx_r_type) | |
15485 | { | |
df58fc94 RS |
15486 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15487 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15488 | /* Return the address of the delay slot. */ | |
15489 | return addr + 2; | |
15490 | ||
15491 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15492 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15493 | case BFD_RELOC_16_PCREL_S2: |
15494 | case BFD_RELOC_MIPS_JMP: | |
15495 | /* Return the address of the delay slot. */ | |
15496 | return addr + 4; | |
df58fc94 | 15497 | |
b47468a6 CM |
15498 | case BFD_RELOC_32_PCREL: |
15499 | return addr; | |
15500 | ||
a7ebbfdf | 15501 | default: |
58ea3d6a | 15502 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15503 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15504 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15505 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15506 | return addr; |
15507 | } | |
252b5132 RH |
15508 | } |
15509 | ||
252b5132 RH |
15510 | /* This is called before the symbol table is processed. In order to |
15511 | work with gcc when using mips-tfile, we must keep all local labels. | |
15512 | However, in other cases, we want to discard them. If we were | |
15513 | called with -g, but we didn't see any debugging information, it may | |
15514 | mean that gcc is smuggling debugging information through to | |
15515 | mips-tfile, in which case we must generate all local labels. */ | |
15516 | ||
15517 | void | |
17a2f251 | 15518 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15519 | { |
15520 | #ifndef NO_ECOFF_DEBUGGING | |
15521 | if (ECOFF_DEBUGGING | |
15522 | && mips_debug != 0 | |
15523 | && ! ecoff_debugging_seen) | |
15524 | flag_keep_locals = 1; | |
15525 | #endif | |
15526 | } | |
15527 | ||
3b91255e | 15528 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15529 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15530 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15531 | relocation operators. | |
15532 | ||
15533 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15534 | expression if: | |
15535 | ||
15536 | (a) it refers to the same symbol; and | |
15537 | (b) the offset applied in the %lo() expression is no lower than | |
15538 | the offset applied in the %got() or %hi(). | |
15539 | ||
15540 | (b) allows us to cope with code like: | |
15541 | ||
15542 | lui $4,%hi(foo) | |
15543 | lh $4,%lo(foo+2)($4) | |
15544 | ||
15545 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15546 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15547 | the high 16 bits. | |
15548 | ||
15549 | When several %lo()s match a particular %got() or %hi(), we use the | |
15550 | following rules to distinguish them: | |
15551 | ||
15552 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15553 | higher offsets. | |
15554 | ||
15555 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15556 | that already have a matching %got() or %hi(). | |
15557 | ||
15558 | (3) later %lo()s are better than earlier %lo()s. | |
15559 | ||
15560 | These rules are applied in order. | |
15561 | ||
15562 | (1) means, among other things, that %lo()s with identical offsets are | |
15563 | chosen if they exist. | |
15564 | ||
15565 | (2) means that we won't associate several high-part relocations with | |
15566 | the same low-part relocation unless there's no alternative. Having | |
15567 | several high parts for the same low part is a GNU extension; this rule | |
15568 | allows careful users to avoid it. | |
15569 | ||
15570 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15571 | with the last high-part relocation being at the front of the list. | |
15572 | It therefore makes sense to choose the last matching low-part | |
15573 | relocation, all other things being equal. It's also easier | |
15574 | to code that way. */ | |
252b5132 RH |
15575 | |
15576 | void | |
17a2f251 | 15577 | mips_frob_file (void) |
252b5132 RH |
15578 | { |
15579 | struct mips_hi_fixup *l; | |
35903be0 | 15580 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15581 | |
15582 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15583 | { | |
15584 | segment_info_type *seginfo; | |
3b91255e RS |
15585 | bfd_boolean matched_lo_p; |
15586 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15587 | |
9c2799c2 | 15588 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15589 | |
5919d012 | 15590 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15591 | there isn't supposed to be a matching LO. Ignore %gots against |
15592 | constants; we'll report an error for those later. */ | |
738e5348 | 15593 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15594 | && !(l->fixp->fx_addsy |
15595 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15596 | continue; |
15597 | ||
15598 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15599 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15600 | continue; |
15601 | ||
252b5132 | 15602 | seginfo = seg_info (l->seg); |
252b5132 | 15603 | |
3b91255e RS |
15604 | /* Set HI_POS to the position of this relocation in the chain. |
15605 | Set LO_POS to the position of the chosen low-part relocation. | |
15606 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15607 | relocation that matches an immediately-preceding high-part | |
15608 | relocation. */ | |
15609 | hi_pos = NULL; | |
15610 | lo_pos = NULL; | |
15611 | matched_lo_p = FALSE; | |
738e5348 | 15612 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15613 | |
3b91255e RS |
15614 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15615 | { | |
15616 | if (*pos == l->fixp) | |
15617 | hi_pos = pos; | |
15618 | ||
35903be0 | 15619 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15620 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15621 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15622 | && (lo_pos == NULL | |
15623 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15624 | || (!matched_lo_p | |
15625 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15626 | lo_pos = pos; | |
15627 | ||
15628 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15629 | && fixup_has_matching_lo_p (*pos)); | |
15630 | } | |
15631 | ||
15632 | /* If we found a match, remove the high-part relocation from its | |
15633 | current position and insert it before the low-part relocation. | |
15634 | Make the offsets match so that fixup_has_matching_lo_p() | |
15635 | will return true. | |
15636 | ||
15637 | We don't warn about unmatched high-part relocations since some | |
15638 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15639 | instructions. */ | |
15640 | if (lo_pos != NULL) | |
15641 | { | |
15642 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15643 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15644 | { |
3b91255e RS |
15645 | *hi_pos = l->fixp->fx_next; |
15646 | l->fixp->fx_next = *lo_pos; | |
15647 | *lo_pos = l->fixp; | |
252b5132 | 15648 | } |
252b5132 RH |
15649 | } |
15650 | } | |
15651 | } | |
15652 | ||
252b5132 | 15653 | int |
17a2f251 | 15654 | mips_force_relocation (fixS *fixp) |
252b5132 | 15655 | { |
ae6063d4 | 15656 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15657 | return 1; |
15658 | ||
df58fc94 RS |
15659 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15660 | so that the linker relaxation can update targets. */ | |
15661 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15662 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15663 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15664 | return 1; | |
15665 | ||
3e722fb5 | 15666 | return 0; |
252b5132 RH |
15667 | } |
15668 | ||
b886a2ab RS |
15669 | /* Read the instruction associated with RELOC from BUF. */ |
15670 | ||
15671 | static unsigned int | |
15672 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15673 | { | |
15674 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15675 | return read_compressed_insn (buf, 4); | |
15676 | else | |
15677 | return read_insn (buf); | |
15678 | } | |
15679 | ||
15680 | /* Write instruction INSN to BUF, given that it has been relocated | |
15681 | by RELOC. */ | |
15682 | ||
15683 | static void | |
15684 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15685 | unsigned long insn) | |
15686 | { | |
15687 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15688 | write_compressed_insn (buf, insn, 4); | |
15689 | else | |
15690 | write_insn (buf, insn); | |
15691 | } | |
15692 | ||
252b5132 RH |
15693 | /* Apply a fixup to the object file. */ |
15694 | ||
94f592af | 15695 | void |
55cf6793 | 15696 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15697 | { |
4d68580a | 15698 | char *buf; |
b886a2ab | 15699 | unsigned long insn; |
a7ebbfdf | 15700 | reloc_howto_type *howto; |
252b5132 | 15701 | |
a7ebbfdf TS |
15702 | /* We ignore generic BFD relocations we don't know about. */ |
15703 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15704 | if (! howto) | |
15705 | return; | |
65551fa4 | 15706 | |
df58fc94 RS |
15707 | gas_assert (fixP->fx_size == 2 |
15708 | || fixP->fx_size == 4 | |
90ecf173 MR |
15709 | || fixP->fx_r_type == BFD_RELOC_16 |
15710 | || fixP->fx_r_type == BFD_RELOC_64 | |
15711 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15712 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15713 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15714 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15715 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15716 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15717 | |
4d68580a | 15718 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15719 | |
df58fc94 RS |
15720 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15721 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15722 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15723 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15724 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15725 | |
15726 | /* Don't treat parts of a composite relocation as done. There are two | |
15727 | reasons for this: | |
15728 | ||
15729 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15730 | should nevertheless be emitted if the first part is. | |
15731 | ||
15732 | (2) In normal usage, composite relocations are never assembly-time | |
15733 | constants. The easiest way of dealing with the pathological | |
15734 | exceptions is to generate a relocation against STN_UNDEF and | |
15735 | leave everything up to the linker. */ | |
3994f87e | 15736 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15737 | fixP->fx_done = 1; |
15738 | ||
15739 | switch (fixP->fx_r_type) | |
15740 | { | |
3f98094e DJ |
15741 | case BFD_RELOC_MIPS_TLS_GD: |
15742 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15743 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15744 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15745 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15746 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15747 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15748 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15749 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15750 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15751 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15752 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15753 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15754 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15755 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15756 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15757 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15758 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15759 | case BFD_RELOC_MIPS16_TLS_GD: |
15760 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15761 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15762 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15763 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15764 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15765 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15766 | if (!fixP->fx_addsy) |
15767 | { | |
15768 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15769 | _("TLS relocation against a constant")); | |
15770 | break; | |
15771 | } | |
3f98094e DJ |
15772 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15773 | /* fall through */ | |
15774 | ||
252b5132 | 15775 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15776 | case BFD_RELOC_MIPS_SHIFT5: |
15777 | case BFD_RELOC_MIPS_SHIFT6: | |
15778 | case BFD_RELOC_MIPS_GOT_DISP: | |
15779 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15780 | case BFD_RELOC_MIPS_GOT_OFST: | |
15781 | case BFD_RELOC_MIPS_SUB: | |
15782 | case BFD_RELOC_MIPS_INSERT_A: | |
15783 | case BFD_RELOC_MIPS_INSERT_B: | |
15784 | case BFD_RELOC_MIPS_DELETE: | |
15785 | case BFD_RELOC_MIPS_HIGHEST: | |
15786 | case BFD_RELOC_MIPS_HIGHER: | |
15787 | case BFD_RELOC_MIPS_SCN_DISP: | |
15788 | case BFD_RELOC_MIPS_REL16: | |
15789 | case BFD_RELOC_MIPS_RELGOT: | |
15790 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15791 | case BFD_RELOC_HI16: |
15792 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15793 | case BFD_RELOC_LO16: |
cdf6fd85 | 15794 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15795 | case BFD_RELOC_MIPS_LITERAL: |
15796 | case BFD_RELOC_MIPS_CALL16: | |
15797 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15798 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15799 | case BFD_RELOC_MIPS_GOT_HI16: |
15800 | case BFD_RELOC_MIPS_GOT_LO16: | |
15801 | case BFD_RELOC_MIPS_CALL_HI16: | |
15802 | case BFD_RELOC_MIPS_CALL_LO16: | |
15803 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15804 | case BFD_RELOC_MIPS16_GOT16: |
15805 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15806 | case BFD_RELOC_MIPS16_HI16: |
15807 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15808 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15809 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15810 | case BFD_RELOC_MICROMIPS_JMP: |
15811 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15812 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15813 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15814 | case BFD_RELOC_MICROMIPS_SUB: | |
15815 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15816 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15817 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15818 | case BFD_RELOC_MICROMIPS_JALR: | |
15819 | case BFD_RELOC_MICROMIPS_HI16: | |
15820 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15821 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15822 | case BFD_RELOC_MICROMIPS_GPREL16: |
15823 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15824 | case BFD_RELOC_MICROMIPS_CALL16: | |
15825 | case BFD_RELOC_MICROMIPS_GOT16: | |
15826 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15827 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15828 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15829 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15830 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15831 | if (fixP->fx_done) |
15832 | { | |
15833 | offsetT value; | |
15834 | ||
15835 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15836 | { | |
15837 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15838 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15839 | insn |= mips16_immed_extend (value, 16); | |
15840 | else | |
15841 | insn |= (value & 0xffff); | |
15842 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15843 | } | |
15844 | else | |
15845 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15846 | _("Unsupported constant in relocation")); | |
15847 | } | |
252b5132 RH |
15848 | break; |
15849 | ||
252b5132 RH |
15850 | case BFD_RELOC_64: |
15851 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15852 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15853 | if (fixP->fx_done) |
252b5132 RH |
15854 | { |
15855 | if (8 <= sizeof (valueT)) | |
4d68580a | 15856 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15857 | else |
15858 | { | |
a7ebbfdf | 15859 | valueT hiv; |
252b5132 | 15860 | |
a7ebbfdf | 15861 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15862 | hiv = 0xffffffff; |
15863 | else | |
15864 | hiv = 0; | |
4d68580a RS |
15865 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15866 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15867 | } |
15868 | } | |
15869 | break; | |
15870 | ||
056350c6 | 15871 | case BFD_RELOC_RVA: |
252b5132 | 15872 | case BFD_RELOC_32: |
b47468a6 | 15873 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15874 | case BFD_RELOC_16: |
15875 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15876 | value now. This can happen if we have a .word which is not |
15877 | resolved when it appears but is later defined. */ | |
252b5132 | 15878 | if (fixP->fx_done) |
4d68580a | 15879 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15880 | break; |
15881 | ||
252b5132 | 15882 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15883 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15884 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15885 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15886 | |
54f4ddb3 TS |
15887 | /* We need to save the bits in the instruction since fixup_segment() |
15888 | might be deleting the relocation entry (i.e., a branch within | |
15889 | the current segment). */ | |
a7ebbfdf | 15890 | if (! fixP->fx_done) |
bb2d6cd7 | 15891 | break; |
252b5132 | 15892 | |
54f4ddb3 | 15893 | /* Update old instruction data. */ |
4d68580a | 15894 | insn = read_insn (buf); |
252b5132 | 15895 | |
a7ebbfdf TS |
15896 | if (*valP + 0x20000 <= 0x3ffff) |
15897 | { | |
15898 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15899 | write_insn (buf, insn); |
a7ebbfdf TS |
15900 | } |
15901 | else if (mips_pic == NO_PIC | |
15902 | && fixP->fx_done | |
15903 | && fixP->fx_frag->fr_address >= text_section->vma | |
15904 | && (fixP->fx_frag->fr_address | |
587aac4e | 15905 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15906 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15907 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15908 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15909 | { |
15910 | /* The branch offset is too large. If this is an | |
15911 | unconditional branch, and we are not generating PIC code, | |
15912 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15913 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15914 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15915 | else |
a7ebbfdf TS |
15916 | insn = 0x08000000; /* j */ |
15917 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15918 | fixP->fx_done = 0; | |
15919 | fixP->fx_addsy = section_symbol (text_section); | |
15920 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15921 | write_insn (buf, insn); |
a7ebbfdf TS |
15922 | } |
15923 | else | |
15924 | { | |
15925 | /* If we got here, we have branch-relaxation disabled, | |
15926 | and there's nothing we can do to fix this instruction | |
15927 | without turning it into a longer sequence. */ | |
15928 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15929 | _("Branch out of range")); | |
252b5132 | 15930 | } |
252b5132 RH |
15931 | break; |
15932 | ||
df58fc94 RS |
15933 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15934 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15935 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15936 | /* We adjust the offset back to even. */ | |
15937 | if ((*valP & 0x1) != 0) | |
15938 | --(*valP); | |
15939 | ||
15940 | if (! fixP->fx_done) | |
15941 | break; | |
15942 | ||
15943 | /* Should never visit here, because we keep the relocation. */ | |
15944 | abort (); | |
15945 | break; | |
15946 | ||
252b5132 RH |
15947 | case BFD_RELOC_VTABLE_INHERIT: |
15948 | fixP->fx_done = 0; | |
15949 | if (fixP->fx_addsy | |
15950 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15951 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15952 | S_SET_WEAK (fixP->fx_addsy); | |
15953 | break; | |
15954 | ||
15955 | case BFD_RELOC_VTABLE_ENTRY: | |
15956 | fixP->fx_done = 0; | |
15957 | break; | |
15958 | ||
15959 | default: | |
b37df7c4 | 15960 | abort (); |
252b5132 | 15961 | } |
a7ebbfdf TS |
15962 | |
15963 | /* Remember value for tc_gen_reloc. */ | |
15964 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15965 | } |
15966 | ||
252b5132 | 15967 | static symbolS * |
17a2f251 | 15968 | get_symbol (void) |
252b5132 RH |
15969 | { |
15970 | int c; | |
15971 | char *name; | |
15972 | symbolS *p; | |
15973 | ||
15974 | name = input_line_pointer; | |
15975 | c = get_symbol_end (); | |
15976 | p = (symbolS *) symbol_find_or_make (name); | |
15977 | *input_line_pointer = c; | |
15978 | return p; | |
15979 | } | |
15980 | ||
742a56fe RS |
15981 | /* Align the current frag to a given power of two. If a particular |
15982 | fill byte should be used, FILL points to an integer that contains | |
15983 | that byte, otherwise FILL is null. | |
15984 | ||
462427c4 RS |
15985 | This function used to have the comment: |
15986 | ||
15987 | The MIPS assembler also automatically adjusts any preceding label. | |
15988 | ||
15989 | The implementation therefore applied the adjustment to a maximum of | |
15990 | one label. However, other label adjustments are applied to batches | |
15991 | of labels, and adjusting just one caused problems when new labels | |
15992 | were added for the sake of debugging or unwind information. | |
15993 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15994 | |
15995 | static void | |
462427c4 | 15996 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15997 | { |
7d10b47d | 15998 | mips_emit_delays (); |
df58fc94 | 15999 | mips_record_compressed_mode (); |
742a56fe RS |
16000 | if (fill == NULL && subseg_text_p (now_seg)) |
16001 | frag_align_code (to, 0); | |
16002 | else | |
16003 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16004 | record_alignment (now_seg, to); |
462427c4 | 16005 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16006 | } |
16007 | ||
16008 | /* Align to a given power of two. .align 0 turns off the automatic | |
16009 | alignment used by the data creating pseudo-ops. */ | |
16010 | ||
16011 | static void | |
17a2f251 | 16012 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16013 | { |
742a56fe | 16014 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16015 | long max_alignment = 28; |
252b5132 | 16016 | |
54f4ddb3 | 16017 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16018 | to the aligned address. |
54f4ddb3 | 16019 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16020 | a .align pseudo instruction. |
54f4ddb3 | 16021 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16022 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16023 | We don't. */ |
252b5132 RH |
16024 | |
16025 | temp = get_absolute_expression (); | |
16026 | if (temp > max_alignment) | |
16027 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16028 | else if (temp < 0) | |
16029 | { | |
16030 | as_warn (_("Alignment negative: 0 assumed.")); | |
16031 | temp = 0; | |
16032 | } | |
16033 | if (*input_line_pointer == ',') | |
16034 | { | |
f9419b05 | 16035 | ++input_line_pointer; |
742a56fe RS |
16036 | fill_value = get_absolute_expression (); |
16037 | fill_ptr = &fill_value; | |
252b5132 RH |
16038 | } |
16039 | else | |
742a56fe | 16040 | fill_ptr = 0; |
252b5132 RH |
16041 | if (temp) |
16042 | { | |
a8dbcb85 TS |
16043 | segment_info_type *si = seg_info (now_seg); |
16044 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16045 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16046 | auto_align = 1; |
462427c4 | 16047 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16048 | } |
16049 | else | |
16050 | { | |
16051 | auto_align = 0; | |
16052 | } | |
16053 | ||
16054 | demand_empty_rest_of_line (); | |
16055 | } | |
16056 | ||
252b5132 | 16057 | static void |
17a2f251 | 16058 | s_change_sec (int sec) |
252b5132 RH |
16059 | { |
16060 | segT seg; | |
16061 | ||
252b5132 RH |
16062 | #ifdef OBJ_ELF |
16063 | /* The ELF backend needs to know that we are changing sections, so | |
16064 | that .previous works correctly. We could do something like check | |
b6ff326e | 16065 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16066 | as it would not be appropriate to use it in the section changing |
16067 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16068 | This should be cleaner, somehow. */ | |
f43abd2b TS |
16069 | if (IS_ELF) |
16070 | obj_elf_section_change_hook (); | |
252b5132 RH |
16071 | #endif |
16072 | ||
7d10b47d | 16073 | mips_emit_delays (); |
6a32d874 | 16074 | |
252b5132 RH |
16075 | switch (sec) |
16076 | { | |
16077 | case 't': | |
16078 | s_text (0); | |
16079 | break; | |
16080 | case 'd': | |
16081 | s_data (0); | |
16082 | break; | |
16083 | case 'b': | |
16084 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16085 | demand_empty_rest_of_line (); | |
16086 | break; | |
16087 | ||
16088 | case 'r': | |
4d0d148d TS |
16089 | seg = subseg_new (RDATA_SECTION_NAME, |
16090 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16091 | if (IS_ELF) |
252b5132 | 16092 | { |
4d0d148d TS |
16093 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16094 | | SEC_READONLY | SEC_RELOC | |
16095 | | SEC_DATA)); | |
c41e87e3 | 16096 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16097 | record_alignment (seg, 4); |
252b5132 | 16098 | } |
4d0d148d | 16099 | demand_empty_rest_of_line (); |
252b5132 RH |
16100 | break; |
16101 | ||
16102 | case 's': | |
4d0d148d | 16103 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16104 | if (IS_ELF) |
252b5132 | 16105 | { |
4d0d148d TS |
16106 | bfd_set_section_flags (stdoutput, seg, |
16107 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16108 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16109 | record_alignment (seg, 4); |
252b5132 | 16110 | } |
4d0d148d TS |
16111 | demand_empty_rest_of_line (); |
16112 | break; | |
998b3c36 MR |
16113 | |
16114 | case 'B': | |
16115 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16116 | if (IS_ELF) | |
16117 | { | |
16118 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16119 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16120 | record_alignment (seg, 4); | |
16121 | } | |
16122 | demand_empty_rest_of_line (); | |
16123 | break; | |
252b5132 RH |
16124 | } |
16125 | ||
16126 | auto_align = 1; | |
16127 | } | |
b34976b6 | 16128 | |
cca86cc8 | 16129 | void |
17a2f251 | 16130 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16131 | { |
7ed4a06a | 16132 | #ifdef OBJ_ELF |
cca86cc8 SC |
16133 | char *section_name; |
16134 | char c; | |
684022ea | 16135 | char next_c = 0; |
cca86cc8 SC |
16136 | int section_type; |
16137 | int section_flag; | |
16138 | int section_entry_size; | |
16139 | int section_alignment; | |
b34976b6 | 16140 | |
f43abd2b | 16141 | if (!IS_ELF) |
7ed4a06a TS |
16142 | return; |
16143 | ||
cca86cc8 SC |
16144 | section_name = input_line_pointer; |
16145 | c = get_symbol_end (); | |
a816d1ed AO |
16146 | if (c) |
16147 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16148 | |
4cf0dd0d TS |
16149 | /* Do we have .section Name<,"flags">? */ |
16150 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16151 | { |
4cf0dd0d TS |
16152 | /* just after name is now '\0'. */ |
16153 | *input_line_pointer = c; | |
cca86cc8 SC |
16154 | input_line_pointer = section_name; |
16155 | obj_elf_section (ignore); | |
16156 | return; | |
16157 | } | |
16158 | input_line_pointer++; | |
16159 | ||
16160 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16161 | if (c == ',') | |
16162 | section_type = get_absolute_expression (); | |
16163 | else | |
16164 | section_type = 0; | |
16165 | if (*input_line_pointer++ == ',') | |
16166 | section_flag = get_absolute_expression (); | |
16167 | else | |
16168 | section_flag = 0; | |
16169 | if (*input_line_pointer++ == ',') | |
16170 | section_entry_size = get_absolute_expression (); | |
16171 | else | |
16172 | section_entry_size = 0; | |
16173 | if (*input_line_pointer++ == ',') | |
16174 | section_alignment = get_absolute_expression (); | |
16175 | else | |
16176 | section_alignment = 0; | |
87975d2a AM |
16177 | /* FIXME: really ignore? */ |
16178 | (void) section_alignment; | |
cca86cc8 | 16179 | |
a816d1ed AO |
16180 | section_name = xstrdup (section_name); |
16181 | ||
8ab8a5c8 RS |
16182 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16183 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16184 | traditionally had to fall back on the more common @progbits instead. | |
16185 | ||
16186 | There's nothing really harmful in this, since bfd will correct | |
16187 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16188 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16189 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16190 | ||
16191 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16192 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16193 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16194 | generic type-checking code. */ | |
16195 | if (section_type == SHT_MIPS_DWARF) | |
16196 | section_type = SHT_PROGBITS; | |
16197 | ||
cca86cc8 SC |
16198 | obj_elf_change_section (section_name, section_type, section_flag, |
16199 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16200 | |
16201 | if (now_seg->name != section_name) | |
16202 | free (section_name); | |
7ed4a06a | 16203 | #endif /* OBJ_ELF */ |
cca86cc8 | 16204 | } |
252b5132 RH |
16205 | |
16206 | void | |
17a2f251 | 16207 | mips_enable_auto_align (void) |
252b5132 RH |
16208 | { |
16209 | auto_align = 1; | |
16210 | } | |
16211 | ||
16212 | static void | |
17a2f251 | 16213 | s_cons (int log_size) |
252b5132 | 16214 | { |
a8dbcb85 TS |
16215 | segment_info_type *si = seg_info (now_seg); |
16216 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16217 | |
7d10b47d | 16218 | mips_emit_delays (); |
252b5132 | 16219 | if (log_size > 0 && auto_align) |
462427c4 | 16220 | mips_align (log_size, 0, l); |
252b5132 | 16221 | cons (1 << log_size); |
a1facbec | 16222 | mips_clear_insn_labels (); |
252b5132 RH |
16223 | } |
16224 | ||
16225 | static void | |
17a2f251 | 16226 | s_float_cons (int type) |
252b5132 | 16227 | { |
a8dbcb85 TS |
16228 | segment_info_type *si = seg_info (now_seg); |
16229 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16230 | |
7d10b47d | 16231 | mips_emit_delays (); |
252b5132 RH |
16232 | |
16233 | if (auto_align) | |
49309057 ILT |
16234 | { |
16235 | if (type == 'd') | |
462427c4 | 16236 | mips_align (3, 0, l); |
49309057 | 16237 | else |
462427c4 | 16238 | mips_align (2, 0, l); |
49309057 | 16239 | } |
252b5132 | 16240 | |
252b5132 | 16241 | float_cons (type); |
a1facbec | 16242 | mips_clear_insn_labels (); |
252b5132 RH |
16243 | } |
16244 | ||
16245 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16246 | permitted to say | |
16247 | .globl foo .text | |
16248 | where foo is an undefined symbol, to mean that foo should be | |
16249 | considered to be the address of a function. */ | |
16250 | ||
16251 | static void | |
17a2f251 | 16252 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16253 | { |
16254 | char *name; | |
16255 | int c; | |
16256 | symbolS *symbolP; | |
16257 | flagword flag; | |
16258 | ||
8a06b769 | 16259 | do |
252b5132 | 16260 | { |
8a06b769 | 16261 | name = input_line_pointer; |
252b5132 | 16262 | c = get_symbol_end (); |
8a06b769 TS |
16263 | symbolP = symbol_find_or_make (name); |
16264 | S_SET_EXTERNAL (symbolP); | |
16265 | ||
252b5132 | 16266 | *input_line_pointer = c; |
8a06b769 | 16267 | SKIP_WHITESPACE (); |
252b5132 | 16268 | |
8a06b769 TS |
16269 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16270 | being a function is apparently labelled as being an object. */ | |
16271 | flag = BSF_OBJECT; | |
252b5132 | 16272 | |
8a06b769 TS |
16273 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16274 | && (*input_line_pointer != ',')) | |
16275 | { | |
16276 | char *secname; | |
16277 | asection *sec; | |
16278 | ||
16279 | secname = input_line_pointer; | |
16280 | c = get_symbol_end (); | |
16281 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16282 | if (sec == NULL) | |
16283 | as_bad (_("%s: no such section"), secname); | |
16284 | *input_line_pointer = c; | |
16285 | ||
16286 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16287 | flag = BSF_FUNCTION; | |
16288 | } | |
16289 | ||
16290 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16291 | ||
16292 | c = *input_line_pointer; | |
16293 | if (c == ',') | |
16294 | { | |
16295 | input_line_pointer++; | |
16296 | SKIP_WHITESPACE (); | |
16297 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16298 | c = '\n'; | |
16299 | } | |
16300 | } | |
16301 | while (c == ','); | |
252b5132 | 16302 | |
252b5132 RH |
16303 | demand_empty_rest_of_line (); |
16304 | } | |
16305 | ||
16306 | static void | |
17a2f251 | 16307 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16308 | { |
16309 | char *opt; | |
16310 | char c; | |
16311 | ||
16312 | opt = input_line_pointer; | |
16313 | c = get_symbol_end (); | |
16314 | ||
16315 | if (*opt == 'O') | |
16316 | { | |
16317 | /* FIXME: What does this mean? */ | |
16318 | } | |
16319 | else if (strncmp (opt, "pic", 3) == 0) | |
16320 | { | |
16321 | int i; | |
16322 | ||
16323 | i = atoi (opt + 3); | |
16324 | if (i == 0) | |
16325 | mips_pic = NO_PIC; | |
16326 | else if (i == 2) | |
143d77c5 | 16327 | { |
8b828383 | 16328 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16329 | mips_abicalls = TRUE; |
16330 | } | |
252b5132 RH |
16331 | else |
16332 | as_bad (_(".option pic%d not supported"), i); | |
16333 | ||
4d0d148d | 16334 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16335 | { |
16336 | if (g_switch_seen && g_switch_value != 0) | |
16337 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16338 | g_switch_value = 0; | |
16339 | bfd_set_gp_size (stdoutput, 0); | |
16340 | } | |
16341 | } | |
16342 | else | |
16343 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16344 | ||
16345 | *input_line_pointer = c; | |
16346 | demand_empty_rest_of_line (); | |
16347 | } | |
16348 | ||
16349 | /* This structure is used to hold a stack of .set values. */ | |
16350 | ||
e972090a NC |
16351 | struct mips_option_stack |
16352 | { | |
252b5132 RH |
16353 | struct mips_option_stack *next; |
16354 | struct mips_set_options options; | |
16355 | }; | |
16356 | ||
16357 | static struct mips_option_stack *mips_opts_stack; | |
16358 | ||
16359 | /* Handle the .set pseudo-op. */ | |
16360 | ||
16361 | static void | |
17a2f251 | 16362 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16363 | { |
16364 | char *name = input_line_pointer, ch; | |
16365 | ||
16366 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16367 | ++input_line_pointer; |
252b5132 RH |
16368 | ch = *input_line_pointer; |
16369 | *input_line_pointer = '\0'; | |
16370 | ||
16371 | if (strcmp (name, "reorder") == 0) | |
16372 | { | |
7d10b47d RS |
16373 | if (mips_opts.noreorder) |
16374 | end_noreorder (); | |
252b5132 RH |
16375 | } |
16376 | else if (strcmp (name, "noreorder") == 0) | |
16377 | { | |
7d10b47d RS |
16378 | if (!mips_opts.noreorder) |
16379 | start_noreorder (); | |
252b5132 | 16380 | } |
741fe287 MR |
16381 | else if (strncmp (name, "at=", 3) == 0) |
16382 | { | |
16383 | char *s = name + 3; | |
16384 | ||
16385 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16386 | as_bad (_("Unrecognized register name `%s'"), s); | |
16387 | } | |
252b5132 RH |
16388 | else if (strcmp (name, "at") == 0) |
16389 | { | |
741fe287 | 16390 | mips_opts.at = ATREG; |
252b5132 RH |
16391 | } |
16392 | else if (strcmp (name, "noat") == 0) | |
16393 | { | |
741fe287 | 16394 | mips_opts.at = ZERO; |
252b5132 RH |
16395 | } |
16396 | else if (strcmp (name, "macro") == 0) | |
16397 | { | |
16398 | mips_opts.warn_about_macros = 0; | |
16399 | } | |
16400 | else if (strcmp (name, "nomacro") == 0) | |
16401 | { | |
16402 | if (mips_opts.noreorder == 0) | |
16403 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16404 | mips_opts.warn_about_macros = 1; | |
16405 | } | |
16406 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16407 | { | |
16408 | mips_opts.nomove = 0; | |
16409 | } | |
16410 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16411 | { | |
16412 | mips_opts.nomove = 1; | |
16413 | } | |
16414 | else if (strcmp (name, "bopt") == 0) | |
16415 | { | |
16416 | mips_opts.nobopt = 0; | |
16417 | } | |
16418 | else if (strcmp (name, "nobopt") == 0) | |
16419 | { | |
16420 | mips_opts.nobopt = 1; | |
16421 | } | |
ad3fea08 TS |
16422 | else if (strcmp (name, "gp=default") == 0) |
16423 | mips_opts.gp32 = file_mips_gp32; | |
16424 | else if (strcmp (name, "gp=32") == 0) | |
16425 | mips_opts.gp32 = 1; | |
16426 | else if (strcmp (name, "gp=64") == 0) | |
16427 | { | |
16428 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16429 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16430 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16431 | mips_opts.gp32 = 0; | |
16432 | } | |
16433 | else if (strcmp (name, "fp=default") == 0) | |
16434 | mips_opts.fp32 = file_mips_fp32; | |
16435 | else if (strcmp (name, "fp=32") == 0) | |
16436 | mips_opts.fp32 = 1; | |
16437 | else if (strcmp (name, "fp=64") == 0) | |
16438 | { | |
16439 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16440 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16441 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16442 | mips_opts.fp32 = 0; | |
16443 | } | |
037b32b9 AN |
16444 | else if (strcmp (name, "softfloat") == 0) |
16445 | mips_opts.soft_float = 1; | |
16446 | else if (strcmp (name, "hardfloat") == 0) | |
16447 | mips_opts.soft_float = 0; | |
16448 | else if (strcmp (name, "singlefloat") == 0) | |
16449 | mips_opts.single_float = 1; | |
16450 | else if (strcmp (name, "doublefloat") == 0) | |
16451 | mips_opts.single_float = 0; | |
252b5132 RH |
16452 | else if (strcmp (name, "mips16") == 0 |
16453 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16454 | { |
16455 | if (mips_opts.micromips == 1) | |
16456 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16457 | mips_opts.mips16 = 1; | |
16458 | } | |
252b5132 RH |
16459 | else if (strcmp (name, "nomips16") == 0 |
16460 | || strcmp (name, "noMIPS-16") == 0) | |
16461 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16462 | else if (strcmp (name, "micromips") == 0) |
16463 | { | |
16464 | if (mips_opts.mips16 == 1) | |
16465 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16466 | mips_opts.micromips = 1; | |
16467 | } | |
16468 | else if (strcmp (name, "nomicromips") == 0) | |
16469 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16470 | else if (strcmp (name, "smartmips") == 0) |
16471 | { | |
ad3fea08 | 16472 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16473 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16474 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16475 | mips_opts.ase_smartmips = 1; | |
16476 | } | |
16477 | else if (strcmp (name, "nosmartmips") == 0) | |
16478 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16479 | else if (strcmp (name, "mips3d") == 0) |
16480 | mips_opts.ase_mips3d = 1; | |
16481 | else if (strcmp (name, "nomips3d") == 0) | |
16482 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16483 | else if (strcmp (name, "mdmx") == 0) |
16484 | mips_opts.ase_mdmx = 1; | |
16485 | else if (strcmp (name, "nomdmx") == 0) | |
16486 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16487 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16488 | { |
16489 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16490 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16491 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16492 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16493 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16494 | } |
74cd071d | 16495 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16496 | { |
16497 | mips_opts.ase_dsp = 0; | |
16498 | mips_opts.ase_dspr2 = 0; | |
16499 | } | |
16500 | else if (strcmp (name, "dspr2") == 0) | |
16501 | { | |
16502 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16503 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16504 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16505 | mips_opts.ase_dspr2 = 1; | |
16506 | mips_opts.ase_dsp = 1; | |
16507 | } | |
16508 | else if (strcmp (name, "nodspr2") == 0) | |
16509 | { | |
16510 | mips_opts.ase_dspr2 = 0; | |
16511 | mips_opts.ase_dsp = 0; | |
16512 | } | |
ef2e4d86 | 16513 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16514 | { |
16515 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16516 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16517 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16518 | mips_opts.ase_mt = 1; | |
16519 | } | |
ef2e4d86 CF |
16520 | else if (strcmp (name, "nomt") == 0) |
16521 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16522 | else if (strcmp (name, "mcu") == 0) |
16523 | mips_opts.ase_mcu = 1; | |
16524 | else if (strcmp (name, "nomcu") == 0) | |
16525 | mips_opts.ase_mcu = 0; | |
b015e599 AP |
16526 | else if (strcmp (name, "virt") == 0) |
16527 | { | |
16528 | if (!ISA_SUPPORTS_VIRT_ASE) | |
16529 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
16530 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
16531 | mips_opts.ase_virt = 1; | |
16532 | } | |
16533 | else if (strcmp (name, "novirt") == 0) | |
16534 | mips_opts.ase_virt = 0; | |
1a2c1fad | 16535 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16536 | { |
af7ee8bf | 16537 | int reset = 0; |
252b5132 | 16538 | |
1a2c1fad CD |
16539 | /* Permit the user to change the ISA and architecture on the fly. |
16540 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16541 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16542 | { |
16543 | reset = 1; | |
16544 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16545 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16546 | } |
16547 | else if (strncmp (name, "arch=", 5) == 0) | |
16548 | { | |
16549 | const struct mips_cpu_info *p; | |
16550 | ||
16551 | p = mips_parse_cpu("internal use", name + 5); | |
16552 | if (!p) | |
16553 | as_bad (_("unknown architecture %s"), name + 5); | |
16554 | else | |
16555 | { | |
16556 | mips_opts.arch = p->cpu; | |
16557 | mips_opts.isa = p->isa; | |
16558 | } | |
16559 | } | |
81a21e38 TS |
16560 | else if (strncmp (name, "mips", 4) == 0) |
16561 | { | |
16562 | const struct mips_cpu_info *p; | |
16563 | ||
16564 | p = mips_parse_cpu("internal use", name); | |
16565 | if (!p) | |
16566 | as_bad (_("unknown ISA level %s"), name + 4); | |
16567 | else | |
16568 | { | |
16569 | mips_opts.arch = p->cpu; | |
16570 | mips_opts.isa = p->isa; | |
16571 | } | |
16572 | } | |
af7ee8bf | 16573 | else |
81a21e38 | 16574 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16575 | |
16576 | switch (mips_opts.isa) | |
98d3f06f KH |
16577 | { |
16578 | case 0: | |
98d3f06f | 16579 | break; |
af7ee8bf CD |
16580 | case ISA_MIPS1: |
16581 | case ISA_MIPS2: | |
16582 | case ISA_MIPS32: | |
16583 | case ISA_MIPS32R2: | |
98d3f06f KH |
16584 | mips_opts.gp32 = 1; |
16585 | mips_opts.fp32 = 1; | |
16586 | break; | |
af7ee8bf CD |
16587 | case ISA_MIPS3: |
16588 | case ISA_MIPS4: | |
16589 | case ISA_MIPS5: | |
16590 | case ISA_MIPS64: | |
5f74bc13 | 16591 | case ISA_MIPS64R2: |
98d3f06f | 16592 | mips_opts.gp32 = 0; |
e407c74b NC |
16593 | if (mips_opts.arch == CPU_R5900) |
16594 | { | |
16595 | mips_opts.fp32 = 1; | |
16596 | } | |
16597 | else | |
16598 | { | |
98d3f06f | 16599 | mips_opts.fp32 = 0; |
e407c74b | 16600 | } |
98d3f06f KH |
16601 | break; |
16602 | default: | |
16603 | as_bad (_("unknown ISA level %s"), name + 4); | |
16604 | break; | |
16605 | } | |
af7ee8bf | 16606 | if (reset) |
98d3f06f | 16607 | { |
af7ee8bf CD |
16608 | mips_opts.gp32 = file_mips_gp32; |
16609 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16610 | } |
252b5132 RH |
16611 | } |
16612 | else if (strcmp (name, "autoextend") == 0) | |
16613 | mips_opts.noautoextend = 0; | |
16614 | else if (strcmp (name, "noautoextend") == 0) | |
16615 | mips_opts.noautoextend = 1; | |
16616 | else if (strcmp (name, "push") == 0) | |
16617 | { | |
16618 | struct mips_option_stack *s; | |
16619 | ||
16620 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16621 | s->next = mips_opts_stack; | |
16622 | s->options = mips_opts; | |
16623 | mips_opts_stack = s; | |
16624 | } | |
16625 | else if (strcmp (name, "pop") == 0) | |
16626 | { | |
16627 | struct mips_option_stack *s; | |
16628 | ||
16629 | s = mips_opts_stack; | |
16630 | if (s == NULL) | |
16631 | as_bad (_(".set pop with no .set push")); | |
16632 | else | |
16633 | { | |
16634 | /* If we're changing the reorder mode we need to handle | |
16635 | delay slots correctly. */ | |
16636 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16637 | start_noreorder (); |
252b5132 | 16638 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16639 | end_noreorder (); |
252b5132 RH |
16640 | |
16641 | mips_opts = s->options; | |
16642 | mips_opts_stack = s->next; | |
16643 | free (s); | |
16644 | } | |
16645 | } | |
aed1a261 RS |
16646 | else if (strcmp (name, "sym32") == 0) |
16647 | mips_opts.sym32 = TRUE; | |
16648 | else if (strcmp (name, "nosym32") == 0) | |
16649 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16650 | else if (strchr (name, ',')) |
16651 | { | |
16652 | /* Generic ".set" directive; use the generic handler. */ | |
16653 | *input_line_pointer = ch; | |
16654 | input_line_pointer = name; | |
16655 | s_set (0); | |
16656 | return; | |
16657 | } | |
252b5132 RH |
16658 | else |
16659 | { | |
16660 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16661 | } | |
16662 | *input_line_pointer = ch; | |
16663 | demand_empty_rest_of_line (); | |
16664 | } | |
16665 | ||
16666 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16667 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16668 | ||
16669 | static void | |
17a2f251 | 16670 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16671 | { |
16672 | mips_pic = SVR4_PIC; | |
143d77c5 | 16673 | mips_abicalls = TRUE; |
4d0d148d TS |
16674 | |
16675 | if (g_switch_seen && g_switch_value != 0) | |
16676 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16677 | g_switch_value = 0; | |
16678 | ||
252b5132 RH |
16679 | bfd_set_gp_size (stdoutput, 0); |
16680 | demand_empty_rest_of_line (); | |
16681 | } | |
16682 | ||
16683 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16684 | PIC code. It sets the $gp register for the function based on the | |
16685 | function address, which is in the register named in the argument. | |
16686 | This uses a relocation against _gp_disp, which is handled specially | |
16687 | by the linker. The result is: | |
16688 | lui $gp,%hi(_gp_disp) | |
16689 | addiu $gp,$gp,%lo(_gp_disp) | |
16690 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16691 | The .cpload argument is normally $25 == $t9. |
16692 | ||
16693 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16694 | lui $gp,%hi(__gnu_local_gp) |
16695 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16696 | and the argument is ignored. This saves an instruction, but the |
16697 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16698 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16699 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16700 | |
16701 | static void | |
17a2f251 | 16702 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16703 | { |
16704 | expressionS ex; | |
aa6975fb ILT |
16705 | int reg; |
16706 | int in_shared; | |
252b5132 | 16707 | |
6478892d TS |
16708 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16709 | .cpload is ignored. */ | |
16710 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16711 | { |
16712 | s_ignore (0); | |
16713 | return; | |
16714 | } | |
16715 | ||
a276b80c MR |
16716 | if (mips_opts.mips16) |
16717 | { | |
16718 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16719 | ignore_rest_of_line (); | |
16720 | return; | |
16721 | } | |
16722 | ||
d3ecfc59 | 16723 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16724 | if (mips_opts.noreorder == 0) |
16725 | as_warn (_(".cpload not in noreorder section")); | |
16726 | ||
aa6975fb ILT |
16727 | reg = tc_get_register (0); |
16728 | ||
16729 | /* If we need to produce a 64-bit address, we are better off using | |
16730 | the default instruction sequence. */ | |
aed1a261 | 16731 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16732 | |
252b5132 | 16733 | ex.X_op = O_symbol; |
bbe506e8 TS |
16734 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16735 | "__gnu_local_gp"); | |
252b5132 RH |
16736 | ex.X_op_symbol = NULL; |
16737 | ex.X_add_number = 0; | |
16738 | ||
16739 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16740 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16741 | |
8a75745d MR |
16742 | mips_mark_labels (); |
16743 | mips_assembling_insn = TRUE; | |
16744 | ||
584892a6 | 16745 | macro_start (); |
67c0d1eb RS |
16746 | macro_build_lui (&ex, mips_gp_register); |
16747 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16748 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16749 | if (in_shared) |
16750 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16751 | mips_gp_register, reg); | |
584892a6 | 16752 | macro_end (); |
252b5132 | 16753 | |
8a75745d | 16754 | mips_assembling_insn = FALSE; |
252b5132 RH |
16755 | demand_empty_rest_of_line (); |
16756 | } | |
16757 | ||
6478892d TS |
16758 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16759 | .cpsetup $reg1, offset|$reg2, label | |
16760 | ||
16761 | If offset is given, this results in: | |
16762 | sd $gp, offset($sp) | |
956cd1d6 | 16763 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16764 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16765 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16766 | |
16767 | If $reg2 is given, this results in: | |
16768 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16769 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16770 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16771 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16772 | $reg1 is normally $25 == $t9. |
16773 | ||
16774 | The -mno-shared option replaces the last three instructions with | |
16775 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16776 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16777 | |
6478892d | 16778 | static void |
17a2f251 | 16779 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16780 | { |
16781 | expressionS ex_off; | |
16782 | expressionS ex_sym; | |
16783 | int reg1; | |
6478892d | 16784 | |
8586fc66 | 16785 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16786 | We also need NewABI support. */ |
16787 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16788 | { | |
16789 | s_ignore (0); | |
16790 | return; | |
16791 | } | |
16792 | ||
a276b80c MR |
16793 | if (mips_opts.mips16) |
16794 | { | |
16795 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16796 | ignore_rest_of_line (); | |
16797 | return; | |
16798 | } | |
16799 | ||
6478892d TS |
16800 | reg1 = tc_get_register (0); |
16801 | SKIP_WHITESPACE (); | |
16802 | if (*input_line_pointer != ',') | |
16803 | { | |
16804 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16805 | return; | |
16806 | } | |
16807 | else | |
80245285 | 16808 | ++input_line_pointer; |
6478892d TS |
16809 | SKIP_WHITESPACE (); |
16810 | if (*input_line_pointer == '$') | |
80245285 TS |
16811 | { |
16812 | mips_cpreturn_register = tc_get_register (0); | |
16813 | mips_cpreturn_offset = -1; | |
16814 | } | |
6478892d | 16815 | else |
80245285 TS |
16816 | { |
16817 | mips_cpreturn_offset = get_absolute_expression (); | |
16818 | mips_cpreturn_register = -1; | |
16819 | } | |
6478892d TS |
16820 | SKIP_WHITESPACE (); |
16821 | if (*input_line_pointer != ',') | |
16822 | { | |
16823 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16824 | return; | |
16825 | } | |
16826 | else | |
f9419b05 | 16827 | ++input_line_pointer; |
6478892d | 16828 | SKIP_WHITESPACE (); |
f21f8242 | 16829 | expression (&ex_sym); |
6478892d | 16830 | |
8a75745d MR |
16831 | mips_mark_labels (); |
16832 | mips_assembling_insn = TRUE; | |
16833 | ||
584892a6 | 16834 | macro_start (); |
6478892d TS |
16835 | if (mips_cpreturn_register == -1) |
16836 | { | |
16837 | ex_off.X_op = O_constant; | |
16838 | ex_off.X_add_symbol = NULL; | |
16839 | ex_off.X_op_symbol = NULL; | |
16840 | ex_off.X_add_number = mips_cpreturn_offset; | |
16841 | ||
67c0d1eb | 16842 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16843 | BFD_RELOC_LO16, SP); |
6478892d TS |
16844 | } |
16845 | else | |
67c0d1eb | 16846 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16847 | mips_gp_register, 0); |
6478892d | 16848 | |
aed1a261 | 16849 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16850 | { |
df58fc94 | 16851 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16852 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16853 | BFD_RELOC_HI16_S); | |
16854 | ||
16855 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16856 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16857 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16858 | ||
16859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16860 | mips_gp_register, reg1); | |
16861 | } | |
16862 | else | |
16863 | { | |
16864 | expressionS ex; | |
16865 | ||
16866 | ex.X_op = O_symbol; | |
4184909a | 16867 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16868 | ex.X_op_symbol = NULL; |
16869 | ex.X_add_number = 0; | |
6e1304d8 | 16870 | |
aa6975fb ILT |
16871 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16872 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16873 | ||
16874 | macro_build_lui (&ex, mips_gp_register); | |
16875 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16876 | mips_gp_register, BFD_RELOC_LO16); | |
16877 | } | |
f21f8242 | 16878 | |
584892a6 | 16879 | macro_end (); |
6478892d | 16880 | |
8a75745d | 16881 | mips_assembling_insn = FALSE; |
6478892d TS |
16882 | demand_empty_rest_of_line (); |
16883 | } | |
16884 | ||
16885 | static void | |
17a2f251 | 16886 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16887 | { |
16888 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16889 | .cplocal is ignored. */ |
6478892d TS |
16890 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16891 | { | |
16892 | s_ignore (0); | |
16893 | return; | |
16894 | } | |
16895 | ||
a276b80c MR |
16896 | if (mips_opts.mips16) |
16897 | { | |
16898 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16899 | ignore_rest_of_line (); | |
16900 | return; | |
16901 | } | |
16902 | ||
6478892d | 16903 | mips_gp_register = tc_get_register (0); |
85b51719 | 16904 | demand_empty_rest_of_line (); |
6478892d TS |
16905 | } |
16906 | ||
252b5132 RH |
16907 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16908 | offset from $sp. The offset is remembered, and after making a PIC | |
16909 | call $gp is restored from that location. */ | |
16910 | ||
16911 | static void | |
17a2f251 | 16912 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16913 | { |
16914 | expressionS ex; | |
252b5132 | 16915 | |
6478892d | 16916 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16917 | .cprestore is ignored. */ |
6478892d | 16918 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16919 | { |
16920 | s_ignore (0); | |
16921 | return; | |
16922 | } | |
16923 | ||
a276b80c MR |
16924 | if (mips_opts.mips16) |
16925 | { | |
16926 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16927 | ignore_rest_of_line (); | |
16928 | return; | |
16929 | } | |
16930 | ||
252b5132 | 16931 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16932 | mips_cprestore_valid = 1; |
252b5132 RH |
16933 | |
16934 | ex.X_op = O_constant; | |
16935 | ex.X_add_symbol = NULL; | |
16936 | ex.X_op_symbol = NULL; | |
16937 | ex.X_add_number = mips_cprestore_offset; | |
16938 | ||
8a75745d MR |
16939 | mips_mark_labels (); |
16940 | mips_assembling_insn = TRUE; | |
16941 | ||
584892a6 | 16942 | macro_start (); |
67c0d1eb RS |
16943 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16944 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16945 | macro_end (); |
252b5132 | 16946 | |
8a75745d | 16947 | mips_assembling_insn = FALSE; |
252b5132 RH |
16948 | demand_empty_rest_of_line (); |
16949 | } | |
16950 | ||
6478892d | 16951 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16952 | was given in the preceding .cpsetup, it results in: |
6478892d | 16953 | ld $gp, offset($sp) |
76b3015f | 16954 | |
6478892d | 16955 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16956 | daddu $gp, $reg2, $0 */ |
16957 | ||
6478892d | 16958 | static void |
17a2f251 | 16959 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16960 | { |
16961 | expressionS ex; | |
6478892d TS |
16962 | |
16963 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16964 | We also need NewABI support. */ | |
16965 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16966 | { | |
16967 | s_ignore (0); | |
16968 | return; | |
16969 | } | |
16970 | ||
a276b80c MR |
16971 | if (mips_opts.mips16) |
16972 | { | |
16973 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16974 | ignore_rest_of_line (); | |
16975 | return; | |
16976 | } | |
16977 | ||
8a75745d MR |
16978 | mips_mark_labels (); |
16979 | mips_assembling_insn = TRUE; | |
16980 | ||
584892a6 | 16981 | macro_start (); |
6478892d TS |
16982 | if (mips_cpreturn_register == -1) |
16983 | { | |
16984 | ex.X_op = O_constant; | |
16985 | ex.X_add_symbol = NULL; | |
16986 | ex.X_op_symbol = NULL; | |
16987 | ex.X_add_number = mips_cpreturn_offset; | |
16988 | ||
67c0d1eb | 16989 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16990 | } |
16991 | else | |
67c0d1eb | 16992 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16993 | mips_cpreturn_register, 0); |
584892a6 | 16994 | macro_end (); |
6478892d | 16995 | |
8a75745d | 16996 | mips_assembling_insn = FALSE; |
6478892d TS |
16997 | demand_empty_rest_of_line (); |
16998 | } | |
16999 | ||
d0f13682 CLT |
17000 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17001 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17002 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17003 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17004 | |
17005 | static void | |
d0f13682 CLT |
17006 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17007 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17008 | { |
17009 | expressionS ex; | |
17010 | char *p; | |
17011 | ||
17012 | expression (&ex); | |
17013 | ||
17014 | if (ex.X_op != O_symbol) | |
17015 | { | |
d0f13682 | 17016 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17017 | ignore_rest_of_line (); |
17018 | } | |
17019 | ||
17020 | p = frag_more (bytes); | |
17021 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17022 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17023 | demand_empty_rest_of_line (); |
de64cffd | 17024 | mips_clear_insn_labels (); |
741d6ea8 JM |
17025 | } |
17026 | ||
17027 | /* Handle .dtprelword. */ | |
17028 | ||
17029 | static void | |
17030 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17031 | { | |
d0f13682 | 17032 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17033 | } |
17034 | ||
17035 | /* Handle .dtpreldword. */ | |
17036 | ||
17037 | static void | |
17038 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17039 | { | |
d0f13682 CLT |
17040 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17041 | } | |
17042 | ||
17043 | /* Handle .tprelword. */ | |
17044 | ||
17045 | static void | |
17046 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17047 | { | |
17048 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17049 | } | |
17050 | ||
17051 | /* Handle .tpreldword. */ | |
17052 | ||
17053 | static void | |
17054 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17055 | { | |
17056 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17057 | } |
17058 | ||
6478892d TS |
17059 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17060 | code. It sets the offset to use in gp_rel relocations. */ | |
17061 | ||
17062 | static void | |
17a2f251 | 17063 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17064 | { |
17065 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17066 | We also need NewABI support. */ | |
17067 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17068 | { | |
17069 | s_ignore (0); | |
17070 | return; | |
17071 | } | |
17072 | ||
def2e0dd | 17073 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17074 | |
17075 | demand_empty_rest_of_line (); | |
17076 | } | |
17077 | ||
252b5132 RH |
17078 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17079 | code. It generates a 32 bit GP relative reloc. */ | |
17080 | ||
17081 | static void | |
17a2f251 | 17082 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17083 | { |
a8dbcb85 TS |
17084 | segment_info_type *si; |
17085 | struct insn_label_list *l; | |
252b5132 RH |
17086 | expressionS ex; |
17087 | char *p; | |
17088 | ||
17089 | /* When not generating PIC code, this is treated as .word. */ | |
17090 | if (mips_pic != SVR4_PIC) | |
17091 | { | |
17092 | s_cons (2); | |
17093 | return; | |
17094 | } | |
17095 | ||
a8dbcb85 TS |
17096 | si = seg_info (now_seg); |
17097 | l = si->label_list; | |
7d10b47d | 17098 | mips_emit_delays (); |
252b5132 | 17099 | if (auto_align) |
462427c4 | 17100 | mips_align (2, 0, l); |
252b5132 RH |
17101 | |
17102 | expression (&ex); | |
a1facbec | 17103 | mips_clear_insn_labels (); |
252b5132 RH |
17104 | |
17105 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17106 | { | |
17107 | as_bad (_("Unsupported use of .gpword")); | |
17108 | ignore_rest_of_line (); | |
17109 | } | |
17110 | ||
17111 | p = frag_more (4); | |
17a2f251 | 17112 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17113 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17114 | BFD_RELOC_GPREL32); |
252b5132 RH |
17115 | |
17116 | demand_empty_rest_of_line (); | |
17117 | } | |
17118 | ||
10181a0d | 17119 | static void |
17a2f251 | 17120 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17121 | { |
a8dbcb85 TS |
17122 | segment_info_type *si; |
17123 | struct insn_label_list *l; | |
10181a0d AO |
17124 | expressionS ex; |
17125 | char *p; | |
17126 | ||
17127 | /* When not generating PIC code, this is treated as .dword. */ | |
17128 | if (mips_pic != SVR4_PIC) | |
17129 | { | |
17130 | s_cons (3); | |
17131 | return; | |
17132 | } | |
17133 | ||
a8dbcb85 TS |
17134 | si = seg_info (now_seg); |
17135 | l = si->label_list; | |
7d10b47d | 17136 | mips_emit_delays (); |
10181a0d | 17137 | if (auto_align) |
462427c4 | 17138 | mips_align (3, 0, l); |
10181a0d AO |
17139 | |
17140 | expression (&ex); | |
a1facbec | 17141 | mips_clear_insn_labels (); |
10181a0d AO |
17142 | |
17143 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17144 | { | |
17145 | as_bad (_("Unsupported use of .gpdword")); | |
17146 | ignore_rest_of_line (); | |
17147 | } | |
17148 | ||
17149 | p = frag_more (8); | |
17a2f251 | 17150 | md_number_to_chars (p, 0, 8); |
a105a300 | 17151 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17152 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17153 | |
17154 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17155 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17156 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17157 | |
17158 | demand_empty_rest_of_line (); | |
17159 | } | |
17160 | ||
a3f278e2 CM |
17161 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17162 | tables. It generates a R_MIPS_EH reloc. */ | |
17163 | ||
17164 | static void | |
17165 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17166 | { | |
17167 | expressionS ex; | |
17168 | char *p; | |
17169 | ||
17170 | mips_emit_delays (); | |
17171 | ||
17172 | expression (&ex); | |
17173 | mips_clear_insn_labels (); | |
17174 | ||
17175 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17176 | { | |
17177 | as_bad (_("Unsupported use of .ehword")); | |
17178 | ignore_rest_of_line (); | |
17179 | } | |
17180 | ||
17181 | p = frag_more (4); | |
17182 | md_number_to_chars (p, 0, 4); | |
17183 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17184 | BFD_RELOC_MIPS_EH); | |
17185 | ||
17186 | demand_empty_rest_of_line (); | |
17187 | } | |
17188 | ||
252b5132 RH |
17189 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17190 | tables in SVR4 PIC code. */ | |
17191 | ||
17192 | static void | |
17a2f251 | 17193 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17194 | { |
252b5132 RH |
17195 | int reg; |
17196 | ||
10181a0d AO |
17197 | /* This is ignored when not generating SVR4 PIC code. */ |
17198 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17199 | { |
17200 | s_ignore (0); | |
17201 | return; | |
17202 | } | |
17203 | ||
8a75745d MR |
17204 | mips_mark_labels (); |
17205 | mips_assembling_insn = TRUE; | |
17206 | ||
252b5132 | 17207 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17208 | macro_start (); |
252b5132 | 17209 | reg = tc_get_register (0); |
67c0d1eb | 17210 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17211 | macro_end (); |
252b5132 | 17212 | |
8a75745d | 17213 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17214 | demand_empty_rest_of_line (); |
252b5132 RH |
17215 | } |
17216 | ||
17217 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17218 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17219 | such as generating jalx instructions when needed. We also make |
17220 | them odd for the duration of the assembly, in order to generate the | |
17221 | right sort of code. We will make them even in the adjust_symtab | |
17222 | routine, while leaving them marked. This is convenient for the | |
17223 | debugger and the disassembler. The linker knows to make them odd | |
17224 | again. */ | |
17225 | ||
17226 | static void | |
17a2f251 | 17227 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17228 | { |
df58fc94 | 17229 | mips_mark_labels (); |
252b5132 RH |
17230 | |
17231 | demand_empty_rest_of_line (); | |
17232 | } | |
17233 | ||
754e2bb9 RS |
17234 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17235 | implemented in a transparent way, so that removing them would not | |
17236 | have any effect on the generated instructions. However, s_stab | |
17237 | internally changes the section, so in practice we need to decide | |
17238 | now whether the preceding label marks compressed code. We do not | |
17239 | support changing the compression mode of a label after a .stab* | |
17240 | directive, such as in: | |
17241 | ||
17242 | foo: | |
17243 | .stabs ... | |
17244 | .set mips16 | |
17245 | ||
17246 | so the current mode wins. */ | |
252b5132 RH |
17247 | |
17248 | static void | |
17a2f251 | 17249 | s_mips_stab (int type) |
252b5132 | 17250 | { |
754e2bb9 | 17251 | mips_mark_labels (); |
252b5132 RH |
17252 | s_stab (type); |
17253 | } | |
17254 | ||
54f4ddb3 | 17255 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17256 | |
17257 | static void | |
17a2f251 | 17258 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17259 | { |
17260 | char *name; | |
17261 | int c; | |
17262 | symbolS *symbolP; | |
17263 | expressionS exp; | |
17264 | ||
17265 | name = input_line_pointer; | |
17266 | c = get_symbol_end (); | |
17267 | symbolP = symbol_find_or_make (name); | |
17268 | S_SET_WEAK (symbolP); | |
17269 | *input_line_pointer = c; | |
17270 | ||
17271 | SKIP_WHITESPACE (); | |
17272 | ||
17273 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17274 | { | |
17275 | if (S_IS_DEFINED (symbolP)) | |
17276 | { | |
20203fb9 | 17277 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17278 | S_GET_NAME (symbolP)); |
17279 | ignore_rest_of_line (); | |
17280 | return; | |
17281 | } | |
bdaaa2e1 | 17282 | |
252b5132 RH |
17283 | if (*input_line_pointer == ',') |
17284 | { | |
17285 | ++input_line_pointer; | |
17286 | SKIP_WHITESPACE (); | |
17287 | } | |
bdaaa2e1 | 17288 | |
252b5132 RH |
17289 | expression (&exp); |
17290 | if (exp.X_op != O_symbol) | |
17291 | { | |
20203fb9 | 17292 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17293 | ignore_rest_of_line (); |
252b5132 RH |
17294 | return; |
17295 | } | |
49309057 | 17296 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17297 | } |
17298 | ||
17299 | demand_empty_rest_of_line (); | |
17300 | } | |
17301 | ||
17302 | /* Parse a register string into a number. Called from the ECOFF code | |
17303 | to parse .frame. The argument is non-zero if this is the frame | |
17304 | register, so that we can record it in mips_frame_reg. */ | |
17305 | ||
17306 | int | |
17a2f251 | 17307 | tc_get_register (int frame) |
252b5132 | 17308 | { |
707bfff6 | 17309 | unsigned int reg; |
252b5132 RH |
17310 | |
17311 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17312 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17313 | reg = 0; | |
252b5132 | 17314 | if (frame) |
7a621144 DJ |
17315 | { |
17316 | mips_frame_reg = reg != 0 ? reg : SP; | |
17317 | mips_frame_reg_valid = 1; | |
17318 | mips_cprestore_valid = 0; | |
17319 | } | |
252b5132 RH |
17320 | return reg; |
17321 | } | |
17322 | ||
17323 | valueT | |
17a2f251 | 17324 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17325 | { |
17326 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17327 | ||
b4c71f56 TS |
17328 | if (IS_ELF) |
17329 | { | |
17330 | /* We don't need to align ELF sections to the full alignment. | |
17331 | However, Irix 5 may prefer that we align them at least to a 16 | |
17332 | byte boundary. We don't bother to align the sections if we | |
17333 | are targeted for an embedded system. */ | |
c41e87e3 | 17334 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17335 | return addr; |
17336 | if (align > 4) | |
17337 | align = 4; | |
17338 | } | |
252b5132 RH |
17339 | |
17340 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17341 | } | |
17342 | ||
17343 | /* Utility routine, called from above as well. If called while the | |
17344 | input file is still being read, it's only an approximation. (For | |
17345 | example, a symbol may later become defined which appeared to be | |
17346 | undefined earlier.) */ | |
17347 | ||
17348 | static int | |
17a2f251 | 17349 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17350 | { |
17351 | if (sym == 0) | |
17352 | return 0; | |
17353 | ||
4d0d148d | 17354 | if (g_switch_value > 0) |
252b5132 RH |
17355 | { |
17356 | const char *symname; | |
17357 | int change; | |
17358 | ||
c9914766 | 17359 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17360 | register. It can be if it is smaller than the -G size or if |
17361 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17362 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17363 | they can. */ |
17364 | symname = S_GET_NAME (sym); | |
17365 | if (symname != (const char *) NULL | |
17366 | && (strcmp (symname, "eprol") == 0 | |
17367 | || strcmp (symname, "etext") == 0 | |
17368 | || strcmp (symname, "_gp") == 0 | |
17369 | || strcmp (symname, "edata") == 0 | |
17370 | || strcmp (symname, "_fbss") == 0 | |
17371 | || strcmp (symname, "_fdata") == 0 | |
17372 | || strcmp (symname, "_ftext") == 0 | |
17373 | || strcmp (symname, "end") == 0 | |
17374 | || strcmp (symname, "_gp_disp") == 0)) | |
17375 | change = 1; | |
17376 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17377 | && (0 | |
17378 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17379 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17380 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17381 | <= g_switch_value)) | |
252b5132 RH |
17382 | #endif |
17383 | /* We must defer this decision until after the whole | |
17384 | file has been read, since there might be a .extern | |
17385 | after the first use of this symbol. */ | |
17386 | || (before_relaxing | |
17387 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17388 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17389 | #endif |
17390 | && S_GET_VALUE (sym) == 0) | |
17391 | || (S_GET_VALUE (sym) != 0 | |
17392 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17393 | change = 0; | |
17394 | else | |
17395 | { | |
17396 | const char *segname; | |
17397 | ||
17398 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17399 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17400 | && strcmp (segname, ".lit4") != 0); |
17401 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17402 | && strcmp (segname, ".sbss") != 0 |
17403 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17404 | && strncmp (segname, ".sbss.", 6) != 0 |
17405 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17406 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17407 | } |
17408 | return change; | |
17409 | } | |
17410 | else | |
c9914766 | 17411 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17412 | return 1; |
17413 | } | |
17414 | ||
5919d012 RS |
17415 | |
17416 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17417 | ||
17418 | static bfd_boolean | |
17a2f251 | 17419 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17420 | { |
17421 | asection *symsec; | |
5919d012 RS |
17422 | |
17423 | /* Handle the case of a symbol equated to another symbol. */ | |
17424 | while (symbol_equated_reloc_p (sym)) | |
17425 | { | |
17426 | symbolS *n; | |
17427 | ||
5f0fe04b | 17428 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17429 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17430 | if (n == sym) | |
17431 | break; | |
17432 | sym = n; | |
17433 | } | |
17434 | ||
df1f3cda DD |
17435 | if (symbol_section_p (sym)) |
17436 | return TRUE; | |
17437 | ||
5919d012 RS |
17438 | symsec = S_GET_SEGMENT (sym); |
17439 | ||
5919d012 | 17440 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17441 | return (!bfd_is_und_section (symsec) |
17442 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17443 | && !bfd_is_com_section (symsec) |
17444 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17445 | #ifdef OBJ_ELF |
17446 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17447 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17448 | #endif |
17449 | ); | |
17450 | } | |
17451 | ||
17452 | ||
252b5132 RH |
17453 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17454 | extended opcode. SEC is the section the frag is in. */ | |
17455 | ||
17456 | static int | |
17a2f251 | 17457 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17458 | { |
17459 | int type; | |
3994f87e | 17460 | const struct mips16_immed_operand *op; |
252b5132 RH |
17461 | offsetT val; |
17462 | int mintiny, maxtiny; | |
17463 | segT symsec; | |
98aa84af | 17464 | fragS *sym_frag; |
252b5132 RH |
17465 | |
17466 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17467 | return 0; | |
17468 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17469 | return 1; | |
17470 | ||
17471 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17472 | op = mips16_immed_operands; | |
17473 | while (op->type != type) | |
17474 | { | |
17475 | ++op; | |
9c2799c2 | 17476 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17477 | } |
17478 | ||
17479 | if (op->unsp) | |
17480 | { | |
17481 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17482 | { | |
17483 | mintiny = 1; | |
17484 | maxtiny = 1 << op->nbits; | |
17485 | } | |
17486 | else | |
17487 | { | |
17488 | mintiny = 0; | |
17489 | maxtiny = (1 << op->nbits) - 1; | |
17490 | } | |
17491 | } | |
17492 | else | |
17493 | { | |
17494 | mintiny = - (1 << (op->nbits - 1)); | |
17495 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17496 | } | |
17497 | ||
98aa84af | 17498 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17499 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17500 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17501 | |
17502 | if (op->pcrel) | |
17503 | { | |
17504 | addressT addr; | |
17505 | ||
17506 | /* We won't have the section when we are called from | |
17507 | mips_relax_frag. However, we will always have been called | |
17508 | from md_estimate_size_before_relax first. If this is a | |
17509 | branch to a different section, we mark it as such. If SEC is | |
17510 | NULL, and the frag is not marked, then it must be a branch to | |
17511 | the same section. */ | |
17512 | if (sec == NULL) | |
17513 | { | |
17514 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17515 | return 1; | |
17516 | } | |
17517 | else | |
17518 | { | |
98aa84af | 17519 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17520 | if (symsec != sec) |
17521 | { | |
17522 | fragp->fr_subtype = | |
17523 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17524 | ||
17525 | /* FIXME: We should support this, and let the linker | |
17526 | catch branches and loads that are out of range. */ | |
17527 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17528 | _("unsupported PC relative reference to different section")); | |
17529 | ||
17530 | return 1; | |
17531 | } | |
98aa84af AM |
17532 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17533 | /* Assume non-extended on the first relaxation pass. | |
17534 | The address we have calculated will be bogus if this is | |
17535 | a forward branch to another frag, as the forward frag | |
17536 | will have fr_address == 0. */ | |
17537 | return 0; | |
252b5132 RH |
17538 | } |
17539 | ||
17540 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17541 | the same section. If the relax_marker of the symbol fragment |
17542 | differs from the relax_marker of this fragment, we have not | |
17543 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17544 | in STRETCH in order to get a better estimate of the address. |
17545 | This particularly matters because of the shift bits. */ | |
17546 | if (stretch != 0 | |
98aa84af | 17547 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17548 | { |
17549 | fragS *f; | |
17550 | ||
17551 | /* Adjust stretch for any alignment frag. Note that if have | |
17552 | been expanding the earlier code, the symbol may be | |
17553 | defined in what appears to be an earlier frag. FIXME: | |
17554 | This doesn't handle the fr_subtype field, which specifies | |
17555 | a maximum number of bytes to skip when doing an | |
17556 | alignment. */ | |
98aa84af | 17557 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17558 | { |
17559 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17560 | { | |
17561 | if (stretch < 0) | |
17562 | stretch = - ((- stretch) | |
17563 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17564 | else | |
17565 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17566 | if (stretch == 0) | |
17567 | break; | |
17568 | } | |
17569 | } | |
17570 | if (f != NULL) | |
17571 | val += stretch; | |
17572 | } | |
17573 | ||
17574 | addr = fragp->fr_address + fragp->fr_fix; | |
17575 | ||
17576 | /* The base address rules are complicated. The base address of | |
17577 | a branch is the following instruction. The base address of a | |
17578 | PC relative load or add is the instruction itself, but if it | |
17579 | is in a delay slot (in which case it can not be extended) use | |
17580 | the address of the instruction whose delay slot it is in. */ | |
17581 | if (type == 'p' || type == 'q') | |
17582 | { | |
17583 | addr += 2; | |
17584 | ||
17585 | /* If we are currently assuming that this frag should be | |
17586 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17587 | higher. */ |
252b5132 RH |
17588 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17589 | addr += 2; | |
17590 | ||
17591 | /* Ignore the low bit in the target, since it will be set | |
17592 | for a text label. */ | |
17593 | if ((val & 1) != 0) | |
17594 | --val; | |
17595 | } | |
17596 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17597 | addr -= 4; | |
17598 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17599 | addr -= 2; | |
17600 | ||
17601 | val -= addr & ~ ((1 << op->shift) - 1); | |
17602 | ||
17603 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17604 | if (type == 'p' || type == 'q') | |
17605 | val /= 2; | |
17606 | ||
17607 | /* If any of the shifted bits are set, we must use an extended | |
17608 | opcode. If the address depends on the size of this | |
17609 | instruction, this can lead to a loop, so we arrange to always | |
17610 | use an extended opcode. We only check this when we are in | |
17611 | the main relaxation loop, when SEC is NULL. */ | |
17612 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17613 | { | |
17614 | fragp->fr_subtype = | |
17615 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17616 | return 1; | |
17617 | } | |
17618 | ||
17619 | /* If we are about to mark a frag as extended because the value | |
17620 | is precisely maxtiny + 1, then there is a chance of an | |
17621 | infinite loop as in the following code: | |
17622 | la $4,foo | |
17623 | .skip 1020 | |
17624 | .align 2 | |
17625 | foo: | |
17626 | In this case when the la is extended, foo is 0x3fc bytes | |
17627 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17628 | the la must be extended. To avoid this loop, we mark the | |
17629 | frag as extended if it was small, and is about to become | |
17630 | extended with a value of maxtiny + 1. */ | |
17631 | if (val == ((maxtiny + 1) << op->shift) | |
17632 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17633 | && sec == NULL) | |
17634 | { | |
17635 | fragp->fr_subtype = | |
17636 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17637 | return 1; | |
17638 | } | |
17639 | } | |
17640 | else if (symsec != absolute_section && sec != NULL) | |
17641 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17642 | ||
17643 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17644 | || val < (mintiny << op->shift) | |
17645 | || val > (maxtiny << op->shift)) | |
17646 | return 1; | |
17647 | else | |
17648 | return 0; | |
17649 | } | |
17650 | ||
4a6a3df4 AO |
17651 | /* Compute the length of a branch sequence, and adjust the |
17652 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17653 | worst-case length is computed, with UPDATE being used to indicate | |
17654 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17655 | branch is to be computed. */ | |
17656 | static int | |
17a2f251 | 17657 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17658 | { |
b34976b6 | 17659 | bfd_boolean toofar; |
4a6a3df4 AO |
17660 | int length; |
17661 | ||
17662 | if (fragp | |
17663 | && S_IS_DEFINED (fragp->fr_symbol) | |
17664 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17665 | { | |
17666 | addressT addr; | |
17667 | offsetT val; | |
17668 | ||
17669 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17670 | ||
17671 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17672 | ||
17673 | val -= addr; | |
17674 | ||
17675 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17676 | } | |
17677 | else if (fragp) | |
17678 | /* If the symbol is not defined or it's in a different segment, | |
17679 | assume the user knows what's going on and emit a short | |
17680 | branch. */ | |
b34976b6 | 17681 | toofar = FALSE; |
4a6a3df4 | 17682 | else |
b34976b6 | 17683 | toofar = TRUE; |
4a6a3df4 AO |
17684 | |
17685 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17686 | fragp->fr_subtype | |
66b3e8da MR |
17687 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17688 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17689 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17690 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17691 | toofar); | |
17692 | ||
17693 | length = 4; | |
17694 | if (toofar) | |
17695 | { | |
17696 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17697 | length += 8; | |
17698 | ||
17699 | if (mips_pic != NO_PIC) | |
17700 | { | |
17701 | /* Additional space for PIC loading of target address. */ | |
17702 | length += 8; | |
17703 | if (mips_opts.isa == ISA_MIPS1) | |
17704 | /* Additional space for $at-stabilizing nop. */ | |
17705 | length += 4; | |
17706 | } | |
17707 | ||
17708 | /* If branch is conditional. */ | |
17709 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17710 | length += 8; | |
17711 | } | |
b34976b6 | 17712 | |
4a6a3df4 AO |
17713 | return length; |
17714 | } | |
17715 | ||
df58fc94 RS |
17716 | /* Compute the length of a branch sequence, and adjust the |
17717 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17718 | worst-case length is computed, with UPDATE being used to indicate | |
17719 | whether an unconditional (-1), or regular (0) branch is to be | |
17720 | computed. */ | |
17721 | ||
17722 | static int | |
17723 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17724 | { | |
17725 | bfd_boolean toofar; | |
17726 | int length; | |
17727 | ||
17728 | if (fragp | |
17729 | && S_IS_DEFINED (fragp->fr_symbol) | |
17730 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17731 | { | |
17732 | addressT addr; | |
17733 | offsetT val; | |
17734 | ||
17735 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17736 | /* Ignore the low bit in the target, since it will be set | |
17737 | for a text label. */ | |
17738 | if ((val & 1) != 0) | |
17739 | --val; | |
17740 | ||
17741 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17742 | ||
17743 | val -= addr; | |
17744 | ||
17745 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17746 | } | |
17747 | else if (fragp) | |
17748 | /* If the symbol is not defined or it's in a different segment, | |
17749 | assume the user knows what's going on and emit a short | |
17750 | branch. */ | |
17751 | toofar = FALSE; | |
17752 | else | |
17753 | toofar = TRUE; | |
17754 | ||
17755 | if (fragp && update | |
17756 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17757 | fragp->fr_subtype = (toofar | |
17758 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17759 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17760 | ||
17761 | length = 4; | |
17762 | if (toofar) | |
17763 | { | |
17764 | bfd_boolean compact_known = fragp != NULL; | |
17765 | bfd_boolean compact = FALSE; | |
17766 | bfd_boolean uncond; | |
17767 | ||
17768 | if (compact_known) | |
17769 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17770 | if (fragp) | |
17771 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17772 | else | |
17773 | uncond = update < 0; | |
17774 | ||
17775 | /* If label is out of range, we turn branch <br>: | |
17776 | ||
17777 | <br> label # 4 bytes | |
17778 | 0: | |
17779 | ||
17780 | into: | |
17781 | ||
17782 | j label # 4 bytes | |
17783 | nop # 2 bytes if compact && !PIC | |
17784 | 0: | |
17785 | */ | |
17786 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17787 | length += 2; | |
17788 | ||
17789 | /* If assembling PIC code, we further turn: | |
17790 | ||
17791 | j label # 4 bytes | |
17792 | ||
17793 | into: | |
17794 | ||
17795 | lw/ld at, %got(label)(gp) # 4 bytes | |
17796 | d/addiu at, %lo(label) # 4 bytes | |
17797 | jr/c at # 2 bytes | |
17798 | */ | |
17799 | if (mips_pic != NO_PIC) | |
17800 | length += 6; | |
17801 | ||
17802 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17803 | ||
17804 | <brneg> 0f # 4 bytes | |
17805 | nop # 2 bytes if !compact | |
17806 | */ | |
17807 | if (!uncond) | |
17808 | length += (compact_known && compact) ? 4 : 6; | |
17809 | } | |
17810 | ||
17811 | return length; | |
17812 | } | |
17813 | ||
17814 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17815 | bit accordingly. */ | |
17816 | ||
17817 | static int | |
17818 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17819 | { | |
17820 | bfd_boolean toofar; | |
17821 | ||
df58fc94 RS |
17822 | if (fragp |
17823 | && S_IS_DEFINED (fragp->fr_symbol) | |
17824 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17825 | { | |
17826 | addressT addr; | |
17827 | offsetT val; | |
17828 | int type; | |
17829 | ||
17830 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17831 | /* Ignore the low bit in the target, since it will be set | |
17832 | for a text label. */ | |
17833 | if ((val & 1) != 0) | |
17834 | --val; | |
17835 | ||
17836 | /* Assume this is a 2-byte branch. */ | |
17837 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17838 | ||
17839 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17840 | long branches. */ | |
17841 | ||
17842 | val -= addr; | |
17843 | ||
17844 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17845 | if (type == 'D') | |
17846 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17847 | else if (type == 'E') | |
17848 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17849 | else | |
17850 | abort (); | |
17851 | } | |
17852 | else | |
17853 | /* If the symbol is not defined or it's in a different segment, | |
17854 | we emit a normal 32-bit branch. */ | |
17855 | toofar = TRUE; | |
17856 | ||
17857 | if (fragp && update | |
17858 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17859 | fragp->fr_subtype | |
17860 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17861 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17862 | ||
17863 | if (toofar) | |
17864 | return 4; | |
17865 | ||
17866 | return 2; | |
17867 | } | |
17868 | ||
252b5132 RH |
17869 | /* Estimate the size of a frag before relaxing. Unless this is the |
17870 | mips16, we are not really relaxing here, and the final size is | |
17871 | encoded in the subtype information. For the mips16, we have to | |
17872 | decide whether we are using an extended opcode or not. */ | |
17873 | ||
252b5132 | 17874 | int |
17a2f251 | 17875 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17876 | { |
5919d012 | 17877 | int change; |
252b5132 | 17878 | |
4a6a3df4 AO |
17879 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17880 | { | |
17881 | ||
b34976b6 AM |
17882 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17883 | ||
4a6a3df4 AO |
17884 | return fragp->fr_var; |
17885 | } | |
17886 | ||
252b5132 | 17887 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17888 | /* We don't want to modify the EXTENDED bit here; it might get us |
17889 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17890 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17891 | |
df58fc94 RS |
17892 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17893 | { | |
17894 | int length = 4; | |
17895 | ||
17896 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17897 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17898 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17899 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17900 | fragp->fr_var = length; | |
17901 | ||
17902 | return length; | |
17903 | } | |
17904 | ||
252b5132 | 17905 | if (mips_pic == NO_PIC) |
5919d012 | 17906 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17907 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17908 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17909 | else if (mips_pic == VXWORKS_PIC) |
17910 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17911 | change = 0; | |
252b5132 RH |
17912 | else |
17913 | abort (); | |
17914 | ||
17915 | if (change) | |
17916 | { | |
4d7206a2 | 17917 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17918 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17919 | } |
4d7206a2 RS |
17920 | else |
17921 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17922 | } |
17923 | ||
17924 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17925 | should be converted into a reloc against a section. */ |
252b5132 RH |
17926 | |
17927 | int | |
17a2f251 | 17928 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17929 | { |
252b5132 RH |
17930 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17931 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17932 | return 0; | |
a161fe53 | 17933 | |
252b5132 RH |
17934 | if (fixp->fx_addsy == NULL) |
17935 | return 1; | |
a161fe53 | 17936 | |
de7e6852 RS |
17937 | /* If symbol SYM is in a mergeable section, relocations of the form |
17938 | SYM + 0 can usually be made section-relative. The mergeable data | |
17939 | is then identified by the section offset rather than by the symbol. | |
17940 | ||
17941 | However, if we're generating REL LO16 relocations, the offset is split | |
17942 | between the LO16 and parterning high part relocation. The linker will | |
17943 | need to recalculate the complete offset in order to correctly identify | |
17944 | the merge data. | |
17945 | ||
17946 | The linker has traditionally not looked for the parterning high part | |
17947 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17948 | placed anywhere. Rather than break backwards compatibility by changing | |
17949 | this, it seems better not to force the issue, and instead keep the | |
17950 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17951 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17952 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17953 | && HAVE_IN_PLACE_ADDENDS |
17954 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17955 | return 0; | |
17956 | ||
ce70d90a | 17957 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17958 | Likewise an in-range offset of limited PC-relative relocations may |
17959 | overflow the in-place relocatable field if recalculated against the | |
17960 | start address of the symbol's containing section. */ | |
ce70d90a | 17961 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17962 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17963 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17964 | return 0; |
17965 | ||
252b5132 | 17966 | #ifdef OBJ_ELF |
b314ec0e RS |
17967 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17968 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17969 | relocations against MIPS16 functions; in this case, the stub becomes | |
17970 | the function's canonical address. | |
17971 | ||
17972 | Floating-point stubs are stored in unique .mips16.call.* or | |
17973 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17974 | the first relocation in section S must be against F; this is how the | |
17975 | linker determines the target function. All relocations that might | |
17976 | resolve to T must also be against F. We therefore have the following | |
17977 | restrictions, which are given in an intentionally-redundant way: | |
17978 | ||
17979 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17980 | symbols. | |
17981 | ||
17982 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17983 | if that stub might be used. | |
17984 | ||
17985 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17986 | symbols. | |
17987 | ||
17988 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17989 | that stub might be used. | |
17990 | ||
17991 | There is a further restriction: | |
17992 | ||
df58fc94 RS |
17993 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17994 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17995 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17996 | encode the low bit. |
17997 | ||
df58fc94 RS |
17998 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17999 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
18000 | such relocations on REL targets. | |
b314ec0e RS |
18001 | |
18002 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18003 | relocation against some symbol R, no relocation against R may be | |
18004 | reduced. (Note that this deals with (2) as well as (1) because | |
18005 | relocations against global symbols will never be reduced on ELF | |
18006 | targets.) This approach is a little simpler than trying to detect | |
18007 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18008 | that we have for MIPS16 symbols. */ | |
f43abd2b | 18009 | if (IS_ELF |
b314ec0e | 18010 | && fixp->fx_subsy == NULL |
30c09090 | 18011 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
18012 | || *symbol_get_tc (fixp->fx_addsy) |
18013 | || (HAVE_IN_PLACE_ADDENDS | |
18014 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
18015 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
18016 | return 0; |
18017 | #endif | |
a161fe53 | 18018 | |
252b5132 RH |
18019 | return 1; |
18020 | } | |
18021 | ||
18022 | /* Translate internal representation of relocation info to BFD target | |
18023 | format. */ | |
18024 | ||
18025 | arelent ** | |
17a2f251 | 18026 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18027 | { |
18028 | static arelent *retval[4]; | |
18029 | arelent *reloc; | |
18030 | bfd_reloc_code_real_type code; | |
18031 | ||
4b0cff4e TS |
18032 | memset (retval, 0, sizeof(retval)); |
18033 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18034 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18035 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18036 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18037 | ||
bad36eac DJ |
18038 | if (fixp->fx_pcrel) |
18039 | { | |
df58fc94 RS |
18040 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18041 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18042 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18043 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18044 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18045 | |
18046 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18047 | Relocations want only the symbol offset. */ | |
18048 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 18049 | if (!IS_ELF) |
bad36eac DJ |
18050 | { |
18051 | /* A gruesome hack which is a result of the gruesome gas | |
18052 | reloc handling. What's worse, for COFF (as opposed to | |
18053 | ECOFF), we might need yet another copy of reloc->address. | |
18054 | See bfd_install_relocation. */ | |
18055 | reloc->addend += reloc->address; | |
18056 | } | |
18057 | } | |
18058 | else | |
18059 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18060 | |
438c16b8 TS |
18061 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18062 | entry to be used in the relocation's section offset. */ | |
18063 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18064 | { |
18065 | reloc->address = reloc->addend; | |
18066 | reloc->addend = 0; | |
18067 | } | |
18068 | ||
252b5132 | 18069 | code = fixp->fx_r_type; |
252b5132 | 18070 | |
bad36eac | 18071 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18072 | if (reloc->howto == NULL) |
18073 | { | |
18074 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18075 | _("Can not represent %s relocation in this object file format"), | |
18076 | bfd_get_reloc_code_name (code)); | |
18077 | retval[0] = NULL; | |
18078 | } | |
18079 | ||
18080 | return retval; | |
18081 | } | |
18082 | ||
18083 | /* Relax a machine dependent frag. This returns the amount by which | |
18084 | the current size of the frag should change. */ | |
18085 | ||
18086 | int | |
17a2f251 | 18087 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18088 | { |
4a6a3df4 AO |
18089 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18090 | { | |
18091 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18092 | |
18093 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18094 | |
18095 | return fragp->fr_var - old_var; | |
18096 | } | |
18097 | ||
df58fc94 RS |
18098 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18099 | { | |
18100 | offsetT old_var = fragp->fr_var; | |
18101 | offsetT new_var = 4; | |
18102 | ||
18103 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18104 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18105 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18106 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18107 | fragp->fr_var = new_var; | |
18108 | ||
18109 | return new_var - old_var; | |
18110 | } | |
18111 | ||
252b5132 RH |
18112 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18113 | return 0; | |
18114 | ||
c4e7957c | 18115 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18116 | { |
18117 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18118 | return 0; | |
18119 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18120 | return 2; | |
18121 | } | |
18122 | else | |
18123 | { | |
18124 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18125 | return 0; | |
18126 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18127 | return -2; | |
18128 | } | |
18129 | ||
18130 | return 0; | |
18131 | } | |
18132 | ||
18133 | /* Convert a machine dependent frag. */ | |
18134 | ||
18135 | void | |
17a2f251 | 18136 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18137 | { |
4a6a3df4 AO |
18138 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18139 | { | |
4d68580a | 18140 | char *buf; |
4a6a3df4 AO |
18141 | unsigned long insn; |
18142 | expressionS exp; | |
18143 | fixS *fixp; | |
b34976b6 | 18144 | |
4d68580a RS |
18145 | buf = fragp->fr_literal + fragp->fr_fix; |
18146 | insn = read_insn (buf); | |
b34976b6 | 18147 | |
4a6a3df4 AO |
18148 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18149 | { | |
18150 | /* We generate a fixup instead of applying it right now | |
18151 | because, if there are linker relaxations, we're going to | |
18152 | need the relocations. */ | |
18153 | exp.X_op = O_symbol; | |
18154 | exp.X_add_symbol = fragp->fr_symbol; | |
18155 | exp.X_add_number = fragp->fr_offset; | |
18156 | ||
4d68580a RS |
18157 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18158 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18159 | fixp->fx_file = fragp->fr_file; |
18160 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18161 | |
4d68580a | 18162 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18163 | } |
18164 | else | |
18165 | { | |
18166 | int i; | |
18167 | ||
18168 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18169 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18170 | |
18171 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18172 | goto uncond; | |
18173 | ||
18174 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18175 | { | |
18176 | /* Reverse the branch. */ | |
18177 | switch ((insn >> 28) & 0xf) | |
18178 | { | |
18179 | case 4: | |
3bf0dbfb MR |
18180 | /* bc[0-3][tf]l? instructions can have the condition |
18181 | reversed by tweaking a single TF bit, and their | |
18182 | opcodes all have 0x4???????. */ | |
18183 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18184 | insn ^= 0x00010000; |
18185 | break; | |
18186 | ||
18187 | case 0: | |
18188 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18189 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18190 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18191 | insn ^= 0x00010000; |
18192 | break; | |
b34976b6 | 18193 | |
4a6a3df4 AO |
18194 | case 1: |
18195 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18196 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18197 | insn ^= 0x04000000; |
18198 | break; | |
18199 | ||
18200 | default: | |
18201 | abort (); | |
18202 | } | |
18203 | } | |
18204 | ||
18205 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18206 | { | |
18207 | /* Clear the and-link bit. */ | |
9c2799c2 | 18208 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18209 | |
54f4ddb3 TS |
18210 | /* bltzal 0x04100000 bgezal 0x04110000 |
18211 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18212 | insn &= ~0x00100000; |
18213 | } | |
18214 | ||
18215 | /* Branch over the branch (if the branch was likely) or the | |
18216 | full jump (not likely case). Compute the offset from the | |
18217 | current instruction to branch to. */ | |
18218 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18219 | i = 16; | |
18220 | else | |
18221 | { | |
18222 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18223 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18224 | /* How many bytes in instructions from here to the end? */ |
18225 | i = fragp->fr_var - i; | |
18226 | } | |
18227 | /* Convert to instruction count. */ | |
18228 | i >>= 2; | |
18229 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18230 | i--; |
4a6a3df4 AO |
18231 | insn |= i; |
18232 | /* Branch over the jump. */ | |
4d68580a | 18233 | buf = write_insn (buf, insn); |
4a6a3df4 | 18234 | |
54f4ddb3 | 18235 | /* nop */ |
4d68580a | 18236 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18237 | |
18238 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18239 | { | |
18240 | /* beql $0, $0, 2f */ | |
18241 | insn = 0x50000000; | |
18242 | /* Compute the PC offset from the current instruction to | |
18243 | the end of the variable frag. */ | |
18244 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18245 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18246 | /* How many bytes in instructions from here to the end? */ |
18247 | i = fragp->fr_var - i; | |
18248 | /* Convert to instruction count. */ | |
18249 | i >>= 2; | |
18250 | /* Don't decrement i, because we want to branch over the | |
18251 | delay slot. */ | |
4a6a3df4 | 18252 | insn |= i; |
4a6a3df4 | 18253 | |
4d68580a RS |
18254 | buf = write_insn (buf, insn); |
18255 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18256 | } |
18257 | ||
18258 | uncond: | |
18259 | if (mips_pic == NO_PIC) | |
18260 | { | |
18261 | /* j or jal. */ | |
18262 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18263 | ? 0x0c000000 : 0x08000000); | |
18264 | exp.X_op = O_symbol; | |
18265 | exp.X_add_symbol = fragp->fr_symbol; | |
18266 | exp.X_add_number = fragp->fr_offset; | |
18267 | ||
4d68580a RS |
18268 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18269 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18270 | fixp->fx_file = fragp->fr_file; |
18271 | fixp->fx_line = fragp->fr_line; | |
18272 | ||
4d68580a | 18273 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18274 | } |
18275 | else | |
18276 | { | |
66b3e8da MR |
18277 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18278 | ||
4a6a3df4 | 18279 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18280 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18281 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18282 | exp.X_op = O_symbol; |
18283 | exp.X_add_symbol = fragp->fr_symbol; | |
18284 | exp.X_add_number = fragp->fr_offset; | |
18285 | ||
18286 | if (fragp->fr_offset) | |
18287 | { | |
18288 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18289 | exp.X_add_number = 0; | |
18290 | } | |
18291 | ||
4d68580a RS |
18292 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18293 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18294 | fixp->fx_file = fragp->fr_file; |
18295 | fixp->fx_line = fragp->fr_line; | |
18296 | ||
4d68580a | 18297 | buf = write_insn (buf, insn); |
b34976b6 | 18298 | |
4a6a3df4 | 18299 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18300 | /* nop */ |
18301 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18302 | |
18303 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18304 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18305 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18306 | |
4d68580a RS |
18307 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18308 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18309 | fixp->fx_file = fragp->fr_file; |
18310 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18311 | |
4d68580a | 18312 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18313 | |
18314 | /* j(al)r $at. */ | |
18315 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18316 | insn = 0x0000f809; |
4a6a3df4 | 18317 | else |
66b3e8da MR |
18318 | insn = 0x00000008; |
18319 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18320 | |
4d68580a | 18321 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18322 | } |
18323 | } | |
18324 | ||
4a6a3df4 | 18325 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18326 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18327 | return; |
18328 | } | |
18329 | ||
df58fc94 RS |
18330 | /* Relax microMIPS branches. */ |
18331 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18332 | { | |
4d68580a | 18333 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18334 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18335 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18336 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18337 | bfd_boolean short_ds; |
df58fc94 RS |
18338 | unsigned long insn; |
18339 | expressionS exp; | |
18340 | fixS *fixp; | |
18341 | ||
18342 | exp.X_op = O_symbol; | |
18343 | exp.X_add_symbol = fragp->fr_symbol; | |
18344 | exp.X_add_number = fragp->fr_offset; | |
18345 | ||
18346 | fragp->fr_fix += fragp->fr_var; | |
18347 | ||
18348 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18349 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18350 | { | |
18351 | /* We generate a fixup instead of applying it right now, | |
18352 | because if there is linker relaxation, we're going to | |
18353 | need the relocations. */ | |
18354 | if (type == 'D') | |
4d68580a | 18355 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18356 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18357 | else if (type == 'E') | |
4d68580a | 18358 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18359 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18360 | else | |
18361 | abort (); | |
18362 | ||
18363 | fixp->fx_file = fragp->fr_file; | |
18364 | fixp->fx_line = fragp->fr_line; | |
18365 | ||
18366 | /* These relocations can have an addend that won't fit in | |
18367 | 2 octets. */ | |
18368 | fixp->fx_no_overflow = 1; | |
18369 | ||
18370 | return; | |
18371 | } | |
18372 | ||
2309ddf2 | 18373 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18374 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18375 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18376 | { | |
18377 | /* We generate a fixup instead of applying it right now, | |
18378 | because if there is linker relaxation, we're going to | |
18379 | need the relocations. */ | |
4d68580a RS |
18380 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18381 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18382 | fixp->fx_file = fragp->fr_file; |
18383 | fixp->fx_line = fragp->fr_line; | |
18384 | ||
18385 | if (type == 0) | |
18386 | return; | |
18387 | } | |
18388 | ||
18389 | /* Relax 16-bit branches to 32-bit branches. */ | |
18390 | if (type != 0) | |
18391 | { | |
4d68580a | 18392 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18393 | |
18394 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18395 | insn = 0x94000000; /* beq */ | |
18396 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18397 | { | |
18398 | unsigned long regno; | |
18399 | ||
18400 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18401 | regno = micromips_to_32_reg_d_map [regno]; | |
18402 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18403 | insn |= regno << MICROMIPSOP_SH_RS; | |
18404 | } | |
18405 | else | |
18406 | abort (); | |
18407 | ||
18408 | /* Nothing else to do, just write it out. */ | |
18409 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18410 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18411 | { | |
4d68580a RS |
18412 | buf = write_compressed_insn (buf, insn, 4); |
18413 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18414 | return; |
18415 | } | |
18416 | } | |
18417 | else | |
4d68580a | 18418 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18419 | |
18420 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18421 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18422 | _("Relaxed out-of-range branch into a jump")); | |
18423 | ||
2309ddf2 MR |
18424 | /* Set the short-delay-slot bit. */ |
18425 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18426 | |
18427 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18428 | { | |
18429 | symbolS *l; | |
18430 | ||
18431 | /* Reverse the branch. */ | |
18432 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18433 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18434 | insn ^= 0x20000000; | |
18435 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18436 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18437 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18438 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18439 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18440 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18441 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18442 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18443 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18444 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18445 | insn ^= 0x00400000; | |
18446 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18447 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18448 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18449 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18450 | insn ^= 0x00200000; | |
18451 | else | |
18452 | abort (); | |
18453 | ||
18454 | if (al) | |
18455 | { | |
18456 | /* Clear the and-link and short-delay-slot bits. */ | |
18457 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18458 | ||
18459 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18460 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18461 | insn &= ~0x02200000; | |
18462 | } | |
18463 | ||
18464 | /* Make a label at the end for use with the branch. */ | |
18465 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18466 | micromips_label_inc (); | |
18467 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18468 | if (IS_ELF) | |
18469 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18470 | #endif | |
18471 | ||
18472 | /* Refer to it. */ | |
4d68580a RS |
18473 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18474 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18475 | fixp->fx_file = fragp->fr_file; |
18476 | fixp->fx_line = fragp->fr_line; | |
18477 | ||
18478 | /* Branch over the jump. */ | |
4d68580a | 18479 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18480 | if (!compact) |
4d68580a RS |
18481 | /* nop */ |
18482 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18483 | } |
18484 | ||
18485 | if (mips_pic == NO_PIC) | |
18486 | { | |
2309ddf2 MR |
18487 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18488 | ||
df58fc94 RS |
18489 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18490 | insn = al ? jal : 0xd4000000; | |
18491 | ||
4d68580a RS |
18492 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18493 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18494 | fixp->fx_file = fragp->fr_file; |
18495 | fixp->fx_line = fragp->fr_line; | |
18496 | ||
4d68580a | 18497 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18498 | if (compact) |
4d68580a RS |
18499 | /* nop */ |
18500 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18501 | } |
18502 | else | |
18503 | { | |
18504 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18505 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18506 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18507 | |
18508 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18509 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18510 | insn |= at << MICROMIPSOP_SH_RT; | |
18511 | ||
18512 | if (exp.X_add_number) | |
18513 | { | |
18514 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18515 | exp.X_add_number = 0; | |
18516 | } | |
18517 | ||
4d68580a RS |
18518 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18519 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18520 | fixp->fx_file = fragp->fr_file; |
18521 | fixp->fx_line = fragp->fr_line; | |
18522 | ||
4d68580a | 18523 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18524 | |
18525 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18526 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18527 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18528 | ||
4d68580a RS |
18529 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18530 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18531 | fixp->fx_file = fragp->fr_file; |
18532 | fixp->fx_line = fragp->fr_line; | |
18533 | ||
4d68580a | 18534 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18535 | |
18536 | /* jr/jrc/jalr/jalrs $at */ | |
18537 | insn = al ? jalr : jr; | |
18538 | insn |= at << MICROMIPSOP_SH_MJ; | |
18539 | ||
4d68580a | 18540 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18541 | } |
18542 | ||
4d68580a | 18543 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18544 | return; |
18545 | } | |
18546 | ||
252b5132 RH |
18547 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18548 | { | |
18549 | int type; | |
3994f87e | 18550 | const struct mips16_immed_operand *op; |
252b5132 | 18551 | offsetT val; |
5c04167a RS |
18552 | char *buf; |
18553 | unsigned int user_length, length; | |
252b5132 | 18554 | unsigned long insn; |
5c04167a | 18555 | bfd_boolean ext; |
252b5132 RH |
18556 | |
18557 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18558 | op = mips16_immed_operands; | |
18559 | while (op->type != type) | |
18560 | ++op; | |
18561 | ||
5c04167a | 18562 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18563 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18564 | if (op->pcrel) |
18565 | { | |
18566 | addressT addr; | |
18567 | ||
18568 | addr = fragp->fr_address + fragp->fr_fix; | |
18569 | ||
18570 | /* The rules for the base address of a PC relative reloc are | |
18571 | complicated; see mips16_extended_frag. */ | |
18572 | if (type == 'p' || type == 'q') | |
18573 | { | |
18574 | addr += 2; | |
18575 | if (ext) | |
18576 | addr += 2; | |
18577 | /* Ignore the low bit in the target, since it will be | |
18578 | set for a text label. */ | |
18579 | if ((val & 1) != 0) | |
18580 | --val; | |
18581 | } | |
18582 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18583 | addr -= 4; | |
18584 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18585 | addr -= 2; | |
18586 | ||
18587 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18588 | val -= addr; | |
18589 | ||
18590 | /* Make sure the section winds up with the alignment we have | |
18591 | assumed. */ | |
18592 | if (op->shift > 0) | |
18593 | record_alignment (asec, op->shift); | |
18594 | } | |
18595 | ||
18596 | if (ext | |
18597 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18598 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18599 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18600 | _("extended instruction in delay slot")); | |
18601 | ||
5c04167a | 18602 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18603 | |
4d68580a | 18604 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18605 | if (ext) |
18606 | insn |= MIPS16_EXTEND; | |
252b5132 | 18607 | |
5c04167a RS |
18608 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18609 | user_length = 4; | |
18610 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18611 | user_length = 2; | |
18612 | else | |
18613 | user_length = 0; | |
18614 | ||
43c0598f | 18615 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18616 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18617 | |
5c04167a RS |
18618 | length = (ext ? 4 : 2); |
18619 | gas_assert (mips16_opcode_length (insn) == length); | |
18620 | write_compressed_insn (buf, insn, length); | |
18621 | fragp->fr_fix += length; | |
252b5132 RH |
18622 | } |
18623 | else | |
18624 | { | |
df58fc94 RS |
18625 | relax_substateT subtype = fragp->fr_subtype; |
18626 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18627 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18628 | int first, second; |
18629 | fixS *fixp; | |
252b5132 | 18630 | |
df58fc94 RS |
18631 | first = RELAX_FIRST (subtype); |
18632 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18633 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18634 | |
df58fc94 RS |
18635 | /* If the delay slot chosen does not match the size of the instruction, |
18636 | then emit a warning. */ | |
18637 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18638 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18639 | { | |
18640 | relax_substateT s; | |
18641 | const char *msg; | |
18642 | ||
18643 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18644 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18645 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18646 | msg = macro_warning (s); | |
18647 | if (msg != NULL) | |
db9b2be4 | 18648 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18649 | subtype &= ~s; |
18650 | } | |
18651 | ||
584892a6 | 18652 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18653 | if (use_second == second_longer) |
584892a6 | 18654 | { |
df58fc94 RS |
18655 | relax_substateT s; |
18656 | const char *msg; | |
18657 | ||
18658 | s = (subtype | |
18659 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18660 | msg = macro_warning (s); | |
18661 | if (msg != NULL) | |
db9b2be4 | 18662 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18663 | subtype &= ~s; |
584892a6 RS |
18664 | } |
18665 | ||
4d7206a2 RS |
18666 | /* Go through all the fixups for the first sequence. Disable them |
18667 | (by marking them as done) if we're going to use the second | |
18668 | sequence instead. */ | |
18669 | while (fixp | |
18670 | && fixp->fx_frag == fragp | |
18671 | && fixp->fx_where < fragp->fr_fix - second) | |
18672 | { | |
df58fc94 | 18673 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18674 | fixp->fx_done = 1; |
18675 | fixp = fixp->fx_next; | |
18676 | } | |
252b5132 | 18677 | |
4d7206a2 RS |
18678 | /* Go through the fixups for the second sequence. Disable them if |
18679 | we're going to use the first sequence, otherwise adjust their | |
18680 | addresses to account for the relaxation. */ | |
18681 | while (fixp && fixp->fx_frag == fragp) | |
18682 | { | |
df58fc94 | 18683 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18684 | fixp->fx_where -= first; |
18685 | else | |
18686 | fixp->fx_done = 1; | |
18687 | fixp = fixp->fx_next; | |
18688 | } | |
18689 | ||
18690 | /* Now modify the frag contents. */ | |
df58fc94 | 18691 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18692 | { |
18693 | char *start; | |
18694 | ||
18695 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18696 | memmove (start, start + first, second); | |
18697 | fragp->fr_fix -= first; | |
18698 | } | |
18699 | else | |
18700 | fragp->fr_fix -= second; | |
252b5132 RH |
18701 | } |
18702 | } | |
18703 | ||
18704 | #ifdef OBJ_ELF | |
18705 | ||
18706 | /* This function is called after the relocs have been generated. | |
18707 | We've been storing mips16 text labels as odd. Here we convert them | |
18708 | back to even for the convenience of the debugger. */ | |
18709 | ||
18710 | void | |
17a2f251 | 18711 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18712 | { |
18713 | asymbol **syms; | |
18714 | unsigned int count, i; | |
18715 | ||
f43abd2b | 18716 | if (!IS_ELF) |
252b5132 RH |
18717 | return; |
18718 | ||
18719 | syms = bfd_get_outsymbols (stdoutput); | |
18720 | count = bfd_get_symcount (stdoutput); | |
18721 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18722 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18723 | && ((*syms)->value & 1) != 0) | |
18724 | { | |
18725 | (*syms)->value &= ~1; | |
18726 | /* If the symbol has an odd size, it was probably computed | |
18727 | incorrectly, so adjust that as well. */ | |
18728 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18729 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18730 | } | |
252b5132 RH |
18731 | } |
18732 | ||
18733 | #endif | |
18734 | ||
a1facbec MR |
18735 | /* This function is called whenever a label is defined, including fake |
18736 | labels instantiated off the dot special symbol. It is used when | |
18737 | handling branch delays; if a branch has a label, we assume we cannot | |
18738 | move it. This also bumps the value of the symbol by 1 in compressed | |
18739 | code. */ | |
252b5132 | 18740 | |
e1b47bd5 | 18741 | static void |
a1facbec | 18742 | mips_record_label (symbolS *sym) |
252b5132 | 18743 | { |
a8dbcb85 | 18744 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18745 | struct insn_label_list *l; |
18746 | ||
18747 | if (free_insn_labels == NULL) | |
18748 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18749 | else | |
18750 | { | |
18751 | l = free_insn_labels; | |
18752 | free_insn_labels = l->next; | |
18753 | } | |
18754 | ||
18755 | l->label = sym; | |
a8dbcb85 TS |
18756 | l->next = si->label_list; |
18757 | si->label_list = l; | |
a1facbec | 18758 | } |
07a53e5c | 18759 | |
a1facbec MR |
18760 | /* This function is called as tc_frob_label() whenever a label is defined |
18761 | and adds a DWARF-2 record we only want for true labels. */ | |
18762 | ||
18763 | void | |
18764 | mips_define_label (symbolS *sym) | |
18765 | { | |
18766 | mips_record_label (sym); | |
07a53e5c RH |
18767 | #ifdef OBJ_ELF |
18768 | dwarf2_emit_label (sym); | |
18769 | #endif | |
252b5132 | 18770 | } |
e1b47bd5 RS |
18771 | |
18772 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18773 | is defined. */ | |
18774 | ||
18775 | void | |
18776 | mips_add_dot_label (symbolS *sym) | |
18777 | { | |
18778 | mips_record_label (sym); | |
18779 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18780 | mips_compressed_mark_label (sym); | |
18781 | } | |
252b5132 RH |
18782 | \f |
18783 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18784 | ||
18785 | /* Some special processing for a MIPS ELF file. */ | |
18786 | ||
18787 | void | |
17a2f251 | 18788 | mips_elf_final_processing (void) |
252b5132 RH |
18789 | { |
18790 | /* Write out the register information. */ | |
316f5878 | 18791 | if (mips_abi != N64_ABI) |
252b5132 RH |
18792 | { |
18793 | Elf32_RegInfo s; | |
18794 | ||
18795 | s.ri_gprmask = mips_gprmask; | |
18796 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18797 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18798 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18799 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18800 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18801 | ||
18802 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18803 | ((Elf32_External_RegInfo *) | |
18804 | mips_regmask_frag)); | |
18805 | } | |
18806 | else | |
18807 | { | |
18808 | Elf64_Internal_RegInfo s; | |
18809 | ||
18810 | s.ri_gprmask = mips_gprmask; | |
18811 | s.ri_pad = 0; | |
18812 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18813 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18814 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18815 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18816 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18817 | ||
18818 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18819 | ((Elf64_External_RegInfo *) | |
18820 | mips_regmask_frag)); | |
18821 | } | |
18822 | ||
18823 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18824 | sort of BFD interface for this. */ | |
18825 | if (mips_any_noreorder) | |
18826 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18827 | if (mips_pic != NO_PIC) | |
143d77c5 | 18828 | { |
8b828383 | 18829 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18830 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18831 | } | |
18832 | if (mips_abicalls) | |
18833 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18834 | |
b015e599 AP |
18835 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18836 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18837 | if (file_ase_mips16) |
18838 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18839 | if (file_ase_micromips) |
18840 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18841 | #if 0 /* XXX FIXME */ |
18842 | if (file_ase_mips3d) | |
18843 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18844 | #endif | |
deec1734 CD |
18845 | if (file_ase_mdmx) |
18846 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18847 | |
bdaaa2e1 | 18848 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18849 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18850 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18851 | else if (mips_abi == O64_ABI) |
252b5132 | 18852 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18853 | else if (mips_abi == EABI_ABI) |
252b5132 | 18854 | { |
316f5878 | 18855 | if (!file_mips_gp32) |
252b5132 RH |
18856 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18857 | else | |
18858 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18859 | } | |
316f5878 | 18860 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18861 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18862 | ||
c9914766 | 18863 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18864 | |
18865 | if (mips_32bitmode) | |
18866 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18867 | |
18868 | #if 0 /* XXX FIXME */ | |
18869 | /* 32 bit code with 64 bit FP registers. */ | |
18870 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18871 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18872 | #endif | |
252b5132 RH |
18873 | } |
18874 | ||
18875 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18876 | \f | |
beae10d5 | 18877 | typedef struct proc { |
9b2f1d35 EC |
18878 | symbolS *func_sym; |
18879 | symbolS *func_end_sym; | |
beae10d5 KH |
18880 | unsigned long reg_mask; |
18881 | unsigned long reg_offset; | |
18882 | unsigned long fpreg_mask; | |
18883 | unsigned long fpreg_offset; | |
18884 | unsigned long frame_offset; | |
18885 | unsigned long frame_reg; | |
18886 | unsigned long pc_reg; | |
18887 | } procS; | |
252b5132 RH |
18888 | |
18889 | static procS cur_proc; | |
18890 | static procS *cur_proc_ptr; | |
18891 | static int numprocs; | |
18892 | ||
df58fc94 RS |
18893 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18894 | as "2", and a normal nop as "0". */ | |
18895 | ||
18896 | #define NOP_OPCODE_MIPS 0 | |
18897 | #define NOP_OPCODE_MIPS16 1 | |
18898 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18899 | |
18900 | char | |
18901 | mips_nop_opcode (void) | |
18902 | { | |
df58fc94 RS |
18903 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18904 | return NOP_OPCODE_MICROMIPS; | |
18905 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18906 | return NOP_OPCODE_MIPS16; | |
18907 | else | |
18908 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18909 | } |
18910 | ||
df58fc94 RS |
18911 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18912 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18913 | |
0a9ef439 | 18914 | void |
17a2f251 | 18915 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18916 | { |
df58fc94 | 18917 | char nop_opcode; |
742a56fe | 18918 | char *p; |
c67a084a NC |
18919 | int bytes, size, excess; |
18920 | valueT opcode; | |
742a56fe | 18921 | |
0a9ef439 RH |
18922 | if (fragp->fr_type != rs_align_code) |
18923 | return; | |
18924 | ||
742a56fe | 18925 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18926 | nop_opcode = *p; |
18927 | switch (nop_opcode) | |
a19d8eb0 | 18928 | { |
df58fc94 RS |
18929 | case NOP_OPCODE_MICROMIPS: |
18930 | opcode = micromips_nop32_insn.insn_opcode; | |
18931 | size = 4; | |
18932 | break; | |
18933 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18934 | opcode = mips16_nop_insn.insn_opcode; |
18935 | size = 2; | |
df58fc94 RS |
18936 | break; |
18937 | case NOP_OPCODE_MIPS: | |
18938 | default: | |
c67a084a NC |
18939 | opcode = nop_insn.insn_opcode; |
18940 | size = 4; | |
df58fc94 | 18941 | break; |
c67a084a | 18942 | } |
a19d8eb0 | 18943 | |
c67a084a NC |
18944 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18945 | excess = bytes % size; | |
df58fc94 RS |
18946 | |
18947 | /* Handle the leading part if we're not inserting a whole number of | |
18948 | instructions, and make it the end of the fixed part of the frag. | |
18949 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18950 | and use zeroes otherwise. */ | |
18951 | gas_assert (excess < 4); | |
18952 | fragp->fr_fix += excess; | |
18953 | switch (excess) | |
c67a084a | 18954 | { |
df58fc94 RS |
18955 | case 3: |
18956 | *p++ = '\0'; | |
18957 | /* Fall through. */ | |
18958 | case 2: | |
18959 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18960 | { | |
4d68580a | 18961 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18962 | break; |
18963 | } | |
18964 | *p++ = '\0'; | |
18965 | /* Fall through. */ | |
18966 | case 1: | |
18967 | *p++ = '\0'; | |
18968 | /* Fall through. */ | |
18969 | case 0: | |
18970 | break; | |
a19d8eb0 | 18971 | } |
c67a084a NC |
18972 | |
18973 | md_number_to_chars (p, opcode, size); | |
18974 | fragp->fr_var = size; | |
a19d8eb0 CP |
18975 | } |
18976 | ||
252b5132 | 18977 | static void |
17a2f251 | 18978 | md_obj_begin (void) |
252b5132 RH |
18979 | { |
18980 | } | |
18981 | ||
18982 | static void | |
17a2f251 | 18983 | md_obj_end (void) |
252b5132 | 18984 | { |
54f4ddb3 | 18985 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18986 | if (cur_proc_ptr) |
9a41af64 | 18987 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18988 | } |
18989 | ||
18990 | static long | |
17a2f251 | 18991 | get_number (void) |
252b5132 RH |
18992 | { |
18993 | int negative = 0; | |
18994 | long val = 0; | |
18995 | ||
18996 | if (*input_line_pointer == '-') | |
18997 | { | |
18998 | ++input_line_pointer; | |
18999 | negative = 1; | |
19000 | } | |
3882b010 | 19001 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19002 | as_bad (_("expected simple number")); |
252b5132 RH |
19003 | if (input_line_pointer[0] == '0') |
19004 | { | |
19005 | if (input_line_pointer[1] == 'x') | |
19006 | { | |
19007 | input_line_pointer += 2; | |
3882b010 | 19008 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19009 | { |
19010 | val <<= 4; | |
19011 | val |= hex_value (*input_line_pointer++); | |
19012 | } | |
19013 | return negative ? -val : val; | |
19014 | } | |
19015 | else | |
19016 | { | |
19017 | ++input_line_pointer; | |
3882b010 | 19018 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19019 | { |
19020 | val <<= 3; | |
19021 | val |= *input_line_pointer++ - '0'; | |
19022 | } | |
19023 | return negative ? -val : val; | |
19024 | } | |
19025 | } | |
3882b010 | 19026 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19027 | { |
19028 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19029 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19030 | as_warn (_("invalid number")); |
252b5132 RH |
19031 | return -1; |
19032 | } | |
3882b010 | 19033 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19034 | { |
19035 | val *= 10; | |
19036 | val += *input_line_pointer++ - '0'; | |
19037 | } | |
19038 | return negative ? -val : val; | |
19039 | } | |
19040 | ||
19041 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19042 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19043 | case .file implies DWARF-2. */ | |
19044 | ||
19045 | static void | |
17a2f251 | 19046 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19047 | { |
ecb4347a DJ |
19048 | static int first_file_directive = 0; |
19049 | ||
c5dd6aab DJ |
19050 | if (ECOFF_DEBUGGING) |
19051 | { | |
19052 | get_number (); | |
19053 | s_app_file (0); | |
19054 | } | |
19055 | else | |
ecb4347a DJ |
19056 | { |
19057 | char *filename; | |
19058 | ||
19059 | filename = dwarf2_directive_file (0); | |
19060 | ||
19061 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19062 | directive even for stabs output. Make sure that this | |
19063 | ".file" is handled. Note that you need a version of GCC | |
19064 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19065 | if (filename != NULL && ! first_file_directive) | |
19066 | { | |
19067 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19068 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19069 | } |
19070 | first_file_directive = 1; | |
19071 | } | |
c5dd6aab DJ |
19072 | } |
19073 | ||
19074 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19075 | |
19076 | static void | |
17a2f251 | 19077 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19078 | { |
c5dd6aab DJ |
19079 | if (!ECOFF_DEBUGGING) |
19080 | dwarf2_directive_loc (0); | |
252b5132 RH |
19081 | } |
19082 | ||
252b5132 RH |
19083 | /* The .end directive. */ |
19084 | ||
19085 | static void | |
17a2f251 | 19086 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19087 | { |
19088 | symbolS *p; | |
252b5132 | 19089 | |
7a621144 DJ |
19090 | /* Following functions need their own .frame and .cprestore directives. */ |
19091 | mips_frame_reg_valid = 0; | |
19092 | mips_cprestore_valid = 0; | |
19093 | ||
252b5132 RH |
19094 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19095 | { | |
19096 | p = get_symbol (); | |
19097 | demand_empty_rest_of_line (); | |
19098 | } | |
19099 | else | |
19100 | p = NULL; | |
19101 | ||
14949570 | 19102 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19103 | as_warn (_(".end not in text section")); |
19104 | ||
19105 | if (!cur_proc_ptr) | |
19106 | { | |
19107 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19108 | demand_empty_rest_of_line (); | |
19109 | return; | |
19110 | } | |
19111 | ||
19112 | if (p != NULL) | |
19113 | { | |
9c2799c2 | 19114 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19115 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19116 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19117 | |
19118 | if (debug_type == DEBUG_STABS) | |
19119 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19120 | S_GET_NAME (p)); | |
252b5132 RH |
19121 | } |
19122 | else | |
19123 | as_warn (_(".end directive missing or unknown symbol")); | |
19124 | ||
2132e3a3 | 19125 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19126 | /* Create an expression to calculate the size of the function. */ |
19127 | if (p && cur_proc_ptr) | |
19128 | { | |
19129 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19130 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19131 | ||
19132 | obj->size = exp; | |
19133 | exp->X_op = O_subtract; | |
19134 | exp->X_add_symbol = symbol_temp_new_now (); | |
19135 | exp->X_op_symbol = p; | |
19136 | exp->X_add_number = 0; | |
19137 | ||
19138 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19139 | } | |
19140 | ||
ecb4347a | 19141 | /* Generate a .pdr section. */ |
f43abd2b | 19142 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19143 | { |
19144 | segT saved_seg = now_seg; | |
19145 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19146 | expressionS exp; |
19147 | char *fragp; | |
252b5132 | 19148 | |
252b5132 | 19149 | #ifdef md_flush_pending_output |
ecb4347a | 19150 | md_flush_pending_output (); |
252b5132 RH |
19151 | #endif |
19152 | ||
9c2799c2 | 19153 | gas_assert (pdr_seg); |
ecb4347a | 19154 | subseg_set (pdr_seg, 0); |
252b5132 | 19155 | |
ecb4347a DJ |
19156 | /* Write the symbol. */ |
19157 | exp.X_op = O_symbol; | |
19158 | exp.X_add_symbol = p; | |
19159 | exp.X_add_number = 0; | |
19160 | emit_expr (&exp, 4); | |
252b5132 | 19161 | |
ecb4347a | 19162 | fragp = frag_more (7 * 4); |
252b5132 | 19163 | |
17a2f251 TS |
19164 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19165 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19166 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19167 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19168 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19169 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19170 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19171 | |
ecb4347a DJ |
19172 | subseg_set (saved_seg, saved_subseg); |
19173 | } | |
19174 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19175 | |
19176 | cur_proc_ptr = NULL; | |
19177 | } | |
19178 | ||
19179 | /* The .aent and .ent directives. */ | |
19180 | ||
19181 | static void | |
17a2f251 | 19182 | s_mips_ent (int aent) |
252b5132 | 19183 | { |
252b5132 | 19184 | symbolS *symbolP; |
252b5132 RH |
19185 | |
19186 | symbolP = get_symbol (); | |
19187 | if (*input_line_pointer == ',') | |
f9419b05 | 19188 | ++input_line_pointer; |
252b5132 | 19189 | SKIP_WHITESPACE (); |
3882b010 | 19190 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19191 | || *input_line_pointer == '-') |
874e8986 | 19192 | get_number (); |
252b5132 | 19193 | |
14949570 | 19194 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19195 | as_warn (_(".ent or .aent not in text section.")); |
19196 | ||
19197 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19198 | as_warn (_("missing .end")); |
252b5132 RH |
19199 | |
19200 | if (!aent) | |
19201 | { | |
7a621144 DJ |
19202 | /* This function needs its own .frame and .cprestore directives. */ |
19203 | mips_frame_reg_valid = 0; | |
19204 | mips_cprestore_valid = 0; | |
19205 | ||
252b5132 RH |
19206 | cur_proc_ptr = &cur_proc; |
19207 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19208 | ||
9b2f1d35 | 19209 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19210 | |
f9419b05 | 19211 | ++numprocs; |
ecb4347a DJ |
19212 | |
19213 | if (debug_type == DEBUG_STABS) | |
19214 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19215 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19216 | } |
19217 | ||
7c0fc524 MR |
19218 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19219 | ||
252b5132 RH |
19220 | demand_empty_rest_of_line (); |
19221 | } | |
19222 | ||
19223 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19224 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19225 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19226 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19227 | symbol table (in the mdebug section). */ |
19228 | ||
19229 | static void | |
17a2f251 | 19230 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19231 | { |
ecb4347a | 19232 | #ifdef OBJ_ELF |
f43abd2b | 19233 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19234 | { |
19235 | long val; | |
252b5132 | 19236 | |
ecb4347a DJ |
19237 | if (cur_proc_ptr == (procS *) NULL) |
19238 | { | |
19239 | as_warn (_(".frame outside of .ent")); | |
19240 | demand_empty_rest_of_line (); | |
19241 | return; | |
19242 | } | |
252b5132 | 19243 | |
ecb4347a DJ |
19244 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19245 | ||
19246 | SKIP_WHITESPACE (); | |
19247 | if (*input_line_pointer++ != ',' | |
19248 | || get_absolute_expression_and_terminator (&val) != ',') | |
19249 | { | |
19250 | as_warn (_("Bad .frame directive")); | |
19251 | --input_line_pointer; | |
19252 | demand_empty_rest_of_line (); | |
19253 | return; | |
19254 | } | |
252b5132 | 19255 | |
ecb4347a DJ |
19256 | cur_proc_ptr->frame_offset = val; |
19257 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19258 | |
252b5132 | 19259 | demand_empty_rest_of_line (); |
252b5132 | 19260 | } |
ecb4347a DJ |
19261 | else |
19262 | #endif /* OBJ_ELF */ | |
19263 | s_ignore (ignore); | |
252b5132 RH |
19264 | } |
19265 | ||
bdaaa2e1 KH |
19266 | /* The .fmask and .mask directives. If the mdebug section is present |
19267 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19268 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19269 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19270 | make reference to the ecoff symbol table (in the mdebug section). */ |
19271 | ||
19272 | static void | |
17a2f251 | 19273 | s_mips_mask (int reg_type) |
252b5132 | 19274 | { |
ecb4347a | 19275 | #ifdef OBJ_ELF |
f43abd2b | 19276 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19277 | { |
ecb4347a | 19278 | long mask, off; |
252b5132 | 19279 | |
ecb4347a DJ |
19280 | if (cur_proc_ptr == (procS *) NULL) |
19281 | { | |
19282 | as_warn (_(".mask/.fmask outside of .ent")); | |
19283 | demand_empty_rest_of_line (); | |
19284 | return; | |
19285 | } | |
252b5132 | 19286 | |
ecb4347a DJ |
19287 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19288 | { | |
19289 | as_warn (_("Bad .mask/.fmask directive")); | |
19290 | --input_line_pointer; | |
19291 | demand_empty_rest_of_line (); | |
19292 | return; | |
19293 | } | |
252b5132 | 19294 | |
ecb4347a DJ |
19295 | off = get_absolute_expression (); |
19296 | ||
19297 | if (reg_type == 'F') | |
19298 | { | |
19299 | cur_proc_ptr->fpreg_mask = mask; | |
19300 | cur_proc_ptr->fpreg_offset = off; | |
19301 | } | |
19302 | else | |
19303 | { | |
19304 | cur_proc_ptr->reg_mask = mask; | |
19305 | cur_proc_ptr->reg_offset = off; | |
19306 | } | |
19307 | ||
19308 | demand_empty_rest_of_line (); | |
252b5132 RH |
19309 | } |
19310 | else | |
ecb4347a DJ |
19311 | #endif /* OBJ_ELF */ |
19312 | s_ignore (reg_type); | |
252b5132 RH |
19313 | } |
19314 | ||
316f5878 RS |
19315 | /* A table describing all the processors gas knows about. Names are |
19316 | matched in the order listed. | |
e7af610e | 19317 | |
316f5878 RS |
19318 | To ease comparison, please keep this table in the same order as |
19319 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19320 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19321 | { | |
316f5878 | 19322 | /* Entries for generic ISAs */ |
ad3fea08 TS |
19323 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
19324 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
19325 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
19326 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
19327 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
19328 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
19329 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19330 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
19331 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19332 | |
19333 | /* MIPS I */ | |
ad3fea08 TS |
19334 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
19335 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
19336 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19337 | |
19338 | /* MIPS II */ | |
ad3fea08 | 19339 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19340 | |
19341 | /* MIPS III */ | |
ad3fea08 TS |
19342 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19343 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19344 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19345 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19346 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19347 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19348 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19349 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19350 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19351 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19352 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19353 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
e407c74b | 19354 | { "r5900", 0, ISA_MIPS3, CPU_R5900 }, |
b15591bb AN |
19355 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19356 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19357 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19358 | |
19359 | /* MIPS IV */ | |
ad3fea08 TS |
19360 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19361 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19362 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19363 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19364 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19365 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19366 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19367 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19368 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19369 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19370 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19371 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19372 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19373 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19374 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19375 | |
19376 | /* MIPS 32 */ | |
ad3fea08 TS |
19377 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19378 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19379 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19380 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19381 | ||
19382 | /* MIPS 32 Release 2 */ | |
19383 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19384 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19385 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19386 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19387 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19388 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19389 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19390 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19391 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19392 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19393 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19394 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19395 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19396 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19397 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19398 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19399 | /* Deprecated forms of the above. */ | |
19400 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19401 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19402 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19403 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19404 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19405 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19406 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19407 | /* Deprecated forms of the above. */ | |
19408 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19409 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19410 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19411 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19412 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19413 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19414 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19415 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19416 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19417 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19418 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19419 | /* Deprecated forms of the above. */ | |
19420 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19421 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19422 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19423 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19424 | /* 34Kn is a 34kc without DSP. */ |
19425 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19426 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19427 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19428 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19429 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19430 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19431 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19432 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19433 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19434 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19435 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19436 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19437 | /* Deprecated forms of the above. */ | |
19438 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19439 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19440 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19441 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19442 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19443 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19444 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19445 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19446 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19447 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19448 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19449 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19450 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19451 | |
316f5878 | 19452 | /* MIPS 64 */ |
ad3fea08 TS |
19453 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19454 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19455 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19456 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19457 | |
c7a23324 | 19458 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19459 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19460 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19461 | /* Broadcom SB-1A CPU core */ |
19462 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19463 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19464 | |
19465 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19466 | |
ed163775 MR |
19467 | /* MIPS 64 Release 2 */ |
19468 | ||
967344c6 AN |
19469 | /* Cavium Networks Octeon CPU core */ |
19470 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19471 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19472 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19473 | |
52b6b6b9 JM |
19474 | /* RMI Xlr */ |
19475 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19476 | ||
55a36193 MK |
19477 | /* Broadcom XLP. |
19478 | XLP is mostly like XLR, with the prominent exception that it is | |
19479 | MIPS64R2 rather than MIPS64. */ | |
19480 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19481 | ||
316f5878 RS |
19482 | /* End marker */ |
19483 | { NULL, 0, 0, 0 } | |
19484 | }; | |
e7af610e | 19485 | |
84ea6cf2 | 19486 | |
316f5878 RS |
19487 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19488 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19489 | |
316f5878 | 19490 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19491 | |
b34976b6 | 19492 | static bfd_boolean |
17a2f251 | 19493 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19494 | { |
19495 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19496 | given++, canonical++; | |
19497 | ||
19498 | return ((*given == 0 && *canonical == 0) | |
19499 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19500 | } | |
19501 | ||
19502 | ||
19503 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19504 | CPU name. We've traditionally allowed a lot of variation here. | |
19505 | ||
19506 | Note: this function is shared between GCC and GAS. */ | |
19507 | ||
b34976b6 | 19508 | static bfd_boolean |
17a2f251 | 19509 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19510 | { |
19511 | /* First see if the name matches exactly, or with a final "000" | |
19512 | turned into "k". */ | |
19513 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19514 | return TRUE; |
316f5878 RS |
19515 | |
19516 | /* If not, try comparing based on numerical designation alone. | |
19517 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19518 | if (TOLOWER (*given) == 'r') | |
19519 | given++; | |
19520 | if (!ISDIGIT (*given)) | |
b34976b6 | 19521 | return FALSE; |
316f5878 RS |
19522 | |
19523 | /* Skip over some well-known prefixes in the canonical name, | |
19524 | hoping to find a number there too. */ | |
19525 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19526 | canonical += 2; | |
19527 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19528 | canonical += 2; | |
19529 | else if (TOLOWER (canonical[0]) == 'r') | |
19530 | canonical += 1; | |
19531 | ||
19532 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19533 | } | |
19534 | ||
19535 | ||
19536 | /* Parse an option that takes the name of a processor as its argument. | |
19537 | OPTION is the name of the option and CPU_STRING is the argument. | |
19538 | Return the corresponding processor enumeration if the CPU_STRING is | |
19539 | recognized, otherwise report an error and return null. | |
19540 | ||
19541 | A similar function exists in GCC. */ | |
e7af610e NC |
19542 | |
19543 | static const struct mips_cpu_info * | |
17a2f251 | 19544 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19545 | { |
316f5878 | 19546 | const struct mips_cpu_info *p; |
e7af610e | 19547 | |
316f5878 RS |
19548 | /* 'from-abi' selects the most compatible architecture for the given |
19549 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19550 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19551 | version. Look first at the -mgp options, if given, otherwise base | |
19552 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19553 | |
316f5878 RS |
19554 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19555 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19556 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19557 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19558 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19559 | { | |
19560 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19561 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19562 | ||
19563 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19564 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19565 | ||
19566 | if (file_mips_gp32 >= 0) | |
19567 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19568 | ||
19569 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19570 | ? ISA_MIPS3 | |
19571 | : ISA_MIPS1); | |
19572 | } | |
19573 | ||
19574 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19575 | if (strcasecmp (cpu_string, "default") == 0) | |
19576 | return 0; | |
19577 | ||
19578 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19579 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19580 | return p; | |
19581 | ||
20203fb9 | 19582 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19583 | return 0; |
e7af610e NC |
19584 | } |
19585 | ||
316f5878 RS |
19586 | /* Return the canonical processor information for ISA (a member of the |
19587 | ISA_MIPS* enumeration). */ | |
19588 | ||
e7af610e | 19589 | static const struct mips_cpu_info * |
17a2f251 | 19590 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19591 | { |
19592 | int i; | |
19593 | ||
19594 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19595 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19596 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19597 | return (&mips_cpu_info_table[i]); |
19598 | ||
e972090a | 19599 | return NULL; |
e7af610e | 19600 | } |
fef14a42 TS |
19601 | |
19602 | static const struct mips_cpu_info * | |
17a2f251 | 19603 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19604 | { |
19605 | int i; | |
19606 | ||
19607 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19608 | if (arch == mips_cpu_info_table[i].cpu) | |
19609 | return (&mips_cpu_info_table[i]); | |
19610 | ||
19611 | return NULL; | |
19612 | } | |
316f5878 RS |
19613 | \f |
19614 | static void | |
17a2f251 | 19615 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19616 | { |
19617 | if (*first_p) | |
19618 | { | |
19619 | fprintf (stream, "%24s", ""); | |
19620 | *col_p = 24; | |
19621 | } | |
19622 | else | |
19623 | { | |
19624 | fprintf (stream, ", "); | |
19625 | *col_p += 2; | |
19626 | } | |
e7af610e | 19627 | |
316f5878 RS |
19628 | if (*col_p + strlen (string) > 72) |
19629 | { | |
19630 | fprintf (stream, "\n%24s", ""); | |
19631 | *col_p = 24; | |
19632 | } | |
19633 | ||
19634 | fprintf (stream, "%s", string); | |
19635 | *col_p += strlen (string); | |
19636 | ||
19637 | *first_p = 0; | |
19638 | } | |
19639 | ||
19640 | void | |
17a2f251 | 19641 | md_show_usage (FILE *stream) |
e7af610e | 19642 | { |
316f5878 RS |
19643 | int column, first; |
19644 | size_t i; | |
19645 | ||
19646 | fprintf (stream, _("\ | |
19647 | MIPS options:\n\ | |
316f5878 RS |
19648 | -EB generate big endian output\n\ |
19649 | -EL generate little endian output\n\ | |
19650 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19651 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19652 | implicitly with the gp register [default 8]\n")); | |
19653 | fprintf (stream, _("\ | |
19654 | -mips1 generate MIPS ISA I instructions\n\ | |
19655 | -mips2 generate MIPS ISA II instructions\n\ | |
19656 | -mips3 generate MIPS ISA III instructions\n\ | |
19657 | -mips4 generate MIPS ISA IV instructions\n\ | |
19658 | -mips5 generate MIPS ISA V instructions\n\ | |
19659 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19660 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19661 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19662 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19663 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19664 | ||
19665 | first = 1; | |
e7af610e NC |
19666 | |
19667 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19668 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19669 | show (stream, "from-abi", &column, &first); | |
19670 | fputc ('\n', stream); | |
e7af610e | 19671 | |
316f5878 RS |
19672 | fprintf (stream, _("\ |
19673 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19674 | -no-mCPU don't generate code specific to CPU.\n\ | |
19675 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19676 | ||
19677 | first = 1; | |
19678 | ||
19679 | show (stream, "3900", &column, &first); | |
19680 | show (stream, "4010", &column, &first); | |
19681 | show (stream, "4100", &column, &first); | |
19682 | show (stream, "4650", &column, &first); | |
19683 | fputc ('\n', stream); | |
19684 | ||
19685 | fprintf (stream, _("\ | |
19686 | -mips16 generate mips16 instructions\n\ | |
19687 | -no-mips16 do not generate mips16 instructions\n")); | |
19688 | fprintf (stream, _("\ | |
df58fc94 RS |
19689 | -mmicromips generate microMIPS instructions\n\ |
19690 | -mno-micromips do not generate microMIPS instructions\n")); | |
19691 | fprintf (stream, _("\ | |
e16bfa71 TS |
19692 | -msmartmips generate smartmips instructions\n\ |
19693 | -mno-smartmips do not generate smartmips instructions\n")); | |
19694 | fprintf (stream, _("\ | |
74cd071d CF |
19695 | -mdsp generate DSP instructions\n\ |
19696 | -mno-dsp do not generate DSP instructions\n")); | |
19697 | fprintf (stream, _("\ | |
8b082fb1 TS |
19698 | -mdspr2 generate DSP R2 instructions\n\ |
19699 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19700 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19701 | -mmt generate MT instructions\n\ |
19702 | -mno-mt do not generate MT instructions\n")); | |
19703 | fprintf (stream, _("\ | |
dec0624d MR |
19704 | -mmcu generate MCU instructions\n\ |
19705 | -mno-mcu do not generate MCU instructions\n")); | |
19706 | fprintf (stream, _("\ | |
b015e599 AP |
19707 | -mvirt generate Virtualization instructions\n\ |
19708 | -mno-virt do not generate Virtualization instructions\n")); | |
19709 | fprintf (stream, _("\ | |
c67a084a NC |
19710 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19711 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19712 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19713 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19714 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19715 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19716 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19717 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19718 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19719 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19720 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19721 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19722 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19723 | fprintf (stream, _("\ |
19724 | -mhard-float allow floating-point instructions\n\ | |
19725 | -msoft-float do not allow floating-point instructions\n\ | |
19726 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19727 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19728 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19729 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19730 | )); |
316f5878 RS |
19731 | #ifdef OBJ_ELF |
19732 | fprintf (stream, _("\ | |
19733 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19734 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19735 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19736 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19737 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19738 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19739 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19740 | position dependent (non shared) code\n\ |
316f5878 RS |
19741 | -mabi=ABI create ABI conformant object file for:\n")); |
19742 | ||
19743 | first = 1; | |
19744 | ||
19745 | show (stream, "32", &column, &first); | |
19746 | show (stream, "o64", &column, &first); | |
19747 | show (stream, "n32", &column, &first); | |
19748 | show (stream, "64", &column, &first); | |
19749 | show (stream, "eabi", &column, &first); | |
19750 | ||
19751 | fputc ('\n', stream); | |
19752 | ||
19753 | fprintf (stream, _("\ | |
19754 | -32 create o32 ABI object file (default)\n\ | |
19755 | -n32 create n32 ABI object file\n\ | |
19756 | -64 create 64 ABI object file\n")); | |
19757 | #endif | |
e7af610e | 19758 | } |
14e777e0 | 19759 | |
1575952e | 19760 | #ifdef TE_IRIX |
14e777e0 | 19761 | enum dwarf2_format |
413a266c | 19762 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19763 | { |
369943fe | 19764 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19765 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19766 | else |
19767 | return dwarf2_format_32bit; | |
19768 | } | |
1575952e | 19769 | #endif |
73369e65 EC |
19770 | |
19771 | int | |
19772 | mips_dwarf2_addr_size (void) | |
19773 | { | |
6b6b3450 | 19774 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19775 | return 8; |
73369e65 EC |
19776 | else |
19777 | return 4; | |
19778 | } | |
5862107c EC |
19779 | |
19780 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19781 | void | |
19782 | mips_cfi_frame_initial_instructions (void) | |
19783 | { | |
19784 | cfi_add_CFA_def_cfa_register (SP); | |
19785 | } | |
19786 | ||
707bfff6 TS |
19787 | int |
19788 | tc_mips_regname_to_dw2regnum (char *regname) | |
19789 | { | |
19790 | unsigned int regnum = -1; | |
19791 | unsigned int reg; | |
19792 | ||
19793 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19794 | regnum = reg; | |
19795 | ||
19796 | return regnum; | |
19797 | } |